Merge tag 'sh-pfc-for-v4.21-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.21
- Fix VIN (Video IN) versioned groups on R-Car V2H, H3, and M3-W,
- Add I2C[0-3], DU1, VIN, QSPI1, and SDHI pin groups on RZ/G1C,
- Add audio, SDHI, VIN, HSCIF, and CAN(FD) support on R-Car E3,
- Add QSPI pin groups on R-Car V3M and V3H,
- Add VIN and CAN(FD) pin groups on R-Car M3-N,
- Add I2C[035] pin groups on R-Car H3 and M3-W,
- Add pinctrl and GPIO support for the new RZ/A2M (R7S9210) SoC,
- Small cleanups,
- Maintainership updates.
diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt
new file mode 100644
index 0000000..d13ff82
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.txt
@@ -0,0 +1,170 @@
+Actions Semi S700 Pin Controller
+
+This binding describes the pin controller found in the S700 SoC.
+
+Required Properties:
+
+- compatible: Should be "actions,s700-pinctrl"
+- reg: Should contain the register base address and size of
+ the pin controller.
+- clocks: phandle of the clock feeding the pin controller
+- gpio-controller: Marks the device node as a GPIO controller.
+- gpio-ranges: Specifies the mapping between gpio controller and
+ pin-controller pins.
+- #gpio-cells: Should be two. The first cell is the gpio pin number
+ and the second cell is used for optional parameters.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Specifies the number of cells needed to encode an
+ interrupt. Shall be set to 2. The first cell
+ defines the interrupt number, the second encodes
+ the trigger flags described in
+ bindings/interrupt-controller/interrupts.txt
+- interrupts: The interrupt outputs from the controller. There is one GPIO
+ interrupt per GPIO bank. The number of interrupts listed depends
+ on the number of GPIO banks on the SoC. The interrupts must be
+ ordered by bank, starting with bank 0.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+Pinmux functions are available only for the pin groups while pinconf
+parameters are available for both pin groups and individual pins.
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+Required Properties:
+
+- pins: An array of strings, each string containing the name of a pin.
+ These pins are used for selecting the pull control and schmitt
+ trigger parameters. The following are the list of pins
+ available:
+
+ eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer,
+ eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk,
+ eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
+ i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
+ pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2,
+ ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp,
+ lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap,
+ lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
+ lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18,
+ lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn,
+ dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2,
+ sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk,
+ sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx,
+ uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx,
+ uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk,
+ i2c1_sdata, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1,
+ csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3,
+ sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2,
+ dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_wrb,
+ dnand_rdb, dnand_rdbn, dnand_dqs, dnand_dqsn, dnand_rb0,
+ dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, dnand_ceb2,
+ dnand_ceb3, porb, clko_25m, bsel, pkg0, pkg1, pkg2, pkg3
+
+- groups: An array of strings, each string containing the name of a pin
+ group. These pin groups are used for selecting the pinmux
+ functions.
+ rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp,
+ rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp,
+ rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp,
+ i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp,
+ i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp,
+ ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
+ dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp,
+ lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, dsi_dnp1_cp_d2_mfp,
+ dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp,
+ uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp,
+ sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
+ uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, uart0_tx_mfp,
+ i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, pcm1_clk_mfp,
+ pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, dnand_acle_ce0_mfp,
+ nand_ceb2_mfp, nand_ceb3_mfp
+
+ These pin groups are used for selecting the drive strength
+ parameters.
+
+ sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv,
+ rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv,
+ smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv,
+ pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv,
+ dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, spi0_all_drv,
+ uart0_rx_drv, uart0_tx_drv, uart2_all_drv, i2c0_all_drv, i2c12_all_drv,
+ sens0_pclk_drv, sens0_ckout_drv, uart3_all_drv
+
+- function: An array of strings, each string containing the name of the
+ pinmux functions. These functions can only be selected by
+ the corresponding pin groups. The following are the list of
+ pinmux functions available:
+
+ nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1,
+ uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
+ pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0,
+ sd0, sd1, sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30,
+ clko_25m, mipi_csi, nand, spdif, sirq0, sirq1, sirq2, bt, lcd0
+
+Optional Properties:
+
+- bias-pull-down: No arguments. The specified pins should be configured as
+ pull down.
+- bias-pull-up: No arguments. The specified pins should be configured as
+ pull up.
+- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
+ pins
+- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
+ pins
+- drive-strength: Integer. Selects the drive strength for the specified
+ pins in mA.
+ Valid values are:
+ <2>
+ <4>
+ <8>
+ <12>
+
+Example:
+
+ pinctrl: pinctrl@e01b0000 {
+ compatible = "actions,s700-pinctrl";
+ reg = <0x0 0xe01b0000 0x0 0x1000>;
+ clocks = <&cmu CLK_GPIO>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 136>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+
+ uart3-default: uart3-default {
+ pinmux {
+ groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp";
+ function = "uart3";
+ };
+ pinconf {
+ groups = "uart3_all_drv";
+ drive-strength = <2>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 258a464..a7f7133 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -29,6 +29,7 @@
"allwinner,sun50i-h5-pinctrl"
"allwinner,sun50i-h6-pinctrl"
"allwinner,sun50i-h6-r-pinctrl"
+ "allwinner,suniv-f1c100s-pinctrl"
"nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
index 44ad670..bfa3703 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
@@ -7,55 +7,47 @@
This binding doc is only for the IOMUXC1 support in A7 Domain and it only
supports generic pin config.
-Please also refer pinctrl-bindings.txt in this directory for generic pinctrl
-binding.
-
-=== Pin Controller Node ===
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding
+part and usage.
Required properties:
-- compatible: "fsl,imx7ulp-iomuxc1"
-- reg: Should contain the base physical address and size of the iomuxc
- registers.
+- compatible: "fsl,imx7ulp-iomuxc1".
+- fsl,pins: Each entry consists of 5 integers which represents the mux
+ and config setting for one pin. The first 4 integers
+ <mux_conf_reg input_reg mux_mode input_val> are specified
+ using a PIN_FUNC_ID macro, which can be found in
+ imx7ulp-pinfunc.h in the device tree source folder.
+ The last integer CONFIG is the pad setting value like
+ pull-up on this pin.
-=== Pin Configuration Node ===
-- pinmux: One integers array, represents a group of pins mux setting.
- The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
- a specific function.
+ Please refer to i.MX7ULP Reference Manual for detailed
+ CONFIG settings.
- NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
- and config register as follows:
- <mux_conf_reg input_reg mux_mode input_val>
-
- Refer to imx7ulp-pinfunc.h in in device tree source folder for all
- available imx7ulp PIN_FUNC_ID.
-
-Optional Properties:
-- drive-strength Integer. Controls Drive Strength
- 0: Standard
- 1: Hi Driver
-- drive-push-pull Bool. Enable Pin Push-pull
-- drive-open-drain Bool. Enable Pin Open-drian
-- slew-rate: Integer. Controls Slew Rate
- 0: Standard
- 1: Slow
-- bias-disable: Bool. Pull disabled
-- bias-pull-down: Bool. Pull down on pin
-- bias-pull-up: Bool. Pull up on pin
+CONFIG bits definition:
+PAD_CTL_OBE (1 << 17)
+PAD_CTL_IBE (1 << 16)
+PAD_CTL_LK (1 << 16)
+PAD_CTL_DSE_HI (1 << 6)
+PAD_CTL_DSE_STD (0 << 6)
+PAD_CTL_ODE (1 << 5)
+PAD_CTL_PUSH_PULL (0 << 5)
+PAD_CTL_SRE_SLOW (1 << 2)
+PAD_CTL_SRE_STD (0 << 2)
+PAD_CTL_PE (1 << 0)
Examples:
#include "imx7ulp-pinfunc.h"
/* Pin Controller Node */
-iomuxc1: iomuxc@40ac0000 {
+iomuxc1: pinctrl@40ac0000 {
compatible = "fsl,imx7ulp-iomuxc1";
reg = <0x40ac0000 0x1000>;
/* Pin Configuration Node */
pinctrl_lpuart4: lpuart4grp {
- pinmux = <
- IMX7ULP_PAD_PTC3__LPUART4_RX
- IMX7ULP_PAD_PTC2__LPUART4_TX
+ fsl,pins = <
+ IMX7ULP_PAD_PTC3__LPUART4_RX 0x1
+ IMX7ULP_PAD_PTC2__LPUART4_TX 0x1
>;
- bias-pull-up;
};
};
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt6797.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt6797.txt
new file mode 100644
index 0000000..bd83401
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt6797.txt
@@ -0,0 +1,83 @@
+* MediaTek MT6797 Pin Controller
+
+The MediaTek's MT6797 Pin controller is used to control SoC pins.
+
+Required properties:
+- compatible: Value should be one of the following.
+ "mediatek,mt6797-pinctrl", compatible with mt6797 pinctrl.
+- reg: Should contain address and size for gpio, iocfgl, iocfgb,
+ iocfgr and iocfgt register bases.
+- reg-names: An array of strings describing the "reg" entries. Must
+ contain "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt".
+- gpio-controller: Marks the device node as a gpio controller.
+- #gpio-cells: Should be two. The first cell is the gpio pin number
+ and the second cell is used for optional parameters.
+
+Optional properties:
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be two.
+- interrupts : The interrupt outputs from the controller.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+Subnode format
+A pinctrl node should contain at least one subnodes representing the
+pinctrl groups available on the machine. Each subnode will list the
+pins it needs, and how they should be configured, with regard to muxer
+configuration, pullups, drive strength, input enable/disable and input schmitt.
+
+ node {
+ pinmux = <PIN_NUMBER_PINMUX>;
+ GENERIC_PINCONFIG;
+ };
+
+Required properties:
+- pinmux: Integer array, represents gpio pin number and mux setting.
+ Supported pin number and mux varies for different SoCs, and are defined
+ as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
+
+Optional properties:
+- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
+ bias-pull, bias-pull-down, input-enable, input-schmitt-enable,
+ input-schmitt-disable, output-enable output-low, output-high,
+ drive-strength, and slew-rate are valid.
+
+ Valid arguments for 'slew-rate' are '0' for no slew rate controlled and
+ '1' for slower slew rate respectively. Valid arguments for 'drive-strength'
+ is limited, such as 2, 4, 8, 12, or 16 in mA.
+
+ Some optional vendor properties as defined are valid to specify in a
+ pinconf subnode:
+ - mediatek,tdsel: An integer describing the steps for output level shifter
+ duty cycle when asserted (high pulse width adjustment). Valid arguments
+ are from 0 to 15.
+ - mediatek,rdsel: An integer describing the steps for input level shifter
+ duty cycle when asserted (high pulse width adjustment). Valid arguments
+ are from 0 to 63.
+ - mediatek,pull-up-adv: An integer describing the code R1R0 as 0, 1, 2
+ or 3 for the advanced pull-up resistors.
+ - mediatek,pull-down-adv: An integer describing the code R1R0 as 0, 1, 2,
+ or 3 for the advanced pull-down resistors.
+
+Examples:
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt6797-pinctrl";
+ reg = <0 0x10005000 0 0x1000>,
+ <0 0x10002000 0 0x400>,
+ <0 0x10002400 0 0x400>,
+ <0 0x10002800 0 0x400>,
+ <0 0x10002C00 0 0x400>;
+ reg-names = "gpio", "iocfgl", "iocfgb",
+ "iocfgr", "iocfgt";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ uart1_pins_a: uart1 {
+ pins1 {
+ pinmux = <MT6797_GPIO232__FUNC_URXD1>,
+ <MT6797_GPIO233__FUNC_UTXD1>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
index 3b69513..7a7aca1 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
@@ -3,6 +3,7 @@
Required properties for the root node:
- compatible: Should be one of the following
"mediatek,mt7622-pinctrl" for MT7622 SoC
+ "mediatek,mt7629-pinctrl" for MT7629 SoC
- reg: offset and length of the pinctrl space
- gpio-controller: Marks the device node as a GPIO controller.
@@ -324,6 +325,136 @@
"uart4_2_rts_cts" "uart" 95, 96
"watchdog" "watchdog" 78
+
+== Valid values for pins, function and groups on MT7629 ==
+
+ Pin #: Valid values for pins
+ -----------------------------
+ PIN 0: "TOP_5G_CLK"
+ PIN 1: "TOP_5G_DATA"
+ PIN 2: "WF0_5G_HB0"
+ PIN 3: "WF0_5G_HB1"
+ PIN 4: "WF0_5G_HB2"
+ PIN 5: "WF0_5G_HB3"
+ PIN 6: "WF0_5G_HB4"
+ PIN 7: "WF0_5G_HB5"
+ PIN 8: "WF0_5G_HB6"
+ PIN 9: "XO_REQ"
+ PIN 10: "TOP_RST_N"
+ PIN 11: "SYS_WATCHDOG"
+ PIN 12: "EPHY_LED0_N_JTDO"
+ PIN 13: "EPHY_LED1_N_JTDI"
+ PIN 14: "EPHY_LED2_N_JTMS"
+ PIN 15: "EPHY_LED3_N_JTCLK"
+ PIN 16: "EPHY_LED4_N_JTRST_N"
+ PIN 17: "WF2G_LED_N"
+ PIN 18: "WF5G_LED_N"
+ PIN 19: "I2C_SDA"
+ PIN 20: "I2C_SCL"
+ PIN 21: "GPIO_9"
+ PIN 22: "GPIO_10"
+ PIN 23: "GPIO_11"
+ PIN 24: "GPIO_12"
+ PIN 25: "UART1_TXD"
+ PIN 26: "UART1_RXD"
+ PIN 27: "UART1_CTS"
+ PIN 28: "UART1_RTS"
+ PIN 29: "UART2_TXD"
+ PIN 30: "UART2_RXD"
+ PIN 31: "UART2_CTS"
+ PIN 32: "UART2_RTS"
+ PIN 33: "MDI_TP_P1"
+ PIN 34: "MDI_TN_P1"
+ PIN 35: "MDI_RP_P1"
+ PIN 36: "MDI_RN_P1"
+ PIN 37: "MDI_RP_P2"
+ PIN 38: "MDI_RN_P2"
+ PIN 39: "MDI_TP_P2"
+ PIN 40: "MDI_TN_P2"
+ PIN 41: "MDI_TP_P3"
+ PIN 42: "MDI_TN_P3"
+ PIN 43: "MDI_RP_P3"
+ PIN 44: "MDI_RN_P3"
+ PIN 45: "MDI_RP_P4"
+ PIN 46: "MDI_RN_P4"
+ PIN 47: "MDI_TP_P4"
+ PIN 48: "MDI_TN_P4"
+ PIN 49: "SMI_MDC"
+ PIN 50: "SMI_MDIO"
+ PIN 51: "PCIE_PERESET_N"
+ PIN 52: "PWM_0"
+ PIN 53: "GPIO_0"
+ PIN 54: "GPIO_1"
+ PIN 55: "GPIO_2"
+ PIN 56: "GPIO_3"
+ PIN 57: "GPIO_4"
+ PIN 58: "GPIO_5"
+ PIN 59: "GPIO_6"
+ PIN 60: "GPIO_7"
+ PIN 61: "GPIO_8"
+ PIN 62: "SPI_CLK"
+ PIN 63: "SPI_CS"
+ PIN 64: "SPI_MOSI"
+ PIN 65: "SPI_MISO"
+ PIN 66: "SPI_WP"
+ PIN 67: "SPI_HOLD"
+ PIN 68: "UART0_TXD"
+ PIN 69: "UART0_RXD"
+ PIN 70: "TOP_2G_CLK"
+ PIN 71: "TOP_2G_DATA"
+ PIN 72: "WF0_2G_HB0"
+ PIN 73: "WF0_2G_HB1"
+ PIN 74: "WF0_2G_HB2"
+ PIN 75: "WF0_2G_HB3"
+ PIN 76: "WF0_2G_HB4"
+ PIN 77: "WF0_2G_HB5"
+ PIN 78: "WF0_2G_HB6"
+
+Valid values for function are:
+ "eth", "i2c", "led", "flash", "pcie", "pwm", "spi", "uart",
+ "watchdog", "wifi"
+
+Valid values for groups are:
+ Valid value function pins (in pin#)
+ ----------------------------------------------------------------
+ "mdc_mdio" "eth" 23, 24
+ "i2c_0" "i2c" 19, 20
+ "i2c_1" "i2c" 53, 54
+ "ephy_leds" "led" 12, 13, 14, 15, 16,
+ 17, 18
+ "ephy0_led" "led" 12
+ "ephy1_led" "led" 13
+ "ephy2_led" "led" 14
+ "ephy3_led" "led" 15
+ "ephy4_led" "led" 16
+ "wf2g_led" "led" 17
+ "wf5g_led" "led" 18
+ "snfi" "flash" 62, 63, 64, 65, 66, 67
+ "spi_nor" "flash" 62, 63, 64, 65, 66, 67
+ "pcie_pereset" "pcie" 51
+ "pcie_wake" "pcie" 55
+ "pcie_clkreq" "pcie" 56
+ "pwm_0" "pwm" 52
+ "pwm_1" "pwm" 61
+ "spi_0" "spi" 21, 22, 23, 24
+ "spi_1" "spi" 62, 63, 64, 65
+ "spi_wp" "spi" 66
+ "spi_hold" "spi" 67
+ "uart0_txd_rxd" "uart" 68, 69
+ "uart1_0_txd_rxd" "uart" 25, 26
+ "uart1_0_cts_rts" "uart" 27, 28
+ "uart1_1_txd_rxd" "uart" 53, 54
+ "uart1_1_cts_rts" "uart" 55, 56
+ "uart2_0_txd_rxd" "uart" 29, 30
+ "uart2_0_cts_rts" "uart" 31, 32
+ "uart2_1_txd_rxd" "uart" 57, 58
+ "uart2_1_cts_rts" "uart" 59, 60
+ "watchdog" "watchdog" 11
+ "wf0_2g" "wifi" 70, 71, 72, 73, 74,
+ 75, 76, 77, 78
+ "wf0_5g" "wifi" 0, 1, 2, 3, 4, 5, 6,
+ 7, 8, 9, 10
+
Example:
pio: pinctrl@10211000 {
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index ef4f2ff..48df30a 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -56,6 +56,7 @@
More details in Documentation/devicetree/bindings/gpio/gpio.txt.
- st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line
used to select GPIOs as interrupts).
+ - hwlocks: reference to a phandle of a hardware spinlock provider node.
Example 1:
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
diff --git a/drivers/pinctrl/actions/Kconfig b/drivers/pinctrl/actions/Kconfig
index 2397cb0..c7ed1d4 100644
--- a/drivers/pinctrl/actions/Kconfig
+++ b/drivers/pinctrl/actions/Kconfig
@@ -9,6 +9,12 @@
help
Say Y here to enable Actions Semi OWL pinctrl driver
+config PINCTRL_S700
+ bool "Actions Semi S700 pinctrl driver"
+ depends on PINCTRL_OWL
+ help
+ Say Y here to enable Actions Semi S700 pinctrl driver
+
config PINCTRL_S900
bool "Actions Semi S900 pinctrl driver"
depends on PINCTRL_OWL
diff --git a/drivers/pinctrl/actions/Makefile b/drivers/pinctrl/actions/Makefile
index bd232d2..86521ed 100644
--- a/drivers/pinctrl/actions/Makefile
+++ b/drivers/pinctrl/actions/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_PINCTRL_OWL) += pinctrl-owl.o
+obj-$(CONFIG_PINCTRL_S700) += pinctrl-s700.o
obj-$(CONFIG_PINCTRL_S900) += pinctrl-s900.o
diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c
index 9d18c02..5dfe718 100644
--- a/drivers/pinctrl/actions/pinctrl-owl.c
+++ b/drivers/pinctrl/actions/pinctrl-owl.c
@@ -246,60 +246,6 @@ static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
return 0;
}
-static int owl_pad_pinconf_arg2val(const struct owl_padinfo *info,
- unsigned int param,
- u32 *arg)
-{
- switch (param) {
- case PIN_CONFIG_BIAS_BUS_HOLD:
- *arg = OWL_PINCONF_PULL_HOLD;
- break;
- case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
- *arg = OWL_PINCONF_PULL_HIZ;
- break;
- case PIN_CONFIG_BIAS_PULL_DOWN:
- *arg = OWL_PINCONF_PULL_DOWN;
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- *arg = OWL_PINCONF_PULL_UP;
- break;
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- *arg = (*arg >= 1 ? 1 : 0);
- break;
- default:
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static int owl_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
- unsigned int param,
- u32 *arg)
-{
- switch (param) {
- case PIN_CONFIG_BIAS_BUS_HOLD:
- *arg = *arg == OWL_PINCONF_PULL_HOLD;
- break;
- case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
- *arg = *arg == OWL_PINCONF_PULL_HIZ;
- break;
- case PIN_CONFIG_BIAS_PULL_DOWN:
- *arg = *arg == OWL_PINCONF_PULL_DOWN;
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- *arg = *arg == OWL_PINCONF_PULL_UP;
- break;
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- *arg = *arg == 1;
- break;
- default:
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
unsigned int pin,
unsigned long *config)
@@ -318,7 +264,10 @@ static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
arg = owl_read_field(pctrl, reg, bit, width);
- ret = owl_pad_pinconf_val2arg(info, param, &arg);
+ if (!pctrl->soc->padctl_val2arg)
+ return -ENOTSUPP;
+
+ ret = pctrl->soc->padctl_val2arg(info, param, &arg);
if (ret)
return ret;
@@ -349,7 +298,10 @@ static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
if (ret)
return ret;
- ret = owl_pad_pinconf_arg2val(info, param, &arg);
+ if (!pctrl->soc->padctl_arg2val)
+ return -ENOTSUPP;
+
+ ret = pctrl->soc->padctl_arg2val(info, param, &arg);
if (ret)
return ret;
@@ -787,7 +739,7 @@ static void owl_gpio_irq_mask(struct irq_data *data)
val = readl_relaxed(gpio_base + port->intc_msk);
if (val == 0)
owl_gpio_update_reg(gpio_base + port->intc_ctl,
- OWL_GPIO_CTLR_ENABLE, false);
+ OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
@@ -811,7 +763,8 @@ static void owl_gpio_irq_unmask(struct irq_data *data)
/* enable port interrupt */
value = readl_relaxed(gpio_base + port->intc_ctl);
- value |= BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M);
+ value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M))
+ << port->shared_ctl_offset * 5);
writel_relaxed(value, gpio_base + port->intc_ctl);
/* enable GPIO interrupt */
@@ -849,7 +802,7 @@ static void owl_gpio_irq_ack(struct irq_data *data)
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->intc_ctl,
- OWL_GPIO_CTLR_PENDING, true);
+ OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
diff --git a/drivers/pinctrl/actions/pinctrl-owl.h b/drivers/pinctrl/actions/pinctrl-owl.h
index a724d1d..dae2e836 100644
--- a/drivers/pinctrl/actions/pinctrl-owl.h
+++ b/drivers/pinctrl/actions/pinctrl-owl.h
@@ -15,12 +15,135 @@
#define OWL_PINCONF_SLEW_SLOW 0
#define OWL_PINCONF_SLEW_FAST 1
-enum owl_pinconf_pull {
- OWL_PINCONF_PULL_HIZ,
- OWL_PINCONF_PULL_DOWN,
- OWL_PINCONF_PULL_UP,
- OWL_PINCONF_PULL_HOLD,
-};
+#define MUX_PG(group_name, reg, shift, width) \
+ { \
+ .name = #group_name, \
+ .pads = group_name##_pads, \
+ .npads = ARRAY_SIZE(group_name##_pads), \
+ .funcs = group_name##_funcs, \
+ .nfuncs = ARRAY_SIZE(group_name##_funcs), \
+ .mfpctl_reg = MFCTL##reg, \
+ .mfpctl_shift = shift, \
+ .mfpctl_width = width, \
+ .drv_reg = -1, \
+ .drv_shift = -1, \
+ .drv_width = -1, \
+ .sr_reg = -1, \
+ .sr_shift = -1, \
+ .sr_width = -1, \
+ }
+
+#define DRV_PG(group_name, reg, shift, width) \
+ { \
+ .name = #group_name, \
+ .pads = group_name##_pads, \
+ .npads = ARRAY_SIZE(group_name##_pads), \
+ .mfpctl_reg = -1, \
+ .mfpctl_shift = -1, \
+ .mfpctl_width = -1, \
+ .drv_reg = PAD_DRV##reg, \
+ .drv_shift = shift, \
+ .drv_width = width, \
+ .sr_reg = -1, \
+ .sr_shift = -1, \
+ .sr_width = -1, \
+ }
+
+#define SR_PG(group_name, reg, shift, width) \
+ { \
+ .name = #group_name, \
+ .pads = group_name##_pads, \
+ .npads = ARRAY_SIZE(group_name##_pads), \
+ .mfpctl_reg = -1, \
+ .mfpctl_shift = -1, \
+ .mfpctl_width = -1, \
+ .drv_reg = -1, \
+ .drv_shift = -1, \
+ .drv_width = -1, \
+ .sr_reg = PAD_SR##reg, \
+ .sr_shift = shift, \
+ .sr_width = width, \
+ }
+
+#define FUNCTION(fname) \
+ { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+/* PAD PULL UP/DOWN CONFIGURES */
+#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \
+ { \
+ .reg = PAD_PULLCTL##pull_reg, \
+ .shift = pull_sft, \
+ .width = pull_wdt, \
+ }
+
+#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \
+ struct owl_pullctl pad_name##_pullctl_conf \
+ = PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
+
+#define ST_CONF(st_reg, st_sft, st_wdt) \
+ { \
+ .reg = PAD_ST##st_reg, \
+ .shift = st_sft, \
+ .width = st_wdt, \
+ }
+
+#define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \
+ struct owl_st pad_name##_st_conf \
+ = ST_CONF(st_reg, st_sft, st_wdt)
+
+#define PAD_INFO(name) \
+ { \
+ .pad = name, \
+ .pullctl = NULL, \
+ .st = NULL, \
+ }
+
+#define PAD_INFO_ST(name) \
+ { \
+ .pad = name, \
+ .pullctl = NULL, \
+ .st = &name##_st_conf, \
+ }
+
+#define PAD_INFO_PULLCTL(name) \
+ { \
+ .pad = name, \
+ .pullctl = &name##_pullctl_conf, \
+ .st = NULL, \
+ }
+
+#define PAD_INFO_PULLCTL_ST(name) \
+ { \
+ .pad = name, \
+ .pullctl = &name##_pullctl_conf, \
+ .st = &name##_st_conf, \
+ }
+
+#define OWL_GPIO_PORT_A 0
+#define OWL_GPIO_PORT_B 1
+#define OWL_GPIO_PORT_C 2
+#define OWL_GPIO_PORT_D 3
+#define OWL_GPIO_PORT_E 4
+#define OWL_GPIO_PORT_F 5
+
+#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, _intc_ctl,\
+ _intc_pd, _intc_msk, _intc_type, _share) \
+ [OWL_GPIO_PORT_##port] = { \
+ .offset = base, \
+ .pins = count, \
+ .outen = _outen, \
+ .inen = _inen, \
+ .dat = _dat, \
+ .intc_ctl = _intc_ctl, \
+ .intc_pd = _intc_pd, \
+ .intc_msk = _intc_msk, \
+ .intc_type = _intc_type, \
+ .shared_ctl_offset = _share, \
+ }
enum owl_pinconf_drv {
OWL_PINCONF_DRV_2MA,
@@ -148,6 +271,7 @@ struct owl_gpio_port {
unsigned int intc_pd;
unsigned int intc_msk;
unsigned int intc_type;
+ u8 shared_ctl_offset;
};
/**
@@ -174,6 +298,12 @@ struct owl_pinctrl_soc_data {
unsigned int ngpios;
const struct owl_gpio_port *ports;
unsigned int nports;
+ int (*padctl_val2arg)(const struct owl_padinfo *padinfo,
+ unsigned int param,
+ u32 *arg);
+ int (*padctl_arg2val)(const struct owl_padinfo *info,
+ unsigned int param,
+ u32 *arg);
};
int owl_pinctrl_probe(struct platform_device *pdev,
diff --git a/drivers/pinctrl/actions/pinctrl-s700.c b/drivers/pinctrl/actions/pinctrl-s700.c
new file mode 100644
index 0000000..8b8121e
--- /dev/null
+++ b/drivers/pinctrl/actions/pinctrl-s700.c
@@ -0,0 +1,1912 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Actions Semi Owl S700 Pinctrl driver
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <[email protected]>
+ *
+ * Author: Pathiban Nallathambi <[email protected]>
+ * Author: Saravanan Sekar <[email protected]>
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-owl.h"
+
+/* Pinctrl registers offset */
+#define MFCTL0 (0x0040)
+#define MFCTL1 (0x0044)
+#define MFCTL2 (0x0048)
+#define MFCTL3 (0x004C)
+#define PAD_PULLCTL0 (0x0060)
+#define PAD_PULLCTL1 (0x0064)
+#define PAD_PULLCTL2 (0x0068)
+#define PAD_ST0 (0x006C)
+#define PAD_ST1 (0x0070)
+#define PAD_CTL (0x0074)
+#define PAD_DRV0 (0x0080)
+#define PAD_DRV1 (0x0084)
+#define PAD_DRV2 (0x0088)
+
+/*
+ * Most pins affected by the pinmux can also be GPIOs. Define these first.
+ * These must match how the GPIO driver names/numbers its pins.
+ */
+#define _GPIOA(offset) (offset)
+#define _GPIOB(offset) (32 + (offset))
+#define _GPIOC(offset) (64 + (offset))
+#define _GPIOD(offset) (96 + (offset))
+#define _GPIOE(offset) (128 + (offset))
+
+/* All non-GPIO pins follow */
+#define NUM_GPIOS (_GPIOE(7) + 1)
+#define _PIN(offset) (NUM_GPIOS + (offset))
+
+/* Ethernet MAC */
+#define ETH_TXD0 _GPIOA(14)
+#define ETH_TXD1 _GPIOA(15)
+#define ETH_TXD2 _GPIOE(4)
+#define ETH_TXD3 _GPIOE(5)
+#define ETH_TXEN _GPIOA(16)
+#define ETH_RXER _GPIOA(17)
+#define ETH_CRS_DV _GPIOA(18)
+#define ETH_RXD1 _GPIOA(19)
+#define ETH_RXD0 _GPIOA(20)
+#define ETH_RXD2 _GPIOE(6)
+#define ETH_RXD3 _GPIOE(7)
+#define ETH_REF_CLK _GPIOA(21)
+#define ETH_MDC _GPIOA(22)
+#define ETH_MDIO _GPIOA(23)
+
+/* SIRQ */
+#define SIRQ0 _GPIOA(24)
+#define SIRQ1 _GPIOA(25)
+#define SIRQ2 _GPIOA(26)
+
+/* I2S */
+#define I2S_D0 _GPIOA(27)
+#define I2S_BCLK0 _GPIOA(28)
+#define I2S_LRCLK0 _GPIOA(29)
+#define I2S_MCLK0 _GPIOA(30)
+#define I2S_D1 _GPIOA(31)
+#define I2S_BCLK1 _GPIOB(0)
+#define I2S_LRCLK1 _GPIOB(1)
+#define I2S_MCLK1 _GPIOB(2)
+
+/* PCM1 */
+#define PCM1_IN _GPIOD(28)
+#define PCM1_CLK _GPIOD(29)
+#define PCM1_SYNC _GPIOD(30)
+#define PCM1_OUT _GPIOD(31)
+
+/* KEY */
+#define KS_IN0 _GPIOB(3)
+#define KS_IN1 _GPIOB(4)
+#define KS_IN2 _GPIOB(5)
+#define KS_IN3 _GPIOB(6)
+#define KS_OUT0 _GPIOB(7)
+#define KS_OUT1 _GPIOB(8)
+#define KS_OUT2 _GPIOB(9)
+
+/* LVDS */
+#define LVDS_OEP _GPIOB(10)
+#define LVDS_OEN _GPIOB(11)
+#define LVDS_ODP _GPIOB(12)
+#define LVDS_ODN _GPIOB(13)
+#define LVDS_OCP _GPIOB(14)
+#define LVDS_OCN _GPIOB(15)
+#define LVDS_OBP _GPIOB(16)
+#define LVDS_OBN _GPIOB(17)
+#define LVDS_OAP _GPIOB(18)
+#define LVDS_OAN _GPIOB(19)
+#define LVDS_EEP _GPIOB(20)
+#define LVDS_EEN _GPIOB(21)
+#define LVDS_EDP _GPIOB(22)
+#define LVDS_EDN _GPIOB(23)
+#define LVDS_ECP _GPIOB(24)
+#define LVDS_ECN _GPIOB(25)
+#define LVDS_EBP _GPIOB(26)
+#define LVDS_EBN _GPIOB(27)
+#define LVDS_EAP _GPIOB(28)
+#define LVDS_EAN _GPIOB(29)
+#define LCD0_D18 _GPIOB(30)
+#define LCD0_D2 _GPIOB(31)
+
+/* DSI */
+#define DSI_DP3 _GPIOC(0)
+#define DSI_DN3 _GPIOC(1)
+#define DSI_DP1 _GPIOC(2)
+#define DSI_DN1 _GPIOC(3)
+#define DSI_CP _GPIOC(4)
+#define DSI_CN _GPIOC(5)
+#define DSI_DP0 _GPIOC(6)
+#define DSI_DN0 _GPIOC(7)
+#define DSI_DP2 _GPIOC(8)
+#define DSI_DN2 _GPIOC(9)
+
+/* SD */
+#define SD0_D0 _GPIOC(10)
+#define SD0_D1 _GPIOC(11)
+#define SD0_D2 _GPIOC(12)
+#define SD0_D3 _GPIOC(13)
+#define SD0_D4 _GPIOC(14)
+#define SD0_D5 _GPIOC(15)
+#define SD0_D6 _GPIOC(16)
+#define SD0_D7 _GPIOC(17)
+#define SD0_CMD _GPIOC(18)
+#define SD0_CLK _GPIOC(19)
+#define SD1_CMD _GPIOC(20)
+#define SD1_CLK _GPIOC(21)
+#define SD1_D0 SD0_D4
+#define SD1_D1 SD0_D5
+#define SD1_D2 SD0_D6
+#define SD1_D3 SD0_D7
+
+/* SPI */
+#define SPI0_SS _GPIOC(23)
+#define SPI0_MISO _GPIOC(24)
+
+/* UART for console */
+#define UART0_RX _GPIOC(26)
+#define UART0_TX _GPIOC(27)
+
+/* UART for Bluetooth */
+#define UART2_RX _GPIOD(18)
+#define UART2_TX _GPIOD(19)
+#define UART2_RTSB _GPIOD(20)
+#define UART2_CTSB _GPIOD(21)
+
+/* UART for 3G */
+#define UART3_RX _GPIOD(22)
+#define UART3_TX _GPIOD(23)
+#define UART3_RTSB _GPIOD(24)
+#define UART3_CTSB _GPIOD(25)
+
+/* I2C */
+#define I2C0_SCLK _GPIOC(28)
+#define I2C0_SDATA _GPIOC(29)
+#define I2C1_SCLK _GPIOE(0)
+#define I2C1_SDATA _GPIOE(1)
+#define I2C2_SCLK _GPIOE(2)
+#define I2C2_SDATA _GPIOE(3)
+
+/* CSI*/
+#define CSI_DN0 _PIN(0)
+#define CSI_DP0 _PIN(1)
+#define CSI_DN1 _PIN(2)
+#define CSI_DP1 _PIN(3)
+#define CSI_CN _PIN(4)
+#define CSI_CP _PIN(5)
+#define CSI_DN2 _PIN(6)
+#define CSI_DP2 _PIN(7)
+#define CSI_DN3 _PIN(8)
+#define CSI_DP3 _PIN(9)
+
+/* Sensor */
+#define SENSOR0_PCLK _GPIOC(31)
+#define SENSOR0_CKOUT _GPIOD(10)
+
+/* NAND (1.8v / 3.3v) */
+#define DNAND_D0 _PIN(10)
+#define DNAND_D1 _PIN(11)
+#define DNAND_D2 _PIN(12)
+#define DNAND_D3 _PIN(13)
+#define DNAND_D4 _PIN(14)
+#define DNAND_D5 _PIN(15)
+#define DNAND_D6 _PIN(16)
+#define DNAND_D7 _PIN(17)
+#define DNAND_WRB _PIN(18)
+#define DNAND_RDB _PIN(19)
+#define DNAND_RDBN _PIN(20)
+#define DNAND_DQS _GPIOA(12)
+#define DNAND_DQSN _GPIOA(13)
+#define DNAND_RB0 _PIN(21)
+#define DNAND_ALE _GPIOD(12)
+#define DNAND_CLE _GPIOD(13)
+#define DNAND_CEB0 _GPIOD(14)
+#define DNAND_CEB1 _GPIOD(15)
+#define DNAND_CEB2 _GPIOD(16)
+#define DNAND_CEB3 _GPIOD(17)
+
+/* System */
+#define PORB _PIN(22)
+#define CLKO_25M _PIN(23)
+#define BSEL _PIN(24)
+#define PKG0 _PIN(25)
+#define PKG1 _PIN(26)
+#define PKG2 _PIN(27)
+#define PKG3 _PIN(28)
+
+#define _FIRSTPAD _GPIOA(0)
+#define _LASTPAD PKG3
+#define NUM_PADS (_PIN(28) + 1)
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc s700_pads[] = {
+ PINCTRL_PIN(ETH_TXD0, "eth_txd0"),
+ PINCTRL_PIN(ETH_TXD1, "eth_txd1"),
+ PINCTRL_PIN(ETH_TXD2, "eth_txd2"),
+ PINCTRL_PIN(ETH_TXD3, "eth_txd3"),
+ PINCTRL_PIN(ETH_TXEN, "eth_txen"),
+ PINCTRL_PIN(ETH_RXER, "eth_rxer"),
+ PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"),
+ PINCTRL_PIN(ETH_RXD1, "eth_rxd1"),
+ PINCTRL_PIN(ETH_RXD0, "eth_rxd0"),
+ PINCTRL_PIN(ETH_RXD2, "eth_rxd2"),
+ PINCTRL_PIN(ETH_RXD3, "eth_rxd3"),
+ PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"),
+ PINCTRL_PIN(ETH_MDC, "eth_mdc"),
+ PINCTRL_PIN(ETH_MDIO, "eth_mdio"),
+ PINCTRL_PIN(SIRQ0, "sirq0"),
+ PINCTRL_PIN(SIRQ1, "sirq1"),
+ PINCTRL_PIN(SIRQ2, "sirq2"),
+ PINCTRL_PIN(I2S_D0, "i2s_d0"),
+ PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"),
+ PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"),
+ PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"),
+ PINCTRL_PIN(I2S_D1, "i2s_d1"),
+ PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"),
+ PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"),
+ PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"),
+ PINCTRL_PIN(PCM1_IN, "pcm1_in"),
+ PINCTRL_PIN(PCM1_CLK, "pcm1_clk"),
+ PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"),
+ PINCTRL_PIN(PCM1_OUT, "pcm1_out"),
+ PINCTRL_PIN(KS_IN0, "ks_in0"),
+ PINCTRL_PIN(KS_IN1, "ks_in1"),
+ PINCTRL_PIN(KS_IN2, "ks_in2"),
+ PINCTRL_PIN(KS_IN3, "ks_in3"),
+ PINCTRL_PIN(KS_OUT0, "ks_out0"),
+ PINCTRL_PIN(KS_OUT1, "ks_out1"),
+ PINCTRL_PIN(KS_OUT2, "ks_out2"),
+ PINCTRL_PIN(LVDS_OEP, "lvds_oep"),
+ PINCTRL_PIN(LVDS_OEN, "lvds_oen"),
+ PINCTRL_PIN(LVDS_ODP, "lvds_odp"),
+ PINCTRL_PIN(LVDS_ODN, "lvds_odn"),
+ PINCTRL_PIN(LVDS_OCP, "lvds_ocp"),
+ PINCTRL_PIN(LVDS_OCN, "lvds_ocn"),
+ PINCTRL_PIN(LVDS_OBP, "lvds_obp"),
+ PINCTRL_PIN(LVDS_OBN, "lvds_obn"),
+ PINCTRL_PIN(LVDS_OAP, "lvds_oap"),
+ PINCTRL_PIN(LVDS_OAN, "lvds_oan"),
+ PINCTRL_PIN(LVDS_EEP, "lvds_eep"),
+ PINCTRL_PIN(LVDS_EEN, "lvds_een"),
+ PINCTRL_PIN(LVDS_EDP, "lvds_edp"),
+ PINCTRL_PIN(LVDS_EDN, "lvds_edn"),
+ PINCTRL_PIN(LVDS_ECP, "lvds_ecp"),
+ PINCTRL_PIN(LVDS_ECN, "lvds_ecn"),
+ PINCTRL_PIN(LVDS_EBP, "lvds_ebp"),
+ PINCTRL_PIN(LVDS_EBN, "lvds_ebn"),
+ PINCTRL_PIN(LVDS_EAP, "lvds_eap"),
+ PINCTRL_PIN(LVDS_EAN, "lvds_ean"),
+ PINCTRL_PIN(LCD0_D18, "lcd0_d18"),
+ PINCTRL_PIN(LCD0_D2, "lcd0_d2"),
+ PINCTRL_PIN(DSI_DP3, "dsi_dp3"),
+ PINCTRL_PIN(DSI_DN3, "dsi_dn3"),
+ PINCTRL_PIN(DSI_DP1, "dsi_dp1"),
+ PINCTRL_PIN(DSI_DN1, "dsi_dn1"),
+ PINCTRL_PIN(DSI_CP, "dsi_cp"),
+ PINCTRL_PIN(DSI_CN, "dsi_cn"),
+ PINCTRL_PIN(DSI_DP0, "dsi_dp0"),
+ PINCTRL_PIN(DSI_DN0, "dsi_dn0"),
+ PINCTRL_PIN(DSI_DP2, "dsi_dp2"),
+ PINCTRL_PIN(DSI_DN2, "dsi_dn2"),
+ PINCTRL_PIN(SD0_D0, "sd0_d0"),
+ PINCTRL_PIN(SD0_D1, "sd0_d1"),
+ PINCTRL_PIN(SD0_D2, "sd0_d2"),
+ PINCTRL_PIN(SD0_D3, "sd0_d3"),
+ PINCTRL_PIN(SD1_D0, "sd1_d0"),
+ PINCTRL_PIN(SD1_D1, "sd1_d1"),
+ PINCTRL_PIN(SD1_D2, "sd1_d2"),
+ PINCTRL_PIN(SD1_D3, "sd1_d3"),
+ PINCTRL_PIN(SD0_CMD, "sd0_cmd"),
+ PINCTRL_PIN(SD0_CLK, "sd0_clk"),
+ PINCTRL_PIN(SD1_CMD, "sd1_cmd"),
+ PINCTRL_PIN(SD1_CLK, "sd1_clk"),
+ PINCTRL_PIN(SPI0_SS, "spi0_ss"),
+ PINCTRL_PIN(SPI0_MISO, "spi0_miso"),
+ PINCTRL_PIN(UART0_RX, "uart0_rx"),
+ PINCTRL_PIN(UART0_TX, "uart0_tx"),
+ PINCTRL_PIN(UART2_RX, "uart2_rx"),
+ PINCTRL_PIN(UART2_TX, "uart2_tx"),
+ PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"),
+ PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"),
+ PINCTRL_PIN(UART3_RX, "uart3_rx"),
+ PINCTRL_PIN(UART3_TX, "uart3_tx"),
+ PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"),
+ PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"),
+ PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"),
+ PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"),
+ PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"),
+ PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"),
+ PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"),
+ PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"),
+ PINCTRL_PIN(CSI_DN0, "csi_dn0"),
+ PINCTRL_PIN(CSI_DP0, "csi_dp0"),
+ PINCTRL_PIN(CSI_DN1, "csi_dn1"),
+ PINCTRL_PIN(CSI_DP1, "csi_dp1"),
+ PINCTRL_PIN(CSI_CN, "csi_cn"),
+ PINCTRL_PIN(CSI_CP, "csi_cp"),
+ PINCTRL_PIN(CSI_DN2, "csi_dn2"),
+ PINCTRL_PIN(CSI_DP2, "csi_dp2"),
+ PINCTRL_PIN(CSI_DN3, "csi_dn3"),
+ PINCTRL_PIN(CSI_DP3, "csi_dp3"),
+ PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"),
+ PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"),
+ PINCTRL_PIN(DNAND_D0, "dnand_d0"),
+ PINCTRL_PIN(DNAND_D1, "dnand_d1"),
+ PINCTRL_PIN(DNAND_D2, "dnand_d2"),
+ PINCTRL_PIN(DNAND_D3, "dnand_d3"),
+ PINCTRL_PIN(DNAND_D4, "dnand_d4"),
+ PINCTRL_PIN(DNAND_D5, "dnand_d5"),
+ PINCTRL_PIN(DNAND_D6, "dnand_d6"),
+ PINCTRL_PIN(DNAND_D7, "dnand_d7"),
+ PINCTRL_PIN(DNAND_WRB, "dnand_wrb"),
+ PINCTRL_PIN(DNAND_RDB, "dnand_rdb"),
+ PINCTRL_PIN(DNAND_RDBN, "dnand_rdbn"),
+ PINCTRL_PIN(DNAND_DQS, "dnand_dqs"),
+ PINCTRL_PIN(DNAND_DQSN, "dnand_dqsn"),
+ PINCTRL_PIN(DNAND_RB0, "dnand_rb0"),
+ PINCTRL_PIN(DNAND_ALE, "dnand_ale"),
+ PINCTRL_PIN(DNAND_CLE, "dnand_cle"),
+ PINCTRL_PIN(DNAND_CEB0, "dnand_ceb0"),
+ PINCTRL_PIN(DNAND_CEB1, "dnand_ceb1"),
+ PINCTRL_PIN(DNAND_CEB2, "dnand_ceb2"),
+ PINCTRL_PIN(DNAND_CEB3, "dnand_ceb3"),
+ PINCTRL_PIN(PORB, "porb"),
+ PINCTRL_PIN(CLKO_25M, "clko_25m"),
+ PINCTRL_PIN(BSEL, "bsel"),
+ PINCTRL_PIN(PKG0, "pkg0"),
+ PINCTRL_PIN(PKG1, "pkg1"),
+ PINCTRL_PIN(PKG2, "pkg2"),
+ PINCTRL_PIN(PKG3, "pkg3"),
+};
+
+enum s700_pinmux_functions {
+ S700_MUX_NOR,
+ S700_MUX_ETH_RGMII,
+ S700_MUX_ETH_SGMII,
+ S700_MUX_SPI0,
+ S700_MUX_SPI1,
+ S700_MUX_SPI2,
+ S700_MUX_SPI3,
+ S700_MUX_SENS0,
+ S700_MUX_SENS1,
+ S700_MUX_UART0,
+ S700_MUX_UART1,
+ S700_MUX_UART2,
+ S700_MUX_UART3,
+ S700_MUX_UART4,
+ S700_MUX_UART5,
+ S700_MUX_UART6,
+ S700_MUX_I2S0,
+ S700_MUX_I2S1,
+ S700_MUX_PCM1,
+ S700_MUX_PCM0,
+ S700_MUX_KS,
+ S700_MUX_JTAG,
+ S700_MUX_PWM0,
+ S700_MUX_PWM1,
+ S700_MUX_PWM2,
+ S700_MUX_PWM3,
+ S700_MUX_PWM4,
+ S700_MUX_PWM5,
+ S700_MUX_P0,
+ S700_MUX_SD0,
+ S700_MUX_SD1,
+ S700_MUX_SD2,
+ S700_MUX_I2C0,
+ S700_MUX_I2C1,
+ S700_MUX_I2C2,
+ S700_MUX_I2C3,
+ S700_MUX_DSI,
+ S700_MUX_LVDS,
+ S700_MUX_USB30,
+ S700_MUX_CLKO_25M,
+ S700_MUX_MIPI_CSI,
+ S700_MUX_NAND,
+ S700_MUX_SPDIF,
+ S700_MUX_SIRQ0,
+ S700_MUX_SIRQ1,
+ S700_MUX_SIRQ2,
+ S700_MUX_BT,
+ S700_MUX_LCD0,
+ S700_MUX_RESERVED,
+};
+
+/* mfp0_31_30 reserved */
+
+/* rgmii_txd23 */
+static unsigned int rgmii_txd23_mfp_pads[] = { ETH_TXD2, ETH_TXD3};
+static unsigned int rgmii_txd23_mfp_funcs[] = { S700_MUX_ETH_RGMII,
+ S700_MUX_I2C1,
+ S700_MUX_UART3 };
+/* rgmii_rxd2 */
+static unsigned int rgmii_rxd2_mfp_pads[] = { ETH_RXD2 };
+static unsigned int rgmii_rxd2_mfp_funcs[] = { S700_MUX_ETH_RGMII,
+ S700_MUX_PWM0,
+ S700_MUX_UART3 };
+/* rgmii_rxd3 */
+static unsigned int rgmii_rxd3_mfp_pads[] = { ETH_RXD3};
+static unsigned int rgmii_rxd3_mfp_funcs[] = { S700_MUX_ETH_RGMII,
+ S700_MUX_PWM2,
+ S700_MUX_UART3 };
+/* lcd0_d18 */
+static unsigned int lcd0_d18_mfp_pads[] = { LCD0_D18 };
+static unsigned int lcd0_d18_mfp_funcs[] = { S700_MUX_NOR,
+ S700_MUX_SENS1,
+ S700_MUX_PWM2,
+ S700_MUX_PWM4,
+ S700_MUX_LCD0 };
+/* rgmii_txd01 */
+static unsigned int rgmii_txd01_mfp_pads[] = { ETH_CRS_DV };
+static unsigned int rgmii_txd01_mfp_funcs[] = { S700_MUX_ETH_RGMII,
+ S700_MUX_RESERVED,
+ S700_MUX_SPI2,
+ S700_MUX_UART4,
+ S700_MUX_PWM4 };
+/* rgmii_txd0 */
+static unsigned int rgmii_txd0_mfp_pads[] = { ETH_TXD0 };
+static unsigned int rgmii_txd0_mfp_funcs[] = { S700_MUX_ETH_RGMII,
+ S700_MUX_ETH_SGMII,
+ S700_MUX_SPI2,
+ S700_MUX_UART6,
+ S700_MUX_PWM4 };
+/* rgmii_txd1 */
+static unsigned int rgmii_txd1_mfp_pads[] = { ETH_TXD1 };
+static unsigned int rgmii_txd1_mfp_funcs[] = { S700_MUX_ETH_RGMII,
+ S700_MUX_ETH_SGMII,
+ S700_MUX_SPI2,
+ S700_MUX_UART6,
+ S700_MUX_PWM5 };
+/* rgmii_txen */
+static unsigned int rgmii_txen_mfp_pads[] = { ETH_TXEN };
+static unsigned int rgmii_txen_mfp_funcs[] = { S700_MUX_ETH_RGMII,
+ S700_MUX_UART2,
+ S700_MUX_SPI3,
+ S700_MUX_PWM0 };
+/* rgmii_rxen */
+static unsigned int rgmii_rxen_mfp_pads[] = { ETH_RXER };
+static unsigned int rgmii_rxen_mfp_funcs[] = { S700_MUX_ETH_RGMII,
+ S700_MUX_UART2,
+ S700_MUX_SPI3,
+ S700_MUX_PWM1 };
+/* mfp0_12_11 reserved */
+/* rgmii_rxd1*/
+static unsigned int rgmii_rxd1_mfp_pads[] = { ETH_RXD1 };
+static unsigned int rgmii_rxd1_mfp_funcs[] = { S700_MUX_ETH_RGMII,
+ S700_MUX_UART2,
+ S700_MUX_SPI3,
+ S700_MUX_PWM2,
+ S700_MUX_UART5,
+ S700_MUX_ETH_SGMII };
+/* rgmii_rxd0 */
+static unsigned int rgmii_rxd0_mfp_pads[] = { ETH_RXD0 };
+static unsigned int rgmii_rxd0_mfp_funcs[] = { S700_MUX_ETH_RGMII,
+ S700_MUX_UART2,
+ S700_MUX_SPI3,
+ S700_MUX_PWM3,
+ S700_MUX_UART5,
+ S700_MUX_ETH_SGMII };
+/* rgmii_ref_clk */
+static unsigned int rgmii_ref_clk_mfp_pads[] = { ETH_REF_CLK };
+static unsigned int rgmii_ref_clk_mfp_funcs[] = { S700_MUX_ETH_RGMII,
+ S700_MUX_UART4,
+ S700_MUX_SPI2,
+ S700_MUX_RESERVED,
+ S700_MUX_ETH_SGMII };
+/* i2s_d0 */
+static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 };
+static unsigned int i2s_d0_mfp_funcs[] = { S700_MUX_I2S0,
+ S700_MUX_NOR };
+/* i2s_pcm1 */
+static unsigned int i2s_pcm1_mfp_pads[] = { I2S_LRCLK0,
+ I2S_MCLK0 };
+static unsigned int i2s_pcm1_mfp_funcs[] = { S700_MUX_I2S0,
+ S700_MUX_NOR,
+ S700_MUX_PCM1,
+ S700_MUX_BT };
+/* i2s0_pcm0 */
+static unsigned int i2s0_pcm0_mfp_pads[] = { I2S_BCLK0 };
+static unsigned int i2s0_pcm0_mfp_funcs[] = { S700_MUX_I2S0,
+ S700_MUX_NOR,
+ S700_MUX_PCM0,
+ S700_MUX_BT };
+/* i2s1_pcm0 */
+static unsigned int i2s1_pcm0_mfp_pads[] = { I2S_BCLK1,
+ I2S_LRCLK1,
+ I2S_MCLK1 };
+
+static unsigned int i2s1_pcm0_mfp_funcs[] = { S700_MUX_I2S1,
+ S700_MUX_NOR,
+ S700_MUX_PCM0,
+ S700_MUX_BT };
+/* i2s_d1 */
+static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 };
+static unsigned int i2s_d1_mfp_funcs[] = { S700_MUX_I2S1,
+ S700_MUX_NOR };
+/* ks_in2 */
+static unsigned int ks_in2_mfp_pads[] = { KS_IN2 };
+static unsigned int ks_in2_mfp_funcs[] = { S700_MUX_KS,
+ S700_MUX_JTAG,
+ S700_MUX_NOR,
+ S700_MUX_BT,
+ S700_MUX_PWM0,
+ S700_MUX_SENS1,
+ S700_MUX_PWM0,
+ S700_MUX_P0 };
+/* ks_in1 */
+static unsigned int ks_in1_mfp_pads[] = { KS_IN1 };
+static unsigned int ks_in1_mfp_funcs[] = { S700_MUX_KS,
+ S700_MUX_JTAG,
+ S700_MUX_NOR,
+ S700_MUX_BT,
+ S700_MUX_PWM5,
+ S700_MUX_SENS1,
+ S700_MUX_PWM1,
+ S700_MUX_USB30 };
+/* ks_in0 */
+static unsigned int ks_in0_mfp_pads[] = { KS_IN0 };
+static unsigned int ks_in0_mfp_funcs[] = { S700_MUX_KS,
+ S700_MUX_JTAG,
+ S700_MUX_NOR,
+ S700_MUX_BT,
+ S700_MUX_PWM4,
+ S700_MUX_SENS1,
+ S700_MUX_PWM4,
+ S700_MUX_P0 };
+/* ks_in3 */
+static unsigned int ks_in3_mfp_pads[] = { KS_IN3 };
+static unsigned int ks_in3_mfp_funcs[] = { S700_MUX_KS,
+ S700_MUX_JTAG,
+ S700_MUX_NOR,
+ S700_MUX_PWM1,
+ S700_MUX_BT,
+ S700_MUX_SENS1 };
+/* ks_out0 */
+static unsigned int ks_out0_mfp_pads[] = { KS_OUT0 };
+static unsigned int ks_out0_mfp_funcs[] = { S700_MUX_KS,
+ S700_MUX_UART5,
+ S700_MUX_NOR,
+ S700_MUX_PWM2,
+ S700_MUX_BT,
+ S700_MUX_SENS1,
+ S700_MUX_SD0,
+ S700_MUX_UART4 };
+
+/* ks_out1 */
+static unsigned int ks_out1_mfp_pads[] = { KS_OUT1 };
+static unsigned int ks_out1_mfp_funcs[] = { S700_MUX_KS,
+ S700_MUX_JTAG,
+ S700_MUX_NOR,
+ S700_MUX_PWM3,
+ S700_MUX_BT,
+ S700_MUX_SENS1,
+ S700_MUX_SD0,
+ S700_MUX_UART4 };
+/* ks_out2 */
+static unsigned int ks_out2_mfp_pads[] = { KS_OUT2 };
+static unsigned int ks_out2_mfp_funcs[] = { S700_MUX_SD0,
+ S700_MUX_KS,
+ S700_MUX_NOR,
+ S700_MUX_PWM2,
+ S700_MUX_UART5,
+ S700_MUX_SENS1,
+ S700_MUX_BT };
+/* lvds_o_pn */
+static unsigned int lvds_o_pn_mfp_pads[] = { LVDS_OEP,
+ LVDS_OEN,
+ LVDS_ODP,
+ LVDS_ODN,
+ LVDS_OCP,
+ LVDS_OCN,
+ LVDS_OBP,
+ LVDS_OBN,
+ LVDS_OAP,
+ LVDS_OAN };
+
+static unsigned int lvds_o_pn_mfp_funcs[] = { S700_MUX_LVDS,
+ S700_MUX_BT,
+ S700_MUX_LCD0 };
+
+/* dsi_dn0 */
+static unsigned int dsi_dn0_mfp_pads[] = { DSI_DN0 };
+static unsigned int dsi_dn0_mfp_funcs[] = { S700_MUX_DSI,
+ S700_MUX_UART2,
+ S700_MUX_SPI0 };
+/* dsi_dp2 */
+static unsigned int dsi_dp2_mfp_pads[] = { DSI_DP2 };
+static unsigned int dsi_dp2_mfp_funcs[] = { S700_MUX_DSI,
+ S700_MUX_UART2,
+ S700_MUX_SPI0,
+ S700_MUX_SD1 };
+/* lcd0_d2 */
+static unsigned int lcd0_d2_mfp_pads[] = { LCD0_D2 };
+static unsigned int lcd0_d2_mfp_funcs[] = { S700_MUX_NOR,
+ S700_MUX_SD0,
+ S700_MUX_RESERVED,
+ S700_MUX_PWM3,
+ S700_MUX_LCD0 };
+/* dsi_dp3 */
+static unsigned int dsi_dp3_mfp_pads[] = { DSI_DP3 };
+static unsigned int dsi_dp3_mfp_funcs[] = { S700_MUX_DSI,
+ S700_MUX_SD0,
+ S700_MUX_SD1,
+ S700_MUX_LCD0 };
+/* dsi_dn3 */
+static unsigned int dsi_dn3_mfp_pads[] = { DSI_DN3 };
+static unsigned int dsi_dn3_mfp_funcs[] = { S700_MUX_DSI,
+ S700_MUX_SD0,
+ S700_MUX_SD1,
+ S700_MUX_LCD0 };
+/* dsi_dp0 */
+static unsigned int dsi_dp0_mfp_pads[] = { DSI_DP0 };
+static unsigned int dsi_dp0_mfp_funcs[] = { S700_MUX_DSI,
+ S700_MUX_RESERVED,
+ S700_MUX_SD0,
+ S700_MUX_UART2,
+ S700_MUX_SPI0 };
+/* lvds_ee_pn */
+static unsigned int lvds_ee_pn_mfp_pads[] = { LVDS_EEP,
+ LVDS_EEN };
+static unsigned int lvds_ee_pn_mfp_funcs[] = { S700_MUX_LVDS,
+ S700_MUX_NOR,
+ S700_MUX_BT,
+ S700_MUX_LCD0 };
+/* uart2_rx_tx */
+static unsigned int uart2_rx_tx_mfp_pads[] = { UART2_RX,
+ UART2_TX };
+static unsigned int uart2_rx_tx_mfp_funcs[] = { S700_MUX_UART2,
+ S700_MUX_NOR,
+ S700_MUX_SPI0,
+ S700_MUX_PCM0 };
+/* spi0_i2c_pcm */
+static unsigned int spi0_i2c_pcm_mfp_pads[] = { SPI0_SS,
+ SPI0_MISO };
+static unsigned int spi0_i2c_pcm_mfp_funcs[] = { S700_MUX_SPI0,
+ S700_MUX_NOR,
+ S700_MUX_I2S1,
+ S700_MUX_PCM1,
+ S700_MUX_PCM0,
+ S700_MUX_I2C2 };
+/* mfp2_31 reserved */
+
+/* dsi_dnp1_cp_d2 */
+static unsigned int dsi_dnp1_cp_d2_mfp_pads[] = { DSI_DP1,
+ DSI_CP,
+ DSI_CN };
+static unsigned int dsi_dnp1_cp_d2_mfp_funcs[] = { S700_MUX_DSI,
+ S700_MUX_LCD0,
+ S700_MUX_RESERVED };
+/* dsi_dnp1_cp_d17 */
+static unsigned int dsi_dnp1_cp_d17_mfp_pads[] = { DSI_DP1,
+ DSI_CP,
+ DSI_CN };
+
+static unsigned int dsi_dnp1_cp_d17_mfp_funcs[] = { S700_MUX_DSI,
+ S700_MUX_RESERVED,
+ S700_MUX_LCD0 };
+/* lvds_e_pn */
+static unsigned int lvds_e_pn_mfp_pads[] = { LVDS_EDP,
+ LVDS_EDN,
+ LVDS_ECP,
+ LVDS_ECN,
+ LVDS_EBP,
+ LVDS_EBN,
+ LVDS_EAP,
+ LVDS_EAN };
+
+static unsigned int lvds_e_pn_mfp_funcs[] = { S700_MUX_LVDS,
+ S700_MUX_NOR,
+ S700_MUX_LCD0 };
+/* dsi_dn2 */
+static unsigned int dsi_dn2_mfp_pads[] = { DSI_DN2 };
+static unsigned int dsi_dn2_mfp_funcs[] = { S700_MUX_DSI,
+ S700_MUX_RESERVED,
+ S700_MUX_SD1,
+ S700_MUX_UART2,
+ S700_MUX_SPI0 };
+/* uart2_rtsb */
+static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB };
+static unsigned int uart2_rtsb_mfp_funcs[] = { S700_MUX_UART2,
+ S700_MUX_UART0 };
+
+/* uart2_ctsb */
+static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB };
+static unsigned int uart2_ctsb_mfp_funcs[] = { S700_MUX_UART2,
+ S700_MUX_UART0 };
+/* uart3_rtsb */
+static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB };
+static unsigned int uart3_rtsb_mfp_funcs[] = { S700_MUX_UART3,
+ S700_MUX_UART5 };
+
+/* uart3_ctsb */
+static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB };
+static unsigned int uart3_ctsb_mfp_funcs[] = { S700_MUX_UART3,
+ S700_MUX_UART5 };
+/* sd0_d0 */
+static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 };
+static unsigned int sd0_d0_mfp_funcs[] = { S700_MUX_SD0,
+ S700_MUX_NOR,
+ S700_MUX_RESERVED,
+ S700_MUX_JTAG,
+ S700_MUX_UART2,
+ S700_MUX_UART5 };
+/* sd0_d1 */
+static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 };
+static unsigned int sd0_d1_mfp_funcs[] = { S700_MUX_SD0,
+ S700_MUX_NOR,
+ S700_MUX_RESERVED,
+ S700_MUX_RESERVED,
+ S700_MUX_UART2,
+ S700_MUX_UART5 };
+/* sd0_d2_d3 */
+static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2,
+ SD0_D3 };
+static unsigned int sd0_d2_d3_mfp_funcs[] = { S700_MUX_SD0,
+ S700_MUX_NOR,
+ S700_MUX_RESERVED,
+ S700_MUX_JTAG,
+ S700_MUX_UART2,
+ S700_MUX_UART1 };
+
+/* sd1_d0_d3 */
+static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0,
+ SD1_D1,
+ SD1_D2,
+ SD1_D3 };
+static unsigned int sd1_d0_d3_mfp_funcs[] = { S700_MUX_SD0,
+ S700_MUX_NOR,
+ S700_MUX_RESERVED,
+ S700_MUX_SD1 };
+
+/* sd0_cmd */
+static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD };
+static unsigned int sd0_cmd_mfp_funcs[] = { S700_MUX_SD0,
+ S700_MUX_NOR,
+ S700_MUX_RESERVED,
+ S700_MUX_JTAG };
+/* sd0_clk */
+static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK };
+static unsigned int sd0_clk_mfp_funcs[] = { S700_MUX_SD0,
+ S700_MUX_RESERVED,
+ S700_MUX_JTAG };
+/* sd1_cmd */
+static unsigned int sd1_cmd_mfp_pads[] = { SD1_CMD };
+static unsigned int sd1_cmd_mfp_funcs[] = { S700_MUX_SD1,
+ S700_MUX_NOR };
+/* uart0_rx */
+static unsigned int uart0_rx_mfp_pads[] = { UART0_RX };
+static unsigned int uart0_rx_mfp_funcs[] = { S700_MUX_UART0,
+ S700_MUX_UART2,
+ S700_MUX_SPI1,
+ S700_MUX_I2C0,
+ S700_MUX_PCM1,
+ S700_MUX_I2S1 };
+/* dnand_data_wr1 reserved */
+
+/* clko_25m */
+static unsigned int clko_25m_mfp_pads[] = { CLKO_25M };
+static unsigned int clko_25m_mfp_funcs[] = { S700_MUX_RESERVED,
+ S700_MUX_CLKO_25M };
+/* csi_cn_cp */
+static unsigned int csi_cn_cp_mfp_pads[] = { CSI_CN,
+ CSI_CP };
+static unsigned int csi_cn_cp_mfp_funcs[] = { S700_MUX_MIPI_CSI,
+ S700_MUX_SENS0 };
+/* dnand_acle_ce07_24 reserved */
+
+/* sens0_ckout */
+static unsigned int sens0_ckout_mfp_pads[] = { SENSOR0_CKOUT };
+static unsigned int sens0_ckout_mfp_funcs[] = { S700_MUX_SENS0,
+ S700_MUX_NOR,
+ S700_MUX_SENS1,
+ S700_MUX_PWM1 };
+/* uart0_tx */
+static unsigned int uart0_tx_mfp_pads[] = { UART0_TX };
+static unsigned int uart0_tx_mfp_funcs[] = { S700_MUX_UART0,
+ S700_MUX_UART2,
+ S700_MUX_SPI1,
+ S700_MUX_I2C0,
+ S700_MUX_SPDIF,
+ S700_MUX_PCM1,
+ S700_MUX_I2S1 };
+/* i2c0_mfp */
+static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK,
+ I2C0_SDATA };
+static unsigned int i2c0_mfp_funcs[] = { S700_MUX_I2C0,
+ S700_MUX_UART2,
+ S700_MUX_I2C1,
+ S700_MUX_UART1,
+ S700_MUX_SPI1 };
+/* csi_dn_dp */
+static unsigned int csi_dn_dp_mfp_pads[] = { CSI_DN0,
+ CSI_DN1,
+ CSI_DN2,
+ CSI_DN3,
+ CSI_DP0,
+ CSI_DP1,
+ CSI_DP2,
+ CSI_DP3 };
+static unsigned int csi_dn_dp_mfp_funcs[] = { S700_MUX_MIPI_CSI,
+ S700_MUX_SENS0 };
+/* sen0_pclk */
+static unsigned int sen0_pclk_mfp_pads[] = { SENSOR0_PCLK };
+static unsigned int sen0_pclk_mfp_funcs[] = { S700_MUX_SENS0,
+ S700_MUX_NOR,
+ S700_MUX_PWM0 };
+/* pcm1_in */
+static unsigned int pcm1_in_mfp_pads[] = { PCM1_IN };
+static unsigned int pcm1_in_mfp_funcs[] = { S700_MUX_PCM1,
+ S700_MUX_SENS1,
+ S700_MUX_BT,
+ S700_MUX_PWM4 };
+/* pcm1_clk */
+static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK };
+static unsigned int pcm1_clk_mfp_funcs[] = { S700_MUX_PCM1,
+ S700_MUX_SENS1,
+ S700_MUX_BT,
+ S700_MUX_PWM5 };
+/* pcm1_sync */
+static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC };
+static unsigned int pcm1_sync_mfp_funcs[] = { S700_MUX_PCM1,
+ S700_MUX_SENS1,
+ S700_MUX_BT,
+ S700_MUX_I2C3 };
+/* pcm1_out */
+static unsigned int pcm1_out_mfp_pads[] = { PCM1_OUT };
+static unsigned int pcm1_out_mfp_funcs[] = { S700_MUX_PCM1,
+ S700_MUX_SENS1,
+ S700_MUX_BT,
+ S700_MUX_I2C3 };
+/* dnand_data_wr */
+static unsigned int dnand_data_wr_mfp_pads[] = { DNAND_D0,
+ DNAND_D1,
+ DNAND_D2,
+ DNAND_D3,
+ DNAND_D4,
+ DNAND_D5,
+ DNAND_D6,
+ DNAND_D7,
+ DNAND_RDB,
+ DNAND_RDBN };
+static unsigned int dnand_data_wr_mfp_funcs[] = { S700_MUX_NAND,
+ S700_MUX_SD2 };
+/* dnand_acle_ce0 */
+static unsigned int dnand_acle_ce0_mfp_pads[] = { DNAND_ALE,
+ DNAND_CLE,
+ DNAND_CEB0,
+ DNAND_CEB1 };
+static unsigned int dnand_acle_ce0_mfp_funcs[] = { S700_MUX_NAND,
+ S700_MUX_SPI2 };
+
+/* nand_ceb2 */
+static unsigned int nand_ceb2_mfp_pads[] = { DNAND_CEB2 };
+static unsigned int nand_ceb2_mfp_funcs[] = { S700_MUX_NAND,
+ S700_MUX_PWM5 };
+/* nand_ceb3 */
+static unsigned int nand_ceb3_mfp_pads[] = { DNAND_CEB3 };
+static unsigned int nand_ceb3_mfp_funcs[] = { S700_MUX_NAND,
+ S700_MUX_PWM4 };
+/*****End MFP group data****************************/
+
+/*****PADDRV group data****************************/
+
+/*PAD_DRV0*/
+static unsigned int sirq_drv_pads[] = { SIRQ0,
+ SIRQ1,
+ SIRQ2 };
+
+static unsigned int rgmii_txd23_drv_pads[] = { ETH_TXD2,
+ ETH_TXD3 };
+
+static unsigned int rgmii_rxd23_drv_pads[] = { ETH_RXD2,
+ ETH_RXD3 };
+
+static unsigned int rgmii_txd01_txen_drv_pads[] = { ETH_TXD0,
+ ETH_TXD1,
+ ETH_TXEN };
+
+static unsigned int rgmii_rxer_drv_pads[] = { ETH_RXER };
+
+static unsigned int rgmii_crs_drv_pads[] = { ETH_CRS_DV };
+
+static unsigned int rgmii_rxd10_drv_pads[] = { ETH_RXD0,
+ ETH_RXD1 };
+
+static unsigned int rgmii_ref_clk_drv_pads[] = { ETH_REF_CLK };
+
+static unsigned int smi_mdc_mdio_drv_pads[] = { ETH_MDC,
+ ETH_MDIO };
+
+static unsigned int i2s_d0_drv_pads[] = { I2S_D0 };
+
+static unsigned int i2s_bclk0_drv_pads[] = { I2S_BCLK0 };
+
+static unsigned int i2s3_drv_pads[] = { I2S_LRCLK0,
+ I2S_MCLK0,
+ I2S_D1 };
+
+static unsigned int i2s13_drv_pads[] = { I2S_BCLK1,
+ I2S_LRCLK1,
+ I2S_MCLK1 };
+
+static unsigned int pcm1_drv_pads[] = { PCM1_IN,
+ PCM1_CLK,
+ PCM1_SYNC,
+ PCM1_OUT };
+
+static unsigned int ks_in_drv_pads[] = { KS_IN0,
+ KS_IN1,
+ KS_IN2,
+ KS_IN3 };
+
+/*PAD_DRV1*/
+static unsigned int ks_out_drv_pads[] = { KS_OUT0,
+ KS_OUT1,
+ KS_OUT2 };
+
+static unsigned int lvds_all_drv_pads[] = { LVDS_OEP,
+ LVDS_OEN,
+ LVDS_ODP,
+ LVDS_ODN,
+ LVDS_OCP,
+ LVDS_OCN,
+ LVDS_OBP,
+ LVDS_OBN,
+ LVDS_OAP,
+ LVDS_OAN,
+ LVDS_EEP,
+ LVDS_EEN,
+ LVDS_EDP,
+ LVDS_EDN,
+ LVDS_ECP,
+ LVDS_ECN,
+ LVDS_EBP,
+ LVDS_EBN,
+ LVDS_EAP,
+ LVDS_EAN };
+
+static unsigned int lcd_d18_d2_drv_pads[] = { LCD0_D18,
+ LCD0_D2 };
+
+static unsigned int dsi_all_drv_pads[] = { DSI_DP0,
+ DSI_DN0,
+ DSI_DP2,
+ DSI_DN2,
+ DSI_DP3,
+ DSI_DN3,
+ DSI_DP1,
+ DSI_DN1,
+ DSI_CP,
+ DSI_CN };
+
+static unsigned int sd0_d0_d3_drv_pads[] = { SD0_D0,
+ SD0_D1,
+ SD0_D2,
+ SD0_D3 };
+
+static unsigned int sd0_cmd_drv_pads[] = { SD0_CMD };
+
+static unsigned int sd0_clk_drv_pads[] = { SD0_CLK };
+
+static unsigned int spi0_all_drv_pads[] = { SPI0_SS,
+ SPI0_MISO };
+
+/*PAD_DRV2*/
+static unsigned int uart0_rx_drv_pads[] = { UART0_RX };
+
+static unsigned int uart0_tx_drv_pads[] = { UART0_TX };
+
+static unsigned int uart2_all_drv_pads[] = { UART2_RX,
+ UART2_TX,
+ UART2_RTSB,
+ UART2_CTSB };
+
+static unsigned int i2c0_all_drv_pads[] = { I2C0_SCLK,
+ I2C0_SDATA };
+
+static unsigned int i2c12_all_drv_pads[] = { I2C1_SCLK,
+ I2C1_SDATA,
+ I2C2_SCLK,
+ I2C2_SDATA };
+
+static unsigned int sens0_pclk_drv_pads[] = { SENSOR0_PCLK };
+
+static unsigned int sens0_ckout_drv_pads[] = { SENSOR0_CKOUT };
+
+static unsigned int uart3_all_drv_pads[] = { UART3_RX,
+ UART3_TX,
+ UART3_RTSB,
+ UART3_CTSB };
+
+/* all pinctrl groups of S700 board */
+static const struct owl_pingroup s700_groups[] = {
+ MUX_PG(rgmii_txd23_mfp, 0, 28, 2),
+ MUX_PG(rgmii_rxd2_mfp, 0, 26, 2),
+ MUX_PG(rgmii_rxd3_mfp, 0, 26, 2),
+ MUX_PG(lcd0_d18_mfp, 0, 23, 3),
+ MUX_PG(rgmii_txd01_mfp, 0, 20, 3),
+ MUX_PG(rgmii_txd0_mfp, 0, 16, 3),
+ MUX_PG(rgmii_txd1_mfp, 0, 16, 3),
+ MUX_PG(rgmii_txen_mfp, 0, 13, 3),
+ MUX_PG(rgmii_rxen_mfp, 0, 13, 3),
+ MUX_PG(rgmii_rxd1_mfp, 0, 8, 3),
+ MUX_PG(rgmii_rxd0_mfp, 0, 8, 3),
+ MUX_PG(rgmii_ref_clk_mfp, 0, 6, 2),
+ MUX_PG(i2s_d0_mfp, 0, 5, 1),
+ MUX_PG(i2s_pcm1_mfp, 0, 3, 2),
+ MUX_PG(i2s0_pcm0_mfp, 0, 1, 2),
+ MUX_PG(i2s1_pcm0_mfp, 0, 1, 2),
+ MUX_PG(i2s_d1_mfp, 0, 0, 1),
+ MUX_PG(ks_in2_mfp, 1, 29, 3),
+ MUX_PG(ks_in1_mfp, 1, 29, 3),
+ MUX_PG(ks_in0_mfp, 1, 29, 3),
+ MUX_PG(ks_in3_mfp, 1, 26, 3),
+ MUX_PG(ks_out0_mfp, 1, 26, 3),
+ MUX_PG(ks_out1_mfp, 1, 26, 3),
+ MUX_PG(ks_out2_mfp, 1, 23, 3),
+ MUX_PG(lvds_o_pn_mfp, 1, 21, 2),
+ MUX_PG(dsi_dn0_mfp, 1, 19, 2),
+ MUX_PG(dsi_dp2_mfp, 1, 17, 2),
+ MUX_PG(lcd0_d2_mfp, 1, 14, 3),
+ MUX_PG(dsi_dp3_mfp, 1, 12, 2),
+ MUX_PG(dsi_dn3_mfp, 1, 10, 2),
+ MUX_PG(dsi_dp0_mfp, 1, 7, 3),
+ MUX_PG(lvds_ee_pn_mfp, 1, 5, 2),
+ MUX_PG(uart2_rx_tx_mfp, 1, 3, 2),
+ MUX_PG(spi0_i2c_pcm_mfp, 1, 0, 3),
+ MUX_PG(dsi_dnp1_cp_d2_mfp, 2, 29, 2),
+ MUX_PG(dsi_dnp1_cp_d17_mfp, 2, 29, 2),
+ MUX_PG(lvds_e_pn_mfp, 2, 27, 2),
+ MUX_PG(dsi_dn2_mfp, 2, 24, 3),
+ MUX_PG(uart2_rtsb_mfp, 2, 23, 1),
+ MUX_PG(uart2_ctsb_mfp, 2, 22, 1),
+ MUX_PG(uart3_rtsb_mfp, 2, 21, 1),
+ MUX_PG(uart3_ctsb_mfp, 2, 20, 1),
+ MUX_PG(sd0_d0_mfp, 2, 17, 3),
+ MUX_PG(sd0_d1_mfp, 2, 14, 3),
+ MUX_PG(sd0_d2_d3_mfp, 2, 11, 3),
+ MUX_PG(sd1_d0_d3_mfp, 2, 9, 2),
+ MUX_PG(sd0_cmd_mfp, 2, 7, 2),
+ MUX_PG(sd0_clk_mfp, 2, 5, 2),
+ MUX_PG(sd1_cmd_mfp, 2, 3, 2),
+ MUX_PG(uart0_rx_mfp, 2, 0, 3),
+ MUX_PG(clko_25m_mfp, 3, 30, 1),
+ MUX_PG(csi_cn_cp_mfp, 3, 28, 2),
+ MUX_PG(sens0_ckout_mfp, 3, 22, 2),
+ MUX_PG(uart0_tx_mfp, 3, 19, 3),
+ MUX_PG(i2c0_mfp, 3, 16, 3),
+ MUX_PG(csi_dn_dp_mfp, 3, 14, 2),
+ MUX_PG(sen0_pclk_mfp, 3, 12, 2),
+ MUX_PG(pcm1_in_mfp, 3, 10, 2),
+ MUX_PG(pcm1_clk_mfp, 3, 8, 2),
+ MUX_PG(pcm1_sync_mfp, 3, 6, 2),
+ MUX_PG(pcm1_out_mfp, 3, 4, 2),
+ MUX_PG(dnand_data_wr_mfp, 3, 3, 1),
+ MUX_PG(dnand_acle_ce0_mfp, 3, 2, 1),
+ MUX_PG(nand_ceb2_mfp, 3, 0, 2),
+ MUX_PG(nand_ceb3_mfp, 3, 0, 2),
+
+ DRV_PG(sirq_drv, 0, 28, 2),
+ DRV_PG(rgmii_txd23_drv, 0, 26, 2),
+ DRV_PG(rgmii_rxd23_drv, 0, 24, 2),
+ DRV_PG(rgmii_txd01_txen_drv, 0, 22, 2),
+ DRV_PG(rgmii_rxer_drv, 0, 20, 2),
+ DRV_PG(rgmii_crs_drv, 0, 18, 2),
+ DRV_PG(rgmii_rxd10_drv, 0, 16, 2),
+ DRV_PG(rgmii_ref_clk_drv, 0, 14, 2),
+ DRV_PG(smi_mdc_mdio_drv, 0, 12, 2),
+ DRV_PG(i2s_d0_drv, 0, 10, 2),
+ DRV_PG(i2s_bclk0_drv, 0, 8, 2),
+ DRV_PG(i2s3_drv, 0, 6, 2),
+ DRV_PG(i2s13_drv, 0, 4, 2),
+ DRV_PG(pcm1_drv, 0, 2, 2),
+ DRV_PG(ks_in_drv, 0, 0, 2),
+ DRV_PG(ks_out_drv, 1, 30, 2),
+ DRV_PG(lvds_all_drv, 1, 28, 2),
+ DRV_PG(lcd_d18_d2_drv, 1, 26, 2),
+ DRV_PG(dsi_all_drv, 1, 24, 2),
+ DRV_PG(sd0_d0_d3_drv, 1, 22, 2),
+ DRV_PG(sd0_cmd_drv, 1, 18, 2),
+ DRV_PG(sd0_clk_drv, 1, 16, 2),
+ DRV_PG(spi0_all_drv, 1, 10, 2),
+ DRV_PG(uart0_rx_drv, 2, 30, 2),
+ DRV_PG(uart0_tx_drv, 2, 28, 2),
+ DRV_PG(uart2_all_drv, 2, 26, 2),
+ DRV_PG(i2c0_all_drv, 2, 23, 2),
+ DRV_PG(i2c12_all_drv, 2, 21, 2),
+ DRV_PG(sens0_pclk_drv, 2, 18, 2),
+ DRV_PG(sens0_ckout_drv, 2, 12, 2),
+ DRV_PG(uart3_all_drv, 2, 2, 2),
+};
+
+static const char * const nor_groups[] = {
+ "lcd0_d18",
+ "i2s_d0",
+ "i2s0_pcm0",
+ "i2s1_pcm0",
+ "i2s_d1",
+ "ks_in2",
+ "ks_in1",
+ "ks_in0",
+ "ks_in3",
+ "ks_out0",
+ "ks_out1",
+ "ks_out2",
+ "lcd0_d2",
+ "lvds_ee_pn",
+ "uart2_rx_tx",
+ "spi0_i2c_pcm",
+ "lvds_e_pn",
+ "sd0_d0",
+ "sd0_d1",
+ "sd0_d2_d3",
+ "sd1_d0_d3",
+ "sd0_cmd",
+ "sd1_cmd",
+ "sens0_ckout",
+ "sen0_pclk",
+};
+
+static const char * const eth_rmii_groups[] = {
+ "rgmii_txd23",
+ "rgmii_rxd2",
+ "rgmii_rxd3",
+ "rgmii_txd01",
+ "rgmii_txd0",
+ "rgmii_txd1",
+ "rgmii_txen",
+ "rgmii_rxen",
+ "rgmii_rxd1",
+ "rgmii_rxd0",
+ "rgmii_ref_clk",
+ "eth_smi_dummy",
+};
+
+static const char * const eth_smii_groups[] = {
+ "rgmii_txd0",
+ "rgmii_txd1",
+ "rgmii_rxd0",
+ "rgmii_rxd1",
+ "rgmii_ref_clk",
+ "eth_smi_dummy",
+};
+
+static const char * const spi0_groups[] = {
+ "dsi_dn0",
+ "dsi_dp2",
+ "dsi_dp0",
+ "uart2_rx_tx",
+ "spi0_i2c_pcm",
+ "dsi_dn2",
+};
+
+static const char * const spi1_groups[] = {
+ "uart0_rx",
+ "uart0_tx",
+ "i2c0_mfp",
+};
+
+static const char * const spi2_groups[] = {
+ "rgmii_txd01",
+ "rgmii_txd0",
+ "rgmii_txd1",
+ "rgmii_ref_clk",
+ "dnand_acle_ce0",
+};
+
+static const char * const spi3_groups[] = {
+ "rgmii_txen",
+ "rgmii_rxen",
+ "rgmii_rxd1",
+ "rgmii_rxd0",
+};
+
+static const char * const sens0_groups[] = {
+ "csi_cn_cp",
+ "sens0_ckout",
+ "csi_dn_dp",
+ "sen0_pclk",
+};
+
+static const char * const sens1_groups[] = {
+ "lcd0_d18",
+ "ks_in2",
+ "ks_in1",
+ "ks_in0",
+ "ks_in3",
+ "ks_out0",
+ "ks_out1",
+ "ks_out2",
+ "sens0_ckout",
+ "pcm1_in",
+ "pcm1_clk",
+ "pcm1_sync",
+ "pcm1_out",
+};
+
+static const char * const uart0_groups[] = {
+ "uart2_rtsb",
+ "uart2_ctsb",
+ "uart0_rx",
+ "uart0_tx",
+};
+
+static const char * const uart1_groups[] = {
+ "sd0_d2_d3",
+ "i2c0_mfp",
+};
+
+static const char * const uart2_groups[] = {
+ "rgmii_txen",
+ "rgmii_rxen",
+ "rgmii_rxd1",
+ "rgmii_rxd0",
+ "dsi_dn0",
+ "dsi_dp2",
+ "dsi_dp0",
+ "uart2_rx_tx",
+ "dsi_dn2",
+ "uart2_rtsb",
+ "uart2_ctsb",
+ "sd0_d0",
+ "sd0_d1",
+ "sd0_d2_d3",
+ "uart0_rx",
+ "uart0_tx",
+ "i2c0_mfp",
+ "uart2_dummy"
+};
+
+static const char * const uart3_groups[] = {
+ "rgmii_txd23",
+ "rgmii_rxd2",
+ "rgmii_rxd3",
+ "uart3_rtsb",
+ "uart3_ctsb",
+ "uart3_dummy"
+};
+
+static const char * const uart4_groups[] = {
+ "rgmii_txd01",
+ "rgmii_ref_clk",
+ "ks_out0",
+ "ks_out1",
+};
+
+static const char * const uart5_groups[] = {
+ "rgmii_rxd1",
+ "rgmii_rxd0",
+ "ks_out0",
+ "ks_out2",
+ "uart3_rtsb",
+ "uart3_ctsb",
+ "sd0_d0",
+ "sd0_d1",
+};
+
+static const char * const uart6_groups[] = {
+ "rgmii_txd0",
+ "rgmii_txd1",
+};
+
+static const char * const i2s0_groups[] = {
+ "i2s_d0",
+ "i2s_pcm1",
+ "i2s0_pcm0",
+};
+
+static const char * const i2s1_groups[] = {
+ "i2s1_pcm0",
+ "i2s_d1",
+ "i2s1_dummy",
+ "spi0_i2c_pcm",
+ "uart0_rx",
+ "uart0_tx",
+};
+
+static const char * const pcm1_groups[] = {
+ "i2s_pcm1",
+ "spi0_i2c_pcm",
+ "uart0_rx",
+ "uart0_tx",
+ "pcm1_in",
+ "pcm1_clk",
+ "pcm1_sync",
+ "pcm1_out",
+};
+
+static const char * const pcm0_groups[] = {
+ "i2s0_pcm0",
+ "i2s1_pcm0",
+ "uart2_rx_tx",
+ "spi0_i2c_pcm",
+};
+
+static const char * const ks_groups[] = {
+ "ks_in2",
+ "ks_in1",
+ "ks_in0",
+ "ks_in3",
+ "ks_out0",
+ "ks_out1",
+ "ks_out2",
+};
+
+static const char * const jtag_groups[] = {
+ "ks_in2",
+ "ks_in1",
+ "ks_in0",
+ "ks_in3",
+ "ks_out1",
+ "sd0_d0",
+ "sd0_d2_d3",
+ "sd0_cmd",
+ "sd0_clk",
+};
+
+static const char * const pwm0_groups[] = {
+ "rgmii_rxd2",
+ "rgmii_txen",
+ "ks_in2",
+ "sen0_pclk",
+};
+
+static const char * const pwm1_groups[] = {
+ "rgmii_rxen",
+ "ks_in1",
+ "ks_in3",
+ "sens0_ckout",
+};
+
+static const char * const pwm2_groups[] = {
+ "lcd0_d18",
+ "rgmii_rxd3",
+ "rgmii_rxd1",
+ "ks_out0",
+ "ks_out2",
+};
+
+static const char * const pwm3_groups[] = {
+ "rgmii_rxd0",
+ "ks_out1",
+ "lcd0_d2",
+};
+
+static const char * const pwm4_groups[] = {
+ "lcd0_d18",
+ "rgmii_txd01",
+ "rgmii_txd0",
+ "ks_in0",
+ "pcm1_in",
+ "nand_ceb3",
+};
+
+static const char * const pwm5_groups[] = {
+ "rgmii_txd1",
+ "ks_in1",
+ "pcm1_clk",
+ "nand_ceb2",
+};
+
+static const char * const p0_groups[] = {
+ "ks_in2",
+ "ks_in0",
+};
+
+static const char * const sd0_groups[] = {
+ "ks_out0",
+ "ks_out1",
+ "ks_out2",
+ "lcd0_d2",
+ "dsi_dp3",
+ "dsi_dp0",
+ "sd0_d0",
+ "sd0_d1",
+ "sd0_d2_d3",
+ "sd1_d0_d3",
+ "sd0_cmd",
+ "sd0_clk",
+};
+
+static const char * const sd1_groups[] = {
+ "dsi_dp2",
+ "mfp1_16_14",
+ "lcd0_d2",
+ "mfp1_16_14_d17",
+ "dsi_dp3",
+ "dsi_dn3",
+ "dsi_dnp1_cp_d2",
+ "dsi_dnp1_cp_d17",
+ "dsi_dn2",
+ "sd1_d0_d3",
+ "sd1_cmd",
+ "sd1_dummy",
+};
+
+static const char * const sd2_groups[] = {
+ "dnand_data_wr",
+};
+
+static const char * const i2c0_groups[] = {
+ "uart0_rx",
+ "uart0_tx",
+ "i2c0_mfp",
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c0_mfp",
+ "i2c1_dummy"
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2_dummy"
+};
+
+static const char * const i2c3_groups[] = {
+ "uart2_rx_tx",
+ "pcm1_sync",
+ "pcm1_out",
+};
+
+static const char * const lvds_groups[] = {
+ "lvds_o_pn",
+ "lvds_ee_pn",
+ "lvds_e_pn",
+};
+
+static const char * const bt_groups[] = {
+ "i2s_pcm1",
+ "i2s0_pcm0",
+ "i2s1_pcm0",
+ "ks_in2",
+ "ks_in1",
+ "ks_in0",
+ "ks_in3",
+ "ks_out0",
+ "ks_out1",
+ "ks_out2",
+ "lvds_o_pn",
+ "lvds_ee_pn",
+ "pcm1_in",
+ "pcm1_clk",
+ "pcm1_sync",
+ "pcm1_out",
+};
+
+static const char * const lcd0_groups[] = {
+ "lcd0_d18",
+ "lcd0_d2",
+ "mfp1_16_14_d17",
+ "lvds_o_pn",
+ "dsi_dp3",
+ "dsi_dn3",
+ "lvds_ee_pn",
+ "dsi_dnp1_cp_d2",
+ "dsi_dnp1_cp_d17",
+ "lvds_e_pn",
+};
+
+
+static const char * const usb30_groups[] = {
+ "ks_in1",
+};
+
+static const char * const clko_25m_groups[] = {
+ "clko_25m",
+};
+
+static const char * const mipi_csi_groups[] = {
+ "csi_cn_cp",
+ "csi_dn_dp",
+};
+
+static const char * const dsi_groups[] = {
+ "dsi_dn0",
+ "dsi_dp2",
+ "dsi_dp3",
+ "dsi_dn3",
+ "dsi_dp0",
+ "dsi_dnp1_cp_d2",
+ "dsi_dnp1_cp_d17",
+ "dsi_dn2",
+ "dsi_dummy",
+};
+
+static const char * const nand_groups[] = {
+ "dnand_data_wr",
+ "dnand_acle_ce0",
+ "nand_ceb2",
+ "nand_ceb3",
+ "nand_dummy",
+};
+
+static const char * const spdif_groups[] = {
+ "uart0_tx",
+};
+
+static const char * const sirq0_groups[] = {
+ "sirq0_dummy",
+};
+
+static const char * const sirq1_groups[] = {
+ "sirq1_dummy",
+};
+
+static const char * const sirq2_groups[] = {
+ "sirq2_dummy",
+};
+
+static const struct owl_pinmux_func s700_functions[] = {
+ [S700_MUX_NOR] = FUNCTION(nor),
+ [S700_MUX_ETH_RGMII] = FUNCTION(eth_rmii),
+ [S700_MUX_ETH_SGMII] = FUNCTION(eth_smii),
+ [S700_MUX_SPI0] = FUNCTION(spi0),
+ [S700_MUX_SPI1] = FUNCTION(spi1),
+ [S700_MUX_SPI2] = FUNCTION(spi2),
+ [S700_MUX_SPI3] = FUNCTION(spi3),
+ [S700_MUX_SENS0] = FUNCTION(sens0),
+ [S700_MUX_SENS1] = FUNCTION(sens1),
+ [S700_MUX_UART0] = FUNCTION(uart0),
+ [S700_MUX_UART1] = FUNCTION(uart1),
+ [S700_MUX_UART2] = FUNCTION(uart2),
+ [S700_MUX_UART3] = FUNCTION(uart3),
+ [S700_MUX_UART4] = FUNCTION(uart4),
+ [S700_MUX_UART5] = FUNCTION(uart5),
+ [S700_MUX_UART6] = FUNCTION(uart6),
+ [S700_MUX_I2S0] = FUNCTION(i2s0),
+ [S700_MUX_I2S1] = FUNCTION(i2s1),
+ [S700_MUX_PCM1] = FUNCTION(pcm1),
+ [S700_MUX_PCM0] = FUNCTION(pcm0),
+ [S700_MUX_KS] = FUNCTION(ks),
+ [S700_MUX_JTAG] = FUNCTION(jtag),
+ [S700_MUX_PWM0] = FUNCTION(pwm0),
+ [S700_MUX_PWM1] = FUNCTION(pwm1),
+ [S700_MUX_PWM2] = FUNCTION(pwm2),
+ [S700_MUX_PWM3] = FUNCTION(pwm3),
+ [S700_MUX_PWM4] = FUNCTION(pwm4),
+ [S700_MUX_PWM5] = FUNCTION(pwm5),
+ [S700_MUX_P0] = FUNCTION(p0),
+ [S700_MUX_SD0] = FUNCTION(sd0),
+ [S700_MUX_SD1] = FUNCTION(sd1),
+ [S700_MUX_SD2] = FUNCTION(sd2),
+ [S700_MUX_I2C0] = FUNCTION(i2c0),
+ [S700_MUX_I2C1] = FUNCTION(i2c1),
+ [S700_MUX_I2C2] = FUNCTION(i2c2),
+ [S700_MUX_I2C3] = FUNCTION(i2c3),
+ [S700_MUX_DSI] = FUNCTION(dsi),
+ [S700_MUX_LVDS] = FUNCTION(lvds),
+ [S700_MUX_USB30] = FUNCTION(usb30),
+ [S700_MUX_CLKO_25M] = FUNCTION(clko_25m),
+ [S700_MUX_MIPI_CSI] = FUNCTION(mipi_csi),
+ [S700_MUX_DSI] = FUNCTION(dsi),
+ [S700_MUX_NAND] = FUNCTION(nand),
+ [S700_MUX_SPDIF] = FUNCTION(spdif),
+ [S700_MUX_SIRQ0] = FUNCTION(sirq0),
+ [S700_MUX_SIRQ1] = FUNCTION(sirq1),
+ [S700_MUX_SIRQ2] = FUNCTION(sirq2),
+ [S700_MUX_BT] = FUNCTION(bt),
+ [S700_MUX_LCD0] = FUNCTION(lcd0),
+};
+
+/* PAD_ST0 */
+static PAD_ST_CONF(UART2_TX, 0, 31, 1);
+static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1);
+static PAD_ST_CONF(UART0_RX, 0, 29, 1);
+static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1);
+static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1);
+static PAD_ST_CONF(ETH_TXEN, 0, 21, 1);
+static PAD_ST_CONF(ETH_TXD0, 0, 20, 1);
+static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1);
+static PAD_ST_CONF(DSI_DP0, 0, 16, 1);
+static PAD_ST_CONF(DSI_DN0, 0, 15, 1);
+static PAD_ST_CONF(UART0_TX, 0, 14, 1);
+static PAD_ST_CONF(SD0_CLK, 0, 12, 1);
+static PAD_ST_CONF(KS_IN0, 0, 11, 1);
+static PAD_ST_CONF(SENSOR0_PCLK, 0, 9, 1);
+static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1);
+static PAD_ST_CONF(KS_OUT0, 0, 6, 1);
+static PAD_ST_CONF(KS_OUT1, 0, 5, 1);
+static PAD_ST_CONF(KS_OUT2, 0, 4, 1);
+static PAD_ST_CONF(ETH_TXD3, 0, 3, 1);
+static PAD_ST_CONF(ETH_TXD2, 0, 2, 1);
+
+/* PAD_ST1 */
+static PAD_ST_CONF(DSI_DP2, 1, 31, 1);
+static PAD_ST_CONF(DSI_DN2, 1, 30, 1);
+static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1);
+static PAD_ST_CONF(UART3_CTSB, 1, 27, 1);
+static PAD_ST_CONF(UART3_RTSB, 1, 26, 1);
+static PAD_ST_CONF(UART3_RX, 1, 25, 1);
+static PAD_ST_CONF(UART2_RTSB, 1, 24, 1);
+static PAD_ST_CONF(UART2_CTSB, 1, 23, 1);
+static PAD_ST_CONF(UART2_RX, 1, 22, 1);
+static PAD_ST_CONF(ETH_RXD0, 1, 21, 1);
+static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);
+static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1);
+static PAD_ST_CONF(ETH_RXER, 1, 18, 1);
+static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);
+static PAD_ST_CONF(LVDS_OAP, 1, 12, 1);
+static PAD_ST_CONF(PCM1_CLK, 1, 11, 1);
+static PAD_ST_CONF(PCM1_IN, 1, 10, 1);
+static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1);
+static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1);
+static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1);
+static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1);
+static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1);
+
+static PAD_ST_CONF(SPI0_MISO, 1, 3, 1);
+static PAD_ST_CONF(SPI0_SS, 1, 2, 1);
+static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
+static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
+
+/* PAD_PULLCTL0 */
+static PAD_PULLCTL_CONF(PCM1_SYNC, 0, 30, 1);
+static PAD_PULLCTL_CONF(PCM1_OUT, 0, 29, 1);
+static PAD_PULLCTL_CONF(KS_OUT2, 0, 28, 1);
+static PAD_PULLCTL_CONF(LCD0_D2, 0, 27, 1);
+static PAD_PULLCTL_CONF(DSI_DN3, 0, 26, 1);
+static PAD_PULLCTL_CONF(ETH_RXER, 0, 16, 1);
+static PAD_PULLCTL_CONF(SIRQ0, 0, 14, 2);
+static PAD_PULLCTL_CONF(SIRQ1, 0, 12, 2);
+static PAD_PULLCTL_CONF(SIRQ2, 0, 10, 2);
+static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 9, 1);
+static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 1);
+static PAD_PULLCTL_CONF(KS_IN0, 0, 7, 1);
+static PAD_PULLCTL_CONF(KS_IN1, 0, 6, 1);
+static PAD_PULLCTL_CONF(KS_IN2, 0, 5, 1);
+static PAD_PULLCTL_CONF(KS_IN3, 0, 4, 1);
+static PAD_PULLCTL_CONF(KS_OUT0, 0, 2, 1);
+static PAD_PULLCTL_CONF(KS_OUT1, 0, 1, 1);
+static PAD_PULLCTL_CONF(DSI_DP1, 0, 0, 1);
+
+/* PAD_PULLCTL1 */
+static PAD_PULLCTL_CONF(SD0_D0, 1, 17, 1);
+static PAD_PULLCTL_CONF(SD0_D1, 1, 16, 1);
+static PAD_PULLCTL_CONF(SD0_D2, 1, 15, 1);
+static PAD_PULLCTL_CONF(SD0_D3, 1, 14, 1);
+static PAD_PULLCTL_CONF(SD0_CMD, 1, 13, 1);
+static PAD_PULLCTL_CONF(SD0_CLK, 1, 12, 1);
+static PAD_PULLCTL_CONF(UART0_RX, 1, 2, 1);
+static PAD_PULLCTL_CONF(UART0_TX, 1, 1, 1);
+static PAD_PULLCTL_CONF(CLKO_25M, 1, 0, 1);
+
+/* PAD_PULLCTL2 */
+static PAD_PULLCTL_CONF(ETH_TXD2, 2, 18, 1);
+static PAD_PULLCTL_CONF(ETH_TXD3, 2, 17, 1);
+static PAD_PULLCTL_CONF(SPI0_SS, 2, 16, 1);
+static PAD_PULLCTL_CONF(SPI0_MISO, 2, 15, 1);
+static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 10, 1);
+static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 9, 1);
+static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1);
+static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1);
+
+/* Pad info table for the pinmux subsystem */
+static struct owl_padinfo s700_padinfo[NUM_PADS] = {
+ [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
+ [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
+ [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),
+ [ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER),
+ [ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV),
+ [ETH_RXD1] = PAD_INFO_ST(ETH_RXD1),
+ [ETH_RXD0] = PAD_INFO_ST(ETH_RXD0),
+ [ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK),
+ [ETH_MDC] = PAD_INFO(ETH_MDC),
+ [ETH_MDIO] = PAD_INFO(ETH_MDIO),
+ [SIRQ0] = PAD_INFO_PULLCTL(SIRQ0),
+ [SIRQ1] = PAD_INFO_PULLCTL(SIRQ1),
+ [SIRQ2] = PAD_INFO_PULLCTL(SIRQ2),
+ [I2S_D0] = PAD_INFO(I2S_D0),
+ [I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0),
+ [I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0),
+ [I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0),
+ [I2S_D1] = PAD_INFO(I2S_D1),
+ [I2S_BCLK1] = PAD_INFO(I2S_BCLK1),
+ [I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1),
+ [I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1),
+ [KS_IN0] = PAD_INFO_PULLCTL_ST(KS_IN0),
+ [KS_IN1] = PAD_INFO_PULLCTL(KS_IN1),
+ [KS_IN2] = PAD_INFO_PULLCTL(KS_IN2),
+ [KS_IN3] = PAD_INFO_PULLCTL(KS_IN3),
+ [KS_OUT0] = PAD_INFO_PULLCTL_ST(KS_OUT0),
+ [KS_OUT1] = PAD_INFO_PULLCTL_ST(KS_OUT1),
+ [KS_OUT2] = PAD_INFO_PULLCTL_ST(KS_OUT2),
+ [LVDS_OEP] = PAD_INFO(LVDS_OEP),
+ [LVDS_OEN] = PAD_INFO(LVDS_OEN),
+ [LVDS_ODP] = PAD_INFO(LVDS_ODP),
+ [LVDS_ODN] = PAD_INFO(LVDS_ODN),
+ [LVDS_OCP] = PAD_INFO(LVDS_OCP),
+ [LVDS_OCN] = PAD_INFO(LVDS_OCN),
+ [LVDS_OBP] = PAD_INFO(LVDS_OBP),
+ [LVDS_OBN] = PAD_INFO(LVDS_OBN),
+ [LVDS_OAP] = PAD_INFO_ST(LVDS_OAP),
+ [LVDS_OAN] = PAD_INFO(LVDS_OAN),
+ [LVDS_EEP] = PAD_INFO(LVDS_EEP),
+ [LVDS_EEN] = PAD_INFO(LVDS_EEN),
+ [LVDS_EDP] = PAD_INFO(LVDS_EDP),
+ [LVDS_EDN] = PAD_INFO(LVDS_EDN),
+ [LVDS_ECP] = PAD_INFO(LVDS_ECP),
+ [LVDS_ECN] = PAD_INFO(LVDS_ECN),
+ [LVDS_EBP] = PAD_INFO(LVDS_EBP),
+ [LVDS_EBN] = PAD_INFO(LVDS_EBN),
+ [LVDS_EAP] = PAD_INFO(LVDS_EAP),
+ [LVDS_EAN] = PAD_INFO(LVDS_EAN),
+ [LCD0_D18] = PAD_INFO(LCD0_D18),
+ [LCD0_D2] = PAD_INFO_PULLCTL(LCD0_D2),
+ [DSI_DP3] = PAD_INFO(DSI_DP3),
+ [DSI_DN3] = PAD_INFO_PULLCTL(DSI_DN3),
+ [DSI_DP1] = PAD_INFO_PULLCTL(DSI_DP1),
+ [DSI_DN1] = PAD_INFO(DSI_DN1),
+ [DSI_DP0] = PAD_INFO_ST(DSI_DP0),
+ [DSI_DN0] = PAD_INFO_ST(DSI_DN0),
+ [DSI_DP2] = PAD_INFO_ST(DSI_DP2),
+ [DSI_DN2] = PAD_INFO_ST(DSI_DN2),
+ [SD0_D0] = PAD_INFO_PULLCTL(SD0_D0),
+ [SD0_D1] = PAD_INFO_PULLCTL(SD0_D1),
+ [SD0_D2] = PAD_INFO_PULLCTL(SD0_D2),
+ [SD0_D3] = PAD_INFO_PULLCTL(SD0_D3),
+ [SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD),
+ [SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK),
+ [SD1_CLK] = PAD_INFO(SD1_CLK),
+ [SPI0_SS] = PAD_INFO_PULLCTL_ST(SPI0_SS),
+ [SPI0_MISO] = PAD_INFO_PULLCTL_ST(SPI0_MISO),
+ [UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX),
+ [UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX),
+ [I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK),
+ [I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA),
+ [SENSOR0_PCLK] = PAD_INFO_ST(SENSOR0_PCLK),
+ [SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT),
+ [DNAND_ALE] = PAD_INFO(DNAND_ALE),
+ [DNAND_CLE] = PAD_INFO(DNAND_CLE),
+ [DNAND_CEB0] = PAD_INFO(DNAND_CEB0),
+ [DNAND_CEB1] = PAD_INFO(DNAND_CEB1),
+ [DNAND_CEB2] = PAD_INFO(DNAND_CEB2),
+ [DNAND_CEB3] = PAD_INFO(DNAND_CEB3),
+ [UART2_RX] = PAD_INFO_ST(UART2_RX),
+ [UART2_TX] = PAD_INFO_ST(UART2_TX),
+ [UART2_RTSB] = PAD_INFO_ST(UART2_RTSB),
+ [UART2_CTSB] = PAD_INFO_ST(UART2_CTSB),
+ [UART3_RX] = PAD_INFO_ST(UART3_RX),
+ [UART3_TX] = PAD_INFO(UART3_TX),
+ [UART3_RTSB] = PAD_INFO_ST(UART3_RTSB),
+ [UART3_CTSB] = PAD_INFO_ST(UART3_CTSB),
+ [PCM1_IN] = PAD_INFO_ST(PCM1_IN),
+ [PCM1_CLK] = PAD_INFO_ST(PCM1_CLK),
+ [PCM1_SYNC] = PAD_INFO_PULLCTL_ST(PCM1_SYNC),
+ [PCM1_OUT] = PAD_INFO_PULLCTL(PCM1_OUT),
+ [I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK),
+ [I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA),
+ [I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK),
+ [I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA),
+ [CSI_DN0] = PAD_INFO(CSI_DN0),
+ [CSI_DP0] = PAD_INFO(CSI_DP0),
+ [CSI_DN1] = PAD_INFO(CSI_DN1),
+ [CSI_DP1] = PAD_INFO(CSI_DP1),
+ [CSI_CN] = PAD_INFO(CSI_CN),
+ [CSI_CP] = PAD_INFO(CSI_CP),
+ [CSI_DN2] = PAD_INFO(CSI_DN2),
+ [CSI_DP2] = PAD_INFO(CSI_DP2),
+ [CSI_DN3] = PAD_INFO(CSI_DN3),
+ [CSI_DP3] = PAD_INFO(CSI_DP3),
+ [DNAND_WRB] = PAD_INFO(DNAND_WRB),
+ [DNAND_RDB] = PAD_INFO(DNAND_RDB),
+ [DNAND_RB0] = PAD_INFO(DNAND_RB0),
+ [PORB] = PAD_INFO(PORB),
+ [CLKO_25M] = PAD_INFO_PULLCTL(CLKO_25M),
+ [BSEL] = PAD_INFO(BSEL),
+ [PKG0] = PAD_INFO(PKG0),
+ [PKG1] = PAD_INFO(PKG1),
+ [PKG2] = PAD_INFO(PKG2),
+ [PKG3] = PAD_INFO(PKG3),
+ [ETH_TXD2] = PAD_INFO_PULLCTL_ST(ETH_TXD2),
+ [ETH_TXD3] = PAD_INFO_PULLCTL_ST(ETH_TXD3),
+};
+
+static const struct owl_gpio_port s700_gpio_ports[] = {
+ OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x230, 0),
+ OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x204, 0x210, 0x214, 0x238, 1),
+ OWL_GPIO_PORT(C, 0x0018, 32, 0x0, 0x4, 0x8, 0x204, 0x218, 0x21C, 0x240, 2),
+ OWL_GPIO_PORT(D, 0x0024, 32, 0x0, 0x4, 0x8, 0x204, 0x220, 0x224, 0x248, 3),
+ /* 0x24C (INTC_GPIOD_TYPE1) used to tweak the driver to handle generic */
+ OWL_GPIO_PORT(E, 0x0030, 8, 0x0, 0x4, 0x8, 0x204, 0x228, 0x22C, 0x24C, 4),
+};
+
+enum s700_pinconf_pull {
+ OWL_PINCONF_PULL_DOWN,
+ OWL_PINCONF_PULL_UP,
+};
+
+static int s700_pad_pinconf_arg2val(const struct owl_padinfo *info,
+ unsigned int param,
+ u32 *arg)
+{
+ switch (param) {
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ *arg = OWL_PINCONF_PULL_DOWN;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ *arg = OWL_PINCONF_PULL_UP;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ *arg = (*arg >= 1 ? 1 : 0);
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ return 0;
+}
+
+static int s700_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
+ unsigned int param,
+ u32 *arg)
+{
+ switch (param) {
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ *arg = *arg == OWL_PINCONF_PULL_DOWN;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ *arg = *arg == OWL_PINCONF_PULL_UP;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ *arg = *arg == 1;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ return 0;
+}
+
+static struct owl_pinctrl_soc_data s700_pinctrl_data = {
+ .padinfo = s700_padinfo,
+ .pins = (const struct pinctrl_pin_desc *)s700_pads,
+ .npins = ARRAY_SIZE(s700_pads),
+ .functions = s700_functions,
+ .nfunctions = ARRAY_SIZE(s700_functions),
+ .groups = s700_groups,
+ .ngroups = ARRAY_SIZE(s700_groups),
+ .ngpios = NUM_GPIOS,
+ .ports = s700_gpio_ports,
+ .nports = ARRAY_SIZE(s700_gpio_ports),
+ .padctl_arg2val = s700_pad_pinconf_arg2val,
+ .padctl_val2arg = s700_pad_pinconf_val2arg,
+};
+
+static int s700_pinctrl_probe(struct platform_device *pdev)
+{
+ return owl_pinctrl_probe(pdev, &s700_pinctrl_data);
+}
+
+static const struct of_device_id s700_pinctrl_of_match[] = {
+ { .compatible = "actions,s700-pinctrl", },
+ {}
+};
+
+static struct platform_driver s700_pinctrl_driver = {
+ .probe = s700_pinctrl_probe,
+ .driver = {
+ .name = "pinctrl-s700",
+ .of_match_table = of_match_ptr(s700_pinctrl_of_match),
+ },
+};
+
+static int __init s700_pinctrl_init(void)
+{
+ return platform_driver_register(&s700_pinctrl_driver);
+}
+arch_initcall(s700_pinctrl_init);
+
+static void __exit s700_pinctrl_exit(void)
+{
+ platform_driver_unregister(&s700_pinctrl_driver);
+}
+module_exit(s700_pinctrl_exit);
+
+MODULE_AUTHOR("Actions Semi Inc.");
+MODULE_DESCRIPTION("Actions Semi S700 Soc Pinctrl Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/actions/pinctrl-s900.c b/drivers/pinctrl/actions/pinctrl-s900.c
index ea67b14..9492b86 100644
--- a/drivers/pinctrl/actions/pinctrl-s900.c
+++ b/drivers/pinctrl/actions/pinctrl-s900.c
@@ -13,6 +13,7 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
#include "pinctrl-owl.h"
/* Pinctrl registers offset */
@@ -33,13 +34,6 @@
#define PAD_SR1 (0x0274)
#define PAD_SR2 (0x0278)
-#define OWL_GPIO_PORT_A 0
-#define OWL_GPIO_PORT_B 1
-#define OWL_GPIO_PORT_C 2
-#define OWL_GPIO_PORT_D 3
-#define OWL_GPIO_PORT_E 4
-#define OWL_GPIO_PORT_F 5
-
#define _GPIOA(offset) (offset)
#define _GPIOB(offset) (32 + (offset))
#define _GPIOC(offset) (64 + (offset))
@@ -892,55 +886,6 @@ static unsigned int i2c2_sr_pads[] = { I2C2_SCLK, I2C2_SDATA };
static unsigned int sensor0_sr_pads[] = { SENSOR0_PCLK,
SENSOR0_CKOUT };
-#define MUX_PG(group_name, reg, shift, width) \
- { \
- .name = #group_name, \
- .pads = group_name##_pads, \
- .npads = ARRAY_SIZE(group_name##_pads), \
- .funcs = group_name##_funcs, \
- .nfuncs = ARRAY_SIZE(group_name##_funcs), \
- .mfpctl_reg = MFCTL##reg, \
- .mfpctl_shift = shift, \
- .mfpctl_width = width, \
- .drv_reg = -1, \
- .drv_shift = -1, \
- .drv_width = -1, \
- .sr_reg = -1, \
- .sr_shift = -1, \
- .sr_width = -1, \
- }
-
-#define DRV_PG(group_name, reg, shift, width) \
- { \
- .name = #group_name, \
- .pads = group_name##_pads, \
- .npads = ARRAY_SIZE(group_name##_pads), \
- .mfpctl_reg = -1, \
- .mfpctl_shift = -1, \
- .mfpctl_width = -1, \
- .drv_reg = PAD_DRV##reg, \
- .drv_shift = shift, \
- .drv_width = width, \
- .sr_reg = -1, \
- .sr_shift = -1, \
- .sr_width = -1, \
- }
-
-#define SR_PG(group_name, reg, shift, width) \
- { \
- .name = #group_name, \
- .pads = group_name##_pads, \
- .npads = ARRAY_SIZE(group_name##_pads), \
- .mfpctl_reg = -1, \
- .mfpctl_shift = -1, \
- .mfpctl_width = -1, \
- .drv_reg = -1, \
- .drv_shift = -1, \
- .drv_width = -1, \
- .sr_reg = PAD_SR##reg, \
- .sr_shift = shift, \
- .sr_width = width, \
- }
/* Pinctrl groups */
static const struct owl_pingroup s900_groups[] = {
@@ -1442,13 +1387,6 @@ static const char * const sirq2_groups[] = {
"sirq2_dummy",
};
-#define FUNCTION(fname) \
- { \
- .name = #fname, \
- .groups = fname##_groups, \
- .ngroups = ARRAY_SIZE(fname##_groups), \
- }
-
static const struct owl_pinmux_func s900_functions[] = {
[S900_MUX_ERAM] = FUNCTION(eram),
[S900_MUX_ETH_RMII] = FUNCTION(eth_rmii),
@@ -1500,28 +1438,6 @@ static const struct owl_pinmux_func s900_functions[] = {
[S900_MUX_SIRQ1] = FUNCTION(sirq1),
[S900_MUX_SIRQ2] = FUNCTION(sirq2)
};
-/* PAD PULL UP/DOWN CONFIGURES */
-#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt) \
- { \
- .reg = PAD_PULLCTL##pull_reg, \
- .shift = pull_sft, \
- .width = pull_wdt, \
- }
-
-#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt) \
- struct owl_pullctl pad_name##_pullctl_conf \
- = PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
-
-#define ST_CONF(st_reg, st_sft, st_wdt) \
- { \
- .reg = PAD_ST##st_reg, \
- .shift = st_sft, \
- .width = st_wdt, \
- }
-
-#define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt) \
- struct owl_st pad_name##_st_conf \
- = ST_CONF(st_reg, st_sft, st_wdt)
/* PAD_PULLCTL0 */
static PAD_PULLCTL_CONF(ETH_RXER, 0, 18, 2);
@@ -1639,34 +1555,6 @@ static PAD_ST_CONF(SPI0_SS, 1, 2, 1);
static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
-#define PAD_INFO(name) \
- { \
- .pad = name, \
- .pullctl = NULL, \
- .st = NULL, \
- }
-
-#define PAD_INFO_ST(name) \
- { \
- .pad = name, \
- .pullctl = NULL, \
- .st = &name##_st_conf, \
- }
-
-#define PAD_INFO_PULLCTL(name) \
- { \
- .pad = name, \
- .pullctl = &name##_pullctl_conf, \
- .st = NULL, \
- }
-
-#define PAD_INFO_PULLCTL_ST(name) \
- { \
- .pad = name, \
- .pullctl = &name##_pullctl_conf, \
- .st = &name##_st_conf, \
- }
-
/* Pad info table */
static struct owl_padinfo s900_padinfo[NUM_PADS] = {
[ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
@@ -1821,28 +1709,75 @@ static struct owl_padinfo s900_padinfo[NUM_PADS] = {
[SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3)
};
-#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, \
- _intc_ctl, _intc_pd, _intc_msk, _intc_type) \
- [OWL_GPIO_PORT_##port] = { \
- .offset = base, \
- .pins = count, \
- .outen = _outen, \
- .inen = _inen, \
- .dat = _dat, \
- .intc_ctl = _intc_ctl, \
- .intc_pd = _intc_pd, \
- .intc_msk = _intc_msk, \
- .intc_type = _intc_type, \
+static const struct owl_gpio_port s900_gpio_ports[] = {
+ OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240, 0),
+ OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C, 0),
+ OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238, 0),
+ OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234, 0),
+ OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230, 0),
+ OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178, 0)
+};
+
+enum s900_pinconf_pull {
+ OWL_PINCONF_PULL_HIZ,
+ OWL_PINCONF_PULL_DOWN,
+ OWL_PINCONF_PULL_UP,
+ OWL_PINCONF_PULL_HOLD,
+};
+
+static int s900_pad_pinconf_arg2val(const struct owl_padinfo *info,
+ unsigned int param,
+ u32 *arg)
+{
+ switch (param) {
+ case PIN_CONFIG_BIAS_BUS_HOLD:
+ *arg = OWL_PINCONF_PULL_HOLD;
+ break;
+ case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+ *arg = OWL_PINCONF_PULL_HIZ;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ *arg = OWL_PINCONF_PULL_DOWN;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ *arg = OWL_PINCONF_PULL_UP;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ *arg = (*arg >= 1 ? 1 : 0);
+ break;
+ default:
+ return -ENOTSUPP;
}
-static const struct owl_gpio_port s900_gpio_ports[] = {
- OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240),
- OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C),
- OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238),
- OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234),
- OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230),
- OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178)
-};
+ return 0;
+}
+
+static int s900_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
+ unsigned int param,
+ u32 *arg)
+{
+ switch (param) {
+ case PIN_CONFIG_BIAS_BUS_HOLD:
+ *arg = *arg == OWL_PINCONF_PULL_HOLD;
+ break;
+ case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+ *arg = *arg == OWL_PINCONF_PULL_HIZ;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ *arg = *arg == OWL_PINCONF_PULL_DOWN;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ *arg = *arg == OWL_PINCONF_PULL_UP;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ *arg = *arg == 1;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ return 0;
+}
static struct owl_pinctrl_soc_data s900_pinctrl_data = {
.padinfo = s900_padinfo,
@@ -1854,7 +1789,9 @@ static struct owl_pinctrl_soc_data s900_pinctrl_data = {
.ngroups = ARRAY_SIZE(s900_groups),
.ngpios = NUM_GPIOS,
.ports = s900_gpio_ports,
- .nports = ARRAY_SIZE(s900_gpio_ports)
+ .nports = ARRAY_SIZE(s900_gpio_ports),
+ .padctl_arg2val = s900_pad_pinconf_arg2val,
+ .padctl_val2arg = s900_pad_pinconf_val2arg,
};
static int s900_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
index fa53091..f180aa4 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
*
@@ -6,16 +7,6 @@
* This driver is inspired by:
* pinctrl-nomadik.c, please see original file for copyright information
* pinctrl-tegra.c, please see original file for copyright information
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/bitmap.h>
@@ -72,10 +63,8 @@
#define GPIO_REG_OFFSET(p) ((p) / 32)
#define GPIO_REG_SHIFT(p) ((p) % 32)
-enum bcm2835_pinconf_param {
- /* argument: bcm2835_pinconf_pull */
- BCM2835_PINCONF_PARAM_PULL = (PIN_CONFIG_END + 1),
-};
+/* argument: bcm2835_pinconf_pull */
+#define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
struct bcm2835_pinctrl {
struct device *dev;
@@ -90,7 +79,7 @@ struct bcm2835_pinctrl {
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range gpio_range;
- spinlock_t irq_lock[BCM2835_NUM_BANKS];
+ raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
};
/* pins are just named GPIO0..GPIO53 */
@@ -461,10 +450,10 @@ static void bcm2835_gpio_irq_enable(struct irq_data *data)
unsigned bank = GPIO_REG_OFFSET(gpio);
unsigned long flags;
- spin_lock_irqsave(&pc->irq_lock[bank], flags);
+ raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
set_bit(offset, &pc->enabled_irq_map[bank]);
bcm2835_gpio_irq_config(pc, gpio, true);
- spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
+ raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
}
static void bcm2835_gpio_irq_disable(struct irq_data *data)
@@ -476,12 +465,12 @@ static void bcm2835_gpio_irq_disable(struct irq_data *data)
unsigned bank = GPIO_REG_OFFSET(gpio);
unsigned long flags;
- spin_lock_irqsave(&pc->irq_lock[bank], flags);
+ raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
bcm2835_gpio_irq_config(pc, gpio, false);
/* Clear events that were latched prior to clearing event sources */
bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
clear_bit(offset, &pc->enabled_irq_map[bank]);
- spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
+ raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
}
static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
@@ -584,7 +573,7 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
unsigned long flags;
int ret;
- spin_lock_irqsave(&pc->irq_lock[bank], flags);
+ raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
if (test_bit(offset, &pc->enabled_irq_map[bank]))
ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
@@ -596,7 +585,7 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
else
irq_set_handler_locked(data, handle_level_irq);
- spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
+ raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
return ret;
}
@@ -1047,7 +1036,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
for_each_set_bit(offset, &events, 32)
bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
- spin_lock_init(&pc->irq_lock[i]);
+ raw_spin_lock_init(&pc->irq_lock[i]);
}
err = gpiochip_add_data(&pc->gpio_chip, pc);
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index dccf64c..2d6db43 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -5,6 +5,10 @@
select GENERIC_PINCONF
select REGMAP
+config PINCTRL_IMX_SCU
+ bool
+ select PINCTRL_IMX
+
config PINCTRL_IMX1_CORE
bool
select PINMUX
@@ -124,6 +128,13 @@
help
Say Y here to enable the imx8mq pinctrl driver
+config PINCTRL_IMX8QXP
+ bool "IMX8QXP pinctrl driver"
+ depends on SOC_IMX8QXP
+ select PINCTRL_IMX_SCU
+ help
+ Say Y here to enable the imx8qxp pinctrl driver
+
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 73175b3..6ee398a 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Freescale pin control drivers
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o
@@ -18,6 +19,7 @@
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
+obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 4e8cf0e..188001b 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -57,9 +57,11 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *num_maps)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct group_desc *grp;
struct pinctrl_map *new_map;
struct device_node *parent;
+ struct imx_pin *pin;
int map_num = 1;
int i, j;
@@ -73,11 +75,14 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
return -EINVAL;
}
- for (i = 0; i < grp->num_pins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- if (!(pin->config & IMX_NO_PAD_CTL))
- map_num++;
+ if (info->flags & IMX_USE_SCU) {
+ map_num += grp->num_pins;
+ } else {
+ for (i = 0; i < grp->num_pins; i++) {
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL))
+ map_num++;
+ }
}
new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
@@ -102,16 +107,35 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
/* create config map */
new_map++;
for (i = j = 0; i < grp->num_pins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
+ pin = &((struct imx_pin *)(grp->data))[i];
- if (!(pin->config & IMX_NO_PAD_CTL)) {
- new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
- new_map[j].data.configs.group_or_pin =
+ /*
+ * We only create config maps for SCU pads or MMIO pads that
+ * are not using the default config(a.k.a IMX_NO_PAD_CTL)
+ */
+ if (!(info->flags & IMX_USE_SCU) &&
+ (pin->conf.mmio.config & IMX_NO_PAD_CTL))
+ continue;
+
+ new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ new_map[j].data.configs.group_or_pin =
pin_get_name(pctldev, pin->pin);
- new_map[j].data.configs.configs = &pin->config;
+
+ if (info->flags & IMX_USE_SCU) {
+ /*
+ * For SCU case, we set mux and conf together
+ * in one IPC call
+ */
+ new_map[j].data.configs.configs =
+ (unsigned long *)&pin->conf.scu;
+ new_map[j].data.configs.num_configs = 2;
+ } else {
+ new_map[j].data.configs.configs =
+ &pin->conf.mmio.config;
new_map[j].data.configs.num_configs = 1;
- j++;
}
+
+ j++;
}
dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
@@ -133,19 +157,96 @@ static const struct pinctrl_ops imx_pctrl_ops = {
.pin_dbg_show = imx_pin_dbg_show,
.dt_node_to_map = imx_dt_node_to_map,
.dt_free_map = imx_dt_free_map,
-
};
+static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl,
+ struct imx_pin *pin)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
+ const struct imx_pin_reg *pin_reg;
+ unsigned int pin_id;
+
+ pin_id = pin->pin;
+ pin_reg = &ipctl->pin_regs[pin_id];
+
+ if (pin_reg->mux_reg == -1) {
+ dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
+ info->pins[pin_id].name);
+ return 0;
+ }
+
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ u32 reg;
+
+ reg = readl(ipctl->base + pin_reg->mux_reg);
+ reg &= ~info->mux_mask;
+ reg |= (pin_mmio->mux_mode << info->mux_shift);
+ writel(reg, ipctl->base + pin_reg->mux_reg);
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->mux_reg, reg);
+ } else {
+ writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg);
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->mux_reg, pin_mmio->mux_mode);
+ }
+
+ /*
+ * If the select input value begins with 0xff, it's a quirky
+ * select input and the value should be interpreted as below.
+ * 31 23 15 7 0
+ * | 0xff | shift | width | select |
+ * It's used to work around the problem that the select
+ * input for some pin is not implemented in the select
+ * input register but in some general purpose register.
+ * We encode the select input value, width and shift of
+ * the bit field into input_val cell of pin function ID
+ * in device tree, and then decode them here for setting
+ * up the select input bits in general purpose register.
+ */
+ if (pin_mmio->input_val >> 24 == 0xff) {
+ u32 val = pin_mmio->input_val;
+ u8 select = val & 0xff;
+ u8 width = (val >> 8) & 0xff;
+ u8 shift = (val >> 16) & 0xff;
+ u32 mask = ((1 << width) - 1) << shift;
+ /*
+ * The input_reg[i] here is actually some IOMUXC general
+ * purpose register, not regular select input register.
+ */
+ val = readl(ipctl->base + pin_mmio->input_reg);
+ val &= ~mask;
+ val |= select << shift;
+ writel(val, ipctl->base + pin_mmio->input_reg);
+ } else if (pin_mmio->input_reg) {
+ /*
+ * Regular select input register can never be at offset
+ * 0, and we only print register value for regular case.
+ */
+ if (ipctl->input_sel_base)
+ writel(pin_mmio->input_val, ipctl->input_sel_base +
+ pin_mmio->input_reg);
+ else
+ writel(pin_mmio->input_val, ipctl->base +
+ pin_mmio->input_reg);
+ dev_dbg(ipctl->dev,
+ "==>select_input: offset 0x%x val 0x%x\n",
+ pin_mmio->input_reg, pin_mmio->input_val);
+ }
+
+ return 0;
+}
+
static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
- const struct imx_pin_reg *pin_reg;
- unsigned int npins, pin_id;
- int i;
- struct group_desc *grp = NULL;
- struct function_desc *func = NULL;
+ struct function_desc *func;
+ struct group_desc *grp;
+ struct imx_pin *pin;
+ unsigned int npins;
+ int i, err;
/*
* Configure the mux mode for each pin in the group for a specific
@@ -165,72 +266,16 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
func->name, grp->name);
for (i = 0; i < npins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- pin_id = pin->pin;
- pin_reg = &ipctl->pin_regs[pin_id];
-
- if (pin_reg->mux_reg == -1) {
- dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
- info->pins[pin_id].name);
- continue;
- }
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- u32 reg;
- reg = readl(ipctl->base + pin_reg->mux_reg);
- reg &= ~info->mux_mask;
- reg |= (pin->mux_mode << info->mux_shift);
- writel(reg, ipctl->base + pin_reg->mux_reg);
- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
- pin_reg->mux_reg, reg);
- } else {
- writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
- pin_reg->mux_reg, pin->mux_mode);
- }
-
/*
- * If the select input value begins with 0xff, it's a quirky
- * select input and the value should be interpreted as below.
- * 31 23 15 7 0
- * | 0xff | shift | width | select |
- * It's used to work around the problem that the select
- * input for some pin is not implemented in the select
- * input register but in some general purpose register.
- * We encode the select input value, width and shift of
- * the bit field into input_val cell of pin function ID
- * in device tree, and then decode them here for setting
- * up the select input bits in general purpose register.
+ * For IMX_USE_SCU case, we postpone the mux setting
+ * until config is set as we can set them together
+ * in one IPC call
*/
- if (pin->input_val >> 24 == 0xff) {
- u32 val = pin->input_val;
- u8 select = val & 0xff;
- u8 width = (val >> 8) & 0xff;
- u8 shift = (val >> 16) & 0xff;
- u32 mask = ((1 << width) - 1) << shift;
- /*
- * The input_reg[i] here is actually some IOMUXC general
- * purpose register, not regular select input register.
- */
- val = readl(ipctl->base + pin->input_reg);
- val &= ~mask;
- val |= select << shift;
- writel(val, ipctl->base + pin->input_reg);
- } else if (pin->input_reg) {
- /*
- * Regular select input register can never be at offset
- * 0, and we only print register value for regular case.
- */
- if (ipctl->input_sel_base)
- writel(pin->input_val, ipctl->input_sel_base +
- pin->input_reg);
- else
- writel(pin->input_val, ipctl->base +
- pin->input_reg);
- dev_dbg(ipctl->dev,
- "==>select_input: offset 0x%x val 0x%x\n",
- pin->input_reg, pin->input_val);
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (!(info->flags & IMX_USE_SCU)) {
+ err = imx_pmx_set_one_pin_mmio(ipctl, pin);
+ if (err)
+ return err;
}
}
@@ -300,8 +345,8 @@ static u32 imx_pinconf_parse_generic_config(struct device_node *np,
return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
}
-static int imx_pinconf_get(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *config)
+static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
@@ -321,9 +366,21 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
return 0;
}
-static int imx_pinconf_set(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *configs,
- unsigned num_configs)
+static int imx_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ if (info->flags & IMX_USE_SCU)
+ return imx_pinconf_get_scu(pctldev, pin_id, config);
+ else
+ return imx_pinconf_get_mmio(pctldev, pin_id, config);
+}
+
+static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
@@ -358,19 +415,48 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
return 0;
}
+static int imx_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ if (info->flags & IMX_USE_SCU)
+ return imx_pinconf_set_scu(pctldev, pin_id,
+ configs, num_configs);
+ else
+ return imx_pinconf_set_mmio(pctldev, pin_id,
+ configs, num_configs);
+}
+
static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg;
unsigned long config;
+ int ret;
- if (!pin_reg || pin_reg->conf_reg == -1) {
- seq_puts(s, "N/A");
- return;
+ if (info->flags & IMX_USE_SCU) {
+ ret = imx_pinconf_get_scu(pctldev, pin_id, &config);
+ if (ret) {
+ dev_err(ipctl->dev, "failed to get %s pinconf\n",
+ pin_get_name(pctldev, pin_id));
+ seq_puts(s, "N/A");
+ return;
+ }
+ } else {
+ pin_reg = &ipctl->pin_regs[pin_id];
+ if (!pin_reg || pin_reg->conf_reg == -1) {
+ seq_puts(s, "N/A");
+ return;
+ }
+
+ config = readl(ipctl->base + pin_reg->conf_reg);
}
- config = readl(ipctl->base + pin_reg->conf_reg);
seq_printf(s, "0x%lx", config);
}
@@ -418,9 +504,65 @@ static const struct pinconf_ops imx_pinconf_ops = {
* <mux_reg conf_reg input_reg mux_mode input_val>
* SHARE_MUX_CONF_REG:
* <mux_conf_reg input_reg mux_mode input_val>
+ * IMX_USE_SCU:
+ * <pin_id mux_mode>
*/
#define FSL_PIN_SIZE 24
#define FSL_PIN_SHARE_SIZE 20
+#define FSL_SCU_PIN_SIZE 12
+
+static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p,
+ struct device_node *np)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
+ struct imx_pin_reg *pin_reg;
+ const __be32 *list = *list_p;
+ u32 mux_reg, conf_reg;
+ u32 config;
+
+ mux_reg = be32_to_cpu(*list++);
+
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
+
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ conf_reg = mux_reg;
+ } else {
+ conf_reg = be32_to_cpu(*list++);
+ if (!conf_reg)
+ conf_reg = -1;
+ }
+
+ *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
+ pin_reg = &ipctl->pin_regs[*pin_id];
+ pin->pin = *pin_id;
+ pin_reg->mux_reg = mux_reg;
+ pin_reg->conf_reg = conf_reg;
+ pin_mmio->input_reg = be32_to_cpu(*list++);
+ pin_mmio->mux_mode = be32_to_cpu(*list++);
+ pin_mmio->input_val = be32_to_cpu(*list++);
+
+ if (info->generic_pinconf) {
+ /* generic pin config decoded */
+ pin_mmio->config = imx_pinconf_parse_generic_config(np, ipctl);
+ } else {
+ /* legacy pin config read from devicetree */
+ config = be32_to_cpu(*list++);
+
+ /* SION bit is in mux register */
+ if (config & IMX_PAD_SION)
+ pin_mmio->mux_mode |= IOMUXC_CONFIG_SION;
+ pin_mmio->config = config & ~IMX_PAD_SION;
+ }
+
+ *list_p = list;
+
+ dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name,
+ pin_mmio->mux_mode, pin_mmio->config);
+}
static int imx_pinctrl_parse_groups(struct device_node *np,
struct group_desc *grp,
@@ -428,14 +570,16 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
u32 index)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin *pin;
int size, pin_size;
const __be32 *list;
int i;
- u32 config;
dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np);
- if (info->flags & SHARE_MUX_CONF_REG)
+ if (info->flags & IMX_USE_SCU)
+ pin_size = FSL_SCU_PIN_SIZE;
+ else if (info->flags & SHARE_MUX_CONF_REG)
pin_size = FSL_PIN_SHARE_SIZE;
else
pin_size = FSL_PIN_SIZE;
@@ -472,9 +616,6 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
return -EINVAL;
}
- /* first try to parse the generic pin config */
- config = imx_pinconf_parse_generic_config(np, ipctl);
-
grp->num_pins = size / pin_size;
grp->data = devm_kcalloc(ipctl->dev,
grp->num_pins, sizeof(struct imx_pin),
@@ -486,48 +627,13 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
return -ENOMEM;
for (i = 0; i < grp->num_pins; i++) {
- u32 mux_reg = be32_to_cpu(*list++);
- u32 conf_reg;
- unsigned int pin_id;
- struct imx_pin_reg *pin_reg;
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
- mux_reg = -1;
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- conf_reg = mux_reg;
- } else {
- conf_reg = be32_to_cpu(*list++);
- if (!conf_reg)
- conf_reg = -1;
- }
-
- pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
- pin_reg = &ipctl->pin_regs[pin_id];
- pin->pin = pin_id;
- grp->pins[i] = pin_id;
- pin_reg->mux_reg = mux_reg;
- pin_reg->conf_reg = conf_reg;
- pin->input_reg = be32_to_cpu(*list++);
- pin->mux_mode = be32_to_cpu(*list++);
- pin->input_val = be32_to_cpu(*list++);
-
- if (info->generic_pinconf) {
- /* generic pin config decoded */
- pin->config = config;
- } else {
- /* legacy pin config read from devicetree */
- config = be32_to_cpu(*list++);
-
- /* SION bit is in mux register */
- if (config & IMX_PAD_SION)
- pin->mux_mode |= IOMUXC_CONFIG_SION;
- pin->config = config & ~IMX_PAD_SION;
- }
-
- dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
- pin->mux_mode, pin->config);
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (info->flags & IMX_USE_SCU)
+ imx_pinctrl_parse_pin_scu(ipctl, &grp->pins[i],
+ pin, &list);
+ else
+ imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
+ pin, &list, np);
}
return 0;
@@ -699,35 +805,37 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (!ipctl)
return -ENOMEM;
- ipctl->pin_regs = devm_kmalloc_array(&pdev->dev,
- info->npins, sizeof(*ipctl->pin_regs),
- GFP_KERNEL);
- if (!ipctl->pin_regs)
- return -ENOMEM;
+ if (!(info->flags & IMX_USE_SCU)) {
+ ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
+ sizeof(*ipctl->pin_regs),
+ GFP_KERNEL);
+ if (!ipctl->pin_regs)
+ return -ENOMEM;
- for (i = 0; i < info->npins; i++) {
- ipctl->pin_regs[i].mux_reg = -1;
- ipctl->pin_regs[i].conf_reg = -1;
- }
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- ipctl->base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(ipctl->base))
- return PTR_ERR(ipctl->base);
-
- if (of_property_read_bool(dev_np, "fsl,input-sel")) {
- np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
- if (!np) {
- dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
- return -EINVAL;
+ for (i = 0; i < info->npins; i++) {
+ ipctl->pin_regs[i].mux_reg = -1;
+ ipctl->pin_regs[i].conf_reg = -1;
}
- ipctl->input_sel_base = of_iomap(np, 0);
- of_node_put(np);
- if (!ipctl->input_sel_base) {
- dev_err(&pdev->dev,
- "iomuxc input select base address not found\n");
- return -ENOMEM;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ipctl->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ipctl->base))
+ return PTR_ERR(ipctl->base);
+
+ if (of_property_read_bool(dev_np, "fsl,input-sel")) {
+ np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
+ if (!np) {
+ dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
+ return -EINVAL;
+ }
+
+ ipctl->input_sel_base = of_iomap(np, 0);
+ of_node_put(np);
+ if (!ipctl->input_sel_base) {
+ dev_err(&pdev->dev,
+ "iomuxc input select base address not found\n");
+ return -ENOMEM;
+ }
}
}
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 4b8225c..98a4889 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -19,16 +19,14 @@ struct platform_device;
extern struct pinmux_ops imx_pmx_ops;
/**
- * struct imx_pin - describes a single i.MX pin
- * @pin: the pin_id of this pin
+ * struct imx_pin_mmio - MMIO pin configurations
* @mux_mode: the mux mode for this pin.
* @input_reg: the select input register offset for this pin if any
* 0 if no select input setting needed.
* @input_val: the select input value for this pin.
* @configs: the config for this pin.
*/
-struct imx_pin {
- unsigned int pin;
+struct imx_pin_mmio {
unsigned int mux_mode;
u16 input_reg;
unsigned int input_val;
@@ -36,6 +34,29 @@ struct imx_pin {
};
/**
+ * struct imx_pin_scu - SCU pin configurations
+ * @mux: the mux mode for this pin.
+ * @configs: the config for this pin.
+ */
+struct imx_pin_scu {
+ unsigned int mux_mode;
+ unsigned long config;
+};
+
+/**
+ * struct imx_pin - describes a single i.MX pin
+ * @pin: the pin_id of this pin
+ * @conf: config type of this pin, either mmio or scu
+ */
+struct imx_pin {
+ unsigned int pin;
+ union {
+ struct imx_pin_mmio mmio;
+ struct imx_pin_scu scu;
+ } conf;
+};
+
+/**
* struct imx_pin_reg - describe a pin reg map
* @mux_reg: mux register offset
* @conf_reg: config register offset
@@ -99,8 +120,9 @@ struct imx_pinctrl {
#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
{ .param = p, .mask = m, .shift = o, .invert = true, }
-#define SHARE_MUX_CONF_REG 0x1
-#define ZERO_OFFSET_VALID 0x2
+#define SHARE_MUX_CONF_REG BIT(0)
+#define ZERO_OFFSET_VALID BIT(1)
+#define IMX_USE_SCU BIT(2)
#define NO_MUX 0x0
#define NO_PAD 0x0
@@ -113,4 +135,37 @@ struct imx_pinctrl {
int imx_pinctrl_probe(struct platform_device *pdev,
const struct imx_pinctrl_soc_info *info);
+
+#ifdef CONFIG_PINCTRL_IMX_SCU
+#define BM_PAD_CTL_GP_ENABLE BIT(30)
+#define BM_PAD_CTL_IFMUX_ENABLE BIT(31)
+#define BP_PAD_CTL_IFMUX 27
+
+int imx_pinctrl_sc_ipc_init(struct platform_device *pdev);
+int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config);
+int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *configs, unsigned num_configs);
+void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p);
+#else
+static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ return -EINVAL;
+}
+static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ return -EINVAL;
+}
+static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id,
+ struct imx_pin *pin,
+ const __be32 **list_p)
+{
+}
+#endif
#endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
index f521bdb..922ff73 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
@@ -256,46 +256,8 @@ static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
#define BM_OBE_ENABLED BIT(17)
#define BM_IBE_ENABLED BIT(16)
-#define BM_LK_ENABLED BIT(15)
#define BM_MUX_MODE 0xf00
#define BP_MUX_MODE 8
-#define BM_PULL_ENABLED BIT(1)
-
-static const struct imx_cfg_params_decode imx7ulp_cfg_decodes[] = {
- IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_STRENGTH, BIT(6), 6),
- IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_PUSH_PULL, BIT(5), 5),
- IMX_CFG_PARAMS_DECODE(PIN_CONFIG_SLEW_RATE, BIT(2), 2),
- IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_DISABLE, BIT(1), 1),
- IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_PULL_UP, BIT(0), 0),
-
- IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_DRIVE_OPEN_DRAIN, BIT(5), 5),
- IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_BIAS_PULL_DOWN, BIT(0), 0),
-};
-
-static void imx7ulp_cfg_params_fixup(unsigned long *configs,
- unsigned int num_configs,
- u32 *raw_config)
-{
- enum pin_config_param param;
- u32 param_val;
- int i;
-
- /* lock field disabled */
- *raw_config &= ~BM_LK_ENABLED;
-
- for (i = 0; i < num_configs; i++) {
- param = pinconf_to_config_param(configs[i]);
- param_val = pinconf_to_config_argument(configs[i]);
-
- if ((param == PIN_CONFIG_BIAS_PULL_UP) ||
- (param == PIN_CONFIG_BIAS_PULL_DOWN)) {
- /* pull enabled */
- *raw_config |= BM_PULL_ENABLED;
-
- return;
- }
- }
-}
static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
@@ -326,10 +288,6 @@ static const struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
.gpio_set_direction = imx7ulp_pmx_gpio_set_direction,
.mux_mask = BM_MUX_MODE,
.mux_shift = BP_MUX_MODE,
- .generic_pinconf = true,
- .decodes = imx7ulp_cfg_decodes,
- .num_decodes = ARRAY_SIZE(imx7ulp_cfg_decodes),
- .fixup = imx7ulp_cfg_params_fixup,
};
static const struct of_device_id imx7ulp_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c
new file mode 100644
index 0000000..1131dc3
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ * Dong Aisheng <[email protected]>
+ */
+
+#include <dt-bindings/pinctrl/pads-imx8qxp.h>
+#include <linux/err.h>
+#include <linux/firmware/imx/sci.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_PERST_B),
+ IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_CLKREQ_B),
+ IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_WAKE_B),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP),
+ IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC0),
+ IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC1),
+ IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC2),
+ IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CLK),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CMD),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA0),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA1),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA2),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA4),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA5),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA6),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA7),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_STROBE),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_RESET_B),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_RESET_B),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_VSELECT),
+ IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_RE_P_N),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_WP),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CD_B),
+ IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_DQS_P_N),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CLK),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CMD),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA0),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA1),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA2),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXC),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TX_CTL),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD0),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD1),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD2),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXC),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RX_CTL),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD0),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD1),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD2),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_REFCLK_125M_25M),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDIO),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDC),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FSR),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FST),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKR),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKT),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX0),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX1),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX2_RX3),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX3_RX2),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX4_RX1),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX5_RX0),
+ IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_EXT_CLK),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_SCK),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDO),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDI),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS0),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS1),
+ IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN1),
+ IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN0),
+ IMX_PINCTRL_PIN(IMX8QXP_MCLK_OUT0),
+ IMX_PINCTRL_PIN(IMX8QXP_UART1_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART1_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART1_RTS_B),
+ IMX_PINCTRL_PIN(IMX8QXP_UART1_CTS_B),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXD),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXC),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI0_RXD),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXFS),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXD),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXC),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXFS),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI2_CS0),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDO),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDI),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI2_SCK),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_SCK),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDI),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDO),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS1),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS0),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN1),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN0),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN3),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN2),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN5),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN4),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART0_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART0_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART2_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART2_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SCL),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SDA),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_00),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_01),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SCL),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SDA),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_00),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_01),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO),
+ IMX_PINCTRL_PIN(IMX8QXP_JTAG_TRST_B),
+ IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SCL),
+ IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SDA),
+ IMX_PINCTRL_PIN(IMX8QXP_PMIC_INT_B),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_00),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_01),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_PMIC_STANDBY),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE0),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE1),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE2),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE3),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D00),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D01),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D02),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D03),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D04),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D05),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D06),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D07),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_HSYNC),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_VSYNC),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_PCLK),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_MCLK),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_EN),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_RESET),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_MCLK_OUT),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SCL),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SDA),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_01),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_00),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA0),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA1),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA2),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA3),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DQS),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS0_B),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS1_B),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SCLK),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SCLK),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA0),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA1),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA2),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA3),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DQS),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS0_B),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS1_B),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B),
+};
+
+static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
+ .pins = imx8qxp_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx8qxp_pinctrl_pads),
+ .flags = IMX_USE_SCU,
+};
+
+static const struct of_device_id imx8qxp_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx8qxp-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx8qxp_pinctrl_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = imx_pinctrl_sc_ipc_init(pdev);
+ if (ret)
+ return ret;
+
+ return imx_pinctrl_probe(pdev, &imx8qxp_pinctrl_info);
+}
+
+static struct platform_driver imx8qxp_pinctrl_driver = {
+ .driver = {
+ .name = "imx8qxp-pinctrl",
+ .of_match_table = of_match_ptr(imx8qxp_pinctrl_of_match),
+ .suppress_bind_attrs = true,
+ },
+ .probe = imx8qxp_pinctrl_probe,
+};
+
+static int __init imx8qxp_pinctrl_init(void)
+{
+ return platform_driver_register(&imx8qxp_pinctrl_driver);
+}
+arch_initcall(imx8qxp_pinctrl_init);
diff --git a/drivers/pinctrl/freescale/pinctrl-scu.c b/drivers/pinctrl/freescale/pinctrl-scu.c
new file mode 100644
index 0000000..83e69c0
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-scu.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ * Dong Aisheng <[email protected]>
+ */
+
+#include <linux/err.h>
+#include <linux/firmware/imx/sci.h>
+#include <linux/of_address.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "../core.h"
+#include "pinctrl-imx.h"
+
+enum pad_func_e {
+ IMX_SC_PAD_FUNC_SET = 15,
+ IMX_SC_PAD_FUNC_GET = 16,
+};
+
+struct imx_sc_msg_req_pad_set {
+ struct imx_sc_rpc_msg hdr;
+ u32 val;
+ u16 pad;
+} __packed;
+
+struct imx_sc_msg_req_pad_get {
+ struct imx_sc_rpc_msg hdr;
+ u16 pad;
+} __packed;
+
+struct imx_sc_msg_resp_pad_get {
+ struct imx_sc_rpc_msg hdr;
+ u32 val;
+} __packed;
+
+struct imx_sc_ipc *pinctrl_ipc_handle;
+
+int imx_pinctrl_sc_ipc_init(struct platform_device *pdev)
+{
+ return imx_scu_get_handle(&pinctrl_ipc_handle);
+}
+
+int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config)
+{
+ struct imx_sc_msg_req_pad_get msg;
+ struct imx_sc_msg_resp_pad_get *resp;
+ struct imx_sc_rpc_msg *hdr = &msg.hdr;
+ int ret;
+
+ hdr->ver = IMX_SC_RPC_VERSION;
+ hdr->svc = IMX_SC_RPC_SVC_PAD;
+ hdr->func = IMX_SC_PAD_FUNC_GET;
+ hdr->size = 2;
+
+ msg.pad = pin_id;
+
+ ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
+ if (ret)
+ return ret;
+
+ resp = (struct imx_sc_msg_resp_pad_get *)&msg;
+ *config = resp->val;
+
+ return 0;
+}
+
+int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *configs, unsigned num_configs)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ struct imx_sc_msg_req_pad_set msg;
+ struct imx_sc_rpc_msg *hdr = &msg.hdr;
+ unsigned int mux = configs[0];
+ unsigned int conf = configs[1];
+ unsigned int val;
+ int ret;
+
+ /*
+ * Set mux and conf together in one IPC call
+ */
+ WARN_ON(num_configs != 2);
+
+ val = conf | BM_PAD_CTL_IFMUX_ENABLE | BM_PAD_CTL_GP_ENABLE;
+ val |= mux << BP_PAD_CTL_IFMUX;
+
+ hdr->ver = IMX_SC_RPC_VERSION;
+ hdr->svc = IMX_SC_RPC_SVC_PAD;
+ hdr->func = IMX_SC_PAD_FUNC_SET;
+ hdr->size = 3;
+
+ msg.pad = pin_id;
+ msg.val = val;
+
+ ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
+
+ dev_dbg(ipctl->dev, "write: pin_id %u config 0x%x val 0x%x\n",
+ pin_id, conf, val);
+
+ return ret;
+}
+
+void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin_scu *pin_scu = &pin->conf.scu;
+ const __be32 *list = *list_p;
+
+ pin->pin = be32_to_cpu(*list++);
+ *pin_id = pin->pin;
+ pin_scu->mux_mode = be32_to_cpu(*list++);
+ pin_scu->config = be32_to_cpu(*list++);
+ *list_p = list;
+
+ dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin->pin].name,
+ pin_scu->mux_mode, pin_scu->config);
+}
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 9d142e1..d8cb584 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -3,7 +3,7 @@
config EINT_MTK
bool "MediaTek External Interrupt Support"
- depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || COMPILE_TEST
+ depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || PINCTRL_MTK_PARIS || COMPILE_TEST
select GPIOLIB
select IRQ_DOMAIN
@@ -48,6 +48,12 @@
depends on PINCTRL_MTK_MOORE
default y
+config PINCTRL_MT7629
+ bool "Mediatek MT7629 pin control"
+ depends on MACH_MT7629 || COMPILE_TEST
+ depends on PINCTRL_MTK_MOORE
+ default y
+
config PINCTRL_MT8135
bool "Mediatek MT8135 pin control"
depends on MACH_MT8135 || COMPILE_TEST
@@ -77,6 +83,13 @@
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
+config PINCTRL_MT6797
+ bool "Mediatek MT6797 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK_PARIS
+
config PINCTRL_MT7622
bool "MediaTek MT7622 pin control"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 70d8000..4b4e2eaf 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -11,8 +11,10 @@
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
+obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
+obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c
index 3133ec0..aa1068d 100644
--- a/drivers/pinctrl/mediatek/pinctrl-moore.c
+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
@@ -310,8 +310,8 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
case PIN_CONFIG_DRIVE_STRENGTH:
if (hw->soc->drive_set) {
err = hw->soc->drive_set(hw, desc, arg);
- if (err)
- return err;
+ if (err)
+ return err;
} else {
err = -ENOTSUPP;
}
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6797.c b/drivers/pinctrl/mediatek/pinctrl-mt6797.c
new file mode 100644
index 0000000..adebe43
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6797.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Based on pinctrl-mt6765.c
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: ZH Chen <[email protected]>
+ *
+ * Copyright (C) Manivannan Sadhasivam <[email protected]>
+ *
+ */
+
+#include "pinctrl-mtk-mt6797.h"
+#include "pinctrl-paris.h"
+
+/*
+ * MT6797 have multiple bases to program pin configuration listed as the below:
+ * gpio:0x10005000, iocfg[l]:0x10002000, iocfg[b]:0x10002400,
+ * iocfg[r]:0x10002800, iocfg[t]:0x10002C00.
+ * _i_base could be used to indicate what base the pin should be mapped into.
+ */
+
+static const struct mtk_pin_field_calc mt6797_pin_mode_range[] = {
+ PIN_FIELD(0, 261, 0x300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt6797_pin_dir_range[] = {
+ PIN_FIELD(0, 261, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt6797_pin_di_range[] = {
+ PIN_FIELD(0, 261, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt6797_pin_do_range[] = {
+ PIN_FIELD(0, 261, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_reg_calc mt6797_reg_cals[PINCTRL_PIN_REG_MAX] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6797_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6797_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6797_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6797_pin_do_range),
+};
+
+static const char * const mt6797_pinctrl_register_base_names[] = {
+ "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt",
+};
+
+static const struct mtk_pin_soc mt6797_data = {
+ .reg_cal = mt6797_reg_cals,
+ .pins = mtk_pins_mt6797,
+ .npins = ARRAY_SIZE(mtk_pins_mt6797),
+ .ngrps = ARRAY_SIZE(mtk_pins_mt6797),
+ .gpio_m = 0,
+ .base_names = mt6797_pinctrl_register_base_names,
+ .nbase_names = ARRAY_SIZE(mt6797_pinctrl_register_base_names),
+};
+
+static const struct of_device_id mt6797_pinctrl_of_match[] = {
+ { .compatible = "mediatek,mt6797-pinctrl", },
+ { }
+};
+
+static int mt6797_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_paris_pinctrl_probe(pdev, &mt6797_data);
+}
+
+static struct platform_driver mt6797_pinctrl_driver = {
+ .driver = {
+ .name = "mt6797-pinctrl",
+ .of_match_table = mt6797_pinctrl_of_match,
+ },
+ .probe = mt6797_pinctrl_probe,
+};
+
+static int __init mt6797_pinctrl_init(void)
+{
+ return platform_driver_register(&mt6797_pinctrl_driver);
+}
+arch_initcall(mt6797_pinctrl_init);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
new file mode 100644
index 0000000..b5f0fa4
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
@@ -0,0 +1,450 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * The MT7629 driver based on Linux generic pinctrl binding.
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee <[email protected]>
+ */
+
+#include "pinctrl-moore.h"
+
+#define MT7629_PIN(_number, _name, _eint_n) \
+ MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1)
+
+static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = {
+ PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = {
+ PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_di_range[] = {
+ PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_do_range[] = {
+ PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = {
+ PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
+ PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
+ PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
+ PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
+ PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
+ PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1),
+ PIN_FIELD(70, 78, 0x7000, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_smt_range[] = {
+ PIN_FIELD(0, 10, 0x1100, 0x10, 0, 1),
+ PIN_FIELD(11, 18, 0x2100, 0x10, 0, 1),
+ PIN_FIELD(19, 32, 0x3100, 0x10, 0, 1),
+ PIN_FIELD(33, 48, 0x4100, 0x10, 0, 1),
+ PIN_FIELD(49, 50, 0x5100, 0x10, 0, 1),
+ PIN_FIELD(51, 69, 0x6100, 0x10, 0, 1),
+ PIN_FIELD(70, 78, 0x7100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_pullen_range[] = {
+ PIN_FIELD(0, 10, 0x1400, 0x10, 0, 1),
+ PIN_FIELD(11, 18, 0x2400, 0x10, 0, 1),
+ PIN_FIELD(19, 32, 0x3400, 0x10, 0, 1),
+ PIN_FIELD(33, 48, 0x4400, 0x10, 0, 1),
+ PIN_FIELD(49, 50, 0x5400, 0x10, 0, 1),
+ PIN_FIELD(51, 69, 0x6400, 0x10, 0, 1),
+ PIN_FIELD(70, 78, 0x7400, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_pullsel_range[] = {
+ PIN_FIELD(0, 10, 0x1500, 0x10, 0, 1),
+ PIN_FIELD(11, 18, 0x2500, 0x10, 0, 1),
+ PIN_FIELD(19, 32, 0x3500, 0x10, 0, 1),
+ PIN_FIELD(33, 48, 0x4500, 0x10, 0, 1),
+ PIN_FIELD(49, 50, 0x5500, 0x10, 0, 1),
+ PIN_FIELD(51, 69, 0x6500, 0x10, 0, 1),
+ PIN_FIELD(70, 78, 0x7500, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_drv_range[] = {
+ PIN_FIELD(0, 10, 0x1600, 0x10, 0, 4),
+ PIN_FIELD(11, 18, 0x2600, 0x10, 0, 4),
+ PIN_FIELD(19, 32, 0x3600, 0x10, 0, 4),
+ PIN_FIELD(33, 48, 0x4600, 0x10, 0, 4),
+ PIN_FIELD(49, 50, 0x5600, 0x10, 0, 4),
+ PIN_FIELD(51, 69, 0x6600, 0x10, 0, 4),
+ PIN_FIELD(70, 78, 0x7600, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_tdsel_range[] = {
+ PIN_FIELD(0, 10, 0x1200, 0x10, 0, 4),
+ PIN_FIELD(11, 18, 0x2200, 0x10, 0, 4),
+ PIN_FIELD(19, 32, 0x3200, 0x10, 0, 4),
+ PIN_FIELD(33, 48, 0x4200, 0x10, 0, 4),
+ PIN_FIELD(49, 50, 0x5200, 0x10, 0, 4),
+ PIN_FIELD(51, 69, 0x6200, 0x10, 0, 4),
+ PIN_FIELD(70, 78, 0x7200, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_rdsel_range[] = {
+ PIN_FIELD(0, 10, 0x1300, 0x10, 0, 4),
+ PIN_FIELD(11, 18, 0x2300, 0x10, 0, 4),
+ PIN_FIELD(19, 32, 0x3300, 0x10, 0, 4),
+ PIN_FIELD(33, 48, 0x4300, 0x10, 0, 4),
+ PIN_FIELD(49, 50, 0x5300, 0x10, 0, 4),
+ PIN_FIELD(51, 69, 0x6300, 0x10, 0, 4),
+ PIN_FIELD(70, 78, 0x7300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_reg_calc mt7629_reg_cals[] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7629_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7629_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7629_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7629_pin_do_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7629_pin_ies_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7629_pin_smt_range),
+ [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7629_pin_pullsel_range),
+ [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7629_pin_pullen_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7629_pin_drv_range),
+ [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7629_pin_tdsel_range),
+ [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7629_pin_rdsel_range),
+};
+
+static const struct mtk_pin_desc mt7629_pins[] = {
+ MT7629_PIN(0, "TOP_5G_CLK", 53),
+ MT7629_PIN(1, "TOP_5G_DATA", 54),
+ MT7629_PIN(2, "WF0_5G_HB0", 55),
+ MT7629_PIN(3, "WF0_5G_HB1", 56),
+ MT7629_PIN(4, "WF0_5G_HB2", 57),
+ MT7629_PIN(5, "WF0_5G_HB3", 58),
+ MT7629_PIN(6, "WF0_5G_HB4", 59),
+ MT7629_PIN(7, "WF0_5G_HB5", 60),
+ MT7629_PIN(8, "WF0_5G_HB6", 61),
+ MT7629_PIN(9, "XO_REQ", 9),
+ MT7629_PIN(10, "TOP_RST_N", 10),
+ MT7629_PIN(11, "SYS_WATCHDOG", 11),
+ MT7629_PIN(12, "EPHY_LED0_N_JTDO", 12),
+ MT7629_PIN(13, "EPHY_LED1_N_JTDI", 13),
+ MT7629_PIN(14, "EPHY_LED2_N_JTMS", 14),
+ MT7629_PIN(15, "EPHY_LED3_N_JTCLK", 15),
+ MT7629_PIN(16, "EPHY_LED4_N_JTRST_N", 16),
+ MT7629_PIN(17, "WF2G_LED_N", 17),
+ MT7629_PIN(18, "WF5G_LED_N", 18),
+ MT7629_PIN(19, "I2C_SDA", 19),
+ MT7629_PIN(20, "I2C_SCL", 20),
+ MT7629_PIN(21, "GPIO_9", 21),
+ MT7629_PIN(22, "GPIO_10", 22),
+ MT7629_PIN(23, "GPIO_11", 23),
+ MT7629_PIN(24, "GPIO_12", 24),
+ MT7629_PIN(25, "UART1_TXD", 25),
+ MT7629_PIN(26, "UART1_RXD", 26),
+ MT7629_PIN(27, "UART1_CTS", 27),
+ MT7629_PIN(28, "UART1_RTS", 28),
+ MT7629_PIN(29, "UART2_TXD", 29),
+ MT7629_PIN(30, "UART2_RXD", 30),
+ MT7629_PIN(31, "UART2_CTS", 31),
+ MT7629_PIN(32, "UART2_RTS", 32),
+ MT7629_PIN(33, "MDI_TP_P1", 33),
+ MT7629_PIN(34, "MDI_TN_P1", 34),
+ MT7629_PIN(35, "MDI_RP_P1", 35),
+ MT7629_PIN(36, "MDI_RN_P1", 36),
+ MT7629_PIN(37, "MDI_RP_P2", 37),
+ MT7629_PIN(38, "MDI_RN_P2", 38),
+ MT7629_PIN(39, "MDI_TP_P2", 39),
+ MT7629_PIN(40, "MDI_TN_P2", 40),
+ MT7629_PIN(41, "MDI_TP_P3", 41),
+ MT7629_PIN(42, "MDI_TN_P3", 42),
+ MT7629_PIN(43, "MDI_RP_P3", 43),
+ MT7629_PIN(44, "MDI_RN_P3", 44),
+ MT7629_PIN(45, "MDI_RP_P4", 45),
+ MT7629_PIN(46, "MDI_RN_P4", 46),
+ MT7629_PIN(47, "MDI_TP_P4", 47),
+ MT7629_PIN(48, "MDI_TN_P4", 48),
+ MT7629_PIN(49, "SMI_MDC", 49),
+ MT7629_PIN(50, "SMI_MDIO", 50),
+ MT7629_PIN(51, "PCIE_PERESET_N", 51),
+ MT7629_PIN(52, "PWM_0", 52),
+ MT7629_PIN(53, "GPIO_0", 0),
+ MT7629_PIN(54, "GPIO_1", 1),
+ MT7629_PIN(55, "GPIO_2", 2),
+ MT7629_PIN(56, "GPIO_3", 3),
+ MT7629_PIN(57, "GPIO_4", 4),
+ MT7629_PIN(58, "GPIO_5", 5),
+ MT7629_PIN(59, "GPIO_6", 6),
+ MT7629_PIN(60, "GPIO_7", 7),
+ MT7629_PIN(61, "GPIO_8", 8),
+ MT7629_PIN(62, "SPI_CLK", 62),
+ MT7629_PIN(63, "SPI_CS", 63),
+ MT7629_PIN(64, "SPI_MOSI", 64),
+ MT7629_PIN(65, "SPI_MISO", 65),
+ MT7629_PIN(66, "SPI_WP", 66),
+ MT7629_PIN(67, "SPI_HOLD", 67),
+ MT7629_PIN(68, "UART0_TXD", 68),
+ MT7629_PIN(69, "UART0_RXD", 69),
+ MT7629_PIN(70, "TOP_2G_CLK", 70),
+ MT7629_PIN(71, "TOP_2G_DATA", 71),
+ MT7629_PIN(72, "WF0_2G_HB0", 72),
+ MT7629_PIN(73, "WF0_2G_HB1", 73),
+ MT7629_PIN(74, "WF0_2G_HB2", 74),
+ MT7629_PIN(75, "WF0_2G_HB3", 75),
+ MT7629_PIN(76, "WF0_2G_HB4", 76),
+ MT7629_PIN(77, "WF0_2G_HB5", 77),
+ MT7629_PIN(78, "WF0_2G_HB6", 78),
+};
+
+/* List all groups consisting of these pins dedicated to the enablement of
+ * certain hardware block and the corresponding mode for all of the pins.
+ * The hardware probably has multiple combinations of these pinouts.
+ */
+
+/* LED for EPHY */
+static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
+static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
+static int mt7629_ephy_led0_pins[] = { 12, };
+static int mt7629_ephy_led0_funcs[] = { 1, };
+static int mt7629_ephy_led1_pins[] = { 13, };
+static int mt7629_ephy_led1_funcs[] = { 1, };
+static int mt7629_ephy_led2_pins[] = { 14, };
+static int mt7629_ephy_led2_funcs[] = { 1, };
+static int mt7629_ephy_led3_pins[] = { 15, };
+static int mt7629_ephy_led3_funcs[] = { 1, };
+static int mt7629_ephy_led4_pins[] = { 16, };
+static int mt7629_ephy_led4_funcs[] = { 1, };
+static int mt7629_wf2g_led_pins[] = { 17, };
+static int mt7629_wf2g_led_funcs[] = { 1, };
+static int mt7629_wf5g_led_pins[] = { 18, };
+static int mt7629_wf5g_led_funcs[] = { 1, };
+
+/* Watchdog */
+static int mt7629_watchdog_pins[] = { 11, };
+static int mt7629_watchdog_funcs[] = { 1, };
+
+/* LED for GPHY */
+static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
+static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
+static int mt7629_gphy_led1_0_pins[] = { 21, };
+static int mt7629_gphy_led1_0_funcs[] = { 2, };
+static int mt7629_gphy_led2_0_pins[] = { 22, };
+static int mt7629_gphy_led2_0_funcs[] = { 2, };
+static int mt7629_gphy_led3_0_pins[] = { 23, };
+static int mt7629_gphy_led3_0_funcs[] = { 2, };
+static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
+static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
+static int mt7629_gphy_led1_1_pins[] = { 57, };
+static int mt7629_gphy_led1_1_funcs[] = { 1, };
+static int mt7629_gphy_led2_1_pins[] = { 58, };
+static int mt7629_gphy_led2_1_funcs[] = { 1, };
+static int mt7629_gphy_led3_1_pins[] = { 59, };
+static int mt7629_gphy_led3_1_funcs[] = { 1, };
+
+/* I2C */
+static int mt7629_i2c_0_pins[] = { 19, 20, };
+static int mt7629_i2c_0_funcs[] = { 1, 1, };
+static int mt7629_i2c_1_pins[] = { 53, 54, };
+static int mt7629_i2c_1_funcs[] = { 1, 1, };
+
+/* SPI */
+static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
+static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
+static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
+static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
+static int mt7629_spi_wp_pins[] = { 66, };
+static int mt7629_spi_wp_funcs[] = { 1, };
+static int mt7629_spi_hold_pins[] = { 67, };
+static int mt7629_spi_hold_funcs[] = { 1, };
+
+/* UART */
+static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
+static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
+static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
+static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
+static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
+static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
+static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
+static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
+static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
+static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
+static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
+static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
+static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
+static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
+static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
+static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
+static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
+static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
+
+/* MDC/MDIO */
+static int mt7629_mdc_mdio_pins[] = { 49, 50, };
+static int mt7629_mdc_mdio_funcs[] = { 1, 1, };
+
+/* PCIE */
+static int mt7629_pcie_pereset_pins[] = { 51, };
+static int mt7629_pcie_pereset_funcs[] = { 1, };
+static int mt7629_pcie_wake_pins[] = { 55, };
+static int mt7629_pcie_wake_funcs[] = { 1, };
+static int mt7629_pcie_clkreq_pins[] = { 56, };
+static int mt7629_pcie_clkreq_funcs[] = { 1, };
+
+/* PWM */
+static int mt7629_pwm_0_pins[] = { 52, };
+static int mt7629_pwm_0_funcs[] = { 1, };
+static int mt7629_pwm_1_pins[] = { 61, };
+static int mt7629_pwm_1_funcs[] = { 2, };
+
+/* WF 2G */
+static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
+static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
+
+/* WF 5G */
+static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
+static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+
+/* SNFI */
+static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
+static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
+
+/* SPI NOR */
+static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
+static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
+
+static const struct group_desc mt7629_groups[] = {
+ PINCTRL_PIN_GROUP("ephy_leds", mt7629_ephy_leds),
+ PINCTRL_PIN_GROUP("ephy_led0", mt7629_ephy_led0),
+ PINCTRL_PIN_GROUP("ephy_led1", mt7629_ephy_led1),
+ PINCTRL_PIN_GROUP("ephy_led2", mt7629_ephy_led2),
+ PINCTRL_PIN_GROUP("ephy_led3", mt7629_ephy_led3),
+ PINCTRL_PIN_GROUP("ephy_led4", mt7629_ephy_led4),
+ PINCTRL_PIN_GROUP("wf2g_led", mt7629_wf2g_led),
+ PINCTRL_PIN_GROUP("wf5g_led", mt7629_wf5g_led),
+ PINCTRL_PIN_GROUP("watchdog", mt7629_watchdog),
+ PINCTRL_PIN_GROUP("gphy_leds_0", mt7629_gphy_leds_0),
+ PINCTRL_PIN_GROUP("gphy_led1_0", mt7629_gphy_led1_0),
+ PINCTRL_PIN_GROUP("gphy_led2_0", mt7629_gphy_led2_0),
+ PINCTRL_PIN_GROUP("gphy_led3_0", mt7629_gphy_led3_0),
+ PINCTRL_PIN_GROUP("gphy_leds_1", mt7629_gphy_leds_1),
+ PINCTRL_PIN_GROUP("gphy_led1_1", mt7629_gphy_led1_1),
+ PINCTRL_PIN_GROUP("gphy_led2_1", mt7629_gphy_led2_1),
+ PINCTRL_PIN_GROUP("gphy_led3_1", mt7629_gphy_led3_1),
+ PINCTRL_PIN_GROUP("i2c_0", mt7629_i2c_0),
+ PINCTRL_PIN_GROUP("i2c_1", mt7629_i2c_1),
+ PINCTRL_PIN_GROUP("spi_0", mt7629_spi_0),
+ PINCTRL_PIN_GROUP("spi_1", mt7629_spi_1),
+ PINCTRL_PIN_GROUP("spi_wp", mt7629_spi_wp),
+ PINCTRL_PIN_GROUP("spi_hold", mt7629_spi_hold),
+ PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7629_uart1_0_txd_rxd),
+ PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7629_uart1_1_txd_rxd),
+ PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7629_uart2_0_txd_rxd),
+ PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7629_uart2_1_txd_rxd),
+ PINCTRL_PIN_GROUP("uart1_0_cts_rts", mt7629_uart1_0_cts_rts),
+ PINCTRL_PIN_GROUP("uart1_1_cts_rts", mt7629_uart1_1_cts_rts),
+ PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7629_uart2_0_cts_rts),
+ PINCTRL_PIN_GROUP("uart2_1_cts_rts", mt7629_uart2_1_cts_rts),
+ PINCTRL_PIN_GROUP("uart0_txd_rxd", mt7629_uart0_txd_rxd),
+ PINCTRL_PIN_GROUP("mdc_mdio", mt7629_mdc_mdio),
+ PINCTRL_PIN_GROUP("pcie_pereset", mt7629_pcie_pereset),
+ PINCTRL_PIN_GROUP("pcie_wake", mt7629_pcie_wake),
+ PINCTRL_PIN_GROUP("pcie_clkreq", mt7629_pcie_clkreq),
+ PINCTRL_PIN_GROUP("pwm_0", mt7629_pwm_0),
+ PINCTRL_PIN_GROUP("pwm_1", mt7629_pwm_1),
+ PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g),
+ PINCTRL_PIN_GROUP("wf0_2g", mt7629_wf0_2g),
+ PINCTRL_PIN_GROUP("snfi", mt7629_snfi),
+ PINCTRL_PIN_GROUP("spi_nor", mt7629_snor),
+};
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+static const char *mt7629_ethernet_groups[] = { "mdc_mdio", };
+static const char *mt7629_i2c_groups[] = { "i2c_0", "i2c_1", };
+static const char *mt7629_led_groups[] = { "ephy_leds", "ephy_led0",
+ "ephy_led1", "ephy_led2",
+ "ephy_led3", "ephy_led4",
+ "wf2g_led", "wf5g_led",
+ "gphy_leds_0", "gphy_led1_0",
+ "gphy_led2_0", "gphy_led3_0",
+ "gphy_leds_1", "gphy_led1_1",
+ "gphy_led2_1", "gphy_led3_1",};
+static const char *mt7629_pcie_groups[] = { "pcie_pereset", "pcie_wake",
+ "pcie_clkreq", };
+static const char *mt7629_pwm_groups[] = { "pwm_0", "pwm_1", };
+static const char *mt7629_spi_groups[] = { "spi_0", "spi_1", "spi_wp",
+ "spi_hold", };
+static const char *mt7629_uart_groups[] = { "uart1_0_txd_rxd",
+ "uart1_1_txd_rxd",
+ "uart2_0_txd_rxd",
+ "uart2_1_txd_rxd",
+ "uart1_0_cts_rts",
+ "uart1_1_cts_rts",
+ "uart2_0_cts_rts",
+ "uart2_1_cts_rts",
+ "uart0_txd_rxd", };
+static const char *mt7629_wdt_groups[] = { "watchdog", };
+static const char *mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", };
+static const char *mt7629_flash_groups[] = { "snfi", "spi_nor" };
+
+static const struct function_desc mt7629_functions[] = {
+ {"eth", mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)},
+ {"i2c", mt7629_i2c_groups, ARRAY_SIZE(mt7629_i2c_groups)},
+ {"led", mt7629_led_groups, ARRAY_SIZE(mt7629_led_groups)},
+ {"pcie", mt7629_pcie_groups, ARRAY_SIZE(mt7629_pcie_groups)},
+ {"pwm", mt7629_pwm_groups, ARRAY_SIZE(mt7629_pwm_groups)},
+ {"spi", mt7629_spi_groups, ARRAY_SIZE(mt7629_spi_groups)},
+ {"uart", mt7629_uart_groups, ARRAY_SIZE(mt7629_uart_groups)},
+ {"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)},
+ {"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)},
+ {"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)},
+};
+
+static const struct mtk_eint_hw mt7629_eint_hw = {
+ .port_mask = 7,
+ .ports = 7,
+ .ap_num = ARRAY_SIZE(mt7629_pins),
+ .db_cnt = 16,
+};
+
+static struct mtk_pin_soc mt7629_data = {
+ .reg_cal = mt7629_reg_cals,
+ .pins = mt7629_pins,
+ .npins = ARRAY_SIZE(mt7629_pins),
+ .grps = mt7629_groups,
+ .ngrps = ARRAY_SIZE(mt7629_groups),
+ .funcs = mt7629_functions,
+ .nfuncs = ARRAY_SIZE(mt7629_functions),
+ .eint_hw = &mt7629_eint_hw,
+ .gpio_m = 0,
+ .ies_present = true,
+ .base_names = mtk_default_register_base_names,
+ .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
+ .bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
+ .bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
+ .bias_set = mtk_pinconf_bias_set_rev1,
+ .bias_get = mtk_pinconf_bias_get_rev1,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+ .drive_get = mtk_pinconf_drive_get_rev1,
+};
+
+static const struct of_device_id mt7629_pinctrl_of_match[] = {
+ { .compatible = "mediatek,mt7629-pinctrl", },
+ {}
+};
+
+static int mt7629_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_moore_pinctrl_probe(pdev, &mt7629_data);
+}
+
+static struct platform_driver mt7629_pinctrl_driver = {
+ .driver = {
+ .name = "mt7629-pinctrl",
+ .of_match_table = mt7629_pinctrl_of_match,
+ },
+ .probe = mt7629_pinctrl_probe,
+};
+
+static int __init mt7629_pinctrl_init(void)
+{
+ return platform_driver_register(&mt7629_pinctrl_driver);
+}
+arch_initcall(mt7629_pinctrl_init);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h
new file mode 100644
index 0000000..86ab78e
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h
@@ -0,0 +1,2429 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Based on pinctrl-mtk-mt6765.h
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: ZH Chen <[email protected]>
+ *
+ * Copyright (c) 2018 Manivannan Sadhasivam
+ */
+
+#ifndef __PINCTRL_MTK_MT6797_H
+#define __PINCTRL_MTK_MT6797_H
+
+#include "pinctrl-paris.h"
+
+static const struct mtk_pin_desc mtk_pins_mt6797[] = {
+ MTK_PIN(
+ 0, "GPIO0",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO0"),
+ MTK_FUNCTION(1, "CSI0A_L0P_T0A")
+ ),
+ MTK_PIN(
+ 1, "GPIO1",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO1"),
+ MTK_FUNCTION(1, "CSI0A_L0N_T0B")
+ ),
+ MTK_PIN(
+ 2, "GPIO2",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO2"),
+ MTK_FUNCTION(1, "CSI0A_L1P_T0C")
+ ),
+ MTK_PIN(
+ 3, "GPIO3",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO3"),
+ MTK_FUNCTION(1, "CSI0A_L1N_T1A")
+ ),
+ MTK_PIN(
+ 4, "GPIO4",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO4"),
+ MTK_FUNCTION(1, "CSI0A_L2P_T1B")
+ ),
+ MTK_PIN(
+ 5, "GPIO5",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO5"),
+ MTK_FUNCTION(1, "CSI0A_L2N_T1C")
+ ),
+ MTK_PIN(
+ 6, "GPIO6",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO6"),
+ MTK_FUNCTION(1, "CSI0B_L0P_T0A")
+ ),
+ MTK_PIN(
+ 7, "GPIO7",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO7"),
+ MTK_FUNCTION(1, "CSI0B_L0N_T0B")
+ ),
+ MTK_PIN(
+ 8, "GPIO8",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO8"),
+ MTK_FUNCTION(1, "CSI0B_L1P_T0C")
+ ),
+ MTK_PIN(
+ 9, "GPIO9",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO9"),
+ MTK_FUNCTION(1, "CSI0B_L1N_T1A")
+ ),
+ MTK_PIN(
+ 10, "GPIO10",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO10"),
+ MTK_FUNCTION(1, "CSI1A_L0P_T0A")
+ ),
+ MTK_PIN(
+ 11, "GPIO11",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO11"),
+ MTK_FUNCTION(1, "CSI1A_L0N_T0B")
+ ),
+ MTK_PIN(
+ 12, "GPIO12",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO12"),
+ MTK_FUNCTION(1, "CSI1A_L1P_T0C")
+ ),
+ MTK_PIN(
+ 13, "GPIO13",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO13"),
+ MTK_FUNCTION(1, "CSI1A_L1N_T1A")
+ ),
+ MTK_PIN(
+ 14, "GPIO14",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO14"),
+ MTK_FUNCTION(1, "CSI1A_L2P_T1B")
+ ),
+ MTK_PIN(
+ 15, "GPIO15",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO15"),
+ MTK_FUNCTION(1, "CSI1A_L2N_T1C")
+ ),
+ MTK_PIN(
+ 16, "GPIO16",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO16"),
+ MTK_FUNCTION(1, "CSI1B_L0P_T0A")
+ ),
+ MTK_PIN(
+ 17, "GPIO17",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO17"),
+ MTK_FUNCTION(1, "CSI1B_L0N_T0B")
+ ),
+ MTK_PIN(
+ 18, "GPIO18",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO18"),
+ MTK_FUNCTION(1, "CSI1B_L1P_T0C")
+ ),
+ MTK_PIN(
+ 19, "GPIO19",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO19"),
+ MTK_FUNCTION(1, "CSI1B_L1N_T1A")
+ ),
+ MTK_PIN(
+ 20, "GPIO20",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO20"),
+ MTK_FUNCTION(1, "CSI1B_L2P_T1B")
+ ),
+ MTK_PIN(
+ 21, "GPIO21",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO21"),
+ MTK_FUNCTION(1, "CSI1B_L2N_T1C")
+ ),
+ MTK_PIN(
+ 22, "GPIO22",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO22"),
+ MTK_FUNCTION(1, "CSI2_L0P_T0A")
+ ),
+ MTK_PIN(
+ 23, "GPIO23",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO23"),
+ MTK_FUNCTION(1, "CSI2_L0N_T0B")
+ ),
+ MTK_PIN(
+ 24, "GPIO24",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO24"),
+ MTK_FUNCTION(1, "CSI2_L1P_T0C")
+ ),
+ MTK_PIN(
+ 25, "GPIO25",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO25"),
+ MTK_FUNCTION(1, "CSI2_L1N_T1A")
+ ),
+ MTK_PIN(
+ 26, "GPIO26",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO26"),
+ MTK_FUNCTION(1, "CSI2_L2P_T1B")
+ ),
+ MTK_PIN(
+ 27, "GPIO27",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO27"),
+ MTK_FUNCTION(1, "CSI2_L2N_T1C")
+ ),
+ MTK_PIN(
+ 28, "GPIO28",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO28"),
+ MTK_FUNCTION(1, "SPI5_CLK_A"),
+ MTK_FUNCTION(2, "IRTX_OUT"),
+ MTK_FUNCTION(3, "UDI_TDO"),
+ MTK_FUNCTION(4, "SCP_JTAG_TDO"),
+ MTK_FUNCTION(5, "CONN_MCU_TDO"),
+ MTK_FUNCTION(6, "PWM_A"),
+ MTK_FUNCTION(7, "C2K_DM_OTDO")
+ ),
+ MTK_PIN(
+ 29, "GPIO29",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO29"),
+ MTK_FUNCTION(1, "SPI5_MI_A"),
+ MTK_FUNCTION(2, "DAP_SIB1_SWD"),
+ MTK_FUNCTION(3, "UDI_TMS"),
+ MTK_FUNCTION(4, "SCP_JTAG_TMS"),
+ MTK_FUNCTION(5, "CONN_MCU_TMS"),
+ MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"),
+ MTK_FUNCTION(7, "C2K_DM_OTMS")
+ ),
+ MTK_PIN(
+ 30, "GPIO30",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO30"),
+ MTK_FUNCTION(1, "CMMCLK0"),
+ MTK_FUNCTION(7, "MD_CLKM0")
+ ),
+ MTK_PIN(
+ 31, "GPIO31",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO31"),
+ MTK_FUNCTION(1, "CMMCLK1"),
+ MTK_FUNCTION(7, "MD_CLKM1")
+ ),
+ MTK_PIN(
+ 32, "GPIO32",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO32"),
+ MTK_FUNCTION(1, "SPI5_CS_A"),
+ MTK_FUNCTION(2, "DAP_SIB1_SWCK"),
+ MTK_FUNCTION(3, "UDI_TCK_XI"),
+ MTK_FUNCTION(4, "SCP_JTAG_TCK"),
+ MTK_FUNCTION(5, "CONN_MCU_TCK"),
+ MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"),
+ MTK_FUNCTION(7, "C2K_DM_OTCK")
+ ),
+ MTK_PIN(
+ 33, "GPIO33",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO33"),
+ MTK_FUNCTION(1, "SPI5_MO_A"),
+ MTK_FUNCTION(2, "CMFLASH"),
+ MTK_FUNCTION(3, "UDI_TDI"),
+ MTK_FUNCTION(4, "SCP_JTAG_TDI"),
+ MTK_FUNCTION(5, "CONN_MCU_TDI"),
+ MTK_FUNCTION(6, "MD_URXD0"),
+ MTK_FUNCTION(7, "C2K_DM_OTDI")
+ ),
+ MTK_PIN(
+ 34, "GPIO34",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO34"),
+ MTK_FUNCTION(1, "CMFLASH"),
+ MTK_FUNCTION(2, "CLKM0"),
+ MTK_FUNCTION(3, "UDI_NTRST"),
+ MTK_FUNCTION(4, "SCP_JTAG_TRSTN"),
+ MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
+ MTK_FUNCTION(6, "MD_UTXD0"),
+ MTK_FUNCTION(7, "C2K_DM_JTINTP")
+ ),
+ MTK_PIN(
+ 35, "GPIO35",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO35"),
+ MTK_FUNCTION(1, "CMMCLK3"),
+ MTK_FUNCTION(2, "CLKM1"),
+ MTK_FUNCTION(3, "MD_URXD1"),
+ MTK_FUNCTION(4, "PTA_RXD"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
+ MTK_FUNCTION(6, "PWM_B"),
+ MTK_FUNCTION(7, "PCC_PPC_IO")
+ ),
+ MTK_PIN(
+ 36, "GPIO36",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO36"),
+ MTK_FUNCTION(1, "CMMCLK2"),
+ MTK_FUNCTION(2, "CLKM2"),
+ MTK_FUNCTION(3, "MD_UTXD1"),
+ MTK_FUNCTION(4, "PTA_TXD"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
+ MTK_FUNCTION(6, "PWM_C"),
+ MTK_FUNCTION(7, "EXT_FRAME_SYNC")
+ ),
+ MTK_PIN(
+ 37, "GPIO37",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO37"),
+ MTK_FUNCTION(1, "SCL0_0")
+ ),
+ MTK_PIN(
+ 38, "GPIO38",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO38"),
+ MTK_FUNCTION(1, "SDA0_0")
+ ),
+ MTK_PIN(
+ 39, "GPIO39",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO39"),
+ MTK_FUNCTION(1, "DPI_D0"),
+ MTK_FUNCTION(2, "SPI1_CLK_A"),
+ MTK_FUNCTION(3, "PCM0_SYNC"),
+ MTK_FUNCTION(4, "I2S0_LRCK"),
+ MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
+ MTK_FUNCTION(6, "URXD3"),
+ MTK_FUNCTION(7, "C2K_NTRST")
+ ),
+ MTK_PIN(
+ 40, "GPIO40",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO40"),
+ MTK_FUNCTION(1, "DPI_D1"),
+ MTK_FUNCTION(2, "SPI1_MI_A"),
+ MTK_FUNCTION(3, "PCM0_CLK"),
+ MTK_FUNCTION(4, "I2S0_BCK"),
+ MTK_FUNCTION(5, "CONN_MCU_TDO"),
+ MTK_FUNCTION(6, "UTXD3"),
+ MTK_FUNCTION(7, "C2K_TCK")
+ ),
+ MTK_PIN(
+ 41, "GPIO41",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO41"),
+ MTK_FUNCTION(1, "DPI_D2"),
+ MTK_FUNCTION(2, "SPI1_CS_A"),
+ MTK_FUNCTION(3, "PCM0_DO"),
+ MTK_FUNCTION(4, "I2S3_DO"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
+ MTK_FUNCTION(6, "URTS3"),
+ MTK_FUNCTION(7, "C2K_TDI")
+ ),
+ MTK_PIN(
+ 42, "GPIO42",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO42"),
+ MTK_FUNCTION(1, "DPI_D3"),
+ MTK_FUNCTION(2, "SPI1_MO_A"),
+ MTK_FUNCTION(3, "PCM0_DI"),
+ MTK_FUNCTION(4, "I2S0_DI"),
+ MTK_FUNCTION(5, "CONN_MCU_TDI"),
+ MTK_FUNCTION(6, "UCTS3"),
+ MTK_FUNCTION(7, "C2K_TMS")
+ ),
+ MTK_PIN(
+ 43, "GPIO43",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO43"),
+ MTK_FUNCTION(1, "DPI_D4"),
+ MTK_FUNCTION(2, "SPI2_CLK_A"),
+ MTK_FUNCTION(3, "PCM1_SYNC"),
+ MTK_FUNCTION(4, "I2S2_LRCK"),
+ MTK_FUNCTION(5, "CONN_MCU_TMS"),
+ MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"),
+ MTK_FUNCTION(7, "C2K_TDO")
+ ),
+ MTK_PIN(
+ 44, "GPIO44",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO44"),
+ MTK_FUNCTION(1, "DPI_D5"),
+ MTK_FUNCTION(2, "SPI2_MI_A"),
+ MTK_FUNCTION(3, "PCM1_CLK"),
+ MTK_FUNCTION(4, "I2S2_BCK"),
+ MTK_FUNCTION(5, "CONN_MCU_TCK"),
+ MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"),
+ MTK_FUNCTION(7, "C2K_RTCK")
+ ),
+ MTK_PIN(
+ 45, "GPIO45",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO45"),
+ MTK_FUNCTION(1, "DPI_D6"),
+ MTK_FUNCTION(2, "SPI2_CS_A"),
+ MTK_FUNCTION(3, "PCM1_DI"),
+ MTK_FUNCTION(4, "I2S2_DI"),
+ MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
+ MTK_FUNCTION(6, "MD_URXD0")
+ ),
+ MTK_PIN(
+ 46, "GPIO46",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO46"),
+ MTK_FUNCTION(1, "DPI_D7"),
+ MTK_FUNCTION(2, "SPI2_MO_A"),
+ MTK_FUNCTION(3, "PCM1_DO0"),
+ MTK_FUNCTION(4, "I2S1_DO"),
+ MTK_FUNCTION(5, "ANT_SEL0"),
+ MTK_FUNCTION(6, "MD_UTXD0")
+ ),
+ MTK_PIN(
+ 47, "GPIO47",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO47"),
+ MTK_FUNCTION(1, "DPI_D8"),
+ MTK_FUNCTION(2, "CLKM0"),
+ MTK_FUNCTION(3, "PCM1_DO1"),
+ MTK_FUNCTION(4, "I2S0_MCK"),
+ MTK_FUNCTION(5, "ANT_SEL1"),
+ MTK_FUNCTION(6, "PTA_RXD"),
+ MTK_FUNCTION(7, "C2K_URXD0")
+ ),
+ MTK_PIN(
+ 48, "GPIO48",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO48"),
+ MTK_FUNCTION(1, "DPI_D9"),
+ MTK_FUNCTION(2, "CLKM1"),
+ MTK_FUNCTION(3, "CMFLASH"),
+ MTK_FUNCTION(4, "I2S2_MCK"),
+ MTK_FUNCTION(5, "ANT_SEL2"),
+ MTK_FUNCTION(6, "PTA_TXD"),
+ MTK_FUNCTION(7, "C2K_UTXD0")
+ ),
+ MTK_PIN(
+ 49, "GPIO49",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO49"),
+ MTK_FUNCTION(1, "DPI_D10"),
+ MTK_FUNCTION(2, "MD_INT1_C2K_UIM1_HOT_PLUG_IN"),
+ MTK_FUNCTION(3, "PWM_C"),
+ MTK_FUNCTION(4, "IRTX_OUT"),
+ MTK_FUNCTION(5, "ANT_SEL3"),
+ MTK_FUNCTION(6, "MD_URXD1")
+ ),
+ MTK_PIN(
+ 50, "GPIO50",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO50"),
+ MTK_FUNCTION(1, "DPI_D11"),
+ MTK_FUNCTION(2, "MD_INT2"),
+ MTK_FUNCTION(3, "PWM_D"),
+ MTK_FUNCTION(4, "CLKM2"),
+ MTK_FUNCTION(5, "ANT_SEL4"),
+ MTK_FUNCTION(6, "MD_UTXD1")
+ ),
+ MTK_PIN(
+ 51, "GPIO51",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO51"),
+ MTK_FUNCTION(1, "DPI_DE"),
+ MTK_FUNCTION(2, "SPI4_CLK_A"),
+ MTK_FUNCTION(3, "IRTX_OUT"),
+ MTK_FUNCTION(4, "SCL0_1"),
+ MTK_FUNCTION(5, "ANT_SEL5"),
+ MTK_FUNCTION(7, "C2K_UTXD1")
+ ),
+ MTK_PIN(
+ 52, "GPIO52",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO52"),
+ MTK_FUNCTION(1, "DPI_CK"),
+ MTK_FUNCTION(2, "SPI4_MI_A"),
+ MTK_FUNCTION(3, "SPI4_MO_A"),
+ MTK_FUNCTION(4, "SDA0_1"),
+ MTK_FUNCTION(5, "ANT_SEL6"),
+ MTK_FUNCTION(7, "C2K_URXD1")
+ ),
+ MTK_PIN(
+ 53, "GPIO53",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO53"),
+ MTK_FUNCTION(1, "DPI_HSYNC"),
+ MTK_FUNCTION(2, "SPI4_CS_A"),
+ MTK_FUNCTION(3, "CMFLASH"),
+ MTK_FUNCTION(4, "SCL1_1"),
+ MTK_FUNCTION(5, "ANT_SEL7"),
+ MTK_FUNCTION(6, "MD_URXD2"),
+ MTK_FUNCTION(7, "PCC_PPC_IO")
+ ),
+ MTK_PIN(
+ 54, "GPIO54",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO54"),
+ MTK_FUNCTION(1, "DPI_VSYNC"),
+ MTK_FUNCTION(2, "SPI4_MO_A"),
+ MTK_FUNCTION(3, "SPI4_MI_A"),
+ MTK_FUNCTION(4, "SDA1_1"),
+ MTK_FUNCTION(5, "PWM_A"),
+ MTK_FUNCTION(6, "MD_UTXD2"),
+ MTK_FUNCTION(7, "EXT_FRAME_SYNC")
+ ),
+ MTK_PIN(
+ 55, "GPIO55",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO55"),
+ MTK_FUNCTION(1, "SCL1_0")
+ ),
+ MTK_PIN(
+ 56, "GPIO56",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO56"),
+ MTK_FUNCTION(1, "SDA1_0")
+ ),
+ MTK_PIN(
+ 57, "GPIO57",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO57"),
+ MTK_FUNCTION(1, "SPI0_CLK"),
+ MTK_FUNCTION(2, "SCL0_2"),
+ MTK_FUNCTION(3, "PWM_B"),
+ MTK_FUNCTION(4, "UTXD3"),
+ MTK_FUNCTION(5, "PCM0_SYNC")
+ ),
+ MTK_PIN(
+ 58, "GPIO58",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO58"),
+ MTK_FUNCTION(1, "SPI0_MI"),
+ MTK_FUNCTION(2, "SPI0_MO"),
+ MTK_FUNCTION(3, "SDA1_2"),
+ MTK_FUNCTION(4, "URXD3"),
+ MTK_FUNCTION(5, "PCM0_CLK")
+ ),
+ MTK_PIN(
+ 59, "GPIO59",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO59"),
+ MTK_FUNCTION(1, "SPI0_MO"),
+ MTK_FUNCTION(2, "SPI0_MI"),
+ MTK_FUNCTION(3, "PWM_C"),
+ MTK_FUNCTION(4, "URTS3"),
+ MTK_FUNCTION(5, "PCM0_DO")
+ ),
+ MTK_PIN(
+ 60, "GPIO60",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO60"),
+ MTK_FUNCTION(1, "SPI0_CS"),
+ MTK_FUNCTION(2, "SDA0_2"),
+ MTK_FUNCTION(3, "SCL1_2"),
+ MTK_FUNCTION(4, "UCTS3"),
+ MTK_FUNCTION(5, "PCM0_DI")
+ ),
+ MTK_PIN(
+ 61, "GPIO61",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO61"),
+ MTK_FUNCTION(1, "EINT0"),
+ MTK_FUNCTION(2, "IDDIG"),
+ MTK_FUNCTION(3, "SPI4_CLK_B"),
+ MTK_FUNCTION(4, "I2S0_LRCK"),
+ MTK_FUNCTION(5, "PCM0_SYNC"),
+ MTK_FUNCTION(7, "C2K_EINT0")
+ ),
+ MTK_PIN(
+ 62, "GPIO62",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO62"),
+ MTK_FUNCTION(1, "EINT1"),
+ MTK_FUNCTION(2, "USB_DRVVBUS"),
+ MTK_FUNCTION(3, "SPI4_MI_B"),
+ MTK_FUNCTION(4, "I2S0_BCK"),
+ MTK_FUNCTION(5, "PCM0_CLK"),
+ MTK_FUNCTION(7, "C2K_EINT1")
+ ),
+ MTK_PIN(
+ 63, "GPIO63",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO63"),
+ MTK_FUNCTION(1, "EINT2"),
+ MTK_FUNCTION(2, "IRTX_OUT"),
+ MTK_FUNCTION(3, "SPI4_MO_B"),
+ MTK_FUNCTION(4, "I2S0_MCK"),
+ MTK_FUNCTION(5, "PCM0_DI"),
+ MTK_FUNCTION(7, "C2K_DM_EINT0")
+ ),
+ MTK_PIN(
+ 64, "GPIO64",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO64"),
+ MTK_FUNCTION(1, "EINT3"),
+ MTK_FUNCTION(2, "CMFLASH"),
+ MTK_FUNCTION(3, "SPI4_CS_B"),
+ MTK_FUNCTION(4, "I2S0_DI"),
+ MTK_FUNCTION(5, "PCM0_DO"),
+ MTK_FUNCTION(7, "C2K_DM_EINT1")
+ ),
+ MTK_PIN(
+ 65, "GPIO65",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO65"),
+ MTK_FUNCTION(1, "EINT4"),
+ MTK_FUNCTION(2, "CLKM0"),
+ MTK_FUNCTION(3, "SPI5_CLK_B"),
+ MTK_FUNCTION(4, "I2S1_LRCK"),
+ MTK_FUNCTION(5, "PWM_A"),
+ MTK_FUNCTION(7, "C2K_DM_EINT2")
+ ),
+ MTK_PIN(
+ 66, "GPIO66",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO66"),
+ MTK_FUNCTION(1, "EINT5"),
+ MTK_FUNCTION(2, "CLKM1"),
+ MTK_FUNCTION(3, "SPI5_MI_B"),
+ MTK_FUNCTION(4, "I2S1_BCK"),
+ MTK_FUNCTION(5, "PWM_B"),
+ MTK_FUNCTION(7, "C2K_DM_EINT3")
+ ),
+ MTK_PIN(
+ 67, "GPIO67",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO67"),
+ MTK_FUNCTION(1, "EINT6"),
+ MTK_FUNCTION(2, "CLKM2"),
+ MTK_FUNCTION(3, "SPI5_MO_B"),
+ MTK_FUNCTION(4, "I2S1_MCK"),
+ MTK_FUNCTION(5, "PWM_C"),
+ MTK_FUNCTION(7, "DBG_MON_A0")
+ ),
+ MTK_PIN(
+ 68, "GPIO68",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO68"),
+ MTK_FUNCTION(1, "EINT7"),
+ MTK_FUNCTION(2, "CLKM3"),
+ MTK_FUNCTION(3, "SPI5_CS_B"),
+ MTK_FUNCTION(4, "I2S1_DO"),
+ MTK_FUNCTION(5, "PWM_D"),
+ MTK_FUNCTION(7, "DBG_MON_A1")
+ ),
+ MTK_PIN(
+ 69, "GPIO69",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO69"),
+ MTK_FUNCTION(1, "I2S0_LRCK"),
+ MTK_FUNCTION(2, "I2S3_LRCK"),
+ MTK_FUNCTION(3, "I2S1_LRCK"),
+ MTK_FUNCTION(4, "I2S2_LRCK"),
+ MTK_FUNCTION(7, "DBG_MON_A2")
+ ),
+ MTK_PIN(
+ 70, "GPIO70",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO70"),
+ MTK_FUNCTION(1, "I2S0_BCK"),
+ MTK_FUNCTION(2, "I2S3_BCK"),
+ MTK_FUNCTION(3, "I2S1_BCK"),
+ MTK_FUNCTION(4, "I2S2_BCK"),
+ MTK_FUNCTION(7, "DBG_MON_A3")
+ ),
+ MTK_PIN(
+ 71, "GPIO71",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO71"),
+ MTK_FUNCTION(1, "I2S0_MCK"),
+ MTK_FUNCTION(2, "I2S3_MCK"),
+ MTK_FUNCTION(3, "I2S1_MCK"),
+ MTK_FUNCTION(4, "I2S2_MCK"),
+ MTK_FUNCTION(7, "DBG_MON_A4")
+ ),
+ MTK_PIN(
+ 72, "GPIO72",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO72"),
+ MTK_FUNCTION(1, "I2S0_DI"),
+ MTK_FUNCTION(2, "I2S0_DI"),
+ MTK_FUNCTION(3, "I2S2_DI"),
+ MTK_FUNCTION(4, "I2S2_DI"),
+ MTK_FUNCTION(7, "DBG_MON_A5")
+ ),
+ MTK_PIN(
+ 73, "GPIO73",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO73"),
+ MTK_FUNCTION(1, "I2S3_DO"),
+ MTK_FUNCTION(2, "I2S3_DO"),
+ MTK_FUNCTION(3, "I2S1_DO"),
+ MTK_FUNCTION(4, "I2S1_DO"),
+ MTK_FUNCTION(7, "DBG_MON_A6")
+ ),
+ MTK_PIN(
+ 74, "GPIO74",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO74"),
+ MTK_FUNCTION(1, "SCL3_0"),
+ MTK_FUNCTION(7, "AUXIF_CLK1")
+ ),
+ MTK_PIN(
+ 75, "GPIO75",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO75"),
+ MTK_FUNCTION(1, "SDA3_0"),
+ MTK_FUNCTION(7, "AUXIF_ST1")
+ ),
+ MTK_PIN(
+ 76, "GPIO76",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO76"),
+ MTK_FUNCTION(1, "CONN_HRST_B"),
+ MTK_FUNCTION(7, "C2K_DM_EINT0")
+ ),
+ MTK_PIN(
+ 77, "GPIO77",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO77"),
+ MTK_FUNCTION(1, "CONN_TOP_CLK"),
+ MTK_FUNCTION(7, "C2K_DM_EINT1")
+ ),
+ MTK_PIN(
+ 78, "GPIO78",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO78"),
+ MTK_FUNCTION(1, "CONN_TOP_DATA"),
+ MTK_FUNCTION(7, "C2K_DM_EINT2")
+ ),
+ MTK_PIN(
+ 79, "GPIO79",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO79"),
+ MTK_FUNCTION(1, "CONN_WB_PTA"),
+ MTK_FUNCTION(7, "C2K_DM_EINT3")
+ ),
+ MTK_PIN(
+ 80, "GPIO80",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO80"),
+ MTK_FUNCTION(1, "CONN_WF_HB0"),
+ MTK_FUNCTION(7, "C2K_EINT0")
+ ),
+ MTK_PIN(
+ 81, "GPIO81",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO81"),
+ MTK_FUNCTION(1, "CONN_WF_HB1"),
+ MTK_FUNCTION(7, "C2K_EINT1")
+ ),
+ MTK_PIN(
+ 82, "GPIO82",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO82"),
+ MTK_FUNCTION(1, "CONN_WF_HB2"),
+ MTK_FUNCTION(7, "MD_CLKM0")
+ ),
+ MTK_PIN(
+ 83, "GPIO83",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO83"),
+ MTK_FUNCTION(1, "CONN_BT_CLK"),
+ MTK_FUNCTION(7, "MD_CLKM1")
+ ),
+ MTK_PIN(
+ 84, "GPIO84",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO84"),
+ MTK_FUNCTION(1, "CONN_BT_DATA")
+ ),
+ MTK_PIN(
+ 85, "GPIO85",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO85"),
+ MTK_FUNCTION(1, "EINT8"),
+ MTK_FUNCTION(2, "I2S1_LRCK"),
+ MTK_FUNCTION(3, "I2S2_LRCK"),
+ MTK_FUNCTION(4, "URXD1"),
+ MTK_FUNCTION(5, "MD_URXD0"),
+ MTK_FUNCTION(7, "DBG_MON_A7")
+ ),
+ MTK_PIN(
+ 86, "GPIO86",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO86"),
+ MTK_FUNCTION(1, "EINT9"),
+ MTK_FUNCTION(2, "I2S1_BCK"),
+ MTK_FUNCTION(3, "I2S2_BCK"),
+ MTK_FUNCTION(4, "UTXD1"),
+ MTK_FUNCTION(5, "MD_UTXD0"),
+ MTK_FUNCTION(7, "DBG_MON_A8")
+ ),
+ MTK_PIN(
+ 87, "GPIO87",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO87"),
+ MTK_FUNCTION(1, "EINT10"),
+ MTK_FUNCTION(2, "I2S1_MCK"),
+ MTK_FUNCTION(3, "I2S2_MCK"),
+ MTK_FUNCTION(4, "URTS1"),
+ MTK_FUNCTION(5, "MD_URXD1"),
+ MTK_FUNCTION(7, "DBG_MON_A9")
+ ),
+ MTK_PIN(
+ 88, "GPIO88",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO88"),
+ MTK_FUNCTION(1, "EINT11"),
+ MTK_FUNCTION(2, "I2S1_DO"),
+ MTK_FUNCTION(3, "I2S2_DI"),
+ MTK_FUNCTION(4, "UCTS1"),
+ MTK_FUNCTION(5, "MD_UTXD1"),
+ MTK_FUNCTION(7, "DBG_MON_A10")
+ ),
+ MTK_PIN(
+ 89, "GPIO89",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO89"),
+ MTK_FUNCTION(1, "EINT12"),
+ MTK_FUNCTION(2, "IRTX_OUT"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "PCM1_SYNC"),
+ MTK_FUNCTION(5, "URTS0"),
+ MTK_FUNCTION(7, "DBG_MON_A11")
+ ),
+ MTK_PIN(
+ 90, "GPIO90",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO90"),
+ MTK_FUNCTION(1, "EINT13"),
+ MTK_FUNCTION(2, "CMFLASH"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, "PCM1_CLK"),
+ MTK_FUNCTION(5, "UCTS0"),
+ MTK_FUNCTION(7, "C2K_DM_EINT0")
+ ),
+ MTK_PIN(
+ 91, "GPIO91",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO91"),
+ MTK_FUNCTION(1, "EINT14"),
+ MTK_FUNCTION(2, "PWM_A"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, "PCM1_DI"),
+ MTK_FUNCTION(5, "SDA0_3"),
+ MTK_FUNCTION(7, "C2K_DM_EINT1")
+ ),
+ MTK_PIN(
+ 92, "GPIO92",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO92"),
+ MTK_FUNCTION(1, "EINT15"),
+ MTK_FUNCTION(2, "PWM_B"),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(4, "PCM1_DO0"),
+ MTK_FUNCTION(5, "SCL0_3")
+ ),
+ MTK_PIN(
+ 93, "GPIO93",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO93"),
+ MTK_FUNCTION(1, "EINT16"),
+ MTK_FUNCTION(2, "IDDIG"),
+ MTK_FUNCTION(3, "CLKM4"),
+ MTK_FUNCTION(4, "PCM1_DO1"),
+ MTK_FUNCTION(5, "MD_INT2"),
+ MTK_FUNCTION(7, "DROP_ZONE")
+ ),
+ MTK_PIN(
+ 94, "GPIO94",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO94"),
+ MTK_FUNCTION(1, "USB_DRVVBUS"),
+ MTK_FUNCTION(2, "PWM_C"),
+ MTK_FUNCTION(3, "CLKM5")
+ ),
+ MTK_PIN(
+ 95, "GPIO95",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO95"),
+ MTK_FUNCTION(1, "SDA2_0"),
+ MTK_FUNCTION(7, "AUXIF_ST0")
+ ),
+ MTK_PIN(
+ 96, "GPIO96",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO96"),
+ MTK_FUNCTION(1, "SCL2_0"),
+ MTK_FUNCTION(7, "AUXIF_CLK0")
+ ),
+ MTK_PIN(
+ 97, "GPIO97",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO97"),
+ MTK_FUNCTION(1, "URXD0"),
+ MTK_FUNCTION(2, "UTXD0"),
+ MTK_FUNCTION(3, "MD_URXD0"),
+ MTK_FUNCTION(4, "MD_URXD1"),
+ MTK_FUNCTION(5, "MD_URXD2"),
+ MTK_FUNCTION(6, "C2K_URXD0"),
+ MTK_FUNCTION(7, "C2K_URXD1")
+ ),
+ MTK_PIN(
+ 98, "GPIO98",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO98"),
+ MTK_FUNCTION(1, "UTXD0"),
+ MTK_FUNCTION(2, "URXD0"),
+ MTK_FUNCTION(3, "MD_UTXD0"),
+ MTK_FUNCTION(4, "MD_UTXD1"),
+ MTK_FUNCTION(5, "MD_UTXD2"),
+ MTK_FUNCTION(6, "C2K_UTXD0"),
+ MTK_FUNCTION(7, "C2K_UTXD1")
+ ),
+ MTK_PIN(
+ 99, "GPIO99",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO99"),
+ MTK_FUNCTION(1, "RTC32K_CK")
+ ),
+ MTK_PIN(
+ 100, "GPIO100",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO100"),
+ MTK_FUNCTION(1, "SRCLKENAI0")
+ ),
+ MTK_PIN(
+ 101, "GPIO101",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO101"),
+ MTK_FUNCTION(1, "SRCLKENAI1")
+ ),
+ MTK_PIN(
+ 102, "GPIO102",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO102"),
+ MTK_FUNCTION(1, "SRCLKENA0")
+ ),
+ MTK_PIN(
+ 103, "GPIO103",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO103"),
+ MTK_FUNCTION(1, "SRCLKENA1")
+ ),
+ MTK_PIN(
+ 104, "GPIO104",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO104"),
+ MTK_FUNCTION(1, "SYSRSTB")
+ ),
+ MTK_PIN(
+ 105, "GPIO105",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO105"),
+ MTK_FUNCTION(1, "WATCHDOG")
+ ),
+ MTK_PIN(
+ 106, "GPIO106",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO106"),
+ MTK_FUNCTION(1, "KPROW0"),
+ MTK_FUNCTION(2, "CMFLASH"),
+ MTK_FUNCTION(3, "CLKM4"),
+ MTK_FUNCTION(4, "TP_GPIO0_AO"),
+ MTK_FUNCTION(5, "IRTX_OUT")
+ ),
+ MTK_PIN(
+ 107, "GPIO107",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO107"),
+ MTK_FUNCTION(1, "KPROW1"),
+ MTK_FUNCTION(2, "IDDIG"),
+ MTK_FUNCTION(3, "CLKM5"),
+ MTK_FUNCTION(4, "TP_GPIO1_AO"),
+ MTK_FUNCTION(5, "I2S1_BCK"),
+ MTK_FUNCTION(7, "DAP_SIB1_SWD")
+ ),
+ MTK_PIN(
+ 108, "GPIO108",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO108"),
+ MTK_FUNCTION(1, "KPROW2"),
+ MTK_FUNCTION(2, "USB_DRVVBUS"),
+ MTK_FUNCTION(3, "PWM_A"),
+ MTK_FUNCTION(4, "CMFLASH"),
+ MTK_FUNCTION(5, "I2S1_LRCK"),
+ MTK_FUNCTION(7, "DAP_SIB1_SWCK")
+ ),
+ MTK_PIN(
+ 109, "GPIO109",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO109"),
+ MTK_FUNCTION(1, "KPCOL0")
+ ),
+ MTK_PIN(
+ 110, "GPIO110",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO110"),
+ MTK_FUNCTION(1, "KPCOL1"),
+ MTK_FUNCTION(2, "SDA1_3"),
+ MTK_FUNCTION(3, "PWM_B"),
+ MTK_FUNCTION(4, "CLKM0"),
+ MTK_FUNCTION(5, "I2S1_DO"),
+ MTK_FUNCTION(7, "C2K_DM_EINT3")
+ ),
+ MTK_PIN(
+ 111, "GPIO111",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO111"),
+ MTK_FUNCTION(1, "KPCOL2"),
+ MTK_FUNCTION(2, "SCL1_3"),
+ MTK_FUNCTION(3, "PWM_C"),
+ MTK_FUNCTION(4, "DISP_PWM"),
+ MTK_FUNCTION(5, "I2S1_MCK"),
+ MTK_FUNCTION(7, "C2K_DM_EINT2")
+ ),
+ MTK_PIN(
+ 112, "GPIO112",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO112"),
+ MTK_FUNCTION(1, "MD_INT1_C2K_UIM1_HOT_PLUG_IN"),
+ MTK_FUNCTION(7, "C2K_DM_EINT1")
+ ),
+ MTK_PIN(
+ 113, "GPIO113",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO113"),
+ MTK_FUNCTION(1, "MD_INT0_C2K_UIM0_HOT_PLUG_IN"),
+ MTK_FUNCTION(7, "C2K_DM_EINT0")
+ ),
+ MTK_PIN(
+ 114, "GPIO114",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO114"),
+ MTK_FUNCTION(1, "MSDC0_DAT0")
+ ),
+ MTK_PIN(
+ 115, "GPIO115",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO115"),
+ MTK_FUNCTION(1, "MSDC0_DAT1")
+ ),
+ MTK_PIN(
+ 116, "GPIO116",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO116"),
+ MTK_FUNCTION(1, "MSDC0_DAT2")
+ ),
+ MTK_PIN(
+ 117, "GPIO117",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO117"),
+ MTK_FUNCTION(1, "MSDC0_DAT3")
+ ),
+ MTK_PIN(
+ 118, "GPIO118",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO118"),
+ MTK_FUNCTION(1, "MSDC0_DAT4")
+ ),
+ MTK_PIN(
+ 119, "GPIO119",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO119"),
+ MTK_FUNCTION(1, "MSDC0_DAT5")
+ ),
+ MTK_PIN(
+ 120, "GPIO120",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO120"),
+ MTK_FUNCTION(1, "MSDC0_DAT6")
+ ),
+ MTK_PIN(
+ 121, "GPIO121",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO121"),
+ MTK_FUNCTION(1, "MSDC0_DAT7")
+ ),
+ MTK_PIN(
+ 122, "GPIO122",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO122"),
+ MTK_FUNCTION(1, "MSDC0_CMD")
+ ),
+ MTK_PIN(
+ 123, "GPIO123",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO123"),
+ MTK_FUNCTION(1, "MSDC0_CLK")
+ ),
+ MTK_PIN(
+ 124, "GPIO124",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO124"),
+ MTK_FUNCTION(1, "MSDC0_DSL")
+ ),
+ MTK_PIN(
+ 125, "GPIO125",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO125"),
+ MTK_FUNCTION(1, "MSDC0_RSTB")
+ ),
+ MTK_PIN(
+ 126, "GPIO126",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO126"),
+ MTK_FUNCTION(1, "MD1_SIM1_SCLK"),
+ MTK_FUNCTION(2, "MD1_SIM2_SCLK"),
+ MTK_FUNCTION(3, "C2K_UIM0_CLK"),
+ MTK_FUNCTION(4, "C2K_UIM1_CLK")
+ ),
+ MTK_PIN(
+ 127, "GPIO127",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO127"),
+ MTK_FUNCTION(1, "MD1_SIM1_SRST"),
+ MTK_FUNCTION(2, "MD1_SIM2_SRST"),
+ MTK_FUNCTION(3, "C2K_UIM0_RST"),
+ MTK_FUNCTION(4, "C2K_UIM1_RST")
+ ),
+ MTK_PIN(
+ 128, "GPIO128",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO128"),
+ MTK_FUNCTION(1, "MD1_SIM1_SIO"),
+ MTK_FUNCTION(2, "MD1_SIM2_SIO"),
+ MTK_FUNCTION(3, "C2K_UIM0_IO"),
+ MTK_FUNCTION(4, "C2K_UIM1_IO")
+ ),
+ MTK_PIN(
+ 129, "GPIO129",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO129"),
+ MTK_FUNCTION(1, "MSDC1_CMD"),
+ MTK_FUNCTION(2, "CONN_DSP_JMS"),
+ MTK_FUNCTION(3, "LTE_JTAG_TMS"),
+ MTK_FUNCTION(4, "UDI_TMS"),
+ MTK_FUNCTION(5, "C2K_TMS")
+ ),
+ MTK_PIN(
+ 130, "GPIO130",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO130"),
+ MTK_FUNCTION(1, "MSDC1_DAT0"),
+ MTK_FUNCTION(2, "CONN_DSP_JDI"),
+ MTK_FUNCTION(3, "LTE_JTAG_TDI"),
+ MTK_FUNCTION(4, "UDI_TDI"),
+ MTK_FUNCTION(5, "C2K_TDI")
+ ),
+ MTK_PIN(
+ 131, "GPIO131",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO131"),
+ MTK_FUNCTION(1, "MSDC1_DAT1"),
+ MTK_FUNCTION(2, "CONN_DSP_JDO"),
+ MTK_FUNCTION(3, "LTE_JTAG_TDO"),
+ MTK_FUNCTION(4, "UDI_TDO"),
+ MTK_FUNCTION(5, "C2K_TDO")
+ ),
+ MTK_PIN(
+ 132, "GPIO132",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO132"),
+ MTK_FUNCTION(1, "MSDC1_DAT2"),
+ MTK_FUNCTION(5, "C2K_RTCK")
+ ),
+ MTK_PIN(
+ 133, "GPIO133",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO133"),
+ MTK_FUNCTION(1, "MSDC1_DAT3"),
+ MTK_FUNCTION(2, "CONN_DSP_JINTP"),
+ MTK_FUNCTION(3, "LTE_JTAG_TRSTN"),
+ MTK_FUNCTION(4, "UDI_NTRST"),
+ MTK_FUNCTION(5, "C2K_NTRST")
+ ),
+ MTK_PIN(
+ 134, "GPIO134",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO134"),
+ MTK_FUNCTION(1, "MSDC1_CLK"),
+ MTK_FUNCTION(2, "CONN_DSP_JCK"),
+ MTK_FUNCTION(3, "LTE_JTAG_TCK"),
+ MTK_FUNCTION(4, "UDI_TCK_XI"),
+ MTK_FUNCTION(5, "C2K_TCK")
+ ),
+ MTK_PIN(
+ 135, "GPIO135",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO135"),
+ MTK_FUNCTION(1, "TDM_LRCK"),
+ MTK_FUNCTION(2, "I2S0_LRCK"),
+ MTK_FUNCTION(3, "CLKM0"),
+ MTK_FUNCTION(4, "PCM1_SYNC"),
+ MTK_FUNCTION(5, "PWM_A"),
+ MTK_FUNCTION(7, "DBG_MON_A12")
+ ),
+ MTK_PIN(
+ 136, "GPIO136",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO136"),
+ MTK_FUNCTION(1, "TDM_BCK"),
+ MTK_FUNCTION(2, "I2S0_BCK"),
+ MTK_FUNCTION(3, "CLKM1"),
+ MTK_FUNCTION(4, "PCM1_CLK"),
+ MTK_FUNCTION(5, "PWM_B"),
+ MTK_FUNCTION(7, "DBG_MON_A13")
+ ),
+ MTK_PIN(
+ 137, "GPIO137",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO137"),
+ MTK_FUNCTION(1, "TDM_MCK"),
+ MTK_FUNCTION(2, "I2S0_MCK"),
+ MTK_FUNCTION(3, "CLKM2"),
+ MTK_FUNCTION(4, "PCM1_DI"),
+ MTK_FUNCTION(5, "IRTX_OUT"),
+ MTK_FUNCTION(7, "DBG_MON_A14")
+ ),
+ MTK_PIN(
+ 138, "GPIO138",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO138"),
+ MTK_FUNCTION(1, "TDM_DATA0"),
+ MTK_FUNCTION(2, "I2S0_DI"),
+ MTK_FUNCTION(3, "CLKM3"),
+ MTK_FUNCTION(4, "PCM1_DO0"),
+ MTK_FUNCTION(5, "PWM_C"),
+ MTK_FUNCTION(6, "SDA3_1"),
+ MTK_FUNCTION(7, "DBG_MON_A15")
+ ),
+ MTK_PIN(
+ 139, "GPIO139",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO139"),
+ MTK_FUNCTION(1, "TDM_DATA1"),
+ MTK_FUNCTION(2, "I2S3_DO"),
+ MTK_FUNCTION(3, "CLKM4"),
+ MTK_FUNCTION(4, "PCM1_DO1"),
+ MTK_FUNCTION(5, "ANT_SEL2"),
+ MTK_FUNCTION(6, "SCL3_1"),
+ MTK_FUNCTION(7, "DBG_MON_A16")
+ ),
+ MTK_PIN(
+ 140, "GPIO140",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO140"),
+ MTK_FUNCTION(1, "TDM_DATA2"),
+ MTK_FUNCTION(2, "DISP_PWM"),
+ MTK_FUNCTION(3, "CLKM5"),
+ MTK_FUNCTION(4, "SDA1_4"),
+ MTK_FUNCTION(5, "ANT_SEL1"),
+ MTK_FUNCTION(6, "URXD3"),
+ MTK_FUNCTION(7, "DBG_MON_A17")
+ ),
+ MTK_PIN(
+ 141, "GPIO141",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO141"),
+ MTK_FUNCTION(1, "TDM_DATA3"),
+ MTK_FUNCTION(2, "CMFLASH"),
+ MTK_FUNCTION(3, "IRTX_OUT"),
+ MTK_FUNCTION(4, "SCL1_4"),
+ MTK_FUNCTION(5, "ANT_SEL0"),
+ MTK_FUNCTION(6, "UTXD3"),
+ MTK_FUNCTION(7, "DBG_MON_A18")
+ ),
+ MTK_PIN(
+ 142, "GPIO142",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO142"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
+ MTK_FUNCTION(2, "PWRAP_SPI0_MO")
+ ),
+ MTK_PIN(
+ 143, "GPIO143",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO143"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
+ MTK_FUNCTION(2, "PWRAP_SPI0_MI")
+ ),
+ MTK_PIN(
+ 144, "GPIO144",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO144"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_CK")
+ ),
+ MTK_PIN(
+ 145, "GPIO145",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO145"),
+ MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
+ ),
+ MTK_PIN(
+ 146, "GPIO146",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO146"),
+ MTK_FUNCTION(1, "AUD_CLK_MOSI")
+ ),
+ MTK_PIN(
+ 147, "GPIO147",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO147"),
+ MTK_FUNCTION(1, "AUD_DAT_MISO"),
+ MTK_FUNCTION(2, "AUD_DAT_MOSI"),
+ MTK_FUNCTION(3, "VOW_DAT_MISO")
+ ),
+ MTK_PIN(
+ 148, "GPIO148",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO148"),
+ MTK_FUNCTION(1, "AUD_DAT_MOSI"),
+ MTK_FUNCTION(2, "AUD_DAT_MISO")
+ ),
+ MTK_PIN(
+ 149, "GPIO149",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO149"),
+ MTK_FUNCTION(1, "VOW_CLK_MISO")
+ ),
+ MTK_PIN(
+ 150, "GPIO150",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO150"),
+ MTK_FUNCTION(1, "ANC_DAT_MOSI")
+ ),
+ MTK_PIN(
+ 151, "GPIO151",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO151"),
+ MTK_FUNCTION(1, "SCL6_0")
+ ),
+ MTK_PIN(
+ 152, "GPIO152",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO152"),
+ MTK_FUNCTION(1, "SDA6_0")
+ ),
+ MTK_PIN(
+ 153, "GPIO153",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO153"),
+ MTK_FUNCTION(1, "SCL7_0")
+ ),
+ MTK_PIN(
+ 154, "GPIO154",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO154"),
+ MTK_FUNCTION(1, "SDA7_0")
+ ),
+ MTK_PIN(
+ 155, "GPIO155",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO155"),
+ MTK_FUNCTION(1, "MD1_SIM2_SCLK"),
+ MTK_FUNCTION(2, "MD1_SIM1_SCLK"),
+ MTK_FUNCTION(3, "C2K_UIM0_CLK"),
+ MTK_FUNCTION(4, "C2K_UIM1_CLK")
+ ),
+ MTK_PIN(
+ 156, "GPIO156",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO156"),
+ MTK_FUNCTION(1, "MD1_SIM2_SRST"),
+ MTK_FUNCTION(2, "MD1_SIM1_SRST"),
+ MTK_FUNCTION(3, "C2K_UIM0_RST"),
+ MTK_FUNCTION(4, "C2K_UIM1_RST")
+ ),
+ MTK_PIN(
+ 157, "GPIO157",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO157"),
+ MTK_FUNCTION(1, "MD1_SIM2_SIO"),
+ MTK_FUNCTION(2, "MD1_SIM1_SIO"),
+ MTK_FUNCTION(3, "C2K_UIM0_IO"),
+ MTK_FUNCTION(4, "C2K_UIM1_IO")
+ ),
+ MTK_PIN(
+ 158, "GPIO158",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO158"),
+ MTK_FUNCTION(1, "MIPI_TDP0")
+ ),
+ MTK_PIN(
+ 159, "GPIO159",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO159"),
+ MTK_FUNCTION(1, "MIPI_TDN0")
+ ),
+ MTK_PIN(
+ 160, "GPIO160",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO160"),
+ MTK_FUNCTION(1, "MIPI_TDP1")
+ ),
+ MTK_PIN(
+ 161, "GPIO161",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO161"),
+ MTK_FUNCTION(1, "MIPI_TDN1")
+ ),
+ MTK_PIN(
+ 162, "GPIO162",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO162"),
+ MTK_FUNCTION(1, "MIPI_TCP")
+ ),
+ MTK_PIN(
+ 163, "GPIO163",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO163"),
+ MTK_FUNCTION(1, "MIPI_TCN")
+ ),
+ MTK_PIN(
+ 164, "GPIO164",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO164"),
+ MTK_FUNCTION(1, "MIPI_TDP2")
+ ),
+ MTK_PIN(
+ 165, "GPIO165",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO165"),
+ MTK_FUNCTION(1, "MIPI_TDN2")
+ ),
+ MTK_PIN(
+ 166, "GPIO166",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO166"),
+ MTK_FUNCTION(1, "MIPI_TDP3")
+ ),
+ MTK_PIN(
+ 167, "GPIO167",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO167"),
+ MTK_FUNCTION(1, "MIPI_TDN3")
+ ),
+ MTK_PIN(
+ 168, "GPIO168",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO168"),
+ MTK_FUNCTION(1, "MIPI_TDP0_A")
+ ),
+ MTK_PIN(
+ 169, "GPIO169",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO169"),
+ MTK_FUNCTION(1, "MIPI_TDN0_A")
+ ),
+ MTK_PIN(
+ 170, "GPIO170",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO170"),
+ MTK_FUNCTION(1, "MIPI_TDP1_A")
+ ),
+ MTK_PIN(
+ 171, "GPIO171",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO171"),
+ MTK_FUNCTION(1, "MIPI_TDN1_A")
+ ),
+ MTK_PIN(
+ 172, "GPIO172",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO172"),
+ MTK_FUNCTION(1, "MIPI_TCP_A")
+ ),
+ MTK_PIN(
+ 173, "GPIO173",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO173"),
+ MTK_FUNCTION(1, "MIPI_TCN_A")
+ ),
+ MTK_PIN(
+ 174, "GPIO174",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO174"),
+ MTK_FUNCTION(1, "MIPI_TDP2_A")
+ ),
+ MTK_PIN(
+ 175, "GPIO175",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO175"),
+ MTK_FUNCTION(1, "MIPI_TDN2_A")
+ ),
+ MTK_PIN(
+ 176, "GPIO176",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO176"),
+ MTK_FUNCTION(1, "MIPI_TDP3_A")
+ ),
+ MTK_PIN(
+ 177, "GPIO177",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO177"),
+ MTK_FUNCTION(1, "MIPI_TDN3_A")
+ ),
+ MTK_PIN(
+ 178, "GPIO178",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO178"),
+ MTK_FUNCTION(1, "DISP_PWM"),
+ MTK_FUNCTION(2, "PWM_D"),
+ MTK_FUNCTION(3, "CLKM5"),
+ MTK_FUNCTION(7, "DBG_MON_A19")
+ ),
+ MTK_PIN(
+ 179, "GPIO179",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO179"),
+ MTK_FUNCTION(1, "DSI_TE0"),
+ MTK_FUNCTION(7, "DBG_MON_A20")
+ ),
+ MTK_PIN(
+ 180, "GPIO180",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO180"),
+ MTK_FUNCTION(1, "LCM_RST"),
+ MTK_FUNCTION(2, "DSI_TE1"),
+ MTK_FUNCTION(7, "DBG_MON_A21")
+ ),
+ MTK_PIN(
+ 181, "GPIO181",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO181"),
+ MTK_FUNCTION(1, "IDDIG"),
+ MTK_FUNCTION(2, "DSI_TE1"),
+ MTK_FUNCTION(7, "DBG_MON_A22")
+ ),
+ MTK_PIN(
+ 182, "GPIO182",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO182"),
+ MTK_FUNCTION(1, "TESTMODE")
+ ),
+ MTK_PIN(
+ 183, "GPIO183",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO183"),
+ MTK_FUNCTION(1, "RFIC0_BSI_CK"),
+ MTK_FUNCTION(2, "SPM_BSI_CK"),
+ MTK_FUNCTION(7, "DBG_MON_B27")
+ ),
+ MTK_PIN(
+ 184, "GPIO184",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO184"),
+ MTK_FUNCTION(1, "RFIC0_BSI_EN"),
+ MTK_FUNCTION(2, "SPM_BSI_EN"),
+ MTK_FUNCTION(7, "DBG_MON_B28")
+ ),
+ MTK_PIN(
+ 185, "GPIO185",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO185"),
+ MTK_FUNCTION(1, "RFIC0_BSI_D0"),
+ MTK_FUNCTION(2, "SPM_BSI_D0"),
+ MTK_FUNCTION(7, "DBG_MON_B29")
+ ),
+ MTK_PIN(
+ 186, "GPIO186",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO186"),
+ MTK_FUNCTION(1, "RFIC0_BSI_D1"),
+ MTK_FUNCTION(2, "SPM_BSI_D1"),
+ MTK_FUNCTION(7, "DBG_MON_B30")
+ ),
+ MTK_PIN(
+ 187, "GPIO187",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO187"),
+ MTK_FUNCTION(1, "RFIC0_BSI_D2"),
+ MTK_FUNCTION(2, "SPM_BSI_D2"),
+ MTK_FUNCTION(7, "DBG_MON_B31")
+ ),
+ MTK_PIN(
+ 188, "GPIO188",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO188"),
+ MTK_FUNCTION(1, "MIPI0_SCLK"),
+ MTK_FUNCTION(7, "DBG_MON_B32")
+ ),
+ MTK_PIN(
+ 189, "GPIO189",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO189"),
+ MTK_FUNCTION(1, "MIPI0_SDATA")
+ ),
+ MTK_PIN(
+ 190, "GPIO190",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO190"),
+ MTK_FUNCTION(1, "MIPI1_SCLK")
+ ),
+ MTK_PIN(
+ 191, "GPIO191",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO191"),
+ MTK_FUNCTION(1, "MIPI1_SDATA")
+ ),
+ MTK_PIN(
+ 192, "GPIO192",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO192"),
+ MTK_FUNCTION(1, "BPI_BUS4")
+ ),
+ MTK_PIN(
+ 193, "GPIO193",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO193"),
+ MTK_FUNCTION(1, "BPI_BUS5"),
+ MTK_FUNCTION(7, "DBG_MON_B0")
+ ),
+ MTK_PIN(
+ 194, "GPIO194",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO194"),
+ MTK_FUNCTION(1, "BPI_BUS6"),
+ MTK_FUNCTION(7, "DBG_MON_B1")
+ ),
+ MTK_PIN(
+ 195, "GPIO195",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO195"),
+ MTK_FUNCTION(1, "BPI_BUS7"),
+ MTK_FUNCTION(7, "DBG_MON_B2")
+ ),
+ MTK_PIN(
+ 196, "GPIO196",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO196"),
+ MTK_FUNCTION(1, "BPI_BUS8"),
+ MTK_FUNCTION(7, "DBG_MON_B3")
+ ),
+ MTK_PIN(
+ 197, "GPIO197",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO197"),
+ MTK_FUNCTION(1, "BPI_BUS9"),
+ MTK_FUNCTION(7, "DBG_MON_B4")
+ ),
+ MTK_PIN(
+ 198, "GPIO198",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO198"),
+ MTK_FUNCTION(1, "BPI_BUS10"),
+ MTK_FUNCTION(7, "DBG_MON_B5")
+ ),
+ MTK_PIN(
+ 199, "GPIO199",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO199"),
+ MTK_FUNCTION(1, "BPI_BUS11"),
+ MTK_FUNCTION(7, "DBG_MON_B6")
+ ),
+ MTK_PIN(
+ 200, "GPIO200",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO200"),
+ MTK_FUNCTION(1, "BPI_BUS12"),
+ MTK_FUNCTION(7, "DBG_MON_B7")
+ ),
+ MTK_PIN(
+ 201, "GPIO201",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO201"),
+ MTK_FUNCTION(1, "BPI_BUS13"),
+ MTK_FUNCTION(7, "DBG_MON_B8")
+ ),
+ MTK_PIN(
+ 202, "GPIO202",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO202"),
+ MTK_FUNCTION(1, "BPI_BUS14"),
+ MTK_FUNCTION(7, "DBG_MON_B9")
+ ),
+ MTK_PIN(
+ 203, "GPIO203",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO203"),
+ MTK_FUNCTION(1, "BPI_BUS15"),
+ MTK_FUNCTION(7, "DBG_MON_B10")
+ ),
+ MTK_PIN(
+ 204, "GPIO204",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO204"),
+ MTK_FUNCTION(1, "BPI_BUS16"),
+ MTK_FUNCTION(2, "PA_VM0"),
+ MTK_FUNCTION(7, "DBG_MON_B11")
+ ),
+ MTK_PIN(
+ 205, "GPIO205",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO205"),
+ MTK_FUNCTION(1, "BPI_BUS17"),
+ MTK_FUNCTION(2, "PA_VM1"),
+ MTK_FUNCTION(7, "DBG_MON_B12")
+ ),
+ MTK_PIN(
+ 206, "GPIO206",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO206"),
+ MTK_FUNCTION(1, "BPI_BUS18"),
+ MTK_FUNCTION(2, "TX_SWAP0"),
+ MTK_FUNCTION(7, "DBG_MON_B13")
+ ),
+ MTK_PIN(
+ 207, "GPIO207",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO207"),
+ MTK_FUNCTION(1, "BPI_BUS19"),
+ MTK_FUNCTION(2, "TX_SWAP1"),
+ MTK_FUNCTION(7, "DBG_MON_B14")
+ ),
+ MTK_PIN(
+ 208, "GPIO208",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO208"),
+ MTK_FUNCTION(1, "BPI_BUS20"),
+ MTK_FUNCTION(2, "TX_SWAP2"),
+ MTK_FUNCTION(7, "DBG_MON_B15")
+ ),
+ MTK_PIN(
+ 209, "GPIO209",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO209"),
+ MTK_FUNCTION(1, "BPI_BUS21"),
+ MTK_FUNCTION(2, "TX_SWAP3"),
+ MTK_FUNCTION(7, "DBG_MON_B16")
+ ),
+ MTK_PIN(
+ 210, "GPIO210",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO210"),
+ MTK_FUNCTION(1, "BPI_BUS22"),
+ MTK_FUNCTION(2, "DET_BPI0"),
+ MTK_FUNCTION(7, "DBG_MON_B17")
+ ),
+ MTK_PIN(
+ 211, "GPIO211",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO211"),
+ MTK_FUNCTION(1, "BPI_BUS23"),
+ MTK_FUNCTION(2, "DET_BPI1"),
+ MTK_FUNCTION(7, "DBG_MON_B18")
+ ),
+ MTK_PIN(
+ 212, "GPIO212",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO212"),
+ MTK_FUNCTION(1, "BPI_BUS0"),
+ MTK_FUNCTION(7, "DBG_MON_B19")
+ ),
+ MTK_PIN(
+ 213, "GPIO213",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO213"),
+ MTK_FUNCTION(1, "BPI_BUS1"),
+ MTK_FUNCTION(7, "DBG_MON_B20")
+ ),
+ MTK_PIN(
+ 214, "GPIO214",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO214"),
+ MTK_FUNCTION(1, "BPI_BUS2"),
+ MTK_FUNCTION(7, "DBG_MON_B21")
+ ),
+ MTK_PIN(
+ 215, "GPIO215",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO215"),
+ MTK_FUNCTION(1, "BPI_BUS3"),
+ MTK_FUNCTION(7, "DBG_MON_B22")
+ ),
+ MTK_PIN(
+ 216, "GPIO216",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO216"),
+ MTK_FUNCTION(1, "MIPI2_SCLK"),
+ MTK_FUNCTION(7, "DBG_MON_B23")
+ ),
+ MTK_PIN(
+ 217, "GPIO217",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO217"),
+ MTK_FUNCTION(1, "MIPI2_SDATA"),
+ MTK_FUNCTION(7, "DBG_MON_B24")
+ ),
+ MTK_PIN(
+ 218, "GPIO218",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO218"),
+ MTK_FUNCTION(1, "MIPI3_SCLK"),
+ MTK_FUNCTION(7, "DBG_MON_B25")
+ ),
+ MTK_PIN(
+ 219, "GPIO219",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO219"),
+ MTK_FUNCTION(1, "MIPI3_SDATA"),
+ MTK_FUNCTION(7, "DBG_MON_B26")
+ ),
+ MTK_PIN(
+ 220, "GPIO220",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO220"),
+ MTK_FUNCTION(1, "CONN_WF_IP")
+ ),
+ MTK_PIN(
+ 221, "GPIO221",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO221"),
+ MTK_FUNCTION(1, "CONN_WF_IN")
+ ),
+ MTK_PIN(
+ 222, "GPIO222",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO222"),
+ MTK_FUNCTION(1, "CONN_WF_QP")
+ ),
+ MTK_PIN(
+ 223, "GPIO223",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO223"),
+ MTK_FUNCTION(1, "CONN_WF_QN")
+ ),
+ MTK_PIN(
+ 224, "GPIO224",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO224"),
+ MTK_FUNCTION(1, "CONN_BT_IP")
+ ),
+ MTK_PIN(
+ 225, "GPIO225",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO225"),
+ MTK_FUNCTION(1, "CONN_BT_IN")
+ ),
+ MTK_PIN(
+ 226, "GPIO226",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO226"),
+ MTK_FUNCTION(1, "CONN_BT_QP")
+ ),
+ MTK_PIN(
+ 227, "GPIO227",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO227"),
+ MTK_FUNCTION(1, "CONN_BT_QN")
+ ),
+ MTK_PIN(
+ 228, "GPIO228",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO228"),
+ MTK_FUNCTION(1, "CONN_GPS_IP")
+ ),
+ MTK_PIN(
+ 229, "GPIO229",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO229"),
+ MTK_FUNCTION(1, "CONN_GPS_IN")
+ ),
+ MTK_PIN(
+ 230, "GPIO230",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO230"),
+ MTK_FUNCTION(1, "CONN_GPS_QP")
+ ),
+ MTK_PIN(
+ 231, "GPIO231",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO231"),
+ MTK_FUNCTION(1, "CONN_GPS_QN")
+ ),
+ MTK_PIN(
+ 232, "GPIO232",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO232"),
+ MTK_FUNCTION(1, "URXD1"),
+ MTK_FUNCTION(2, "UTXD1"),
+ MTK_FUNCTION(3, "MD_URXD0"),
+ MTK_FUNCTION(4, "MD_URXD1"),
+ MTK_FUNCTION(5, "MD_URXD2"),
+ MTK_FUNCTION(6, "C2K_URXD0"),
+ MTK_FUNCTION(7, "C2K_URXD1")
+ ),
+ MTK_PIN(
+ 233, "GPIO233",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO233"),
+ MTK_FUNCTION(1, "UTXD1"),
+ MTK_FUNCTION(2, "URXD1"),
+ MTK_FUNCTION(3, "MD_UTXD0"),
+ MTK_FUNCTION(4, "MD_UTXD1"),
+ MTK_FUNCTION(5, "MD_UTXD2"),
+ MTK_FUNCTION(6, "C2K_UTXD0"),
+ MTK_FUNCTION(7, "C2K_UTXD1")
+ ),
+ MTK_PIN(
+ 234, "GPIO234",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO234"),
+ MTK_FUNCTION(1, "SPI1_CLK_B"),
+ MTK_FUNCTION(2, "TP_UTXD1_AO"),
+ MTK_FUNCTION(3, "SCL4_1"),
+ MTK_FUNCTION(4, "UTXD0"),
+ MTK_FUNCTION(6, "PWM_A"),
+ MTK_FUNCTION(7, "DBG_MON_A23")
+ ),
+ MTK_PIN(
+ 235, "GPIO235",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO235"),
+ MTK_FUNCTION(1, "SPI1_MI_B"),
+ MTK_FUNCTION(2, "SPI1_MO_B"),
+ MTK_FUNCTION(3, "SDA4_1"),
+ MTK_FUNCTION(4, "URXD0"),
+ MTK_FUNCTION(6, "CLKM0"),
+ MTK_FUNCTION(7, "DBG_MON_A24")
+ ),
+ MTK_PIN(
+ 236, "GPIO236",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO236"),
+ MTK_FUNCTION(1, "SPI1_MO_B"),
+ MTK_FUNCTION(2, "SPI1_MI_B"),
+ MTK_FUNCTION(3, "SCL5_1"),
+ MTK_FUNCTION(4, "URTS0"),
+ MTK_FUNCTION(6, "PWM_B"),
+ MTK_FUNCTION(7, "DBG_MON_A25")
+ ),
+ MTK_PIN(
+ 237, "GPIO237",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO237"),
+ MTK_FUNCTION(1, "SPI1_CS_B"),
+ MTK_FUNCTION(2, "TP_URXD1_AO"),
+ MTK_FUNCTION(3, "SDA5_1"),
+ MTK_FUNCTION(4, "UCTS0"),
+ MTK_FUNCTION(6, "CLKM1"),
+ MTK_FUNCTION(7, "DBG_MON_A26")
+ ),
+ MTK_PIN(
+ 238, "GPIO238",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO238"),
+ MTK_FUNCTION(1, "SDA4_0")
+ ),
+ MTK_PIN(
+ 239, "GPIO239",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO239"),
+ MTK_FUNCTION(1, "SCL4_0")
+ ),
+ MTK_PIN(
+ 240, "GPIO240",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO240"),
+ MTK_FUNCTION(1, "SDA5_0")
+ ),
+ MTK_PIN(
+ 241, "GPIO241",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO241"),
+ MTK_FUNCTION(1, "SCL5_0")
+ ),
+ MTK_PIN(
+ 242, "GPIO242",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO242"),
+ MTK_FUNCTION(1, "SPI2_CLK_B"),
+ MTK_FUNCTION(2, "TP_UTXD2_AO"),
+ MTK_FUNCTION(3, "SCL4_2"),
+ MTK_FUNCTION(4, "UTXD1"),
+ MTK_FUNCTION(5, "URTS3"),
+ MTK_FUNCTION(6, "PWM_C"),
+ MTK_FUNCTION(7, "DBG_MON_A27")
+ ),
+ MTK_PIN(
+ 243, "GPIO243",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO243"),
+ MTK_FUNCTION(1, "SPI2_MI_B"),
+ MTK_FUNCTION(2, "SPI2_MO_B"),
+ MTK_FUNCTION(3, "SDA4_2"),
+ MTK_FUNCTION(4, "URXD1"),
+ MTK_FUNCTION(5, "UCTS3"),
+ MTK_FUNCTION(6, "CLKM2"),
+ MTK_FUNCTION(7, "DBG_MON_A28")
+ ),
+ MTK_PIN(
+ 244, "GPIO244",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO244"),
+ MTK_FUNCTION(1, "SPI2_MO_B"),
+ MTK_FUNCTION(2, "SPI2_MI_B"),
+ MTK_FUNCTION(3, "SCL5_2"),
+ MTK_FUNCTION(4, "URTS1"),
+ MTK_FUNCTION(5, "UTXD3"),
+ MTK_FUNCTION(6, "PWM_D"),
+ MTK_FUNCTION(7, "DBG_MON_A29")
+ ),
+ MTK_PIN(
+ 245, "GPIO245",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO245"),
+ MTK_FUNCTION(1, "SPI2_CS_B"),
+ MTK_FUNCTION(2, "TP_URXD2_AO"),
+ MTK_FUNCTION(3, "SDA5_2"),
+ MTK_FUNCTION(4, "UCTS1"),
+ MTK_FUNCTION(5, "URXD3"),
+ MTK_FUNCTION(6, "CLKM3"),
+ MTK_FUNCTION(7, "DBG_MON_A30")
+ ),
+ MTK_PIN(
+ 246, "GPIO246",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO246"),
+ MTK_FUNCTION(1, "I2S1_LRCK"),
+ MTK_FUNCTION(2, "I2S2_LRCK"),
+ MTK_FUNCTION(3, "I2S0_LRCK"),
+ MTK_FUNCTION(4, "I2S3_LRCK"),
+ MTK_FUNCTION(5, "PCM0_SYNC"),
+ MTK_FUNCTION(6, "SPI5_CLK_C"),
+ MTK_FUNCTION(7, "DBG_MON_A31")
+ ),
+ MTK_PIN(
+ 247, "GPIO247",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO247"),
+ MTK_FUNCTION(1, "I2S1_BCK"),
+ MTK_FUNCTION(2, "I2S2_BCK"),
+ MTK_FUNCTION(3, "I2S0_BCK"),
+ MTK_FUNCTION(4, "I2S3_BCK"),
+ MTK_FUNCTION(5, "PCM0_CLK"),
+ MTK_FUNCTION(6, "SPI5_MI_C"),
+ MTK_FUNCTION(7, "DBG_MON_A32")
+ ),
+ MTK_PIN(
+ 248, "GPIO248",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO248"),
+ MTK_FUNCTION(1, "I2S2_DI"),
+ MTK_FUNCTION(2, "I2S2_DI"),
+ MTK_FUNCTION(3, "I2S0_DI"),
+ MTK_FUNCTION(4, "I2S0_DI"),
+ MTK_FUNCTION(5, "PCM0_DI"),
+ MTK_FUNCTION(6, "SPI5_CS_C")
+ ),
+ MTK_PIN(
+ 249, "GPIO249",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO249"),
+ MTK_FUNCTION(1, "I2S1_DO"),
+ MTK_FUNCTION(2, "I2S1_DO"),
+ MTK_FUNCTION(3, "I2S3_DO"),
+ MTK_FUNCTION(4, "I2S3_DO"),
+ MTK_FUNCTION(5, "PCM0_DO"),
+ MTK_FUNCTION(6, "SPI5_MO_C"),
+ MTK_FUNCTION(7, "TRAP_SRAM_PWR_BYPASS")
+ ),
+ MTK_PIN(
+ 250, "GPIO250",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO250"),
+ MTK_FUNCTION(1, "SPI3_MI"),
+ MTK_FUNCTION(2, "SPI3_MO"),
+ MTK_FUNCTION(3, "IRTX_OUT"),
+ MTK_FUNCTION(6, "TP_URXD1_AO"),
+ MTK_FUNCTION(7, "DROP_ZONE")
+ ),
+ MTK_PIN(
+ 251, "GPIO251",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO251"),
+ MTK_FUNCTION(1, "SPI3_MO"),
+ MTK_FUNCTION(2, "SPI3_MI"),
+ MTK_FUNCTION(3, "CMFLASH"),
+ MTK_FUNCTION(6, "TP_UTXD1_AO"),
+ MTK_FUNCTION(7, "C2K_RTCK")
+ ),
+ MTK_PIN(
+ 252, "GPIO252",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO252"),
+ MTK_FUNCTION(1, "SPI3_CLK"),
+ MTK_FUNCTION(2, "SCL0_4"),
+ MTK_FUNCTION(3, "PWM_D"),
+ MTK_FUNCTION(7, "C2K_TMS")
+ ),
+ MTK_PIN(
+ 253, "GPIO253",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO253"),
+ MTK_FUNCTION(1, "SPI3_CS"),
+ MTK_FUNCTION(2, "SDA0_4"),
+ MTK_FUNCTION(3, "PWM_A"),
+ MTK_FUNCTION(7, "C2K_TCK")
+ ),
+ MTK_PIN(
+ 254, "GPIO254",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO254"),
+ MTK_FUNCTION(1, "I2S1_MCK"),
+ MTK_FUNCTION(2, "I2S2_MCK"),
+ MTK_FUNCTION(3, "I2S0_MCK"),
+ MTK_FUNCTION(4, "I2S3_MCK"),
+ MTK_FUNCTION(5, "CLKM0"),
+ MTK_FUNCTION(7, "C2K_TDI")
+ ),
+ MTK_PIN(
+ 255, "GPIO255",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO255"),
+ MTK_FUNCTION(1, "CLKM1"),
+ MTK_FUNCTION(2, "DISP_PWM"),
+ MTK_FUNCTION(3, "PWM_B"),
+ MTK_FUNCTION(6, "TP_GPIO1_AO"),
+ MTK_FUNCTION(7, "C2K_TDO")
+ ),
+ MTK_PIN(
+ 256, "GPIO256",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO256"),
+ MTK_FUNCTION(1, "CLKM2"),
+ MTK_FUNCTION(2, "IRTX_OUT"),
+ MTK_FUNCTION(3, "PWM_C"),
+ MTK_FUNCTION(6, "TP_GPIO0_AO"),
+ MTK_FUNCTION(7, "C2K_NTRST")
+ ),
+ MTK_PIN(
+ 257, "GPIO257",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO257"),
+ MTK_FUNCTION(1, "IO_JTAG_TMS"),
+ MTK_FUNCTION(2, "LTE_JTAG_TMS"),
+ MTK_FUNCTION(3, "DFD_TMS"),
+ MTK_FUNCTION(4, "DAP_SIB1_SWD"),
+ MTK_FUNCTION(5, "ANC_JTAG_TMS"),
+ MTK_FUNCTION(6, "SCP_JTAG_TMS"),
+ MTK_FUNCTION(7, "C2K_DM_OTMS")
+ ),
+ MTK_PIN(
+ 258, "GPIO258",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO258"),
+ MTK_FUNCTION(1, "IO_JTAG_TCK"),
+ MTK_FUNCTION(2, "LTE_JTAG_TCK"),
+ MTK_FUNCTION(3, "DFD_TCK_XI"),
+ MTK_FUNCTION(4, "DAP_SIB1_SWCK"),
+ MTK_FUNCTION(5, "ANC_JTAG_TCK"),
+ MTK_FUNCTION(6, "SCP_JTAG_TCK"),
+ MTK_FUNCTION(7, "C2K_DM_OTCK")
+ ),
+ MTK_PIN(
+ 259, "GPIO259",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO259"),
+ MTK_FUNCTION(1, "IO_JTAG_TDI"),
+ MTK_FUNCTION(2, "LTE_JTAG_TDI"),
+ MTK_FUNCTION(3, "DFD_TDI"),
+ MTK_FUNCTION(5, "ANC_JTAG_TDI"),
+ MTK_FUNCTION(6, "SCP_JTAG_TDI"),
+ MTK_FUNCTION(7, "C2K_DM_OTDI")
+ ),
+ MTK_PIN(
+ 260, "GPIO260",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO260"),
+ MTK_FUNCTION(1, "IO_JTAG_TDO"),
+ MTK_FUNCTION(2, "LTE_JTAG_TDO"),
+ MTK_FUNCTION(3, "DFD_TDO"),
+ MTK_FUNCTION(5, "ANC_JTAG_TDO"),
+ MTK_FUNCTION(6, "SCP_JTAG_TDO"),
+ MTK_FUNCTION(7, "C2K_DM_OTDO")
+ ),
+ MTK_PIN(
+ 261, "GPIO261",
+ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+ DRV_GRP3,
+ MTK_FUNCTION(0, "GPIO261"),
+ MTK_FUNCTION(2, "LTE_JTAG_TRSTN"),
+ MTK_FUNCTION(3, "DFD_NTRST"),
+ MTK_FUNCTION(5, "ANC_JTAG_TRSTN"),
+ MTK_FUNCTION(6, "SCP_JTAG_TRSTN"),
+ MTK_FUNCTION(7, "C2K_DM_JTINTP")
+ ),
+};
+
+#endif /* __PINCTRL_MTK_MT6797_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c
index d217902..b59e108 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -282,8 +282,8 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
case PIN_CONFIG_DRIVE_STRENGTH:
if (hw->soc->drive_set) {
err = hw->soc->drive_set(hw, desc, arg);
- if (err)
- return err;
+ if (err)
+ return err;
} else {
return -ENOTSUPP;
}
@@ -419,8 +419,8 @@ static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
pins = of_find_property(node, "pinmux", NULL);
if (!pins) {
- dev_err(hw->dev, "missing pins property in node %s .\n",
- node->name);
+ dev_err(hw->dev, "missing pins property in node %pOFn .\n",
+ node);
return -EINVAL;
}
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
index 7dae1d7..3277d17 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
@@ -239,13 +239,9 @@ static const unsigned int eth_link_led_pins[] = { GPIOZ_14 };
static const unsigned int eth_act_led_pins[] = { GPIOZ_15 };
static const unsigned int tsin_a_d0_pins[] = { GPIODV_0 };
-static const unsigned int tsin_a_d0_x_pins[] = { GPIOX_10 };
static const unsigned int tsin_a_clk_pins[] = { GPIODV_8 };
-static const unsigned int tsin_a_clk_x_pins[] = { GPIOX_11 };
static const unsigned int tsin_a_sop_pins[] = { GPIODV_9 };
-static const unsigned int tsin_a_sop_x_pins[] = { GPIOX_8 };
static const unsigned int tsin_a_d_valid_pins[] = { GPIODV_10 };
-static const unsigned int tsin_a_d_valid_x_pins[] = { GPIOX_9 };
static const unsigned int tsin_a_fail_pins[] = { GPIODV_11 };
static const unsigned int tsin_a_dp_pins[] = {
GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, GPIODV_6, GPIODV_7,
@@ -432,10 +428,6 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
GROUP(spi_miso, 5, 2),
GROUP(spi_ss0, 5, 1),
GROUP(spi_sclk, 5, 0),
- GROUP(tsin_a_sop_x, 6, 3),
- GROUP(tsin_a_d_valid_x, 6, 2),
- GROUP(tsin_a_d0_x, 6, 1),
- GROUP(tsin_a_clk_x, 6, 0),
/* Bank Z */
GROUP(eth_mdio, 4, 23),
@@ -698,8 +690,8 @@ static const char * const eth_led_groups[] = {
};
static const char * const tsin_a_groups[] = {
- "tsin_a_clk", "tsin_a_clk_x", "tsin_a_sop", "tsin_a_sop_x",
- "tsin_a_d_valid", "tsin_a_d_valid_x", "tsin_a_d0", "tsin_a_d0_x",
+ "tsin_a_clk", "tsin_a_sop",
+ "tsin_a_d_valid", "tsin_a_d0",
"tsin_a_dp", "tsin_a_fail",
};
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
index 7ad50d9..b455209 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
@@ -1799,19 +1799,12 @@ static int npcm7xx_config_set_one(struct npcm7xx_pinctrl *npcm,
npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
break;
case PIN_CONFIG_INPUT_ENABLE:
- if (arg) {
- iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
- npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_IEM,
- gpio);
- } else
- npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_IEM,
- gpio);
+ iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
+ bank->direction_input(&bank->gc, pin % bank->gc.ngpio);
break;
case PIN_CONFIG_OUTPUT:
- npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_IEM, gpio);
- iowrite32(gpio, arg ? bank->base + NPCM7XX_GP_N_DOS :
- bank->base + NPCM7XX_GP_N_DOC);
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
+ bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 67718b0..2a7d638 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -791,8 +791,7 @@ static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
static int amd_gpio_suspend(struct device *dev)
{
- struct platform_device *pdev = to_platform_device(dev);
- struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
+ struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
int i;
@@ -810,8 +809,7 @@ static int amd_gpio_suspend(struct device *dev)
static int amd_gpio_resume(struct device *dev)
{
- struct platform_device *pdev = to_platform_device(dev);
- struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
+ struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
int i;
diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
index 5a85049..4ee135d 100644
--- a/drivers/pinctrl/pinctrl-at91-pio4.c
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -868,8 +868,7 @@ static struct pinctrl_desc atmel_pinctrl_desc = {
static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
{
- struct platform_device *pdev = to_platform_device(dev);
- struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
+ struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
int i, j;
/*
@@ -897,8 +896,7 @@ static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
static int __maybe_unused atmel_pctrl_resume(struct device *dev)
{
- struct platform_device *pdev = to_platform_device(dev);
- struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
+ struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
int i, j;
for (i = 0; i < atmel_pioctrl->nbanks; i++) {
diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c
index a14bc5e5..06be55d 100644
--- a/drivers/pinctrl/pinctrl-lpc18xx.c
+++ b/drivers/pinctrl/pinctrl-lpc18xx.c
@@ -630,14 +630,8 @@ static const struct pinctrl_pin_desc lpc18xx_pins[] = {
LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA),
};
-/**
- * enum lpc18xx_pin_config_param - possible pin configuration parameters
- * @PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt
- * controller.
- */
-enum lpc18xx_pin_config_param {
- PIN_CONFIG_GPIO_PIN_INT = PIN_CONFIG_END + 1,
-};
+/* PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt controller */
+#define PIN_CONFIG_GPIO_PIN_INT (PIN_CONFIG_END + 1)
static const struct pinconf_generic_params lpc18xx_params[] = {
{"nxp,gpio-pin-interrupt", PIN_CONFIG_GPIO_PIN_INT, 0},
diff --git a/drivers/pinctrl/pinctrl-max77620.c b/drivers/pinctrl/pinctrl-max77620.c
index a7f3706..3d05bc1 100644
--- a/drivers/pinctrl/pinctrl-max77620.c
+++ b/drivers/pinctrl/pinctrl-max77620.c
@@ -34,14 +34,12 @@ enum max77620_pin_ppdrv {
MAX77620_PIN_PP_DRV,
};
-enum max77620_pinconf_param {
- MAX77620_ACTIVE_FPS_SOURCE = PIN_CONFIG_END + 1,
- MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
- MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
- MAX77620_SUSPEND_FPS_SOURCE,
- MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
- MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
-};
+#define MAX77620_ACTIVE_FPS_SOURCE (PIN_CONFIG_END + 1)
+#define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 2)
+#define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 3)
+#define MAX77620_SUSPEND_FPS_SOURCE (PIN_CONFIG_END + 4)
+#define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 5)
+#define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 6)
struct max77620_pin_function {
const char *name;
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 95e4a06..16bf21b 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -307,6 +307,12 @@ struct rockchip_mux_recalced_data {
u8 mask;
};
+enum rockchip_mux_route_location {
+ ROCKCHIP_ROUTE_SAME = 0,
+ ROCKCHIP_ROUTE_PMU,
+ ROCKCHIP_ROUTE_GRF,
+};
+
/**
* struct rockchip_mux_recalced_data: represent a pin iomux data.
* @bank_num: bank number.
@@ -319,6 +325,7 @@ struct rockchip_mux_route_data {
u8 bank_num;
u8 pin;
u8 func;
+ enum rockchip_mux_route_location route_location;
u32 route_offset;
u32 route_val;
};
@@ -815,6 +822,26 @@ static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
},
};
+static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
+ {
+ /* non-iomuxed emmc/flash pins on flash-dqs */
+ .bank_num = 0,
+ .pin = 24,
+ .func = 1,
+ .route_location = ROCKCHIP_ROUTE_GRF,
+ .route_offset = 0xa0,
+ .route_val = BIT(16 + 11),
+ }, {
+ /* non-iomuxed emmc/flash pins on emmc-clk */
+ .bank_num = 0,
+ .pin = 24,
+ .func = 2,
+ .route_location = ROCKCHIP_ROUTE_GRF,
+ .route_offset = 0xa0,
+ .route_val = BIT(16 + 11) | BIT(11),
+ },
+};
+
static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
{
/* pwm0-0 */
@@ -1091,7 +1118,7 @@ static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
};
static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
- int mux, u32 *reg, u32 *value)
+ int mux, u32 *loc, u32 *reg, u32 *value)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
@@ -1108,6 +1135,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
if (i >= ctrl->niomux_routes)
return false;
+ *loc = data->route_location;
*reg = data->route_offset;
*value = data->route_val;
@@ -1210,7 +1238,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
- u32 data, rmask, route_reg, route_val;
+ u32 data, rmask, route_location, route_reg, route_val;
ret = rockchip_verify_mux(bank, pin, mux);
if (ret < 0)
@@ -1247,9 +1275,21 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
if (bank->route_mask & BIT(pin)) {
- if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
- &route_val)) {
- ret = regmap_write(regmap, route_reg, route_val);
+ if (rockchip_get_mux_route(bank, pin, mux, &route_location,
+ &route_reg, &route_val)) {
+ struct regmap *route_regmap = regmap;
+
+ /* handle special locations */
+ switch (route_location) {
+ case ROCKCHIP_ROUTE_PMU:
+ route_regmap = info->regmap_pmu;
+ break;
+ case ROCKCHIP_ROUTE_GRF:
+ route_regmap = info->regmap_base;
+ break;
+ }
+
+ ret = regmap_write(route_regmap, route_reg, route_val);
if (ret)
return ret;
}
@@ -3606,6 +3646,8 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
.label = "RK3188-GPIO",
.type = RK3188,
.grf_mux_offset = 0x60,
+ .iomux_routes = rk3188_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
.pull_calc_reg = rk3188_calc_pull_reg_and_bit,
};
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
index a0daf27..90fd37e 100644
--- a/drivers/pinctrl/pinctrl-zynq.c
+++ b/drivers/pinctrl/pinctrl-zynq.c
@@ -971,15 +971,12 @@ enum zynq_io_standards {
zynq_iostd_max
};
-/**
- * enum zynq_pin_config_param - possible pin configuration parameters
- * @PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to
+/*
+ * PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to
* this parameter (on a custom format) tells the driver which alternative
* IO standard to use.
*/
-enum zynq_pin_config_param {
- PIN_CONFIG_IOSTANDARD = PIN_CONFIG_END + 1,
-};
+#define PIN_CONFIG_IOSTANDARD (PIN_CONFIG_END + 1)
static const struct pinconf_generic_params zynq_dt_params[] = {
{"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18},
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 7c7d083..87cbebe 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -1072,6 +1072,25 @@ static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
}
}
+static int msm_pinctrl_suspend(struct device *dev)
+{
+ struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
+
+ return pinctrl_force_sleep(pctrl->pctrl);
+}
+
+static int msm_pinctrl_resume(struct device *dev)
+{
+ struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
+
+ return pinctrl_force_default(pctrl->pctrl);
+}
+
+SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
+ msm_pinctrl_resume);
+
+EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
+
int msm_pinctrl_probe(struct platform_device *pdev,
const struct msm_pinctrl_soc_data *soc_data)
{
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index 29172fd..c12048e 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -123,6 +123,8 @@ struct msm_pinctrl_soc_data {
unsigned int ntiles;
};
+extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
+
int msm_pinctrl_probe(struct platform_device *pdev,
const struct msm_pinctrl_soc_data *soc_data);
int msm_pinctrl_remove(struct platform_device *pdev);
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a88..c97f20f 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -1300,6 +1300,7 @@ static const struct of_device_id sdm845_pinctrl_of_match[] = {
static struct platform_driver sdm845_pinctrl_driver = {
.driver = {
.name = "sdm845-pinctrl",
+ .pm = &msm_pinctrl_dev_pm_ops,
.of_match_table = sdm845_pinctrl_of_match,
},
.probe = sdm845_pinctrl_probe,
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
index a29efbe..4c1ff9a 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
@@ -1028,10 +1028,23 @@ static int pmic_gpio_probe(struct platform_device *pdev)
return ret;
}
- ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
- if (ret) {
- dev_err(dev, "failed to add pin range\n");
- goto err_range;
+ /*
+ * For DeviceTree-supported systems, the gpio core checks the
+ * pinctrl's device node for the "gpio-ranges" property.
+ * If it is present, it takes care of adding the pin ranges
+ * for the driver. In this case the driver can skip ahead.
+ *
+ * In order to remain compatible with older, existing DeviceTree
+ * files which don't set the "gpio-ranges" property or systems that
+ * utilize ACPI the driver has to call gpiochip_add_pin_range().
+ */
+ if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
+ ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
+ npins);
+ if (ret) {
+ dev_err(dev, "failed to add pin range\n");
+ goto err_range;
+ }
}
return 0;
diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
index 6b30bef..ded7d76 100644
--- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
@@ -762,12 +762,23 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev)
return ret;
}
- ret = gpiochip_add_pin_range(&pctrl->chip,
- dev_name(pctrl->dev),
- 0, 0, pctrl->chip.ngpio);
- if (ret) {
- dev_err(pctrl->dev, "failed to add pin range\n");
- goto unregister_gpiochip;
+ /*
+ * For DeviceTree-supported systems, the gpio core checks the
+ * pinctrl's device node for the "gpio-ranges" property.
+ * If it is present, it takes care of adding the pin ranges
+ * for the driver. In this case the driver can skip ahead.
+ *
+ * In order to remain compatible with older, existing DeviceTree
+ * files which don't set the "gpio-ranges" property or systems that
+ * utilize ACPI the driver has to call gpiochip_add_pin_range().
+ */
+ if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
+ ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
+ 0, 0, pctrl->chip.ngpio);
+ if (ret) {
+ dev_err(pctrl->dev, "failed to add pin range\n");
+ goto unregister_gpiochip;
+ }
}
platform_set_drvdata(pdev, pctrl);
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c
index 4537b54..7d9a44bd 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.c
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.c
@@ -159,10 +159,8 @@ struct sprd_pinctrl {
struct sprd_pinctrl_soc_info *info;
};
-enum sprd_pinconf_params {
- SPRD_PIN_CONFIG_CONTROL = PIN_CONFIG_END + 1,
- SPRD_PIN_CONFIG_SLEEP_MODE = PIN_CONFIG_END + 2,
-};
+#define SPRD_PIN_CONFIG_CONTROL (PIN_CONFIG_END + 1)
+#define SPRD_PIN_CONFIG_SLEEP_MODE (PIN_CONFIG_END + 2)
static int sprd_pinctrl_get_id_by_name(struct sprd_pinctrl *sprd_pctl,
const char *name)
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 0fbfcc9..813eccb 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -8,6 +8,7 @@
*/
#include <linux/clk.h>
#include <linux/gpio/driver.h>
+#include <linux/hwspinlock.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/mfd/syscon.h>
@@ -51,6 +52,8 @@
#define gpio_range_to_bank(chip) \
container_of(chip, struct stm32_gpio_bank, range)
+#define HWSPINLOCK_TIMEOUT 5 /* msec */
+
static const char * const stm32_gpio_functions[] = {
"gpio", "af0", "af1",
"af2", "af3", "af4",
@@ -91,6 +94,7 @@ struct stm32_pinctrl {
struct irq_domain *domain;
struct regmap *regmap;
struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
+ struct hwspinlock *hwlock;
};
static inline int stm32_gpio_pin(int gpio)
@@ -576,14 +580,24 @@ static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
int pin, u32 mode, u32 alt)
{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
u32 val;
int alt_shift = (pin % 8) * 4;
int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
unsigned long flags;
+ int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
+ if (pctl->hwlock)
+ err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
+
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+
val = readl_relaxed(bank->base + alt_offset);
val &= ~GENMASK(alt_shift + 3, alt_shift);
val |= (alt << alt_shift);
@@ -594,6 +608,10 @@ static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
val |= mode << (pin * 2);
writel_relaxed(val, bank->base + STM32_GPIO_MODER);
+ if (pctl->hwlock)
+ hwspin_unlock(pctl->hwlock);
+
+unlock:
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
@@ -683,17 +701,31 @@ static const struct pinmux_ops stm32_pmx_ops = {
static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
unsigned offset, u32 drive)
{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
+ int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
+ if (pctl->hwlock)
+ err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
+
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+
val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
val &= ~BIT(offset);
val |= drive << offset;
writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
+ if (pctl->hwlock)
+ hwspin_unlock(pctl->hwlock);
+
+unlock:
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
@@ -719,17 +751,31 @@ static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
unsigned offset, u32 speed)
{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
+ int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
+ if (pctl->hwlock)
+ err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
+
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+
val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
val &= ~GENMASK(offset * 2 + 1, offset * 2);
val |= speed << (offset * 2);
writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
+ if (pctl->hwlock)
+ hwspin_unlock(pctl->hwlock);
+
+unlock:
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
@@ -755,17 +801,31 @@ static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
unsigned offset, u32 bias)
{
+ struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
unsigned long flags;
u32 val;
+ int err = 0;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
+ if (pctl->hwlock)
+ err = hwspin_lock_timeout(pctl->hwlock, HWSPINLOCK_TIMEOUT);
+
+ if (err) {
+ dev_err(pctl->dev, "Can't get hwspinlock\n");
+ goto unlock;
+ }
+
val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
val &= ~GENMASK(offset * 2 + 1, offset * 2);
val |= bias << (offset * 2);
writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
+ if (pctl->hwlock)
+ hwspin_unlock(pctl->hwlock);
+
+unlock:
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
@@ -1140,7 +1200,7 @@ int stm32_pctl_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct stm32_pinctrl *pctl;
struct pinctrl_pin_desc *pins;
- int i, ret, banks = 0;
+ int i, ret, hwlock_id, banks = 0;
if (!np)
return -EINVAL;
@@ -1160,6 +1220,15 @@ int stm32_pctl_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pctl);
+ /* hwspinlock is optional */
+ hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
+ if (hwlock_id < 0) {
+ if (hwlock_id == -EPROBE_DEFER)
+ return hwlock_id;
+ } else {
+ pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
+ }
+
pctl->dev = dev;
pctl->match_data = match->data;
ret = stm32_pctrl_build_state(pdev);
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 95282cd..a731fc9 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -6,6 +6,10 @@
select GENERIC_PINCONF
select GPIOLIB
+config PINCTRL_SUNIV_F1C100S
+ def_bool MACH_SUNIV
+ select PINCTRL_SUNXI
+
config PINCTRL_SUN4I_A10
def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
select PINCTRL_SUNXI
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index adb8443..fafcdae 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -3,6 +3,7 @@
obj-y += pinctrl-sunxi.o
# SoC Drivers
+obj-$(CONFIG_PINCTRL_SUNIV_F1C100S) += pinctrl-suniv-f1c100s.o
obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
obj-$(CONFIG_PINCTRL_SUN5I) += pinctrl-sun5i.o
obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c b/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c
new file mode 100644
index 0000000..2801ca7
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c
@@ -0,0 +1,416 @@
+/*
+ * Allwinner new F-series F1C100s SoC (suniv) pinctrl driver.
+ *
+ * Copyright (C) 2018 Icenowy Zheng
+ *
+ * Icenowy Zheng <[email protected]>
+ *
+ * Copyright (C) 2014 Jackie Hwang
+ *
+ * Jackie Hwang <[email protected]>
+ *
+ * Copyright (C) 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <[email protected]>
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ *
+ * Maxime Ripard <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+static const struct sunxi_desc_pin suniv_f1c100s_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "rtp"), /* X1 */
+ SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
+ SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
+ SUNXI_FUNCTION(0x6, "spi1")), /* CS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "rtp"), /* X2 */
+ SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
+ SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
+ SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "rtp"), /* Y1 */
+ SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
+ SUNXI_FUNCTION(0x4, "i2s"), /* IN */
+ SUNXI_FUNCTION(0x5, "uart1"), /* RX */
+ SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "rtp"), /* Y2 */
+ SUNXI_FUNCTION(0x3, "ir0"), /* RX */
+ SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
+ SUNXI_FUNCTION(0x5, "uart1"), /* TX */
+ SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "dram"), /* DQS0 */
+ SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
+ SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
+ SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
+ SUNXI_FUNCTION(0x6, "spi1")), /* CS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "dram"), /* DQS1 */
+ SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
+ SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
+ SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
+ SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "dram"), /* CKE */
+ SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
+ SUNXI_FUNCTION(0x4, "i2s"), /* IN */
+ SUNXI_FUNCTION(0x5, "uart1"), /* RX */
+ SUNXI_FUNCTION(0x6, "spi1")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "dram"), /* DDR_REF_D */
+ SUNXI_FUNCTION(0x3, "ir0"), /* RX */
+ SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
+ SUNXI_FUNCTION(0x5, "uart1"), /* TX */
+ SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi0"), /* CS */
+ SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
+ SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
+ SUNXI_FUNCTION(0x3, "uart0")), /* TX */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D2 */
+ SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
+ SUNXI_FUNCTION(0x4, "rsb"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D3 */
+ SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D4*/
+ SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D5 */
+ SUNXI_FUNCTION(0x3, "uart1"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D6 */
+ SUNXI_FUNCTION(0x3, "uart1"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D7 */
+ SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D10 */
+ SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D11 */
+ SUNXI_FUNCTION(0x3, "i2s"), /* MCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D12 */
+ SUNXI_FUNCTION(0x3, "i2s"), /* BCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D13 */
+ SUNXI_FUNCTION(0x3, "i2s"), /* LRCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D14 */
+ SUNXI_FUNCTION(0x3, "i2s"), /* IN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D15 */
+ SUNXI_FUNCTION(0x3, "i2s"), /* OUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D18 */
+ SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
+ SUNXI_FUNCTION(0x4, "rsb"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D19 */
+ SUNXI_FUNCTION(0x3, "uart2"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D20 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D21 */
+ SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
+ SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D22 */
+ SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
+ SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D23 */
+ SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* CLK */
+ SUNXI_FUNCTION(0x3, "spi0"), /* CS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* DE */
+ SUNXI_FUNCTION(0x3, "spi0"), /* MOSI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* HYSNC */
+ SUNXI_FUNCTION(0x3, "spi0"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */
+ SUNXI_FUNCTION(0x3, "spi0"), /* MISO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
+ SUNXI_FUNCTION(0x3, "lcd"), /* D0 */
+ SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
+ SUNXI_FUNCTION(0x5, "uart0"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
+ SUNXI_FUNCTION(0x3, "lcd"), /* D1 */
+ SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
+ SUNXI_FUNCTION(0x5, "uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
+ SUNXI_FUNCTION(0x3, "lcd"), /* D8 */
+ SUNXI_FUNCTION(0x4, "clk"), /* OUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D0 */
+ SUNXI_FUNCTION(0x3, "lcd"), /* D9 */
+ SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
+ SUNXI_FUNCTION(0x5, "rsb"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D1 */
+ SUNXI_FUNCTION(0x3, "lcd"), /* D16 */
+ SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
+ SUNXI_FUNCTION(0x5, "rsb"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D2 */
+ SUNXI_FUNCTION(0x3, "lcd"), /* D17 */
+ SUNXI_FUNCTION(0x4, "i2s"), /* IN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D3 */
+ SUNXI_FUNCTION(0x3, "pwm1"), /* PWM1 */
+ SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
+ SUNXI_FUNCTION(0x5, "spdif"), /* OUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D4 */
+ SUNXI_FUNCTION(0x3, "uart2"), /* TX */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D5 */
+ SUNXI_FUNCTION(0x3, "uart2"), /* RX */
+ SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D6 */
+ SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* D7 */
+ SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
+ SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "clk0"), /* OUT */
+ SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
+ SUNXI_FUNCTION(0x4, "ir"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
+ SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
+ SUNXI_FUNCTION(0x4, "pwm0"), /* PWM0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
+
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* MS */
+ SUNXI_FUNCTION(0x4, "ir0"), /* MS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "dgb0"), /* DI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* CK */
+ SUNXI_FUNCTION(0x4, "pwm1"), /* PWM1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
+};
+
+static const struct sunxi_pinctrl_desc suniv_f1c100s_pinctrl_data = {
+ .pins = suniv_f1c100s_pins,
+ .npins = ARRAY_SIZE(suniv_f1c100s_pins),
+ .irq_banks = 3,
+};
+
+static int suniv_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ &suniv_f1c100s_pinctrl_data);
+}
+
+static const struct of_device_id suniv_f1c100s_pinctrl_match[] = {
+ { .compatible = "allwinner,suniv-f1c100s-pinctrl", },
+ {}
+};
+
+static struct platform_driver suniv_f1c100s_pinctrl_driver = {
+ .probe = suniv_pinctrl_probe,
+ .driver = {
+ .name = "suniv-f1c100s-pinctrl",
+ .of_match_table = suniv_f1c100s_pinctrl_match,
+ },
+};
+builtin_platform_driver(suniv_f1c100s_pinctrl_driver);
diff --git a/include/dt-bindings/pinctrl/bcm2835.h b/include/dt-bindings/pinctrl/bcm2835.h
index e4e4fdf..b5b2654 100644
--- a/include/dt-bindings/pinctrl/bcm2835.h
+++ b/include/dt-bindings/pinctrl/bcm2835.h
@@ -1,14 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Header providing constants for bcm2835 pinctrl bindings.
*
* Copyright (C) 2015 Stefan Wahren <[email protected]>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DT_BINDINGS_PINCTRL_BCM2835_H__
diff --git a/include/dt-bindings/pinctrl/mt6797-pinfunc.h b/include/dt-bindings/pinctrl/mt6797-pinfunc.h
new file mode 100644
index 0000000..e981336
--- /dev/null
+++ b/include/dt-bindings/pinctrl/mt6797-pinfunc.h
@@ -0,0 +1,1368 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DTS_MT6797_PINFUNC_H
+#define __DTS_MT6797_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT6797_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT6797_GPIO0__FUNC_CSI0A_L0P_T0A (MTK_PIN_NO(0) | 1)
+
+#define MT6797_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT6797_GPIO1__FUNC_CSI0A_L0N_T0B (MTK_PIN_NO(1) | 1)
+
+#define MT6797_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT6797_GPIO2__FUNC_CSI0A_L1P_T0C (MTK_PIN_NO(2) | 1)
+
+#define MT6797_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT6797_GPIO3__FUNC_CSI0A_L1N_T1A (MTK_PIN_NO(3) | 1)
+
+#define MT6797_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT6797_GPIO4__FUNC_CSI0A_L2P_T1B (MTK_PIN_NO(4) | 1)
+
+#define MT6797_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT6797_GPIO5__FUNC_CSI0A_L2N_T1C (MTK_PIN_NO(5) | 1)
+
+#define MT6797_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT6797_GPIO6__FUNC_CSI0B_L0P_T0A (MTK_PIN_NO(6) | 1)
+
+#define MT6797_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT6797_GPIO7__FUNC_CSI0B_L0N_T0B (MTK_PIN_NO(7) | 1)
+
+#define MT6797_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT6797_GPIO8__FUNC_CSI0B_L1P_T0C (MTK_PIN_NO(8) | 1)
+
+#define MT6797_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT6797_GPIO9__FUNC_CSI0B_L1N_T1A (MTK_PIN_NO(9) | 1)
+
+#define MT6797_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT6797_GPIO10__FUNC_CSI1A_L0P_T0A (MTK_PIN_NO(10) | 1)
+
+#define MT6797_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT6797_GPIO11__FUNC_CSI1A_L0N_T0B (MTK_PIN_NO(11) | 1)
+
+#define MT6797_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT6797_GPIO12__FUNC_CSI1A_L1P_T0C (MTK_PIN_NO(12) | 1)
+
+#define MT6797_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT6797_GPIO13__FUNC_CSI1A_L1N_T1A (MTK_PIN_NO(13) | 1)
+
+#define MT6797_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT6797_GPIO14__FUNC_CSI1A_L2P_T1B (MTK_PIN_NO(14) | 1)
+
+#define MT6797_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT6797_GPIO15__FUNC_CSI1A_L2N_T1C (MTK_PIN_NO(15) | 1)
+
+#define MT6797_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define MT6797_GPIO16__FUNC_CSI1B_L0P_T0A (MTK_PIN_NO(16) | 1)
+
+#define MT6797_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define MT6797_GPIO17__FUNC_CSI1B_L0N_T0B (MTK_PIN_NO(17) | 1)
+
+#define MT6797_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT6797_GPIO18__FUNC_CSI1B_L1P_T0C (MTK_PIN_NO(18) | 1)
+
+#define MT6797_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT6797_GPIO19__FUNC_CSI1B_L1N_T1A (MTK_PIN_NO(19) | 1)
+
+#define MT6797_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT6797_GPIO20__FUNC_CSI1B_L2P_T1B (MTK_PIN_NO(20) | 1)
+
+#define MT6797_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT6797_GPIO21__FUNC_CSI1B_L2N_T1C (MTK_PIN_NO(21) | 1)
+
+#define MT6797_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT6797_GPIO22__FUNC_CSI2_L0P_T0A (MTK_PIN_NO(22) | 1)
+
+#define MT6797_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT6797_GPIO23__FUNC_CSI2_L0N_T0B (MTK_PIN_NO(23) | 1)
+
+#define MT6797_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT6797_GPIO24__FUNC_CSI2_L1P_T0C (MTK_PIN_NO(24) | 1)
+
+#define MT6797_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT6797_GPIO25__FUNC_CSI2_L1N_T1A (MTK_PIN_NO(25) | 1)
+
+#define MT6797_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT6797_GPIO26__FUNC_CSI2_L2P_T1B (MTK_PIN_NO(26) | 1)
+
+#define MT6797_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT6797_GPIO27__FUNC_CSI2_L2N_T1C (MTK_PIN_NO(27) | 1)
+
+#define MT6797_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT6797_GPIO28__FUNC_SPI5_CLK_A (MTK_PIN_NO(28) | 1)
+#define MT6797_GPIO28__FUNC_IRTX_OUT (MTK_PIN_NO(28) | 2)
+#define MT6797_GPIO28__FUNC_UDI_TDO (MTK_PIN_NO(28) | 3)
+#define MT6797_GPIO28__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(28) | 4)
+#define MT6797_GPIO28__FUNC_CONN_MCU_TDO (MTK_PIN_NO(28) | 5)
+#define MT6797_GPIO28__FUNC_PWM_A (MTK_PIN_NO(28) | 6)
+#define MT6797_GPIO28__FUNC_C2K_DM_OTDO (MTK_PIN_NO(28) | 7)
+
+#define MT6797_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT6797_GPIO29__FUNC_SPI5_MI_A (MTK_PIN_NO(29) | 1)
+#define MT6797_GPIO29__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(29) | 2)
+#define MT6797_GPIO29__FUNC_UDI_TMS (MTK_PIN_NO(29) | 3)
+#define MT6797_GPIO29__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(29) | 4)
+#define MT6797_GPIO29__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 5)
+#define MT6797_GPIO29__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(29) | 6)
+#define MT6797_GPIO29__FUNC_C2K_DM_OTMS (MTK_PIN_NO(29) | 7)
+
+#define MT6797_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define MT6797_GPIO30__FUNC_CMMCLK0 (MTK_PIN_NO(30) | 1)
+#define MT6797_GPIO30__FUNC_MD_CLKM0 (MTK_PIN_NO(30) | 7)
+
+#define MT6797_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define MT6797_GPIO31__FUNC_CMMCLK1 (MTK_PIN_NO(31) | 1)
+#define MT6797_GPIO31__FUNC_MD_CLKM1 (MTK_PIN_NO(31) | 7)
+
+#define MT6797_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define MT6797_GPIO32__FUNC_SPI5_CS_A (MTK_PIN_NO(32) | 1)
+#define MT6797_GPIO32__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(32) | 2)
+#define MT6797_GPIO32__FUNC_UDI_TCK_XI (MTK_PIN_NO(32) | 3)
+#define MT6797_GPIO32__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(32) | 4)
+#define MT6797_GPIO32__FUNC_CONN_MCU_TCK (MTK_PIN_NO(32) | 5)
+#define MT6797_GPIO32__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(32) | 6)
+#define MT6797_GPIO32__FUNC_C2K_DM_OTCK (MTK_PIN_NO(32) | 7)
+
+#define MT6797_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT6797_GPIO33__FUNC_SPI5_MO_A (MTK_PIN_NO(33) | 1)
+#define MT6797_GPIO33__FUNC_CMFLASH (MTK_PIN_NO(33) | 2)
+#define MT6797_GPIO33__FUNC_UDI_TDI (MTK_PIN_NO(33) | 3)
+#define MT6797_GPIO33__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(33) | 4)
+#define MT6797_GPIO33__FUNC_CONN_MCU_TDI (MTK_PIN_NO(33) | 5)
+#define MT6797_GPIO33__FUNC_MD_URXD0 (MTK_PIN_NO(33) | 6)
+#define MT6797_GPIO33__FUNC_C2K_DM_OTDI (MTK_PIN_NO(33) | 7)
+
+#define MT6797_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT6797_GPIO34__FUNC_CMFLASH (MTK_PIN_NO(34) | 1)
+#define MT6797_GPIO34__FUNC_CLKM0 (MTK_PIN_NO(34) | 2)
+#define MT6797_GPIO34__FUNC_UDI_NTRST (MTK_PIN_NO(34) | 3)
+#define MT6797_GPIO34__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(34) | 4)
+#define MT6797_GPIO34__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5)
+#define MT6797_GPIO34__FUNC_MD_UTXD0 (MTK_PIN_NO(34) | 6)
+#define MT6797_GPIO34__FUNC_C2K_DM_JTINTP (MTK_PIN_NO(34) | 7)
+
+#define MT6797_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT6797_GPIO35__FUNC_CMMCLK3 (MTK_PIN_NO(35) | 1)
+#define MT6797_GPIO35__FUNC_CLKM1 (MTK_PIN_NO(35) | 2)
+#define MT6797_GPIO35__FUNC_MD_URXD1 (MTK_PIN_NO(35) | 3)
+#define MT6797_GPIO35__FUNC_PTA_RXD (MTK_PIN_NO(35) | 4)
+#define MT6797_GPIO35__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(35) | 5)
+#define MT6797_GPIO35__FUNC_PWM_B (MTK_PIN_NO(35) | 6)
+#define MT6797_GPIO35__FUNC_PCC_PPC_IO (MTK_PIN_NO(35) | 7)
+
+#define MT6797_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT6797_GPIO36__FUNC_CMMCLK2 (MTK_PIN_NO(36) | 1)
+#define MT6797_GPIO36__FUNC_CLKM2 (MTK_PIN_NO(36) | 2)
+#define MT6797_GPIO36__FUNC_MD_UTXD1 (MTK_PIN_NO(36) | 3)
+#define MT6797_GPIO36__FUNC_PTA_TXD (MTK_PIN_NO(36) | 4)
+#define MT6797_GPIO36__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(36) | 5)
+#define MT6797_GPIO36__FUNC_PWM_C (MTK_PIN_NO(36) | 6)
+#define MT6797_GPIO36__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(36) | 7)
+
+#define MT6797_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT6797_GPIO37__FUNC_SCL0_0 (MTK_PIN_NO(37) | 1)
+
+#define MT6797_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define MT6797_GPIO38__FUNC_SDA0_0 (MTK_PIN_NO(38) | 1)
+
+#define MT6797_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT6797_GPIO39__FUNC_DPI_D0 (MTK_PIN_NO(39) | 1)
+#define MT6797_GPIO39__FUNC_SPI1_CLK_A (MTK_PIN_NO(39) | 2)
+#define MT6797_GPIO39__FUNC_PCM0_SYNC (MTK_PIN_NO(39) | 3)
+#define MT6797_GPIO39__FUNC_I2S0_LRCK (MTK_PIN_NO(39) | 4)
+#define MT6797_GPIO39__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(39) | 5)
+#define MT6797_GPIO39__FUNC_URXD3 (MTK_PIN_NO(39) | 6)
+#define MT6797_GPIO39__FUNC_C2K_NTRST (MTK_PIN_NO(39) | 7)
+
+#define MT6797_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT6797_GPIO40__FUNC_DPI_D1 (MTK_PIN_NO(40) | 1)
+#define MT6797_GPIO40__FUNC_SPI1_MI_A (MTK_PIN_NO(40) | 2)
+#define MT6797_GPIO40__FUNC_PCM0_CLK (MTK_PIN_NO(40) | 3)
+#define MT6797_GPIO40__FUNC_I2S0_BCK (MTK_PIN_NO(40) | 4)
+#define MT6797_GPIO40__FUNC_CONN_MCU_TDO (MTK_PIN_NO(40) | 5)
+#define MT6797_GPIO40__FUNC_UTXD3 (MTK_PIN_NO(40) | 6)
+#define MT6797_GPIO40__FUNC_C2K_TCK (MTK_PIN_NO(40) | 7)
+
+#define MT6797_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT6797_GPIO41__FUNC_DPI_D2 (MTK_PIN_NO(41) | 1)
+#define MT6797_GPIO41__FUNC_SPI1_CS_A (MTK_PIN_NO(41) | 2)
+#define MT6797_GPIO41__FUNC_PCM0_DO (MTK_PIN_NO(41) | 3)
+#define MT6797_GPIO41__FUNC_I2S3_DO (MTK_PIN_NO(41) | 4)
+#define MT6797_GPIO41__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(41) | 5)
+#define MT6797_GPIO41__FUNC_URTS3 (MTK_PIN_NO(41) | 6)
+#define MT6797_GPIO41__FUNC_C2K_TDI (MTK_PIN_NO(41) | 7)
+
+#define MT6797_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT6797_GPIO42__FUNC_DPI_D3 (MTK_PIN_NO(42) | 1)
+#define MT6797_GPIO42__FUNC_SPI1_MO_A (MTK_PIN_NO(42) | 2)
+#define MT6797_GPIO42__FUNC_PCM0_DI (MTK_PIN_NO(42) | 3)
+#define MT6797_GPIO42__FUNC_I2S0_DI (MTK_PIN_NO(42) | 4)
+#define MT6797_GPIO42__FUNC_CONN_MCU_TDI (MTK_PIN_NO(42) | 5)
+#define MT6797_GPIO42__FUNC_UCTS3 (MTK_PIN_NO(42) | 6)
+#define MT6797_GPIO42__FUNC_C2K_TMS (MTK_PIN_NO(42) | 7)
+
+#define MT6797_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT6797_GPIO43__FUNC_DPI_D4 (MTK_PIN_NO(43) | 1)
+#define MT6797_GPIO43__FUNC_SPI2_CLK_A (MTK_PIN_NO(43) | 2)
+#define MT6797_GPIO43__FUNC_PCM1_SYNC (MTK_PIN_NO(43) | 3)
+#define MT6797_GPIO43__FUNC_I2S2_LRCK (MTK_PIN_NO(43) | 4)
+#define MT6797_GPIO43__FUNC_CONN_MCU_TMS (MTK_PIN_NO(43) | 5)
+#define MT6797_GPIO43__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(43) | 6)
+#define MT6797_GPIO43__FUNC_C2K_TDO (MTK_PIN_NO(43) | 7)
+
+#define MT6797_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT6797_GPIO44__FUNC_DPI_D5 (MTK_PIN_NO(44) | 1)
+#define MT6797_GPIO44__FUNC_SPI2_MI_A (MTK_PIN_NO(44) | 2)
+#define MT6797_GPIO44__FUNC_PCM1_CLK (MTK_PIN_NO(44) | 3)
+#define MT6797_GPIO44__FUNC_I2S2_BCK (MTK_PIN_NO(44) | 4)
+#define MT6797_GPIO44__FUNC_CONN_MCU_TCK (MTK_PIN_NO(44) | 5)
+#define MT6797_GPIO44__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(44) | 6)
+#define MT6797_GPIO44__FUNC_C2K_RTCK (MTK_PIN_NO(44) | 7)
+
+#define MT6797_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT6797_GPIO45__FUNC_DPI_D6 (MTK_PIN_NO(45) | 1)
+#define MT6797_GPIO45__FUNC_SPI2_CS_A (MTK_PIN_NO(45) | 2)
+#define MT6797_GPIO45__FUNC_PCM1_DI (MTK_PIN_NO(45) | 3)
+#define MT6797_GPIO45__FUNC_I2S2_DI (MTK_PIN_NO(45) | 4)
+#define MT6797_GPIO45__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(45) | 5)
+#define MT6797_GPIO45__FUNC_MD_URXD0 (MTK_PIN_NO(45) | 6)
+
+#define MT6797_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT6797_GPIO46__FUNC_DPI_D7 (MTK_PIN_NO(46) | 1)
+#define MT6797_GPIO46__FUNC_SPI2_MO_A (MTK_PIN_NO(46) | 2)
+#define MT6797_GPIO46__FUNC_PCM1_DO0 (MTK_PIN_NO(46) | 3)
+#define MT6797_GPIO46__FUNC_I2S1_DO (MTK_PIN_NO(46) | 4)
+#define MT6797_GPIO46__FUNC_ANT_SEL0 (MTK_PIN_NO(46) | 5)
+#define MT6797_GPIO46__FUNC_MD_UTXD0 (MTK_PIN_NO(46) | 6)
+
+#define MT6797_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT6797_GPIO47__FUNC_DPI_D8 (MTK_PIN_NO(47) | 1)
+#define MT6797_GPIO47__FUNC_CLKM0 (MTK_PIN_NO(47) | 2)
+#define MT6797_GPIO47__FUNC_PCM1_DO1 (MTK_PIN_NO(47) | 3)
+#define MT6797_GPIO47__FUNC_I2S0_MCK (MTK_PIN_NO(47) | 4)
+#define MT6797_GPIO47__FUNC_ANT_SEL1 (MTK_PIN_NO(47) | 5)
+#define MT6797_GPIO47__FUNC_PTA_RXD (MTK_PIN_NO(47) | 6)
+#define MT6797_GPIO47__FUNC_C2K_URXD0 (MTK_PIN_NO(47) | 7)
+
+#define MT6797_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT6797_GPIO48__FUNC_DPI_D9 (MTK_PIN_NO(48) | 1)
+#define MT6797_GPIO48__FUNC_CLKM1 (MTK_PIN_NO(48) | 2)
+#define MT6797_GPIO48__FUNC_CMFLASH (MTK_PIN_NO(48) | 3)
+#define MT6797_GPIO48__FUNC_I2S2_MCK (MTK_PIN_NO(48) | 4)
+#define MT6797_GPIO48__FUNC_ANT_SEL2 (MTK_PIN_NO(48) | 5)
+#define MT6797_GPIO48__FUNC_PTA_TXD (MTK_PIN_NO(48) | 6)
+#define MT6797_GPIO48__FUNC_C2K_UTXD0 (MTK_PIN_NO(48) | 7)
+
+#define MT6797_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT6797_GPIO49__FUNC_DPI_D10 (MTK_PIN_NO(49) | 1)
+#define MT6797_GPIO49__FUNC_MD_INT1_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(49) | 2)
+#define MT6797_GPIO49__FUNC_PWM_C (MTK_PIN_NO(49) | 3)
+#define MT6797_GPIO49__FUNC_IRTX_OUT (MTK_PIN_NO(49) | 4)
+#define MT6797_GPIO49__FUNC_ANT_SEL3 (MTK_PIN_NO(49) | 5)
+#define MT6797_GPIO49__FUNC_MD_URXD1 (MTK_PIN_NO(49) | 6)
+
+#define MT6797_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define MT6797_GPIO50__FUNC_DPI_D11 (MTK_PIN_NO(50) | 1)
+#define MT6797_GPIO50__FUNC_MD_INT2 (MTK_PIN_NO(50) | 2)
+#define MT6797_GPIO50__FUNC_PWM_D (MTK_PIN_NO(50) | 3)
+#define MT6797_GPIO50__FUNC_CLKM2 (MTK_PIN_NO(50) | 4)
+#define MT6797_GPIO50__FUNC_ANT_SEL4 (MTK_PIN_NO(50) | 5)
+#define MT6797_GPIO50__FUNC_MD_UTXD1 (MTK_PIN_NO(50) | 6)
+
+#define MT6797_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define MT6797_GPIO51__FUNC_DPI_DE (MTK_PIN_NO(51) | 1)
+#define MT6797_GPIO51__FUNC_SPI4_CLK_A (MTK_PIN_NO(51) | 2)
+#define MT6797_GPIO51__FUNC_IRTX_OUT (MTK_PIN_NO(51) | 3)
+#define MT6797_GPIO51__FUNC_SCL0_1 (MTK_PIN_NO(51) | 4)
+#define MT6797_GPIO51__FUNC_ANT_SEL5 (MTK_PIN_NO(51) | 5)
+#define MT6797_GPIO51__FUNC_C2K_UTXD1 (MTK_PIN_NO(51) | 7)
+
+#define MT6797_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define MT6797_GPIO52__FUNC_DPI_CK (MTK_PIN_NO(52) | 1)
+#define MT6797_GPIO52__FUNC_SPI4_MI_A (MTK_PIN_NO(52) | 2)
+#define MT6797_GPIO52__FUNC_SPI4_MO_A (MTK_PIN_NO(52) | 3)
+#define MT6797_GPIO52__FUNC_SDA0_1 (MTK_PIN_NO(52) | 4)
+#define MT6797_GPIO52__FUNC_ANT_SEL6 (MTK_PIN_NO(52) | 5)
+#define MT6797_GPIO52__FUNC_C2K_URXD1 (MTK_PIN_NO(52) | 7)
+
+#define MT6797_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT6797_GPIO53__FUNC_DPI_HSYNC (MTK_PIN_NO(53) | 1)
+#define MT6797_GPIO53__FUNC_SPI4_CS_A (MTK_PIN_NO(53) | 2)
+#define MT6797_GPIO53__FUNC_CMFLASH (MTK_PIN_NO(53) | 3)
+#define MT6797_GPIO53__FUNC_SCL1_1 (MTK_PIN_NO(53) | 4)
+#define MT6797_GPIO53__FUNC_ANT_SEL7 (MTK_PIN_NO(53) | 5)
+#define MT6797_GPIO53__FUNC_MD_URXD2 (MTK_PIN_NO(53) | 6)
+#define MT6797_GPIO53__FUNC_PCC_PPC_IO (MTK_PIN_NO(53) | 7)
+
+#define MT6797_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT6797_GPIO54__FUNC_DPI_VSYNC (MTK_PIN_NO(54) | 1)
+#define MT6797_GPIO54__FUNC_SPI4_MO_A (MTK_PIN_NO(54) | 2)
+#define MT6797_GPIO54__FUNC_SPI4_MI_A (MTK_PIN_NO(54) | 3)
+#define MT6797_GPIO54__FUNC_SDA1_1 (MTK_PIN_NO(54) | 4)
+#define MT6797_GPIO54__FUNC_PWM_A (MTK_PIN_NO(54) | 5)
+#define MT6797_GPIO54__FUNC_MD_UTXD2 (MTK_PIN_NO(54) | 6)
+#define MT6797_GPIO54__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(54) | 7)
+
+#define MT6797_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT6797_GPIO55__FUNC_SCL1_0 (MTK_PIN_NO(55) | 1)
+
+#define MT6797_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT6797_GPIO56__FUNC_SDA1_0 (MTK_PIN_NO(56) | 1)
+
+#define MT6797_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define MT6797_GPIO57__FUNC_SPI0_CLK (MTK_PIN_NO(57) | 1)
+#define MT6797_GPIO57__FUNC_SCL0_2 (MTK_PIN_NO(57) | 2)
+#define MT6797_GPIO57__FUNC_PWM_B (MTK_PIN_NO(57) | 3)
+#define MT6797_GPIO57__FUNC_UTXD3 (MTK_PIN_NO(57) | 4)
+#define MT6797_GPIO57__FUNC_PCM0_SYNC (MTK_PIN_NO(57) | 5)
+
+#define MT6797_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define MT6797_GPIO58__FUNC_SPI0_MI (MTK_PIN_NO(58) | 1)
+#define MT6797_GPIO58__FUNC_SPI0_MO (MTK_PIN_NO(58) | 2)
+#define MT6797_GPIO58__FUNC_SDA1_2 (MTK_PIN_NO(58) | 3)
+#define MT6797_GPIO58__FUNC_URXD3 (MTK_PIN_NO(58) | 4)
+#define MT6797_GPIO58__FUNC_PCM0_CLK (MTK_PIN_NO(58) | 5)
+
+#define MT6797_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define MT6797_GPIO59__FUNC_SPI0_MO (MTK_PIN_NO(59) | 1)
+#define MT6797_GPIO59__FUNC_SPI0_MI (MTK_PIN_NO(59) | 2)
+#define MT6797_GPIO59__FUNC_PWM_C (MTK_PIN_NO(59) | 3)
+#define MT6797_GPIO59__FUNC_URTS3 (MTK_PIN_NO(59) | 4)
+#define MT6797_GPIO59__FUNC_PCM0_DO (MTK_PIN_NO(59) | 5)
+
+#define MT6797_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define MT6797_GPIO60__FUNC_SPI0_CS (MTK_PIN_NO(60) | 1)
+#define MT6797_GPIO60__FUNC_SDA0_2 (MTK_PIN_NO(60) | 2)
+#define MT6797_GPIO60__FUNC_SCL1_2 (MTK_PIN_NO(60) | 3)
+#define MT6797_GPIO60__FUNC_UCTS3 (MTK_PIN_NO(60) | 4)
+#define MT6797_GPIO60__FUNC_PCM0_DI (MTK_PIN_NO(60) | 5)
+
+#define MT6797_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define MT6797_GPIO61__FUNC_EINT0 (MTK_PIN_NO(61) | 1)
+#define MT6797_GPIO61__FUNC_IDDIG (MTK_PIN_NO(61) | 2)
+#define MT6797_GPIO61__FUNC_SPI4_CLK_B (MTK_PIN_NO(61) | 3)
+#define MT6797_GPIO61__FUNC_I2S0_LRCK (MTK_PIN_NO(61) | 4)
+#define MT6797_GPIO61__FUNC_PCM0_SYNC (MTK_PIN_NO(61) | 5)
+#define MT6797_GPIO61__FUNC_C2K_EINT0 (MTK_PIN_NO(61) | 7)
+
+#define MT6797_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define MT6797_GPIO62__FUNC_EINT1 (MTK_PIN_NO(62) | 1)
+#define MT6797_GPIO62__FUNC_USB_DRVVBUS (MTK_PIN_NO(62) | 2)
+#define MT6797_GPIO62__FUNC_SPI4_MI_B (MTK_PIN_NO(62) | 3)
+#define MT6797_GPIO62__FUNC_I2S0_BCK (MTK_PIN_NO(62) | 4)
+#define MT6797_GPIO62__FUNC_PCM0_CLK (MTK_PIN_NO(62) | 5)
+#define MT6797_GPIO62__FUNC_C2K_EINT1 (MTK_PIN_NO(62) | 7)
+
+#define MT6797_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define MT6797_GPIO63__FUNC_EINT2 (MTK_PIN_NO(63) | 1)
+#define MT6797_GPIO63__FUNC_IRTX_OUT (MTK_PIN_NO(63) | 2)
+#define MT6797_GPIO63__FUNC_SPI4_MO_B (MTK_PIN_NO(63) | 3)
+#define MT6797_GPIO63__FUNC_I2S0_MCK (MTK_PIN_NO(63) | 4)
+#define MT6797_GPIO63__FUNC_PCM0_DI (MTK_PIN_NO(63) | 5)
+#define MT6797_GPIO63__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(63) | 7)
+
+#define MT6797_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define MT6797_GPIO64__FUNC_EINT3 (MTK_PIN_NO(64) | 1)
+#define MT6797_GPIO64__FUNC_CMFLASH (MTK_PIN_NO(64) | 2)
+#define MT6797_GPIO64__FUNC_SPI4_CS_B (MTK_PIN_NO(64) | 3)
+#define MT6797_GPIO64__FUNC_I2S0_DI (MTK_PIN_NO(64) | 4)
+#define MT6797_GPIO64__FUNC_PCM0_DO (MTK_PIN_NO(64) | 5)
+#define MT6797_GPIO64__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(64) | 7)
+
+#define MT6797_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define MT6797_GPIO65__FUNC_EINT4 (MTK_PIN_NO(65) | 1)
+#define MT6797_GPIO65__FUNC_CLKM0 (MTK_PIN_NO(65) | 2)
+#define MT6797_GPIO65__FUNC_SPI5_CLK_B (MTK_PIN_NO(65) | 3)
+#define MT6797_GPIO65__FUNC_I2S1_LRCK (MTK_PIN_NO(65) | 4)
+#define MT6797_GPIO65__FUNC_PWM_A (MTK_PIN_NO(65) | 5)
+#define MT6797_GPIO65__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(65) | 7)
+
+#define MT6797_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define MT6797_GPIO66__FUNC_EINT5 (MTK_PIN_NO(66) | 1)
+#define MT6797_GPIO66__FUNC_CLKM1 (MTK_PIN_NO(66) | 2)
+#define MT6797_GPIO66__FUNC_SPI5_MI_B (MTK_PIN_NO(66) | 3)
+#define MT6797_GPIO66__FUNC_I2S1_BCK (MTK_PIN_NO(66) | 4)
+#define MT6797_GPIO66__FUNC_PWM_B (MTK_PIN_NO(66) | 5)
+#define MT6797_GPIO66__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(66) | 7)
+
+#define MT6797_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define MT6797_GPIO67__FUNC_EINT6 (MTK_PIN_NO(67) | 1)
+#define MT6797_GPIO67__FUNC_CLKM2 (MTK_PIN_NO(67) | 2)
+#define MT6797_GPIO67__FUNC_SPI5_MO_B (MTK_PIN_NO(67) | 3)
+#define MT6797_GPIO67__FUNC_I2S1_MCK (MTK_PIN_NO(67) | 4)
+#define MT6797_GPIO67__FUNC_PWM_C (MTK_PIN_NO(67) | 5)
+#define MT6797_GPIO67__FUNC_DBG_MON_A0 (MTK_PIN_NO(67) | 7)
+
+#define MT6797_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define MT6797_GPIO68__FUNC_EINT7 (MTK_PIN_NO(68) | 1)
+#define MT6797_GPIO68__FUNC_CLKM3 (MTK_PIN_NO(68) | 2)
+#define MT6797_GPIO68__FUNC_SPI5_CS_B (MTK_PIN_NO(68) | 3)
+#define MT6797_GPIO68__FUNC_I2S1_DO (MTK_PIN_NO(68) | 4)
+#define MT6797_GPIO68__FUNC_PWM_D (MTK_PIN_NO(68) | 5)
+#define MT6797_GPIO68__FUNC_DBG_MON_A1 (MTK_PIN_NO(68) | 7)
+
+#define MT6797_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define MT6797_GPIO69__FUNC_I2S0_LRCK (MTK_PIN_NO(69) | 1)
+#define MT6797_GPIO69__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 2)
+#define MT6797_GPIO69__FUNC_I2S1_LRCK (MTK_PIN_NO(69) | 3)
+#define MT6797_GPIO69__FUNC_I2S2_LRCK (MTK_PIN_NO(69) | 4)
+#define MT6797_GPIO69__FUNC_DBG_MON_A2 (MTK_PIN_NO(69) | 7)
+
+#define MT6797_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define MT6797_GPIO70__FUNC_I2S0_BCK (MTK_PIN_NO(70) | 1)
+#define MT6797_GPIO70__FUNC_I2S3_BCK (MTK_PIN_NO(70) | 2)
+#define MT6797_GPIO70__FUNC_I2S1_BCK (MTK_PIN_NO(70) | 3)
+#define MT6797_GPIO70__FUNC_I2S2_BCK (MTK_PIN_NO(70) | 4)
+#define MT6797_GPIO70__FUNC_DBG_MON_A3 (MTK_PIN_NO(70) | 7)
+
+#define MT6797_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define MT6797_GPIO71__FUNC_I2S0_MCK (MTK_PIN_NO(71) | 1)
+#define MT6797_GPIO71__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 2)
+#define MT6797_GPIO71__FUNC_I2S1_MCK (MTK_PIN_NO(71) | 3)
+#define MT6797_GPIO71__FUNC_I2S2_MCK (MTK_PIN_NO(71) | 4)
+#define MT6797_GPIO71__FUNC_DBG_MON_A4 (MTK_PIN_NO(71) | 7)
+
+#define MT6797_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+/* #define MT6797_GPIO72__FUNC_I2S0_DI (MTK_PIN_NO(72) | 1) */
+#define MT6797_GPIO72__FUNC_I2S0_DI (MTK_PIN_NO(72) | 2)
+/* #define MT6797_GPIO72__FUNC_I2S2_DI (MTK_PIN_NO(72) | 3) */
+#define MT6797_GPIO72__FUNC_I2S2_DI (MTK_PIN_NO(72) | 4)
+#define MT6797_GPIO72__FUNC_DBG_MON_A5 (MTK_PIN_NO(72) | 7)
+
+#define MT6797_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+/* #define MT6797_GPIO73__FUNC_I2S3_DO (MTK_PIN_NO(73) | 1) */
+#define MT6797_GPIO73__FUNC_I2S3_DO (MTK_PIN_NO(73) | 2)
+/* #define MT6797_GPIO73__FUNC_I2S1_DO (MTK_PIN_NO(73) | 3) */
+#define MT6797_GPIO73__FUNC_I2S1_DO (MTK_PIN_NO(73) | 4)
+#define MT6797_GPIO73__FUNC_DBG_MON_A6 (MTK_PIN_NO(73) | 7)
+
+#define MT6797_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define MT6797_GPIO74__FUNC_SCL3_0 (MTK_PIN_NO(74) | 1)
+#define MT6797_GPIO74__FUNC_AUXIF_CLK1 (MTK_PIN_NO(74) | 7)
+
+#define MT6797_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define MT6797_GPIO75__FUNC_SDA3_0 (MTK_PIN_NO(75) | 1)
+#define MT6797_GPIO75__FUNC_AUXIF_ST1 (MTK_PIN_NO(75) | 7)
+
+#define MT6797_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define MT6797_GPIO76__FUNC_CONN_HRST_B (MTK_PIN_NO(76) | 1)
+#define MT6797_GPIO76__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(76) | 7)
+
+#define MT6797_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define MT6797_GPIO77__FUNC_CONN_TOP_CLK (MTK_PIN_NO(77) | 1)
+#define MT6797_GPIO77__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(77) | 7)
+
+#define MT6797_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define MT6797_GPIO78__FUNC_CONN_TOP_DATA (MTK_PIN_NO(78) | 1)
+#define MT6797_GPIO78__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(78) | 7)
+
+#define MT6797_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define MT6797_GPIO79__FUNC_CONN_WB_PTA (MTK_PIN_NO(79) | 1)
+#define MT6797_GPIO79__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(79) | 7)
+
+#define MT6797_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define MT6797_GPIO80__FUNC_CONN_WF_HB0 (MTK_PIN_NO(80) | 1)
+#define MT6797_GPIO80__FUNC_C2K_EINT0 (MTK_PIN_NO(80) | 7)
+
+#define MT6797_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define MT6797_GPIO81__FUNC_CONN_WF_HB1 (MTK_PIN_NO(81) | 1)
+#define MT6797_GPIO81__FUNC_C2K_EINT1 (MTK_PIN_NO(81) | 7)
+
+#define MT6797_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define MT6797_GPIO82__FUNC_CONN_WF_HB2 (MTK_PIN_NO(82) | 1)
+#define MT6797_GPIO82__FUNC_MD_CLKM0 (MTK_PIN_NO(82) | 7)
+
+#define MT6797_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define MT6797_GPIO83__FUNC_CONN_BT_CLK (MTK_PIN_NO(83) | 1)
+#define MT6797_GPIO83__FUNC_MD_CLKM1 (MTK_PIN_NO(83) | 7)
+
+#define MT6797_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define MT6797_GPIO84__FUNC_CONN_BT_DATA (MTK_PIN_NO(84) | 1)
+
+#define MT6797_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define MT6797_GPIO85__FUNC_EINT8 (MTK_PIN_NO(85) | 1)
+#define MT6797_GPIO85__FUNC_I2S1_LRCK (MTK_PIN_NO(85) | 2)
+#define MT6797_GPIO85__FUNC_I2S2_LRCK (MTK_PIN_NO(85) | 3)
+#define MT6797_GPIO85__FUNC_URXD1 (MTK_PIN_NO(85) | 4)
+#define MT6797_GPIO85__FUNC_MD_URXD0 (MTK_PIN_NO(85) | 5)
+#define MT6797_GPIO85__FUNC_DBG_MON_A7 (MTK_PIN_NO(85) | 7)
+
+#define MT6797_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define MT6797_GPIO86__FUNC_EINT9 (MTK_PIN_NO(86) | 1)
+#define MT6797_GPIO86__FUNC_I2S1_BCK (MTK_PIN_NO(86) | 2)
+#define MT6797_GPIO86__FUNC_I2S2_BCK (MTK_PIN_NO(86) | 3)
+#define MT6797_GPIO86__FUNC_UTXD1 (MTK_PIN_NO(86) | 4)
+#define MT6797_GPIO86__FUNC_MD_UTXD0 (MTK_PIN_NO(86) | 5)
+#define MT6797_GPIO86__FUNC_DBG_MON_A8 (MTK_PIN_NO(86) | 7)
+
+#define MT6797_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define MT6797_GPIO87__FUNC_EINT10 (MTK_PIN_NO(87) | 1)
+#define MT6797_GPIO87__FUNC_I2S1_MCK (MTK_PIN_NO(87) | 2)
+#define MT6797_GPIO87__FUNC_I2S2_MCK (MTK_PIN_NO(87) | 3)
+#define MT6797_GPIO87__FUNC_URTS1 (MTK_PIN_NO(87) | 4)
+#define MT6797_GPIO87__FUNC_MD_URXD1 (MTK_PIN_NO(87) | 5)
+#define MT6797_GPIO87__FUNC_DBG_MON_A9 (MTK_PIN_NO(87) | 7)
+
+#define MT6797_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define MT6797_GPIO88__FUNC_EINT11 (MTK_PIN_NO(88) | 1)
+#define MT6797_GPIO88__FUNC_I2S1_DO (MTK_PIN_NO(88) | 2)
+#define MT6797_GPIO88__FUNC_I2S2_DI (MTK_PIN_NO(88) | 3)
+#define MT6797_GPIO88__FUNC_UCTS1 (MTK_PIN_NO(88) | 4)
+#define MT6797_GPIO88__FUNC_MD_UTXD1 (MTK_PIN_NO(88) | 5)
+#define MT6797_GPIO88__FUNC_DBG_MON_A10 (MTK_PIN_NO(88) | 7)
+
+#define MT6797_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define MT6797_GPIO89__FUNC_EINT12 (MTK_PIN_NO(89) | 1)
+#define MT6797_GPIO89__FUNC_IRTX_OUT (MTK_PIN_NO(89) | 2)
+#define MT6797_GPIO89__FUNC_CLKM0 (MTK_PIN_NO(89) | 3)
+#define MT6797_GPIO89__FUNC_PCM1_SYNC (MTK_PIN_NO(89) | 4)
+#define MT6797_GPIO89__FUNC_URTS0 (MTK_PIN_NO(89) | 5)
+#define MT6797_GPIO89__FUNC_DBG_MON_A11 (MTK_PIN_NO(89) | 7)
+
+#define MT6797_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define MT6797_GPIO90__FUNC_EINT13 (MTK_PIN_NO(90) | 1)
+#define MT6797_GPIO90__FUNC_CMFLASH (MTK_PIN_NO(90) | 2)
+#define MT6797_GPIO90__FUNC_CLKM1 (MTK_PIN_NO(90) | 3)
+#define MT6797_GPIO90__FUNC_PCM1_CLK (MTK_PIN_NO(90) | 4)
+#define MT6797_GPIO90__FUNC_UCTS0 (MTK_PIN_NO(90) | 5)
+#define MT6797_GPIO90__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(90) | 7)
+
+#define MT6797_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define MT6797_GPIO91__FUNC_EINT14 (MTK_PIN_NO(91) | 1)
+#define MT6797_GPIO91__FUNC_PWM_A (MTK_PIN_NO(91) | 2)
+#define MT6797_GPIO91__FUNC_CLKM2 (MTK_PIN_NO(91) | 3)
+#define MT6797_GPIO91__FUNC_PCM1_DI (MTK_PIN_NO(91) | 4)
+#define MT6797_GPIO91__FUNC_SDA0_3 (MTK_PIN_NO(91) | 5)
+#define MT6797_GPIO91__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(91) | 7)
+
+#define MT6797_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define MT6797_GPIO92__FUNC_EINT15 (MTK_PIN_NO(92) | 1)
+#define MT6797_GPIO92__FUNC_PWM_B (MTK_PIN_NO(92) | 2)
+#define MT6797_GPIO92__FUNC_CLKM3 (MTK_PIN_NO(92) | 3)
+#define MT6797_GPIO92__FUNC_PCM1_DO0 (MTK_PIN_NO(92) | 4)
+#define MT6797_GPIO92__FUNC_SCL0_3 (MTK_PIN_NO(92) | 5)
+
+#define MT6797_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define MT6797_GPIO93__FUNC_EINT16 (MTK_PIN_NO(93) | 1)
+#define MT6797_GPIO93__FUNC_IDDIG (MTK_PIN_NO(93) | 2)
+#define MT6797_GPIO93__FUNC_CLKM4 (MTK_PIN_NO(93) | 3)
+#define MT6797_GPIO93__FUNC_PCM1_DO1 (MTK_PIN_NO(93) | 4)
+#define MT6797_GPIO93__FUNC_MD_INT2 (MTK_PIN_NO(93) | 5)
+#define MT6797_GPIO93__FUNC_DROP_ZONE (MTK_PIN_NO(93) | 7)
+
+#define MT6797_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define MT6797_GPIO94__FUNC_USB_DRVVBUS (MTK_PIN_NO(94) | 1)
+#define MT6797_GPIO94__FUNC_PWM_C (MTK_PIN_NO(94) | 2)
+#define MT6797_GPIO94__FUNC_CLKM5 (MTK_PIN_NO(94) | 3)
+
+#define MT6797_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define MT6797_GPIO95__FUNC_SDA2_0 (MTK_PIN_NO(95) | 1)
+#define MT6797_GPIO95__FUNC_AUXIF_ST0 (MTK_PIN_NO(95) | 7)
+
+#define MT6797_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define MT6797_GPIO96__FUNC_SCL2_0 (MTK_PIN_NO(96) | 1)
+#define MT6797_GPIO96__FUNC_AUXIF_CLK0 (MTK_PIN_NO(96) | 7)
+
+#define MT6797_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define MT6797_GPIO97__FUNC_URXD0 (MTK_PIN_NO(97) | 1)
+#define MT6797_GPIO97__FUNC_UTXD0 (MTK_PIN_NO(97) | 2)
+#define MT6797_GPIO97__FUNC_MD_URXD0 (MTK_PIN_NO(97) | 3)
+#define MT6797_GPIO97__FUNC_MD_URXD1 (MTK_PIN_NO(97) | 4)
+#define MT6797_GPIO97__FUNC_MD_URXD2 (MTK_PIN_NO(97) | 5)
+#define MT6797_GPIO97__FUNC_C2K_URXD0 (MTK_PIN_NO(97) | 6)
+#define MT6797_GPIO97__FUNC_C2K_URXD1 (MTK_PIN_NO(97) | 7)
+
+#define MT6797_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define MT6797_GPIO98__FUNC_UTXD0 (MTK_PIN_NO(98) | 1)
+#define MT6797_GPIO98__FUNC_URXD0 (MTK_PIN_NO(98) | 2)
+#define MT6797_GPIO98__FUNC_MD_UTXD0 (MTK_PIN_NO(98) | 3)
+#define MT6797_GPIO98__FUNC_MD_UTXD1 (MTK_PIN_NO(98) | 4)
+#define MT6797_GPIO98__FUNC_MD_UTXD2 (MTK_PIN_NO(98) | 5)
+#define MT6797_GPIO98__FUNC_C2K_UTXD0 (MTK_PIN_NO(98) | 6)
+#define MT6797_GPIO98__FUNC_C2K_UTXD1 (MTK_PIN_NO(98) | 7)
+
+#define MT6797_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define MT6797_GPIO99__FUNC_RTC32K_CK (MTK_PIN_NO(99) | 1)
+
+#define MT6797_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define MT6797_GPIO100__FUNC_SRCLKENAI0 (MTK_PIN_NO(100) | 1)
+
+#define MT6797_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define MT6797_GPIO101__FUNC_SRCLKENAI1 (MTK_PIN_NO(101) | 1)
+
+#define MT6797_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define MT6797_GPIO102__FUNC_SRCLKENA0 (MTK_PIN_NO(102) | 1)
+
+#define MT6797_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define MT6797_GPIO103__FUNC_SRCLKENA1 (MTK_PIN_NO(103) | 1)
+
+#define MT6797_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define MT6797_GPIO104__FUNC_SYSRSTB (MTK_PIN_NO(104) | 1)
+
+#define MT6797_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT6797_GPIO105__FUNC_WATCHDOG (MTK_PIN_NO(105) | 1)
+
+#define MT6797_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT6797_GPIO106__FUNC_KPROW0 (MTK_PIN_NO(106) | 1)
+#define MT6797_GPIO106__FUNC_CMFLASH (MTK_PIN_NO(106) | 2)
+#define MT6797_GPIO106__FUNC_CLKM4 (MTK_PIN_NO(106) | 3)
+#define MT6797_GPIO106__FUNC_TP_GPIO0_AO (MTK_PIN_NO(106) | 4)
+#define MT6797_GPIO106__FUNC_IRTX_OUT (MTK_PIN_NO(106) | 5)
+
+#define MT6797_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT6797_GPIO107__FUNC_KPROW1 (MTK_PIN_NO(107) | 1)
+#define MT6797_GPIO107__FUNC_IDDIG (MTK_PIN_NO(107) | 2)
+#define MT6797_GPIO107__FUNC_CLKM5 (MTK_PIN_NO(107) | 3)
+#define MT6797_GPIO107__FUNC_TP_GPIO1_AO (MTK_PIN_NO(107) | 4)
+#define MT6797_GPIO107__FUNC_I2S1_BCK (MTK_PIN_NO(107) | 5)
+#define MT6797_GPIO107__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(107) | 7)
+
+#define MT6797_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT6797_GPIO108__FUNC_KPROW2 (MTK_PIN_NO(108) | 1)
+#define MT6797_GPIO108__FUNC_USB_DRVVBUS (MTK_PIN_NO(108) | 2)
+#define MT6797_GPIO108__FUNC_PWM_A (MTK_PIN_NO(108) | 3)
+#define MT6797_GPIO108__FUNC_CMFLASH (MTK_PIN_NO(108) | 4)
+#define MT6797_GPIO108__FUNC_I2S1_LRCK (MTK_PIN_NO(108) | 5)
+#define MT6797_GPIO108__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(108) | 7)
+
+#define MT6797_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT6797_GPIO109__FUNC_KPCOL0 (MTK_PIN_NO(109) | 1)
+
+#define MT6797_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT6797_GPIO110__FUNC_KPCOL1 (MTK_PIN_NO(110) | 1)
+#define MT6797_GPIO110__FUNC_SDA1_3 (MTK_PIN_NO(110) | 2)
+#define MT6797_GPIO110__FUNC_PWM_B (MTK_PIN_NO(110) | 3)
+#define MT6797_GPIO110__FUNC_CLKM0 (MTK_PIN_NO(110) | 4)
+#define MT6797_GPIO110__FUNC_I2S1_DO (MTK_PIN_NO(110) | 5)
+#define MT6797_GPIO110__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(110) | 7)
+
+#define MT6797_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT6797_GPIO111__FUNC_KPCOL2 (MTK_PIN_NO(111) | 1)
+#define MT6797_GPIO111__FUNC_SCL1_3 (MTK_PIN_NO(111) | 2)
+#define MT6797_GPIO111__FUNC_PWM_C (MTK_PIN_NO(111) | 3)
+#define MT6797_GPIO111__FUNC_DISP_PWM (MTK_PIN_NO(111) | 4)
+#define MT6797_GPIO111__FUNC_I2S1_MCK (MTK_PIN_NO(111) | 5)
+#define MT6797_GPIO111__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(111) | 7)
+
+#define MT6797_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT6797_GPIO112__FUNC_MD_INT1_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(112) | 1)
+#define MT6797_GPIO112__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(112) | 7)
+
+#define MT6797_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT6797_GPIO113__FUNC_MD_INT0_C2K_UIM0_HOT_PLUG_IN (MTK_PIN_NO(113) | 1)
+#define MT6797_GPIO113__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(113) | 7)
+
+#define MT6797_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT6797_GPIO114__FUNC_MSDC0_DAT0 (MTK_PIN_NO(114) | 1)
+
+#define MT6797_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT6797_GPIO115__FUNC_MSDC0_DAT1 (MTK_PIN_NO(115) | 1)
+
+#define MT6797_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT6797_GPIO116__FUNC_MSDC0_DAT2 (MTK_PIN_NO(116) | 1)
+
+#define MT6797_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT6797_GPIO117__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1)
+
+#define MT6797_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT6797_GPIO118__FUNC_MSDC0_DAT4 (MTK_PIN_NO(118) | 1)
+
+#define MT6797_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT6797_GPIO119__FUNC_MSDC0_DAT5 (MTK_PIN_NO(119) | 1)
+
+#define MT6797_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT6797_GPIO120__FUNC_MSDC0_DAT6 (MTK_PIN_NO(120) | 1)
+
+#define MT6797_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define MT6797_GPIO121__FUNC_MSDC0_DAT7 (MTK_PIN_NO(121) | 1)
+
+#define MT6797_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define MT6797_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1)
+
+#define MT6797_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT6797_GPIO123__FUNC_MSDC0_CLK (MTK_PIN_NO(123) | 1)
+
+#define MT6797_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define MT6797_GPIO124__FUNC_MSDC0_DSL (MTK_PIN_NO(124) | 1)
+
+#define MT6797_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define MT6797_GPIO125__FUNC_MSDC0_RSTB (MTK_PIN_NO(125) | 1)
+
+#define MT6797_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define MT6797_GPIO126__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(126) | 1)
+#define MT6797_GPIO126__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(126) | 2)
+#define MT6797_GPIO126__FUNC_C2K_UIM0_CLK (MTK_PIN_NO(126) | 3)
+#define MT6797_GPIO126__FUNC_C2K_UIM1_CLK (MTK_PIN_NO(126) | 4)
+
+#define MT6797_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define MT6797_GPIO127__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(127) | 1)
+#define MT6797_GPIO127__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(127) | 2)
+#define MT6797_GPIO127__FUNC_C2K_UIM0_RST (MTK_PIN_NO(127) | 3)
+#define MT6797_GPIO127__FUNC_C2K_UIM1_RST (MTK_PIN_NO(127) | 4)
+
+#define MT6797_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define MT6797_GPIO128__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(128) | 1)
+#define MT6797_GPIO128__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(128) | 2)
+#define MT6797_GPIO128__FUNC_C2K_UIM0_IO (MTK_PIN_NO(128) | 3)
+#define MT6797_GPIO128__FUNC_C2K_UIM1_IO (MTK_PIN_NO(128) | 4)
+
+#define MT6797_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define MT6797_GPIO129__FUNC_MSDC1_CMD (MTK_PIN_NO(129) | 1)
+#define MT6797_GPIO129__FUNC_CONN_DSP_JMS (MTK_PIN_NO(129) | 2)
+#define MT6797_GPIO129__FUNC_LTE_JTAG_TMS (MTK_PIN_NO(129) | 3)
+#define MT6797_GPIO129__FUNC_UDI_TMS (MTK_PIN_NO(129) | 4)
+#define MT6797_GPIO129__FUNC_C2K_TMS (MTK_PIN_NO(129) | 5)
+
+#define MT6797_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define MT6797_GPIO130__FUNC_MSDC1_DAT0 (MTK_PIN_NO(130) | 1)
+#define MT6797_GPIO130__FUNC_CONN_DSP_JDI (MTK_PIN_NO(130) | 2)
+#define MT6797_GPIO130__FUNC_LTE_JTAG_TDI (MTK_PIN_NO(130) | 3)
+#define MT6797_GPIO130__FUNC_UDI_TDI (MTK_PIN_NO(130) | 4)
+#define MT6797_GPIO130__FUNC_C2K_TDI (MTK_PIN_NO(130) | 5)
+
+#define MT6797_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define MT6797_GPIO131__FUNC_MSDC1_DAT1 (MTK_PIN_NO(131) | 1)
+#define MT6797_GPIO131__FUNC_CONN_DSP_JDO (MTK_PIN_NO(131) | 2)
+#define MT6797_GPIO131__FUNC_LTE_JTAG_TDO (MTK_PIN_NO(131) | 3)
+#define MT6797_GPIO131__FUNC_UDI_TDO (MTK_PIN_NO(131) | 4)
+#define MT6797_GPIO131__FUNC_C2K_TDO (MTK_PIN_NO(131) | 5)
+
+#define MT6797_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define MT6797_GPIO132__FUNC_MSDC1_DAT2 (MTK_PIN_NO(132) | 1)
+#define MT6797_GPIO132__FUNC_C2K_RTCK (MTK_PIN_NO(132) | 5)
+
+#define MT6797_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define MT6797_GPIO133__FUNC_MSDC1_DAT3 (MTK_PIN_NO(133) | 1)
+#define MT6797_GPIO133__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(133) | 2)
+#define MT6797_GPIO133__FUNC_LTE_JTAG_TRSTN (MTK_PIN_NO(133) | 3)
+#define MT6797_GPIO133__FUNC_UDI_NTRST (MTK_PIN_NO(133) | 4)
+#define MT6797_GPIO133__FUNC_C2K_NTRST (MTK_PIN_NO(133) | 5)
+
+#define MT6797_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define MT6797_GPIO134__FUNC_MSDC1_CLK (MTK_PIN_NO(134) | 1)
+#define MT6797_GPIO134__FUNC_CONN_DSP_JCK (MTK_PIN_NO(134) | 2)
+#define MT6797_GPIO134__FUNC_LTE_JTAG_TCK (MTK_PIN_NO(134) | 3)
+#define MT6797_GPIO134__FUNC_UDI_TCK_XI (MTK_PIN_NO(134) | 4)
+#define MT6797_GPIO134__FUNC_C2K_TCK (MTK_PIN_NO(134) | 5)
+
+#define MT6797_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define MT6797_GPIO135__FUNC_TDM_LRCK (MTK_PIN_NO(135) | 1)
+#define MT6797_GPIO135__FUNC_I2S0_LRCK (MTK_PIN_NO(135) | 2)
+#define MT6797_GPIO135__FUNC_CLKM0 (MTK_PIN_NO(135) | 3)
+#define MT6797_GPIO135__FUNC_PCM1_SYNC (MTK_PIN_NO(135) | 4)
+#define MT6797_GPIO135__FUNC_PWM_A (MTK_PIN_NO(135) | 5)
+#define MT6797_GPIO135__FUNC_DBG_MON_A12 (MTK_PIN_NO(135) | 7)
+
+#define MT6797_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define MT6797_GPIO136__FUNC_TDM_BCK (MTK_PIN_NO(136) | 1)
+#define MT6797_GPIO136__FUNC_I2S0_BCK (MTK_PIN_NO(136) | 2)
+#define MT6797_GPIO136__FUNC_CLKM1 (MTK_PIN_NO(136) | 3)
+#define MT6797_GPIO136__FUNC_PCM1_CLK (MTK_PIN_NO(136) | 4)
+#define MT6797_GPIO136__FUNC_PWM_B (MTK_PIN_NO(136) | 5)
+#define MT6797_GPIO136__FUNC_DBG_MON_A13 (MTK_PIN_NO(136) | 7)
+
+#define MT6797_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define MT6797_GPIO137__FUNC_TDM_MCK (MTK_PIN_NO(137) | 1)
+#define MT6797_GPIO137__FUNC_I2S0_MCK (MTK_PIN_NO(137) | 2)
+#define MT6797_GPIO137__FUNC_CLKM2 (MTK_PIN_NO(137) | 3)
+#define MT6797_GPIO137__FUNC_PCM1_DI (MTK_PIN_NO(137) | 4)
+#define MT6797_GPIO137__FUNC_IRTX_OUT (MTK_PIN_NO(137) | 5)
+#define MT6797_GPIO137__FUNC_DBG_MON_A14 (MTK_PIN_NO(137) | 7)
+
+#define MT6797_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define MT6797_GPIO138__FUNC_TDM_DATA0 (MTK_PIN_NO(138) | 1)
+#define MT6797_GPIO138__FUNC_I2S0_DI (MTK_PIN_NO(138) | 2)
+#define MT6797_GPIO138__FUNC_CLKM3 (MTK_PIN_NO(138) | 3)
+#define MT6797_GPIO138__FUNC_PCM1_DO0 (MTK_PIN_NO(138) | 4)
+#define MT6797_GPIO138__FUNC_PWM_C (MTK_PIN_NO(138) | 5)
+#define MT6797_GPIO138__FUNC_SDA3_1 (MTK_PIN_NO(138) | 6)
+#define MT6797_GPIO138__FUNC_DBG_MON_A15 (MTK_PIN_NO(138) | 7)
+
+#define MT6797_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define MT6797_GPIO139__FUNC_TDM_DATA1 (MTK_PIN_NO(139) | 1)
+#define MT6797_GPIO139__FUNC_I2S3_DO (MTK_PIN_NO(139) | 2)
+#define MT6797_GPIO139__FUNC_CLKM4 (MTK_PIN_NO(139) | 3)
+#define MT6797_GPIO139__FUNC_PCM1_DO1 (MTK_PIN_NO(139) | 4)
+#define MT6797_GPIO139__FUNC_ANT_SEL2 (MTK_PIN_NO(139) | 5)
+#define MT6797_GPIO139__FUNC_SCL3_1 (MTK_PIN_NO(139) | 6)
+#define MT6797_GPIO139__FUNC_DBG_MON_A16 (MTK_PIN_NO(139) | 7)
+
+#define MT6797_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define MT6797_GPIO140__FUNC_TDM_DATA2 (MTK_PIN_NO(140) | 1)
+#define MT6797_GPIO140__FUNC_DISP_PWM (MTK_PIN_NO(140) | 2)
+#define MT6797_GPIO140__FUNC_CLKM5 (MTK_PIN_NO(140) | 3)
+#define MT6797_GPIO140__FUNC_SDA1_4 (MTK_PIN_NO(140) | 4)
+#define MT6797_GPIO140__FUNC_ANT_SEL1 (MTK_PIN_NO(140) | 5)
+#define MT6797_GPIO140__FUNC_URXD3 (MTK_PIN_NO(140) | 6)
+#define MT6797_GPIO140__FUNC_DBG_MON_A17 (MTK_PIN_NO(140) | 7)
+
+#define MT6797_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define MT6797_GPIO141__FUNC_TDM_DATA3 (MTK_PIN_NO(141) | 1)
+#define MT6797_GPIO141__FUNC_CMFLASH (MTK_PIN_NO(141) | 2)
+#define MT6797_GPIO141__FUNC_IRTX_OUT (MTK_PIN_NO(141) | 3)
+#define MT6797_GPIO141__FUNC_SCL1_4 (MTK_PIN_NO(141) | 4)
+#define MT6797_GPIO141__FUNC_ANT_SEL0 (MTK_PIN_NO(141) | 5)
+#define MT6797_GPIO141__FUNC_UTXD3 (MTK_PIN_NO(141) | 6)
+#define MT6797_GPIO141__FUNC_DBG_MON_A18 (MTK_PIN_NO(141) | 7)
+
+#define MT6797_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define MT6797_GPIO142__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(142) | 1)
+#define MT6797_GPIO142__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(142) | 2)
+
+#define MT6797_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define MT6797_GPIO143__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(143) | 1)
+#define MT6797_GPIO143__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(143) | 2)
+
+#define MT6797_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define MT6797_GPIO144__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(144) | 1)
+
+#define MT6797_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
+#define MT6797_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1)
+
+#define MT6797_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
+#define MT6797_GPIO146__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(146) | 1)
+
+#define MT6797_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
+#define MT6797_GPIO147__FUNC_AUD_DAT_MISO (MTK_PIN_NO(147) | 1)
+#define MT6797_GPIO147__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(147) | 2)
+#define MT6797_GPIO147__FUNC_VOW_DAT_MISO (MTK_PIN_NO(147) | 3)
+
+#define MT6797_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
+#define MT6797_GPIO148__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(148) | 1)
+#define MT6797_GPIO148__FUNC_AUD_DAT_MISO (MTK_PIN_NO(148) | 2)
+
+#define MT6797_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
+#define MT6797_GPIO149__FUNC_VOW_CLK_MISO (MTK_PIN_NO(149) | 1)
+
+#define MT6797_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
+#define MT6797_GPIO150__FUNC_ANC_DAT_MOSI (MTK_PIN_NO(150) | 1)
+
+#define MT6797_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
+#define MT6797_GPIO151__FUNC_SCL6_0 (MTK_PIN_NO(151) | 1)
+
+#define MT6797_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
+#define MT6797_GPIO152__FUNC_SDA6_0 (MTK_PIN_NO(152) | 1)
+
+#define MT6797_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
+#define MT6797_GPIO153__FUNC_SCL7_0 (MTK_PIN_NO(153) | 1)
+
+#define MT6797_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
+#define MT6797_GPIO154__FUNC_SDA7_0 (MTK_PIN_NO(154) | 1)
+
+#define MT6797_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
+#define MT6797_GPIO155__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(155) | 1)
+#define MT6797_GPIO155__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(155) | 2)
+#define MT6797_GPIO155__FUNC_C2K_UIM0_CLK (MTK_PIN_NO(155) | 3)
+#define MT6797_GPIO155__FUNC_C2K_UIM1_CLK (MTK_PIN_NO(155) | 4)
+
+#define MT6797_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
+#define MT6797_GPIO156__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(156) | 1)
+#define MT6797_GPIO156__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(156) | 2)
+#define MT6797_GPIO156__FUNC_C2K_UIM0_RST (MTK_PIN_NO(156) | 3)
+#define MT6797_GPIO156__FUNC_C2K_UIM1_RST (MTK_PIN_NO(156) | 4)
+
+#define MT6797_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
+#define MT6797_GPIO157__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(157) | 1)
+#define MT6797_GPIO157__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(157) | 2)
+#define MT6797_GPIO157__FUNC_C2K_UIM0_IO (MTK_PIN_NO(157) | 3)
+#define MT6797_GPIO157__FUNC_C2K_UIM1_IO (MTK_PIN_NO(157) | 4)
+
+#define MT6797_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
+#define MT6797_GPIO158__FUNC_MIPI_TDP0 (MTK_PIN_NO(158) | 1)
+
+#define MT6797_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
+#define MT6797_GPIO159__FUNC_MIPI_TDN0 (MTK_PIN_NO(159) | 1)
+
+#define MT6797_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
+#define MT6797_GPIO160__FUNC_MIPI_TDP1 (MTK_PIN_NO(160) | 1)
+
+#define MT6797_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
+#define MT6797_GPIO161__FUNC_MIPI_TDN1 (MTK_PIN_NO(161) | 1)
+
+#define MT6797_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
+#define MT6797_GPIO162__FUNC_MIPI_TCP (MTK_PIN_NO(162) | 1)
+
+#define MT6797_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
+#define MT6797_GPIO163__FUNC_MIPI_TCN (MTK_PIN_NO(163) | 1)
+
+#define MT6797_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
+#define MT6797_GPIO164__FUNC_MIPI_TDP2 (MTK_PIN_NO(164) | 1)
+
+#define MT6797_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
+#define MT6797_GPIO165__FUNC_MIPI_TDN2 (MTK_PIN_NO(165) | 1)
+
+#define MT6797_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
+#define MT6797_GPIO166__FUNC_MIPI_TDP3 (MTK_PIN_NO(166) | 1)
+
+#define MT6797_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
+#define MT6797_GPIO167__FUNC_MIPI_TDN3 (MTK_PIN_NO(167) | 1)
+
+#define MT6797_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
+#define MT6797_GPIO168__FUNC_MIPI_TDP0_A (MTK_PIN_NO(168) | 1)
+
+#define MT6797_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
+#define MT6797_GPIO169__FUNC_MIPI_TDN0_A (MTK_PIN_NO(169) | 1)
+
+#define MT6797_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
+#define MT6797_GPIO170__FUNC_MIPI_TDP1_A (MTK_PIN_NO(170) | 1)
+
+#define MT6797_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
+#define MT6797_GPIO171__FUNC_MIPI_TDN1_A (MTK_PIN_NO(171) | 1)
+
+#define MT6797_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
+#define MT6797_GPIO172__FUNC_MIPI_TCP_A (MTK_PIN_NO(172) | 1)
+
+#define MT6797_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
+#define MT6797_GPIO173__FUNC_MIPI_TCN_A (MTK_PIN_NO(173) | 1)
+
+#define MT6797_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
+#define MT6797_GPIO174__FUNC_MIPI_TDP2_A (MTK_PIN_NO(174) | 1)
+
+#define MT6797_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
+#define MT6797_GPIO175__FUNC_MIPI_TDN2_A (MTK_PIN_NO(175) | 1)
+
+#define MT6797_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
+#define MT6797_GPIO176__FUNC_MIPI_TDP3_A (MTK_PIN_NO(176) | 1)
+
+#define MT6797_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
+#define MT6797_GPIO177__FUNC_MIPI_TDN3_A (MTK_PIN_NO(177) | 1)
+
+#define MT6797_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
+#define MT6797_GPIO178__FUNC_DISP_PWM (MTK_PIN_NO(178) | 1)
+#define MT6797_GPIO178__FUNC_PWM_D (MTK_PIN_NO(178) | 2)
+#define MT6797_GPIO178__FUNC_CLKM5 (MTK_PIN_NO(178) | 3)
+#define MT6797_GPIO178__FUNC_DBG_MON_A19 (MTK_PIN_NO(178) | 7)
+
+#define MT6797_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
+#define MT6797_GPIO179__FUNC_DSI_TE0 (MTK_PIN_NO(179) | 1)
+#define MT6797_GPIO179__FUNC_DBG_MON_A20 (MTK_PIN_NO(179) | 7)
+
+#define MT6797_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)
+#define MT6797_GPIO180__FUNC_LCM_RST (MTK_PIN_NO(180) | 1)
+#define MT6797_GPIO180__FUNC_DSI_TE1 (MTK_PIN_NO(180) | 2)
+#define MT6797_GPIO180__FUNC_DBG_MON_A21 (MTK_PIN_NO(180) | 7)
+
+#define MT6797_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)
+#define MT6797_GPIO181__FUNC_IDDIG (MTK_PIN_NO(181) | 1)
+#define MT6797_GPIO181__FUNC_DSI_TE1 (MTK_PIN_NO(181) | 2)
+#define MT6797_GPIO181__FUNC_DBG_MON_A22 (MTK_PIN_NO(181) | 7)
+
+#define MT6797_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)
+#define MT6797_GPIO182__FUNC_TESTMODE (MTK_PIN_NO(182) | 1)
+
+#define MT6797_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0)
+#define MT6797_GPIO183__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(183) | 1)
+#define MT6797_GPIO183__FUNC_SPM_BSI_CK (MTK_PIN_NO(183) | 2)
+#define MT6797_GPIO183__FUNC_DBG_MON_B27 (MTK_PIN_NO(183) | 7)
+
+#define MT6797_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0)
+#define MT6797_GPIO184__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(184) | 1)
+#define MT6797_GPIO184__FUNC_SPM_BSI_EN (MTK_PIN_NO(184) | 2)
+#define MT6797_GPIO184__FUNC_DBG_MON_B28 (MTK_PIN_NO(184) | 7)
+
+#define MT6797_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0)
+#define MT6797_GPIO185__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(185) | 1)
+#define MT6797_GPIO185__FUNC_SPM_BSI_D0 (MTK_PIN_NO(185) | 2)
+#define MT6797_GPIO185__FUNC_DBG_MON_B29 (MTK_PIN_NO(185) | 7)
+
+#define MT6797_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0)
+#define MT6797_GPIO186__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(186) | 1)
+#define MT6797_GPIO186__FUNC_SPM_BSI_D1 (MTK_PIN_NO(186) | 2)
+#define MT6797_GPIO186__FUNC_DBG_MON_B30 (MTK_PIN_NO(186) | 7)
+
+#define MT6797_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0)
+#define MT6797_GPIO187__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(187) | 1)
+#define MT6797_GPIO187__FUNC_SPM_BSI_D2 (MTK_PIN_NO(187) | 2)
+#define MT6797_GPIO187__FUNC_DBG_MON_B31 (MTK_PIN_NO(187) | 7)
+
+#define MT6797_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0)
+#define MT6797_GPIO188__FUNC_MIPI0_SCLK (MTK_PIN_NO(188) | 1)
+#define MT6797_GPIO188__FUNC_DBG_MON_B32 (MTK_PIN_NO(188) | 7)
+
+#define MT6797_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0)
+#define MT6797_GPIO189__FUNC_MIPI0_SDATA (MTK_PIN_NO(189) | 1)
+
+#define MT6797_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0)
+#define MT6797_GPIO190__FUNC_MIPI1_SCLK (MTK_PIN_NO(190) | 1)
+
+#define MT6797_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0)
+#define MT6797_GPIO191__FUNC_MIPI1_SDATA (MTK_PIN_NO(191) | 1)
+
+#define MT6797_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0)
+#define MT6797_GPIO192__FUNC_BPI_BUS4 (MTK_PIN_NO(192) | 1)
+
+#define MT6797_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0)
+#define MT6797_GPIO193__FUNC_BPI_BUS5 (MTK_PIN_NO(193) | 1)
+#define MT6797_GPIO193__FUNC_DBG_MON_B0 (MTK_PIN_NO(193) | 7)
+
+#define MT6797_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0)
+#define MT6797_GPIO194__FUNC_BPI_BUS6 (MTK_PIN_NO(194) | 1)
+#define MT6797_GPIO194__FUNC_DBG_MON_B1 (MTK_PIN_NO(194) | 7)
+
+#define MT6797_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0)
+#define MT6797_GPIO195__FUNC_BPI_BUS7 (MTK_PIN_NO(195) | 1)
+#define MT6797_GPIO195__FUNC_DBG_MON_B2 (MTK_PIN_NO(195) | 7)
+
+#define MT6797_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0)
+#define MT6797_GPIO196__FUNC_BPI_BUS8 (MTK_PIN_NO(196) | 1)
+#define MT6797_GPIO196__FUNC_DBG_MON_B3 (MTK_PIN_NO(196) | 7)
+
+#define MT6797_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0)
+#define MT6797_GPIO197__FUNC_BPI_BUS9 (MTK_PIN_NO(197) | 1)
+#define MT6797_GPIO197__FUNC_DBG_MON_B4 (MTK_PIN_NO(197) | 7)
+
+#define MT6797_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0)
+#define MT6797_GPIO198__FUNC_BPI_BUS10 (MTK_PIN_NO(198) | 1)
+#define MT6797_GPIO198__FUNC_DBG_MON_B5 (MTK_PIN_NO(198) | 7)
+
+#define MT6797_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define MT6797_GPIO199__FUNC_BPI_BUS11 (MTK_PIN_NO(199) | 1)
+#define MT6797_GPIO199__FUNC_DBG_MON_B6 (MTK_PIN_NO(199) | 7)
+
+#define MT6797_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define MT6797_GPIO200__FUNC_BPI_BUS12 (MTK_PIN_NO(200) | 1)
+#define MT6797_GPIO200__FUNC_DBG_MON_B7 (MTK_PIN_NO(200) | 7)
+
+#define MT6797_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define MT6797_GPIO201__FUNC_BPI_BUS13 (MTK_PIN_NO(201) | 1)
+#define MT6797_GPIO201__FUNC_DBG_MON_B8 (MTK_PIN_NO(201) | 7)
+
+#define MT6797_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
+#define MT6797_GPIO202__FUNC_BPI_BUS14 (MTK_PIN_NO(202) | 1)
+#define MT6797_GPIO202__FUNC_DBG_MON_B9 (MTK_PIN_NO(202) | 7)
+
+#define MT6797_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
+#define MT6797_GPIO203__FUNC_BPI_BUS15 (MTK_PIN_NO(203) | 1)
+#define MT6797_GPIO203__FUNC_DBG_MON_B10 (MTK_PIN_NO(203) | 7)
+
+#define MT6797_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
+#define MT6797_GPIO204__FUNC_BPI_BUS16 (MTK_PIN_NO(204) | 1)
+#define MT6797_GPIO204__FUNC_PA_VM0 (MTK_PIN_NO(204) | 2)
+#define MT6797_GPIO204__FUNC_DBG_MON_B11 (MTK_PIN_NO(204) | 7)
+
+#define MT6797_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
+#define MT6797_GPIO205__FUNC_BPI_BUS17 (MTK_PIN_NO(205) | 1)
+#define MT6797_GPIO205__FUNC_PA_VM1 (MTK_PIN_NO(205) | 2)
+#define MT6797_GPIO205__FUNC_DBG_MON_B12 (MTK_PIN_NO(205) | 7)
+
+#define MT6797_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
+#define MT6797_GPIO206__FUNC_BPI_BUS18 (MTK_PIN_NO(206) | 1)
+#define MT6797_GPIO206__FUNC_TX_SWAP0 (MTK_PIN_NO(206) | 2)
+#define MT6797_GPIO206__FUNC_DBG_MON_B13 (MTK_PIN_NO(206) | 7)
+
+#define MT6797_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
+#define MT6797_GPIO207__FUNC_BPI_BUS19 (MTK_PIN_NO(207) | 1)
+#define MT6797_GPIO207__FUNC_TX_SWAP1 (MTK_PIN_NO(207) | 2)
+#define MT6797_GPIO207__FUNC_DBG_MON_B14 (MTK_PIN_NO(207) | 7)
+
+#define MT6797_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
+#define MT6797_GPIO208__FUNC_BPI_BUS20 (MTK_PIN_NO(208) | 1)
+#define MT6797_GPIO208__FUNC_TX_SWAP2 (MTK_PIN_NO(208) | 2)
+#define MT6797_GPIO208__FUNC_DBG_MON_B15 (MTK_PIN_NO(208) | 7)
+
+#define MT6797_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
+#define MT6797_GPIO209__FUNC_BPI_BUS21 (MTK_PIN_NO(209) | 1)
+#define MT6797_GPIO209__FUNC_TX_SWAP3 (MTK_PIN_NO(209) | 2)
+#define MT6797_GPIO209__FUNC_DBG_MON_B16 (MTK_PIN_NO(209) | 7)
+
+#define MT6797_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0)
+#define MT6797_GPIO210__FUNC_BPI_BUS22 (MTK_PIN_NO(210) | 1)
+#define MT6797_GPIO210__FUNC_DET_BPI0 (MTK_PIN_NO(210) | 2)
+#define MT6797_GPIO210__FUNC_DBG_MON_B17 (MTK_PIN_NO(210) | 7)
+
+#define MT6797_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0)
+#define MT6797_GPIO211__FUNC_BPI_BUS23 (MTK_PIN_NO(211) | 1)
+#define MT6797_GPIO211__FUNC_DET_BPI1 (MTK_PIN_NO(211) | 2)
+#define MT6797_GPIO211__FUNC_DBG_MON_B18 (MTK_PIN_NO(211) | 7)
+
+#define MT6797_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0)
+#define MT6797_GPIO212__FUNC_BPI_BUS0 (MTK_PIN_NO(212) | 1)
+#define MT6797_GPIO212__FUNC_DBG_MON_B19 (MTK_PIN_NO(212) | 7)
+
+#define MT6797_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0)
+#define MT6797_GPIO213__FUNC_BPI_BUS1 (MTK_PIN_NO(213) | 1)
+#define MT6797_GPIO213__FUNC_DBG_MON_B20 (MTK_PIN_NO(213) | 7)
+
+#define MT6797_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0)
+#define MT6797_GPIO214__FUNC_BPI_BUS2 (MTK_PIN_NO(214) | 1)
+#define MT6797_GPIO214__FUNC_DBG_MON_B21 (MTK_PIN_NO(214) | 7)
+
+#define MT6797_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0)
+#define MT6797_GPIO215__FUNC_BPI_BUS3 (MTK_PIN_NO(215) | 1)
+#define MT6797_GPIO215__FUNC_DBG_MON_B22 (MTK_PIN_NO(215) | 7)
+
+#define MT6797_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0)
+#define MT6797_GPIO216__FUNC_MIPI2_SCLK (MTK_PIN_NO(216) | 1)
+#define MT6797_GPIO216__FUNC_DBG_MON_B23 (MTK_PIN_NO(216) | 7)
+
+#define MT6797_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0)
+#define MT6797_GPIO217__FUNC_MIPI2_SDATA (MTK_PIN_NO(217) | 1)
+#define MT6797_GPIO217__FUNC_DBG_MON_B24 (MTK_PIN_NO(217) | 7)
+
+#define MT6797_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0)
+#define MT6797_GPIO218__FUNC_MIPI3_SCLK (MTK_PIN_NO(218) | 1)
+#define MT6797_GPIO218__FUNC_DBG_MON_B25 (MTK_PIN_NO(218) | 7)
+
+#define MT6797_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0)
+#define MT6797_GPIO219__FUNC_MIPI3_SDATA (MTK_PIN_NO(219) | 1)
+#define MT6797_GPIO219__FUNC_DBG_MON_B26 (MTK_PIN_NO(219) | 7)
+
+#define MT6797_GPIO220__FUNC_GPIO220 (MTK_PIN_NO(220) | 0)
+#define MT6797_GPIO220__FUNC_CONN_WF_IP (MTK_PIN_NO(220) | 1)
+
+#define MT6797_GPIO221__FUNC_GPIO221 (MTK_PIN_NO(221) | 0)
+#define MT6797_GPIO221__FUNC_CONN_WF_IN (MTK_PIN_NO(221) | 1)
+
+#define MT6797_GPIO222__FUNC_GPIO222 (MTK_PIN_NO(222) | 0)
+#define MT6797_GPIO222__FUNC_CONN_WF_QP (MTK_PIN_NO(222) | 1)
+
+#define MT6797_GPIO223__FUNC_GPIO223 (MTK_PIN_NO(223) | 0)
+#define MT6797_GPIO223__FUNC_CONN_WF_QN (MTK_PIN_NO(223) | 1)
+
+#define MT6797_GPIO224__FUNC_GPIO224 (MTK_PIN_NO(224) | 0)
+#define MT6797_GPIO224__FUNC_CONN_BT_IP (MTK_PIN_NO(224) | 1)
+
+#define MT6797_GPIO225__FUNC_GPIO225 (MTK_PIN_NO(225) | 0)
+#define MT6797_GPIO225__FUNC_CONN_BT_IN (MTK_PIN_NO(225) | 1)
+
+#define MT6797_GPIO226__FUNC_GPIO226 (MTK_PIN_NO(226) | 0)
+#define MT6797_GPIO226__FUNC_CONN_BT_QP (MTK_PIN_NO(226) | 1)
+
+#define MT6797_GPIO227__FUNC_GPIO227 (MTK_PIN_NO(227) | 0)
+#define MT6797_GPIO227__FUNC_CONN_BT_QN (MTK_PIN_NO(227) | 1)
+
+#define MT6797_GPIO228__FUNC_GPIO228 (MTK_PIN_NO(228) | 0)
+#define MT6797_GPIO228__FUNC_CONN_GPS_IP (MTK_PIN_NO(228) | 1)
+
+#define MT6797_GPIO229__FUNC_GPIO229 (MTK_PIN_NO(229) | 0)
+#define MT6797_GPIO229__FUNC_CONN_GPS_IN (MTK_PIN_NO(229) | 1)
+
+#define MT6797_GPIO230__FUNC_GPIO230 (MTK_PIN_NO(230) | 0)
+#define MT6797_GPIO230__FUNC_CONN_GPS_QP (MTK_PIN_NO(230) | 1)
+
+#define MT6797_GPIO231__FUNC_GPIO231 (MTK_PIN_NO(231) | 0)
+#define MT6797_GPIO231__FUNC_CONN_GPS_QN (MTK_PIN_NO(231) | 1)
+
+#define MT6797_GPIO232__FUNC_GPIO232 (MTK_PIN_NO(232) | 0)
+#define MT6797_GPIO232__FUNC_URXD1 (MTK_PIN_NO(232) | 1)
+#define MT6797_GPIO232__FUNC_UTXD1 (MTK_PIN_NO(232) | 2)
+#define MT6797_GPIO232__FUNC_MD_URXD0 (MTK_PIN_NO(232) | 3)
+#define MT6797_GPIO232__FUNC_MD_URXD1 (MTK_PIN_NO(232) | 4)
+#define MT6797_GPIO232__FUNC_MD_URXD2 (MTK_PIN_NO(232) | 5)
+#define MT6797_GPIO232__FUNC_C2K_URXD0 (MTK_PIN_NO(232) | 6)
+#define MT6797_GPIO232__FUNC_C2K_URXD1 (MTK_PIN_NO(232) | 7)
+
+#define MT6797_GPIO233__FUNC_GPIO233 (MTK_PIN_NO(233) | 0)
+#define MT6797_GPIO233__FUNC_UTXD1 (MTK_PIN_NO(233) | 1)
+#define MT6797_GPIO233__FUNC_URXD1 (MTK_PIN_NO(233) | 2)
+#define MT6797_GPIO233__FUNC_MD_UTXD0 (MTK_PIN_NO(233) | 3)
+#define MT6797_GPIO233__FUNC_MD_UTXD1 (MTK_PIN_NO(233) | 4)
+#define MT6797_GPIO233__FUNC_MD_UTXD2 (MTK_PIN_NO(233) | 5)
+#define MT6797_GPIO233__FUNC_C2K_UTXD0 (MTK_PIN_NO(233) | 6)
+#define MT6797_GPIO233__FUNC_C2K_UTXD1 (MTK_PIN_NO(233) | 7)
+
+#define MT6797_GPIO234__FUNC_GPIO234 (MTK_PIN_NO(234) | 0)
+#define MT6797_GPIO234__FUNC_SPI1_CLK_B (MTK_PIN_NO(234) | 1)
+#define MT6797_GPIO234__FUNC_TP_UTXD1_AO (MTK_PIN_NO(234) | 2)
+#define MT6797_GPIO234__FUNC_SCL4_1 (MTK_PIN_NO(234) | 3)
+#define MT6797_GPIO234__FUNC_UTXD0 (MTK_PIN_NO(234) | 4)
+#define MT6797_GPIO234__FUNC_PWM_A (MTK_PIN_NO(234) | 6)
+#define MT6797_GPIO234__FUNC_DBG_MON_A23 (MTK_PIN_NO(234) | 7)
+
+#define MT6797_GPIO235__FUNC_GPIO235 (MTK_PIN_NO(235) | 0)
+#define MT6797_GPIO235__FUNC_SPI1_MI_B (MTK_PIN_NO(235) | 1)
+#define MT6797_GPIO235__FUNC_SPI1_MO_B (MTK_PIN_NO(235) | 2)
+#define MT6797_GPIO235__FUNC_SDA4_1 (MTK_PIN_NO(235) | 3)
+#define MT6797_GPIO235__FUNC_URXD0 (MTK_PIN_NO(235) | 4)
+#define MT6797_GPIO235__FUNC_CLKM0 (MTK_PIN_NO(235) | 6)
+#define MT6797_GPIO235__FUNC_DBG_MON_A24 (MTK_PIN_NO(235) | 7)
+
+#define MT6797_GPIO236__FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
+#define MT6797_GPIO236__FUNC_SPI1_MO_B (MTK_PIN_NO(236) | 1)
+#define MT6797_GPIO236__FUNC_SPI1_MI_B (MTK_PIN_NO(236) | 2)
+#define MT6797_GPIO236__FUNC_SCL5_1 (MTK_PIN_NO(236) | 3)
+#define MT6797_GPIO236__FUNC_URTS0 (MTK_PIN_NO(236) | 4)
+#define MT6797_GPIO236__FUNC_PWM_B (MTK_PIN_NO(236) | 6)
+#define MT6797_GPIO236__FUNC_DBG_MON_A25 (MTK_PIN_NO(236) | 7)
+
+#define MT6797_GPIO237__FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
+#define MT6797_GPIO237__FUNC_SPI1_CS_B (MTK_PIN_NO(237) | 1)
+#define MT6797_GPIO237__FUNC_TP_URXD1_AO (MTK_PIN_NO(237) | 2)
+#define MT6797_GPIO237__FUNC_SDA5_1 (MTK_PIN_NO(237) | 3)
+#define MT6797_GPIO237__FUNC_UCTS0 (MTK_PIN_NO(237) | 4)
+#define MT6797_GPIO237__FUNC_CLKM1 (MTK_PIN_NO(237) | 6)
+#define MT6797_GPIO237__FUNC_DBG_MON_A26 (MTK_PIN_NO(237) | 7)
+
+#define MT6797_GPIO238__FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
+#define MT6797_GPIO238__FUNC_SDA4_0 (MTK_PIN_NO(238) | 1)
+
+#define MT6797_GPIO239__FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
+#define MT6797_GPIO239__FUNC_SCL4_0 (MTK_PIN_NO(239) | 1)
+
+#define MT6797_GPIO240__FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
+#define MT6797_GPIO240__FUNC_SDA5_0 (MTK_PIN_NO(240) | 1)
+
+#define MT6797_GPIO241__FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
+#define MT6797_GPIO241__FUNC_SCL5_0 (MTK_PIN_NO(241) | 1)
+
+#define MT6797_GPIO242__FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
+#define MT6797_GPIO242__FUNC_SPI2_CLK_B (MTK_PIN_NO(242) | 1)
+#define MT6797_GPIO242__FUNC_TP_UTXD2_AO (MTK_PIN_NO(242) | 2)
+#define MT6797_GPIO242__FUNC_SCL4_2 (MTK_PIN_NO(242) | 3)
+#define MT6797_GPIO242__FUNC_UTXD1 (MTK_PIN_NO(242) | 4)
+#define MT6797_GPIO242__FUNC_URTS3 (MTK_PIN_NO(242) | 5)
+#define MT6797_GPIO242__FUNC_PWM_C (MTK_PIN_NO(242) | 6)
+#define MT6797_GPIO242__FUNC_DBG_MON_A27 (MTK_PIN_NO(242) | 7)
+
+#define MT6797_GPIO243__FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
+#define MT6797_GPIO243__FUNC_SPI2_MI_B (MTK_PIN_NO(243) | 1)
+#define MT6797_GPIO243__FUNC_SPI2_MO_B (MTK_PIN_NO(243) | 2)
+#define MT6797_GPIO243__FUNC_SDA4_2 (MTK_PIN_NO(243) | 3)
+#define MT6797_GPIO243__FUNC_URXD1 (MTK_PIN_NO(243) | 4)
+#define MT6797_GPIO243__FUNC_UCTS3 (MTK_PIN_NO(243) | 5)
+#define MT6797_GPIO243__FUNC_CLKM2 (MTK_PIN_NO(243) | 6)
+#define MT6797_GPIO243__FUNC_DBG_MON_A28 (MTK_PIN_NO(243) | 7)
+
+#define MT6797_GPIO244__FUNC_GPIO244 (MTK_PIN_NO(244) | 0)
+#define MT6797_GPIO244__FUNC_SPI2_MO_B (MTK_PIN_NO(244) | 1)
+#define MT6797_GPIO244__FUNC_SPI2_MI_B (MTK_PIN_NO(244) | 2)
+#define MT6797_GPIO244__FUNC_SCL5_2 (MTK_PIN_NO(244) | 3)
+#define MT6797_GPIO244__FUNC_URTS1 (MTK_PIN_NO(244) | 4)
+#define MT6797_GPIO244__FUNC_UTXD3 (MTK_PIN_NO(244) | 5)
+#define MT6797_GPIO244__FUNC_PWM_D (MTK_PIN_NO(244) | 6)
+#define MT6797_GPIO244__FUNC_DBG_MON_A29 (MTK_PIN_NO(244) | 7)
+
+#define MT6797_GPIO245__FUNC_GPIO245 (MTK_PIN_NO(245) | 0)
+#define MT6797_GPIO245__FUNC_SPI2_CS_B (MTK_PIN_NO(245) | 1)
+#define MT6797_GPIO245__FUNC_TP_URXD2_AO (MTK_PIN_NO(245) | 2)
+#define MT6797_GPIO245__FUNC_SDA5_2 (MTK_PIN_NO(245) | 3)
+#define MT6797_GPIO245__FUNC_UCTS1 (MTK_PIN_NO(245) | 4)
+#define MT6797_GPIO245__FUNC_URXD3 (MTK_PIN_NO(245) | 5)
+#define MT6797_GPIO245__FUNC_CLKM3 (MTK_PIN_NO(245) | 6)
+#define MT6797_GPIO245__FUNC_DBG_MON_A30 (MTK_PIN_NO(245) | 7)
+
+#define MT6797_GPIO246__FUNC_GPIO246 (MTK_PIN_NO(246) | 0)
+#define MT6797_GPIO246__FUNC_I2S1_LRCK (MTK_PIN_NO(246) | 1)
+#define MT6797_GPIO246__FUNC_I2S2_LRCK (MTK_PIN_NO(246) | 2)
+#define MT6797_GPIO246__FUNC_I2S0_LRCK (MTK_PIN_NO(246) | 3)
+#define MT6797_GPIO246__FUNC_I2S3_LRCK (MTK_PIN_NO(246) | 4)
+#define MT6797_GPIO246__FUNC_PCM0_SYNC (MTK_PIN_NO(246) | 5)
+#define MT6797_GPIO246__FUNC_SPI5_CLK_C (MTK_PIN_NO(246) | 6)
+#define MT6797_GPIO246__FUNC_DBG_MON_A31 (MTK_PIN_NO(246) | 7)
+
+#define MT6797_GPIO247__FUNC_GPIO247 (MTK_PIN_NO(247) | 0)
+#define MT6797_GPIO247__FUNC_I2S1_BCK (MTK_PIN_NO(247) | 1)
+#define MT6797_GPIO247__FUNC_I2S2_BCK (MTK_PIN_NO(247) | 2)
+#define MT6797_GPIO247__FUNC_I2S0_BCK (MTK_PIN_NO(247) | 3)
+#define MT6797_GPIO247__FUNC_I2S3_BCK (MTK_PIN_NO(247) | 4)
+#define MT6797_GPIO247__FUNC_PCM0_CLK (MTK_PIN_NO(247) | 5)
+#define MT6797_GPIO247__FUNC_SPI5_MI_C (MTK_PIN_NO(247) | 6)
+#define MT6797_GPIO247__FUNC_DBG_MON_A32 (MTK_PIN_NO(247) | 7)
+
+#define MT6797_GPIO248__FUNC_GPIO248 (MTK_PIN_NO(248) | 0)
+/* #define MT6797_GPIO248__FUNC_I2S2_DI (MTK_PIN_NO(248) | 1) */
+#define MT6797_GPIO248__FUNC_I2S2_DI (MTK_PIN_NO(248) | 2)
+/* #define MT6797_GPIO248__FUNC_I2S0_DI (MTK_PIN_NO(248) | 3) */
+#define MT6797_GPIO248__FUNC_I2S0_DI (MTK_PIN_NO(248) | 4)
+#define MT6797_GPIO248__FUNC_PCM0_DI (MTK_PIN_NO(248) | 5)
+#define MT6797_GPIO248__FUNC_SPI5_CS_C (MTK_PIN_NO(248) | 6)
+
+#define MT6797_GPIO249__FUNC_GPIO249 (MTK_PIN_NO(249) | 0)
+/* #define MT6797_GPIO249__FUNC_I2S1_DO (MTK_PIN_NO(249) | 1) */
+#define MT6797_GPIO249__FUNC_I2S1_DO (MTK_PIN_NO(249) | 2)
+/* #define MT6797_GPIO249__FUNC_I2S3_DO (MTK_PIN_NO(249) | 3) */
+#define MT6797_GPIO249__FUNC_I2S3_DO (MTK_PIN_NO(249) | 4)
+#define MT6797_GPIO249__FUNC_PCM0_DO (MTK_PIN_NO(249) | 5)
+#define MT6797_GPIO249__FUNC_SPI5_MO_C (MTK_PIN_NO(249) | 6)
+#define MT6797_GPIO249__FUNC_TRAP_SRAM_PWR_BYPASS (MTK_PIN_NO(249) | 7)
+
+#define MT6797_GPIO250__FUNC_GPIO250 (MTK_PIN_NO(250) | 0)
+#define MT6797_GPIO250__FUNC_SPI3_MI (MTK_PIN_NO(250) | 1)
+#define MT6797_GPIO250__FUNC_SPI3_MO (MTK_PIN_NO(250) | 2)
+#define MT6797_GPIO250__FUNC_IRTX_OUT (MTK_PIN_NO(250) | 3)
+#define MT6797_GPIO250__FUNC_TP_URXD1_AO (MTK_PIN_NO(250) | 6)
+#define MT6797_GPIO250__FUNC_DROP_ZONE (MTK_PIN_NO(250) | 7)
+
+#define MT6797_GPIO251__FUNC_GPIO251 (MTK_PIN_NO(251) | 0)
+#define MT6797_GPIO251__FUNC_SPI3_MO (MTK_PIN_NO(251) | 1)
+#define MT6797_GPIO251__FUNC_SPI3_MI (MTK_PIN_NO(251) | 2)
+#define MT6797_GPIO251__FUNC_CMFLASH (MTK_PIN_NO(251) | 3)
+#define MT6797_GPIO251__FUNC_TP_UTXD1_AO (MTK_PIN_NO(251) | 6)
+#define MT6797_GPIO251__FUNC_C2K_RTCK (MTK_PIN_NO(251) | 7)
+
+#define MT6797_GPIO252__FUNC_GPIO252 (MTK_PIN_NO(252) | 0)
+#define MT6797_GPIO252__FUNC_SPI3_CLK (MTK_PIN_NO(252) | 1)
+#define MT6797_GPIO252__FUNC_SCL0_4 (MTK_PIN_NO(252) | 2)
+#define MT6797_GPIO252__FUNC_PWM_D (MTK_PIN_NO(252) | 3)
+#define MT6797_GPIO252__FUNC_C2K_TMS (MTK_PIN_NO(252) | 7)
+
+#define MT6797_GPIO253__FUNC_GPIO253 (MTK_PIN_NO(253) | 0)
+#define MT6797_GPIO253__FUNC_SPI3_CS (MTK_PIN_NO(253) | 1)
+#define MT6797_GPIO253__FUNC_SDA0_4 (MTK_PIN_NO(253) | 2)
+#define MT6797_GPIO253__FUNC_PWM_A (MTK_PIN_NO(253) | 3)
+#define MT6797_GPIO253__FUNC_C2K_TCK (MTK_PIN_NO(253) | 7)
+
+#define MT6797_GPIO254__FUNC_GPIO254 (MTK_PIN_NO(254) | 0)
+#define MT6797_GPIO254__FUNC_I2S1_MCK (MTK_PIN_NO(254) | 1)
+#define MT6797_GPIO254__FUNC_I2S2_MCK (MTK_PIN_NO(254) | 2)
+#define MT6797_GPIO254__FUNC_I2S0_MCK (MTK_PIN_NO(254) | 3)
+#define MT6797_GPIO254__FUNC_I2S3_MCK (MTK_PIN_NO(254) | 4)
+#define MT6797_GPIO254__FUNC_CLKM0 (MTK_PIN_NO(254) | 5)
+#define MT6797_GPIO254__FUNC_C2K_TDI (MTK_PIN_NO(254) | 7)
+
+#define MT6797_GPIO255__FUNC_GPIO255 (MTK_PIN_NO(255) | 0)
+#define MT6797_GPIO255__FUNC_CLKM1 (MTK_PIN_NO(255) | 1)
+#define MT6797_GPIO255__FUNC_DISP_PWM (MTK_PIN_NO(255) | 2)
+#define MT6797_GPIO255__FUNC_PWM_B (MTK_PIN_NO(255) | 3)
+#define MT6797_GPIO255__FUNC_TP_GPIO1_AO (MTK_PIN_NO(255) | 6)
+#define MT6797_GPIO255__FUNC_C2K_TDO (MTK_PIN_NO(255) | 7)
+
+#define MT6797_GPIO256__FUNC_GPIO256 (MTK_PIN_NO(256) | 0)
+#define MT6797_GPIO256__FUNC_CLKM2 (MTK_PIN_NO(256) | 1)
+#define MT6797_GPIO256__FUNC_IRTX_OUT (MTK_PIN_NO(256) | 2)
+#define MT6797_GPIO256__FUNC_PWM_C (MTK_PIN_NO(256) | 3)
+#define MT6797_GPIO256__FUNC_TP_GPIO0_AO (MTK_PIN_NO(256) | 6)
+#define MT6797_GPIO256__FUNC_C2K_NTRST (MTK_PIN_NO(256) | 7)
+
+#define MT6797_GPIO257__FUNC_GPIO257 (MTK_PIN_NO(257) | 0)
+#define MT6797_GPIO257__FUNC_IO_JTAG_TMS (MTK_PIN_NO(257) | 1)
+#define MT6797_GPIO257__FUNC_LTE_JTAG_TMS (MTK_PIN_NO(257) | 2)
+#define MT6797_GPIO257__FUNC_DFD_TMS (MTK_PIN_NO(257) | 3)
+#define MT6797_GPIO257__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(257) | 4)
+#define MT6797_GPIO257__FUNC_ANC_JTAG_TMS (MTK_PIN_NO(257) | 5)
+#define MT6797_GPIO257__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(257) | 6)
+#define MT6797_GPIO257__FUNC_C2K_DM_OTMS (MTK_PIN_NO(257) | 7)
+
+#define MT6797_GPIO258__FUNC_GPIO258 (MTK_PIN_NO(258) | 0)
+#define MT6797_GPIO258__FUNC_IO_JTAG_TCK (MTK_PIN_NO(258) | 1)
+#define MT6797_GPIO258__FUNC_LTE_JTAG_TCK (MTK_PIN_NO(258) | 2)
+#define MT6797_GPIO258__FUNC_DFD_TCK_XI (MTK_PIN_NO(258) | 3)
+#define MT6797_GPIO258__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(258) | 4)
+#define MT6797_GPIO258__FUNC_ANC_JTAG_TCK (MTK_PIN_NO(258) | 5)
+#define MT6797_GPIO258__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(258) | 6)
+#define MT6797_GPIO258__FUNC_C2K_DM_OTCK (MTK_PIN_NO(258) | 7)
+
+#define MT6797_GPIO259__FUNC_GPIO259 (MTK_PIN_NO(259) | 0)
+#define MT6797_GPIO259__FUNC_IO_JTAG_TDI (MTK_PIN_NO(259) | 1)
+#define MT6797_GPIO259__FUNC_LTE_JTAG_TDI (MTK_PIN_NO(259) | 2)
+#define MT6797_GPIO259__FUNC_DFD_TDI (MTK_PIN_NO(259) | 3)
+#define MT6797_GPIO259__FUNC_ANC_JTAG_TDI (MTK_PIN_NO(259) | 5)
+#define MT6797_GPIO259__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(259) | 6)
+#define MT6797_GPIO259__FUNC_C2K_DM_OTDI (MTK_PIN_NO(259) | 7)
+
+#define MT6797_GPIO260__FUNC_GPIO260 (MTK_PIN_NO(260) | 0)
+#define MT6797_GPIO260__FUNC_IO_JTAG_TDO (MTK_PIN_NO(260) | 1)
+#define MT6797_GPIO260__FUNC_LTE_JTAG_TDO (MTK_PIN_NO(260) | 2)
+#define MT6797_GPIO260__FUNC_DFD_TDO (MTK_PIN_NO(260) | 3)
+#define MT6797_GPIO260__FUNC_ANC_JTAG_TDO (MTK_PIN_NO(260) | 5)
+#define MT6797_GPIO260__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(260) | 6)
+#define MT6797_GPIO260__FUNC_C2K_DM_OTDO (MTK_PIN_NO(260) | 7)
+
+#define MT6797_GPIO261__FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
+#define MT6797_GPIO261__FUNC_LTE_JTAG_TRSTN (MTK_PIN_NO(261) | 2)
+#define MT6797_GPIO261__FUNC_DFD_NTRST (MTK_PIN_NO(261) | 3)
+#define MT6797_GPIO261__FUNC_ANC_JTAG_TRSTN (MTK_PIN_NO(261) | 5)
+#define MT6797_GPIO261__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(261) | 6)
+#define MT6797_GPIO261__FUNC_C2K_DM_JTINTP (MTK_PIN_NO(261) | 7)
+
+#endif /* __DTS_MT6797_PINFUNC_H */
diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h
new file mode 100644
index 0000000..fbfee7e
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h
@@ -0,0 +1,751 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ */
+
+#ifndef _IMX8QXP_PADS_H
+#define _IMX8QXP_PADS_H
+
+/* pin id */
+#define IMX8QXP_PCIE_CTRL0_PERST_B 0
+#define IMX8QXP_PCIE_CTRL0_CLKREQ_B 1
+#define IMX8QXP_PCIE_CTRL0_WAKE_B 2
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3
+#define IMX8QXP_USB_SS3_TC0 4
+#define IMX8QXP_USB_SS3_TC1 5
+#define IMX8QXP_USB_SS3_TC2 6
+#define IMX8QXP_USB_SS3_TC3 7
+#define IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO 8
+#define IMX8QXP_EMMC0_CLK 9
+#define IMX8QXP_EMMC0_CMD 10
+#define IMX8QXP_EMMC0_DATA0 11
+#define IMX8QXP_EMMC0_DATA1 12
+#define IMX8QXP_EMMC0_DATA2 13
+#define IMX8QXP_EMMC0_DATA3 14
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15
+#define IMX8QXP_EMMC0_DATA4 16
+#define IMX8QXP_EMMC0_DATA5 17
+#define IMX8QXP_EMMC0_DATA6 18
+#define IMX8QXP_EMMC0_DATA7 19
+#define IMX8QXP_EMMC0_STROBE 20
+#define IMX8QXP_EMMC0_RESET_B 21
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22
+#define IMX8QXP_USDHC1_RESET_B 23
+#define IMX8QXP_USDHC1_VSELECT 24
+#define IMX8QXP_CTL_NAND_RE_P_N 25
+#define IMX8QXP_USDHC1_WP 26
+#define IMX8QXP_USDHC1_CD_B 27
+#define IMX8QXP_CTL_NAND_DQS_P_N 28
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29
+#define IMX8QXP_USDHC1_CLK 30
+#define IMX8QXP_USDHC1_CMD 31
+#define IMX8QXP_USDHC1_DATA0 32
+#define IMX8QXP_USDHC1_DATA1 33
+#define IMX8QXP_USDHC1_DATA2 34
+#define IMX8QXP_USDHC1_DATA3 35
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3 36
+#define IMX8QXP_ENET0_RGMII_TXC 37
+#define IMX8QXP_ENET0_RGMII_TX_CTL 38
+#define IMX8QXP_ENET0_RGMII_TXD0 39
+#define IMX8QXP_ENET0_RGMII_TXD1 40
+#define IMX8QXP_ENET0_RGMII_TXD2 41
+#define IMX8QXP_ENET0_RGMII_TXD3 42
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43
+#define IMX8QXP_ENET0_RGMII_RXC 44
+#define IMX8QXP_ENET0_RGMII_RX_CTL 45
+#define IMX8QXP_ENET0_RGMII_RXD0 46
+#define IMX8QXP_ENET0_RGMII_RXD1 47
+#define IMX8QXP_ENET0_RGMII_RXD2 48
+#define IMX8QXP_ENET0_RGMII_RXD3 49
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50
+#define IMX8QXP_ENET0_REFCLK_125M_25M 51
+#define IMX8QXP_ENET0_MDIO 52
+#define IMX8QXP_ENET0_MDC 53
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54
+#define IMX8QXP_ESAI0_FSR 55
+#define IMX8QXP_ESAI0_FST 56
+#define IMX8QXP_ESAI0_SCKR 57
+#define IMX8QXP_ESAI0_SCKT 58
+#define IMX8QXP_ESAI0_TX0 59
+#define IMX8QXP_ESAI0_TX1 60
+#define IMX8QXP_ESAI0_TX2_RX3 61
+#define IMX8QXP_ESAI0_TX3_RX2 62
+#define IMX8QXP_ESAI0_TX4_RX1 63
+#define IMX8QXP_ESAI0_TX5_RX0 64
+#define IMX8QXP_SPDIF0_RX 65
+#define IMX8QXP_SPDIF0_TX 66
+#define IMX8QXP_SPDIF0_EXT_CLK 67
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68
+#define IMX8QXP_SPI3_SCK 69
+#define IMX8QXP_SPI3_SDO 70
+#define IMX8QXP_SPI3_SDI 71
+#define IMX8QXP_SPI3_CS0 72
+#define IMX8QXP_SPI3_CS1 73
+#define IMX8QXP_MCLK_IN1 74
+#define IMX8QXP_MCLK_IN0 75
+#define IMX8QXP_MCLK_OUT0 76
+#define IMX8QXP_UART1_TX 77
+#define IMX8QXP_UART1_RX 78
+#define IMX8QXP_UART1_RTS_B 79
+#define IMX8QXP_UART1_CTS_B 80
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81
+#define IMX8QXP_SAI0_TXD 82
+#define IMX8QXP_SAI0_TXC 83
+#define IMX8QXP_SAI0_RXD 84
+#define IMX8QXP_SAI0_TXFS 85
+#define IMX8QXP_SAI1_RXD 86
+#define IMX8QXP_SAI1_RXC 87
+#define IMX8QXP_SAI1_RXFS 88
+#define IMX8QXP_SPI2_CS0 89
+#define IMX8QXP_SPI2_SDO 90
+#define IMX8QXP_SPI2_SDI 91
+#define IMX8QXP_SPI2_SCK 92
+#define IMX8QXP_SPI0_SCK 93
+#define IMX8QXP_SPI0_SDI 94
+#define IMX8QXP_SPI0_SDO 95
+#define IMX8QXP_SPI0_CS1 96
+#define IMX8QXP_SPI0_CS0 97
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98
+#define IMX8QXP_ADC_IN1 99
+#define IMX8QXP_ADC_IN0 100
+#define IMX8QXP_ADC_IN3 101
+#define IMX8QXP_ADC_IN2 102
+#define IMX8QXP_ADC_IN5 103
+#define IMX8QXP_ADC_IN4 104
+#define IMX8QXP_FLEXCAN0_RX 105
+#define IMX8QXP_FLEXCAN0_TX 106
+#define IMX8QXP_FLEXCAN1_RX 107
+#define IMX8QXP_FLEXCAN1_TX 108
+#define IMX8QXP_FLEXCAN2_RX 109
+#define IMX8QXP_FLEXCAN2_TX 110
+#define IMX8QXP_UART0_RX 111
+#define IMX8QXP_UART0_TX 112
+#define IMX8QXP_UART2_TX 113
+#define IMX8QXP_UART2_RX 114
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115
+#define IMX8QXP_MIPI_DSI0_I2C0_SCL 116
+#define IMX8QXP_MIPI_DSI0_I2C0_SDA 117
+#define IMX8QXP_MIPI_DSI0_GPIO0_00 118
+#define IMX8QXP_MIPI_DSI0_GPIO0_01 119
+#define IMX8QXP_MIPI_DSI1_I2C0_SCL 120
+#define IMX8QXP_MIPI_DSI1_I2C0_SDA 121
+#define IMX8QXP_MIPI_DSI1_GPIO0_00 122
+#define IMX8QXP_MIPI_DSI1_GPIO0_01 123
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124
+#define IMX8QXP_JTAG_TRST_B 125
+#define IMX8QXP_PMIC_I2C_SCL 126
+#define IMX8QXP_PMIC_I2C_SDA 127
+#define IMX8QXP_PMIC_INT_B 128
+#define IMX8QXP_SCU_GPIO0_00 129
+#define IMX8QXP_SCU_GPIO0_01 130
+#define IMX8QXP_SCU_PMIC_STANDBY 131
+#define IMX8QXP_SCU_BOOT_MODE0 132
+#define IMX8QXP_SCU_BOOT_MODE1 133
+#define IMX8QXP_SCU_BOOT_MODE2 134
+#define IMX8QXP_SCU_BOOT_MODE3 135
+#define IMX8QXP_CSI_D00 136
+#define IMX8QXP_CSI_D01 137
+#define IMX8QXP_CSI_D02 138
+#define IMX8QXP_CSI_D03 139
+#define IMX8QXP_CSI_D04 140
+#define IMX8QXP_CSI_D05 141
+#define IMX8QXP_CSI_D06 142
+#define IMX8QXP_CSI_D07 143
+#define IMX8QXP_CSI_HSYNC 144
+#define IMX8QXP_CSI_VSYNC 145
+#define IMX8QXP_CSI_PCLK 146
+#define IMX8QXP_CSI_MCLK 147
+#define IMX8QXP_CSI_EN 148
+#define IMX8QXP_CSI_RESET 149
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150
+#define IMX8QXP_MIPI_CSI0_MCLK_OUT 151
+#define IMX8QXP_MIPI_CSI0_I2C0_SCL 152
+#define IMX8QXP_MIPI_CSI0_I2C0_SDA 153
+#define IMX8QXP_MIPI_CSI0_GPIO0_01 154
+#define IMX8QXP_MIPI_CSI0_GPIO0_00 155
+#define IMX8QXP_QSPI0A_DATA0 156
+#define IMX8QXP_QSPI0A_DATA1 157
+#define IMX8QXP_QSPI0A_DATA2 158
+#define IMX8QXP_QSPI0A_DATA3 159
+#define IMX8QXP_QSPI0A_DQS 160
+#define IMX8QXP_QSPI0A_SS0_B 161
+#define IMX8QXP_QSPI0A_SS1_B 162
+#define IMX8QXP_QSPI0A_SCLK 163
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164
+#define IMX8QXP_QSPI0B_SCLK 165
+#define IMX8QXP_QSPI0B_DATA0 166
+#define IMX8QXP_QSPI0B_DATA1 167
+#define IMX8QXP_QSPI0B_DATA2 168
+#define IMX8QXP_QSPI0B_DATA3 169
+#define IMX8QXP_QSPI0B_DQS 170
+#define IMX8QXP_QSPI0B_SS0_B 171
+#define IMX8QXP_QSPI0B_SS1_B 172
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173
+
+/*
+ * format: <pin_id mux_mode>
+ */
+#define IMX8QXP_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8QXP_PCIE_CTRL0_PERST_B 0
+#define IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8QXP_PCIE_CTRL0_PERST_B 4
+#define IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8QXP_PCIE_CTRL0_CLKREQ_B 0
+#define IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8QXP_PCIE_CTRL0_CLKREQ_B 4
+#define IMX8QXP_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8QXP_PCIE_CTRL0_WAKE_B 0
+#define IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8QXP_PCIE_CTRL0_WAKE_B 4
+#define IMX8QXP_USB_SS3_TC0_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC0 0
+#define IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8QXP_USB_SS3_TC0 1
+#define IMX8QXP_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC0 2
+#define IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8QXP_USB_SS3_TC0 4
+#define IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC1 0
+#define IMX8QXP_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC1 1
+#define IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8QXP_USB_SS3_TC1 4
+#define IMX8QXP_USB_SS3_TC2_ADMA_I2C1_SDA IMX8QXP_USB_SS3_TC2 0
+#define IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8QXP_USB_SS3_TC2 1
+#define IMX8QXP_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC2 2
+#define IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8QXP_USB_SS3_TC2 4
+#define IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA IMX8QXP_USB_SS3_TC3 0
+#define IMX8QXP_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC3 1
+#define IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8QXP_USB_SS3_TC3 4
+#define IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK IMX8QXP_EMMC0_CLK 0
+#define IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B IMX8QXP_EMMC0_CLK 1
+#define IMX8QXP_EMMC0_CLK_LSIO_GPIO4_IO07 IMX8QXP_EMMC0_CLK 4
+#define IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD IMX8QXP_EMMC0_CMD 0
+#define IMX8QXP_EMMC0_CMD_CONN_NAND_DQS IMX8QXP_EMMC0_CMD 1
+#define IMX8QXP_EMMC0_CMD_LSIO_GPIO4_IO08 IMX8QXP_EMMC0_CMD 4
+#define IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8QXP_EMMC0_DATA0 0
+#define IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00 IMX8QXP_EMMC0_DATA0 1
+#define IMX8QXP_EMMC0_DATA0_LSIO_GPIO4_IO09 IMX8QXP_EMMC0_DATA0 4
+#define IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8QXP_EMMC0_DATA1 0
+#define IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01 IMX8QXP_EMMC0_DATA1 1
+#define IMX8QXP_EMMC0_DATA1_LSIO_GPIO4_IO10 IMX8QXP_EMMC0_DATA1 4
+#define IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8QXP_EMMC0_DATA2 0
+#define IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02 IMX8QXP_EMMC0_DATA2 1
+#define IMX8QXP_EMMC0_DATA2_LSIO_GPIO4_IO11 IMX8QXP_EMMC0_DATA2 4
+#define IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8QXP_EMMC0_DATA3 0
+#define IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03 IMX8QXP_EMMC0_DATA3 1
+#define IMX8QXP_EMMC0_DATA3_LSIO_GPIO4_IO12 IMX8QXP_EMMC0_DATA3 4
+#define IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8QXP_EMMC0_DATA4 0
+#define IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04 IMX8QXP_EMMC0_DATA4 1
+#define IMX8QXP_EMMC0_DATA4_CONN_EMMC0_WP IMX8QXP_EMMC0_DATA4 3
+#define IMX8QXP_EMMC0_DATA4_LSIO_GPIO4_IO13 IMX8QXP_EMMC0_DATA4 4
+#define IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8QXP_EMMC0_DATA5 0
+#define IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05 IMX8QXP_EMMC0_DATA5 1
+#define IMX8QXP_EMMC0_DATA5_CONN_EMMC0_VSELECT IMX8QXP_EMMC0_DATA5 3
+#define IMX8QXP_EMMC0_DATA5_LSIO_GPIO4_IO14 IMX8QXP_EMMC0_DATA5 4
+#define IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8QXP_EMMC0_DATA6 0
+#define IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06 IMX8QXP_EMMC0_DATA6 1
+#define IMX8QXP_EMMC0_DATA6_CONN_MLB_CLK IMX8QXP_EMMC0_DATA6 3
+#define IMX8QXP_EMMC0_DATA6_LSIO_GPIO4_IO15 IMX8QXP_EMMC0_DATA6 4
+#define IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8QXP_EMMC0_DATA7 0
+#define IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07 IMX8QXP_EMMC0_DATA7 1
+#define IMX8QXP_EMMC0_DATA7_CONN_MLB_SIG IMX8QXP_EMMC0_DATA7 3
+#define IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16 IMX8QXP_EMMC0_DATA7 4
+#define IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8QXP_EMMC0_STROBE 0
+#define IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE IMX8QXP_EMMC0_STROBE 1
+#define IMX8QXP_EMMC0_STROBE_CONN_MLB_DATA IMX8QXP_EMMC0_STROBE 3
+#define IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17 IMX8QXP_EMMC0_STROBE 4
+#define IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8QXP_EMMC0_RESET_B 0
+#define IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B IMX8QXP_EMMC0_RESET_B 1
+#define IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 IMX8QXP_EMMC0_RESET_B 4
+#define IMX8QXP_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8QXP_USDHC1_RESET_B 0
+#define IMX8QXP_USDHC1_RESET_B_CONN_NAND_RE_N IMX8QXP_USDHC1_RESET_B 1
+#define IMX8QXP_USDHC1_RESET_B_ADMA_SPI2_SCK IMX8QXP_USDHC1_RESET_B 2
+#define IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 IMX8QXP_USDHC1_RESET_B 4
+#define IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8QXP_USDHC1_VSELECT 0
+#define IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_P IMX8QXP_USDHC1_VSELECT 1
+#define IMX8QXP_USDHC1_VSELECT_ADMA_SPI2_SDO IMX8QXP_USDHC1_VSELECT 2
+#define IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B IMX8QXP_USDHC1_VSELECT 3
+#define IMX8QXP_USDHC1_VSELECT_LSIO_GPIO4_IO20 IMX8QXP_USDHC1_VSELECT 4
+#define IMX8QXP_USDHC1_WP_CONN_USDHC1_WP IMX8QXP_USDHC1_WP 0
+#define IMX8QXP_USDHC1_WP_CONN_NAND_DQS_N IMX8QXP_USDHC1_WP 1
+#define IMX8QXP_USDHC1_WP_ADMA_SPI2_SDI IMX8QXP_USDHC1_WP 2
+#define IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 IMX8QXP_USDHC1_WP 4
+#define IMX8QXP_USDHC1_CD_B_CONN_USDHC1_CD_B IMX8QXP_USDHC1_CD_B 0
+#define IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS_P IMX8QXP_USDHC1_CD_B 1
+#define IMX8QXP_USDHC1_CD_B_ADMA_SPI2_CS0 IMX8QXP_USDHC1_CD_B 2
+#define IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS IMX8QXP_USDHC1_CD_B 3
+#define IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 IMX8QXP_USDHC1_CD_B 4
+#define IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK IMX8QXP_USDHC1_CLK 0
+#define IMX8QXP_USDHC1_CLK_ADMA_UART3_RX IMX8QXP_USDHC1_CLK 2
+#define IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 IMX8QXP_USDHC1_CLK 4
+#define IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD IMX8QXP_USDHC1_CMD 0
+#define IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B IMX8QXP_USDHC1_CMD 1
+#define IMX8QXP_USDHC1_CMD_ADMA_MQS_R IMX8QXP_USDHC1_CMD 2
+#define IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 IMX8QXP_USDHC1_CMD 4
+#define IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 IMX8QXP_USDHC1_DATA0 0
+#define IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B IMX8QXP_USDHC1_DATA0 1
+#define IMX8QXP_USDHC1_DATA0_ADMA_MQS_L IMX8QXP_USDHC1_DATA0 2
+#define IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 IMX8QXP_USDHC1_DATA0 4
+#define IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 IMX8QXP_USDHC1_DATA1 0
+#define IMX8QXP_USDHC1_DATA1_CONN_NAND_RE_B IMX8QXP_USDHC1_DATA1 1
+#define IMX8QXP_USDHC1_DATA1_ADMA_UART3_TX IMX8QXP_USDHC1_DATA1 2
+#define IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 IMX8QXP_USDHC1_DATA1 4
+#define IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 IMX8QXP_USDHC1_DATA2 0
+#define IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B IMX8QXP_USDHC1_DATA2 1
+#define IMX8QXP_USDHC1_DATA2_ADMA_UART3_CTS_B IMX8QXP_USDHC1_DATA2 2
+#define IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 IMX8QXP_USDHC1_DATA2 4
+#define IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 IMX8QXP_USDHC1_DATA3 0
+#define IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE IMX8QXP_USDHC1_DATA3 1
+#define IMX8QXP_USDHC1_DATA3_ADMA_UART3_RTS_B IMX8QXP_USDHC1_DATA3 2
+#define IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 IMX8QXP_USDHC1_DATA3 4
+#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8QXP_ENET0_RGMII_TXC 0
+#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8QXP_ENET0_RGMII_TXC 1
+#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8QXP_ENET0_RGMII_TXC 2
+#define IMX8QXP_ENET0_RGMII_TXC_CONN_NAND_CE1_B IMX8QXP_ENET0_RGMII_TXC 3
+#define IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 IMX8QXP_ENET0_RGMII_TXC 4
+#define IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8QXP_ENET0_RGMII_TX_CTL 0
+#define IMX8QXP_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B IMX8QXP_ENET0_RGMII_TX_CTL 3
+#define IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 IMX8QXP_ENET0_RGMII_TX_CTL 4
+#define IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8QXP_ENET0_RGMII_TXD0 0
+#define IMX8QXP_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT IMX8QXP_ENET0_RGMII_TXD0 3
+#define IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 IMX8QXP_ENET0_RGMII_TXD0 4
+#define IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8QXP_ENET0_RGMII_TXD1 0
+#define IMX8QXP_ENET0_RGMII_TXD1_CONN_USDHC1_WP IMX8QXP_ENET0_RGMII_TXD1 3
+#define IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 IMX8QXP_ENET0_RGMII_TXD1 4
+#define IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8QXP_ENET0_RGMII_TXD2 0
+#define IMX8QXP_ENET0_RGMII_TXD2_CONN_MLB_CLK IMX8QXP_ENET0_RGMII_TXD2 1
+#define IMX8QXP_ENET0_RGMII_TXD2_CONN_NAND_CE0_B IMX8QXP_ENET0_RGMII_TXD2 2
+#define IMX8QXP_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B IMX8QXP_ENET0_RGMII_TXD2 3
+#define IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 IMX8QXP_ENET0_RGMII_TXD2 4
+#define IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8QXP_ENET0_RGMII_TXD3 0
+#define IMX8QXP_ENET0_RGMII_TXD3_CONN_MLB_SIG IMX8QXP_ENET0_RGMII_TXD3 1
+#define IMX8QXP_ENET0_RGMII_TXD3_CONN_NAND_RE_B IMX8QXP_ENET0_RGMII_TXD3 2
+#define IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 IMX8QXP_ENET0_RGMII_TXD3 4
+#define IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8QXP_ENET0_RGMII_RXC 0
+#define IMX8QXP_ENET0_RGMII_RXC_CONN_MLB_DATA IMX8QXP_ENET0_RGMII_RXC 1
+#define IMX8QXP_ENET0_RGMII_RXC_CONN_NAND_WE_B IMX8QXP_ENET0_RGMII_RXC 2
+#define IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK IMX8QXP_ENET0_RGMII_RXC 3
+#define IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 IMX8QXP_ENET0_RGMII_RXC 4
+#define IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8QXP_ENET0_RGMII_RX_CTL 0
+#define IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD IMX8QXP_ENET0_RGMII_RX_CTL 3
+#define IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 IMX8QXP_ENET0_RGMII_RX_CTL 4
+#define IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8QXP_ENET0_RGMII_RXD0 0
+#define IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 IMX8QXP_ENET0_RGMII_RXD0 3
+#define IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 IMX8QXP_ENET0_RGMII_RXD0 4
+#define IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8QXP_ENET0_RGMII_RXD1 0
+#define IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 IMX8QXP_ENET0_RGMII_RXD1 3
+#define IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 IMX8QXP_ENET0_RGMII_RXD1 4
+#define IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8QXP_ENET0_RGMII_RXD2 0
+#define IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8QXP_ENET0_RGMII_RXD2 1
+#define IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 IMX8QXP_ENET0_RGMII_RXD2 3
+#define IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 IMX8QXP_ENET0_RGMII_RXD2 4
+#define IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8QXP_ENET0_RGMII_RXD3 0
+#define IMX8QXP_ENET0_RGMII_RXD3_CONN_NAND_ALE IMX8QXP_ENET0_RGMII_RXD3 2
+#define IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 IMX8QXP_ENET0_RGMII_RXD3 3
+#define IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 IMX8QXP_ENET0_RGMII_RXD3 4
+#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8QXP_ENET0_REFCLK_125M_25M 0
+#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8QXP_ENET0_REFCLK_125M_25M 1
+#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS IMX8QXP_ENET0_REFCLK_125M_25M 2
+#define IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 IMX8QXP_ENET0_REFCLK_125M_25M 4
+#define IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO IMX8QXP_ENET0_MDIO 0
+#define IMX8QXP_ENET0_MDIO_ADMA_I2C3_SDA IMX8QXP_ENET0_MDIO 1
+#define IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO IMX8QXP_ENET0_MDIO 2
+#define IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 IMX8QXP_ENET0_MDIO 4
+#define IMX8QXP_ENET0_MDC_CONN_ENET0_MDC IMX8QXP_ENET0_MDC 0
+#define IMX8QXP_ENET0_MDC_ADMA_I2C3_SCL IMX8QXP_ENET0_MDC 1
+#define IMX8QXP_ENET0_MDC_CONN_ENET1_MDC IMX8QXP_ENET0_MDC 2
+#define IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 IMX8QXP_ENET0_MDC 4
+#define IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR IMX8QXP_ESAI0_FSR 0
+#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT IMX8QXP_ESAI0_FSR 1
+#define IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 IMX8QXP_ESAI0_FSR 2
+#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC IMX8QXP_ESAI0_FSR 3
+#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_IN IMX8QXP_ESAI0_FSR 4
+#define IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST IMX8QXP_ESAI0_FST 0
+#define IMX8QXP_ESAI0_FST_CONN_MLB_CLK IMX8QXP_ESAI0_FST 1
+#define IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 IMX8QXP_ESAI0_FST 2
+#define IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 IMX8QXP_ESAI0_FST 3
+#define IMX8QXP_ESAI0_FST_LSIO_GPIO0_IO01 IMX8QXP_ESAI0_FST 4
+#define IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR IMX8QXP_ESAI0_SCKR 0
+#define IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 IMX8QXP_ESAI0_SCKR 2
+#define IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL IMX8QXP_ESAI0_SCKR 3
+#define IMX8QXP_ESAI0_SCKR_LSIO_GPIO0_IO02 IMX8QXP_ESAI0_SCKR 4
+#define IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT IMX8QXP_ESAI0_SCKT 0
+#define IMX8QXP_ESAI0_SCKT_CONN_MLB_SIG IMX8QXP_ESAI0_SCKT 1
+#define IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 IMX8QXP_ESAI0_SCKT 2
+#define IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 IMX8QXP_ESAI0_SCKT 3
+#define IMX8QXP_ESAI0_SCKT_LSIO_GPIO0_IO03 IMX8QXP_ESAI0_SCKT 4
+#define IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 IMX8QXP_ESAI0_TX0 0
+#define IMX8QXP_ESAI0_TX0_CONN_MLB_DATA IMX8QXP_ESAI0_TX0 1
+#define IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 IMX8QXP_ESAI0_TX0 2
+#define IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC IMX8QXP_ESAI0_TX0 3
+#define IMX8QXP_ESAI0_TX0_LSIO_GPIO0_IO04 IMX8QXP_ESAI0_TX0 4
+#define IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 IMX8QXP_ESAI0_TX1 0
+#define IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 IMX8QXP_ESAI0_TX1 2
+#define IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 IMX8QXP_ESAI0_TX1 3
+#define IMX8QXP_ESAI0_TX1_LSIO_GPIO0_IO05 IMX8QXP_ESAI0_TX1 4
+#define IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 IMX8QXP_ESAI0_TX2_RX3 0
+#define IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER IMX8QXP_ESAI0_TX2_RX3 1
+#define IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 IMX8QXP_ESAI0_TX2_RX3 2
+#define IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 IMX8QXP_ESAI0_TX2_RX3 3
+#define IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 IMX8QXP_ESAI0_TX2_RX3 4
+#define IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 IMX8QXP_ESAI0_TX3_RX2 0
+#define IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 IMX8QXP_ESAI0_TX3_RX2 2
+#define IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 IMX8QXP_ESAI0_TX3_RX2 3
+#define IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 IMX8QXP_ESAI0_TX3_RX2 4
+#define IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 IMX8QXP_ESAI0_TX4_RX1 0
+#define IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 IMX8QXP_ESAI0_TX4_RX1 2
+#define IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 IMX8QXP_ESAI0_TX4_RX1 3
+#define IMX8QXP_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 IMX8QXP_ESAI0_TX4_RX1 4
+#define IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 IMX8QXP_ESAI0_TX5_RX0 0
+#define IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 IMX8QXP_ESAI0_TX5_RX0 2
+#define IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 IMX8QXP_ESAI0_TX5_RX0 3
+#define IMX8QXP_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 IMX8QXP_ESAI0_TX5_RX0 4
+#define IMX8QXP_SPDIF0_RX_ADMA_SPDIF0_RX IMX8QXP_SPDIF0_RX 0
+#define IMX8QXP_SPDIF0_RX_ADMA_MQS_R IMX8QXP_SPDIF0_RX 1
+#define IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 IMX8QXP_SPDIF0_RX 2
+#define IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 IMX8QXP_SPDIF0_RX 3
+#define IMX8QXP_SPDIF0_RX_LSIO_GPIO0_IO10 IMX8QXP_SPDIF0_RX 4
+#define IMX8QXP_SPDIF0_TX_ADMA_SPDIF0_TX IMX8QXP_SPDIF0_TX 0
+#define IMX8QXP_SPDIF0_TX_ADMA_MQS_L IMX8QXP_SPDIF0_TX 1
+#define IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 IMX8QXP_SPDIF0_TX 2
+#define IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL IMX8QXP_SPDIF0_TX 3
+#define IMX8QXP_SPDIF0_TX_LSIO_GPIO0_IO11 IMX8QXP_SPDIF0_TX 4
+#define IMX8QXP_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK IMX8QXP_SPDIF0_EXT_CLK 0
+#define IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 IMX8QXP_SPDIF0_EXT_CLK 2
+#define IMX8QXP_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M IMX8QXP_SPDIF0_EXT_CLK 3
+#define IMX8QXP_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 IMX8QXP_SPDIF0_EXT_CLK 4
+#define IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK IMX8QXP_SPI3_SCK 0
+#define IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 IMX8QXP_SPI3_SCK 2
+#define IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13 IMX8QXP_SPI3_SCK 4
+#define IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO IMX8QXP_SPI3_SDO 0
+#define IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 IMX8QXP_SPI3_SDO 2
+#define IMX8QXP_SPI3_SDO_LSIO_GPIO0_IO14 IMX8QXP_SPI3_SDO 4
+#define IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI IMX8QXP_SPI3_SDI 0
+#define IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 IMX8QXP_SPI3_SDI 2
+#define IMX8QXP_SPI3_SDI_LSIO_GPIO0_IO15 IMX8QXP_SPI3_SDI 4
+#define IMX8QXP_SPI3_CS0_ADMA_SPI3_CS0 IMX8QXP_SPI3_CS0 0
+#define IMX8QXP_SPI3_CS0_ADMA_ACM_MCLK_OUT1 IMX8QXP_SPI3_CS0 1
+#define IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC IMX8QXP_SPI3_CS0 2
+#define IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 IMX8QXP_SPI3_CS0 4
+#define IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1 IMX8QXP_SPI3_CS1 0
+#define IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL IMX8QXP_SPI3_CS1 1
+#define IMX8QXP_SPI3_CS1_ADMA_LCDIF_RESET IMX8QXP_SPI3_CS1 2
+#define IMX8QXP_SPI3_CS1_ADMA_SPI2_CS0 IMX8QXP_SPI3_CS1 3
+#define IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 IMX8QXP_SPI3_CS1 4
+#define IMX8QXP_MCLK_IN1_ADMA_ACM_MCLK_IN1 IMX8QXP_MCLK_IN1 0
+#define IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA IMX8QXP_MCLK_IN1 1
+#define IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN IMX8QXP_MCLK_IN1 2
+#define IMX8QXP_MCLK_IN1_ADMA_SPI2_SCK IMX8QXP_MCLK_IN1 3
+#define IMX8QXP_MCLK_IN1_ADMA_LCDIF_D17 IMX8QXP_MCLK_IN1 4
+#define IMX8QXP_MCLK_IN0_ADMA_ACM_MCLK_IN0 IMX8QXP_MCLK_IN0 0
+#define IMX8QXP_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK IMX8QXP_MCLK_IN0 1
+#define IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC IMX8QXP_MCLK_IN0 2
+#define IMX8QXP_MCLK_IN0_ADMA_SPI2_SDI IMX8QXP_MCLK_IN0 3
+#define IMX8QXP_MCLK_IN0_LSIO_GPIO0_IO19 IMX8QXP_MCLK_IN0 4
+#define IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 IMX8QXP_MCLK_OUT0 0
+#define IMX8QXP_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK IMX8QXP_MCLK_OUT0 1
+#define IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK IMX8QXP_MCLK_OUT0 2
+#define IMX8QXP_MCLK_OUT0_ADMA_SPI2_SDO IMX8QXP_MCLK_OUT0 3
+#define IMX8QXP_MCLK_OUT0_LSIO_GPIO0_IO20 IMX8QXP_MCLK_OUT0 4
+#define IMX8QXP_UART1_TX_ADMA_UART1_TX IMX8QXP_UART1_TX 0
+#define IMX8QXP_UART1_TX_LSIO_PWM0_OUT IMX8QXP_UART1_TX 1
+#define IMX8QXP_UART1_TX_LSIO_GPT0_CAPTURE IMX8QXP_UART1_TX 2
+#define IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 IMX8QXP_UART1_TX 4
+#define IMX8QXP_UART1_RX_ADMA_UART1_RX IMX8QXP_UART1_RX 0
+#define IMX8QXP_UART1_RX_LSIO_PWM1_OUT IMX8QXP_UART1_RX 1
+#define IMX8QXP_UART1_RX_LSIO_GPT0_COMPARE IMX8QXP_UART1_RX 2
+#define IMX8QXP_UART1_RX_LSIO_GPT1_CLK IMX8QXP_UART1_RX 3
+#define IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 IMX8QXP_UART1_RX 4
+#define IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B IMX8QXP_UART1_RTS_B 0
+#define IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT IMX8QXP_UART1_RTS_B 1
+#define IMX8QXP_UART1_RTS_B_ADMA_LCDIF_D16 IMX8QXP_UART1_RTS_B 2
+#define IMX8QXP_UART1_RTS_B_LSIO_GPT1_CAPTURE IMX8QXP_UART1_RTS_B 3
+#define IMX8QXP_UART1_RTS_B_LSIO_GPT0_CLK IMX8QXP_UART1_RTS_B 4
+#define IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B IMX8QXP_UART1_CTS_B 0
+#define IMX8QXP_UART1_CTS_B_LSIO_PWM3_OUT IMX8QXP_UART1_CTS_B 1
+#define IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 IMX8QXP_UART1_CTS_B 2
+#define IMX8QXP_UART1_CTS_B_LSIO_GPT1_COMPARE IMX8QXP_UART1_CTS_B 3
+#define IMX8QXP_UART1_CTS_B_LSIO_GPIO0_IO24 IMX8QXP_UART1_CTS_B 4
+#define IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD IMX8QXP_SAI0_TXD 0
+#define IMX8QXP_SAI0_TXD_ADMA_SAI1_RXC IMX8QXP_SAI0_TXD 1
+#define IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO IMX8QXP_SAI0_TXD 2
+#define IMX8QXP_SAI0_TXD_ADMA_LCDIF_D18 IMX8QXP_SAI0_TXD 3
+#define IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 IMX8QXP_SAI0_TXD 4
+#define IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC IMX8QXP_SAI0_TXC 0
+#define IMX8QXP_SAI0_TXC_ADMA_SAI1_TXD IMX8QXP_SAI0_TXC 1
+#define IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI IMX8QXP_SAI0_TXC 2
+#define IMX8QXP_SAI0_TXC_ADMA_LCDIF_D19 IMX8QXP_SAI0_TXC 3
+#define IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 IMX8QXP_SAI0_TXC 4
+#define IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD IMX8QXP_SAI0_RXD 0
+#define IMX8QXP_SAI0_RXD_ADMA_SAI1_RXFS IMX8QXP_SAI0_RXD 1
+#define IMX8QXP_SAI0_RXD_ADMA_SPI1_CS0 IMX8QXP_SAI0_RXD 2
+#define IMX8QXP_SAI0_RXD_ADMA_LCDIF_D20 IMX8QXP_SAI0_RXD 3
+#define IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 IMX8QXP_SAI0_RXD 4
+#define IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS IMX8QXP_SAI0_TXFS 0
+#define IMX8QXP_SAI0_TXFS_ADMA_SPI2_CS1 IMX8QXP_SAI0_TXFS 1
+#define IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK IMX8QXP_SAI0_TXFS 2
+#define IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 IMX8QXP_SAI0_TXFS 4
+#define IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD IMX8QXP_SAI1_RXD 0
+#define IMX8QXP_SAI1_RXD_ADMA_SAI0_RXFS IMX8QXP_SAI1_RXD 1
+#define IMX8QXP_SAI1_RXD_ADMA_SPI1_CS1 IMX8QXP_SAI1_RXD 2
+#define IMX8QXP_SAI1_RXD_ADMA_LCDIF_D21 IMX8QXP_SAI1_RXD 3
+#define IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 IMX8QXP_SAI1_RXD 4
+#define IMX8QXP_SAI1_RXC_ADMA_SAI1_RXC IMX8QXP_SAI1_RXC 0
+#define IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC IMX8QXP_SAI1_RXC 1
+#define IMX8QXP_SAI1_RXC_ADMA_LCDIF_D22 IMX8QXP_SAI1_RXC 3
+#define IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 IMX8QXP_SAI1_RXC 4
+#define IMX8QXP_SAI1_RXFS_ADMA_SAI1_RXFS IMX8QXP_SAI1_RXFS 0
+#define IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS IMX8QXP_SAI1_RXFS 1
+#define IMX8QXP_SAI1_RXFS_ADMA_LCDIF_D23 IMX8QXP_SAI1_RXFS 3
+#define IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 IMX8QXP_SAI1_RXFS 4
+#define IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 IMX8QXP_SPI2_CS0 0
+#define IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 IMX8QXP_SPI2_CS0 4
+#define IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO IMX8QXP_SPI2_SDO 0
+#define IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 IMX8QXP_SPI2_SDO 4
+#define IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI IMX8QXP_SPI2_SDI 0
+#define IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 IMX8QXP_SPI2_SDI 4
+#define IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK IMX8QXP_SPI2_SCK 0
+#define IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 IMX8QXP_SPI2_SCK 4
+#define IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK IMX8QXP_SPI0_SCK 0
+#define IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC IMX8QXP_SPI0_SCK 1
+#define IMX8QXP_SPI0_SCK_M40_I2C0_SCL IMX8QXP_SPI0_SCK 2
+#define IMX8QXP_SPI0_SCK_M40_GPIO0_IO00 IMX8QXP_SPI0_SCK 3
+#define IMX8QXP_SPI0_SCK_LSIO_GPIO1_IO04 IMX8QXP_SPI0_SCK 4
+#define IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI IMX8QXP_SPI0_SDI 0
+#define IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD IMX8QXP_SPI0_SDI 1
+#define IMX8QXP_SPI0_SDI_M40_TPM0_CH0 IMX8QXP_SPI0_SDI 2
+#define IMX8QXP_SPI0_SDI_M40_GPIO0_IO02 IMX8QXP_SPI0_SDI 3
+#define IMX8QXP_SPI0_SDI_LSIO_GPIO1_IO05 IMX8QXP_SPI0_SDI 4
+#define IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO IMX8QXP_SPI0_SDO 0
+#define IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS IMX8QXP_SPI0_SDO 1
+#define IMX8QXP_SPI0_SDO_M40_I2C0_SDA IMX8QXP_SPI0_SDO 2
+#define IMX8QXP_SPI0_SDO_M40_GPIO0_IO01 IMX8QXP_SPI0_SDO 3
+#define IMX8QXP_SPI0_SDO_LSIO_GPIO1_IO06 IMX8QXP_SPI0_SDO 4
+#define IMX8QXP_SPI0_CS1_ADMA_SPI0_CS1 IMX8QXP_SPI0_CS1 0
+#define IMX8QXP_SPI0_CS1_ADMA_SAI0_RXC IMX8QXP_SPI0_CS1 1
+#define IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD IMX8QXP_SPI0_CS1 2
+#define IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT IMX8QXP_SPI0_CS1 3
+#define IMX8QXP_SPI0_CS1_LSIO_GPIO1_IO07 IMX8QXP_SPI0_CS1 4
+#define IMX8QXP_SPI0_CS0_ADMA_SPI0_CS0 IMX8QXP_SPI0_CS0 0
+#define IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD IMX8QXP_SPI0_CS0 1
+#define IMX8QXP_SPI0_CS0_M40_TPM0_CH1 IMX8QXP_SPI0_CS0 2
+#define IMX8QXP_SPI0_CS0_M40_GPIO0_IO03 IMX8QXP_SPI0_CS0 3
+#define IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 IMX8QXP_SPI0_CS0 4
+#define IMX8QXP_ADC_IN1_ADMA_ADC_IN1 IMX8QXP_ADC_IN1 0
+#define IMX8QXP_ADC_IN1_M40_I2C0_SDA IMX8QXP_ADC_IN1 1
+#define IMX8QXP_ADC_IN1_M40_GPIO0_IO01 IMX8QXP_ADC_IN1 2
+#define IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 IMX8QXP_ADC_IN1 4
+#define IMX8QXP_ADC_IN0_ADMA_ADC_IN0 IMX8QXP_ADC_IN0 0
+#define IMX8QXP_ADC_IN0_M40_I2C0_SCL IMX8QXP_ADC_IN0 1
+#define IMX8QXP_ADC_IN0_M40_GPIO0_IO00 IMX8QXP_ADC_IN0 2
+#define IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 IMX8QXP_ADC_IN0 4
+#define IMX8QXP_ADC_IN3_ADMA_ADC_IN3 IMX8QXP_ADC_IN3 0
+#define IMX8QXP_ADC_IN3_M40_UART0_TX IMX8QXP_ADC_IN3 1
+#define IMX8QXP_ADC_IN3_M40_GPIO0_IO03 IMX8QXP_ADC_IN3 2
+#define IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 IMX8QXP_ADC_IN3 3
+#define IMX8QXP_ADC_IN3_LSIO_GPIO1_IO11 IMX8QXP_ADC_IN3 4
+#define IMX8QXP_ADC_IN2_ADMA_ADC_IN2 IMX8QXP_ADC_IN2 0
+#define IMX8QXP_ADC_IN2_M40_UART0_RX IMX8QXP_ADC_IN2 1
+#define IMX8QXP_ADC_IN2_M40_GPIO0_IO02 IMX8QXP_ADC_IN2 2
+#define IMX8QXP_ADC_IN2_ADMA_ACM_MCLK_IN0 IMX8QXP_ADC_IN2 3
+#define IMX8QXP_ADC_IN2_LSIO_GPIO1_IO12 IMX8QXP_ADC_IN2 4
+#define IMX8QXP_ADC_IN5_ADMA_ADC_IN5 IMX8QXP_ADC_IN5 0
+#define IMX8QXP_ADC_IN5_M40_TPM0_CH1 IMX8QXP_ADC_IN5 1
+#define IMX8QXP_ADC_IN5_M40_GPIO0_IO05 IMX8QXP_ADC_IN5 2
+#define IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 IMX8QXP_ADC_IN5 4
+#define IMX8QXP_ADC_IN4_ADMA_ADC_IN4 IMX8QXP_ADC_IN4 0
+#define IMX8QXP_ADC_IN4_M40_TPM0_CH0 IMX8QXP_ADC_IN4 1
+#define IMX8QXP_ADC_IN4_M40_GPIO0_IO04 IMX8QXP_ADC_IN4 2
+#define IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 IMX8QXP_ADC_IN4 4
+#define IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX IMX8QXP_FLEXCAN0_RX 0
+#define IMX8QXP_FLEXCAN0_RX_ADMA_SAI2_RXC IMX8QXP_FLEXCAN0_RX 1
+#define IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B IMX8QXP_FLEXCAN0_RX 2
+#define IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC IMX8QXP_FLEXCAN0_RX 3
+#define IMX8QXP_FLEXCAN0_RX_LSIO_GPIO1_IO15 IMX8QXP_FLEXCAN0_RX 4
+#define IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX IMX8QXP_FLEXCAN0_TX 0
+#define IMX8QXP_FLEXCAN0_TX_ADMA_SAI2_RXD IMX8QXP_FLEXCAN0_TX 1
+#define IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B IMX8QXP_FLEXCAN0_TX 2
+#define IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS IMX8QXP_FLEXCAN0_TX 3
+#define IMX8QXP_FLEXCAN0_TX_LSIO_GPIO1_IO16 IMX8QXP_FLEXCAN0_TX 4
+#define IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX IMX8QXP_FLEXCAN1_RX 0
+#define IMX8QXP_FLEXCAN1_RX_ADMA_SAI2_RXFS IMX8QXP_FLEXCAN1_RX 1
+#define IMX8QXP_FLEXCAN1_RX_ADMA_FTM_CH2 IMX8QXP_FLEXCAN1_RX 2
+#define IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD IMX8QXP_FLEXCAN1_RX 3
+#define IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 IMX8QXP_FLEXCAN1_RX 4
+#define IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX IMX8QXP_FLEXCAN1_TX 0
+#define IMX8QXP_FLEXCAN1_TX_ADMA_SAI3_RXC IMX8QXP_FLEXCAN1_TX 1
+#define IMX8QXP_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 IMX8QXP_FLEXCAN1_TX 2
+#define IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD IMX8QXP_FLEXCAN1_TX 3
+#define IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 IMX8QXP_FLEXCAN1_TX 4
+#define IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX IMX8QXP_FLEXCAN2_RX 0
+#define IMX8QXP_FLEXCAN2_RX_ADMA_SAI3_RXD IMX8QXP_FLEXCAN2_RX 1
+#define IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX IMX8QXP_FLEXCAN2_RX 2
+#define IMX8QXP_FLEXCAN2_RX_ADMA_SAI1_RXFS IMX8QXP_FLEXCAN2_RX 3
+#define IMX8QXP_FLEXCAN2_RX_LSIO_GPIO1_IO19 IMX8QXP_FLEXCAN2_RX 4
+#define IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX IMX8QXP_FLEXCAN2_TX 0
+#define IMX8QXP_FLEXCAN2_TX_ADMA_SAI3_RXFS IMX8QXP_FLEXCAN2_TX 1
+#define IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX IMX8QXP_FLEXCAN2_TX 2
+#define IMX8QXP_FLEXCAN2_TX_ADMA_SAI1_RXC IMX8QXP_FLEXCAN2_TX 3
+#define IMX8QXP_FLEXCAN2_TX_LSIO_GPIO1_IO20 IMX8QXP_FLEXCAN2_TX 4
+#define IMX8QXP_UART0_RX_ADMA_UART0_RX IMX8QXP_UART0_RX 0
+#define IMX8QXP_UART0_RX_ADMA_MQS_R IMX8QXP_UART0_RX 1
+#define IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX IMX8QXP_UART0_RX 2
+#define IMX8QXP_UART0_RX_LSIO_GPIO1_IO21 IMX8QXP_UART0_RX 4
+#define IMX8QXP_UART0_TX_ADMA_UART0_TX IMX8QXP_UART0_TX 0
+#define IMX8QXP_UART0_TX_ADMA_MQS_L IMX8QXP_UART0_TX 1
+#define IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX IMX8QXP_UART0_TX 2
+#define IMX8QXP_UART0_TX_LSIO_GPIO1_IO22 IMX8QXP_UART0_TX 4
+#define IMX8QXP_UART2_TX_ADMA_UART2_TX IMX8QXP_UART2_TX 0
+#define IMX8QXP_UART2_TX_ADMA_FTM_CH1 IMX8QXP_UART2_TX 1
+#define IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX IMX8QXP_UART2_TX 2
+#define IMX8QXP_UART2_TX_LSIO_GPIO1_IO23 IMX8QXP_UART2_TX 4
+#define IMX8QXP_UART2_RX_ADMA_UART2_RX IMX8QXP_UART2_RX 0
+#define IMX8QXP_UART2_RX_ADMA_FTM_CH0 IMX8QXP_UART2_RX 1
+#define IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX IMX8QXP_UART2_RX 2
+#define IMX8QXP_UART2_RX_LSIO_GPIO1_IO24 IMX8QXP_UART2_RX 4
+#define IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL IMX8QXP_MIPI_DSI0_I2C0_SCL 0
+#define IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 IMX8QXP_MIPI_DSI0_I2C0_SCL 1
+#define IMX8QXP_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 IMX8QXP_MIPI_DSI0_I2C0_SCL 4
+#define IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA IMX8QXP_MIPI_DSI0_I2C0_SDA 0
+#define IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 IMX8QXP_MIPI_DSI0_I2C0_SDA 1
+#define IMX8QXP_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 IMX8QXP_MIPI_DSI0_I2C0_SDA 4
+#define IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 IMX8QXP_MIPI_DSI0_GPIO0_00 0
+#define IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL IMX8QXP_MIPI_DSI0_GPIO0_00 1
+#define IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT IMX8QXP_MIPI_DSI0_GPIO0_00 2
+#define IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 IMX8QXP_MIPI_DSI0_GPIO0_00 4
+#define IMX8QXP_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 IMX8QXP_MIPI_DSI0_GPIO0_01 0
+#define IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA IMX8QXP_MIPI_DSI0_GPIO0_01 1
+#define IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 IMX8QXP_MIPI_DSI0_GPIO0_01 4
+#define IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL IMX8QXP_MIPI_DSI1_I2C0_SCL 0
+#define IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 IMX8QXP_MIPI_DSI1_I2C0_SCL 1
+#define IMX8QXP_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 IMX8QXP_MIPI_DSI1_I2C0_SCL 4
+#define IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA IMX8QXP_MIPI_DSI1_I2C0_SDA 0
+#define IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 IMX8QXP_MIPI_DSI1_I2C0_SDA 1
+#define IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 IMX8QXP_MIPI_DSI1_I2C0_SDA 4
+#define IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 IMX8QXP_MIPI_DSI1_GPIO0_00 0
+#define IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL IMX8QXP_MIPI_DSI1_GPIO0_00 1
+#define IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT IMX8QXP_MIPI_DSI1_GPIO0_00 2
+#define IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 IMX8QXP_MIPI_DSI1_GPIO0_00 4
+#define IMX8QXP_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 IMX8QXP_MIPI_DSI1_GPIO0_01 0
+#define IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA IMX8QXP_MIPI_DSI1_GPIO0_01 1
+#define IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 IMX8QXP_MIPI_DSI1_GPIO0_01 4
+#define IMX8QXP_JTAG_TRST_B_SCU_JTAG_TRST_B IMX8QXP_JTAG_TRST_B 0
+#define IMX8QXP_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT IMX8QXP_JTAG_TRST_B 1
+#define IMX8QXP_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8QXP_PMIC_I2C_SCL 0
+#define IMX8QXP_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON IMX8QXP_PMIC_I2C_SCL 1
+#define IMX8QXP_PMIC_I2C_SCL_LSIO_GPIO2_IO01 IMX8QXP_PMIC_I2C_SCL 4
+#define IMX8QXP_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8QXP_PMIC_I2C_SDA 0
+#define IMX8QXP_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON IMX8QXP_PMIC_I2C_SDA 1
+#define IMX8QXP_PMIC_I2C_SDA_LSIO_GPIO2_IO02 IMX8QXP_PMIC_I2C_SDA 4
+#define IMX8QXP_PMIC_INT_B_SCU_DIMX8QXPMIC_INT_B IMX8QXP_PMIC_INT_B 0
+#define IMX8QXP_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8QXP_SCU_GPIO0_00 0
+#define IMX8QXP_SCU_GPIO0_00_SCU_UART0_RX IMX8QXP_SCU_GPIO0_00 1
+#define IMX8QXP_SCU_GPIO0_00_M40_UART0_RX IMX8QXP_SCU_GPIO0_00 2
+#define IMX8QXP_SCU_GPIO0_00_ADMA_UART3_RX IMX8QXP_SCU_GPIO0_00 3
+#define IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 IMX8QXP_SCU_GPIO0_00 4
+#define IMX8QXP_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8QXP_SCU_GPIO0_01 0
+#define IMX8QXP_SCU_GPIO0_01_SCU_UART0_TX IMX8QXP_SCU_GPIO0_01 1
+#define IMX8QXP_SCU_GPIO0_01_M40_UART0_TX IMX8QXP_SCU_GPIO0_01 2
+#define IMX8QXP_SCU_GPIO0_01_ADMA_UART3_TX IMX8QXP_SCU_GPIO0_01 3
+#define IMX8QXP_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT IMX8QXP_SCU_GPIO0_01 4
+#define IMX8QXP_SCU_PMIC_STANDBY_SCU_DIMX8QXPMIC_STANDBY IMX8QXP_SCU_PMIC_STANDBY 0
+#define IMX8QXP_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8QXP_SCU_BOOT_MODE0 0
+#define IMX8QXP_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8QXP_SCU_BOOT_MODE1 0
+#define IMX8QXP_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8QXP_SCU_BOOT_MODE2 0
+#define IMX8QXP_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA IMX8QXP_SCU_BOOT_MODE2 1
+#define IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 IMX8QXP_SCU_BOOT_MODE3 0
+#define IMX8QXP_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL IMX8QXP_SCU_BOOT_MODE3 1
+#define IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8QXP_SCU_BOOT_MODE3 3
+#define IMX8QXP_CSI_D00_CI_PI_D02 IMX8QXP_CSI_D00 0
+#define IMX8QXP_CSI_D00_ADMA_SAI0_RXC IMX8QXP_CSI_D00 2
+#define IMX8QXP_CSI_D01_CI_PI_D03 IMX8QXP_CSI_D01 0
+#define IMX8QXP_CSI_D01_ADMA_SAI0_RXD IMX8QXP_CSI_D01 2
+#define IMX8QXP_CSI_D02_CI_PI_D04 IMX8QXP_CSI_D02 0
+#define IMX8QXP_CSI_D02_ADMA_SAI0_RXFS IMX8QXP_CSI_D02 2
+#define IMX8QXP_CSI_D03_CI_PI_D05 IMX8QXP_CSI_D03 0
+#define IMX8QXP_CSI_D03_ADMA_SAI2_RXC IMX8QXP_CSI_D03 2
+#define IMX8QXP_CSI_D04_CI_PI_D06 IMX8QXP_CSI_D04 0
+#define IMX8QXP_CSI_D04_ADMA_SAI2_RXD IMX8QXP_CSI_D04 2
+#define IMX8QXP_CSI_D05_CI_PI_D07 IMX8QXP_CSI_D05 0
+#define IMX8QXP_CSI_D05_ADMA_SAI2_RXFS IMX8QXP_CSI_D05 2
+#define IMX8QXP_CSI_D06_CI_PI_D08 IMX8QXP_CSI_D06 0
+#define IMX8QXP_CSI_D06_ADMA_SAI3_RXC IMX8QXP_CSI_D06 2
+#define IMX8QXP_CSI_D07_CI_PI_D09 IMX8QXP_CSI_D07 0
+#define IMX8QXP_CSI_D07_ADMA_SAI3_RXD IMX8QXP_CSI_D07 2
+#define IMX8QXP_CSI_HSYNC_CI_PI_HSYNC IMX8QXP_CSI_HSYNC 0
+#define IMX8QXP_CSI_HSYNC_CI_PI_D00 IMX8QXP_CSI_HSYNC 1
+#define IMX8QXP_CSI_HSYNC_ADMA_SAI3_RXFS IMX8QXP_CSI_HSYNC 2
+#define IMX8QXP_CSI_VSYNC_CI_PI_VSYNC IMX8QXP_CSI_VSYNC 0
+#define IMX8QXP_CSI_VSYNC_CI_PI_D01 IMX8QXP_CSI_VSYNC 1
+#define IMX8QXP_CSI_PCLK_CI_PI_PCLK IMX8QXP_CSI_PCLK 0
+#define IMX8QXP_CSI_PCLK_MIPI_CSI0_I2C0_SCL IMX8QXP_CSI_PCLK 1
+#define IMX8QXP_CSI_PCLK_ADMA_SPI1_SCK IMX8QXP_CSI_PCLK 3
+#define IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 IMX8QXP_CSI_PCLK 4
+#define IMX8QXP_CSI_MCLK_CI_PI_MCLK IMX8QXP_CSI_MCLK 0
+#define IMX8QXP_CSI_MCLK_MIPI_CSI0_I2C0_SDA IMX8QXP_CSI_MCLK 1
+#define IMX8QXP_CSI_MCLK_ADMA_SPI1_SDO IMX8QXP_CSI_MCLK 3
+#define IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 IMX8QXP_CSI_MCLK 4
+#define IMX8QXP_CSI_EN_CI_PI_EN IMX8QXP_CSI_EN 0
+#define IMX8QXP_CSI_EN_CI_PI_I2C_SCL IMX8QXP_CSI_EN 1
+#define IMX8QXP_CSI_EN_ADMA_I2C3_SCL IMX8QXP_CSI_EN 2
+#define IMX8QXP_CSI_EN_ADMA_SPI1_SDI IMX8QXP_CSI_EN 3
+#define IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 IMX8QXP_CSI_EN 4
+#define IMX8QXP_CSI_RESET_CI_PI_RESET IMX8QXP_CSI_RESET 0
+#define IMX8QXP_CSI_RESET_CI_PI_I2C_SDA IMX8QXP_CSI_RESET 1
+#define IMX8QXP_CSI_RESET_ADMA_I2C3_SDA IMX8QXP_CSI_RESET 2
+#define IMX8QXP_CSI_RESET_ADMA_SPI1_CS0 IMX8QXP_CSI_RESET 3
+#define IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 IMX8QXP_CSI_RESET 4
+#define IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT IMX8QXP_MIPI_CSI0_MCLK_OUT 0
+#define IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 IMX8QXP_MIPI_CSI0_MCLK_OUT 4
+#define IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL IMX8QXP_MIPI_CSI0_I2C0_SCL 0
+#define IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 IMX8QXP_MIPI_CSI0_I2C0_SCL 1
+#define IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 IMX8QXP_MIPI_CSI0_I2C0_SCL 4
+#define IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA IMX8QXP_MIPI_CSI0_I2C0_SDA 0
+#define IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 IMX8QXP_MIPI_CSI0_I2C0_SDA 1
+#define IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 IMX8QXP_MIPI_CSI0_I2C0_SDA 4
+#define IMX8QXP_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 IMX8QXP_MIPI_CSI0_GPIO0_01 0
+#define IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA IMX8QXP_MIPI_CSI0_GPIO0_01 1
+#define IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 IMX8QXP_MIPI_CSI0_GPIO0_01 4
+#define IMX8QXP_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 IMX8QXP_MIPI_CSI0_GPIO0_00 0
+#define IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL IMX8QXP_MIPI_CSI0_GPIO0_00 1
+#define IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 IMX8QXP_MIPI_CSI0_GPIO0_00 4
+#define IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8QXP_QSPI0A_DATA0 0
+#define IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 IMX8QXP_QSPI0A_DATA0 4
+#define IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8QXP_QSPI0A_DATA1 0
+#define IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 IMX8QXP_QSPI0A_DATA1 4
+#define IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8QXP_QSPI0A_DATA2 0
+#define IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 IMX8QXP_QSPI0A_DATA2 4
+#define IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8QXP_QSPI0A_DATA3 0
+#define IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 IMX8QXP_QSPI0A_DATA3 4
+#define IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8QXP_QSPI0A_DQS 0
+#define IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 IMX8QXP_QSPI0A_DQS 4
+#define IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8QXP_QSPI0A_SS0_B 0
+#define IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 IMX8QXP_QSPI0A_SS0_B 4
+#define IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B IMX8QXP_QSPI0A_SS1_B 0
+#define IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 IMX8QXP_QSPI0A_SS1_B 4
+#define IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8QXP_QSPI0A_SCLK 0
+#define IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 IMX8QXP_QSPI0A_SCLK 4
+#define IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8QXP_QSPI0B_SCLK 0
+#define IMX8QXP_QSPI0B_SCLK_LSIO_QSPI1A_SCLK IMX8QXP_QSPI0B_SCLK 1
+#define IMX8QXP_QSPI0B_SCLK_LSIO_KPP0_COL0 IMX8QXP_QSPI0B_SCLK 2
+#define IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 IMX8QXP_QSPI0B_SCLK 4
+#define IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8QXP_QSPI0B_DATA0 0
+#define IMX8QXP_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 IMX8QXP_QSPI0B_DATA0 1
+#define IMX8QXP_QSPI0B_DATA0_LSIO_KPP0_COL1 IMX8QXP_QSPI0B_DATA0 2
+#define IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 IMX8QXP_QSPI0B_DATA0 4
+#define IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8QXP_QSPI0B_DATA1 0
+#define IMX8QXP_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 IMX8QXP_QSPI0B_DATA1 1
+#define IMX8QXP_QSPI0B_DATA1_LSIO_KPP0_COL2 IMX8QXP_QSPI0B_DATA1 2
+#define IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 IMX8QXP_QSPI0B_DATA1 4
+#define IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8QXP_QSPI0B_DATA2 0
+#define IMX8QXP_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 IMX8QXP_QSPI0B_DATA2 1
+#define IMX8QXP_QSPI0B_DATA2_LSIO_KPP0_COL3 IMX8QXP_QSPI0B_DATA2 2
+#define IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 IMX8QXP_QSPI0B_DATA2 4
+#define IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8QXP_QSPI0B_DATA3 0
+#define IMX8QXP_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 IMX8QXP_QSPI0B_DATA3 1
+#define IMX8QXP_QSPI0B_DATA3_LSIO_KPP0_ROW0 IMX8QXP_QSPI0B_DATA3 2
+#define IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 IMX8QXP_QSPI0B_DATA3 4
+#define IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8QXP_QSPI0B_DQS 0
+#define IMX8QXP_QSPI0B_DQS_LSIO_QSPI1A_DQS IMX8QXP_QSPI0B_DQS 1
+#define IMX8QXP_QSPI0B_DQS_LSIO_KPP0_ROW1 IMX8QXP_QSPI0B_DQS 2
+#define IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 IMX8QXP_QSPI0B_DQS 4
+#define IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8QXP_QSPI0B_SS0_B 0
+#define IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B IMX8QXP_QSPI0B_SS0_B 1
+#define IMX8QXP_QSPI0B_SS0_B_LSIO_KPP0_ROW2 IMX8QXP_QSPI0B_SS0_B 2
+#define IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 IMX8QXP_QSPI0B_SS0_B 4
+#define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B IMX8QXP_QSPI0B_SS1_B 0
+#define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B IMX8QXP_QSPI0B_SS1_B 1
+#define IMX8QXP_QSPI0B_SS1_B_LSIO_KPP0_ROW3 IMX8QXP_QSPI0B_SS1_B 2
+#define IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 IMX8QXP_QSPI0B_SS1_B 4
+
+#endif /* _IMX8QXP_PADS_H */
