| commit | 89ac8567b97fea558238c4bb73637471f9197813 | [log] [tgz] |
|---|---|---|
| author | Tuomas Tynkkynen <[email protected]> | Wed Aug 28 18:18:47 2013 +0300 |
| committer | Mike Turquette <[email protected]> | Wed Aug 28 19:08:09 2013 -0700 |
| tree | aae20760c9d0163f2ae08484dd6b544d946a7efa | |
| parent | 5b0dde99e8a9971030b36096ee1dc85a1a12ff57 [diff] |
clk: tegra30: Don't wait for PLL_U lock bit The lock bit on PLL_U does not seem to be working correctly and sometimes never gets set when waiting for the PLL to come up. Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay. Signed-off-by: Tuomas Tynkkynen <[email protected]> Tested-by: Stephen Warren <[email protected]> Acked-by: Stephen Warren <[email protected]> Signed-off-by: Mike Turquette <[email protected]>