drm/amd/display: Multi display synchronization logic
This feature synchronizes multiple displays with various timings
to a display with the highest refresh rate
it is enabled if edid caps flag multi_display_sync is set to one
There are limitations on refresh rates allowed
that can be synchronized. That would
prevent from underflow and other potential
corruptions.
Multi display synchronization is using the
same functions as timing_sync in order to minimize
redunduncy and decision to disable synchronization is
based on trigger parametre set in DM
Feature is developed for DCN1 and DCE11
Signed-off-by: Mikita Lipski <[email protected]>
Reviewed-by: Mikita Lipski <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 8734689..cebbba3 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -114,6 +114,11 @@ struct hw_sequencer_funcs {
int group_size,
struct pipe_ctx *grouped_pipes[]);
+ void (*enable_per_frame_crtc_position_reset)(
+ struct dc *dc,
+ int group_size,
+ struct pipe_ctx *grouped_pipes[]);
+
void (*enable_display_pipe_clock_gating)(
struct dc_context *ctx,
bool clock_gating);
