auto import from //depot/cupcake/@135843
diff --git a/include/msm7k/dmov.h b/include/msm7k/dmov.h
new file mode 100644
index 0000000..b151289
--- /dev/null
+++ b/include/msm7k/dmov.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __ASM_ARCH_MSM7200_DMOV_H
+#define __ASM_ARCH_MSM7200_DMOV_H
+
+#define MSM_DMOV_BASE 0xA9700000
+
+/* see 80-VA736-2 C pp 415-439 */
+
+#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
+#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
+#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
+#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
+
+/* only security domain 3 is available to the ARM11
+**
+** SD0 -> mARM trusted, SD1 -> mARM nontrusted, SD2 -> aDSP, SD3 -> aARM
+**
+*/
+
+#define DMOV_CMD_PTR(ch) DMOV_SD3(0x000, ch)
+#define DMOV_CMD_LIST (0 << 29) /* does not work */
+#define DMOV_CMD_PTR_LIST (1 << 29) /* works */
+#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */
+#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */
+#define DMOV_CMD_ADDR(addr) ((addr) >> 3)
+
+#define DMOV_RSLT(ch) DMOV_SD3(0x040, ch)
+#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */
+#define DMOV_RSLT_ERROR (1 << 3)
+#define DMOV_RSLT_FLUSH (1 << 2)
+#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */
+#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */
+
+#define DMOV_FLUSH0(ch) DMOV_SD3(0x080, ch)
+#define DMOV_FLUSH1(ch) DMOV_SD3(0x0C0, ch)
+#define DMOV_FLUSH2(ch) DMOV_SD3(0x100, ch)
+#define DMOV_FLUSH3(ch) DMOV_SD3(0x140, ch)
+#define DMOV_FLUSH4(ch) DMOV_SD3(0x180, ch)
+#define DMOV_FLUSH5(ch) DMOV_SD3(0x1C0, ch)
+
+#define DMOV_STATUS(ch) DMOV_SD3(0x200, ch)
+#define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29))
+#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3)
+#define DMOV_STATUS_RSLT_VALID (1 << 1)
+#define DMOV_STATUS_CMD_PTR_RDY (1 << 0)
+
+#define DMOV_ISR DMOV_SD3(0x380, 0)
+
+#define DMOV_CONFIG(ch) DMOV_SD3(0x300, ch)
+#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
+#define DMOV_CONFIG_FOREC_FLUSH_RSLT (1 << 1)
+#define DMOV_CONFIG_IRQ_EN (1 << 0)
+
+/* channel assignments - from qc/dmov_7500.h */
+
+#define DMOV_NAND_CHAN 7
+#define DMOV_NAND_CRCI_CMD 5
+#define DMOV_NAND_CRCI_DATA 4
+
+#define DMOV_SDC1_CHAN 8
+#define DMOV_SDC1_CRCI 6
+
+#define DMOV_SDC2_CHAN 8
+#define DMOV_SDC2_CRCI 7
+
+#define DMOV_TSIF_CHAN 10
+#define DMOV_TSIF_CRCI 10
+
+#define DMOV_USB_CHAN 11
+
+/* no client rate control ifc (eg, ram) */
+#define DMOV_NONE_CRCI 0
+
+
+/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover
+** is going to walk a list of 32bit pointers as described below. Each
+** pointer points to a *array* of dmov_s, etc structs. The last pointer
+** in the list is marked with CMD_PTR_LP. The last struct in each array
+** is marked with CMD_LC (see below).
+*/
+#define CMD_PTR_ADDR(addr) ((addr) >> 3)
+#define CMD_PTR_LP (1 << 31) /* last pointer */
+#define CMD_PTR_PT (3 << 29) /* ? */
+
+
+/* Single Item Mode -- seems to work as expected */
+typedef struct {
+ unsigned cmd;
+ unsigned src;
+ unsigned dst;
+ unsigned len;
+} dmov_s;
+
+/* Scatter/Gather Mode -- does this work?*/
+typedef struct {
+ unsigned cmd;
+ unsigned src_dscr;
+ unsigned dst_dscr;
+ unsigned _reserved;
+} dmov_sg;
+
+/* bits for the cmd field of the above structures */
+
+#define CMD_LC (1 << 31) /* last command */
+#define CMD_FR (1 << 22) /* force result -- does not work? */
+#define CMD_OCU (1 << 21) /* other channel unblock */
+#define CMD_OCB (1 << 20) /* other channel block */
+#define CMD_TCB (1 << 19) /* ? */
+#define CMD_DAH (1 << 18) /* destination address hold -- does not work?*/
+#define CMD_SAH (1 << 17) /* source address hold -- does not work? */
+
+#define CMD_MODE_SINGLE (0 << 0) /* dmov_s structure used */
+#define CMD_MODE_SG (1 << 0) /* untested */
+#define CMD_MODE_IND_SG (2 << 0) /* untested */
+#define CMD_MODE_BOX (3 << 0) /* untested */
+
+#define CMD_DST_SWAP_BYTES (1 << 14) /* exchange each byte n with byte n+1 */
+#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
+#define CMD_DST_SWAP_WORDS (1 << 16) /* exchange each word n with word n+1 */
+
+#define CMD_SRC_SWAP_BYTES (1 << 11) /* exchange each byte n with byte n+1 */
+#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
+#define CMD_SRC_SWAP_WORDS (1 << 13) /* exchange each word n with word n+1 */
+
+#define CMD_DST_CRCI(n) (((n) & 15) << 7)
+#define CMD_SRC_CRCI(n) (((n) & 15) << 3)
+
+
+/* NOTES:
+**
+** Looks like Channels 4, 5, 6, 7, 8, 10, 11 are available to the ARM11
+**
+*/
+#endif
diff --git a/include/msm7k/gpio.h b/include/msm7k/gpio.h
new file mode 100644
index 0000000..8d56a03
--- /dev/null
+++ b/include/msm7k/gpio.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __ASM_ARCH_MSM7200_GPIO_H
+#define __ASM_ARCH_MSM7200_GPIO_H
+
+#define MSM_GPIO1_BASE 0xA9200000
+#define MSM_GPIO2_BASE 0xA9300000
+
+/* see 80-VA736-2 Rev C pp 695-751
+**
+** These are actually the *shadow* gpio registers, since the
+** real ones (which allow full access) are only available to the
+** ARM9 side of the world.
+**
+** Since the _BASE need to be page-aligned when we're mapping them
+** to virtual addresses, adjust for the additional offset in these
+** macros.
+*/
+
+#define GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
+#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
+
+/* output value */
+#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */
+#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 42-16 */
+#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-43 */
+#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */
+#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */
+
+/* same pin map as above, output enable */
+#define GPIO_OE_0 GPIO1_REG(0x10)
+#define GPIO_OE_1 GPIO2_REG(0x08)
+#define GPIO_OE_2 GPIO1_REG(0x14)
+#define GPIO_OE_3 GPIO1_REG(0x18)
+#define GPIO_OE_4 GPIO1_REG(0x1C)
+
+/* same pin map as above, input read */
+#define GPIO_IN_0 GPIO1_REG(0x34)
+#define GPIO_IN_1 GPIO2_REG(0x20)
+#define GPIO_IN_2 GPIO1_REG(0x38)
+#define GPIO_IN_3 GPIO1_REG(0x3C)
+#define GPIO_IN_4 GPIO1_REG(0x40)
+
+/* same pin map as above, 1=edge 0=level interrup */
+#define GPIO_INT_EDGE_0 GPIO1_REG(0x60)
+#define GPIO_INT_EDGE_1 GPIO2_REG(0x50)
+#define GPIO_INT_EDGE_2 GPIO1_REG(0x64)
+#define GPIO_INT_EDGE_3 GPIO1_REG(0x68)
+#define GPIO_INT_EDGE_4 GPIO1_REG(0x6C)
+
+/* same pin map as above, 1=positive 0=negative */
+#define GPIO_INT_POS_0 GPIO1_REG(0x70)
+#define GPIO_INT_POS_1 GPIO2_REG(0x58)
+#define GPIO_INT_POS_2 GPIO1_REG(0x74)
+#define GPIO_INT_POS_3 GPIO1_REG(0x78)
+#define GPIO_INT_POS_4 GPIO1_REG(0x7C)
+
+/* same pin map as above, interrupt enable */
+#define GPIO_INT_EN_0 GPIO1_REG(0x80)
+#define GPIO_INT_EN_1 GPIO2_REG(0x60)
+#define GPIO_INT_EN_2 GPIO1_REG(0x84)
+#define GPIO_INT_EN_3 GPIO1_REG(0x88)
+#define GPIO_INT_EN_4 GPIO1_REG(0x8C)
+
+/* same pin map as above, write 1 to clear interrupt */
+#define GPIO_INT_CLEAR_0 GPIO1_REG(0x90)
+#define GPIO_INT_CLEAR_1 GPIO2_REG(0x68)
+#define GPIO_INT_CLEAR_2 GPIO1_REG(0x94)
+#define GPIO_INT_CLEAR_3 GPIO1_REG(0x98)
+#define GPIO_INT_CLEAR_4 GPIO1_REG(0x9C)
+
+/* same pin map as above, 1=interrupt pending */
+#define GPIO_INT_STATUS_0 GPIO1_REG(0xA0)
+#define GPIO_INT_STATUS_1 GPIO2_REG(0x70)
+#define GPIO_INT_STATUS_2 GPIO1_REG(0xA4)
+#define GPIO_INT_STATUS_3 GPIO1_REG(0xA8)
+#define GPIO_INT_STATUS_4 GPIO1_REG(0xAC)
+
+#endif
diff --git a/include/msm7k/gpt.h b/include/msm7k/gpt.h
new file mode 100644
index 0000000..69211ca
--- /dev/null
+++ b/include/msm7k/gpt.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __ASM_ARCH_MSM7200_GPT_H
+#define __ASM_ARCH_MSM7200_GPT_H
+
+#define MSM_GPT_BASE 0xC0100000
+
+#define GPT_REG(off) (MSM_GPT_BASE + (off))
+
+/* See 80-VE113-1 A, pp 229-231 */
+
+#define GPT_MATCH_VAL GPT_REG(0x0000)
+#define GPT_COUNT_VAL GPT_REG(0x0004)
+#define GPT_ENABLE GPT_REG(0x0008)
+#define GPT_ENABLE_CLR_ON_MATCH_EN 2
+#define GPT_ENABLE_EN 1
+#define GPT_CLEAR GPT_REG(0x000C)
+
+#define DGT_MATCH_VAL GPT_REG(0x0010)
+#define DGT_COUNT_VAL GPT_REG(0x0014)
+#define DGT_ENABLE GPT_REG(0x0018)
+#define DGT_ENABLE_CLR_ON_MATCH_EN 2
+#define DGT_ENABLE_EN 1
+#define DGT_CLEAR GPT_REG(0x001C)
+
+#define CSR_PROTECTION GPT_REG(0x0020)
+#define CSR_PROTECTION_EN 1
+
+#endif
diff --git a/include/msm7k/hsusb.h b/include/msm7k/hsusb.h
new file mode 100644
index 0000000..5420d14
--- /dev/null
+++ b/include/msm7k/hsusb.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _MSM7200_USB_H_
+#define _MSM7200_USB_H_
+
+#define MSM_USB_BASE 0xA0800000
+
+
+#define USB_ID (MSM_USB_BASE + 0x0000)
+#define USB_HWGENERAL (MSM_USB_BASE + 0x0004)
+#define USB_HWHOST (MSM_USB_BASE + 0x0008)
+#define USB_HWDEVICE (MSM_USB_BASE + 0x000C)
+#define USB_HWTXBUF (MSM_USB_BASE + 0x0010)
+#define USB_HWRXBUF (MSM_USB_BASE + 0x0014)
+#define USB_SBUSCFG (MSM_USB_BASE + 0x0090)
+
+#define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */
+#define USB_HCIVERSION (MSM_USB_BASE + 0x0102) /* 16 bit */
+#define USB_HCSPARAMS (MSM_USB_BASE + 0x0104)
+#define USB_HCCPARAMS (MSM_USB_BASE + 0x0108)
+#define USB_DCIVERSION (MSM_USB_BASE + 0x0120) /* 16 bit */
+#define USB_USBCMD (MSM_USB_BASE + 0x0140)
+#define USB_USBSTS (MSM_USB_BASE + 0x0144)
+#define USB_USBINTR (MSM_USB_BASE + 0x0148)
+#define USB_FRINDEX (MSM_USB_BASE + 0x014C)
+#define USB_DEVICEADDR (MSM_USB_BASE + 0x0154)
+#define USB_ENDPOINTLISTADDR (MSM_USB_BASE + 0x0158)
+#define USB_BURSTSIZE (MSM_USB_BASE + 0x0160)
+#define USB_TXFILLTUNING (MSM_USB_BASE + 0x0164)
+#define USB_ULPI_VIEWPORT (MSM_USB_BASE + 0x0170)
+#define USB_ENDPTNAK (MSM_USB_BASE + 0x0178)
+#define USB_ENDPTNAKEN (MSM_USB_BASE + 0x017C)
+#define USB_PORTSC (MSM_USB_BASE + 0x0184)
+#define USB_OTGSC (MSM_USB_BASE + 0x01A4)
+#define USB_USBMODE (MSM_USB_BASE + 0x01A8)
+#define USB_ENDPTSETUPSTAT (MSM_USB_BASE + 0x01AC)
+#define USB_ENDPTPRIME (MSM_USB_BASE + 0x01B0)
+#define USB_ENDPTFLUSH (MSM_USB_BASE + 0x01B4)
+#define USB_ENDPTSTAT (MSM_USB_BASE + 0x01B8)
+#define USB_ENDPTCOMPLETE (MSM_USB_BASE + 0x01BC)
+#define USB_ENDPTCTRL(n) (MSM_USB_BASE + 0x01C0 + (4 * (n)))
+
+
+#define USBCMD_RESET 2
+#define USBCMD_ATTACH 1
+
+#define USBMODE_DEVICE 2
+#define USBMODE_HOST 3
+
+struct ept_queue_head
+{
+ unsigned config;
+ unsigned current; /* read-only */
+
+ unsigned next;
+ unsigned info;
+ unsigned page0;
+ unsigned page1;
+ unsigned page2;
+ unsigned page3;
+ unsigned page4;
+ unsigned reserved_0;
+
+ unsigned char setup_data[8];
+
+ unsigned reserved_1;
+ unsigned reserved_2;
+ unsigned reserved_3;
+ unsigned reserved_4;
+};
+
+#define CONFIG_MAX_PKT(n) ((n) << 16)
+#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */
+#define CONFIG_IOS (1 << 15) /* IRQ on setup */
+
+struct ept_queue_item
+{
+ unsigned next;
+ unsigned info;
+ unsigned page0;
+ unsigned page1;
+ unsigned page2;
+ unsigned page3;
+ unsigned page4;
+ unsigned reserved;
+};
+
+#define TERMINATE 1
+
+#define INFO_BYTES(n) ((n) << 16)
+#define INFO_IOC (1 << 15)
+#define INFO_ACTIVE (1 << 7)
+#define INFO_HALTED (1 << 6)
+#define INFO_BUFFER_ERROR (1 << 5)
+#define INFO_TX_ERROR (1 << 3)
+
+
+#define STS_NAKI (1 << 16) /* */
+#define STS_SLI (1 << 8) /* R/WC - suspend state entered */
+#define STS_SRI (1 << 7) /* R/WC - SOF recv'd */
+#define STS_URI (1 << 6) /* R/WC - RESET recv'd - write to clear */
+#define STS_FRI (1 << 3) /* R/WC - Frame List Rollover */
+#define STS_PCI (1 << 2) /* R/WC - Port Change Detect */
+#define STS_UEI (1 << 1) /* R/WC - USB Error */
+#define STS_UI (1 << 0) /* R/WC - USB Transaction Complete */
+
+
+/* bits used in all the endpoint status registers */
+#define EPT_TX(n) (1 << ((n) + 16))
+#define EPT_RX(n) (1 << (n))
+
+
+#define CTRL_TXE (1 << 23)
+#define CTRL_TXR (1 << 22)
+#define CTRL_TXI (1 << 21)
+#define CTRL_TXD (1 << 17)
+#define CTRL_TXS (1 << 16)
+#define CTRL_RXE (1 << 7)
+#define CTRL_RXR (1 << 6)
+#define CTRL_RXI (1 << 5)
+#define CTRL_RXD (1 << 1)
+#define CTRL_RXS (1 << 0)
+
+#define CTRL_TXT_CTRL (0 << 18)
+#define CTRL_TXT_ISOCH (1 << 18)
+#define CTRL_TXT_BULK (2 << 18)
+#define CTRL_TXT_INT (3 << 18)
+
+#define CTRL_RXT_CTRL (0 << 2)
+#define CTRL_RXT_ISOCH (1 << 2)
+#define CTRL_RXT_BULK (2 << 2)
+#define CTRL_RXT_INT (3 << 2)
+
+#define ULPI_WAKEUP (1 << 31)
+#define ULPI_RUN (1 << 30)
+#define ULPI_WRITE (1 << 29)
+#define ULPI_READ (0 << 29)
+#define ULPI_STATE_NORMAL (1 << 27)
+#define ULPI_ADDR(n) (((n) & 255) << 16)
+#define ULPI_DATA(n) ((n) & 255)
+#define ULPI_DATA_READ(n) (((n) >> 8) & 255)
+
+#endif
diff --git a/include/msm7k/irqs.h b/include/msm7k/irqs.h
new file mode 100644
index 0000000..d37d50d
--- /dev/null
+++ b/include/msm7k/irqs.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __ASM_ARCH_MSM7200_IRQS_H
+
+/* MSM7200 ARM11 Interrupt Numbers */
+/* See 80-VE113-1 A, pp219-221 */
+
+#define INT_A9_M2A_0 0
+#define INT_A9_M2A_1 1
+#define INT_A9_M2A_2 2
+#define INT_A9_M2A_3 3
+#define INT_A9_M2A_4 4
+#define INT_A9_M2A_5 5
+#define INT_A9_M2A_6 6
+#define INT_GP_TIMER_EXP 7
+#define INT_DEBUG_TIMER_EXP 8
+#define INT_UART1 9
+#define INT_UART2 10
+#define INT_UART3 11
+#define INT_UART1_RX 12
+#define INT_UART2_RX 13
+#define INT_UART3_RX 14
+#define INT_USB_OTG 15
+#define INT_MDDI_PRI 16
+#define INT_MDDI_EXT 17
+#define INT_MDDI_CLIENT 18
+#define INT_MDP 19
+#define INT_GRAPHICS 20
+#define INT_ADM_AARM 21
+#define INT_ADSP_A11 22
+#define INT_ADSP_A9_A11 23
+#define INT_SDC1_0 24
+#define INT_SDC1_1 25
+#define INT_SDC2_0 26
+#define INT_SDC2_1 27
+#define INT_KEYSENSE 28
+#define INT_TCHSCRN_SSBI 29
+#define INT_TCHSCRN1 30
+#define INT_TCHSCRN2 31
+
+#define INT_GPIO_GROUP1 (32 + 0)
+#define INT_GPIO_GROUP2 (32 + 1)
+#define INT_PWB_I2C (32 + 2)
+#define INT_NAND_WR_ER_DONE (32 + 3)
+#define INT_NAND_OP_DONE (32 + 4)
+#define INT_SOFTRESET (32 + 5)
+#define INT_PBUS_ARM11 (32 + 6)
+#define INT_AXI_MPU_SMI (32 + 7)
+#define INT_AXI_MPU_EBI1 (32 + 8)
+#define INT_AD_HSSD (32 + 9)
+#define INT_ARM11_PM (32 + 10)
+#define INT_ARM11_DMA (32 + 11)
+#define INT_TSIF_IRQ (32 + 12)
+#define INT_UART1DM_IRQ (32 + 13)
+#define INT_UART1DM_RX (32 + 14)
+#define INT_SPARE0 (32 + 15)
+
+#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
+
+#define NR_IRQS 48
+
+#endif
diff --git a/include/msm7k/mddi.h b/include/msm7k/mddi.h
new file mode 100644
index 0000000..619655e
--- /dev/null
+++ b/include/msm7k/mddi.h
@@ -0,0 +1,272 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __ASM_ARCH_MSM7200_MDDI_H
+#define __ASM_ARCH_MSM7200_MDDI_H
+
+#define MSM_MDDI_BASE 0xAA600000
+
+/* see 80-VA736-2 C pp 776-787 */
+
+#define MDDI_REG(off) (MSM_MDDI_BASE + (off))
+
+#define MDDI_CMD MDDI_REG(0x0000)
+#define MDDI_VERSION MDDI_REG(0x0004)
+#define MDDI_PRI_PTR MDDI_REG(0x0008)
+#define MDDI_SEC_PTR MDDI_REG(0x000C)
+#define MDDI_BPS MDDI_REG(0x0010)
+#define MDDI_SPM MDDI_REG(0x0014)
+#define MDDI_INT MDDI_REG(0x0018)
+
+#define MDDI_INT_PRI_PTR_READ (1 << 0)
+#define MDDI_INT_SEC_PTR_READ (1 << 1)
+#define MDDI_INT_REV_DATA_AVAIL (1 << 2)
+#define MDDI_INT_DISP_REQ (1 << 3)
+#define MDDI_INT_PRI_UNDERFLOW (1 << 4)
+#define MDDI_INT_SEC_UNDERFLOW (1 << 5)
+#define MDDI_INT_REV_OVERFLOW (1 << 6)
+#define MDDI_INT_CRC_ERROR (1 << 7)
+#define MDDI_INT_MDDI_IN (1 << 8)
+#define MDDI_INT_PRI_OVERWRITE (1 << 9)
+#define MDDI_INT_SEC_OVERWRITE (1 << 10)
+#define MDDI_INT_REV_OVERWRITE (1 << 11)
+#define MDDI_INT_DMA_FAILURE (1 << 12)
+#define MDDI_INT_LINK_ACTIVE (1 << 13)
+#define MDDI_INT_IN_HIBERNATION (1 << 14)
+#define MDDI_INT_PRI_LINK_LIST_DONE (1 << 15)
+#define MDDI_INT_SEC_LINK_LIST_DONE (1 << 16)
+#define MDDI_INT_NO_REQ_PKTS_PENDING (1 << 17)
+#define MDDI_INT_RTD_FAILURE (1 << 18)
+#define MDDI_INT_REV_PKT_RECEIVED (1 << 19)
+#define MDDI_INT_REV_PKTS_AVAIL (1 << 20)
+
+#define MDDI_INTEN MDDI_REG(0x001C)
+#define MDDI_REV_PTR MDDI_REG(0x0020)
+#define MDDI_REV_SIZE MDDI_REG(0x0024)
+#define MDDI_STAT MDDI_REG(0x0028)
+
+#define MDDI_STAT_LINK_ACTIVE (1 << 0)
+#define MDDI_STAT_NEW_REV_PTR (1 << 1)
+#define MDDI_STAT_NEW_PRI_PTR (1 << 2)
+#define MDDI_STAT_NEW_SEC_PTR (1 << 3)
+#define MDDI_STAT_IN_HIBERNATION (1 << 4)
+#define MDDI_STAT_PRI_LINK_LIST_DONE (1 << 5)
+#define MDDI_STAT_SEC_LINK_LIST_DONE (1 << 6)
+#define MDDI_STAT_SEND_TIMING_PKT (1 << 7)
+#define MDDI_STAT_SEND_REV_ENCAP_WITH_FLAGS (1 << 8)
+#define MDDI_STAT_SEND_POWER_DOWN (1 << 9)
+#define MDDI_STAT_DO_HANDSHAKE (1 << 10)
+#define MDDI_STAT_RTD_MEAS_FAIL (1 << 11)
+#define MDDI_STAT_CLIENT_WAKEUP_REQ (1 << 12)
+#define MDDI_STAT_DMA_ABORT (1 << 13)
+#define MDDI_STAT_REV_OVERFLOW_RESET (1 << 14)
+#define MDDI_STAT_FORCE_NEW_REV_PTR (1 << 15)
+#define MDDI_STAT_CRC_ERRORS (1 << 16)
+
+#define MDDI_REV_RATE_DIV MDDI_REG(0x002C)
+#define MDDI_REV_CRC_ERR MDDI_REG(0x0030)
+#define MDDI_TA1_LEN MDDI_REG(0x0034)
+#define MDDI_TA2_LEN MDDI_REG(0x0038)
+#define MDDI_TEST_BUS MDDI_REG(0x003C)
+#define MDDI_TEST MDDI_REG(0x0040)
+#define MDDI_REV_PKT_CNT MDDI_REG(0x0044)
+#define MDDI_DRIVE_HI MDDI_REG(0x0048)
+#define MDDI_DRIVE_LO MDDI_REG(0x004C)
+#define MDDI_DISP_WAKE MDDI_REG(0x0050)
+#define MDDI_REV_ENCAP_SZ MDDI_REG(0x0054)
+#define MDDI_RTD_VAL MDDI_REG(0x0058)
+#define MDDI_MDP_VID_FMT_DES MDDI_REG(0x005C)
+#define MDDI_MDP_VID_PIX_ATTR MDDI_REG(0x0060)
+#define MDDI_MDP_VID_CLIENTID MDDI_REG(0x0064)
+#define MDDI_PAD_CTL MDDI_REG(0x0068)
+#define MDDI_DRIVER_START_CNT MDDI_REG(0x006C)
+#define MDDI_NEXT_PRI_PTR MDDI_REG(0x0070)
+#define MDDI_NEXT_SEC_PTR MDDI_REG(0x0074)
+#define MDDI_MISR_CTL MDDI_REG(0x0078)
+#define MDDI_MISR_DATA MDDI_REG(0x007C)
+#define MDDI_SF_CNT MDDI_REG(0x0080)
+#define MDDI_MF_CNT MDDI_REG(0x0084)
+#define MDDI_CURR_REV_PTR MDDI_REG(0x0088)
+#define MDDI_CORE_VER MDDI_REG(0x008C)
+
+#define CMD_POWER_DOWN 0x0100
+#define CMD_POWER_UP 0x0200
+#define CMD_HIBERNATE 0x0300
+#define CMD_RESET 0x0400
+#define CMD_IGNORE 0x0500
+#define CMD_REV_ENC_REQ 0x0600
+#define CMD_RTD_MEASURE 0x0700
+#define CMD_LINK_ACTIVE 0x0900
+#define CMD_PERIODIC_REV_ENC 0x0A00
+#define CMD_FORCE_NEW_REV_PTR 0x0C00
+
+#define CMD_GET_CLIENT_CAP 0x0601
+#define CMD_GET_CLIENT_STATUS 0x0602
+
+#if 1
+#define FORMAT_18BPP 0x5666
+#define FORMAT_24BPP 0x5888
+#define FORMAT_16BPP 0x5565
+#else
+#define FORMAT_MONOCHROME (0 << 13)
+#define FORMAT_PALETTE (1 << 13)
+#define FORMAT_RGB (2 << 13)
+#define FORMAT_YCBCR422 (3 << 13)
+#define FORMAT_BAYER (4 << 13)
+#endif
+
+#define PIXATTR_BOTH_EYES 3
+#define PIXATTR_LEFT_EYE 2
+#define PIXATTR_RIGHT_EYE 1
+#define PIXATTR_ALT_DISPLAY 0
+
+#define PIXATTR_PROGRESSIVE 0
+#define PIXATTR_INTERLACED (1 << 2)
+#define PIXATTR_ALTERNATE (1 << 3)
+
+#define PIXATTR_IGNORE_LRTB (1 << 5)
+
+#define PIXATTR_TO_REFRESH (0 << 6)
+#define PIXATTR_TO_OFFLINE (1 << 6)
+#define PIXATTR_TO_ALL (3 << 6)
+
+#define PIXATTR_LAST_ROW (1 << 15)
+
+#define TYPE_VIDEO_STREAM 16
+#define TYPE_CLIENT_CAPS 66
+#define TYPE_REGISTER_ACCESS 146
+#define TYPE_CLIENT_STATUS 70
+
+typedef struct mddi_video_stream mddi_video_stream;
+typedef struct mddi_register_access mddi_register_access;
+typedef struct mddi_client_caps mddi_client_caps;
+
+typedef struct mddi_llentry mddi_llentry;
+
+struct __attribute__((packed)) mddi_video_stream
+{
+ unsigned short length; /* length in bytes excluding this field */
+ unsigned short type; /* MDDI_TYPE_VIDEO_STREAM */
+ unsigned short client_id; /* set to zero */
+
+ unsigned short format;
+ unsigned short pixattr;
+
+ unsigned short left;
+ unsigned short top;
+ unsigned short right;
+ unsigned short bottom;
+
+ unsigned short start_x;
+ unsigned short start_y;
+
+ unsigned short pixels;
+
+ unsigned short crc;
+ unsigned short reserved;
+};
+
+struct __attribute__((packed)) mddi_register_access
+{
+ unsigned short length;
+ unsigned short type;
+ unsigned short client_id;
+
+ unsigned short rw_info; /* flag below | count of reg_data */
+#define MDDI_WRITE (0 << 14)
+#define MDDI_READ (2 << 14)
+#define MDDI_READ_RESP (3 << 14)
+
+ unsigned reg_addr;
+ unsigned short crc; /* 16 bit crc of the above */
+
+ unsigned reg_data; /* "list" of 3byte data values */
+};
+
+struct __attribute__((packed)) mddi_llentry {
+ unsigned short flags;
+ unsigned short header_count;
+ unsigned short data_count;
+ void *data;
+ mddi_llentry *next;
+ unsigned short reserved;
+ union {
+ mddi_video_stream v;
+ mddi_register_access r;
+ unsigned _[12];
+ } u;
+};
+
+struct __attribute__((packed)) mddi_client_caps
+{
+ unsigned short length;
+ unsigned short type;
+ unsigned short client_id;
+
+ unsigned short protocol_ver;
+ unsigned short min_protocol_ver;
+ unsigned short data_rate_cap;
+ unsigned char interface_type_cap;
+ unsigned char num_alt_displays;
+ unsigned short postcal_data_rate;
+ unsigned short bitmap_width;
+ unsigned short bitmap_height;
+ unsigned short display_window_width;
+ unsigned short display_window_height;
+ unsigned cmap_size;
+ unsigned short cmap_rgb_width;
+ unsigned short rgb_cap;
+ unsigned char mono_cap;
+ unsigned char reserved1;
+ unsigned short ycbcr_cap;
+ unsigned short bayer_cap;
+ unsigned short alpha_cursor_planes;
+ unsigned client_feature_cap;
+ unsigned char max_video_frame_rate_cap;
+ unsigned char min_video_frame_rate_cap;
+ unsigned short min_sub_frame_rate;
+ unsigned short audio_buf_depth;
+ unsigned short audio_channel_cap;
+ unsigned short audio_sampe_rate_rap;
+ unsigned char audio_sample_res;
+ unsigned char mic_audio_sample_res;
+ unsigned short mic_sample_rate_cap;
+ unsigned char keyboard_data_fmt;
+ unsigned char pointing_device_data_fmt;
+ unsigned short content_protection_type;
+ unsigned short manufacturer_name;
+ unsigned short product_code;
+ unsigned short reserved3;
+ unsigned serial_no;
+ unsigned char week_of_manufacture;
+ unsigned char year_of_manufacture;
+
+ unsigned short crc;
+};
+
+#endif
diff --git a/include/msm7k/mdp.h b/include/msm7k/mdp.h
new file mode 100644
index 0000000..11f05e8
--- /dev/null
+++ b/include/msm7k/mdp.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __ASM_ARCH_MSM7200_MDP_H
+#define __ASM_ARCH_MSM7200_MDP_H
+
+#define MSM_MDP_BASE1 0xAA200000
+#define MSM_MDP_BASE2 0xAA210100
+
+/* see 80-VA736-2 C pp 587-627 */
+
+#define MDP_REG1(off) (MSM_MDP_BASE1 + (off))
+#define MDP_REG(off) (MSM_MDP_BASE2 + (off))
+
+
+#define MDP_SYNC_CONFIG_0 MDP_REG1(0x0000)
+#define MDP_SYNC_CONFIG_1 MDP_REG1(0x0004)
+#define MDP_SYNC_CONFIG_2 MDP_REG1(0x0008)
+#define MDP_SYNC_VSYNC_EN (1 << 17)
+#define MDP_SYNC_SYNC_EN (1 << 16)
+#define MDP_SYNC_DIV_CNT(n) ((n) & 0xffff)
+
+#define MDP_SYNC_STATUS_0 MDP_REG1(0x000C)
+#define MDP_SYNC_STATUS_1 MDP_REG1(0x0010)
+#define MDP_SYNC_STATUS_2 MDP_REG1(0x0014)
+#define MDP_SYNC_FRAME_COUNT(n) (((n) >> 16) & 0xfff)
+#define MDP_SYNC_LINE_COUNT(n) ((n) & 0x3ff)
+
+#define MDP_SYNC_THRESH_0 MDP_REG1(0x0018)
+#define MDP_SYNC_SEC_ABOVE(n) (((n) & 0xFF) << 24)
+#define MDP_SYNC_SEC_BELOW(n) (((n) & 0xFF) << 16)
+#define MDP_SYNC_PRIM_ABOVE(n) (((n) & 0xFF) << 8)
+#define MDP_SYNC_PRIM_BELOW(n) ((n) & 0xFF)
+
+#define MDP_SYNC_THRESH_1 MDP_REG1(0x001C)
+#define MDP_SYNC_EXT_ABOVE(n) (((n) & 0xFF) << 8)
+#define MDP_SYNC_EXT_BELOW(n) ((n) & 0xFF)
+
+#define MDP_INTR_ENABLE MDP_REG1(0x0020)
+#define MDP_INTR_STATUS MDP_REG1(0x0024)
+#define MDP_INTR_CLEAR MDP_REG1(0x0028)
+#define MDP_INTR_LIST0_DONE (1 << 0)
+#define MDP_INTR_LIST1_DONE (1 << 1)
+#define MDP_INTR_DMA_DONE (1 << 2)
+#define MDP_INTR_TV_DONE (1 << 3)
+#define MDP_INTR_CONFIG_ERR (1 << 4)
+#define MDP_INTR_ROI_ERR (1 << 5)
+#define MDP_INTR_TV_UNDERRUN (1 << 6)
+
+#define MDP_HW_VERSION MDP_REG1(0x0070)
+
+
+#define MDP_EDGE_CONFIG MDP_REG(0x0000)
+#define MDP_TILE_CONFIG MDP_REG(0x0004)
+
+/* BLT controls */
+#define MDP_SRC_ROI MDP_REG(0x0008)
+#define MDP_SRCP0_ADDR MDP_REG(0x000C)
+#define MDP_SRCP1_ADDR MDP_REG(0x0010)
+#define MDP_SRCP2_ADDR MDP_REG(0x0014)
+#define MDP_SRCP3_ADDR MDP_REG(0x0018)
+#define MDP_SRCP01_STRIDE MDP_REG(0x001C)
+#define MDP_SRCP23_STRIDE MDP_REG(0x0020)
+#define MDP_SRC_CONFIG MDP_REG(0x0024)
+#define MDP_UNPACK_PATTERN0 MDP_REG(0x0028)
+#define MDP_UNPACK_PATTERN1 MDP_REG(0x002C)
+#define MDP_UNPACK_PATTERN2 MDP_REG(0x0030)
+#define MDP_UNPACK_PATTERN3 MDP_REG(0x0034)
+#define MDP_PPP_CONFIG MDP_REG(0x0038)
+#define MDP_PHASEX_INIT MDP_REG(0x003C)
+#define MDP_PHASEY_INIT MDP_REG(0x0040)
+#define MDP_PHASEX_STEP MDP_REG(0x0044)
+#define MDP_PHASEY_STEP MDP_REG(0x0048)
+#define MDP_ALPHA_CONFIG MDP_REG(0x004C)
+#define MDP_DST_CONFIG MDP_REG(0x0050)
+#define MDP_PACK_PATTERN0 MDP_REG(0x0054)
+#define MDP_PACK_PATTERN1 MDP_REG(0x0058)
+#define MDP_PACK_PATTERN2 MDP_REG(0x005C)
+#define MDP_PACK_PATTERN3 MDP_REG(0x0060)
+#define MDP_DST_ROI MDP_REG(0x0064)
+#define MDP_DSTP0_ADDR MDP_REG(0x0068)
+#define MDP_DSTP1_ADDR MDP_REG(0x006C)
+#define MDP_DSTP2_ADDR MDP_REG(0x0070)
+#define MDP_DSTP3_ADDR MDP_REG(0x0074)
+#define MDP_DSTP01_STRIDE MDP_REG(0x0078)
+#define MDP_DSTP23_STRIDE MDP_REG(0x007C)
+
+#endif
diff --git a/include/msm7k/nand.h b/include/msm7k/nand.h
new file mode 100644
index 0000000..12f2f9a
--- /dev/null
+++ b/include/msm7k/nand.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __ASM_ARCH_MSM7200_NAND_H
+#define __ASM_ARCH_MSM7200_NAND_H
+
+#define MSM_NAND_BASE 0xA0A00000
+
+/* see 80-VA736-2 C pp 354-414 */
+
+#define NAND_REG(off) (MSM_NAND_BASE + (off))
+
+#define NAND_FLASH_CMD NAND_REG(0x0000)
+#define NAND_ADDR0 NAND_REG(0x0004)
+#define NAND_ADDR1 NAND_REG(0x0008)
+#define NAND_FLASH_CHIP_SELECT NAND_REG(0x000C)
+#define NAND_EXEC_CMD NAND_REG(0x0010)
+#define NAND_FLASH_STATUS NAND_REG(0x0014)
+#define NAND_BUFFER_STATUS NAND_REG(0x0018)
+#define NAND_DEV0_CFG0 NAND_REG(0x0020)
+#define NAND_DEV0_CFG1 NAND_REG(0x0024)
+#define NAND_DEV1_CFG0 NAND_REG(0x0030)
+#define NAND_DEV1_CFG1 NAND_REG(0x0034)
+#define NAND_READ_ID NAND_REG(0x0040)
+#define NAND_READ_STATUS NAND_REG(0x0044)
+#define NAND_CONFIG_DATA NAND_REG(0x0050)
+#define NAND_CONFIG NAND_REG(0x0054)
+#define NAND_CONFIG_MODE NAND_REG(0x0058)
+#define NAND_CONFIG_STATUS NAND_REG(0x0060)
+#define NAND_MACRO1_REG NAND_REG(0x0064)
+#define NAND_XFR_STEP1 NAND_REG(0x0070)
+#define NAND_XFR_STEP2 NAND_REG(0x0074)
+#define NAND_XFR_STEP3 NAND_REG(0x0078)
+#define NAND_XFR_STEP4 NAND_REG(0x007C)
+#define NAND_XFR_STEP5 NAND_REG(0x0080)
+#define NAND_XFR_STEP6 NAND_REG(0x0084)
+#define NAND_XFR_STEP7 NAND_REG(0x0088)
+#define NAND_DEV_CMD0 NAND_REG(0x00A0)
+#define NAND_DEV_CMD1 NAND_REG(0x00A4)
+#define NAND_DEV_CMD2 NAND_REG(0x00A8)
+#define NAND_DEV_CMD_VLD NAND_REG(0x00AC)
+#define NAND_EBI2_MISR_SIG_REG NAND_REG(0x00B0)
+#define NAND_EBI2_ECC_BUF_CFG NAND_REG(0x00F0)
+#define NAND_FLASH_BUFFER NAND_REG(0x0100)
+
+/* device commands */
+
+#define NAND_CMD_SOFT_RESET 0x01
+#define NAND_CMD_PAGE_READ 0x32
+#define NAND_CMD_PAGE_READ_ECC 0x33
+#define NAND_CMD_PAGE_READ_ALL 0x34
+#define NAND_CMD_SEQ_PAGE_READ 0x15
+#define NAND_CMD_PRG_PAGE 0x36
+#define NAND_CMD_PRG_PAGE_ECC 0x37
+#define NAND_CMD_PRG_PAGE_ALL 0x39
+#define NAND_CMD_BLOCK_ERASE 0x3A
+#define NAND_CMD_FETCH_ID 0x0B
+#define NAND_CMD_STATUS 0x0C
+#define NAND_CMD_RESET 0x0D
+
+#endif
diff --git a/include/msm7k/shared.h b/include/msm7k/shared.h
new file mode 100644
index 0000000..b81732b
--- /dev/null
+++ b/include/msm7k/shared.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef MSM7K_SHARED_H
+#define MSM7K_SHARED_H
+
+#define MSM7K_SHARED_PHYS 0x01F00000
+
+#define MSM7K_VERSION (MSM7K_SHARED_PHYS + 0x40)
+
+#define VERSION_QDSP6 4
+#define VERSION_APPS_SBL 6
+#define VERSION_MODEM_SBL 7
+#define VERSION_APPS 8
+#define VERSION_MODEM 9
+
+void get_version_modem(char *s);
+void get_version_modem_sbl(char *s);
+
+
+#define ACPU_CLK 0 /* Applications processor clock */
+#define ADM_CLK 1 /* Applications data mover clock */
+#define ADSP_CLK 2 /* ADSP clock */
+#define EBI1_CLK 3 /* External bus interface 1 clock */
+#define EBI2_CLK 4 /* External bus interface 2 clock */
+#define ECODEC_CLK 5 /* External CODEC clock */
+#define EMDH_CLK 6 /* External MDDI host clock */
+#define GP_CLK 7 /* General purpose clock */
+#define GRP_CLK 8 /* Graphics clock */
+#define I2C_CLK 9 /* I2C clock */
+#define ICODEC_RX_CLK 10 /* Internal CODEX RX clock */
+#define ICODEC_TX_CLK 11 /* Internal CODEX TX clock */
+#define IMEM_CLK 12 /* Internal graphics memory clock */
+#define MDC_CLK 13 /* MDDI client clock */
+#define MDP_CLK 14 /* Mobile display processor clock */
+#define PBUS_CLK 15 /* Peripheral bus clock */
+#define PCM_CLK 16 /* PCM clock */
+#define PMDH_CLK 17 /* Primary MDDI host clock */
+#define SDAC_CLK 18 /* Stereo DAC clock */
+#define SDC1_CLK 19 /* Secure Digital Card clocks */
+#define SDC1_PCLK 20
+#define SDC2_CLK 21
+#define SDC2_PCLK 22
+#define SDC3_CLK 23
+#define SDC3_PCLK 24
+#define SDC4_CLK 25
+#define SDC4_PCLK 26
+#define TSIF_CLK 27 /* Transport Stream Interface clocks */
+#define TSIF_REF_CLK 28
+#define TV_DAC_CLK 29 /* TV clocks */
+#define TV_ENC_CLK 30
+#define UART1_CLK 31 /* UART clocks */
+#define UART2_CLK 32
+#define UART3_CLK 33
+#define UART1DM_CLK 34
+#define UART2DM_CLK 35
+#define USB_HS_CLK 36 /* High speed USB core clock */
+#define USB_HS_PCLK 37 /* High speed USB pbus clock */
+#define USB_OTG_CLK 38 /* Full speed USB clock */
+#define VDC_CLK 39 /* Video controller clock */
+#define VFE_CLK 40 /* Camera / Video Front End clock */
+#define VFE_MDC_CLK 41 /* VFE MDDI client clock */
+
+enum
+{
+ VREG_MSMA_ID,
+ VREG_MSMP_ID,
+ VREG_MSME1_ID, /* Not supported in Panoramix */
+ VREG_MSMC1_ID, /* Not supported in PM6620 */
+ VREG_MSMC2_ID, /* Supported in PM7500 only */
+ VREG_GP3_ID, /* Supported in PM7500 only */
+ VREG_MSME2_ID, /* Supported in PM7500 and Panoramix only */
+ VREG_GP4_ID, /* Supported in PM7500 only */
+ VREG_GP1_ID, /* Supported in PM7500 only */
+ VREG_TCXO_ID,
+ VREG_PA_ID,
+ VREG_RFTX_ID,
+ VREG_RFRX1_ID,
+ VREG_RFRX2_ID,
+ VREG_SYNT_ID,
+ VREG_WLAN_ID,
+ VREG_USB_ID,
+ VREG_BOOST_ID,
+ VREG_MMC_ID,
+ VREG_RUIM_ID,
+ VREG_MSMC0_ID, /* Supported in PM6610 only */
+ VREG_GP2_ID, /* Supported in PM7500 only */
+ VREG_GP5_ID, /* Supported in PM7500 only */
+ VREG_GP6_ID, /* Supported in PM7500 only */
+ VREG_RF_ID,
+ VREG_RF_VCO_ID,
+ VREG_MPLL_ID,
+ VREG_S2_ID,
+ VREG_S3_ID,
+ VREG_RFUBM_ID,
+ VREG_NCP_ID,
+};
+
+int clock_enable(unsigned id);
+int clock_disable(unsigned id);
+int clock_set_rate(unsigned id, unsigned hz);
+int clock_get_rate(unsigned id);
+
+int vreg_enable(unsigned id);
+int vreg_disable(unsigned id);
+int vreg_set_level(unsigned id, unsigned mv);
+
+void reboot(void);
+
+#endif
diff --git a/include/msm7k/uart.h b/include/msm7k/uart.h
new file mode 100644
index 0000000..cbcd960
--- /dev/null
+++ b/include/msm7k/uart.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __ASM_ARCH_MSM7200_UART_H
+#define __ASM_ARCH_MSM7200_UART_H
+
+#define MSM_UART1_BASE 0xA9A00000
+#define MSM_UART2_BASE 0xA9B00000
+#define MSM_UART3_BASE 0xA9C00000
+
+#define UART_MR1 0x0000
+
+#define UART_MR1_AUTO_RFR_LEVEL0(n) (((n) & 0x3f) << 8)
+#define UART_MR1_RX_RDY_CTL (1 << 7)
+#define UART_MR1_CTS_CTL (1 << 6)
+#define UART_MR1_AUTO_RFR_LEVEL1(n) ((n) & 0x3f)
+
+#define UART_MR2 0x0004
+#define UART_MR2_ERROR_MODE (1 << 6)
+#define UART_MR2_BITS_PER_CHAR_5 (0 << 4)
+#define UART_MR2_BITS_PER_CHAR_6 (1 << 4)
+#define UART_MR2_BITS_PER_CHAR_7 (2 << 4)
+#define UART_MR2_BITS_PER_CHAR_8 (3 << 4)
+#define UART_MR2_STOP_BIT_LEN_0563 (0 << 2)
+#define UART_MR2_STOP_BIT_LEN_1000 (1 << 2)
+#define UART_MR2_STOP_BIT_LEN_1563 (2 << 2)
+#define UART_MR2_STOP_BIT_LEN_2000 (3 << 2)
+#define UART_MR2_PARITY_MODE_NONE (0)
+#define UART_MR2_PARITY_MODE_ODD (1)
+#define UART_MR2_PARITY_MODE_EVEN (2)
+#define UART_MR2_PARITY_MODE_SPACE (3)
+
+#define UART_CSR 0x0008
+#define UART_CSR_115200 0xFF
+#define UART_CSR_57600 0xEE
+#define UART_CSR_38400 0xDD
+#define UART_CSR_19200 0xBB
+
+#define UART_TF 0x000C
+
+#define UART_CR 0x0010
+#define UART_CR_CMD_NULL (0 << 4)
+#define UART_CR_CMD_RESET_RX (1 << 4)
+#define UART_CR_CMD_RESET_TX (2 << 4)
+#define UART_CR_CMD_RESET_ERR (3 << 4)
+#define UART_CR_CMD_RESET_BCI (4 << 4)
+#define UART_CR_CMD_START_BREAK (5 << 4)
+#define UART_CR_CMD_STOP_BREAK (6 << 4)
+#define UART_CR_CMD_RESET_CTS_N (7 << 4)
+#define UART_CR_CMD_PACKET_MODE (9 << 4)
+#define UART_CR_CMD_MODE_RESET (12<< 4)
+#define UART_CR_CMD_SET_RFR_N (13<< 4)
+#define UART_CR_CMD_RESET_RFR_ND (14<< 4)
+#define UART_CR_TX_DISABLE (1 << 3)
+#define UART_CR_TX_ENABLE (1 << 3)
+#define UART_CR_RX_DISABLE (1 << 3)
+#define UART_CR_RX_ENABLE (1 << 3)
+
+#define UART_IMR 0x0014
+#define UART_IMR_RXLEV (1 << 4)
+#define UART_IMR_TXLEV (1 << 0)
+
+#define UART_IPR 0x0018
+#define UART_TFWR 0x001C
+#define UART_RFWR 0x0020
+#define UART_HCR 0x0024
+
+#define UART_MREG 0x0028
+#define UART_NREG 0x002C
+#define UART_DREG 0x0030
+#define UART_MNDREG 0x0034
+#define UART_IRDA 0x0038
+#define UART_MISR_MODE 0x0040
+#define UART_MISR_RESET 0x0044
+#define UART_MISR_EXPORT 0x0048
+#define UART_MISR_VAL 0x004C
+#define UART_TEST_CTRL 0x0050
+
+#define UART_SR 0x0008
+#define UART_SR_HUNT_CHAR (1 << 7)
+#define UART_SR_RX_BREAK (1 << 6)
+#define UART_SR_PAR_FRAME_ERR (1 << 5)
+#define UART_SR_OVERRUN (1 << 4)
+#define UART_SR_TX_EMPTY (1 << 3)
+#define UART_SR_TX_READY (1 << 2)
+#define UART_SR_RX_FULL (1 << 1)
+#define UART_SR_RX_READY (1 << 0)
+
+#define UART_RF 0x000C
+#define UART_MISR 0x0010
+#define UART_ISR 0x0014
+
+
+#endif
diff --git a/include/msm7k/vic.h b/include/msm7k/vic.h
new file mode 100644
index 0000000..46f3adf
--- /dev/null
+++ b/include/msm7k/vic.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __ASM_ARCH_MSM7200_VIC_H
+#define __ASM_ARCH_MSM7200_VIC_H
+
+#define MSM_VIC_BASE 0xC0000000
+
+#define VIC_REG(off) (MSM_VIC_BASE + (off))
+
+/* See 80-VE113-1 A, pp 218-228 */
+
+#define VIC_IRQ_STATUS0 VIC_REG(0x0000)
+#define VIC_IRQ_STATUS1 VIC_REG(0x0004)
+#define VIC_FIQ_STATUS0 VIC_REG(0x0008)
+#define VIC_FIQ_STATUS1 VIC_REG(0x000C)
+#define VIC_RAW_STATUS0 VIC_REG(0x0010)
+#define VIC_RAW_STATUS1 VIC_REG(0x0014)
+#define VIC_INT_CLEAR0 VIC_REG(0x0018)
+#define VIC_INT_CLEAR1 VIC_REG(0x001C)
+#define VIC_INT_SELECT0 VIC_REG(0x0020) /* 1: FIQ, 0: IRQ */
+#define VIC_INT_SELECT1 VIC_REG(0x0024) /* 1: FIQ, 0: IRQ */
+#define VIC_INT_EN0 VIC_REG(0x0028)
+#define VIC_INT_EN1 VIC_REG(0x002C)
+#define VIC_INT_ENCLEAR0 VIC_REG(0x0040)
+#define VIC_INT_ENCLEAR1 VIC_REG(0x0044)
+#define VIC_SOFTINT0 VIC_REG(0x0050)
+#define VIC_SOFTINT1 VIC_REG(0x0054)
+#define VIC_INT_MASTEREN VIC_REG(0x0060) /* 1: IRQ, 2: FIQ */
+#define VIC_PROTECTION VIC_REG(0x0064) /* 1: ENABLE */
+#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
+#define VIC_INT_TYPE0 VIC_REG(0x0070) /* 1: EDGE, 0: LEVEL */
+#define VIC_INT_TYPE1 VIC_REG(0x0074) /* 1: EDGE, 0: LEVEL */
+#define VIC_IRQ_VEC_RD VIC_REG(0x0F00) /* pending int # */
+#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x0F20) /* pending vector addr */
+
+#define VIC_VECTADDR(n) VIC_REG(0x0100+((n) * 4))
+#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
+
+#endif
