Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
diff --git a/test/CodeGen/SPARC/2009-08-28-PIC.ll b/test/CodeGen/SPARC/2009-08-28-PIC.ll
index a2ba0d0..b004b11 100644
--- a/test/CodeGen/SPARC/2009-08-28-PIC.ll
+++ b/test/CodeGen/SPARC/2009-08-28-PIC.ll
@@ -1,9 +1,45 @@
-; RUN: llc -march=sparc --relocation-model=pic < %s | grep _GLOBAL_OFFSET_TABLE_
+; RUN: llc -march=sparc --relocation-model=pic < %s | FileCheck %s --check-prefix=V8
+; RUN: llc -march=sparcv9 --relocation-model=pic < %s | FileCheck %s --check-prefix=V9
+; RUN: llc -march=sparc --relocation-model=pic < %s -O0 | FileCheck %s --check-prefix=V8UNOPT
+; RUN: llc -march=sparcv9 --relocation-model=pic < %s -O0 | FileCheck %s --check-prefix=V9UNOPT
+
+
+; V8-LABEL: func
+; V8: _GLOBAL_OFFSET_TABLE_
+
+; V9-LABEL: func
+; V9: _GLOBAL_OFFSET_TABLE_
@foo = global i32 0 ; <i32*> [#uses=1]
-define i32 @func() nounwind readonly {
+define i32 @func(i32 %a) nounwind readonly {
entry:
%0 = load i32* @foo, align 4 ; <i32> [#uses=1]
ret i32 %0
}
+
+; V8UNOPT-LABEL: test_spill
+; V8UNOPT: sethi %hi(_GLOBAL_OFFSET_TABLE_+{{.+}}), [[R:%[goli][0-7]]]
+; V8UNOPT: or [[R]], %lo(_GLOBAL_OFFSET_TABLE_+{{.+}}), [[R]]
+; V8UNOPT: add [[R]], %o7, [[R]]
+; V8UNOPT: st [[R]], [%fp+{{.+}}]
+
+; V9UNOPT-LABEL: test_spill
+; V9UNOPT: sethi %hi(_GLOBAL_OFFSET_TABLE_+{{.+}}), [[R:%[goli][0-7]]]
+; V9UNOPT: or [[R]], %lo(_GLOBAL_OFFSET_TABLE_+{{.+}}), [[R]]
+; V9UNOPT: add [[R]], %o7, [[R]]
+; V9UNOPT: stx [[R]], [%fp+{{.+}}]
+
+define i32 @test_spill(i32 %a, i32 %b) {
+entry:
+ %cmp = icmp eq i32 %b, 0
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ %ret = load i32* @foo, align 4
+ ret i32 %ret
+
+if.end:
+ %add = add nsw i32 %b, %a
+ ret i32 %add
+}
diff --git a/test/CodeGen/SPARC/2011-01-11-Call.ll b/test/CodeGen/SPARC/2011-01-11-Call.ll
index a0f478e..067bade 100644
--- a/test/CodeGen/SPARC/2011-01-11-Call.ll
+++ b/test/CodeGen/SPARC/2011-01-11-Call.ll
@@ -8,7 +8,7 @@
; V8-NEXT: nop
; V8: call bar
; V8-NEXT: nop
-; V8: jmp %i7+8
+; V8: ret
; V8-NEXT: restore
; V9-LABEL: test
@@ -17,7 +17,7 @@
; V9-NEXT: nop
; V9: call bar
; V9-NEXT: nop
-; V9: jmp %i7+8
+; V9: ret
; V9-NEXT: restore
define void @test() nounwind {
@@ -36,14 +36,14 @@
; V8: save %sp
; V8: call foo
; V8-NEXT: nop
-; V8: jmp %i7+8
+; V8: ret
; V8-NEXT: restore %g0, %o0, %o0
; V9-LABEL: test_tail_call_with_return
; V9: save %sp
; V9: call foo
; V9-NEXT: nop
-; V9: jmp %i7+8
+; V9: ret
; V9-NEXT: restore %g0, %o0, %o0
define i32 @test_tail_call_with_return() nounwind {
diff --git a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
index 7cc7868..050b76d 100644
--- a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
+++ b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
@@ -2,19 +2,28 @@
;RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9
;RUN: llc -march=sparc -regalloc=basic < %s | FileCheck %s -check-prefix=V8
;RUN: llc -march=sparc -regalloc=basic -mattr=v9 < %s | FileCheck %s -check-prefix=V9
+;RUN: llc -march=sparcv9 < %s | FileCheck %s -check-prefix=SPARC64
define i8* @frameaddr() nounwind readnone {
entry:
;V8-LABEL: frameaddr:
;V8: save %sp, -96, %sp
-;V8: jmp %i7+8
+;V8: ret
;V8: restore %g0, %fp, %o0
;V9-LABEL: frameaddr:
;V9: save %sp, -96, %sp
-;V9: jmp %i7+8
+;V9: ret
;V9: restore %g0, %fp, %o0
+
+;SPARC64-LABEL: frameaddr
+;SPARC64: save %sp, -128, %sp
+;SPARC64: add %fp, 2047, %i0
+;SPARC64: ret
+;SPARC64-NOT: restore %g0, %g0, %g0
+;SPARC64: restore
+
%0 = tail call i8* @llvm.frameaddress(i32 0)
ret i8* %0
}
@@ -32,6 +41,14 @@
;V9: ld [%fp+56], {{.+}}
;V9: ld [{{.+}}+56], {{.+}}
;V9: ld [{{.+}}+56], {{.+}}
+
+;SPARC64-LABEL: frameaddr2
+;SPARC64: flushw
+;SPARC64: ldx [%fp+2159], %[[R0:[goli][0-7]]]
+;SPARC64: ldx [%[[R0]]+2159], %[[R1:[goli][0-7]]]
+;SPARC64: ldx [%[[R1]]+2159], %[[R2:[goli][0-7]]]
+;SPARC64: add %[[R2]], 2047, {{.+}}
+
%0 = tail call i8* @llvm.frameaddress(i32 3)
ret i8* %0
}
@@ -48,6 +65,9 @@
;V9-LABEL: retaddr:
;V9: or %g0, %o7, {{.+}}
+;SPARC64-LABEL: retaddr
+;SPARC64: or %g0, %o7, {{.+}}
+
%0 = tail call i8* @llvm.returnaddress(i32 0)
ret i8* %0
}
@@ -66,17 +86,11 @@
;V9: ld [{{.+}}+56], {{.+}}
;V9: ld [{{.+}}+60], {{.+}}
-;V8LEAF-LABEL: retaddr2:
-;V8LEAF: ta 3
-;V8LEAF: ld [%fp+56], %[[R:[goli][0-7]]]
-;V8LEAF: ld [%[[R]]+56], %[[R1:[goli][0-7]]]
-;V8LEAF: ld [%[[R1]]+60], {{.+}}
-
-;V9LEAF-LABEL: retaddr2:
-;V9LEAF: flushw
-;V9LEAF: ld [%fp+56], %[[R:[goli][0-7]]]
-;V9LEAF: ld [%[[R]]+56], %[[R1:[goli][0-7]]]
-;V9LEAF: ld [%[[R1]]+60], {{.+}}
+;SPARC64-LABEL: retaddr2
+;SPARC64: flushw
+;SPARC64: ldx [%fp+2159], %[[R0:[goli][0-7]]]
+;SPARC64: ldx [%[[R0]]+2159], %[[R1:[goli][0-7]]]
+;SPARC64: ldx [%[[R1]]+2167], {{.+}}
%0 = tail call i8* @llvm.returnaddress(i32 3)
ret i8* %0
diff --git a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
index c71e7c0..60bdf06 100644
--- a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
+++ b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
@@ -1,5 +1,5 @@
-;RUN: llc -march=sparc < %s | FileCheck %s
-;RUN: llc -march=sparc -O0 < %s | FileCheck %s -check-prefix=UNOPT
+;RUN: llc -march=sparc < %s -verify-machineinstrs | FileCheck %s
+;RUN: llc -march=sparc -O0 < %s -verify-machineinstrs | FileCheck %s -check-prefix=UNOPT
define i32 @test(i32 %a) nounwind {
@@ -7,7 +7,7 @@
; CHECK: test
; CHECK: call bar
; CHECK-NOT: nop
-; CHECK: jmp
+; CHECK: ret
; CHECK-NEXT: restore
%0 = tail call i32 @bar(i32 %a) nounwind
ret i32 %0
@@ -18,7 +18,7 @@
; CHECK: test_jmpl
; CHECK: call
; CHECK-NOT: nop
-; CHECK: jmp
+; CHECK: ret
; CHECK-NEXT: restore
%0 = tail call i32 %f(i32 %a, i32 %b) nounwind
ret i32 %0
@@ -47,7 +47,7 @@
bb5: ; preds = %bb, %entry
%a_addr.1.lcssa = phi i32 [ %a, %entry ], [ %a_addr.0, %bb ]
-;CHECK: jmp
+;CHECK: retl
;CHECK-NOT: restore
ret i32 %a_addr.1.lcssa
}
@@ -110,7 +110,7 @@
define i32 @restore_add(i32 %a, i32 %b) {
entry:
;CHECK-LABEL: restore_add:
-;CHECK: jmp %i7+8
+;CHECK: ret
;CHECK: restore %o0, %i1, %o0
%0 = tail call i32 @bar(i32 %a) nounwind
%1 = add nsw i32 %0, %b
@@ -120,7 +120,7 @@
define i32 @restore_add_imm(i32 %a) {
entry:
;CHECK-LABEL: restore_add_imm:
-;CHECK: jmp %i7+8
+;CHECK: ret
;CHECK: restore %o0, 20, %o0
%0 = tail call i32 @bar(i32 %a) nounwind
%1 = add nsw i32 %0, 20
@@ -130,7 +130,7 @@
define i32 @restore_or(i32 %a) {
entry:
;CHECK-LABEL: restore_or:
-;CHECK: jmp %i7+8
+;CHECK: ret
;CHECK: restore %g0, %o0, %o0
%0 = tail call i32 @bar(i32 %a) nounwind
ret i32 %0
@@ -140,8 +140,9 @@
entry:
;CHECK-LABEL: restore_or_imm:
;CHECK: or %o0, 20, %i0
-;CHECK: jmp %i7+8
-;CHECK: restore %g0, %g0, %g0
+;CHECK: ret
+;CHECK-NOT: restore %g0, %g0, %g0
+;CHECK: restore
%0 = tail call i32 @bar(i32 %a) nounwind
%1 = or i32 %0, 20
ret i32 %1
@@ -174,7 +175,8 @@
entry:
;CHECK-LABEL: restore_sethi_large:
;CHECK: sethi 4000, %i0
-;CHECK: restore %g0, %g0, %g0
+;CHECK-NOT: restore %g0, %g0, %g0
+;CHECK: restore
%0 = tail call i32 @bar(i32 %a) nounwind
%1 = icmp ne i32 %0, 0
%2 = select i1 %1, i32 4096000, i32 0
diff --git a/test/CodeGen/SPARC/64abi.ll b/test/CodeGen/SPARC/64abi.ll
index 8b752a1..3771888 100644
--- a/test/CodeGen/SPARC/64abi.ll
+++ b/test/CodeGen/SPARC/64abi.ll
@@ -180,7 +180,7 @@
}
; CHECK: inreg_ff
-; CHECK: fsubs %f0, %f1, %f1
+; CHECK: fsubs %f0, %f1, %f0
define float @inreg_ff(float inreg %a0, ; %f0
float inreg %a1) { ; %f1
%rv = fsub float %a0, %a1
@@ -262,10 +262,10 @@
ret void
}
-; This is not a C struct, each member uses 8 bytes.
+; This is not a C struct, the i32 member uses 8 bytes, but the float only 4.
; CHECK: ret_i32_float_pair
; CHECK: ld [%i2], %i0
-; CHECK: ld [%i3], %f3
+; CHECK: ld [%i3], %f2
define { i32, float } @ret_i32_float_pair(i32 %a0, i32 %a1,
i32* %p, float* %q) {
%r1 = load i32* %p
@@ -279,7 +279,7 @@
; CHECK: call_ret_i32_float_pair
; CHECK: call ret_i32_float_pair
; CHECK: st %o0, [%i0]
-; CHECK: st %f3, [%i1]
+; CHECK: st %f2, [%i1]
define void @call_ret_i32_float_pair(i32* %i0, float* %i1) {
%rv = call { i32, float } @ret_i32_float_pair(i32 undef, i32 undef,
i32* undef, float* undef)
@@ -411,3 +411,54 @@
}
declare i32 @use_buf(i32, i8*)
+
+; CHECK-LABEL: test_fp128_args
+; CHECK-DAG: std %f0, [%fp+{{.+}}]
+; CHECK-DAG: std %f2, [%fp+{{.+}}]
+; CHECK-DAG: std %f6, [%fp+{{.+}}]
+; CHECK-DAG: std %f4, [%fp+{{.+}}]
+; CHECK: add %fp, [[Offset:[0-9]+]], %o0
+; CHECK: call _Qp_add
+; CHECK: ldd [%fp+[[Offset]]], %f0
+define fp128 @test_fp128_args(fp128 %a, fp128 %b) {
+entry:
+ %0 = fadd fp128 %a, %b
+ ret fp128 %0
+}
+
+declare i64 @receive_fp128(i64 %a, ...)
+
+; CHECK-LABEL: test_fp128_variable_args
+; CHECK-DAG: std %f4, [%sp+[[Offset0:[0-9]+]]]
+; CHECK-DAG: std %f6, [%sp+[[Offset1:[0-9]+]]]
+; CHECK-DAG: ldx [%sp+[[Offset0]]], %o2
+; CHECK-DAG: ldx [%sp+[[Offset1]]], %o3
+; CHECK: call receive_fp128
+define i64 @test_fp128_variable_args(i64 %a, fp128 %b) {
+entry:
+ %0 = call i64 (i64, ...)* @receive_fp128(i64 %a, fp128 %b)
+ ret i64 %0
+}
+
+; CHECK-LABEL: test_call_libfunc
+; CHECK: st %f1, [%fp+[[Offset0:[0-9]+]]]
+; CHECK: fmovs %f3, %f1
+; CHECK: call cosf
+; CHECK: st %f0, [%fp+[[Offset1:[0-9]+]]]
+; CHECK: ld [%fp+[[Offset0]]], %f1
+; CHECK: call sinf
+; CHECK: ld [%fp+[[Offset1]]], %f1
+; CHECK: fmuls %f1, %f0, %f0
+
+define inreg float @test_call_libfunc(float %arg0, float %arg1) {
+entry:
+ %0 = tail call inreg float @cosf(float %arg1)
+ %1 = tail call inreg float @sinf(float %arg0)
+ %2 = fmul float %0, %1
+ ret float %2
+}
+
+declare inreg float @cosf(float %arg) readnone nounwind
+declare inreg float @sinf(float %arg) readnone nounwind
+
+
diff --git a/test/CodeGen/SPARC/64bit.ll b/test/CodeGen/SPARC/64bit.ll
index f5ed047..7ab19f3 100644
--- a/test/CodeGen/SPARC/64bit.ll
+++ b/test/CodeGen/SPARC/64bit.ll
@@ -1,11 +1,11 @@
-; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s
-; RUN: llc < %s -march=sparcv9 | FileCheck %s -check-prefix=OPT
+; RUN: llc < %s -march=sparcv9 -mattr=+popc -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s
+; RUN: llc < %s -march=sparcv9 -mattr=+popc | FileCheck %s -check-prefix=OPT
; CHECK-LABEL: ret2:
; CHECK: or %g0, %i1, %i0
; OPT-LABEL: ret2:
-; OPT: jmp %o7+8
+; OPT: retl
; OPT: or %g0, %o1, %o0
define i64 @ret2(i64 %a, i64 %b) {
ret i64 %b
@@ -15,7 +15,7 @@
; CHECK: sllx %i0, 7, %i0
; OPT-LABEL: shl_imm:
-; OPT: jmp %o7+8
+; OPT: retl
; OPT: sllx %o0, 7, %o0
define i64 @shl_imm(i64 %a) {
%x = shl i64 %a, 7
@@ -26,7 +26,7 @@
; CHECK: srax %i0, %i1, %i0
; OPT-LABEL: sra_reg:
-; OPT: jmp %o7+8
+; OPT: retl
; OPT: srax %o0, %o1, %o0
define i64 @sra_reg(i64 %a, i64 %b) {
%x = ashr i64 %a, %b
@@ -42,7 +42,7 @@
; CHECK: or %g0, 0, %i0
; OPT: ret_imm0
-; OPT: jmp %o7+8
+; OPT: retl
; OPT: or %g0, 0, %o0
define i64 @ret_imm0() {
ret i64 0
@@ -52,7 +52,7 @@
; CHECK: or %g0, -4096, %i0
; OPT: ret_simm13
-; OPT: jmp %o7+8
+; OPT: retl
; OPT: or %g0, -4096, %o0
define i64 @ret_simm13() {
ret i64 -4096
@@ -64,7 +64,7 @@
; CHECK: restore
; OPT: ret_sethi
-; OPT: jmp %o7+8
+; OPT: retl
; OPT: sethi 4, %o0
define i64 @ret_sethi() {
ret i64 4096
@@ -76,7 +76,7 @@
; OPT: ret_sethi_or
; OPT: sethi 4, [[R:%[go][0-7]]]
-; OPT: jmp %o7+8
+; OPT: retl
; OPT: or [[R]], 1, %o0
define i64 @ret_sethi_or() {
@@ -89,7 +89,7 @@
; OPT: ret_nimm33
; OPT: sethi 4, [[R:%[go][0-7]]]
-; OPT: jmp %o7+8
+; OPT: retl
; OPT: xor [[R]], -4, %o0
define i64 @ret_nimm33() {
diff --git a/test/CodeGen/SPARC/64cond.ll b/test/CodeGen/SPARC/64cond.ll
index 7451b04..1bd17a4 100644
--- a/test/CodeGen/SPARC/64cond.ll
+++ b/test/CodeGen/SPARC/64cond.ll
@@ -80,7 +80,7 @@
; CHECK: selectf32_xcc
; CHECK: cmp %i0, %i1
; CHECK: fmovsg %xcc, %f5, %f7
-; CHECK: fmovs %f7, %f1
+; CHECK: fmovs %f7, %f0
define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
entry:
%tobool = icmp sgt i64 %x, %y
@@ -111,6 +111,11 @@
}
; CHECK-LABEL: setcc_resultty
+; CHECK-DAG: srax %i0, 63, %o0
+; CHECK-DAG: or %g0, %i0, %o1
+; CHECK-DAG: or %g0, 0, %o2
+; CHECK-DAG: or %g0, 32, %o3
+; CHECK-DAG: call __multi3
; CHECK: cmp
; CHECK: movne %xcc, 1, [[R:%[gilo][0-7]]]
; CHECK: or [[R]], %i1, %i0
diff --git a/test/CodeGen/SPARC/64spill.ll b/test/CodeGen/SPARC/64spill.ll
new file mode 100644
index 0000000..ab08d6b
--- /dev/null
+++ b/test/CodeGen/SPARC/64spill.ll
@@ -0,0 +1,116 @@
+; RUN: llc < %s -march=sparcv9 | FileCheck %s
+
+target datalayout = "E-i64:64-n32:64-S128"
+target triple = "sparc64-sun-sparc"
+
+; CHECK-LABEL: test_and_spill
+; CHECK: and %i0, %i1, [[R:%[gilo][0-7]]]
+; CHECK: stx [[R]], [%fp+{{.+}}]
+; CHECK: ldx [%fp+{{.+}}, %i0
+define i64 @test_and_spill(i64 %a, i64 %b) {
+entry:
+ %r0 = and i64 %a, %b
+ %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
+ ret i64 %r0
+}
+
+; CHECK-LABEL: test_or_spill
+; CHECK: or %i0, %i1, [[R:%[gilo][0-7]]]
+; CHECK: stx [[R]], [%fp+{{.+}}]
+; CHECK: ldx [%fp+{{.+}}, %i0
+define i64 @test_or_spill(i64 %a, i64 %b) {
+entry:
+ %r0 = or i64 %a, %b
+ %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
+ ret i64 %r0
+}
+
+; CHECK-LABEL: test_xor_spill
+; CHECK: xor %i0, %i1, [[R:%[gilo][0-7]]]
+; CHECK: stx [[R]], [%fp+{{.+}}]
+; CHECK: ldx [%fp+{{.+}}, %i0
+define i64 @test_xor_spill(i64 %a, i64 %b) {
+entry:
+ %r0 = xor i64 %a, %b
+ %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
+ ret i64 %r0
+}
+
+
+; CHECK-LABEL: test_add_spill
+; CHECK: add %i0, %i1, [[R:%[gilo][0-7]]]
+; CHECK: stx [[R]], [%fp+{{.+}}]
+; CHECK: ldx [%fp+{{.+}}, %i0
+define i64 @test_add_spill(i64 %a, i64 %b) {
+entry:
+ %r0 = add i64 %a, %b
+ %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
+ ret i64 %r0
+}
+
+; CHECK-LABEL: test_sub_spill
+; CHECK: sub %i0, %i1, [[R:%[gilo][0-7]]]
+; CHECK: stx [[R]], [%fp+{{.+}}]
+; CHECK: ldx [%fp+{{.+}}, %i0
+define i64 @test_sub_spill(i64 %a, i64 %b) {
+entry:
+ %r0 = sub i64 %a, %b
+ %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
+ ret i64 %r0
+}
+
+; CHECK-LABEL: test_andi_spill
+; CHECK: and %i0, 1729, [[R:%[gilo][0-7]]]
+; CHECK: stx [[R]], [%fp+{{.+}}]
+; CHECK: ldx [%fp+{{.+}}, %i0
+define i64 @test_andi_spill(i64 %a) {
+entry:
+ %r0 = and i64 %a, 1729
+ %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
+ ret i64 %r0
+}
+
+; CHECK-LABEL: test_ori_spill
+; CHECK: or %i0, 1729, [[R:%[gilo][0-7]]]
+; CHECK: stx [[R]], [%fp+{{.+}}]
+; CHECK: ldx [%fp+{{.+}}, %i0
+define i64 @test_ori_spill(i64 %a) {
+entry:
+ %r0 = or i64 %a, 1729
+ %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
+ ret i64 %r0
+}
+
+; CHECK-LABEL: test_xori_spill
+; CHECK: xor %i0, 1729, [[R:%[gilo][0-7]]]
+; CHECK: stx [[R]], [%fp+{{.+}}]
+; CHECK: ldx [%fp+{{.+}}, %i0
+define i64 @test_xori_spill(i64 %a) {
+entry:
+ %r0 = xor i64 %a, 1729
+ %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
+ ret i64 %r0
+}
+
+; CHECK-LABEL: test_addi_spill
+; CHECK: add %i0, 1729, [[R:%[gilo][0-7]]]
+; CHECK: stx [[R]], [%fp+{{.+}}]
+; CHECK: ldx [%fp+{{.+}}, %i0
+define i64 @test_addi_spill(i64 %a) {
+entry:
+ %r0 = add i64 %a, 1729
+ %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
+ ret i64 %r0
+}
+
+; CHECK-LABEL: test_subi_spill
+; CHECK: add %i0, -1729, [[R:%[gilo][0-7]]]
+; CHECK: stx [[R]], [%fp+{{.+}}]
+; CHECK: ldx [%fp+{{.+}}, %i0
+define i64 @test_subi_spill(i64 %a) {
+entry:
+ %r0 = sub i64 %a, 1729
+ %0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
+ ret i64 %r0
+}
+
diff --git a/test/CodeGen/SPARC/atomics.ll b/test/CodeGen/SPARC/atomics.ll
new file mode 100644
index 0000000..4e3e7ae
--- /dev/null
+++ b/test/CodeGen/SPARC/atomics.ll
@@ -0,0 +1,153 @@
+; RUN: llc < %s -march=sparcv9 -verify-machineinstrs | FileCheck %s
+
+; CHECK-LABEL: test_atomic_i32
+; CHECK: ld [%o0]
+; CHECK: membar
+; CHECK: ld [%o1]
+; CHECK: membar
+; CHECK: membar
+; CHECK: st {{.+}}, [%o2]
+define i32 @test_atomic_i32(i32* %ptr1, i32* %ptr2, i32* %ptr3) {
+entry:
+ %0 = load atomic i32* %ptr1 acquire, align 8
+ %1 = load atomic i32* %ptr2 acquire, align 8
+ %2 = add i32 %0, %1
+ store atomic i32 %2, i32* %ptr3 release, align 8
+ ret i32 %2
+}
+
+; CHECK-LABEL: test_atomic_i64
+; CHECK: ldx [%o0]
+; CHECK: membar
+; CHECK: ldx [%o1]
+; CHECK: membar
+; CHECK: membar
+; CHECK: stx {{.+}}, [%o2]
+define i64 @test_atomic_i64(i64* %ptr1, i64* %ptr2, i64* %ptr3) {
+entry:
+ %0 = load atomic i64* %ptr1 acquire, align 8
+ %1 = load atomic i64* %ptr2 acquire, align 8
+ %2 = add i64 %0, %1
+ store atomic i64 %2, i64* %ptr3 release, align 8
+ ret i64 %2
+}
+
+; CHECK-LABEL: test_cmpxchg_i32
+; CHECK: or %g0, 123, [[R:%[gilo][0-7]]]
+; CHECK: cas [%o1], %o0, [[R]]
+
+define i32 @test_cmpxchg_i32(i32 %a, i32* %ptr) {
+entry:
+ %b = cmpxchg i32* %ptr, i32 %a, i32 123 monotonic monotonic
+ ret i32 %b
+}
+
+; CHECK-LABEL: test_cmpxchg_i64
+; CHECK: or %g0, 123, [[R:%[gilo][0-7]]]
+; CHECK: casx [%o1], %o0, [[R]]
+
+define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
+entry:
+ %b = cmpxchg i64* %ptr, i64 %a, i64 123 monotonic monotonic
+ ret i64 %b
+}
+
+; CHECK-LABEL: test_swap_i32
+; CHECK: or %g0, 42, [[R:%[gilo][0-7]]]
+; CHECK: swap [%o1], [[R]]
+
+define i32 @test_swap_i32(i32 %a, i32* %ptr) {
+entry:
+ %b = atomicrmw xchg i32* %ptr, i32 42 monotonic
+ ret i32 %b
+}
+
+; CHECK-LABEL: test_swap_i64
+; CHECK: casx [%o1],
+
+define i64 @test_swap_i64(i64 %a, i64* %ptr) {
+entry:
+ %b = atomicrmw xchg i64* %ptr, i64 42 monotonic
+ ret i64 %b
+}
+
+; CHECK-LABEL: test_load_add_32
+; CHECK: membar
+; CHECK: add [[V:%[gilo][0-7]]], %o1, [[U:%[gilo][0-7]]]
+; CHECK: cas [%o0], [[V]], [[U]]
+; CHECK: membar
+define zeroext i32 @test_load_add_32(i32* %p, i32 zeroext %v) {
+entry:
+ %0 = atomicrmw add i32* %p, i32 %v seq_cst
+ ret i32 %0
+}
+
+; CHECK-LABEL: test_load_sub_64
+; CHECK: membar
+; CHECK: sub
+; CHECK: casx [%o0]
+; CHECK: membar
+define zeroext i64 @test_load_sub_64(i64* %p, i64 zeroext %v) {
+entry:
+ %0 = atomicrmw sub i64* %p, i64 %v seq_cst
+ ret i64 %0
+}
+
+; CHECK-LABEL: test_load_xor_32
+; CHECK: membar
+; CHECK: xor
+; CHECK: cas [%o0]
+; CHECK: membar
+define zeroext i32 @test_load_xor_32(i32* %p, i32 zeroext %v) {
+entry:
+ %0 = atomicrmw xor i32* %p, i32 %v seq_cst
+ ret i32 %0
+}
+
+; CHECK-LABEL: test_load_and_32
+; CHECK: membar
+; CHECK: and
+; CHECK-NOT: xor
+; CHECK: cas [%o0]
+; CHECK: membar
+define zeroext i32 @test_load_and_32(i32* %p, i32 zeroext %v) {
+entry:
+ %0 = atomicrmw and i32* %p, i32 %v seq_cst
+ ret i32 %0
+}
+
+; CHECK-LABEL: test_load_nand_32
+; CHECK: membar
+; CHECK: and
+; CHECK: xor
+; CHECK: cas [%o0]
+; CHECK: membar
+define zeroext i32 @test_load_nand_32(i32* %p, i32 zeroext %v) {
+entry:
+ %0 = atomicrmw nand i32* %p, i32 %v seq_cst
+ ret i32 %0
+}
+
+; CHECK-LABEL: test_load_max_64
+; CHECK: membar
+; CHECK: cmp
+; CHECK: movg %xcc
+; CHECK: casx [%o0]
+; CHECK: membar
+define zeroext i64 @test_load_max_64(i64* %p, i64 zeroext %v) {
+entry:
+ %0 = atomicrmw max i64* %p, i64 %v seq_cst
+ ret i64 %0
+}
+
+; CHECK-LABEL: test_load_umin_32
+; CHECK: membar
+; CHECK: cmp
+; CHECK: movleu %icc
+; CHECK: cas [%o0]
+; CHECK: membar
+define zeroext i32 @test_load_umin_32(i32* %p, i32 zeroext %v) {
+entry:
+ %0 = atomicrmw umin i32* %p, i32 %v seq_cst
+ ret i32 %0
+}
diff --git a/test/CodeGen/SPARC/constpool.ll b/test/CodeGen/SPARC/constpool.ll
index b861676..8b0d1d9 100644
--- a/test/CodeGen/SPARC/constpool.ll
+++ b/test/CodeGen/SPARC/constpool.ll
@@ -12,7 +12,7 @@
; abs32: floatCP
; abs32: sethi %hi(.LCPI0_0), %[[R:[gilo][0-7]]]
-; abs32: jmp %o7+8
+; abs32: retl
; abs32: ld [%[[R]]+%lo(.LCPI0_0)], %f
@@ -20,8 +20,8 @@
; abs44: sethi %h44(.LCPI0_0), %[[R1:[gilo][0-7]]]
; abs44: add %[[R1]], %m44(.LCPI0_0), %[[R2:[gilo][0-7]]]
; abs44: sllx %[[R2]], 12, %[[R3:[gilo][0-7]]]
-; abs44: jmp %o7+8
-; abs44: ld [%[[R3]]+%l44(.LCPI0_0)], %f1
+; abs44: retl
+; abs44: ld [%[[R3]]+%l44(.LCPI0_0)], %f0
; abs64: floatCP
@@ -30,8 +30,8 @@
; abs64: sethi %hh(.LCPI0_0), %[[R3:[gilo][0-7]]]
; abs64: add %[[R3]], %hm(.LCPI0_0), %[[R4:[gilo][0-7]]]
; abs64: sllx %[[R4]], 32, %[[R5:[gilo][0-7]]]
-; abs64: jmp %o7+8
-; abs64: ld [%[[R5]]+%[[R2]]], %f1
+; abs64: retl
+; abs64: ld [%[[R5]]+%[[R2]]], %f0
; v8pic32: floatCP
@@ -40,7 +40,7 @@
; v8pic32: add %[[R1]], %lo(.LCPI0_0), %[[Goffs:[gilo][0-7]]]
; v8pic32: ld [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]]
; v8pic32: ld [%[[Gaddr]]], %f0
-; v8pic32: jmp %i7+8
+; v8pic32: ret
; v8pic32: restore
@@ -50,8 +50,8 @@
; v9pic32: sethi %hi(.LCPI0_0), %[[R1:[gilo][0-7]]]
; v9pic32: add %[[R1]], %lo(.LCPI0_0), %[[Goffs:[gilo][0-7]]]
; v9pic32: ldx [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]]
-; v9pic32: ld [%[[Gaddr]]], %f1
-; v9pic32: jmp %i7+8
+; v9pic32: ld [%[[Gaddr]]], %f0
+; v9pic32: ret
; v9pic32: restore
diff --git a/test/CodeGen/SPARC/ctpop.ll b/test/CodeGen/SPARC/ctpop.ll
index 916a414..3a37340 100644
--- a/test/CodeGen/SPARC/ctpop.ll
+++ b/test/CodeGen/SPARC/ctpop.ll
@@ -1,8 +1,29 @@
-; RUN: llc < %s -march=sparc -mattr=-v9 | not grep popc
-; RUN: llc < %s -march=sparc -mattr=+v9 | grep popc
+; RUN: llc < %s -march=sparc -mattr=-v9 | FileCheck %s -check-prefix=V8
+; RUN: llc < %s -march=sparc -mattr=+v9,+popc | FileCheck %s -check-prefix=V9
+; RUN: llc < %s -march=sparc -mcpu=v9 | FileCheck %s -check-prefix=V8
+; RUN: llc < %s -march=sparc -mcpu=ultrasparc | FileCheck %s -check-prefix=V8
+; RUN: llc < %s -march=sparc -mcpu=ultrasparc3 | FileCheck %s -check-prefix=V8
+; RUN: llc < %s -march=sparc -mcpu=niagara | FileCheck %s -check-prefix=V8
+; RUN: llc < %s -march=sparc -mcpu=niagara2 | FileCheck %s -check-prefix=V9
+; RUN: llc < %s -march=sparc -mcpu=niagara3 | FileCheck %s -check-prefix=V9
+; RUN: llc < %s -march=sparc -mcpu=niagara4 | FileCheck %s -check-prefix=V9
+; RUN: llc < %s -march=sparcv9 -mattr=+popc | FileCheck %s -check-prefix=SPARC64
declare i32 @llvm.ctpop.i32(i32)
+; V8-LABEL: test
+; V8-NOT: popc
+
+; V9-LABEL: test
+; V9: srl %o0, 0, %o0
+; V9-NEXT: retl
+; V9-NEXT: popc %o0, %o0
+
+; SPARC64-LABEL: test
+; SPARC64: srl %o0, 0, %o0
+; SPARC64: retl
+; SPARC64: popc %o0, %o0
+
define i32 @test(i32 %X) {
%Y = call i32 @llvm.ctpop.i32( i32 %X ) ; <i32> [#uses=1]
ret i32 %Y
diff --git a/test/CodeGen/SPARC/exception.ll b/test/CodeGen/SPARC/exception.ll
index cb5b6e5..3a3f59f 100644
--- a/test/CodeGen/SPARC/exception.ll
+++ b/test/CodeGen/SPARC/exception.ll
@@ -1,4 +1,9 @@
-; RUN: llc < %s -march=sparc | FileCheck %s
+; RUN: llc < %s -march=sparc -relocation-model=static | FileCheck -check-prefix=V8ABS %s
+; RUN: llc < %s -march=sparc -relocation-model=pic | FileCheck -check-prefix=V8PIC %s
+; RUN: llc < %s -march=sparc -relocation-model=pic -disable-cfi | FileCheck -check-prefix=V8PIC_NOCFI %s
+; RUN: llc < %s -march=sparcv9 -relocation-model=static | FileCheck -check-prefix=V9ABS %s
+; RUN: llc < %s -march=sparcv9 -relocation-model=pic | FileCheck -check-prefix=V9PIC %s
+; RUN: llc < %s -march=sparcv9 -relocation-model=pic -disable-cfi | FileCheck -check-prefix=V9PIC_NOCFI %s
%struct.__fundamental_type_info_pseudo = type { %struct.__type_info_pseudo }
@@ -6,25 +11,99 @@
@_ZTIi = external constant %struct.__fundamental_type_info_pseudo
@_ZTIf = external constant %struct.__fundamental_type_info_pseudo
[email protected] = linker_private unnamed_addr constant [12 x i8] c"catched int\00", align 64
[email protected] = linker_private unnamed_addr constant [14 x i8] c"catched float\00", align 64
[email protected] = private unnamed_addr constant [12 x i8] c"catched int\00", align 64
[email protected] = private unnamed_addr constant [14 x i8] c"catched float\00", align 64
-; CHECK-LABEL: main:
-; CHECK: .cfi_startproc
-; CHECK: .cfi_def_cfa_register 30
-; CHECK: .cfi_window_save
-; CHECK: .cfi_register 15, 31
+; V8ABS-LABEL: main:
+; V8ABS: .cfi_startproc
+; V8ABS: .cfi_personality 0, __gxx_personality_v0
+; V8ABS: .cfi_lsda 0,
+; V8ABS: .cfi_def_cfa_register {{30|%fp}}
+; V8ABS: .cfi_window_save
+; V8ABS: .cfi_register 15, 31
-; CHECK: call __cxa_throw
-; CHECK: call __cxa_throw
+; V8ABS: call __cxa_throw
+; V8ABS: call __cxa_throw
-; CHECK: call __cxa_begin_catch
-; CHECK: call __cxa_end_catch
+; V8ABS: call __cxa_begin_catch
+; V8ABS: call __cxa_end_catch
-; CHECK: call __cxa_begin_catch
-; CHECK: call __cxa_end_catch
+; V8ABS: call __cxa_begin_catch
+; V8ABS: call __cxa_end_catch
-; CHECK: .cfi_endproc
+; V8ABS: .cfi_endproc
+
+; V8PIC-LABEL: main:
+; V8PIC: .cfi_startproc
+; V8PIC: .cfi_personality 155, DW.ref.__gxx_personality_v0
+; V8PIC: .cfi_lsda 27,
+; V8PIC: .cfi_def_cfa_register {{30|%fp}}
+; V8PIC: .cfi_window_save
+; V8PIC: .cfi_register 15, 31
+; V8PIC: .section .gcc_except_table
+; V8PIC-NOT: .section
+; V8PIC: .word %r_disp32(.L_ZTIi.DW.stub)
+; V8PIC: .data
+; V8PIC: .L_ZTIi.DW.stub:
+; V8PIC-NEXT: .word _ZTIi
+
+; V8PIC_NOCFI-LABEL: main:
+; V8PIC_NOCFI: .section .gcc_except_table
+; V8PIC_NOCFI-NOT: .section
+; V8PIC_NOCFI: .word %r_disp32(.L_ZTIi.DW.stub)
+; V8PIC_NOCFI: .data
+; V8PIC_NOCFI: .L_ZTIi.DW.stub:
+; V8PIC_NOCFI-NEXT: .word _ZTIi
+; V8PIC_NOCFI: .section .eh_frame
+; V8PIC_NOCFI-NOT: .section
+; V8PIC_NOCFI: .byte 15 ! CIE Return Address Column
+; V8PIC_NOCFI: .word %r_disp32(DW.ref.__gxx_personality_v0)
+; V8PIC_NOCFI: .byte 12 ! DW_CFA_def_cfa
+; V8PIC_NOCFI: .byte 14 ! Reg 14
+; V8PIC_NOCFI-NEXT: .byte 0 ! Offset 0
+; V8PIC_NOCFI: .word %r_disp32(.Ltmp{{.+}}) ! FDE initial location
+
+
+; V9ABS-LABEL: main:
+; V9ABS: .cfi_startproc
+; V9ABS: .cfi_personality 0, __gxx_personality_v0
+; V9ABS: .cfi_lsda 27,
+; V9ABS: .cfi_def_cfa_register {{30|%fp}}
+; V9ABS: .cfi_window_save
+; V9ABS: .cfi_register 15, 31
+; V9ABS: .section .gcc_except_table
+; V9ABS-NOT: .section
+; V9ABS: .xword _ZTIi
+
+; V9PIC-LABEL: main:
+; V9PIC: .cfi_startproc
+; V9PIC: .cfi_personality 155, DW.ref.__gxx_personality_v0
+; V9PIC: .cfi_lsda 27,
+; V9PIC: .cfi_def_cfa_register {{30|%fp}}
+; V9PIC: .cfi_window_save
+; V9PIC: .cfi_register 15, 31
+; V9PIC: .section .gcc_except_table
+; V9PIC-NOT: .section
+; V9PIC: .word %r_disp32(.L_ZTIi.DW.stub)
+; V9PIC: .data
+; V9PIC: .L_ZTIi.DW.stub:
+; V9PIC-NEXT: .xword _ZTIi
+
+; V9PIC_NOCFI-LABEL: main:
+; V9PIC_NOCFI: .section .gcc_except_table
+; V9PIC_NOCFI-NOT: .section
+; V9PIC_NOCFI: .word %r_disp32(.L_ZTIi.DW.stub)
+; V9PIC_NOCFI: .data
+; V9PIC_NOCFI: .L_ZTIi.DW.stub:
+; V9PIC_NOCFI-NEXT: .xword _ZTIi
+; V9PIC_NOCFI: .section .eh_frame
+; V9PIC_NOCFI-NOT: .section
+; V9PIC_NOCFI: .byte 15 ! CIE Return Address Column
+; V9PIC_NOCFI: .word %r_disp32(DW.ref.__gxx_personality_v0)
+; V9PIC_NOCFI: .byte 12 ! DW_CFA_def_cfa
+; V9PIC_NOCFI-NEXT: .byte 14 ! Reg 14
+; V9PIC_NOCFI: .ascii "\377\017" ! Offset 2047
+; V9PIC_NOCFI: .word %r_disp32(.Ltmp{{.+}}) ! FDE initial location
define i32 @main(i32 %argc, i8** nocapture readnone %argv) unnamed_addr #0 {
entry:
diff --git a/test/CodeGen/SPARC/fp128.ll b/test/CodeGen/SPARC/fp128.ll
index c761361..abd89bf 100644
--- a/test/CodeGen/SPARC/fp128.ll
+++ b/test/CodeGen/SPARC/fp128.ll
@@ -45,14 +45,14 @@
; HARD: std %f{{.+}}, [%[[S1:.+]]]
; HARD-DAG: ldd [%[[S0]]], %f{{.+}}
; HARD-DAG: ldd [%[[S1]]], %f{{.+}}
-; HARD: jmp
+; HARD: jmp %o7+12
; SOFT-LABEL: f128_spill
; SOFT: std %f{{.+}}, [%[[S0:.+]]]
; SOFT: std %f{{.+}}, [%[[S1:.+]]]
; SOFT-DAG: ldd [%[[S0]]], %f{{.+}}
; SOFT-DAG: ldd [%[[S1]]], %f{{.+}}
-; SOFT: jmp
+; SOFT: jmp %o7+12
define void @f128_spill(fp128* noalias sret %scalar.result, fp128* byval %a) {
entry:
@@ -132,13 +132,13 @@
; HARD: ldub
; HARD: faddq
; HARD: stb
-; HARD: jmp
+; HARD: ret
; SOFT-LABEL: fp128_unaligned
; SOFT: ldub
; SOFT: call _Q_add
; SOFT: stb
-; SOFT: jmp
+; SOFT: ret
define void @fp128_unaligned(fp128* %a, fp128* %b, fp128* %c) {
entry:
@@ -232,3 +232,14 @@
store i32 %3, i32* %4, align 8
ret void
}
+
+; SOFT-LABEL: f128_neg
+; SOFT: fnegs
+
+define void @f128_neg(fp128* noalias sret %scalar.result, fp128* byval %a) {
+entry:
+ %0 = load fp128* %a, align 8
+ %1 = fsub fp128 0xL00000000000000008000000000000000, %0
+ store fp128 %1, fp128* %scalar.result, align 8
+ ret void
+}
diff --git a/test/CodeGen/SPARC/globals.ll b/test/CodeGen/SPARC/globals.ll
index 7e3effe..3d3eba2 100644
--- a/test/CodeGen/SPARC/globals.ll
+++ b/test/CodeGen/SPARC/globals.ll
@@ -14,7 +14,7 @@
; abs32: loadG
; abs32: sethi %hi(G), %[[R:[gilo][0-7]]]
-; abs32: jmp %o7+8
+; abs32: retl
; abs32: ldub [%[[R]]+%lo(G)], %o0
@@ -22,7 +22,7 @@
; abs44: sethi %h44(G), %[[R1:[gilo][0-7]]]
; abs44: add %[[R1]], %m44(G), %[[R2:[gilo][0-7]]]
; abs44: sllx %[[R2]], 12, %[[R3:[gilo][0-7]]]
-; abs44: jmp %o7+8
+; abs44: retl
; abs44: ldub [%[[R3]]+%l44(G)], %o0
@@ -32,7 +32,7 @@
; abs64: sethi %hh(G), %[[R3:[gilo][0-7]]]
; abs64: add %[[R3]], %hm(G), %[[R4:[gilo][0-7]]]
; abs64: sllx %[[R4]], 32, %[[R5:[gilo][0-7]]]
-; abs64: jmp %o7+8
+; abs64: retl
; abs64: ldub [%[[R5]]+%[[R2]]], %o0
@@ -42,7 +42,7 @@
; v8pic32: add %[[R1]], %lo(G), %[[Goffs:[gilo][0-7]]]
; v8pic32: ld [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]]
; v8pic32: ldub [%[[Gaddr]]], %i0
-; v8pic32: jmp %i7+8
+; v8pic32: ret
; v8pic32: restore
@@ -52,6 +52,6 @@
; v9pic32: add %[[R1]], %lo(G), %[[Goffs:[gilo][0-7]]]
; v9pic32: ldx [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]]
; v9pic32: ldub [%[[Gaddr]]], %i0
-; v9pic32: jmp %i7+8
+; v9pic32: ret
; v9pic32: restore
diff --git a/test/CodeGen/SPARC/inlineasm.ll b/test/CodeGen/SPARC/inlineasm.ll
new file mode 100644
index 0000000..2650533
--- /dev/null
+++ b/test/CodeGen/SPARC/inlineasm.ll
@@ -0,0 +1,45 @@
+; RUN: llc -march=sparc <%s | FileCheck %s
+
+; CHECK-LABEL: test_constraint_r
+; CHECK: add %o1, %o0, %o0
+define i32 @test_constraint_r(i32 %a, i32 %b) {
+entry:
+ %0 = tail call i32 asm sideeffect "add $2, $1, $0", "=r,r,r"(i32 %a, i32 %b)
+ ret i32 %0
+}
+
+; CHECK-LABEL: test_constraint_I
+; CHECK: add %o0, 1023, %o0
+define i32 @test_constraint_I(i32 %a) {
+entry:
+ %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 1023)
+ ret i32 %0
+}
+
+; CHECK-LABEL: test_constraint_I_neg
+; CHECK: add %o0, -4096, %o0
+define i32 @test_constraint_I_neg(i32 %a) {
+entry:
+ %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 -4096)
+ ret i32 %0
+}
+
+; CHECK-LABEL: test_constraint_I_largeimm
+; CHECK: sethi 9, [[R0:%[gilo][0-7]]]
+; CHECK: or [[R0]], 784, [[R1:%[gilo][0-7]]]
+; CHECK: add %o0, [[R1]], %o0
+define i32 @test_constraint_I_largeimm(i32 %a) {
+entry:
+ %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 10000)
+ ret i32 %0
+}
+
+; CHECK-LABEL: test_constraint_reg
+; CHECK: ldda [%o1] 43, %g2
+; CHECK: ldda [%o1] 43, %g3
+define void @test_constraint_reg(i32 %s, i32* %ptr) {
+entry:
+ %0 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={r2},r,n"(i32* %ptr, i32 43)
+ %1 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={g3},r,n"(i32* %ptr, i32 43)
+ ret void
+}
diff --git a/test/CodeGen/SPARC/leafproc.ll b/test/CodeGen/SPARC/leafproc.ll
index 0a7ae08..963fac0 100644
--- a/test/CodeGen/SPARC/leafproc.ll
+++ b/test/CodeGen/SPARC/leafproc.ll
@@ -1,7 +1,7 @@
; RUN: llc -march=sparc -disable-sparc-leaf-proc=0 < %s | FileCheck %s
; CHECK-LABEL: func_nobody:
-; CHECK: jmp %o7+8
+; CHECK: retl
; CHECK-NEXT: nop
define void @func_nobody() {
entry:
@@ -10,7 +10,7 @@
; CHECK-LABEL: return_int_const:
-; CHECK: jmp %o7+8
+; CHECK: retl
; CHECK-NEXT: or %g0, 1729, %o0
define i32 @return_int_const() {
entry:
@@ -19,7 +19,7 @@
; CHECK-LABEL: return_double_const:
; CHECK: sethi
-; CHECK: jmp %o7+8
+; CHECK: retl
; CHECK-NEXT: ldd {{.*}}, %f0
define double @return_double_const() {
@@ -29,7 +29,7 @@
; CHECK-LABEL: leaf_proc_with_args:
; CHECK: add {{%o[0-1]}}, {{%o[0-1]}}, [[R:%[go][0-7]]]
-; CHECK: jmp %o7+8
+; CHECK: retl
; CHECK-NEXT: add [[R]], %o2, %o0
define i32 @leaf_proc_with_args(i32 %a, i32 %b, i32 %c) {
@@ -42,7 +42,7 @@
; CHECK-LABEL: leaf_proc_with_args_in_stack:
; CHECK-DAG: ld [%sp+92], {{%[go][0-7]}}
; CHECK-DAG: ld [%sp+96], {{%[go][0-7]}}
-; CHECK: jmp %o7+8
+; CHECK: retl
; CHECK-NEXT: add {{.*}}, %o0
define i32 @leaf_proc_with_args_in_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) {
entry:
@@ -63,7 +63,7 @@
; CHECK: or %g0, 2, [[R2:%[go][0-7]]]
; CHECK: st [[R2]], [%sp+100]
; CHECK: ld {{.+}}, %o0
-; CHECK: jmp %o7+8
+; CHECK: retl
; CHECK-NEXT: add %sp, 104, %sp
define i32 @leaf_proc_with_local_array(i32 %a, i32 %b, i32 %c) {
diff --git a/test/CodeGen/SPARC/mature-mc-support.ll b/test/CodeGen/SPARC/mature-mc-support.ll
new file mode 100644
index 0000000..4ed3309
--- /dev/null
+++ b/test/CodeGen/SPARC/mature-mc-support.ll
@@ -0,0 +1,20 @@
+; Test that inline assembly is parsed by the MC layer when MC support is mature
+; (even when the output is assembly).
+; FIXME: SPARC doesn't use the integrated assembler by default in all cases
+; so we only test that -filetype=obj tries to parse the assembly.
+
+; SKIP: not llc -march=sparc < %s > /dev/null 2> %t1
+; SKIP: FileCheck %s < %t1
+
+; RUN: not llc -march=sparc -filetype=obj < %s > /dev/null 2> %t2
+; RUN: FileCheck %s < %t2
+
+; SKIP: not llc -march=sparcv9 < %s > /dev/null 2> %t3
+; SKIP: FileCheck %s < %t3
+
+; RUN: not llc -march=sparcv9 -filetype=obj < %s > /dev/null 2> %t4
+; RUN: FileCheck %s < %t4
+
+module asm " .this_directive_is_very_unlikely_to_exist"
+
+; CHECK: LLVM ERROR: Error parsing inline asm
diff --git a/test/CodeGen/SPARC/missinglabel.ll b/test/CodeGen/SPARC/missinglabel.ll
new file mode 100644
index 0000000..bcf384b
--- /dev/null
+++ b/test/CodeGen/SPARC/missinglabel.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -verify-machineinstrs | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64-S128"
+target triple = "sparc64-unknown-linux-gnu"
+
+define void @f() align 2 {
+entry:
+; CHECK: %xcc, .LBB0_1
+ %cmp = icmp eq i64 undef, 0
+ br i1 %cmp, label %targetblock, label %cond.false
+
+cond.false:
+ unreachable
+
+; CHECK: .LBB0_1: ! %targetblock
+targetblock:
+ br i1 undef, label %cond.false.i83, label %exit.i85
+
+cond.false.i83:
+ unreachable
+
+exit.i85:
+ unreachable
+}
diff --git a/test/CodeGen/SPARC/obj-relocs.ll b/test/CodeGen/SPARC/obj-relocs.ll
new file mode 100644
index 0000000..6d57598
--- /dev/null
+++ b/test/CodeGen/SPARC/obj-relocs.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=sparcv9 -filetype=obj --relocation-model=static | llvm-readobj -r | FileCheck %s --check-prefix=CHECK-ABS
+; RUN: llc < %s -march=sparcv9 -filetype=obj --relocation-model=pic | llvm-readobj -r | FileCheck %s --check-prefix=CHECK-PIC
+
+;CHECK-ABS: Relocations [
+;CHECK-ABS: 0x{{[0-9,A-F]+}} R_SPARC_H44 AGlobalVar 0x0
+;CHECK-ABS: 0x{{[0-9,A-F]+}} R_SPARC_M44 AGlobalVar 0x0
+;CHECK-ABS: 0x{{[0-9,A-F]+}} R_SPARC_L44 AGlobalVar 0x0
+;CHECK-ABS: 0x{{[0-9,A-F]+}} R_SPARC_WDISP30 bar 0x0
+;CHECK-ABS:]
+
+; CHECK-PIC: Relocations [
+; CHECK-PIC: 0x{{[0-9,A-F]+}} R_SPARC_PC22 _GLOBAL_OFFSET_TABLE_ 0x4
+; CHECK-PIC: 0x{{[0-9,A-F]+}} R_SPARC_PC10 _GLOBAL_OFFSET_TABLE_ 0x8
+; CHECK-PIC: 0x{{[0-9,A-F]+}} R_SPARC_GOT22 AGlobalVar 0x0
+; CHECK-PIC: 0x{{[0-9,A-F]+}} R_SPARC_GOT10 AGlobalVar 0x0
+; CHECK-PIC: 0x{{[0-9,A-F]+}} R_SPARC_WPLT30 bar 0x0
+; CHECK-PIC: ]
+
+
+@AGlobalVar = global i64 0, align 8
+
+define i64 @foo(i64 %a) {
+entry:
+ %0 = load i64* @AGlobalVar, align 4
+ %1 = add i64 %a, %0
+ %2 = call i64 @bar(i64 %1)
+ ret i64 %2
+}
+
+
+declare i64 @bar(i64)
diff --git a/test/CodeGen/SPARC/parts.ll b/test/CodeGen/SPARC/parts.ll
new file mode 100644
index 0000000..57add49
--- /dev/null
+++ b/test/CodeGen/SPARC/parts.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=sparcv9 | FileCheck %s
+
+; CHECK-LABEL: test
+; CHECK: srl %i1, 0, %o2
+; CHECK-NEXT: or %g0, %i2, %o0
+; CHECK-NEXT: call __ashlti3
+; CHECK-NEXT: or %g0, %i3, %o1
+; CHECK-NEXT: or %g0, %o0, %i0
+
+define i128 @test(i128 %a, i128 %b) {
+entry:
+ %tmp = shl i128 %b, %a
+ ret i128 %tmp
+}
diff --git a/test/CodeGen/SPARC/rem.ll b/test/CodeGen/SPARC/rem.ll
index abef1fc..3b01a55 100644
--- a/test/CodeGen/SPARC/rem.ll
+++ b/test/CodeGen/SPARC/rem.ll
@@ -3,7 +3,7 @@
; CHECK-LABEL: test1:
; CHECK: sdivx %o0, %o1, %o2
; CHECK-NEXT: mulx %o2, %o1, %o1
-; CHECK-NEXT: jmp %o7+8
+; CHECK-NEXT: retl
; CHECK-NEXT: sub %o0, %o1, %o0
define i64 @test1(i64 %X, i64 %Y) {
@@ -14,7 +14,7 @@
; CHECK-LABEL: test2:
; CHECK: udivx %o0, %o1, %o2
; CHECK-NEXT: mulx %o2, %o1, %o1
-; CHECK-NEXT: jmp %o7+8
+; CHECK-NEXT: retl
; CHECK-NEXT: sub %o0, %o1, %o0
define i64 @test2(i64 %X, i64 %Y) {
diff --git a/test/CodeGen/SPARC/setjmp.ll b/test/CodeGen/SPARC/setjmp.ll
index 39984fb..a31cd70 100644
--- a/test/CodeGen/SPARC/setjmp.ll
+++ b/test/CodeGen/SPARC/setjmp.ll
@@ -7,7 +7,7 @@
%struct.__jmp_buf_tag = type { [3 x i32], i32, %0 }
@jenv = common unnamed_addr global %struct.jmpbuf_env* null
[email protected] = linker_private unnamed_addr constant [30 x i8] c"in bar with jmp_buf's id: %d\0A\00", align 64
[email protected] = private unnamed_addr constant [30 x i8] c"in bar with jmp_buf's id: %d\0A\00", align 64
; CHECK-LABEL: foo
; CHECK-DAG: st {{.+}}, [%i0]
diff --git a/test/CodeGen/SPARC/spillsize.ll b/test/CodeGen/SPARC/spillsize.ll
new file mode 100644
index 0000000..64f63f9
--- /dev/null
+++ b/test/CodeGen/SPARC/spillsize.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -verify-machineinstrs | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64-S128"
+target triple = "sparcv9"
+
+; CHECK-LABEL: spill4
+; This function spills two values: %p and the materialized large constant.
+; Both must use 8-byte spill and fill instructions.
+; CHECK: stx %{{..}}, [%fp+
+; CHECK: stx %{{..}}, [%fp+
+; CHECK: ldx [%fp+
+; CHECK: ldx [%fp+
+define void @spill4(i64* nocapture %p) {
+entry:
+ %val0 = load i64* %p
+ %cmp0 = icmp ult i64 %val0, 385672958347594845
+ %cm80 = zext i1 %cmp0 to i64
+ store i64 %cm80, i64* %p, align 8
+ tail call void asm sideeffect "", "~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{g2},~{g3},~{g4},~{g5},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o7}"()
+ %arrayidx1 = getelementptr inbounds i64* %p, i64 1
+ %val = load i64* %arrayidx1
+ %cmp = icmp ult i64 %val, 385672958347594845
+ %cm8 = select i1 %cmp, i64 10, i64 20
+ store i64 %cm8, i64* %arrayidx1, align 8
+ ret void
+}
diff --git a/test/CodeGen/SPARC/tls.ll b/test/CodeGen/SPARC/tls.ll
index 660ddff..ce3e005 100644
--- a/test/CodeGen/SPARC/tls.ll
+++ b/test/CodeGen/SPARC/tls.ll
@@ -3,6 +3,10 @@
; RUN: llc <%s -march=sparc -relocation-model=pic | FileCheck %s --check-prefix=pic
; RUN: llc <%s -march=sparcv9 -relocation-model=pic | FileCheck %s --check-prefix=pic
+; RUN: llc <%s -march=sparc -relocation-model=static -filetype=obj | llvm-readobj -r | FileCheck %s --check-prefix=v8abs-obj
+; RUN: llc <%s -march=sparcv9 -relocation-model=static -filetype=obj | llvm-readobj -r | FileCheck %s --check-prefix=v9abs-obj
+; RUN: llc <%s -march=sparc -relocation-model=pic -filetype=obj | llvm-readobj -r | FileCheck %s --check-prefix=pic-obj
+; RUN: llc <%s -march=sparcv9 -relocation-model=pic -filetype=obj | llvm-readobj -r | FileCheck %s --check-prefix=pic-obj
@local_symbol = internal thread_local global i32 0
@extern_symbol = external thread_local global i32
@@ -38,8 +42,7 @@
; v8abs-LABEL: test_tls_extern
-; v8abs: or {{%[goli][0-7]}}, %lo(_GLOBAL_OFFSET_TABLE_+{{.+}}), [[PC:%[goli][0-7]]]
-; v8abs: add [[PC]], %o7, %[[GOTBASE:[goli][0-7]]]
+; v8abs: or {{%[goli][0-7]}}, %lo(_GLOBAL_OFFSET_TABLE_), %[[GOTBASE:[goli][0-7]]]
; v8abs: sethi %tie_hi22(extern_symbol), [[R1:%[goli][0-7]]]
; v8abs: add [[R1]], %tie_lo10(extern_symbol), %[[R2:[goli][0-7]]]
; v8abs: ld [%[[GOTBASE]]+%[[R2]]], [[R3:%[goli][0-7]]], %tie_ld(extern_symbol)
@@ -47,8 +50,7 @@
; v8abs: ld [%[[R4]]]
; v9abs-LABEL: test_tls_extern
-; v9abs: or {{%[goli][0-7]}}, %lo(_GLOBAL_OFFSET_TABLE_+{{.+}}), [[PC:%[goli][0-7]]]
-; v9abs: add [[PC]], %o7, %[[GOTBASE:[goli][0-7]]]
+; v9abs: or {{%[goli][0-7]}}, %l44(_GLOBAL_OFFSET_TABLE_), %[[GOTBASE:[goli][0-7]]]
; v9abs: sethi %tie_hi22(extern_symbol), [[R1:%[goli][0-7]]]
; v9abs: add [[R1]], %tie_lo10(extern_symbol), %[[R2:[goli][0-7]]]
; v9abs: ldx [%[[GOTBASE]]+%[[R2]]], [[R3:%[goli][0-7]]], %tie_ldx(extern_symbol)
@@ -71,3 +73,47 @@
store i32 %1, i32* @extern_symbol, align 4
ret i32 %1
}
+
+
+; v8abs-obj: Relocations [
+; v8abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LE_HIX22 local_symbol 0x0
+; v8abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LE_LOX10 local_symbol 0x0
+; v8abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_HI22 _GLOBAL_OFFSET_TABLE_ 0x0
+; v8abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_LO10 _GLOBAL_OFFSET_TABLE_ 0x0
+; v8abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_IE_HI22 extern_symbol 0x0
+; v8abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_IE_LO10 extern_symbol 0x0
+; v8abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_IE_LD extern_symbol 0x0
+; v8abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_IE_ADD extern_symbol 0x0
+; v8abs-obj: ]
+
+; v9abs-obj: Relocations [
+; v9abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LE_HIX22 local_symbol 0x0
+; v9abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LE_LOX10 local_symbol 0x0
+; v9abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_H44 _GLOBAL_OFFSET_TABLE_ 0x0
+; v9abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_M44 _GLOBAL_OFFSET_TABLE_ 0x0
+; v9abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_L44 _GLOBAL_OFFSET_TABLE_ 0x0
+; v9abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_IE_HI22 extern_symbol 0x0
+; v9abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_IE_LO10 extern_symbol 0x0
+; v9abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_IE_LDX extern_symbol 0x0
+; v9abs-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_IE_ADD extern_symbol 0x0
+; v9abs-obj: ]
+
+; pic-obj: Relocations [
+; pic-obj: Section (2) .rela.text {
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_PC22 _GLOBAL_OFFSET_TABLE_ 0x4
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_PC10 _GLOBAL_OFFSET_TABLE_ 0x8
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDO_HIX22 local_symbol 0x0
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDO_LOX10 local_symbol 0x0
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDM_HI22 local_symbol 0x0
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDM_LO10 local_symbol 0x0
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDM_ADD local_symbol 0x0
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDM_CALL local_symbol 0x0
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_LDO_ADD local_symbol 0x0
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_PC22 _GLOBAL_OFFSET_TABLE_ 0x4
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_PC10 _GLOBAL_OFFSET_TABLE_ 0x8
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_GD_HI22 extern_symbol 0x0
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_GD_LO10 extern_symbol 0x0
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_GD_ADD extern_symbol 0x0
+; pic-obj: 0x{{[0-9,A-F]+}} R_SPARC_TLS_GD_CALL extern_symbol 0x0
+; pic-obj: ]
+
diff --git a/test/CodeGen/SPARC/trap.ll b/test/CodeGen/SPARC/trap.ll
new file mode 100644
index 0000000..b72a63c
--- /dev/null
+++ b/test/CodeGen/SPARC/trap.ll
@@ -0,0 +1,11 @@
+; RUN: llc -mtriple=sparc-linux-gnu < %s -show-mc-encoding | FileCheck %s
+
+define void @test1() {
+ tail call void @llvm.trap()
+ unreachable
+
+; CHECK-LABEL: test1:
+; CHECK: ta 5 ! encoding: [0x91,0xd0,0x20,0x05]
+}
+
+declare void @llvm.trap()
