commit 3f3373166227b13e762e20d2fb51eadfa6a2d653
author bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> Wed Aug 20 23:02:09 2003 +0000
committer bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> Wed Aug 20 23:02:09 2003 +0000
tree 61211017f0428c56b245c36b357aa0e2de4ec91e
parent d05e66d217f8f83487c3b1d3015a67316b47645f

pop ss, mov ss, x and sti disable irqs for the next instruction - began dispatch optimization by adding new x86 cpu 'hidden' flags


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@372 c046a42c-6fe2-441c-8c8c-71466251a162

cpu-exec.c

diff --git a/cpu-exec.c b/cpu-exec.c
index 39bb933..7899a90 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -186,7 +186,8 @@
 #if defined(TARGET_I386)
                     /* if hardware interrupt pending, we execute it */
                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
-                        (env->eflags & IF_MASK)) {
+                        (env->eflags & IF_MASK) && 
+                        !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
                         int intno;
                         intno = cpu_x86_get_pic_interrupt(env);
                         if (loglevel) {
@@ -233,21 +234,20 @@
 #endif
                 }
 #endif
-                /* we compute the CPU state. We assume it will not
-                   change during the whole generated block. */
+                /* we record a subset of the CPU state. It will
+                   always be the same before a given translated block
+                   is executed. */
 #if defined(TARGET_I386)
                 flags = (env->segs[R_CS].flags & DESC_B_MASK)
-                    >> (DESC_B_SHIFT - GEN_FLAG_CODE32_SHIFT);
+                    >> (DESC_B_SHIFT - HF_CS32_SHIFT);
                 flags |= (env->segs[R_SS].flags & DESC_B_MASK)
-                    >> (DESC_B_SHIFT - GEN_FLAG_SS32_SHIFT);
+                    >> (DESC_B_SHIFT - HF_SS32_SHIFT);
                 flags |= (((unsigned long)env->segs[R_DS].base | 
                            (unsigned long)env->segs[R_ES].base |
                            (unsigned long)env->segs[R_SS].base) != 0) << 
-                    GEN_FLAG_ADDSEG_SHIFT;
-                flags |= env->cpl << GEN_FLAG_CPL_SHIFT;
-                flags |= env->soft_mmu << GEN_FLAG_SOFT_MMU_SHIFT;
-                flags |= (env->eflags & VM_MASK) >> (17 - GEN_FLAG_VM_SHIFT);
-                flags |= (env->eflags & (IOPL_MASK | TF_MASK));
+                    HF_ADDSEG_SHIFT;
+                flags |= env->hflags;
+                flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
                 cs_base = env->segs[R_CS].base;
                 pc = cs_base + env->eip;
 #elif defined(TARGET_ARM)
@@ -337,8 +337,8 @@
                 /* reset soft MMU for next block (it can currently
                    only be set by a memory fault) */
 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
-                if (env->soft_mmu) {
-                    env->soft_mmu = 0;
+                if (env->hflags & HF_SOFTMMU_MASK) {
+                    env->hflags &= ~HF_SOFTMMU_MASK;
                     /* do not allow linking to another block */
                     T0 = 0;
                 }
@@ -499,7 +499,7 @@
         raise_exception_err(EXCP0E_PAGE, env->error_code);
     } else {
         /* activate soft MMU for this block */
-        env->soft_mmu = 1;
+        env->hflags |= HF_SOFTMMU_MASK;
         sigprocmask(SIG_SETMASK, old_set, NULL);
         cpu_loop_exit();
     }