commit 4fa5d7722db71a4bd6f01e607cf01c758c150dd1
author bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> Sun Jan 30 22:57:54 2005 +0000
committer bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> Sun Jan 30 22:57:54 2005 +0000
tree 25172771ceec9e4e6ad2543feb59ba47404d123a
parent 64b3ab24391c47869a09d082ee073e9832718fc2

fixed sparc cpu load/save


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1255 c046a42c-6fe2-441c-8c8c-71466251a162

vl.c

diff --git a/vl.c b/vl.c
index 107845e..21c7775 100644
--- a/vl.c
+++ b/vl.c
@@ -2328,28 +2328,27 @@
     int i;
     uint32_t tmp;
 
-    for(i = 1; i < 8; i++)
-        qemu_put_be32s(f, &env->gregs[i]);
-    tmp = env->regwptr - env->regbase;
-    qemu_put_be32s(f, &tmp);
-    for(i = 1; i < NWINDOWS * 16 + 8; i++)
-        qemu_put_be32s(f, &env->regbase[i]);
+    for(i = 0; i < 8; i++)
+        qemu_put_betls(f, &env->gregs[i]);
+    for(i = 0; i < NWINDOWS * 16; i++)
+        qemu_put_betls(f, &env->regbase[i]);
 
     /* FPU */
-    for(i = 0; i < 32; i++) {
-        uint64_t mant;
-        uint16_t exp;
-	cpu_get_fp64(&mant, &exp, env->fpr[i]);
-        qemu_put_be64(f, mant);
-        qemu_put_be16(f, exp);
+    for(i = 0; i < TARGET_FPREGS; i++) {
+        union {
+            TARGET_FPREG_T f;
+            target_ulong i;
+        } u;
+        u.f = env->fpr[i];
+        qemu_put_betl(f, u.i);
     }
-    qemu_put_be32s(f, &env->pc);
-    qemu_put_be32s(f, &env->npc);
-    qemu_put_be32s(f, &env->y);
+
+    qemu_put_betls(f, &env->pc);
+    qemu_put_betls(f, &env->npc);
+    qemu_put_betls(f, &env->y);
     tmp = GET_PSR(env);
-    qemu_put_be32s(f, &tmp);
+    qemu_put_be32(f, tmp);
     qemu_put_be32s(f, &env->fsr);
-    qemu_put_be32s(f, &env->cwp);
     qemu_put_be32s(f, &env->wim);
     qemu_put_be32s(f, &env->tbr);
     /* MMU */
@@ -2363,34 +2362,35 @@
     int i;
     uint32_t tmp;
 
-    for(i = 1; i < 8; i++)
-        qemu_get_be32s(f, &env->gregs[i]);
-    qemu_get_be32s(f, &tmp);
-    env->regwptr = env->regbase + tmp;
-    for(i = 1; i < NWINDOWS * 16 + 8; i++)
-        qemu_get_be32s(f, &env->regbase[i]);
+    for(i = 0; i < 8; i++)
+        qemu_get_betls(f, &env->gregs[i]);
+    for(i = 0; i < NWINDOWS * 16; i++)
+        qemu_get_betls(f, &env->regbase[i]);
 
     /* FPU */
-    for(i = 0; i < 32; i++) {
-        uint64_t mant;
-        uint16_t exp;
-
-        qemu_get_be64s(f, &mant);
-        qemu_get_be16s(f, &exp);
-	env->fpr[i] = cpu_put_fp64(mant, exp);
+    for(i = 0; i < TARGET_FPREGS; i++) {
+        union {
+            TARGET_FPREG_T f;
+            target_ulong i;
+        } u;
+        u.i = qemu_get_betl(f);
+        env->fpr[i] = u.f;
     }
-    qemu_get_be32s(f, &env->pc);
-    qemu_get_be32s(f, &env->npc);
-    qemu_get_be32s(f, &env->y);
-    qemu_get_be32s(f, &tmp);
+
+    qemu_get_betls(f, &env->pc);
+    qemu_get_betls(f, &env->npc);
+    qemu_get_betls(f, &env->y);
+    tmp = qemu_get_be32(f);
+    env->cwp = 0; /* needed to ensure that the wrapping registers are
+                     correctly updated */
     PUT_PSR(env, tmp);
     qemu_get_be32s(f, &env->fsr);
-    qemu_get_be32s(f, &env->cwp);
     qemu_get_be32s(f, &env->wim);
     qemu_get_be32s(f, &env->tbr);
     /* MMU */
     for(i = 0; i < 16; i++)
         qemu_get_be32s(f, &env->mmuregs[i]);
+
     tlb_flush(env, 1);
     return 0;
 }