find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
diff --git a/hw/acpi.c b/hw/acpi.c
index 871a737..add8cc8 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -1,8 +1,8 @@
/*
* ACPI implementation
- *
+ *
* Copyright (c) 2006 Fabrice Bellard
- *
+ *
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License version 2 as published by the Free Software Foundation.
@@ -87,9 +87,9 @@
{
int sci_level, pmsts;
int64_t expire_time;
-
+
pmsts = get_pmsts(s);
- sci_level = (((pmsts & s->pmen) &
+ sci_level = (((pmsts & s->pmen) &
(RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
qemu_set_irq(s->dev.irq[0], sci_level);
/* schedule a timer interruption if needed */
@@ -239,7 +239,7 @@
{
PIIX4PMState *s = opaque;
uint32_t val;
-
+
addr &= 1;
if (addr == 0) {
val = s->apmc;
@@ -413,7 +413,7 @@
}
}
-static void pm_write_config(PCIDevice *d,
+static void pm_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len)
{
pci_default_write_config(d, address, val, len);
@@ -480,9 +480,9 @@
pci_conf[0x0b] = 0x06; // bridge device
pci_conf[0x0e] = 0x00; // header_type
pci_conf[0x3d] = 0x01; // interrupt pin 1
-
+
pci_conf[0x40] = 0x01; /* PM io base read only bit */
-
+
register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
diff --git a/hw/adb.c b/hw/adb.c
index 3f664a9..756c079 100644
--- a/hw/adb.c
+++ b/hw/adb.c
@@ -1,8 +1,8 @@
/*
* QEMU ADB support
- *
+ *
* Copyright (c) 2004 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -96,9 +96,9 @@
return olen;
}
-ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
- ADBDeviceRequest *devreq,
- ADBDeviceReset *devreset,
+ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
+ ADBDeviceRequest *devreq,
+ ADBDeviceReset *devreset,
void *opaque)
{
ADBDevice *d;
@@ -299,31 +299,31 @@
if (s->last_buttons_state == s->buttons_state &&
s->dx == 0 && s->dy == 0)
return 0;
-
+
dx = s->dx;
if (dx < -63)
dx = -63;
else if (dx > 63)
dx = 63;
-
+
dy = s->dy;
if (dy < -63)
dy = -63;
else if (dy > 63)
dy = 63;
-
+
s->dx -= dx;
s->dy -= dy;
s->last_buttons_state = s->buttons_state;
-
+
dx &= 0x7f;
dy &= 0x7f;
-
+
if (!(s->buttons_state & MOUSE_EVENT_LBUTTON))
dy |= 0x80;
if (!(s->buttons_state & MOUSE_EVENT_RBUTTON))
dx |= 0x80;
-
+
obuf[0] = dy;
obuf[1] = dx;
return 2;
@@ -334,7 +334,7 @@
{
MouseState *s = d->opaque;
int cmd, reg, olen;
-
+
if ((buf[0] & 0x0f) == ADB_FLUSH) {
/* flush mouse fifo */
s->buttons_state = s->last_buttons_state;
diff --git a/hw/alpha_palcode.c b/hw/alpha_palcode.c
index 0fe9d96..8df7d89 100644
--- a/hw/alpha_palcode.c
+++ b/hw/alpha_palcode.c
@@ -1,6 +1,6 @@
/*
* Alpha emulation - PALcode emulation for qemu.
- *
+ *
* Copyright (c) 2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
@@ -62,7 +62,7 @@
mtpr(TB_TAG);
mtpr(TB_CTL);
/* This commits the TB update */
- mtpr(ITB_PTE);
+ mtpr(ITB_PTE);
}
static void update_dtb ();
@@ -937,7 +937,7 @@
}
}
*paddr = (pfn << page_bits) | (vaddr & page_mask);
-
+
return 0;
}
@@ -998,7 +998,7 @@
if (env->user_mode_only) {
ret = 2;
- } else {
+ } else {
ret = virtual_to_physical(env, &physical, &zbits, &prot,
address, is_user, rw);
}
diff --git a/hw/an5206.c b/hw/an5206.c
index 379f48e..94ecccb 100644
--- a/hw/an5206.c
+++ b/hw/an5206.c
@@ -1,4 +1,4 @@
-/*
+/*
* Arnewsh 5206 ColdFire system emulation.
*
* Copyright (c) 2007 CodeSourcery.
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 38c56a2..1de3353 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -2,7 +2,7 @@
* QEMU Ultrasparc APB PCI host
*
* Copyright (c) 2006 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -233,7 +233,7 @@
cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, pci_ioport);
cpu_register_physical_memory(mem_base, 0x10000000, pci_mem_data); // XXX size should be 4G-prom
- d = pci_register_device(s->bus, "Advanced PCI Bus", sizeof(PCIDevice),
+ d = pci_register_device(s->bus, "Advanced PCI Bus", sizeof(PCIDevice),
0, NULL, NULL);
d->config[0x00] = 0x8e; // vendor_id : Sun
d->config[0x01] = 0x10;
diff --git a/hw/apic.c b/hw/apic.c
index d503d45..bbe44fa 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -1,6 +1,6 @@
/*
* APIC support
- *
+ *
* Copyright (c) 2004-2005 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
@@ -182,7 +182,7 @@
}\
}
-static void apic_bus_deliver(const uint32_t *deliver_bitmask,
+static void apic_bus_deliver(const uint32_t *deliver_bitmask,
uint8_t delivery_mode,
uint8_t vector_num, uint8_t polarity,
uint8_t trigger_mode)
@@ -219,10 +219,10 @@
case APIC_DM_INIT:
/* normal INIT IPI sent to processors */
- foreach_apic(apic_iter, deliver_bitmask,
+ foreach_apic(apic_iter, deliver_bitmask,
apic_init_ipi(apic_iter) );
return;
-
+
case APIC_DM_EXTINT:
/* handled in I/O APIC code */
break;
@@ -231,7 +231,7 @@
return;
}
- foreach_apic(apic_iter, deliver_bitmask,
+ foreach_apic(apic_iter, deliver_bitmask,
apic_set_irq(apic_iter, vector_num, trigger_mode) );
}
@@ -241,7 +241,7 @@
#ifdef DEBUG_APIC
printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
#endif
- s->apicbase = (val & 0xfffff000) |
+ s->apicbase = (val & 0xfffff000) |
(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
/* if disabled, cannot be enabled again */
if (!(val & MSR_IA32_APICBASE_ENABLE)) {
@@ -407,7 +407,7 @@
if (!(env->hflags & HF_HALTED_MASK))
return;
env->eip = 0;
- cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
+ cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
0xffff, 0);
env->hflags &= ~HF_HALTED_MASK;
}
@@ -443,7 +443,7 @@
int trig_mode = (s->icr[0] >> 15) & 1;
int level = (s->icr[0] >> 14) & 1;
if (level == 0 && trig_mode == 1) {
- foreach_apic(apic_iter, deliver_bitmask,
+ foreach_apic(apic_iter, deliver_bitmask,
apic_iter->arb_id = apic_iter->id );
return;
}
@@ -451,7 +451,7 @@
break;
case APIC_DM_SIPI:
- foreach_apic(apic_iter, deliver_bitmask,
+ foreach_apic(apic_iter, deliver_bitmask,
apic_startup(apic_iter, vector_num) );
return;
}
@@ -471,7 +471,7 @@
return -1;
if (!(s->spurious_vec & APIC_SV_ENABLE))
return -1;
-
+
/* XXX: spurious IRQ handling */
intno = get_highest_priority_int(s->irr);
if (intno < 0)
@@ -488,7 +488,7 @@
{
int64_t d;
uint32_t val;
- d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
+ d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
s->count_shift;
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
/* periodic */
@@ -505,9 +505,9 @@
static void apic_timer_update(APICState *s, int64_t current_time)
{
int64_t next_time, d;
-
+
if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
- d = (current_time - s->initial_count_load_time) >>
+ d = (current_time - s->initial_count_load_time) >>
s->count_shift;
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
@@ -818,14 +818,14 @@
s->id = last_apic_id++;
env->cpuid_apic_id = s->id;
s->cpu_env = env;
- s->apicbase = 0xfee00000 |
+ s->apicbase = 0xfee00000 |
(s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
/* XXX: mapping more APICs at the same memory location */
if (apic_io_memory == 0) {
/* NOTE: the APIC is directly connected to the CPU - it is not
on the global memory bus. */
- apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
+ apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
apic_mem_write, NULL);
cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
apic_io_memory);
@@ -834,7 +834,7 @@
register_savevm("apic", s->id, 2, apic_save, apic_load, s);
qemu_register_reset(apic_reset, s);
-
+
local_apics[s->id] = s;
return 0;
}
@@ -868,9 +868,9 @@
vector = pic_read_irq(isa_pic);
else
vector = entry & 0xff;
-
+
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
- apic_bus_deliver(deliver_bitmask, delivery_mode,
+ apic_bus_deliver(deliver_bitmask, delivery_mode,
vector, polarity, trig_mode);
}
}
@@ -1036,12 +1036,12 @@
ioapic_reset(s);
s->id = last_apic_id++;
- io_memory = cpu_register_io_memory(0, ioapic_mem_read,
+ io_memory = cpu_register_io_memory(0, ioapic_mem_read,
ioapic_mem_write, s);
cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
qemu_register_reset(ioapic_reset, s);
-
+
return s;
}
diff --git a/hw/arm_boot.c b/hw/arm_boot.c
index ccc9ecb..7a99b41 100644
--- a/hw/arm_boot.c
+++ b/hw/arm_boot.c
@@ -1,4 +1,4 @@
-/*
+/*
* ARM kernel loader.
*
* Copyright (c) 2006 CodeSourcery.
@@ -30,8 +30,8 @@
cpu_reset(env);
if (env->kernel_filename)
- arm_load_kernel(env, env->ram_size, env->kernel_filename,
- env->kernel_cmdline, env->initrd_filename,
+ arm_load_kernel(env, env->ram_size, env->kernel_filename,
+ env->kernel_cmdline, env->initrd_filename,
env->board_id, env->loader_start);
}
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 58d8404..8cd7182 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -1,4 +1,4 @@
-/*
+/*
* ARM AMBA Generic/Distributed Interrupt Controller
*
* Copyright (c) 2006 CodeSourcery.
@@ -115,7 +115,7 @@
gic_state *s = (gic_state *)opaque;
/* The first external input line is internal interrupt 32. */
irq += 32;
- if (level == GIC_TEST_LEVEL(irq))
+ if (level == GIC_TEST_LEVEL(irq))
return;
if (level) {
diff --git a/hw/arm_pic.c b/hw/arm_pic.c
index dcc1198..7f4a694 100644
--- a/hw/arm_pic.c
+++ b/hw/arm_pic.c
@@ -1,4 +1,4 @@
-/*
+/*
* Generic ARM Programmable Interrupt Controller support.
*
* Copyright (c) 2006 CodeSourcery.
diff --git a/hw/arm_pic.h b/hw/arm_pic.h
index 6c5ed17..1eba2ba 100644
--- a/hw/arm_pic.h
+++ b/hw/arm_pic.h
@@ -1,4 +1,4 @@
-/*
+/*
* Generic ARM Programmable Interrupt Controller support.
*
* Copyright (c) 2006 CodeSourcery.
diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
index 600889d..468a494 100644
--- a/hw/arm_sysctl.c
+++ b/hw/arm_sysctl.c
@@ -1,4 +1,4 @@
-/*
+/*
* Status and system control registers for ARM RealView/Versatile boards.
*
* Copyright (c) 2006 CodeSourcery.
diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index c0a0aa9..3df386a 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -1,4 +1,4 @@
-/*
+/*
* ARM PrimeCell Timer modules.
*
* Copyright (c) 2005-2006 CodeSourcery.
diff --git a/hw/cdrom.c b/hw/cdrom.c
index a43b417..18c7e31 100644
--- a/hw/cdrom.c
+++ b/hw/cdrom.c
@@ -1,8 +1,8 @@
/*
* QEMU ATAPI CD-ROM Emulator
- *
+ *
* Copyright (c) 2006 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -41,7 +41,7 @@
{
uint8_t *q;
int len;
-
+
if (start_track > 1 && start_track != 0xaa)
return -1;
q = buf + 2;
@@ -85,7 +85,7 @@
{
uint8_t *q;
int len;
-
+
q = buf + 2;
*q++ = 1; /* first session */
*q++ = 1; /* last session */
@@ -101,7 +101,7 @@
*q++ = 1; /* first track */
*q++ = 0x00; /* disk type */
*q++ = 0x00;
-
+
*q++ = 1; /* session number */
*q++ = 0x14; /* data track */
*q++ = 0; /* track number */
@@ -113,7 +113,7 @@
*q++ = 1; /* last track */
*q++ = 0x00;
*q++ = 0x00;
-
+
*q++ = 1; /* session number */
*q++ = 0x14; /* data track */
*q++ = 0; /* track number */
@@ -138,14 +138,14 @@
*q++ = 0; /* sec */
*q++ = 0; /* frame */
if (msf) {
- *q++ = 0;
+ *q++ = 0;
lba_to_msf(q, 0);
q += 3;
} else {
- *q++ = 0;
- *q++ = 0;
- *q++ = 0;
- *q++ = 0;
+ *q++ = 0;
+ *q++ = 0;
+ *q++ = 0;
+ *q++ = 0;
}
len = q - buf;
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index d8633c9..febac44 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -1,9 +1,9 @@
/*
* QEMU Cirrus CLGD 54xx VGA Emulator.
- *
+ *
* Copyright (c) 2004 Fabrice Bellard
* Copyright (c) 2004 Makoto Suzuki (suzu)
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -275,7 +275,7 @@
} PCICirrusVGAState;
static uint8_t rop_to_index[256];
-
+
/***************************************
*
* prototypes.
@@ -590,7 +590,7 @@
s->cirrus_blt_fgcol = le16_to_cpu(color);
break;
case 3:
- s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
+ s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
(s->gr[0x11] << 8) | (s->gr[0x13] << 16);
break;
default:
@@ -614,7 +614,7 @@
s->cirrus_blt_bgcol = le16_to_cpu(color);
break;
case 3:
- s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
+ s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
(s->gr[0x10] << 8) | (s->gr[0x12] << 16);
break;
default:
@@ -653,7 +653,7 @@
dst = s->vram_ptr + s->cirrus_blt_dstaddr;
(*s->cirrus_rop) (s, dst, src,
- s->cirrus_blt_dstpitch, 0,
+ s->cirrus_blt_dstpitch, 0,
s->cirrus_blt_width, s->cirrus_blt_height);
cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
s->cirrus_blt_dstpitch, s->cirrus_blt_width,
@@ -668,7 +668,7 @@
cirrus_fill_t rop_func;
rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
- rop_func(s, s->vram_ptr + s->cirrus_blt_dstaddr,
+ rop_func(s, s->vram_ptr + s->cirrus_blt_dstaddr,
s->cirrus_blt_dstpitch,
s->cirrus_blt_width, s->cirrus_blt_height);
cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
@@ -687,7 +687,7 @@
static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
{
return cirrus_bitblt_common_patterncopy(s,
- s->vram_ptr +
+ s->vram_ptr +
(s->cirrus_blt_srcaddr & ~7));
}
@@ -788,7 +788,7 @@
{
int copy_count;
uint8_t *end_ptr;
-
+
if (s->cirrus_srccounter > 0) {
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
@@ -854,7 +854,7 @@
} else {
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
- if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
+ if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
s->cirrus_blt_srcpitch = ((w + 31) >> 5);
else
s->cirrus_blt_srcpitch = ((w + 7) >> 3);
@@ -913,7 +913,7 @@
#ifdef DEBUG_BITBLT
printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
- blt_rop,
+ blt_rop,
s->cirrus_blt_mode,
s->cirrus_blt_modeext,
s->cirrus_blt_width,
@@ -957,16 +957,16 @@
}
if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
- (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
+ (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
CIRRUS_BLTMODE_TRANSPARENTCOMP |
- CIRRUS_BLTMODE_PATTERNCOPY |
- CIRRUS_BLTMODE_COLOREXPAND)) ==
+ CIRRUS_BLTMODE_PATTERNCOPY |
+ CIRRUS_BLTMODE_COLOREXPAND)) ==
(CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
cirrus_bitblt_fgcol(s);
cirrus_bitblt_solidfill(s, blt_rop);
} else {
- if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
- CIRRUS_BLTMODE_PATTERNCOPY)) ==
+ if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
+ CIRRUS_BLTMODE_PATTERNCOPY)) ==
CIRRUS_BLTMODE_COLOREXPAND) {
if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
@@ -1059,7 +1059,7 @@
*
***************************************/
-static void cirrus_get_offsets(VGAState *s1,
+static void cirrus_get_offsets(VGAState *s1,
uint32_t *pline_offset,
uint32_t *pstart_addr,
uint32_t *pline_compare)
@@ -1079,7 +1079,7 @@
| ((s->cr[0x1d] & 0x80) << 12);
*pstart_addr = start_addr;
- line_compare = s->cr[0x18] |
+ line_compare = s->cr[0x18] |
((s->cr[0x07] & 0x10) << 4) |
((s->cr[0x09] & 0x40) << 3);
*pline_compare = line_compare;
@@ -1148,10 +1148,10 @@
static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
{
int width, height;
-
+
width = (s->cr[0x01] + 1) * 8;
- height = s->cr[0x12] |
- ((s->cr[0x07] & 0x02) << 7) |
+ height = s->cr[0x12] |
+ ((s->cr[0x07] & 0x02) << 7) |
((s->cr[0x07] & 0x40) << 3);
height = (height + 1);
/* interlace support */
@@ -2036,7 +2036,7 @@
return v;
}
-static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t mem_value)
{
CirrusVGAState *s = opaque;
@@ -2147,7 +2147,7 @@
static inline void invalidate_cursor1(CirrusVGAState *s)
{
if (s->last_hw_cursor_size) {
- vga_invalidate_scanlines((VGAState *)s,
+ vga_invalidate_scanlines((VGAState *)s,
s->last_hw_cursor_y + s->last_hw_cursor_y_start,
s->last_hw_cursor_y + s->last_hw_cursor_y_end);
}
@@ -2223,7 +2223,7 @@
s->last_hw_cursor_y != s->hw_cursor_y) {
invalidate_cursor1(s);
-
+
s->last_hw_cursor_size = size;
s->last_hw_cursor_x = s->hw_cursor_x;
s->last_hw_cursor_y = s->hw_cursor_y;
@@ -2240,8 +2240,8 @@
unsigned int color0, color1;
const uint8_t *palette, *src;
uint32_t content;
-
- if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
+
+ if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
return;
/* fast test to see if the cursor intersects with the scan line */
if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
@@ -2252,7 +2252,7 @@
if (scr_y < s->hw_cursor_y ||
scr_y >= (s->hw_cursor_y + h))
return;
-
+
src = s->vram_ptr + s->real_vram_size - 16 * 1024;
if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
src += (s->sr[0x13] & 0x3c) * 256;
@@ -2282,11 +2282,11 @@
x2 = s->last_scr_width;
w = x2 - x1;
palette = s->cirrus_hidden_palette;
- color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
- c6_to_8(palette[0x0 * 3 + 1]),
+ color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
+ c6_to_8(palette[0x0 * 3 + 1]),
c6_to_8(palette[0x0 * 3 + 2]));
- color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
- c6_to_8(palette[0xf * 3 + 1]),
+ color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
+ c6_to_8(palette[0xf * 3 + 1]),
c6_to_8(palette[0xf * 3 + 2]));
bpp = ((s->ds->depth + 7) >> 3);
d1 += x1 * bpp;
@@ -2321,7 +2321,7 @@
addr &= s->cirrus_addr_mask;
- if (((s->sr[0x17] & 0x44) == 0x44) &&
+ if (((s->sr[0x17] & 0x44) == 0x44) &&
((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
/* memory-mapped I/O */
ret = cirrus_mmio_blt_read(s, addr & 0xff);
@@ -2379,8 +2379,8 @@
unsigned mode;
addr &= s->cirrus_addr_mask;
-
- if (((s->sr[0x17] & 0x44) == 0x44) &&
+
+ if (((s->sr[0x17] & 0x44) == 0x44) &&
((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
/* memory-mapped I/O */
cirrus_mmio_blt_write(s, addr & 0xff, val);
@@ -2600,7 +2600,7 @@
} else if (s->gr[0x0B] & 0x02) {
goto generic_io;
}
-
+
mode = s->gr[0x05] & 0x7;
if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
@@ -3110,9 +3110,9 @@
register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
- vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
+ vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
cirrus_vga_mem_write, s);
- cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
+ cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
vga_io_memory);
s->sr[0x06] = 0x0f;
@@ -3134,7 +3134,7 @@
} else {
s->sr[0x1F] = 0x22; // MemClock
s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
- if (is_pci)
+ if (is_pci)
s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
else
s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
@@ -3184,14 +3184,14 @@
*
***************************************/
-void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
+void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
{
CirrusVGAState *s;
s = qemu_mallocz(sizeof(CirrusVGAState));
-
- vga_common_init((VGAState *)s,
+
+ vga_common_init((VGAState *)s,
ds, vga_ram_base, vga_ram_offset, vga_ram_size);
cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
/* XXX ISA-LFB support */
@@ -3224,19 +3224,19 @@
s->cirrus_mmio_io_addr);
}
-void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
+void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
{
PCICirrusVGAState *d;
uint8_t *pci_conf;
CirrusVGAState *s;
int device_id;
-
+
device_id = CIRRUS_ID_CLGD5446;
/* setup PCI configuration registers */
- d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
- sizeof(PCICirrusVGAState),
+ d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
+ sizeof(PCICirrusVGAState),
-1, NULL, NULL);
pci_conf = d->dev.config;
pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
@@ -3250,7 +3250,7 @@
/* setup VGA */
s = &d->cirrus_vga;
- vga_common_init((VGAState *)s,
+ vga_common_init((VGAState *)s,
ds, vga_ram_base, vga_ram_offset, vga_ram_size);
cirrus_init_common(s, device_id, 1);
diff --git a/hw/cirrus_vga_rop.h b/hw/cirrus_vga_rop.h
index fbee6ed..3d6a1fe 100644
--- a/hw/cirrus_vga_rop.h
+++ b/hw/cirrus_vga_rop.h
@@ -1,8 +1,8 @@
/*
* QEMU Cirrus CLGD 54xx VGA Emulator.
- *
+ *
* Copyright (c) 2004 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
diff --git a/hw/cirrus_vga_rop2.h b/hw/cirrus_vga_rop2.h
index da11d0f..91f0db8 100644
--- a/hw/cirrus_vga_rop2.h
+++ b/hw/cirrus_vga_rop2.h
@@ -1,8 +1,8 @@
/*
* QEMU Cirrus CLGD 54xx VGA Emulator.
- *
+ *
* Copyright (c) 2004 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -34,13 +34,13 @@
#define PUTPIXEL() ROP_OP(((uint32_t *)d)[0], col)
#else
#error unsupported DEPTH
-#endif
+#endif
static void
glue(glue(glue(cirrus_patternfill_, ROP_NAME), _),DEPTH)
(CirrusVGAState * s, uint8_t * dst,
- const uint8_t * src,
- int dstpitch, int srcpitch,
+ const uint8_t * src,
+ int dstpitch, int srcpitch,
int bltwidth, int bltheight)
{
uint8_t *d;
@@ -94,8 +94,8 @@
static void
glue(glue(glue(cirrus_colorexpand_transp_, ROP_NAME), _),DEPTH)
(CirrusVGAState * s, uint8_t * dst,
- const uint8_t * src,
- int dstpitch, int srcpitch,
+ const uint8_t * src,
+ int dstpitch, int srcpitch,
int bltwidth, int bltheight)
{
uint8_t *d;
@@ -143,8 +143,8 @@
static void
glue(glue(glue(cirrus_colorexpand_, ROP_NAME), _),DEPTH)
(CirrusVGAState * s, uint8_t * dst,
- const uint8_t * src,
- int dstpitch, int srcpitch,
+ const uint8_t * src,
+ int dstpitch, int srcpitch,
int bltwidth, int bltheight)
{
uint32_t colors[2];
@@ -179,8 +179,8 @@
static void
glue(glue(glue(cirrus_colorexpand_pattern_transp_, ROP_NAME), _),DEPTH)
(CirrusVGAState * s, uint8_t * dst,
- const uint8_t * src,
- int dstpitch, int srcpitch,
+ const uint8_t * src,
+ int dstpitch, int srcpitch,
int bltwidth, int bltheight)
{
uint8_t *d;
@@ -223,8 +223,8 @@
static void
glue(glue(glue(cirrus_colorexpand_pattern_, ROP_NAME), _),DEPTH)
(CirrusVGAState * s, uint8_t * dst,
- const uint8_t * src,
- int dstpitch, int srcpitch,
+ const uint8_t * src,
+ int dstpitch, int srcpitch,
int bltwidth, int bltheight)
{
uint32_t colors[2];
@@ -254,10 +254,10 @@
}
}
-static void
+static void
glue(glue(glue(cirrus_fill_, ROP_NAME), _),DEPTH)
(CirrusVGAState *s,
- uint8_t *dst, int dst_pitch,
+ uint8_t *dst, int dst_pitch,
int width, int height)
{
uint8_t *d, *d1;
diff --git a/hw/cuda.c b/hw/cuda.c
index dc143e2..75ceea1 100644
--- a/hw/cuda.c
+++ b/hw/cuda.c
@@ -1,8 +1,8 @@
/*
* QEMU CUDA support
- *
+ *
* Copyright (c) 2004 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -94,7 +94,7 @@
#define RTC_OFFSET 2082844800
typedef struct CUDATimer {
- int index;
+ int index;
uint16_t latch;
uint16_t counter_value; /* counter value at load time */
int64_t load_time;
@@ -116,10 +116,10 @@
uint8_t anh; /* A-side data, no handshake */
CUDATimer timers[2];
-
+
uint8_t last_b; /* last value of B register */
uint8_t last_acr; /* last value of B register */
-
+
int data_in_size;
int data_in_index;
int data_out_index;
@@ -135,9 +135,9 @@
ADBBusState adb_bus;
static void cuda_update(CUDAState *s);
-static void cuda_receive_packet_from_host(CUDAState *s,
+static void cuda_receive_packet_from_host(CUDAState *s,
const uint8_t *data, int len);
-static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
+static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
int64_t current_time);
static void cuda_update_irq(CUDAState *s)
@@ -154,7 +154,7 @@
int64_t d;
unsigned int counter;
- d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
+ d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
CUDA_TIMER_FREQ, ticks_per_sec);
if (s->index == 0) {
/* the timer goes down from latch to -1 (period of latch + 2) */
@@ -162,7 +162,7 @@
counter = (s->counter_value - d) & 0xffff;
} else {
counter = (d - (s->counter_value + 1)) % (s->latch + 2);
- counter = (s->latch - counter) & 0xffff;
+ counter = (s->latch - counter) & 0xffff;
}
} else {
counter = (s->counter_value - d) & 0xffff;
@@ -187,16 +187,16 @@
unsigned int counter;
/* current counter value */
- d = muldiv64(current_time - s->load_time,
+ d = muldiv64(current_time - s->load_time,
CUDA_TIMER_FREQ, ticks_per_sec);
/* the timer goes down from latch to -1 (period of latch + 2) */
if (d <= (s->counter_value + 1)) {
counter = (s->counter_value - d) & 0xffff;
} else {
counter = (d - (s->counter_value + 1)) % (s->latch + 2);
- counter = (s->latch - counter) & 0xffff;
+ counter = (s->latch - counter) & 0xffff;
}
-
+
/* Note: we consider the irq is raised on 0 */
if (counter == 0xffff) {
next_time = d + s->latch + 1;
@@ -207,18 +207,18 @@
}
#if 0
#ifdef DEBUG_CUDA
- printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
+ printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
s->latch, d, next_time - d);
#endif
#endif
- next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
+ next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
s->load_time;
if (next_time <= current_time)
next_time = current_time + 1;
return next_time;
}
-static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
+static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
int64_t current_time)
{
if (!ti->timer)
@@ -296,7 +296,7 @@
break;
case 13:
val = s->ifr;
- if (s->ifr & s->ier)
+ if (s->ifr & s->ier)
val |= 0x80;
break;
case 14:
@@ -317,7 +317,7 @@
static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
CUDAState *s = opaque;
-
+
addr = (addr >> 9) & 0xf;
#ifdef DEBUG_CUDA
printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
@@ -470,7 +470,7 @@
}
}
-static void cuda_send_packet_to_host(CUDAState *s,
+static void cuda_send_packet_to_host(CUDAState *s,
const uint8_t *data, int len)
{
#ifdef DEBUG_CUDA_PACKET
@@ -502,12 +502,12 @@
obuf[1] = 0x40; /* polled data */
cuda_send_packet_to_host(s, obuf, olen + 2);
}
- qemu_mod_timer(s->adb_poll_timer,
- qemu_get_clock(vm_clock) +
+ qemu_mod_timer(s->adb_poll_timer,
+ qemu_get_clock(vm_clock) +
(ticks_per_sec / CUDA_ADB_POLL_FREQ));
}
-static void cuda_receive_packet(CUDAState *s,
+static void cuda_receive_packet(CUDAState *s,
const uint8_t *data, int len)
{
uint8_t obuf[16];
@@ -519,8 +519,8 @@
if (autopoll != s->autopoll) {
s->autopoll = autopoll;
if (autopoll) {
- qemu_mod_timer(s->adb_poll_timer,
- qemu_get_clock(vm_clock) +
+ qemu_mod_timer(s->adb_poll_timer,
+ qemu_get_clock(vm_clock) +
(ticks_per_sec / CUDA_ADB_POLL_FREQ));
} else {
qemu_del_timer(s->adb_poll_timer);
@@ -562,7 +562,7 @@
}
}
-static void cuda_receive_packet_from_host(CUDAState *s,
+static void cuda_receive_packet_from_host(CUDAState *s,
const uint8_t *data, int len)
{
#ifdef DEBUG_CUDA_PACKET
diff --git a/hw/eepro100.c b/hw/eepro100.c
index 36b0925..975aeb1 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -1618,7 +1618,7 @@
for (i = 0; i < 3; i++)
qemu_get_be32s(f, &s->region[i]);
qemu_get_buffer(f, s->macaddr, 6);
- for (i = 0; i < 19; i++)
+ for (i = 0; i < 19; i++)
qemu_get_be32s(f, &s->statcounter[i]);
for (i = 0; i < 32; i++)
qemu_get_be16s(f, &s->mdimem[i]);
@@ -1697,7 +1697,7 @@
for (i = 0; i < 3; i++)
qemu_put_be32s(f, &s->region[i]);
qemu_put_buffer(f, s->macaddr, 6);
- for (i = 0; i < 19; i++)
+ for (i = 0; i < 19; i++)
qemu_put_be32s(f, &s->statcounter[i]);
for (i = 0; i < 32; i++)
qemu_put_be16s(f, &s->mdimem[i]);
diff --git a/hw/esp.c b/hw/esp.c
index 10d4cad..0d22ce3 100644
--- a/hw/esp.c
+++ b/hw/esp.c
@@ -1,8 +1,8 @@
/*
* QEMU ESP/NCR53C9x emulation
- *
+ *
* Copyright (c) 2005-2006 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -531,7 +531,7 @@
static int esp_load(QEMUFile *f, void *opaque, int version_id)
{
ESPState *s = opaque;
-
+
if (version_id != 3)
return -EINVAL; // Cannot emulate 2
diff --git a/hw/fdc.c b/hw/fdc.c
index 98a3c31..dcd1d46 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -1,8 +1,8 @@
/*
* QEMU Floppy disk emulator (Intel 82078)
- *
+ *
* Copyright (c) 2003, 2007 Jocelyn Mayer
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -217,7 +217,7 @@
{ FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
{ FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
{ FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
- /* 320 kB 5"1/4 floppy disks */
+ /* 320 kB 5"1/4 floppy disks */
{ FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
{ FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
/* 360 kB must match 5"1/4 better than 3"1/2... */
@@ -467,7 +467,7 @@
return fdctrl_read(opaque, (uint32_t)reg);
}
-static void fdctrl_write_mem (void *opaque,
+static void fdctrl_write_mem (void *opaque,
target_phys_addr_t reg, uint32_t value)
{
fdctrl_write(opaque, (uint32_t)reg, value);
@@ -578,7 +578,7 @@
fdctrl_reset(s, 0);
}
-fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
+fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
target_phys_addr_t io_base,
BlockDriverState **fds)
{
@@ -590,7 +590,7 @@
fdctrl = qemu_mallocz(sizeof(fdctrl_t));
if (!fdctrl)
return NULL;
- fdctrl->result_timer = qemu_new_timer(vm_clock,
+ fdctrl->result_timer = qemu_new_timer(vm_clock,
fdctrl_result_timer, fdctrl);
fdctrl->version = 0x90; /* Intel 82078 controller */
@@ -842,7 +842,7 @@
static int fdctrl_media_changed(fdrive_t *drv)
{
int ret;
- if (!drv->bs)
+ if (!drv->bs)
return 0;
ret = bdrv_media_changed(drv->bs);
if (ret) {
@@ -1141,7 +1141,7 @@
cur_drv->sect = 1;
if (FD_MULTI_TRACK(fdctrl->data_state)) {
if (cur_drv->head == 0 &&
- (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
+ (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
cur_drv->head = 1;
} else {
cur_drv->head = 0;
@@ -1732,7 +1732,7 @@
FLOPPY_DPRINTF("treat READ_ID command\n");
/* XXX: should set main status register to busy */
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
- qemu_mod_timer(fdctrl->result_timer,
+ qemu_mod_timer(fdctrl->result_timer,
qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
break;
case 0x4C:
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index 74d4efc..a2f938c 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -2,7 +2,7 @@
* QEMU Grackle (heathrow PPC) PCI host
*
* Copyright (c) 2006 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -95,13 +95,13 @@
s->bus = pci_register_bus(pci_grackle_set_irq, pci_grackle_map_irq,
pic, 0, 0);
- pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
+ pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
pci_grackle_config_write, s);
pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,
pci_grackle_write, s);
cpu_register_physical_memory(base, 0x1000, pci_mem_config);
cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);
- d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice),
+ d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice),
0, NULL, NULL);
d->config[0x00] = 0x57; // vendor_id
d->config[0x01] = 0x10;
@@ -118,12 +118,12 @@
d->config[0x1a] = 0x00; // subordinate_bus
d->config[0x1c] = 0x00;
d->config[0x1d] = 0x00;
-
+
d->config[0x20] = 0x00; // memory_base
d->config[0x21] = 0x00;
d->config[0x22] = 0x01; // memory_limit
d->config[0x23] = 0x00;
-
+
d->config[0x24] = 0x00; // prefetchable_memory_base
d->config[0x25] = 0x00;
d->config[0x26] = 0x00; // prefetchable_memory_limit
@@ -145,12 +145,12 @@
d->config[0x1a] = 0x1; // subordinate_bus
d->config[0x1c] = 0x10; // io_base
d->config[0x1d] = 0x20; // io_limit
-
+
d->config[0x20] = 0x80; // memory_base
d->config[0x21] = 0x80;
d->config[0x22] = 0x90; // memory_limit
d->config[0x23] = 0x80;
-
+
d->config[0x24] = 0x00; // prefetchable_memory_base
d->config[0x25] = 0x84;
d->config[0x26] = 0x00; // prefetchable_memory_limit
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index b027ce8..26821e8 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -2,7 +2,7 @@
* QEMU GT64120 PCI host
*
* Copyright (c) 2006,2007 Aurelien Jarno
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -287,10 +287,10 @@
/* Update IO mapping */
if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
{
- /* Unmap old IO address */
+ /* Unmap old IO address */
if (s->PCI0IO_length)
{
- cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
+ cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
}
/* Map new IO address */
s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
@@ -604,7 +604,7 @@
case GT_CPUERR_DATAHI:
case GT_CPUERR_PARITY:
/* Emulated memory has no error, always return the initial
- values */
+ values */
val = s->regs[saddr];
break;
@@ -614,7 +614,7 @@
/* Reading those register should empty all FIFO on the PCI
bus, which are not emulated. The return value should be
a random value that should be ignored. */
- val = 0xc000ffee;
+ val = 0xc000ffee;
break;
/* ECC */
@@ -624,7 +624,7 @@
case GT_ECC_CALC:
case GT_ECC_ERRADDR:
/* Emulated memory has no error, always return the initial
- values */
+ values */
val = s->regs[saddr];
break;
@@ -663,7 +663,7 @@
val = s->regs[saddr];
break;
case GT_PCI0_IACK:
- /* Read the IRQ number */
+ /* Read the IRQ number */
val = pic_read_irq(isa_pic);
break;
diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c
index c0edaea..a31d24b 100644
--- a/hw/heathrow_pic.c
+++ b/hw/heathrow_pic.c
@@ -1,8 +1,8 @@
/*
* Heathrow PIC support (standard PowerMac PIC)
- *
+ *
* Copyright (c) 2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -88,7 +88,7 @@
HeathrowPIC *pic;
unsigned int n;
uint32_t value;
-
+
n = ((addr & 0xfff) - 0x10) >> 4;
if (n >= 2) {
value = 0;
@@ -159,7 +159,7 @@
qemu_irq *heathrow_pic_init(int *pmem_index)
{
HeathrowPICS *s;
-
+
s = qemu_mallocz(sizeof(HeathrowPICS));
s->pics[0].level_triggered = 0;
s->pics[1].level_triggered = 0x1ff00000;
diff --git a/hw/i2c.c b/hw/i2c.c
index 3fc0733..f0d117c 100644
--- a/hw/i2c.c
+++ b/hw/i2c.c
@@ -1,4 +1,4 @@
-/*
+/*
* QEMU I2C bus interface.
*
* Copyright (c) 2007 CodeSourcery.
diff --git a/hw/i8254.c b/hw/i8254.c
index f0b41d7..db8a1b9 100644
--- a/hw/i8254.c
+++ b/hw/i8254.c
@@ -1,8 +1,8 @@
/*
* QEMU 8253/8254 interval timer emulation
- *
+ *
* Copyright (c) 2003-2004 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -121,7 +121,7 @@
}
/* return -1 if no transition will occur. */
-static int64_t pit_get_next_transition_time(PITChannelState *s,
+static int64_t pit_get_next_transition_time(PITChannelState *s,
int64_t current_time)
{
uint64_t d, next_time, base;
@@ -147,7 +147,7 @@
case 3:
base = (d / s->count) * s->count;
period2 = ((s->count + 1) >> 1);
- if ((d - base) < period2)
+ if ((d - base) < period2)
next_time = base + period2;
else
next_time = base + s->count;
@@ -309,7 +309,7 @@
PITState *pit = opaque;
int ret, count;
PITChannelState *s;
-
+
addr &= 3;
s = &pit->channels[addr];
if (s->status_latched) {
@@ -369,7 +369,7 @@
qemu_set_irq(s->irq, irq_level);
#ifdef DEBUG_PIT
printf("irq_level=%d next_delay=%f\n",
- irq_level,
+ irq_level,
(double)(expire_time - current_time) / ticks_per_sec);
#endif
s->next_transition_time = expire_time;
@@ -391,7 +391,7 @@
PITState *pit = opaque;
PITChannelState *s;
int i;
-
+
for(i = 0; i < 3; i++) {
s = &pit->channels[i];
qemu_put_be32s(f, &s->count);
@@ -419,7 +419,7 @@
PITState *pit = opaque;
PITChannelState *s;
int i;
-
+
if (version_id != 1)
return -EINVAL;
diff --git a/hw/i8259.c b/hw/i8259.c
index 5063770..09aabe2 100644
--- a/hw/i8259.c
+++ b/hw/i8259.c
@@ -1,8 +1,8 @@
/*
* QEMU 8259 interrupt controller emulation
- *
+ *
* Copyright (c) 2003-2004 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -152,10 +152,10 @@
{
int i;
for(i = 0; i < 2; i++) {
- printf("pic%d: imr=%x irr=%x padd=%d\n",
- i, s->pics[i].imr, s->pics[i].irr,
+ printf("pic%d: imr=%x irr=%x padd=%d\n",
+ i, s->pics[i].imr, s->pics[i].irr,
s->pics[i].priority_add);
-
+
}
}
printf("pic: cpu_interrupt\n");
@@ -243,10 +243,10 @@
intno = s->pics[0].irq_base + irq;
}
pic_update_irq(s);
-
+
#ifdef DEBUG_IRQ_LATENCY
- printf("IRQ%d latency=%0.3fus\n",
- irq,
+ printf("IRQ%d latency=%0.3fus\n",
+ irq,
(double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
#endif
#if defined(DEBUG_PIC)
@@ -429,7 +429,7 @@
ret = pic_poll_read(&s->pics[1], 0x80) + 8;
/* Prepare for ISR read */
s->pics[0].read_reg_select = 1;
-
+
return ret;
}
@@ -448,7 +448,7 @@
static void pic_save(QEMUFile *f, void *opaque)
{
PicState *s = opaque;
-
+
qemu_put_8s(f, &s->last_irr);
qemu_put_8s(f, &s->irr);
qemu_put_8s(f, &s->imr);
@@ -470,7 +470,7 @@
static int pic_load(QEMUFile *f, void *opaque, int version_id)
{
PicState *s = opaque;
-
+
if (version_id != 1)
return -EINVAL;
@@ -510,15 +510,15 @@
{
int i;
PicState *s;
-
+
if (!isa_pic)
return;
for(i=0;i<2;i++) {
s = &isa_pic->pics[i];
term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
- i, s->irr, s->imr, s->isr, s->priority_add,
- s->irq_base, s->read_reg_select, s->elcr,
+ i, s->irr, s->imr, s->isr, s->priority_add,
+ s->irq_base, s->read_reg_select, s->elcr,
s->special_fully_nested_mode);
}
}
diff --git a/hw/ide.c b/hw/ide.c
index 4e17db3..c3b0e11 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -1,9 +1,9 @@
/*
* QEMU IDE disk and CD-ROM Emulator
- *
+ *
* Copyright (c) 2003 Fabrice Bellard
* Copyright (c) 2006 Openedhand Ltd.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -156,7 +156,7 @@
#define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
#define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
#define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
-#define WIN_GETMEDIASTATUS 0xDA
+#define WIN_GETMEDIASTATUS 0xDA
#define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
#define WIN_POSTBOOT 0xDC
#define WIN_PREBOOT 0xDD
@@ -248,12 +248,12 @@
#define GPCMD_VERIFY_10 0x2f
#define GPCMD_WRITE_10 0x2a
#define GPCMD_WRITE_AND_VERIFY_10 0x2e
-/* This is listed as optional in ATAPI 2.6, but is (curiously)
+/* This is listed as optional in ATAPI 2.6, but is (curiously)
* missing from Mt. Fuji, Table 57. It _is_ mentioned in Mt. Fuji
* Table 377 as an MMC command for SCSi devices though... Most ATAPI
* drives support it. */
#define GPCMD_SET_SPEED 0xbb
-/* This seems to be a SCSI specific CD-ROM opcode
+/* This seems to be a SCSI specific CD-ROM opcode
* to play data at track/index */
#define GPCMD_PLAYAUDIO_TI 0x48
/*
@@ -339,7 +339,7 @@
/* set for lba48 access */
uint8_t lba48;
/* depends on bit 4 in select, only meaningful for drive 0 */
- struct IDEState *cur_drive;
+ struct IDEState *cur_drive;
BlockDriverState *bs;
/* ATAPI specific */
uint8_t sense_key;
@@ -392,7 +392,7 @@
uint8_t cmd;
uint8_t status;
uint32_t addr;
-
+
struct PCIIDEState *pci_dev;
/* current transfer state */
uint32_t cur_addr;
@@ -457,11 +457,11 @@
memset(s->io_buffer, 0, 512);
p = (uint16_t *)s->io_buffer;
put_le16(p + 0, 0x0040);
- put_le16(p + 1, s->cylinders);
+ put_le16(p + 1, s->cylinders);
put_le16(p + 3, s->heads);
put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
put_le16(p + 5, 512); /* XXX: retired, remove ? */
- put_le16(p + 6, s->sectors);
+ put_le16(p + 6, s->sectors);
snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
padstr((uint8_t *)(p + 10), buf, 20); /* serial number */
put_le16(p + 20, 3); /* XXX: retired, remove ? */
@@ -469,7 +469,7 @@
put_le16(p + 22, 4); /* ecc bytes */
padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40); /* model */
-#if MAX_MULT_SECTORS > 1
+#if MAX_MULT_SECTORS > 1
put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
#endif
put_le16(p + 48, 1); /* dword I/O */
@@ -666,7 +666,7 @@
}
/* prepare data transfer and tell what to do after */
-static void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
+static void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
EndTransferFunc *end_transfer_func)
{
s->end_transfer_func = end_transfer_func;
@@ -771,7 +771,7 @@
for(;;) {
l = s->io_buffer_size - s->io_buffer_index;
- if (l <= 0)
+ if (l <= 0)
break;
if (bm->cur_prd_len == 0) {
/* end of table (with a fail safe of one page) */
@@ -793,10 +793,10 @@
l = bm->cur_prd_len;
if (l > 0) {
if (is_write) {
- cpu_physical_memory_write(bm->cur_prd_addr,
+ cpu_physical_memory_write(bm->cur_prd_addr,
s->io_buffer + s->io_buffer_index, l);
} else {
- cpu_physical_memory_read(bm->cur_prd_addr,
+ cpu_physical_memory_read(bm->cur_prd_addr,
s->io_buffer + s->io_buffer_index, l);
}
bm->cur_prd_addr += l;
@@ -847,7 +847,7 @@
#ifdef DEBUG_AIO
printf("aio_read: sector_num=%lld n=%d\n", sector_num, n);
#endif
- bm->aiocb = bdrv_aio_read(s->bs, sector_num, s->io_buffer, n,
+ bm->aiocb = bdrv_aio_read(s->bs, sector_num, s->io_buffer, n,
ide_read_dma_cb, bm);
}
@@ -923,7 +923,7 @@
ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
}
ide_set_sector(s, sector_num + n);
-
+
bm->aiocb = bdrv_aio_write(s->bs, sector_num, s->io_buffer, n,
ide_sector_write_aio_cb, bm);
}
@@ -969,7 +969,7 @@
#ifdef DEBUG_AIO
printf("aio_write: sector_num=%lld n=%d\n", sector_num, n);
#endif
- bm->aiocb = bdrv_aio_write(s->bs, sector_num, s->io_buffer, n,
+ bm->aiocb = bdrv_aio_write(s->bs, sector_num, s->io_buffer, n,
ide_write_dma_cb, bm);
}
@@ -1051,7 +1051,7 @@
memset(buf, 0, 288);
}
-static int cd_read_sector(BlockDriverState *bs, int lba, uint8_t *buf,
+static int cd_read_sector(BlockDriverState *bs, int lba, uint8_t *buf,
int sector_size)
{
int ret;
@@ -1077,10 +1077,10 @@
{
/* XXX: handle more errors */
if (ret == -ENOMEDIUM) {
- ide_atapi_cmd_error(s, SENSE_NOT_READY,
+ ide_atapi_cmd_error(s, SENSE_NOT_READY,
ASC_MEDIUM_NOT_PRESENT);
} else {
- ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
+ ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
ASC_LOGICAL_BLOCK_OOR);
}
}
@@ -1090,7 +1090,7 @@
{
int byte_count_limit, size, ret;
#ifdef DEBUG_IDE_ATAPI
- printf("reply: tx_size=%d elem_tx_size=%d index=%d\n",
+ printf("reply: tx_size=%d elem_tx_size=%d index=%d\n",
s->packet_transfer_size,
s->elementary_transfer_size,
s->io_buffer_index);
@@ -1122,7 +1122,7 @@
size = s->cd_sector_size - s->io_buffer_index;
if (size > s->elementary_transfer_size)
size = s->elementary_transfer_size;
- ide_transfer_start(s, s->io_buffer + s->io_buffer_index,
+ ide_transfer_start(s, s->io_buffer + s->io_buffer_index,
size, ide_atapi_cmd_reply_end);
s->packet_transfer_size -= size;
s->elementary_transfer_size -= size;
@@ -1151,7 +1151,7 @@
if (size > (s->cd_sector_size - s->io_buffer_index))
size = (s->cd_sector_size - s->io_buffer_index);
}
- ide_transfer_start(s, s->io_buffer + s->io_buffer_index,
+ ide_transfer_start(s, s->io_buffer + s->io_buffer_index,
size, ide_atapi_cmd_reply_end);
s->packet_transfer_size -= size;
s->elementary_transfer_size -= size;
@@ -1246,7 +1246,7 @@
bm->aiocb = NULL;
return;
}
-
+
s->io_buffer_index = 0;
if (s->cd_sector_size == 2352) {
n = 1;
@@ -1262,12 +1262,12 @@
#ifdef DEBUG_AIO
printf("aio_read_cd: lba=%u n=%d\n", s->lba, n);
#endif
- bm->aiocb = bdrv_aio_read(s->bs, (int64_t)s->lba << 2,
- s->io_buffer + data_offset, n * 4,
+ bm->aiocb = bdrv_aio_read(s->bs, (int64_t)s->lba << 2,
+ s->io_buffer + data_offset, n * 4,
ide_atapi_cmd_read_dma_cb, bm);
if (!bm->aiocb) {
/* Note: media not present is the most likely case */
- ide_atapi_cmd_error(s, SENSE_NOT_READY,
+ ide_atapi_cmd_error(s, SENSE_NOT_READY,
ASC_MEDIUM_NOT_PRESENT);
goto eot;
}
@@ -1289,7 +1289,7 @@
ide_dma_start(s, ide_atapi_cmd_read_dma_cb);
}
-static void ide_atapi_cmd_read(IDEState *s, int lba, int nb_sectors,
+static void ide_atapi_cmd_read(IDEState *s, int lba, int nb_sectors,
int sector_size)
{
#ifdef DEBUG_IDE_ATAPI
@@ -1326,7 +1326,7 @@
if (bdrv_is_inserted(s->bs)) {
ide_atapi_cmd_ok(s);
} else {
- ide_atapi_cmd_error(s, SENSE_NOT_READY,
+ ide_atapi_cmd_error(s, SENSE_NOT_READY,
ASC_MEDIUM_NOT_PRESENT);
}
break;
@@ -1375,7 +1375,7 @@
buf[9] = 0x12;
buf[10] = 0x08;
buf[11] = 0x00;
-
+
buf[12] = 0x70;
buf[13] = 3 << 5;
buf[14] = (1 << 0) | (1 << 3) | (1 << 5);
@@ -1403,7 +1403,7 @@
goto error_cmd;
default:
case 3: /* saved values */
- ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
+ ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
break;
}
@@ -1423,7 +1423,7 @@
bdrv_set_locked(s->bs, packet[4] & 1);
ide_atapi_cmd_ok(s);
} else {
- ide_atapi_cmd_error(s, SENSE_NOT_READY,
+ ide_atapi_cmd_error(s, SENSE_NOT_READY,
ASC_MEDIUM_NOT_PRESENT);
}
break;
@@ -1469,7 +1469,7 @@
ide_atapi_cmd_read(s, lba, nb_sectors, 2352);
break;
default:
- ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
+ ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
ASC_INV_FIELD_IN_CMD_PACKET);
break;
}
@@ -1483,13 +1483,13 @@
bdrv_get_geometry(s->bs, &total_sectors);
total_sectors >>= 2;
if (total_sectors <= 0) {
- ide_atapi_cmd_error(s, SENSE_NOT_READY,
+ ide_atapi_cmd_error(s, SENSE_NOT_READY,
ASC_MEDIUM_NOT_PRESENT);
break;
}
lba = ube32_to_cpu(packet + 2);
if (lba >= total_sectors) {
- ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
+ ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
ASC_LOGICAL_BLOCK_OOR);
break;
}
@@ -1501,7 +1501,7 @@
int start, eject;
start = packet[4] & 1;
eject = (packet[4] >> 1) & 1;
-
+
if (eject && !start) {
/* eject the disk */
bdrv_eject(s->bs, 1);
@@ -1533,7 +1533,7 @@
bdrv_get_geometry(s->bs, &total_sectors);
total_sectors >>= 2;
if (total_sectors <= 0) {
- ide_atapi_cmd_error(s, SENSE_NOT_READY,
+ ide_atapi_cmd_error(s, SENSE_NOT_READY,
ASC_MEDIUM_NOT_PRESENT);
break;
}
@@ -1564,7 +1564,7 @@
break;
default:
error_cmd:
- ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
+ ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
ASC_INV_FIELD_IN_CMD_PACKET);
break;
}
@@ -1577,7 +1577,7 @@
bdrv_get_geometry(s->bs, &total_sectors);
total_sectors >>= 2;
if (total_sectors <= 0) {
- ide_atapi_cmd_error(s, SENSE_NOT_READY,
+ ide_atapi_cmd_error(s, SENSE_NOT_READY,
ASC_MEDIUM_NOT_PRESENT);
break;
}
@@ -1670,7 +1670,7 @@
break;
}
default:
- ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
+ ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
ASC_ILLEGAL_OPCODE);
break;
}
@@ -1838,7 +1838,7 @@
#endif
s = ide_if->cur_drive;
/* ignore commands to non existant slave */
- if (s != ide_if && !s->bs)
+ if (s != ide_if && !s->bs)
break;
switch(val) {
@@ -1892,7 +1892,7 @@
lba48 = 1;
case WIN_READ:
case WIN_READ_ONCE:
- if (!s->bs)
+ if (!s->bs)
goto abort_cmd;
ide_cmd_lba48_transform(s, lba48);
s->req_nb_sectors = 1;
@@ -1940,7 +1940,7 @@
lba48 = 1;
case WIN_READDMA:
case WIN_READDMA_ONCE:
- if (!s->bs)
+ if (!s->bs)
goto abort_cmd;
ide_cmd_lba48_transform(s, lba48);
ide_sector_read_dma(s);
@@ -1949,7 +1949,7 @@
lba48 = 1;
case WIN_WRITEDMA:
case WIN_WRITEDMA_ONCE:
- if (!s->bs)
+ if (!s->bs)
goto abort_cmd;
ide_cmd_lba48_transform(s, lba48);
ide_sector_write_dma(s);
@@ -2071,7 +2071,7 @@
s->status = READY_STAT;
s->atapi_dma = s->feature & 1;
s->nsector = 1;
- ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
+ ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
ide_atapi_cmd);
break;
/* CF-ATA commands */
@@ -2330,7 +2330,7 @@
IDEState *s = ((IDEState *)opaque)->cur_drive;
uint8_t *p;
int ret;
-
+
p = s->data_ptr;
ret = cpu_to_le32(*(uint32_t *)p);
p += 4;
@@ -2381,7 +2381,7 @@
} __attribute__((packed));
/* try to guess the disk logical geometry from the MSDOS partition table. Return 0 if OK, -1 if could not guess */
-static int guess_disk_lchs(IDEState *s,
+static int guess_disk_lchs(IDEState *s,
int *pcylinders, int *pheads, int *psectors)
{
uint8_t buf[512];
@@ -2412,7 +2412,7 @@
*psectors = sectors;
*pcylinders = cylinders;
#if 0
- printf("guessed geometry: LCHS=%d %d %d\n",
+ printf("guessed geometry: LCHS=%d %d %d\n",
cylinders, heads, sectors);
#endif
return 0;
@@ -2495,7 +2495,7 @@
}
s->drive_serial = drive_serial++;
s->irq = irq;
- s->sector_write_timer = qemu_new_timer(vm_clock,
+ s->sector_write_timer = qemu_new_timer(vm_clock,
ide_sector_write_timer_cb, s);
ide_reset(s);
}
@@ -2509,7 +2509,7 @@
register_ioport_read(iobase2, 1, 1, ide_status_read, ide_state);
register_ioport_write(iobase2, 1, 1, ide_cmd_write, ide_state);
}
-
+
/* data ports */
register_ioport_write(iobase, 2, 2, ide_data_writew, ide_state);
register_ioport_read(iobase, 2, 2, ide_data_readw, ide_state);
@@ -2584,7 +2584,7 @@
ide_state = qemu_mallocz(sizeof(IDEState) * 2);
if (!ide_state)
return;
-
+
ide_init2(ide_state, hd0, hd1, irq);
ide_init_ioport(ide_state, iobase, iobase2);
}
@@ -2594,7 +2594,7 @@
static void cmd646_update_irq(PCIIDEState *d);
-static void ide_map(PCIDevice *pci_dev, int region_num,
+static void ide_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
PCIIDEState *d = (PCIIDEState *)pci_dev;
@@ -2671,9 +2671,9 @@
BMDMAState *bm = opaque;
PCIIDEState *pci_dev;
uint32_t val;
-
+
switch(addr & 3) {
- case 0:
+ case 0:
val = bm->cmd;
break;
case 1:
@@ -2719,7 +2719,7 @@
case 1:
pci_dev = bm->pci_dev;
if (pci_dev->type == IDE_TYPE_CMD646) {
- pci_dev->dev.config[MRDMODE] =
+ pci_dev->dev.config[MRDMODE] =
(pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
cmd646_update_irq(pci_dev);
}
@@ -2760,7 +2760,7 @@
bm->cur_addr = bm->addr;
}
-static void bmdma_map(PCIDevice *pci_dev, int region_num,
+static void bmdma_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
PCIIDEState *d = (PCIIDEState *)pci_dev;
@@ -2818,9 +2818,9 @@
int i;
qemu_irq *irq;
- d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
+ d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
sizeof(PCIIDEState),
- -1,
+ -1,
NULL, NULL);
d->type = IDE_TYPE_CMD646;
pci_conf = d->dev.config;
@@ -2830,30 +2830,30 @@
pci_conf[0x03] = 0x06;
pci_conf[0x08] = 0x07; // IDE controller revision
- pci_conf[0x09] = 0x8f;
+ pci_conf[0x09] = 0x8f;
pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
pci_conf[0x0e] = 0x00; // header_type
-
+
if (secondary_ide_enabled) {
/* XXX: if not enabled, really disable the seconday IDE controller */
pci_conf[0x51] = 0x80; /* enable IDE1 */
}
- pci_register_io_region((PCIDevice *)d, 0, 0x8,
+ pci_register_io_region((PCIDevice *)d, 0, 0x8,
PCI_ADDRESS_SPACE_IO, ide_map);
- pci_register_io_region((PCIDevice *)d, 1, 0x4,
+ pci_register_io_region((PCIDevice *)d, 1, 0x4,
PCI_ADDRESS_SPACE_IO, ide_map);
- pci_register_io_region((PCIDevice *)d, 2, 0x8,
+ pci_register_io_region((PCIDevice *)d, 2, 0x8,
PCI_ADDRESS_SPACE_IO, ide_map);
- pci_register_io_region((PCIDevice *)d, 3, 0x4,
+ pci_register_io_region((PCIDevice *)d, 3, 0x4,
PCI_ADDRESS_SPACE_IO, ide_map);
- pci_register_io_region((PCIDevice *)d, 4, 0x10,
+ pci_register_io_region((PCIDevice *)d, 4, 0x10,
PCI_ADDRESS_SPACE_IO, bmdma_map);
pci_conf[0x3d] = 0x01; // interrupt on pin 1
-
+
for(i = 0; i < 4; i++)
d->ide_if[i].pci_dev = (PCIDevice *)d;
@@ -2945,9 +2945,9 @@
{
PCIIDEState *d;
uint8_t *pci_conf;
-
+
/* register a function 1 of PIIX3 */
- d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
+ d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
sizeof(PCIIDEState),
devfn,
NULL, NULL);
@@ -2965,7 +2965,7 @@
piix3_reset(d);
- pci_register_io_region((PCIDevice *)d, 4, 0x10,
+ pci_register_io_region((PCIDevice *)d, 4, 0x10,
PCI_ADDRESS_SPACE_IO, bmdma_map);
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);
@@ -3021,7 +3021,7 @@
static void pmac_ide_writeb (void *opaque,
target_phys_addr_t addr, uint32_t val)
{
- addr = (addr & 0xFFF) >> 4;
+ addr = (addr & 0xFFF) >> 4;
switch (addr) {
case 1 ... 7:
ide_ioport_write(opaque, addr, val);
@@ -3058,7 +3058,7 @@
static void pmac_ide_writew (void *opaque,
target_phys_addr_t addr, uint32_t val)
{
- addr = (addr & 0xFFF) >> 4;
+ addr = (addr & 0xFFF) >> 4;
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap16(val);
#endif
@@ -3071,7 +3071,7 @@
{
uint16_t retval;
- addr = (addr & 0xFFF) >> 4;
+ addr = (addr & 0xFFF) >> 4;
if (addr == 0) {
retval = ide_data_readw(opaque, 0);
} else {
@@ -3086,7 +3086,7 @@
static void pmac_ide_writel (void *opaque,
target_phys_addr_t addr, uint32_t val)
{
- addr = (addr & 0xFFF) >> 4;
+ addr = (addr & 0xFFF) >> 4;
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
@@ -3099,7 +3099,7 @@
{
uint32_t retval;
- addr = (addr & 0xFFF) >> 4;
+ addr = (addr & 0xFFF) >> 4;
if (addr == 0) {
retval = ide_data_readl(opaque, 0);
} else {
@@ -3133,7 +3133,7 @@
ide_if = qemu_mallocz(sizeof(IDEState) * 2);
ide_init2(&ide_if[0], hd_table[0], hd_table[1], irq);
-
+
pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
pmac_ide_write, &ide_if[0]);
return pmac_ide_memory;
diff --git a/hw/integratorcp.c b/hw/integratorcp.c
index 93d980a..83c6208 100644
--- a/hw/integratorcp.c
+++ b/hw/integratorcp.c
@@ -1,4 +1,4 @@
-/*
+/*
* ARM Integrator CP System emulation.
*
* Copyright (c) 2005-2007 CodeSourcery.
diff --git a/hw/iommu.c b/hw/iommu.c
index f87c79c..bd52454 100644
--- a/hw/iommu.c
+++ b/hw/iommu.c
@@ -2,7 +2,7 @@
* QEMU SPARC iommu emulation
*
* Copyright (c) 2003-2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -279,7 +279,7 @@
{
IOMMUState *s = opaque;
int i;
-
+
for (i = 0; i < IOMMU_NREGS; i++)
qemu_put_be32s(f, &s->regs[i]);
qemu_put_be64s(f, &s->iostart);
@@ -289,7 +289,7 @@
{
IOMMUState *s = opaque;
int i;
-
+
if (version_id != 2)
return -EINVAL;
@@ -322,7 +322,7 @@
iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
-
+
register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
qemu_register_reset(iommu_reset, s);
return s;
diff --git a/hw/irq.c b/hw/irq.c
index 4bc8d80..e46ee60 100644
--- a/hw/irq.c
+++ b/hw/irq.c
@@ -1,8 +1,8 @@
/*
* QEMU IRQ/GPIO common code.
- *
+ *
* Copyright (c) 2007 CodeSourcery.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c
index 070f6f5..4e7914e 100644
--- a/hw/isa_mmio.c
+++ b/hw/isa_mmio.c
@@ -2,7 +2,7 @@
* Memory mapped access to ISA IO space.
*
* Copyright (c) 2006 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
diff --git a/hw/jazz_led.c b/hw/jazz_led.c
index 6f74173..1c7c176 100644
--- a/hw/jazz_led.c
+++ b/hw/jazz_led.c
@@ -1,8 +1,8 @@
/*
* QEMU JAZZ LED emulator.
- *
+ *
* Copyright (c) 2007 Hervé Poussineau
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c
index 19bf2a1..e9866ba 100644
--- a/hw/lsi53c895a.c
+++ b/hw/lsi53c895a.c
@@ -1,4 +1,4 @@
-/*
+/*
* QEMU LSI53C895A SCSI Host Bus Adapter emulation
*
* Copyright (c) 2006 CodeSourcery.
@@ -1773,7 +1773,7 @@
lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
}
-static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
+static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
LSIState *s = (LSIState *)pci_dev;
@@ -1788,7 +1788,7 @@
register_ioport_read(addr, 256, 4, lsi_io_readl, s);
}
-static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
+static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
LSIState *s = (LSIState *)pci_dev;
@@ -1798,7 +1798,7 @@
cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr);
}
-static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
+static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
LSIState *s = (LSIState *)pci_dev;
diff --git a/hw/m48t59.c b/hw/m48t59.c
index 053acb5..e097a7c 100644
--- a/hw/m48t59.c
+++ b/hw/m48t59.c
@@ -1,8 +1,8 @@
/*
* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
- *
+ *
* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -90,7 +90,7 @@
static void set_time (m48t59_t *NVRAM, struct tm *tm)
{
time_t now, new_time;
-
+
new_time = mktime(tm);
now = time(NULL);
NVRAM->time_offset = new_time - now;
@@ -104,7 +104,7 @@
m48t59_t *NVRAM = opaque;
qemu_set_irq(NVRAM->IRQ, 1);
- if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
+ if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
@@ -208,7 +208,7 @@
if (addr > 0x1FF8 && addr < 0x2000)
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
- if (NVRAM->type == 8 &&
+ if (NVRAM->type == 8 &&
(addr >= 0x1ff0 && addr <= 0x1ff7))
goto do_write;
switch (addr) {
@@ -364,7 +364,7 @@
struct tm tm;
uint32_t retval = 0xFF;
- if (NVRAM->type == 8 &&
+ if (NVRAM->type == 8 &&
(addr >= 0x1ff0 && addr <= 0x1ff7))
goto do_read;
switch (addr) {
@@ -430,7 +430,7 @@
case 0x1FFF:
/* year */
get_time(NVRAM, &tm);
- if (NVRAM->type == 8)
+ if (NVRAM->type == 8)
retval = toBCD(tm.tm_year - 68); // Base year is 1968
else
retval = toBCD(tm.tm_year);
@@ -510,7 +510,7 @@
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
m48t59_t *NVRAM = opaque;
-
+
addr -= NVRAM->mem_base;
m48t59_write(NVRAM, addr, value & 0xff);
}
@@ -518,7 +518,7 @@
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
m48t59_t *NVRAM = opaque;
-
+
addr -= NVRAM->mem_base;
m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
m48t59_write(NVRAM, addr + 1, value & 0xff);
@@ -527,7 +527,7 @@
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
m48t59_t *NVRAM = opaque;
-
+
addr -= NVRAM->mem_base;
m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
@@ -539,7 +539,7 @@
{
m48t59_t *NVRAM = opaque;
uint32_t retval;
-
+
addr -= NVRAM->mem_base;
retval = m48t59_read(NVRAM, addr);
return retval;
@@ -549,7 +549,7 @@
{
m48t59_t *NVRAM = opaque;
uint32_t retval;
-
+
addr -= NVRAM->mem_base;
retval = m48t59_read(NVRAM, addr) << 8;
retval |= m48t59_read(NVRAM, addr + 1);
diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c
index e30791f..8d0da95 100644
--- a/hw/mc146818rtc.c
+++ b/hw/mc146818rtc.c
@@ -1,8 +1,8 @@
/*
* QEMU MC146818 RTC emulation
- *
+ *
* Copyright (c) 2003-2004 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -75,7 +75,7 @@
int64_t cur_clock, next_irq_clock;
period_code = s->cmos_data[RTC_REG_A] & 0x0f;
- if (period_code != 0 &&
+ if (period_code != 0 &&
(s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
if (period_code <= 2)
period_code += 7;
@@ -110,7 +110,7 @@
#ifdef DEBUG_CMOS
printf("cmos: write index=0x%02x val=0x%02x\n",
s->cmos_index, data);
-#endif
+#endif
switch(s->cmos_index) {
case RTC_SECONDS_ALARM:
case RTC_MINUTES_ALARM:
@@ -221,8 +221,8 @@
/* month is between 0 and 11. */
static int get_days_in_month(int month, int year)
{
- static const int days_tab[12] = {
- 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
+ static const int days_tab[12] = {
+ 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
};
int d;
if ((unsigned )month >= 12)
@@ -253,7 +253,7 @@
tm->tm_wday++;
if ((unsigned)tm->tm_wday >= 7)
tm->tm_wday = 0;
- days_in_month = get_days_in_month(tm->tm_mon,
+ days_in_month = get_days_in_month(tm->tm_mon,
tm->tm_year + 1900);
tm->tm_mday++;
if (tm->tm_mday < 1) {
@@ -283,7 +283,7 @@
qemu_mod_timer(s->second_timer, s->next_second_time);
} else {
rtc_next_second(&s->current_tm);
-
+
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
/* update in progress bit */
s->cmos_data[RTC_REG_A] |= REG_A_UIP;
@@ -293,7 +293,7 @@
delay = (ticks_per_sec * 1) / 100;
if (delay < 1)
delay = 1;
- qemu_mod_timer(s->second_timer2,
+ qemu_mod_timer(s->second_timer2,
s->next_second_time + delay);
}
}
@@ -315,14 +315,14 @@
((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
- s->cmos_data[RTC_REG_C] |= 0xa0;
+ s->cmos_data[RTC_REG_C] |= 0xa0;
qemu_irq_raise(s->irq);
}
}
/* update ended interrupt */
if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
- s->cmos_data[RTC_REG_C] |= 0x90;
+ s->cmos_data[RTC_REG_C] |= 0x90;
qemu_irq_raise(s->irq);
}
@@ -356,7 +356,7 @@
case RTC_REG_C:
ret = s->cmos_data[s->cmos_index];
qemu_irq_lower(s->irq);
- s->cmos_data[RTC_REG_C] = 0x00;
+ s->cmos_data[RTC_REG_C] = 0x00;
break;
default:
ret = s->cmos_data[s->cmos_index];
@@ -411,7 +411,7 @@
qemu_put_buffer(f, s->cmos_data, 128);
qemu_put_8s(f, &s->cmos_index);
-
+
qemu_put_be32s(f, &s->current_tm.tm_sec);
qemu_put_be32s(f, &s->current_tm.tm_min);
qemu_put_be32s(f, &s->current_tm.tm_hour);
@@ -471,11 +471,11 @@
rtc_set_date_from_host(s);
- s->periodic_timer = qemu_new_timer(vm_clock,
+ s->periodic_timer = qemu_new_timer(vm_clock,
rtc_periodic_timer, s);
- s->second_timer = qemu_new_timer(vm_clock,
+ s->second_timer = qemu_new_timer(vm_clock,
rtc_update_second, s);
- s->second_timer2 = qemu_new_timer(vm_clock,
+ s->second_timer2 = qemu_new_timer(vm_clock,
rtc_update_second2, s);
s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
diff --git a/hw/mcf5206.c b/hw/mcf5206.c
index ce4676b..32117ae 100644
--- a/hw/mcf5206.c
+++ b/hw/mcf5206.c
@@ -1,4 +1,4 @@
-/*
+/*
* Motorola ColdFire MCF5206 SoC embedded peripheral emulation.
*
* Copyright (c) 2007 CodeSourcery.
@@ -58,7 +58,7 @@
prescale *= 16;
if (mode == 3 || mode == 0)
- cpu_abort(cpu_single_env,
+ cpu_abort(cpu_single_env,
"m5206_timer: mode %d not implemented\n", mode);
if ((s->tmr & TMR_FRR) == 0)
cpu_abort(cpu_single_env,
@@ -354,7 +354,7 @@
/* Internal peripherals use a variety of register widths.
This lookup table allows a single routine to handle all of them. */
-static const int m5206_mbar_width[] =
+static const int m5206_mbar_width[] =
{
/* 000-040 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
/* 040-080 */ 1, 2, 2, 2, 4, 1, 2, 4, 1, 2, 4, 2, 2, 4, 2, 2,
diff --git a/hw/mcf5208.c b/hw/mcf5208.c
index 8068f78..993a686 100644
--- a/hw/mcf5208.c
+++ b/hw/mcf5208.c
@@ -1,4 +1,4 @@
-/*
+/*
* Motorola ColdFire MCF5208 SoC emulation.
*
* Copyright (c) 2007 CodeSourcery.
diff --git a/hw/mcf_fec.c b/hw/mcf_fec.c
index d4613dd..a218108 100644
--- a/hw/mcf_fec.c
+++ b/hw/mcf_fec.c
@@ -1,4 +1,4 @@
-/*
+/*
* ColdFire Fast Ethernet Controller emulation.
*
* Copyright (c) 2007 CodeSourcery.
diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c
index 5bdebf8..e469c31 100644
--- a/hw/mcf_intc.c
+++ b/hw/mcf_intc.c
@@ -1,4 +1,4 @@
-/*
+/*
* ColdFire Interrupt Controller emulation.
*
* Copyright (c) 2007 CodeSourcery.
diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c
index fcdfc44..ab0f54f 100644
--- a/hw/mcf_uart.c
+++ b/hw/mcf_uart.c
@@ -1,4 +1,4 @@
-/*
+/*
* ColdFire UART emulation.
*
* Copyright (c) 2007 CodeSourcery.
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index ed23052..ab4d3fd 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -510,9 +510,9 @@
stl_raw(p++, 0x00000000); /* nop */
/* YAMON service vector */
- stl_raw(phys_ram_base + bios_offset + 0x500, 0xbfc00580); /* start: */
+ stl_raw(phys_ram_base + bios_offset + 0x500, 0xbfc00580); /* start: */
stl_raw(phys_ram_base + bios_offset + 0x504, 0xbfc0083c); /* print_count: */
- stl_raw(phys_ram_base + bios_offset + 0x520, 0xbfc00580); /* start: */
+ stl_raw(phys_ram_base + bios_offset + 0x520, 0xbfc00580); /* start: */
stl_raw(phys_ram_base + bios_offset + 0x52c, 0xbfc00800); /* flush_cache: */
stl_raw(phys_ram_base + bios_offset + 0x534, 0xbfc00808); /* print: */
stl_raw(phys_ram_base + bios_offset + 0x538, 0xbfc00800); /* reg_cpu_isr: */
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index 8278227..5769ade 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -221,7 +221,7 @@
}
}
- isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
+ isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
vga_ram_size);
if (nd_table[0].vlan) {
diff --git a/hw/nand.c b/hw/nand.c
index 8e39acd..118d04e 100644
--- a/hw/nand.c
+++ b/hw/nand.c
@@ -323,7 +323,7 @@
*
* CE, WP and R/B are active low.
*/
-void nand_setpins(struct nand_flash_s *s,
+void nand_setpins(struct nand_flash_s *s,
int cle, int ale, int ce, int wp, int gnd)
{
s->cle = cle;
@@ -416,7 +416,7 @@
uint8_t nand_getio(struct nand_flash_s *s)
{
int offset;
-
+
/* Allow sequential reading */
if (!s->iolen && s->cmd == NAND_CMD_READ0) {
offset = (s->addr & ((1 << s->addr_shift) - 1)) + s->offset;
diff --git a/hw/ne2000.c b/hw/ne2000.c
index 6d5aa56..a5e0331 100644
--- a/hw/ne2000.c
+++ b/hw/ne2000.c
@@ -1,8 +1,8 @@
/*
* QEMU NE2000 emulation
- *
+ *
* Copyright (c) 2003-2004 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -212,7 +212,7 @@
static int ne2000_can_receive(void *opaque)
{
NE2000State *s = opaque;
-
+
if (s->cmd & E8390_STOP)
return 1;
return !ne2000_buffer_full(s);
@@ -226,16 +226,16 @@
uint8_t *p;
unsigned int total_len, next, avail, len, index, mcast_idx;
uint8_t buf1[60];
- static const uint8_t broadcast_macaddr[6] =
+ static const uint8_t broadcast_macaddr[6] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
-
+
#if defined(DEBUG_NE2000)
printf("NE2000: received len=%d\n", size);
#endif
if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
return;
-
+
/* XXX: check this */
if (s->rxcr & 0x10) {
/* promiscuous: receive all */
@@ -252,10 +252,10 @@
if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
return;
} else if (s->mem[0] == buf[0] &&
- s->mem[2] == buf[1] &&
- s->mem[4] == buf[2] &&
- s->mem[6] == buf[3] &&
- s->mem[8] == buf[4] &&
+ s->mem[2] == buf[1] &&
+ s->mem[4] == buf[2] &&
+ s->mem[6] == buf[3] &&
+ s->mem[8] == buf[4] &&
s->mem[10] == buf[5]) {
/* match */
} else {
@@ -336,7 +336,7 @@
}
if (val & E8390_TRANS) {
index = (s->tpsr << 8);
- /* XXX: next 2 lines are a hack to make netware 3.11 work */
+ /* XXX: next 2 lines are a hack to make netware 3.11 work */
if (index >= NE2000_PMEM_END)
index -= NE2000_PMEM_SIZE;
/* fail safe: check range on the transmitted length */
@@ -346,7 +346,7 @@
/* signal end of transfer */
s->tsr = ENTSR_PTX;
s->isr |= ENISR_TX;
- s->cmd &= ~E8390_TRANS;
+ s->cmd &= ~E8390_TRANS;
ne2000_update_irq(s);
}
}
@@ -482,30 +482,30 @@
return ret;
}
-static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
+static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
uint32_t val)
{
- if (addr < 32 ||
+ if (addr < 32 ||
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
s->mem[addr] = val;
}
}
-static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
+static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
uint32_t val)
{
addr &= ~1; /* XXX: check exact behaviour if not even */
- if (addr < 32 ||
+ if (addr < 32 ||
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
*(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
}
}
-static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
+static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
uint32_t val)
{
addr &= ~1; /* XXX: check exact behaviour if not even */
- if (addr < 32 ||
+ if (addr < 32 ||
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
}
@@ -513,7 +513,7 @@
static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
{
- if (addr < 32 ||
+ if (addr < 32 ||
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
return s->mem[addr];
} else {
@@ -524,7 +524,7 @@
static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
{
addr &= ~1; /* XXX: check exact behaviour if not even */
- if (addr < 32 ||
+ if (addr < 32 ||
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
return le16_to_cpu(*(uint16_t *)(s->mem + addr));
} else {
@@ -535,7 +535,7 @@
static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
{
addr &= ~1; /* XXX: check exact behaviour if not even */
- if (addr < 32 ||
+ if (addr < 32 ||
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
return le32_to_cpupu((uint32_t *)(s->mem + addr));
} else {
@@ -718,11 +718,11 @@
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd)
{
NE2000State *s;
-
+
s = qemu_mallocz(sizeof(NE2000State));
if (!s)
return;
-
+
register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
@@ -749,7 +749,7 @@
s->macaddr[3],
s->macaddr[4],
s->macaddr[5]);
-
+
register_savevm("ne2000", 0, 2, ne2000_save, ne2000_load, s);
}
@@ -761,7 +761,7 @@
NE2000State ne2000;
} PCINE2000State;
-static void ne2000_map(PCIDevice *pci_dev, int region_num,
+static void ne2000_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
PCINE2000State *d = (PCINE2000State *)pci_dev;
@@ -786,22 +786,22 @@
PCINE2000State *d;
NE2000State *s;
uint8_t *pci_conf;
-
+
d = (PCINE2000State *)pci_register_device(bus,
"NE2000", sizeof(PCINE2000State),
- devfn,
+ devfn,
NULL, NULL);
pci_conf = d->dev.config;
pci_conf[0x00] = 0xec; // Realtek 8029
pci_conf[0x01] = 0x10;
pci_conf[0x02] = 0x29;
pci_conf[0x03] = 0x80;
- pci_conf[0x0a] = 0x00; // ethernet network controller
+ pci_conf[0x0a] = 0x00; // ethernet network controller
pci_conf[0x0b] = 0x02;
pci_conf[0x0e] = 0x00; // header_type
pci_conf[0x3d] = 1; // interrupt pin 0
-
- pci_register_io_region(&d->dev, 0, 0x100,
+
+ pci_register_io_region(&d->dev, 0, 0x100,
PCI_ADDRESS_SPACE_IO, ne2000_map);
s = &d->ne2000;
s->irq = d->dev.irq[0];
@@ -819,7 +819,7 @@
s->macaddr[3],
s->macaddr[4],
s->macaddr[5]);
-
+
/* XXX: instance number ? */
register_savevm("ne2000", 0, 3, ne2000_save, ne2000_load, s);
}
diff --git a/hw/omap.h b/hw/omap.h
index 16e764b..96cd3af 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -483,7 +483,7 @@
qemu_irq wakeup;
struct omap_dma_port_if_s {
- uint32_t (*read[3])(struct omap_mpu_state_s *s,
+ uint32_t (*read[3])(struct omap_mpu_state_s *s,
target_phys_addr_t offset);
void (*write[3])(struct omap_mpu_state_s *s,
target_phys_addr_t offset, uint32_t value);
diff --git a/hw/omap_lcd_template.h b/hw/omap_lcd_template.h
index cdfa562..4e84fa1 100644
--- a/hw/omap_lcd_template.h
+++ b/hw/omap_lcd_template.h
@@ -29,18 +29,18 @@
#if DEPTH == 8
# define BPP 1
-# define PIXEL_TYPE uint8_t
+# define PIXEL_TYPE uint8_t
#elif DEPTH == 15 || DEPTH == 16
# define BPP 2
-# define PIXEL_TYPE uint16_t
+# define PIXEL_TYPE uint16_t
#elif DEPTH == 32
# define BPP 4
-# define PIXEL_TYPE uint32_t
+# define PIXEL_TYPE uint32_t
#else
# error unsupport depth
#endif
-/*
+/*
* 2-bit colour
*/
static void glue(draw_line2_, DEPTH)(
@@ -78,7 +78,7 @@
} while (width > 0);
}
-/*
+/*
* 4-bit colour
*/
static void glue(draw_line4_, DEPTH)(
@@ -104,7 +104,7 @@
} while (width > 0);
}
-/*
+/*
* 8-bit colour
*/
static void glue(draw_line8_, DEPTH)(
@@ -123,7 +123,7 @@
} while (-- width != 0);
}
-/*
+/*
* 12-bit colour
*/
static void glue(draw_line12_, DEPTH)(
@@ -143,7 +143,7 @@
} while (-- width != 0);
}
-/*
+/*
* 16-bit colour
*/
static void glue(draw_line16_, DEPTH)(
diff --git a/hw/openpic.c b/hw/openpic.c
index d52eb75..bd52828 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -1,8 +1,8 @@
/*
* OpenPIC emulation
- *
+ *
* Copyright (c) 2004 Jocelyn Mayer
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -30,7 +30,7 @@
* - Motorola Harrier programmer manuel
*
* Serial interrupts, as implemented in Raven chipset are not supported yet.
- *
+ *
*/
#include "vl.h"
@@ -224,7 +224,7 @@
priority = -1;
for (i = 0; i < MAX_IRQ; i++) {
if (IRQ_testbit(q, i)) {
- DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
+ DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
i, IPVP_PRIORITY(opp->src[i].ipvp), priority);
if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
next = i;
@@ -350,7 +350,7 @@
IRQ_src_t *src;
src = &opp->src[n_IRQ];
- DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
+ DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
n_IRQ, level, src->ipvp);
if (test_bit(&src->ipvp, IPVP_SENSE)) {
/* level-sensitive irq */
@@ -438,11 +438,11 @@
/* NOTE: not fully accurate for special IRQs, but simple and
sufficient */
/* ACTIVITY bit is read-only */
- opp->src[n_IRQ].ipvp =
+ opp->src[n_IRQ].ipvp =
(opp->src[n_IRQ].ipvp & 0x40000000) |
(val & 0x800F00FF);
openpic_update_irq(opp, n_IRQ);
- DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
+ DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
n_IRQ, val, opp->src[n_IRQ].ipvp);
break;
case IRQ_IDE:
@@ -475,7 +475,7 @@
return retval;
}
-
+
static void write_doorbell_register (penpic_t *opp, int n_dbl,
uint32_t offset, uint32_t value)
{
@@ -831,7 +831,7 @@
IRQ_dst_t *dst;
uint32_t retval;
int idx, n_IRQ;
-
+
DPRINTF("%s: addr %08x\n", __func__, addr);
retval = 0xFFFFFFFF;
if (addr & 0xF)
@@ -971,7 +971,7 @@
&openpic_readl,
};
-static void openpic_map(PCIDevice *pci_dev, int region_num,
+static void openpic_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
openpic_t *opp;
@@ -1005,7 +1005,7 @@
openpic_t *opp;
uint8_t *pci_conf;
int i, m;
-
+
/* XXX: for now, only one CPU is supported */
if (nb_cpus != 1)
return NULL;
@@ -1023,7 +1023,7 @@
pci_conf[0x0b] = 0x08;
pci_conf[0x0e] = 0x00; // header_type
pci_conf[0x3d] = 0x00; // no interrupt pin
-
+
/* Register I/O spaces */
pci_register_io_region((PCIDevice *)opp, 0, 0x40000,
PCI_ADDRESS_SPACE_MEM, &openpic_map);
@@ -1032,7 +1032,7 @@
}
opp->mem_index = cpu_register_io_memory(0, openpic_read,
openpic_write, opp);
-
+
// isu_base &= 0xFFFC0000;
opp->nb_cpus = nb_cpus;
/* Set IRQ types */
diff --git a/hw/parallel.c b/hw/parallel.c
index f05daf3..9558c3f 100644
--- a/hw/parallel.c
+++ b/hw/parallel.c
@@ -1,9 +1,9 @@
/*
* QEMU Parallel PORT emulation
- *
+ *
* Copyright (c) 2003-2005 Fabrice Bellard
* Copyright (c) 2007 Marko Kohtala
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -88,7 +88,7 @@
parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
{
ParallelState *s = opaque;
-
+
pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
addr &= 7;
diff --git a/hw/pc.c b/hw/pc.c
index 7d86f32..a4ce37e 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1,8 +1,8 @@
/*
* QEMU PC System Emulator
- *
+ *
* Copyright (c) 2003-2004 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -65,7 +65,7 @@
#if USE_KQEMU
if (env->kqemu_enabled) {
return cpu_get_real_ticks();
- } else
+ } else
#endif
{
return cpu_get_ticks();
@@ -89,7 +89,7 @@
if (intno >= 0) {
/* set irq request if a PIC irq is still pending */
/* XXX: improve that */
- pic_update_irq(isa_pic);
+ pic_update_irq(isa_pic);
return intno;
}
/* read the irq from the PIC */
@@ -134,7 +134,7 @@
return val;
}
-static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
+static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
{
RTCState *s = rtc_state;
int cylinders, heads, sectors;
@@ -182,7 +182,7 @@
val = 65535;
rtc_set_memory(s, 0x34, val);
rtc_set_memory(s, 0x35, val >> 8);
-
+
switch(boot_device) {
case 'a':
case 'b':
@@ -199,7 +199,7 @@
break;
case 'n':
rtc_set_memory(s, 0x3d, 0x04); /* Network boot */
- break;
+ break;
}
/* floppy type */
@@ -209,7 +209,7 @@
val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
rtc_set_memory(s, 0x10, val);
-
+
val = 0;
nb = 0;
if (fd0 < 3)
@@ -235,7 +235,7 @@
rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
if (hd_table[0])
cmos_init_hd(0x19, 0x1b, hd_table[0]);
- if (hd_table[1])
+ if (hd_table[1])
cmos_init_hd(0x1a, 0x24, hd_table[1]);
val = 0;
@@ -294,7 +294,7 @@
{
static const char shutdown_str[8] = "Shutdown";
static int shutdown_index = 0;
-
+
switch(addr) {
/* Bochs BIOS messages */
case 0x400:
@@ -404,7 +404,7 @@
bdrv_set_boot_sector(bs_table[0], bootsect, sizeof(bootsect));
}
-int load_kernel(const char *filename, uint8_t *addr,
+int load_kernel(const char *filename, uint8_t *addr,
uint8_t *real_addr)
{
int fd, size;
@@ -420,7 +420,7 @@
setup_sects = real_addr[0x1F1];
if (!setup_sects)
setup_sects = 4;
- if (read(fd, real_addr + 512, setup_sects * 512) !=
+ if (read(fd, real_addr + 512, setup_sects * 512) !=
setup_sects * 512)
goto fail;
@@ -708,7 +708,7 @@
/* BIOS load */
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
bios_size = get_image_size(buf);
- if (bios_size <= 0 ||
+ if (bios_size <= 0 ||
(bios_size % 65536) != 0) {
goto bios_error;
}
@@ -727,7 +727,7 @@
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
}
vga_bios_size = get_image_size(buf);
- if (vga_bios_size <= 0 || vga_bios_size > 65536)
+ if (vga_bios_size <= 0 || vga_bios_size > 65536)
goto vga_bios_error;
vga_bios_offset = qemu_ram_alloc(65536);
@@ -739,17 +739,17 @@
}
/* setup basic memory access */
- cpu_register_physical_memory(0xc0000, 0x10000,
+ cpu_register_physical_memory(0xc0000, 0x10000,
vga_bios_offset | IO_MEM_ROM);
/* map the last 128KB of the BIOS in ISA space */
isa_bios_size = bios_size;
if (isa_bios_size > (128 * 1024))
isa_bios_size = 128 * 1024;
- cpu_register_physical_memory(0xd0000, (192 * 1024) - isa_bios_size,
+ cpu_register_physical_memory(0xd0000, (192 * 1024) - isa_bios_size,
IO_MEM_UNASSIGNED);
- cpu_register_physical_memory(0x100000 - isa_bios_size,
- isa_bios_size,
+ cpu_register_physical_memory(0x100000 - isa_bios_size,
+ isa_bios_size,
(bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
{
@@ -760,7 +760,7 @@
for (i = 0; i < nb_option_roms; i++) {
size = get_image_size(option_rom[i]);
if (size < 0) {
- fprintf(stderr, "Could not load option rom '%s'\n",
+ fprintf(stderr, "Could not load option rom '%s'\n",
option_rom[i]);
exit(1);
}
@@ -781,9 +781,9 @@
}
/* map all the bios at the top of memory */
- cpu_register_physical_memory((uint32_t)(-bios_size),
+ cpu_register_physical_memory((uint32_t)(-bios_size),
bios_size, bios_offset | IO_MEM_ROM);
-
+
bochs_bios_init();
if (linux_boot)
@@ -807,11 +807,11 @@
if (cirrus_vga_enabled) {
if (pci_enabled) {
- pci_cirrus_vga_init(pci_bus,
- ds, phys_ram_base + vga_ram_addr,
+ pci_cirrus_vga_init(pci_bus,
+ ds, phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
} else {
- isa_cirrus_vga_init(ds, phys_ram_base + vga_ram_addr,
+ isa_cirrus_vga_init(ds, phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
}
} else if (vmsvga_enabled) {
@@ -822,10 +822,10 @@
fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
} else {
if (pci_enabled) {
- pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_addr,
+ pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size, 0, 0);
} else {
- isa_vga_init(ds, phys_ram_base + vga_ram_addr,
+ isa_vga_init(ds, phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
}
}
@@ -914,7 +914,7 @@
smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
}
}
-
+
if (i440fx_state) {
i440fx_init_memory_mappings(i440fx_state);
}
@@ -938,9 +938,9 @@
}
static void pc_init_pci(int ram_size, int vga_ram_size, int boot_device,
- DisplayState *ds, const char **fd_filename,
- int snapshot,
- const char *kernel_filename,
+ DisplayState *ds, const char **fd_filename,
+ int snapshot,
+ const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
@@ -952,9 +952,9 @@
}
static void pc_init_isa(int ram_size, int vga_ram_size, int boot_device,
- DisplayState *ds, const char **fd_filename,
- int snapshot,
- const char *kernel_filename,
+ DisplayState *ds, const char **fd_filename,
+ int snapshot,
+ const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
diff --git a/hw/pci.c b/hw/pci.c
index c7ea314..55cdaa4 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -2,7 +2,7 @@
* QEMU PCI bus manager
*
* Copyright (c) 2004 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -96,16 +96,16 @@
}
/* -1 for devfn means auto assign */
-PCIDevice *pci_register_device(PCIBus *bus, const char *name,
+PCIDevice *pci_register_device(PCIBus *bus, const char *name,
int instance_size, int devfn,
- PCIConfigReadFunc *config_read,
+ PCIConfigReadFunc *config_read,
PCIConfigWriteFunc *config_write)
{
PCIDevice *pci_dev;
if (pci_irq_index >= PCI_DEVICES_MAX)
return NULL;
-
+
if (devfn < 0) {
for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
if (!bus->devices[devfn])
@@ -134,8 +134,8 @@
return pci_dev;
}
-void pci_register_io_region(PCIDevice *pci_dev, int region_num,
- uint32_t size, int type,
+void pci_register_io_region(PCIDevice *pci_dev, int region_num,
+ uint32_t size, int type,
PCIMapIORegionFunc *map_func)
{
PCIIORegion *r;
@@ -166,7 +166,7 @@
PCIIORegion *r;
int cmd, i;
uint32_t last_addr, new_addr, config_ofs;
-
+
cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
for(i = 0; i < PCI_NUM_REGIONS; i++) {
r = &d->io_regions[i];
@@ -178,7 +178,7 @@
if (r->size != 0) {
if (r->type & PCI_ADDRESS_SPACE_IO) {
if (cmd & PCI_COMMAND_IO) {
- new_addr = le32_to_cpu(*(uint32_t *)(d->config +
+ new_addr = le32_to_cpu(*(uint32_t *)(d->config +
config_ofs));
new_addr = new_addr & ~(r->size - 1);
last_addr = new_addr + r->size - 1;
@@ -192,7 +192,7 @@
}
} else {
if (cmd & PCI_COMMAND_MEMORY) {
- new_addr = le32_to_cpu(*(uint32_t *)(d->config +
+ new_addr = le32_to_cpu(*(uint32_t *)(d->config +
config_ofs));
/* the ROM slot has a specific enable bit */
if (i == PCI_ROM_SLOT && !(new_addr & 1))
@@ -227,7 +227,7 @@
}
} else {
cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
- r->size,
+ r->size,
IO_MEM_UNASSIGNED);
}
}
@@ -240,7 +240,7 @@
}
}
-uint32_t pci_default_read_config(PCIDevice *d,
+uint32_t pci_default_read_config(PCIDevice *d,
uint32_t address, int len)
{
uint32_t val;
@@ -266,13 +266,13 @@
return val;
}
-void pci_default_write_config(PCIDevice *d,
+void pci_default_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len)
{
int can_write, i;
uint32_t end, addr;
- if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
+ if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
(address >= 0x30 && address < 0x34))) {
PCIIORegion *r;
int reg;
@@ -367,7 +367,7 @@
PCIBus *s = opaque;
PCIDevice *pci_dev;
int config_addr, bus_num;
-
+
#if defined(DEBUG_PCI) && 0
printf("pci_data_write: addr=%08x val=%08x len=%d\n",
addr, val, len);
@@ -440,7 +440,7 @@
PCIDevice *pci_dev = (PCIDevice *)opaque;
PCIBus *bus;
int change;
-
+
change = level - pci_dev->irq_state[irq_num];
if (!change)
return;
@@ -465,7 +465,7 @@
const char *desc;
} pci_class_desc;
-static pci_class_desc pci_class_descriptions[] =
+static pci_class_desc pci_class_descriptions[] =
{
{ 0x0100, "SCSI controller"},
{ 0x0101, "IDE controller"},
@@ -538,10 +538,10 @@
if (r->size != 0) {
term_printf(" BAR%d: ", i);
if (r->type & PCI_ADDRESS_SPACE_IO) {
- term_printf("I/O at 0x%04x [0x%04x].\n",
+ term_printf("I/O at 0x%04x [0x%04x].\n",
r->addr, r->addr + r->size - 1);
} else {
- term_printf("32 bit memory at 0x%08x [0x%08x].\n",
+ term_printf("32 bit memory at 0x%08x [0x%08x].\n",
r->addr, r->addr + r->size - 1);
}
}
@@ -556,7 +556,7 @@
PCIBus *bus = first_bus;
PCIDevice *d;
int devfn;
-
+
while (bus && bus->bus_num != bus_num)
bus = bus->next;
if (bus) {
@@ -603,7 +603,7 @@
PCIBus *bus;
} PCIBridge;
-void pci_bridge_write_config(PCIDevice *d,
+void pci_bridge_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len)
{
PCIBridge *s = (PCIBridge *)d;
@@ -624,7 +624,7 @@
pci_map_irq_fn map_irq, const char *name)
{
PCIBridge *s;
- s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
+ s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
devfn, NULL, pci_bridge_write_config);
s->dev.config[0x00] = id >> 16;
s->dev.config[0x01] = id >> 24;
diff --git a/hw/pci_host.h b/hw/pci_host.h
index 708dae2..49a0c59 100644
--- a/hw/pci_host.h
+++ b/hw/pci_host.h
@@ -2,7 +2,7 @@
* QEMU Common PCI Host bridge configuration data space access routines.
*
* Copyright (c) 2006 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
diff --git a/hw/pckbd.c b/hw/pckbd.c
index 8f2466d..9b036a6 100644
--- a/hw/pckbd.c
+++ b/hw/pckbd.c
@@ -1,8 +1,8 @@
/*
* QEMU PC keyboard emulation
- *
+ *
* Copyright (c) 2003 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -148,7 +148,7 @@
if (s->mode & KBD_MODE_MOUSE_INT)
irq_mouse_level = 1;
} else {
- if ((s->mode & KBD_MODE_KBD_INT) &&
+ if ((s->mode & KBD_MODE_KBD_INT) &&
!(s->mode & KBD_MODE_DISABLE_KBD))
irq_kbd_level = 1;
}
@@ -338,7 +338,7 @@
static void kbd_save(QEMUFile* f, void* opaque)
{
KBDState *s = (KBDState*)opaque;
-
+
qemu_put_8s(f, &s->write_cmd);
qemu_put_8s(f, &s->status);
qemu_put_8s(f, &s->mode);
@@ -348,7 +348,7 @@
static int kbd_load(QEMUFile* f, void* opaque, int version_id)
{
KBDState *s = (KBDState*)opaque;
-
+
if (version_id != 3)
return -EINVAL;
qemu_get_8s(f, &s->write_cmd);
diff --git a/hw/pcnet.c b/hw/pcnet.c
index ed263ed..11e8fe9 100644
--- a/hw/pcnet.c
+++ b/hw/pcnet.c
@@ -1,8 +1,8 @@
/*
* QEMU AMD PC-Net II (Am79C970A) emulation
- *
+ *
* Copyright (c) 2004 Antony T Curtis
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -21,12 +21,12 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-
+
/* This software was written to be compatible with the specification:
* AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
* AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
*/
-
+
/*
* On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also
* produced as NCR89C100. See
@@ -652,10 +652,10 @@
static inline int padr_match(PCNetState *s, const uint8_t *buf, int size)
{
struct qemu_ether_header *hdr = (void *)buf;
- uint8_t padr[6] = {
+ uint8_t padr[6] = {
s->csr[12] & 0xff, s->csr[12] >> 8,
s->csr[13] & 0xff, s->csr[13] >> 8,
- s->csr[14] & 0xff, s->csr[14] >> 8
+ s->csr[14] & 0xff, s->csr[14] >> 8
};
int result = (!CSR_DRCVPA(s)) && !memcmp(hdr->ether_dhost, padr, 6);
#ifdef PCNET_DEBUG_MATCH
@@ -683,13 +683,13 @@
static inline int ladr_match(PCNetState *s, const uint8_t *buf, int size)
{
struct qemu_ether_header *hdr = (void *)buf;
- if ((*(hdr->ether_dhost)&0x01) &&
+ if ((*(hdr->ether_dhost)&0x01) &&
((uint64_t *)&s->csr[8])[0] != 0LL) {
- uint8_t ladr[8] = {
+ uint8_t ladr[8] = {
s->csr[8] & 0xff, s->csr[8] >> 8,
s->csr[9] & 0xff, s->csr[9] >> 8,
- s->csr[10] & 0xff, s->csr[10] >> 8,
- s->csr[11] & 0xff, s->csr[11] >> 8
+ s->csr[10] & 0xff, s->csr[10] >> 8,
+ s->csr[11] & 0xff, s->csr[11] >> 8
};
int index = lnc_mchash(hdr->ether_dhost) >> 26;
return !!(ladr[index >> 3] & (1 << (index & 7)));
@@ -697,7 +697,7 @@
return 0;
}
-static inline target_phys_addr_t pcnet_rdra_addr(PCNetState *s, int idx)
+static inline target_phys_addr_t pcnet_rdra_addr(PCNetState *s, int idx)
{
while (idx < 1) idx += CSR_RCVRL(s);
return s->rdra + ((CSR_RCVRL(s) - idx) * (BCR_SWSTYLE(s) ? 16 : 8));
@@ -705,8 +705,8 @@
static inline int64_t pcnet_get_next_poll_time(PCNetState *s, int64_t current_time)
{
- int64_t next_time = current_time +
- muldiv64(65536 - (CSR_SPND(s) ? 0 : CSR_POLL(s)),
+ int64_t next_time = current_time +
+ muldiv64(65536 - (CSR_SPND(s) ? 0 : CSR_POLL(s)),
ticks_per_sec, 33000000L);
if (next_time <= current_time)
next_time = current_time + 1;
@@ -731,7 +731,7 @@
s->rdra = 0;
s->tdra = 0;
s->rap = 0;
-
+
s->bcr[BCR_BSBC] &= ~0x0080;
s->csr[0] = 0x0004;
@@ -770,7 +770,7 @@
{
int isr = 0;
s->csr[0] &= ~0x0080;
-
+
#if 1
if (((s->csr[0] & ~s->csr[3]) & 0x5f00) ||
(((s->csr[4]>>1) & ~s->csr[4]) & 0x0115) ||
@@ -790,11 +790,11 @@
(!!(s->csr[5] & 0x0008) && !!(s->csr[5] & 0x0010)) /* MPINT */)
#endif
{
-
+
isr = CSR_INEA(s);
s->csr[0] |= 0x0080;
}
-
+
if (!!(s->csr[4] & 0x0080) && CSR_INEA(s)) { /* UINT */
s->csr[4] &= ~0x0080;
s->csr[4] |= 0x0040;
@@ -806,7 +806,7 @@
}
#if 1
- if (((s->csr[5]>>1) & s->csr[5]) & 0x0500)
+ if (((s->csr[5]>>1) & s->csr[5]) & 0x0500)
#else
if ((!!(s->csr[5] & 0x0400) && !!(s->csr[5] & 0x0800)) /* SINT */ ||
(!!(s->csr[5] & 0x0100) && !!(s->csr[5] & 0x0200)) /* SLPINT */ )
@@ -834,7 +834,7 @@
#ifdef PCNET_DEBUG
printf("pcnet_init init_addr=0x%08x\n", PHYSADDR(s,CSR_IADR(s)));
#endif
-
+
if (BCR_SSIZE32(s)) {
struct pcnet_initblk32 initblk;
s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
@@ -893,12 +893,12 @@
CSR_XMTRC(s) = CSR_XMTRL(s);
#ifdef PCNET_DEBUG
- printf("pcnet ss32=%d rdra=0x%08x[%d] tdra=0x%08x[%d]\n",
+ printf("pcnet ss32=%d rdra=0x%08x[%d] tdra=0x%08x[%d]\n",
BCR_SSIZE32(s),
s->rdra, CSR_RCVRL(s), s->tdra, CSR_XMTRL(s));
#endif
- s->csr[0] |= 0x0101;
+ s->csr[0] |= 0x0101;
s->csr[0] &= ~0x0004; /* clear STOP bit */
}
@@ -910,7 +910,7 @@
if (!CSR_DTX(s))
s->csr[0] |= 0x0010; /* set TXON */
-
+
if (!CSR_DRX(s))
s->csr[0] |= 0x0020; /* set RXON */
@@ -940,15 +940,15 @@
target_phys_addr_t nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
target_phys_addr_t nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
#else
- target_phys_addr_t crda = s->rdra +
+ target_phys_addr_t crda = s->rdra +
(CSR_RCVRL(s) - CSR_RCVRC(s)) *
(BCR_SWSTYLE(s) ? 16 : 8 );
int nrdc = CSR_RCVRC(s)<=1 ? CSR_RCVRL(s) : CSR_RCVRC(s)-1;
- target_phys_addr_t nrda = s->rdra +
+ target_phys_addr_t nrda = s->rdra +
(CSR_RCVRL(s) - nrdc) *
(BCR_SWSTYLE(s) ? 16 : 8 );
int nnrc = nrdc<=1 ? CSR_RCVRL(s) : nrdc-1;
- target_phys_addr_t nnrd = s->rdra +
+ target_phys_addr_t nnrd = s->rdra +
(CSR_RCVRL(s) - nnrc) *
(BCR_SWSTYLE(s) ? 16 : 8 );
#endif
@@ -976,7 +976,7 @@
#endif
}
}
-
+
if (CSR_CRDA(s)) {
struct pcnet_RMD rmd;
RMDLOAD(&rmd, PHYSADDR(s,CSR_CRDA(s)));
@@ -991,7 +991,7 @@
} else {
CSR_CRBC(s) = CSR_CRST(s) = 0;
}
-
+
if (CSR_NRDA(s)) {
struct pcnet_RMD rmd;
RMDLOAD(&rmd, PHYSADDR(s,CSR_NRDA(s)));
@@ -1007,7 +1007,7 @@
{
s->csr[34] = s->csr[35] = 0;
if (s->tdra) {
- target_phys_addr_t cxda = s->tdra +
+ target_phys_addr_t cxda = s->tdra +
(CSR_XMTRL(s) - CSR_XMTRC(s)) *
(BCR_SWSTYLE(s) ? 16 : 8);
int bad = 0;
@@ -1030,14 +1030,14 @@
if (CSR_CXDA(s)) {
struct pcnet_TMD tmd;
- TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
+ TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
CSR_CXBC(s) = GET_FIELD(tmd.length, TMDL, BCNT);
CSR_CXST(s) = tmd.status;
} else {
CSR_CXBC(s) = CSR_CXST(s) = 0;
}
-
+
return !!(CSR_CXST(s) & 0x8000);
}
@@ -1046,7 +1046,7 @@
PCNetState *s = opaque;
if (CSR_STOP(s) || CSR_SPND(s))
return 0;
-
+
if (s->recv_pos > 0)
return 0;
@@ -1076,8 +1076,8 @@
size = MIN_BUF_SIZE;
}
- if (CSR_PROM(s)
- || (is_padr=padr_match(s, buf, size))
+ if (CSR_PROM(s)
+ || (is_padr=padr_match(s, buf, size))
|| (is_bcast=padr_bcast(s, buf, size))
|| (is_ladr=ladr_match(s, buf, size))) {
@@ -1093,10 +1093,10 @@
nrda = s->rdra +
(CSR_RCVRL(s) - rcvrc) *
(BCR_SWSTYLE(s) ? 16 : 8 );
- RMDLOAD(&rmd, PHYSADDR(s,nrda));
+ RMDLOAD(&rmd, PHYSADDR(s,nrda));
if (GET_FIELD(rmd.status, RMDS, OWN)) {
#ifdef PCNET_DEBUG_RMD
- printf("pcnet - scan buffer: RCVRC=%d PREV_RCVRC=%d\n",
+ printf("pcnet - scan buffer: RCVRC=%d PREV_RCVRC=%d\n",
rcvrc, CSR_RCVRC(s));
#endif
CSR_RCVRC(s) = rcvrc;
@@ -1119,7 +1119,7 @@
int pktcount = 0;
memcpy(src, buf, size);
-
+
#if 1
/* no need to compute the CRC */
src[size] = 0;
@@ -1136,7 +1136,7 @@
while (size < 46) {
src[size++] = 0;
}
-
+
while (p != &src[size]) {
CRC(fcs, *p++);
}
@@ -1178,7 +1178,7 @@
PCNET_RECV_STORE();
}
}
- }
+ }
}
#undef PCNET_RECV_STORE
@@ -1198,27 +1198,27 @@
s->csr[0] |= 0x0400;
#ifdef PCNET_DEBUG
- printf("RCVRC=%d CRDA=0x%08x BLKS=%d\n",
+ printf("RCVRC=%d CRDA=0x%08x BLKS=%d\n",
CSR_RCVRC(s), PHYSADDR(s,CSR_CRDA(s)), pktcount);
#endif
#ifdef PCNET_DEBUG_RMD
PRINT_RMD(&rmd);
-#endif
+#endif
while (pktcount--) {
if (CSR_RCVRC(s) <= 1)
CSR_RCVRC(s) = CSR_RCVRL(s);
else
- CSR_RCVRC(s)--;
+ CSR_RCVRC(s)--;
}
-
+
pcnet_rdte_poll(s);
- }
+ }
}
pcnet_poll(s);
- pcnet_update_irq(s);
+ pcnet_update_irq(s);
}
static void pcnet_transmit(PCNetState *s)
@@ -1226,7 +1226,7 @@
target_phys_addr_t xmit_cxda = 0;
int count = CSR_XMTRL(s)-1;
s->xmit_pos = -1;
-
+
if (!CSR_TXON(s)) {
s->csr[0] &= ~0x0008;
return;
@@ -1285,7 +1285,7 @@
if (count--)
goto txagain;
- } else
+ } else
if (s->xmit_pos >= 0) {
struct pcnet_TMD tmd;
TMDLOAD(&tmd, PHYSADDR(s,xmit_cxda));
@@ -1311,7 +1311,7 @@
pcnet_rdte_poll(s);
}
- if (CSR_TDMD(s) ||
+ if (CSR_TDMD(s) ||
(CSR_TXON(s) && !CSR_DPOLL(s) && pcnet_tdte_poll(s)))
{
/* prevent recursion */
@@ -1332,7 +1332,7 @@
pcnet_transmit(s);
}
- pcnet_update_irq(s);
+ pcnet_update_irq(s);
if (!CSR_STOP(s) && !CSR_SPND(s) && !CSR_DPOLL(s)) {
uint64_t now = qemu_get_clock(vm_clock) * 33;
@@ -1346,7 +1346,7 @@
} else
CSR_POLL(s) = t;
}
- qemu_mod_timer(s->poll_timer,
+ qemu_mod_timer(s->poll_timer,
pcnet_get_next_poll_time(s,qemu_get_clock(vm_clock)));
}
}
@@ -1379,7 +1379,7 @@
if (!CSR_STRT(s) && (val & 2))
pcnet_start(s);
- if (CSR_TDMD(s))
+ if (CSR_TDMD(s))
pcnet_transmit(s);
return;
@@ -1434,11 +1434,11 @@
case 3:
break;
case 4:
- s->csr[4] &= ~(val & 0x026a);
+ s->csr[4] &= ~(val & 0x026a);
val &= ~0x026a; val |= s->csr[4] & 0x026a;
break;
case 5:
- s->csr[5] &= ~(val & 0x0a90);
+ s->csr[5] &= ~(val & 0x0a90);
val &= ~0x0a90; val |= s->csr[5] & 0x0a90;
break;
case 16:
@@ -1592,11 +1592,11 @@
PCNetState *s = opaque;
#ifdef PCNET_DEBUG
printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val);
-#endif
+#endif
/* Check APROMWE bit to enable write access */
if (pcnet_bcr_readw(s,2) & 0x80)
s->prom[addr & 15] = val;
-}
+}
static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
{
@@ -1685,7 +1685,7 @@
pcnet_bcr_writew(s, BCR_BSBC, pcnet_bcr_readw(s, BCR_BSBC) | 0x0080);
#ifdef PCNET_DEBUG_IO
printf("device switched into dword i/o mode\n");
-#endif
+#endif
}
pcnet_update_irq(s);
}
@@ -1695,7 +1695,7 @@
PCNetState *s = opaque;
uint32_t val = -1;
pcnet_poll_timer(s);
- if (BCR_DWIO(s)) {
+ if (BCR_DWIO(s)) {
switch (addr & 0x0f) {
case 0x00: /* RDP */
val = pcnet_csr_readw(s, s->rap);
@@ -1719,7 +1719,7 @@
return val;
}
-static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,
+static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
PCNetState *d = (PCNetState *)pci_dev;
@@ -1730,7 +1730,7 @@
register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d);
register_ioport_read(addr, 16, 1, pcnet_aprom_readb, d);
-
+
register_ioport_write(addr + 0x10, 0x10, 2, pcnet_ioport_writew, d);
register_ioport_read(addr + 0x10, 0x10, 2, pcnet_ioport_readw, d);
register_ioport_write(addr + 0x10, 0x10, 4, pcnet_ioport_writel, d);
@@ -1747,7 +1747,7 @@
pcnet_aprom_writeb(d, addr & 0x0f, val);
}
-static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
{
PCNetState *d = opaque;
uint32_t val = -1;
@@ -1774,7 +1774,7 @@
}
}
-static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
{
PCNetState *d = opaque;
uint32_t val = -1;
@@ -1809,7 +1809,7 @@
}
}
-static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
{
PCNetState *d = opaque;
uint32_t val;
@@ -1931,7 +1931,7 @@
(CPUReadMemoryFunc *)&pcnet_mmio_readl
};
-static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num,
+static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
PCNetState *d = (PCNetState *)pci_dev;
@@ -1961,28 +1961,28 @@
uint8_t *pci_conf;
#if 0
- printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
+ printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
#endif
d = (PCNetState *)pci_register_device(bus, "PCNet", sizeof(PCNetState),
devfn, NULL, NULL);
-
+
pci_conf = d->dev.config;
-
+
*(uint16_t *)&pci_conf[0x00] = cpu_to_le16(0x1022);
- *(uint16_t *)&pci_conf[0x02] = cpu_to_le16(0x2000);
- *(uint16_t *)&pci_conf[0x04] = cpu_to_le16(0x0007);
+ *(uint16_t *)&pci_conf[0x02] = cpu_to_le16(0x2000);
+ *(uint16_t *)&pci_conf[0x04] = cpu_to_le16(0x0007);
*(uint16_t *)&pci_conf[0x06] = cpu_to_le16(0x0280);
pci_conf[0x08] = 0x10;
pci_conf[0x09] = 0x00;
- pci_conf[0x0a] = 0x00; // ethernet network controller
+ pci_conf[0x0a] = 0x00; // ethernet network controller
pci_conf[0x0b] = 0x02;
pci_conf[0x0e] = 0x00; // header_type
-
+
*(uint32_t *)&pci_conf[0x10] = cpu_to_le32(0x00000001);
*(uint32_t *)&pci_conf[0x14] = cpu_to_le32(0x00000000);
-
+
pci_conf[0x3d] = 1; // interrupt pin 0
pci_conf[0x3e] = 0x06;
pci_conf[0x3f] = 0xff;
@@ -1991,12 +1991,12 @@
d->mmio_index =
cpu_register_io_memory(0, pcnet_mmio_read, pcnet_mmio_write, d);
- pci_register_io_region((PCIDevice *)d, 0, PCNET_IOPORT_SIZE,
+ pci_register_io_region((PCIDevice *)d, 0, PCNET_IOPORT_SIZE,
PCI_ADDRESS_SPACE_IO, pcnet_ioport_map);
-
- pci_register_io_region((PCIDevice *)d, 1, PCNET_PNPMMIO_SIZE,
+
+ pci_register_io_region((PCIDevice *)d, 1, PCNET_PNPMMIO_SIZE,
PCI_ADDRESS_SPACE_MEM, pcnet_mmio_map);
-
+
d->irq = d->dev.irq[0];
d->phys_mem_read = pci_physical_memory_read;
d->phys_mem_write = pci_physical_memory_write;
diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c
index f98d114..2545bcb 100644
--- a/hw/pflash_cfi02.c
+++ b/hw/pflash_cfi02.c
@@ -1,6 +1,6 @@
/*
* CFI parallel flash with AMD command set emulation
- *
+ *
* Copyright (c) 2005 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
@@ -185,7 +185,7 @@
}
/* update flash content on disk */
-static void pflash_update(pflash_t *pfl, int offset,
+static void pflash_update(pflash_t *pfl, int offset,
int size)
{
int offset_end;
@@ -194,7 +194,7 @@
/* round to sectors */
offset = offset >> 9;
offset_end = (offset_end + 511) >> 9;
- bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
+ bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
offset_end - offset);
}
}
@@ -222,7 +222,7 @@
offset -= (uint32_t)(long)pfl->storage;
else
offset -= pfl->base;
-
+
DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__,
offset, value, width);
/* Set the device in I/O access mode */
@@ -369,7 +369,7 @@
pfl->status = 0x00;
pflash_update(pfl, 0, pfl->total_len);
/* Let's wait 5 seconds before chip erase is done */
- qemu_mod_timer(pfl->timer,
+ qemu_mod_timer(pfl->timer,
qemu_get_clock(vm_clock) + (ticks_per_sec * 5));
break;
case 0x30:
@@ -382,7 +382,7 @@
pflash_update(pfl, offset, pfl->sector_len);
pfl->status = 0x00;
/* Let's wait 1/2 second before sector erase is done */
- qemu_mod_timer(pfl->timer,
+ qemu_mod_timer(pfl->timer,
qemu_get_clock(vm_clock) + (ticks_per_sec / 2));
break;
default:
@@ -524,7 +524,7 @@
pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width,
- uint16_t id0, uint16_t id1,
+ uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3)
{
pflash_t *pfl;
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 095698c..8c00f0d 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -2,7 +2,7 @@
* QEMU i440FX/PIIX3 PCI Bridge Emulation
*
* Copyright (c) 2006 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -63,19 +63,19 @@
switch(r) {
case 3:
/* RAM */
- cpu_register_physical_memory(start, end - start,
+ cpu_register_physical_memory(start, end - start,
start);
break;
case 1:
/* ROM (XXX: not quite correct) */
- cpu_register_physical_memory(start, end - start,
+ cpu_register_physical_memory(start, end - start,
start | IO_MEM_ROM);
break;
case 2:
case 0:
/* XXX: should distinguish read/write cases */
for(addr = start; addr < end; addr += 4096) {
- cpu_register_physical_memory(addr, 4096,
+ cpu_register_physical_memory(addr, 4096,
isa_page_descs[(addr - 0xa0000) >> 12]);
}
break;
@@ -97,7 +97,7 @@
cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
} else {
for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
- cpu_register_physical_memory(addr, 4096,
+ cpu_register_physical_memory(addr, 4096,
isa_page_descs[(addr - 0xa0000) >> 12]);
}
}
@@ -124,7 +124,7 @@
}
}
-static void i440fx_write_config(PCIDevice *d,
+static void i440fx_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len)
{
/* XXX: implement SMRAM.D_LOCK */
@@ -175,7 +175,7 @@
register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
- d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
+ d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
NULL, i440fx_write_config);
d->config[0x00] = 0x86; // vendor_id
diff --git a/hw/pl011.c b/hw/pl011.c
index 149a85e..e66741b 100644
--- a/hw/pl011.c
+++ b/hw/pl011.c
@@ -1,4 +1,4 @@
-/*
+/*
* Arm PrimeCell PL011 UART
*
* Copyright (c) 2006 CodeSourcery.
@@ -44,7 +44,7 @@
static void pl011_update(pl011_state *s)
{
uint32_t flags;
-
+
flags = s->int_level & s->int_enabled;
qemu_set_irq(s->irq, flags != 0);
}
@@ -240,7 +240,7 @@
s->ifl = 0x12;
s->cr = 0x300;
s->flags = 0x90;
- if (chr){
+ if (chr){
qemu_chr_add_handlers(chr, pl011_can_receive, pl011_receive,
pl011_event, s);
}
diff --git a/hw/pl050.c b/hw/pl050.c
index 521c9e6..b3a2797 100644
--- a/hw/pl050.c
+++ b/hw/pl050.c
@@ -1,4 +1,4 @@
-/*
+/*
* Arm PrimeCell PL050 Keyboard / Mouse Interface
*
* Copyright (c) 2006-2007 CodeSourcery.
diff --git a/hw/pl080.c b/hw/pl080.c
index bc1a975..b24cfba 100644
--- a/hw/pl080.c
+++ b/hw/pl080.c
@@ -1,4 +1,4 @@
-/*
+/*
* Arm PrimeCell PL080/PL081 DMA controller
*
* Copyright (c) 2006 CodeSourcery.
@@ -111,7 +111,7 @@
continue;
flow = (ch->conf >> 11) & 7;
if (flow >= 4) {
- cpu_abort(cpu_single_env,
+ cpu_abort(cpu_single_env,
"pl080_run: Peripheral flow control not implemented\n");
}
src_id = (ch->conf >> 1) & 0x1f;
diff --git a/hw/pl110.c b/hw/pl110.c
index 9df77c4..3494264 100644
--- a/hw/pl110.c
+++ b/hw/pl110.c
@@ -1,4 +1,4 @@
-/*
+/*
* Arm PrimeCell PL110 Color LCD Controller
*
* Copyright (c) 2005-2006 CodeSourcery.
@@ -117,7 +117,7 @@
if (!pl110_enabled(s))
return;
-
+
switch (s->ds->depth) {
case 0:
return;
@@ -151,7 +151,7 @@
fn = fntable[s->bpp + 12];
else
fn = fntable[s->bpp];
-
+
src_width = s->cols;
switch (s->bpp) {
case BPP_1:
diff --git a/hw/pl110_template.h b/hw/pl110_template.h
index ed533ac..f7cb1f4 100644
--- a/hw/pl110_template.h
+++ b/hw/pl110_template.h
@@ -1,4 +1,4 @@
-/*
+/*
* Arm PrimeCell PL110 Color LCD Controller
*
* Copyright (c) 2005 CodeSourcery, LLC.
@@ -15,7 +15,7 @@
#define COPY_PIXEL(to, from) *(to++) = from
#elif BITS == 15 || BITS == 16
#define COPY_PIXEL(to, from) *(uint16_t *)to = from; to += 2;
-#elif BITS == 24
+#elif BITS == 24
#define COPY_PIXEL(to, from) \
*(to++) = from; *(to++) = (from) >> 8; *(to++) = (from) >> 16
#elif BITS == 32
diff --git a/hw/pl181.c b/hw/pl181.c
index 62ccad9..b450e58 100644
--- a/hw/pl181.c
+++ b/hw/pl181.c
@@ -1,4 +1,4 @@
-/*
+/*
* Arm PrimeCell PL181 MultiMedia Card Interface
*
* Copyright (c) 2007 CodeSourcery.
@@ -177,7 +177,7 @@
/* Transfer data between the card and the FIFO. This is complicated by
the FIFO holding 32-bit words and the card taking data in single byte
chunks. FIFO bytes are transferred in little-endian order. */
-
+
static void pl181_fifo_run(pl181_state *s)
{
uint32_t bits;
diff --git a/hw/pl190.c b/hw/pl190.c
index e36c448..23494d8 100644
--- a/hw/pl190.c
+++ b/hw/pl190.c
@@ -1,4 +1,4 @@
-/*
+/*
* Arm PrimeCell PL190 Vector Interrupt Controller
*
* Copyright (c) 2006 CodeSourcery.
diff --git a/hw/ppc.c b/hw/ppc.c
index b4748f6..a901243 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -1,8 +1,8 @@
/*
* QEMU generic PowerPC hardware System Emulator
- *
+ *
* Copyright (c) 2003-2007 Jocelyn Mayer
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -623,7 +623,7 @@
uint64_t wdt_next; /* Tick for next WDT interrupt */
struct QEMUTimer *wdt_timer;
};
-
+
/* Fixed interval timer */
static void cpu_4xx_fit_cb (void *opaque)
{
diff --git a/hw/ppc405.h b/hw/ppc405.h
index b2624c3..b3f3b3d 100644
--- a/hw/ppc405.h
+++ b/hw/ppc405.h
@@ -1,8 +1,8 @@
/*
* QEMU PowerPC 405 shared definitions
- *
+ *
* Copyright (c) 2007 Jocelyn Mayer
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
index b0be417..cfb592e 100644
--- a/hw/ppc405_boards.c
+++ b/hw/ppc405_boards.c
@@ -1,8 +1,8 @@
/*
* QEMU PowerPC 405 evaluation boards emulation
- *
+ *
* Copyright (c) 2007 Jocelyn Mayer
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -172,9 +172,9 @@
}
static void ref405ep_init (int ram_size, int vga_ram_size, int boot_device,
- DisplayState *ds, const char **fd_filename,
+ DisplayState *ds, const char **fd_filename,
int snapshot,
- const char *kernel_filename,
+ const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
@@ -243,7 +243,7 @@
exit(1);
}
bios_size = (bios_size + 0xfff) & ~0xfff;
- cpu_register_physical_memory((uint32_t)(-bios_size),
+ cpu_register_physical_memory((uint32_t)(-bios_size),
bios_size, bios_offset | IO_MEM_ROM);
}
bios_offset += bios_size;
@@ -294,7 +294,7 @@
/* now we can load the kernel */
kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
if (kernel_size < 0) {
- fprintf(stderr, "qemu: could not load kernel '%s'\n",
+ fprintf(stderr, "qemu: could not load kernel '%s'\n",
kernel_filename);
exit(1);
}
@@ -310,7 +310,7 @@
initrd_size = load_image(initrd_filename,
phys_ram_base + initrd_base);
if (initrd_size < 0) {
- fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
+ fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
initrd_filename);
exit(1);
}
@@ -495,9 +495,9 @@
}
static void taihu_405ep_init(int ram_size, int vga_ram_size, int boot_device,
- DisplayState *ds, const char **fd_filename,
+ DisplayState *ds, const char **fd_filename,
int snapshot,
- const char *kernel_filename,
+ const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
@@ -511,7 +511,7 @@
target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
int linux_boot;
int fl_idx, fl_sectors;
-
+
/* RAM is soldered to the board so the size cannot be changed */
ram_bases[0] = 0x00000000;
ram_sizes[0] = 0x04000000;
@@ -556,7 +556,7 @@
exit(1);
}
bios_size = (bios_size + 0xfff) & ~0xfff;
- cpu_register_physical_memory((uint32_t)(-bios_size),
+ cpu_register_physical_memory((uint32_t)(-bios_size),
bios_size, bios_offset | IO_MEM_ROM);
}
bios_offset += bios_size;
@@ -592,7 +592,7 @@
/* now we can load the kernel */
kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
if (kernel_size < 0) {
- fprintf(stderr, "qemu: could not load kernel '%s'\n",
+ fprintf(stderr, "qemu: could not load kernel '%s'\n",
kernel_filename);
exit(1);
}
@@ -603,7 +603,7 @@
phys_ram_base + initrd_base);
if (initrd_size < 0) {
fprintf(stderr,
- "qemu: could not load initial ram disk '%s'\n",
+ "qemu: could not load initial ram disk '%s'\n",
initrd_filename);
exit(1);
}
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 384eb0d..1a6a666 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -1,8 +1,8 @@
/*
* QEMU PowerPC 405 embedded processors emulation
- *
+ *
* Copyright (c) 2007 Jocelyn Mayer
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -2212,7 +2212,7 @@
}
mask = mask >> 1;
}
-
+
}
static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
@@ -2228,7 +2228,7 @@
qemu_irq_lower(gpt->irqs[i]);
mask = mask >> 1;
}
-
+
}
static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
diff --git a/hw/ppc_chrp.c b/hw/ppc_chrp.c
index a8114fa..e5a6313 100644
--- a/hw/ppc_chrp.c
+++ b/hw/ppc_chrp.c
@@ -1,8 +1,8 @@
/*
* QEMU PPC CHRP/PMAC hardware System Emulator
- *
+ *
* Copyright (c) 2004-2007 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -129,16 +129,16 @@
s = qemu_mallocz(sizeof(MacIONVRAMState));
if (!s)
return NULL;
- macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
+ macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
macio_nvram_write, s);
return s;
}
-static void macio_map(PCIDevice *pci_dev, int region_num,
+static void macio_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
if (heathrow_pic_mem_index >= 0) {
- cpu_register_physical_memory(addr + 0x00000, 0x1000,
+ cpu_register_physical_memory(addr + 0x00000, 0x1000,
heathrow_pic_mem_index);
}
cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index);
@@ -148,7 +148,7 @@
if (ide1_mem_index >= 0)
cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
if (openpic_mem_index >= 0) {
- cpu_register_physical_memory(addr + 0x40000, 0x40000,
+ cpu_register_physical_memory(addr + 0x40000, 0x40000,
openpic_mem_index);
}
if (macio_nvram_mem_index >= 0)
@@ -173,10 +173,10 @@
d->config[0x0e] = 0x00; // header_type
d->config[0x3d] = 0x01; // interrupt on pin 1
-
+
dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);
- pci_register_io_region(d, 0, 0x80000,
+ pci_register_io_region(d, 0, 0x80000,
PCI_ADDRESS_SPACE_MEM, macio_map);
}
@@ -208,7 +208,7 @@
{
static int vga_vbl_enabled;
int linesize;
-
+
// printf("osi_call R5=%d\n", env->gpr[5]);
/* same handler as PearPC, coming from the original MOL video
@@ -229,7 +229,7 @@
break;
}
}
- env->gpr[3] = 0;
+ env->gpr[3] = 0;
env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
@@ -255,7 +255,7 @@
break;
case 64: /* get color */
/* R6 = index */
- env->gpr[3] = 0;
+ env->gpr[3] = 0;
break;
case 116: /* set hwcursor */
/* R6 = x, R7 = y, R8 = visible, R9 = data */
@@ -280,14 +280,14 @@
void pmac_format_nvram_partition(uint8_t *buf, int len)
{
char partition_name[12] = "wwwwwwwwwwww";
-
+
buf[0] = 0x7f; /* free partition magic */
buf[1] = 0; /* checksum */
buf[2] = len >> 8;
buf[3] = len;
memcpy(buf + 4, partition_name, 12);
buf[1] = nvram_chksum(buf, 16);
-}
+}
/* PowerPC CHRP hardware initialisation */
static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
@@ -355,7 +355,7 @@
bios_size = (bios_size + 0xfff) & ~0xfff;
cpu_register_physical_memory((uint32_t)(-bios_size),
bios_size, bios_offset | IO_MEM_ROM);
-
+
/* allocate and load VGA BIOS */
vga_bios_offset = bios_offset + bios_size;
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
@@ -371,12 +371,12 @@
phys_ram_base[vga_bios_offset + 1] = 'D';
phys_ram_base[vga_bios_offset + 2] = 'R';
phys_ram_base[vga_bios_offset + 3] = 'V';
- cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
+ cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
vga_bios_size);
vga_bios_size += 8;
}
vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
-
+
if (linux_boot) {
kernel_base = KERNEL_LOAD_ADDR;
/* now we can load the kernel */
@@ -427,24 +427,24 @@
/* XXX: suppress that */
dummy_irq = i8259_init(NULL);
-
+
/* XXX: use Mac Serial port */
serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
-
+
for(i = 0; i < nb_nics; i++) {
if (!nd_table[i].model)
nd_table[i].model = "ne2k_pci";
pci_nic_init(pci_bus, &nd_table[i], -1);
}
-
+
pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
/* cuda also initialize ADB */
cuda_mem_index = cuda_init(pic[0x12]);
-
+
adb_kbd_init(&adb_bus);
adb_mouse_init(&adb_bus);
-
+
{
MacIONVRAMState *nvr;
nvr = macio_nvram_init();
@@ -534,14 +534,14 @@
#endif
/* cuda also initialize ADB */
cuda_mem_index = cuda_init(pic[0x19]);
-
+
adb_kbd_init(&adb_bus);
adb_mouse_init(&adb_bus);
-
+
macio_init(pci_bus, 0x0022);
-
+
nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
-
+
arch_name = "MAC99";
}
@@ -578,7 +578,7 @@
kernel_filename, kernel_cmdline,
initrd_filename, cpu_model, 0);
}
-
+
static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device,
DisplayState *ds, const char **fd_filename,
int snapshot,
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 4b9d9d1..d1075d9 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -1,8 +1,8 @@
/*
* QEMU PPC PREP hardware System Emulator
- *
+ *
* Copyright (c) 2003-2007 Jocelyn Mayer
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -612,7 +612,7 @@
cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
/* init basic PC hardware */
- pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size,
+ pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size,
vga_ram_size, 0, 0);
// openpic = openpic_init(0x00000000, 0xF0000000, 1);
// pit = pit_init(0x40, i8259[0]);
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index be62b89..f384e42 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -2,7 +2,7 @@
* QEMU PREP PCI host
*
* Copyright (c) 2006 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -147,12 +147,12 @@
register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
- PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
+ PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
PPC_PCIIO_write, s);
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
- /* PCI host bridge */
- d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
+ /* PCI host bridge */
+ d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
sizeof(PCIDevice), 0, NULL, NULL);
d->config[0x00] = 0x57; // vendor_id : Motorola
d->config[0x01] = 0x10;
diff --git a/hw/ps2.c b/hw/ps2.c
index 2d87f1f..233ff54 100644
--- a/hw/ps2.c
+++ b/hw/ps2.c
@@ -1,8 +1,8 @@
/*
* QEMU PS/2 keyboard/mouse emulation
- *
+ *
* Copyright (c) 2003 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -146,7 +146,7 @@
PS2State *s = (PS2State *)opaque;
PS2Queue *q;
int val, index;
-
+
q = &s->queue;
if (q->count == 0) {
/* NOTE: if no data left, we return the last keyboard one
@@ -294,7 +294,7 @@
s->mouse_dz -= dz1;
}
-static void ps2_mouse_event(void *opaque,
+static void ps2_mouse_event(void *opaque,
int dx, int dy, int dz, int buttons_state)
{
PS2MouseState *s = opaque;
@@ -311,7 +311,7 @@
s->mouse_buttons == buttons_state)
return;
s->mouse_buttons = buttons_state;
-
+
if (!(s->mouse_status & MOUSE_STATUS_REMOTE) &&
(s->common.queue.count < (PS2_QUEUE_SIZE - 16))) {
for(;;) {
@@ -434,12 +434,12 @@
s->mouse_detect_state = 0;
break;
case 2:
- if (val == 80)
+ if (val == 80)
s->mouse_type = 3; /* IMPS/2 */
s->mouse_detect_state = 0;
break;
case 3:
- if (val == 80)
+ if (val == 80)
s->mouse_type = 4; /* IMEX */
s->mouse_detect_state = 0;
break;
diff --git a/hw/ptimer.c b/hw/ptimer.c
index 2abf285..d81503a 100644
--- a/hw/ptimer.c
+++ b/hw/ptimer.c
@@ -1,4 +1,4 @@
-/*
+/*
* General purpose implementation of a simple periodic countdown timer.
*
* Copyright (c) 2007 CodeSourcery.
diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c
index b3db974..85aeb50 100644
--- a/hw/pxa2xx_gpio.c
+++ b/hw/pxa2xx_gpio.c
@@ -53,7 +53,7 @@
} pxa2xx_gpio_regs[0x200] = {
[0 ... 0x1ff] = { GPIO_NONE, 0 },
#define PXA2XX_REG(reg, a0, a1, a2, a3) \
- [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
+ [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
diff --git a/hw/pxa2xx_template.h b/hw/pxa2xx_template.h
index 341be12..ad3799d 100644
--- a/hw/pxa2xx_template.h
+++ b/hw/pxa2xx_template.h
@@ -14,7 +14,7 @@
# define COPY_PIXEL(to, from) *to = from; SKIP_PIXEL(to)
#elif BITS == 15 || BITS == 16
# define COPY_PIXEL(to, from) *(uint16_t *) to = from; SKIP_PIXEL(to)
-#elif BITS == 24
+#elif BITS == 24
# define COPY_PIXEL(to, from) \
*(uint16_t *) to = from; *(to + 2) = (from) >> 16; SKIP_PIXEL(to)
#elif BITS == 32
diff --git a/hw/realview.c b/hw/realview.c
index 1ca02d5..375f78a 100644
--- a/hw/realview.c
+++ b/hw/realview.c
@@ -1,4 +1,4 @@
-/*
+/*
* ARM RealView Baseboard System emulation.
*
* Copyright (c) 2006-2007 CodeSourcery.
diff --git a/hw/rtl8139.c b/hw/rtl8139.c
index 210af44..097ad47 100644
--- a/hw/rtl8139.c
+++ b/hw/rtl8139.c
@@ -1,8 +1,8 @@
/**
* QEMU RTL8139 emulation
- *
+ *
* Copyright (c) 2006 Igor Kovalenko
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -20,13 +20,13 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
-
+
* Modifications:
* 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
- *
+ *
* 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
* HW revision ID changes for FreeBSD driver
- *
+ *
* 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
* Corrected packet transfer reassembly routine for 8139C+ mode
* Rearranged debugging print statements
@@ -305,11 +305,11 @@
CSCR_LinkDownCmd = 0x0f3c0,
*/
enum CSCRBits {
- CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
+ CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
- CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
+ CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
@@ -813,7 +813,7 @@
uint32_t packet_header = 0;
uint8_t buf1[60];
- static const uint8_t broadcast_macaddr[6] =
+ static const uint8_t broadcast_macaddr[6] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
@@ -890,10 +890,10 @@
++s->tally_counters.RxOkMul;
} else if (s->phys[0] == buf[0] &&
- s->phys[1] == buf[1] &&
- s->phys[2] == buf[2] &&
- s->phys[3] == buf[3] &&
- s->phys[4] == buf[4] &&
+ s->phys[1] == buf[1] &&
+ s->phys[2] == buf[2] &&
+ s->phys[3] == buf[3] &&
+ s->phys[4] == buf[4] &&
s->phys[5] == buf[5]) {
/* match */
if (!(s->RxConfig & AcceptMyPhys))
@@ -1225,7 +1225,7 @@
s->Config3 = 0x1; /* fast back-to-back compatible */
s->Config5 = 0x0;
- s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
+ s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
s->CpCmd = 0x0; /* reset C+ mode */
@@ -2420,17 +2420,17 @@
|((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
|((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
|((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
-
+
|((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
|((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
|((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
|((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
-
+
|((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
|((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
|((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
|((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
-
+
DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
@@ -3315,7 +3315,7 @@
RTL8139State rtl8139;
} PCIRTL8139State;
-static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
+static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
@@ -3324,7 +3324,7 @@
cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
}
-static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
+static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
@@ -3354,7 +3354,7 @@
static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time)
{
- int64_t next_time = current_time +
+ int64_t next_time = current_time +
muldiv64(1, ticks_per_sec, PCI_FREQUENCY);
if (next_time <= current_time)
next_time = current_time + 1;
@@ -3400,7 +3400,7 @@
rtl8139_update_irq(s);
}
- qemu_mod_timer(s->timer,
+ qemu_mod_timer(s->timer,
rtl8139_get_next_tctr_time(s,curr_time));
}
#endif /* RTL8139_ONBOARD_TIMER */
@@ -3410,10 +3410,10 @@
PCIRTL8139State *d;
RTL8139State *s;
uint8_t *pci_conf;
-
+
d = (PCIRTL8139State *)pci_register_device(bus,
"RTL8139", sizeof(PCIRTL8139State),
- devfn,
+ devfn,
NULL, NULL);
pci_conf = d->dev.config;
pci_conf[0x00] = 0xec; /* Realtek 8139 */
@@ -3434,10 +3434,10 @@
s->rtl8139_mmio_io_addr =
cpu_register_io_memory(0, rtl8139_mmio_read, rtl8139_mmio_write, s);
- pci_register_io_region(&d->dev, 0, 0x100,
+ pci_register_io_region(&d->dev, 0, 0x100,
PCI_ADDRESS_SPACE_IO, rtl8139_ioport_map);
- pci_register_io_region(&d->dev, 1, 0x100,
+ pci_register_io_region(&d->dev, 1, 0x100,
PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map);
s->pci_dev = (PCIDevice *)d;
@@ -3458,14 +3458,14 @@
s->cplus_txbuffer = NULL;
s->cplus_txbuffer_len = 0;
s->cplus_txbuffer_offset = 0;
-
+
/* XXX: instance number ? */
register_savevm("rtl8139", 0, 3, rtl8139_save, rtl8139_load, s);
#if RTL8139_ONBOARD_TIMER
s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
- qemu_mod_timer(s->timer,
+ qemu_mod_timer(s->timer,
rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock)));
#endif /* RTL8139_ONBOARD_TIMER */
}
diff --git a/hw/sd.c b/hw/sd.c
index 7974564..d59c4bf 100644
--- a/hw/sd.c
+++ b/hw/sd.c
@@ -1,4 +1,4 @@
-/*
+/*
* SD Memory Card emulation as defined in the "SD Memory Card Physical
* layer specification, Version 1.10."
*
diff --git a/hw/sd.h b/hw/sd.h
index 2851e72..ab20064 100644
--- a/hw/sd.h
+++ b/hw/sd.h
@@ -1,4 +1,4 @@
-/*
+/*
* SD Memory Card emulation. Mostly correct for MMC too.
*
* Copyright (c) 2006 Andrzej Zaborowski <[email protected]>
diff --git a/hw/serial.c b/hw/serial.c
index 5513007..ac3995b 100644
--- a/hw/serial.c
+++ b/hw/serial.c
@@ -1,8 +1,8 @@
/*
* QEMU 16450 UART emulation
- *
+ *
* Copyright (c) 2003-2004 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -119,7 +119,7 @@
} else {
parity = 'N';
}
- if (s->lcr & 0x04)
+ if (s->lcr & 0x04)
stop_bits = 2;
else
stop_bits = 1;
@@ -133,7 +133,7 @@
ssp.stop_bits = stop_bits;
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
#if 0
- printf("speed=%d parity=%c data=%d stop=%d\n",
+ printf("speed=%d parity=%c data=%d stop=%d\n",
speed, parity, data_bits, stop_bits);
#endif
}
@@ -142,7 +142,7 @@
{
SerialState *s = opaque;
unsigned char ch;
-
+
addr &= 7;
#ifdef DEBUG_SERIAL
printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
@@ -187,7 +187,7 @@
break_enable = (val >> 6) & 1;
if (break_enable != s->last_break_enable) {
s->last_break_enable = break_enable;
- qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
+ qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
&break_enable);
}
}
@@ -215,7 +215,7 @@
default:
case 0:
if (s->lcr & UART_LCR_DLAB) {
- ret = s->divider & 0xff;
+ ret = s->divider & 0xff;
} else {
ret = s->rbr;
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 164ce71..dcba14e 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -1,8 +1,8 @@
/*
* SH7750 device
- *
+ *
* Copyright (c) 2005 Samuel Tardieu
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
diff --git a/hw/sh7750_regs.h b/hw/sh7750_regs.h
index 44ae95b..6b18ad2 100644
--- a/hw/sh7750_regs.h
+++ b/hw/sh7750_regs.h
@@ -12,26 +12,26 @@
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
- *
+ *
* @(#) sh7750_regs.h,v 1.2.4.1 2003/09/04 18:46:00 joel Exp
*/
#ifndef __SH7750_REGS_H__
#define __SH7750_REGS_H__
-/*
- * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
+/*
+ * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
* in 0x1f000000 - 0x1fffffff (area 7 address)
*/
-#define SH7750_P4_BASE 0xff000000 /* Accessable only in
+#define SH7750_P4_BASE 0xff000000 /* Accessable only in
priveleged mode */
#define SH7750_A7_BASE 0x1f000000 /* Accessable only using TLB */
#define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs))
#define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs))
-/*
- * MMU Registers
+/*
+ * MMU Registers
*/
/* Page Table Entry High register - PTEH */
@@ -61,9 +61,9 @@
#define SH7750_PTEL_PR_RWPO 0x00000020 /* read-write in priv mode */
#define SH7750_PTEL_PR_ROPU 0x00000040 /* read-only in priv or user mode */
#define SH7750_PTEL_PR_RWPU 0x00000060 /* read-write in priv or user mode */
-#define SH7750_PTEL_C 0x00000008 /* Cacheability
+#define SH7750_PTEL_C 0x00000008 /* Cacheability
(0 - page not cacheable) */
-#define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been
+#define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been
performed to a page) */
#define SH7750_PTEL_SH 0x00000002 /* Share Status bit (1 - page are
shared by processes) */
@@ -130,12 +130,12 @@
#define SH7750_CCR_A7 SH7750_A7_REG32(SH7750_CCR_REGOFS)
#define SH7750_CCR_IIX 0x00008000 /* IC index enable bit */
-#define SH7750_CCR_ICI 0x00000800 /* IC invalidation bit:
+#define SH7750_CCR_ICI 0x00000800 /* IC invalidation bit:
set it to clear IC */
#define SH7750_CCR_ICE 0x00000100 /* IC enable bit */
#define SH7750_CCR_OIX 0x00000080 /* OC index enable bit */
-#define SH7750_CCR_ORA 0x00000020 /* OC RAM enable bit
- if you set OCE = 0,
+#define SH7750_CCR_ORA 0x00000020 /* OC RAM enable bit
+ if you set OCE = 0,
you should set ORA = 0 */
#define SH7750_CCR_OCI 0x00000008 /* OC invalidation bit */
#define SH7750_CCR_CB 0x00000004 /* Copy-back bit for P1 area */
@@ -254,7 +254,7 @@
/* Peripheral Module Interrupts - Memory Refresh Unit (REF) */
#define SH7750_EVT_REF_RCMI 0x580 /* Compare-match Interrupt */
-#define SH7750_EVT_REF_ROVI 0x5A0 /* Refresh Counter Overflow
+#define SH7750_EVT_REF_ROVI 0x5A0 /* Refresh Counter Overflow
interrupt */
/* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */
@@ -331,7 +331,7 @@
#define SH7750_FRQCR SH7750_P4_REG32(SH7750_FRQCR_REGOFS)
#define SH7750_FRQCR_A7 SH7750_A7_REG32(SH7750_FRQCR_REGOFS)
-#define SH7750_FRQCR_CKOEN 0x0800 /* Clock Output Enable
+#define SH7750_FRQCR_CKOEN 0x0800 /* Clock Output Enable
0 - CKIO pin goes to HiZ/pullup
1 - Clock is output from CKIO */
#define SH7750_FRQCR_PLL1EN 0x0400 /* PLL circuit 1 enable */
@@ -643,7 +643,7 @@
#define SH7750_BCR1_BREQEN 0x00080000 /* BREQ Enable:
0 - External requests are not
accepted
- 1 - External requests are
+ 1 - External requests are
accepted */
#define SH7750_BCR1_PSHR 0x00040000 /* Partial Sharing Bit:
0 - Master Mode
@@ -877,7 +877,7 @@
#define SH7750_MCR_TCAS_1 0x00000000 /* 1 */
#define SH7750_MCR_TCAS_2 0x00800000 /* 2 */
-#define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period
+#define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period
SDRAM: minimum number of cycles
until the next bank active cmd
is output after precharging */
@@ -1148,7 +1148,7 @@
#define SH7750_CHCR_DSA_AMEM16 0x0E000000 /* 16-bit attribute memory space */
#define SH7750_CHCR_DTC 0x01000000 /* Destination Address Wait Control
- Select, specifies CS5 or CS6
+ Select, specifies CS5 or CS6
space wait control for PCMCIA
access */
@@ -1186,8 +1186,8 @@
Address Mode (External Addr
Space -> External Device) */
#define SH7750_CHCR_RS_ER_SA_ED_TO_EA 0x300 /* External Request, Single
- Address Mode, (External
- Device -> External Addr
+ Address Mode, (External
+ Device -> External Addr
Space) */
#define SH7750_CHCR_RS_AR_EA_TO_EA 0x400 /* Auto-Request (External Addr
Space -> External Addr Space) */
@@ -1195,7 +1195,7 @@
#define SH7750_CHCR_RS_AR_EA_TO_OCP 0x500 /* Auto-Request (External Addr
Space -> On-chip Peripheral
Module) */
-#define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip
+#define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip
Peripheral Module ->
External Addr Space */
#define SH7750_CHCR_RS_SCITX_EA_TO_SC 0x800 /* SCI Transmit-Data-Empty intr
@@ -1596,7 +1596,7 @@
#define SH7750_IPRC_HUDI_S 0
-/*
+/*
* User Break Controller registers
*/
#define SH7750_BARA 0x200000 /* Break address regiser A */
diff --git a/hw/shix.c b/hw/shix.c
index 000fd6a..e668426 100644
--- a/hw/shix.c
+++ b/hw/shix.c
@@ -1,8 +1,8 @@
/*
* SHIX 2.0 board description
- *
+ *
* Copyright (c) 2005 Samuel Tardieu
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -21,7 +21,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-/*
+/*
Shix 2.0 board by Alexis Polti, described at
http://perso.enst.fr/~polti/realisations/shix20/
diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c
index 993c319..98cac6e 100644
--- a/hw/slavio_intctl.c
+++ b/hw/slavio_intctl.c
@@ -1,8 +1,8 @@
/*
* QEMU Sparc SLAVIO interrupt controller emulation
- *
+ *
* Copyright (c) 2003-2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -40,7 +40,7 @@
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
*
* There is a system master controller and one for each cpu.
- *
+ *
*/
#define MAX_CPUS 16
@@ -308,7 +308,7 @@
{
SLAVIO_INTCTLState *s = opaque;
int i;
-
+
for (i = 0; i < MAX_CPUS; i++) {
qemu_put_be32s(f, &s->intreg_pending[i]);
}
diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c
index e8a4ea4..34072c6 100644
--- a/hw/slavio_misc.c
+++ b/hw/slavio_misc.c
@@ -1,8 +1,8 @@
/*
* QEMU Sparc SLAVIO aux io port emulation
- *
+ *
* Copyright (c) 2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
diff --git a/hw/slavio_serial.c b/hw/slavio_serial.c
index 86e661c..990f5c7 100644
--- a/hw/slavio_serial.c
+++ b/hw/slavio_serial.c
@@ -1,8 +1,8 @@
/*
* QEMU Sparc SLAVIO serial port emulation
- *
+ *
* Copyright (c) 2003-2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -35,7 +35,7 @@
* This is the serial port, mouse and keyboard part of chip STP2001
* (Slave I/O), also produced as NCR89C105. See
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
- *
+ *
* The serial ports implement full AMD AM8530 or Zilog Z8530 chips,
* mouse and keyboard ports don't implement all functions and they are
* only asynchronous. There is no DMA.
@@ -136,7 +136,7 @@
ChannelState *s = opaque;
SERIOQueue *q = &s->queue;
int val;
-
+
if (q->count == 0) {
return 0;
} else {
@@ -662,7 +662,7 @@
}
}
-static void sunmouse_event(void *opaque,
+static void sunmouse_event(void *opaque,
int dx, int dy, int dz, int buttons_state)
{
ChannelState *s = opaque;
diff --git a/hw/slavio_timer.c b/hw/slavio_timer.c
index 2ade177..c9a3a56 100644
--- a/hw/slavio_timer.c
+++ b/hw/slavio_timer.c
@@ -2,7 +2,7 @@
* QEMU Sparc SLAVIO timer controller emulation
*
* Copyright (c) 2003-2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -38,7 +38,7 @@
* This is the timer/counter part of chip STP2001 (Slave I/O), also
* produced as NCR89C105. See
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
- *
+ *
* The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
* are zero. Bit 31 is 1 when count has been reached.
*
@@ -210,7 +210,7 @@
{
SLAVIO_TIMERState *s = opaque;
uint32_t tmp;
-
+
if (version_id != 2)
return -EINVAL;
diff --git a/hw/smbus.c b/hw/smbus.c
index 5189d51..103e917 100644
--- a/hw/smbus.c
+++ b/hw/smbus.c
@@ -1,4 +1,4 @@
-/*
+/*
* QEMU SMBus device emulation.
*
* Copyright (c) 2007 CodeSourcery.
diff --git a/hw/smbus.h b/hw/smbus.h
index 3697773..0d35bb6 100644
--- a/hw/smbus.h
+++ b/hw/smbus.h
@@ -1,8 +1,8 @@
/*
* QEMU SMBus API
- *
+ *
* Copyright (c) 2007 Arastra, Inc.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
diff --git a/hw/smbus_eeprom.c b/hw/smbus_eeprom.c
index 699bd54..5b8637d 100644
--- a/hw/smbus_eeprom.c
+++ b/hw/smbus_eeprom.c
@@ -1,8 +1,8 @@
/*
* QEMU SMBus EEPROM device
- *
+ *
* Copyright (c) 2007 Arastra, Inc.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -94,7 +94,7 @@
void smbus_eeprom_device_init(i2c_bus *bus, uint8_t addr, uint8_t *buf)
{
SMBusEEPROMDevice *eeprom;
-
+
eeprom = (SMBusEEPROMDevice *)smbus_device_init(bus, addr,
sizeof(SMBusEEPROMDevice));
diff --git a/hw/smc91c111.c b/hw/smc91c111.c
index d90ab32..a6a11e0 100644
--- a/hw/smc91c111.c
+++ b/hw/smc91c111.c
@@ -1,4 +1,4 @@
-/*
+/*
* SMSC 91C111 Ethernet interface emulation
*
* Copyright (c) 2005 CodeSourcery, LLC.
@@ -649,7 +649,7 @@
/* Pad short packets. */
if (size < 64) {
int pad;
-
+
if (size & 1)
*(p++) = buf[size - 1];
pad = 64 - size;
diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c
index d2fe576..3c80fd6 100644
--- a/hw/sparc32_dma.c
+++ b/hw/sparc32_dma.c
@@ -63,7 +63,7 @@
};
/* Note: on sparc, the lance 16 bit bus is swapped */
-void ledma_memory_read(void *opaque, target_phys_addr_t addr,
+void ledma_memory_read(void *opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int do_bswap)
{
DMAState *s = opaque;
@@ -84,7 +84,7 @@
}
}
-void ledma_memory_write(void *opaque, target_phys_addr_t addr,
+void ledma_memory_write(void *opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int do_bswap)
{
DMAState *s = opaque;
diff --git a/hw/sun4m.c b/hw/sun4m.c
index dba6f38..4da4138 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -1,8 +1,8 @@
/*
* QEMU Sun4m System Emulator
- *
+ *
* Copyright (c) 2003-2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -425,14 +425,14 @@
linux_boot = (kernel_filename != NULL);
prom_offset = RAM_size + vram_size;
- cpu_register_physical_memory(PROM_ADDR,
- (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK,
+ cpu_register_physical_memory(PROM_ADDR,
+ (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK,
prom_offset | IO_MEM_ROM);
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
ret = load_elf(buf, 0, NULL, NULL, NULL);
if (ret < 0) {
- fprintf(stderr, "qemu: could not load prom '%s'\n",
+ fprintf(stderr, "qemu: could not load prom '%s'\n",
buf);
exit(1);
}
@@ -445,7 +445,7 @@
if (kernel_size < 0)
kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
if (kernel_size < 0) {
- fprintf(stderr, "qemu: could not load kernel '%s'\n",
+ fprintf(stderr, "qemu: could not load kernel '%s'\n",
kernel_filename);
exit(1);
}
@@ -455,7 +455,7 @@
if (initrd_filename) {
initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
if (initrd_size < 0) {
- fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
+ fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
initrd_filename);
exit(1);
}
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 4be94fa..0e9e72e 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -1,8 +1,8 @@
/*
* QEMU Sun4u System Emulator
- *
+ *
* Copyright (c) 2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -378,14 +378,14 @@
cpu_register_physical_memory(0, ram_size, 0);
prom_offset = ram_size + vga_ram_size;
- cpu_register_physical_memory(PROM_ADDR,
- (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
+ cpu_register_physical_memory(PROM_ADDR,
+ (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
prom_offset | IO_MEM_ROM);
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
if (ret < 0) {
- fprintf(stderr, "qemu: could not load prom '%s'\n",
+ fprintf(stderr, "qemu: could not load prom '%s'\n",
buf);
exit(1);
}
@@ -400,7 +400,7 @@
if (kernel_size < 0)
kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
if (kernel_size < 0) {
- fprintf(stderr, "qemu: could not load kernel '%s'\n",
+ fprintf(stderr, "qemu: could not load kernel '%s'\n",
kernel_filename);
exit(1);
}
@@ -409,7 +409,7 @@
if (initrd_filename) {
initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
if (initrd_size < 0) {
- fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
+ fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
initrd_filename);
exit(1);
}
diff --git a/hw/tcx.c b/hw/tcx.c
index c334f09..72c9bcd 100644
--- a/hw/tcx.c
+++ b/hw/tcx.c
@@ -1,8 +1,8 @@
/*
* QEMU TCX Frame buffer
- *
+ *
* Copyright (c) 2003-2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -83,7 +83,7 @@
tcx_invalidate_display(s);
}
-static void tcx_draw_line32(TCXState *s1, uint8_t *d,
+static void tcx_draw_line32(TCXState *s1, uint8_t *d,
const uint8_t *s, int width)
{
int x;
@@ -96,7 +96,7 @@
}
}
-static void tcx_draw_line16(TCXState *s1, uint8_t *d,
+static void tcx_draw_line16(TCXState *s1, uint8_t *d,
const uint8_t *s, int width)
{
int x;
@@ -109,7 +109,7 @@
}
}
-static void tcx_draw_line8(TCXState *s1, uint8_t *d,
+static void tcx_draw_line8(TCXState *s1, uint8_t *d,
const uint8_t *s, int width)
{
int x;
@@ -208,7 +208,7 @@
case 0:
return;
}
-
+
for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
if (y_start < 0)
@@ -232,7 +232,7 @@
} else {
if (y_start >= 0) {
/* flush to display */
- dpy_update(ts->ds, 0, y_start,
+ dpy_update(ts->ds, 0, y_start,
ts->width, y - y_start);
y_start = -1;
}
@@ -242,7 +242,7 @@
}
if (y_start >= 0) {
/* flush to display */
- dpy_update(ts->ds, 0, y_start,
+ dpy_update(ts->ds, 0, y_start,
ts->width, y - y_start);
}
/* reset modified pages */
@@ -353,7 +353,7 @@
static void tcx_save(QEMUFile *f, void *opaque)
{
TCXState *s = opaque;
-
+
qemu_put_be16s(f, (uint16_t *)&s->height);
qemu_put_be16s(f, (uint16_t *)&s->width);
qemu_put_be16s(f, (uint16_t *)&s->depth);
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index f32d195..8728f11 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -2,7 +2,7 @@
* QEMU Uninorth PCI host (for all Mac99 and newer machines)
*
* Copyright (c) 2006 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -163,13 +163,13 @@
s->bus = pci_register_bus(pci_unin_set_irq, pci_unin_map_irq,
pic, 11 << 3, 4);
- pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
+ pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
pci_unin_main_config_write, s);
pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
pci_unin_main_write, s);
cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
- d = pci_register_device(s->bus, "Uni-north main", sizeof(PCIDevice),
+ d = pci_register_device(s->bus, "Uni-north main", sizeof(PCIDevice),
11 << 3, NULL, NULL);
d->config[0x00] = 0x6b; // vendor_id : Apple
d->config[0x01] = 0x10;
@@ -217,7 +217,7 @@
#if 0 // XXX: not needed for now
/* Uninorth AGP bus */
s = &pci_bridge[1];
- pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
+ pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
pci_unin_config_write, s);
pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
pci_unin_write, s);
@@ -242,7 +242,7 @@
#if 0 // XXX: not needed for now
/* Uninorth internal bus */
s = &pci_bridge[2];
- pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
+ pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
pci_unin_config_write, s);
pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
pci_unin_write, s);
diff --git a/hw/usb-hid.c b/hw/usb-hid.c
index f119735..e3b94d0 100644
--- a/hw/usb-hid.c
+++ b/hw/usb-hid.c
@@ -1,9 +1,9 @@
/*
* QEMU USB HID devices
- *
+ *
* Copyright (c) 2005 Fabrice Bellard
* Copyright (c) 2007 OpenMoko, Inc. ([email protected])
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -96,13 +96,13 @@
0x01, /* u8 bNumInterfaces; (1) */
0x01, /* u8 bConfigurationValue; */
0x04, /* u8 iConfiguration; */
- 0xa0, /* u8 bmAttributes;
+ 0xa0, /* u8 bmAttributes;
Bit 7: must be set,
6: Self-powered,
5: Remote wakeup,
4..0: resvd */
50, /* u8 MaxPower; */
-
+
/* USB 1.1:
* USB 2.0, single TT organization (mandatory):
* one interface, protocol 0
@@ -124,7 +124,7 @@
0x01, /* u8 if_bInterfaceSubClass; */
0x02, /* u8 if_bInterfaceProtocol; [usb1.1 or single tt] */
0x07, /* u8 if_iInterface; */
-
+
/* HID descriptor */
0x09, /* u8 bLength; */
0x21, /* u8 bDescriptorType; */
@@ -151,13 +151,13 @@
0x01, /* u8 bNumInterfaces; (1) */
0x01, /* u8 bConfigurationValue; */
0x05, /* u8 iConfiguration; */
- 0xa0, /* u8 bmAttributes;
+ 0xa0, /* u8 bmAttributes;
Bit 7: must be set,
6: Self-powered,
5: Remote wakeup,
4..0: resvd */
50, /* u8 MaxPower; */
-
+
/* USB 1.1:
* USB 2.0, single TT organization (mandatory):
* one interface, protocol 0
@@ -206,7 +206,7 @@
0x01, /* u8 bNumInterfaces; (1) */
0x01, /* u8 bConfigurationValue; */
0x06, /* u8 iConfiguration; */
- 0xa0, /* u8 bmAttributes;
+ 0xa0, /* u8 bmAttributes;
Bit 7: must be set,
6: Self-powered,
5: Remote wakeup,
@@ -254,11 +254,11 @@
};
static const uint8_t qemu_mouse_hid_report_descriptor[] = {
- 0x05, 0x01, 0x09, 0x02, 0xA1, 0x01, 0x09, 0x01,
+ 0x05, 0x01, 0x09, 0x02, 0xA1, 0x01, 0x09, 0x01,
0xA1, 0x00, 0x05, 0x09, 0x19, 0x01, 0x29, 0x03,
- 0x15, 0x00, 0x25, 0x01, 0x95, 0x03, 0x75, 0x01,
+ 0x15, 0x00, 0x25, 0x01, 0x95, 0x03, 0x75, 0x01,
0x81, 0x02, 0x95, 0x01, 0x75, 0x05, 0x81, 0x01,
- 0x05, 0x01, 0x09, 0x30, 0x09, 0x31, 0x15, 0x81,
+ 0x05, 0x01, 0x09, 0x30, 0x09, 0x31, 0x15, 0x81,
0x25, 0x7F, 0x75, 0x08, 0x95, 0x02, 0x81, 0x06,
0xC0, 0xC0,
};
@@ -474,7 +474,7 @@
0, "QEMU USB Mouse");
s->mouse_grabbed = 1;
}
-
+
dx = int_clamp(s->dx, -128, 127);
dy = int_clamp(s->dy, -128, 127);
dz = int_clamp(s->dz, -128, 127);
@@ -482,7 +482,7 @@
s->dx -= dx;
s->dy -= dy;
s->dz -= dz;
-
+
b = 0;
if (s->buttons_state & MOUSE_EVENT_LBUTTON)
b |= 0x01;
@@ -490,7 +490,7 @@
b |= 0x02;
if (s->buttons_state & MOUSE_EVENT_MBUTTON)
b |= 0x04;
-
+
buf[0] = b;
buf[1] = dx;
buf[2] = dy;
@@ -512,7 +512,7 @@
1, "QEMU USB Tablet");
s->mouse_grabbed = 1;
}
-
+
dz = int_clamp(s->dz, -128, 127);
s->dz -= dz;
@@ -622,21 +622,21 @@
case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
switch(value >> 8) {
case USB_DT_DEVICE:
- memcpy(data, qemu_mouse_dev_descriptor,
+ memcpy(data, qemu_mouse_dev_descriptor,
sizeof(qemu_mouse_dev_descriptor));
ret = sizeof(qemu_mouse_dev_descriptor);
break;
case USB_DT_CONFIG:
if (s->kind == USB_MOUSE) {
- memcpy(data, qemu_mouse_config_descriptor,
+ memcpy(data, qemu_mouse_config_descriptor,
sizeof(qemu_mouse_config_descriptor));
ret = sizeof(qemu_mouse_config_descriptor);
} else if (s->kind == USB_TABLET) {
- memcpy(data, qemu_tablet_config_descriptor,
+ memcpy(data, qemu_tablet_config_descriptor,
sizeof(qemu_tablet_config_descriptor));
ret = sizeof(qemu_tablet_config_descriptor);
} else if (s->kind == USB_KEYBOARD) {
- memcpy(data, qemu_keyboard_config_descriptor,
+ memcpy(data, qemu_keyboard_config_descriptor,
sizeof(qemu_keyboard_config_descriptor));
ret = sizeof(qemu_keyboard_config_descriptor);
}
@@ -702,15 +702,15 @@
switch(value >> 8) {
case 0x22:
if (s->kind == USB_MOUSE) {
- memcpy(data, qemu_mouse_hid_report_descriptor,
+ memcpy(data, qemu_mouse_hid_report_descriptor,
sizeof(qemu_mouse_hid_report_descriptor));
ret = sizeof(qemu_mouse_hid_report_descriptor);
} else if (s->kind == USB_TABLET) {
- memcpy(data, qemu_tablet_hid_report_descriptor,
+ memcpy(data, qemu_tablet_hid_report_descriptor,
sizeof(qemu_tablet_hid_report_descriptor));
ret = sizeof(qemu_tablet_hid_report_descriptor);
} else if (s->kind == USB_KEYBOARD) {
- memcpy(data, qemu_keyboard_hid_report_descriptor,
+ memcpy(data, qemu_keyboard_hid_report_descriptor,
sizeof(qemu_keyboard_hid_report_descriptor));
ret = sizeof(qemu_keyboard_hid_report_descriptor);
}
diff --git a/hw/usb-hub.c b/hw/usb-hub.c
index 651dac2..bfdd5f9 100644
--- a/hw/usb-hub.c
+++ b/hw/usb-hub.c
@@ -2,7 +2,7 @@
* QEMU USB HUB emulation
*
* Copyright (c) 2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -112,13 +112,13 @@
0x01, /* u8 bNumInterfaces; (1) */
0x01, /* u8 bConfigurationValue; */
0x00, /* u8 iConfiguration; */
- 0xc0, /* u8 bmAttributes;
+ 0xc0, /* u8 bmAttributes;
Bit 7: must be set,
6: Self-powered,
5: Remote wakeup,
4..0: resvd */
0x00, /* u8 MaxPower; */
-
+
/* USB 1.1:
* USB 2.0, single TT organization (mandatory):
* one interface, protocol 0
@@ -140,7 +140,7 @@
0x00, /* u8 if_bInterfaceSubClass; */
0x00, /* u8 if_bInterfaceProtocol; [usb1.1 or single tt] */
0x00, /* u8 if_iInterface; */
-
+
/* one endpoint (status change endpoint) */
0x07, /* u8 ep_bLength; */
0x05, /* u8 ep_bDescriptorType; Endpoint */
@@ -167,11 +167,11 @@
{
USBHubState *s = port1->opaque;
USBHubPort *port = &s->ports[port1->index];
-
+
if (dev) {
if (port->port.dev)
usb_attach(port1, NULL);
-
+
port->wPortStatus |= PORT_STAT_CONNECTION;
port->wPortChange |= PORT_STAT_C_CONNECTION;
if (dev->speed == USB_SPEED_LOW)
@@ -244,12 +244,12 @@
case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
switch(value >> 8) {
case USB_DT_DEVICE:
- memcpy(data, qemu_hub_dev_descriptor,
+ memcpy(data, qemu_hub_dev_descriptor,
sizeof(qemu_hub_dev_descriptor));
ret = sizeof(qemu_hub_dev_descriptor);
break;
case USB_DT_CONFIG:
- memcpy(data, qemu_hub_config_descriptor,
+ memcpy(data, qemu_hub_config_descriptor,
sizeof(qemu_hub_config_descriptor));
/* status change endpoint size based on number
@@ -401,7 +401,7 @@
case GetHubDescriptor:
{
unsigned int n, limit, var_hub_size = 0;
- memcpy(data, qemu_hub_hub_descriptor,
+ memcpy(data, qemu_hub_hub_descriptor,
sizeof(qemu_hub_hub_descriptor));
data[2] = s->nb_ports;
@@ -504,8 +504,8 @@
if (dev->state == USB_STATE_DEFAULT &&
dev->addr != 0 &&
p->devaddr != dev->addr &&
- (p->pid == USB_TOKEN_SETUP ||
- p->pid == USB_TOKEN_OUT ||
+ (p->pid == USB_TOKEN_SETUP ||
+ p->pid == USB_TOKEN_OUT ||
p->pid == USB_TOKEN_IN)) {
/* broadcast the packet to the devices */
return usb_hub_broadcast_packet(s, p);
diff --git a/hw/usb-msd.c b/hw/usb-msd.c
index 08fc5c3..f428916 100644
--- a/hw/usb-msd.c
+++ b/hw/usb-msd.c
@@ -1,4 +1,4 @@
-/*
+/*
* USB Mass Storage Device emulation
*
* Copyright (c) 2006 CodeSourcery.
@@ -93,13 +93,13 @@
0x01, /* u8 bNumInterfaces; (1) */
0x01, /* u8 bConfigurationValue; */
0x00, /* u8 iConfiguration; */
- 0xc0, /* u8 bmAttributes;
+ 0xc0, /* u8 bmAttributes;
Bit 7: must be set,
6: Self-powered,
5: Remote wakeup,
4..0: resvd */
0x00, /* u8 MaxPower; */
-
+
/* one interface */
0x09, /* u8 if_bLength; */
0x04, /* u8 if_bDescriptorType; Interface */
@@ -110,7 +110,7 @@
0x06, /* u8 if_bInterfaceSubClass; SCSI */
0x50, /* u8 if_bInterfaceProtocol; Bulk Only */
0x00, /* u8 if_iInterface; */
-
+
/* Bulk-In endpoint */
0x07, /* u8 ep_bLength; */
0x05, /* u8 ep_bDescriptorType; Endpoint */
@@ -259,12 +259,12 @@
case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
switch(value >> 8) {
case USB_DT_DEVICE:
- memcpy(data, qemu_msd_dev_descriptor,
+ memcpy(data, qemu_msd_dev_descriptor,
sizeof(qemu_msd_dev_descriptor));
ret = sizeof(qemu_msd_dev_descriptor);
break;
case USB_DT_CONFIG:
- memcpy(data, qemu_msd_config_descriptor,
+ memcpy(data, qemu_msd_config_descriptor,
sizeof(qemu_msd_config_descriptor));
ret = sizeof(qemu_msd_config_descriptor);
break;
diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c
index f4f2608..cd04ad1 100644
--- a/hw/usb-uhci.c
+++ b/hw/usb-uhci.c
@@ -1,8 +1,8 @@
/*
* USB UHCI controller emulation
- *
+ *
* Copyright (c) 2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -84,7 +84,7 @@
/* For simplicity of implementation we only allow a single pending USB
request. This means all usb traffic on this controller is effectively
suspended until that transfer completes. When the transfer completes
- the next transfer from that queue will be processed. However
+ the next transfer from that queue will be processed. However
other queues will not be processed until the next frame. The solution
is to allow multiple pending requests. */
uint32_t async_qh;
@@ -149,7 +149,7 @@
static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
{
UHCIState *s = opaque;
-
+
addr &= 0x1f;
switch(addr) {
case 0x0c:
@@ -178,7 +178,7 @@
static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
{
UHCIState *s = opaque;
-
+
addr &= 0x1f;
#ifdef DEBUG
printf("uhci writew port=0x%04x val=0x%04x\n", addr, val);
@@ -243,7 +243,7 @@
dev = port->port.dev;
if (dev) {
/* port reset */
- if ( (val & UHCI_PORT_RESET) &&
+ if ( (val & UHCI_PORT_RESET) &&
!(port->ctrl & UHCI_PORT_RESET) ) {
usb_send_msg(dev, USB_MSG_RESET);
}
@@ -280,7 +280,7 @@
UHCIPort *port;
int n;
n = (addr >> 1) & 7;
- if (n >= NB_PORTS)
+ if (n >= NB_PORTS)
goto read_default;
port = &s->ports[n];
val = port->ctrl;
@@ -458,7 +458,7 @@
if (td->ctrl & TD_CTRL_IOC) {
*int_mask |= 0x01;
}
-
+
if (!(td->ctrl & TD_CTRL_ACTIVE))
return 1;
@@ -530,7 +530,7 @@
here. The docs are somewhat unclear, but win2k relies on this
behavior. */
td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
- if (pid == USB_TOKEN_IN &&
+ if (pid == USB_TOKEN_IN &&
(td->ctrl & TD_CTRL_SPD) &&
len < max_len) {
*int_mask |= 0x02;
@@ -555,7 +555,7 @@
uhci_update_irq(s);
}
}
- td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
+ td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
(err << TD_CTRL_ERROR_SHIFT);
return 1;
case USB_RET_NAK:
@@ -597,7 +597,7 @@
le32_to_cpus(&qh.el_link);
/* Re-process the queue containing the async packet. */
while (1) {
- cpu_physical_memory_read(qh.el_link & ~0xf,
+ cpu_physical_memory_read(qh.el_link & ~0xf,
(uint8_t *)&td, sizeof(td));
le32_to_cpus(&td.link);
le32_to_cpus(&td.ctrl);
@@ -608,8 +608,8 @@
/* update the status bits of the TD */
if (old_td_ctrl != td.ctrl) {
val = cpu_to_le32(td.ctrl);
- cpu_physical_memory_write((qh.el_link & ~0xf) + 4,
- (const uint8_t *)&val,
+ cpu_physical_memory_write((qh.el_link & ~0xf) + 4,
+ (const uint8_t *)&val,
sizeof(val));
}
if (ret < 0)
@@ -621,8 +621,8 @@
/* update qh element link */
qh.el_link = td.link;
val = cpu_to_le32(qh.el_link);
- cpu_physical_memory_write((link & ~0xf) + 4,
- (const uint8_t *)&val,
+ cpu_physical_memory_write((link & ~0xf) + 4,
+ (const uint8_t *)&val,
sizeof(val));
if (!(qh.el_link & 4))
break;
@@ -690,7 +690,7 @@
/* TD */
if (--cnt == 0)
break;
- cpu_physical_memory_read(qh.el_link & ~0xf,
+ cpu_physical_memory_read(qh.el_link & ~0xf,
(uint8_t *)&td, sizeof(td));
le32_to_cpus(&td.link);
le32_to_cpus(&td.ctrl);
@@ -701,8 +701,8 @@
/* update the status bits of the TD */
if (old_td_ctrl != td.ctrl) {
val = cpu_to_le32(td.ctrl);
- cpu_physical_memory_write((qh.el_link & ~0xf) + 4,
- (const uint8_t *)&val,
+ cpu_physical_memory_write((qh.el_link & ~0xf) + 4,
+ (const uint8_t *)&val,
sizeof(val));
}
if (ret < 0)
@@ -713,8 +713,8 @@
/* update qh element link */
qh.el_link = td.link;
val = cpu_to_le32(qh.el_link);
- cpu_physical_memory_write((link & ~0xf) + 4,
- (const uint8_t *)&val,
+ cpu_physical_memory_write((link & ~0xf) + 4,
+ (const uint8_t *)&val,
sizeof(val));
if (qh.el_link & 4) {
/* depth first */
@@ -740,8 +740,8 @@
/* update the status bits of the TD */
if (old_td_ctrl != td.ctrl) {
val = cpu_to_le32(td.ctrl);
- cpu_physical_memory_write((link & ~0xf) + 4,
- (const uint8_t *)&val,
+ cpu_physical_memory_write((link & ~0xf) + 4,
+ (const uint8_t *)&val,
sizeof(val));
}
if (ret < 0)
@@ -768,12 +768,12 @@
s->async_qh = 0;
}
/* prepare the timer for the next frame */
- expire_time = qemu_get_clock(vm_clock) +
+ expire_time = qemu_get_clock(vm_clock) +
(ticks_per_sec / FRAME_TIMER_FREQ);
qemu_mod_timer(s->frame_timer, expire_time);
}
-static void uhci_map(PCIDevice *pci_dev, int region_num,
+static void uhci_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
UHCIState *s = (UHCIState *)pci_dev;
@@ -807,7 +807,7 @@
pci_conf[0x0e] = 0x00; // header_type
pci_conf[0x3d] = 4; // interrupt pin 3
pci_conf[0x60] = 0x10; // release number
-
+
for(i = 0; i < NB_PORTS; i++) {
qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach);
}
@@ -817,7 +817,7 @@
/* Use region 4 for consistency with real hardware. BSD guests seem
to rely on this. */
- pci_register_io_region(&s->dev, 4, 0x20,
+ pci_register_io_region(&s->dev, 4, 0x20,
PCI_ADDRESS_SPACE_IO, uhci_map);
}
diff --git a/hw/usb-wacom.c b/hw/usb-wacom.c
index 0acafaa..99b8f9e 100644
--- a/hw/usb-wacom.c
+++ b/hw/usb-wacom.c
@@ -78,7 +78,7 @@
0x01, /* u8 bNumInterfaces; (1) */
0x01, /* u8 bConfigurationValue; */
0x00, /* u8 iConfiguration; */
- 0x80, /* u8 bmAttributes;
+ 0x80, /* u8 bmAttributes;
Bit 7: must be set,
6: Self-powered,
5: Remote wakeup,
@@ -272,12 +272,12 @@
case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
switch (value >> 8) {
case USB_DT_DEVICE:
- memcpy(data, qemu_wacom_dev_descriptor,
+ memcpy(data, qemu_wacom_dev_descriptor,
sizeof(qemu_wacom_dev_descriptor));
ret = sizeof(qemu_wacom_dev_descriptor);
break;
case USB_DT_CONFIG:
- memcpy(data, qemu_wacom_config_descriptor,
+ memcpy(data, qemu_wacom_config_descriptor,
sizeof(qemu_wacom_config_descriptor));
ret = sizeof(qemu_wacom_config_descriptor);
break;
diff --git a/hw/usb.c b/hw/usb.c
index 17cb8df..75e5a80 100644
--- a/hw/usb.c
+++ b/hw/usb.c
@@ -2,7 +2,7 @@
* QEMU USB emulation
*
* Copyright (c) 2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -31,7 +31,7 @@
/**********************/
/* generic USB device helpers (you are not forced to use them when
writing your USB device driver, but they help handling the
- protocol)
+ protocol)
*/
#define SETUP_STATE_IDLE 0
@@ -66,7 +66,7 @@
s->setup_len = (s->setup_buf[7] << 8) | s->setup_buf[6];
s->setup_index = 0;
if (s->setup_buf[0] & USB_DIR_IN) {
- ret = s->handle_control(s,
+ ret = s->handle_control(s,
(s->setup_buf[0] << 8) | s->setup_buf[1],
(s->setup_buf[3] << 8) | s->setup_buf[2],
(s->setup_buf[5] << 8) | s->setup_buf[4],
@@ -93,7 +93,7 @@
case SETUP_STATE_ACK:
if (!(s->setup_buf[0] & USB_DIR_IN)) {
s->setup_state = SETUP_STATE_IDLE;
- ret = s->handle_control(s,
+ ret = s->handle_control(s,
(s->setup_buf[0] << 8) | s->setup_buf[1],
(s->setup_buf[3] << 8) | s->setup_buf[2],
(s->setup_buf[5] << 8) | s->setup_buf[4],
diff --git a/hw/usb.h b/hw/usb.h
index 868118a..17832cf 100644
--- a/hw/usb.h
+++ b/hw/usb.h
@@ -1,8 +1,8 @@
/*
* QEMU USB API
- *
+ *
* Copyright (c) 2005 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -30,7 +30,7 @@
#define USB_MSG_DETACH 0x101
#define USB_MSG_RESET 0x102
-#define USB_RET_NODEV (-1)
+#define USB_RET_NODEV (-1)
#define USB_RET_NAK (-2)
#define USB_RET_STALL (-3)
#define USB_RET_BABBLE (-4)
@@ -119,7 +119,7 @@
void (*handle_destroy)(USBDevice *dev);
int speed;
-
+
/* The following fields are used by the generic USB device
layer. They are here just to avoid creating a new structure for
them. */
@@ -129,7 +129,7 @@
int (*handle_data)(USBDevice *dev, USBPacket *p);
uint8_t addr;
char devname[32];
-
+
int state;
uint8_t setup_buf[8];
uint8_t data_buf[1024];
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index 98a2f4f..68f18ef 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -1,4 +1,4 @@
-/*
+/*
* ARM Versatile/PB PCI host controller
*
* Copyright (c) 2006 CodeSourcery.
diff --git a/hw/versatilepb.c b/hw/versatilepb.c
index f0142ad..2e3dedd 100644
--- a/hw/versatilepb.c
+++ b/hw/versatilepb.c
@@ -1,4 +1,4 @@
-/*
+/*
* ARM Versatile Platform/Application Baseboard System emulation.
*
* Copyright (c) 2005-2007 CodeSourcery.
diff --git a/hw/vga.c b/hw/vga.c
index b2c6bc8..de74764 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -1,8 +1,8 @@
/*
* QEMU VGA Emulator.
- *
+ *
* Copyright (c) 2003 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -166,7 +166,7 @@
break;
case 0x3c1:
index = s->ar_index & 0x1f;
- if (index < 21)
+ if (index < 21)
val = s->ar[index];
else
val = 0;
@@ -390,11 +390,11 @@
val = VBE_DISPI_MAX_BPP;
break;
default:
- val = s->vbe_regs[s->vbe_index];
+ val = s->vbe_regs[s->vbe_index];
break;
}
} else {
- val = s->vbe_regs[s->vbe_index];
+ val = s->vbe_regs[s->vbe_index];
}
} else {
val = 0;
@@ -442,7 +442,7 @@
case VBE_DISPI_INDEX_BPP:
if (val == 0)
val = 8;
- if (val == 4 || val == 8 || val == 15 ||
+ if (val == 4 || val == 8 || val == 15 ||
val == 16 || val == 24 || val == 32) {
s->vbe_regs[s->vbe_index] = val;
}
@@ -461,26 +461,26 @@
!(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
int h, shift_control;
- s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
+ s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
s->vbe_regs[VBE_DISPI_INDEX_XRES];
- s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
+ s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
s->vbe_regs[VBE_DISPI_INDEX_YRES];
s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
-
+
if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
else
- s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
+ s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
s->vbe_start_addr = 0;
/* clear the screen (should be done in BIOS) */
if (!(val & VBE_DISPI_NOCLEARMEM)) {
- memset(s->vram_ptr, 0,
+ memset(s->vram_ptr, 0,
s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
}
-
+
/* we initialize the VGA graphic mode (should be done
in BIOS) */
s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
@@ -491,13 +491,13 @@
/* height (only meaningful if < 1024) */
h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
s->cr[0x12] = h;
- s->cr[0x07] = (s->cr[0x07] & ~0x42) |
+ s->cr[0x07] = (s->cr[0x07] & ~0x42) |
((h >> 7) & 0x02) | ((h >> 3) & 0x40);
/* line compare to 1023 */
s->cr[0x18] = 0xff;
s->cr[0x07] |= 0x10;
s->cr[0x09] |= 0x40;
-
+
if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
shift_control = 0;
s->sr[0x01] &= ~8; /* no double line */
@@ -562,7 +562,7 @@
VGAState *s = opaque;
int memory_map_mode, plane;
uint32_t ret;
-
+
/* convert to VGA memory offset */
memory_map_mode = (s->gr[6] >> 2) & 3;
addr &= 0x1ffff;
@@ -586,7 +586,7 @@
return 0xff;
break;
}
-
+
if (s->sr[4] & 0x08) {
/* chain 4 mode : simplest access */
ret = s->vram_ptr[addr];
@@ -676,7 +676,7 @@
return;
break;
}
-
+
if (s->sr[4] & 0x08) {
/* chain 4 mode : simplest access */
plane = addr & 3;
@@ -767,11 +767,11 @@
mask = s->sr[2];
s->plane_updated |= mask; /* only used to detect font change */
write_mask = mask16[mask];
- ((uint32_t *)s->vram_ptr)[addr] =
- (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
+ ((uint32_t *)s->vram_ptr)[addr] =
+ (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
(val & write_mask);
#ifdef DEBUG_VGA_MEM
- printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
+ printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
addr * 4, write_mask, val);
#endif
cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
@@ -808,9 +808,9 @@
const uint8_t *font_ptr, int h,
uint32_t fgcol, uint32_t bgcol);
typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
- const uint8_t *font_ptr, int h,
+ const uint8_t *font_ptr, int h,
uint32_t fgcol, uint32_t bgcol, int dup9);
-typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
+typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
const uint8_t *s, int width);
#define DEPTH 8
@@ -909,8 +909,8 @@
else
v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
v = v * 3;
- col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
- c6_to_8(s->palette[v + 1]),
+ col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
+ c6_to_8(s->palette[v + 1]),
c6_to_8(s->palette[v + 2]));
if (col != palette[i]) {
full_update = 1;
@@ -931,12 +931,12 @@
v = 0;
for(i = 0; i < 256; i++) {
if (s->dac_8bit) {
- col = s->rgb_to_pixel(s->palette[v],
- s->palette[v + 1],
+ col = s->rgb_to_pixel(s->palette[v],
+ s->palette[v + 1],
s->palette[v + 2]);
} else {
- col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
- c6_to_8(s->palette[v + 1]),
+ col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
+ c6_to_8(s->palette[v + 1]),
c6_to_8(s->palette[v + 2]));
}
if (col != palette[i]) {
@@ -948,8 +948,8 @@
return full_update;
}
-static void vga_get_offsets(VGAState *s,
- uint32_t *pline_offset,
+static void vga_get_offsets(VGAState *s,
+ uint32_t *pline_offset,
uint32_t *pstart_addr,
uint32_t *pline_compare)
{
@@ -961,7 +961,7 @@
line_compare = 65535;
} else
#endif
- {
+ {
/* compute line_offset in bytes */
line_offset = s->cr[0x13];
line_offset <<= 3;
@@ -970,7 +970,7 @@
start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
/* line compare */
- line_compare = s->cr[0x18] |
+ line_compare = s->cr[0x18] |
((s->cr[0x07] & 0x10) << 4) |
((s->cr[0x09] & 0x40) << 3);
}
@@ -984,7 +984,7 @@
{
int full_update;
uint32_t start_addr, line_offset, line_compare;
-
+
full_update = 0;
s->get_offsets(s, &line_offset, &start_addr, &line_compare);
@@ -1055,7 +1055,7 @@
vga_draw_glyph9_16,
vga_draw_glyph9_16,
};
-
+
static const uint8_t cursor_glyph[32 * 4] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
@@ -1073,13 +1073,13 @@
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-};
+};
-/*
- * Text mode update
+/*
+ * Text mode update
* Missing:
* - double scan
- * - double width
+ * - double width
* - underline
* - flashing
*/
@@ -1098,7 +1098,7 @@
full_update |= update_palette16(s);
palette = s->last_palette;
-
+
/* compute font data address (in plane 2) */
v = s->sr[3];
offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
@@ -1138,8 +1138,8 @@
/* ugly hack for CGA 160x100x16 - explain me the logic */
height = 100;
} else {
- height = s->cr[0x12] |
- ((s->cr[0x07] & 0x02) << 7) |
+ height = s->cr[0x12] |
+ ((s->cr[0x07] & 0x02) << 7) |
((s->cr[0x07] & 0x40) << 3);
height = (height + 1) / cheight;
}
@@ -1174,14 +1174,14 @@
s->cursor_end = s->cr[0xb];
}
cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
-
+
depth_index = get_depth_index(s->ds);
if (cw == 16)
vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
else
vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
-
+
dest = s->ds->data;
linesize = s->ds->linesize;
ch_attr_ptr = s->last_ch_attr;
@@ -1210,13 +1210,13 @@
bgcol = palette[cattr >> 4];
fgcol = palette[cattr & 0x0f];
if (cw != 9) {
- vga_draw_glyph8(d1, linesize,
+ vga_draw_glyph8(d1, linesize,
font_ptr, cheight, fgcol, bgcol);
} else {
dup9 = 0;
if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
dup9 = 1;
- vga_draw_glyph9(d1, linesize,
+ vga_draw_glyph9(d1, linesize,
font_ptr, cheight, fgcol, bgcol, dup9);
}
if (src == cursor_ptr &&
@@ -1232,10 +1232,10 @@
h = line_last - line_start + 1;
d = d1 + linesize * line_start;
if (cw != 9) {
- vga_draw_glyph8(d, linesize,
+ vga_draw_glyph8(d, linesize,
cursor_glyph, h, fgcol, bgcol);
} else {
- vga_draw_glyph9(d, linesize,
+ vga_draw_glyph9(d, linesize,
cursor_glyph, h, fgcol, bgcol, 1);
}
}
@@ -1246,7 +1246,7 @@
ch_attr_ptr++;
}
if (cx_max != -1) {
- dpy_update(s->ds, cx_min * cw, cy * cheight,
+ dpy_update(s->ds, cx_min * cw, cy * cheight,
(cx_max - cx_min + 1) * cw, cheight);
}
dest += linesize * cheight;
@@ -1368,7 +1368,7 @@
#ifdef CONFIG_BOCHS_VBE
if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
- } else
+ } else
#endif
{
ret = 0;
@@ -1379,17 +1379,17 @@
static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
{
int width, height;
-
+
#ifdef CONFIG_BOCHS_VBE
if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
- } else
+ } else
#endif
{
width = (s->cr[0x01] + 1) * 8;
- height = s->cr[0x12] |
- ((s->cr[0x07] & 0x02) << 7) |
+ height = s->cr[0x12] |
+ ((s->cr[0x07] & 0x02) << 7) |
((s->cr[0x07] & 0x40) << 3);
height = (height + 1);
}
@@ -1409,7 +1409,7 @@
}
}
-/*
+/*
* graphic modes
*/
static void vga_draw_graphic(VGAState *s, int full_update)
@@ -1420,7 +1420,7 @@
uint8_t *d;
uint32_t v, addr1, addr;
vga_draw_line_func *vga_draw_line;
-
+
full_update |= update_basic_params(s);
s->get_resolution(s, &width, &height);
@@ -1442,7 +1442,7 @@
s->shift_control = shift_control;
s->double_scan = double_scan;
}
-
+
if (shift_control == 0) {
full_update |= update_palette16(s);
if (s->sr[0x01] & 8) {
@@ -1497,7 +1497,7 @@
}
if (s->cursor_invalidate)
s->cursor_invalidate(s);
-
+
line_offset = s->line_offset;
#if 0
printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
@@ -1524,12 +1524,12 @@
}
page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
- update = full_update |
+ update = full_update |
cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
if ((page1 - page0) > TARGET_PAGE_SIZE) {
/* if wide line, can use another page */
- update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
+ update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
VGA_DIRTY_FLAG);
}
/* explicit invalidation for the hardware cursor */
@@ -1547,7 +1547,7 @@
} else {
if (y_start >= 0) {
/* flush to display */
- dpy_update(s->ds, 0, y_start,
+ dpy_update(s->ds, 0, y_start,
disp_width, y - y_start);
y_start = -1;
}
@@ -1568,7 +1568,7 @@
}
if (y_start >= 0) {
/* flush to display */
- dpy_update(s->ds, 0, y_start,
+ dpy_update(s->ds, 0, y_start,
disp_width, y - y_start);
}
/* reset modified pages */
@@ -1588,7 +1588,7 @@
return;
if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
return;
- if (s->ds->depth == 8)
+ if (s->ds->depth == 8)
val = s->rgb_to_pixel(0, 0, 0);
else
val = 0;
@@ -1598,13 +1598,13 @@
memset(d, val, w);
d += s->ds->linesize;
}
- dpy_update(s->ds, 0, 0,
+ dpy_update(s->ds, 0, 0,
s->last_scr_width, s->last_scr_height);
}
#define GMODE_TEXT 0
#define GMODE_GRAPH 1
-#define GMODE_BLANK 2
+#define GMODE_BLANK 2
static void vga_update_display(void *opaque)
{
@@ -1614,9 +1614,9 @@
if (s->ds->depth == 0) {
/* nothing to do */
} else {
- s->rgb_to_pixel =
+ s->rgb_to_pixel =
rgb_to_pixel_dup_table[get_depth_index(s->ds)];
-
+
full_update = 0;
if (!(s->ar_index & 0x20)) {
graphic_mode = GMODE_BLANK;
@@ -1646,7 +1646,7 @@
static void vga_invalidate_display(void *opaque)
{
VGAState *s = (VGAState *)opaque;
-
+
s->last_width = -1;
s->last_height = -1;
}
@@ -1775,7 +1775,7 @@
VGAState vga_state;
} PCIVGAState;
-static void vga_map(PCIDevice *pci_dev, int region_num,
+static void vga_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
PCIVGAState *d = (PCIVGAState *)pci_dev;
@@ -1787,7 +1787,7 @@
}
}
-void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
+void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
{
int i, j, v, b;
@@ -1866,7 +1866,7 @@
register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
- register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
+ register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
#else
register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
@@ -1877,7 +1877,7 @@
#endif /* CONFIG_BOCHS_VBE */
vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
- cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
+ cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
vga_io_memory);
}
@@ -1956,7 +1956,7 @@
cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
}
-int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
+int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
{
VGAState *s;
@@ -1972,7 +1972,7 @@
#ifdef CONFIG_BOCHS_VBE
/* XXX: use optimized standard vga accesses */
- cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
+ cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
vga_ram_size, vga_ram_offset);
#endif
return 0;
@@ -2002,39 +2002,39 @@
return 0;
}
-int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
+int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size,
unsigned long vga_bios_offset, int vga_bios_size)
{
PCIVGAState *d;
VGAState *s;
uint8_t *pci_conf;
-
- d = (PCIVGAState *)pci_register_device(bus, "VGA",
+
+ d = (PCIVGAState *)pci_register_device(bus, "VGA",
sizeof(PCIVGAState),
-1, NULL, NULL);
if (!d)
return -1;
s = &d->vga_state;
-
+
vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_init(s);
graphic_console_init(s->ds, s->update, s->invalidate, s->screen_dump, s);
s->pci_dev = &d->dev;
-
+
pci_conf = d->dev.config;
pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID)
pci_conf[0x01] = 0x12;
pci_conf[0x02] = 0x11;
pci_conf[0x03] = 0x11;
- pci_conf[0x0a] = 0x00; // VGA controller
+ pci_conf[0x0a] = 0x00; // VGA controller
pci_conf[0x0b] = 0x03;
pci_conf[0x0e] = 0x00; // header_type
-
+
/* XXX: vga_ram_size must be a power of two */
- pci_register_io_region(&d->dev, 0, vga_ram_size,
+ pci_register_io_region(&d->dev, 0, vga_ram_size,
PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
if (vga_bios_size != 0) {
unsigned int bios_total_size;
@@ -2044,7 +2044,7 @@
bios_total_size = 1;
while (bios_total_size < vga_bios_size)
bios_total_size <<= 1;
- pci_register_io_region(&d->dev, PCI_ROM_SLOT, bios_total_size,
+ pci_register_io_region(&d->dev, PCI_ROM_SLOT, bios_total_size,
PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
}
return 0;
@@ -2055,7 +2055,7 @@
static int vga_save_w, vga_save_h;
-static void vga_save_dpy_update(DisplayState *s,
+static void vga_save_dpy_update(DisplayState *s,
int x, int y, int w, int h)
{
}
@@ -2072,7 +2072,7 @@
{
}
-int ppm_save(const char *filename, uint8_t *data,
+int ppm_save(const char *filename, uint8_t *data,
int w, int h, int linesize)
{
FILE *f;
@@ -2107,7 +2107,7 @@
{
VGAState *s = (VGAState *)opaque;
DisplayState *saved_ds, ds1, *ds = &ds1;
-
+
/* XXX: this is a little hackish */
vga_invalidate_display(s);
saved_ds = s->ds;
@@ -2121,9 +2121,9 @@
s->ds = ds;
s->graphic_mode = -1;
vga_update_display(s);
-
+
if (ds->data) {
- ppm_save(filename, ds->data, vga_save_w, vga_save_h,
+ ppm_save(filename, ds->data, vga_save_w, vga_save_h,
s->ds->linesize);
qemu_free(ds->data);
}
diff --git a/hw/vga_int.h b/hw/vga_int.h
index 2a4e9b9..3eb4e29 100644
--- a/hw/vga_int.h
+++ b/hw/vga_int.h
@@ -1,8 +1,8 @@
/*
* QEMU internal VGA defines.
- *
+ *
* Copyright (c) 2003-2004 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -45,20 +45,20 @@
#define VBE_DISPI_INDEX_X_OFFSET 0x8
#define VBE_DISPI_INDEX_Y_OFFSET 0x9
#define VBE_DISPI_INDEX_NB 0xa
-
+
#define VBE_DISPI_ID0 0xB0C0
#define VBE_DISPI_ID1 0xB0C1
#define VBE_DISPI_ID2 0xB0C2
#define VBE_DISPI_ID3 0xB0C3
#define VBE_DISPI_ID4 0xB0C4
-
+
#define VBE_DISPI_DISABLED 0x00
#define VBE_DISPI_ENABLED 0x01
#define VBE_DISPI_GETCAPS 0x02
#define VBE_DISPI_8BIT_DAC 0x20
#define VBE_DISPI_LFB_ENABLED 0x40
#define VBE_DISPI_NOCLEARMEM 0x80
-
+
#define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
#ifdef CONFIG_BOCHS_VBE
@@ -160,25 +160,25 @@
return (v << 2) | (b << 1) | b;
}
-void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
+void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size);
void vga_init(VGAState *s);
uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
void vga_invalidate_scanlines(VGAState *s, int y1, int y2);
-int ppm_save(const char *filename, uint8_t *data,
+int ppm_save(const char *filename, uint8_t *data,
int w, int h, int linesize);
-void vga_draw_cursor_line_8(uint8_t *d1, const uint8_t *src1,
- int poffset, int w,
+void vga_draw_cursor_line_8(uint8_t *d1, const uint8_t *src1,
+ int poffset, int w,
unsigned int color0, unsigned int color1,
unsigned int color_xor);
-void vga_draw_cursor_line_16(uint8_t *d1, const uint8_t *src1,
- int poffset, int w,
+void vga_draw_cursor_line_16(uint8_t *d1, const uint8_t *src1,
+ int poffset, int w,
unsigned int color0, unsigned int color1,
unsigned int color_xor);
-void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1,
- int poffset, int w,
+void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1,
+ int poffset, int w,
unsigned int color0, unsigned int color1,
unsigned int color_xor);
diff --git a/hw/vga_template.h b/hw/vga_template.h
index e7e8cb8..41f6e25 100644
--- a/hw/vga_template.h
+++ b/hw/vga_template.h
@@ -1,8 +1,8 @@
/*
* QEMU VGA Emulator templates
- *
+ *
* Copyright (c) 2003 Fabrice Bellard
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@@ -24,13 +24,13 @@
#if DEPTH == 8
#define BPP 1
-#define PIXEL_TYPE uint8_t
+#define PIXEL_TYPE uint8_t
#elif DEPTH == 15 || DEPTH == 16
#define BPP 2
-#define PIXEL_TYPE uint16_t
+#define PIXEL_TYPE uint16_t
#elif DEPTH == 32
#define BPP 4
-#define PIXEL_TYPE uint32_t
+#define PIXEL_TYPE uint32_t
#else
#error unsupport depth
#endif
@@ -43,9 +43,9 @@
#if DEPTH != 15 && !defined(BGR_FORMAT)
-static inline void glue(vga_draw_glyph_line_, DEPTH)(uint8_t *d,
+static inline void glue(vga_draw_glyph_line_, DEPTH)(uint8_t *d,
uint32_t font_data,
- uint32_t xorcol,
+ uint32_t xorcol,
uint32_t bgcol)
{
#if BPP == 1
@@ -73,7 +73,7 @@
uint32_t fgcol, uint32_t bgcol)
{
uint32_t font_data, xorcol;
-
+
xorcol = bgcol ^ fgcol;
do {
font_data = font_ptr[0];
@@ -88,15 +88,15 @@
uint32_t fgcol, uint32_t bgcol)
{
uint32_t font_data, xorcol;
-
+
xorcol = bgcol ^ fgcol;
do {
font_data = font_ptr[0];
- glue(vga_draw_glyph_line_, DEPTH)(d,
- expand4to8[font_data >> 4],
+ glue(vga_draw_glyph_line_, DEPTH)(d,
+ expand4to8[font_data >> 4],
xorcol, bgcol);
- glue(vga_draw_glyph_line_, DEPTH)(d + 8 * BPP,
- expand4to8[font_data & 0x0f],
+ glue(vga_draw_glyph_line_, DEPTH)(d + 8 * BPP,
+ expand4to8[font_data & 0x0f],
xorcol, bgcol);
font_ptr += 4;
d += linesize;
@@ -104,11 +104,11 @@
}
static void glue(vga_draw_glyph9_, DEPTH)(uint8_t *d, int linesize,
- const uint8_t *font_ptr, int h,
+ const uint8_t *font_ptr, int h,
uint32_t fgcol, uint32_t bgcol, int dup9)
{
uint32_t font_data, xorcol, v;
-
+
xorcol = bgcol ^ fgcol;
do {
font_data = font_ptr[0];
@@ -120,7 +120,7 @@
((uint8_t *)d)[8] = v >> (24 * (1 - BIG));
else
((uint8_t *)d)[8] = bgcol;
-
+
#elif BPP == 2
cpu_to_32wu(((uint32_t *)d)+0, (dmask4[(font_data >> 6)] & xorcol) ^ bgcol);
cpu_to_32wu(((uint32_t *)d)+1, (dmask4[(font_data >> 4) & 3] & xorcol) ^ bgcol);
@@ -151,10 +151,10 @@
} while (--h);
}
-/*
+/*
* 4 color mode
*/
-static void glue(vga_draw_line2_, DEPTH)(VGAState *s1, uint8_t *d,
+static void glue(vga_draw_line2_, DEPTH)(VGAState *s1, uint8_t *d,
const uint8_t *s, int width)
{
uint32_t plane_mask, *palette, data, v;
@@ -193,10 +193,10 @@
((uint32_t *)d)[2*(n)] = ((uint32_t *)d)[2*(n)+1] = (v)
#endif
-/*
+/*
* 4 color mode, dup2 horizontal
*/
-static void glue(vga_draw_line2d2_, DEPTH)(VGAState *s1, uint8_t *d,
+static void glue(vga_draw_line2d2_, DEPTH)(VGAState *s1, uint8_t *d,
const uint8_t *s, int width)
{
uint32_t plane_mask, *palette, data, v;
@@ -226,10 +226,10 @@
}
}
-/*
+/*
* 16 color mode
*/
-static void glue(vga_draw_line4_, DEPTH)(VGAState *s1, uint8_t *d,
+static void glue(vga_draw_line4_, DEPTH)(VGAState *s1, uint8_t *d,
const uint8_t *s, int width)
{
uint32_t plane_mask, data, v, *palette;
@@ -258,10 +258,10 @@
}
}
-/*
+/*
* 16 color mode, dup2 horizontal
*/
-static void glue(vga_draw_line4d2_, DEPTH)(VGAState *s1, uint8_t *d,
+static void glue(vga_draw_line4d2_, DEPTH)(VGAState *s1, uint8_t *d,
const uint8_t *s, int width)
{
uint32_t plane_mask, data, v, *palette;
@@ -290,12 +290,12 @@
}
}
-/*
+/*
* 256 color mode, double pixels
*
* XXX: add plane_mask support (never used in standard VGA modes)
*/
-static void glue(vga_draw_line8d2_, DEPTH)(VGAState *s1, uint8_t *d,
+static void glue(vga_draw_line8d2_, DEPTH)(VGAState *s1, uint8_t *d,
const uint8_t *s, int width)
{
uint32_t *palette;
@@ -313,12 +313,12 @@
}
}
-/*
+/*
* standard 256 color mode
*
* XXX: add plane_mask support (never used in standard VGA modes)
*/
-static void glue(vga_draw_line8_, DEPTH)(VGAState *s1, uint8_t *d,
+static void glue(vga_draw_line8_, DEPTH)(VGAState *s1, uint8_t *d,
const uint8_t *s, int width)
{
uint32_t *palette;
@@ -340,10 +340,10 @@
}
}
-void glue(vga_draw_cursor_line_, DEPTH)(uint8_t *d1,
- const uint8_t *src1,
+void glue(vga_draw_cursor_line_, DEPTH)(uint8_t *d1,
+ const uint8_t *src1,
int poffset, int w,
- unsigned int color0,
+ unsigned int color0,
unsigned int color1,
unsigned int color_xor)
{
@@ -411,10 +411,10 @@
/* XXX: optimize */
-/*
+/*
* 15 bit color
*/
-static void glue(vga_draw_line15_, PIXEL_NAME)(VGAState *s1, uint8_t *d,
+static void glue(vga_draw_line15_, PIXEL_NAME)(VGAState *s1, uint8_t *d,
const uint8_t *s, int width)
{
#if DEPTH == 15 && defined(WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
@@ -433,13 +433,13 @@
s += 2;
d += BPP;
} while (--w != 0);
-#endif
+#endif
}
-/*
+/*
* 16 bit color
*/
-static void glue(vga_draw_line16_, PIXEL_NAME)(VGAState *s1, uint8_t *d,
+static void glue(vga_draw_line16_, PIXEL_NAME)(VGAState *s1, uint8_t *d,
const uint8_t *s, int width)
{
#if DEPTH == 16 && defined(WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
@@ -458,13 +458,13 @@
s += 2;
d += BPP;
} while (--w != 0);
-#endif
+#endif
}
-/*
+/*
* 24 bit color
*/
-static void glue(vga_draw_line24_, PIXEL_NAME)(VGAState *s1, uint8_t *d,
+static void glue(vga_draw_line24_, PIXEL_NAME)(VGAState *s1, uint8_t *d,
const uint8_t *s, int width)
{
int w;
@@ -487,10 +487,10 @@
} while (--w != 0);
}
-/*
+/*
* 32 bit color
*/
-static void glue(vga_draw_line32_, PIXEL_NAME)(VGAState *s1, uint8_t *d,
+static void glue(vga_draw_line32_, PIXEL_NAME)(VGAState *s1, uint8_t *d,
const uint8_t *s, int width)
{
#if DEPTH == 32 && defined(WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) && !defined(BGR_FORMAT)
diff --git a/hw/vmmouse.c b/hw/vmmouse.c
index 52c8e0c..3c4f667 100644
--- a/hw/vmmouse.c
+++ b/hw/vmmouse.c
@@ -1,8 +1,8 @@
/*
* QEMU VMMouse emulation
- *
+ *
* Copyright (C) 2007 Anthony Liguori <[email protected]>
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
