commit 93a40ea9264dfd5df63669e785fed1c9db0041f4
author bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> Mon Oct 27 21:13:06 2003 +0000
committer bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> Mon Oct 27 21:13:06 2003 +0000
tree a2bfd3ce07e66bc95cc692c798a597c163da6a9e
parent db8d74668856e5bbc6c8fede0bb17c4f83e7debf

fixed mmu fault priviledge logic


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@406 c046a42c-6fe2-441c-8c8c-71466251a162

cpu-exec.c

diff --git a/cpu-exec.c b/cpu-exec.c
index 035f104..956504d 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -225,7 +225,7 @@
                     cpu_arm_dump_state(env, logfile, 0);
                     env->cpsr &= ~0xf0000000;
 #elif defined(TARGET_SPARC)
-					cpu_sparc_dump_state (env, logfile, 0);
+                    cpu_sparc_dump_state (env, logfile, 0);
 #else
 #error unsupported target CPU 
 #endif
@@ -273,6 +273,7 @@
                     tb->tc_ptr = tc_ptr;
                     tb->cs_base = (unsigned long)cs_base;
                     tb->flags = flags;
+                    /* XXX: an MMU exception can occur here */
                     cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
                     *ptb = tb;
                     tb->hash_next = NULL;
@@ -456,7 +457,8 @@
         return 1;
     }
     /* see if it is an MMU fault */
-    ret = cpu_x86_handle_mmu_fault(env, address, is_write);
+    ret = cpu_x86_handle_mmu_fault(env, address, is_write, 
+                                   ((env->hflags & HF_CPL_MASK) == 3), 0);
     if (ret < 0)
         return 0; /* not an MMU fault */
     if (ret == 0)