pci: Q35, Root Ports, and Switches create PCI Express buses
Convert q35, ioh3420, xio3130_upstream, and xio3130_downstream to
use the new TYPE_PCIE_BUS.
Signed-off-by: Alex Williamson <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
diff --git a/hw/ioh3420.c b/hw/ioh3420.c
index 74d84d4..5cff61e 100644
--- a/hw/ioh3420.c
+++ b/hw/ioh3420.c
@@ -97,7 +97,7 @@
PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
int rc;
- rc = pci_bridge_initfn(d, TYPE_PCI_BUS);
+ rc = pci_bridge_initfn(d, TYPE_PCIE_BUS);
if (rc < 0) {
return rc;
}
diff --git a/hw/q35.c b/hw/q35.c
index 37592bc..6ea081a 100644
--- a/hw/q35.c
+++ b/hw/q35.c
@@ -55,7 +55,7 @@
}
b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0",
s->mch.pci_address_space, s->mch.address_space_io,
- 0, TYPE_PCI_BUS);
+ 0, TYPE_PCIE_BUS);
s->host.pci.bus = b;
qdev_set_parent_bus(DEVICE(&s->mch), BUS(b));
qdev_init_nofail(DEVICE(&s->mch));
diff --git a/hw/xio3130_downstream.c b/hw/xio3130_downstream.c
index a76d89b..b868f56 100644
--- a/hw/xio3130_downstream.c
+++ b/hw/xio3130_downstream.c
@@ -61,7 +61,7 @@
PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
int rc;
- rc = pci_bridge_initfn(d, TYPE_PCI_BUS);
+ rc = pci_bridge_initfn(d, TYPE_PCIE_BUS);
if (rc < 0) {
return rc;
}
diff --git a/hw/xio3130_upstream.c b/hw/xio3130_upstream.c
index d8fd19e..cd5d97d 100644
--- a/hw/xio3130_upstream.c
+++ b/hw/xio3130_upstream.c
@@ -57,7 +57,7 @@
PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
int rc;
- rc = pci_bridge_initfn(d, TYPE_PCI_BUS);
+ rc = pci_bridge_initfn(d, TYPE_PCIE_BUS);
if (rc < 0) {
return rc;
}
