commit ba3c64fb476d57c35013970ac444f04f35893ca9
author bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> Mon Dec 05 20:31:52 2005 +0000
committer bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> Mon Dec 05 20:31:52 2005 +0000
tree ef1a50165c32cf861862c94cfd9bcf9ebffcd9f2
parent b9788fc4c4974a4871e0ee46b5c06fee105a6aff

Initial SPARC SMP support (Blue Swirl)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1694 c046a42c-6fe2-441c-8c8c-71466251a162

cpu-exec.c

diff --git a/cpu-exec.c b/cpu-exec.c
index 128b5ff..740037e 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -274,6 +274,15 @@
             return EXCP_HALTED;
         }
     }
+#elif defined(TARGET_SPARC)
+    if (env1->halted) {
+        if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
+            (env1->psret != 0)) {
+            env1->halted = 0;
+        } else {
+            return EXCP_HALTED;
+        }
+    }
 #elif defined(TARGET_ARM)
     if (env1->halted) {
         /* An interrupt wakes the CPU even if the I and F CPSR bits are
@@ -522,7 +531,10 @@
 		    } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
 			//do_interrupt(0, 0, 0, 0, 0);
 			env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
-		    }
+		    } else if (interrupt_request & CPU_INTERRUPT_HALT) {
+                        env1->halted = 1;
+                        return EXCP_HALTED;
+                    }
 #elif defined(TARGET_ARM)
                     if (interrupt_request & CPU_INTERRUPT_FIQ
                         && !(env->uncached_cpsr & CPSR_F)) {