Rename CPUState to CPUOldState.
Upstream qemu has split the cpu state into two new data structures:
CPUState -> is used to model the CPU state through the QEMU
object model.
CPUArchState -> actually a macro that aliases CPUArmState,
CPUX86State or CPUMIPSState.
Both were part of the "CPUState" in the current emulator sources.
Previous patches introduced CPUArchState, as a simple alias to the
machine-specific state. This patch renames any use of CPUState in
the current code to CPUOldState, except within target-*/ directories
where it is replaced by CPU${ARCH}State instead.
This will allow bringing the upstream CPUState definition in the
source tree, and slowly migrate everything to the right location.
Change-Id: I88b79e6e89f1f36084dc2642e1cf415135e4da09
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 7de79d1..94cd742 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -35,7 +35,7 @@
};
/* no MMU emulation */
-int no_mmu_map_address (CPUState *env, hwaddr *physical, int *prot,
+int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
{
*physical = address;
@@ -44,7 +44,7 @@
}
/* fixed mapping MMU emulation */
-int fixed_mmu_map_address (CPUState *env, hwaddr *physical, int *prot,
+int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
{
if (address <= (int32_t)0x7FFFFFFFUL) {
@@ -62,7 +62,7 @@
}
/* MIPS32/MIPS64 R4000-style MMU emulation */
-int r4k_map_address (CPUState *env, hwaddr *physical, int *prot,
+int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
{
uint8_t ASID = env->CP0_EntryHi & 0xFF;
@@ -105,7 +105,7 @@
}
#if !defined(CONFIG_USER_ONLY)
-static int get_physical_address (CPUState *env, hwaddr *physical,
+static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
int *prot, target_ulong address,
int rw, int access_type)
{
@@ -207,7 +207,7 @@
}
#endif
-static void raise_mmu_exception(CPUState *env, target_ulong address,
+static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
int rw, int tlb_error)
{
int exception = 0, error_code = 0;
@@ -269,7 +269,7 @@
int softshift;
} linux_pte_info = {0};
-static inline target_ulong cpu_mips_get_pgd(CPUState *env)
+static inline target_ulong cpu_mips_get_pgd(CPUMIPSState *env)
{
if (unlikely(linux_pte_info.pgd_current_p == 0)) {
int i;
@@ -341,9 +341,9 @@
}
// in target-mips/op_helper.c
-extern void r4k_helper_ptw_tlbrefill(CPUState*);
+extern void r4k_helper_ptw_tlbrefill(CPUMIPSState*);
-static inline int cpu_mips_tlb_refill(CPUState *env, target_ulong address, int rw ,
+static inline int cpu_mips_tlb_refill(CPUMIPSState *env, target_ulong address, int rw ,
int mmu_idx, int is_softmmu)
{
int32_t saved_hflags;
@@ -436,7 +436,7 @@
return ret;
}
-int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
{
#if !defined(CONFIG_USER_ONLY)
@@ -484,7 +484,7 @@
}
#if !defined(CONFIG_USER_ONLY)
-hwaddr cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
+hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
{
hwaddr physical;
int prot;
@@ -506,7 +506,7 @@
}
#endif
-hwaddr cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUMIPSState *env, target_ulong addr)
{
#if defined(CONFIG_USER_ONLY)
return addr;
@@ -584,7 +584,7 @@
[EXCP_CACHE] = "cache error",
};
-void do_interrupt (CPUState *env)
+void do_interrupt (CPUMIPSState *env)
{
#if !defined(CONFIG_USER_ONLY)
target_ulong offset;
@@ -807,7 +807,7 @@
env->exception_index = EXCP_NONE;
}
-void r4k_invalidate_tlb (CPUState *env, int idx)
+void r4k_invalidate_tlb (CPUMIPSState *env, int idx)
{
r4k_tlb_t *tlb;
target_ulong addr;
