commit	a5868477b2953c4707318a947a1d1d98483bed95	[log] [tgz]
author	Chris Jones <[email protected]>	Fri Feb 07 15:36:10 2025 +0000
committer	Chris Jones <[email protected]>	Mon Feb 10 17:23:15 2025 +0000
tree	a31a2400045cfb4b2bb14bedf5417414d740a696
parent	2a6e3c3d527e9987a325a6ed523550207d95f373 [diff]
parent	6c8128e26b693e7d91eca544aee32eaa86019891 [diff]

Merge tag '8.0.0' into AOSP

Merge from https://github.com/Linaro/vixl.

Merged commits:
ff82b3328c Fix python 3.12+ error (#128)
89bd929e3d Add support for DC ZVA (#127)
1e7883a659 Remove printf positional argument requirements from disassembler (#125)
4415fe4817 [sve] Support PMULLB/T for Q destination elements (#126)
aca39bdd86 Make MOPS tests tolerant of implementation options.
bdbc225b2a Support SM4 accelerating instructions (#123)
d17400fdc2 Restrict some multiply instructions element sizes (#121)
ed687ad221 Fix backward branch veneers (#120)
16e6647575 Update code coverage and formatting (#119)
e6076e92c4 Skip BTI tests on hardware.
f5cadc8c41 Don't accept B or D lanes for SQRDMLxH.
8bd595824b Initialise NZCV for FlagM tests.
a01ff906dd Restore sp after test.
01cd1c2f65 Don't assume that GCS is present in CHKFEAT tests.
ecd241c0cd Make PAuth tests more robust against collisions.
080c942b39 Work around LLVM #108722.
598b0bb3bd Fix 'set but not used' warnings.
8088bb8b2b [aarch32] Make RawLiteral (and therefore Literal) noncopyable but movable (#116)
15c11bf616 Document limits of branches and literal instructions (#115)
d0c2c933e2 [aarch32] Apply veneers to out-of-range backwards conditional branches (#114)
49d6efa6b9 Fix compilation of Simulator/Debugger with MSVC (#113)
95cb2f5d18 Improve irg test (#112)
4474f58971 Refactor fcvt tests (#111)
dfc2ffb973 Replace rand48 with std::linear_congruential_engine in simulator (#110)
f4e68058f9 fix: avoid template-id-cdtor warning with GCC 14 (#109)
b7ab6ec2ee Support SM3 accelerating instructions (#108)
da718c2b77 Support AES accelerating instructions (#107)
a22e9a5ca6 Fix warnings with recent Python.
a1856a3203 Support SHA-512 accelerating instructions (#104)
aabfa0ce0a Support SHA-2 accelerating instructions (#103)
7eb48c6e00 Support SHA-1 accelerating instructions (#102)
f307b4a2db Support SHA-3 accelerating instructions (#101)
3c40723a26 [gcs] Support Guarded Control Stacks (#100)
16609c81df Fix negation of immediates in ccmp, ccmn and neg (#99)
662828c826 Fix disassembly of Neon FCM, RDM and dot product instructions (#98)
5e267967c8 Fix zeroing part of SVE register for Neon instructions (#97)
2cdba9ed4a Fix zeroing part of SVE register for Neon INS (#95)
3134e2560d Perform implicit checks on store instructions
89dfbc0093 Check ld* functions for failure (#92)
5a2144d133 Support PMULL for 1Q destination vectors (#91)
30e7bbdc37 Add support for implicit checks (#86)
accc97f168 Ensure the `threaded_tests` module can be imported safely (#90)
ef2f4d152c Fix some portability and build problems (#89)
1a2c1d379f Update clang tools to version 11+ (#87)
2decd2cf31 Update tools to python3 (#85)
08574f1bae Update code coverage (#83)
7a2a47281b Update to C++17 (#82)
a0a143959b Add a debugger to VIXL simulator (#81)
8eca2b7b2f Add branch interception to VIXL simulator (#77)
b13d3bf3b1 Fixes post-index vector loadstore writeback (#76)
279f08b57b Improve SIMD & FP constant materialization (#74)
02c6706933 Update code coverage record (#73)
a20c62b4b1 Update comment to match the macro name (#72)
c5b3101ece Define PrintVector function only when necessary (#70)
64c25fed56 Small optimisation for Assembler::Emit (#71)
b5c57c94bc Add support for CSSC instructions (#69)
94b311af82 Update instruction decoder (#68)
b6725cfeb8 Fix BIC macro assembler definition to be non-commutative (#66)
1b2332d406 Update code coverage record (#67)
48c8bedeca Regression test for SVE loads/stores with sp base address (#65)
d7b7a306fb Fix pointer authentication modifier source register (#61)
84e54a2d6f Restore FPCR after modifying it in a test.
9128d58004 Fix register trace involving sp and xzr (#59)
8ab3dd5beb Fix incorrect instruction mappings (#58)
d3f755c30c simulator-aarch64: Fix use of zero register in several SVE load/stores (#47)
7bf4bab6ce aarch64: Allow testing for the presence of SVE FEAT_EBF16 (#57)
f03979c481 Add regression test for movprfx/ext and fix splice (#56)
c40e2ab0d3 instructions-aarch64: Handle destructive EXT in CanTakeSVEMovprfx (#55)
8c05ce7c0f Tidy up System instruction simulation (#54)
537074becf Regression test for XTN fix (#52)
28fd4e9d2e Use correct format specifier in one of the examples (#51)
1ba324d89f logic-aarch64: Fix register clearing bug in extractnarrow (#49)
8c95620eca Update code coverage records (#50)
088b01fecf Fix compilation with Microsoft Visual C++ (#46)
19dfd91163 Fix disassembly of Neon by-element instructions (#45)
7df62a379c Merge branch 'main' into mte
024d1cb319 Update code coverage results
bcb9ee3ef8 cpu-features: Update OS queryable hwcaps (#43)
d6acdadcd4 Add support for MOPS instructions
eeae1749b9 Merge branch 'main' into mte
b43d6ef204 Spelling (#41)
64f990af81 [mte] Fix casts for Mac builds
5c310da1e6 [mte] Add cache maintenance operations
2d2f24cfde [mte] Implement ldg, st2g, stg, stgp, stz2g and stzg (#28)
0e7c55b439 Merge branch 'main' into mte
6767df0a78 A prototype to support memory metadata in the Simulator. (#24)
e2e0b2d3d6 [mte] Add data processing instructions
2e4aff6c58 [mte] Add skeleton disassembler and simulator
224fc7355b [mte] Add skeleton assembler

Also fix format specifiers to silence -Wformat warnings.

Test: test.py --host --target
Change-Id: If86680738ec2266b75cc24440bf07fbe40379cb8

tree: a31a2400045cfb4b2bb14bedf5417414d740a696

README.md

VIXL: ARMv8 Runtime Code Generation Library 8.0.0

Contents:

Overview
Licence
Requirements
Known limitations
Bug reports
Usage

Overview

VIXL contains three components.

Programmatic assemblers to generate A64, A32 or T32 code at runtime. The assemblers abstract some of the constraints of each ISA; for example, most instructions support any immediate.
Disassemblers that can print any instruction emitted by the assemblers.
A simulator that can simulate any instruction emitted by the A64 assembler. The simulator allows generated code to be run on another architecture without the need for a full ISA model.

The VIXL git repository can be found on GitHub.

Build and Test Status

Simulator
Native
MacOS

Licence

This software is covered by the licence described in the LICENCE file.

Contributions, as pull requests or via other means, are accepted under the terms of the same LICENCE.

Requirements

To build VIXL the following software is required:

Python 3.5+
SCons 2.0
GCC 4.8+ or Clang 4.0+

A 64-bit host machine is required, implementing an LP64 data model. VIXL has been tested using GCC on AArch64 Debian, GCC and Clang on amd64 Ubuntu systems.

To run the linter and code formatting stages of the tests, the following software is also required:

Git
Google's cpplint.py
clang-format 11+
clang-tidy 11+

Refer to the ‘Usage’ section for details.

Note that in Ubuntu 18.04, clang-tidy-4.0 will only work if the clang-4.0 package is also installed.

Supported Arm Architecture Features

Feature	VIXL CPUFeatures Flag	Notes
BTI	kBTI	Per-page enabling not supported
DotProd	kDotProduct
FCMA	kFcma
FHM	kFHM
FP16	kFPHalf, kNEONHalf
FRINTTS	kFrintToFixedSizedInt
FlagM	kFlagM
FlagM2	kAXFlag
I8MM	kI8MM
JSCVT	kJSCVT
LOR	kLORegions
LRCPC	kRCpc
LRCPC2	kRCpcImm
LSE	kAtomics
PAuth	kPAuth, kPAuthGeneric	Not ERETAA, ERETAB
RAS	kRAS
RDM	kRDM
SVE	kSVE
SVE2	kSVE2
SVEBitPerm	kSVEBitPerm
SVEF32MM	kSVEF32MM
SVEF64MM	kSVEF64MM
SVEI8MM	kSVEI8MM

Enable generating code for an architecture feature by combining a flag with the MacroAssembler's defaults. For example, to generate code for SVE, use masm.GetCPUFeatures()->Combine(CPUFeatures::kSVE);.

See the cpu features header file for more information.

Known Limitations

VIXL was developed for JavaScript engines so a number of features from A64 were deemed unnecessary:

Limited rounding mode support for floating point.
Limited support for synchronisation instructions.
Limited support for system instructions.
A few miscellaneous integer and floating point instructions are missing.

The VIXL simulator supports only those instructions that the VIXL assembler can generate. The doc directory contains a list of supported A64 instructions.

The VIXL simulator was developed to run on 64-bit amd64 platforms. Whilst it builds and mostly works for 32-bit x86 platforms, there are a number of floating-point operations which do not work correctly, and a number of tests fail as a result.

Debug Builds

Your project's build system must define VIXL_DEBUG (eg. -DVIXL_DEBUG) when using a VIXL library that has been built with debug enabled.

Some classes defined in VIXL header files contain fields that are only present in debug builds, so if VIXL_DEBUG is defined when the library is built, but not defined for the header files included in your project, you will see runtime failures.

Exclusive-Access Instructions

All exclusive-access instructions are supported, but the simulator cannot accurately simulate their behaviour as described in the ARMv8 Architecture Reference Manual.

A local monitor is simulated, so simulated exclusive loads and stores execute as expected in a single-threaded environment.
The global monitor is simulated by occasionally causing exclusive-access instructions to fail regardless of the local monitor state.
Load-acquire, store-release semantics are approximated by issuing a host memory barrier after loads or before stores. The built-in __sync_synchronize() is used for this purpose.

The simulator tries to be strict, and implements the following restrictions that the ARMv8 ARM allows:

A pair of load-/store-exclusive instructions will only succeed if they have the same address and access size.
Most of the time, cache-maintenance operations or explicit memory accesses will clear the exclusive monitor.
- To ensure that simulated code does not depend on this behaviour, the exclusive monitor will sometimes be left intact after these instructions.

Instructions affected by these limitations: stxrb, stxrh, stxr, ldxrb, ldxrh, ldxr, stxp, ldxp, stlxrb, stlxrh, stlxr, ldaxrb, ldaxrh, ldaxr, stlxp, ldaxp, stlrb, stlrh, stlr, ldarb, ldarh, ldar, clrex.

Security Considerations

VIXL allows callers to generate any code they want. The generated code is arbitrary, and can therefore call back into any other component in the process. As with any self-modifying code, vulnerabilities in the client or in VIXL itself could lead to arbitrary code generation.

For performance reasons, VIXL‘s Assembler only performs debug-mode checking of instruction operands (such as immediate field encodability). This can minimise code-generation overheads for advanced compilers that already model instructions accurately, and might consider the Assembler’s checks to be redundant. The Assembler should only be used directly where encodability is independently checked, and where fine control over all generated code is required.

The MacroAssembler synthesises multiple-instruction sequences to support some unencodable operand combinations. The MacroAssembler can provide a useful safety check in cases where the Assembler's precision is not required; an unexpected unencodable operand should result in a macro with the correct behaviour, rather than an invalid instruction.

In general, the MacroAssembler handles operands which are likely to vary with user-supplied data, but does not usually handle inputs which are likely to be easily covered by tests. For example, move-immediate arguments are likely to be data-dependent, but register types (e.g. x vs w) are not.

We recommend that all users use the MacroAssembler, using ExactAssemblyScope to invoke the Assembler when specific instruction sequences are required. This approach is recommended even in cases where a compiler can model the instructions precisely, because, subject to the limitations described above, it offers an additional layer of protection against logic bugs in instruction selection.

Bug reports

Bug reports may be made in the Issues section of GitHub, or sent to [email protected]. Please provide any steps required to recreate a bug, along with build environment and host system information.

Usage

Running all Tests

The helper script tools/test.py will build and run every test that is provided with VIXL, in both release and debug mode. It is a useful script for verifying that all of VIXL's dependencies are in place and that VIXL is working as it should.

By default, the tools/test.py script runs a linter to check that the source code conforms with the code style guide, and to detect several common errors that the compiler may not warn about. This is most useful for VIXL developers. The linter has the following dependencies:

Git must be installed, and the VIXL project must be in a valid Git repository, such as one produced using git clone.
cpplint.py, as provided by Google, must be available (and executable) on the PATH.

It is possible to tell tools/test.py to skip the linter stage by passing --nolint. This removes the dependency on cpplint.py and Git. The --nolint option is implied if the VIXL project is a snapshot (with no .git directory).

Additionally, tools/test.py tests code formatting using clang-format-4.0, and performs static analysis using clang-tidy-4.0. If you don't have these tools, disable the test using --noclang-format or --noclang-tidy, respectively.

Also note that the tests for the tracing features depend upon external diff and sed tools. If these tools are not available in PATH, these tests will fail.

Getting Started

We have separate guides for introducing VIXL, depending on what architecture you are targeting. A guide for working with AArch32 can be found here, while the AArch64 guide is here. Example source code is provided in the examples directory. You can build examples with either scons aarch32_examples or scons aarch64_examples from the root directory, or use scons --help to get a detailed list of available build targets.