// Copyright 2016, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
//     and/or other materials provided with the distribution.
//   * Neither the name of ARM Limited nor the names of its contributors may be
//     used to endorse or promote products derived from this software without
//     specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

{
  "mnemonics": [
    "Ldrh",  // LDRH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
             // LDRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_3> ; A1
             // LDRH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}]! ; A1
    "Ldrsh", // LDRSH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_2>}] ; A1
             // LDRSH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_2> ; A1
             // LDRSH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_2>}]! ; A1
    "Ldrsb", // LDRSB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_2>}] ; A1
             // LDRSB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_2> ; A1
             // LDRSB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_2>}]! ; A1
    "Strh"   // STRH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}] ; A1
             // STRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_3> ; A1
             // STRH{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_3>}]! ; A1
  ],
  "description": {
    "operands": [
      {
        "name": "cond",
        "type": "Condition"
      },
      {
        "name": "rd",
        "type": "AllRegistersButPC"
      },
      {
        "name": "memop",
        "wrapper": "MemOperand",
        "operands": [
          {
            "name": "rn",
            "type": "AllRegistersButPC"
          },
          {
            "name": "sign",
            "type": "Sign"
          },
          {
            "name": "offset",
            "type": "OffsetLowerThan256"
          },
          {
            "name": "addr_mode",
            "type": "AddressingMode"
          }
        ]
      }
    ],
    "inputs": [
      {
        "name": "apsr",
        "type": "NZCV"
      },
      {
        "name": "rd",
        "type": "Register"
      },
      {
        "name": "memop",
        "type": "MemOperand"
      }
    ]
  },
  "test-files": [
    {
      "type": "assembler",
      "test-cases": [
        {
          "name": "Registers",
          "operands": [
            "cond", "rd", "rn"
          ],
          "operand-limit": 100
        },
        {
          "name": "MemOperandsOffset",
          "operands": [
            "rn", "sign", "offset", "addr_mode"
          ],
          "operand-filter": "addr_mode == 'Offset'",
          "operand-limit": 200
        },
        {
          "name": "MemOperandsWriteBack",
          "operands": [
            "rd", "rn", "sign", "offset", "addr_mode"
          ],
          "operand-filter": "addr_mode != 'Offset' and rd != rn",
          "operand-limit": 400
        }
      ]
    },
    {
      // TODO: The simulator tests do not support the case where `rd` ==
      // `rn`. See `data_types.MemOperand.Epilogue()` for details.
      "type": "simulator",
      "test-cases": [
        {
          "name": "Condition",
          "operands": [
            "cond", "rd", "rn"
          ],
          "operand-filter": "rd == 'r0' and rn == 'r1'",
          "inputs": [
            "apsr"
          ]
        },
        {
          "name": "PositiveOffset",
          "operands": [
            "rd", "rn", "sign", "offset", "addr_mode"
          ],
          "operand-filter": "sign == 'plus' and addr_mode == 'Offset' and rd != rn",
          "operand-limit": 100,
          "inputs": [
            "rd", "memop"
          ],
          "input-limit": 10
        },
        {
          "name": "NegativeOffset",
          "operands": [
            "rd", "rn", "sign", "offset", "addr_mode"
          ],
          "operand-filter": "sign == 'minus' and addr_mode == 'Offset' and rd != rn",
          "operand-limit": 100,
          "inputs": [
            "rd", "memop"
          ],
          "input-limit": 10
        },
        {
          "name": "PositivePostIndex",
          "operands": [
            "rd", "rn", "sign", "offset", "addr_mode"
          ],
          "operand-filter": "sign == 'plus' and addr_mode == 'PostIndex' and rd != rn",
          "operand-limit": 100,
          "inputs": [
            "rd", "memop"
          ],
          "input-limit": 10
        },
        {
          "name": "NegativePostIndex",
          "operands": [
            "rd", "rn", "sign", "offset", "addr_mode"
          ],
          "operand-filter": "sign == 'minus' and addr_mode == 'PostIndex' and rd != rn",
          "operand-limit": 100,
          "inputs": [
            "rd", "memop"
          ],
          "input-limit": 10
        },
        {
          "name": "PositivePreIndex",
          "operands": [
            "rd", "rn", "sign", "offset", "addr_mode"
          ],
          "operand-filter": "sign == 'plus' and addr_mode == 'PreIndex' and rd != rn",
          "operand-limit": 100,
          "inputs": [
            "rd", "memop"
          ],
          "input-limit": 10
        },
        {
          "name": "NegativePreIndex",
          "operands": [
            "rd", "rn", "sign", "offset", "addr_mode"
          ],
          "operand-filter": "sign == 'minus' and addr_mode == 'PreIndex' and rd != rn",
          "operand-limit": 100,
          "inputs": [
            "rd", "memop"
          ],
          "input-limit": 10
        }
      ]
    }
  ]
}