// Copyright 2016, VIXL authors
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are met:
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//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
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// Test description for instructions of the following form:
//   MNEMONIC{<c>}.W <Rn>, #<const>

{
  "mnemonics" : [
    "Cmn",  // CMN{<c>}{<q>} <Rn>, #<const> ; T1
    "Cmp",  // CMP{<c>}{<q>} <Rn>, #<const> ; T2
    "Mov",  // MOV{<c>}{<q>} <Rd>, #<const> ; T2
    "Movs", // MOVS{<c>}{<q>} <Rd>, #<const> ; T2
    "Mvn",  // MVN{<c>}{<q>} <Rd>, #<const> ; T1
    "Mvns", // MVNS{<c>}{<q>} <Rd>, #<const> ; T1
    "Teq",  // TEQ{<c>}{<q>} <Rn>, #<const> ; T1
    "Tst"   // TST{<c>}{<q>} <Rn>, #<const> ; T1
  ],
  "description" : {
    "operands": [
      {
        "name": "cond",
        "type": "Condition"
      },
      {
        "name": "rd",
        "type": "AllRegistersButPC"
      },
      {
        "name": "op",
        "wrapper": "Operand",
        "operands": [
          {
            "name": "immediate",
            "type": "T32ModifiedImmediate"
          }
        ]
      }
    ],
    "inputs": [
      {
        "name": "apsr",
        "type": "NZCV"
      },
      {
        "name": "rd",
        "type": "Register"
      }
    ]
  },
  "test-files": [
    {
      "type": "assembler",
      "test-cases": [
        {
          "name": "Operands",
          "operands": [
            "cond", "rd", "immediate"
          ],
          "operand-filter": "cond == 'al'"
        }
      ]
    },
    {
      "type": "simulator",
      "test-cases": [
        {
          "name": "Condition",
          "operands": [
            "cond"
          ],
          "inputs": [
            "apsr"
          ]
        },
        {
          "name": "ModifiedImmediate",
          "operands": [
            "immediate"
          ],
          "inputs": [
            "rd"
          ]
        }
      ]
    }
  ]
}