// Copyright 2016, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
//     and/or other materials provided with the distribution.
//   * Neither the name of ARM Limited nor the names of its contributors may be
//     used to endorse or promote products derived from this software without
//     specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

{
  "mnemonics" : [
    "Cmn",  // CMN{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1
    "Cmp",  // CMP{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1
    "Mov",  // MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
    "Movs", // MOVS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
    "Mvn",  // MVN{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
    "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
    "Teq",  // TEQ{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1
    "Tst"   // TST{<c>}{<q>} <Rn>, <Rm> {, <shift> #<amount> } ; A1
  ],
  "description" : {
    "operands": [
      {
        "name": "cond",
        "type": "Condition"
      },
      {
        "name": "rd",
        "type": "AllRegistersButPC"
      },
      {
        "name": "op",
        "wrapper": "Operand",
        "operands": [
          {
            "name": "rn",
            "type": "AllRegistersButPC"
          },
          {
            "name": "shift",
            "type": "Shift1To31"
          },
          {
            "name": "amount",
            "type": "ShiftAmount1To31"
          }
        ]
      }
    ],
    "inputs": [
      {
        "name": "apsr",
        "type": "NZCV"
      },
      {
        "name": "rd",
        "type": "Register"
      },
      {
        "name": "rn",
        "type": "Register"
      }
    ]
  },
  "test-files": [
    {
      "type": "assembler",
      "test-cases": [
        {
          "name": "Operands",
          "operands": [
            "cond", "rd", "rn", "shift", "amount"
          ],
          "operand-limit": 1000
        }
      ]
    },
    {
      "type": "simulator",
      "test-cases": [
        {
          "name": "Condition",
          "operands": [
            "cond"
          ],
          "inputs": [
            "apsr"
          ]
        },
        // Test combinations of registers values with rd == rn.
        {
          "name": "RdIsRn",
          "operands": [
            "rd", "rn"
          ],
          "inputs": [
            "rd", "rn"
          ],
          "operand-filter": "rd == rn",
          "input-filter": "rd == rn"
        },
        // Test combinations of registers values.
        {
          "name": "RdIsNotRn",
          "operands": [
            "rd", "rn"
          ],
          "inputs": [
            "rd", "rn"
          ],
          "operand-filter": "rd != rn",
          "operand-limit": 10,
          "input-limit": 200
        },
        // Test combinations of shift types and register values.
        {
          "name": "ShiftTypes",
          "operands": [
            "shift", "amount"
          ],
          "inputs": [
            "rn"
          ]
        }
      ]
    }
  ]
}