// Copyright 2016, VIXL authors
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are met:
//
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//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
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//     used to endorse or promote products derived from this software without
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// Test description for instructions of the following form:
//   MNEMONIC{<c>}.N <Rdm>, <Rdm>, ASR <Rs>
//   MNEMONIC{<c>}.N <Rdm>, <Rdm>, LSL <Rs>
//   MNEMONIC{<c>}.N <Rdm>, <Rdm>, LSR <Rs>
//   MNEMONIC{<c>}.N <Rdm>, <Rdm>, ROR <Rs>
//   MNEMONIC{<c>}.W <Rd>, <Rm>, <shift> <Rs>

{
  "mnemonics": [
    "Mov", // MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
           // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
           // MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
           // MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
           // MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; T2
    "Movs" // MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
           // MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
           // MOVS{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
           // MOVS{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
           // MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; T2
  ],
  "description" : {
    "operands": [
      {
        "name": "cond",
        "type": "Condition"
      },
      {
        "name": "rd",
        "type": "AllRegistersButPC"
      },
      {
        "name": "op",
        "wrapper": "Operand",
        "operands": [
          {
            "name": "rn",
            "type": "AllRegistersButPC"
          },
          {
            "name": "shift",
            "type": "Shift"
          },
          {
            "name": "rs",
            "type": "AllRegistersButPC"
          }
        ]
      }
    ],
    "inputs": [
      {
        "name": "apsr",
        "type": "NZCV"
      },
      {
        "name": "rd",
        "type": "Register"
      },
      {
        "name": "rn",
        "type": "Register"
      },
      {
        "name": "rs",
        "type": "RegisterShift"
      }
    ]
  },
  "test-files": [
    {
      "type": "assembler",
      "test-cases": [
        {
          "name": "Unconditional",
          "operands": [
            "cond", "rd", "rn", "shift", "rs"
          ],
          "operand-filter": "cond == 'al'",
          "operand-limit": 1000
        }
      ]
    },
    {
      "name": "narrow-out-it-block",
      "type": "assembler",
      "mnemonics" : [
        "Movs" // MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
               // MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
               // MOVS{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
               // MOVS{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
      ],
      "test-cases": [
        {
          "name": "OutITBlock",
          "operands": [
            "cond", "rd", "rn", "shift", "rs"
          ],
          "operand-filter": "cond == 'al' and rd == rn and register_is_low(rd) and register_is_low(rs)"
        }
      ]
    },
    {
      "name": "in-it-block",
      "type": "assembler",
      "mnemonics" : [
        "Mov" // MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1
              // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
              // MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1
              // MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1
      ],
      "test-cases": [
        {
          "name": "InITBlock",
          "operands": [
            "cond", "rd", "rn", "shift", "rs"
          ],
          // Generate an extra IT instruction.
          "in-it-block": "{cond}",
          "operand-filter": "cond != 'al' and rd == rn and register_is_low(rd) and register_is_low(rs)",
          "operand-limit": 1000
        }
      ]
    },
    {
      "type": "simulator",
      "test-cases": [
        {
          "name": "Condition",
          "operands": [
            "cond"
          ],
          "inputs": [
            "apsr"
          ]
        },
        // Test combinations of registers values with rd == rn.
        {
          "name": "RdIsRn",
          "operands": [
            "rd", "rn"
          ],
          "inputs": [
            "rd", "rn"
          ],
          "operand-filter": "rd == rn",
          "input-filter": "rd == rn"
        },
        // Test combinations of registers values with rd != rn.
        {
          "name": "RdIsNotRn",
          "operands": [
            "rd", "rn"
          ],
          "inputs": [
            "rd", "rn"
          ],
          "operand-filter": "rd != rn",
          "operand-limit": 10,
          "input-limit": 200
        },
        // Test combinations of shift types and register values.
        {
          "name": "ShiftTypes",
          "operands": [
            "rn", "shift", "rs"
          ],
          "inputs": [
            "rn", "rs"
          ],
          // Make sure the registers are different.
          "operand-filter": "rn == 'r1' and rs == 'r2'"
        }
      ]
    }
  ]
}