// Copyright 2016, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
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//     used to endorse or promote products derived from this software without
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// Test description for instructions of the following forms:
//   MNEMONIC{<c>}.N <Rd>, <Rn>, #0
//   MNEMONIC{<c>}.N <Rd>, <Rn>, #<imm3>
//   MNEMONIC{<c>}.N <Rdn>, <Rdn>, #<imm8>

{
  "mnemonics" : [
    "Add",  // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
            // ADD<c>{<q>} <Rdn>, #<imm8> ; T2
            // ADD<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
    "Adds", // ADDS{<q>} <Rd>, <Rn>, #<imm3> ; T1
            // ADDS{<q>} <Rdn>, #<imm8> ; T2
            // ADDS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
    "Rsb",  // RSB<c>{<q>} {<Rd>}, <Rn>, #0 ; T1
    "Rsbs", // RSBS{<q>} {<Rd>}, <Rn>, #0 ; T1
    "Sub",  // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
            // SUB<c>{<q>} <Rdn>, #<imm8> ; T2
            // SUB<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
    "Subs"  // SUBS{<q>} <Rd>, <Rn>, #<imm3> ; T1
            // SUBS{<q>} <Rdn>, #<imm8> ; T2
            // SUBS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
  ],
  "description" : {
    "operands": [
      {
        "name": "cond",
        "type": "Condition"
      },
      {
        "name": "rd",
        "type": "LowRegisters"
      },
      {
        "name": "rn",
        "type": "LowRegisters"
      },
      {
        "name": "op",
        "wrapper": "Operand",
        "operands": [
          {
            "name": "immediate",
            "type": "OffsetLowerThan256"
          }
        ]
      }
    ],
    "inputs": [
      {
        "name": "apsr",
        "type": "NZCV"
      },
      {
        "name": "rd",
        "type": "Register"
      },
      {
        "name": "rn",
        "type": "Register"
      }
    ]
  },
  "test-files": [
    {
      "type": "simulator",
      "test-cases": [
        {
          "name": "RdIsRn",
          "operands": [
            "cond", "rd", "rn", "immediate"
          ],
          "inputs": [
            "apsr", "rd", "rn"
          ],
          "operand-filter": "rd == rn",
          "operand-limit": 20,
          "input-filter": "rd == rn",
          "input-limit": 300
        },
        {
          "name": "RdIsNotRn",
          "operands": [
            "cond", "rd", "rn", "immediate"
          ],
          "inputs": [
            "apsr", "rd", "rn"
          ],
          "operand-filter": "rd != rn",
          "operand-limit": 20,
          "input-limit": 300
        },
        {
          "name": "Immediate",
          "operands": [
            "cond", "immediate"
          ],
          "inputs": [
            "apsr", "rn"
          ],
          "operand-limit": 20,
          "input-limit": 300
        }
      ]
    },
    // Test encodings with an 8 bit immediate and identical rn and rd.
    {
      "name": "imm8",
      "type": "assembler",
      "mnemonics" : [
        "Adds", // ADDS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
        "Subs"  // SUBS{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
      ],
      "test-cases": [
        {
          "name": "OutItBlock",
          "operands": [
            "cond", "rd", "rn", "immediate"
          ],
          "operand-filter": "cond == 'al' and rd == rn"
        }
      ]
    },
    {
      "name": "imm8-in-it-block",
      "type": "assembler",
      "mnemonics" : [
        "Add", // ADD<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
        "Sub"  // SUB<c>{<q>} {<Rdn>}, <Rdn>, #<imm8> ; T2
      ],
      "test-cases": [
        {
          "name": "InITBlock",
          "operands": [
            "cond", "rd", "rn", "immediate"
          ],
          // Generate an extra IT instruction.
          "in-it-block": "{cond}",
          "operand-filter": "cond != 'al' and rd == rn",
          "operand-limit": 1000
        }
      ]
    },
    // Test encodings with a 3 bit immediate and different rn and rd.
    {
      "name": "imm3",
      "type": "assembler",
      "mnemonics" : [
        "Adds", // ADDS{<q>} <Rd>, <Rn>, #<imm3> ; T1
        "Subs"  // SUBS{<q>} <Rd>, <Rn>, #<imm3> ; T1
      ],
      "test-cases": [
        {
          "name": "OutITBlock",
          "operands": [
            "cond", "rd", "rn", "immediate"
          ],
          "operand-filter": "cond == 'al' and int(immediate) <= 7"
        }
      ]
    },
    {
      "name": "imm3-in-it-block",
      "type": "assembler",
      "mnemonics" : [
        "Add", // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
        "Sub"  // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1
      ],
      "test-cases": [
        {
          "name": "InITBlock",
          "operands": [
            "cond", "rd", "rn", "immediate"
          ],
          // Generate an extra IT instruction.
          "in-it-block": "{cond}",
          "operand-filter": "cond != 'al' and int(immediate) <= 7",
          "operand-limit": 1000
        }
      ]
    },
    // Test special cases for Rsb and Rsbs where there is a special
    // encoding when the immediate is zero.
    {
      "name": "zero",
      "type": "assembler",
      "mnemonics" : [
        "Rsbs" // RSBS{<q>} {<Rd>}, <Rn>, #0 ; T1
      ],
      "test-cases": [
        {
          "name": "OutITBlock",
          "operands": [
            "cond", "rd", "rn", "immediate"
          ],
          "operand-filter": "cond == 'al' and int(immediate) == 0"
        }
      ]
    },
    {
      "name": "zero-in-it-block",
      "type": "assembler",
      "mnemonics" : [
        "Rsb" // RSB<c>{<q>} {<Rd>}, <Rn>, #0 ; T1
      ],
      "test-cases": [
        {
          "name": "InITBlock",
          "operands": [
            "cond", "rd", "rn", "immediate"
          ],
          // Generate an extra IT instruction.
          "in-it-block": "{cond}",
          "operand-filter": "cond != 'al' and int(immediate) == 0"
        }
      ]
    }
  ]
}