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// All rights reserved.
//
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//     this list of conditions and the following disclaimer.
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//     this list of conditions and the following disclaimer in the documentation
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// ---------------------------------------------------------------------
// This file is auto generated using tools/generate_simulator_traces.py.
//
// PLEASE DO NOT EDIT.
// ---------------------------------------------------------------------

#ifndef VIXL_SIM_FCVTMS_WS_TRACE_AARCH64_H_
#define VIXL_SIM_FCVTMS_WS_TRACE_AARCH64_H_

const int32_t kExpected_fcvtms_ws[] = {
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(10),
  INT32_C(0),
  INT32_C(2147483647),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(2),
  -INT32_C(2),
  -INT32_C(10),
  INT32_C(0),
  -INT32_C(2147483647) - 1,
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  INT32_C(8388608),
  INT32_C(8388609),
  INT32_C(8388610),
  INT32_C(8388611),
  INT32_C(16143410),
  INT32_C(16777212),
  INT32_C(16777213),
  INT32_C(16777214),
  INT32_C(16777215),
  INT32_C(4194304),
  INT32_C(4194304),
  INT32_C(4194305),
  INT32_C(4194305),
  INT32_C(8071705),
  INT32_C(8388606),
  INT32_C(8388606),
  INT32_C(8388607),
  INT32_C(8388607),
  INT32_C(2097152),
  INT32_C(2097152),
  INT32_C(2097152),
  INT32_C(2097152),
  INT32_C(4035852),
  INT32_C(4194303),
  INT32_C(4194303),
  INT32_C(4194303),
  INT32_C(4194303),
  -INT32_C(8388608),
  -INT32_C(8388609),
  -INT32_C(8388610),
  -INT32_C(8388611),
  -INT32_C(16143410),
  -INT32_C(16777212),
  -INT32_C(16777213),
  -INT32_C(16777214),
  -INT32_C(16777215),
  -INT32_C(4194304),
  -INT32_C(4194305),
  -INT32_C(4194305),
  -INT32_C(4194306),
  -INT32_C(8071705),
  -INT32_C(8388606),
  -INT32_C(8388607),
  -INT32_C(8388607),
  -INT32_C(8388608),
  -INT32_C(2097152),
  -INT32_C(2097153),
  -INT32_C(2097153),
  -INT32_C(2097153),
  -INT32_C(4035853),
  -INT32_C(4194303),
  -INT32_C(4194304),
  -INT32_C(4194304),
  -INT32_C(4194304),
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483520),
  INT32_C(2147483520),
  INT32_C(2147483647),
};
const unsigned kExpectedCount_fcvtms_ws = 104;

#endif  // VIXL_SIM_FCVTMS_WS_TRACE_AARCH64_H_