// Copyright 2015, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
//     and/or other materials provided with the distribution.
//   * Neither the name of ARM Limited nor the names of its contributors may be
//     used to endorse or promote products derived from this software without
//     specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// ---------------------------------------------------------------------
// This file is auto generated using tools/generate_simulator_traces.py.
//
// PLEASE DO NOT EDIT.
// ---------------------------------------------------------------------

#ifndef VIXL_SIM_FCVTNS_WD_TRACE_AARCH64_H_
#define VIXL_SIM_FCVTNS_WD_TRACE_AARCH64_H_

const int32_t kExpected_fcvtns_wd[] = {
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(2),
  INT32_C(10),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(2147483647),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(2),
  -INT32_C(10),
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  -INT32_C(2147483647) - 1,
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(2147483647),
  INT32_C(0),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(1),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  -INT32_C(2147483647) - 1,
  INT32_C(0),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(1),
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(0),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647) - 1,
  -INT32_C(2147483647),
  INT32_C(2147483646),
  INT32_C(2147483646),
  INT32_C(2147483646),
  INT32_C(2147483646),
  INT32_C(2147483646),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
  INT32_C(2147483647),
};
const unsigned kExpectedCount_fcvtns_wd = 207;

#endif  // VIXL_SIM_FCVTNS_WD_TRACE_AARCH64_H_