Add disassembler support for STDW and LDDW opcodes in v6 mode
Test: TH
Change-Id: I8084339e173357a23a6ffc0120f69c160ef4628f
diff --git a/disassembler.c b/disassembler.c
index 65b90d1..ad72982 100644
--- a/disassembler.c
+++ b/disassembler.c
@@ -32,6 +32,7 @@
char print_buf[1024];
char* buf_ptr;
int buf_remain;
+bool v6_mode = false;
__attribute__ ((format (printf, 1, 2) ))
static void bprintf(const char* format, ...) {
@@ -162,6 +163,7 @@
PRINT_OPCODE();
print_jump_target(*ptr2pc + imm, program_len);
} else {
+ v6_mode = true;
print_opcode("data");
bprintf("%d, ", imm);
uint32_t len = imm;
@@ -356,12 +358,20 @@
case LDDW_OPCODE:
case STDW_OPCODE:
PRINT_OPCODE();
- if (signed_imm > 0) {
- bprintf("r%u, [r%u+%d]", reg_num, reg_num ^ 1, signed_imm);
- } else if (signed_imm < 0) {
- bprintf("r%u, [r%u-%d]", reg_num, reg_num ^ 1, -signed_imm);
+ if (v6_mode) {
+ if (opcode == LDDW_OPCODE) {
+ bprintf("r%u, cnt=%d", reg_num, imm);
+ } else {
+ bprintf("cnt=%d, r%u", imm, reg_num);
+ }
} else {
- bprintf("r%u, [r%u]", reg_num, reg_num ^ 1);
+ if (signed_imm > 0) {
+ bprintf("r%u, [r%u+%d]", reg_num, reg_num ^ 1, signed_imm);
+ } else if (signed_imm < 0) {
+ bprintf("r%u, [r%u-%d]", reg_num, reg_num ^ 1, -signed_imm);
+ } else {
+ bprintf("r%u, [r%u]", reg_num, reg_num ^ 1);
+ }
}
break;
case WRITE_OPCODE: {
