[CodeGen] Rename functions PrintReg* to printReg*

LLVM Coding Standards:
  Function names should be verb phrases (as they represent actions), and
  command-like function should be imperative. The name should be camel
  case, and start with a lower case letter (e.g. openFile() or isFoo()).

Differential Revision: https://reviews.llvm.org/D40416

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319168 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/AMDGPU/GCNRegPressure.cpp b/lib/Target/AMDGPU/GCNRegPressure.cpp
index 17ff272..1204f86 100644
--- a/lib/Target/AMDGPU/GCNRegPressure.cpp
+++ b/lib/Target/AMDGPU/GCNRegPressure.cpp
@@ -49,7 +49,7 @@
       for (const auto &S : LI.subranges()) {
         if (!S.liveAt(SI)) continue;
         if (firstTime) {
-          dbgs() << "  " << PrintReg(Reg, MRI.getTargetRegisterInfo())
+          dbgs() << "  " << printReg(Reg, MRI.getTargetRegisterInfo())
                  << '\n';
           firstTime = false;
         }
@@ -441,12 +441,12 @@
   for (auto const &P : TrackedLR) {
     auto I = LISLR.find(P.first);
     if (I == LISLR.end()) {
-      dbgs() << "  " << PrintReg(P.first, TRI)
+      dbgs() << "  " << printReg(P.first, TRI)
              << ":L" << PrintLaneMask(P.second)
              << " isn't found in LIS reported set\n";
     }
     else if (I->second != P.second) {
-      dbgs() << "  " << PrintReg(P.first, TRI)
+      dbgs() << "  " << printReg(P.first, TRI)
         << " masks doesn't match: LIS reported "
         << PrintLaneMask(I->second)
         << ", tracked "
@@ -457,7 +457,7 @@
   for (auto const &P : LISLR) {
     auto I = TrackedLR.find(P.first);
     if (I == TrackedLR.end()) {
-      dbgs() << "  " << PrintReg(P.first, TRI)
+      dbgs() << "  " << printReg(P.first, TRI)
              << ":L" << PrintLaneMask(P.second)
              << " isn't found in tracked set\n";
     }
@@ -495,7 +495,7 @@
     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
     auto It = LiveRegs.find(Reg);
     if (It != LiveRegs.end() && It->second.any())
-      OS << ' ' << PrintVRegOrUnit(Reg, TRI) << ':'
+      OS << ' ' << printVRegOrUnit(Reg, TRI) << ':'
          << PrintLaneMask(It->second);
   }
   OS << '\n';