commit 247d86b41af526c167272cfa93558c963a2b4bd5
author Jeff Vander Stoep <jeffv@google.com> Tue Aug 11 14:27:44 2020 +0200
committer Jeff Vander Stoep <jeffv@google.com> Thu Aug 13 09:36:38 2020 +0200
tree 590387519cee745a9d5ce2ce7c8050d58b97d300
parent ad6790c3e6ce2ddece9abacd825a4cf8cc499009

Importing rustc-1.45.2

Change-Id: Idd187dd729f3089d9529753a17db5fbb40bacdeb

src/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp

diff --git a/src/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp b/src/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp
index 34a8195..4314aa6 100644
--- a/src/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp
+++ b/src/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp
@@ -68,7 +68,7 @@
       if (MI->getOpcode() != WebAssembly::BR_UNLESS)
         continue;
 
-      unsigned Cond = MI->getOperand(1).getReg();
+      Register Cond = MI->getOperand(1).getReg();
       bool Inverted = false;
 
       // Attempt to invert the condition in place.
@@ -188,7 +188,7 @@
       // If we weren't able to invert the condition in place. Insert an
       // instruction to invert it.
       if (!Inverted) {
-        unsigned Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
+        Register Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
         BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQZ_I32), Tmp)
             .addReg(Cond);
         MFI.stackifyVReg(Tmp);