|  | // SPDX-License-Identifier: GPL-2.0 OR X11 | 
|  | /* | 
|  | * Copyright (C) 2015 Amarula Solutions B.V. | 
|  | * Copyright (C) 2015 Engicam S.r.l. | 
|  | */ | 
|  |  | 
|  | #include <dt-bindings/gpio/gpio.h> | 
|  | #include <dt-bindings/clock/imx6qdl-clock.h> | 
|  | #include <dt-bindings/sound/fsl-imx-audmux.h> | 
|  |  | 
|  | / { | 
|  | memory@10000000 { | 
|  | device_type = "memory"; | 
|  | reg = <0x10000000 0x80000000>; | 
|  | }; | 
|  |  | 
|  | reg_1p8v: regulator-1p8v { | 
|  | compatible = "regulator-fixed"; | 
|  | regulator-name = "1P8V"; | 
|  | regulator-min-microvolt = <1800000>; | 
|  | regulator-max-microvolt = <1800000>; | 
|  | regulator-boot-on; | 
|  | regulator-always-on; | 
|  | }; | 
|  |  | 
|  | reg_2p5v: regulator-2p5v { | 
|  | compatible = "regulator-fixed"; | 
|  | regulator-name = "2P5V"; | 
|  | regulator-min-microvolt = <2500000>; | 
|  | regulator-max-microvolt = <2500000>; | 
|  | regulator-boot-on; | 
|  | regulator-always-on; | 
|  | }; | 
|  |  | 
|  | reg_3p3v: regulator-3p3v { | 
|  | compatible = "regulator-fixed"; | 
|  | regulator-name = "3P3V"; | 
|  | regulator-min-microvolt = <3300000>; | 
|  | regulator-max-microvolt = <3300000>; | 
|  | regulator-boot-on; | 
|  | regulator-always-on; | 
|  | }; | 
|  |  | 
|  | reg_sd3_vmmc: regulator-sd3-vmmc { | 
|  | compatible = "regulator-fixed"; | 
|  | regulator-name = "P3V3_SD3_SWITCHED"; | 
|  | regulator-min-microvolt = <3300000>; | 
|  | regulator-max-microvolt = <3300000>; | 
|  | gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; | 
|  | enable-active-high; | 
|  | }; | 
|  |  | 
|  | reg_sd4_vmmc: regulator-sd4-vmmc { | 
|  | compatible = "regulator-fixed"; | 
|  | regulator-name = "P3V3_SD4_SWITCHED"; | 
|  | regulator-min-microvolt = <3300000>; | 
|  | regulator-max-microvolt = <3300000>; | 
|  | regulator-boot-on; | 
|  | regulator-always-on; | 
|  | }; | 
|  |  | 
|  | reg_usb_h1_vbus: regulator-usb-h1-vbus { | 
|  | compatible = "regulator-fixed"; | 
|  | regulator-name = "usb_h1_vbus"; | 
|  | regulator-min-microvolt = <5000000>; | 
|  | regulator-max-microvolt = <5000000>; | 
|  | regulator-boot-on; | 
|  | regulator-always-on; | 
|  | }; | 
|  |  | 
|  | reg_usb_otg_vbus: regulator-usb-otg-vbus { | 
|  | compatible = "regulator-fixed"; | 
|  | regulator-name = "usb_otg_vbus"; | 
|  | regulator-min-microvolt = <5000000>; | 
|  | regulator-max-microvolt = <5000000>; | 
|  | regulator-boot-on; | 
|  | regulator-always-on; | 
|  | }; | 
|  |  | 
|  | usb_hub: usb-hub { | 
|  | compatible = "smsc,usb3503a"; | 
|  | pinctrl-names = "default"; | 
|  | pinctrl-0 = <&pinctrl_usbhub>; | 
|  | reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; | 
|  | clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>; | 
|  | clock-names = "refclk"; | 
|  | }; | 
|  |  | 
|  | sound { | 
|  | compatible = "simple-audio-card"; | 
|  | simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000"; | 
|  | simple-audio-card,format = "i2s"; | 
|  | simple-audio-card,bitclock-master = <&dailink_master>; | 
|  | simple-audio-card,frame-master = <&dailink_master>; | 
|  | simple-audio-card,widgets = | 
|  | "Microphone", "Mic Jack", | 
|  | "Headphone", "Headphone Jack", | 
|  | "Line", "Line In Jack", | 
|  | "Speaker", "Line Out Jack", | 
|  | "Speaker", "Ext Spk"; | 
|  | simple-audio-card,routing = | 
|  | "MIC_IN", "Mic Jack", | 
|  | "Mic Jack", "Mic Bias", | 
|  | "Headphone Jack", "HP_OUT"; | 
|  |  | 
|  | simple-audio-card,cpu { | 
|  | sound-dai = <&ssi1>; | 
|  | }; | 
|  |  | 
|  | dailink_master: simple-audio-card,codec { | 
|  | sound-dai = <&sgtl5000>; | 
|  | }; | 
|  | }; | 
|  | }; | 
|  |  | 
|  | &audmux { | 
|  | pinctrl-names = "default"; | 
|  | pinctrl-0 = <&pinctrl_audmux>; | 
|  | status = "okay"; | 
|  |  | 
|  | audmux_ssi1 { | 
|  | fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; | 
|  | fsl,port-config = < | 
|  | (IMX_AUDMUX_V2_PTCR_TFSDIR | | 
|  | IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | | 
|  | IMX_AUDMUX_V2_PTCR_TCLKDIR | | 
|  | IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | | 
|  | IMX_AUDMUX_V2_PTCR_SYN) | 
|  | IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) | 
|  | >; | 
|  | }; | 
|  |  | 
|  | audmux_aud4 { | 
|  | fsl,audmux-port = <MX51_AUDMUX_PORT4>; | 
|  | fsl,port-config = < | 
|  | IMX_AUDMUX_V2_PTCR_SYN | 
|  | IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) | 
|  | >; | 
|  | }; | 
|  | }; | 
|  |  | 
|  | &can1 { | 
|  | pinctrl-names = "default"; | 
|  | pinctrl-0 = <&pinctrl_can1>; | 
|  | xceiver-supply = <®_3p3v>; | 
|  | status = "okay"; | 
|  | }; | 
|  |  | 
|  | &can2 { | 
|  | pinctrl-names = "default"; | 
|  | pinctrl-0 = <&pinctrl_can2>; | 
|  | xceiver-supply = <®_3p3v>; | 
|  | status = "okay"; | 
|  | }; | 
|  |  | 
|  | &clks { | 
|  | assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; | 
|  | assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; | 
|  | }; | 
|  |  | 
|  | &fec { | 
|  | pinctrl-names = "default"; | 
|  | pinctrl-0 = <&pinctrl_enet>; | 
|  | phy-handle = <ð_phy>; | 
|  | phy-mode = "rgmii"; | 
|  | status = "okay"; | 
|  |  | 
|  | mdio { | 
|  | #address-cells = <1>; | 
|  | #size-cells = <0>; | 
|  |  | 
|  | eth_phy: ethernet-phy@0 { | 
|  | reg = <0x0>; | 
|  | rxc-skew-ps = <1140>; | 
|  | txc-skew-ps = <1140>; | 
|  | txen-skew-ps = <600>; | 
|  | rxdv-skew-ps = <240>; | 
|  | rxd0-skew-ps = <420>; | 
|  | rxd1-skew-ps = <600>; | 
|  | rxd2-skew-ps = <420>; | 
|  | rxd3-skew-ps = <240>; | 
|  | txd0-skew-ps = <60>; | 
|  | txd1-skew-ps = <60>; | 
|  | txd2-skew-ps = <60>; | 
|  | txd3-skew-ps = <240>; | 
|  | }; | 
|  | }; | 
|  | }; | 
|  |  | 
|  | &i2c1 { | 
|  | clock-frequency = <100000>; | 
|  | pinctrl-names = "default"; | 
|  | pinctrl-0 = <&pinctrl_i2c1>; | 
|  | status = "okay"; | 
|  | }; | 
|  |  | 
|  | &i2c2 { | 
|  | clock-frequency = <100000>; | 
|  | pinctrl-names = "default"; | 
|  | pinctrl-0 = <&pinctrl_i2c2>; | 
|  | status = "okay"; | 
|  | }; | 
|  |  | 
|  | &i2c3 { | 
|  | pinctrl-names = "default"; | 
|  | pinctrl-0 = <&pinctrl_i2c3>; | 
|  | status = "okay"; | 
|  |  | 
|  | sgtl5000: codec@a { | 
|  | #sound-dai-cells = <0>; | 
|  | compatible = "fsl,sgtl5000"; | 
|  | reg = <0x0a>; | 
|  | clocks = <&clks IMX6QDL_CLK_CKO>; | 
|  | VDDA-supply = <®_2p5v>; | 
|  | VDDIO-supply = <®_3p3v>; | 
|  | VDDD-supply = <®_1p8v>; | 
|  | }; | 
|  | }; | 
|  |  | 
|  | &pcie { | 
|  | pinctrl-names = "default"; | 
|  | pinctrl-0 = <&pinctrl_pcie>; | 
|  | reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; | 
|  | status = "okay"; | 
|  | }; | 
|  |  | 
|  | &ssi1 { | 
|  | fsl,mode = "i2s-slave"; | 
|  | status = "okay"; | 
|  | }; | 
|  |  | 
|  | &uart4 { | 
|  | pinctrl-names = "default"; | 
|  | pinctrl-0 = <&pinctrl_uart4>; | 
|  | status = "okay"; | 
|  | }; | 
|  |  | 
|  | &usbh1 { | 
|  | vbus-supply = <®_usb_h1_vbus>; | 
|  | disable-over-current; | 
|  | clocks = <&clks IMX6QDL_CLK_USBOH3>; | 
|  | status = "okay"; | 
|  | }; | 
|  |  | 
|  | &usbotg { | 
|  | vbus-supply = <®_usb_otg_vbus>; | 
|  | pinctrl-names = "default"; | 
|  | pinctrl-0 = <&pinctrl_usbotg>; | 
|  | disable-over-current; | 
|  | status = "okay"; | 
|  | }; | 
|  |  | 
|  | &usdhc1 { | 
|  | pinctrl-names = "default"; | 
|  | pinctrl-0 = <&pinctrl_usdhc1>; | 
|  | no-1-8-v; | 
|  | status = "okay"; | 
|  | }; | 
|  |  | 
|  | &usdhc3 { | 
|  | pinctrl-names = "default", "state_100mhz", "state_200mhz"; | 
|  | pinctrl-0 = <&pinctrl_usdhc3>; | 
|  | pinctrl-1 = <&pinctrl_usdhc3_100mhz>; | 
|  | pinctrl-2 = <&pinctrl_usdhc3_200mhz>; | 
|  | vmcc-supply = <®_sd3_vmmc>; | 
|  | cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; | 
|  | bus-width = <4>; | 
|  | no-1-8-v; | 
|  | status = "okay"; | 
|  | }; | 
|  |  | 
|  | &usdhc4 { | 
|  | pinctrl-names = "default", "state_100mhz", "state_200mhz"; | 
|  | pinctrl-0 = <&pinctrl_usdhc4>; | 
|  | pinctrl-1 = <&pinctrl_usdhc4_100mhz>; | 
|  | pinctrl-2 = <&pinctrl_usdhc4_200mhz>; | 
|  | vmcc-supply = <®_sd4_vmmc>; | 
|  | bus-width = <8>; | 
|  | no-1-8-v; | 
|  | non-removable; | 
|  | status = "okay"; | 
|  | }; | 
|  |  | 
|  | &iomuxc { | 
|  | pinctrl_audmux: audmuxgrp { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0 | 
|  | MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0 | 
|  | MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 | 
|  | MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0 | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_enet: enetgrp { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0 | 
|  | MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0 | 
|  | MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030 | 
|  | MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030 | 
|  | MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030 | 
|  | MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030 | 
|  | MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030 | 
|  | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 | 
|  | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0 | 
|  | MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030 | 
|  | MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030 | 
|  | MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030 | 
|  | MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030 | 
|  | MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030 | 
|  | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 | 
|  | MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0 | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_can1: can1grp { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 | 
|  | MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_can2: can2grp { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 | 
|  | MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_i2c1: i2c1grp { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | 
|  | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_i2c2: i2c2grp { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | 
|  | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_i2c3: i2c3grp { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1 | 
|  | MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 | 
|  | MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0 | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_pcie: pciegrp { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059	/* PCIe Reset */ | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_uart4: uart4grp { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | 
|  | MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_usbhub: usbhubgrp { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_GPIO_6__GPIO1_IO06  0x1f059	/* HUB USB Reset */ | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_usbotg: usbotggrp { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_usdhc1: usdhc1grp { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071 | 
|  | MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071 | 
|  | MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 | 
|  | MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 | 
|  | MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 | 
|  | MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_usdhc3: usdhc3grp { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17070 | 
|  | MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10070 | 
|  | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070 | 
|  | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070 | 
|  | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070 | 
|  | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070 | 
|  | MX6QDL_PAD_GPIO_1__GPIO1_IO01  0x1f059	/* CD */ | 
|  | MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1f059	/* PWR */ | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170B1 | 
|  | MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100B1 | 
|  | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1 | 
|  | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1 | 
|  | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1 | 
|  | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1 | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170F9 | 
|  | MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100F9 | 
|  | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 | 
|  | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 | 
|  | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 | 
|  | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_usdhc4: usdhc4grp { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17070 | 
|  | MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10070 | 
|  | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070 | 
|  | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070 | 
|  | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070 | 
|  | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070 | 
|  | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070 | 
|  | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070 | 
|  | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070 | 
|  | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070 | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_usdhc4_100mhz: usdhc4grp_100mhz { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_SD4_CMD__SD4_CMD    0x170B1 | 
|  | MX6QDL_PAD_SD4_CLK__SD4_CLK    0x100B1 | 
|  | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1 | 
|  | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1 | 
|  | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1 | 
|  | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1 | 
|  | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1 | 
|  | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1 | 
|  | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1 | 
|  | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1 | 
|  | >; | 
|  | }; | 
|  |  | 
|  | pinctrl_usdhc4_200mhz: usdhc4grp_200mhz { | 
|  | fsl,pins = < | 
|  | MX6QDL_PAD_SD4_CMD__SD4_CMD    0x170F9 | 
|  | MX6QDL_PAD_SD4_CLK__SD4_CLK    0x100F9 | 
|  | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9 | 
|  | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9 | 
|  | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9 | 
|  | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9 | 
|  | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9 | 
|  | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9 | 
|  | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9 | 
|  | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9 | 
|  | >; | 
|  | }; | 
|  | }; |