| /* SPDX-License-Identifier: GPL-2.0 | |
| * | |
| * Copyright (C) 2018 Renesas Electronics Corp. | |
| * | |
| */ | |
| #ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ | |
| #define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ | |
| #include <dt-bindings/clock/renesas-cpg-mssr.h> | |
| /* R7S9210 CPG Core Clocks */ | |
| #define R7S9210_CLK_I 0 | |
| #define R7S9210_CLK_G 1 | |
| #define R7S9210_CLK_B 2 | |
| #define R7S9210_CLK_P1 3 | |
| #define R7S9210_CLK_P1C 4 | |
| #define R7S9210_CLK_P0 5 | |
| #endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */ |