| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2024 Qualcomm Innovation Center. All rights reserved. |
| */ |
| |
| #ifndef QCOM_PHY_QMP_PCS_V6_30_H_ |
| #define QCOM_PHY_QMP_PCS_V6_30_H_ |
| |
| /* Only for QMP V6_30 PHY - PCIe PCS registers */ |
| #define QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2 0x0cc |
| #define QPHY_V6_30_PCS_G3S2_PRE_GAIN 0x17c |
| #define QPHY_V6_30_PCS_RX_SIGDET_LVL 0x194 |
| #define QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7 0x1dc |
| #define QPHY_V6_30_PCS_TX_RX_CONFIG 0x1e0 |
| #define QPHY_V6_30_PCS_TX_RX_CONFIG2 0x1e4 |
| #define QPHY_V6_30_PCS_EQ_CONFIG4 0x1fc |
| #define QPHY_V6_30_PCS_EQ_CONFIG5 0x200 |
| |
| #endif |
