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Cezary Gapinskid57a9842018-12-24 23:00:27 +01001// SPDX-License-Identifier: GPL-2.0
2//
3// STMicroelectronics STM32 SPI Controller driver (master mode only)
4//
5// Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6// Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
7
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02008#include <linux/debugfs.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +020012#include <linux/interrupt.h>
13#include <linux/iopoll.h>
14#include <linux/module.h>
15#include <linux/of_platform.h>
Amelie Delaunaydb96bf92020-08-10 09:12:37 +020016#include <linux/pinctrl/consumer.h>
Amelie Delaunay038ac862017-06-27 17:45:18 +020017#include <linux/pm_runtime.h>
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +020018#include <linux/reset.h>
19#include <linux/spi/spi.h>
20
21#define DRIVER_NAME "spi_stm32"
22
Cezary Gapinski00505ed2018-12-24 23:00:38 +010023/* STM32F4 SPI registers */
24#define STM32F4_SPI_CR1 0x00
25#define STM32F4_SPI_CR2 0x04
26#define STM32F4_SPI_SR 0x08
27#define STM32F4_SPI_DR 0x0C
28#define STM32F4_SPI_I2SCFGR 0x1C
29
30/* STM32F4_SPI_CR1 bit fields */
31#define STM32F4_SPI_CR1_CPHA BIT(0)
32#define STM32F4_SPI_CR1_CPOL BIT(1)
33#define STM32F4_SPI_CR1_MSTR BIT(2)
34#define STM32F4_SPI_CR1_BR_SHIFT 3
35#define STM32F4_SPI_CR1_BR GENMASK(5, 3)
36#define STM32F4_SPI_CR1_SPE BIT(6)
37#define STM32F4_SPI_CR1_LSBFRST BIT(7)
38#define STM32F4_SPI_CR1_SSI BIT(8)
39#define STM32F4_SPI_CR1_SSM BIT(9)
40#define STM32F4_SPI_CR1_RXONLY BIT(10)
41#define STM32F4_SPI_CR1_DFF BIT(11)
42#define STM32F4_SPI_CR1_CRCNEXT BIT(12)
43#define STM32F4_SPI_CR1_CRCEN BIT(13)
44#define STM32F4_SPI_CR1_BIDIOE BIT(14)
45#define STM32F4_SPI_CR1_BIDIMODE BIT(15)
46#define STM32F4_SPI_CR1_BR_MIN 0
47#define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
48
49/* STM32F4_SPI_CR2 bit fields */
50#define STM32F4_SPI_CR2_RXDMAEN BIT(0)
51#define STM32F4_SPI_CR2_TXDMAEN BIT(1)
52#define STM32F4_SPI_CR2_SSOE BIT(2)
53#define STM32F4_SPI_CR2_FRF BIT(4)
54#define STM32F4_SPI_CR2_ERRIE BIT(5)
55#define STM32F4_SPI_CR2_RXNEIE BIT(6)
56#define STM32F4_SPI_CR2_TXEIE BIT(7)
57
58/* STM32F4_SPI_SR bit fields */
59#define STM32F4_SPI_SR_RXNE BIT(0)
60#define STM32F4_SPI_SR_TXE BIT(1)
61#define STM32F4_SPI_SR_CHSIDE BIT(2)
62#define STM32F4_SPI_SR_UDR BIT(3)
63#define STM32F4_SPI_SR_CRCERR BIT(4)
64#define STM32F4_SPI_SR_MODF BIT(5)
65#define STM32F4_SPI_SR_OVR BIT(6)
66#define STM32F4_SPI_SR_BSY BIT(7)
67#define STM32F4_SPI_SR_FRE BIT(8)
68
69/* STM32F4_SPI_I2SCFGR bit fields */
70#define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
71
72/* STM32F4 SPI Baud Rate min/max divisor */
73#define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
74#define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
75
Cezary Gapinski860266302018-12-24 23:00:33 +010076/* STM32H7 SPI registers */
77#define STM32H7_SPI_CR1 0x00
78#define STM32H7_SPI_CR2 0x04
79#define STM32H7_SPI_CFG1 0x08
80#define STM32H7_SPI_CFG2 0x0C
81#define STM32H7_SPI_IER 0x10
82#define STM32H7_SPI_SR 0x14
83#define STM32H7_SPI_IFCR 0x18
84#define STM32H7_SPI_TXDR 0x20
85#define STM32H7_SPI_RXDR 0x30
86#define STM32H7_SPI_I2SCFGR 0x50
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +020087
Cezary Gapinski860266302018-12-24 23:00:33 +010088/* STM32H7_SPI_CR1 bit fields */
89#define STM32H7_SPI_CR1_SPE BIT(0)
90#define STM32H7_SPI_CR1_MASRX BIT(8)
91#define STM32H7_SPI_CR1_CSTART BIT(9)
92#define STM32H7_SPI_CR1_CSUSP BIT(10)
93#define STM32H7_SPI_CR1_HDDIR BIT(11)
94#define STM32H7_SPI_CR1_SSI BIT(12)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +020095
Cezary Gapinski860266302018-12-24 23:00:33 +010096/* STM32H7_SPI_CR2 bit fields */
97#define STM32H7_SPI_CR2_TSIZE_SHIFT 0
98#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +020099
Cezary Gapinski860266302018-12-24 23:00:33 +0100100/* STM32H7_SPI_CFG1 bit fields */
101#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
102#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
103#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
104#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
105#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
106#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
107#define STM32H7_SPI_CFG1_MBR_SHIFT 28
108#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
109#define STM32H7_SPI_CFG1_MBR_MIN 0
110#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200111
Cezary Gapinski860266302018-12-24 23:00:33 +0100112/* STM32H7_SPI_CFG2 bit fields */
113#define STM32H7_SPI_CFG2_MIDI_SHIFT 4
114#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
115#define STM32H7_SPI_CFG2_COMM_SHIFT 17
116#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
117#define STM32H7_SPI_CFG2_SP_SHIFT 19
118#define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
119#define STM32H7_SPI_CFG2_MASTER BIT(22)
120#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
121#define STM32H7_SPI_CFG2_CPHA BIT(24)
122#define STM32H7_SPI_CFG2_CPOL BIT(25)
123#define STM32H7_SPI_CFG2_SSM BIT(26)
124#define STM32H7_SPI_CFG2_AFCNTR BIT(31)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200125
Cezary Gapinski860266302018-12-24 23:00:33 +0100126/* STM32H7_SPI_IER bit fields */
127#define STM32H7_SPI_IER_RXPIE BIT(0)
128#define STM32H7_SPI_IER_TXPIE BIT(1)
129#define STM32H7_SPI_IER_DXPIE BIT(2)
130#define STM32H7_SPI_IER_EOTIE BIT(3)
131#define STM32H7_SPI_IER_TXTFIE BIT(4)
132#define STM32H7_SPI_IER_OVRIE BIT(6)
133#define STM32H7_SPI_IER_MODFIE BIT(9)
134#define STM32H7_SPI_IER_ALL GENMASK(10, 0)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200135
Cezary Gapinski860266302018-12-24 23:00:33 +0100136/* STM32H7_SPI_SR bit fields */
137#define STM32H7_SPI_SR_RXP BIT(0)
138#define STM32H7_SPI_SR_TXP BIT(1)
139#define STM32H7_SPI_SR_EOT BIT(3)
140#define STM32H7_SPI_SR_OVR BIT(6)
141#define STM32H7_SPI_SR_MODF BIT(9)
142#define STM32H7_SPI_SR_SUSP BIT(11)
143#define STM32H7_SPI_SR_RXPLVL_SHIFT 13
144#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
145#define STM32H7_SPI_SR_RXWNE BIT(15)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200146
Cezary Gapinski860266302018-12-24 23:00:33 +0100147/* STM32H7_SPI_IFCR bit fields */
148#define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200149
Cezary Gapinski860266302018-12-24 23:00:33 +0100150/* STM32H7_SPI_I2SCFGR bit fields */
151#define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200152
Cezary Gapinski860266302018-12-24 23:00:33 +0100153/* STM32H7 SPI Master Baud Rate min/max divisor */
154#define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
155#define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200156
Cezary Gapinski9d5fce12018-12-24 23:00:35 +0100157/* STM32H7 SPI Communication mode */
158#define STM32H7_SPI_FULL_DUPLEX 0
159#define STM32H7_SPI_SIMPLEX_TX 1
160#define STM32H7_SPI_SIMPLEX_RX 2
161#define STM32H7_SPI_HALF_DUPLEX 3
162
163/* SPI Communication type */
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200164#define SPI_FULL_DUPLEX 0
165#define SPI_SIMPLEX_TX 1
166#define SPI_SIMPLEX_RX 2
Cezary Gapinski9d5fce12018-12-24 23:00:35 +0100167#define SPI_3WIRE_TX 3
168#define SPI_3WIRE_RX 4
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200169
170#define SPI_1HZ_NS 1000000000
171
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100172/*
173 * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
174 * without fifo buffers.
175 */
176#define SPI_DMA_MIN_BYTES 16
177
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200178/**
Alain Volmat1c52be82020-03-20 14:44:17 +0100179 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
Cezary Gapinski55166852018-12-24 23:00:37 +0100180 * @reg: register offset
181 * @mask: bitfield mask
182 * @shift: left shift
183 */
184struct stm32_spi_reg {
185 int reg;
186 int mask;
187 int shift;
188};
189
190/**
Alain Volmat1c52be82020-03-20 14:44:17 +0100191 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
192 * @en: enable register and SPI enable bit
193 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
194 * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
195 * @cpol: clock polarity register and polarity bit
196 * @cpha: clock phase register and phase bit
197 * @lsb_first: LSB transmitted first register and bit
198 * @br: baud rate register and bitfields
199 * @rx: SPI RX data register
200 * @tx: SPI TX data register
Cezary Gapinski55166852018-12-24 23:00:37 +0100201 */
202struct stm32_spi_regspec {
203 const struct stm32_spi_reg en;
204 const struct stm32_spi_reg dma_rx_en;
205 const struct stm32_spi_reg dma_tx_en;
206 const struct stm32_spi_reg cpol;
207 const struct stm32_spi_reg cpha;
208 const struct stm32_spi_reg lsb_first;
209 const struct stm32_spi_reg br;
210 const struct stm32_spi_reg rx;
211 const struct stm32_spi_reg tx;
212};
213
214struct stm32_spi;
215
216/**
Alain Volmat1c52be82020-03-20 14:44:17 +0100217 * struct stm32_spi_cfg - stm32 compatible configuration data
Cezary Gapinski55166852018-12-24 23:00:37 +0100218 * @regs: registers descriptions
219 * @get_fifo_size: routine to get fifo size
220 * @get_bpw_mask: routine to get bits per word mask
221 * @disable: routine to disable controller
222 * @config: routine to configure controller as SPI Master
223 * @set_bpw: routine to configure registers to for bits per word
224 * @set_mode: routine to configure registers to desired mode
225 * @set_data_idleness: optional routine to configure registers to desired idle
226 * time between frames (if driver has this functionality)
Alain Volmat1c52be82020-03-20 14:44:17 +0100227 * @set_number_of_data: optional routine to configure registers to desired
Cezary Gapinski55166852018-12-24 23:00:37 +0100228 * number of data (if driver has this functionality)
229 * @can_dma: routine to determine if the transfer is eligible for DMA use
230 * @transfer_one_dma_start: routine to start transfer a single spi_transfer
231 * using DMA
Alain Volmat1c52be82020-03-20 14:44:17 +0100232 * @dma_rx_cb: routine to call after DMA RX channel operation is complete
233 * @dma_tx_cb: routine to call after DMA TX channel operation is complete
Cezary Gapinski55166852018-12-24 23:00:37 +0100234 * @transfer_one_irq: routine to configure interrupts for driver
235 * @irq_handler_event: Interrupt handler for SPI controller events
236 * @irq_handler_thread: thread of interrupt handler for SPI controller
237 * @baud_rate_div_min: minimum baud rate divisor
238 * @baud_rate_div_max: maximum baud rate divisor
239 * @has_fifo: boolean to know if fifo is used for driver
240 * @has_startbit: boolean to know if start bit is used to start transfer
241 */
242struct stm32_spi_cfg {
243 const struct stm32_spi_regspec *regs;
244 int (*get_fifo_size)(struct stm32_spi *spi);
245 int (*get_bpw_mask)(struct stm32_spi *spi);
246 void (*disable)(struct stm32_spi *spi);
247 int (*config)(struct stm32_spi *spi);
248 void (*set_bpw)(struct stm32_spi *spi);
249 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
250 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
251 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
252 void (*transfer_one_dma_start)(struct stm32_spi *spi);
253 void (*dma_rx_cb)(void *data);
254 void (*dma_tx_cb)(void *data);
255 int (*transfer_one_irq)(struct stm32_spi *spi);
256 irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
257 irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
258 unsigned int baud_rate_div_min;
259 unsigned int baud_rate_div_max;
260 bool has_fifo;
261};
262
263/**
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200264 * struct stm32_spi - private data of the SPI controller
265 * @dev: driver model representation of the controller
266 * @master: controller master interface
Cezary Gapinski55166852018-12-24 23:00:37 +0100267 * @cfg: compatible configuration data
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200268 * @base: virtual memory area
269 * @clk: hw kernel clock feeding the SPI clock generator
270 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
271 * @rst: SPI controller reset line
272 * @lock: prevent I/O concurrent access
273 * @irq: SPI controller interrupt line
274 * @fifo_size: size of the embedded fifo in bytes
275 * @cur_midi: master inter-data idleness in ns
276 * @cur_speed: speed configured in Hz
277 * @cur_bpw: number of bits in a single SPI data frame
278 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
279 * @cur_comm: SPI communication mode
280 * @cur_xferlen: current transfer length in bytes
281 * @cur_usedma: boolean to know if dma is used in current transfer
282 * @tx_buf: data to be written, or NULL
283 * @rx_buf: data to be read, or NULL
284 * @tx_len: number of data to be written in bytes
285 * @rx_len: number of data to be read in bytes
286 * @dma_tx: dma channel for TX transfer
287 * @dma_rx: dma channel for RX transfer
288 * @phys_addr: SPI registers physical base address
289 */
290struct stm32_spi {
291 struct device *dev;
292 struct spi_master *master;
Cezary Gapinski55166852018-12-24 23:00:37 +0100293 const struct stm32_spi_cfg *cfg;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200294 void __iomem *base;
295 struct clk *clk;
296 u32 clk_rate;
297 struct reset_control *rst;
298 spinlock_t lock; /* prevent I/O concurrent access */
299 int irq;
300 unsigned int fifo_size;
301
302 unsigned int cur_midi;
303 unsigned int cur_speed;
304 unsigned int cur_bpw;
305 unsigned int cur_fthlv;
306 unsigned int cur_comm;
307 unsigned int cur_xferlen;
308 bool cur_usedma;
309
310 const void *tx_buf;
311 void *rx_buf;
312 int tx_len;
313 int rx_len;
314 struct dma_chan *dma_tx;
315 struct dma_chan *dma_rx;
316 dma_addr_t phys_addr;
317};
318
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100319static const struct stm32_spi_regspec stm32f4_spi_regspec = {
320 .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
321
322 .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
323 .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
324
325 .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
326 .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
327 .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
328 .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
329
330 .rx = { STM32F4_SPI_DR },
331 .tx = { STM32F4_SPI_DR },
332};
333
Cezary Gapinski55166852018-12-24 23:00:37 +0100334static const struct stm32_spi_regspec stm32h7_spi_regspec = {
335 /* SPI data transfer is enabled but spi_ker_ck is idle.
336 * CFG1 and CFG2 registers are write protected when SPE is enabled.
337 */
338 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
339
340 .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
341 .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
342
343 .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
344 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
345 .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
346 .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
347 STM32H7_SPI_CFG1_MBR_SHIFT },
348
349 .rx = { STM32H7_SPI_RXDR },
350 .tx = { STM32H7_SPI_TXDR },
351};
352
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200353static inline void stm32_spi_set_bits(struct stm32_spi *spi,
354 u32 offset, u32 bits)
355{
356 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
357 spi->base + offset);
358}
359
360static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
361 u32 offset, u32 bits)
362{
363 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
364 spi->base + offset);
365}
366
367/**
Cezary Gapinski55166852018-12-24 23:00:37 +0100368 * stm32h7_spi_get_fifo_size - Return fifo size
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200369 * @spi: pointer to the spi controller data structure
370 */
Cezary Gapinski55166852018-12-24 23:00:37 +0100371static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200372{
373 unsigned long flags;
374 u32 count = 0;
375
376 spin_lock_irqsave(&spi->lock, flags);
377
Cezary Gapinski860266302018-12-24 23:00:33 +0100378 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200379
Cezary Gapinski860266302018-12-24 23:00:33 +0100380 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
381 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200382
Cezary Gapinski860266302018-12-24 23:00:33 +0100383 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200384
385 spin_unlock_irqrestore(&spi->lock, flags);
386
387 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
388
389 return count;
390}
391
392/**
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100393 * stm32f4_spi_get_bpw_mask - Return bits per word mask
394 * @spi: pointer to the spi controller data structure
395 */
396static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
397{
398 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
399 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
400}
401
402/**
Cezary Gapinski55166852018-12-24 23:00:37 +0100403 * stm32h7_spi_get_bpw_mask - Return bits per word mask
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200404 * @spi: pointer to the spi controller data structure
405 */
Cezary Gapinski55166852018-12-24 23:00:37 +0100406static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200407{
408 unsigned long flags;
409 u32 cfg1, max_bpw;
410
411 spin_lock_irqsave(&spi->lock, flags);
412
413 /*
414 * The most significant bit at DSIZE bit field is reserved when the
415 * maximum data size of periperal instances is limited to 16-bit
416 */
Cezary Gapinski860266302018-12-24 23:00:33 +0100417 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200418
Cezary Gapinski860266302018-12-24 23:00:33 +0100419 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
420 max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
421 STM32H7_SPI_CFG1_DSIZE_SHIFT;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200422 max_bpw += 1;
423
424 spin_unlock_irqrestore(&spi->lock, flags);
425
426 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
427
428 return SPI_BPW_RANGE_MASK(4, max_bpw);
429}
430
431/**
Cezary Gapinski9d5fce12018-12-24 23:00:35 +0100432 * stm32_spi_prepare_mbr - Determine baud rate divisor value
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200433 * @spi: pointer to the spi controller data structure
434 * @speed_hz: requested speed
Cezary Gapinski9d5fce12018-12-24 23:00:35 +0100435 * @min_div: minimum baud rate divisor
436 * @max_div: maximum baud rate divisor
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200437 *
Cezary Gapinski9d5fce12018-12-24 23:00:35 +0100438 * Return baud rate divisor value in case of success or -EINVAL
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200439 */
Cezary Gapinski9d5fce12018-12-24 23:00:35 +0100440static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
441 u32 min_div, u32 max_div)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200442{
443 u32 div, mbrdiv;
444
Amelie Delaunay9cc61972020-08-10 09:12:36 +0200445 /* Ensure spi->clk_rate is even */
446 div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200447
448 /*
449 * SPI framework set xfer->speed_hz to master->max_speed_hz if
450 * xfer->speed_hz is greater than master->max_speed_hz, and it returns
451 * an error when xfer->speed_hz is lower than master->min_speed_hz, so
452 * no need to check it there.
453 * However, we need to ensure the following calculations.
454 */
Cezary Gapinski9d5fce12018-12-24 23:00:35 +0100455 if ((div < min_div) || (div > max_div))
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200456 return -EINVAL;
457
458 /* Determine the first power of 2 greater than or equal to div */
Amelie Delaunay128ebb82017-06-27 17:45:17 +0200459 if (div & (div - 1))
460 mbrdiv = fls(div);
461 else
462 mbrdiv = fls(div) - 1;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200463
464 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
465
466 return mbrdiv - 1;
467}
468
469/**
Cezary Gapinski55166852018-12-24 23:00:37 +0100470 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200471 * @spi: pointer to the spi controller data structure
Amelie Delaunay3373e902020-08-10 09:12:35 +0200472 * @xfer_len: length of the message to be transferred
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200473 */
Amelie Delaunay3373e902020-08-10 09:12:35 +0200474static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200475{
Amelie Delaunay3373e902020-08-10 09:12:35 +0200476 u32 fthlv, half_fifo, packet;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200477
478 /* data packet should not exceed 1/2 of fifo space */
479 half_fifo = (spi->fifo_size / 2);
480
Amelie Delaunay3373e902020-08-10 09:12:35 +0200481 /* data_packet should not exceed transfer length */
482 if (half_fifo > xfer_len)
483 packet = xfer_len;
Amelie Delaunay128ebb82017-06-27 17:45:17 +0200484 else
Amelie Delaunay3373e902020-08-10 09:12:35 +0200485 packet = half_fifo;
486
487 if (spi->cur_bpw <= 8)
488 fthlv = packet;
489 else if (spi->cur_bpw <= 16)
490 fthlv = packet / 2;
491 else
492 fthlv = packet / 4;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200493
494 /* align packet size with data registers access */
495 if (spi->cur_bpw > 8)
Roman Guskov7a30d662020-12-21 13:35:32 +0100496 fthlv += (fthlv % 2) ? 1 : 0;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200497 else
Roman Guskov7a30d662020-12-21 13:35:32 +0100498 fthlv += (fthlv % 4) ? (4 - (fthlv % 4)) : 0;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200499
Amelie Delaunay3373e902020-08-10 09:12:35 +0200500 if (!fthlv)
501 fthlv = 1;
502
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200503 return fthlv;
504}
505
506/**
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100507 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
508 * @spi: pointer to the spi controller data structure
509 *
510 * Read from tx_buf depends on remaining bytes to avoid to read beyond
511 * tx_buf end.
512 */
513static void stm32f4_spi_write_tx(struct stm32_spi *spi)
514{
515 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
516 STM32F4_SPI_SR_TXE)) {
517 u32 offs = spi->cur_xferlen - spi->tx_len;
518
519 if (spi->cur_bpw == 16) {
520 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
521
522 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
523 spi->tx_len -= sizeof(u16);
524 } else {
525 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
526
527 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
528 spi->tx_len -= sizeof(u8);
529 }
530 }
531
532 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
533}
534
535/**
Cezary Gapinski55166852018-12-24 23:00:37 +0100536 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200537 * @spi: pointer to the spi controller data structure
538 *
539 * Read from tx_buf depends on remaining bytes to avoid to read beyond
540 * tx_buf end.
541 */
Cezary Gapinski55166852018-12-24 23:00:37 +0100542static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200543{
544 while ((spi->tx_len > 0) &&
Cezary Gapinski860266302018-12-24 23:00:33 +0100545 (readl_relaxed(spi->base + STM32H7_SPI_SR) &
546 STM32H7_SPI_SR_TXP)) {
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200547 u32 offs = spi->cur_xferlen - spi->tx_len;
548
549 if (spi->tx_len >= sizeof(u32)) {
550 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
551
Cezary Gapinski860266302018-12-24 23:00:33 +0100552 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200553 spi->tx_len -= sizeof(u32);
554 } else if (spi->tx_len >= sizeof(u16)) {
555 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
556
Cezary Gapinski860266302018-12-24 23:00:33 +0100557 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200558 spi->tx_len -= sizeof(u16);
559 } else {
560 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
561
Cezary Gapinski860266302018-12-24 23:00:33 +0100562 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200563 spi->tx_len -= sizeof(u8);
564 }
565 }
566
567 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
568}
569
570/**
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100571 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
572 * @spi: pointer to the spi controller data structure
573 *
574 * Write in rx_buf depends on remaining bytes to avoid to write beyond
575 * rx_buf end.
576 */
577static void stm32f4_spi_read_rx(struct stm32_spi *spi)
578{
579 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
580 STM32F4_SPI_SR_RXNE)) {
581 u32 offs = spi->cur_xferlen - spi->rx_len;
582
583 if (spi->cur_bpw == 16) {
584 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
585
586 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
587 spi->rx_len -= sizeof(u16);
588 } else {
589 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
590
591 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
592 spi->rx_len -= sizeof(u8);
593 }
594 }
595
596 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
597}
598
599/**
Cezary Gapinski55166852018-12-24 23:00:37 +0100600 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200601 * @spi: pointer to the spi controller data structure
Alain Volmat1c52be82020-03-20 14:44:17 +0100602 * @flush: boolean indicating that FIFO should be flushed
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200603 *
604 * Write in rx_buf depends on remaining bytes to avoid to write beyond
605 * rx_buf end.
606 */
Cezary Gapinski55166852018-12-24 23:00:37 +0100607static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200608{
Cezary Gapinski860266302018-12-24 23:00:33 +0100609 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
610 u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
611 STM32H7_SPI_SR_RXPLVL_SHIFT;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200612
613 while ((spi->rx_len > 0) &&
Cezary Gapinski860266302018-12-24 23:00:33 +0100614 ((sr & STM32H7_SPI_SR_RXP) ||
615 (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200616 u32 offs = spi->cur_xferlen - spi->rx_len;
617
618 if ((spi->rx_len >= sizeof(u32)) ||
Cezary Gapinski860266302018-12-24 23:00:33 +0100619 (flush && (sr & STM32H7_SPI_SR_RXWNE))) {
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200620 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
621
Cezary Gapinski860266302018-12-24 23:00:33 +0100622 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200623 spi->rx_len -= sizeof(u32);
624 } else if ((spi->rx_len >= sizeof(u16)) ||
625 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
626 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
627
Cezary Gapinski860266302018-12-24 23:00:33 +0100628 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200629 spi->rx_len -= sizeof(u16);
630 } else {
631 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
632
Cezary Gapinski860266302018-12-24 23:00:33 +0100633 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200634 spi->rx_len -= sizeof(u8);
635 }
636
Cezary Gapinski860266302018-12-24 23:00:33 +0100637 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
638 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
639 STM32H7_SPI_SR_RXPLVL_SHIFT;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200640 }
641
642 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
643 flush ? "(flush)" : "", spi->rx_len);
644}
645
646/**
647 * stm32_spi_enable - Enable SPI controller
648 * @spi: pointer to the spi controller data structure
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200649 */
650static void stm32_spi_enable(struct stm32_spi *spi)
651{
652 dev_dbg(spi->dev, "enable controller\n");
653
Cezary Gapinski55166852018-12-24 23:00:37 +0100654 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
655 spi->cfg->regs->en.mask);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200656}
657
658/**
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100659 * stm32f4_spi_disable - Disable SPI controller
660 * @spi: pointer to the spi controller data structure
661 */
662static void stm32f4_spi_disable(struct stm32_spi *spi)
663{
664 unsigned long flags;
665 u32 sr;
666
667 dev_dbg(spi->dev, "disable controller\n");
668
669 spin_lock_irqsave(&spi->lock, flags);
670
671 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
672 STM32F4_SPI_CR1_SPE)) {
673 spin_unlock_irqrestore(&spi->lock, flags);
674 return;
675 }
676
677 /* Disable interrupts */
678 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
679 STM32F4_SPI_CR2_RXNEIE |
680 STM32F4_SPI_CR2_ERRIE);
681
682 /* Wait until BSY = 0 */
683 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
684 sr, !(sr & STM32F4_SPI_SR_BSY),
685 10, 100000) < 0) {
686 dev_warn(spi->dev, "disabling condition timeout\n");
687 }
688
689 if (spi->cur_usedma && spi->dma_tx)
690 dmaengine_terminate_all(spi->dma_tx);
691 if (spi->cur_usedma && spi->dma_rx)
692 dmaengine_terminate_all(spi->dma_rx);
693
694 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
695
696 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
697 STM32F4_SPI_CR2_RXDMAEN);
698
699 /* Sequence to clear OVR flag */
700 readl_relaxed(spi->base + STM32F4_SPI_DR);
701 readl_relaxed(spi->base + STM32F4_SPI_SR);
702
703 spin_unlock_irqrestore(&spi->lock, flags);
704}
705
706/**
Cezary Gapinski55166852018-12-24 23:00:37 +0100707 * stm32h7_spi_disable - Disable SPI controller
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200708 * @spi: pointer to the spi controller data structure
709 *
710 * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
Cezary Gapinski55166852018-12-24 23:00:37 +0100711 * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200712 * RX-Fifo.
Cezary Gapinski55166852018-12-24 23:00:37 +0100713 * Normally, if TSIZE has been configured, we should relax the hardware at the
714 * reception of the EOT interrupt. But in case of error, EOT will not be
715 * raised. So the subsystem unprepare_message call allows us to properly
716 * complete the transfer from an hardware point of view.
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200717 */
Cezary Gapinski55166852018-12-24 23:00:37 +0100718static void stm32h7_spi_disable(struct stm32_spi *spi)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200719{
720 unsigned long flags;
721 u32 cr1, sr;
722
723 dev_dbg(spi->dev, "disable controller\n");
724
725 spin_lock_irqsave(&spi->lock, flags);
726
Cezary Gapinski860266302018-12-24 23:00:33 +0100727 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200728
Cezary Gapinski860266302018-12-24 23:00:33 +0100729 if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200730 spin_unlock_irqrestore(&spi->lock, flags);
731 return;
732 }
733
734 /* Wait on EOT or suspend the flow */
Cezary Gapinski860266302018-12-24 23:00:33 +0100735 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
736 sr, !(sr & STM32H7_SPI_SR_EOT),
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200737 10, 100000) < 0) {
Cezary Gapinski860266302018-12-24 23:00:33 +0100738 if (cr1 & STM32H7_SPI_CR1_CSTART) {
739 writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
740 spi->base + STM32H7_SPI_CR1);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200741 if (readl_relaxed_poll_timeout_atomic(
Cezary Gapinski860266302018-12-24 23:00:33 +0100742 spi->base + STM32H7_SPI_SR,
743 sr, !(sr & STM32H7_SPI_SR_SUSP),
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200744 10, 100000) < 0)
745 dev_warn(spi->dev,
746 "Suspend request timeout\n");
747 }
748 }
749
750 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
Cezary Gapinski55166852018-12-24 23:00:37 +0100751 stm32h7_spi_read_rxfifo(spi, true);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200752
Cezary Gapinski2cbee7f2018-12-24 23:00:29 +0100753 if (spi->cur_usedma && spi->dma_tx)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200754 dmaengine_terminate_all(spi->dma_tx);
Cezary Gapinski2cbee7f2018-12-24 23:00:29 +0100755 if (spi->cur_usedma && spi->dma_rx)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200756 dmaengine_terminate_all(spi->dma_rx);
757
Cezary Gapinski860266302018-12-24 23:00:33 +0100758 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200759
Cezary Gapinski860266302018-12-24 23:00:33 +0100760 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
761 STM32H7_SPI_CFG1_RXDMAEN);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200762
763 /* Disable interrupts and clear status flags */
Cezary Gapinski860266302018-12-24 23:00:33 +0100764 writel_relaxed(0, spi->base + STM32H7_SPI_IER);
765 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200766
767 spin_unlock_irqrestore(&spi->lock, flags);
768}
769
770/**
771 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
Alain Volmat1c52be82020-03-20 14:44:17 +0100772 * @master: controller master interface
773 * @spi_dev: pointer to the spi device
774 * @transfer: pointer to spi transfer
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200775 *
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100776 * If driver has fifo and the current transfer size is greater than fifo size,
777 * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200778 */
779static bool stm32_spi_can_dma(struct spi_master *master,
780 struct spi_device *spi_dev,
781 struct spi_transfer *transfer)
782{
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100783 unsigned int dma_size;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200784 struct stm32_spi *spi = spi_master_get_devdata(master);
785
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100786 if (spi->cfg->has_fifo)
787 dma_size = spi->fifo_size;
788 else
789 dma_size = SPI_DMA_MIN_BYTES;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200790
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100791 dev_dbg(spi->dev, "%s: %s\n", __func__,
792 (transfer->len > dma_size) ? "true" : "false");
793
794 return (transfer->len > dma_size);
795}
796
797/**
798 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
799 * @irq: interrupt line
800 * @dev_id: SPI controller master interface
801 */
802static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
803{
804 struct spi_master *master = dev_id;
805 struct stm32_spi *spi = spi_master_get_devdata(master);
806 u32 sr, mask = 0;
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100807 bool end = false;
808
Barry Songe2368932020-09-26 12:16:16 +1200809 spin_lock(&spi->lock);
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100810
811 sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
812 /*
813 * BSY flag is not handled in interrupt but it is normal behavior when
814 * this flag is set.
815 */
816 sr &= ~STM32F4_SPI_SR_BSY;
817
818 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
819 spi->cur_comm == SPI_3WIRE_TX)) {
820 /* OVR flag shouldn't be handled for TX only mode */
821 sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE;
822 mask |= STM32F4_SPI_SR_TXE;
823 }
824
dillon min61367d02020-05-25 11:45:47 +0800825 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
826 spi->cur_comm == SPI_SIMPLEX_RX ||
827 spi->cur_comm == SPI_3WIRE_RX)) {
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100828 /* TXE flag is set and is handled when RXNE flag occurs */
829 sr &= ~STM32F4_SPI_SR_TXE;
830 mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
831 }
832
833 if (!(sr & mask)) {
834 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
Barry Songe2368932020-09-26 12:16:16 +1200835 spin_unlock(&spi->lock);
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100836 return IRQ_NONE;
837 }
838
839 if (sr & STM32F4_SPI_SR_OVR) {
840 dev_warn(spi->dev, "Overrun: received value discarded\n");
841
842 /* Sequence to clear OVR flag */
843 readl_relaxed(spi->base + STM32F4_SPI_DR);
844 readl_relaxed(spi->base + STM32F4_SPI_SR);
845
846 /*
847 * If overrun is detected, it means that something went wrong,
848 * so stop the current transfer. Transfer can wait for next
849 * RXNE but DR is already read and end never happens.
850 */
851 end = true;
852 goto end_irq;
853 }
854
855 if (sr & STM32F4_SPI_SR_TXE) {
856 if (spi->tx_buf)
857 stm32f4_spi_write_tx(spi);
858 if (spi->tx_len == 0)
859 end = true;
860 }
861
862 if (sr & STM32F4_SPI_SR_RXNE) {
863 stm32f4_spi_read_rx(spi);
864 if (spi->rx_len == 0)
865 end = true;
dillon min61367d02020-05-25 11:45:47 +0800866 else if (spi->tx_buf)/* Load data for discontinuous mode */
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100867 stm32f4_spi_write_tx(spi);
868 }
869
870end_irq:
871 if (end) {
872 /* Immediately disable interrupts to do not generate new one */
873 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
874 STM32F4_SPI_CR2_TXEIE |
875 STM32F4_SPI_CR2_RXNEIE |
876 STM32F4_SPI_CR2_ERRIE);
Barry Songe2368932020-09-26 12:16:16 +1200877 spin_unlock(&spi->lock);
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100878 return IRQ_WAKE_THREAD;
879 }
880
Barry Songe2368932020-09-26 12:16:16 +1200881 spin_unlock(&spi->lock);
Cezary Gapinski00505ed2018-12-24 23:00:38 +0100882 return IRQ_HANDLED;
883}
884
885/**
886 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
887 * @irq: interrupt line
888 * @dev_id: SPI controller master interface
889 */
890static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
891{
892 struct spi_master *master = dev_id;
893 struct stm32_spi *spi = spi_master_get_devdata(master);
894
895 spi_finalize_current_transfer(master);
896 stm32f4_spi_disable(spi);
897
898 return IRQ_HANDLED;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200899}
900
901/**
Cezary Gapinski55166852018-12-24 23:00:37 +0100902 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200903 * @irq: interrupt line
904 * @dev_id: SPI controller master interface
905 */
Cezary Gapinski55166852018-12-24 23:00:37 +0100906static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200907{
908 struct spi_master *master = dev_id;
909 struct stm32_spi *spi = spi_master_get_devdata(master);
910 u32 sr, ier, mask;
911 unsigned long flags;
912 bool end = false;
913
914 spin_lock_irqsave(&spi->lock, flags);
915
Cezary Gapinski860266302018-12-24 23:00:33 +0100916 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
917 ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200918
919 mask = ier;
Alain Volmat03258512021-06-30 10:45:19 +0200920 /*
921 * EOTIE enables irq from EOT, SUSP and TXC events. We need to set
922 * SUSP to acknowledge it later. TXC is automatically cleared
923 */
924
Cezary Gapinski860266302018-12-24 23:00:33 +0100925 mask |= STM32H7_SPI_SR_SUSP;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200926 /*
Alain Volmat03258512021-06-30 10:45:19 +0200927 * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP
928 * are set. So in case of Full-Duplex, need to poll TXP and RXP event.
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200929 */
Alain Volmat03258512021-06-30 10:45:19 +0200930 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
931 mask |= STM32H7_SPI_SR_TXP | STM32H7_SPI_SR_RXP;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200932
933 if (!(sr & mask)) {
Alain Volmat2314d502021-02-05 19:59:32 +0100934 dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
935 sr, ier);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200936 spin_unlock_irqrestore(&spi->lock, flags);
937 return IRQ_NONE;
938 }
939
Cezary Gapinski860266302018-12-24 23:00:33 +0100940 if (sr & STM32H7_SPI_SR_SUSP) {
Marek Vasutea8be08c2020-09-05 17:19:13 +0200941 static DEFINE_RATELIMIT_STATE(rs,
942 DEFAULT_RATELIMIT_INTERVAL * 10,
943 1);
944 if (__ratelimit(&rs))
945 dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200946 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
Cezary Gapinski55166852018-12-24 23:00:37 +0100947 stm32h7_spi_read_rxfifo(spi, false);
Amelie Delaunayc67ad362017-06-27 17:45:19 +0200948 /*
949 * If communication is suspended while using DMA, it means
950 * that something went wrong, so stop the current transfer
951 */
952 if (spi->cur_usedma)
953 end = true;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200954 }
955
Cezary Gapinski860266302018-12-24 23:00:33 +0100956 if (sr & STM32H7_SPI_SR_MODF) {
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200957 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
958 end = true;
959 }
960
Cezary Gapinski860266302018-12-24 23:00:33 +0100961 if (sr & STM32H7_SPI_SR_OVR) {
Alain Volmat2314d502021-02-05 19:59:32 +0100962 dev_err(spi->dev, "Overrun: RX data lost\n");
963 end = true;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200964 }
965
Cezary Gapinski860266302018-12-24 23:00:33 +0100966 if (sr & STM32H7_SPI_SR_EOT) {
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200967 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
Cezary Gapinski55166852018-12-24 23:00:37 +0100968 stm32h7_spi_read_rxfifo(spi, true);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200969 end = true;
970 }
971
Cezary Gapinski860266302018-12-24 23:00:33 +0100972 if (sr & STM32H7_SPI_SR_TXP)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200973 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
Cezary Gapinski55166852018-12-24 23:00:37 +0100974 stm32h7_spi_write_txfifo(spi);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200975
Cezary Gapinski860266302018-12-24 23:00:33 +0100976 if (sr & STM32H7_SPI_SR_RXP)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200977 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
Cezary Gapinski55166852018-12-24 23:00:37 +0100978 stm32h7_spi_read_rxfifo(spi, false);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200979
Tobias Schrammae1ba502020-08-04 21:51:36 +0200980 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200981
982 spin_unlock_irqrestore(&spi->lock, flags);
983
984 if (end) {
Cezary Gapinski55166852018-12-24 23:00:37 +0100985 stm32h7_spi_disable(spi);
Antonio Borneo135dd872020-08-10 09:12:34 +0200986 spi_finalize_current_transfer(master);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200987 }
988
989 return IRQ_HANDLED;
990}
991
992/**
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200993 * stm32_spi_prepare_msg - set up the controller to transfer a single message
Alain Volmat1c52be82020-03-20 14:44:17 +0100994 * @master: controller master interface
995 * @msg: pointer to spi message
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +0200996 */
997static int stm32_spi_prepare_msg(struct spi_master *master,
998 struct spi_message *msg)
999{
1000 struct stm32_spi *spi = spi_master_get_devdata(master);
1001 struct spi_device *spi_dev = msg->spi;
1002 struct device_node *np = spi_dev->dev.of_node;
1003 unsigned long flags;
Cezary Gapinski55166852018-12-24 23:00:37 +01001004 u32 clrb = 0, setb = 0;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001005
1006 /* SPI slave device may need time between data frames */
1007 spi->cur_midi = 0;
Amelie Delaunay042c1c62017-06-27 17:45:16 +02001008 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001009 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
1010
1011 if (spi_dev->mode & SPI_CPOL)
Cezary Gapinski55166852018-12-24 23:00:37 +01001012 setb |= spi->cfg->regs->cpol.mask;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001013 else
Cezary Gapinski55166852018-12-24 23:00:37 +01001014 clrb |= spi->cfg->regs->cpol.mask;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001015
1016 if (spi_dev->mode & SPI_CPHA)
Cezary Gapinski55166852018-12-24 23:00:37 +01001017 setb |= spi->cfg->regs->cpha.mask;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001018 else
Cezary Gapinski55166852018-12-24 23:00:37 +01001019 clrb |= spi->cfg->regs->cpha.mask;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001020
1021 if (spi_dev->mode & SPI_LSB_FIRST)
Cezary Gapinski55166852018-12-24 23:00:37 +01001022 setb |= spi->cfg->regs->lsb_first.mask;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001023 else
Cezary Gapinski55166852018-12-24 23:00:37 +01001024 clrb |= spi->cfg->regs->lsb_first.mask;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001025
1026 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
1027 spi_dev->mode & SPI_CPOL,
1028 spi_dev->mode & SPI_CPHA,
1029 spi_dev->mode & SPI_LSB_FIRST,
1030 spi_dev->mode & SPI_CS_HIGH);
1031
1032 spin_lock_irqsave(&spi->lock, flags);
1033
Cezary Gapinski55166852018-12-24 23:00:37 +01001034 /* CPOL, CPHA and LSB FIRST bits have common register */
1035 if (clrb || setb)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001036 writel_relaxed(
Cezary Gapinski55166852018-12-24 23:00:37 +01001037 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1038 ~clrb) | setb,
1039 spi->base + spi->cfg->regs->cpol.reg);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001040
1041 spin_unlock_irqrestore(&spi->lock, flags);
1042
1043 return 0;
1044}
1045
1046/**
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001047 * stm32f4_spi_dma_tx_cb - dma callback
Alain Volmat1c52be82020-03-20 14:44:17 +01001048 * @data: pointer to the spi controller data structure
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001049 *
1050 * DMA callback is called when the transfer is complete for DMA TX channel.
1051 */
1052static void stm32f4_spi_dma_tx_cb(void *data)
1053{
1054 struct stm32_spi *spi = data;
1055
1056 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1057 spi_finalize_current_transfer(spi->master);
1058 stm32f4_spi_disable(spi);
1059 }
1060}
1061
1062/**
1063 * stm32f4_spi_dma_rx_cb - dma callback
Alain Volmat1c52be82020-03-20 14:44:17 +01001064 * @data: pointer to the spi controller data structure
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001065 *
1066 * DMA callback is called when the transfer is complete for DMA RX channel.
1067 */
1068static void stm32f4_spi_dma_rx_cb(void *data)
1069{
1070 struct stm32_spi *spi = data;
1071
1072 spi_finalize_current_transfer(spi->master);
1073 stm32f4_spi_disable(spi);
1074}
1075
1076/**
Cezary Gapinski55166852018-12-24 23:00:37 +01001077 * stm32h7_spi_dma_cb - dma callback
Alain Volmat1c52be82020-03-20 14:44:17 +01001078 * @data: pointer to the spi controller data structure
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001079 *
1080 * DMA callback is called when the transfer is complete or when an error
1081 * occurs. If the transfer is complete, EOT flag is raised.
1082 */
Cezary Gapinski55166852018-12-24 23:00:37 +01001083static void stm32h7_spi_dma_cb(void *data)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001084{
1085 struct stm32_spi *spi = data;
1086 unsigned long flags;
1087 u32 sr;
1088
1089 spin_lock_irqsave(&spi->lock, flags);
1090
Cezary Gapinski860266302018-12-24 23:00:33 +01001091 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001092
1093 spin_unlock_irqrestore(&spi->lock, flags);
1094
Cezary Gapinski860266302018-12-24 23:00:33 +01001095 if (!(sr & STM32H7_SPI_SR_EOT))
Amelie Delaunayc67ad362017-06-27 17:45:19 +02001096 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001097
Amelie Delaunayc67ad362017-06-27 17:45:19 +02001098 /* Now wait for EOT, or SUSP or OVR in case of error */
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001099}
1100
1101/**
1102 * stm32_spi_dma_config - configure dma slave channel depending on current
1103 * transfer bits_per_word.
Alain Volmat1c52be82020-03-20 14:44:17 +01001104 * @spi: pointer to the spi controller data structure
1105 * @dma_conf: pointer to the dma_slave_config structure
1106 * @dir: direction of the dma transfer
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001107 */
1108static void stm32_spi_dma_config(struct stm32_spi *spi,
1109 struct dma_slave_config *dma_conf,
1110 enum dma_transfer_direction dir)
1111{
1112 enum dma_slave_buswidth buswidth;
1113 u32 maxburst;
1114
Amelie Delaunay128ebb82017-06-27 17:45:17 +02001115 if (spi->cur_bpw <= 8)
1116 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1117 else if (spi->cur_bpw <= 16)
1118 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1119 else
1120 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001121
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001122 if (spi->cfg->has_fifo) {
1123 /* Valid for DMA Half or Full Fifo threshold */
1124 if (spi->cur_fthlv == 2)
1125 maxburst = 1;
1126 else
1127 maxburst = spi->cur_fthlv;
1128 } else {
Amelie Delaunay128ebb82017-06-27 17:45:17 +02001129 maxburst = 1;
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001130 }
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001131
1132 memset(dma_conf, 0, sizeof(struct dma_slave_config));
1133 dma_conf->direction = dir;
1134 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
Cezary Gapinski55166852018-12-24 23:00:37 +01001135 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001136 dma_conf->src_addr_width = buswidth;
1137 dma_conf->src_maxburst = maxburst;
1138
1139 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1140 buswidth, maxburst);
1141 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
Cezary Gapinski55166852018-12-24 23:00:37 +01001142 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001143 dma_conf->dst_addr_width = buswidth;
1144 dma_conf->dst_maxburst = maxburst;
1145
1146 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1147 buswidth, maxburst);
1148 }
1149}
1150
1151/**
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001152 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
1153 * interrupts
Alain Volmat1c52be82020-03-20 14:44:17 +01001154 * @spi: pointer to the spi controller data structure
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001155 *
1156 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1157 * in progress.
1158 */
1159static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
1160{
1161 unsigned long flags;
1162 u32 cr2 = 0;
1163
1164 /* Enable the interrupts relative to the current communication mode */
1165 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1166 cr2 |= STM32F4_SPI_CR2_TXEIE;
dillon min61367d02020-05-25 11:45:47 +08001167 } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
1168 spi->cur_comm == SPI_SIMPLEX_RX ||
1169 spi->cur_comm == SPI_3WIRE_RX) {
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001170 /* In transmit-only mode, the OVR flag is set in the SR register
1171 * since the received data are never read. Therefore set OVR
1172 * interrupt only when rx buffer is available.
1173 */
1174 cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE;
1175 } else {
1176 return -EINVAL;
1177 }
1178
1179 spin_lock_irqsave(&spi->lock, flags);
1180
1181 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
1182
1183 stm32_spi_enable(spi);
1184
1185 /* starting data transfer when buffer is loaded */
1186 if (spi->tx_buf)
1187 stm32f4_spi_write_tx(spi);
1188
1189 spin_unlock_irqrestore(&spi->lock, flags);
1190
1191 return 1;
1192}
1193
1194/**
Cezary Gapinski55166852018-12-24 23:00:37 +01001195 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1196 * interrupts
Alain Volmat1c52be82020-03-20 14:44:17 +01001197 * @spi: pointer to the spi controller data structure
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001198 *
1199 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1200 * in progress.
1201 */
Cezary Gapinski55166852018-12-24 23:00:37 +01001202static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001203{
1204 unsigned long flags;
1205 u32 ier = 0;
1206
1207 /* Enable the interrupts relative to the current communication mode */
1208 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
Cezary Gapinski860266302018-12-24 23:00:33 +01001209 ier |= STM32H7_SPI_IER_DXPIE;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001210 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
Cezary Gapinski860266302018-12-24 23:00:33 +01001211 ier |= STM32H7_SPI_IER_TXPIE;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001212 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
Cezary Gapinski860266302018-12-24 23:00:33 +01001213 ier |= STM32H7_SPI_IER_RXPIE;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001214
1215 /* Enable the interrupts relative to the end of transfer */
Cezary Gapinski860266302018-12-24 23:00:33 +01001216 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
1217 STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001218
1219 spin_lock_irqsave(&spi->lock, flags);
1220
1221 stm32_spi_enable(spi);
1222
1223 /* Be sure to have data in fifo before starting data transfer */
1224 if (spi->tx_buf)
Cezary Gapinski55166852018-12-24 23:00:37 +01001225 stm32h7_spi_write_txfifo(spi);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001226
Cezary Gapinski860266302018-12-24 23:00:33 +01001227 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001228
Cezary Gapinski860266302018-12-24 23:00:33 +01001229 writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001230
1231 spin_unlock_irqrestore(&spi->lock, flags);
1232
1233 return 1;
1234}
1235
1236/**
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001237 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1238 * transfer using DMA
Alain Volmat1c52be82020-03-20 14:44:17 +01001239 * @spi: pointer to the spi controller data structure
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001240 */
1241static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
1242{
1243 /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
1244 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1245 spi->cur_comm == SPI_FULL_DUPLEX) {
1246 /*
1247 * In transmit-only mode, the OVR flag is set in the SR register
1248 * since the received data are never read. Therefore set OVR
1249 * interrupt only when rx buffer is available.
1250 */
1251 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
1252 }
1253
1254 stm32_spi_enable(spi);
1255}
1256
1257/**
Cezary Gapinski55166852018-12-24 23:00:37 +01001258 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1259 * transfer using DMA
Alain Volmat1c52be82020-03-20 14:44:17 +01001260 * @spi: pointer to the spi controller data structure
Cezary Gapinskif8bb12f2018-12-24 23:00:36 +01001261 */
Cezary Gapinski55166852018-12-24 23:00:37 +01001262static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
Cezary Gapinskif8bb12f2018-12-24 23:00:36 +01001263{
1264 /* Enable the interrupts relative to the end of transfer */
1265 stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE |
1266 STM32H7_SPI_IER_TXTFIE |
1267 STM32H7_SPI_IER_OVRIE |
1268 STM32H7_SPI_IER_MODFIE);
1269
1270 stm32_spi_enable(spi);
1271
1272 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1273}
1274
1275/**
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001276 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
Alain Volmat1c52be82020-03-20 14:44:17 +01001277 * @spi: pointer to the spi controller data structure
1278 * @xfer: pointer to the spi_transfer structure
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001279 *
1280 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1281 * in progress.
1282 */
1283static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1284 struct spi_transfer *xfer)
1285{
1286 struct dma_slave_config tx_dma_conf, rx_dma_conf;
1287 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
1288 unsigned long flags;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001289
1290 spin_lock_irqsave(&spi->lock, flags);
1291
1292 rx_dma_desc = NULL;
Cezary Gapinski2cbee7f2018-12-24 23:00:29 +01001293 if (spi->rx_buf && spi->dma_rx) {
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001294 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
1295 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1296
1297 /* Enable Rx DMA request */
Cezary Gapinski55166852018-12-24 23:00:37 +01001298 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1299 spi->cfg->regs->dma_rx_en.mask);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001300
1301 rx_dma_desc = dmaengine_prep_slave_sg(
1302 spi->dma_rx, xfer->rx_sg.sgl,
1303 xfer->rx_sg.nents,
1304 rx_dma_conf.direction,
1305 DMA_PREP_INTERRUPT);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001306 }
1307
1308 tx_dma_desc = NULL;
Cezary Gapinski2cbee7f2018-12-24 23:00:29 +01001309 if (spi->tx_buf && spi->dma_tx) {
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001310 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
1311 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1312
1313 tx_dma_desc = dmaengine_prep_slave_sg(
1314 spi->dma_tx, xfer->tx_sg.sgl,
1315 xfer->tx_sg.nents,
1316 tx_dma_conf.direction,
1317 DMA_PREP_INTERRUPT);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001318 }
1319
Cezary Gapinski2cbee7f2018-12-24 23:00:29 +01001320 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1321 (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1322 goto dma_desc_error;
1323
1324 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001325 goto dma_desc_error;
1326
1327 if (rx_dma_desc) {
Cezary Gapinski55166852018-12-24 23:00:37 +01001328 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
Amelie Delaunay7b821a62017-06-27 17:45:20 +02001329 rx_dma_desc->callback_param = spi;
1330
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001331 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
1332 dev_err(spi->dev, "Rx DMA submit failed\n");
1333 goto dma_desc_error;
1334 }
1335 /* Enable Rx DMA channel */
1336 dma_async_issue_pending(spi->dma_rx);
1337 }
1338
1339 if (tx_dma_desc) {
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001340 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1341 spi->cur_comm == SPI_3WIRE_TX) {
Cezary Gapinski55166852018-12-24 23:00:37 +01001342 tx_dma_desc->callback = spi->cfg->dma_tx_cb;
Amelie Delaunay7b821a62017-06-27 17:45:20 +02001343 tx_dma_desc->callback_param = spi;
1344 }
1345
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001346 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
1347 dev_err(spi->dev, "Tx DMA submit failed\n");
1348 goto dma_submit_error;
1349 }
1350 /* Enable Tx DMA channel */
1351 dma_async_issue_pending(spi->dma_tx);
1352
1353 /* Enable Tx DMA request */
Cezary Gapinski55166852018-12-24 23:00:37 +01001354 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1355 spi->cfg->regs->dma_tx_en.mask);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001356 }
1357
Cezary Gapinski55166852018-12-24 23:00:37 +01001358 spi->cfg->transfer_one_dma_start(spi);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001359
1360 spin_unlock_irqrestore(&spi->lock, flags);
1361
1362 return 1;
1363
1364dma_submit_error:
Cezary Gapinski2cbee7f2018-12-24 23:00:29 +01001365 if (spi->dma_rx)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001366 dmaengine_terminate_all(spi->dma_rx);
1367
1368dma_desc_error:
Cezary Gapinski55166852018-12-24 23:00:37 +01001369 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1370 spi->cfg->regs->dma_rx_en.mask);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001371
1372 spin_unlock_irqrestore(&spi->lock, flags);
1373
1374 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1375
Cezary Gapinski2cbee7f2018-12-24 23:00:29 +01001376 spi->cur_usedma = false;
Cezary Gapinski55166852018-12-24 23:00:37 +01001377 return spi->cfg->transfer_one_irq(spi);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001378}
1379
1380/**
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001381 * stm32f4_spi_set_bpw - Configure bits per word
1382 * @spi: pointer to the spi controller data structure
1383 */
1384static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1385{
1386 if (spi->cur_bpw == 16)
1387 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1388 else
1389 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1390}
1391
1392/**
Cezary Gapinski55166852018-12-24 23:00:37 +01001393 * stm32h7_spi_set_bpw - configure bits per word
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001394 * @spi: pointer to the spi controller data structure
1395 */
Cezary Gapinski55166852018-12-24 23:00:37 +01001396static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001397{
1398 u32 bpw, fthlv;
1399 u32 cfg1_clrb = 0, cfg1_setb = 0;
1400
1401 bpw = spi->cur_bpw - 1;
1402
1403 cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
1404 cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
1405 STM32H7_SPI_CFG1_DSIZE;
1406
Amelie Delaunay3373e902020-08-10 09:12:35 +02001407 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001408 fthlv = spi->cur_fthlv - 1;
1409
1410 cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
1411 cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
1412 STM32H7_SPI_CFG1_FTHLV;
1413
1414 writel_relaxed(
1415 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1416 ~cfg1_clrb) | cfg1_setb,
1417 spi->base + STM32H7_SPI_CFG1);
1418}
1419
1420/**
1421 * stm32_spi_set_mbr - Configure baud rate divisor in master mode
1422 * @spi: pointer to the spi controller data structure
1423 * @mbrdiv: baud rate divisor value
1424 */
1425static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1426{
Cezary Gapinski55166852018-12-24 23:00:37 +01001427 u32 clrb = 0, setb = 0;
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001428
Cezary Gapinski55166852018-12-24 23:00:37 +01001429 clrb |= spi->cfg->regs->br.mask;
1430 setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
1431 spi->cfg->regs->br.mask;
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001432
Cezary Gapinski55166852018-12-24 23:00:37 +01001433 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1434 ~clrb) | setb,
1435 spi->base + spi->cfg->regs->br.reg);
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001436}
1437
1438/**
1439 * stm32_spi_communication_type - return transfer communication type
1440 * @spi_dev: pointer to the spi device
Alain Volmat1c52be82020-03-20 14:44:17 +01001441 * @transfer: pointer to spi transfer
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001442 */
1443static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
1444 struct spi_transfer *transfer)
1445{
1446 unsigned int type = SPI_FULL_DUPLEX;
1447
1448 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
1449 /*
1450 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
1451 * is forbidden and unvalidated by SPI subsystem so depending
1452 * on the valid buffer, we can determine the direction of the
1453 * transfer.
1454 */
1455 if (!transfer->tx_buf)
1456 type = SPI_3WIRE_RX;
1457 else
1458 type = SPI_3WIRE_TX;
1459 } else {
1460 if (!transfer->tx_buf)
1461 type = SPI_SIMPLEX_RX;
1462 else if (!transfer->rx_buf)
1463 type = SPI_SIMPLEX_TX;
1464 }
1465
1466 return type;
1467}
1468
1469/**
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001470 * stm32f4_spi_set_mode - configure communication mode
1471 * @spi: pointer to the spi controller data structure
1472 * @comm_type: type of communication to configure
1473 */
1474static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1475{
1476 if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
1477 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1478 STM32F4_SPI_CR1_BIDIMODE |
1479 STM32F4_SPI_CR1_BIDIOE);
dillon min61367d02020-05-25 11:45:47 +08001480 } else if (comm_type == SPI_FULL_DUPLEX ||
1481 comm_type == SPI_SIMPLEX_RX) {
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001482 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1483 STM32F4_SPI_CR1_BIDIMODE |
1484 STM32F4_SPI_CR1_BIDIOE);
dillon min61367d02020-05-25 11:45:47 +08001485 } else if (comm_type == SPI_3WIRE_RX) {
1486 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1487 STM32F4_SPI_CR1_BIDIMODE);
1488 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1489 STM32F4_SPI_CR1_BIDIOE);
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001490 } else {
1491 return -EINVAL;
1492 }
1493
1494 return 0;
1495}
1496
1497/**
Cezary Gapinski55166852018-12-24 23:00:37 +01001498 * stm32h7_spi_set_mode - configure communication mode
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001499 * @spi: pointer to the spi controller data structure
1500 * @comm_type: type of communication to configure
1501 */
Cezary Gapinski55166852018-12-24 23:00:37 +01001502static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001503{
1504 u32 mode;
1505 u32 cfg2_clrb = 0, cfg2_setb = 0;
1506
1507 if (comm_type == SPI_3WIRE_RX) {
1508 mode = STM32H7_SPI_HALF_DUPLEX;
1509 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1510 } else if (comm_type == SPI_3WIRE_TX) {
1511 mode = STM32H7_SPI_HALF_DUPLEX;
1512 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1513 } else if (comm_type == SPI_SIMPLEX_RX) {
1514 mode = STM32H7_SPI_SIMPLEX_RX;
1515 } else if (comm_type == SPI_SIMPLEX_TX) {
1516 mode = STM32H7_SPI_SIMPLEX_TX;
1517 } else {
1518 mode = STM32H7_SPI_FULL_DUPLEX;
1519 }
1520
1521 cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
1522 cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
1523 STM32H7_SPI_CFG2_COMM;
1524
1525 writel_relaxed(
1526 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1527 ~cfg2_clrb) | cfg2_setb,
1528 spi->base + STM32H7_SPI_CFG2);
1529
1530 return 0;
1531}
1532
1533/**
Cezary Gapinski55166852018-12-24 23:00:37 +01001534 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1535 * consecutive data frames in master mode
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001536 * @spi: pointer to the spi controller data structure
1537 * @len: transfer len
1538 */
Cezary Gapinski55166852018-12-24 23:00:37 +01001539static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001540{
1541 u32 cfg2_clrb = 0, cfg2_setb = 0;
1542
1543 cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
1544 if ((len > 1) && (spi->cur_midi > 0)) {
1545 u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
1546 u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1547 (u32)STM32H7_SPI_CFG2_MIDI >>
1548 STM32H7_SPI_CFG2_MIDI_SHIFT);
1549
1550 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1551 sck_period_ns, midi, midi * sck_period_ns);
1552 cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
1553 STM32H7_SPI_CFG2_MIDI;
1554 }
1555
1556 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1557 ~cfg2_clrb) | cfg2_setb,
1558 spi->base + STM32H7_SPI_CFG2);
1559}
1560
1561/**
Cezary Gapinski55166852018-12-24 23:00:37 +01001562 * stm32h7_spi_number_of_data - configure number of data at current transfer
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001563 * @spi: pointer to the spi controller data structure
Alain Volmat1c52be82020-03-20 14:44:17 +01001564 * @nb_words: transfer length (in words)
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001565 */
Cezary Gapinski55166852018-12-24 23:00:37 +01001566static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001567{
1568 u32 cr2_clrb = 0, cr2_setb = 0;
1569
1570 if (nb_words <= (STM32H7_SPI_CR2_TSIZE >>
1571 STM32H7_SPI_CR2_TSIZE_SHIFT)) {
1572 cr2_clrb |= STM32H7_SPI_CR2_TSIZE;
1573 cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT;
1574 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) &
1575 ~cr2_clrb) | cr2_setb,
1576 spi->base + STM32H7_SPI_CR2);
1577 } else {
1578 return -EMSGSIZE;
1579 }
1580
1581 return 0;
1582}
1583
1584/**
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001585 * stm32_spi_transfer_one_setup - common setup to transfer a single
1586 * spi_transfer either using DMA or
1587 * interrupts.
Alain Volmat1c52be82020-03-20 14:44:17 +01001588 * @spi: pointer to the spi controller data structure
1589 * @spi_dev: pointer to the spi device
1590 * @transfer: pointer to spi transfer
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001591 */
1592static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1593 struct spi_device *spi_dev,
1594 struct spi_transfer *transfer)
1595{
1596 unsigned long flags;
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001597 unsigned int comm_type;
1598 int nb_words, ret = 0;
Alain Volmat60ccb352020-08-10 09:12:38 +02001599 int mbr;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001600
1601 spin_lock_irqsave(&spi->lock, flags);
1602
Amelie Delaunay3373e902020-08-10 09:12:35 +02001603 spi->cur_xferlen = transfer->len;
1604
Alain Volmat60ccb352020-08-10 09:12:38 +02001605 spi->cur_bpw = transfer->bits_per_word;
1606 spi->cfg->set_bpw(spi);
1607
1608 /* Update spi->cur_speed with real clock speed */
1609 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1610 spi->cfg->baud_rate_div_min,
1611 spi->cfg->baud_rate_div_max);
1612 if (mbr < 0) {
1613 ret = mbr;
1614 goto out;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001615 }
1616
Alain Volmat60ccb352020-08-10 09:12:38 +02001617 transfer->speed_hz = spi->cur_speed;
1618 stm32_spi_set_mbr(spi, mbr);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001619
Cezary Gapinski9d5fce12018-12-24 23:00:35 +01001620 comm_type = stm32_spi_communication_type(spi_dev, transfer);
Alain Volmat60ccb352020-08-10 09:12:38 +02001621 ret = spi->cfg->set_mode(spi, comm_type);
1622 if (ret < 0)
1623 goto out;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001624
Alain Volmat60ccb352020-08-10 09:12:38 +02001625 spi->cur_comm = comm_type;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001626
Cezary Gapinski55166852018-12-24 23:00:37 +01001627 if (spi->cfg->set_data_idleness)
1628 spi->cfg->set_data_idleness(spi, transfer->len);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001629
Amelie Delaunay128ebb82017-06-27 17:45:17 +02001630 if (spi->cur_bpw <= 8)
1631 nb_words = transfer->len;
1632 else if (spi->cur_bpw <= 16)
1633 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
1634 else
1635 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001636
Cezary Gapinski55166852018-12-24 23:00:37 +01001637 if (spi->cfg->set_number_of_data) {
1638 ret = spi->cfg->set_number_of_data(spi, nb_words);
1639 if (ret < 0)
1640 goto out;
1641 }
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001642
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001643 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1644 spi->cur_comm);
1645 dev_dbg(spi->dev,
1646 "data frame of %d-bit, data packet of %d data frames\n",
1647 spi->cur_bpw, spi->cur_fthlv);
1648 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1649 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1650 spi->cur_xferlen, nb_words);
1651 dev_dbg(spi->dev, "dma %s\n",
1652 (spi->cur_usedma) ? "enabled" : "disabled");
1653
1654out:
1655 spin_unlock_irqrestore(&spi->lock, flags);
1656
1657 return ret;
1658}
1659
1660/**
1661 * stm32_spi_transfer_one - transfer a single spi_transfer
Alain Volmat1c52be82020-03-20 14:44:17 +01001662 * @master: controller master interface
1663 * @spi_dev: pointer to the spi device
1664 * @transfer: pointer to spi transfer
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001665 *
1666 * It must return 0 if the transfer is finished or 1 if the transfer is still
1667 * in progress.
1668 */
1669static int stm32_spi_transfer_one(struct spi_master *master,
1670 struct spi_device *spi_dev,
1671 struct spi_transfer *transfer)
1672{
1673 struct stm32_spi *spi = spi_master_get_devdata(master);
1674 int ret;
1675
Alain Volmat03a422e2021-02-05 19:59:25 +01001676 /* Don't do anything on 0 bytes transfers */
1677 if (transfer->len == 0)
1678 return 0;
1679
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001680 spi->tx_buf = transfer->tx_buf;
1681 spi->rx_buf = transfer->rx_buf;
1682 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1683 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1684
Amelie Delaunayc67ad362017-06-27 17:45:19 +02001685 spi->cur_usedma = (master->can_dma &&
Cezary Gapinski2cbee7f2018-12-24 23:00:29 +01001686 master->can_dma(master, spi_dev, transfer));
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001687
1688 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1689 if (ret) {
1690 dev_err(spi->dev, "SPI transfer setup failed\n");
1691 return ret;
1692 }
1693
1694 if (spi->cur_usedma)
1695 return stm32_spi_transfer_one_dma(spi, transfer);
1696 else
Cezary Gapinski55166852018-12-24 23:00:37 +01001697 return spi->cfg->transfer_one_irq(spi);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001698}
1699
1700/**
1701 * stm32_spi_unprepare_msg - relax the hardware
Alain Volmat1c52be82020-03-20 14:44:17 +01001702 * @master: controller master interface
1703 * @msg: pointer to the spi message
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001704 */
1705static int stm32_spi_unprepare_msg(struct spi_master *master,
1706 struct spi_message *msg)
1707{
1708 struct stm32_spi *spi = spi_master_get_devdata(master);
1709
Cezary Gapinski55166852018-12-24 23:00:37 +01001710 spi->cfg->disable(spi);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001711
1712 return 0;
1713}
1714
1715/**
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001716 * stm32f4_spi_config - Configure SPI controller as SPI master
Alain Volmat1c52be82020-03-20 14:44:17 +01001717 * @spi: pointer to the spi controller data structure
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001718 */
1719static int stm32f4_spi_config(struct stm32_spi *spi)
1720{
1721 unsigned long flags;
1722
1723 spin_lock_irqsave(&spi->lock, flags);
1724
1725 /* Ensure I2SMOD bit is kept cleared */
1726 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
1727 STM32F4_SPI_I2SCFGR_I2SMOD);
1728
1729 /*
1730 * - SS input value high
1731 * - transmitter half duplex direction
1732 * - Set the master mode (default Motorola mode)
1733 * - Consider 1 master/n slaves configuration and
1734 * SS input value is determined by the SSI bit
1735 */
1736 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
1737 STM32F4_SPI_CR1_BIDIOE |
1738 STM32F4_SPI_CR1_MSTR |
1739 STM32F4_SPI_CR1_SSM);
1740
1741 spin_unlock_irqrestore(&spi->lock, flags);
1742
1743 return 0;
1744}
1745
1746/**
Cezary Gapinski55166852018-12-24 23:00:37 +01001747 * stm32h7_spi_config - Configure SPI controller as SPI master
Alain Volmat1c52be82020-03-20 14:44:17 +01001748 * @spi: pointer to the spi controller data structure
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001749 */
Cezary Gapinski55166852018-12-24 23:00:37 +01001750static int stm32h7_spi_config(struct stm32_spi *spi)
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001751{
1752 unsigned long flags;
1753
1754 spin_lock_irqsave(&spi->lock, flags);
1755
1756 /* Ensure I2SMOD bit is kept cleared */
Cezary Gapinski860266302018-12-24 23:00:33 +01001757 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1758 STM32H7_SPI_I2SCFGR_I2SMOD);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001759
1760 /*
1761 * - SS input value high
1762 * - transmitter half duplex direction
1763 * - automatic communication suspend when RX-Fifo is full
1764 */
Cezary Gapinski860266302018-12-24 23:00:33 +01001765 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
1766 STM32H7_SPI_CR1_HDDIR |
1767 STM32H7_SPI_CR1_MASRX);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001768
1769 /*
1770 * - Set the master mode (default Motorola mode)
1771 * - Consider 1 master/n slaves configuration and
1772 * SS input value is determined by the SSI bit
1773 * - keep control of all associated GPIOs
1774 */
Cezary Gapinski860266302018-12-24 23:00:33 +01001775 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
1776 STM32H7_SPI_CFG2_SSM |
1777 STM32H7_SPI_CFG2_AFCNTR);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001778
1779 spin_unlock_irqrestore(&spi->lock, flags);
1780
1781 return 0;
1782}
1783
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001784static const struct stm32_spi_cfg stm32f4_spi_cfg = {
1785 .regs = &stm32f4_spi_regspec,
1786 .get_bpw_mask = stm32f4_spi_get_bpw_mask,
1787 .disable = stm32f4_spi_disable,
1788 .config = stm32f4_spi_config,
1789 .set_bpw = stm32f4_spi_set_bpw,
1790 .set_mode = stm32f4_spi_set_mode,
1791 .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
1792 .dma_tx_cb = stm32f4_spi_dma_tx_cb,
1793 .dma_rx_cb = stm32f4_spi_dma_rx_cb,
1794 .transfer_one_irq = stm32f4_spi_transfer_one_irq,
1795 .irq_handler_event = stm32f4_spi_irq_event,
1796 .irq_handler_thread = stm32f4_spi_irq_thread,
1797 .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
1798 .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
1799 .has_fifo = false,
1800};
1801
Cezary Gapinski55166852018-12-24 23:00:37 +01001802static const struct stm32_spi_cfg stm32h7_spi_cfg = {
1803 .regs = &stm32h7_spi_regspec,
1804 .get_fifo_size = stm32h7_spi_get_fifo_size,
1805 .get_bpw_mask = stm32h7_spi_get_bpw_mask,
1806 .disable = stm32h7_spi_disable,
1807 .config = stm32h7_spi_config,
1808 .set_bpw = stm32h7_spi_set_bpw,
1809 .set_mode = stm32h7_spi_set_mode,
1810 .set_data_idleness = stm32h7_spi_data_idleness,
1811 .set_number_of_data = stm32h7_spi_number_of_data,
1812 .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
1813 .dma_rx_cb = stm32h7_spi_dma_cb,
1814 .dma_tx_cb = stm32h7_spi_dma_cb,
1815 .transfer_one_irq = stm32h7_spi_transfer_one_irq,
1816 .irq_handler_thread = stm32h7_spi_irq_thread,
1817 .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
1818 .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
1819 .has_fifo = true,
1820};
1821
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001822static const struct of_device_id stm32_spi_of_match[] = {
Cezary Gapinski55166852018-12-24 23:00:37 +01001823 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
Cezary Gapinski00505ed2018-12-24 23:00:38 +01001824 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001825 {},
1826};
1827MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
1828
1829static int stm32_spi_probe(struct platform_device *pdev)
1830{
1831 struct spi_master *master;
1832 struct stm32_spi *spi;
1833 struct resource *res;
Linus Walleij8a6553e2019-12-05 09:34:01 +01001834 int ret;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001835
Alain Volmat05b3f9b2021-03-18 08:24:50 +01001836 master = devm_spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001837 if (!master) {
1838 dev_err(&pdev->dev, "spi master allocation failed\n");
1839 return -ENOMEM;
1840 }
1841 platform_set_drvdata(pdev, master);
1842
1843 spi = spi_master_get_devdata(master);
1844 spi->dev = &pdev->dev;
1845 spi->master = master;
1846 spin_lock_init(&spi->lock);
1847
Cezary Gapinski55166852018-12-24 23:00:37 +01001848 spi->cfg = (const struct stm32_spi_cfg *)
1849 of_match_device(pdev->dev.driver->of_match_table,
1850 &pdev->dev)->data;
1851
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001852 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1853 spi->base = devm_ioremap_resource(&pdev->dev, res);
Alain Volmat05b3f9b2021-03-18 08:24:50 +01001854 if (IS_ERR(spi->base))
1855 return PTR_ERR(spi->base);
Cezary Gapinski55166852018-12-24 23:00:37 +01001856
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001857 spi->phys_addr = (dma_addr_t)res->start;
1858
1859 spi->irq = platform_get_irq(pdev, 0);
Alain Volmat05b3f9b2021-03-18 08:24:50 +01001860 if (spi->irq <= 0)
1861 return dev_err_probe(&pdev->dev, spi->irq,
1862 "failed to get irq\n");
1863
Cezary Gapinski55166852018-12-24 23:00:37 +01001864 ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
1865 spi->cfg->irq_handler_event,
1866 spi->cfg->irq_handler_thread,
1867 IRQF_ONESHOT, pdev->name, master);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001868 if (ret) {
1869 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1870 ret);
Alain Volmat05b3f9b2021-03-18 08:24:50 +01001871 return ret;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001872 }
1873
Cezary Gapinskid4c91342018-12-24 23:00:28 +01001874 spi->clk = devm_clk_get(&pdev->dev, NULL);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001875 if (IS_ERR(spi->clk)) {
1876 ret = PTR_ERR(spi->clk);
1877 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
Alain Volmat05b3f9b2021-03-18 08:24:50 +01001878 return ret;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001879 }
1880
1881 ret = clk_prepare_enable(spi->clk);
1882 if (ret) {
1883 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
Alain Volmat05b3f9b2021-03-18 08:24:50 +01001884 return ret;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001885 }
1886 spi->clk_rate = clk_get_rate(spi->clk);
1887 if (!spi->clk_rate) {
1888 dev_err(&pdev->dev, "clk rate = 0\n");
1889 ret = -EINVAL;
Alexey Khoroshilov3dbb3ee2018-03-30 22:54:44 +03001890 goto err_clk_disable;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001891 }
1892
Philipp Zabeld5e9a4a2017-07-19 17:26:20 +02001893 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001894 if (!IS_ERR(spi->rst)) {
1895 reset_control_assert(spi->rst);
1896 udelay(2);
1897 reset_control_deassert(spi->rst);
1898 }
1899
Cezary Gapinski55166852018-12-24 23:00:37 +01001900 if (spi->cfg->has_fifo)
1901 spi->fifo_size = spi->cfg->get_fifo_size(spi);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001902
Cezary Gapinski55166852018-12-24 23:00:37 +01001903 ret = spi->cfg->config(spi);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001904 if (ret) {
1905 dev_err(&pdev->dev, "controller configuration failed: %d\n",
1906 ret);
1907 goto err_clk_disable;
1908 }
1909
1910 master->dev.of_node = pdev->dev.of_node;
1911 master->auto_runtime_pm = true;
1912 master->bus_num = pdev->id;
Cezary Gapinskid6cea112018-12-24 23:00:31 +01001913 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
Cezary Gapinski6962b052018-12-24 23:00:32 +01001914 SPI_3WIRE;
Cezary Gapinski55166852018-12-24 23:00:37 +01001915 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
1916 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
1917 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
Linus Walleij8a6553e2019-12-05 09:34:01 +01001918 master->use_gpio_descriptors = true;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001919 master->prepare_message = stm32_spi_prepare_msg;
1920 master->transfer_one = stm32_spi_transfer_one;
1921 master->unprepare_message = stm32_spi_unprepare_msg;
dillon min61367d02020-05-25 11:45:47 +08001922 master->flags = SPI_MASTER_MUST_TX;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001923
Peter Ujfalusi0a454252019-12-12 15:55:50 +02001924 spi->dma_tx = dma_request_chan(spi->dev, "tx");
1925 if (IS_ERR(spi->dma_tx)) {
1926 ret = PTR_ERR(spi->dma_tx);
1927 spi->dma_tx = NULL;
1928 if (ret == -EPROBE_DEFER)
1929 goto err_clk_disable;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001930
Peter Ujfalusi0a454252019-12-12 15:55:50 +02001931 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1932 } else {
1933 master->dma_tx = spi->dma_tx;
1934 }
1935
1936 spi->dma_rx = dma_request_chan(spi->dev, "rx");
1937 if (IS_ERR(spi->dma_rx)) {
1938 ret = PTR_ERR(spi->dma_rx);
1939 spi->dma_rx = NULL;
1940 if (ret == -EPROBE_DEFER)
1941 goto err_dma_release;
1942
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001943 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
Peter Ujfalusi0a454252019-12-12 15:55:50 +02001944 } else {
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001945 master->dma_rx = spi->dma_rx;
Peter Ujfalusi0a454252019-12-12 15:55:50 +02001946 }
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001947
1948 if (spi->dma_tx || spi->dma_rx)
1949 master->can_dma = stm32_spi_can_dma;
1950
Amelie Delaunay038ac862017-06-27 17:45:18 +02001951 pm_runtime_set_active(&pdev->dev);
Alain Volmat23811b72021-07-07 10:27:00 +02001952 pm_runtime_get_noresume(&pdev->dev);
Amelie Delaunay038ac862017-06-27 17:45:18 +02001953 pm_runtime_enable(&pdev->dev);
1954
Antonio Borneo0390f6f2021-03-12 11:34:46 +01001955 ret = spi_register_master(master);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001956 if (ret) {
1957 dev_err(&pdev->dev, "spi master registration failed: %d\n",
1958 ret);
Peter Ujfalusi0a454252019-12-12 15:55:50 +02001959 goto err_pm_disable;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001960 }
1961
Linus Walleij8a6553e2019-12-05 09:34:01 +01001962 if (!master->cs_gpiods) {
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001963 dev_err(&pdev->dev, "no CS gpios available\n");
1964 ret = -EINVAL;
Peter Ujfalusi0a454252019-12-12 15:55:50 +02001965 goto err_pm_disable;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001966 }
1967
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001968 dev_info(&pdev->dev, "driver initialized\n");
1969
1970 return 0;
1971
Peter Ujfalusi0a454252019-12-12 15:55:50 +02001972err_pm_disable:
1973 pm_runtime_disable(&pdev->dev);
Alain Volmat23811b72021-07-07 10:27:00 +02001974 pm_runtime_put_noidle(&pdev->dev);
1975 pm_runtime_set_suspended(&pdev->dev);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001976err_dma_release:
1977 if (spi->dma_tx)
1978 dma_release_channel(spi->dma_tx);
1979 if (spi->dma_rx)
1980 dma_release_channel(spi->dma_rx);
1981err_clk_disable:
1982 clk_disable_unprepare(spi->clk);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001983
1984 return ret;
1985}
1986
1987static int stm32_spi_remove(struct platform_device *pdev)
1988{
1989 struct spi_master *master = platform_get_drvdata(pdev);
1990 struct stm32_spi *spi = spi_master_get_devdata(master);
1991
Alain Volmat23811b72021-07-07 10:27:00 +02001992 pm_runtime_get_sync(&pdev->dev);
1993
Antonio Borneo0390f6f2021-03-12 11:34:46 +01001994 spi_unregister_master(master);
Cezary Gapinski55166852018-12-24 23:00:37 +01001995 spi->cfg->disable(spi);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02001996
Alain Volmat23811b72021-07-07 10:27:00 +02001997 pm_runtime_disable(&pdev->dev);
1998 pm_runtime_put_noidle(&pdev->dev);
1999 pm_runtime_set_suspended(&pdev->dev);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02002000 if (master->dma_tx)
2001 dma_release_channel(master->dma_tx);
2002 if (master->dma_rx)
2003 dma_release_channel(master->dma_rx);
2004
2005 clk_disable_unprepare(spi->clk);
2006
Amelie Delaunay038ac862017-06-27 17:45:18 +02002007
Amelie Delaunaydb96bf92020-08-10 09:12:37 +02002008 pinctrl_pm_select_sleep_state(&pdev->dev);
2009
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02002010 return 0;
2011}
2012
Amelie Delaunay038ac862017-06-27 17:45:18 +02002013#ifdef CONFIG_PM
2014static int stm32_spi_runtime_suspend(struct device *dev)
2015{
2016 struct spi_master *master = dev_get_drvdata(dev);
2017 struct stm32_spi *spi = spi_master_get_devdata(master);
2018
2019 clk_disable_unprepare(spi->clk);
2020
Amelie Delaunaydb96bf92020-08-10 09:12:37 +02002021 return pinctrl_pm_select_sleep_state(dev);
Amelie Delaunay038ac862017-06-27 17:45:18 +02002022}
2023
2024static int stm32_spi_runtime_resume(struct device *dev)
2025{
2026 struct spi_master *master = dev_get_drvdata(dev);
2027 struct stm32_spi *spi = spi_master_get_devdata(master);
Amelie Delaunaydb96bf92020-08-10 09:12:37 +02002028 int ret;
2029
2030 ret = pinctrl_pm_select_default_state(dev);
2031 if (ret)
2032 return ret;
Amelie Delaunay038ac862017-06-27 17:45:18 +02002033
2034 return clk_prepare_enable(spi->clk);
2035}
2036#endif
2037
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02002038#ifdef CONFIG_PM_SLEEP
2039static int stm32_spi_suspend(struct device *dev)
2040{
2041 struct spi_master *master = dev_get_drvdata(dev);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02002042 int ret;
2043
2044 ret = spi_master_suspend(master);
2045 if (ret)
2046 return ret;
2047
Amelie Delaunay038ac862017-06-27 17:45:18 +02002048 return pm_runtime_force_suspend(dev);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02002049}
2050
2051static int stm32_spi_resume(struct device *dev)
2052{
2053 struct spi_master *master = dev_get_drvdata(dev);
2054 struct stm32_spi *spi = spi_master_get_devdata(master);
2055 int ret;
2056
Amelie Delaunay038ac862017-06-27 17:45:18 +02002057 ret = pm_runtime_force_resume(dev);
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02002058 if (ret)
2059 return ret;
Amelie Delaunay038ac862017-06-27 17:45:18 +02002060
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02002061 ret = spi_master_resume(master);
Amelie Delaunaydb96bf92020-08-10 09:12:37 +02002062 if (ret) {
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02002063 clk_disable_unprepare(spi->clk);
Amelie Delaunaydb96bf92020-08-10 09:12:37 +02002064 return ret;
2065 }
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02002066
Amelie Delaunaydb96bf92020-08-10 09:12:37 +02002067 ret = pm_runtime_get_sync(dev);
Dan Carpenterc170a5a2020-09-09 12:43:04 +03002068 if (ret < 0) {
Zhang Qilong26a19bb2020-11-06 09:52:17 +08002069 pm_runtime_put_noidle(dev);
Amelie Delaunaydb96bf92020-08-10 09:12:37 +02002070 dev_err(dev, "Unable to power device:%d\n", ret);
2071 return ret;
2072 }
2073
2074 spi->cfg->config(spi);
2075
2076 pm_runtime_mark_last_busy(dev);
2077 pm_runtime_put_autosuspend(dev);
2078
2079 return 0;
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02002080}
2081#endif
2082
Amelie Delaunay038ac862017-06-27 17:45:18 +02002083static const struct dev_pm_ops stm32_spi_pm_ops = {
2084 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
2085 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
2086 stm32_spi_runtime_resume, NULL)
2087};
Amelie Delaunaydcbe0d82017-06-21 16:32:06 +02002088
2089static struct platform_driver stm32_spi_driver = {
2090 .probe = stm32_spi_probe,
2091 .remove = stm32_spi_remove,
2092 .driver = {
2093 .name = DRIVER_NAME,
2094 .pm = &stm32_spi_pm_ops,
2095 .of_match_table = stm32_spi_of_match,
2096 },
2097};
2098
2099module_platform_driver(stm32_spi_driver);
2100
2101MODULE_ALIAS("platform:" DRIVER_NAME);
2102MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
2103MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
2104MODULE_LICENSE("GPL v2");