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Peter Korsgaard1e16dfc2008-09-23 17:35:38 +02001/*
Liu Gang42178e22016-02-03 19:27:34 +08002 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +02003 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
Liu Gang42178e22016-02-03 19:27:34 +08005 * Copyright (C) 2016 Freescale Semiconductor Inc.
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +02006 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/spinlock.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/of_gpio.h>
Liu Gang42178e22016-02-03 19:27:34 +080018#include <linux/of_address.h>
Rob Herring5af50732013-09-17 14:28:33 -050019#include <linux/of_irq.h>
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +010020#include <linux/of_platform.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Peter Korsgaard345e5c82010-01-07 17:57:46 +010022#include <linux/irq.h>
Liu Gang42178e22016-02-03 19:27:34 +080023#include <linux/gpio/driver.h>
Linus Walleijb3222f72017-10-20 16:08:12 +020024#include <linux/bitops.h>
Song Hui698b8ee2019-10-11 08:56:43 +080025#include <linux/interrupt.h>
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020026
27#define MPC8XXX_GPIO_PINS 32
28
29#define GPIO_DIR 0x00
30#define GPIO_ODR 0x04
31#define GPIO_DAT 0x08
32#define GPIO_IER 0x0c
33#define GPIO_IMR 0x10
34#define GPIO_ICR 0x14
Anatolij Gustschine39d5ef62010-08-09 07:58:48 +020035#define GPIO_ICR2 0x18
Song Huibd4bd332019-07-18 17:49:02 +080036#define GPIO_IBE 0x18
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020037
38struct mpc8xxx_gpio_chip {
Liu Gang42178e22016-02-03 19:27:34 +080039 struct gpio_chip gc;
40 void __iomem *regs;
Alexander Stein50593612015-07-21 15:54:30 +020041 raw_spinlock_t lock;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020042
Liu Gang42178e22016-02-03 19:27:34 +080043 int (*direction_output)(struct gpio_chip *chip,
44 unsigned offset, int value);
45
Grant Likelybae1d8f2012-02-14 14:06:50 -070046 struct irq_domain *irq;
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +010047 unsigned int irqn;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020048};
49
Linus Walleijb3222f72017-10-20 16:08:12 +020050/*
51 * This hardware has a big endian bit assignment such that GPIO line 0 is
52 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
53 * This inline helper give the right bitmask for a certain line.
54 */
55static inline u32 mpc_pin2mask(unsigned int offset)
56{
57 return BIT(31 - offset);
58}
59
Felix Radenskyc1a676d2009-08-12 08:57:39 +030060/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
61 * defined as output cannot be determined by reading GPDAT register,
62 * so we use shadow data register instead. The status of input pins
63 * is determined by reading GPDAT register.
64 */
65static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
66{
67 u32 val;
Linus Walleij709d71a2015-12-07 10:34:28 +010068 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
Liu Gang1aeef302013-11-22 16:12:40 +080069 u32 out_mask, out_shadow;
Felix Radenskyc1a676d2009-08-12 08:57:39 +030070
Axel Lincd0d3f52016-02-22 15:24:01 +080071 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
72 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
Liu Gang42178e22016-02-03 19:27:34 +080073 out_shadow = gc->bgpio_data & out_mask;
Felix Radenskyc1a676d2009-08-12 08:57:39 +030074
Linus Walleijb3222f72017-10-20 16:08:12 +020075 return !!((val | out_shadow) & mpc_pin2mask(gpio));
Felix Radenskyc1a676d2009-08-12 08:57:39 +030076}
77
Liu Gang42178e22016-02-03 19:27:34 +080078static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
79 unsigned int gpio, int val)
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020080{
Linus Walleij709d71a2015-12-07 10:34:28 +010081 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
Wolfram Sang28538df2011-12-13 10:12:48 +010082 /* GPIO 28..31 are input only on MPC5121 */
83 if (gpio >= 28)
84 return -EINVAL;
85
Liu Gang42178e22016-02-03 19:27:34 +080086 return mpc8xxx_gc->direction_output(gc, gpio, val);
Wolfram Sang28538df2011-12-13 10:12:48 +010087}
88
Liu Gang42178e22016-02-03 19:27:34 +080089static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
90 unsigned int gpio, int val)
Uwe Kleine-König0ba69e02015-07-16 21:08:23 +020091{
Liu Gang42178e22016-02-03 19:27:34 +080092 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
Uwe Kleine-König0ba69e02015-07-16 21:08:23 +020093 /* GPIO 0..3 are input only on MPC5125 */
94 if (gpio <= 3)
95 return -EINVAL;
96
Liu Gang42178e22016-02-03 19:27:34 +080097 return mpc8xxx_gc->direction_output(gc, gpio, val);
Uwe Kleine-König0ba69e02015-07-16 21:08:23 +020098}
99
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100100static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
101{
Linus Walleij709d71a2015-12-07 10:34:28 +0100102 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100103
104 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
105 return irq_create_mapping(mpc8xxx_gc->irq, offset);
106 else
107 return -ENXIO;
108}
109
Song Hui698b8ee2019-10-11 08:56:43 +0800110static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100111{
Song Hui698b8ee2019-10-11 08:56:43 +0800112 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
Axel Lincd0d3f52016-02-22 15:24:01 +0800113 struct gpio_chip *gc = &mpc8xxx_gc->gc;
Song Hui698b8ee2019-10-11 08:56:43 +0800114 unsigned long mask;
115 int i;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100116
Axel Lincd0d3f52016-02-22 15:24:01 +0800117 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
118 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
Song Hui698b8ee2019-10-11 08:56:43 +0800119 for_each_set_bit(i, &mask, 32)
120 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i));
121
122 return IRQ_HANDLED;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100123}
124
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000125static void mpc8xxx_irq_unmask(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100126{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000127 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Liu Gang42178e22016-02-03 19:27:34 +0800128 struct gpio_chip *gc = &mpc8xxx_gc->gc;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100129 unsigned long flags;
130
Alexander Stein50593612015-07-21 15:54:30 +0200131 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100132
Axel Lincd0d3f52016-02-22 15:24:01 +0800133 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
134 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
Linus Walleijb3222f72017-10-20 16:08:12 +0200135 | mpc_pin2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100136
Alexander Stein50593612015-07-21 15:54:30 +0200137 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100138}
139
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000140static void mpc8xxx_irq_mask(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100141{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000142 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Liu Gang42178e22016-02-03 19:27:34 +0800143 struct gpio_chip *gc = &mpc8xxx_gc->gc;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100144 unsigned long flags;
145
Alexander Stein50593612015-07-21 15:54:30 +0200146 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100147
Axel Lincd0d3f52016-02-22 15:24:01 +0800148 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
149 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
Linus Walleijb3222f72017-10-20 16:08:12 +0200150 & ~mpc_pin2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100151
Alexander Stein50593612015-07-21 15:54:30 +0200152 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100153}
154
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000155static void mpc8xxx_irq_ack(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100156{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000157 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Liu Gang42178e22016-02-03 19:27:34 +0800158 struct gpio_chip *gc = &mpc8xxx_gc->gc;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100159
Axel Lincd0d3f52016-02-22 15:24:01 +0800160 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
Linus Walleijb3222f72017-10-20 16:08:12 +0200161 mpc_pin2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100162}
163
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000164static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100165{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000166 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Liu Gang42178e22016-02-03 19:27:34 +0800167 struct gpio_chip *gc = &mpc8xxx_gc->gc;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100168 unsigned long flags;
169
170 switch (flow_type) {
171 case IRQ_TYPE_EDGE_FALLING:
Pali Rohár24196212022-09-06 12:54:31 +0200172 case IRQ_TYPE_LEVEL_LOW:
Alexander Stein50593612015-07-21 15:54:30 +0200173 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
Axel Lincd0d3f52016-02-22 15:24:01 +0800174 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
175 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
Linus Walleijb3222f72017-10-20 16:08:12 +0200176 | mpc_pin2mask(irqd_to_hwirq(d)));
Alexander Stein50593612015-07-21 15:54:30 +0200177 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100178 break;
179
180 case IRQ_TYPE_EDGE_BOTH:
Alexander Stein50593612015-07-21 15:54:30 +0200181 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
Axel Lincd0d3f52016-02-22 15:24:01 +0800182 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
183 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
Linus Walleijb3222f72017-10-20 16:08:12 +0200184 & ~mpc_pin2mask(irqd_to_hwirq(d)));
Alexander Stein50593612015-07-21 15:54:30 +0200185 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100186 break;
187
188 default:
189 return -EINVAL;
190 }
191
192 return 0;
193}
194
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000195static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
Anatolij Gustschine39d5ef62010-08-09 07:58:48 +0200196{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000197 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Axel Lincd0d3f52016-02-22 15:24:01 +0800198 struct gpio_chip *gc = &mpc8xxx_gc->gc;
Grant Likely476eb492011-05-04 15:02:15 +1000199 unsigned long gpio = irqd_to_hwirq(d);
Anatolij Gustschine39d5ef62010-08-09 07:58:48 +0200200 void __iomem *reg;
201 unsigned int shift;
202 unsigned long flags;
203
204 if (gpio < 16) {
Liu Gang42178e22016-02-03 19:27:34 +0800205 reg = mpc8xxx_gc->regs + GPIO_ICR;
Anatolij Gustschine39d5ef62010-08-09 07:58:48 +0200206 shift = (15 - gpio) * 2;
207 } else {
Liu Gang42178e22016-02-03 19:27:34 +0800208 reg = mpc8xxx_gc->regs + GPIO_ICR2;
Anatolij Gustschine39d5ef62010-08-09 07:58:48 +0200209 shift = (15 - (gpio % 16)) * 2;
210 }
211
212 switch (flow_type) {
213 case IRQ_TYPE_EDGE_FALLING:
214 case IRQ_TYPE_LEVEL_LOW:
Alexander Stein50593612015-07-21 15:54:30 +0200215 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
Axel Lincd0d3f52016-02-22 15:24:01 +0800216 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
Liu Gang42178e22016-02-03 19:27:34 +0800217 | (2 << shift));
Alexander Stein50593612015-07-21 15:54:30 +0200218 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
Anatolij Gustschine39d5ef62010-08-09 07:58:48 +0200219 break;
220
221 case IRQ_TYPE_EDGE_RISING:
222 case IRQ_TYPE_LEVEL_HIGH:
Alexander Stein50593612015-07-21 15:54:30 +0200223 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
Axel Lincd0d3f52016-02-22 15:24:01 +0800224 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
Liu Gang42178e22016-02-03 19:27:34 +0800225 | (1 << shift));
Alexander Stein50593612015-07-21 15:54:30 +0200226 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
Anatolij Gustschine39d5ef62010-08-09 07:58:48 +0200227 break;
228
229 case IRQ_TYPE_EDGE_BOTH:
Alexander Stein50593612015-07-21 15:54:30 +0200230 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
Axel Lincd0d3f52016-02-22 15:24:01 +0800231 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
Alexander Stein50593612015-07-21 15:54:30 +0200232 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
Anatolij Gustschine39d5ef62010-08-09 07:58:48 +0200233 break;
234
235 default:
236 return -EINVAL;
237 }
238
239 return 0;
240}
241
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100242static struct irq_chip mpc8xxx_irq_chip = {
243 .name = "mpc8xxx-gpio",
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000244 .irq_unmask = mpc8xxx_irq_unmask,
245 .irq_mask = mpc8xxx_irq_mask,
246 .irq_ack = mpc8xxx_irq_ack,
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200247 /* this might get overwritten in mpc8xxx_probe() */
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000248 .irq_set_type = mpc8xxx_irq_set_type,
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100249};
250
Linus Walleij5ba17ae2013-10-11 19:37:30 +0200251static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
252 irq_hw_number_t hwirq)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100253{
Linus Walleij5ba17ae2013-10-11 19:37:30 +0200254 irq_set_chip_data(irq, h->host_data);
Liu Gangd71cf152016-10-21 15:31:28 +0800255 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100256
257 return 0;
258}
259
Krzysztof Kozlowski0b354dc2015-04-27 21:54:07 +0900260static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100261 .map = mpc8xxx_gpio_irq_map,
Grant Likelyff8c3ab2012-01-24 17:09:13 -0700262 .xlate = irq_domain_xlate_twocell,
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100263};
264
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200265struct mpc8xxx_gpio_devtype {
266 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
267 int (*gpio_get)(struct gpio_chip *, unsigned int);
268 int (*irq_set_type)(struct irq_data *, unsigned int);
269};
270
271static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
272 .gpio_dir_out = mpc5121_gpio_dir_out,
273 .irq_set_type = mpc512x_irq_set_type,
274};
275
Uwe Kleine-König0ba69e02015-07-16 21:08:23 +0200276static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
277 .gpio_dir_out = mpc5125_gpio_dir_out,
278 .irq_set_type = mpc512x_irq_set_type,
279};
280
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200281static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
282 .gpio_get = mpc8572_gpio_get,
283};
284
285static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200286 .irq_set_type = mpc8xxx_irq_set_type,
287};
288
Uwe Kleine-König4183afe2015-07-16 21:08:21 +0200289static const struct of_device_id mpc8xxx_gpio_ids[] = {
Anatolij Gustschine39d5ef62010-08-09 07:58:48 +0200290 { .compatible = "fsl,mpc8349-gpio", },
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200291 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
Anatolij Gustschine39d5ef62010-08-09 07:58:48 +0200292 { .compatible = "fsl,mpc8610-gpio", },
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200293 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
Uwe Kleine-König0ba69e02015-07-16 21:08:23 +0200294 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
Kumar Gala15a51482011-10-22 16:20:42 -0500295 { .compatible = "fsl,pq3-gpio", },
Michael Walle3795d7c2020-09-30 09:42:11 +0200296 { .compatible = "fsl,ls1028a-gpio", },
297 { .compatible = "fsl,ls1088a-gpio", },
Anatolij Gustschind1dcfbb2011-01-08 16:51:16 +0100298 { .compatible = "fsl,qoriq-gpio", },
Anatolij Gustschine39d5ef62010-08-09 07:58:48 +0200299 {}
300};
301
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100302static int mpc8xxx_probe(struct platform_device *pdev)
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200303{
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100304 struct device_node *np = pdev->dev.of_node;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200305 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
Liu Gang42178e22016-02-03 19:27:34 +0800306 struct gpio_chip *gc;
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200307 const struct mpc8xxx_gpio_devtype *devtype =
308 of_device_get_match_data(&pdev->dev);
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200309 int ret;
310
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100311 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
312 if (!mpc8xxx_gc)
313 return -ENOMEM;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200314
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100315 platform_set_drvdata(pdev, mpc8xxx_gc);
316
Alexander Stein50593612015-07-21 15:54:30 +0200317 raw_spin_lock_init(&mpc8xxx_gc->lock);
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200318
Liu Gang42178e22016-02-03 19:27:34 +0800319 mpc8xxx_gc->regs = of_iomap(np, 0);
320 if (!mpc8xxx_gc->regs)
321 return -ENOMEM;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200322
Liu Gang42178e22016-02-03 19:27:34 +0800323 gc = &mpc8xxx_gc->gc;
Johnson CH Chen (陳昭勳)322f6a32019-11-26 06:51:11 +0000324 gc->parent = &pdev->dev;
Liu Gang42178e22016-02-03 19:27:34 +0800325
326 if (of_property_read_bool(np, "little-endian")) {
327 ret = bgpio_init(gc, &pdev->dev, 4,
328 mpc8xxx_gc->regs + GPIO_DAT,
329 NULL, NULL,
330 mpc8xxx_gc->regs + GPIO_DIR, NULL,
331 BGPIOF_BIG_ENDIAN);
332 if (ret)
333 goto err;
334 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
335 } else {
336 ret = bgpio_init(gc, &pdev->dev, 4,
337 mpc8xxx_gc->regs + GPIO_DAT,
338 NULL, NULL,
339 mpc8xxx_gc->regs + GPIO_DIR, NULL,
340 BGPIOF_BIG_ENDIAN
341 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
342 if (ret)
343 goto err;
344 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
345 }
346
Axel Linfa4007c2016-02-22 15:22:52 +0800347 mpc8xxx_gc->direction_output = gc->direction_output;
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200348
349 if (!devtype)
350 devtype = &mpc8xxx_gpio_devtype_default;
351
352 /*
353 * It's assumed that only a single type of gpio controller is available
354 * on the current machine, so overwriting global data is fine.
355 */
Vladimir Oltean4e505732019-11-15 14:55:51 +0200356 if (devtype->irq_set_type)
357 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
Uwe Kleine-König82e39b02015-07-16 21:08:22 +0200358
Axel Linadf32ea2016-02-22 15:24:54 +0800359 if (devtype->gpio_dir_out)
360 gc->direction_output = devtype->gpio_dir_out;
361 if (devtype->gpio_get)
362 gc->get = devtype->gpio_get;
363
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100364 gc->to_irq = mpc8xxx_gpio_to_irq;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200365
Michael Walle3795d7c2020-09-30 09:42:11 +0200366 /*
367 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
368 * the input enable of each individual GPIO port. When an individual
369 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
370 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
371 * the port value to the GPIO Data Register.
372 */
373 if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
374 of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
375 of_device_is_compatible(np, "fsl,ls1088a-gpio"))
Russell King787b64a2019-11-19 13:10:38 +0000376 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
377
Christophe JAILLETb167a0c2021-08-20 17:38:13 +0200378 ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
Liu Gang42178e22016-02-03 19:27:34 +0800379 if (ret) {
Rob Herring7eb6ce22017-07-18 16:43:03 -0500380 pr_err("%pOF: GPIO chip registration failed with status %d\n",
381 np, ret);
Liu Gang42178e22016-02-03 19:27:34 +0800382 goto err;
383 }
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200384
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100385 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
Liu Gang42178e22016-02-03 19:27:34 +0800386 if (!mpc8xxx_gc->irqn)
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100387 return 0;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100388
Grant Likelya8db8cf2012-02-14 14:06:54 -0700389 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
390 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100391 if (!mpc8xxx_gc->irq)
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100392 return 0;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100393
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100394 /* ack and mask all irqs */
Axel Lincd0d3f52016-02-22 15:24:01 +0800395 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
396 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100397
Song Hui698b8ee2019-10-11 08:56:43 +0800398 ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
399 mpc8xxx_gpio_irq_cascade,
Rasmus Villemoes9851ad22021-07-02 15:37:12 +0200400 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
Song Hui698b8ee2019-10-11 08:56:43 +0800401 mpc8xxx_gc);
402 if (ret) {
403 dev_err(&pdev->dev, "%s: failed to devm_request_irq(%d), ret = %d\n",
404 np->full_name, mpc8xxx_gc->irqn, ret);
405 goto err;
406 }
407
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100408 return 0;
Liu Gang42178e22016-02-03 19:27:34 +0800409err:
Christophe JAILLETf8695612021-08-20 17:37:55 +0200410 if (mpc8xxx_gc->irq)
411 irq_domain_remove(mpc8xxx_gc->irq);
Liu Gang42178e22016-02-03 19:27:34 +0800412 iounmap(mpc8xxx_gc->regs);
413 return ret;
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100414}
415
416static int mpc8xxx_remove(struct platform_device *pdev)
417{
418 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
419
420 if (mpc8xxx_gc->irq) {
Thomas Gleixner05379812015-06-21 21:10:46 +0200421 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100422 irq_domain_remove(mpc8xxx_gc->irq);
423 }
424
Liu Gang42178e22016-02-03 19:27:34 +0800425 iounmap(mpc8xxx_gc->regs);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100426
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200427 return 0;
428}
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100429
430static struct platform_driver mpc8xxx_plat_driver = {
431 .probe = mpc8xxx_probe,
Ricardo Ribalda Delgado257e1072015-01-18 12:39:33 +0100432 .remove = mpc8xxx_remove,
Ricardo Ribalda Delgado98686d9a52015-01-18 12:39:32 +0100433 .driver = {
434 .name = "gpio-mpc8xxx",
435 .of_match_table = mpc8xxx_gpio_ids,
436 },
437};
438
439static int __init mpc8xxx_init(void)
440{
441 return platform_driver_register(&mpc8xxx_plat_driver);
442}
443
444arch_initcall(mpc8xxx_init);