max77779_regs.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright 2023 Google, LLC
 *
 * SW Support for MAX77779 IF-PMIC
 */

#ifndef MAX77779_REG_H_
#define MAX77779_REG_H_

#include "max77779_v070_0510b_prelim_regs.h"

/* b/257314583 FSHIP_EXIT_DTLS is still read only */
#define MAX77779_FSHIP_EXIT_DTLS	  MAX77779_PMIC_INT_MASK
#define MAX77759_FSHIP_EXIT_DTLS_RD \
				MAX77779_PMIC_INT_MASK_FSHIP_NOT_RD
#define MAX77759_FSHIP_EXIT_DTLS_RD_SHIFT \
				MAX77779_PMIC_INT_MASK_FSHIP_NOT_RD_SHIFT
#define MAX77759_FSHIP_EXIT_DTLS_RD_MASK \
				MAX77779_PMIC_INT_MASK_FSHIP_NOT_RD_MASK
#define MAX77759_FSHIP_EXIT_DTLS_RD_CLEAR \
				MAX77779_PMIC_INT_MASK_FSHIP_NOT_RD_CLEAR

/* TODO: b/257309885 do we still need this? */
#define MAX77779_CHG_CNFG_11_OTG_VBYP_5000MV	0x0
#define MAX77779_CHG_CNFG_11_OTG_VBYP_5100MV	0x2

/* TODO: b/257309885 do we still need this? */
#define MAX77779_CHG_CNFG_05_OTG_ILIM_DISABLE	0x00
#define MAX77779_CHG_CNFG_05_OTG_ILIM_500MA		0x01
#define MAX77779_CHG_CNFG_05_OTG_ILIM_1500MA	0x0b

#define MAX77779_CHG_CNFG_12_CHG_EN	(0x1 << 7)
#define MAX77779_CHG_CNFG_12_WCINSEL	(0x1 << 6)
#define MAX77779_CHG_CNFG_12_CHGINSEL	(0x1 << 5)
#define MAX77779_CHG_CNFG_12_DISKIP	(0x1 << 0)
/* TODO: b/257309885 do we still need this? */
#define MAX77779_CHG_CNFG_12_WCIN_REG_4_5  (0x0 << MAX77779_CHG_CNFG_12_WCIN_REG_SHIFT)
#define MAX77779_CHG_CNFG_12_WCIN_REG_4_85 (0x3 << MAX77779_CHG_CNFG_12_WCIN_REG_SHIFT)

/* TODO: b/284182020 - add config2, USR, and nIChgTerm to 0.7 regmap */
#define MAX77779_FG_CONFIG2	0xab
#define MAX77779_FG_CONFIG2_TALRTEN_SHIFT	6
#define MAX77779_FG_CONFIG2_TALRTEN_MASK	(0x1 << 6)
#define MAX77779_FG_CONFIG2_TALRTEN_CLEAR	(~(0x1 << 6))
#define MAX77779_FG_CONFIG2_DSOCEN_SHIFT	7
#define MAX77779_FG_CONFIG2_DSOCEN_MASK	(0x1 << 7)
#define MAX77779_FG_CONFIG2_DSOCEN_CLEAR	(~(0x1 << 7))
#define MAX77779_FG_CONFIG2_SPR_13_08_SHIFT	8
#define MAX77779_FG_CONFIG2_SPR_13_08_MASK	(0x3f << 8)
#define MAX77779_FG_CONFIG2_SPR_13_08_CLEAR	(~(0x3f << 8))
#define MAX77779_FG_CONFIG2_NRLD_SHIFT	14
#define MAX77779_FG_CONFIG2_NRLD_MASK	(0x1 << 14)
#define MAX77779_FG_CONFIG2_NRLD_CLEAR	(~(0x1 << 14))
#define MAX77779_FG_CONFIG2_LDMDL_SHIFT	15
#define MAX77779_FG_CONFIG2_LDMDL_MASK	(0x1 << 15)
#define MAX77779_FG_CONFIG2_LDMDL_CLEAR	(~(0x1 << 15))

MAX77779_BFF(max77779_fg_config2_talrten,6,6)
MAX77779_BFF(max77779_fg_config2_dsocen,7,7)
MAX77779_BFF(max77779_fg_config2_spr_13_08,13,8)
MAX77779_BFF(max77779_fg_config2_nrld,14,14)
MAX77779_BFF(max77779_fg_config2_ldmdl,15,15)

#define MAX77779_FG_USR	0xff
#define MAX77779_FG_USR_NLOCK_SHIFT	1
#define MAX77779_FG_USR_NLOCK_MASK	(0x1 << 1)
#define MAX77779_FG_USR_NLOCK_CLEAR	(~(0x1 << 1))
#define MAX77779_FG_USR_VLOCK_SHIFT	2
#define MAX77779_FG_USR_VLOCK_MASK	(0x1 << 2)
#define MAX77779_FG_USR_VLOCK_CLEAR	(~(0x1 << 2))
#define MAX77779_FG_USR_RLOCK_SHIFT	3
#define MAX77779_FG_USR_RLOCK_MASK	(0x1 << 3)
#define MAX77779_FG_USR_RLOCK_CLEAR	(~(0x1 << 3))
#define MAX77779_FG_USR_SPR_USR_0_SHIFT	4
#define MAX77779_FG_USR_SPR_USR_0_MASK	(0xfff << 4)
#define MAX77779_FG_USR_SPR_USR_0_CLEAR	(~(0xfff << 4))

MAX77779_BFF(max77779_fg_usr_nlock,1,1)
MAX77779_BFF(max77779_fg_usr_vlock,2,2)
MAX77779_BFF(max77779_fg_usr_rlock,3,3)
MAX77779_BFF(max77779_fg_usr_spr_usr_0,15,4)

#define MAX77779_FG_DBG_nIChgTerm	0x9c

/* ----------------------------------------------------------------------------
 * Mode Register
 */

enum max77779_charger_modes {
	MAX77779_CHGR_MODE_ALL_OFF			= 0x00,
	MAX77779_CHGR_MODE_BUCK_ON			= 0x04,
	MAX77779_CHGR_MODE_CHGR_BUCK_ON			= 0x05,
	MAX77779_CHGR_MODE_BOOST_UNO_ON			= 0x08,
	MAX77779_CHGR_MODE_BOOST_ON			= 0x09,
	MAX77779_CHGR_MODE_OTG_BOOST_ON			= 0x0a,
	MAX77779_CHGR_MODE_OTG_BOOST_UNO_ON		= 0x0b,
	MAX77779_CHGR_MODE_BUCK_BOOST_UNO_ON		= 0x0c,
	MAX77779_CHGR_MODE_CHGR_BUCK_BOOST_UNO_ON	= 0x0d,
	MAX77779_CHGR_MODE_OTG_BUCK_BOOST_ON		= 0x0e,
	MAX77779_CHGR_MODE_CHGR_OTG_BUCK_BOOST_ON	= 0x0f,
};


#endif /* MAX77779_REG_H_ */