| Ken Tsou | 8acade1 | 2020-07-09 03:17:35 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* machine generated DO NOT MODIFY |
| 3 | * source MW_regmap_ds_v0p54_091819.csv |
| 4 | * 2019-11-04 |
| 5 | */ |
| 6 | |
| 7 | #ifndef MAX_M5_REG_H_ |
| 8 | #define MAX_M5_REG_H_ |
| 9 | |
| 10 | /* Status,0x0,0b00000010,0x02 |
| 11 | * Br,Smx,Tmx,Vmx,Bi,Smn,Tmn |
| 12 | */ |
| 13 | #define MAX_M5_STATUS 0x0 |
| 14 | #define MAX_M5_STATUS_BR (0x1 << 15) |
| 15 | #define MAX_M5_STATUS_SMX (0x1 << 14) |
| 16 | #define MAX_M5_STATUS_TMX (0x1 << 13) |
| 17 | #define MAX_M5_STATUS_VMX (0x1 << 12) |
| 18 | #define MAX_M5_STATUS_BI (0x1 << 11) |
| 19 | #define MAX_M5_STATUS_SMN (0x1 << 10) |
| 20 | #define MAX_M5_STATUS_TMN (0x1 << 9) |
| 21 | #define MAX_M5_STATUS_VMN (0x1 << 8) |
| 22 | #define MAX_M5_STATUS_DSOCI (0x1 << 7) |
| 23 | #define MAX_M5_STATUS_THMHOT (0x1 << 6) |
| 24 | #define MAX_M5_STATUS_SPR_5 (0x1 << 5) |
| 25 | #define MAX_M5_STATUS_ISYSMX (0x1 << 4) |
| 26 | #define MAX_M5_STATUS_BST (0x1 << 3) |
| 27 | #define MAX_M5_STATUS_SPR_2 (0x1 << 2) |
| 28 | #define MAX_M5_STATUS_POR (0x1 << 1) |
| 29 | #define MAX_M5_STATUS_IMN (0x1 << 0) |
| 30 | |
| 31 | #define MAX_M5_STATUS_BR_MASK 0x1 |
| 32 | #define MAX_M5_STATUS_BR_SHIFT 15 |
| 33 | #define MAX_M5_STATUS_BR_CLEAR (~(0x1 << 15)) |
| 34 | #define MAX_M5_STATUS_BR_CLR(v) ((v) & MAX_M5_STATUS_BR_CLEAR) |
| 35 | #define MAX_M5_STATUS_BR_SET(v) \ |
| 36 | (MAX_M5_STATUS_BR_CLR(v) | MAX_M5_STATUS_BR) |
| 37 | #define MAX_M5_STATUS_SMX_MASK 0x1 |
| 38 | #define MAX_M5_STATUS_SMX_SHIFT 14 |
| 39 | #define MAX_M5_STATUS_SMX_CLEAR (~(0x1 << 14)) |
| 40 | #define MAX_M5_STATUS_SMX_CLR(v) ((v) & MAX_M5_STATUS_SMX_CLEAR) |
| 41 | #define MAX_M5_STATUS_SMX_SET(v) \ |
| 42 | (MAX_M5_STATUS_SMX_CLR(v) | MAX_M5_STATUS_SMX) |
| 43 | #define MAX_M5_STATUS_TMX_MASK 0x1 |
| 44 | #define MAX_M5_STATUS_TMX_SHIFT 13 |
| 45 | #define MAX_M5_STATUS_TMX_CLEAR (~(0x1 << 13)) |
| 46 | #define MAX_M5_STATUS_TMX_CLR(v) ((v) & MAX_M5_STATUS_TMX_CLEAR) |
| 47 | #define MAX_M5_STATUS_TMX_SET(v) \ |
| 48 | (MAX_M5_STATUS_TMX_CLR(v) | MAX_M5_STATUS_TMX) |
| 49 | #define MAX_M5_STATUS_VMX_MASK 0x1 |
| 50 | #define MAX_M5_STATUS_VMX_SHIFT 12 |
| 51 | #define MAX_M5_STATUS_VMX_CLEAR (~(0x1 << 12)) |
| 52 | #define MAX_M5_STATUS_VMX_CLR(v) ((v) & MAX_M5_STATUS_VMX_CLEAR) |
| 53 | #define MAX_M5_STATUS_VMX_SET(v) \ |
| 54 | (MAX_M5_STATUS_VMX_CLR(v) | MAX_M5_STATUS_VMX) |
| 55 | #define MAX_M5_STATUS_BI_MASK 0x1 |
| 56 | #define MAX_M5_STATUS_BI_SHIFT 11 |
| 57 | #define MAX_M5_STATUS_BI_CLEAR (~(0x1 << 11)) |
| 58 | #define MAX_M5_STATUS_BI_CLR(v) ((v) & MAX_M5_STATUS_BI_CLEAR) |
| 59 | #define MAX_M5_STATUS_BI_SET(v) \ |
| 60 | (MAX_M5_STATUS_BI_CLR(v) | MAX_M5_STATUS_BI) |
| 61 | #define MAX_M5_STATUS_SMN_MASK 0x1 |
| 62 | #define MAX_M5_STATUS_SMN_SHIFT 10 |
| 63 | #define MAX_M5_STATUS_SMN_CLEAR (~(0x1 << 10)) |
| 64 | #define MAX_M5_STATUS_SMN_CLR(v) ((v) & MAX_M5_STATUS_SMN_CLEAR) |
| 65 | #define MAX_M5_STATUS_SMN_SET(v) \ |
| 66 | (MAX_M5_STATUS_SMN_CLR(v) | MAX_M5_STATUS_SMN) |
| 67 | #define MAX_M5_STATUS_TMN_MASK 0x1 |
| 68 | #define MAX_M5_STATUS_TMN_SHIFT 9 |
| 69 | #define MAX_M5_STATUS_TMN_CLEAR (~(0x1 << 9)) |
| 70 | #define MAX_M5_STATUS_TMN_CLR(v) ((v) & MAX_M5_STATUS_TMN_CLEAR) |
| 71 | #define MAX_M5_STATUS_TMN_SET(v) \ |
| 72 | (MAX_M5_STATUS_TMN_CLR(v) | MAX_M5_STATUS_TMN) |
| 73 | #define MAX_M5_STATUS_VMN_MASK 0x1 |
| 74 | #define MAX_M5_STATUS_VMN_SHIFT 8 |
| 75 | #define MAX_M5_STATUS_VMN_CLEAR (~(0x1 << 8)) |
| 76 | #define MAX_M5_STATUS_VMN_CLR(v) ((v) & MAX_M5_STATUS_VMN_CLEAR) |
| 77 | #define MAX_M5_STATUS_VMN_SET(v) \ |
| 78 | (MAX_M5_STATUS_VMN_CLR(v) | MAX_M5_STATUS_VMN) |
| 79 | #define MAX_M5_STATUS_DSOCI_MASK 0x1 |
| 80 | #define MAX_M5_STATUS_DSOCI_SHIFT 7 |
| 81 | #define MAX_M5_STATUS_DSOCI_CLEAR (~(0x1 << 7)) |
| 82 | #define MAX_M5_STATUS_DSOCI_CLR(v) ((v) & MAX_M5_STATUS_DSOCI_CLEAR) |
| 83 | #define MAX_M5_STATUS_DSOCI_SET(v) \ |
| 84 | (MAX_M5_STATUS_DSOCI_CLR(v) | MAX_M5_STATUS_DSOCI) |
| 85 | #define MAX_M5_STATUS_THMHOT_MASK 0x1 |
| 86 | #define MAX_M5_STATUS_THMHOT_SHIFT 6 |
| 87 | #define MAX_M5_STATUS_THMHOT_CLEAR (~(0x1 << 6)) |
| 88 | #define MAX_M5_STATUS_THMHOT_CLR(v) \ |
| 89 | ((v) & MAX_M5_STATUS_THMHOT_CLEAR) |
| 90 | #define MAX_M5_STATUS_THMHOT_SET(v) \ |
| 91 | (MAX_M5_STATUS_THMHOT_CLR(v) | MAX_M5_STATUS_THMHOT) |
| 92 | #define MAX_M5_STATUS_SPR_5_MASK 0x1 |
| 93 | #define MAX_M5_STATUS_SPR_5_SHIFT 5 |
| 94 | #define MAX_M5_STATUS_SPR_5_CLEAR (~(0x1 << 5)) |
| 95 | #define MAX_M5_STATUS_SPR_5_CLR(v) ((v) & MAX_M5_STATUS_SPR_5_CLEAR) |
| 96 | #define MAX_M5_STATUS_SPR_5_SET(v) \ |
| 97 | (MAX_M5_STATUS_SPR_5_CLR(v) | MAX_M5_STATUS_SPR_5) |
| 98 | #define MAX_M5_STATUS_ISYSMX_MASK 0x1 |
| 99 | #define MAX_M5_STATUS_ISYSMX_SHIFT 4 |
| 100 | #define MAX_M5_STATUS_ISYSMX_CLEAR (~(0x1 << 4)) |
| 101 | #define MAX_M5_STATUS_ISYSMX_CLR(v) \ |
| 102 | ((v) & MAX_M5_STATUS_ISYSMX_CLEAR) |
| 103 | #define MAX_M5_STATUS_ISYSMX_SET(v) \ |
| 104 | (MAX_M5_STATUS_ISYSMX_CLR(v) | MAX_M5_STATUS_ISYSMX) |
| 105 | #define MAX_M5_STATUS_BST_MASK 0x1 |
| 106 | #define MAX_M5_STATUS_BST_SHIFT 3 |
| 107 | #define MAX_M5_STATUS_BST_CLEAR (~(0x1 << 3)) |
| 108 | #define MAX_M5_STATUS_BST_CLR(v) ((v) & MAX_M5_STATUS_BST_CLEAR) |
| 109 | #define MAX_M5_STATUS_BST_SET(v) \ |
| 110 | (MAX_M5_STATUS_BST_CLR(v) | MAX_M5_STATUS_BST) |
| 111 | #define MAX_M5_STATUS_SPR_2_MASK 0x1 |
| 112 | #define MAX_M5_STATUS_SPR_2_SHIFT 2 |
| 113 | #define MAX_M5_STATUS_SPR_2_CLEAR (~(0x1 << 2)) |
| 114 | #define MAX_M5_STATUS_SPR_2_CLR(v) ((v) & MAX_M5_STATUS_SPR_2_CLEAR) |
| 115 | #define MAX_M5_STATUS_SPR_2_SET(v) \ |
| 116 | (MAX_M5_STATUS_SPR_2_CLR(v) | MAX_M5_STATUS_SPR_2) |
| 117 | #define MAX_M5_STATUS_POR_MASK 0x1 |
| 118 | #define MAX_M5_STATUS_POR_SHIFT 1 |
| 119 | #define MAX_M5_STATUS_POR_CLEAR (~(0x1 << 1)) |
| 120 | #define MAX_M5_STATUS_POR_CLR(v) ((v) & MAX_M5_STATUS_POR_CLEAR) |
| 121 | #define MAX_M5_STATUS_POR_SET(v) \ |
| 122 | (MAX_M5_STATUS_POR_CLR(v) | MAX_M5_STATUS_POR) |
| 123 | #define MAX_M5_STATUS_IMN_MASK 0x1 |
| 124 | #define MAX_M5_STATUS_IMN_SHIFT 0 |
| 125 | #define MAX_M5_STATUS_IMN_CLEAR (~(0x1 << 0)) |
| 126 | #define MAX_M5_STATUS_IMN_CLR(v) ((v) & MAX_M5_STATUS_IMN_CLEAR) |
| 127 | #define MAX_M5_STATUS_IMN_SET(v) \ |
| 128 | (MAX_M5_STATUS_IMN_CLR(v) | MAX_M5_STATUS_IMN) |
| 129 | |
| 130 | /* VAlrtTh,0x1,0b1111111100000000,0xff00 |
| 131 | * MaxVoltageAlrt[7:0],,,,,, |
| 132 | */ |
| 133 | #define MAX_M5_VALRTTH 0x1 |
| 134 | #define MAX_M5_VALRTTH_MAXVOLTAGEALRT (0xff << 8) |
| 135 | #define MAX_M5_VALRTTH_MINVOLTAGEALRT (0xff << 0) |
| 136 | |
| 137 | #define MAX_M5_VALRTTH_MAXVOLTAGEALRT_MASK 0xff |
| 138 | #define MAX_M5_VALRTTH_MAXVOLTAGEALRT_SHIFT 8 |
| 139 | #define MAX_M5_VALRTTH_MAXVOLTAGEALRT_CLEAR (~(0xff << 8)) |
| 140 | #define MAX_M5_VALRTTH_MAXVOLTAGEALRT_CLR(v) \ |
| 141 | ((v) & MAX_M5_VALRTTH_MAXVOLTAGEALRT_CLEAR) |
| 142 | #define MAX_M5_VALRTTH_MAXVOLTAGEALRT_SET(v) \ |
| 143 | (MAX_M5_VALRTTH_MAXVOLTAGEALRT_CLR(v) | MAX_M5_VALRTTH_MAXVOLTAGEALRT) |
| 144 | #define MAX_M5_VALRTTH_MINVOLTAGEALRT_MASK 0xff |
| 145 | #define MAX_M5_VALRTTH_MINVOLTAGEALRT_SHIFT 0 |
| 146 | #define MAX_M5_VALRTTH_MINVOLTAGEALRT_CLEAR (~(0xff << 0)) |
| 147 | #define MAX_M5_VALRTTH_MINVOLTAGEALRT_CLR(v) \ |
| 148 | ((v) & MAX_M5_VALRTTH_MINVOLTAGEALRT_CLEAR) |
| 149 | #define MAX_M5_VALRTTH_MINVOLTAGEALRT_SET(v) \ |
| 150 | (MAX_M5_VALRTTH_MINVOLTAGEALRT_CLR(v) | MAX_M5_VALRTTH_MINVOLTAGEALRT) |
| 151 | |
| 152 | /* TAlrtTh,0x2,0b111111110000000,0x7f80 |
| 153 | * MaxTempAlrt[7:0],,,,,, |
| 154 | */ |
| 155 | #define MAX_M5_TALRTTH 0x2 |
| 156 | #define MAX_M5_TALRTTH_MAXTEMPALRT (0xff << 8) |
| 157 | #define MAX_M5_TALRTTH_MINTEMPALRT (0xff << 0) |
| 158 | |
| 159 | #define MAX_M5_TALRTTH_MAXTEMPALRT_MASK 0xff |
| 160 | #define MAX_M5_TALRTTH_MAXTEMPALRT_SHIFT 8 |
| 161 | #define MAX_M5_TALRTTH_MAXTEMPALRT_CLEAR (~(0xff << 8)) |
| 162 | #define MAX_M5_TALRTTH_MAXTEMPALRT_CLR(v) \ |
| 163 | ((v) & MAX_M5_TALRTTH_MAXTEMPALRT_CLEAR) |
| 164 | #define MAX_M5_TALRTTH_MAXTEMPALRT_SET(v) \ |
| 165 | (MAX_M5_TALRTTH_MAXTEMPALRT_CLR(v) | MAX_M5_TALRTTH_MAXTEMPALRT) |
| 166 | #define MAX_M5_TALRTTH_MINTEMPALRT_MASK 0xff |
| 167 | #define MAX_M5_TALRTTH_MINTEMPALRT_SHIFT 0 |
| 168 | #define MAX_M5_TALRTTH_MINTEMPALRT_CLEAR (~(0xff << 0)) |
| 169 | #define MAX_M5_TALRTTH_MINTEMPALRT_CLR(v) \ |
| 170 | ((v) & MAX_M5_TALRTTH_MINTEMPALRT_CLEAR) |
| 171 | #define MAX_M5_TALRTTH_MINTEMPALRT_SET(v) \ |
| 172 | (MAX_M5_TALRTTH_MINTEMPALRT_CLR(v) | MAX_M5_TALRTTH_MINTEMPALRT) |
| 173 | |
| 174 | /* SAlrtTh,0x3,0b1111111100000000,0xff00 |
| 175 | * MaxSocAlrt[7:0],,,,,, |
| 176 | */ |
| 177 | #define MAX_M5_SALRTTH 0x3 |
| 178 | #define MAX_M5_SALRTTH_MAXSOCALRT (0xff << 8) |
| 179 | #define MAX_M5_SALRTTH_MINSOCALRT (0xff << 0) |
| 180 | |
| 181 | #define MAX_M5_SALRTTH_MAXSOCALRT_MASK 0xff |
| 182 | #define MAX_M5_SALRTTH_MAXSOCALRT_SHIFT 8 |
| 183 | #define MAX_M5_SALRTTH_MAXSOCALRT_CLEAR (~(0xff << 8)) |
| 184 | #define MAX_M5_SALRTTH_MAXSOCALRT_CLR(v) \ |
| 185 | ((v) & MAX_M5_SALRTTH_MAXSOCALRT_CLEAR) |
| 186 | #define MAX_M5_SALRTTH_MAXSOCALRT_SET(v) \ |
| 187 | (MAX_M5_SALRTTH_MAXSOCALRT_CLR(v) | MAX_M5_SALRTTH_MAXSOCALRT) |
| 188 | #define MAX_M5_SALRTTH_MINSOCALRT_MASK 0xff |
| 189 | #define MAX_M5_SALRTTH_MINSOCALRT_SHIFT 0 |
| 190 | #define MAX_M5_SALRTTH_MINSOCALRT_CLEAR (~(0xff << 0)) |
| 191 | #define MAX_M5_SALRTTH_MINSOCALRT_CLR(v) \ |
| 192 | ((v) & MAX_M5_SALRTTH_MINSOCALRT_CLEAR) |
| 193 | #define MAX_M5_SALRTTH_MINSOCALRT_SET(v) \ |
| 194 | (MAX_M5_SALRTTH_MINSOCALRT_CLR(v) | MAX_M5_SALRTTH_MINSOCALRT) |
| 195 | |
| 196 | /* AtRate,0x4,0b00000000,0x00 |
| 197 | * AtRate[15:8],,,,,, |
| 198 | */ |
| 199 | #define MAX_M5_ATRATE 0x4 |
| 200 | |
| 201 | /* RepCap,0x5,0b10111011100,0x5dc |
| 202 | * RepCap[15:8],,,,,, |
| 203 | */ |
| 204 | #define MAX_M5_REPCAP 0x5 |
| 205 | |
| 206 | /* RepSOC,0x6,0b11001000000000,0x3200 |
| 207 | * RepSOC[15:8],,,,,, |
| 208 | */ |
| 209 | #define MAX_M5_REPSOC 0x6 |
| 210 | |
| 211 | /* Age,0x7,0b110010000000000,0x6400 |
| 212 | * Age[15:8],,,,,, |
| 213 | */ |
| 214 | #define MAX_M5_AGE 0x7 |
| 215 | |
| 216 | /* Temp,0x8,0b1011000000000,0x1600 |
| 217 | * TEMP[15:8],,,,,, |
| 218 | */ |
| 219 | #define MAX_M5_TEMP 0x8 |
| 220 | |
| 221 | /* Vcell,0x9,0b1011010000000000,0xb400 |
| 222 | * VCELL[15:8],,,,,, |
| 223 | */ |
| 224 | #define MAX_M5_VCELL 0x9 |
| 225 | |
| 226 | /* Current,0xA,0b00000000,0x00 |
| 227 | * Current[15:8],,,,,, |
| 228 | */ |
| 229 | #define MAX_M5_CURRENT 0xA |
| 230 | |
| 231 | /* AvgCurrent,0xB,0b00000000,0x00 |
| 232 | * AvgCurrent[15:8],,,,,, |
| 233 | */ |
| 234 | #define MAX_M5_AVGCURRENT 0xB |
| 235 | |
| 236 | /* QResidual,0xC,0b00000000,0x00 |
| 237 | * Qresidual[15:8],,,,,, |
| 238 | */ |
| 239 | #define MAX_M5_QRESIDUAL 0xC |
| 240 | |
| 241 | /* MixSOC,0xD,0b11001000000000,0x3200 |
| 242 | * MixSOC[15:8],,,,,, |
| 243 | */ |
| 244 | #define MAX_M5_MIXSOC 0xD |
| 245 | |
| 246 | /* AvSOC,0xE,0b11001000000000,0x3200 |
| 247 | * AvSOC[15:8],,,,,, |
| 248 | */ |
| 249 | #define MAX_M5_AVSOC 0xE |
| 250 | |
| 251 | /* MixCap,0xF,0b10111011100,0x5dc |
| 252 | * MixCapH[15:8],,,,,, |
| 253 | */ |
| 254 | #define MAX_M5_MIXCAP 0xF |
| 255 | |
| 256 | /* FullCap,0x10,0b101110111000,0xbb8 |
| 257 | * FullCAP[15:8],,,,,, |
| 258 | */ |
| 259 | #define MAX_M5_FULLCAP 0x10 |
| 260 | |
| 261 | /* TTE,0x11,0b00000000,0x00 |
| 262 | * hr[5:0],,,,,,mn[5:4] |
| 263 | */ |
| 264 | #define MAX_M5_TTE 0x11 |
| 265 | #define MAX_M5_TTE_HR (0x3f << 10) |
| 266 | #define MAX_M5_TTE_MN (0x3f << 4) |
| 267 | #define MAX_M5_TTE_SEC (0xf << 0) |
| 268 | |
| 269 | #define MAX_M5_TTE_HR_MASK 0x3f |
| 270 | #define MAX_M5_TTE_HR_SHIFT 10 |
| 271 | #define MAX_M5_TTE_HR_CLEAR (~(0x3f << 10)) |
| 272 | #define MAX_M5_TTE_HR_CLR(v) ((v) & MAX_M5_TTE_HR_CLEAR) |
| 273 | #define MAX_M5_TTE_HR_SET(v) (MAX_M5_TTE_HR_CLR(v) | MAX_M5_TTE_HR) |
| 274 | #define MAX_M5_TTE_MN_MASK 0x3f |
| 275 | #define MAX_M5_TTE_MN_SHIFT 4 |
| 276 | #define MAX_M5_TTE_MN_CLEAR (~(0x3f << 4)) |
| 277 | #define MAX_M5_TTE_MN_CLR(v) ((v) & MAX_M5_TTE_MN_CLEAR) |
| 278 | #define MAX_M5_TTE_MN_SET(v) (MAX_M5_TTE_MN_CLR(v) | MAX_M5_TTE_MN) |
| 279 | #define MAX_M5_TTE_SEC_MASK 0xf |
| 280 | #define MAX_M5_TTE_SEC_SHIFT 0 |
| 281 | #define MAX_M5_TTE_SEC_CLEAR (~(0xf << 0)) |
| 282 | #define MAX_M5_TTE_SEC_CLR(v) ((v) & MAX_M5_TTE_SEC_CLEAR) |
| 283 | #define MAX_M5_TTE_SEC_SET(v) \ |
| 284 | (MAX_M5_TTE_SEC_CLR(v) | MAX_M5_TTE_SEC) |
| 285 | |
| 286 | /* QRTable00,0x12,0b11110000000000,0x3c00 |
| 287 | * QRTable00[15:8],,,,,, |
| 288 | */ |
| 289 | #define MAX_M5_QRTABLE00 0x12 |
| 290 | |
| 291 | /* FullSocThr,0x13,0b101000000000000,0x5000 |
| 292 | * FullSOCThr[15:8],,,,,, |
| 293 | */ |
| 294 | #define MAX_M5_FULLSOCTHR 0x13 |
| 295 | |
| 296 | /* Rslow,0x14,0b1010010000,0x290 |
| 297 | * RSLOW[15:8],,,,,, |
| 298 | */ |
| 299 | #define MAX_M5_RSLOW 0x14 |
| 300 | |
| 301 | /* RFast,0x15,0b101001000,0x148 |
| 302 | * RFAST[15:8],,,,,, |
| 303 | */ |
| 304 | #define MAX_M5_RFAST 0x15 |
| 305 | |
| 306 | /* AvgTA,0x16,0b1011000000000,0x1600 |
| 307 | * AvgTA[15:8],,,,,, |
| 308 | */ |
| 309 | #define MAX_M5_AVGTA 0x16 |
| 310 | |
| 311 | /* Cycles,0x17,0b00000000,0x00 |
| 312 | * Cycles[15:8],,,,,, |
| 313 | */ |
| 314 | #define MAX_M5_CYCLES 0x17 |
| 315 | |
| 316 | /* DesignCap,0x18,0b101110111000,0xbb8 |
| 317 | * DesignCap[15:8],,,,,, |
| 318 | */ |
| 319 | #define MAX_M5_DESIGNCAP 0x18 |
| 320 | |
| 321 | /* AvgVCell,0x19,0b1011010000000000,0xb400 |
| 322 | * AvgVCELL[15:8],,,,,, |
| 323 | */ |
| 324 | #define MAX_M5_AVGVCELL 0x19 |
| 325 | |
| 326 | /* MaxMinTemp,0x1A,0b1000000001111111,0x807f |
| 327 | * MaxTemperature[7:0],,,,,, |
| 328 | */ |
| 329 | #define MAX_M5_MAXMINTEMP 0x1A |
| 330 | #define MAX_M5_MAXMINTEMP_MAXTEMPERATURE (0xff << 8) |
| 331 | #define MAX_M5_MAXMINTEMP_MINTEMPERATURE (0xff << 0) |
| 332 | |
| 333 | #define MAX_M5_MAXMINTEMP_MAXTEMPERATURE_MASK 0xff |
| 334 | #define MAX_M5_MAXMINTEMP_MAXTEMPERATURE_SHIFT 8 |
| 335 | #define MAX_M5_MAXMINTEMP_MAXTEMPERATURE_CLEAR (~(0xff << 8)) |
| 336 | #define MAX_M5_MAXMINTEMP_MAXTEMPERATURE_CLR(v) \ |
| 337 | ((v) & MAX_M5_MAXMINTEMP_MAXTEMPERATURE_CLEAR) |
| 338 | #define MAX_M5_MAXMINTEMP_MAXTEMPERATURE_SET(v) \ |
| 339 | (MAX_M5_MAXMINTEMP_MAXTEMPERATURE_CLR(v) | MAX_M5_MAXMINTEMP_MAXTEMPERATURE) |
| 340 | #define MAX_M5_MAXMINTEMP_MINTEMPERATURE_MASK 0xff |
| 341 | #define MAX_M5_MAXMINTEMP_MINTEMPERATURE_SHIFT 0 |
| 342 | #define MAX_M5_MAXMINTEMP_MINTEMPERATURE_CLEAR (~(0xff << 0)) |
| 343 | #define MAX_M5_MAXMINTEMP_MINTEMPERATURE_CLR(v) \ |
| 344 | ((v) & MAX_M5_MAXMINTEMP_MINTEMPERATURE_CLEAR) |
| 345 | #define MAX_M5_MAXMINTEMP_MINTEMPERATURE_SET(v) \ |
| 346 | (MAX_M5_MAXMINTEMP_MINTEMPERATURE_CLR(v) | MAX_M5_MAXMINTEMP_MINTEMPERATURE) |
| 347 | |
| 348 | /* MaxMinVolt,0x1B,0b11111111,0xff |
| 349 | * MaxVoltage[7:0],,,,,, |
| 350 | */ |
| 351 | #define MAX_M5_MAXMINVOLT 0x1B |
| 352 | #define MAX_M5_MAXMINVOLT_MAXVOLTAGE (0xff << 8) |
| 353 | #define MAX_M5_MAXMINVOLT_MINVOLTAGE (0xff << 0) |
| 354 | |
| 355 | #define MAX_M5_MAXMINVOLT_MAXVOLTAGE_MASK 0xff |
| 356 | #define MAX_M5_MAXMINVOLT_MAXVOLTAGE_SHIFT 8 |
| 357 | #define MAX_M5_MAXMINVOLT_MAXVOLTAGE_CLEAR (~(0xff << 8)) |
| 358 | #define MAX_M5_MAXMINVOLT_MAXVOLTAGE_CLR(v) \ |
| 359 | ((v) & MAX_M5_MAXMINVOLT_MAXVOLTAGE_CLEAR) |
| 360 | #define MAX_M5_MAXMINVOLT_MAXVOLTAGE_SET(v) \ |
| 361 | (MAX_M5_MAXMINVOLT_MAXVOLTAGE_CLR(v) | MAX_M5_MAXMINVOLT_MAXVOLTAGE) |
| 362 | #define MAX_M5_MAXMINVOLT_MINVOLTAGE_MASK 0xff |
| 363 | #define MAX_M5_MAXMINVOLT_MINVOLTAGE_SHIFT 0 |
| 364 | #define MAX_M5_MAXMINVOLT_MINVOLTAGE_CLEAR (~(0xff << 0)) |
| 365 | #define MAX_M5_MAXMINVOLT_MINVOLTAGE_CLR(v) \ |
| 366 | ((v) & MAX_M5_MAXMINVOLT_MINVOLTAGE_CLEAR) |
| 367 | #define MAX_M5_MAXMINVOLT_MINVOLTAGE_SET(v) \ |
| 368 | (MAX_M5_MAXMINVOLT_MINVOLTAGE_CLR(v) | MAX_M5_MAXMINVOLT_MINVOLTAGE) |
| 369 | |
| 370 | /* MaxMinCurr,0x1C,0b1000000001111111,0x807f |
| 371 | * MaxChargeCurrent[7:0],,,,,, |
| 372 | */ |
| 373 | #define MAX_M5_MAXMINCURR 0x1C |
| 374 | #define MAX_M5_MAXMINCURR_MAXCHARGECURRENT (0xff << 8) |
| 375 | #define MAX_M5_MAXMINCURR_MAXDISCURRENT (0xff << 0) |
| 376 | |
| 377 | #define MAX_M5_MAXMINCURR_MAXCHARGECURRENT_MASK 0xff |
| 378 | #define MAX_M5_MAXMINCURR_MAXCHARGECURRENT_SHIFT 8 |
| 379 | #define MAX_M5_MAXMINCURR_MAXCHARGECURRENT_CLEAR (~(0xff << 8)) |
| 380 | #define MAX_M5_MAXMINCURR_MAXCHARGECURRENT_CLR(v) \ |
| 381 | ((v) & MAX_M5_MAXMINCURR_MAXCHARGECURRENT_CLEAR) |
| 382 | #define MAX_M5_MAXMINCURR_MAXCHARGECURRENT_SET(v) \ |
| 383 | (MAX_M5_MAXMINCURR_MAXCHARGECURRENT_CLR(v) | MAX_M5_MAXMINCURR_MAXCHARGECURRENT) |
| 384 | #define MAX_M5_MAXMINCURR_MAXDISCURRENT_MASK 0xff |
| 385 | #define MAX_M5_MAXMINCURR_MAXDISCURRENT_SHIFT 0 |
| 386 | #define MAX_M5_MAXMINCURR_MAXDISCURRENT_CLEAR (~(0xff << 0)) |
| 387 | #define MAX_M5_MAXMINCURR_MAXDISCURRENT_CLR(v) \ |
| 388 | ((v) & MAX_M5_MAXMINCURR_MAXDISCURRENT_CLEAR) |
| 389 | #define MAX_M5_MAXMINCURR_MAXDISCURRENT_SET(v) \ |
| 390 | (MAX_M5_MAXMINCURR_MAXDISCURRENT_CLR(v) | MAX_M5_MAXMINCURR_MAXDISCURRENT) |
| 391 | |
| 392 | /* Config,0x1D,0b10001101010000,0x2350 |
| 393 | * FCFE,Ss,Ts,Vs,FGCC,AINSH,Ten |
| 394 | */ |
| 395 | #define MAX_M5_CONFIG 0x1D |
| 396 | #define MAX_M5_CONFIG_FCFE (0x1 << 15) |
| 397 | #define MAX_M5_CONFIG_SS (0x1 << 14) |
| 398 | #define MAX_M5_CONFIG_TS (0x1 << 13) |
| 399 | #define MAX_M5_CONFIG_VS (0x1 << 12) |
| 400 | #define MAX_M5_CONFIG_FGCC (0x1 << 11) |
| 401 | #define MAX_M5_CONFIG_AINSH (0x1 << 10) |
| 402 | #define MAX_M5_CONFIG_TEN (0x1 << 9) |
| 403 | #define MAX_M5_CONFIG_TEX (0x1 << 8) |
| 404 | #define MAX_M5_CONFIG_SHDN (0x1 << 7) |
| 405 | #define MAX_M5_CONFIG_I2CSH (0x1 << 6) |
| 406 | #define MAX_M5_CONFIG_ICFE (0x1 << 5) |
| 407 | #define MAX_M5_CONFIG_ETHRM (0x1 << 4) |
| 408 | #define MAX_M5_CONFIG_FTHRM (0x1 << 3) |
| 409 | #define MAX_M5_CONFIG_AEN (0x1 << 2) |
| 410 | #define MAX_M5_CONFIG_BEI (0x1 << 1) |
| 411 | #define MAX_M5_CONFIG_BER (0x1 << 0) |
| 412 | |
| 413 | #define MAX_M5_CONFIG_FCFE_MASK 0x1 |
| 414 | #define MAX_M5_CONFIG_FCFE_SHIFT 15 |
| 415 | #define MAX_M5_CONFIG_FCFE_CLEAR (~(0x1 << 15)) |
| 416 | #define MAX_M5_CONFIG_FCFE_CLR(v) ((v) & MAX_M5_CONFIG_FCFE_CLEAR) |
| 417 | #define MAX_M5_CONFIG_FCFE_SET(v) \ |
| 418 | (MAX_M5_CONFIG_FCFE_CLR(v) | MAX_M5_CONFIG_FCFE) |
| 419 | #define MAX_M5_CONFIG_SS_MASK 0x1 |
| 420 | #define MAX_M5_CONFIG_SS_SHIFT 14 |
| 421 | #define MAX_M5_CONFIG_SS_CLEAR (~(0x1 << 14)) |
| 422 | #define MAX_M5_CONFIG_SS_CLR(v) ((v) & MAX_M5_CONFIG_SS_CLEAR) |
| 423 | #define MAX_M5_CONFIG_SS_SET(v) \ |
| 424 | (MAX_M5_CONFIG_SS_CLR(v) | MAX_M5_CONFIG_SS) |
| 425 | #define MAX_M5_CONFIG_TS_MASK 0x1 |
| 426 | #define MAX_M5_CONFIG_TS_SHIFT 13 |
| 427 | #define MAX_M5_CONFIG_TS_CLEAR (~(0x1 << 13)) |
| 428 | #define MAX_M5_CONFIG_TS_CLR(v) ((v) & MAX_M5_CONFIG_TS_CLEAR) |
| 429 | #define MAX_M5_CONFIG_TS_SET(v) \ |
| 430 | (MAX_M5_CONFIG_TS_CLR(v) | MAX_M5_CONFIG_TS) |
| 431 | #define MAX_M5_CONFIG_VS_MASK 0x1 |
| 432 | #define MAX_M5_CONFIG_VS_SHIFT 12 |
| 433 | #define MAX_M5_CONFIG_VS_CLEAR (~(0x1 << 12)) |
| 434 | #define MAX_M5_CONFIG_VS_CLR(v) ((v) & MAX_M5_CONFIG_VS_CLEAR) |
| 435 | #define MAX_M5_CONFIG_VS_SET(v) \ |
| 436 | (MAX_M5_CONFIG_VS_CLR(v) | MAX_M5_CONFIG_VS) |
| 437 | #define MAX_M5_CONFIG_FGCC_MASK 0x1 |
| 438 | #define MAX_M5_CONFIG_FGCC_SHIFT 11 |
| 439 | #define MAX_M5_CONFIG_FGCC_CLEAR (~(0x1 << 11)) |
| 440 | #define MAX_M5_CONFIG_FGCC_CLR(v) ((v) & MAX_M5_CONFIG_FGCC_CLEAR) |
| 441 | #define MAX_M5_CONFIG_FGCC_SET(v) \ |
| 442 | (MAX_M5_CONFIG_FGCC_CLR(v) | MAX_M5_CONFIG_FGCC) |
| 443 | #define MAX_M5_CONFIG_AINSH_MASK 0x1 |
| 444 | #define MAX_M5_CONFIG_AINSH_SHIFT 10 |
| 445 | #define MAX_M5_CONFIG_AINSH_CLEAR (~(0x1 << 10)) |
| 446 | #define MAX_M5_CONFIG_AINSH_CLR(v) ((v) & MAX_M5_CONFIG_AINSH_CLEAR) |
| 447 | #define MAX_M5_CONFIG_AINSH_SET(v) \ |
| 448 | (MAX_M5_CONFIG_AINSH_CLR(v) | MAX_M5_CONFIG_AINSH) |
| 449 | #define MAX_M5_CONFIG_TEN_MASK 0x1 |
| 450 | #define MAX_M5_CONFIG_TEN_SHIFT 9 |
| 451 | #define MAX_M5_CONFIG_TEN_CLEAR (~(0x1 << 9)) |
| 452 | #define MAX_M5_CONFIG_TEN_CLR(v) ((v) & MAX_M5_CONFIG_TEN_CLEAR) |
| 453 | #define MAX_M5_CONFIG_TEN_SET(v) \ |
| 454 | (MAX_M5_CONFIG_TEN_CLR(v) | MAX_M5_CONFIG_TEN) |
| 455 | #define MAX_M5_CONFIG_TEX_MASK 0x1 |
| 456 | #define MAX_M5_CONFIG_TEX_SHIFT 8 |
| 457 | #define MAX_M5_CONFIG_TEX_CLEAR (~(0x1 << 8)) |
| 458 | #define MAX_M5_CONFIG_TEX_CLR(v) ((v) & MAX_M5_CONFIG_TEX_CLEAR) |
| 459 | #define MAX_M5_CONFIG_TEX_SET(v) \ |
| 460 | (MAX_M5_CONFIG_TEX_CLR(v) | MAX_M5_CONFIG_TEX) |
| 461 | #define MAX_M5_CONFIG_SHDN_MASK 0x1 |
| 462 | #define MAX_M5_CONFIG_SHDN_SHIFT 7 |
| 463 | #define MAX_M5_CONFIG_SHDN_CLEAR (~(0x1 << 7)) |
| 464 | #define MAX_M5_CONFIG_SHDN_CLR(v) ((v) & MAX_M5_CONFIG_SHDN_CLEAR) |
| 465 | #define MAX_M5_CONFIG_SHDN_SET(v) \ |
| 466 | (MAX_M5_CONFIG_SHDN_CLR(v) | MAX_M5_CONFIG_SHDN) |
| 467 | #define MAX_M5_CONFIG_I2CSH_MASK 0x1 |
| 468 | #define MAX_M5_CONFIG_I2CSH_SHIFT 6 |
| 469 | #define MAX_M5_CONFIG_I2CSH_CLEAR (~(0x1 << 6)) |
| 470 | #define MAX_M5_CONFIG_I2CSH_CLR(v) ((v) & MAX_M5_CONFIG_I2CSH_CLEAR) |
| 471 | #define MAX_M5_CONFIG_I2CSH_SET(v) \ |
| 472 | (MAX_M5_CONFIG_I2CSH_CLR(v) | MAX_M5_CONFIG_I2CSH) |
| 473 | #define MAX_M5_CONFIG_ICFE_MASK 0x1 |
| 474 | #define MAX_M5_CONFIG_ICFE_SHIFT 5 |
| 475 | #define MAX_M5_CONFIG_ICFE_CLEAR (~(0x1 << 5)) |
| 476 | #define MAX_M5_CONFIG_ICFE_CLR(v) ((v) & MAX_M5_CONFIG_ICFE_CLEAR) |
| 477 | #define MAX_M5_CONFIG_ICFE_SET(v) \ |
| 478 | (MAX_M5_CONFIG_ICFE_CLR(v) | MAX_M5_CONFIG_ICFE) |
| 479 | #define MAX_M5_CONFIG_ETHRM_MASK 0x1 |
| 480 | #define MAX_M5_CONFIG_ETHRM_SHIFT 4 |
| 481 | #define MAX_M5_CONFIG_ETHRM_CLEAR (~(0x1 << 4)) |
| 482 | #define MAX_M5_CONFIG_ETHRM_CLR(v) ((v) & MAX_M5_CONFIG_ETHRM_CLEAR) |
| 483 | #define MAX_M5_CONFIG_ETHRM_SET(v) \ |
| 484 | (MAX_M5_CONFIG_ETHRM_CLR(v) | MAX_M5_CONFIG_ETHRM) |
| 485 | #define MAX_M5_CONFIG_FTHRM_MASK 0x1 |
| 486 | #define MAX_M5_CONFIG_FTHRM_SHIFT 3 |
| 487 | #define MAX_M5_CONFIG_FTHRM_CLEAR (~(0x1 << 3)) |
| 488 | #define MAX_M5_CONFIG_FTHRM_CLR(v) ((v) & MAX_M5_CONFIG_FTHRM_CLEAR) |
| 489 | #define MAX_M5_CONFIG_FTHRM_SET(v) \ |
| 490 | (MAX_M5_CONFIG_FTHRM_CLR(v) | MAX_M5_CONFIG_FTHRM) |
| 491 | #define MAX_M5_CONFIG_AEN_MASK 0x1 |
| 492 | #define MAX_M5_CONFIG_AEN_SHIFT 2 |
| 493 | #define MAX_M5_CONFIG_AEN_CLEAR (~(0x1 << 2)) |
| 494 | #define MAX_M5_CONFIG_AEN_CLR(v) ((v) & MAX_M5_CONFIG_AEN_CLEAR) |
| 495 | #define MAX_M5_CONFIG_AEN_SET(v) \ |
| 496 | (MAX_M5_CONFIG_AEN_CLR(v) | MAX_M5_CONFIG_AEN) |
| 497 | #define MAX_M5_CONFIG_BEI_MASK 0x1 |
| 498 | #define MAX_M5_CONFIG_BEI_SHIFT 1 |
| 499 | #define MAX_M5_CONFIG_BEI_CLEAR (~(0x1 << 1)) |
| 500 | #define MAX_M5_CONFIG_BEI_CLR(v) ((v) & MAX_M5_CONFIG_BEI_CLEAR) |
| 501 | #define MAX_M5_CONFIG_BEI_SET(v) \ |
| 502 | (MAX_M5_CONFIG_BEI_CLR(v) | MAX_M5_CONFIG_BEI) |
| 503 | #define MAX_M5_CONFIG_BER_MASK 0x1 |
| 504 | #define MAX_M5_CONFIG_BER_SHIFT 0 |
| 505 | #define MAX_M5_CONFIG_BER_CLEAR (~(0x1 << 0)) |
| 506 | #define MAX_M5_CONFIG_BER_CLR(v) ((v) & MAX_M5_CONFIG_BER_CLEAR) |
| 507 | #define MAX_M5_CONFIG_BER_SET(v) \ |
| 508 | (MAX_M5_CONFIG_BER_CLR(v) | MAX_M5_CONFIG_BER) |
| 509 | |
| 510 | /* IChgTerm,0x1E,0b1111000000,0x3c0 |
| 511 | * ICHGTerm[15:8],,,,,, |
| 512 | */ |
| 513 | #define MAX_M5_ICHGTERM 0x1E |
| 514 | |
| 515 | /* AvCap,0x1F,0b10111011100,0x5dc |
| 516 | * AvCap[15:8],,,,,, |
| 517 | */ |
| 518 | #define MAX_M5_AVCAP 0x1F |
| 519 | |
| 520 | /* TTF,0x20,0b1111111111111111,0xffff |
| 521 | * hr[5:0],,,,,,mn[5:4] |
| 522 | */ |
| 523 | #define MAX_M5_TTF 0x20 |
| 524 | #define MAX_M5_TTF_HR (0x3f << 10) |
| 525 | #define MAX_M5_TTF_MN (0x3f << 4) |
| 526 | #define MAX_M5_TTF_SEC (0xf << 0) |
| 527 | |
| 528 | #define MAX_M5_TTF_HR_MASK 0x3f |
| 529 | #define MAX_M5_TTF_HR_SHIFT 10 |
| 530 | #define MAX_M5_TTF_HR_CLEAR (~(0x3f << 10)) |
| 531 | #define MAX_M5_TTF_HR_CLR(v) ((v) & MAX_M5_TTF_HR_CLEAR) |
| 532 | #define MAX_M5_TTF_HR_SET(v) (MAX_M5_TTF_HR_CLR(v) | MAX_M5_TTF_HR) |
| 533 | #define MAX_M5_TTF_MN_MASK 0x3f |
| 534 | #define MAX_M5_TTF_MN_SHIFT 4 |
| 535 | #define MAX_M5_TTF_MN_CLEAR (~(0x3f << 4)) |
| 536 | #define MAX_M5_TTF_MN_CLR(v) ((v) & MAX_M5_TTF_MN_CLEAR) |
| 537 | #define MAX_M5_TTF_MN_SET(v) (MAX_M5_TTF_MN_CLR(v) | MAX_M5_TTF_MN) |
| 538 | #define MAX_M5_TTF_SEC_MASK 0xf |
| 539 | #define MAX_M5_TTF_SEC_SHIFT 0 |
| 540 | #define MAX_M5_TTF_SEC_CLEAR (~(0xf << 0)) |
| 541 | #define MAX_M5_TTF_SEC_CLR(v) ((v) & MAX_M5_TTF_SEC_CLEAR) |
| 542 | #define MAX_M5_TTF_SEC_SET(v) \ |
| 543 | (MAX_M5_TTF_SEC_CLR(v) | MAX_M5_TTF_SEC) |
| 544 | |
| 545 | /* DevName,0x21,0b110001000000000,0x6200 |
| 546 | * DevName[15:8],,,,,, |
| 547 | */ |
| 548 | #define MAX_M5_DEVNAME 0x21 |
| 549 | |
| 550 | /* QRTable10,0x22,0b1101110000000,0x1b80 |
| 551 | * QRTable10[15:8],,,,,, |
| 552 | */ |
| 553 | #define MAX_M5_QRTABLE10 0x22 |
| 554 | |
| 555 | /* FullCapNom,0x23,0b101110111000,0xbb8 |
| 556 | * FullCapNom[15:8],,,,,, |
| 557 | */ |
| 558 | #define MAX_M5_FULLCAPNOM 0x23 |
| 559 | |
| 560 | /* TempNom,0x24,0b1010000000000,0x1400 |
| 561 | * TempNom[9:2],,,,,, |
| 562 | */ |
| 563 | #define MAX_M5_TEMPNOM 0x24 |
| 564 | #define MAX_M5_TEMPNOM_TEMPNOM (0x3ff << 6) |
| 565 | #define MAX_M5_TEMPNOM_SPR_5_0 (0x3f << 0) |
| 566 | |
| 567 | #define MAX_M5_TEMPNOM_TEMPNOM_MASK 0x3ff |
| 568 | #define MAX_M5_TEMPNOM_TEMPNOM_SHIFT 6 |
| 569 | #define MAX_M5_TEMPNOM_TEMPNOM_CLEAR (~(0x3ff << 6)) |
| 570 | #define MAX_M5_TEMPNOM_TEMPNOM_CLR(v) \ |
| 571 | ((v) & MAX_M5_TEMPNOM_TEMPNOM_CLEAR) |
| 572 | #define MAX_M5_TEMPNOM_TEMPNOM_SET(v) \ |
| 573 | (MAX_M5_TEMPNOM_TEMPNOM_CLR(v) | MAX_M5_TEMPNOM_TEMPNOM) |
| 574 | #define MAX_M5_TEMPNOM_SPR_5_0_MASK 0x3f |
| 575 | #define MAX_M5_TEMPNOM_SPR_5_0_SHIFT 0 |
| 576 | #define MAX_M5_TEMPNOM_SPR_5_0_CLEAR (~(0x3f << 0)) |
| 577 | #define MAX_M5_TEMPNOM_SPR_5_0_CLR(v) \ |
| 578 | ((v) & MAX_M5_TEMPNOM_SPR_5_0_CLEAR) |
| 579 | #define MAX_M5_TEMPNOM_SPR_5_0_SET(v) \ |
| 580 | (MAX_M5_TEMPNOM_SPR_5_0_CLR(v) | MAX_M5_TEMPNOM_SPR_5_0) |
| 581 | |
| 582 | /* TempLim,0x25,0b10001100000101,0x2305 |
| 583 | * TempHot[7:0],,,,,, |
| 584 | */ |
| 585 | #define MAX_M5_TEMPLIM 0x25 |
| 586 | #define MAX_M5_TEMPLIM_TEMPHOT (0xff << 8) |
| 587 | #define MAX_M5_TEMPLIM_TEMPCOLD (0xff << 0) |
| 588 | |
| 589 | #define MAX_M5_TEMPLIM_TEMPHOT_MASK 0xff |
| 590 | #define MAX_M5_TEMPLIM_TEMPHOT_SHIFT 8 |
| 591 | #define MAX_M5_TEMPLIM_TEMPHOT_CLEAR (~(0xff << 8)) |
| 592 | #define MAX_M5_TEMPLIM_TEMPHOT_CLR(v) \ |
| 593 | ((v) & MAX_M5_TEMPLIM_TEMPHOT_CLEAR) |
| 594 | #define MAX_M5_TEMPLIM_TEMPHOT_SET(v) \ |
| 595 | (MAX_M5_TEMPLIM_TEMPHOT_CLR(v) | MAX_M5_TEMPLIM_TEMPHOT) |
| 596 | #define MAX_M5_TEMPLIM_TEMPCOLD_MASK 0xff |
| 597 | #define MAX_M5_TEMPLIM_TEMPCOLD_SHIFT 0 |
| 598 | #define MAX_M5_TEMPLIM_TEMPCOLD_CLEAR (~(0xff << 0)) |
| 599 | #define MAX_M5_TEMPLIM_TEMPCOLD_CLR(v) \ |
| 600 | ((v) & MAX_M5_TEMPLIM_TEMPCOLD_CLEAR) |
| 601 | #define MAX_M5_TEMPLIM_TEMPCOLD_SET(v) \ |
| 602 | (MAX_M5_TEMPLIM_TEMPCOLD_CLR(v) | MAX_M5_TEMPLIM_TEMPCOLD) |
| 603 | |
| 604 | /* AvgTA0,0x26,0b1011000000000,0x1600 |
| 605 | * AvgTA0[15:8],,,,,, |
| 606 | */ |
| 607 | #define MAX_M5_AVGTA0 0x26 |
| 608 | |
| 609 | /* AIN0,0x27,0b1000100011010000,0x88d0 |
| 610 | * AIN0[15:8],,,,,, |
| 611 | */ |
| 612 | #define MAX_M5_AIN0 0x27 |
| 613 | |
| 614 | /* LearnCfg,0x28,0b10011000000011,0x2603 |
| 615 | * LearnRCOMP[2:0],,,LearnTCO[2:0],,,FCLm[1:0] |
| 616 | */ |
| 617 | #define MAX_M5_LEARNCFG 0x28 |
| 618 | #define MAX_M5_LEARNCFG_LEARNRCOMP (0x7 << 13) |
| 619 | #define MAX_M5_LEARNCFG_LEARNTCO (0x7 << 10) |
| 620 | #define MAX_M5_LEARNCFG_FCLM (0x3 << 8) |
| 621 | #define MAX_M5_LEARNCFG_FCX (0x1 << 7) |
| 622 | #define MAX_M5_LEARNCFG_FCLRNSTAGE (0x7 << 4) |
| 623 | #define MAX_M5_LEARNCFG_SPR_3 (0x1 << 3) |
| 624 | #define MAX_M5_LEARNCFG_FILLEMPTY (0x1 << 2) |
| 625 | #define MAX_M5_LEARNCFG_MIXEN (0x1 << 1) |
| 626 | #define MAX_M5_LEARNCFG_SPR_0 (0x1 << 0) |
| 627 | |
| 628 | #define MAX_M5_LEARNCFG_LEARNRCOMP_MASK 0x7 |
| 629 | #define MAX_M5_LEARNCFG_LEARNRCOMP_SHIFT 13 |
| 630 | #define MAX_M5_LEARNCFG_LEARNRCOMP_CLEAR (~(0x7 << 13)) |
| 631 | #define MAX_M5_LEARNCFG_LEARNRCOMP_CLR(v) \ |
| 632 | ((v) & MAX_M5_LEARNCFG_LEARNRCOMP_CLEAR) |
| 633 | #define MAX_M5_LEARNCFG_LEARNRCOMP_SET(v) \ |
| 634 | (MAX_M5_LEARNCFG_LEARNRCOMP_CLR(v) | MAX_M5_LEARNCFG_LEARNRCOMP) |
| 635 | #define MAX_M5_LEARNCFG_LEARNTCO_MASK 0x7 |
| 636 | #define MAX_M5_LEARNCFG_LEARNTCO_SHIFT 10 |
| 637 | #define MAX_M5_LEARNCFG_LEARNTCO_CLEAR (~(0x7 << 10)) |
| 638 | #define MAX_M5_LEARNCFG_LEARNTCO_CLR(v) \ |
| 639 | ((v) & MAX_M5_LEARNCFG_LEARNTCO_CLEAR) |
| 640 | #define MAX_M5_LEARNCFG_LEARNTCO_SET(v) \ |
| 641 | (MAX_M5_LEARNCFG_LEARNTCO_CLR(v) | MAX_M5_LEARNCFG_LEARNTCO) |
| 642 | #define MAX_M5_LEARNCFG_FCLM_MASK 0x3 |
| 643 | #define MAX_M5_LEARNCFG_FCLM_SHIFT 8 |
| 644 | #define MAX_M5_LEARNCFG_FCLM_CLEAR (~(0x3 << 8)) |
| 645 | #define MAX_M5_LEARNCFG_FCLM_CLR(v) \ |
| 646 | ((v) & MAX_M5_LEARNCFG_FCLM_CLEAR) |
| 647 | #define MAX_M5_LEARNCFG_FCLM_SET(v) \ |
| 648 | (MAX_M5_LEARNCFG_FCLM_CLR(v) | MAX_M5_LEARNCFG_FCLM) |
| 649 | #define MAX_M5_LEARNCFG_FCX_MASK 0x1 |
| 650 | #define MAX_M5_LEARNCFG_FCX_SHIFT 7 |
| 651 | #define MAX_M5_LEARNCFG_FCX_CLEAR (~(0x1 << 7)) |
| 652 | #define MAX_M5_LEARNCFG_FCX_CLR(v) ((v) & MAX_M5_LEARNCFG_FCX_CLEAR) |
| 653 | #define MAX_M5_LEARNCFG_FCX_SET(v) \ |
| 654 | (MAX_M5_LEARNCFG_FCX_CLR(v) | MAX_M5_LEARNCFG_FCX) |
| 655 | #define MAX_M5_LEARNCFG_FCLRNSTAGE_MASK 0x7 |
| 656 | #define MAX_M5_LEARNCFG_FCLRNSTAGE_SHIFT 4 |
| 657 | #define MAX_M5_LEARNCFG_FCLRNSTAGE_CLEAR (~(0x7 << 4)) |
| 658 | #define MAX_M5_LEARNCFG_FCLRNSTAGE_CLR(v) \ |
| 659 | ((v) & MAX_M5_LEARNCFG_FCLRNSTAGE_CLEAR) |
| 660 | #define MAX_M5_LEARNCFG_FCLRNSTAGE_SET(v) \ |
| 661 | (MAX_M5_LEARNCFG_FCLRNSTAGE_CLR(v) | MAX_M5_LEARNCFG_FCLRNSTAGE) |
| 662 | #define MAX_M5_LEARNCFG_SPR_3_MASK 0x1 |
| 663 | #define MAX_M5_LEARNCFG_SPR_3_SHIFT 3 |
| 664 | #define MAX_M5_LEARNCFG_SPR_3_CLEAR (~(0x1 << 3)) |
| 665 | #define MAX_M5_LEARNCFG_SPR_3_CLR(v) \ |
| 666 | ((v) & MAX_M5_LEARNCFG_SPR_3_CLEAR) |
| 667 | #define MAX_M5_LEARNCFG_SPR_3_SET(v) \ |
| 668 | (MAX_M5_LEARNCFG_SPR_3_CLR(v) | MAX_M5_LEARNCFG_SPR_3) |
| 669 | #define MAX_M5_LEARNCFG_FILLEMPTY_MASK 0x1 |
| 670 | #define MAX_M5_LEARNCFG_FILLEMPTY_SHIFT 2 |
| 671 | #define MAX_M5_LEARNCFG_FILLEMPTY_CLEAR (~(0x1 << 2)) |
| 672 | #define MAX_M5_LEARNCFG_FILLEMPTY_CLR(v) \ |
| 673 | ((v) & MAX_M5_LEARNCFG_FILLEMPTY_CLEAR) |
| 674 | #define MAX_M5_LEARNCFG_FILLEMPTY_SET(v) \ |
| 675 | (MAX_M5_LEARNCFG_FILLEMPTY_CLR(v) | MAX_M5_LEARNCFG_FILLEMPTY) |
| 676 | #define MAX_M5_LEARNCFG_MIXEN_MASK 0x1 |
| 677 | #define MAX_M5_LEARNCFG_MIXEN_SHIFT 1 |
| 678 | #define MAX_M5_LEARNCFG_MIXEN_CLEAR (~(0x1 << 1)) |
| 679 | #define MAX_M5_LEARNCFG_MIXEN_CLR(v) \ |
| 680 | ((v) & MAX_M5_LEARNCFG_MIXEN_CLEAR) |
| 681 | #define MAX_M5_LEARNCFG_MIXEN_SET(v) \ |
| 682 | (MAX_M5_LEARNCFG_MIXEN_CLR(v) | MAX_M5_LEARNCFG_MIXEN) |
| 683 | #define MAX_M5_LEARNCFG_SPR_0_MASK 0x1 |
| 684 | #define MAX_M5_LEARNCFG_SPR_0_SHIFT 0 |
| 685 | #define MAX_M5_LEARNCFG_SPR_0_CLEAR (~(0x1 << 0)) |
| 686 | #define MAX_M5_LEARNCFG_SPR_0_CLR(v) \ |
| 687 | ((v) & MAX_M5_LEARNCFG_SPR_0_CLEAR) |
| 688 | #define MAX_M5_LEARNCFG_SPR_0_SET(v) \ |
| 689 | (MAX_M5_LEARNCFG_SPR_0_CLR(v) | MAX_M5_LEARNCFG_SPR_0) |
| 690 | |
| Jenny Ho | c6bc588 | 2021-02-18 09:21:21 +0800 | [diff] [blame] | 691 | /* RC is customizable in MWA1+, not in datasheet */ |
| 692 | #define MAX_M5_LEARNCFG_RC_VER_MASK MAX_M5_LEARNCFG_SPR_3_MASK |
| 693 | #define MAX_M5_LEARNCFG_RC_VER_SHIFT MAX_M5_LEARNCFG_SPR_3_SHIFT |
| 694 | #define MAX_M5_LEARNCFG_RC_VER_CLEAR MAX_M5_LEARNCFG_SPR_3_CLEAR |
| 695 | #define MAX_M5_LEARNCFG_RC_VER_CLR(v) MAX_M5_LEARNCFG_SPR_3_CLR(v) |
| 696 | #define MAX_M5_LEARNCFG_RC_VER_SET(v) MAX_M5_LEARNCFG_SPR_3_SET(v) |
| 697 | |
| 698 | #define MAX_M5_LEARNCFG_RC_VER MAX_M5_LEARNCFG_SPR_3 |
| 699 | #define MAX_M5_LEARNCFG_RC1 (0x0 << MAX_M5_LEARNCFG_RC_VER_SHIFT) |
| 700 | #define MAX_M5_LEARNCFG_RC2 (0x1 << MAX_M5_LEARNCFG_RC_VER_SHIFT) |
| 701 | |
| Ken Tsou | 8acade1 | 2020-07-09 03:17:35 +0800 | [diff] [blame] | 702 | /* FilterCfg,0x29,0b1100111010100100,0xcea4 |
| 703 | * NEMPTY[1:0],,NTEMP[2:0],,,NMIX[3:1], |
| 704 | */ |
| 705 | #define MAX_M5_FILTERCFG 0x29 |
| 706 | #define MAX_M5_FILTERCFG_NEMPTY (0x3 << 14) |
| 707 | #define MAX_M5_FILTERCFG_NTEMP (0x7 << 11) |
| 708 | #define MAX_M5_FILTERCFG_NMIX (0x7 << 8) |
| 709 | #define MAX_M5_FILTERCFG_NAVGCELL (0x7 << 5) |
| 710 | #define MAX_M5_FILTERCFG_NCURR (0xf << 1) |
| 711 | |
| 712 | #define MAX_M5_FILTERCFG_NEMPTY_MASK 0x3 |
| 713 | #define MAX_M5_FILTERCFG_NEMPTY_SHIFT 14 |
| 714 | #define MAX_M5_FILTERCFG_NEMPTY_CLEAR (~(0x3 << 14)) |
| 715 | #define MAX_M5_FILTERCFG_NEMPTY_CLR(v) \ |
| 716 | ((v) & MAX_M5_FILTERCFG_NEMPTY_CLEAR) |
| 717 | #define MAX_M5_FILTERCFG_NEMPTY_SET(v) \ |
| 718 | (MAX_M5_FILTERCFG_NEMPTY_CLR(v) | MAX_M5_FILTERCFG_NEMPTY) |
| 719 | #define MAX_M5_FILTERCFG_NTEMP_MASK 0x7 |
| 720 | #define MAX_M5_FILTERCFG_NTEMP_SHIFT 11 |
| 721 | #define MAX_M5_FILTERCFG_NTEMP_CLEAR (~(0x7 << 11)) |
| 722 | #define MAX_M5_FILTERCFG_NTEMP_CLR(v) \ |
| 723 | ((v) & MAX_M5_FILTERCFG_NTEMP_CLEAR) |
| 724 | #define MAX_M5_FILTERCFG_NTEMP_SET(v) \ |
| 725 | (MAX_M5_FILTERCFG_NTEMP_CLR(v) | MAX_M5_FILTERCFG_NTEMP) |
| 726 | #define MAX_M5_FILTERCFG_NMIX_MASK 0x7 |
| 727 | #define MAX_M5_FILTERCFG_NMIX_SHIFT 8 |
| 728 | #define MAX_M5_FILTERCFG_NMIX_CLEAR (~(0x7 << 8)) |
| 729 | #define MAX_M5_FILTERCFG_NMIX_CLR(v) \ |
| 730 | ((v) & MAX_M5_FILTERCFG_NMIX_CLEAR) |
| 731 | #define MAX_M5_FILTERCFG_NMIX_SET(v) \ |
| 732 | (MAX_M5_FILTERCFG_NMIX_CLR(v) | MAX_M5_FILTERCFG_NMIX) |
| 733 | #define MAX_M5_FILTERCFG_NAVGCELL_MASK 0x7 |
| 734 | #define MAX_M5_FILTERCFG_NAVGCELL_SHIFT 5 |
| 735 | #define MAX_M5_FILTERCFG_NAVGCELL_CLEAR (~(0x7 << 5)) |
| 736 | #define MAX_M5_FILTERCFG_NAVGCELL_CLR(v) \ |
| 737 | ((v) & MAX_M5_FILTERCFG_NAVGCELL_CLEAR) |
| 738 | #define MAX_M5_FILTERCFG_NAVGCELL_SET(v) \ |
| 739 | (MAX_M5_FILTERCFG_NAVGCELL_CLR(v) | MAX_M5_FILTERCFG_NAVGCELL) |
| 740 | #define MAX_M5_FILTERCFG_NCURR_MASK 0xf |
| 741 | #define MAX_M5_FILTERCFG_NCURR_SHIFT 1 |
| 742 | #define MAX_M5_FILTERCFG_NCURR_CLEAR (~(0xf << 1)) |
| 743 | #define MAX_M5_FILTERCFG_NCURR_CLR(v) \ |
| 744 | ((v) & MAX_M5_FILTERCFG_NCURR_CLEAR) |
| 745 | #define MAX_M5_FILTERCFG_NCURR_SET(v) \ |
| 746 | (MAX_M5_FILTERCFG_NCURR_CLR(v) | MAX_M5_FILTERCFG_NCURR) |
| 747 | |
| 748 | /* RelaxCfg,0x2A,0b10000011001001,0x20c9 |
| 749 | * LoadThr[6:0],,,,,, |
| 750 | */ |
| 751 | #define MAX_M5_RELAXCFG 0x2A |
| 752 | #define MAX_M5_RELAXCFG_LOADTHR (0x7f << 9) |
| 753 | #define MAX_M5_RELAXCFG_DVTHR (0xf << 4) |
| 754 | #define MAX_M5_RELAXCFG_DTTHR (0xf << 0) |
| 755 | |
| 756 | #define MAX_M5_RELAXCFG_LOADTHR_MASK 0x7f |
| 757 | #define MAX_M5_RELAXCFG_LOADTHR_SHIFT 9 |
| 758 | #define MAX_M5_RELAXCFG_LOADTHR_CLEAR (~(0x7f << 9)) |
| 759 | #define MAX_M5_RELAXCFG_LOADTHR_CLR(v) \ |
| 760 | ((v) & MAX_M5_RELAXCFG_LOADTHR_CLEAR) |
| 761 | #define MAX_M5_RELAXCFG_LOADTHR_SET(v) \ |
| 762 | (MAX_M5_RELAXCFG_LOADTHR_CLR(v) | MAX_M5_RELAXCFG_LOADTHR) |
| 763 | #define MAX_M5_RELAXCFG_DVTHR_MASK 0xf |
| 764 | #define MAX_M5_RELAXCFG_DVTHR_SHIFT 4 |
| 765 | #define MAX_M5_RELAXCFG_DVTHR_CLEAR (~(0xf << 4)) |
| 766 | #define MAX_M5_RELAXCFG_DVTHR_CLR(v) \ |
| 767 | ((v) & MAX_M5_RELAXCFG_DVTHR_CLEAR) |
| 768 | #define MAX_M5_RELAXCFG_DVTHR_SET(v) \ |
| 769 | (MAX_M5_RELAXCFG_DVTHR_CLR(v) | MAX_M5_RELAXCFG_DVTHR) |
| 770 | #define MAX_M5_RELAXCFG_DTTHR_MASK 0xf |
| 771 | #define MAX_M5_RELAXCFG_DTTHR_SHIFT 0 |
| 772 | #define MAX_M5_RELAXCFG_DTTHR_CLEAR (~(0xf << 0)) |
| 773 | #define MAX_M5_RELAXCFG_DTTHR_CLR(v) \ |
| 774 | ((v) & MAX_M5_RELAXCFG_DTTHR_CLEAR) |
| 775 | #define MAX_M5_RELAXCFG_DTTHR_SET(v) \ |
| 776 | (MAX_M5_RELAXCFG_DTTHR_CLR(v) | MAX_M5_RELAXCFG_DTTHR) |
| 777 | |
| 778 | /* MiscCfg,0x2B,0b100111010000,0x9d0 |
| 779 | * OopsFilter[3:0],,,,EnBi1,InitVFG,MixRate[4:3] |
| 780 | */ |
| 781 | #define MAX_M5_MISCCFG 0x2B |
| 782 | #define MAX_M5_MISCCFG_OOPSFILTER (0xf << 12) |
| 783 | #define MAX_M5_MISCCFG_ENBI1 (0x1 << 11) |
| 784 | #define MAX_M5_MISCCFG_INITVFG (0x1 << 10) |
| 785 | #define MAX_M5_MISCCFG_MIXRATE (0x1f << 5) |
| 786 | #define MAX_M5_MISCCFG_RDFCLRN (0x1 << 4) |
| 787 | #define MAX_M5_MISCCFG_VTTL (0x1 << 3) |
| 788 | #define MAX_M5_MISCCFG_VEX (0x1 << 2) |
| 789 | #define MAX_M5_MISCCFG_SACFG (0x3 << 0) |
| 790 | |
| 791 | #define MAX_M5_MISCCFG_OOPSFILTER_MASK 0xf |
| 792 | #define MAX_M5_MISCCFG_OOPSFILTER_SHIFT 12 |
| 793 | #define MAX_M5_MISCCFG_OOPSFILTER_CLEAR (~(0xf << 12)) |
| 794 | #define MAX_M5_MISCCFG_OOPSFILTER_CLR(v) \ |
| 795 | ((v) & MAX_M5_MISCCFG_OOPSFILTER_CLEAR) |
| 796 | #define MAX_M5_MISCCFG_OOPSFILTER_SET(v) \ |
| 797 | (MAX_M5_MISCCFG_OOPSFILTER_CLR(v) | MAX_M5_MISCCFG_OOPSFILTER) |
| 798 | #define MAX_M5_MISCCFG_ENBI1_MASK 0x1 |
| 799 | #define MAX_M5_MISCCFG_ENBI1_SHIFT 11 |
| 800 | #define MAX_M5_MISCCFG_ENBI1_CLEAR (~(0x1 << 11)) |
| 801 | #define MAX_M5_MISCCFG_ENBI1_CLR(v) \ |
| 802 | ((v) & MAX_M5_MISCCFG_ENBI1_CLEAR) |
| 803 | #define MAX_M5_MISCCFG_ENBI1_SET(v) \ |
| 804 | (MAX_M5_MISCCFG_ENBI1_CLR(v) | MAX_M5_MISCCFG_ENBI1) |
| 805 | #define MAX_M5_MISCCFG_INITVFG_MASK 0x1 |
| 806 | #define MAX_M5_MISCCFG_INITVFG_SHIFT 10 |
| 807 | #define MAX_M5_MISCCFG_INITVFG_CLEAR (~(0x1 << 10)) |
| 808 | #define MAX_M5_MISCCFG_INITVFG_CLR(v) \ |
| 809 | ((v) & MAX_M5_MISCCFG_INITVFG_CLEAR) |
| 810 | #define MAX_M5_MISCCFG_INITVFG_SET(v) \ |
| 811 | (MAX_M5_MISCCFG_INITVFG_CLR(v) | MAX_M5_MISCCFG_INITVFG) |
| 812 | #define MAX_M5_MISCCFG_MIXRATE_MASK 0x1f |
| 813 | #define MAX_M5_MISCCFG_MIXRATE_SHIFT 5 |
| 814 | #define MAX_M5_MISCCFG_MIXRATE_CLEAR (~(0x1f << 5)) |
| 815 | #define MAX_M5_MISCCFG_MIXRATE_CLR(v) \ |
| 816 | ((v) & MAX_M5_MISCCFG_MIXRATE_CLEAR) |
| 817 | #define MAX_M5_MISCCFG_MIXRATE_SET(v) \ |
| 818 | (MAX_M5_MISCCFG_MIXRATE_CLR(v) | MAX_M5_MISCCFG_MIXRATE) |
| 819 | #define MAX_M5_MISCCFG_RDFCLRN_MASK 0x1 |
| 820 | #define MAX_M5_MISCCFG_RDFCLRN_SHIFT 4 |
| 821 | #define MAX_M5_MISCCFG_RDFCLRN_CLEAR (~(0x1 << 4)) |
| 822 | #define MAX_M5_MISCCFG_RDFCLRN_CLR(v) \ |
| 823 | ((v) & MAX_M5_MISCCFG_RDFCLRN_CLEAR) |
| 824 | #define MAX_M5_MISCCFG_RDFCLRN_SET(v) \ |
| 825 | (MAX_M5_MISCCFG_RDFCLRN_CLR(v) | MAX_M5_MISCCFG_RDFCLRN) |
| 826 | #define MAX_M5_MISCCFG_VTTL_MASK 0x1 |
| 827 | #define MAX_M5_MISCCFG_VTTL_SHIFT 3 |
| 828 | #define MAX_M5_MISCCFG_VTTL_CLEAR (~(0x1 << 3)) |
| 829 | #define MAX_M5_MISCCFG_VTTL_CLR(v) ((v) & MAX_M5_MISCCFG_VTTL_CLEAR) |
| 830 | #define MAX_M5_MISCCFG_VTTL_SET(v) \ |
| 831 | (MAX_M5_MISCCFG_VTTL_CLR(v) | MAX_M5_MISCCFG_VTTL) |
| 832 | #define MAX_M5_MISCCFG_VEX_MASK 0x1 |
| 833 | #define MAX_M5_MISCCFG_VEX_SHIFT 2 |
| 834 | #define MAX_M5_MISCCFG_VEX_CLEAR (~(0x1 << 2)) |
| 835 | #define MAX_M5_MISCCFG_VEX_CLR(v) ((v) & MAX_M5_MISCCFG_VEX_CLEAR) |
| 836 | #define MAX_M5_MISCCFG_VEX_SET(v) \ |
| 837 | (MAX_M5_MISCCFG_VEX_CLR(v) | MAX_M5_MISCCFG_VEX) |
| 838 | #define MAX_M5_MISCCFG_SACFG_MASK 0x3 |
| 839 | #define MAX_M5_MISCCFG_SACFG_SHIFT 0 |
| 840 | #define MAX_M5_MISCCFG_SACFG_CLEAR (~(0x3 << 0)) |
| 841 | #define MAX_M5_MISCCFG_SACFG_CLR(v) \ |
| 842 | ((v) & MAX_M5_MISCCFG_SACFG_CLEAR) |
| 843 | #define MAX_M5_MISCCFG_SACFG_SET(v) \ |
| 844 | (MAX_M5_MISCCFG_SACFG_CLR(v) | MAX_M5_MISCCFG_SACFG) |
| 845 | |
| 846 | /* TGain,0x2C,0b1110101110001101,0xeb8d |
| 847 | * TGAIN[15:8],,,,,, |
| 848 | */ |
| 849 | #define MAX_M5_TGAIN 0x2C |
| 850 | |
| 851 | /* TOff,0x2D,0b10000010101010,0x20aa |
| 852 | * TOFF[15:8],,,,,, |
| 853 | */ |
| 854 | #define MAX_M5_TOFF 0x2D |
| 855 | |
| 856 | /* CGain,0x2E,0b10000000000,0x400 |
| 857 | * CGAIN[15:8],,,,,, |
| 858 | */ |
| 859 | #define MAX_M5_CGAIN 0x2E |
| 860 | |
| 861 | /* COff,0x2F,0b00000000,0x00 |
| 862 | * COFF[15:8],,,,,, |
| 863 | */ |
| 864 | #define MAX_M5_COFF 0x2F |
| 865 | |
| 866 | /* dV_acc,0x30,0b10000000000,0x400 |
| 867 | * dV_acc[15:8],,,,,, |
| 868 | */ |
| 869 | #define MAX_M5_DV_ACC 0x30 |
| 870 | |
| 871 | /* dI_acc,0x31,0b11001000000,0x640 |
| 872 | * dI_acc[15:8],,,,,, |
| 873 | */ |
| 874 | #define MAX_M5_DI_ACC 0x31 |
| 875 | |
| 876 | /* QRTable20,0x32,0b101100000100,0xb04 |
| 877 | * QRTable20[15:8],,,,,, |
| 878 | */ |
| 879 | #define MAX_M5_QRTABLE20 0x32 |
| 880 | |
| 881 | /* AtTTF,0x33,0b1111111111111111,0xffff |
| 882 | * AtTTF[15:8],,,,,, |
| 883 | */ |
| 884 | #define MAX_M5_ATTTF 0x33 |
| 885 | |
| 886 | /* TConvert,0x34,0b1011000000000,0x1600 |
| 887 | * TConvert[15:8],,,,,, |
| 888 | */ |
| 889 | #define MAX_M5_TCONVERT 0x34 |
| 890 | |
| 891 | /* FullCapRep,0x35,0b101110111000,0xbb8 |
| 892 | * FullCapRep[15:8],,,,,, |
| 893 | */ |
| 894 | #define MAX_M5_FULLCAPREP 0x35 |
| 895 | |
| 896 | /* IAvgEmpty,0x36,0b1111010001001000,0xf448 |
| 897 | * Iavg_empty[15:8],,,,,, |
| 898 | */ |
| 899 | #define MAX_M5_IAVGEMPTY 0x36 |
| 900 | |
| 901 | /* FCTC,0x37,0b10111100000,0x5e0 |
| 902 | * FCTC[15:8],,,,,, |
| 903 | */ |
| 904 | #define MAX_M5_FCTC 0x37 |
| 905 | |
| 906 | /* RComp0,0x38,0b01110000,0x70 |
| 907 | * SPR_15_8[7:0],,,,,, |
| 908 | */ |
| 909 | #define MAX_M5_RCOMP0 0x38 |
| 910 | #define MAX_M5_RCOMP0_SPR_15_8 (0xff << 8) |
| 911 | #define MAX_M5_RCOMP0_RCOMP0 (0xff << 0) |
| 912 | |
| 913 | #define MAX_M5_RCOMP0_SPR_15_8_MASK 0xff |
| 914 | #define MAX_M5_RCOMP0_SPR_15_8_SHIFT 8 |
| 915 | #define MAX_M5_RCOMP0_SPR_15_8_CLEAR (~(0xff << 8)) |
| 916 | #define MAX_M5_RCOMP0_SPR_15_8_CLR(v) \ |
| 917 | ((v) & MAX_M5_RCOMP0_SPR_15_8_CLEAR) |
| 918 | #define MAX_M5_RCOMP0_SPR_15_8_SET(v) \ |
| 919 | (MAX_M5_RCOMP0_SPR_15_8_CLR(v) | MAX_M5_RCOMP0_SPR_15_8) |
| 920 | #define MAX_M5_RCOMP0_RCOMP0_MASK 0xff |
| 921 | #define MAX_M5_RCOMP0_RCOMP0_SHIFT 0 |
| 922 | #define MAX_M5_RCOMP0_RCOMP0_CLEAR (~(0xff << 0)) |
| 923 | #define MAX_M5_RCOMP0_RCOMP0_CLR(v) \ |
| 924 | ((v) & MAX_M5_RCOMP0_RCOMP0_CLEAR) |
| 925 | #define MAX_M5_RCOMP0_RCOMP0_SET(v) \ |
| 926 | (MAX_M5_RCOMP0_RCOMP0_CLR(v) | MAX_M5_RCOMP0_RCOMP0) |
| 927 | |
| 928 | /* TempCo,0x39,0b10011000111101,0x263d |
| 929 | * TempCoHot[7:0],,,,,, |
| 930 | */ |
| 931 | #define MAX_M5_TEMPCO 0x39 |
| 932 | #define MAX_M5_TEMPCO_TEMPCOHOT (0xff << 8) |
| 933 | #define MAX_M5_TEMPCO_TEMPCOCOLD (0xff << 0) |
| 934 | |
| 935 | #define MAX_M5_TEMPCO_TEMPCOHOT_MASK 0xff |
| 936 | #define MAX_M5_TEMPCO_TEMPCOHOT_SHIFT 8 |
| 937 | #define MAX_M5_TEMPCO_TEMPCOHOT_CLEAR (~(0xff << 8)) |
| 938 | #define MAX_M5_TEMPCO_TEMPCOHOT_CLR(v) \ |
| 939 | ((v) & MAX_M5_TEMPCO_TEMPCOHOT_CLEAR) |
| 940 | #define MAX_M5_TEMPCO_TEMPCOHOT_SET(v) \ |
| 941 | (MAX_M5_TEMPCO_TEMPCOHOT_CLR(v) | MAX_M5_TEMPCO_TEMPCOHOT) |
| 942 | #define MAX_M5_TEMPCO_TEMPCOCOLD_MASK 0xff |
| 943 | #define MAX_M5_TEMPCO_TEMPCOCOLD_SHIFT 0 |
| 944 | #define MAX_M5_TEMPCO_TEMPCOCOLD_CLEAR (~(0xff << 0)) |
| 945 | #define MAX_M5_TEMPCO_TEMPCOCOLD_CLR(v) \ |
| 946 | ((v) & MAX_M5_TEMPCO_TEMPCOCOLD_CLEAR) |
| 947 | #define MAX_M5_TEMPCO_TEMPCOCOLD_SET(v) \ |
| 948 | (MAX_M5_TEMPCO_TEMPCOCOLD_CLR(v) | MAX_M5_TEMPCO_TEMPCOCOLD) |
| 949 | |
| 950 | /* VEmpty,0x3A,0b1010010101100001,0xa561 |
| 951 | * V_Empty[8:1],,,,,, |
| 952 | */ |
| 953 | #define MAX_M5_VEMPTY 0x3A |
| 954 | #define MAX_M5_VEMPTY_V_EMPTY (0xff << 8) |
| 955 | #define MAX_M5_VEMPTY_V_RECOVER (0x7f << 1) |
| 956 | |
| 957 | #define MAX_M5_VEMPTY_V_EMPTY_MASK 0xff |
| 958 | #define MAX_M5_VEMPTY_V_EMPTY_SHIFT 8 |
| 959 | #define MAX_M5_VEMPTY_V_EMPTY_CLEAR (~(0xff << 8)) |
| 960 | #define MAX_M5_VEMPTY_V_EMPTY_CLR(v) \ |
| 961 | ((v) & MAX_M5_VEMPTY_V_EMPTY_CLEAR) |
| 962 | #define MAX_M5_VEMPTY_V_EMPTY_SET(v) \ |
| 963 | (MAX_M5_VEMPTY_V_EMPTY_CLR(v) | MAX_M5_VEMPTY_V_EMPTY) |
| 964 | #define MAX_M5_VEMPTY_V_RECOVER_MASK 0x7f |
| 965 | #define MAX_M5_VEMPTY_V_RECOVER_SHIFT 1 |
| 966 | #define MAX_M5_VEMPTY_V_RECOVER_CLEAR (~(0x7f << 1)) |
| 967 | #define MAX_M5_VEMPTY_V_RECOVER_CLR(v) \ |
| 968 | ((v) & MAX_M5_VEMPTY_V_RECOVER_CLEAR) |
| 969 | #define MAX_M5_VEMPTY_V_RECOVER_SET(v) \ |
| 970 | (MAX_M5_VEMPTY_V_RECOVER_CLR(v) | MAX_M5_VEMPTY_V_RECOVER) |
| 971 | |
| 972 | /* AvgCurrent0,0x3B,0b111111111111111,0x7fff |
| 973 | * AvgCurrent0[15:8],,,,,, |
| 974 | */ |
| 975 | #define MAX_M5_AVGCURRENT0 0x3B |
| 976 | |
| 977 | /* TaskPeriod,0x3C,0b1011010000000,0x1680 |
| 978 | * TaskPeriod[15:8],,,,,, |
| 979 | */ |
| 980 | #define MAX_M5_TASKPERIOD 0x3C |
| 981 | |
| 982 | /* FStat,0x3D,0b00000001,0x01 |
| 983 | * xBr,RDF,tmode,DeBn,xBi,Relck,RelDt |
| 984 | */ |
| 985 | #define MAX_M5_FSTAT 0x3D |
| 986 | #define MAX_M5_FSTAT_XBR (0x1 << 15) |
| 987 | #define MAX_M5_FSTAT_RDF (0x1 << 14) |
| 988 | #define MAX_M5_FSTAT_TMODE (0x1 << 13) |
| 989 | #define MAX_M5_FSTAT_DEBN (0x1 << 12) |
| 990 | #define MAX_M5_FSTAT_XBI (0x1 << 11) |
| 991 | #define MAX_M5_FSTAT_RELCK (0x1 << 10) |
| 992 | #define MAX_M5_FSTAT_RELDT (0x1 << 9) |
| 993 | #define MAX_M5_FSTAT_EDET (0x1 << 8) |
| 994 | #define MAX_M5_FSTAT_FQ (0x1 << 7) |
| 995 | #define MAX_M5_FSTAT_RELDT2 (0x1 << 6) |
| 996 | #define MAX_M5_FSTAT_TIMER_START (0x1 << 5) |
| 997 | #define MAX_M5_FSTAT_XBST (0x1 << 4) |
| 998 | #define MAX_M5_FSTAT_ACCEN (0x1 << 3) |
| 999 | #define MAX_M5_FSTAT_WK (0x1 << 2) |
| 1000 | #define MAX_M5_FSTAT_LDMDL (0x1 << 1) |
| 1001 | #define MAX_M5_FSTAT_DNR (0x1 << 0) |
| 1002 | |
| 1003 | #define MAX_M5_FSTAT_XBR_MASK 0x1 |
| 1004 | #define MAX_M5_FSTAT_XBR_SHIFT 15 |
| 1005 | #define MAX_M5_FSTAT_XBR_CLEAR (~(0x1 << 15)) |
| 1006 | #define MAX_M5_FSTAT_XBR_CLR(v) ((v) & MAX_M5_FSTAT_XBR_CLEAR) |
| 1007 | #define MAX_M5_FSTAT_XBR_SET(v) \ |
| 1008 | (MAX_M5_FSTAT_XBR_CLR(v) | MAX_M5_FSTAT_XBR) |
| 1009 | #define MAX_M5_FSTAT_RDF_MASK 0x1 |
| 1010 | #define MAX_M5_FSTAT_RDF_SHIFT 14 |
| 1011 | #define MAX_M5_FSTAT_RDF_CLEAR (~(0x1 << 14)) |
| 1012 | #define MAX_M5_FSTAT_RDF_CLR(v) ((v) & MAX_M5_FSTAT_RDF_CLEAR) |
| 1013 | #define MAX_M5_FSTAT_RDF_SET(v) \ |
| 1014 | (MAX_M5_FSTAT_RDF_CLR(v) | MAX_M5_FSTAT_RDF) |
| 1015 | #define MAX_M5_FSTAT_TMODE_MASK 0x1 |
| 1016 | #define MAX_M5_FSTAT_TMODE_SHIFT 13 |
| 1017 | #define MAX_M5_FSTAT_TMODE_CLEAR (~(0x1 << 13)) |
| 1018 | #define MAX_M5_FSTAT_TMODE_CLR(v) ((v) & MAX_M5_FSTAT_TMODE_CLEAR) |
| 1019 | #define MAX_M5_FSTAT_TMODE_SET(v) \ |
| 1020 | (MAX_M5_FSTAT_TMODE_CLR(v) | MAX_M5_FSTAT_TMODE) |
| 1021 | #define MAX_M5_FSTAT_DEBN_MASK 0x1 |
| 1022 | #define MAX_M5_FSTAT_DEBN_SHIFT 12 |
| 1023 | #define MAX_M5_FSTAT_DEBN_CLEAR (~(0x1 << 12)) |
| 1024 | #define MAX_M5_FSTAT_DEBN_CLR(v) ((v) & MAX_M5_FSTAT_DEBN_CLEAR) |
| 1025 | #define MAX_M5_FSTAT_DEBN_SET(v) \ |
| 1026 | (MAX_M5_FSTAT_DEBN_CLR(v) | MAX_M5_FSTAT_DEBN) |
| 1027 | #define MAX_M5_FSTAT_XBI_MASK 0x1 |
| 1028 | #define MAX_M5_FSTAT_XBI_SHIFT 11 |
| 1029 | #define MAX_M5_FSTAT_XBI_CLEAR (~(0x1 << 11)) |
| 1030 | #define MAX_M5_FSTAT_XBI_CLR(v) ((v) & MAX_M5_FSTAT_XBI_CLEAR) |
| 1031 | #define MAX_M5_FSTAT_XBI_SET(v) \ |
| 1032 | (MAX_M5_FSTAT_XBI_CLR(v) | MAX_M5_FSTAT_XBI) |
| 1033 | #define MAX_M5_FSTAT_RELCK_MASK 0x1 |
| 1034 | #define MAX_M5_FSTAT_RELCK_SHIFT 10 |
| 1035 | #define MAX_M5_FSTAT_RELCK_CLEAR (~(0x1 << 10)) |
| 1036 | #define MAX_M5_FSTAT_RELCK_CLR(v) ((v) & MAX_M5_FSTAT_RELCK_CLEAR) |
| 1037 | #define MAX_M5_FSTAT_RELCK_SET(v) \ |
| 1038 | (MAX_M5_FSTAT_RELCK_CLR(v) | MAX_M5_FSTAT_RELCK) |
| 1039 | #define MAX_M5_FSTAT_RELDT_MASK 0x1 |
| 1040 | #define MAX_M5_FSTAT_RELDT_SHIFT 9 |
| 1041 | #define MAX_M5_FSTAT_RELDT_CLEAR (~(0x1 << 9)) |
| 1042 | #define MAX_M5_FSTAT_RELDT_CLR(v) ((v) & MAX_M5_FSTAT_RELDT_CLEAR) |
| 1043 | #define MAX_M5_FSTAT_RELDT_SET(v) \ |
| 1044 | (MAX_M5_FSTAT_RELDT_CLR(v) | MAX_M5_FSTAT_RELDT) |
| 1045 | #define MAX_M5_FSTAT_EDET_MASK 0x1 |
| 1046 | #define MAX_M5_FSTAT_EDET_SHIFT 8 |
| 1047 | #define MAX_M5_FSTAT_EDET_CLEAR (~(0x1 << 8)) |
| 1048 | #define MAX_M5_FSTAT_EDET_CLR(v) ((v) & MAX_M5_FSTAT_EDET_CLEAR) |
| 1049 | #define MAX_M5_FSTAT_EDET_SET(v) \ |
| 1050 | (MAX_M5_FSTAT_EDET_CLR(v) | MAX_M5_FSTAT_EDET) |
| 1051 | #define MAX_M5_FSTAT_FQ_MASK 0x1 |
| 1052 | #define MAX_M5_FSTAT_FQ_SHIFT 7 |
| 1053 | #define MAX_M5_FSTAT_FQ_CLEAR (~(0x1 << 7)) |
| 1054 | #define MAX_M5_FSTAT_FQ_CLR(v) ((v) & MAX_M5_FSTAT_FQ_CLEAR) |
| 1055 | #define MAX_M5_FSTAT_FQ_SET(v) \ |
| 1056 | (MAX_M5_FSTAT_FQ_CLR(v) | MAX_M5_FSTAT_FQ) |
| 1057 | #define MAX_M5_FSTAT_RELDT2_MASK 0x1 |
| 1058 | #define MAX_M5_FSTAT_RELDT2_SHIFT 6 |
| 1059 | #define MAX_M5_FSTAT_RELDT2_CLEAR (~(0x1 << 6)) |
| 1060 | #define MAX_M5_FSTAT_RELDT2_CLR(v) ((v) & MAX_M5_FSTAT_RELDT2_CLEAR) |
| 1061 | #define MAX_M5_FSTAT_RELDT2_SET(v) \ |
| 1062 | (MAX_M5_FSTAT_RELDT2_CLR(v) | MAX_M5_FSTAT_RELDT2) |
| 1063 | #define MAX_M5_FSTAT_TIMER_START_MASK 0x1 |
| 1064 | #define MAX_M5_FSTAT_TIMER_START_SHIFT 5 |
| 1065 | #define MAX_M5_FSTAT_TIMER_START_CLEAR (~(0x1 << 5)) |
| 1066 | #define MAX_M5_FSTAT_TIMER_START_CLR(v) \ |
| 1067 | ((v) & MAX_M5_FSTAT_TIMER_START_CLEAR) |
| 1068 | #define MAX_M5_FSTAT_TIMER_START_SET(v) \ |
| 1069 | (MAX_M5_FSTAT_TIMER_START_CLR(v) | MAX_M5_FSTAT_TIMER_START) |
| 1070 | #define MAX_M5_FSTAT_XBST_MASK 0x1 |
| 1071 | #define MAX_M5_FSTAT_XBST_SHIFT 4 |
| 1072 | #define MAX_M5_FSTAT_XBST_CLEAR (~(0x1 << 4)) |
| 1073 | #define MAX_M5_FSTAT_XBST_CLR(v) ((v) & MAX_M5_FSTAT_XBST_CLEAR) |
| 1074 | #define MAX_M5_FSTAT_XBST_SET(v) \ |
| 1075 | (MAX_M5_FSTAT_XBST_CLR(v) | MAX_M5_FSTAT_XBST) |
| 1076 | #define MAX_M5_FSTAT_ACCEN_MASK 0x1 |
| 1077 | #define MAX_M5_FSTAT_ACCEN_SHIFT 3 |
| 1078 | #define MAX_M5_FSTAT_ACCEN_CLEAR (~(0x1 << 3)) |
| 1079 | #define MAX_M5_FSTAT_ACCEN_CLR(v) ((v) & MAX_M5_FSTAT_ACCEN_CLEAR) |
| 1080 | #define MAX_M5_FSTAT_ACCEN_SET(v) \ |
| 1081 | (MAX_M5_FSTAT_ACCEN_CLR(v) | MAX_M5_FSTAT_ACCEN) |
| 1082 | #define MAX_M5_FSTAT_WK_MASK 0x1 |
| 1083 | #define MAX_M5_FSTAT_WK_SHIFT 2 |
| 1084 | #define MAX_M5_FSTAT_WK_CLEAR (~(0x1 << 2)) |
| 1085 | #define MAX_M5_FSTAT_WK_CLR(v) ((v) & MAX_M5_FSTAT_WK_CLEAR) |
| 1086 | #define MAX_M5_FSTAT_WK_SET(v) \ |
| 1087 | (MAX_M5_FSTAT_WK_CLR(v) | MAX_M5_FSTAT_WK) |
| 1088 | #define MAX_M5_FSTAT_LDMDL_MASK 0x1 |
| 1089 | #define MAX_M5_FSTAT_LDMDL_SHIFT 1 |
| 1090 | #define MAX_M5_FSTAT_LDMDL_CLEAR (~(0x1 << 1)) |
| 1091 | #define MAX_M5_FSTAT_LDMDL_CLR(v) ((v) & MAX_M5_FSTAT_LDMDL_CLEAR) |
| 1092 | #define MAX_M5_FSTAT_LDMDL_SET(v) \ |
| 1093 | (MAX_M5_FSTAT_LDMDL_CLR(v) | MAX_M5_FSTAT_LDMDL) |
| 1094 | #define MAX_M5_FSTAT_DNR_MASK 0x1 |
| 1095 | #define MAX_M5_FSTAT_DNR_SHIFT 0 |
| 1096 | #define MAX_M5_FSTAT_DNR_CLEAR (~(0x1 << 0)) |
| 1097 | #define MAX_M5_FSTAT_DNR_CLR(v) ((v) & MAX_M5_FSTAT_DNR_CLEAR) |
| 1098 | #define MAX_M5_FSTAT_DNR_SET(v) \ |
| 1099 | (MAX_M5_FSTAT_DNR_CLR(v) | MAX_M5_FSTAT_DNR) |
| 1100 | |
| 1101 | /* Timer,0x3E,0b00000000,0x00 |
| 1102 | * TIMER[15:8],,,,,, |
| 1103 | */ |
| 1104 | #define MAX_M5_TIMER 0x3E |
| 1105 | |
| 1106 | /* ShdnTimer,0x3F,0b1110000000000000,0xe000 |
| 1107 | * SHDN_THR[2:0],,,SHDNCTR[12:8],,, |
| 1108 | */ |
| 1109 | #define MAX_M5_SHDNTIMER 0x3F |
| 1110 | #define MAX_M5_SHDNTIMER_SHDN_THR (0x7 << 13) |
| 1111 | #define MAX_M5_SHDNTIMER_SHDNCTR (0x1fff << 0) |
| 1112 | |
| 1113 | #define MAX_M5_SHDNTIMER_SHDN_THR_MASK 0x7 |
| 1114 | #define MAX_M5_SHDNTIMER_SHDN_THR_SHIFT 13 |
| 1115 | #define MAX_M5_SHDNTIMER_SHDN_THR_CLEAR (~(0x7 << 13)) |
| 1116 | #define MAX_M5_SHDNTIMER_SHDN_THR_CLR(v) \ |
| 1117 | ((v) & MAX_M5_SHDNTIMER_SHDN_THR_CLEAR) |
| 1118 | #define MAX_M5_SHDNTIMER_SHDN_THR_SET(v) \ |
| 1119 | (MAX_M5_SHDNTIMER_SHDN_THR_CLR(v) | MAX_M5_SHDNTIMER_SHDN_THR) |
| 1120 | #define MAX_M5_SHDNTIMER_SHDNCTR_MASK 0x1fff |
| 1121 | #define MAX_M5_SHDNTIMER_SHDNCTR_SHIFT 0 |
| 1122 | #define MAX_M5_SHDNTIMER_SHDNCTR_CLEAR (~(0x1fff << 0)) |
| 1123 | #define MAX_M5_SHDNTIMER_SHDNCTR_CLR(v) \ |
| 1124 | ((v) & MAX_M5_SHDNTIMER_SHDNCTR_CLEAR) |
| 1125 | #define MAX_M5_SHDNTIMER_SHDNCTR_SET(v) \ |
| 1126 | (MAX_M5_SHDNTIMER_SHDNCTR_CLR(v) | MAX_M5_SHDNTIMER_SHDNCTR) |
| 1127 | |
| 1128 | /* THMHOT,0x40,0b11111111100,0x7fc |
| 1129 | * VR[4:0],,,,,Vhys[2:0], |
| 1130 | */ |
| 1131 | #define MAX_M5_THMHOT 0x40 |
| 1132 | #define MAX_M5_THMHOT_VR (0x1f << 11) |
| 1133 | #define MAX_M5_THMHOT_VHYS (0x7 << 8) |
| 1134 | #define MAX_M5_THMHOT_TR (0x1f << 3) |
| 1135 | #define MAX_M5_THMHOT_THYS (0x7 << 0) |
| 1136 | |
| 1137 | #define MAX_M5_THMHOT_VR_MASK 0x1f |
| 1138 | #define MAX_M5_THMHOT_VR_SHIFT 11 |
| 1139 | #define MAX_M5_THMHOT_VR_CLEAR (~(0x1f << 11)) |
| 1140 | #define MAX_M5_THMHOT_VR_CLR(v) ((v) & MAX_M5_THMHOT_VR_CLEAR) |
| 1141 | #define MAX_M5_THMHOT_VR_SET(v) \ |
| 1142 | (MAX_M5_THMHOT_VR_CLR(v) | MAX_M5_THMHOT_VR) |
| 1143 | #define MAX_M5_THMHOT_VHYS_MASK 0x7 |
| 1144 | #define MAX_M5_THMHOT_VHYS_SHIFT 8 |
| 1145 | #define MAX_M5_THMHOT_VHYS_CLEAR (~(0x7 << 8)) |
| 1146 | #define MAX_M5_THMHOT_VHYS_CLR(v) ((v) & MAX_M5_THMHOT_VHYS_CLEAR) |
| 1147 | #define MAX_M5_THMHOT_VHYS_SET(v) \ |
| 1148 | (MAX_M5_THMHOT_VHYS_CLR(v) | MAX_M5_THMHOT_VHYS) |
| 1149 | #define MAX_M5_THMHOT_TR_MASK 0x1f |
| 1150 | #define MAX_M5_THMHOT_TR_SHIFT 3 |
| 1151 | #define MAX_M5_THMHOT_TR_CLEAR (~(0x1f << 3)) |
| 1152 | #define MAX_M5_THMHOT_TR_CLR(v) ((v) & MAX_M5_THMHOT_TR_CLEAR) |
| 1153 | #define MAX_M5_THMHOT_TR_SET(v) \ |
| 1154 | (MAX_M5_THMHOT_TR_CLR(v) | MAX_M5_THMHOT_TR) |
| 1155 | #define MAX_M5_THMHOT_THYS_MASK 0x7 |
| 1156 | #define MAX_M5_THMHOT_THYS_SHIFT 0 |
| 1157 | #define MAX_M5_THMHOT_THYS_CLEAR (~(0x7 << 0)) |
| 1158 | #define MAX_M5_THMHOT_THYS_CLR(v) ((v) & MAX_M5_THMHOT_THYS_CLEAR) |
| 1159 | #define MAX_M5_THMHOT_THYS_SET(v) \ |
| 1160 | (MAX_M5_THMHOT_THYS_CLR(v) | MAX_M5_THMHOT_THYS) |
| 1161 | |
| 1162 | /* CTESample,0x41,0b00000000,0x00 |
| 1163 | * CTESample[15:8],,,,,, |
| 1164 | */ |
| 1165 | #define MAX_M5_CTESAMPLE 0x41 |
| 1166 | |
| 1167 | /* QRTable30,0x42,0b100010000101,0x885 |
| 1168 | * QRTable30[15:8],,,,,, |
| 1169 | */ |
| 1170 | #define MAX_M5_QRTABLE30 0x42 |
| 1171 | |
| 1172 | /* ISys,0x43,0b00000000,0x00 |
| 1173 | * ISYS[15:8],,,,,, |
| 1174 | */ |
| 1175 | #define MAX_M5_ISYS 0x43 |
| 1176 | |
| 1177 | /* AvgVCell0,0x44,0b1000000000000000,0x8000 |
| 1178 | * AvgVCELL0[15:8],,,,,, |
| 1179 | */ |
| 1180 | #define MAX_M5_AVGVCELL0 0x44 |
| 1181 | |
| 1182 | /* dQAcc,0x45,0b00010111,0x17 |
| 1183 | * dQacc[15:8],,,,,, |
| 1184 | */ |
| 1185 | #define MAX_M5_DQACC 0x45 |
| 1186 | |
| 1187 | /* dPAcc,0x46,0b110010000,0x190 |
| 1188 | * dPacc[15:8],,,,,, |
| 1189 | */ |
| 1190 | #define MAX_M5_DPACC 0x46 |
| 1191 | |
| 1192 | /* RlxSOC,0x47,0b00000000,0x00 |
| 1193 | * RlxSOC[15:8],,,,,, |
| 1194 | */ |
| 1195 | #define MAX_M5_RLXSOC 0x47 |
| 1196 | |
| 1197 | /* VFSOC0,0x48,0b11001000000000,0x3200 |
| 1198 | * VFSOC0[15:8],,,,,, |
| 1199 | */ |
| 1200 | #define MAX_M5_VFSOC0 0x48 |
| 1201 | |
| 1202 | /* ConvgCfg,0x49,0b10001001000001,0x2241 |
| 1203 | * RepLow[3:0],,,,VoltLowOff[4:1],, |
| 1204 | */ |
| 1205 | #define MAX_M5_CONVGCFG 0x49 |
| 1206 | #define MAX_M5_CONVGCFG_REPLOW (0xf << 12) |
| 1207 | #define MAX_M5_CONVGCFG_VOLTLOWOFF (0xf << 8) |
| 1208 | #define MAX_M5_CONVGCFG_MINSLOPEX (0xf << 4) |
| 1209 | #define MAX_M5_CONVGCFG_REPL_PER_STAGE (0x7 << 1) |
| 1210 | |
| 1211 | #define MAX_M5_CONVGCFG_REPLOW_MASK 0xf |
| 1212 | #define MAX_M5_CONVGCFG_REPLOW_SHIFT 12 |
| 1213 | #define MAX_M5_CONVGCFG_REPLOW_CLEAR (~(0xf << 12)) |
| 1214 | #define MAX_M5_CONVGCFG_REPLOW_CLR(v) \ |
| 1215 | ((v) & MAX_M5_CONVGCFG_REPLOW_CLEAR) |
| 1216 | #define MAX_M5_CONVGCFG_REPLOW_SET(v) \ |
| 1217 | (MAX_M5_CONVGCFG_REPLOW_CLR(v) | MAX_M5_CONVGCFG_REPLOW) |
| 1218 | #define MAX_M5_CONVGCFG_VOLTLOWOFF_MASK 0xf |
| 1219 | #define MAX_M5_CONVGCFG_VOLTLOWOFF_SHIFT 8 |
| 1220 | #define MAX_M5_CONVGCFG_VOLTLOWOFF_CLEAR (~(0xf << 8)) |
| 1221 | #define MAX_M5_CONVGCFG_VOLTLOWOFF_CLR(v) \ |
| 1222 | ((v) & MAX_M5_CONVGCFG_VOLTLOWOFF_CLEAR) |
| 1223 | #define MAX_M5_CONVGCFG_VOLTLOWOFF_SET(v) \ |
| 1224 | (MAX_M5_CONVGCFG_VOLTLOWOFF_CLR(v) | MAX_M5_CONVGCFG_VOLTLOWOFF) |
| 1225 | #define MAX_M5_CONVGCFG_MINSLOPEX_MASK 0xf |
| 1226 | #define MAX_M5_CONVGCFG_MINSLOPEX_SHIFT 4 |
| 1227 | #define MAX_M5_CONVGCFG_MINSLOPEX_CLEAR (~(0xf << 4)) |
| 1228 | #define MAX_M5_CONVGCFG_MINSLOPEX_CLR(v) \ |
| 1229 | ((v) & MAX_M5_CONVGCFG_MINSLOPEX_CLEAR) |
| 1230 | #define MAX_M5_CONVGCFG_MINSLOPEX_SET(v) \ |
| 1231 | (MAX_M5_CONVGCFG_MINSLOPEX_CLR(v) | MAX_M5_CONVGCFG_MINSLOPEX) |
| 1232 | #define MAX_M5_CONVGCFG_REPL_PER_STAGE_MASK 0x7 |
| 1233 | #define MAX_M5_CONVGCFG_REPL_PER_STAGE_SHIFT 1 |
| 1234 | #define MAX_M5_CONVGCFG_REPL_PER_STAGE_CLEAR (~(0x7 << 1)) |
| 1235 | #define MAX_M5_CONVGCFG_REPL_PER_STAGE_CLR(v) \ |
| 1236 | ((v) & MAX_M5_CONVGCFG_REPL_PER_STAGE_CLEAR) |
| 1237 | #define MAX_M5_CONVGCFG_REPL_PER_STAGE_SET(v) \ |
| 1238 | (MAX_M5_CONVGCFG_REPL_PER_STAGE_CLR(v) | MAX_M5_CONVGCFG_REPL_PER_STAGE) |
| 1239 | |
| 1240 | /* VFRemCap,0x4A,0b10111011100,0x5dc |
| 1241 | * VFRemCap[15:8],,,,,, |
| 1242 | */ |
| 1243 | #define MAX_M5_VFREMCAP 0x4A |
| 1244 | |
| 1245 | /* AvgISys,0x4B,0b00000000,0x00 |
| 1246 | * AVGISYS[15:8],,,,,, |
| 1247 | */ |
| 1248 | #define MAX_M5_AVGISYS 0x4B |
| 1249 | |
| 1250 | /* QH0,0x4C,0b00000000,0x00 |
| 1251 | * QH0[15:8],,,,,, |
| 1252 | */ |
| 1253 | #define MAX_M5_QH0 0x4C |
| 1254 | |
| 1255 | /* QH,0x4D,0b00000000,0x00 |
| 1256 | * QH[15:8],,,,,, |
| 1257 | */ |
| 1258 | #define MAX_M5_QH 0x4D |
| 1259 | |
| 1260 | /* QL,0x4E,0b00000000,0x00 |
| 1261 | * QL[15:8],,,,,, |
| 1262 | */ |
| 1263 | #define MAX_M5_QL 0x4E |
| 1264 | |
| 1265 | /* MixAtFull,0x4F,0b101110111000,0xbb8 |
| 1266 | * MixAtFull[15:8],,,,,, |
| 1267 | */ |
| 1268 | #define MAX_M5_MIXATFULL 0x4F |
| 1269 | |
| 1270 | /* Status2,0xB0,0b00000000,0x00 |
| 1271 | * SPR_15_6[9:2],,,,,, |
| 1272 | */ |
| 1273 | #define MAX_M5_STATUS2 0xB0 |
| 1274 | #define MAX_M5_STATUS2_SPR_15_6 (0x3ff << 6) |
| 1275 | #define MAX_M5_STATUS2_FULLDET (0x1 << 5) |
| 1276 | #define MAX_M5_STATUS2_SPR_4_2 (0x7 << 2) |
| 1277 | #define MAX_M5_STATUS2_HIB (0x1 << 1) |
| 1278 | #define MAX_M5_STATUS2_SPR_0 (0x1 << 0) |
| 1279 | |
| 1280 | #define MAX_M5_STATUS2_SPR_15_6_MASK 0x3ff |
| 1281 | #define MAX_M5_STATUS2_SPR_15_6_SHIFT 6 |
| 1282 | #define MAX_M5_STATUS2_SPR_15_6_CLEAR (~(0x3ff << 6)) |
| 1283 | #define MAX_M5_STATUS2_SPR_15_6_CLR(v) \ |
| 1284 | ((v) & MAX_M5_STATUS2_SPR_15_6_CLEAR) |
| 1285 | #define MAX_M5_STATUS2_SPR_15_6_SET(v) \ |
| 1286 | (MAX_M5_STATUS2_SPR_15_6_CLR(v) | MAX_M5_STATUS2_SPR_15_6) |
| 1287 | #define MAX_M5_STATUS2_FULLDET_MASK 0x1 |
| 1288 | #define MAX_M5_STATUS2_FULLDET_SHIFT 5 |
| 1289 | #define MAX_M5_STATUS2_FULLDET_CLEAR (~(0x1 << 5)) |
| 1290 | #define MAX_M5_STATUS2_FULLDET_CLR(v) \ |
| 1291 | ((v) & MAX_M5_STATUS2_FULLDET_CLEAR) |
| 1292 | #define MAX_M5_STATUS2_FULLDET_SET(v) \ |
| 1293 | (MAX_M5_STATUS2_FULLDET_CLR(v) | MAX_M5_STATUS2_FULLDET) |
| 1294 | #define MAX_M5_STATUS2_SPR_4_2_MASK 0x7 |
| 1295 | #define MAX_M5_STATUS2_SPR_4_2_SHIFT 2 |
| 1296 | #define MAX_M5_STATUS2_SPR_4_2_CLEAR (~(0x7 << 2)) |
| 1297 | #define MAX_M5_STATUS2_SPR_4_2_CLR(v) \ |
| 1298 | ((v) & MAX_M5_STATUS2_SPR_4_2_CLEAR) |
| 1299 | #define MAX_M5_STATUS2_SPR_4_2_SET(v) \ |
| 1300 | (MAX_M5_STATUS2_SPR_4_2_CLR(v) | MAX_M5_STATUS2_SPR_4_2) |
| 1301 | #define MAX_M5_STATUS2_HIB_MASK 0x1 |
| 1302 | #define MAX_M5_STATUS2_HIB_SHIFT 1 |
| 1303 | #define MAX_M5_STATUS2_HIB_CLEAR (~(0x1 << 1)) |
| 1304 | #define MAX_M5_STATUS2_HIB_CLR(v) ((v) & MAX_M5_STATUS2_HIB_CLEAR) |
| 1305 | #define MAX_M5_STATUS2_HIB_SET(v) \ |
| 1306 | (MAX_M5_STATUS2_HIB_CLR(v) | MAX_M5_STATUS2_HIB) |
| 1307 | #define MAX_M5_STATUS2_SPR_0_MASK 0x1 |
| 1308 | #define MAX_M5_STATUS2_SPR_0_SHIFT 0 |
| 1309 | #define MAX_M5_STATUS2_SPR_0_CLEAR (~(0x1 << 0)) |
| 1310 | #define MAX_M5_STATUS2_SPR_0_CLR(v) \ |
| 1311 | ((v) & MAX_M5_STATUS2_SPR_0_CLEAR) |
| 1312 | #define MAX_M5_STATUS2_SPR_0_SET(v) \ |
| 1313 | (MAX_M5_STATUS2_SPR_0_CLR(v) | MAX_M5_STATUS2_SPR_0) |
| 1314 | |
| 1315 | /* VSys,0xB1,0b00000000,0x00 |
| 1316 | * VSys[15:8],,,,,, |
| 1317 | */ |
| 1318 | #define MAX_M5_VSYS 0xB1 |
| 1319 | |
| 1320 | /* TAlrtTh2,0xB2,0b111111110000000,0x7f80 |
| 1321 | * TempWarm[7:0],,,,,, |
| 1322 | */ |
| 1323 | #define MAX_M5_TALRTTH2 0xB2 |
| 1324 | #define MAX_M5_TALRTTH2_TEMPWARM (0xff << 8) |
| 1325 | #define MAX_M5_TALRTTH2_TEMPCOOL (0xff << 0) |
| 1326 | |
| 1327 | #define MAX_M5_TALRTTH2_TEMPWARM_MASK 0xff |
| 1328 | #define MAX_M5_TALRTTH2_TEMPWARM_SHIFT 8 |
| 1329 | #define MAX_M5_TALRTTH2_TEMPWARM_CLEAR (~(0xff << 8)) |
| 1330 | #define MAX_M5_TALRTTH2_TEMPWARM_CLR(v) \ |
| 1331 | ((v) & MAX_M5_TALRTTH2_TEMPWARM_CLEAR) |
| 1332 | #define MAX_M5_TALRTTH2_TEMPWARM_SET(v) \ |
| 1333 | (MAX_M5_TALRTTH2_TEMPWARM_CLR(v) | MAX_M5_TALRTTH2_TEMPWARM) |
| 1334 | #define MAX_M5_TALRTTH2_TEMPCOOL_MASK 0xff |
| 1335 | #define MAX_M5_TALRTTH2_TEMPCOOL_SHIFT 0 |
| 1336 | #define MAX_M5_TALRTTH2_TEMPCOOL_CLEAR (~(0xff << 0)) |
| 1337 | #define MAX_M5_TALRTTH2_TEMPCOOL_CLR(v) \ |
| 1338 | ((v) & MAX_M5_TALRTTH2_TEMPCOOL_CLEAR) |
| 1339 | #define MAX_M5_TALRTTH2_TEMPCOOL_SET(v) \ |
| 1340 | (MAX_M5_TALRTTH2_TEMPCOOL_CLR(v) | MAX_M5_TALRTTH2_TEMPCOOL) |
| 1341 | |
| 1342 | /* VByp,0xB3,0b00000000,0x00 |
| 1343 | * VByp[15:8],,,,,, |
| 1344 | */ |
| 1345 | #define MAX_M5_VBYP 0xB3 |
| 1346 | |
| 1347 | /* IAlrtTh,0xB4,0b111111110000000,0x7f80 |
| 1348 | * ISYSOCP_TH[7:0],,,,,, |
| 1349 | */ |
| 1350 | #define MAX_M5_IALRTTH 0xB4 |
| 1351 | #define MAX_M5_IALRTTH_ISYSOCP_TH (0xff << 8) |
| 1352 | #define MAX_M5_IALRTTH_IBATTMIN_TH (0xff << 0) |
| 1353 | |
| 1354 | #define MAX_M5_IALRTTH_ISYSOCP_TH_MASK 0xff |
| 1355 | #define MAX_M5_IALRTTH_ISYSOCP_TH_SHIFT 8 |
| 1356 | #define MAX_M5_IALRTTH_ISYSOCP_TH_CLEAR (~(0xff << 8)) |
| 1357 | #define MAX_M5_IALRTTH_ISYSOCP_TH_CLR(v) \ |
| 1358 | ((v) & MAX_M5_IALRTTH_ISYSOCP_TH_CLEAR) |
| 1359 | #define MAX_M5_IALRTTH_ISYSOCP_TH_SET(v) \ |
| 1360 | (MAX_M5_IALRTTH_ISYSOCP_TH_CLR(v) | MAX_M5_IALRTTH_ISYSOCP_TH) |
| 1361 | #define MAX_M5_IALRTTH_IBATTMIN_TH_MASK 0xff |
| 1362 | #define MAX_M5_IALRTTH_IBATTMIN_TH_SHIFT 0 |
| 1363 | #define MAX_M5_IALRTTH_IBATTMIN_TH_CLEAR (~(0xff << 0)) |
| 1364 | #define MAX_M5_IALRTTH_IBATTMIN_TH_CLR(v) \ |
| 1365 | ((v) & MAX_M5_IALRTTH_IBATTMIN_TH_CLEAR) |
| 1366 | #define MAX_M5_IALRTTH_IBATTMIN_TH_SET(v) \ |
| 1367 | (MAX_M5_IALRTTH_IBATTMIN_TH_CLR(v) | MAX_M5_IALRTTH_IBATTMIN_TH) |
| 1368 | |
| 1369 | /* TTF_CFG,0xB5,0b00000101,0x05 |
| 1370 | * SPR_15_3[12:5],,,,,, |
| 1371 | */ |
| 1372 | #define MAX_M5_TTF_CFG 0xB5 |
| 1373 | #define MAX_M5_TTF_CFG_SPR_15_3 (0x1fff << 3) |
| 1374 | #define MAX_M5_TTF_CFG_TTF_CFG (0x7 << 0) |
| 1375 | |
| 1376 | #define MAX_M5_TTF_CFG_SPR_15_3_MASK 0x1fff |
| 1377 | #define MAX_M5_TTF_CFG_SPR_15_3_SHIFT 3 |
| 1378 | #define MAX_M5_TTF_CFG_SPR_15_3_CLEAR (~(0x1fff << 3)) |
| 1379 | #define MAX_M5_TTF_CFG_SPR_15_3_CLR(v) \ |
| 1380 | ((v) & MAX_M5_TTF_CFG_SPR_15_3_CLEAR) |
| 1381 | #define MAX_M5_TTF_CFG_SPR_15_3_SET(v) \ |
| 1382 | (MAX_M5_TTF_CFG_SPR_15_3_CLR(v) | MAX_M5_TTF_CFG_SPR_15_3) |
| 1383 | #define MAX_M5_TTF_CFG_TTF_CFG_MASK 0x7 |
| 1384 | #define MAX_M5_TTF_CFG_TTF_CFG_SHIFT 0 |
| 1385 | #define MAX_M5_TTF_CFG_TTF_CFG_CLEAR (~(0x7 << 0)) |
| 1386 | #define MAX_M5_TTF_CFG_TTF_CFG_CLR(v) \ |
| 1387 | ((v) & MAX_M5_TTF_CFG_TTF_CFG_CLEAR) |
| 1388 | #define MAX_M5_TTF_CFG_TTF_CFG_SET(v) \ |
| 1389 | (MAX_M5_TTF_CFG_TTF_CFG_CLR(v) | MAX_M5_TTF_CFG_TTF_CFG) |
| 1390 | |
| 1391 | /* CV_MixCap,0xB6,0b100011001010,0x8ca |
| 1392 | * CV_MixCap[15:8],,,,,, |
| 1393 | */ |
| 1394 | #define MAX_M5_CV_MIXCAP 0xB6 |
| 1395 | |
| 1396 | /* CV_HalfTime,0xB7,0b101000000000,0xa00 |
| 1397 | * CV_Halftime[15:8],,,,,, |
| 1398 | */ |
| 1399 | #define MAX_M5_CV_HALFTIME 0xB7 |
| 1400 | |
| 1401 | /* CGTempCo,0xB8,0b00000000,0x00 |
| 1402 | * CGTempCo[15:8],,,,,, |
| 1403 | */ |
| 1404 | #define MAX_M5_CGTEMPCO 0xB8 |
| 1405 | |
| 1406 | /* Curve,0xB9,0b01101011,0x6b |
| 1407 | * ECURVE[7:0],,,,,, |
| 1408 | */ |
| 1409 | #define MAX_M5_CURVE 0xB9 |
| 1410 | #define MAX_M5_CURVE_ECURVE (0xff << 8) |
| 1411 | #define MAX_M5_CURVE_TCURVE (0xff << 0) |
| 1412 | |
| 1413 | #define MAX_M5_CURVE_ECURVE_MASK 0xff |
| 1414 | #define MAX_M5_CURVE_ECURVE_SHIFT 8 |
| 1415 | #define MAX_M5_CURVE_ECURVE_CLEAR (~(0xff << 8)) |
| 1416 | #define MAX_M5_CURVE_ECURVE_CLR(v) ((v) & MAX_M5_CURVE_ECURVE_CLEAR) |
| 1417 | #define MAX_M5_CURVE_ECURVE_SET(v) \ |
| 1418 | (MAX_M5_CURVE_ECURVE_CLR(v) | MAX_M5_CURVE_ECURVE) |
| 1419 | #define MAX_M5_CURVE_TCURVE_MASK 0xff |
| 1420 | #define MAX_M5_CURVE_TCURVE_SHIFT 0 |
| 1421 | #define MAX_M5_CURVE_TCURVE_CLEAR (~(0xff << 0)) |
| 1422 | #define MAX_M5_CURVE_TCURVE_CLR(v) ((v) & MAX_M5_CURVE_TCURVE_CLEAR) |
| 1423 | #define MAX_M5_CURVE_TCURVE_SET(v) \ |
| 1424 | (MAX_M5_CURVE_TCURVE_CLR(v) | MAX_M5_CURVE_TCURVE) |
| 1425 | |
| 1426 | /* HibCfg,0xBA,0b100100001100,0x90c |
| 1427 | * EnHib,HibEnterTime[2:0],,,HibThreshold[3:0],, |
| 1428 | */ |
| 1429 | #define MAX_M5_HIBCFG 0xBA |
| 1430 | #define MAX_M5_HIBCFG_ENHIB (0x1 << 15) |
| 1431 | #define MAX_M5_HIBCFG_HIBENTERTIME (0x7 << 12) |
| 1432 | #define MAX_M5_HIBCFG_HIBTHRESHOLD (0xf << 8) |
| 1433 | #define MAX_M5_HIBCFG_SPR_7_5 (0x7 << 5) |
| 1434 | #define MAX_M5_HIBCFG_HIBEXITTIME (0x3 << 3) |
| 1435 | #define MAX_M5_HIBCFG_HIBSCALAR (0x7 << 0) |
| 1436 | |
| 1437 | #define MAX_M5_HIBCFG_ENHIB_MASK 0x1 |
| 1438 | #define MAX_M5_HIBCFG_ENHIB_SHIFT 15 |
| 1439 | #define MAX_M5_HIBCFG_ENHIB_CLEAR (~(0x1 << 15)) |
| 1440 | #define MAX_M5_HIBCFG_ENHIB_CLR(v) ((v) & MAX_M5_HIBCFG_ENHIB_CLEAR) |
| 1441 | #define MAX_M5_HIBCFG_ENHIB_SET(v) \ |
| 1442 | (MAX_M5_HIBCFG_ENHIB_CLR(v) | MAX_M5_HIBCFG_ENHIB) |
| 1443 | #define MAX_M5_HIBCFG_HIBENTERTIME_MASK 0x7 |
| 1444 | #define MAX_M5_HIBCFG_HIBENTERTIME_SHIFT 12 |
| 1445 | #define MAX_M5_HIBCFG_HIBENTERTIME_CLEAR (~(0x7 << 12)) |
| 1446 | #define MAX_M5_HIBCFG_HIBENTERTIME_CLR(v) \ |
| 1447 | ((v) & MAX_M5_HIBCFG_HIBENTERTIME_CLEAR) |
| 1448 | #define MAX_M5_HIBCFG_HIBENTERTIME_SET(v) \ |
| 1449 | (MAX_M5_HIBCFG_HIBENTERTIME_CLR(v) | MAX_M5_HIBCFG_HIBENTERTIME) |
| 1450 | #define MAX_M5_HIBCFG_HIBTHRESHOLD_MASK 0xf |
| 1451 | #define MAX_M5_HIBCFG_HIBTHRESHOLD_SHIFT 8 |
| 1452 | #define MAX_M5_HIBCFG_HIBTHRESHOLD_CLEAR (~(0xf << 8)) |
| 1453 | #define MAX_M5_HIBCFG_HIBTHRESHOLD_CLR(v) \ |
| 1454 | ((v) & MAX_M5_HIBCFG_HIBTHRESHOLD_CLEAR) |
| 1455 | #define MAX_M5_HIBCFG_HIBTHRESHOLD_SET(v) \ |
| 1456 | (MAX_M5_HIBCFG_HIBTHRESHOLD_CLR(v) | MAX_M5_HIBCFG_HIBTHRESHOLD) |
| 1457 | #define MAX_M5_HIBCFG_SPR_7_5_MASK 0x7 |
| 1458 | #define MAX_M5_HIBCFG_SPR_7_5_SHIFT 5 |
| 1459 | #define MAX_M5_HIBCFG_SPR_7_5_CLEAR (~(0x7 << 5)) |
| 1460 | #define MAX_M5_HIBCFG_SPR_7_5_CLR(v) \ |
| 1461 | ((v) & MAX_M5_HIBCFG_SPR_7_5_CLEAR) |
| 1462 | #define MAX_M5_HIBCFG_SPR_7_5_SET(v) \ |
| 1463 | (MAX_M5_HIBCFG_SPR_7_5_CLR(v) | MAX_M5_HIBCFG_SPR_7_5) |
| 1464 | #define MAX_M5_HIBCFG_HIBEXITTIME_MASK 0x3 |
| 1465 | #define MAX_M5_HIBCFG_HIBEXITTIME_SHIFT 3 |
| 1466 | #define MAX_M5_HIBCFG_HIBEXITTIME_CLEAR (~(0x3 << 3)) |
| 1467 | #define MAX_M5_HIBCFG_HIBEXITTIME_CLR(v) \ |
| 1468 | ((v) & MAX_M5_HIBCFG_HIBEXITTIME_CLEAR) |
| 1469 | #define MAX_M5_HIBCFG_HIBEXITTIME_SET(v) \ |
| 1470 | (MAX_M5_HIBCFG_HIBEXITTIME_CLR(v) | MAX_M5_HIBCFG_HIBEXITTIME) |
| 1471 | #define MAX_M5_HIBCFG_HIBSCALAR_MASK 0x7 |
| 1472 | #define MAX_M5_HIBCFG_HIBSCALAR_SHIFT 0 |
| 1473 | #define MAX_M5_HIBCFG_HIBSCALAR_CLEAR (~(0x7 << 0)) |
| 1474 | #define MAX_M5_HIBCFG_HIBSCALAR_CLR(v) \ |
| 1475 | ((v) & MAX_M5_HIBCFG_HIBSCALAR_CLEAR) |
| 1476 | #define MAX_M5_HIBCFG_HIBSCALAR_SET(v) \ |
| 1477 | (MAX_M5_HIBCFG_HIBSCALAR_CLR(v) | MAX_M5_HIBCFG_HIBSCALAR) |
| 1478 | |
| 1479 | /* Config2,0xBB,0b01010000,0x50 |
| 1480 | * SPR_15_11[4:0],,,,,FCThmHot,ThmHotEn |
| 1481 | */ |
| 1482 | #define MAX_M5_CONFIG2 0xBB |
| 1483 | #define MAX_M5_CONFIG2_SPR_15_11 (0x1f << 11) |
| 1484 | #define MAX_M5_CONFIG2_FCTHMHOT (0x1 << 10) |
| 1485 | #define MAX_M5_CONFIG2_THMHOTEN (0x1 << 9) |
| 1486 | #define MAX_M5_CONFIG2_THMHOTALRTEN (0x1 << 8) |
| 1487 | #define MAX_M5_CONFIG2_DSOCEN (0x1 << 7) |
| 1488 | #define MAX_M5_CONFIG2_TALRTEN (0x1 << 6) |
| 1489 | #define MAX_M5_CONFIG2_LDMDL (0x1 << 5) |
| 1490 | #define MAX_M5_CONFIG2_OCVQEN (0x1 << 4) |
| 1491 | #define MAX_M5_CONFIG2_ISYSNCURR (0xf << 0) |
| 1492 | |
| 1493 | #define MAX_M5_CONFIG2_SPR_15_11_MASK 0x1f |
| 1494 | #define MAX_M5_CONFIG2_SPR_15_11_SHIFT 11 |
| 1495 | #define MAX_M5_CONFIG2_SPR_15_11_CLEAR (~(0x1f << 11)) |
| 1496 | #define MAX_M5_CONFIG2_SPR_15_11_CLR(v) \ |
| 1497 | ((v) & MAX_M5_CONFIG2_SPR_15_11_CLEAR) |
| 1498 | #define MAX_M5_CONFIG2_SPR_15_11_SET(v) \ |
| 1499 | (MAX_M5_CONFIG2_SPR_15_11_CLR(v) | MAX_M5_CONFIG2_SPR_15_11) |
| 1500 | #define MAX_M5_CONFIG2_FCTHMHOT_MASK 0x1 |
| 1501 | #define MAX_M5_CONFIG2_FCTHMHOT_SHIFT 10 |
| 1502 | #define MAX_M5_CONFIG2_FCTHMHOT_CLEAR (~(0x1 << 10)) |
| 1503 | #define MAX_M5_CONFIG2_FCTHMHOT_CLR(v) \ |
| 1504 | ((v) & MAX_M5_CONFIG2_FCTHMHOT_CLEAR) |
| 1505 | #define MAX_M5_CONFIG2_FCTHMHOT_SET(v) \ |
| 1506 | (MAX_M5_CONFIG2_FCTHMHOT_CLR(v) | MAX_M5_CONFIG2_FCTHMHOT) |
| 1507 | #define MAX_M5_CONFIG2_THMHOTEN_MASK 0x1 |
| 1508 | #define MAX_M5_CONFIG2_THMHOTEN_SHIFT 9 |
| 1509 | #define MAX_M5_CONFIG2_THMHOTEN_CLEAR (~(0x1 << 9)) |
| 1510 | #define MAX_M5_CONFIG2_THMHOTEN_CLR(v) \ |
| 1511 | ((v) & MAX_M5_CONFIG2_THMHOTEN_CLEAR) |
| 1512 | #define MAX_M5_CONFIG2_THMHOTEN_SET(v) \ |
| 1513 | (MAX_M5_CONFIG2_THMHOTEN_CLR(v) | MAX_M5_CONFIG2_THMHOTEN) |
| 1514 | #define MAX_M5_CONFIG2_THMHOTALRTEN_MASK 0x1 |
| 1515 | #define MAX_M5_CONFIG2_THMHOTALRTEN_SHIFT 8 |
| 1516 | #define MAX_M5_CONFIG2_THMHOTALRTEN_CLEAR (~(0x1 << 8)) |
| 1517 | #define MAX_M5_CONFIG2_THMHOTALRTEN_CLR(v) \ |
| 1518 | ((v) & MAX_M5_CONFIG2_THMHOTALRTEN_CLEAR) |
| 1519 | #define MAX_M5_CONFIG2_THMHOTALRTEN_SET(v) \ |
| 1520 | (MAX_M5_CONFIG2_THMHOTALRTEN_CLR(v) | MAX_M5_CONFIG2_THMHOTALRTEN) |
| 1521 | #define MAX_M5_CONFIG2_DSOCEN_MASK 0x1 |
| 1522 | #define MAX_M5_CONFIG2_DSOCEN_SHIFT 7 |
| 1523 | #define MAX_M5_CONFIG2_DSOCEN_CLEAR (~(0x1 << 7)) |
| 1524 | #define MAX_M5_CONFIG2_DSOCEN_CLR(v) \ |
| 1525 | ((v) & MAX_M5_CONFIG2_DSOCEN_CLEAR) |
| 1526 | #define MAX_M5_CONFIG2_DSOCEN_SET(v) \ |
| 1527 | (MAX_M5_CONFIG2_DSOCEN_CLR(v) | MAX_M5_CONFIG2_DSOCEN) |
| 1528 | #define MAX_M5_CONFIG2_TALRTEN_MASK 0x1 |
| 1529 | #define MAX_M5_CONFIG2_TALRTEN_SHIFT 6 |
| 1530 | #define MAX_M5_CONFIG2_TALRTEN_CLEAR (~(0x1 << 6)) |
| 1531 | #define MAX_M5_CONFIG2_TALRTEN_CLR(v) \ |
| 1532 | ((v) & MAX_M5_CONFIG2_TALRTEN_CLEAR) |
| 1533 | #define MAX_M5_CONFIG2_TALRTEN_SET(v) \ |
| 1534 | (MAX_M5_CONFIG2_TALRTEN_CLR(v) | MAX_M5_CONFIG2_TALRTEN) |
| 1535 | #define MAX_M5_CONFIG2_LDMDL_MASK 0x1 |
| 1536 | #define MAX_M5_CONFIG2_LDMDL_SHIFT 5 |
| 1537 | #define MAX_M5_CONFIG2_LDMDL_CLEAR (~(0x1 << 5)) |
| 1538 | #define MAX_M5_CONFIG2_LDMDL_CLR(v) \ |
| 1539 | ((v) & MAX_M5_CONFIG2_LDMDL_CLEAR) |
| 1540 | #define MAX_M5_CONFIG2_LDMDL_SET(v) \ |
| 1541 | (MAX_M5_CONFIG2_LDMDL_CLR(v) | MAX_M5_CONFIG2_LDMDL) |
| 1542 | #define MAX_M5_CONFIG2_OCVQEN_MASK 0x1 |
| 1543 | #define MAX_M5_CONFIG2_OCVQEN_SHIFT 4 |
| 1544 | #define MAX_M5_CONFIG2_OCVQEN_CLEAR (~(0x1 << 4)) |
| 1545 | #define MAX_M5_CONFIG2_OCVQEN_CLR(v) \ |
| 1546 | ((v) & MAX_M5_CONFIG2_OCVQEN_CLEAR) |
| 1547 | #define MAX_M5_CONFIG2_OCVQEN_SET(v) \ |
| 1548 | (MAX_M5_CONFIG2_OCVQEN_CLR(v) | MAX_M5_CONFIG2_OCVQEN) |
| 1549 | #define MAX_M5_CONFIG2_ISYSNCURR_MASK 0xf |
| 1550 | #define MAX_M5_CONFIG2_ISYSNCURR_SHIFT 0 |
| 1551 | #define MAX_M5_CONFIG2_ISYSNCURR_CLEAR (~(0xf << 0)) |
| 1552 | #define MAX_M5_CONFIG2_ISYSNCURR_CLR(v) \ |
| 1553 | ((v) & MAX_M5_CONFIG2_ISYSNCURR_CLEAR) |
| 1554 | #define MAX_M5_CONFIG2_ISYSNCURR_SET(v) \ |
| 1555 | (MAX_M5_CONFIG2_ISYSNCURR_CLR(v) | MAX_M5_CONFIG2_ISYSNCURR) |
| 1556 | |
| 1557 | /* VRipple,0xBC,0b00000000,0x00 |
| 1558 | * Vripple[15:8],,,,,, |
| 1559 | */ |
| 1560 | #define MAX_M5_VRIPPLE 0xBC |
| 1561 | |
| 1562 | /* RippleCfg,0xBD,0b1000000100,0x204 |
| 1563 | * kDV[12:5],,,,,, |
| 1564 | */ |
| 1565 | #define MAX_M5_RIPPLECFG 0xBD |
| 1566 | #define MAX_M5_RIPPLECFG_KDV (0x1fff << 3) |
| 1567 | #define MAX_M5_RIPPLECFG_NR (0x7 << 0) |
| 1568 | |
| 1569 | #define MAX_M5_RIPPLECFG_KDV_MASK 0x1fff |
| 1570 | #define MAX_M5_RIPPLECFG_KDV_SHIFT 3 |
| 1571 | #define MAX_M5_RIPPLECFG_KDV_CLEAR (~(0x1fff << 3)) |
| 1572 | #define MAX_M5_RIPPLECFG_KDV_CLR(v) \ |
| 1573 | ((v) & MAX_M5_RIPPLECFG_KDV_CLEAR) |
| 1574 | #define MAX_M5_RIPPLECFG_KDV_SET(v) \ |
| 1575 | (MAX_M5_RIPPLECFG_KDV_CLR(v) | MAX_M5_RIPPLECFG_KDV) |
| 1576 | #define MAX_M5_RIPPLECFG_NR_MASK 0x7 |
| 1577 | #define MAX_M5_RIPPLECFG_NR_SHIFT 0 |
| 1578 | #define MAX_M5_RIPPLECFG_NR_CLEAR (~(0x7 << 0)) |
| 1579 | #define MAX_M5_RIPPLECFG_NR_CLR(v) ((v) & MAX_M5_RIPPLECFG_NR_CLEAR) |
| 1580 | #define MAX_M5_RIPPLECFG_NR_SET(v) \ |
| 1581 | (MAX_M5_RIPPLECFG_NR_CLR(v) | MAX_M5_RIPPLECFG_NR) |
| 1582 | |
| 1583 | /* TimerH,0xBE,0b00000000,0x00 |
| 1584 | * TIMERH[15:8],,,,,, |
| 1585 | */ |
| 1586 | #define MAX_M5_TIMERH 0xBE |
| 1587 | |
| 1588 | /* MaxError,0xBF,0b00000000,0x00 |
| 1589 | * MaxError[15:8],,,,,, |
| 1590 | */ |
| 1591 | #define MAX_M5_MAXERROR 0xBF |
| 1592 | |
| 1593 | /* IIn,0xD0,0b00000000,0x00 |
| 1594 | * IIn[15:8],,,,,, |
| 1595 | */ |
| 1596 | #define MAX_M5_IIN 0xD0 |
| 1597 | |
| 1598 | /* AtQresidual,0xDC,0b00000000,0x00 |
| 1599 | * AtQresidual[15:8],,,,,, |
| 1600 | */ |
| 1601 | #define MAX_M5_ATQRESIDUAL 0xDC |
| 1602 | |
| 1603 | /* AtTTE,0xDD,0b00000000,0x00 |
| 1604 | * AtTTE[15:8],,,,,, |
| 1605 | */ |
| 1606 | #define MAX_M5_ATTTE 0xDD |
| 1607 | |
| 1608 | /* AtAvSOC,0xDE,0b00000000,0x00 |
| 1609 | * AtAvSOC[15:8],,,,,, |
| 1610 | */ |
| 1611 | #define MAX_M5_ATAVSOC 0xDE |
| 1612 | |
| 1613 | /* AtAvCap,0xDF,0b00000000,0x00 |
| 1614 | * AtAvCap[15:8],,,,,, |
| 1615 | */ |
| 1616 | #define MAX_M5_ATAVCAP 0xDF |
| 1617 | |
| 1618 | #endif /* MAX_M5_REG_H_ */ |
