| /* SPDX-License-Identifier: GPL-2.0-only */ | |
| // | |
| // Copyright (C) 2019 Samsung Electronics Co., Ltd. | |
| // | |
| // Authors: | |
| // Kiwoong <[email protected]> | |
| // | |
| // This program is free software; you can redistribute it and/or modify | |
| // it under the terms of the GNU General Public License as published by | |
| // the Free Software Foundation; either version 2 of the License, or | |
| // (at your option) any later version. | |
| #ifndef _UFS_VS_REGS_H_ | |
| #define _UFS_VS_REGS_H_ | |
| /* HCI */ | |
| #define HCI_TXPRDT_ENTRY_SIZE 0x00 | |
| #define HCI_RXPRDT_ENTRY_SIZE 0x04 | |
| #define HCI_TO_CNT_DIV_VAL 0x08 | |
| #define HCI_1US_TO_CNT_VAL 0x0C | |
| #define CNT_VAL_1US_MASK 0x3ff | |
| #define HCI_INVALID_UPIU_CTRL 0x10 | |
| #define HCI_INVALID_UPIU_BADDR 0x14 | |
| #define HCI_INVALID_UPIU_UBADDR 0x18 | |
| #define HCI_INVALID_UTMR_OFFSET_ADDR 0x1C | |
| #define HCI_INVALID_UTR_OFFSET_ADDR 0x20 | |
| #define HCI_INVALID_DIN_OFFSET_ADDR 0x24 | |
| #define HCI_VENDOR_SPECIFIC_IS 0x38 | |
| #define HCI_VENDOR_SPECIFIC_IE 0x3C | |
| #define AH8_ERR_UECPA_EN BIT(10) | |
| #define AH8_ERR_UECDL_EN BIT(9) | |
| #define AH8_ERR_UECN_EN BIT(8) | |
| #define AH8_ERR_UECT_EN BIT(7) | |
| #define AH8_ERR_UECDME_EN BIT(6) | |
| /* When the controller is in auto-hibernation sequence and UIC error happens, | |
| * report as UIC error with IS.UE register. | |
| */ | |
| #define AH8_ERR_REPORT_UE (AH8_ERR_UECPA_EN | AH8_ERR_UECDL_EN |\ | |
| AH8_ERR_UECN_EN | AH8_ERR_UECT_EN |\ | |
| AH8_ERR_UECDME_EN) | |
| #define HCI_UTRL_NEXUS_TYPE 0x40 | |
| #define HCI_UTMRL_NEXUS_TYPE 0x44 | |
| #define HCI_E2EFC_CTRL 0x48 | |
| #define HCI_SW_RST 0x50 | |
| #define UFS_LINK_SW_RST BIT(0) | |
| #define UFS_UNIPRO_SW_RST BIT(1) | |
| #define UFS_SW_RST_MASK (UFS_UNIPRO_SW_RST | UFS_LINK_SW_RST) | |
| #define HCI_LINK_VERSION 0x54 | |
| #define HCI_IDLE_TIMER_CONFIG 0x58 | |
| #define HCI_RX_UPIU_MATCH_ERROR_CODE 0x5C | |
| #define HCI_DATA_REORDER 0x60 | |
| #define HCI_MAX_DOUT_DATA_SIZE 0x64 | |
| #define HCI_UNIPRO_APB_CLK_CTRL 0x68 | |
| #define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C | |
| #define BURST_LEN(x) ((x) << 27 | (x)) | |
| #define WLU_EN BIT(31) | |
| #define AXIDMA_RWDATA_BURST_LEN (0xF) | |
| #define HCI_GPIO_OUT 0x70 | |
| #define HCI_WRITE_DMA_CTRL 0x74 | |
| #define HCI_ERROR_EN_PA_LAYER 0x78 | |
| #define HCI_ERROR_EN_DL_LAYER 0x7C | |
| #define HCI_ERROR_EN_N_LAYER 0x80 | |
| #define HCI_ERROR_EN_T_LAYER 0x84 | |
| #define HCI_ERROR_EN_DME_LAYER 0x88 | |
| #define HCI_UFSHCI_V2P1_CTRL 0X8C | |
| #define IA_TICK_SEL BIT(16) | |
| #define HCI_REQ_HOLD_EN 0xAC | |
| #define HCI_CLKSTOP_CTRL 0xB0 | |
| #define REFCLKOUT_STOP BIT(4) | |
| #define MPHY_APBCLK_STOP BIT(3) | |
| #define REFCLK_STOP BIT(2) | |
| #define UNIPRO_MCLK_STOP BIT(1) | |
| #define UNIPRO_PCLK_STOP BIT(0) | |
| #define CLK_STOP_ALL (REFCLKOUT_STOP |\ | |
| REFCLK_STOP |\ | |
| UNIPRO_MCLK_STOP |\ | |
| UNIPRO_PCLK_STOP) | |
| #define HCI_FORCE_HCS 0xB4 | |
| #define REFCLKOUT_STOP_EN BIT(11) | |
| #define MPHY_APBCLK_STOP_EN BIT(10) | |
| #define UFSP_DRCG_EN BIT(8) //FMP | |
| #define REFCLK_STOP_EN BIT(7) | |
| #define UNIPRO_PCLK_STOP_EN BIT(6) | |
| #define UNIPRO_MCLK_STOP_EN BIT(5) | |
| #define HCI_CORECLK_STOP_EN BIT(4) | |
| #define CLK_STOP_CTRL_EN_ALL (UFSP_DRCG_EN |\ | |
| MPHY_APBCLK_STOP_EN |\ | |
| REFCLKOUT_STOP_EN |\ | |
| REFCLK_STOP_EN |\ | |
| UNIPRO_PCLK_STOP_EN |\ | |
| UNIPRO_MCLK_STOP_EN) | |
| #define HCI_FSM_MONITOR 0xC0 | |
| #define HCI_PRDT_HIT_RATIO 0xC4 | |
| #define HCI_DMA0_MONITOR_STATE 0xC8 | |
| #define HCI_DMA0_MONITOR_CNT 0xCC | |
| #define HCI_DMA1_MONITOR_STATE 0xD0 | |
| #define HCI_DMA1_MONITOR_CNT 0xD4 | |
| #define HCI_DMA0_DOORBELL_DEBUG 0xD8 | |
| #define HCI_DMA1_DOORBELL_DEBUG 0xDC | |
| #define HCI_UFS_AXI_DMA_IF_CTRL 0xF8 | |
| #define HCI_UFS_ACG_DISABLE 0xFC | |
| #define HCI_UFS_ACG_DISABLE_EN BIT(0) | |
| #define HCI_IOP_ACG_DISABLE 0x100 | |
| #define HCI_IOP_ACG_DISABLE_EN BIT(0) | |
| #define HCI_MPHY_REFCLK_SEL 0x108 | |
| #define MPHY_REFCLK_SEL BIT(0) | |
| #define HCI_SMU_RD_ABORT_MATCH_INFO 0x118 | |
| #define HCI_SMU_WR_ABORT_MATCH_INFO 0x11C | |
| #define HCI_DBR_DUPLICATION_INFO 0x120 | |
| #define HCI_INVALID_PRDT_CTRL 0x130 | |
| #define HCI_DBR_TIMER_CONFIG 0x140 | |
| #define HCI_UTRL_DBR_TIMER_ENABLE 0x144 | |
| #define HCI_UTRL_DBR_TIMER_STATUS 0x148 | |
| #define HCI_UTMRL_DBR_TIMER_ENABLE 0x14C | |
| #define HCI_UTMRL_DBR_TIMER_STATUS 0x150 | |
| #define HCI_UTRL_DBR_3_0_TIMER_EXPIRED_VALUE 0x160 | |
| #define HCI_UTRL_DBR_7_4_TIMER_EXPIRED_VALUE 0x164 | |
| #define HCI_UTRL_DBR_11_8_TIMER_EXPIRED_VALUE 0x168 | |
| #define HCI_UTRL_DBR_15_12_TIMER_EXPIRED_VALUE 0x16C | |
| #define HCI_UTRL_DBR_19_16_TIMER_EXPIRED_VALUE 0x170 | |
| #define HCI_UTRL_DBR_23_20_TIMER_EXPIRED_VALUE 0x174 | |
| #define HCI_UTRL_DBR_27_24_TIMER_EXPIRED_VALUE 0x178 | |
| #define HCI_UTRL_DBR_31_28_TIMER_EXPIRED_VALUE 0x17C | |
| #define HCI_UTMRL_DBR_3_0_TIMER_EXPIRED_VALUE 0x180 | |
| #define HCI_AH8_RESET 0x500 | |
| #define HCI_AH8_STATE 0x50C | |
| #define HCI_AH8_STATE_ERROR BIT(16) | |
| #define HCI_AH8_HIBERNATION_STATE BIT(8) | |
| #define HCI_AH8_IDLE_STATE BIT(0) | |
| /* Device fatal error */ | |
| #define DFES_ERR_EN BIT(31) | |
| #define DFES_DEF_DL_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\ | |
| UIC_DATA_LINK_LAYER_ERROR_PA_INIT) | |
| #define DFES_DEF_N_ERRS (UIC_NETWORK_UNSUPPORTED_HEADER_TYPE |\ | |
| UIC_NETWORK_BAD_DEVICEID_ENC |\ | |
| UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING) | |
| #define DFES_DEF_T_ERRS (UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE |\ | |
| UIC_TRANSPORT_UNKNOWN_CPORTID |\ | |
| UIC_TRANSPORT_NO_CONNECTION_RX |\ | |
| UIC_TRANSPORT_BAD_TC) | |
| /* TXPRDT defines */ | |
| #define PRDT_PREFECT_EN BIT(31) | |
| #define PRDT_SET_SIZE(x) ((x) & 0x1F) | |
| /* | |
| * UNIPRO registers | |
| */ | |
| #define UNIP_COMP_VERSION 0x000 | |
| #define UNIP_COMP_INFO 0x004 | |
| #define UNIP_COMP_RESET 0x010 | |
| #define UNIP_PA_AVAILTXDATALENS 0x3080 | |
| #define UNIP_PA_AVAILRXDATALENS 0x3100 | |
| #define UNIP_PA_ACTIVETXDATALENS 0x3180 | |
| #define UNIP_PA_CONNECTEDTXDATALANES 0x3184 /* PA_ConnectedTxDataLanes */ | |
| #define UNIP_PA_ACTIVERXDATALENS 0x3200 | |
| #define UNIP_PA_CONNECTEDRXDATALANES 0x3204 /* PA_ConnectedRxDataLanes */ | |
| #define UNIP_PA_MAXRXHSGEAR 0x321C | |
| #define UNIP_DBG_RX_INFO_CONTROL_DIRECT 0x4818 /* to raise an error */ | |
| #define DBG_DL_RX_INFO_FORCE (1 << 28) | |
| #define DBG_DL_RX_INFO_TYPE (21 << 18) | |
| #define DBG_RX_BUFFER_OVERFLOW (1 << 15) | |
| #define UNIP_DME_POWERON_REQ 0x7800 | |
| #define UNIP_DME_POWERON_CNF_RESULT 0x7804 | |
| #define UNIP_DME_POWEROFF_REQ 0x7810 | |
| #define UNIP_DME_POWEROFF_CNF_RESULT 0x7814 | |
| #define UNIP_DME_RESET_REQ 0x7820 | |
| #define UNIP_DME_RESET_REQ_LEVEL 0x7824 | |
| #define UNIP_DME_ENABLE_REQ 0x7830 | |
| #define UNIP_DME_ENABLE_CNF_RESULT 0x7834 | |
| #define UNIP_DME_ENDPOINTRESET_REQ 0x7840 | |
| #define UNIP_DME_ENDPOINTRESET_CNF_RESULT 0x7844 | |
| #define UNIP_DME_LINKSTARTUP_REQ 0x7850 | |
| #define UNIP_DME_LINKSTARTUP_CNF_RESULT 0x7854 | |
| #define UNIP_DME_HIBERN8_ENTER_REQ 0x7860 | |
| #define UNIP_DME_HIBERN8_ENTER_CNF_RESULT 0x7864 | |
| #define UNIP_DME_HIBERN8_ENTER_IND_RESULT 0x7868 | |
| #define UNIP_DME_HIBERN8_EXIT_REQ 0x7870 | |
| #define UNIP_DME_HIBERN8_EXIT_CNF_RESULT 0x7874 | |
| #define UNIP_DME_HIBERN8_EXIT_IND_RESULT 0x7878 | |
| #define UNIP_DME_PWR_REQ 0x7880 | |
| #define UNIP_DME_PWR_REQ_POWERMODE 0x7884 | |
| #define UNIP_DME_PWR_REQ_LOCALL2TIMER0 0x7888 | |
| #define UNIP_DME_PWR_REQ_LOCALL2TIMER1 0x788C | |
| #define UNIP_DME_PWR_REQ_LOCALL2TIMER2 0x7890 | |
| #define UNIP_DME_PWR_REQ_REMOTEL2TIMER0 0x78B8 | |
| #define UNIP_DME_PWR_REQ_REMOTEL2TIMER1 0x78BC | |
| #define UNIP_DME_PWR_REQ_REMOTEL2TIMER2 0x78C0 | |
| #define UNIP_DME_PWR_CNF_RESULT 0x78E8 | |
| #define UNIP_DME_PWR_IND_RESULT 0x78EC | |
| #define UNIP_DME_TEST_MODE_REQ 0x7900 | |
| #define UNIP_DME_TEST_MODE_CNF_RESULT 0x7904 | |
| #define UNIP_DME_ERROR_IND_LAYER 0x0C0 | |
| #define UNIP_DME_ERROR_IND_ERRCODE 0x0C4 | |
| #define UNIP_DME_PACP_CNFBIT 0x0C8 | |
| #define UNIP_DME_DL_FRAME_IND 0x0D0 | |
| #define UNIP_DME_INTR_STATUS 0x0E0 | |
| #define UNIP_DME_INTR_ENABLE 0x0E4 | |
| #define UNIP_DME_GETSET_CONTROL 0x7A00 | |
| #define UNIP_DME_GETSET_ADDR 0x7A04 | |
| #define UNIP_DME_GETSET_WDATA 0x7A08 | |
| #define UNIP_DME_GETSET_RDATA 0x7A0C | |
| #define UNIP_DME_GETSET_RESULT 0x7A10 | |
| #define UNIP_DME_PEER_GETSET_CONTROL 0x7A20 | |
| #define UNIP_DME_PEER_GETSET_ADDR 0x7A24 | |
| #define UNIP_DME_PEER_GETSET_WDATA 0x7A28 | |
| #define UNIP_DME_PEER_GETSET_RDATA 0x7A2C | |
| #define UNIP_DME_PEER_GETSET_RESULT 0x7A30 | |
| #define UNIP_DME_INTR_STATUS_LSB 0x7B00 | |
| #define UNIP_DME_INTR_STATUS_MSB 0x7B04 | |
| #define UNIP_DME_INTR_ERROR_CODE 0x7B20 | |
| #define UNIP_DME_DISCARD_PORT_ID 0x7B24 | |
| #define UNIP_DME_DBG_OPTION_SUITE 0x7C00 | |
| #define UNIP_DME_DBG_CTRL_FSM 0x7D00 | |
| #define UNIP_DME_DBG_FLAG_STATUS 0x7D14 | |
| #define UNIP_DME_DBG_LINKCFG_FSM 0x7D18 | |
| #define UNIP_DME_INTR_ERROR_CODE 0x7B20 | |
| #define UNIP_DME_DEEPSTALL_ENTER_REQ 0x7910 | |
| #define UNIP_DME_DISCARD_CPORT_ID 0x7B24 | |
| #define UNIP_DBG_FORCE_DME_CTRL_STATE 0x150 | |
| #define UNIP_DBG_AUTO_DME_LINKSTARTUP 0x158 | |
| #define UNIP_DBG_PA_CTRLSTATE 0x15C | |
| #define UNIP_DBG_PA_TX_STATE 0x160 | |
| #define UNIP_DBG_BREAK_DME_CTRL_STATE 0x164 | |
| #define UNIP_DBG_STEP_DME_CTRL_STATE 0x168 | |
| #define UNIP_DBG_NEXT_DME_CTRL_STATE 0x16C | |
| /* | |
| * UFS Protector registers | |
| */ | |
| #define UFSPRCTRL 0x000 | |
| #define UFSPRSTAT 0x008 | |
| #define UFSPRSECURITY 0x010 | |
| #define NSSMU BIT(14) | |
| #define DESCTYPE(type) ((type & 0x3) << 19) | |
| #define ARPROTPRDT(type) ((type & 0x3) << 16) | |
| #define ARPROTDESC(type) ((type & 0x3) << 9) | |
| #define ARPROTDATA(type) ((type & 0x3) << 6) | |
| #define AWPROTDESC(type) ((type & 0x3) << 3) | |
| #define AWPROTDATA(type) ((type & 0x3)) | |
| #define CFG_AXPROT(type) (ARPROTPRDT(type) | ARPROTDESC(type) | \ | |
| ARPROTDATA(type) | AWPROTDESC(type) | \ | |
| AWPROTDATA(type)) | |
| #define UFSPVERSION 0x01C | |
| #define UFSPRENCKEY0 0x020 | |
| #define UFSPRENCKEY1 0x024 | |
| #define UFSPRENCKEY2 0x028 | |
| #define UFSPRENCKEY3 0x02C | |
| #define UFSPRENCKEY4 0x030 | |
| #define UFSPRENCKEY5 0x034 | |
| #define UFSPRENCKEY6 0x038 | |
| #define UFSPRENCKEY7 0x03C | |
| #define UFSPRTWKEY0 0x040 | |
| #define UFSPRTWKEY1 0x044 | |
| #define UFSPRTWKEY2 0x048 | |
| #define UFSPRTWKEY3 0x04C | |
| #define UFSPRTWKEY4 0x050 | |
| #define UFSPRTWKEY5 0x054 | |
| #define UFSPRTWKEY6 0x058 | |
| #define UFSPRTWKEY7 0x05C | |
| #define UFSPWCTRL 0x100 | |
| #define UFSPWSTAT 0x108 | |
| #define UFSPWSECURITY 0x110 | |
| #define UFSPWENCKEY0 0x120 | |
| #define UFSPWENCKEY1 0x124 | |
| #define UFSPWENCKEY2 0x128 | |
| #define UFSPWENCKEY3 0x12C | |
| #define UFSPWENCKEY4 0x130 | |
| #define UFSPWENCKEY5 0x134 | |
| #define UFSPWENCKEY6 0x138 | |
| #define UFSPWENCKEY7 0x13C | |
| #define UFSPWTWKEY0 0x140 | |
| #define UFSPWTWKEY1 0x144 | |
| #define UFSPWTWKEY2 0x148 | |
| #define UFSPWTWKEY3 0x14C | |
| #define UFSPWTWKEY4 0x150 | |
| #define UFSPWTWKEY5 0x154 | |
| #define UFSPWTWKEY6 0x158 | |
| #define UFSPWTWKEY7 0x15C | |
| #define UFSPSBEGIN0 0x200 | |
| #define UFSPSEND0 0x204 | |
| #define UFSPSLUN0 0x208 | |
| #define UFSPSCTRL0 0x20C | |
| #define UFSPSBEGIN1 0x210 | |
| #define UFSPSEND1 0x214 | |
| #define UFSPSLUN1 0x218 | |
| #define UFSPSCTRL1 0x21C | |
| #define UFSPSBEGIN2 0x220 | |
| #define UFSPSEND2 0x224 | |
| #define UFSPSLUN2 0x228 | |
| #define UFSPSCTRL2 0x22C | |
| #define UFSPSBEGIN3 0x230 | |
| #define UFSPSEND3 0x234 | |
| #define UFSPSLUN3 0x238 | |
| #define UFSPSCTRL3 0x23C | |
| #define UFSPSBEGIN4 0x240 | |
| #define UFSPSEND4 0x244 | |
| #define UFSPSLUN4 0x248 | |
| #define UFSPSCTRL4 0x24C | |
| #define UFSPSBEGIN5 0x250 | |
| #define UFSPSEND5 0x254 | |
| #define UFSPSLUN5 0x258 | |
| #define UFSPSCTRL5 0x25C | |
| #define UFSPSBEGIN6 0x260 | |
| #define UFSPSEND6 0x264 | |
| #define UFSPSLUN6 0x268 | |
| #define UFSPSCTRL6 0x26C | |
| #define UFSPSBEGIN7 0x270 | |
| #define UFSPSEND7 0x274 | |
| #define UFSPSLUN7 0x278 | |
| #define UFSPSCTRL7 0x27C | |
| #endif /* _UFS_VS_REGS_H_ */ |