| /* SPDX-License-Identifier: GPL-2.0 */ | |
| /* | |
| * Defines DT bindinding IDs for ZUMA clock controller. | |
| * | |
| * Copyright (c) 2022 Samsung Electronics Co., Ltd. | |
| */ | |
| #ifndef _DT_BINDINGS_CLOCK_ZUMA_H | |
| #define _DT_BINDINGS_CLOCK_ZUMA_H | |
| /* External clock */ | |
| #define NONE (0 + 0) | |
| #define OSCCLK (0 + 1) | |
| /* APM level CLK's ID */ | |
| #define CLK_APM_BASE (10) | |
| #define MUX_APM_FUNCSRC (CLK_APM_BASE + 0) | |
| #define MUX_APM_FUNC (CLK_APM_BASE + 1) | |
| #define DOUT_CLK_APM_NOC (CLK_APM_BASE + 2) | |
| #define DOUT_CLK_APM_NOC_LH (CLK_APM_BASE + 3) | |
| #define DOUT_CLK_APM_BOOST (CLK_APM_BASE + 4) | |
| #define DOUT_CLK_APM_USI0_UART (CLK_APM_BASE + 5) | |
| #define DOUT_CLK_APM_USI1_UART (CLK_APM_BASE + 6) | |
| #define DOUT_CLK_APM_USI0_USI (CLK_APM_BASE + 7) | |
| /* TOP level CLK's ID */ | |
| #define CLK_TOP_BASE (50) | |
| #define GATE_DFTMUX_CMU_CIS_CLK0 (CLK_TOP_BASE + 0) | |
| #define GATE_DFTMUX_CMU_CIS_CLK1 (CLK_TOP_BASE + 1) | |
| #define GATE_DFTMUX_CMU_CIS_CLK2 (CLK_TOP_BASE + 2) | |
| #define GATE_DFTMUX_CMU_CIS_CLK3 (CLK_TOP_BASE + 3) | |
| #define GATE_DFTMUX_CMU_CIS_CLK4 (CLK_TOP_BASE + 4) | |
| #define GATE_DFTMUX_CMU_CIS_CLK5 (CLK_TOP_BASE + 5) | |
| #define GATE_DFTMUX_CMU_CIS_CLK6 (CLK_TOP_BASE + 6) | |
| #define GATE_DFTMUX_CMU_CIS_CLK7 (CLK_TOP_BASE + 7) | |
| #define CIS_CLK0 (CLK_TOP_BASE + 9) | |
| #define CIS_CLK1 (CLK_TOP_BASE + 10) | |
| #define CIS_CLK2 (CLK_TOP_BASE + 11) | |
| #define CIS_CLK3 (CLK_TOP_BASE + 12) | |
| #define CIS_CLK4 (CLK_TOP_BASE + 13) | |
| #define CIS_CLK5 (CLK_TOP_BASE + 14) | |
| #define CIS_CLK6 (CLK_TOP_BASE + 15) | |
| #define CIS_CLK7 (CLK_TOP_BASE + 16) | |
| #define VDOUT_CLK_TOP_HSI0_NOC (CLK_TOP_BASE + 17) | |
| /* NOC level CLK's ID */ | |
| #define CLK_NOCL1B_BASE (100) /* AON bus */ | |
| #define UMUX_CLKCMU_NOCL1B_NOC (CLK_NOCL1B_BASE + 0) | |
| #define MUX_NOCL1B_NOC_OPTION1 (CLK_NOCL1B_BASE + 1) | |
| #define DOUT_CLK_NOCL1B_NOCP (CLK_NOCL1B_BASE + 2) | |
| #define CLK_NOCL2A_BASE (150) /* M/M bus */ | |
| #define UMUX_CLKCMU_NOCL2AA_NOC (CLK_NOCL2A_BASE + 0) | |
| #define UMUX_CLKCMU_NOCL2AB_NOC (CLK_NOCL2A_BASE + 0) | |
| #define DOUT_CLK_NOCL2AA_NOCP (CLK_NOCL2A_BASE + 1) | |
| #define DOUT_CLK_NOCL2AB_NOCP (CLK_NOCL2A_BASE + 1) | |
| #define CLK_NOCL1A_BASE (200) | |
| #define UMUX_CLKCMU_NOCL1A_NOC (CLK_NOCL1A_BASE + 0) | |
| #define DOUT_CLK_NOCL1A_NOCP (CLK_NOCL1A_BASE + 1) | |
| #define CLK_NOCL0_BASE (250) | |
| #define UMUX_CLKCMU_NOCL0_NOC (CLK_NOCL0_BASE + 0) | |
| /* IP block level CLK's ID */ | |
| #define CLK_EH_BASE (300) | |
| #define UMUX_CLKCMU_EH_NOC (CLK_EH_BASE + 0) | |
| #define DOUT_CLK_EH_NOCP (CLK_EH_BASE + 1) | |
| #define CLK_G3D_BASE (350) | |
| #define GATE_GPU (CLK_G3D_BASE + 0) | |
| #define CLK_DPUF_BASE (400) /* DPU */ | |
| #define UMUX_CLKCMU_DPUF0_NOC (CLK_DPUF_BASE + 0) | |
| #define UMUX_CLKCMU_DPUF1_NOC (CLK_DPUF_BASE + 1) | |
| #define DOUT_CLK_DPUF0_NOCP (CLK_DPUF_BASE + 2) | |
| #define DOUT_CLK_DPUF1_NOCP (CLK_DPUF_BASE + 3) | |
| #define CLK_DPUB_BASE (450) /* DISP */ | |
| #define UMUX_CLKCMU_DPUB_NOC (CLK_DPUB_BASE + 0) | |
| #define GATE_DPUB (CLK_DPUB_BASE + 1) | |
| #define DOUT_CLK_DPUB_NOCP (CLK_DPUB_BASE + 2) | |
| #define CLK_G2D_BASE (500) | |
| #define UMUX_CLKCMU_G2D_G2D (CLK_G2D_BASE + 0) | |
| #define UMUX_CLKCMU_G2D_JPEG (CLK_G2D_BASE + 1) | |
| #define GATE_G2D (CLK_G2D_BASE + 2) | |
| #define GATE_JPEG (CLK_G2D_BASE + 3) | |
| #define DOUT_CLK_G2D_NOCP (CLK_G2D_BASE + 4) | |
| #define CLK_HSI0_BASE (550) | |
| #define UMUX_CLKCMU_HSI0_TCXO (CLK_HSI0_BASE + 0) | |
| #define MUX_HSI0_USB20_REF (CLK_HSI0_BASE + 1) | |
| #define UMUX_CLKCMU_HSI0_USB32DRD (CLK_HSI0_BASE + 2) | |
| #define UMUX_CLKCMU_HSI0_USB20 (CLK_HSI0_BASE + 3) | |
| #define MUX_HSI0_USB32DRD (CLK_HSI0_BASE + 4) | |
| #define UMUX_CLKCMU_HSI0_NOC (CLK_HSI0_BASE + 5) | |
| #define UMUX_CLKCMU_HSI0_ALT (CLK_HSI0_BASE + 6) | |
| #define MUX_HSI0_NOC (CLK_HSI0_BASE + 7) | |
| #define UMUX_CLKCMU_HSI0_DPGTC (CLK_HSI0_BASE + 8) | |
| #define GATE_USB32DRD_LINK (CLK_HSI0_BASE + 9) | |
| #define DOUT_CLK_HSI0_USB32DRD (CLK_HSI0_BASE + 10) | |
| #define GATE_HSI0_USI0_USI (CLK_HSI0_BASE + 11) | |
| #define GATE_HSI0_USI1_USI (CLK_HSI0_BASE + 12) | |
| #define GATE_HSI0_USI2_USI (CLK_HSI0_BASE + 13) | |
| #define GATE_HSI0_USI3_USI (CLK_HSI0_BASE + 14) | |
| #define GATE_HSI0_USI4_USI (CLK_HSI0_BASE + 15) | |
| #define VDOUT_CLK_HSI0_USI0_USI (CLK_HSI0_BASE + 16) | |
| #define VDOUT_CLK_HSI0_USI1_USI (CLK_HSI0_BASE + 17) | |
| #define VDOUT_CLK_HSI0_USI2_USI (CLK_HSI0_BASE + 18) | |
| #define VDOUT_CLK_HSI0_USI3_USI (CLK_HSI0_BASE + 19) | |
| #define VDOUT_CLK_HSI0_USI4_USI (CLK_HSI0_BASE + 20) | |
| #define UMUX_CLKCMU_HSI0_DPOSC_USER (CLK_HSI0_BASE + 21) | |
| #define CLK_HSI1_BASE (600) | |
| #define UMUX_CLKCMU_HSI1_NOC (CLK_HSI1_BASE + 0) | |
| #define UMUX_CLKCMU_HSI1_PCIE (CLK_HSI1_BASE + 1) | |
| #define GATE_PCIE_GEN3_0_UDBG (CLK_HSI1_BASE + 2) | |
| #define GATE_PCIE_GEN3_0_AXI (CLK_HSI1_BASE + 3) | |
| #define GATE_PCIE_GEN3_0_APB (CLK_HSI1_BASE + 4) | |
| #define GATE_PCIE_GEN3_0_PCS_APB (CLK_HSI1_BASE + 6) | |
| #define GATE_PCIE_GEN3_0_PMA_APB (CLK_HSI1_BASE + 7) | |
| #define CLK_HSI2_BASE (650) | |
| #define UMUX_CLKCMU_HSI2_NOC (CLK_HSI2_BASE + 0) | |
| #define UMUX_CLKCMU_HSI2_PCIE (CLK_HSI2_BASE + 1) | |
| #define UMUX_CLKCMU_HSI2_UFS_EMBD (CLK_HSI2_BASE + 2) | |
| #define UMUX_CLKCMU_HSI2_MMC_CARD (CLK_HSI2_BASE + 3) | |
| #define GATE_MMC_CARD (CLK_HSI2_BASE + 4) | |
| #define GATE_PCIE_GEN3A_1_AXI (CLK_HSI2_BASE + 5) | |
| #define GATE_PCIE_GEN3A_1_APB (CLK_HSI2_BASE + 6) | |
| #define GATE_PCIE_GEN3A_1_DBG (CLK_HSI2_BASE + 7) | |
| #define GATE_PCIE_GEN3A_1_UDBG (CLK_HSI2_BASE + 8) | |
| #define GATE_PCIE_GEN3A_1_PCS_APB (CLK_HSI2_BASE + 9) | |
| #define GATE_PCIE_GEN3A_1_PMA_APB (CLK_HSI2_BASE + 10) | |
| #define GATE_PCIE_GEN3B_1_AXI (CLK_HSI2_BASE + 5) | |
| #define GATE_PCIE_GEN3B_1_APB (CLK_HSI2_BASE + 6) | |
| #define GATE_PCIE_GEN3B_1_DBG (CLK_HSI2_BASE + 7) | |
| #define GATE_PCIE_GEN3B_1_UDBG (CLK_HSI2_BASE + 8) | |
| #define GATE_PCIE_GEN3B_1_PCS_APB (CLK_HSI2_BASE + 9) | |
| #define GATE_PCIE_GEN3B_1_PMA_APB (CLK_HSI2_BASE + 10) | |
| #define GATE_UFS_EMBD (CLK_HSI2_BASE + 15) | |
| #define GATE_UFS_EMBD_FMP (CLK_HSI2_BASE + 16) | |
| #define DOUT_CLKCMU_HSI2_MMC_CARD (CLK_HSI2_BASE + 17) | |
| #define UFS_EMBD (CLK_HSI2_BASE + 18) | |
| #define CLK_ISPFE_BASE (700) | |
| #define UMUX_CLKCMU_ISPFE (CLK_ISPFE_BASE + 0) | |
| #define DOUT_CLK_ISPFE_NOCP (CLK_ISPFE_BASE + 1) | |
| #define CLK_YUVP_BASE (750) | |
| #define UMUX_CLKCMU_YUVP (CLK_YUVP_BASE + 0) | |
| #define DOUT_CLK_YUVP_NOCP (CLK_YUVP_BASE + 1) | |
| #define CLK_GSE_BASE (800) | |
| #define UMUX_CLKCMU_GSE (CLK_GSE_BASE + 0) | |
| #define DOUT_CLK_GSE_NOCP (CLK_GSE_BASE + 1) | |
| #define CLK_RGBP_BASE (800) | |
| #define UMUX_CLKCMU_RGBP_RGBP (CLK_RGBP_BASE + 0) | |
| #define UMUX_CLKCMU_RGBP_MCFP (CLK_RGBP_BASE + 1) | |
| #define DOUT_CLK_RGBP_NOCP (CLK_RGBP_BASE + 2) | |
| #define CLK_MCSC_BASE (1050) | |
| #define UMUX_CLKCMU_MCSC (CLK_MCSC_BASE + 0) | |
| #define DOUT_CLK_MCSC_NOCP (CLK_MCSC_BASE + 1) | |
| #define CLK_GDC_BASE (1100) | |
| #define UMUX_CLKCMU_GDC_LME (CLK_GDC_BASE + 0) | |
| #define UMUX_CLKCMU_GDC_GDC0 (CLK_GDC_BASE + 1) | |
| #define UMUX_CLKCMU_GDC_GDC1 (CLK_GDC_BASE + 2) | |
| #define DOUT_CLK_GDC_NOCP (CLK_GDC_BASE + 3) | |
| #define CLK_TNR_BASE (1100) | |
| #define UMUX_CLKCMU_TNR_MERGE (CLK_TNR_BASE + 0) | |
| #define UMUX_CLKCMU_TNR_ALIGN (CLK_TNR_BASE + 1) | |
| #define DOUT_CLK_TNR_NOCP (CLK_TNR_BASE + 2) | |
| #define CLK_MFC_BASE (1150) | |
| #define UMUX_CLKCMU_MFC_MFC (CLK_MFC_BASE + 0) | |
| #define DOUT_CLK_MFC_NOCP (CLK_MFC_BASE + 1) | |
| #define GATE_MFC (CLK_MFC_BASE + 2) | |
| #define CLK_MIF_BASE (1200) | |
| #define UMUX_MIF_DDRPHY2X (CLK_MIF_BASE + 0) | |
| #define CLK_MISC_BASE (1250) | |
| #define UMUX_CLKCMU_MISC_NOC (CLK_MISC_BASE + 0) | |
| #define UMUX_CLKCMU_MISC_SC (CLK_MISC_BASE + 1) | |
| #define GATE_MCT (CLK_MISC_BASE + 2) | |
| #define GATE_WDT_CL0 (CLK_MISC_BASE + 3) | |
| #define GATE_WDT_CL1 (CLK_MISC_BASE + 4) | |
| #define GATE_PDMA0 (CLK_MISC_BASE + 5) | |
| #define GATE_PDMA1 (CLK_MISC_BASE + 6) | |
| #define DOUT_CLK_MISC_NOCP (CLK_MISC_BASE + 7) | |
| #define ATCLK (CLK_MISC_BASE + 8) | |
| #define CLK_PERIC0_BASE (1300) | |
| #define UMUX_CLKCMU_PERIC0_NOC (CLK_PERIC0_BASE + 0) | |
| #define UMUX_CLKCMU_PERIC0_USI0_UART (CLK_PERIC0_BASE + 1) | |
| #define GATE_PERIC0_TOP0_USI1_USI (CLK_PERIC0_BASE + 2) | |
| #define GATE_PERIC0_TOP0_USI2_USI (CLK_PERIC0_BASE + 3) | |
| #define GATE_PERIC0_TOP0_USI3_USI (CLK_PERIC0_BASE + 4) | |
| #define GATE_PERIC0_TOP0_USI4_USI (CLK_PERIC0_BASE + 5) | |
| #define GATE_PERIC0_TOP0_USI5_USI (CLK_PERIC0_BASE + 6) | |
| #define GATE_PERIC0_TOP0_USI6_USI (CLK_PERIC0_BASE + 7) | |
| #define GATE_PERIC0_TOP0_USI14_USI (CLK_PERIC0_BASE + 8) | |
| #define GATE_PERIC0_TOP1_USI0_UART (CLK_PERIC0_BASE + 26) | |
| #define VDOUT_CLK_PERIC0_USI0_UART (CLK_PERIC0_BASE + 28) | |
| #define VDOUT_CLK_PERIC0_USI1_USI (CLK_PERIC0_BASE + 29) | |
| #define VDOUT_CLK_PERIC0_USI2_USI (CLK_PERIC0_BASE + 30) | |
| #define VDOUT_CLK_PERIC0_USI3_USI (CLK_PERIC0_BASE + 31) | |
| #define VDOUT_CLK_PERIC0_USI4_USI (CLK_PERIC0_BASE + 32) | |
| #define VDOUT_CLK_PERIC0_USI5_USI (CLK_PERIC0_BASE + 33) | |
| #define VDOUT_CLK_PERIC0_USI6_USI (CLK_PERIC0_BASE + 34) | |
| #define VDOUT_CLK_PERIC0_USI14_USI (CLK_PERIC0_BASE + 37) | |
| #define CLK_PERIC1_BASE (1400) | |
| #define UMUX_CLKCMU_PERIC1_NOC (CLK_PERIC1_BASE + 0) | |
| #define GATE_PERIC1_TOP0_USI0_USI (CLK_PERIC1_BASE + 1) | |
| #define GATE_PERIC1_TOP0_USI9_USI (CLK_PERIC1_BASE + 2) | |
| #define GATE_PERIC1_TOP0_USI10_USI (CLK_PERIC1_BASE + 3) | |
| #define GATE_PERIC1_TOP0_USI11_USI (CLK_PERIC1_BASE + 4) | |
| #define GATE_PERIC1_TOP0_USI12_USI (CLK_PERIC1_BASE + 5) | |
| #define GATE_PERIC1_TOP0_USI13_USI (CLK_PERIC1_BASE + 6) | |
| #define GATE_PERIC1_TOP0_USI15_USI (CLK_PERIC1_BASE + 7) | |
| #define GATE_PERIC1_TOP0_PWM (CLK_PERIC1_BASE + 8) | |
| #define VDOUT_CLK_PERIC1_USI0_USI (CLK_PERIC1_BASE + 10) | |
| #define VDOUT_CLK_PERIC1_USI9_USI (CLK_PERIC1_BASE + 11) | |
| #define VDOUT_CLK_PERIC1_USI10_USI (CLK_PERIC1_BASE + 12) | |
| #define VDOUT_CLK_PERIC1_USI11_USI (CLK_PERIC1_BASE + 13) | |
| #define VDOUT_CLK_PERIC1_USI12_USI (CLK_PERIC1_BASE + 14) | |
| #define VDOUT_CLK_PERIC1_USI13_USI (CLK_PERIC1_BASE + 15) | |
| #define VDOUT_CLK_PERIC1_USI15_USI (CLK_PERIC1_BASE + 16) | |
| #define CLK_TPU_BASE (1450) | |
| #define UMUX_CLKCMU_TPU_TPU (CLK_TPU_BASE + 0) | |
| #define UMUX_CLKCMU_TPU_TPUCTL (CLK_TPU_BASE + 1) | |
| #define UMUX_CLKCMU_TPU_NOC (CLK_TPU_BASE + 2) | |
| #define MUX_TPU_TPU (CLK_TPU_BASE + 4) | |
| #define MUX_TPU_TPUCTL (CLK_TPU_BASE + 5) | |
| #define DOUT_CLK_TPU_TPU (CLK_TPU_BASE + 6) | |
| #define DOUT_CLK_TPU_TPUCTL (CLK_TPU_BASE + 7) | |
| #define DOUT_CLK_TPU_NOCP (CLK_TPU_BASE + 8) | |
| #define CLK_BW_BASE (1500) | |
| #define UMUX_CLKCMU_BW_NOC (CLK_BW_BASE + 0) | |
| #define DOUT_CLK_BW_NOCP (CLK_BW_BASE + 1) | |
| #define CLK_CLKOUT_BASE (1550) | |
| #define CLKOUT1 (CLK_CLKOUT_BASE + 0) | |
| #define CLKOUT0 (CLK_CLKOUT_BASE + 1) | |
| #define CLK_NR_CLKS (1700) | |
| #define ACPM_DVFS_MIF (0x0B040000) | |
| #define ACPM_DVFS_INT (0x0B040001) | |
| #define ACPM_DVFS_CPUCL0 (0x0B040002) | |
| #define ACPM_DVFS_CPUCL1 (0x0B040003) | |
| #define ACPM_DVFS_CPUCL2 (0x0B040004) | |
| #define ACPM_DVFS_DSU (0x0B040005) | |
| #define ACPM_DVFS_BCI (0x0B040006) | |
| #define ACPM_DVFS_G3D (0x0B040007) | |
| #define ACPM_DVFS_G3DL2 (0x0B040008) | |
| #define ACPM_DVFS_TPU (0x0B040009) | |
| #define ACPM_DVFS_INTCAM (0x0B04000A) | |
| #define ACPM_DVFS_TNR (0x0B04000B) | |
| #define ACPM_DVFS_CAM (0x0B04000C) | |
| #define ACPM_DVFS_MFC (0x0B04000D) | |
| #define ACPM_DVFS_DISP (0x0B04000E) | |
| #define ACPM_DVFS_AOC (0x0B04000F) | |
| #define ACPM_DVFS_BW (0x0B040010) | |
| #define ACPM_DVFS_SPARE (0x0B040011) | |
| #define ACPM_DVFS_LPM (0x0B040012) | |
| #define ACPM_DVFS_AUR (0x0B040013) | |
| #define CAMERA_CLOCK_FAMILY_CAM (0) | |
| #define CAMERA_CLOCK_FAMILY_INTCAM (1) | |
| #define CAMERA_CLOCK_FAMILY_TNR (2) | |
| #endif /* _DT_BINDINGS_CLOCK_ZUMA_H */ |