blob: b3c63cfda577031d40535bbe1d736ce271bf25cd [file] [edit]
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* include/linux/mfd/samsung/s2mpg10-register.h
*
* Copyright (C) 2015 Samsung Electronics
*
* header file including register information of s2mpg10
*/
#ifndef __LINUX_MFD_S2MPG10_REGISTER_H
#define __LINUX_MFD_S2MPG10_REGISTER_H
#include <linux/i2c.h>
#include "s2mpg1x-register.h"
#define S2MPG10_REG_INVALID (0xFF)
#define S2MPG10_IRQSRC_PMIC BIT(0)
/* Common(0x0) Registers */
enum S2MPG10_COMMON_REG {
S2MPG10_COMMON_CHIPID = 0x0,
S2MPG10_COMMON_INT,
S2MPG10_COMMON_INT_MASK,
};
/* PM(0x1) Registers */
enum S2MPG10_PM_REG {
S2MPG10_PM_INT1 = 0x0,
S2MPG10_PM_INT2 = 0x1,
S2MPG10_PM_INT3 = 0x2,
S2MPG10_PM_INT4 = 0x3,
S2MPG10_PM_INT5 = 0x4,
S2MPG10_PM_INT6 = 0x5,
S2MPG10_PM_INT1M = 0x6,
S2MPG10_PM_INT2M = 0x7,
S2MPG10_PM_INT3M = 0x8,
S2MPG10_PM_INT4M = 0x9,
S2MPG10_PM_INT5M = 0xA,
S2MPG10_PM_INT6M = 0xB,
S2MPG10_PM_STATUS1 = 0xC,
S2MPG10_PM_STATUS2 = 0xD,
S2MPG10_PM_PWRONSRC = 0xE,
S2MPG10_PM_OFFSRC = 0xF,
S2MPG10_PM_RTCBUF = 0x11,
S2MPG10_PM_COMMON_CTRL1 = 0x12,
S2MPG10_PM_COMMON_CTRL2 = 0x13,
S2MPG10_PM_COMMON_CTRL3 = 0x14,
S2MPG10_PM_COMMON_CTRL4 = 0x15,
S2MPG10_PM_SMPL_WARN_CTRL = 0x16,
S2MPG10_PM_MIMICKING_CTRL = 0x17,
S2MPG10_PM_B1M_CTRL = 0x18,
S2MPG10_PM_B1M_OUT1 = 0x19,
S2MPG10_PM_B1M_OUT2 = 0x1A,
S2MPG10_PM_B2M_CTRL = 0x1B,
S2MPG10_PM_B2M_OUT1 = 0x1C,
S2MPG10_PM_B2M_OUT2 = 0x1D,
S2MPG10_PM_B3M_CTRL = 0x1E,
S2MPG10_PM_B3M_OUT1 = 0x1F,
S2MPG10_PM_B3M_OUT2 = 0x20,
S2MPG10_PM_B4M_CTRL = 0x21,
S2MPG10_PM_B4M_OUT1 = 0x22,
S2MPG10_PM_B4M_OUT2 = 0x23,
S2MPG10_PM_B5M_CTRL = 0x24,
S2MPG10_PM_B5M_OUT1 = 0x25,
S2MPG10_PM_B5M_OUT2 = 0x26,
S2MPG10_PM_B6M_CTRL = 0x27,
S2MPG10_PM_B6M_OUT1 = 0x28,
S2MPG10_PM_B6M_OUT2 = 0x29,
S2MPG10_PM_B7M_CTRL = 0x2A,
S2MPG10_PM_B7M_OUT1 = 0x2B,
S2MPG10_PM_B7M_OUT2 = 0x2C,
S2MPG10_PM_B8M_CTRL = 0x2D,
S2MPG10_PM_B8M_OUT1 = 0x2E,
S2MPG10_PM_B8M_OUT2 = 0x2F,
S2MPG10_PM_B9M_CTRL = 0x30,
S2MPG10_PM_B9M_OUT1 = 0x31,
S2MPG10_PM_B9M_OUT2 = 0x32,
S2MPG10_PM_B10M_CTRL = 0x33,
S2MPG10_PM_B10M_OUT1 = 0x34,
S2MPG10_PM_B10M_OUT2 = 0x35,
S2MPG10_PM_L1M_CTRL = 0x40,
S2MPG10_PM_L2M_CTRL = 0x41,
S2MPG10_PM_L3M_CTRL = 0x42,
S2MPG10_PM_L4M_CTRL = 0x43,
S2MPG10_PM_L5M_CTRL = 0x44,
S2MPG10_PM_L6M_CTRL = 0x45,
S2MPG10_PM_L7M_CTRL = 0x46,
S2MPG10_PM_L8M_CTRL = 0x47,
S2MPG10_PM_L9M_CTRL = 0x48,
S2MPG10_PM_L10M_CTRL = 0x49,
S2MPG10_PM_L11M_CTRL1 = 0x4A,
S2MPG10_PM_L11M_CTRL2 = 0x4B,
S2MPG10_PM_L12M_CTRL1 = 0x4C,
S2MPG10_PM_L12M_CTRL2 = 0x4D,
S2MPG10_PM_L13M_CTRL1 = 0x4E,
S2MPG10_PM_L13M_CTRL2 = 0x4F,
S2MPG10_PM_L14M_CTRL = 0x50,
S2MPG10_PM_L15M_CTRL1 = 0x51,
S2MPG10_PM_L15M_CTRL2 = 0x52,
S2MPG10_PM_L16M_CTRL = 0x53,
S2MPG10_PM_L17M_CTRL = 0x54,
S2MPG10_PM_L18M_CTRL = 0x55,
S2MPG10_PM_L19M_CTRL = 0x56,
S2MPG10_PM_L20M_CTRL = 0x57,
S2MPG10_PM_L21M_CTRL = 0x58,
S2MPG10_PM_L22M_CTRL = 0x59,
S2MPG10_PM_L23M_CTRL = 0x5A,
S2MPG10_PM_L24M_CTRL = 0x5B,
S2MPG10_PM_L25M_CTRL = 0x5C,
S2MPG10_PM_L26M_CTRL = 0x5D,
S2MPG10_PM_L27M_CTRL = 0x5E,
S2MPG10_PM_L28M_CTRL = 0x5F,
S2MPG10_PM_L29M_CTRL = 0x60,
S2MPG10_PM_L30M_CTRL = 0x61,
S2MPG10_PM_L31M_CTRL = 0x62,
S2MPG10_PM_LDO_CTRL1 = 0x63,
S2MPG10_PM_LDO_CTRL2 = 0x64,
S2MPG10_PM_DVS_RAMP1 = 0x6E,
S2MPG10_PM_DVS_RAMP2 = 0x6F,
S2MPG10_PM_DVS_RAMP3 = 0x70,
S2MPG10_PM_DVS_RAMP4 = 0x71,
S2MPG10_PM_DVS_RAMP5 = 0x72,
S2MPG10_PM_DVS_RAMP6 = 0x73,
S2MPG10_PM_DCTRLSEL7 = 0xC6,
S2MPG10_PM_GPIO_CTRL1 = 0xC7,
S2MPG10_PM_GPIO_CTRL2 = 0xC8,
S2MPG10_PM_GPIO_CTRL3 = 0xC9,
S2MPG10_PM_GPIO_CTRL4 = 0xCA,
S2MPG10_PM_GPIO_CTRL5 = 0xCB,
S2MPG10_PM_GPIO_CTRL6 = 0xCC,
S2MPG10_PM_GPIO_CTRL7 = 0xCD,
S2MPG10_PM_B2M_OCP_WARN = 0xCE,
S2MPG10_PM_B3M_OCP_WARN = 0xD2,
S2MPG10_PM_B10M_OCP_WARN = 0xD6,
S2MPG10_PM_B2M_SOFT_OCP_WARN = 0xDA,
S2MPG10_PM_B3M_SOFT_OCP_WARN = 0xDE,
S2MPG10_PM_B10M_SOFT_OCP_WARN = 0xE2,
S2MPG10_PM_BUCK_OCP_CTRL1 = 0xEA,
S2MPG10_PM_BUCK_OCP_CTRL2 = 0xEB,
S2MPG10_PM_BUCK_OCP_CTRL3 = 0xEC,
S2MPG10_PM_BUCK_OCP_CTRL4 = 0xED,
S2MPG10_PM_BUCK_OCP_CTRL5 = 0xEE,
};
/* Meter(0xA) Registers */
enum S2MPG10_METER_REG {
S2MPG10_METER_CTRL1 = 0x0,
S2MPG10_METER_CTRL2 = 0x1,
S2MPG10_METER_CTRL3 = 0x2,
S2MPG10_METER_CTRL4 = 0x3,
S2MPG10_METER_BUCKEN1 = 0x4,
S2MPG10_METER_BUCKEN2 = 0x5,
S2MPG10_METER_MUXSEL0 = 0x6,
S2MPG10_METER_MUXSEL1 = 0x7,
S2MPG10_METER_MUXSEL2 = 0x8,
S2MPG10_METER_MUXSEL3 = 0x9,
S2MPG10_METER_MUXSEL4 = 0xA,
S2MPG10_METER_MUXSEL5 = 0xB,
S2MPG10_METER_MUXSEL6 = 0xC,
S2MPG10_METER_MUXSEL7 = 0xD,
S2MPG10_METER_LPF_C0_0 = 0xE,
S2MPG10_METER_LPF_C0_1 = 0xF,
S2MPG10_METER_LPF_C0_2 = 0x10,
S2MPG10_METER_LPF_C0_3 = 0x11,
S2MPG10_METER_LPF_C0_4 = 0x12,
S2MPG10_METER_LPF_C0_5 = 0x13,
S2MPG10_METER_LPF_C0_6 = 0x14,
S2MPG10_METER_LPF_C0_7 = 0x15,
S2MPG10_METER_PWR_WARN0 = 0x16,
S2MPG10_METER_PWR_WARN1 = 0x17,
S2MPG10_METER_PWR_WARN2 = 0x18,
S2MPG10_METER_PWR_WARN3 = 0x19,
S2MPG10_METER_PWR_WARN4 = 0x1A,
S2MPG10_METER_PWR_WARN5 = 0x1B,
S2MPG10_METER_PWR_WARN6 = 0x1C,
S2MPG10_METER_PWR_WARN7 = 0x1D,
S2MPG10_METER_ACC_DATA_CH0_1 = 0x40,
S2MPG10_METER_ACC_DATA_CH0_2 = 0x41,
S2MPG10_METER_ACC_DATA_CH0_3 = 0x42,
S2MPG10_METER_ACC_DATA_CH0_4 = 0x43,
S2MPG10_METER_ACC_DATA_CH0_5 = 0x44,
S2MPG10_METER_ACC_DATA_CH0_6 = 0x45,
S2MPG10_METER_ACC_DATA_CH1_1 = 0x46,
S2MPG10_METER_ACC_DATA_CH1_2 = 0x47,
S2MPG10_METER_ACC_DATA_CH1_3 = 0x48,
S2MPG10_METER_ACC_DATA_CH1_4 = 0x49,
S2MPG10_METER_ACC_DATA_CH1_5 = 0x4A,
S2MPG10_METER_ACC_DATA_CH1_6 = 0x4B,
S2MPG10_METER_ACC_DATA_CH2_1 = 0x4C,
S2MPG10_METER_ACC_DATA_CH2_2 = 0x4D,
S2MPG10_METER_ACC_DATA_CH2_3 = 0x4E,
S2MPG10_METER_ACC_DATA_CH2_4 = 0x4F,
S2MPG10_METER_ACC_DATA_CH2_5 = 0x50,
S2MPG10_METER_ACC_DATA_CH2_6 = 0x51,
S2MPG10_METER_ACC_DATA_CH3_1 = 0x52,
S2MPG10_METER_ACC_DATA_CH3_2 = 0x53,
S2MPG10_METER_ACC_DATA_CH3_3 = 0x54,
S2MPG10_METER_ACC_DATA_CH3_4 = 0x55,
S2MPG10_METER_ACC_DATA_CH3_5 = 0x56,
S2MPG10_METER_ACC_DATA_CH3_6 = 0x57,
S2MPG10_METER_ACC_DATA_CH4_1 = 0x58,
S2MPG10_METER_ACC_DATA_CH4_2 = 0x59,
S2MPG10_METER_ACC_DATA_CH4_3 = 0x5A,
S2MPG10_METER_ACC_DATA_CH4_4 = 0x5B,
S2MPG10_METER_ACC_DATA_CH4_5 = 0x5C,
S2MPG10_METER_ACC_DATA_CH4_6 = 0x5D,
S2MPG10_METER_ACC_DATA_CH5_1 = 0x5E,
S2MPG10_METER_ACC_DATA_CH5_2 = 0x5F,
S2MPG10_METER_ACC_DATA_CH5_3 = 0x60,
S2MPG10_METER_ACC_DATA_CH5_4 = 0x61,
S2MPG10_METER_ACC_DATA_CH5_5 = 0x62,
S2MPG10_METER_ACC_DATA_CH5_6 = 0x63,
S2MPG10_METER_ACC_DATA_CH6_1 = 0x64,
S2MPG10_METER_ACC_DATA_CH6_2 = 0x65,
S2MPG10_METER_ACC_DATA_CH6_3 = 0x66,
S2MPG10_METER_ACC_DATA_CH6_4 = 0x67,
S2MPG10_METER_ACC_DATA_CH6_5 = 0x68,
S2MPG10_METER_ACC_DATA_CH6_6 = 0x69,
S2MPG10_METER_ACC_DATA_CH7_1 = 0x6A,
S2MPG10_METER_ACC_DATA_CH7_2 = 0x6B,
S2MPG10_METER_ACC_DATA_CH7_3 = 0x6C,
S2MPG10_METER_ACC_DATA_CH7_4 = 0x6D,
S2MPG10_METER_ACC_DATA_CH7_5 = 0x6E,
S2MPG10_METER_ACC_DATA_CH7_6 = 0x6F,
S2MPG10_METER_ACC_COUNT_1 = 0x70,
S2MPG10_METER_ACC_COUNT_2 = 0x71,
S2MPG10_METER_ACC_COUNT_3 = 0x72,
S2MPG10_METER_LPF_DATA_CH0_1 = 0x73,
S2MPG10_METER_LPF_DATA_CH0_2 = 0x74,
S2MPG10_METER_LPF_DATA_CH0_3 = 0x75,
S2MPG10_METER_LPF_DATA_CH1_1 = 0x76,
S2MPG10_METER_LPF_DATA_CH1_2 = 0x77,
S2MPG10_METER_LPF_DATA_CH1_3 = 0x78,
S2MPG10_METER_LPF_DATA_CH2_1 = 0x79,
S2MPG10_METER_LPF_DATA_CH2_2 = 0x7A,
S2MPG10_METER_LPF_DATA_CH2_3 = 0x7B,
S2MPG10_METER_LPF_DATA_CH3_1 = 0x7C,
S2MPG10_METER_LPF_DATA_CH3_2 = 0x7D,
S2MPG10_METER_LPF_DATA_CH3_3 = 0x7E,
S2MPG10_METER_LPF_DATA_CH4_1 = 0x7F,
S2MPG10_METER_LPF_DATA_CH4_2 = 0x80,
S2MPG10_METER_LPF_DATA_CH4_3 = 0x81,
S2MPG10_METER_LPF_DATA_CH5_1 = 0x82,
S2MPG10_METER_LPF_DATA_CH5_2 = 0x83,
S2MPG10_METER_LPF_DATA_CH5_3 = 0x84,
S2MPG10_METER_LPF_DATA_CH6_1 = 0x85,
S2MPG10_METER_LPF_DATA_CH6_2 = 0x86,
S2MPG10_METER_LPF_DATA_CH6_3 = 0x87,
S2MPG10_METER_LPF_DATA_CH7_1 = 0x88,
S2MPG10_METER_LPF_DATA_CH7_2 = 0x89,
S2MPG10_METER_LPF_DATA_CH7_3 = 0x8A,
S2MPG10_METER_DSM_TRIM_OFFSET = 0xEE,
S2MPG10_METER_BUCK_METER_TRIM3 = 0xF1,
};
/* can be added */
#define S2MPG10_EVT0 0
#define S2MPG10_EVT1 1
/* S2MPG10 regulator ids */
enum S2MPG10_REGULATOR {
S2MPG10_LDO1,
S2MPG10_LDO2,
S2MPG10_LDO3,
S2MPG10_LDO4,
S2MPG10_LDO5,
S2MPG10_LDO6,
S2MPG10_LDO7,
S2MPG10_LDO8,
S2MPG10_LDO9,
S2MPG10_LDO10,
S2MPG10_LDO11,
S2MPG10_LDO12,
S2MPG10_LDO13,
S2MPG10_LDO14,
S2MPG10_LDO15,
S2MPG10_LDO16,
S2MPG10_LDO17,
S2MPG10_LDO18,
S2MPG10_LDO19,
S2MPG10_LDO20,
S2MPG10_LDO21,
S2MPG10_LDO22,
S2MPG10_LDO23,
S2MPG10_LDO24,
S2MPG10_LDO25,
S2MPG10_LDO26,
S2MPG10_LDO27,
S2MPG10_LDO28,
S2MPG10_LDO29,
S2MPG10_LDO30,
S2MPG10_LDO31,
S2MPG10_BUCK1,
S2MPG10_BUCK2,
S2MPG10_BUCK3,
S2MPG10_BUCK4,
S2MPG10_BUCK5,
S2MPG10_BUCK6,
S2MPG10_BUCK7,
S2MPG10_BUCK8,
S2MPG10_BUCK9,
S2MPG10_BUCK10,
S2MPG10_REGULATOR_MAX,
};
#define S2MPG10_BUCK_MAX 10
#define S2MPG10_LDO_MAX 31
/* Unit : uV */
/* BUCK1M~10M */
#define S2MPG10_REG_MIN1 200000
#define S2MPG10_REG_STEP1 6250
/* LDO 1M,7M,11M~13M,15M */
#define S2MPG10_REG_MIN2 300000
#define S2MPG10_REG_STEP2 12500
/* LDO 3M,5M,6M,8M,16M,17M,24M,28M */
#define S2MPG10_REG_MIN3 725000
#define S2MPG10_REG_STEP3 12500
/* LDO 2M,4M,9M,14M,18M~20M,23M,25M,29M~31M */
#define S2MPG10_REG_MIN4 700000
#define S2MPG10_REG_STEP4 25000
/* LDO 10M,21M,22M,26M,27M */
#define S2MPG10_REG_MIN5 1800000
#define S2MPG10_REG_STEP5 25000
#define S2MPG10_REG_N_VOLTAGES_64 0x40
#define S2MPG10_REG_N_VOLTAGES_128 0x80
#define S2MPG10_REG_N_VOLTAGES_256 0x100
#define S2MPG10_REG_ENABLE_MASK_1_0 (0x3 << 0)
#define S2MPG10_REG_ENABLE_MASK_3_2 (0x3 << 2)
#define S2MPG10_REG_ENABLE_MASK_4_3 (0x3 << 3)
#define S2MPG10_REG_ENABLE_MASK_5_4 (0x3 << 4)
#define S2MPG10_REG_ENABLE_MASK_7_6 (0x3 << 6)
#define S2MPG10_REG_ENABLE_MASK_7 (0x1 << 7)
#define S2MPG10_ENABLE_TIME_LDO 128
#define S2MPG10_ENABLE_TIME_BUCK 130
#define DCTRLSEL_HPM 0x0
#define DCTRLSEL_PWREN 0x1
#define DCTRLSEL_PWREN_TRG 0x2
#define DCTRLSEL_PWREN_MIF 0x3
#define DCTRLSEL_PWREN_MIF_TRG 0x4
#define DCTRLSEL_AP_ACTIVE_N 0x5
#define DCTRLSEL_AP_ACTIVE_N_TRG 0x6
#define DCTRLSEL_CPUCL1 0x7
#define DCTRLSEL_CPUCL1_PWREN 0x8
#define DCTRLSEL_CPUCL2 0x9
#define DCTRLSEL_CPUCL2_PWREN 0xa
#define DCTRLSEL_TPU_EN 0xb
#define DCTRLSEL_TPU_EN_AP_ACTIVE_N 0xc
/* S2MPG10_PM_SMPL_WARN_CTRL(0x16) */
#define S2MPG10_SMPL_WARN_LBDT_SHIFT 0
#define S2MPG10_SMPL_WARN_HYS_SHIFT 2
#define S2MPG10_SMPL_WARN_LVL_SHIFT 5
/* S2MPG10_PM_OCP_WARN */
#define S2MPG10_OCP_WARN_EN_SHIFT 7
#define S2MPG10_OCP_WARN_CNT_SHIFT 6
#define S2MPG10_OCP_WARN_DVS_MASK_SHIFT 5
#define S2MPG10_OCP_WARN_LVL_SHIFT 0
/* S2MPG10_METER_DSM_TRIM_OFFSET */
#define S2MPG10_METER_DSM_TRIM_LOW_SHIFT 0
#define S2MPG10_METER_DSM_TRIM_LOW_MASK (0x3f << S2MPG10_METER_DSM_TRIM_LOW_SHIFT)
/* S2MPG10_METER_BUCK_METER_TRIM3 */
#define S2MPG10_METER_DSM_TRIM_HIGH_SHIFT 6
#define S2MPG10_METER_DSM_TRIM_HIGH_MASK (0x3 << S2MPG10_METER_DSM_TRIM_HIGH_SHIFT)
/* w/a DSM Trim OFFSET default value */
#define S2MPG10_DSM_TRIM_OFFSET_THRESHOLD 99
#define S2MPG10_DSM_TRIM_OFFSET_MAX_VALUE 127
#define S2MPG10_DSM_TRIM_OFFSET_ADD_VALUE 28
enum s2mpg10_irq {
/* PMIC */
S2MPG10_IRQ_PWRONF_INT1,
S2MPG10_IRQ_PWRONR_INT1,
S2MPG10_IRQ_JIGONBF_INT1,
S2MPG10_IRQ_JIGONBR_INT1,
S2MPG10_IRQ_ACOKBF_INT1,
S2MPG10_IRQ_ACOKBR_INT1,
S2MPG10_IRQ_PWRON1S_INT1,
S2MPG10_IRQ_MRB_INT1,
S2MPG10_IRQ_RTC60S_INT2,
S2MPG10_IRQ_RTCA1_INT2,
S2MPG10_IRQ_RTCA0_INT2,
S2MPG10_IRQ_RTC1S_INT2,
S2MPG10_IRQ_WTSR_COLDRST_INT2,
S2MPG10_IRQ_WTSR_INT2,
S2MPG10_IRQ_WRST_INT2,
S2MPG10_IRQ_SMPL_INT2,
S2MPG10_IRQ_120C_INT3,
S2MPG10_IRQ_140C_INT3,
S2MPG10_IRQ_TSD_INT3,
S2MPG10_IRQ_PIF_TIMEOUT1_INT3,
S2MPG10_IRQ_PIF_TIMEOUT2_INT3,
S2MPG10_IRQ_SPD_PARITY_ERR_INT3,
S2MPG10_IRQ_SPD_ABNORMAL_STOP_INT3,
S2MPG10_IRQ_PMETER_OVERF_INT3,
S2MPG10_IRQ_OCP_B1M_INT4,
S2MPG10_IRQ_OCP_B2M_INT4,
S2MPG10_IRQ_OCP_B3M_INT4,
S2MPG10_IRQ_OCP_B4M_INT4,
S2MPG10_IRQ_OCP_B5M_INT4,
S2MPG10_IRQ_OCP_B6M_INT4,
S2MPG10_IRQ_OCP_B7M_INT4,
S2MPG10_IRQ_OCP_B8M_INT4,
S2MPG10_IRQ_OCP_B9M_INT5,
S2MPG10_IRQ_OCP_B10M_INT5,
S2MPG10_IRQ_WLWP_ACC_INT5,
S2MPG10_IRQ_PIF_TIMEOUT2_MIF_INT5,
S2MPG10_IRQ_SMPL_TIMEOUT_INT5,
S2MPG10_IRQ_WTSR_TIMEOUT_INT5,
S2MPG10_IRQ_SPD_SRP_PKT_RST_INT5,
S2MPG10_IRQ_PWR_WARN_CH1_INT6,
S2MPG10_IRQ_PWR_WARN_CH2_INT6,
S2MPG10_IRQ_PWR_WARN_CH3_INT6,
S2MPG10_IRQ_PWR_WARN_CH4_INT6,
S2MPG10_IRQ_PWR_WARN_CH5_INT6,
S2MPG10_IRQ_PWR_WARN_CH6_INT6,
S2MPG10_IRQ_PWR_WARN_CH7_INT6,
S2MPG10_IRQ_PWR_WARN_CH8_INT6,
S2MPG10_IRQ_NR,
};
#endif /* __LINUX_MFD_S2MPG10_REGISTER_H */