| // Copyright 2019 Google LLC |
| // |
| // This source code is licensed under the BSD-style license found in the |
| // LICENSE file in the root directory of this source tree. |
| |
| $assert BATCH_TILE % 4 == 0 |
| $assert BATCH_TILE >= 4 |
| $assert DIV_ALGO in ["div", "nr2fma", "nr2recps", "nr1recps1fma"] |
| $ABC = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ" |
| $VMULADDQ_F32 = "vfmaq_f32" if FMA else "vmlaq_f32" |
| $VMULSUBQ_F32 = "vfmsq_f32" if FMA else "vmlsq_f32" |
| #include <assert.h> |
| |
| #include <arm_neon.h> |
| |
| #include <xnnpack/common.h> |
| #include <xnnpack/vunary.h> |
| |
| |
| extern XNN_INTERNAL const float xnn_table_exp2minus_k_over_64[64]; |
| |
| $PARAMS_STRUCT = "neonfma_rr1_lut64_p2" if FMA else "neon_rr2_lut64_p2" |
| void xnn_f32_vsigmoid_ukernel__${"neonfma" if FMA else "neon"}_rr${1 if FMA else 2}_lut64_p2_${DIV_ALGO}_x${BATCH_TILE}( |
| size_t n, |
| const float* x, |
| float* y, |
| const union xnn_f32_sigmoid_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS |
| { |
| assert(n % sizeof(float) == 0); |
| |
| const float32x4_t vmagic_bias = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.magic_bias); |
| const float32x4_t vminus_log2e = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.minus_log2e); |
| const int32x4_t vindex_mask = vmovq_n_s32(INT32_C(0x3F)); |
| $if FMA: |
| const float32x4_t vln2 = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.ln2); |
| $else: |
| const float32x4_t vln2_hi = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.ln2_hi); |
| const float32x4_t vln2_lo = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.ln2_lo); |
| const float32x4_t vc2 = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.c2); |
| const float32x4_t vone = vmovq_n_f32(1.0f); |
| const float32x4_t vdenorm_cutoff = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.denorm_cutoff); |
| |
| $if BATCH_TILE > 4: |
| for (; n >= ${BATCH_TILE} * sizeof(float); n -= ${BATCH_TILE} * sizeof(float)) { |
| $for N in range(0, BATCH_TILE, 4): |
| const float32x4_t vx${ABC[N:N+4]} = vld1q_f32(x); x += 4; |
| |
| $for N in range(0, BATCH_TILE, 4): |
| const float32x4_t vz${ABC[N:N+4]} = vabsq_f32(vx${ABC[N:N+4]}); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| float32x4_t vn${ABC[N:N+4]} = ${VMULADDQ_F32}(vmagic_bias, vz${ABC[N:N+4]}, vminus_log2e); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| const int32x4_t ve${ABC[N:N+4]} = vshlq_n_s32(vreinterpretq_s32_f32(vn${ABC[N:N+4]}), 17); |
| |
| // Use bits 0:6 bits of n, as integer, as an index for table lookup of l := 2**(n % 64). |
| $for N in range(0, BATCH_TILE, 4): |
| const uint64x2_t vidx${ABC[N:N+4]} = vreinterpretq_u64_s32(vandq_s32(vreinterpretq_s32_f32(vn${ABC[N:N+4]}), vindex_mask)); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| const uint64_t vidx${ABC[N:N+2]} = vgetq_lane_u64(vidx${ABC[N:N+4]}, 0); |
| const uint64_t vidx${ABC[N+2:N+4]} = vgetq_lane_u64(vidx${ABC[N:N+4]}, 1); |
| float32x2_t vl${ABC[N:N+2]} = vld1_dup_f32(&xnn_table_exp2minus_k_over_64[(uint32_t) vidx${ABC[N:N+2]}]); |
| float32x2_t vl${ABC[N+2:N+4]} = vld1_dup_f32(&xnn_table_exp2minus_k_over_64[(uint32_t) vidx${ABC[N+2:N+4]}]); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| vl${ABC[N:N+2]} = vld1_lane_f32(&xnn_table_exp2minus_k_over_64[(uint32_t) (vidx${ABC[N:N+2]} >> 32)], vl${ABC[N:N+2]}, 1); |
| vl${ABC[N+2:N+4]} = vld1_lane_f32(&xnn_table_exp2minus_k_over_64[(uint32_t) (vidx${ABC[N+2:N+4]} >> 32)], vl${ABC[N+2:N+4]}, 1); |
| const float32x4_t vl${ABC[N:N+4]} = vcombine_f32(vl${ABC[N:N+2]}, vl${ABC[N+2:N+4]}); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| const float32x4_t vs${ABC[N:N+4]} = vreinterpretq_f32_s32(vaddq_s32(vreinterpretq_s32_f32(vl${ABC[N:N+4]}), ve${ABC[N:N+4]})); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| vn${ABC[N:N+4]} = vsubq_f32(vn${ABC[N:N+4]}, vmagic_bias); |
| |
| $if FMA: |
| $for N in range(0, BATCH_TILE, 4): |
| float32x4_t vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vz${ABC[N:N+4]}, vn${ABC[N:N+4]}, vln2); |
| $else: |
| $for N in range(0, BATCH_TILE, 4): |
| float32x4_t vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vz${ABC[N:N+4]}, vn${ABC[N:N+4]}, vln2_hi); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vt${ABC[N:N+4]}, vn${ABC[N:N+4]}, vln2_lo); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| float32x4_t vp${ABC[N:N+4]} = vmulq_f32(vt${ABC[N:N+4]}, vc2); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| vp${ABC[N:N+4]} = ${VMULSUBQ_F32}(vt${ABC[N:N+4]}, vp${ABC[N:N+4]}, vt${ABC[N:N+4]}); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| const float32x4_t vy${ABC[N:N+4]} = ${VMULSUBQ_F32}(vs${ABC[N:N+4]}, vs${ABC[N:N+4]}, vp${ABC[N:N+4]}); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| const float32x4_t vd${ABC[N:N+4]} = vaddq_f32(vy${ABC[N:N+4]}, vone); |
| |
| $if DIV_ALGO == "div": |
| $for N in range(0, BATCH_TILE, 4): |
| float32x4_t vf${ABC[N:N+4]} = vdivq_f32(vy${ABC[N:N+4]}, vd${ABC[N:N+4]}); |
| $else: |
| $for N in range(0, BATCH_TILE, 4): |
| float32x4_t vr${ABC[N:N+4]} = vrecpeq_f32(vd${ABC[N:N+4]}); |
| |
| $if DIV_ALGO == "nr2fma": |
| $for N in range(0, BATCH_TILE, 4): |
| vr${ABC[N:N+4]} = vfmaq_f32(vr${ABC[N:N+4]}, vr${ABC[N:N+4]}, vfmsq_f32(vone, vr${ABC[N:N+4]}, vd${ABC[N:N+4]})); |
| $else: |
| $for N in range(0, BATCH_TILE, 4): |
| vr${ABC[N:N+4]} = vmulq_f32(vr${ABC[N:N+4]}, vrecpsq_f32(vr${ABC[N:N+4]}, vd${ABC[N:N+4]})); |
| |
| $if DIV_ALGO == "nr2recps": |
| $for N in range(0, BATCH_TILE, 4): |
| vr${ABC[N:N+4]} = vmulq_f32(vr${ABC[N:N+4]}, vrecpsq_f32(vr${ABC[N:N+4]}, vd${ABC[N:N+4]})); |
| $else: |
| $for N in range(0, BATCH_TILE, 4): |
| vr${ABC[N:N+4]} = vfmaq_f32(vr${ABC[N:N+4]}, vr${ABC[N:N+4]}, vfmsq_f32(vone, vr${ABC[N:N+4]}, vd${ABC[N:N+4]})); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| float32x4_t vf${ABC[N:N+4]} = vmulq_f32(vy${ABC[N:N+4]}, vr${ABC[N:N+4]}); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| vf${ABC[N:N+4]} = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf${ABC[N:N+4]}), vcagtq_f32(vx${ABC[N:N+4]}, vdenorm_cutoff))); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| const uint32x4_t vm${ABC[N:N+4]} = vcltq_f32(vx${ABC[N:N+4]}, vmovq_n_f32(0.0f)); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| vf${ABC[N:N+4]} = vbslq_f32(vm${ABC[N:N+4]}, vf${ABC[N:N+4]}, vsubq_f32(vone, vf${ABC[N:N+4]})); |
| |
| $for N in range(0, BATCH_TILE, 4): |
| vst1q_f32(y, vf${ABC[N:N+4]}); y += 4; |
| } |
| for (; n >= 4 * sizeof(float); n -= 4 * sizeof(float)) { |
| const float32x4_t vx = vld1q_f32(x); x += 4; |
| |
| const float32x4_t vz = vabsq_f32(vx); |
| |
| float32x4_t vn = ${VMULADDQ_F32}(vmagic_bias, vz, vminus_log2e); |
| const int32x4_t ve = vshlq_n_s32(vreinterpretq_s32_f32(vn), 17); |
| |
| const uint64x2_t vidx = vreinterpretq_u64_s32(vandq_s32(vreinterpretq_s32_f32(vn), vindex_mask)); |
| const uint64_t vidx_lo = vgetq_lane_u64(vidx, 0); |
| const uint64_t vidx_hi = vgetq_lane_u64(vidx, 1); |
| float32x2_t vl_lo = vld1_dup_f32(&xnn_table_exp2minus_k_over_64[(uint32_t) vidx_lo]); |
| float32x2_t vl_hi = vld1_dup_f32(&xnn_table_exp2minus_k_over_64[(uint32_t) vidx_hi]); |
| vl_lo = vld1_lane_f32(&xnn_table_exp2minus_k_over_64[(uint32_t) (vidx_lo >> 32)], vl_lo, 1); |
| vl_hi = vld1_lane_f32(&xnn_table_exp2minus_k_over_64[(uint32_t) (vidx_hi >> 32)], vl_hi, 1); |
| const float32x4_t vl = vcombine_f32(vl_lo, vl_hi); |
| |
| const float32x4_t vs = vreinterpretq_f32_s32(vaddq_s32(vreinterpretq_s32_f32(vl), ve)); |
| vn = vsubq_f32(vn, vmagic_bias); |
| $if FMA: |
| float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vln2); |
| $else: |
| float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vln2_hi); |
| vt = ${VMULADDQ_F32}(vt, vn, vln2_lo); |
| |
| float32x4_t vp = vmulq_f32(vt, vc2); |
| vp = ${VMULSUBQ_F32}(vt, vp, vt); |
| |
| const float32x4_t vy = ${VMULSUBQ_F32}(vs, vs, vp); |
| const float32x4_t vd = vaddq_f32(vy, vone); |
| |
| $if DIV_ALGO == "div": |
| float32x4_t vf = vdivq_f32(vy, vd); |
| $else: |
| float32x4_t vr = vrecpeq_f32(vd); |
| $if DIV_ALGO == "nr2fma": |
| vr = vfmaq_f32(vr, vr, vfmsq_f32(vone, vr, vd)); |
| $else: |
| vr = vmulq_f32(vr, vrecpsq_f32(vr, vd)); |
| $if DIV_ALGO == "nr2recps": |
| vr = vmulq_f32(vr, vrecpsq_f32(vr, vd)); |
| $else: |
| vr = vfmaq_f32(vr, vr, vfmsq_f32(vone, vr, vd)); |
| |
| float32x4_t vf = vmulq_f32(vy, vr); |
| vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcagtq_f32(vx, vdenorm_cutoff))); |
| const uint32x4_t vm = vcltq_f32(vx, vmovq_n_f32(0.0f)); |
| vf = vbslq_f32(vm, vf, vsubq_f32(vone, vf)); |
| |
| vst1q_f32(y, vf); y += 4; |
| } |
| if XNN_UNLIKELY(n != 0) { |
| const float32x4_t vx = vld1q_f32(x); |
| |
| const float32x4_t vz = vabsq_f32(vx); |
| |
| float32x4_t vn = ${VMULADDQ_F32}(vmagic_bias, vz, vminus_log2e); |
| const int32x4_t ve = vshlq_n_s32(vreinterpretq_s32_f32(vn), 17); |
| |
| const uint64x2_t vidx = vreinterpretq_u64_s32(vandq_s32(vreinterpretq_s32_f32(vn), vindex_mask)); |
| const uint64_t vidx_lo = vgetq_lane_u64(vidx, 0); |
| const uint64_t vidx_hi = vgetq_lane_u64(vidx, 1); |
| float32x2_t vl_lo = vld1_dup_f32(&xnn_table_exp2minus_k_over_64[(uint32_t) vidx_lo]); |
| float32x2_t vl_hi = vld1_dup_f32(&xnn_table_exp2minus_k_over_64[(uint32_t) vidx_hi]); |
| vl_lo = vld1_lane_f32(&xnn_table_exp2minus_k_over_64[(uint32_t) (vidx_lo >> 32)], vl_lo, 1); |
| vl_hi = vld1_lane_f32(&xnn_table_exp2minus_k_over_64[(uint32_t) (vidx_hi >> 32)], vl_hi, 1); |
| const float32x4_t vl = vcombine_f32(vl_lo, vl_hi); |
| |
| const float32x4_t vs = vreinterpretq_f32_s32(vaddq_s32(vreinterpretq_s32_f32(vl), ve)); |
| vn = vsubq_f32(vn, vmagic_bias); |
| $if FMA: |
| float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vln2); |
| $else: |
| float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vln2_hi); |
| vt = ${VMULADDQ_F32}(vt, vn, vln2_lo); |
| |
| float32x4_t vp = vmulq_f32(vt, vc2); |
| vp = ${VMULSUBQ_F32}(vt, vp, vt); |
| |
| const float32x4_t vy = ${VMULSUBQ_F32}(vs, vs, vp); |
| const float32x4_t vd = vaddq_f32(vy, vone); |
| |
| $if DIV_ALGO == "div": |
| float32x4_t vf = vdivq_f32(vy, vd); |
| $else: |
| float32x4_t vr = vrecpeq_f32(vd); |
| $if DIV_ALGO == "nr2fma": |
| vr = vfmaq_f32(vr, vr, vfmsq_f32(vone, vr, vd)); |
| $else: |
| vr = vmulq_f32(vr, vrecpsq_f32(vr, vd)); |
| $if DIV_ALGO == "nr2recps": |
| vr = vmulq_f32(vr, vrecpsq_f32(vr, vd)); |
| $else: |
| vr = vfmaq_f32(vr, vr, vfmsq_f32(vone, vr, vd)); |
| |
| float32x4_t vf = vmulq_f32(vy, vr); |
| vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcagtq_f32(vx, vdenorm_cutoff))); |
| const uint32x4_t vm = vcltq_f32(vx, vmovq_n_f32(0.0f)); |
| vf = vbslq_f32(vm, vf, vsubq_f32(vone, vf)); |
| |
| float32x2_t vf_lo = vget_low_f32(vf); |
| if (n & (2 * sizeof(float))) { |
| vst1_f32(y, vf_lo); y += 2; |
| vf_lo = vget_high_f32(vf); |
| } |
| if (n & (1 * sizeof(float))) { |
| vst1_lane_f32(y, vf_lo, 0); |
| } |
| } |
| } |