Check in LLVM r95781.
diff --git a/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll b/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll
new file mode 100644
index 0000000..a0235f7
--- /dev/null
+++ b/test/CodeGen/ARM/2006-11-10-CycleInDAG.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=arm -mattr=+v6
+
+%struct.layer_data = type { i32, [2048 x i8], i8*, [16 x i8], i32, i8*, i32, i32, [64 x i32], [64 x i32], [64 x i32], [64 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [12 x [64 x i16]] }
+@ld = external global %struct.layer_data* ; <%struct.layer_data**> [#uses=1]
+
+define void @main() {
+entry:
+ br i1 false, label %bb169.i, label %cond_true11
+
+bb169.i: ; preds = %entry
+ ret void
+
+cond_true11: ; preds = %entry
+ %tmp.i32 = load %struct.layer_data** @ld ; <%struct.layer_data*> [#uses=2]
+ %tmp3.i35 = getelementptr %struct.layer_data* %tmp.i32, i32 0, i32 1, i32 2048; <i8*> [#uses=2]
+ %tmp.i36 = getelementptr %struct.layer_data* %tmp.i32, i32 0, i32 2 ; <i8**> [#uses=1]
+ store i8* %tmp3.i35, i8** %tmp.i36
+ store i8* %tmp3.i35, i8** null
+ ret void
+}
diff --git a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
new file mode 100644
index 0000000..81483cb4
--- /dev/null
+++ b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
@@ -0,0 +1,103 @@
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2
+
+@quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
+@dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
+@A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1]
+
+define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) {
+entry:
+ %predicted_block = alloca [4 x [4 x i32]], align 4 ; <[4 x [4 x i32]]*> [#uses=1]
+ br label %cond_next489
+
+cond_next489: ; preds = %cond_false, %bb471
+ %j.7.in = load i8* null ; <i8> [#uses=1]
+ %i.8.in = load i8* null ; <i8> [#uses=1]
+ %i.8 = zext i8 %i.8.in to i32 ; <i32> [#uses=4]
+ %j.7 = zext i8 %j.7.in to i32 ; <i32> [#uses=4]
+ %tmp495 = getelementptr [4 x [4 x i32]]* %predicted_block, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=2]
+ %tmp496 = load i32* %tmp495 ; <i32> [#uses=2]
+ %tmp502 = load i32* null ; <i32> [#uses=1]
+ %tmp542 = getelementptr [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1]
+ %tmp543 = load i32* %tmp542 ; <i32> [#uses=1]
+ %tmp548 = ashr i32 0, 0 ; <i32> [#uses=3]
+ %tmp561 = sub i32 0, %tmp496 ; <i32> [#uses=3]
+ %abscond563 = icmp sgt i32 %tmp561, -1 ; <i1> [#uses=1]
+ %abs564 = select i1 %abscond563, i32 %tmp561, i32 0 ; <i32> [#uses=1]
+ %tmp572 = mul i32 %abs564, %tmp543 ; <i32> [#uses=1]
+ %tmp574 = add i32 %tmp572, 0 ; <i32> [#uses=1]
+ %tmp576 = ashr i32 %tmp574, 0 ; <i32> [#uses=7]
+ %tmp579 = icmp eq i32 %tmp548, %tmp576 ; <i1> [#uses=1]
+ br i1 %tmp579, label %bb712, label %cond_next589
+
+cond_next589: ; preds = %cond_next489
+ %tmp605 = getelementptr [6 x [4 x [4 x i32]]]* @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1]
+ %tmp606 = load i32* %tmp605 ; <i32> [#uses=1]
+ %tmp612 = load i32* null ; <i32> [#uses=1]
+ %tmp629 = load i32* null ; <i32> [#uses=1]
+ %tmp629a = sitofp i32 %tmp629 to double ; <double> [#uses=1]
+ %tmp631 = fmul double %tmp629a, 0.000000e+00 ; <double> [#uses=1]
+ %tmp632 = fadd double 0.000000e+00, %tmp631 ; <double> [#uses=1]
+ %tmp642 = call fastcc i32 @sign( i32 %tmp576, i32 %tmp561 ) ; <i32> [#uses=1]
+ %tmp650 = mul i32 %tmp606, %tmp642 ; <i32> [#uses=1]
+ %tmp656 = mul i32 %tmp650, %tmp612 ; <i32> [#uses=1]
+ %tmp658 = shl i32 %tmp656, 0 ; <i32> [#uses=1]
+ %tmp659 = ashr i32 %tmp658, 6 ; <i32> [#uses=1]
+ %tmp660 = sub i32 0, %tmp659 ; <i32> [#uses=1]
+ %tmp666 = sub i32 %tmp660, %tmp496 ; <i32> [#uses=1]
+ %tmp667 = sitofp i32 %tmp666 to double ; <double> [#uses=2]
+ call void @levrun_linfo_inter( i32 %tmp576, i32 0, i32* null, i32* null )
+ %tmp671 = fmul double %tmp667, %tmp667 ; <double> [#uses=1]
+ %tmp675 = fadd double %tmp671, 0.000000e+00 ; <double> [#uses=1]
+ %tmp678 = fcmp oeq double %tmp632, %tmp675 ; <i1> [#uses=1]
+ br i1 %tmp678, label %cond_true679, label %cond_false693
+
+cond_true679: ; preds = %cond_next589
+ %abscond681 = icmp sgt i32 %tmp548, -1 ; <i1> [#uses=1]
+ %abs682 = select i1 %abscond681, i32 %tmp548, i32 0 ; <i32> [#uses=1]
+ %abscond684 = icmp sgt i32 %tmp576, -1 ; <i1> [#uses=1]
+ %abs685 = select i1 %abscond684, i32 %tmp576, i32 0 ; <i32> [#uses=1]
+ %tmp686 = icmp slt i32 %abs682, %abs685 ; <i1> [#uses=1]
+ br i1 %tmp686, label %cond_next702, label %cond_false689
+
+cond_false689: ; preds = %cond_true679
+ %tmp739 = icmp eq i32 %tmp576, 0 ; <i1> [#uses=1]
+ br i1 %tmp579, label %bb737, label %cond_false708
+
+cond_false693: ; preds = %cond_next589
+ ret i32 0
+
+cond_next702: ; preds = %cond_true679
+ ret i32 0
+
+cond_false708: ; preds = %cond_false689
+ ret i32 0
+
+bb712: ; preds = %cond_next489
+ ret i32 0
+
+bb737: ; preds = %cond_false689
+ br i1 %tmp739, label %cond_next791, label %cond_true740
+
+cond_true740: ; preds = %bb737
+ %tmp761 = call fastcc i32 @sign( i32 %tmp576, i32 0 ) ; <i32> [#uses=1]
+ %tmp780 = load i32* null ; <i32> [#uses=1]
+ %tmp785 = getelementptr [4 x [4 x i32]]* @A, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1]
+ %tmp786 = load i32* %tmp785 ; <i32> [#uses=1]
+ %tmp781 = mul i32 %tmp780, %tmp761 ; <i32> [#uses=1]
+ %tmp787 = mul i32 %tmp781, %tmp786 ; <i32> [#uses=1]
+ %tmp789 = shl i32 %tmp787, 0 ; <i32> [#uses=1]
+ %tmp790 = ashr i32 %tmp789, 6 ; <i32> [#uses=1]
+ br label %cond_next791
+
+cond_next791: ; preds = %cond_true740, %bb737
+ %ilev.1 = phi i32 [ %tmp790, %cond_true740 ], [ 0, %bb737 ] ; <i32> [#uses=1]
+ %tmp796 = load i32* %tmp495 ; <i32> [#uses=1]
+ %tmp798 = add i32 %tmp796, %ilev.1 ; <i32> [#uses=1]
+ %tmp812 = mul i32 0, %tmp502 ; <i32> [#uses=0]
+ %tmp818 = call fastcc i32 @sign( i32 0, i32 %tmp798 ) ; <i32> [#uses=0]
+ unreachable
+}
+
+declare i32 @sign(i32, i32)
+
+declare void @levrun_linfo_inter(i32, i32, i32*, i32*)
diff --git a/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll b/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll
new file mode 100644
index 0000000..83b26d3
--- /dev/null
+++ b/test/CodeGen/ARM/2007-03-07-CombinerCrash.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
+
+define fastcc i8* @read_sleb128(i8* %p, i32* %val) {
+ br label %bb
+
+bb: ; preds = %bb, %0
+ %p_addr.0 = getelementptr i8* %p, i32 0 ; <i8*> [#uses=1]
+ %tmp2 = load i8* %p_addr.0 ; <i8> [#uses=2]
+ %tmp4.rec = add i32 0, 1 ; <i32> [#uses=1]
+ %tmp4 = getelementptr i8* %p, i32 %tmp4.rec ; <i8*> [#uses=1]
+ %tmp56 = zext i8 %tmp2 to i32 ; <i32> [#uses=1]
+ %tmp7 = and i32 %tmp56, 127 ; <i32> [#uses=1]
+ %tmp9 = shl i32 %tmp7, 0 ; <i32> [#uses=1]
+ %tmp11 = or i32 %tmp9, 0 ; <i32> [#uses=1]
+ icmp slt i8 %tmp2, 0 ; <i1>:1 [#uses=1]
+ br i1 %1, label %bb, label %cond_next28
+
+cond_next28: ; preds = %bb
+ store i32 %tmp11, i32* %val
+ ret i8* %tmp4
+}
diff --git a/test/CodeGen/ARM/2007-03-13-InstrSched.ll b/test/CodeGen/ARM/2007-03-13-InstrSched.ll
new file mode 100644
index 0000000..33f935e
--- /dev/null
+++ b/test/CodeGen/ARM/2007-03-13-InstrSched.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \
+; RUN: -mattr=+v6 | grep r9
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \
+; RUN: -mattr=+v6 -arm-reserve-r9 -ifcvt-limit=0 -stats |& grep asm-printer
+; | grep 35
+
+define void @test(i32 %tmp56222, i32 %tmp36224, i32 %tmp46223, i32 %i.0196.0.ph, i32 %tmp8, i32* %tmp1011, i32** %tmp1, i32* %d2.1.out, i32* %d3.1.out, i32* %d0.1.out, i32* %d1.1.out) {
+newFuncRoot:
+ br label %bb74
+
+bb78.exitStub: ; preds = %bb74
+ store i32 %d2.1, i32* %d2.1.out
+ store i32 %d3.1, i32* %d3.1.out
+ store i32 %d0.1, i32* %d0.1.out
+ store i32 %d1.1, i32* %d1.1.out
+ ret void
+
+bb74: ; preds = %bb26, %newFuncRoot
+ %fp.1.rec = phi i32 [ 0, %newFuncRoot ], [ %tmp71.rec, %bb26 ] ; <i32> [#uses=3]
+ %fm.1.in = phi i32* [ %tmp71, %bb26 ], [ %tmp1011, %newFuncRoot ] ; <i32*> [#uses=1]
+ %d0.1 = phi i32 [ %tmp44, %bb26 ], [ 8192, %newFuncRoot ] ; <i32> [#uses=2]
+ %d1.1 = phi i32 [ %tmp54, %bb26 ], [ 8192, %newFuncRoot ] ; <i32> [#uses=2]
+ %d2.1 = phi i32 [ %tmp64, %bb26 ], [ 8192, %newFuncRoot ] ; <i32> [#uses=2]
+ %d3.1 = phi i32 [ %tmp69, %bb26 ], [ 8192, %newFuncRoot ] ; <i32> [#uses=2]
+ %fm.1 = load i32* %fm.1.in ; <i32> [#uses=4]
+ icmp eq i32 %fp.1.rec, %tmp8 ; <i1>:0 [#uses=1]
+ br i1 %0, label %bb78.exitStub, label %bb26
+
+bb26: ; preds = %bb74
+ %tmp28 = getelementptr i32** %tmp1, i32 %fp.1.rec ; <i32**> [#uses=1]
+ %tmp30 = load i32** %tmp28 ; <i32*> [#uses=4]
+ %tmp33 = getelementptr i32* %tmp30, i32 %i.0196.0.ph ; <i32*> [#uses=1]
+ %tmp34 = load i32* %tmp33 ; <i32> [#uses=1]
+ %tmp38 = getelementptr i32* %tmp30, i32 %tmp36224 ; <i32*> [#uses=1]
+ %tmp39 = load i32* %tmp38 ; <i32> [#uses=1]
+ %tmp42 = mul i32 %tmp34, %fm.1 ; <i32> [#uses=1]
+ %tmp44 = add i32 %tmp42, %d0.1 ; <i32> [#uses=1]
+ %tmp48 = getelementptr i32* %tmp30, i32 %tmp46223 ; <i32*> [#uses=1]
+ %tmp49 = load i32* %tmp48 ; <i32> [#uses=1]
+ %tmp52 = mul i32 %tmp39, %fm.1 ; <i32> [#uses=1]
+ %tmp54 = add i32 %tmp52, %d1.1 ; <i32> [#uses=1]
+ %tmp58 = getelementptr i32* %tmp30, i32 %tmp56222 ; <i32*> [#uses=1]
+ %tmp59 = load i32* %tmp58 ; <i32> [#uses=1]
+ %tmp62 = mul i32 %tmp49, %fm.1 ; <i32> [#uses=1]
+ %tmp64 = add i32 %tmp62, %d2.1 ; <i32> [#uses=1]
+ %tmp67 = mul i32 %tmp59, %fm.1 ; <i32> [#uses=1]
+ %tmp69 = add i32 %tmp67, %d3.1 ; <i32> [#uses=1]
+ %tmp71.rec = add i32 %fp.1.rec, 1 ; <i32> [#uses=2]
+ %tmp71 = getelementptr i32* %tmp1011, i32 %tmp71.rec ; <i32*> [#uses=1]
+ br label %bb74
+}
diff --git a/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll b/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll
new file mode 100644
index 0000000..b0953dc
--- /dev/null
+++ b/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll
@@ -0,0 +1,96 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; PR1257
+
+ %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 }
+ %struct.arm_stack_offsets = type { i32, i32, i32, i32, i32 }
+ %struct.c_arg_info = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i8 }
+ %struct.c_language_function = type { %struct.stmt_tree_s }
+ %struct.c_switch = type opaque
+ %struct.eh_status = type opaque
+ %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }
+ %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+ %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 }
+ %struct.ht_identifier = type { i8*, i32, i32 }
+ %struct.initial_value_struct = type opaque
+ %struct.lang_decl = type { i8 }
+ %struct.language_function = type { %struct.c_language_function, %struct.tree_node*, %struct.tree_node*, %struct.c_switch*, %struct.c_arg_info*, i32, i32, i32, i32 }
+ %struct.location_t = type { i8*, i32 }
+ %struct.machine_function = type { %struct.rtx_def*, i32, i32, i32, %struct.arm_stack_offsets, i32, i32, i32, [14 x %struct.rtx_def*] }
+ %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }
+ %struct.rtx_def = type { i16, i8, i8, %struct.u }
+ %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
+ %struct.stmt_tree_s = type { %struct.tree_node*, i32 }
+ %struct.temp_slot = type opaque
+ %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 }
+ %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_decl_u1 = type { i64 }
+ %struct.tree_decl_u2 = type { %struct.function* }
+ %struct.tree_identifier = type { %struct.tree_common, %struct.ht_identifier }
+ %struct.tree_node = type { %struct.tree_decl }
+ %struct.u = type { [1 x i64] }
+ %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+ %struct.varasm_status = type opaque
+ %struct.varray_head_tag = type opaque
+ %union.tree_ann_d = type opaque
+
+
+define void @declspecs_add_type(i32 %spec.1) {
+entry:
+ %spec.1961 = zext i32 %spec.1 to i64 ; <i64> [#uses=1]
+ %spec.1961.adj = shl i64 %spec.1961, 32 ; <i64> [#uses=1]
+ %spec.1961.adj.ins = or i64 %spec.1961.adj, 0 ; <i64> [#uses=2]
+ %tmp10959 = lshr i64 %spec.1961.adj.ins, 32 ; <i64> [#uses=2]
+ %tmp1920 = inttoptr i64 %tmp10959 to %struct.tree_common* ; <%struct.tree_common*> [#uses=1]
+ %tmp21 = getelementptr %struct.tree_common* %tmp1920, i32 0, i32 3 ; <i8*> [#uses=1]
+ %tmp2122 = bitcast i8* %tmp21 to i32* ; <i32*> [#uses=1]
+ br i1 false, label %cond_next53, label %cond_true
+
+cond_true: ; preds = %entry
+ ret void
+
+cond_next53: ; preds = %entry
+ br i1 false, label %cond_true63, label %cond_next689
+
+cond_true63: ; preds = %cond_next53
+ ret void
+
+cond_next689: ; preds = %cond_next53
+ br i1 false, label %cond_false841, label %bb743
+
+bb743: ; preds = %cond_next689
+ ret void
+
+cond_false841: ; preds = %cond_next689
+ br i1 false, label %cond_true851, label %cond_true918
+
+cond_true851: ; preds = %cond_false841
+ tail call void @lookup_name( )
+ br i1 false, label %bb866, label %cond_next856
+
+cond_next856: ; preds = %cond_true851
+ ret void
+
+bb866: ; preds = %cond_true851
+ %tmp874 = load i32* %tmp2122 ; <i32> [#uses=1]
+ %tmp876877 = trunc i32 %tmp874 to i8 ; <i8> [#uses=1]
+ icmp eq i8 %tmp876877, 1 ; <i1>:0 [#uses=1]
+ br i1 %0, label %cond_next881, label %cond_true878
+
+cond_true878: ; preds = %bb866
+ unreachable
+
+cond_next881: ; preds = %bb866
+ %tmp884885 = inttoptr i64 %tmp10959 to %struct.tree_identifier* ; <%struct.tree_identifier*> [#uses=1]
+ %tmp887 = getelementptr %struct.tree_identifier* %tmp884885, i32 0, i32 1, i32 0 ; <i8**> [#uses=1]
+ %tmp888 = load i8** %tmp887 ; <i8*> [#uses=1]
+ tail call void (i32, ...)* @error( i32 undef, i8* %tmp888 )
+ ret void
+
+cond_true918: ; preds = %cond_false841
+ %tmp920957 = trunc i64 %spec.1961.adj.ins to i32 ; <i32> [#uses=0]
+ ret void
+}
+
+declare void @error(i32, ...)
+
+declare void @lookup_name()
diff --git a/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll b/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll
new file mode 100644
index 0000000..d741112
--- /dev/null
+++ b/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll
@@ -0,0 +1,947 @@
+; RUN: llc < %s -march=arm
+; PR1266
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "arm-linux-gnueabi"
+ %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 }
+ %struct.FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct.FILE*, i32, i32, i32, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i32, [52 x i8] }
+ %struct.VEC_edge = type { i32, i32, [1 x %struct.edge_def*] }
+ %struct.VEC_tree = type { i32, i32, [1 x %struct.tree_node*] }
+ %struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 }
+ %struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
+ %struct.addr_diff_vec_flags = type { i8, i8, i8, i8 }
+ %struct.arm_stack_offsets = type { i32, i32, i32, i32, i32 }
+ %struct.attribute_spec = type { i8*, i32, i32, i8, i8, i8, %struct.tree_node* (%struct.tree_node**, %struct.tree_node*, %struct.tree_node*, i32, i8*)* }
+ %struct.basic_block_def = type { %struct.rtx_def*, %struct.rtx_def*, %struct.tree_node*, %struct.VEC_edge*, %struct.VEC_edge*, %struct.bitmap_head_def*, %struct.bitmap_head_def*, i8*, %struct.loop*, [2 x %struct.et_node*], %struct.basic_block_def*, %struct.basic_block_def*, %struct.reorder_block_def*, %struct.bb_ann_d*, i64, i32, i32, i32, i32 }
+ %struct.bb_ann_d = type { %struct.tree_node*, i8, %struct.edge_prediction* }
+ %struct.bitmap_element_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, [4 x i32] }
+ %struct.bitmap_head_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, %struct.bitmap_obstack* }
+ %struct.bitmap_obstack = type { %struct.bitmap_element_def*, %struct.bitmap_head_def*, %struct.obstack }
+ %struct.cgraph_edge = type { %struct.cgraph_node*, %struct.cgraph_node*, %struct.cgraph_edge*, %struct.cgraph_edge*, %struct.cgraph_edge*, %struct.cgraph_edge*, %struct.tree_node*, i8*, i8* }
+ %struct.cgraph_global_info = type { %struct.cgraph_node*, i32, i8 }
+ %struct.cgraph_local_info = type { i32, i8, i8, i8, i8, i8, i8, i8 }
+ %struct.cgraph_node = type { %struct.tree_node*, %struct.cgraph_edge*, %struct.cgraph_edge*, %struct.cgraph_node*, %struct.cgraph_node*, %struct.cgraph_node*, %struct.cgraph_node*, %struct.cgraph_node*, %struct.cgraph_node*, %struct.cgraph_node*, i8*, %struct.cgraph_local_info, %struct.cgraph_global_info, %struct.cgraph_rtl_info, i32, i8, i8, i8, i8, i8 }
+ %struct.cgraph_rtl_info = type { i32, i8, i8 }
+ %struct.cl_perfunc_opts = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.cselib_val_struct = type opaque
+ %struct.dataflow_d = type { %struct.varray_head_tag*, [2 x %struct.tree_node*] }
+ %struct.def_operand_ptr = type { %struct.tree_node** }
+ %struct.def_optype_d = type { i32, [1 x %struct.def_operand_ptr] }
+ %struct.diagnostic_context = type { %struct.pretty_printer*, [8 x i32], i8, i8, i8, void (%struct.diagnostic_context*, %struct.diagnostic_info*)*, void (%struct.diagnostic_context*, %struct.diagnostic_info*)*, void (i8*, i8**)*, %struct.tree_node*, i32, i32 }
+ %struct.diagnostic_info = type { %struct.text_info, %struct.location_t, i32 }
+ %struct.die_struct = type opaque
+ %struct.edge_def = type { %struct.basic_block_def*, %struct.basic_block_def*, %struct.edge_def_insns, i8*, %struct.location_t*, i32, i32, i64, i32 }
+ %struct.edge_def_insns = type { %struct.rtx_def* }
+ %struct.edge_prediction = type { %struct.edge_prediction*, %struct.edge_def*, i32, i32 }
+ %struct.eh_status = type opaque
+ %struct.elt_list = type opaque
+ %struct.elt_t = type { %struct.tree_node*, %struct.tree_node* }
+ %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }
+ %struct.et_node = type opaque
+ %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+ %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 }
+ %struct.ggc_root_tab = type { i8*, i32, i32, void (i8*)*, void (i8*)* }
+ %struct.gimplify_ctx = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.varray_head_tag*, %struct.htab*, i32, i8, i8 }
+ %struct.gimplify_init_ctor_preeval_data = type { %struct.tree_node*, i32 }
+ %struct.ht_identifier = type { i8*, i32, i32 }
+ %struct.htab = type { i32 (i8*)*, i32 (i8*, i8*)*, void (i8*)*, i8**, i32, i32, i32, i32, i32, i8* (i32, i32)*, void (i8*)*, i8*, i8* (i8*, i32, i32)*, void (i8*, i8*)*, i32 }
+ %struct.initial_value_struct = type opaque
+ %struct.lang_decl = type opaque
+ %struct.lang_hooks = type { i8*, i32, i32 (i32)*, i32 (i32, i8**)*, void (%struct.diagnostic_context*)*, i32 (i32, i8*, i32)*, i8 (i8*, i32) zeroext *, i8 (i8**) zeroext *, i8 () zeroext *, void ()*, void ()*, void (i32)*, void ()*, i64 (%struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*)*, %struct.rtx_def* (%struct.tree_node*, %struct.rtx_def*, i32, i32, %struct.rtx_def**)*, i32 (%struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*)*, i32 (%struct.rtx_def*, %struct.tree_node*)*, void (%struct.tree_node*)*, i8 (%struct.tree_node*) zeroext *, %struct.tree_node* (%struct.tree_node*)*, void (%struct.tree_node*)*, void (%struct.tree_node*)*, i8 () zeroext *, i8, i8, void ()*, void (%struct.FILE*, %struct.tree_node*, i32)*, void (%struct.FILE*, %struct.tree_node*, i32)*, void (%struct.FILE*, %struct.tree_node*, i32)*, void (%struct.FILE*, %struct.tree_node*, i32)*, i8* (%struct.tree_node*, i32)*, i32 (%struct.tree_node*, %struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*)*, void (%struct.diagnostic_context*, i8*)*, %struct.tree_node* (%struct.tree_node*)*, i64 (i64)*, %struct.attribute_spec*, %struct.attribute_spec*, %struct.attribute_spec*, i32 (%struct.tree_node*)*, %struct.lang_hooks_for_functions, %struct.lang_hooks_for_tree_inlining, %struct.lang_hooks_for_callgraph, %struct.lang_hooks_for_tree_dump, %struct.lang_hooks_for_decls, %struct.lang_hooks_for_types, i32 (%struct.tree_node**, %struct.tree_node**, %struct.tree_node**)*, %struct.tree_node* (%struct.tree_node*, %struct.tree_node*)*, %struct.tree_node* (i8*, %struct.tree_node*, i32, i32, i8*, %struct.tree_node*)* }
+ %struct.lang_hooks_for_callgraph = type { %struct.tree_node* (%struct.tree_node**, i32*, %struct.tree_node*)*, void (%struct.tree_node*)* }
+ %struct.lang_hooks_for_decls = type { i32 ()*, void (%struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*)*, %struct.tree_node* ()*, i8 (%struct.tree_node*) zeroext *, void ()*, void (%struct.tree_node*)*, i8 (%struct.tree_node*) zeroext *, i8* (%struct.tree_node*)* }
+ %struct.lang_hooks_for_functions = type { void (%struct.function*)*, void (%struct.function*)*, void (%struct.function*)*, void (%struct.function*)*, i8 (%struct.tree_node*) zeroext * }
+ %struct.lang_hooks_for_tree_dump = type { i8 (i8*, %struct.tree_node*) zeroext *, i32 (%struct.tree_node*)* }
+ %struct.lang_hooks_for_tree_inlining = type { %struct.tree_node* (%struct.tree_node**, i32*, %struct.tree_node* (%struct.tree_node**, i32*, i8*)*, i8*, %struct.pointer_set_t*)*, i32 (%struct.tree_node**)*, i32 (%struct.tree_node*)*, %struct.tree_node* (i8*, %struct.tree_node*)*, i32 (%struct.tree_node*, %struct.tree_node*)*, i32 (%struct.tree_node*)*, i8 (%struct.tree_node*, %struct.tree_node*) zeroext *, i32 (%struct.tree_node*)*, void (%struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i32)* }
+ %struct.lang_hooks_for_types = type { %struct.tree_node* (i32)*, %struct.tree_node* (i32, i32)*, %struct.tree_node* (i32, i32)*, %struct.tree_node* (%struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*)*, %struct.tree_node* (i32, %struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*)*, void (%struct.tree_node*, i8*)*, void (%struct.tree_node*, %struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*)*, i8 }
+ %struct.lang_type = type opaque
+ %struct.language_function = type opaque
+ %struct.location_t = type { i8*, i32 }
+ %struct.loop = type opaque
+ %struct.machine_function = type { %struct.rtx_def*, i32, i32, i32, %struct.arm_stack_offsets, i32, i32, i32, [14 x %struct.rtx_def*] }
+ %struct.mem_attrs = type { i64, %struct.tree_node*, %struct.rtx_def*, %struct.rtx_def*, i32 }
+ %struct.obstack = type { i32, %struct._obstack_chunk*, i8*, i8*, i8*, i32, i32, %struct._obstack_chunk* (i8*, i32)*, void (i8*, %struct._obstack_chunk*)*, i8*, i8 }
+ %struct.output_buffer = type { %struct.obstack, %struct.FILE*, i32, [128 x i8] }
+ %struct.phi_arg_d = type { %struct.tree_node*, i8 }
+ %struct.pointer_set_t = type opaque
+ %struct.pretty_printer = type { %struct.output_buffer*, i8*, i32, i32, i32, i32, i32, i8 (%struct.pretty_printer*, %struct.text_info*) zeroext *, i8, i8 }
+ %struct.ptr_info_def = type { i8, %struct.bitmap_head_def*, %struct.tree_node* }
+ %struct.real_value = type { i8, [3 x i8], [5 x i32] }
+ %struct.reg_attrs = type { %struct.tree_node*, i64 }
+ %struct.reg_info_def = type opaque
+ %struct.reorder_block_def = type { %struct.rtx_def*, %struct.rtx_def*, %struct.basic_block_def*, %struct.basic_block_def*, %struct.basic_block_def*, i32, i32, i32 }
+ %struct.rtunion = type { i32 }
+ %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }
+ %struct.rtx_def = type { i16, i8, i8, %struct.u }
+ %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
+ %struct.stmt_ann_d = type { %struct.tree_ann_common_d, i8, %struct.basic_block_def*, %struct.stmt_operands_d, %struct.dataflow_d*, %struct.bitmap_head_def*, i32 }
+ %struct.stmt_operands_d = type { %struct.def_optype_d*, %struct.def_optype_d*, %struct.v_may_def_optype_d*, %struct.vuse_optype_d*, %struct.v_may_def_optype_d* }
+ %struct.temp_slot = type opaque
+ %struct.text_info = type { i8*, i8**, i32 }
+ %struct.tree_ann_common_d = type { i32, i8*, %struct.tree_node* }
+ %struct.tree_ann_d = type { %struct.stmt_ann_d }
+ %struct.tree_binfo = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.VEC_tree*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.VEC_tree }
+ %struct.tree_block = type { %struct.tree_common, i8, [3 x i8], %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node* }
+ %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_ann_d*, i8, i8, i8, i8, i8 }
+ %struct.tree_complex = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node* }
+ %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_decl_u1 = type { i64 }
+ %struct.tree_decl_u1_a = type { i32 }
+ %struct.tree_decl_u2 = type { %struct.function* }
+ %struct.tree_exp = type { %struct.tree_common, %struct.location_t*, i32, %struct.tree_node*, [1 x %struct.tree_node*] }
+ %struct.tree_identifier = type { %struct.tree_common, %struct.ht_identifier }
+ %struct.tree_int_cst = type { %struct.tree_common, %struct.tree_int_cst_lowhi }
+ %struct.tree_int_cst_lowhi = type { i64, i64 }
+ %struct.tree_list = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node* }
+ %struct.tree_node = type { %struct.tree_decl }
+ %struct.tree_phi_node = type { %struct.tree_common, %struct.tree_node*, i32, i32, i32, %struct.basic_block_def*, %struct.dataflow_d*, [1 x %struct.phi_arg_d] }
+ %struct.tree_real_cst = type { %struct.tree_common, %struct.real_value* }
+ %struct.tree_ssa_name = type { %struct.tree_common, %struct.tree_node*, i32, %struct.ptr_info_def*, %struct.tree_node*, i8* }
+ %struct.tree_statement_list = type { %struct.tree_common, %struct.tree_statement_list_node*, %struct.tree_statement_list_node* }
+ %struct.tree_statement_list_node = type { %struct.tree_statement_list_node*, %struct.tree_statement_list_node*, %struct.tree_node* }
+ %struct.tree_stmt_iterator = type { %struct.tree_statement_list_node*, %struct.tree_node* }
+ %struct.tree_string = type { %struct.tree_common, i32, [1 x i8] }
+ %struct.tree_type = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i32, i16, i8, i8, i32, %struct.tree_node*, %struct.tree_node*, %struct.rtunion, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_type* }
+ %struct.tree_type_symtab = type { i32 }
+ %struct.tree_value_handle = type { %struct.tree_common, %struct.value_set*, i32 }
+ %struct.tree_vec = type { %struct.tree_common, i32, [1 x %struct.tree_node*] }
+ %struct.tree_vector = type { %struct.tree_common, %struct.tree_node* }
+ %struct.u = type { [1 x i64] }
+ %struct.use_operand_ptr = type { %struct.tree_node** }
+ %struct.use_optype_d = type { i32, [1 x %struct.def_operand_ptr] }
+ %struct.v_def_use_operand_type_t = type { %struct.tree_node*, %struct.tree_node* }
+ %struct.v_may_def_optype_d = type { i32, [1 x %struct.elt_t] }
+ %struct.v_must_def_optype_d = type { i32, [1 x %struct.elt_t] }
+ %struct.value_set = type opaque
+ %struct.var_ann_d = type { %struct.tree_ann_common_d, i8, i8, %struct.tree_node*, %struct.varray_head_tag*, i32, i32, i32, %struct.tree_node*, %struct.tree_node* }
+ %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+ %struct.varasm_status = type opaque
+ %struct.varray_data = type { [1 x i64] }
+ %struct.varray_head_tag = type { i32, i32, i32, i8*, %struct.u }
+ %struct.vuse_optype_d = type { i32, [1 x %struct.tree_node*] }
+@gt_pch_rs_gt_gimplify_h = external global [2 x %struct.ggc_root_tab] ; <[2 x %struct.ggc_root_tab]*> [#uses=0]
+@tmp_var_id_num = external global i32 ; <i32*> [#uses=0]
+@gt_ggc_r_gt_gimplify_h = external global [1 x %struct.ggc_root_tab] ; <[1 x %struct.ggc_root_tab]*> [#uses=0]
+@__FUNCTION__.19956 = external global [15 x i8] ; <[15 x i8]*> [#uses=0]
+@str = external global [42 x i8] ; <[42 x i8]*> [#uses=1]
+@__FUNCTION__.19974 = external global [22 x i8] ; <[22 x i8]*> [#uses=0]
+@gimplify_ctxp = external global %struct.gimplify_ctx* ; <%struct.gimplify_ctx**> [#uses=0]
+@cl_pf_opts = external global %struct.cl_perfunc_opts ; <%struct.cl_perfunc_opts*> [#uses=0]
+@__FUNCTION__.20030 = external global [22 x i8] ; <[22 x i8]*> [#uses=0]
+@__FUNCTION__.20099 = external global [24 x i8] ; <[24 x i8]*> [#uses=0]
+@global_trees = external global [47 x %struct.tree_node*] ; <[47 x %struct.tree_node*]*> [#uses=0]
+@tree_code_type = external global [0 x i32] ; <[0 x i32]*> [#uses=2]
+@current_function_decl = external global %struct.tree_node* ; <%struct.tree_node**> [#uses=0]
+@str1 = external global [2 x i8] ; <[2 x i8]*> [#uses=0]
+@str2 = external global [7 x i8] ; <[7 x i8]*> [#uses=0]
+@__FUNCTION__.20151 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
+@__FUNCTION__.20221 = external global [9 x i8] ; <[9 x i8]*> [#uses=0]
+@tree_code_length = external global [0 x i8] ; <[0 x i8]*> [#uses=0]
+@__FUNCTION__.20435 = external global [17 x i8] ; <[17 x i8]*> [#uses=0]
+@__FUNCTION__.20496 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
+@cfun = external global %struct.function* ; <%struct.function**> [#uses=0]
+@__FUNCTION__.20194 = external global [15 x i8] ; <[15 x i8]*> [#uses=0]
+@__FUNCTION__.19987 = external global [21 x i8] ; <[21 x i8]*> [#uses=0]
+@__FUNCTION__.20532 = external global [21 x i8] ; <[21 x i8]*> [#uses=0]
+@__FUNCTION__.20583 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
+@__FUNCTION__.20606 = external global [22 x i8] ; <[22 x i8]*> [#uses=0]
+@__FUNCTION__.20644 = external global [17 x i8] ; <[17 x i8]*> [#uses=0]
+@__FUNCTION__.20681 = external global [13 x i8] ; <[13 x i8]*> [#uses=0]
+@__FUNCTION__.20700 = external global [13 x i8] ; <[13 x i8]*> [#uses=0]
+@__FUNCTION__.21426 = external global [20 x i8] ; <[20 x i8]*> [#uses=0]
+@__FUNCTION__.21471 = external global [17 x i8] ; <[17 x i8]*> [#uses=0]
+@__FUNCTION__.21962 = external global [27 x i8] ; <[27 x i8]*> [#uses=0]
+@__FUNCTION__.22992 = external global [21 x i8] ; <[21 x i8]*> [#uses=0]
+@__FUNCTION__.23735 = external global [15 x i8] ; <[15 x i8]*> [#uses=0]
+@lang_hooks = external global %struct.lang_hooks ; <%struct.lang_hooks*> [#uses=0]
+@__FUNCTION__.27383 = external global [22 x i8] ; <[22 x i8]*> [#uses=0]
+@__FUNCTION__.20776 = external global [21 x i8] ; <[21 x i8]*> [#uses=0]
+@__FUNCTION__.10672 = external global [9 x i8] ; <[9 x i8]*> [#uses=0]
+@str3 = external global [47 x i8] ; <[47 x i8]*> [#uses=0]
+@str4 = external global [7 x i8] ; <[7 x i8]*> [#uses=0]
+@__FUNCTION__.20065 = external global [25 x i8] ; <[25 x i8]*> [#uses=0]
+@__FUNCTION__.23256 = external global [16 x i8] ; <[16 x i8]*> [#uses=0]
+@__FUNCTION__.23393 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
+@__FUNCTION__.20043 = external global [21 x i8] ; <[21 x i8]*> [#uses=0]
+@__FUNCTION__.20729 = external global [23 x i8] ; <[23 x i8]*> [#uses=0]
+@__FUNCTION__.20563 = external global [24 x i8] ; <[24 x i8]*> [#uses=0]
+@__FUNCTION__.10663 = external global [10 x i8] ; <[10 x i8]*> [#uses=0]
+@__FUNCTION__.20367 = external global [21 x i8] ; <[21 x i8]*> [#uses=0]
+@__FUNCTION__.20342 = external global [15 x i8] ; <[15 x i8]*> [#uses=0]
+@input_location = external global %struct.location_t ; <%struct.location_t*> [#uses=0]
+@__FUNCTION__.24510 = external global [27 x i8] ; <[27 x i8]*> [#uses=0]
+@__FUNCTION__.25097 = external global [25 x i8] ; <[25 x i8]*> [#uses=0]
+@__FUNCTION__.24705 = external global [26 x i8] ; <[26 x i8]*> [#uses=0]
+@str5 = external global [2 x i8] ; <[2 x i8]*> [#uses=0]
+@__FUNCTION__.25136 = external global [21 x i8] ; <[21 x i8]*> [#uses=0]
+@__FUNCTION__.24450 = external global [31 x i8] ; <[31 x i8]*> [#uses=0]
+@implicit_built_in_decls = external global [471 x %struct.tree_node*] ; <[471 x %struct.tree_node*]*> [#uses=0]
+@__FUNCTION__.24398 = external global [31 x i8] ; <[31 x i8]*> [#uses=0]
+@__FUNCTION__.26156 = external global [14 x i8] ; <[14 x i8]*> [#uses=1]
+@unknown_location = external global %struct.location_t ; <%struct.location_t*> [#uses=0]
+@__FUNCTION__.23038 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
+@str6 = external global [43 x i8] ; <[43 x i8]*> [#uses=0]
+@__FUNCTION__.25476 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
+@__FUNCTION__.22136 = external global [20 x i8] ; <[20 x i8]*> [#uses=1]
+@__FUNCTION__.21997 = external global [23 x i8] ; <[23 x i8]*> [#uses=0]
+@__FUNCTION__.21247 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
+@built_in_decls = external global [471 x %struct.tree_node*] ; <[471 x %struct.tree_node*]*> [#uses=0]
+@__FUNCTION__.21924 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
+@__FUNCTION__.21861 = external global [25 x i8] ; <[25 x i8]*> [#uses=0]
+@global_dc = external global %struct.diagnostic_context* ; <%struct.diagnostic_context**> [#uses=0]
+@__FUNCTION__.25246 = external global [32 x i8] ; <[32 x i8]*> [#uses=0]
+@str7 = external global [4 x i8] ; <[4 x i8]*> [#uses=0]
+@stderr = external global %struct.FILE* ; <%struct.FILE**> [#uses=0]
+@str8 = external global [24 x i8] ; <[24 x i8]*> [#uses=0]
+@str9 = external global [22 x i8] ; <[22 x i8]*> [#uses=0]
+@__FUNCTION__.27653 = external global [21 x i8] ; <[21 x i8]*> [#uses=0]
+@__FUNCTION__.27322 = external global [21 x i8] ; <[21 x i8]*> [#uses=0]
+@__FUNCTION__.27139 = external global [20 x i8] ; <[20 x i8]*> [#uses=0]
+@__FUNCTION__.22462 = external global [23 x i8] ; <[23 x i8]*> [#uses=0]
+@str10 = external global [6 x i8] ; <[6 x i8]*> [#uses=0]
+@__FUNCTION__.25389 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
+@__FUNCTION__.25650 = external global [18 x i8] ; <[18 x i8]*> [#uses=0]
+@str11 = external global [32 x i8] ; <[32 x i8]*> [#uses=0]
+@str12 = external global [3 x i8] ; <[3 x i8]*> [#uses=0]
+@str13 = external global [44 x i8] ; <[44 x i8]*> [#uses=0]
+@__FUNCTION__.27444 = external global [14 x i8] ; <[14 x i8]*> [#uses=0]
+@timevar_enable = external global i8 ; <i8*> [#uses=0]
+@__FUNCTION__.27533 = external global [23 x i8] ; <[23 x i8]*> [#uses=0]
+@flag_instrument_function_entry_exit = external global i32 ; <i32*> [#uses=0]
+@__FUNCTION__.25331 = external global [23 x i8] ; <[23 x i8]*> [#uses=0]
+@__FUNCTION__.20965 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
+@str14 = external global [12 x i8] ; <[12 x i8]*> [#uses=0]
+@__FUNCTION__.26053 = external global [21 x i8] ; <[21 x i8]*> [#uses=0]
+@__FUNCTION__.26004 = external global [20 x i8] ; <[20 x i8]*> [#uses=0]
+@str15 = external global [8 x i8] ; <[8 x i8]*> [#uses=0]
+@__FUNCTION__.21584 = external global [21 x i8] ; <[21 x i8]*> [#uses=0]
+@str16 = external global [12 x i8] ; <[12 x i8]*> [#uses=0]
+@__FUNCTION__.25903 = external global [28 x i8] ; <[28 x i8]*> [#uses=0]
+@__FUNCTION__.22930 = external global [23 x i8] ; <[23 x i8]*> [#uses=0]
+@__FUNCTION__.23832 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
+@str17 = external global [6 x i8] ; <[6 x i8]*> [#uses=0]
+@__FUNCTION__.24620 = external global [24 x i8] ; <[24 x i8]*> [#uses=0]
+@__FUNCTION__.24582 = external global [30 x i8] ; <[30 x i8]*> [#uses=0]
+@__FUNCTION__.21382 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
+@__FUNCTION__.21117 = external global [21 x i8] ; <[21 x i8]*> [#uses=0]
+
+
+declare void @push_gimplify_context()
+
+declare i32 @gimple_tree_hash(i8*)
+
+declare i32 @iterative_hash_expr(%struct.tree_node*, i32)
+
+declare i32 @gimple_tree_eq(i8*, i8*)
+
+declare i32 @operand_equal_p(%struct.tree_node*, %struct.tree_node*, i32)
+
+declare void @fancy_abort(i8*, i32, i8*)
+
+declare i8* @xcalloc(i32, i32)
+
+declare %struct.htab* @htab_create(i32, i32 (i8*)*, i32 (i8*, i8*)*, void (i8*)*)
+
+declare void @free(i8*)
+
+declare void @gimple_push_bind_expr(%struct.tree_node*)
+
+declare void @gimple_pop_bind_expr()
+
+declare %struct.tree_node* @gimple_current_bind_expr()
+
+declare fastcc void @gimple_push_condition()
+
+declare %struct.tree_node* @create_artificial_label()
+
+declare %struct.tree_node* @build_decl_stat(i32, %struct.tree_node*, %struct.tree_node*)
+
+declare void @tree_class_check_failed(%struct.tree_node*, i32, i8*, i32, i8*)
+
+declare %struct.tree_node* @create_tmp_var_name(i8*)
+
+declare i32 @strlen(i8*)
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32)
+
+declare i32 @sprintf(i8*, i8*, ...)
+
+declare %struct.tree_node* @get_identifier(i8*)
+
+declare %struct.tree_node* @create_tmp_var_raw(%struct.tree_node*, i8*)
+
+declare %struct.tree_node* @build_qualified_type(%struct.tree_node*, i32)
+
+declare i8* @get_name(%struct.tree_node*)
+
+declare void @tree_operand_check_failed(i32, i32, i8*, i32, i8*)
+
+declare void @tree_check_failed(%struct.tree_node*, i8*, i32, i8*, ...)
+
+declare void @declare_tmp_vars(%struct.tree_node*, %struct.tree_node*)
+
+declare %struct.tree_node* @nreverse(%struct.tree_node*)
+
+declare void @gimple_add_tmp_var(%struct.tree_node*)
+
+declare void @record_vars(%struct.tree_node*)
+
+declare %struct.tree_node* @create_tmp_var(%struct.tree_node*, i8*)
+
+declare void @pop_gimplify_context(%struct.tree_node*)
+
+declare void @htab_delete(%struct.htab*)
+
+declare fastcc void @annotate_one_with_locus(%struct.tree_node*, i32, i32)
+
+declare void @annotate_with_locus(%struct.tree_node*, i32, i32)
+
+declare %struct.tree_node* @mostly_copy_tree_r(%struct.tree_node**, i32*, i8*)
+
+declare %struct.tree_node* @copy_tree_r(%struct.tree_node**, i32*, i8*)
+
+declare %struct.tree_node* @mark_decls_volatile_r(%struct.tree_node**, i32*, i8*)
+
+declare %struct.tree_node* @copy_if_shared_r(%struct.tree_node**, i32*, i8*)
+
+declare %struct.tree_node* @walk_tree(%struct.tree_node**, %struct.tree_node* (%struct.tree_node**, i32*, i8*)*, i8*, %struct.pointer_set_t*)
+
+declare %struct.tree_node* @unmark_visited_r(%struct.tree_node**, i32*, i8*)
+
+declare fastcc void @unshare_body(%struct.tree_node**, %struct.tree_node*)
+
+declare %struct.cgraph_node* @cgraph_node(%struct.tree_node*)
+
+declare fastcc void @unvisit_body(%struct.tree_node**, %struct.tree_node*)
+
+declare void @unshare_all_trees(%struct.tree_node*)
+
+declare %struct.tree_node* @unshare_expr(%struct.tree_node*)
+
+declare %struct.tree_node* @build_and_jump(%struct.tree_node**)
+
+declare %struct.tree_node* @build1_stat(i32, %struct.tree_node*, %struct.tree_node*)
+
+declare i32 @compare_case_labels(i8*, i8*)
+
+declare i32 @tree_int_cst_compare(%struct.tree_node*, %struct.tree_node*)
+
+declare void @sort_case_labels(%struct.tree_node*)
+
+declare void @tree_vec_elt_check_failed(i32, i32, i8*, i32, i8*)
+
+declare void @qsort(i8*, i32, i32, i32 (i8*, i8*)*)
+
+declare %struct.tree_node* @force_labels_r(%struct.tree_node**, i32*, i8*)
+
+declare fastcc void @canonicalize_component_ref(%struct.tree_node**)
+
+declare %struct.tree_node* @get_unwidened(%struct.tree_node*, %struct.tree_node*)
+
+declare fastcc void @maybe_with_size_expr(%struct.tree_node**)
+
+declare %struct.tree_node* @substitute_placeholder_in_expr(%struct.tree_node*, %struct.tree_node*)
+
+declare %struct.tree_node* @build2_stat(i32, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*)
+
+declare fastcc %struct.tree_node* @gimple_boolify(%struct.tree_node*)
+
+declare %struct.tree_node* @convert(%struct.tree_node*, %struct.tree_node*)
+
+declare %struct.tree_node* @gimplify_init_ctor_preeval_1(%struct.tree_node**, i32*, i8*)
+
+declare i64 @get_alias_set(%struct.tree_node*)
+
+declare i32 @alias_sets_conflict_p(i64, i64)
+
+declare fastcc i8 @cpt_same_type(%struct.tree_node*, %struct.tree_node*) zeroext
+
+declare %struct.tree_node* @check_pointer_types_r(%struct.tree_node**, i32*, i8*)
+
+declare %struct.tree_node* @voidify_wrapper_expr(%struct.tree_node*, %struct.tree_node*)
+
+declare i32 @integer_zerop(%struct.tree_node*)
+
+declare fastcc void @append_to_statement_list_1(%struct.tree_node*, %struct.tree_node**)
+
+declare %struct.tree_node* @alloc_stmt_list()
+
+declare void @tsi_link_after(%struct.tree_stmt_iterator*, %struct.tree_node*, i32)
+
+declare void @append_to_statement_list_force(%struct.tree_node*, %struct.tree_node**)
+
+declare void @append_to_statement_list(%struct.tree_node*, %struct.tree_node**)
+
+declare fastcc %struct.tree_node* @shortcut_cond_r(%struct.tree_node*, %struct.tree_node**, %struct.tree_node**)
+
+declare %struct.tree_node* @build3_stat(i32, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*)
+
+declare fastcc %struct.tree_node* @shortcut_cond_expr(%struct.tree_node*)
+
+declare %struct.tree_node* @expr_last(%struct.tree_node*)
+
+declare i8 @block_may_fallthru(%struct.tree_node*) zeroext
+
+declare fastcc void @gimple_pop_condition(%struct.tree_node**)
+
+declare %struct.tree_node* @gimple_build_eh_filter(%struct.tree_node*, %struct.tree_node*, %struct.tree_node*)
+
+declare void @annotate_all_with_locus(%struct.tree_node**, i32, i32)
+
+declare fastcc %struct.tree_node* @internal_get_tmp_var(%struct.tree_node*, %struct.tree_node**, %struct.tree_node**, i8 zeroext )
+
+define i32 @gimplify_expr(%struct.tree_node** %expr_p, %struct.tree_node** %pre_p, %struct.tree_node** %post_p, i8 (%struct.tree_node*) zeroext * %gimple_test_f, i32 %fallback) {
+entry:
+ %internal_post = alloca %struct.tree_node*, align 4 ; <%struct.tree_node**> [#uses=2]
+ %pre_p_addr.0 = select i1 false, %struct.tree_node** null, %struct.tree_node** %pre_p ; <%struct.tree_node**> [#uses=7]
+ %post_p_addr.0 = select i1 false, %struct.tree_node** %internal_post, %struct.tree_node** %post_p ; <%struct.tree_node**> [#uses=7]
+ br i1 false, label %bb277, label %bb191
+
+bb191: ; preds = %entry
+ ret i32 0
+
+bb277: ; preds = %entry
+ %tmp283 = call i32 null( %struct.tree_node** %expr_p, %struct.tree_node** %pre_p_addr.0, %struct.tree_node** %post_p_addr.0 ) ; <i32> [#uses=1]
+ switch i32 %tmp283, label %bb7478 [
+ i32 0, label %cond_next289
+ i32 -1, label %cond_next298
+ ]
+
+cond_next289: ; preds = %bb277
+ ret i32 0
+
+cond_next298: ; preds = %bb277
+ switch i32 0, label %bb7444 [
+ i32 24, label %bb7463
+ i32 25, label %bb7463
+ i32 26, label %bb7463
+ i32 27, label %bb7463
+ i32 28, label %bb7463
+ i32 33, label %bb4503
+ i32 39, label %bb397
+ i32 40, label %bb5650
+ i32 41, label %bb4339
+ i32 42, label %bb4350
+ i32 43, label %bb4350
+ i32 44, label %bb319
+ i32 45, label %bb397
+ i32 46, label %bb6124
+ i32 47, label %bb7463
+ i32 49, label %bb5524
+ i32 50, label %bb1283
+ i32 51, label %bb1289
+ i32 52, label %bb1289
+ i32 53, label %bb5969
+ i32 54, label %bb408
+ i32 56, label %bb5079
+ i32 57, label %bb428
+ i32 59, label %bb5965
+ i32 74, label %bb4275
+ i32 75, label %bb4275
+ i32 76, label %bb4275
+ i32 77, label %bb4275
+ i32 91, label %bb1296
+ i32 92, label %bb1296
+ i32 96, label %bb1322
+ i32 112, label %bb2548
+ i32 113, label %bb2548
+ i32 115, label %bb397
+ i32 116, label %bb5645
+ i32 117, label %bb1504
+ i32 121, label %bb397
+ i32 122, label %bb397
+ i32 123, label %bb313
+ i32 124, label %bb313
+ i32 125, label %bb313
+ i32 126, label %bb313
+ i32 127, label %bb2141
+ i32 128, label %cond_next5873
+ i32 129, label %cond_next5873
+ i32 130, label %bb4536
+ i32 131, label %bb5300
+ i32 132, label %bb5170
+ i32 133, label %bb5519
+ i32 134, label %bb5091
+ i32 135, label %bb5083
+ i32 136, label %bb5087
+ i32 137, label %bb5382
+ i32 139, label %bb7463
+ i32 140, label %bb7463
+ i32 142, label %bb5974
+ i32 143, label %bb6049
+ i32 147, label %bb6296
+ i32 151, label %cond_next6474
+ ]
+
+bb313: ; preds = %cond_next298, %cond_next298, %cond_next298, %cond_next298
+ ret i32 0
+
+bb319: ; preds = %cond_next298
+ ret i32 0
+
+bb397: ; preds = %cond_next298, %cond_next298, %cond_next298, %cond_next298, %cond_next298
+ ret i32 0
+
+bb408: ; preds = %cond_next298
+ %tmp413 = call fastcc i32 @gimplify_cond_expr( %struct.tree_node** %expr_p, %struct.tree_node** %pre_p_addr.0, %struct.tree_node** %post_p_addr.0, %struct.tree_node* null, i32 %fallback ) ; <i32> [#uses=0]
+ ret i32 0
+
+bb428: ; preds = %cond_next298
+ ret i32 0
+
+bb1283: ; preds = %cond_next298
+ ret i32 0
+
+bb1289: ; preds = %cond_next298, %cond_next298
+ ret i32 0
+
+bb1296: ; preds = %cond_next298, %cond_next298
+ ret i32 0
+
+bb1322: ; preds = %cond_next298
+ ret i32 0
+
+bb1504: ; preds = %cond_next298
+ ret i32 0
+
+bb2141: ; preds = %cond_next298
+ ret i32 0
+
+bb2548: ; preds = %cond_next298, %cond_next298
+ %tmp2554 = load %struct.tree_node** %expr_p ; <%struct.tree_node*> [#uses=2]
+ %tmp2562 = and i32 0, 255 ; <i32> [#uses=1]
+ %tmp2569 = add i8 0, -4 ; <i8> [#uses=1]
+ icmp ugt i8 %tmp2569, 5 ; <i1>:0 [#uses=2]
+ %tmp2587 = load i8* null ; <i8> [#uses=1]
+ icmp eq i8 %tmp2587, 0 ; <i1>:1 [#uses=2]
+ %tmp2607 = load %struct.tree_node** null ; <%struct.tree_node*> [#uses=2]
+ br i1 false, label %bb2754, label %cond_next2617
+
+cond_next2617: ; preds = %bb2548
+ ret i32 0
+
+bb2754: ; preds = %bb2548
+ br i1 %0, label %cond_true2780, label %cond_next2783
+
+cond_true2780: ; preds = %bb2754
+ call void @tree_class_check_failed( %struct.tree_node* %tmp2554, i32 9, i8* getelementptr ([42 x i8]* @str, i32 0, i32 0), i32 1415, i8* getelementptr ([20 x i8]* @__FUNCTION__.22136, i32 0, i32 0) )
+ unreachable
+
+cond_next2783: ; preds = %bb2754
+ %tmp2825 = and i32 0, 255 ; <i32> [#uses=1]
+ %tmp2829 = load i32* null ; <i32> [#uses=1]
+ %tmp28292830 = trunc i32 %tmp2829 to i8 ; <i8> [#uses=1]
+ %tmp2832 = add i8 %tmp28292830, -4 ; <i8> [#uses=1]
+ icmp ugt i8 %tmp2832, 5 ; <i1>:2 [#uses=1]
+ icmp eq i8 0, 0 ; <i1>:3 [#uses=1]
+ %tmp28652866 = bitcast %struct.tree_node* %tmp2607 to %struct.tree_exp* ; <%struct.tree_exp*> [#uses=1]
+ %tmp2868 = getelementptr %struct.tree_exp* %tmp28652866, i32 0, i32 4, i32 0 ; <%struct.tree_node**> [#uses=1]
+ %tmp2870 = load %struct.tree_node** %tmp2868 ; <%struct.tree_node*> [#uses=1]
+ br i1 %1, label %cond_true2915, label %cond_next2927
+
+cond_true2915: ; preds = %cond_next2783
+ unreachable
+
+cond_next2927: ; preds = %cond_next2783
+ %tmp2938 = load %struct.tree_node** null ; <%struct.tree_node*> [#uses=1]
+ %tmp2944 = load i32* null ; <i32> [#uses=1]
+ %tmp2946 = and i32 %tmp2944, 255 ; <i32> [#uses=1]
+ %tmp2949 = getelementptr [0 x i32]* @tree_code_type, i32 0, i32 %tmp2946 ; <i32*> [#uses=1]
+ %tmp2950 = load i32* %tmp2949 ; <i32> [#uses=1]
+ icmp eq i32 %tmp2950, 2 ; <i1>:4 [#uses=1]
+ br i1 %4, label %cond_next2954, label %cond_true2951
+
+cond_true2951: ; preds = %cond_next2927
+ call void @tree_class_check_failed( %struct.tree_node* %tmp2938, i32 2, i8* getelementptr ([42 x i8]* @str, i32 0, i32 0), i32 1415, i8* getelementptr ([20 x i8]* @__FUNCTION__.22136, i32 0, i32 0) )
+ unreachable
+
+cond_next2954: ; preds = %cond_next2927
+ br i1 %0, label %cond_true2991, label %cond_next2994
+
+cond_true2991: ; preds = %cond_next2954
+ unreachable
+
+cond_next2994: ; preds = %cond_next2954
+ br i1 %1, label %cond_true3009, label %cond_next3021
+
+cond_true3009: ; preds = %cond_next2994
+ call void @tree_operand_check_failed( i32 0, i32 %tmp2562, i8* getelementptr ([42 x i8]* @str, i32 0, i32 0), i32 1415, i8* getelementptr ([20 x i8]* @__FUNCTION__.22136, i32 0, i32 0) )
+ unreachable
+
+cond_next3021: ; preds = %cond_next2994
+ br i1 %2, label %cond_true3044, label %cond_next3047
+
+cond_true3044: ; preds = %cond_next3021
+ call void @tree_class_check_failed( %struct.tree_node* %tmp2607, i32 9, i8* getelementptr ([42 x i8]* @str, i32 0, i32 0), i32 1415, i8* getelementptr ([20 x i8]* @__FUNCTION__.22136, i32 0, i32 0) )
+ unreachable
+
+cond_next3047: ; preds = %cond_next3021
+ br i1 %3, label %cond_true3062, label %cond_next3074
+
+cond_true3062: ; preds = %cond_next3047
+ call void @tree_operand_check_failed( i32 0, i32 %tmp2825, i8* getelementptr ([42 x i8]* @str, i32 0, i32 0), i32 1415, i8* getelementptr ([20 x i8]* @__FUNCTION__.22136, i32 0, i32 0) )
+ unreachable
+
+cond_next3074: ; preds = %cond_next3047
+ %tmp3084 = getelementptr %struct.tree_node* %tmp2870, i32 0, i32 0, i32 0, i32 1 ; <%struct.tree_node**> [#uses=1]
+ %tmp3085 = load %struct.tree_node** %tmp3084 ; <%struct.tree_node*> [#uses=1]
+ %tmp31043105 = bitcast %struct.tree_node* %tmp3085 to %struct.tree_type* ; <%struct.tree_type*> [#uses=1]
+ %tmp3106 = getelementptr %struct.tree_type* %tmp31043105, i32 0, i32 6 ; <i16*> [#uses=1]
+ %tmp31063107 = bitcast i16* %tmp3106 to i32* ; <i32*> [#uses=1]
+ %tmp3108 = load i32* %tmp31063107 ; <i32> [#uses=1]
+ xor i32 %tmp3108, 0 ; <i32>:5 [#uses=1]
+ %tmp81008368 = and i32 %5, 65024 ; <i32> [#uses=1]
+ icmp eq i32 %tmp81008368, 0 ; <i1>:6 [#uses=1]
+ br i1 %6, label %cond_next3113, label %bb3351
+
+cond_next3113: ; preds = %cond_next3074
+ ret i32 0
+
+bb3351: ; preds = %cond_next3074
+ %tmp3354 = call i8 @tree_ssa_useless_type_conversion( %struct.tree_node* %tmp2554 ) zeroext ; <i8> [#uses=1]
+ icmp eq i8 %tmp3354, 0 ; <i1>:7 [#uses=1]
+ %tmp3424 = load i32* null ; <i32> [#uses=1]
+ br i1 %7, label %cond_next3417, label %cond_true3356
+
+cond_true3356: ; preds = %bb3351
+ ret i32 0
+
+cond_next3417: ; preds = %bb3351
+ br i1 false, label %cond_true3429, label %cond_next4266
+
+cond_true3429: ; preds = %cond_next3417
+ %tmp3443 = and i32 %tmp3424, 255 ; <i32> [#uses=0]
+ ret i32 0
+
+cond_next4266: ; preds = %cond_next3417
+ %tmp4268 = load %struct.tree_node** %expr_p ; <%struct.tree_node*> [#uses=1]
+ icmp eq %struct.tree_node* %tmp4268, null ; <i1>:8 [#uses=1]
+ br i1 %8, label %bb4275, label %bb7463
+
+bb4275: ; preds = %cond_next4266, %cond_next298, %cond_next298, %cond_next298, %cond_next298
+ %tmp4289 = and i32 0, 255 ; <i32> [#uses=2]
+ %tmp4292 = getelementptr [0 x i32]* @tree_code_type, i32 0, i32 %tmp4289 ; <i32*> [#uses=1]
+ %tmp4293 = load i32* %tmp4292 ; <i32> [#uses=1]
+ %tmp42934294 = trunc i32 %tmp4293 to i8 ; <i8> [#uses=1]
+ %tmp4296 = add i8 %tmp42934294, -4 ; <i8> [#uses=1]
+ icmp ugt i8 %tmp4296, 5 ; <i1>:9 [#uses=1]
+ br i1 %9, label %cond_true4297, label %cond_next4300
+
+cond_true4297: ; preds = %bb4275
+ unreachable
+
+cond_next4300: ; preds = %bb4275
+ %tmp4314 = load i8* null ; <i8> [#uses=1]
+ icmp eq i8 %tmp4314, 0 ; <i1>:10 [#uses=1]
+ br i1 %10, label %cond_true4315, label %cond_next4327
+
+cond_true4315: ; preds = %cond_next4300
+ call void @tree_operand_check_failed( i32 0, i32 %tmp4289, i8* getelementptr ([42 x i8]* @str, i32 0, i32 0), i32 3997, i8* getelementptr ([14 x i8]* @__FUNCTION__.26156, i32 0, i32 0) )
+ unreachable
+
+cond_next4327: ; preds = %cond_next4300
+ %tmp4336 = call i32 @gimplify_expr( %struct.tree_node** null, %struct.tree_node** %pre_p_addr.0, %struct.tree_node** %post_p_addr.0, i8 (%struct.tree_node*) zeroext * @is_gimple_val, i32 1 ) ; <i32> [#uses=0]
+ ret i32 0
+
+bb4339: ; preds = %cond_next298
+ ret i32 0
+
+bb4350: ; preds = %cond_next298, %cond_next298
+ ret i32 0
+
+bb4503: ; preds = %cond_next298
+ ret i32 0
+
+bb4536: ; preds = %cond_next298
+ ret i32 0
+
+bb5079: ; preds = %cond_next298
+ ret i32 0
+
+bb5083: ; preds = %cond_next298
+ ret i32 0
+
+bb5087: ; preds = %cond_next298
+ ret i32 0
+
+bb5091: ; preds = %cond_next298
+ ret i32 0
+
+bb5170: ; preds = %cond_next298
+ ret i32 0
+
+bb5300: ; preds = %cond_next298
+ ret i32 0
+
+bb5382: ; preds = %cond_next298
+ ret i32 0
+
+bb5519: ; preds = %cond_next298
+ ret i32 0
+
+bb5524: ; preds = %cond_next298
+ ret i32 0
+
+bb5645: ; preds = %cond_next298
+ ret i32 0
+
+bb5650: ; preds = %cond_next298
+ ret i32 0
+
+cond_next5873: ; preds = %cond_next298, %cond_next298
+ ret i32 0
+
+bb5965: ; preds = %cond_next298
+ %tmp5968 = call fastcc i32 @gimplify_cleanup_point_expr( %struct.tree_node** %expr_p, %struct.tree_node** %pre_p_addr.0 ) ; <i32> [#uses=0]
+ ret i32 0
+
+bb5969: ; preds = %cond_next298
+ %tmp5973 = call fastcc i32 @gimplify_target_expr( %struct.tree_node** %expr_p, %struct.tree_node** %pre_p_addr.0, %struct.tree_node** %post_p_addr.0 ) ; <i32> [#uses=0]
+ ret i32 0
+
+bb5974: ; preds = %cond_next298
+ ret i32 0
+
+bb6049: ; preds = %cond_next298
+ ret i32 0
+
+bb6124: ; preds = %cond_next298
+ ret i32 0
+
+bb6296: ; preds = %cond_next298
+ ret i32 0
+
+cond_next6474: ; preds = %cond_next298
+ icmp eq %struct.tree_node** %internal_post, %post_p_addr.0 ; <i1>:11 [#uses=1]
+ %iftmp.381.0 = select i1 %11, %struct.tree_node** null, %struct.tree_node** %post_p_addr.0 ; <%struct.tree_node**> [#uses=1]
+ %tmp6490 = call i32 @gimplify_expr( %struct.tree_node** null, %struct.tree_node** %pre_p_addr.0, %struct.tree_node** %iftmp.381.0, i8 (%struct.tree_node*) zeroext * %gimple_test_f, i32 %fallback ) ; <i32> [#uses=0]
+ %tmp6551 = call i32 @gimplify_expr( %struct.tree_node** null, %struct.tree_node** %pre_p_addr.0, %struct.tree_node** %post_p_addr.0, i8 (%struct.tree_node*) zeroext * @is_gimple_val, i32 1 ) ; <i32> [#uses=0]
+ ret i32 0
+
+bb7444: ; preds = %cond_next298
+ ret i32 0
+
+bb7463: ; preds = %cond_next4266, %cond_next298, %cond_next298, %cond_next298, %cond_next298, %cond_next298, %cond_next298, %cond_next298, %cond_next298
+ ret i32 0
+
+bb7478: ; preds = %bb277
+ ret i32 0
+}
+
+declare i8 @is_gimple_formal_tmp_rhs(%struct.tree_node*) zeroext
+
+declare void @gimplify_and_add(%struct.tree_node*, %struct.tree_node**)
+
+declare %struct.tree_node* @get_initialized_tmp_var(%struct.tree_node*, %struct.tree_node**, %struct.tree_node**)
+
+declare %struct.tree_node* @get_formal_tmp_var(%struct.tree_node*, %struct.tree_node**)
+
+declare fastcc void @gimplify_init_ctor_preeval(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**, %struct.gimplify_init_ctor_preeval_data*)
+
+declare i8 @type_contains_placeholder_p(%struct.tree_node*) zeroext
+
+declare i8 @is_gimple_mem_rhs(%struct.tree_node*) zeroext
+
+declare fastcc i32 @gimplify_modify_expr_rhs(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**, %struct.tree_node**, %struct.tree_node**, i8 zeroext )
+
+declare %struct.tree_node* @fold_indirect_ref(%struct.tree_node*)
+
+declare fastcc i32 @gimplify_compound_expr(%struct.tree_node**, %struct.tree_node**, i8 zeroext )
+
+declare i8 @is_gimple_lvalue(%struct.tree_node*) zeroext
+
+declare void @categorize_ctor_elements(%struct.tree_node*, i64*, i64*, i64*, i8*)
+
+declare void @lhd_set_decl_assembler_name(%struct.tree_node*)
+
+declare i64 @int_size_in_bytes(%struct.tree_node*)
+
+declare i32 @can_move_by_pieces(i64, i32)
+
+declare i64 @count_type_elements(%struct.tree_node*)
+
+declare void @gimplify_stmt(%struct.tree_node**)
+
+declare %struct.tree_node* @get_base_address(%struct.tree_node*)
+
+declare fastcc void @gimplify_init_ctor_eval(%struct.tree_node*, %struct.tree_node*, %struct.tree_node**, i8 zeroext )
+
+declare %struct.tree_node* @build_complex(%struct.tree_node*, %struct.tree_node*, %struct.tree_node*)
+
+declare i8 (%struct.tree_node*) zeroext * @rhs_predicate_for(%struct.tree_node*)
+
+declare %struct.tree_node* @build_vector(%struct.tree_node*, %struct.tree_node*)
+
+declare i8 @is_gimple_val(%struct.tree_node*) zeroext
+
+declare i8 @is_gimple_reg_type(%struct.tree_node*) zeroext
+
+declare fastcc i32 @gimplify_cond_expr(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**, %struct.tree_node*, i32)
+
+declare fastcc i32 @gimplify_modify_expr(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**, i8 zeroext )
+
+declare %struct.tree_node* @tree_cons_stat(%struct.tree_node*, %struct.tree_node*, %struct.tree_node*)
+
+declare %struct.tree_node* @build_fold_addr_expr(%struct.tree_node*)
+
+declare %struct.tree_node* @build_function_call_expr(%struct.tree_node*, %struct.tree_node*)
+
+declare i8 @is_gimple_addressable(%struct.tree_node*) zeroext
+
+declare i8 @is_gimple_reg(%struct.tree_node*) zeroext
+
+declare %struct.tree_node* @make_ssa_name(%struct.tree_node*, %struct.tree_node*)
+
+declare i8 @tree_ssa_useless_type_conversion(%struct.tree_node*) zeroext
+
+declare fastcc i32 @gimplify_self_mod_expr(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**, i8 zeroext )
+
+declare fastcc i32 @gimplify_compound_lval(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**, i32)
+
+declare %struct.tree_node* @get_callee_fndecl(%struct.tree_node*)
+
+declare %struct.tree_node* @fold_builtin(%struct.tree_node*, i8 zeroext )
+
+declare void @error(i8*, ...)
+
+declare %struct.tree_node* @build_empty_stmt()
+
+declare i8 @fold_builtin_next_arg(%struct.tree_node*) zeroext
+
+declare fastcc i32 @gimplify_arg(%struct.tree_node**, %struct.tree_node**)
+
+declare i8 @is_gimple_call_addr(%struct.tree_node*) zeroext
+
+declare i32 @call_expr_flags(%struct.tree_node*)
+
+declare void @recalculate_side_effects(%struct.tree_node*)
+
+declare %struct.tree_node* @fold_convert(%struct.tree_node*, %struct.tree_node*)
+
+declare void @recompute_tree_invarant_for_addr_expr(%struct.tree_node*)
+
+declare i32 @gimplify_va_arg_expr(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**)
+
+declare %struct.tree_node* @size_int_kind(i64, i32)
+
+declare %struct.tree_node* @size_binop(i32, %struct.tree_node*, %struct.tree_node*)
+
+declare %struct.tree_node* @build4_stat(i32, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*)
+
+declare void @gimplify_type_sizes(%struct.tree_node*, %struct.tree_node**)
+
+declare void @gimplify_one_sizepos(%struct.tree_node**, %struct.tree_node**)
+
+declare %struct.tree_node* @build_pointer_type(%struct.tree_node*)
+
+declare %struct.tree_node* @build_fold_indirect_ref(%struct.tree_node*)
+
+declare fastcc i32 @gimplify_bind_expr(%struct.tree_node**, %struct.tree_node*, %struct.tree_node**)
+
+declare fastcc void @gimplify_loop_expr(%struct.tree_node**, %struct.tree_node**)
+
+declare fastcc i32 @gimplify_switch_expr(%struct.tree_node**, %struct.tree_node**)
+
+declare %struct.tree_node* @decl_function_context(%struct.tree_node*)
+
+declare %struct.varray_head_tag* @varray_grow(%struct.varray_head_tag*, i32)
+
+declare fastcc void @gimplify_return_expr(%struct.tree_node*, %struct.tree_node**)
+
+declare fastcc i32 @gimplify_save_expr(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**)
+
+declare fastcc i32 @gimplify_asm_expr(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**)
+
+declare void @gimplify_to_stmt_list(%struct.tree_node**)
+
+declare fastcc i32 @gimplify_cleanup_point_expr(%struct.tree_node**, %struct.tree_node**)
+
+declare fastcc i32 @gimplify_target_expr(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**)
+
+declare void @tsi_delink(%struct.tree_stmt_iterator*)
+
+declare void @tsi_link_before(%struct.tree_stmt_iterator*, %struct.tree_node*, i32)
+
+declare i8 @is_gimple_stmt(%struct.tree_node*) zeroext
+
+declare void @print_generic_expr(%struct.FILE*, %struct.tree_node*, i32)
+
+declare void @debug_tree(%struct.tree_node*)
+
+declare void @internal_error(i8*, ...)
+
+declare %struct.tree_node* @force_gimple_operand(%struct.tree_node*, %struct.tree_node**, i8 zeroext , %struct.tree_node*)
+
+declare i8 @is_gimple_reg_rhs(%struct.tree_node*) zeroext
+
+declare void @add_referenced_tmp_var(%struct.tree_node*)
+
+declare i8 @contains_placeholder_p(%struct.tree_node*) zeroext
+
+declare %struct.varray_head_tag* @varray_init(i32, i32, i8*)
+
+declare i32 @handled_component_p(%struct.tree_node*)
+
+declare void @varray_check_failed(%struct.varray_head_tag*, i32, i8*, i32, i8*)
+
+declare %struct.tree_node* @array_ref_low_bound(%struct.tree_node*)
+
+declare i8 @is_gimple_min_invariant(%struct.tree_node*) zeroext
+
+declare i8 @is_gimple_formal_tmp_reg(%struct.tree_node*) zeroext
+
+declare %struct.tree_node* @array_ref_element_size(%struct.tree_node*)
+
+declare %struct.tree_node* @component_ref_field_offset(%struct.tree_node*)
+
+declare i8 @is_gimple_min_lval(%struct.tree_node*) zeroext
+
+declare void @varray_underflow(%struct.varray_head_tag*, i8*, i32, i8*)
+
+declare i32 @list_length(%struct.tree_node*)
+
+declare i8 @parse_output_constraint(i8**, i32, i32, i32, i8*, i8*, i8*) zeroext
+
+declare i8* @xstrdup(i8*)
+
+declare %struct.tree_node* @build_string(i32, i8*)
+
+declare i8* @strchr(i8*, i32)
+
+declare %struct.tree_node* @build_tree_list_stat(%struct.tree_node*, %struct.tree_node*)
+
+declare %struct.tree_node* @chainon(%struct.tree_node*, %struct.tree_node*)
+
+declare i8 @parse_input_constraint(i8**, i32, i32, i32, i32, i8**, i8*, i8*) zeroext
+
+declare i8 @is_gimple_asm_val(%struct.tree_node*) zeroext
+
+declare void @gimplify_body(%struct.tree_node**, %struct.tree_node*, i8 zeroext )
+
+declare void @timevar_push_1(i32)
+
+declare %struct.tree_node* @gimplify_parameters()
+
+declare %struct.tree_node* @expr_only(%struct.tree_node*)
+
+declare void @timevar_pop_1(i32)
+
+declare void @gimplify_function_tree(%struct.tree_node*)
+
+declare void @allocate_struct_function(%struct.tree_node*)
+
+declare %struct.tree_node* @make_tree_vec_stat(i32)
+
+declare %struct.tree_node* @tsi_split_statement_list_after(%struct.tree_stmt_iterator*)
+
+declare i8 @is_gimple_condexpr(%struct.tree_node*) zeroext
+
+declare %struct.tree_node* @invert_truthvalue(%struct.tree_node*)
+
+declare i8 @initializer_zerop(%struct.tree_node*) zeroext
+
+declare i32 @simple_cst_equal(%struct.tree_node*, %struct.tree_node*)
+
+declare i32 @aggregate_value_p(%struct.tree_node*, %struct.tree_node*)
+
+declare i32 @fwrite(i8*, i32, i32, %struct.FILE*)
diff --git a/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll b/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll
new file mode 100644
index 0000000..e4635f5
--- /dev/null
+++ b/test/CodeGen/ARM/2007-03-27-RegScavengerAssert.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi
+; PR1279
+
+ %struct.rtx_def = type { i16, i8, i8, %struct.u }
+ %struct.u = type { [1 x i64] }
+
+define fastcc void @find_reloads_address(%struct.rtx_def** %loc) {
+entry:
+ %ad_addr = alloca %struct.rtx_def* ; <%struct.rtx_def**> [#uses=2]
+ br i1 false, label %cond_next416, label %cond_true340
+
+cond_true340: ; preds = %entry
+ ret void
+
+cond_next416: ; preds = %entry
+ %tmp1085 = load %struct.rtx_def** %ad_addr ; <%struct.rtx_def*> [#uses=1]
+ br i1 false, label %bb1084, label %cond_true418
+
+cond_true418: ; preds = %cond_next416
+ ret void
+
+bb1084: ; preds = %cond_next416
+ br i1 false, label %cond_true1092, label %cond_next1102
+
+cond_true1092: ; preds = %bb1084
+ %tmp1094 = getelementptr %struct.rtx_def* %tmp1085, i32 0, i32 3 ; <%struct.u*> [#uses=1]
+ %tmp10981099 = bitcast %struct.u* %tmp1094 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=2]
+ %tmp1101 = load %struct.rtx_def** %tmp10981099 ; <%struct.rtx_def*> [#uses=1]
+ store %struct.rtx_def* %tmp1101, %struct.rtx_def** %ad_addr
+ br label %cond_next1102
+
+cond_next1102: ; preds = %cond_true1092, %bb1084
+ %loc_addr.0 = phi %struct.rtx_def** [ %tmp10981099, %cond_true1092 ], [ %loc, %bb1084 ] ; <%struct.rtx_def**> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll b/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll
new file mode 100644
index 0000000..ea27676
--- /dev/null
+++ b/test/CodeGen/ARM/2007-03-30-RegScavengerAssert.ll
@@ -0,0 +1,101 @@
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi
+; PR1279
+
+ %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 }
+ %struct.arm_stack_offsets = type { i32, i32, i32, i32, i32 }
+ %struct.eh_status = type opaque
+ %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }
+ %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+ %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 }
+ %struct.initial_value_struct = type opaque
+ %struct.lang_decl = type opaque
+ %struct.language_function = type opaque
+ %struct.location_t = type { i8*, i32 }
+ %struct.machine_function = type { %struct.rtx_def*, i32, i32, i32, %struct.arm_stack_offsets, i32, i32, i32, [14 x %struct.rtx_def*] }
+ %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }
+ %struct.rtx_def = type { i16, i8, i8, %struct.u }
+ %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
+ %struct.temp_slot = type opaque
+ %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 }
+ %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_decl_u1 = type { i64 }
+ %struct.tree_decl_u2 = type { %struct.function* }
+ %struct.tree_node = type { %struct.tree_decl }
+ %struct.u = type { [1 x i64] }
+ %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+ %struct.varasm_status = type opaque
+ %struct.varray_head_tag = type { i32, i32, i32, i8*, %struct.u }
+ %union.tree_ann_d = type opaque
+@str469 = external global [42 x i8] ; <[42 x i8]*> [#uses=0]
+@__FUNCTION__.24265 = external global [19 x i8] ; <[19 x i8]*> [#uses=0]
+
+declare void @fancy_abort()
+
+define fastcc void @fold_builtin_bitop() {
+entry:
+ br i1 false, label %cond_true105, label %UnifiedReturnBlock
+
+cond_true105: ; preds = %entry
+ br i1 false, label %cond_true134, label %UnifiedReturnBlock
+
+cond_true134: ; preds = %cond_true105
+ switch i32 0, label %bb479 [
+ i32 378, label %bb313
+ i32 380, label %bb313
+ i32 381, label %bb313
+ i32 383, label %bb366
+ i32 385, label %bb366
+ i32 386, label %bb366
+ i32 403, label %bb250
+ i32 405, label %bb250
+ i32 406, label %bb250
+ i32 434, label %bb464
+ i32 436, label %bb464
+ i32 437, label %bb464
+ i32 438, label %bb441
+ i32 440, label %bb441
+ i32 441, label %bb441
+ ]
+
+bb250: ; preds = %cond_true134, %cond_true134, %cond_true134
+ ret void
+
+bb313: ; preds = %cond_true134, %cond_true134, %cond_true134
+ ret void
+
+bb366: ; preds = %cond_true134, %cond_true134, %cond_true134
+ ret void
+
+bb441: ; preds = %cond_true134, %cond_true134, %cond_true134
+ ret void
+
+bb457: ; preds = %bb464, %bb457
+ %tmp459 = add i64 0, 1 ; <i64> [#uses=1]
+ br i1 false, label %bb474.preheader, label %bb457
+
+bb464: ; preds = %cond_true134, %cond_true134, %cond_true134
+ br i1 false, label %bb474.preheader, label %bb457
+
+bb474.preheader: ; preds = %bb464, %bb457
+ %result.5.ph = phi i64 [ 0, %bb464 ], [ %tmp459, %bb457 ] ; <i64> [#uses=1]
+ br label %bb474
+
+bb467: ; preds = %bb474
+ %indvar.next586 = add i64 %indvar585, 1 ; <i64> [#uses=1]
+ br label %bb474
+
+bb474: ; preds = %bb467, %bb474.preheader
+ %indvar585 = phi i64 [ 0, %bb474.preheader ], [ %indvar.next586, %bb467 ] ; <i64> [#uses=2]
+ br i1 false, label %bb476, label %bb467
+
+bb476: ; preds = %bb474
+ %result.5 = add i64 %indvar585, %result.5.ph ; <i64> [#uses=0]
+ ret void
+
+bb479: ; preds = %cond_true134
+ tail call void @fancy_abort( )
+ unreachable
+
+UnifiedReturnBlock: ; preds = %cond_true105, %entry
+ ret void
+}
diff --git a/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll b/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll
new file mode 100644
index 0000000..f24def3
--- /dev/null
+++ b/test/CodeGen/ARM/2007-04-02-RegScavengerAssert.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin
+
+ %struct.H_TBL = type { [17 x i8], [256 x i8], i32 }
+ %struct.Q_TBL = type { [64 x i16], i32 }
+ %struct.anon = type { [80 x i8] }
+ %struct.X_c_coef_ccler = type { void (%struct.X_Y*, i32)*, i32 (%struct.X_Y*, i8***)* }
+ %struct.X_c_main_ccler = type { void (%struct.X_Y*, i32)*, void (%struct.X_Y*, i8**, i32*, i32)* }
+ %struct.X_c_prep_ccler = type { void (%struct.X_Y*, i32)*, void (%struct.X_Y*, i8**, i32*, i32, i8***, i32*, i32)* }
+ %struct.X_color_converter = type { void (%struct.X_Y*)*, void (%struct.X_Y*, i8**, i8***, i32, i32)* }
+ %struct.X_common_struct = type { %struct.X_error_mgr*, %struct.X_memory_mgr*, %struct.X_progress_mgr*, i8*, i32, i32 }
+ %struct.X_comp_master = type { void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, i32, i32 }
+ %struct.X_component_info = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.Q_TBL*, i8* }
+ %struct.X_Y = type { %struct.X_error_mgr*, %struct.X_memory_mgr*, %struct.X_progress_mgr*, i8*, i32, i32, %struct.X_destination_mgr*, i32, i32, i32, i32, double, i32, i32, i32, %struct.X_component_info*, [4 x %struct.Q_TBL*], [4 x %struct.H_TBL*], [4 x %struct.H_TBL*], [16 x i8], [16 x i8], [16 x i8], i32, %struct.X_scan_info*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i16, i16, i32, i32, i32, i32, i32, i32, i32, [4 x %struct.X_component_info*], i32, i32, i32, [10 x i32], i32, i32, i32, i32, %struct.X_comp_master*, %struct.X_c_main_ccler*, %struct.X_c_prep_ccler*, %struct.X_c_coef_ccler*, %struct.X_marker_writer*, %struct.X_color_converter*, %struct.X_downssr*, %struct.X_forward_D*, %struct.X_entropy_en*, %struct.X_scan_info*, i32 }
+ %struct.X_destination_mgr = type { i8*, i32, void (%struct.X_Y*)*, i32 (%struct.X_Y*)*, void (%struct.X_Y*)* }
+ %struct.X_downssr = type { void (%struct.X_Y*)*, void (%struct.X_Y*, i8***, i32, i8***, i32)*, i32 }
+ %struct.X_entropy_en = type { void (%struct.X_Y*, i32)*, i32 (%struct.X_Y*, [64 x i16]**)*, void (%struct.X_Y*)* }
+ %struct.X_error_mgr = type { void (%struct.X_common_struct*)*, void (%struct.X_common_struct*, i32)*, void (%struct.X_common_struct*)*, void (%struct.X_common_struct*, i8*)*, void (%struct.X_common_struct*)*, i32, %struct.anon, i32, i32, i8**, i32, i8**, i32, i32 }
+ %struct.X_forward_D = type { void (%struct.X_Y*)*, void (%struct.X_Y*, %struct.X_component_info*, i8**, [64 x i16]*, i32, i32, i32)* }
+ %struct.X_marker_writer = type { void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*)*, void (%struct.X_Y*, i32, i32)*, void (%struct.X_Y*, i32)* }
+ %struct.X_memory_mgr = type { i8* (%struct.X_common_struct*, i32, i32)*, i8* (%struct.X_common_struct*, i32, i32)*, i8** (%struct.X_common_struct*, i32, i32, i32)*, [64 x i16]** (%struct.X_common_struct*, i32, i32, i32)*, %struct.jvirt_sAY_cc* (%struct.X_common_struct*, i32, i32, i32, i32, i32)*, %struct.jvirt_bAY_cc* (%struct.X_common_struct*, i32, i32, i32, i32, i32)*, void (%struct.X_common_struct*)*, i8** (%struct.X_common_struct*, %struct.jvirt_sAY_cc*, i32, i32, i32)*, [64 x i16]** (%struct.X_common_struct*, %struct.jvirt_bAY_cc*, i32, i32, i32)*, void (%struct.X_common_struct*, i32)*, void (%struct.X_common_struct*)*, i32, i32 }
+ %struct.X_progress_mgr = type { void (%struct.X_common_struct*)*, i32, i32, i32, i32 }
+ %struct.X_scan_info = type { i32, [4 x i32], i32, i32, i32, i32 }
+ %struct.jvirt_bAY_cc = type opaque
+ %struct.jvirt_sAY_cc = type opaque
+
+define void @test(%struct.X_Y* %cinfo) {
+entry:
+ br i1 false, label %bb.preheader, label %return
+
+bb.preheader: ; preds = %entry
+ %tbl.014.us = load i32* null ; <i32> [#uses=1]
+ br i1 false, label %cond_next.us, label %bb
+
+cond_next51.us: ; preds = %cond_next.us, %cond_true33.us.cond_true46.us_crit_edge
+ %htblptr.019.1.us = phi %struct.H_TBL** [ %tmp37.us, %cond_true33.us.cond_true46.us_crit_edge ], [ %tmp37.us, %cond_next.us ] ; <%struct.H_TBL**> [#uses=0]
+ ret void
+
+cond_true33.us.cond_true46.us_crit_edge: ; preds = %cond_next.us
+ call void @_C_X_a_HT( )
+ br label %cond_next51.us
+
+cond_next.us: ; preds = %bb.preheader
+ %tmp37.us = getelementptr %struct.X_Y* %cinfo, i32 0, i32 17, i32 %tbl.014.us ; <%struct.H_TBL**> [#uses=3]
+ %tmp4524.us = load %struct.H_TBL** %tmp37.us ; <%struct.H_TBL*> [#uses=1]
+ icmp eq %struct.H_TBL* %tmp4524.us, null ; <i1>:0 [#uses=1]
+ br i1 %0, label %cond_true33.us.cond_true46.us_crit_edge, label %cond_next51.us
+
+bb: ; preds = %bb.preheader
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
+
+declare void @_C_X_a_HT()
diff --git a/test/CodeGen/ARM/2007-04-03-PEIBug.ll b/test/CodeGen/ARM/2007-04-03-PEIBug.ll
new file mode 100644
index 0000000..b543c57
--- /dev/null
+++ b/test/CodeGen/ARM/2007-04-03-PEIBug.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=arm | not grep {add.*#0}
+
+define i32 @foo() {
+entry:
+ %A = alloca [1123 x i32], align 16 ; <[1123 x i32]*> [#uses=1]
+ %B = alloca [3123 x i32], align 16 ; <[3123 x i32]*> [#uses=1]
+ %C = alloca [12312 x i32], align 16 ; <[12312 x i32]*> [#uses=1]
+ %tmp = call i32 (...)* @bar( [3123 x i32]* %B, [1123 x i32]* %A, [12312 x i32]* %C ) ; <i32> [#uses=0]
+ ret i32 undef
+}
+
+declare i32 @bar(...)
diff --git a/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll b/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll
new file mode 100644
index 0000000..e001cde
--- /dev/null
+++ b/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll
@@ -0,0 +1,99 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | \
+; RUN: not grep LPC9
+
+ %struct.B = type { i32 }
+ %struct.anon = type { void (%struct.B*)*, i32 }
+@str = internal constant [7 x i8] c"i, %d\0A\00" ; <[7 x i8]*> [#uses=1]
+@str1 = internal constant [7 x i8] c"j, %d\0A\00" ; <[7 x i8]*> [#uses=1]
+
+define internal void @_ZN1B1iEv(%struct.B* %this) {
+entry:
+ %tmp1 = getelementptr %struct.B* %this, i32 0, i32 0 ; <i32*> [#uses=1]
+ %tmp2 = load i32* %tmp1 ; <i32> [#uses=1]
+ %tmp4 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8]* @str, i32 0, i32 0), i32 %tmp2 ) ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @printf(i8*, ...)
+
+define internal void @_ZN1B1jEv(%struct.B* %this) {
+entry:
+ %tmp1 = getelementptr %struct.B* %this, i32 0, i32 0 ; <i32*> [#uses=1]
+ %tmp2 = load i32* %tmp1 ; <i32> [#uses=1]
+ %tmp4 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8]* @str1, i32 0, i32 0), i32 %tmp2 ) ; <i32> [#uses=0]
+ ret void
+}
+
+define i32 @main() {
+entry:
+ %b.i29 = alloca %struct.B, align 4 ; <%struct.B*> [#uses=3]
+ %b.i1 = alloca %struct.B, align 4 ; <%struct.B*> [#uses=3]
+ %b.i = alloca %struct.B, align 4 ; <%struct.B*> [#uses=3]
+ %tmp2.i = getelementptr %struct.B* %b.i, i32 0, i32 0 ; <i32*> [#uses=1]
+ store i32 4, i32* %tmp2.i
+ br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit, label %cond_true.i
+
+cond_true.i: ; preds = %entry
+ %b2.i = bitcast %struct.B* %b.i to i8* ; <i8*> [#uses=1]
+ %ctg23.i = getelementptr i8* %b2.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1]
+ %tmp121314.i = bitcast i8* %ctg23.i to i32 (...)*** ; <i32 (...)***> [#uses=1]
+ %tmp15.i = load i32 (...)*** %tmp121314.i ; <i32 (...)**> [#uses=1]
+ %tmp151.i = bitcast i32 (...)** %tmp15.i to i8* ; <i8*> [#uses=1]
+ %ctg2.i = getelementptr i8* %tmp151.i, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) ; <i8*> [#uses=1]
+ %tmp2021.i = bitcast i8* %ctg2.i to i32 (...)** ; <i32 (...)**> [#uses=1]
+ %tmp22.i = load i32 (...)** %tmp2021.i ; <i32 (...)*> [#uses=1]
+ %tmp2223.i = bitcast i32 (...)* %tmp22.i to void (%struct.B*)* ; <void (%struct.B*)*> [#uses=1]
+ br label %_Z3fooiM1BFvvE.exit
+
+_Z3fooiM1BFvvE.exit: ; preds = %cond_true.i, %entry
+ %iftmp.2.0.i = phi void (%struct.B*)* [ %tmp2223.i, %cond_true.i ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to void (%struct.B*)*), %entry ] ; <void (%struct.B*)*> [#uses=1]
+ %b4.i = bitcast %struct.B* %b.i to i8* ; <i8*> [#uses=1]
+ %ctg25.i = getelementptr i8* %b4.i, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1]
+ %tmp3031.i = bitcast i8* %ctg25.i to %struct.B* ; <%struct.B*> [#uses=1]
+ call void %iftmp.2.0.i( %struct.B* %tmp3031.i )
+ %tmp2.i30 = getelementptr %struct.B* %b.i29, i32 0, i32 0 ; <i32*> [#uses=1]
+ store i32 6, i32* %tmp2.i30
+ br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit56, label %cond_true.i46
+
+cond_true.i46: ; preds = %_Z3fooiM1BFvvE.exit
+ %b2.i35 = bitcast %struct.B* %b.i29 to i8* ; <i8*> [#uses=1]
+ %ctg23.i36 = getelementptr i8* %b2.i35, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1]
+ %tmp121314.i37 = bitcast i8* %ctg23.i36 to i32 (...)*** ; <i32 (...)***> [#uses=1]
+ %tmp15.i38 = load i32 (...)*** %tmp121314.i37 ; <i32 (...)**> [#uses=1]
+ %tmp151.i41 = bitcast i32 (...)** %tmp15.i38 to i8* ; <i8*> [#uses=1]
+ %ctg2.i42 = getelementptr i8* %tmp151.i41, i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) ; <i8*> [#uses=1]
+ %tmp2021.i43 = bitcast i8* %ctg2.i42 to i32 (...)** ; <i32 (...)**> [#uses=1]
+ %tmp22.i44 = load i32 (...)** %tmp2021.i43 ; <i32 (...)*> [#uses=1]
+ %tmp2223.i45 = bitcast i32 (...)* %tmp22.i44 to void (%struct.B*)* ; <void (%struct.B*)*> [#uses=1]
+ br label %_Z3fooiM1BFvvE.exit56
+
+_Z3fooiM1BFvvE.exit56: ; preds = %cond_true.i46, %_Z3fooiM1BFvvE.exit
+ %iftmp.2.0.i49 = phi void (%struct.B*)* [ %tmp2223.i45, %cond_true.i46 ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to void (%struct.B*)*), %_Z3fooiM1BFvvE.exit ] ; <void (%struct.B*)*> [#uses=1]
+ %b4.i53 = bitcast %struct.B* %b.i29 to i8* ; <i8*> [#uses=1]
+ %ctg25.i54 = getelementptr i8* %b4.i53, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1jEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1]
+ %tmp3031.i55 = bitcast i8* %ctg25.i54 to %struct.B* ; <%struct.B*> [#uses=1]
+ call void %iftmp.2.0.i49( %struct.B* %tmp3031.i55 )
+ %tmp2.i2 = getelementptr %struct.B* %b.i1, i32 0, i32 0 ; <i32*> [#uses=1]
+ store i32 -1, i32* %tmp2.i2
+ br i1 icmp eq (i64 and (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 4294967296), i64 0), label %_Z3fooiM1BFvvE.exit28, label %cond_true.i18
+
+cond_true.i18: ; preds = %_Z3fooiM1BFvvE.exit56
+ %b2.i7 = bitcast %struct.B* %b.i1 to i8* ; <i8*> [#uses=1]
+ %ctg23.i8 = getelementptr i8* %b2.i7, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1]
+ %tmp121314.i9 = bitcast i8* %ctg23.i8 to i32 (...)*** ; <i32 (...)***> [#uses=1]
+ %tmp15.i10 = load i32 (...)*** %tmp121314.i9 ; <i32 (...)**> [#uses=1]
+ %tmp151.i13 = bitcast i32 (...)** %tmp15.i10 to i8* ; <i8*> [#uses=1]
+ %ctg2.i14 = getelementptr i8* %tmp151.i13, i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) ; <i8*> [#uses=1]
+ %tmp2021.i15 = bitcast i8* %ctg2.i14 to i32 (...)** ; <i32 (...)**> [#uses=1]
+ %tmp22.i16 = load i32 (...)** %tmp2021.i15 ; <i32 (...)*> [#uses=1]
+ %tmp2223.i17 = bitcast i32 (...)* %tmp22.i16 to void (%struct.B*)* ; <void (%struct.B*)*> [#uses=1]
+ br label %_Z3fooiM1BFvvE.exit28
+
+_Z3fooiM1BFvvE.exit28: ; preds = %cond_true.i18, %_Z3fooiM1BFvvE.exit56
+ %iftmp.2.0.i21 = phi void (%struct.B*)* [ %tmp2223.i17, %cond_true.i18 ], [ inttoptr (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to void (%struct.B*)*), %_Z3fooiM1BFvvE.exit56 ] ; <void (%struct.B*)*> [#uses=1]
+ %b4.i25 = bitcast %struct.B* %b.i1 to i8* ; <i8*> [#uses=1]
+ %ctg25.i26 = getelementptr i8* %b4.i25, i32 ashr (i32 trunc (i64 lshr (i64 zext (i32 ptrtoint (void (%struct.B*)* @_ZN1B1iEv to i32) to i64), i64 32) to i32), i32 1) ; <i8*> [#uses=1]
+ %tmp3031.i27 = bitcast i8* %ctg25.i26 to %struct.B* ; <%struct.B*> [#uses=1]
+ call void %iftmp.2.0.i21( %struct.B* %tmp3031.i27 )
+ ret i32 0
+}
diff --git a/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll b/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll
new file mode 100644
index 0000000..a89e937
--- /dev/null
+++ b/test/CodeGen/ARM/2007-04-30-CombinerCrash.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
+target triple = "arm-apple-darwin8"
+ %struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 }
+@search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=3]
+@file_mask = external global [8 x i64] ; <[8 x i64]*> [#uses=1]
+@rank_mask.1.b = external global i1 ; <i1*> [#uses=1]
+
+define fastcc void @EvaluateDevelopment() {
+entry:
+ %tmp7 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 7) ; <i64> [#uses=1]
+ %tmp50 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 0) ; <i64> [#uses=1]
+ %tmp52 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 1) ; <i64> [#uses=1]
+ %tmp53 = or i64 %tmp52, %tmp50 ; <i64> [#uses=1]
+ %tmp57.b = load i1* @rank_mask.1.b ; <i1> [#uses=1]
+ %tmp57 = select i1 %tmp57.b, i64 71776119061217280, i64 0 ; <i64> [#uses=1]
+ %tmp58 = and i64 %tmp57, %tmp7 ; <i64> [#uses=1]
+ %tmp59 = lshr i64 %tmp58, 8 ; <i64> [#uses=1]
+ %tmp63 = load i64* getelementptr ([8 x i64]* @file_mask, i32 0, i32 4) ; <i64> [#uses=1]
+ %tmp64 = or i64 %tmp63, 0 ; <i64> [#uses=1]
+ %tmp65 = and i64 %tmp59, %tmp53 ; <i64> [#uses=1]
+ %tmp66 = and i64 %tmp65, %tmp64 ; <i64> [#uses=1]
+ %tmp67 = icmp eq i64 %tmp66, 0 ; <i1> [#uses=1]
+ br i1 %tmp67, label %cond_next145, label %cond_true70
+
+cond_true70: ; preds = %entry
+ ret void
+
+cond_next145: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll b/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll
new file mode 100644
index 0000000..c73b6793
--- /dev/null
+++ b/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll
@@ -0,0 +1,113 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+ %struct.Connection = type { i32, [10 x i8], i32 }
+ %struct.IntChunk = type { %struct.cppobjtype, i32, i32*, i32 }
+ %struct.Point = type { i8*, %struct.cppobjtype, i16 (%struct.Point*) signext *, i16 (%struct.Point*) signext *, double (%struct.Point*)*, double (%struct.Point*)* }
+ %struct.RefPoint = type { %struct.Point*, %struct.cppobjtype }
+ %struct.ShortArray = type { %struct.cppobjtype, i32, i16* }
+ %struct.TestObj = type { i8*, %struct.cppobjtype, i8, [32 x i8], i8*, i8**, i16, i16, i32, i32, i32, i32, float, double, %struct.cppobjtype, i32, i16*, i16**, i8**, i32, %struct.XyPoint, [3 x %struct.Connection], %struct.Point*, %struct.XyPoint*, i32, i8*, i8*, i16*, %struct.ShortArray, %struct.IntChunk, %struct.cppobjtype, %struct.cppobjtype, %struct.RefPoint, i32, %struct.cppobjtype, %struct.cppobjtype }
+ %struct.XyPoint = type { i16, i16 }
+ %struct.cppobjtype = type { i32, i16, i16 }
+@Msg = external global [256 x i8] ; <[256 x i8]*> [#uses=1]
[email protected] = external constant [48 x i8] ; <[48 x i8]*> [#uses=1]
[email protected] = external global i1 ; <i1*> [#uses=1]
+
+define fastcc void @Draw7(i32 %Option, i32* %Status) {
+entry:
+ %tmp115.b = load i1* @FirstTime.4637.b ; <i1> [#uses=1]
+ br i1 %tmp115.b, label %cond_next239, label %cond_next.i
+
+cond_next.i: ; preds = %entry
+ ret void
+
+cond_next239: ; preds = %entry
+ %tmp242 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp242, label %cond_next253, label %cond_next296
+
+cond_next253: ; preds = %cond_next239
+ switch i32 %Option, label %bb1326 [
+ i32 3, label %cond_true258
+ i32 4, label %cond_true268
+ i32 2, label %cond_true279
+ i32 1, label %cond_next315
+ ]
+
+cond_true258: ; preds = %cond_next253
+ ret void
+
+cond_true268: ; preds = %cond_next253
+ ret void
+
+cond_true279: ; preds = %cond_next253
+ ret void
+
+cond_next296: ; preds = %cond_next239
+ ret void
+
+cond_next315: ; preds = %cond_next253
+ %tmp1140 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp1140, label %cond_true1143, label %bb1326
+
+cond_true1143: ; preds = %cond_next315
+ %tmp1148 = icmp eq i32 0, 0 ; <i1> [#uses=4]
+ br i1 %tmp1148, label %cond_next1153, label %cond_true1151
+
+cond_true1151: ; preds = %cond_true1143
+ ret void
+
+cond_next1153: ; preds = %cond_true1143
+ %tmp8.i.i185 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp8.i.i185, label %TestObj_new1.exit, label %cond_true.i.i187
+
+cond_true.i.i187: ; preds = %cond_next1153
+ ret void
+
+TestObj_new1.exit: ; preds = %cond_next1153
+ %tmp1167 = icmp eq i16 0, 0 ; <i1> [#uses=1]
+ %tmp1178 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ %bothcond = and i1 %tmp1167, %tmp1178 ; <i1> [#uses=1]
+ br i1 %bothcond, label %bb1199, label %bb1181
+
+bb1181: ; preds = %TestObj_new1.exit
+ ret void
+
+bb1199: ; preds = %TestObj_new1.exit
+ br i1 %tmp1148, label %cond_next1235, label %Object_Dump.exit302
+
+Object_Dump.exit302: ; preds = %bb1199
+ ret void
+
+cond_next1235: ; preds = %bb1199
+ %bothcond10485 = or i1 false, %tmp1148 ; <i1> [#uses=1]
+ br i1 %bothcond10485, label %cond_next1267, label %cond_true1248
+
+cond_true1248: ; preds = %cond_next1235
+ ret void
+
+cond_next1267: ; preds = %cond_next1235
+ br i1 %tmp1148, label %cond_next1275, label %cond_true1272
+
+cond_true1272: ; preds = %cond_next1267
+ %tmp1273 = load %struct.TestObj** null ; <%struct.TestObj*> [#uses=2]
+ %tmp2930.i = ptrtoint %struct.TestObj* %tmp1273 to i32 ; <i32> [#uses=1]
+ %tmp42.i348 = sub i32 0, %tmp2930.i ; <i32> [#uses=1]
+ %tmp45.i = getelementptr %struct.TestObj* %tmp1273, i32 0, i32 0 ; <i8**> [#uses=2]
+ %tmp48.i = load i8** %tmp45.i ; <i8*> [#uses=1]
+ %tmp50.i350 = call i32 (i8*, i8*, ...)* @sprintf( i8* getelementptr ([256 x i8]* @Msg, i32 0, i32 0), i8* getelementptr ([48 x i8]* @.str53615, i32 0, i32 0), i8* null, i8** %tmp45.i, i8* %tmp48.i ) ; <i32> [#uses=0]
+ br i1 false, label %cond_true.i632.i, label %Ut_TraceMsg.exit648.i
+
+cond_true.i632.i: ; preds = %cond_true1272
+ ret void
+
+Ut_TraceMsg.exit648.i: ; preds = %cond_true1272
+ %tmp57.i = getelementptr i8* null, i32 %tmp42.i348 ; <i8*> [#uses=0]
+ ret void
+
+cond_next1275: ; preds = %cond_next1267
+ ret void
+
+bb1326: ; preds = %cond_next315, %cond_next253
+ ret void
+}
+
+declare i32 @sprintf(i8*, i8*, ...)
diff --git a/test/CodeGen/ARM/2007-05-07-jumptoentry.ll b/test/CodeGen/ARM/2007-05-07-jumptoentry.ll
new file mode 100644
index 0000000..26864f1
--- /dev/null
+++ b/test/CodeGen/ARM/2007-05-07-jumptoentry.ll
@@ -0,0 +1,58 @@
+; RUN: llc < %s | not grep 1_0
+; This used to create an extra branch to 'entry', LBB1_0.
+
+; ModuleID = 'bug.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
+target triple = "arm-apple-darwin8"
+ %struct.HexxagonMove = type { i8, i8, i32 }
+ %struct.HexxagonMoveList = type { i32, %struct.HexxagonMove* }
+
+define void @_ZN16HexxagonMoveList8sortListEv(%struct.HexxagonMoveList* %this) {
+entry:
+ %tmp51 = getelementptr %struct.HexxagonMoveList* %this, i32 0, i32 0 ; <i32*> [#uses=1]
+ %tmp2 = getelementptr %struct.HexxagonMoveList* %this, i32 0, i32 1 ; <%struct.HexxagonMove**> [#uses=2]
+ br label %bb49
+
+bb1: ; preds = %bb49
+ %tmp3 = load %struct.HexxagonMove** %tmp2 ; <%struct.HexxagonMove*> [#uses=5]
+ %tmp6 = getelementptr %struct.HexxagonMove* %tmp3, i32 %i.1, i32 2 ; <i32*> [#uses=1]
+ %tmp7 = load i32* %tmp6 ; <i32> [#uses=2]
+ %tmp12 = add i32 %i.1, 1 ; <i32> [#uses=7]
+ %tmp14 = getelementptr %struct.HexxagonMove* %tmp3, i32 %tmp12, i32 2 ; <i32*> [#uses=1]
+ %tmp15 = load i32* %tmp14 ; <i32> [#uses=1]
+ %tmp16 = icmp slt i32 %tmp7, %tmp15 ; <i1> [#uses=1]
+ br i1 %tmp16, label %cond_true, label %bb49
+
+cond_true: ; preds = %bb1
+ %tmp23.0 = getelementptr %struct.HexxagonMove* %tmp3, i32 %i.1, i32 0 ; <i8*> [#uses=2]
+ %tmp67 = load i8* %tmp23.0 ; <i8> [#uses=1]
+ %tmp23.1 = getelementptr %struct.HexxagonMove* %tmp3, i32 %i.1, i32 1 ; <i8*> [#uses=1]
+ %tmp68 = load i8* %tmp23.1 ; <i8> [#uses=1]
+ %tmp3638 = getelementptr %struct.HexxagonMove* %tmp3, i32 %tmp12, i32 0 ; <i8*> [#uses=1]
+ tail call void @llvm.memcpy.i32( i8* %tmp23.0, i8* %tmp3638, i32 8, i32 4 )
+ %tmp41 = load %struct.HexxagonMove** %tmp2 ; <%struct.HexxagonMove*> [#uses=3]
+ %tmp44.0 = getelementptr %struct.HexxagonMove* %tmp41, i32 %tmp12, i32 0 ; <i8*> [#uses=1]
+ store i8 %tmp67, i8* %tmp44.0
+ %tmp44.1 = getelementptr %struct.HexxagonMove* %tmp41, i32 %tmp12, i32 1 ; <i8*> [#uses=1]
+ store i8 %tmp68, i8* %tmp44.1
+ %tmp44.2 = getelementptr %struct.HexxagonMove* %tmp41, i32 %tmp12, i32 2 ; <i32*> [#uses=1]
+ store i32 %tmp7, i32* %tmp44.2
+ br label %bb49
+
+bb49: ; preds = %bb59, %cond_true, %bb1, %entry
+ %i.1 = phi i32 [ 0, %entry ], [ %tmp12, %bb1 ], [ %tmp12, %cond_true ], [ 0, %bb59 ] ; <i32> [#uses=5]
+ %move.2 = phi i32 [ 0, %entry ], [ 1, %cond_true ], [ %move.2, %bb1 ], [ 0, %bb59 ] ; <i32> [#uses=2]
+ %tmp52 = load i32* %tmp51 ; <i32> [#uses=1]
+ %tmp53 = add i32 %tmp52, -1 ; <i32> [#uses=1]
+ %tmp55 = icmp sgt i32 %tmp53, %i.1 ; <i1> [#uses=1]
+ br i1 %tmp55, label %bb1, label %bb59
+
+bb59: ; preds = %bb49
+ %tmp61 = icmp eq i32 %move.2, 0 ; <i1> [#uses=1]
+ br i1 %tmp61, label %return, label %bb49
+
+return: ; preds = %bb59
+ ret void
+}
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32)
diff --git a/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll b/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll
new file mode 100644
index 0000000..f2a8ee1
--- /dev/null
+++ b/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll
@@ -0,0 +1,68 @@
+; RUN: llc < %s -march=arm -enable-tail-merge | grep bl.*baz | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge | grep bl.*quux | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge -enable-eh | grep bl.*baz | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge -enable-eh | grep bl.*quux | count 1
+; Check that calls to baz and quux are tail-merged.
+; PR1628
+
+; ModuleID = 'tail.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+
+define i32 @f(i32 %i, i32 %q) {
+entry:
+ %i_addr = alloca i32 ; <i32*> [#uses=2]
+ %q_addr = alloca i32 ; <i32*> [#uses=2]
+ %retval = alloca i32, align 4 ; <i32*> [#uses=1]
+ "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %i, i32* %i_addr
+ store i32 %q, i32* %q_addr
+ %tmp = load i32* %i_addr ; <i32> [#uses=1]
+ %tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
+ %tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1]
+ %toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1]
+ br i1 %toBool, label %cond_true, label %cond_false
+
+cond_true: ; preds = %entry
+ %tmp3 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
+ br label %cond_next
+
+cond_false: ; preds = %entry
+ %tmp5 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
+ %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
+ br label %cond_next
+
+cond_next: ; preds = %cond_false, %cond_true
+ %tmp7 = load i32* %q_addr ; <i32> [#uses=1]
+ %tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1]
+ %tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1]
+ %toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1]
+ br i1 %toBool10, label %cond_true11, label %cond_false15
+
+cond_true11: ; preds = %cond_next
+ %tmp13 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
+ %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
+ br label %cond_next18
+
+cond_false15: ; preds = %cond_next
+ %tmp16 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
+ br label %cond_next18
+
+cond_next18: ; preds = %cond_false15, %cond_true11
+ %tmp19 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ br label %return
+
+return: ; preds = %cond_next18
+ %retval20 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval20
+}
+
+declare i32 @bar(...)
+
+declare i32 @baz(...)
+
+declare i32 @foo(...)
+
+declare i32 @quux(...)
diff --git a/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll b/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll
new file mode 100644
index 0000000..2758505
--- /dev/null
+++ b/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll
@@ -0,0 +1,69 @@
+; RUN: llc < %s -march=arm -enable-tail-merge | grep bl.*baz | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge | grep bl.*quux | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge -enable-eh | grep bl.*baz | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge -enable-eh | grep bl.*quux | count 1
+; Check that calls to baz and quux are tail-merged.
+; PR1628
+
+; ModuleID = 'tail.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+
+define i32 @f(i32 %i, i32 %q) {
+entry:
+ %i_addr = alloca i32 ; <i32*> [#uses=2]
+ %q_addr = alloca i32 ; <i32*> [#uses=2]
+ %retval = alloca i32, align 4 ; <i32*> [#uses=1]
+ "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %i, i32* %i_addr
+ store i32 %q, i32* %q_addr
+ %tmp = load i32* %i_addr ; <i32> [#uses=1]
+ %tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
+ %tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1]
+ %toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1]
+ br i1 %toBool, label %cond_true, label %cond_false
+
+cond_true: ; preds = %entry
+ %tmp3 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
+ %tmp7 = load i32* %q_addr ; <i32> [#uses=1]
+ %tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1]
+ %tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1]
+ %toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1]
+ br i1 %toBool10, label %cond_true11, label %cond_false15
+
+cond_false: ; preds = %entry
+ %tmp5 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
+ %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
+ %tmp27 = load i32* %q_addr ; <i32> [#uses=1]
+ %tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1]
+ %tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1]
+ %toBool210 = icmp ne i8 %tmp289, 0 ; <i1> [#uses=1]
+ br i1 %toBool210, label %cond_true11, label %cond_false15
+
+cond_true11: ; preds = %cond_next
+ %tmp13 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
+ %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
+ br label %cond_next18
+
+cond_false15: ; preds = %cond_next
+ %tmp16 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
+ br label %cond_next18
+
+cond_next18: ; preds = %cond_false15, %cond_true11
+ %tmp19 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ br label %return
+
+return: ; preds = %cond_next18
+ %retval20 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval20
+}
+
+declare i32 @bar(...)
+
+declare i32 @baz(...)
+
+declare i32 @foo(...)
+
+declare i32 @quux(...)
diff --git a/test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll b/test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll
new file mode 100644
index 0000000..b3b07693
--- /dev/null
+++ b/test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=arm -mattr=+v6
+
+define i32 @test3() {
+ tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )
+ ret i32 11
+}
diff --git a/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll b/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll
new file mode 100644
index 0000000..7b15ded
--- /dev/null
+++ b/test/CodeGen/ARM/2007-05-14-RegScavengerAssert.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi
+; PR1406
+
+ %struct.AVClass = type { i8*, i8* (i8*)*, %struct.AVOption* }
+ %struct.AVCodec = type { i8*, i32, i32, i32, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32, i8*)*, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32*, i8*, i32)*, i32, %struct.AVCodec*, void (%struct.AVCodecContext*)*, %struct.AVRational*, i32* }
+ %struct.AVCodecContext = type { %struct.AVClass*, i32, i32, i32, i32, i32, i8*, i32, %struct.AVRational, i32, i32, i32, i32, i32, void (%struct.AVCodecContext*, %struct.AVFrame*, i32*, i32, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32, i32, i32, %struct.AVCodec*, i8*, i32, i32, void (%struct.AVCodecContext*, i8*, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, [32 x i8], i32, i32, i32, i32, i32, i32, i32, float, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, void (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i8*, i8*, float, float, i32, %struct.RcOverride*, i32, i8*, i32, i32, i32, float, float, float, float, i32, float, float, float, float, float, i32, i32, i32, i32*, i32, i32, i32, i32, %struct.AVRational, %struct.AVFrame*, i32, i32, [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32*)*, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i16*, i16*, i32, i32, i32, i32, %struct.AVPaletteControl*, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32 (%struct.AVCodecContext*, i8*)*, i8**, i32*, i32)*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64 }
+ %struct.AVFrame = type { [4 x i8*], [4 x i32], [4 x i8*], i32, i32, i64, i32, i32, i32, i32, i32, i8*, i32, i8*, [2 x [2 x i16]*], i32*, i8, i8*, [4 x i64], i32, i32, i32, i32, i32, %struct.AVPanScan*, i32, i32, i16*, [2 x i8*] }
+ %struct.AVOption = type opaque
+ %struct.AVPaletteControl = type { i32, [256 x i32] }
+ %struct.AVPanScan = type { i32, i32, i32, [3 x [2 x i16]] }
+ %struct.AVRational = type { i32, i32 }
+ %struct.RcOverride = type { i32, i32, i32, float }
+
+define i32 @decode_init(%struct.AVCodecContext* %avctx) {
+entry:
+ br i1 false, label %bb, label %cond_next789
+
+bb: ; preds = %bb, %entry
+ br i1 false, label %bb59, label %bb
+
+bb59: ; preds = %bb
+ %tmp68 = sdiv i64 0, 0 ; <i64> [#uses=1]
+ %tmp6869 = trunc i64 %tmp68 to i32 ; <i32> [#uses=2]
+ %tmp81 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, $1, lsl $5\0A\09", "=&r,=*&r,r,r,i,i"( i32* null, i32 %tmp6869, i32 13316085, i32 23, i32 9 ) ; <i32> [#uses=0]
+ %tmp90 = call i32 asm "smull $0, $1, $2, $3 \0A\09mov $0, $0, lsr $4\0A\09add $1, $0, $1, lsl $5\0A\09", "=&r,=*&r,r,r,i,i"( i32* null, i32 %tmp6869, i32 10568984, i32 23, i32 9 ) ; <i32> [#uses=0]
+ unreachable
+
+cond_next789: ; preds = %entry
+ ret i32 0
+}
diff --git a/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll b/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll
new file mode 100644
index 0000000..061bf5e
--- /dev/null
+++ b/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll
@@ -0,0 +1,73 @@
+; RUN: llc < %s -march=arm | grep bl.*baz | count 1
+; RUN: llc < %s -march=arm | grep bl.*quux | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge=0 | grep bl.*baz | count 2
+; RUN: llc < %s -march=arm -enable-tail-merge=0 | grep bl.*quux | count 2
+; RUN: llc < %s -march=arm -enable-eh | grep bl.*baz | count 1
+; RUN: llc < %s -march=arm -enable-eh | grep bl.*quux | count 1
+; RUN: llc < %s -march=arm -enable-tail-merge=0 -enable-eh | grep bl.*baz | count 2
+; RUN: llc < %s -march=arm -enable-tail-merge=0 -enable-eh | grep bl.*quux | count 2
+; Check that tail merging is the default on ARM, and that -enable-tail-merge=0 works.
+; PR1628
+
+; ModuleID = 'tail.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+
+define i32 @f(i32 %i, i32 %q) {
+entry:
+ %i_addr = alloca i32 ; <i32*> [#uses=2]
+ %q_addr = alloca i32 ; <i32*> [#uses=2]
+ %retval = alloca i32, align 4 ; <i32*> [#uses=1]
+ "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %i, i32* %i_addr
+ store i32 %q, i32* %q_addr
+ %tmp = load i32* %i_addr ; <i32> [#uses=1]
+ %tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
+ %tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1]
+ %toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1]
+ br i1 %toBool, label %cond_true, label %cond_false
+
+cond_true: ; preds = %entry
+ %tmp3 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
+ %tmp7 = load i32* %q_addr ; <i32> [#uses=1]
+ %tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1]
+ %tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1]
+ %toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1]
+ br i1 %toBool10, label %cond_true11, label %cond_false15
+
+cond_false: ; preds = %entry
+ %tmp5 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
+ %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
+ %tmp27 = load i32* %q_addr ; <i32> [#uses=1]
+ %tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1]
+ %tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1]
+ %toBool210 = icmp ne i8 %tmp289, 0 ; <i1> [#uses=1]
+ br i1 %toBool210, label %cond_true11, label %cond_false15
+
+cond_true11: ; preds = %cond_next
+ %tmp13 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
+ %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
+ br label %cond_next18
+
+cond_false15: ; preds = %cond_next
+ %tmp16 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
+ br label %cond_next18
+
+cond_next18: ; preds = %cond_false15, %cond_true11
+ %tmp19 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ br label %return
+
+return: ; preds = %cond_next18
+ %retval20 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval20
+}
+
+declare i32 @bar(...)
+
+declare i32 @baz(...)
+
+declare i32 @foo(...)
+
+declare i32 @quux(...)
diff --git a/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll b/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll
new file mode 100644
index 0000000..d2eb85d
--- /dev/null
+++ b/test/CodeGen/ARM/2007-05-23-BadPreIndexedStore.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=arm | not grep {str.*\\!}
+
+ %struct.shape_edge_t = type { %struct.shape_edge_t*, %struct.shape_edge_t*, i32, i32, i32, i32 }
+ %struct.shape_path_t = type { %struct.shape_edge_t*, %struct.shape_edge_t*, i32, i32, i32, i32, i32, i32 }
+ %struct.shape_pool_t = type { i8* (%struct.shape_pool_t*, i8*, i32)*, i8* (%struct.shape_pool_t*, i32)*, void (%struct.shape_pool_t*, i8*)* }
+
+define %struct.shape_path_t* @shape_path_alloc(%struct.shape_pool_t* %pool, i32* %shape) {
+entry:
+ br i1 false, label %cond_false, label %bb45
+
+bb45: ; preds = %entry
+ ret %struct.shape_path_t* null
+
+cond_false: ; preds = %entry
+ br i1 false, label %bb140, label %bb174
+
+bb140: ; preds = %bb140, %cond_false
+ %indvar = phi i32 [ 0, %cond_false ], [ %indvar.next, %bb140 ] ; <i32> [#uses=2]
+ %edge.230.0.rec = shl i32 %indvar, 1 ; <i32> [#uses=3]
+ %edge.230.0 = getelementptr %struct.shape_edge_t* null, i32 %edge.230.0.rec ; <%struct.shape_edge_t*> [#uses=1]
+ %edge.230.0.sum6970 = or i32 %edge.230.0.rec, 1 ; <i32> [#uses=2]
+ %tmp154 = getelementptr %struct.shape_edge_t* null, i32 %edge.230.0.sum6970 ; <%struct.shape_edge_t*> [#uses=1]
+ %tmp11.i5 = getelementptr %struct.shape_edge_t* null, i32 %edge.230.0.sum6970, i32 0 ; <%struct.shape_edge_t**> [#uses=1]
+ store %struct.shape_edge_t* %edge.230.0, %struct.shape_edge_t** %tmp11.i5
+ store %struct.shape_edge_t* %tmp154, %struct.shape_edge_t** null
+ %tmp16254.0.rec = add i32 %edge.230.0.rec, 2 ; <i32> [#uses=1]
+ %xp.350.sum = add i32 0, %tmp16254.0.rec ; <i32> [#uses=1]
+ %tmp168 = icmp slt i32 %xp.350.sum, 0 ; <i1> [#uses=1]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br i1 %tmp168, label %bb140, label %bb174
+
+bb174: ; preds = %bb140, %cond_false
+ ret %struct.shape_path_t* null
+}
diff --git a/test/CodeGen/ARM/2007-05-31-RegScavengerInfiniteLoop.ll b/test/CodeGen/ARM/2007-05-31-RegScavengerInfiniteLoop.ll
new file mode 100644
index 0000000..030486a
--- /dev/null
+++ b/test/CodeGen/ARM/2007-05-31-RegScavengerInfiniteLoop.ll
@@ -0,0 +1,237 @@
+; RUN: llc < %s
+; PR1424
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "arm-linux-gnueabi"
+ %struct.AVClass = type { i8*, i8* (i8*)*, %struct.AVOption* }
+ %struct.AVCodec = type { i8*, i32, i32, i32, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32, i8*)*, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32*, i8*, i32)*, i32, %struct.AVCodec*, void (%struct.AVCodecContext*)*, %struct.AVRational*, i32* }
+ %struct.AVCodecContext = type { %struct.AVClass*, i32, i32, i32, i32, i32, i8*, i32, %struct.AVRational, i32, i32, i32, i32, i32, void (%struct.AVCodecContext*, %struct.AVFrame*, i32*, i32, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32, i32, i32, %struct.AVCodec*, i8*, i32, i32, void (%struct.AVCodecContext*, i8*, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, [32 x i8], i32, i32, i32, i32, i32, i32, i32, float, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, void (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i8*, i8*, float, float, i32, %struct.RcOverride*, i32, i8*, i32, i32, i32, float, float, float, float, i32, float, float, float, float, float, i32, i32, i32, i32*, i32, i32, i32, i32, %struct.AVRational, %struct.AVFrame*, i32, i32, [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32*)*, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i16*, i16*, i32, i32, i32, i32, %struct.AVPaletteControl*, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32 (%struct.AVCodecContext*, i8*)*, i8**, i32*, i32)*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64 }
+ %struct.AVEvalExpr = type opaque
+ %struct.AVFrame = type { [4 x i8*], [4 x i32], [4 x i8*], i32, i32, i64, i32, i32, i32, i32, i32, i8*, i32, i8*, [2 x [2 x i16]*], i32*, i8, i8*, [4 x i64], i32, i32, i32, i32, i32, %struct.AVPanScan*, i32, i32, i16*, [2 x i8*] }
+ %struct.AVOption = type opaque
+ %struct.AVPaletteControl = type { i32, [256 x i32] }
+ %struct.AVPanScan = type { i32, i32, i32, [3 x [2 x i16]] }
+ %struct.AVRational = type { i32, i32 }
+ %struct.BlockNode = type { i16, i16, i8, [3 x i8], i8, i8 }
+ %struct.DSPContext = type { void (i16*, i8*, i32)*, void (i16*, i8*, i8*, i32)*, void (i16*, i8*, i32)*, void (i16*, i8*, i32)*, void (i16*, i8*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, i32 (i16*)*, void (i8*, i8*, i32, i32, i32, i32, i32)*, void (i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)*, void (i16*)*, i32 (i8*, i32)*, i32 (i8*, i32)*, [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], i32 (i8*, i16*, i32)*, [4 x [4 x void (i8*, i8*, i32, i32)*]], [4 x [4 x void (i8*, i8*, i32, i32)*]], [4 x [4 x void (i8*, i8*, i32, i32)*]], [4 x [4 x void (i8*, i8*, i32, i32)*]], [2 x void (i8*, i8*, i8*, i32, i32)*], [11 x void (i8*, i8*, i32, i32, i32)*], [11 x void (i8*, i8*, i32, i32, i32)*], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], [8 x void (i8*, i8*, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [10 x void (i8*, i32, i32, i32, i32)*], [10 x void (i8*, i8*, i32, i32, i32, i32, i32)*], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i16*, i32)*, [2 x [4 x i32 (i8*, i8*, i8*, i32, i32)*]], void (i8*, i8*, i32)*, void (i8*, i8*, i8*, i32)*, void (i8*, i8*, i8*, i32, i32*, i32*)*, void (i32*, i32*, i32)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32)*, void (i8*, i32, i32, i32)*, void ([4 x [4 x i16]]*, i8*, [40 x i8]*, [40 x [2 x i16]]*, i32, i32, i32, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32)*, void (float*, float*, i32)*, void (float*, float*, i32)*, void (float*, float*, float*, i32)*, void (float*, float*, float*, float*, i32, i32, i32)*, void (i16*, float*, i32)*, void (i16*)*, void (i16*)*, void (i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, [64 x i8], i32, i32 (i16*, i16*, i16*, i32)*, void (i16*, i16*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void ([4 x i16]*)*, void (i32*, i32*, i32*, i32*, i32*, i32*, i32)*, void (i32*, i32)*, void (i8*, i32, i8**, i32, i32, i32, i32, i32, %struct.slice_buffer*, i32, i8*)*, void (i8*, i32, i32)*, [4 x void (i8*, i32, i8*, i32, i32, i32)*], void (i16*)*, void (i16*, i32)*, void (i16*, i32)*, void (i16*, i32)*, void (i8*, i32)*, void (i8*, i32)*, [16 x void (i8*, i8*, i32, i32)*] }
+ %struct.FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct.FILE*, i32, i32, i32, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i32, i32, [40 x i8] }
+ %struct.GetBitContext = type { i8*, i8*, i32*, i32, i32, i32, i32 }
+ %struct.MJpegContext = type opaque
+ %struct.MotionEstContext = type { %struct.AVCodecContext*, i32, [4 x [2 x i32]], [4 x [2 x i32]], i8*, i8*, [2 x i8*], i8*, i32, i32*, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x [4 x i8*]], [4 x [4 x i8*]], i32, i32, i32, i32, i32, [4 x void (i8*, i8*, i32, i32)*]*, [4 x void (i8*, i8*, i32, i32)*]*, [16 x void (i8*, i8*, i32)*]*, [16 x void (i8*, i8*, i32)*]*, [4097 x i8]*, i8*, i32 (%struct.MpegEncContext*, i32*, i32*, i32, i32, i32, i32, i32)* }
+ %struct.MpegEncContext = type { %struct.AVCodecContext*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.PutBitContext, i32, i32, i32, i32, i32, i32, i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.Picture*, %struct.Picture**, %struct.Picture**, i32, i32, [8 x %struct.MpegEncContext*], %struct.Picture, %struct.Picture, %struct.Picture, %struct.Picture, %struct.Picture*, %struct.Picture*, %struct.Picture*, [3 x i8*], [3 x i32], i16*, [3 x i16*], [20 x i16], i32, i32, i8*, i8*, i8*, i8*, i8*, [16 x i16]*, [3 x [16 x i16]*], i32, i8*, i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32*, i32, i32, i32, i32, i32, i32, i32, [5 x i32], i32, i32, i32, i32, %struct.DSPContext, i32, i32, [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x [2 x [2 x i16]*]], [2 x [2 x [2 x [2 x i16]*]]], [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x [2 x [2 x i16]*]], [2 x [2 x [2 x [2 x i16]*]]], [2 x i8*], [2 x [2 x i8*]], i32, i32, i32, [2 x [4 x [2 x i32]]], [2 x [2 x i32]], [2 x [2 x [2 x i32]]], i8*, [2 x [64 x i16]], %struct.MotionEstContext, i32, i32, i32, i32, i32, i32, i16*, [6 x i32], [6 x i32], [3 x i8*], i32*, [64 x i16], [64 x i16], [64 x i16], [64 x i16], i32, i32, i32, i32, i32, i8*, i8*, i8*, i8*, i8*, i8*, [8 x i32], [64 x i32]*, [64 x i32]*, [2 x [64 x i16]]*, [2 x [64 x i16]]*, [12 x i32], %struct.ScanTable, %struct.ScanTable, %struct.ScanTable, %struct.ScanTable, [64 x i32]*, [2 x i32], [64 x i16]*, i8*, i64, i64, i32, i32, %struct.RateControlContext, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i32, i32, %struct.GetBitContext, i32, i32, i32, %struct.ParseContext, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i16, i16, i16, i16, i32, i32, i32, i32, i32, i32, i32, i32, i32, [2 x [2 x i32]], [2 x [2 x i32]], [2 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.PutBitContext, %struct.PutBitContext, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, i32, [3 x i32], %struct.MJpegContext*, [3 x i32], [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [2 x [65 x [65 x [2 x i32]]]]*, i32, i32, %struct.GetBitContext, i32, i32, i32, i8*, i32, [2 x [2 x i32]], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [2 x i32], i32, i32, i32, i32, i8*, i32, [12 x i16*], [64 x i16]*, [8 x [64 x i16]]*, i32 (%struct.MpegEncContext*, [64 x i16]*)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, i32 (%struct.MpegEncContext*, i16*, i32, i32, i32*)*, i32 (%struct.MpegEncContext*, i16*, i32, i32, i32*)*, void (%struct.MpegEncContext*, i16*)* }
+ %struct.ParseContext = type { i8*, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.Picture = type { [4 x i8*], [4 x i32], [4 x i8*], i32, i32, i64, i32, i32, i32, i32, i32, i8*, i32, i8*, [2 x [2 x i16]*], i32*, i8, i8*, [4 x i64], i32, i32, i32, i32, i32, %struct.AVPanScan*, i32, i32, i16*, [2 x i8*], [3 x i8*], [2 x [2 x i16]*], i32*, [2 x i32], i32, i32, i32, i32, [2 x [16 x i32]], [2 x i32], i32, i32, i16*, i16*, i8*, i32*, i32 }
+ %struct.Plane = type { i32, i32, [8 x [4 x %struct.SubBand]] }
+ %struct.Predictor = type { double, double, double }
+ %struct.PutBitContext = type { i32, i32, i8*, i8*, i8* }
+ %struct.RangeCoder = type { i32, i32, i32, i32, [256 x i8], [256 x i8], i8*, i8*, i8* }
+ %struct.RateControlContext = type { %struct.FILE*, i32, %struct.RateControlEntry*, double, [5 x %struct.Predictor], double, double, double, double, double, [5 x double], i32, i32, [5 x i64], [5 x i64], [5 x i64], [5 x i64], [5 x i32], i32, i8*, float, i32, %struct.AVEvalExpr* }
+ %struct.RateControlEntry = type { i32, float, i32, i32, i32, i32, i32, i64, i32, float, i32, i32, i32, i32, i32, i32 }
+ %struct.RcOverride = type { i32, i32, i32, float }
+ %struct.ScanTable = type { i8*, [64 x i8], [64 x i8] }
+ %struct.SnowContext = type { %struct.AVCodecContext*, %struct.RangeCoder, %struct.DSPContext, %struct.AVFrame, %struct.AVFrame, %struct.AVFrame, [8 x %struct.AVFrame], %struct.AVFrame, [32 x i8], [4224 x i8], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [8 x [2 x i16]*], [8 x i32*], i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x %struct.Plane], %struct.BlockNode*, [1024 x i32], i32, %struct.slice_buffer, %struct.MpegEncContext }
+ %struct.SubBand = type { i32, i32, i32, i32, i32, i32*, i32, i32, i32, %struct.x_and_coeff*, %struct.SubBand*, [519 x [32 x i8]] }
+ %struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 }
+ %struct.slice_buffer = type { i32**, i32**, i32, i32, i32, i32, i32* }
+ %struct.x_and_coeff = type { i16, i16 }
+
+define fastcc void @iterative_me(%struct.SnowContext* %s) {
+entry:
+ %state = alloca [4224 x i8], align 8 ; <[4224 x i8]*> [#uses=0]
+ %best_rd4233 = alloca i32, align 4 ; <i32*> [#uses=0]
+ %tmp21 = getelementptr %struct.SnowContext* %s, i32 0, i32 36 ; <i32*> [#uses=2]
+ br label %bb4198
+
+bb79: ; preds = %bb4189.preheader
+ br i1 false, label %cond_next239, label %cond_true
+
+cond_true: ; preds = %bb79
+ ret void
+
+cond_next239: ; preds = %bb79
+ %tmp286 = alloca i8, i32 0 ; <i8*> [#uses=0]
+ ret void
+
+bb4198: ; preds = %bb4189.preheader, %entry
+ br i1 false, label %bb4189.preheader, label %bb4204
+
+bb4189.preheader: ; preds = %bb4198
+ br i1 false, label %bb79, label %bb4198
+
+bb4204: ; preds = %bb4198
+ br i1 false, label %bb4221, label %cond_next4213
+
+cond_next4213: ; preds = %bb4204
+ ret void
+
+bb4221: ; preds = %bb4204
+ br i1 false, label %bb5242.preheader, label %UnifiedReturnBlock
+
+bb5242.preheader: ; preds = %bb4221
+ br label %bb5242
+
+bb4231: ; preds = %bb5233
+ %tmp4254.sum = add i32 0, 1 ; <i32> [#uses=2]
+ br i1 false, label %bb4559, label %cond_next4622
+
+bb4559: ; preds = %bb4231
+ ret void
+
+cond_next4622: ; preds = %bb4231
+ %tmp4637 = load i16* null ; <i16> [#uses=1]
+ %tmp46374638 = sext i16 %tmp4637 to i32 ; <i32> [#uses=1]
+ %tmp4642 = load i16* null ; <i16> [#uses=1]
+ %tmp46424643 = sext i16 %tmp4642 to i32 ; <i32> [#uses=1]
+ %tmp4648 = load i16* null ; <i16> [#uses=1]
+ %tmp46484649 = sext i16 %tmp4648 to i32 ; <i32> [#uses=1]
+ %tmp4653 = getelementptr %struct.BlockNode* null, i32 %tmp4254.sum, i32 0 ; <i16*> [#uses=1]
+ %tmp4654 = load i16* %tmp4653 ; <i16> [#uses=1]
+ %tmp46544655 = sext i16 %tmp4654 to i32 ; <i32> [#uses=1]
+ %tmp4644 = add i32 %tmp46374638, 2 ; <i32> [#uses=1]
+ %tmp4650 = add i32 %tmp4644, %tmp46424643 ; <i32> [#uses=1]
+ %tmp4656 = add i32 %tmp4650, %tmp46484649 ; <i32> [#uses=1]
+ %tmp4657 = add i32 %tmp4656, %tmp46544655 ; <i32> [#uses=2]
+ %tmp4658 = ashr i32 %tmp4657, 2 ; <i32> [#uses=1]
+ %tmp4662 = load i16* null ; <i16> [#uses=1]
+ %tmp46624663 = sext i16 %tmp4662 to i32 ; <i32> [#uses=1]
+ %tmp4672 = getelementptr %struct.BlockNode* null, i32 0, i32 1 ; <i16*> [#uses=1]
+ %tmp4673 = load i16* %tmp4672 ; <i16> [#uses=1]
+ %tmp46734674 = sext i16 %tmp4673 to i32 ; <i32> [#uses=1]
+ %tmp4678 = getelementptr %struct.BlockNode* null, i32 %tmp4254.sum, i32 1 ; <i16*> [#uses=1]
+ %tmp4679 = load i16* %tmp4678 ; <i16> [#uses=1]
+ %tmp46794680 = sext i16 %tmp4679 to i32 ; <i32> [#uses=1]
+ %tmp4669 = add i32 %tmp46624663, 2 ; <i32> [#uses=1]
+ %tmp4675 = add i32 %tmp4669, 0 ; <i32> [#uses=1]
+ %tmp4681 = add i32 %tmp4675, %tmp46734674 ; <i32> [#uses=1]
+ %tmp4682 = add i32 %tmp4681, %tmp46794680 ; <i32> [#uses=2]
+ %tmp4683 = ashr i32 %tmp4682, 2 ; <i32> [#uses=1]
+ %tmp4703 = load i32* %tmp21 ; <i32> [#uses=1]
+ %tmp4707 = shl i32 %tmp4703, 0 ; <i32> [#uses=4]
+ %tmp4710 = load %struct.BlockNode** null ; <%struct.BlockNode*> [#uses=6]
+ %tmp4713 = mul i32 %tmp4707, %mb_y.4 ; <i32> [#uses=1]
+ %tmp4715 = add i32 %tmp4713, %mb_x.7 ; <i32> [#uses=7]
+ store i8 0, i8* null
+ store i8 0, i8* null
+ %tmp47594761 = bitcast %struct.BlockNode* null to i8* ; <i8*> [#uses=2]
+ call void @llvm.memcpy.i32( i8* null, i8* %tmp47594761, i32 10, i32 0 )
+ %tmp4716.sum5775 = add i32 %tmp4715, 1 ; <i32> [#uses=1]
+ %tmp4764 = getelementptr %struct.BlockNode* %tmp4710, i32 %tmp4716.sum5775 ; <%struct.BlockNode*> [#uses=1]
+ %tmp47644766 = bitcast %struct.BlockNode* %tmp4764 to i8* ; <i8*> [#uses=1]
+ %tmp4716.sum5774 = add i32 %tmp4715, %tmp4707 ; <i32> [#uses=0]
+ %tmp47704772 = bitcast %struct.BlockNode* null to i8* ; <i8*> [#uses=1]
+ %tmp4774 = add i32 %tmp4707, 1 ; <i32> [#uses=1]
+ %tmp4716.sum5773 = add i32 %tmp4774, %tmp4715 ; <i32> [#uses=1]
+ %tmp4777 = getelementptr %struct.BlockNode* %tmp4710, i32 %tmp4716.sum5773 ; <%struct.BlockNode*> [#uses=1]
+ %tmp47774779 = bitcast %struct.BlockNode* %tmp4777 to i8* ; <i8*> [#uses=1]
+ %tmp4781 = icmp slt i32 %mb_x.7, 0 ; <i1> [#uses=1]
+ %tmp4788 = or i1 %tmp4781, %tmp4784 ; <i1> [#uses=2]
+ br i1 %tmp4788, label %cond_true4791, label %cond_next4794
+
+cond_true4791: ; preds = %cond_next4622
+ unreachable
+
+cond_next4794: ; preds = %cond_next4622
+ %tmp4797 = icmp slt i32 %mb_x.7, %tmp4707 ; <i1> [#uses=1]
+ br i1 %tmp4797, label %cond_next4803, label %cond_true4800
+
+cond_true4800: ; preds = %cond_next4794
+ unreachable
+
+cond_next4803: ; preds = %cond_next4794
+ %tmp4825 = ashr i32 %tmp4657, 12 ; <i32> [#uses=1]
+ shl i32 %tmp4682, 4 ; <i32>:0 [#uses=1]
+ %tmp4828 = and i32 %0, -64 ; <i32> [#uses=1]
+ %tmp4831 = getelementptr %struct.BlockNode* %tmp4710, i32 %tmp4715, i32 2 ; <i8*> [#uses=0]
+ %tmp4826 = add i32 %tmp4828, %tmp4825 ; <i32> [#uses=1]
+ %tmp4829 = add i32 %tmp4826, 0 ; <i32> [#uses=1]
+ %tmp4835 = add i32 %tmp4829, 0 ; <i32> [#uses=1]
+ store i32 %tmp4835, i32* null
+ %tmp48534854 = trunc i32 %tmp4658 to i16 ; <i16> [#uses=1]
+ %tmp4856 = getelementptr %struct.BlockNode* %tmp4710, i32 %tmp4715, i32 0 ; <i16*> [#uses=1]
+ store i16 %tmp48534854, i16* %tmp4856
+ %tmp48574858 = trunc i32 %tmp4683 to i16 ; <i16> [#uses=1]
+ %tmp4860 = getelementptr %struct.BlockNode* %tmp4710, i32 %tmp4715, i32 1 ; <i16*> [#uses=1]
+ store i16 %tmp48574858, i16* %tmp4860
+ %tmp4866 = getelementptr %struct.BlockNode* %tmp4710, i32 %tmp4715, i32 4 ; <i8*> [#uses=0]
+ br i1 false, label %bb4933, label %cond_false4906
+
+cond_false4906: ; preds = %cond_next4803
+ call void @llvm.memcpy.i32( i8* %tmp47594761, i8* null, i32 10, i32 0 )
+ call void @llvm.memcpy.i32( i8* %tmp47644766, i8* null, i32 10, i32 0 )
+ call void @llvm.memcpy.i32( i8* %tmp47704772, i8* null, i32 10, i32 0 )
+ call void @llvm.memcpy.i32( i8* %tmp47774779, i8* null, i32 10, i32 0 )
+ br label %bb5215
+
+bb4933: ; preds = %bb5215, %cond_next4803
+ br i1 false, label %cond_true4944, label %bb5215
+
+cond_true4944: ; preds = %bb4933
+ %tmp4982 = load i32* %tmp21 ; <i32> [#uses=1]
+ %tmp4986 = shl i32 %tmp4982, 0 ; <i32> [#uses=2]
+ %tmp4992 = mul i32 %tmp4986, %mb_y.4 ; <i32> [#uses=1]
+ %tmp4994 = add i32 %tmp4992, %mb_x.7 ; <i32> [#uses=5]
+ %tmp4995.sum5765 = add i32 %tmp4994, 1 ; <i32> [#uses=1]
+ %tmp5043 = getelementptr %struct.BlockNode* null, i32 %tmp4995.sum5765 ; <%struct.BlockNode*> [#uses=1]
+ %tmp50435045 = bitcast %struct.BlockNode* %tmp5043 to i8* ; <i8*> [#uses=2]
+ call void @llvm.memcpy.i32( i8* null, i8* %tmp50435045, i32 10, i32 0 )
+ %tmp4995.sum5764 = add i32 %tmp4994, %tmp4986 ; <i32> [#uses=1]
+ %tmp5049 = getelementptr %struct.BlockNode* null, i32 %tmp4995.sum5764 ; <%struct.BlockNode*> [#uses=1]
+ %tmp50495051 = bitcast %struct.BlockNode* %tmp5049 to i8* ; <i8*> [#uses=2]
+ call void @llvm.memcpy.i32( i8* null, i8* %tmp50495051, i32 10, i32 0 )
+ %tmp4995.sum5763 = add i32 0, %tmp4994 ; <i32> [#uses=1]
+ %tmp5056 = getelementptr %struct.BlockNode* null, i32 %tmp4995.sum5763 ; <%struct.BlockNode*> [#uses=1]
+ %tmp50565058 = bitcast %struct.BlockNode* %tmp5056 to i8* ; <i8*> [#uses=1]
+ br i1 %tmp4788, label %cond_true5070, label %cond_next5073
+
+cond_true5070: ; preds = %cond_true4944
+ unreachable
+
+cond_next5073: ; preds = %cond_true4944
+ %tmp5139 = getelementptr %struct.BlockNode* null, i32 %tmp4994, i32 1 ; <i16*> [#uses=0]
+ %tmp5145 = getelementptr %struct.BlockNode* null, i32 %tmp4994, i32 4 ; <i8*> [#uses=0]
+ call void @llvm.memcpy.i32( i8* %tmp50435045, i8* null, i32 10, i32 0 )
+ call void @llvm.memcpy.i32( i8* %tmp50495051, i8* null, i32 10, i32 0 )
+ call void @llvm.memcpy.i32( i8* %tmp50565058, i8* null, i32 10, i32 0 )
+ br label %bb5215
+
+bb5215: ; preds = %cond_next5073, %bb4933, %cond_false4906
+ %i4232.3 = phi i32 [ 0, %cond_false4906 ], [ 0, %cond_next5073 ], [ 0, %bb4933 ] ; <i32> [#uses=1]
+ %tmp5217 = icmp slt i32 %i4232.3, 4 ; <i1> [#uses=1]
+ br i1 %tmp5217, label %bb4933, label %bb5220
+
+bb5220: ; preds = %bb5215
+ br i1 false, label %bb5230, label %cond_true5226
+
+cond_true5226: ; preds = %bb5220
+ ret void
+
+bb5230: ; preds = %bb5220
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br label %bb5233
+
+bb5233: ; preds = %bb5233.preheader, %bb5230
+ %indvar = phi i32 [ 0, %bb5233.preheader ], [ %indvar.next, %bb5230 ] ; <i32> [#uses=2]
+ %mb_x.7 = shl i32 %indvar, 1 ; <i32> [#uses=4]
+ br i1 false, label %bb4231, label %bb5239
+
+bb5239: ; preds = %bb5233
+ %indvar.next37882 = add i32 %indvar37881, 1 ; <i32> [#uses=1]
+ br label %bb5242
+
+bb5242: ; preds = %bb5239, %bb5242.preheader
+ %indvar37881 = phi i32 [ 0, %bb5242.preheader ], [ %indvar.next37882, %bb5239 ] ; <i32> [#uses=2]
+ %mb_y.4 = shl i32 %indvar37881, 1 ; <i32> [#uses=3]
+ br i1 false, label %bb5233.preheader, label %bb5248
+
+bb5233.preheader: ; preds = %bb5242
+ %tmp4784 = icmp slt i32 %mb_y.4, 0 ; <i1> [#uses=1]
+ br label %bb5233
+
+bb5248: ; preds = %bb5242
+ ret void
+
+UnifiedReturnBlock: ; preds = %bb4221
+ ret void
+}
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32)
diff --git a/test/CodeGen/ARM/2007-08-15-ReuseBug.ll b/test/CodeGen/ARM/2007-08-15-ReuseBug.ll
new file mode 100644
index 0000000..30b72e0
--- /dev/null
+++ b/test/CodeGen/ARM/2007-08-15-ReuseBug.ll
@@ -0,0 +1,106 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -mattr=+v6
+; PR1609
+
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+@_C_nextcmd = external global i32 ; <i32*> [#uses=2]
+@_C_cmds = external global [100 x i8*] ; <[100 x i8*]*> [#uses=2]
[email protected] = external constant [2 x i8] ; <[2 x i8]*> [#uses=1]
+
+define i32 @main(i32 %argc, i8** %argv) {
+entry:
+ br label %cond_next212.i
+
+bb21.i: ; preds = %cond_next212.i
+ br label %cond_next212.i
+
+bb24.i: ; preds = %cond_next212.i
+ ret i32 0
+
+bb27.i: ; preds = %cond_next212.i
+ ret i32 0
+
+bb30.i: ; preds = %cond_next212.i
+ %tmp205399.i = add i32 %argc_addr.2358.0.i, -1 ; <i32> [#uses=1]
+ br label %cond_next212.i
+
+bb33.i: ; preds = %cond_next212.i
+ ret i32 0
+
+cond_next73.i: ; preds = %cond_next212.i
+ ret i32 0
+
+bb75.i: ; preds = %cond_next212.i
+ ret i32 0
+
+bb77.i: ; preds = %cond_next212.i
+ ret i32 0
+
+bb79.i: ; preds = %cond_next212.i
+ ret i32 0
+
+bb102.i: ; preds = %cond_next212.i
+ br i1 false, label %cond_true110.i, label %cond_next123.i
+
+cond_true110.i: ; preds = %bb102.i
+ %tmp116.i = getelementptr i8** %argv_addr.2321.0.i, i32 2 ; <i8**> [#uses=1]
+ %tmp117.i = load i8** %tmp116.i ; <i8*> [#uses=1]
+ %tmp126425.i = call %struct.FILE* @fopen( i8* %tmp117.i, i8* getelementptr ([2 x i8]* @.str44, i32 0, i32 0) ) ; <%struct.FILE*> [#uses=0]
+ ret i32 0
+
+cond_next123.i: ; preds = %bb102.i
+ %tmp122.i = getelementptr i8* %tmp215.i, i32 2 ; <i8*> [#uses=0]
+ ret i32 0
+
+bb162.i: ; preds = %cond_next212.i
+ ret i32 0
+
+C_addcmd.exit120.i: ; preds = %cond_next212.i
+ %tmp3.i.i.i.i105.i = call i8* @calloc( i32 15, i32 1 ) ; <i8*> [#uses=1]
+ %tmp1.i108.i = getelementptr [100 x i8*]* @_C_cmds, i32 0, i32 0 ; <i8**> [#uses=1]
+ store i8* %tmp3.i.i.i.i105.i, i8** %tmp1.i108.i, align 4
+ %tmp.i91.i = load i32* @_C_nextcmd, align 4 ; <i32> [#uses=1]
+ store i32 0, i32* @_C_nextcmd, align 4
+ %tmp3.i.i.i.i95.i = call i8* @calloc( i32 15, i32 1 ) ; <i8*> [#uses=1]
+ %tmp1.i98.i = getelementptr [100 x i8*]* @_C_cmds, i32 0, i32 %tmp.i91.i ; <i8**> [#uses=1]
+ store i8* %tmp3.i.i.i.i95.i, i8** %tmp1.i98.i, align 4
+ br label %cond_next212.i
+
+bb174.i: ; preds = %cond_next212.i
+ ret i32 0
+
+bb192.i: ; preds = %cond_next212.i
+ br label %cond_next212.i
+
+cond_next212.i: ; preds = %cond_next212.i, %cond_next212.i, %cond_next212.i, %cond_next212.i, %bb192.i, %C_addcmd.exit120.i, %bb30.i, %bb21.i, %entry
+ %max_d.3 = phi i32 [ -1, %entry ], [ %max_d.3, %bb30.i ], [ %max_d.3, %bb21.i ], [ %max_d.3, %C_addcmd.exit120.i ], [ 0, %bb192.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ], [ %max_d.3, %cond_next212.i ] ; <i32> [#uses=7]
+ %argv_addr.2321.0.i = phi i8** [ %argv, %entry ], [ %tmp214.i, %bb192.i ], [ %tmp214.i, %C_addcmd.exit120.i ], [ %tmp214.i, %bb30.i ], [ %tmp214.i, %bb21.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ], [ %tmp214.i, %cond_next212.i ] ; <i8**> [#uses=2]
+ %argc_addr.2358.0.i = phi i32 [ %argc, %entry ], [ %tmp205399.i, %bb30.i ], [ 0, %bb21.i ], [ 0, %C_addcmd.exit120.i ], [ 0, %bb192.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ], [ 0, %cond_next212.i ] ; <i32> [#uses=1]
+ %tmp214.i = getelementptr i8** %argv_addr.2321.0.i, i32 1 ; <i8**> [#uses=9]
+ %tmp215.i = load i8** %tmp214.i ; <i8*> [#uses=1]
+ %tmp1314.i = sext i8 0 to i32 ; <i32> [#uses=1]
+ switch i32 %tmp1314.i, label %bb192.i [
+ i32 76, label %C_addcmd.exit120.i
+ i32 77, label %bb174.i
+ i32 83, label %bb162.i
+ i32 97, label %bb33.i
+ i32 98, label %bb21.i
+ i32 99, label %bb24.i
+ i32 100, label %bb27.i
+ i32 101, label %cond_next212.i
+ i32 102, label %bb102.i
+ i32 105, label %bb75.i
+ i32 109, label %bb30.i
+ i32 113, label %cond_next212.i
+ i32 114, label %cond_next73.i
+ i32 115, label %bb79.i
+ i32 116, label %cond_next212.i
+ i32 118, label %bb77.i
+ i32 119, label %cond_next212.i
+ ]
+}
+
+declare %struct.FILE* @fopen(i8*, i8*)
+
+declare i8* @calloc(i32, i32)
diff --git a/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll b/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll
new file mode 100644
index 0000000..ff01506
--- /dev/null
+++ b/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=local
+; PR1925
+
+ %struct.encode_aux_nearestmatch = type { i32*, i32*, i32*, i32*, i32, i32 }
+ %struct.encode_aux_pigeonhole = type { float, float, i32, i32, i32*, i32, i32*, i32*, i32* }
+ %struct.encode_aux_threshmatch = type { float*, i32*, i32, i32 }
+ %struct.oggpack_buffer = type { i32, i32, i8*, i8*, i32 }
+ %struct.static_codebook = type { i32, i32, i32*, i32, i32, i32, i32, i32, i32*, %struct.encode_aux_nearestmatch*, %struct.encode_aux_threshmatch*, %struct.encode_aux_pigeonhole*, i32 }
+
+define i32 @vorbis_staticbook_pack(%struct.static_codebook* %c, %struct.oggpack_buffer* %opb) {
+entry:
+ %opb_addr = alloca %struct.oggpack_buffer* ; <%struct.oggpack_buffer**> [#uses=1]
+ %tmp1 = load %struct.oggpack_buffer** %opb_addr, align 4 ; <%struct.oggpack_buffer*> [#uses=1]
+ call void @oggpack_write( %struct.oggpack_buffer* %tmp1, i32 5653314, i32 24 ) nounwind
+ call void @oggpack_write( %struct.oggpack_buffer* null, i32 0, i32 24 ) nounwind
+ unreachable
+}
+
+declare void @oggpack_write(%struct.oggpack_buffer*, i32, i32)
diff --git a/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll b/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll
new file mode 100644
index 0000000..06bc987
--- /dev/null
+++ b/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=local
+; PR1925
+
+ %"struct.kc::impl_Ccode_option" = type { %"struct.kc::impl_abstract_phylum" }
+ %"struct.kc::impl_ID" = type { %"struct.kc::impl_abstract_phylum", %"struct.kc::impl_Ccode_option"*, %"struct.kc::impl_casestring__Str"*, i32, %"struct.kc::impl_casestring__Str"* }
+ %"struct.kc::impl_abstract_phylum" = type { i32 (...)** }
+ %"struct.kc::impl_casestring__Str" = type { %"struct.kc::impl_abstract_phylum", i8* }
+
+define %"struct.kc::impl_ID"* @_ZN2kc18f_typeofunpsubtermEPNS_15impl_unpsubtermEPNS_7impl_IDE(%"struct.kc::impl_Ccode_option"* %a_unpsubterm, %"struct.kc::impl_ID"* %a_operator) {
+entry:
+ %tmp8 = getelementptr %"struct.kc::impl_Ccode_option"* %a_unpsubterm, i32 0, i32 0, i32 0 ; <i32 (...)***> [#uses=0]
+ br i1 false, label %bb41, label %bb55
+
+bb41: ; preds = %entry
+ ret %"struct.kc::impl_ID"* null
+
+bb55: ; preds = %entry
+ %tmp67 = tail call i32 null( %"struct.kc::impl_abstract_phylum"* null ) ; <i32> [#uses=0]
+ %tmp97 = tail call i32 null( %"struct.kc::impl_abstract_phylum"* null ) ; <i32> [#uses=0]
+ ret %"struct.kc::impl_ID"* null
+}
diff --git a/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll b/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll
new file mode 100644
index 0000000..a604c5c
--- /dev/null
+++ b/test/CodeGen/ARM/2008-03-05-SxtInRegBug.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=arm -mattr=+v6 | not grep 255
+
+define i32 @main(i32 %argc, i8** %argv) {
+entry:
+ br label %bb1
+bb1: ; preds = %entry
+ %tmp3.i.i = load i8* null, align 1 ; <i8> [#uses=1]
+ %tmp4.i.i = icmp slt i8 %tmp3.i.i, 0 ; <i1> [#uses=1]
+ br i1 %tmp4.i.i, label %bb2, label %bb3
+bb2: ; preds = %bb1
+ ret i32 1
+bb3: ; preds = %bb1
+ ret i32 0
+}
diff --git a/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll b/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
new file mode 100644
index 0000000..78c6222
--- /dev/null
+++ b/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2
+
+@accum = external global { double, double } ; <{ double, double }*> [#uses=1]
[email protected] = external constant [4 x i8] ; <[4 x i8]*> [#uses=1]
+
+define i32 @main() {
+entry:
+ br label %bb74.i
+bb74.i: ; preds = %bb88.i, %bb74.i, %entry
+ br i1 false, label %bb88.i, label %bb74.i
+bb88.i: ; preds = %bb74.i
+ br i1 false, label %mandel.exit, label %bb74.i
+mandel.exit: ; preds = %bb88.i
+ %tmp2 = volatile load double* getelementptr ({ double, double }* @accum, i32 0, i32 0), align 8 ; <double> [#uses=1]
+ %tmp23 = fptosi double %tmp2 to i32 ; <i32> [#uses=1]
+ %tmp5 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i32 %tmp23 ) ; <i32> [#uses=0]
+ ret i32 0
+}
+
+declare i32 @printf(i8*, ...)
diff --git a/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll b/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll
new file mode 100644
index 0000000..234c7b6
--- /dev/null
+++ b/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll
@@ -0,0 +1,60 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+@numBinsY = external global i32 ; <i32*> [#uses=1]
+
+declare double @pow(double, double)
+
+define void @main(i32 %argc, i8** %argv) noreturn nounwind {
+entry:
+ br i1 false, label %bb34.outer.i.i.i, label %cond_false674
+bb34.outer.i.i.i: ; preds = %entry
+ br i1 false, label %bb2.i.i.i, label %bb47.i.i.i
+bb2.i.i.i: ; preds = %bb34.outer.i.i.i
+ %tmp24.i.i.i = call double @pow( double 0.000000e+00, double 2.000000e+00 ) ; <double> [#uses=0]
+ ret void
+bb47.i.i.i: ; preds = %bb34.outer.i.i.i
+ br i1 false, label %bb220.i.i.i, label %bb62.preheader.i.i.i
+bb62.preheader.i.i.i: ; preds = %bb47.i.i.i
+ ret void
+bb220.i.i.i: ; preds = %bb47.i.i.i
+ br i1 false, label %bb248.i.i.i, label %cond_next232.i.i.i
+cond_next232.i.i.i: ; preds = %bb220.i.i.i
+ ret void
+bb248.i.i.i: ; preds = %bb220.i.i.i
+ br i1 false, label %bb300.i.i.i, label %cond_false256.i.i.i
+cond_false256.i.i.i: ; preds = %bb248.i.i.i
+ ret void
+bb300.i.i.i: ; preds = %bb248.i.i.i
+ store i32 undef, i32* @numBinsY, align 4
+ ret void
+cond_false674: ; preds = %entry
+ ret void
+}
+
+ %struct.anon = type { %struct.rnode*, %struct.rnode* }
+ %struct.ch_set = type { { i8, i8 }*, %struct.ch_set* }
+ %struct.pat_list = type { i32, %struct.pat_list* }
+ %struct.rnode = type { i16, { %struct.anon }, i16, %struct.pat_list*, %struct.pat_list* }
+
+define fastcc { i16, %struct.rnode* }* @get_token(i8** %s) nounwind {
+entry:
+ br i1 false, label %bb42, label %bb78
+bb42: ; preds = %entry
+ br label %cond_next119.i
+bb17.i: ; preds = %cond_next119.i
+ br i1 false, label %cond_true53.i, label %cond_false99.i
+cond_true53.i: ; preds = %bb17.i
+ ret { i16, %struct.rnode* }* null
+cond_false99.i: ; preds = %bb17.i
+ %tmp106.i = malloc %struct.ch_set ; <%struct.ch_set*> [#uses=1]
+ br i1 false, label %bb126.i, label %cond_next119.i
+cond_next119.i: ; preds = %cond_false99.i, %bb42
+ %curr_ptr.0.reg2mem.0.i = phi %struct.ch_set* [ %tmp106.i, %cond_false99.i ], [ null, %bb42 ] ; <%struct.ch_set*> [#uses=2]
+ %prev_ptr.0.reg2mem.0.i = phi %struct.ch_set* [ %curr_ptr.0.reg2mem.0.i, %cond_false99.i ], [ undef, %bb42 ] ; <%struct.ch_set*> [#uses=1]
+ br i1 false, label %bb126.i, label %bb17.i
+bb126.i: ; preds = %cond_next119.i, %cond_false99.i
+ %prev_ptr.0.reg2mem.1.i = phi %struct.ch_set* [ %prev_ptr.0.reg2mem.0.i, %cond_next119.i ], [ %curr_ptr.0.reg2mem.0.i, %cond_false99.i ] ; <%struct.ch_set*> [#uses=0]
+ ret { i16, %struct.rnode* }* null
+bb78: ; preds = %entry
+ ret { i16, %struct.rnode* }* null
+}
diff --git a/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll b/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll
new file mode 100644
index 0000000..77418be
--- /dev/null
+++ b/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll
@@ -0,0 +1,258 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+ %struct.CONTENTBOX = type { i32, i32, i32, i32, i32 }
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.LOCBOX = type { i32, i32, i32, i32 }
+ %struct.SIDEBOX = type { i32, i32 }
+ %struct.UNCOMBOX = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+ %struct.cellbox = type { i8*, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, %struct.CONTENTBOX*, %struct.UNCOMBOX*, [8 x %struct.tilebox*], %struct.SIDEBOX* }
+ %struct.termbox = type { %struct.termbox*, i32, i32, i32, i32, i32 }
+ %struct.tilebox = type { %struct.tilebox*, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.termbox*, %struct.LOCBOX* }
[email protected] = external constant [2 x i8] ; <[2 x i8]*> [#uses=1]
[email protected] = external constant [5 x i8] ; <[5 x i8]*> [#uses=1]
[email protected] = external constant [9 x i8] ; <[9 x i8]*> [#uses=1]
+
+declare %struct.FILE* @fopen(i8*, i8*)
+
+declare i32 @strcmp(i8*, i8*)
+
+declare i32 @fscanf(%struct.FILE*, i8*, ...)
+
+define void @main(i32 %argc, i8** %argv) noreturn {
+entry:
+ br i1 false, label %cond_next48, label %cond_false674
+cond_next48: ; preds = %entry
+ %tmp61 = call %struct.FILE* @fopen( i8* null, i8* getelementptr ([2 x i8]* @.str127, i32 0, i32 0) ) ; <%struct.FILE*> [#uses=2]
+ br i1 false, label %bb220.i.i.i, label %bb62.preheader.i.i.i
+bb62.preheader.i.i.i: ; preds = %cond_next48
+ ret void
+bb220.i.i.i: ; preds = %cond_next48
+ br i1 false, label %bb248.i.i.i, label %cond_next232.i.i.i
+cond_next232.i.i.i: ; preds = %bb220.i.i.i
+ ret void
+bb248.i.i.i: ; preds = %bb220.i.i.i
+ br i1 false, label %bb300.i.i.i, label %cond_false256.i.i.i
+cond_false256.i.i.i: ; preds = %bb248.i.i.i
+ ret void
+bb300.i.i.i: ; preds = %bb248.i.i.i
+ br label %bb.i.i347.i
+bb.i.i347.i: ; preds = %bb.i.i347.i, %bb300.i.i.i
+ br i1 false, label %bb894.loopexit.i.i, label %bb.i.i347.i
+bb.i350.i: ; preds = %bb894.i.i
+ br i1 false, label %bb24.i.i, label %cond_false373.i.i
+bb24.i.i: ; preds = %bb24.i.i, %bb.i350.i
+ br i1 false, label %bb40.i.i, label %bb24.i.i
+bb40.i.i: ; preds = %bb24.i.i
+ br i1 false, label %bb177.i393.i, label %bb82.i.i
+bb82.i.i: ; preds = %bb40.i.i
+ ret void
+bb177.i393.i: ; preds = %bb40.i.i
+ br i1 false, label %bb894.i.i, label %bb192.i.i
+bb192.i.i: ; preds = %bb177.i393.i
+ ret void
+cond_false373.i.i: ; preds = %bb.i350.i
+ %tmp376.i.i = call i32 @strcmp( i8* null, i8* getelementptr ([9 x i8]* @.str8115, i32 0, i32 0) ) ; <i32> [#uses=0]
+ br i1 false, label %cond_true380.i.i, label %cond_next602.i.i
+cond_true380.i.i: ; preds = %cond_false373.i.i
+ %tmp394.i418.i = add i32 %cell.0.i.i, 1 ; <i32> [#uses=1]
+ %tmp397.i420.i = load %struct.cellbox** null, align 4 ; <%struct.cellbox*> [#uses=1]
+ br label %bb398.i.i
+bb398.i.i: ; preds = %bb398.i.i, %cond_true380.i.i
+ br i1 false, label %bb414.i.i, label %bb398.i.i
+bb414.i.i: ; preds = %bb398.i.i
+ br i1 false, label %bb581.i.i, label %bb455.i442.i
+bb455.i442.i: ; preds = %bb414.i.i
+ ret void
+bb581.i.i: ; preds = %bb581.i.i, %bb414.i.i
+ br i1 false, label %bb894.i.i, label %bb581.i.i
+cond_next602.i.i: ; preds = %cond_false373.i.i
+ br i1 false, label %bb609.i.i, label %bb661.i.i
+bb609.i.i: ; preds = %cond_next602.i.i
+ br label %bb620.i.i
+bb620.i.i: ; preds = %bb620.i.i, %bb609.i.i
+ %indvar166.i465.i = phi i32 [ %indvar.next167.i.i, %bb620.i.i ], [ 0, %bb609.i.i ] ; <i32> [#uses=1]
+ %tmp640.i.i = call i32 (%struct.FILE*, i8*, ...)* @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; <i32> [#uses=0]
+ %tmp648.i.i = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp650.i468.i = icmp sgt i32 0, %tmp648.i.i ; <i1> [#uses=1]
+ %tmp624.i469.i = call i32 (%struct.FILE*, i8*, ...)* @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; <i32> [#uses=0]
+ %indvar.next167.i.i = add i32 %indvar166.i465.i, 1 ; <i32> [#uses=1]
+ br i1 %tmp650.i468.i, label %bb653.i.i.loopexit, label %bb620.i.i
+bb653.i.i.loopexit: ; preds = %bb620.i.i
+ %tmp642.i466.i = add i32 0, 1 ; <i32> [#uses=1]
+ br label %bb894.i.i
+bb661.i.i: ; preds = %cond_next602.i.i
+ ret void
+bb894.loopexit.i.i: ; preds = %bb.i.i347.i
+ br label %bb894.i.i
+bb894.i.i: ; preds = %bb894.loopexit.i.i, %bb653.i.i.loopexit, %bb581.i.i, %bb177.i393.i
+ %pinctr.0.i.i = phi i32 [ 0, %bb894.loopexit.i.i ], [ %tmp642.i466.i, %bb653.i.i.loopexit ], [ %pinctr.0.i.i, %bb177.i393.i ], [ %pinctr.0.i.i, %bb581.i.i ] ; <i32> [#uses=2]
+ %soft.0.i.i = phi i32 [ undef, %bb894.loopexit.i.i ], [ %soft.0.i.i, %bb653.i.i.loopexit ], [ 0, %bb177.i393.i ], [ 1, %bb581.i.i ] ; <i32> [#uses=1]
+ %cell.0.i.i = phi i32 [ 0, %bb894.loopexit.i.i ], [ %cell.0.i.i, %bb653.i.i.loopexit ], [ 0, %bb177.i393.i ], [ %tmp394.i418.i, %bb581.i.i ] ; <i32> [#uses=2]
+ %ptr.0.i.i = phi %struct.cellbox* [ undef, %bb894.loopexit.i.i ], [ %ptr.0.i.i, %bb653.i.i.loopexit ], [ null, %bb177.i393.i ], [ %tmp397.i420.i, %bb581.i.i ] ; <%struct.cellbox*> [#uses=1]
+ br i1 false, label %bb.i350.i, label %bb902.i502.i
+bb902.i502.i: ; preds = %bb894.i.i
+ ret void
+cond_false674: ; preds = %entry
+ ret void
+}
+
+ %struct.III_psy_xmin = type { [22 x double], [13 x [3 x double]] }
+ %struct.III_scalefac_t = type { [22 x i32], [13 x [3 x i32]] }
+ %struct.gr_info = type { i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32*, [4 x i32] }
+ %struct.lame_global_flags = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, float, float, float, float, i32, i32, i32, i32, i32, i32, i32, i32 }
+@scalefac_band.1 = external global [14 x i32] ; <[14 x i32]*> [#uses=2]
+
+declare fastcc i32 @init_outer_loop(%struct.lame_global_flags*, double*, %struct.gr_info*)
+
+define fastcc void @outer_loop(%struct.lame_global_flags* %gfp, double* %xr, i32 %targ_bits, double* %best_noise, %struct.III_psy_xmin* %l3_xmin, i32* %l3_enc, %struct.III_scalefac_t* %scalefac, %struct.gr_info* %cod_info, i32 %ch) {
+entry:
+ %cod_info.182 = getelementptr %struct.gr_info* %cod_info, i32 0, i32 1 ; <i32*> [#uses=1]
+ br label %bb
+bb: ; preds = %bb226, %entry
+ %save_cod_info.1.1 = phi i32 [ undef, %entry ], [ %save_cod_info.1.1, %bb226 ] ; <i32> [#uses=2]
+ br i1 false, label %cond_next, label %cond_true
+cond_true: ; preds = %bb
+ ret void
+cond_next: ; preds = %bb
+ br i1 false, label %cond_next144, label %cond_false
+cond_false: ; preds = %cond_next
+ ret void
+cond_next144: ; preds = %cond_next
+ br i1 false, label %cond_next205, label %cond_true163
+cond_true163: ; preds = %cond_next144
+ br i1 false, label %bb34.i, label %bb.i53
+bb.i53: ; preds = %cond_true163
+ ret void
+bb34.i: ; preds = %cond_true163
+ %tmp37.i55 = load i32* null, align 4 ; <i32> [#uses=1]
+ br i1 false, label %bb65.preheader.i, label %bb78.i
+bb65.preheader.i: ; preds = %bb34.i
+ br label %bb65.outer.us.i
+bb65.outer.us.i: ; preds = %bb65.outer.us.i, %bb65.preheader.i
+ br i1 false, label %bb78.i, label %bb65.outer.us.i
+bb78.i: ; preds = %bb65.outer.us.i, %bb34.i
+ br i1 false, label %bb151.i.preheader, label %bb90.i
+bb90.i: ; preds = %bb78.i
+ ret void
+bb151.i.preheader: ; preds = %bb78.i
+ br label %bb151.i
+bb151.i: ; preds = %bb226.backedge.i, %bb151.i.preheader
+ %i.154.i = phi i32 [ %tmp15747.i, %bb226.backedge.i ], [ 0, %bb151.i.preheader ] ; <i32> [#uses=2]
+ %tmp15747.i = add i32 %i.154.i, 1 ; <i32> [#uses=3]
+ br i1 false, label %bb155.i, label %bb226.backedge.i
+bb226.backedge.i: ; preds = %cond_next215.i, %bb151.i
+ %tmp228.i71 = icmp slt i32 %tmp15747.i, 3 ; <i1> [#uses=1]
+ br i1 %tmp228.i71, label %bb151.i, label %amp_scalefac_bands.exit
+bb155.i: ; preds = %cond_next215.i, %bb151.i
+ %indvar90.i = phi i32 [ %indvar.next91.i, %cond_next215.i ], [ 0, %bb151.i ] ; <i32> [#uses=2]
+ %sfb.3.reg2mem.0.i = add i32 %indvar90.i, %tmp37.i55 ; <i32> [#uses=4]
+ %tmp161.i = getelementptr [4 x [21 x double]]* null, i32 0, i32 %tmp15747.i, i32 %sfb.3.reg2mem.0.i ; <double*> [#uses=1]
+ %tmp162.i74 = load double* %tmp161.i, align 4 ; <double> [#uses=0]
+ br i1 false, label %cond_true167.i, label %cond_next215.i
+cond_true167.i: ; preds = %bb155.i
+ %tmp173.i = getelementptr %struct.III_scalefac_t* null, i32 0, i32 1, i32 %sfb.3.reg2mem.0.i, i32 %i.154.i ; <i32*> [#uses=1]
+ store i32 0, i32* %tmp173.i, align 4
+ %tmp182.1.i = getelementptr [14 x i32]* @scalefac_band.1, i32 0, i32 %sfb.3.reg2mem.0.i ; <i32*> [#uses=0]
+ %tmp185.i78 = add i32 %sfb.3.reg2mem.0.i, 1 ; <i32> [#uses=1]
+ %tmp187.1.i = getelementptr [14 x i32]* @scalefac_band.1, i32 0, i32 %tmp185.i78 ; <i32*> [#uses=1]
+ %tmp188.i = load i32* %tmp187.1.i, align 4 ; <i32> [#uses=1]
+ %tmp21153.i = icmp slt i32 0, %tmp188.i ; <i1> [#uses=1]
+ br i1 %tmp21153.i, label %bb190.preheader.i, label %cond_next215.i
+bb190.preheader.i: ; preds = %cond_true167.i
+ ret void
+cond_next215.i: ; preds = %cond_true167.i, %bb155.i
+ %indvar.next91.i = add i32 %indvar90.i, 1 ; <i32> [#uses=2]
+ %exitcond99.i87 = icmp eq i32 %indvar.next91.i, 0 ; <i1> [#uses=1]
+ br i1 %exitcond99.i87, label %bb226.backedge.i, label %bb155.i
+amp_scalefac_bands.exit: ; preds = %bb226.backedge.i
+ br i1 false, label %bb19.i, label %bb.i16
+bb.i16: ; preds = %amp_scalefac_bands.exit
+ ret void
+bb19.i: ; preds = %amp_scalefac_bands.exit
+ br i1 false, label %bb40.outer.i, label %cond_next205
+bb40.outer.i: ; preds = %bb19.i
+ ret void
+cond_next205: ; preds = %bb19.i, %cond_next144
+ br i1 false, label %bb226, label %cond_true210
+cond_true210: ; preds = %cond_next205
+ br i1 false, label %bb226, label %cond_true217
+cond_true217: ; preds = %cond_true210
+ %tmp221 = call fastcc i32 @init_outer_loop( %struct.lame_global_flags* %gfp, double* %xr, %struct.gr_info* %cod_info ) ; <i32> [#uses=0]
+ ret void
+bb226: ; preds = %cond_true210, %cond_next205
+ br i1 false, label %bb231, label %bb
+bb231: ; preds = %bb226
+ store i32 %save_cod_info.1.1, i32* %cod_info.182
+ ret void
+}
+
+ %struct.III_psy_xmin = type { [22 x double], [13 x [3 x double]] }
+ %struct.III_scalefac_t = type { [22 x i32], [13 x [3 x i32]] }
+ %struct.gr_info = type { i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32*, [4 x i32] }
+ %struct.lame_global_flags = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, float, float, float, float, i32, i32, i32, i32, i32, i32, i32, i32 }
+
+define fastcc void @outer_loop2(%struct.lame_global_flags* %gfp, double* %xr, i32 %targ_bits, double* %best_noise, %struct.III_psy_xmin* %l3_xmin, i32* %l3_enc, %struct.III_scalefac_t* %scalefac, %struct.gr_info* %cod_info, i32 %ch) {
+entry:
+ %cod_info.20128.1 = getelementptr %struct.gr_info* %cod_info, i32 0, i32 20, i32 1 ; <i32*> [#uses=1]
+ %cod_info.20128.2 = getelementptr %struct.gr_info* %cod_info, i32 0, i32 20, i32 2 ; <i32*> [#uses=1]
+ %cod_info.20128.3 = getelementptr %struct.gr_info* %cod_info, i32 0, i32 20, i32 3 ; <i32*> [#uses=1]
+ br label %bb
+bb: ; preds = %bb226, %entry
+ %save_cod_info.19.1 = phi i32* [ undef, %entry ], [ %save_cod_info.19.0, %bb226 ] ; <i32*> [#uses=1]
+ %save_cod_info.0.1 = phi i32 [ undef, %entry ], [ %save_cod_info.0.0, %bb226 ] ; <i32> [#uses=1]
+ br i1 false, label %cond_next144, label %cond_false
+cond_false: ; preds = %bb
+ br i1 false, label %cond_true56, label %cond_false78
+cond_true56: ; preds = %cond_false
+ br i1 false, label %inner_loop.exit, label %cond_next85
+inner_loop.exit: ; preds = %cond_true56
+ br i1 false, label %cond_next104, label %cond_false96
+cond_false78: ; preds = %cond_false
+ ret void
+cond_next85: ; preds = %cond_true56
+ ret void
+cond_false96: ; preds = %inner_loop.exit
+ ret void
+cond_next104: ; preds = %inner_loop.exit
+ br i1 false, label %cond_next144, label %cond_false110
+cond_false110: ; preds = %cond_next104
+ ret void
+cond_next144: ; preds = %cond_next104, %bb
+ %save_cod_info.19.0 = phi i32* [ %save_cod_info.19.1, %bb ], [ null, %cond_next104 ] ; <i32*> [#uses=1]
+ %save_cod_info.4.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1]
+ %save_cod_info.3.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1]
+ %save_cod_info.2.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1]
+ %save_cod_info.1.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1]
+ %save_cod_info.0.0 = phi i32 [ %save_cod_info.0.1, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1]
+ %over.1 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1]
+ %best_over.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1]
+ %notdone.0 = phi i32 [ 0, %bb ], [ 0, %cond_next104 ] ; <i32> [#uses=1]
+ %tmp147 = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp148 = icmp eq i32 %tmp147, 0 ; <i1> [#uses=1]
+ %tmp153 = icmp eq i32 %over.1, 0 ; <i1> [#uses=1]
+ %bothcond = and i1 %tmp148, %tmp153 ; <i1> [#uses=1]
+ %notdone.2 = select i1 %bothcond, i32 0, i32 %notdone.0 ; <i32> [#uses=1]
+ br i1 false, label %cond_next205, label %cond_true163
+cond_true163: ; preds = %cond_next144
+ ret void
+cond_next205: ; preds = %cond_next144
+ br i1 false, label %bb226, label %cond_true210
+cond_true210: ; preds = %cond_next205
+ ret void
+bb226: ; preds = %cond_next205
+ %tmp228 = icmp eq i32 %notdone.2, 0 ; <i1> [#uses=1]
+ br i1 %tmp228, label %bb231, label %bb
+bb231: ; preds = %bb226
+ store i32 %save_cod_info.1.0, i32* null
+ store i32 %save_cod_info.2.0, i32* null
+ store i32 %save_cod_info.3.0, i32* null
+ store i32 %save_cod_info.4.0, i32* null
+ store i32 0, i32* %cod_info.20128.1
+ store i32 0, i32* %cod_info.20128.2
+ store i32 0, i32* %cod_info.20128.3
+ %tmp244245 = sitofp i32 %best_over.0 to double ; <double> [#uses=1]
+ store double %tmp244245, double* %best_noise, align 4
+ ret void
+}
diff --git a/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll b/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll
new file mode 100644
index 0000000..33bd4de
--- /dev/null
+++ b/test/CodeGen/ARM/2008-04-11-PHIofImpDef.ll
@@ -0,0 +1,3544 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+declare void @foo(i8*, i8*, i32, i32, i32, i32, i32, i32, i32)
+
+define void @t() nounwind {
+ br label %1
+; <label>:1 ; preds = %0
+ br label %bb4351.i
+bb4351.i: ; preds = %1
+ switch i32 0, label %bb4411.i [
+ i32 1, label %bb4354.i
+ i32 2, label %bb4369.i
+ ]
+bb4354.i: ; preds = %bb4351.i
+ br label %t.exit
+bb4369.i: ; preds = %bb4351.i
+ br label %bb4374.i
+bb4374.i: ; preds = %bb4369.i
+ br label %bb4411.i
+bb4411.i: ; preds = %bb4374.i, %bb4351.i
+ %sf4083.0.i = phi i32 [ 0, %bb4374.i ], [ 6, %bb4351.i ] ; <i32> [#uses=8]
+ br label %bb4498.i
+bb4498.i: ; preds = %bb4411.i
+ %sfComp4077.1.i = phi i32 [ undef, %bb4411.i ] ; <i32> [#uses=2]
+ %stComp4075.1.i = phi i32 [ undef, %bb4411.i ] ; <i32> [#uses=1]
+ switch i32 0, label %bb4553.i [
+ i32 1, label %bb4501.i
+ i32 2, label %bb4521.i
+ ]
+bb4501.i: ; preds = %bb4498.i
+ %sfComp4077.1.reg2mem.0.i = phi i32 [ %sfComp4077.1.i, %bb4498.i ] ; <i32> [#uses=1]
+ call void @foo( i8* null, i8* null, i32 %sfComp4077.1.reg2mem.0.i, i32 0, i32 8, i32 0, i32 0, i32 0, i32 0 ) nounwind
+ br i1 false, label %UnifiedReturnBlock.i, label %bb4517.i
+bb4517.i: ; preds = %bb4501.i
+ br label %t.exit
+bb4521.i: ; preds = %bb4498.i
+ br label %bb4526.i
+bb4526.i: ; preds = %bb4521.i
+ switch i32 0, label %bb4529.i [
+ i32 6, label %bb4530.i
+ i32 7, label %bb4530.i
+ ]
+bb4529.i: ; preds = %bb4526.i
+ br label %bb4530.i
+bb4530.i: ; preds = %bb4529.i, %bb4526.i, %bb4526.i
+ br label %bb4553.i
+bb4553.i: ; preds = %bb4530.i, %bb4498.i
+ %dt4080.0.i = phi i32 [ %stComp4075.1.i, %bb4530.i ], [ 7, %bb4498.i ] ; <i32> [#uses=32]
+ %df4081.0.i = phi i32 [ %sfComp4077.1.i, %bb4530.i ], [ 8, %bb4498.i ] ; <i32> [#uses=17]
+ switch i32 %sf4083.0.i, label %bb4559.i [
+ i32 0, label %bb4558.i
+ i32 1, label %bb4558.i
+ i32 2, label %bb4558.i
+ i32 5, label %bb4561.i
+ i32 6, label %bb4561.i
+ i32 7, label %bb4561.i
+ i32 9, label %bb4557.i
+ ]
+bb4557.i: ; preds = %bb4553.i
+ switch i32 %df4081.0.i, label %bb4569.i [
+ i32 0, label %bb4568.i
+ i32 1, label %bb4568.i
+ i32 2, label %bb4568.i
+ i32 5, label %bb4571.i
+ i32 6, label %bb4571.i
+ i32 7, label %bb4571.i
+ i32 9, label %bb4567.i
+ ]
+bb4558.i: ; preds = %bb4553.i, %bb4553.i, %bb4553.i
+ switch i32 %df4081.0.i, label %bb4569.i [
+ i32 0, label %bb4568.i
+ i32 1, label %bb4568.i
+ i32 2, label %bb4568.i
+ i32 5, label %bb4571.i
+ i32 6, label %bb4571.i
+ i32 7, label %bb4571.i
+ i32 9, label %bb4567.i
+ ]
+bb4559.i: ; preds = %bb4553.i
+ br label %bb4561.i
+bb4561.i: ; preds = %bb4559.i, %bb4553.i, %bb4553.i, %bb4553.i
+ switch i32 %df4081.0.i, label %bb4569.i [
+ i32 0, label %bb4568.i
+ i32 1, label %bb4568.i
+ i32 2, label %bb4568.i
+ i32 5, label %bb4571.i
+ i32 6, label %bb4571.i
+ i32 7, label %bb4571.i
+ i32 9, label %bb4567.i
+ ]
+bb4567.i: ; preds = %bb4561.i, %bb4558.i, %bb4557.i
+ br label %bb4580.i
+bb4568.i: ; preds = %bb4561.i, %bb4561.i, %bb4561.i, %bb4558.i, %bb4558.i, %bb4558.i, %bb4557.i, %bb4557.i, %bb4557.i
+ br label %bb4580.i
+bb4569.i: ; preds = %bb4561.i, %bb4558.i, %bb4557.i
+ br label %bb4571.i
+bb4571.i: ; preds = %bb4569.i, %bb4561.i, %bb4561.i, %bb4561.i, %bb4558.i, %bb4558.i, %bb4558.i, %bb4557.i, %bb4557.i, %bb4557.i
+ br label %bb4580.i
+bb4580.i: ; preds = %bb4571.i, %bb4568.i, %bb4567.i
+ br i1 false, label %bb4611.i, label %bb4593.i
+bb4593.i: ; preds = %bb4580.i
+ br i1 false, label %bb4610.i, label %bb4611.i
+bb4610.i: ; preds = %bb4593.i
+ br label %bb4611.i
+bb4611.i: ; preds = %bb4610.i, %bb4593.i, %bb4580.i
+ br i1 false, label %bb4776.i, label %bb4620.i
+bb4620.i: ; preds = %bb4611.i
+ switch i32 0, label %bb4776.i [
+ i32 0, label %bb4691.i
+ i32 2, label %bb4740.i
+ i32 4, label %bb4755.i
+ i32 8, label %bb4622.i
+ i32 9, label %bb4622.i
+ i32 10, label %bb4629.i
+ i32 11, label %bb4629.i
+ i32 12, label %bb4651.i
+ i32 13, label %bb4651.i
+ i32 14, label %bb4665.i
+ i32 15, label %bb4665.i
+ i32 16, label %bb4691.i
+ i32 17, label %bb4691.i
+ i32 18, label %bb4712.i
+ i32 19, label %bb4712.i
+ i32 22, label %bb4733.i
+ i32 23, label %bb4733.i
+ ]
+bb4622.i: ; preds = %bb4620.i, %bb4620.i
+ br i1 false, label %bb4628.i, label %bb4776.i
+bb4628.i: ; preds = %bb4622.i
+ br label %bb4776.i
+bb4629.i: ; preds = %bb4620.i, %bb4620.i
+ br i1 false, label %bb4776.i, label %bb4644.i
+bb4644.i: ; preds = %bb4629.i
+ br i1 false, label %bb4650.i, label %bb4776.i
+bb4650.i: ; preds = %bb4644.i
+ br label %bb4776.i
+bb4651.i: ; preds = %bb4620.i, %bb4620.i
+ br i1 false, label %bb4776.i, label %bb4658.i
+bb4658.i: ; preds = %bb4651.i
+ br i1 false, label %bb4664.i, label %bb4776.i
+bb4664.i: ; preds = %bb4658.i
+ br label %bb4776.i
+bb4665.i: ; preds = %bb4620.i, %bb4620.i
+ br i1 false, label %bb4776.i, label %bb4684.i
+bb4684.i: ; preds = %bb4665.i
+ br i1 false, label %bb4690.i, label %bb4776.i
+bb4690.i: ; preds = %bb4684.i
+ br label %bb4776.i
+bb4691.i: ; preds = %bb4620.i, %bb4620.i, %bb4620.i
+ br i1 false, label %bb4776.i, label %bb4698.i
+bb4698.i: ; preds = %bb4691.i
+ br i1 false, label %bb4711.i, label %bb4776.i
+bb4711.i: ; preds = %bb4698.i
+ br label %bb4776.i
+bb4712.i: ; preds = %bb4620.i, %bb4620.i
+ br i1 false, label %bb4776.i, label %bb4726.i
+bb4726.i: ; preds = %bb4712.i
+ br i1 false, label %bb4732.i, label %bb4776.i
+bb4732.i: ; preds = %bb4726.i
+ br label %bb4776.i
+bb4733.i: ; preds = %bb4620.i, %bb4620.i
+ br i1 false, label %bb4739.i, label %bb4776.i
+bb4739.i: ; preds = %bb4733.i
+ br label %bb4776.i
+bb4740.i: ; preds = %bb4620.i
+ br i1 false, label %bb4776.i, label %bb4754.i
+bb4754.i: ; preds = %bb4740.i
+ br label %bb4776.i
+bb4755.i: ; preds = %bb4620.i
+ br i1 false, label %bb4776.i, label %bb4774.i
+bb4774.i: ; preds = %bb4755.i
+ br label %bb4776.i
+bb4776.i: ; preds = %bb4774.i, %bb4755.i, %bb4754.i, %bb4740.i, %bb4739.i, %bb4733.i, %bb4732.i, %bb4726.i, %bb4712.i, %bb4711.i, %bb4698.i, %bb4691.i, %bb4690.i, %bb4684.i, %bb4665.i, %bb4664.i, %bb4658.i, %bb4651.i, %bb4650.i, %bb4644.i, %bb4629.i, %bb4628.i, %bb4622.i, %bb4620.i, %bb4611.i
+ switch i32 0, label %bb4790.i [
+ i32 0, label %bb4786.i
+ i32 1, label %bb4784.i
+ i32 3, label %bb4784.i
+ i32 5, label %bb4784.i
+ i32 6, label %bb4785.i
+ i32 7, label %bb4785.i
+ i32 8, label %bb4791.i
+ i32 9, label %bb4791.i
+ i32 10, label %bb4791.i
+ i32 11, label %bb4791.i
+ i32 12, label %bb4791.i
+ i32 13, label %bb4791.i
+ i32 14, label %bb4791.i
+ i32 15, label %bb4791.i
+ i32 16, label %bb4791.i
+ i32 17, label %bb4791.i
+ i32 18, label %bb4791.i
+ i32 19, label %bb4791.i
+ ]
+bb4784.i: ; preds = %bb4776.i, %bb4776.i, %bb4776.i
+ br label %bb4791.i
+bb4785.i: ; preds = %bb4776.i, %bb4776.i
+ br label %bb4791.i
+bb4786.i: ; preds = %bb4776.i
+ br label %bb4791.i
+bb4790.i: ; preds = %bb4776.i
+ br label %bb4791.i
+bb4791.i: ; preds = %bb4790.i, %bb4786.i, %bb4785.i, %bb4784.i, %bb4776.i, %bb4776.i, %bb4776.i, %bb4776.i, %bb4776.i, %bb4776.i, %bb4776.i, %bb4776.i, %bb4776.i, %bb4776.i, %bb4776.i, %bb4776.i
+ switch i32 %dt4080.0.i, label %bb4803.i [
+ i32 0, label %bb4799.i
+ i32 6, label %bb4794.i
+ i32 7, label %bb4794.i
+ i32 8, label %bb4804.i
+ i32 9, label %bb4804.i
+ i32 10, label %bb4804.i
+ i32 11, label %bb4804.i
+ i32 12, label %bb4804.i
+ i32 13, label %bb4804.i
+ i32 14, label %bb4804.i
+ i32 15, label %bb4804.i
+ i32 16, label %bb4804.i
+ i32 17, label %bb4804.i
+ i32 18, label %bb4804.i
+ i32 19, label %bb4804.i
+ ]
+bb4794.i: ; preds = %bb4791.i, %bb4791.i
+ br i1 false, label %bb4809.i, label %bb4819.i
+bb4799.i: ; preds = %bb4791.i
+ br i1 false, label %bb4809.i, label %bb4819.i
+bb4803.i: ; preds = %bb4791.i
+ br label %bb4804.i
+bb4804.i: ; preds = %bb4803.i, %bb4791.i, %bb4791.i, %bb4791.i, %bb4791.i, %bb4791.i, %bb4791.i, %bb4791.i, %bb4791.i, %bb4791.i, %bb4791.i, %bb4791.i, %bb4791.i
+ br i1 false, label %bb4809.i, label %bb4819.i
+bb4809.i: ; preds = %bb4804.i, %bb4799.i, %bb4794.i
+ switch i32 %df4081.0.i, label %bb71.i.i [
+ i32 3, label %bb61.i.i
+ i32 4, label %bb.i.i
+ i32 5, label %bb.i.i
+ i32 6, label %bb.i.i
+ i32 7, label %bb.i.i
+ i32 8, label %bb38.i.i
+ i32 9, label %bb38.i.i
+ i32 10, label %bb50.i.i
+ i32 11, label %bb40.i.i
+ i32 16, label %bb38.i.i
+ ]
+bb.i.i: ; preds = %bb4809.i, %bb4809.i, %bb4809.i, %bb4809.i
+ br label %bb403.i.i
+bb38.i.i: ; preds = %bb4809.i, %bb4809.i, %bb4809.i
+ br label %bb403.i.i
+bb40.i.i: ; preds = %bb4809.i
+ br label %bb403.i.i
+bb50.i.i: ; preds = %bb4809.i
+ br label %bb403.i.i
+bb61.i.i: ; preds = %bb4809.i
+ br label %bb403.i.i
+bb71.i.i: ; preds = %bb4809.i
+ br label %bb403.i.i
+bb403.i.i: ; preds = %bb71.i.i, %bb61.i.i, %bb50.i.i, %bb40.i.i, %bb38.i.i, %bb.i.i
+ br i1 false, label %bb408.i.i, label %bb502.i.i
+bb408.i.i: ; preds = %bb403.i.i
+ br label %bb708.i.i
+bb502.i.i: ; preds = %bb403.i.i
+ br label %bb708.i.i
+bb708.i.i: ; preds = %bb502.i.i, %bb408.i.i
+ switch i32 0, label %bb758.i.i [
+ i32 0, label %bb710.i.i
+ i32 1, label %bb713.i.i
+ i32 2, label %bb718.i.i
+ i32 3, label %bb721.i.i
+ i32 4, label %bb726.i.i
+ i32 5, label %bb729.i.i
+ i32 8, label %bb732.i.i
+ i32 9, label %bb732.i.i
+ i32 10, label %bb737.i.i
+ i32 11, label %bb737.i.i
+ i32 12, label %bb742.i.i
+ i32 13, label %bb742.i.i
+ i32 14, label %bb745.i.i
+ i32 15, label %bb745.i.i
+ i32 16, label %bb750.i.i
+ i32 17, label %bb750.i.i
+ i32 18, label %bb753.i.i
+ i32 19, label %bb753.i.i
+ i32 22, label %bb750.i.i
+ i32 23, label %bb750.i.i
+ ]
+bb710.i.i: ; preds = %bb708.i.i
+ br label %bb758.i.i
+bb713.i.i: ; preds = %bb708.i.i
+ br label %bb758.i.i
+bb718.i.i: ; preds = %bb708.i.i
+ br label %bb758.i.i
+bb721.i.i: ; preds = %bb708.i.i
+ br label %bb758.i.i
+bb726.i.i: ; preds = %bb708.i.i
+ br label %bb758.i.i
+bb729.i.i: ; preds = %bb708.i.i
+ br label %bb758.i.i
+bb732.i.i: ; preds = %bb708.i.i, %bb708.i.i
+ br label %bb758.i.i
+bb737.i.i: ; preds = %bb708.i.i, %bb708.i.i
+ br label %bb758.i.i
+bb742.i.i: ; preds = %bb708.i.i, %bb708.i.i
+ br label %bb758.i.i
+bb745.i.i: ; preds = %bb708.i.i, %bb708.i.i
+ br label %bb758.i.i
+bb750.i.i: ; preds = %bb708.i.i, %bb708.i.i, %bb708.i.i, %bb708.i.i
+ br label %bb758.i.i
+bb753.i.i: ; preds = %bb708.i.i, %bb708.i.i
+ br label %bb758.i.i
+bb758.i.i: ; preds = %bb753.i.i, %bb750.i.i, %bb745.i.i, %bb742.i.i, %bb737.i.i, %bb732.i.i, %bb729.i.i, %bb726.i.i, %bb721.i.i, %bb718.i.i, %bb713.i.i, %bb710.i.i, %bb708.i.i
+ switch i32 %dt4080.0.i, label %bb808.i.i [
+ i32 0, label %bb760.i.i
+ i32 1, label %bb763.i.i
+ i32 2, label %bb768.i.i
+ i32 3, label %bb771.i.i
+ i32 4, label %bb776.i.i
+ i32 5, label %bb779.i.i
+ i32 8, label %bb782.i.i
+ i32 9, label %bb782.i.i
+ i32 10, label %bb787.i.i
+ i32 11, label %bb787.i.i
+ i32 12, label %bb792.i.i
+ i32 13, label %bb792.i.i
+ i32 14, label %bb795.i.i
+ i32 15, label %bb795.i.i
+ i32 16, label %bb800.i.i
+ i32 17, label %bb800.i.i
+ i32 18, label %bb803.i.i
+ i32 19, label %bb803.i.i
+ i32 22, label %bb800.i.i
+ i32 23, label %bb800.i.i
+ ]
+bb760.i.i: ; preds = %bb758.i.i
+ br label %bb811.i.i
+bb763.i.i: ; preds = %bb758.i.i
+ br label %bb811.i.i
+bb768.i.i: ; preds = %bb758.i.i
+ br label %bb811.i.i
+bb771.i.i: ; preds = %bb758.i.i
+ br label %bb811.i.i
+bb776.i.i: ; preds = %bb758.i.i
+ br label %bb811.i.i
+bb779.i.i: ; preds = %bb758.i.i
+ br label %bb811.i.i
+bb782.i.i: ; preds = %bb758.i.i, %bb758.i.i
+ br label %bb811.i.i
+bb787.i.i: ; preds = %bb758.i.i, %bb758.i.i
+ br label %bb811.i.i
+bb792.i.i: ; preds = %bb758.i.i, %bb758.i.i
+ br label %bb811.i.i
+bb795.i.i: ; preds = %bb758.i.i, %bb758.i.i
+ br label %bb811.i.i
+bb800.i.i: ; preds = %bb758.i.i, %bb758.i.i, %bb758.i.i, %bb758.i.i
+ br label %bb811.i.i
+bb803.i.i: ; preds = %bb758.i.i, %bb758.i.i
+ br label %bb808.i.i
+bb808.i.i: ; preds = %bb803.i.i, %bb758.i.i
+ br label %bb811.i.i
+bb811.i.i: ; preds = %bb808.i.i, %bb800.i.i, %bb795.i.i, %bb792.i.i, %bb787.i.i, %bb782.i.i, %bb779.i.i, %bb776.i.i, %bb771.i.i, %bb768.i.i, %bb763.i.i, %bb760.i.i
+ switch i32 0, label %bb928.i.i [
+ i32 0, label %bb813.i.i
+ i32 1, label %bb833.i.i
+ i32 2, label %bb813.i.i
+ i32 3, label %bb833.i.i
+ i32 4, label %bb813.i.i
+ i32 5, label %bb813.i.i
+ i32 8, label %bb872.i.i
+ i32 9, label %bb872.i.i
+ i32 10, label %bb890.i.i
+ i32 11, label %bb890.i.i
+ i32 12, label %bb813.i.i
+ i32 13, label %bb813.i.i
+ i32 14, label %bb908.i.i
+ i32 15, label %bb908.i.i
+ i32 16, label %bb813.i.i
+ i32 17, label %bb813.i.i
+ i32 18, label %bb908.i.i
+ i32 19, label %bb908.i.i
+ i32 22, label %bb813.i.i
+ i32 23, label %bb813.i.i
+ ]
+bb813.i.i: ; preds = %bb811.i.i, %bb811.i.i, %bb811.i.i, %bb811.i.i, %bb811.i.i, %bb811.i.i, %bb811.i.i, %bb811.i.i, %bb811.i.i, %bb811.i.i
+ switch i32 %dt4080.0.i, label %bb1065.i.i [
+ i32 0, label %bb930.i.i
+ i32 1, label %bb950.i.i
+ i32 2, label %bb930.i.i
+ i32 3, label %bb950.i.i
+ i32 4, label %bb989.i.i
+ i32 5, label %bb989.i.i
+ i32 8, label %bb1009.i.i
+ i32 9, label %bb1009.i.i
+ i32 10, label %bb1027.i.i
+ i32 11, label %bb1027.i.i
+ i32 12, label %bb930.i.i
+ i32 13, label %bb930.i.i
+ i32 14, label %bb1045.i.i
+ i32 15, label %bb1045.i.i
+ i32 16, label %bb930.i.i
+ i32 17, label %bb930.i.i
+ i32 18, label %bb1045.i.i
+ i32 19, label %bb1045.i.i
+ i32 22, label %bb930.i.i
+ i32 23, label %bb930.i.i
+ ]
+bb833.i.i: ; preds = %bb811.i.i, %bb811.i.i
+ switch i32 %dt4080.0.i, label %bb1065.i.i [
+ i32 0, label %bb930.i.i
+ i32 1, label %bb950.i.i
+ i32 2, label %bb930.i.i
+ i32 3, label %bb950.i.i
+ i32 4, label %bb989.i.i
+ i32 5, label %bb989.i.i
+ i32 8, label %bb1009.i.i
+ i32 9, label %bb1009.i.i
+ i32 10, label %bb1027.i.i
+ i32 11, label %bb1027.i.i
+ i32 12, label %bb930.i.i
+ i32 13, label %bb930.i.i
+ i32 14, label %bb1045.i.i
+ i32 15, label %bb1045.i.i
+ i32 16, label %bb930.i.i
+ i32 17, label %bb930.i.i
+ i32 18, label %bb1045.i.i
+ i32 19, label %bb1045.i.i
+ i32 22, label %bb930.i.i
+ i32 23, label %bb930.i.i
+ ]
+bb872.i.i: ; preds = %bb811.i.i, %bb811.i.i
+ switch i32 %dt4080.0.i, label %bb1065.i.i [
+ i32 0, label %bb930.i.i
+ i32 1, label %bb950.i.i
+ i32 2, label %bb930.i.i
+ i32 3, label %bb950.i.i
+ i32 4, label %bb989.i.i
+ i32 5, label %bb989.i.i
+ i32 8, label %bb1009.i.i
+ i32 9, label %bb1009.i.i
+ i32 10, label %bb1027.i.i
+ i32 11, label %bb1027.i.i
+ i32 12, label %bb930.i.i
+ i32 13, label %bb930.i.i
+ i32 14, label %bb1045.i.i
+ i32 15, label %bb1045.i.i
+ i32 16, label %bb930.i.i
+ i32 17, label %bb930.i.i
+ i32 18, label %bb1045.i.i
+ i32 19, label %bb1045.i.i
+ i32 22, label %bb930.i.i
+ i32 23, label %bb930.i.i
+ ]
+bb890.i.i: ; preds = %bb811.i.i, %bb811.i.i
+ switch i32 %dt4080.0.i, label %bb1065.i.i [
+ i32 0, label %bb930.i.i
+ i32 1, label %bb950.i.i
+ i32 2, label %bb930.i.i
+ i32 3, label %bb950.i.i
+ i32 4, label %bb989.i.i
+ i32 5, label %bb989.i.i
+ i32 8, label %bb1009.i.i
+ i32 9, label %bb1009.i.i
+ i32 10, label %bb1027.i.i
+ i32 11, label %bb1027.i.i
+ i32 12, label %bb930.i.i
+ i32 13, label %bb930.i.i
+ i32 14, label %bb1045.i.i
+ i32 15, label %bb1045.i.i
+ i32 16, label %bb930.i.i
+ i32 17, label %bb930.i.i
+ i32 18, label %bb1045.i.i
+ i32 19, label %bb1045.i.i
+ i32 22, label %bb930.i.i
+ i32 23, label %bb930.i.i
+ ]
+bb908.i.i: ; preds = %bb811.i.i, %bb811.i.i, %bb811.i.i, %bb811.i.i
+ br label %bb928.i.i
+bb928.i.i: ; preds = %bb908.i.i, %bb811.i.i
+ switch i32 %dt4080.0.i, label %bb1065.i.i [
+ i32 0, label %bb930.i.i
+ i32 1, label %bb950.i.i
+ i32 2, label %bb930.i.i
+ i32 3, label %bb950.i.i
+ i32 4, label %bb989.i.i
+ i32 5, label %bb989.i.i
+ i32 8, label %bb1009.i.i
+ i32 9, label %bb1009.i.i
+ i32 10, label %bb1027.i.i
+ i32 11, label %bb1027.i.i
+ i32 12, label %bb930.i.i
+ i32 13, label %bb930.i.i
+ i32 14, label %bb1045.i.i
+ i32 15, label %bb1045.i.i
+ i32 16, label %bb930.i.i
+ i32 17, label %bb930.i.i
+ i32 18, label %bb1045.i.i
+ i32 19, label %bb1045.i.i
+ i32 22, label %bb930.i.i
+ i32 23, label %bb930.i.i
+ ]
+bb930.i.i: ; preds = %bb928.i.i, %bb928.i.i, %bb928.i.i, %bb928.i.i, %bb928.i.i, %bb928.i.i, %bb928.i.i, %bb928.i.i, %bb890.i.i, %bb890.i.i, %bb890.i.i, %bb890.i.i, %bb890.i.i, %bb890.i.i, %bb890.i.i, %bb890.i.i, %bb872.i.i, %bb872.i.i, %bb872.i.i, %bb872.i.i, %bb872.i.i, %bb872.i.i, %bb872.i.i, %bb872.i.i, %bb833.i.i, %bb833.i.i, %bb833.i.i, %bb833.i.i, %bb833.i.i, %bb833.i.i, %bb833.i.i, %bb833.i.i, %bb813.i.i, %bb813.i.i, %bb813.i.i, %bb813.i.i, %bb813.i.i, %bb813.i.i, %bb813.i.i, %bb813.i.i
+ br label %bb5235.i
+bb950.i.i: ; preds = %bb928.i.i, %bb928.i.i, %bb890.i.i, %bb890.i.i, %bb872.i.i, %bb872.i.i, %bb833.i.i, %bb833.i.i, %bb813.i.i, %bb813.i.i
+ br label %bb5235.i
+bb989.i.i: ; preds = %bb928.i.i, %bb928.i.i, %bb890.i.i, %bb890.i.i, %bb872.i.i, %bb872.i.i, %bb833.i.i, %bb833.i.i, %bb813.i.i, %bb813.i.i
+ br label %bb5235.i
+bb1009.i.i: ; preds = %bb928.i.i, %bb928.i.i, %bb890.i.i, %bb890.i.i, %bb872.i.i, %bb872.i.i, %bb833.i.i, %bb833.i.i, %bb813.i.i, %bb813.i.i
+ br label %bb5235.i
+bb1027.i.i: ; preds = %bb928.i.i, %bb928.i.i, %bb890.i.i, %bb890.i.i, %bb872.i.i, %bb872.i.i, %bb833.i.i, %bb833.i.i, %bb813.i.i, %bb813.i.i
+ br label %bb5235.i
+bb1045.i.i: ; preds = %bb928.i.i, %bb928.i.i, %bb928.i.i, %bb928.i.i, %bb890.i.i, %bb890.i.i, %bb890.i.i, %bb890.i.i, %bb872.i.i, %bb872.i.i, %bb872.i.i, %bb872.i.i, %bb833.i.i, %bb833.i.i, %bb833.i.i, %bb833.i.i, %bb813.i.i, %bb813.i.i, %bb813.i.i, %bb813.i.i
+ br label %bb1065.i.i
+bb1065.i.i: ; preds = %bb1045.i.i, %bb928.i.i, %bb890.i.i, %bb872.i.i, %bb833.i.i, %bb813.i.i
+ br label %bb5235.i
+bb4819.i: ; preds = %bb4804.i, %bb4799.i, %bb4794.i
+ br i1 false, label %bb5208.i, label %bb5011.i
+bb5011.i: ; preds = %bb4819.i
+ switch i32 0, label %bb5039.i [
+ i32 10, label %bb5016.i
+ i32 3, label %bb5103.i
+ ]
+bb5016.i: ; preds = %bb5011.i
+ br i1 false, label %bb5103.i, label %bb5039.i
+bb5039.i: ; preds = %bb5016.i, %bb5011.i
+ switch i32 0, label %bb5052.i [
+ i32 3, label %bb5103.i
+ i32 10, label %bb5103.i
+ ]
+bb5052.i: ; preds = %bb5039.i
+ br i1 false, label %bb5103.i, label %bb5065.i
+bb5065.i: ; preds = %bb5052.i
+ br i1 false, label %bb5078.i, label %bb5103.i
+bb5078.i: ; preds = %bb5065.i
+ br i1 false, label %bb5103.i, label %bb5084.i
+bb5084.i: ; preds = %bb5078.i
+ br i1 false, label %bb5103.i, label %bb5090.i
+bb5090.i: ; preds = %bb5084.i
+ br i1 false, label %bb5103.i, label %bb5096.i
+bb5096.i: ; preds = %bb5090.i
+ br i1 false, label %bb5103.i, label %bb5102.i
+bb5102.i: ; preds = %bb5096.i
+ br label %bb5103.i
+bb5103.i: ; preds = %bb5102.i, %bb5096.i, %bb5090.i, %bb5084.i, %bb5078.i, %bb5065.i, %bb5052.i, %bb5039.i, %bb5039.i, %bb5016.i, %bb5011.i
+ switch i32 0, label %bb5208.i [
+ i32 0, label %bb5133.i
+ i32 2, label %bb5162.i
+ i32 4, label %bb5182.i
+ i32 10, label %bb5113.i
+ i32 11, label %bb5113.i
+ i32 12, label %bb5121.i
+ i32 13, label %bb5121.i
+ i32 14, label %bb5125.i
+ i32 15, label %bb5125.i
+ i32 16, label %bb5133.i
+ i32 17, label %bb5133.i
+ i32 18, label %bb5146.i
+ i32 19, label %bb5146.i
+ ]
+bb5113.i: ; preds = %bb5103.i, %bb5103.i
+ switch i32 %dt4080.0.i, label %bb5208.i [
+ i32 8, label %bb5115.i
+ i32 9, label %bb5115.i
+ i32 12, label %bb5117.i
+ i32 13, label %bb5117.i
+ i32 14, label %bb5119.i
+ i32 15, label %bb5119.i
+ ]
+bb5115.i: ; preds = %bb5113.i, %bb5113.i
+ br label %bb5208.i
+bb5117.i: ; preds = %bb5113.i, %bb5113.i
+ br label %bb5208.i
+bb5119.i: ; preds = %bb5113.i, %bb5113.i
+ br label %bb5208.i
+bb5121.i: ; preds = %bb5103.i, %bb5103.i
+ switch i32 %dt4080.0.i, label %bb5208.i [
+ i32 8, label %bb5123.i
+ i32 9, label %bb5123.i
+ ]
+bb5123.i: ; preds = %bb5121.i, %bb5121.i
+ br label %bb5208.i
+bb5125.i: ; preds = %bb5103.i, %bb5103.i
+ switch i32 %dt4080.0.i, label %bb5208.i [
+ i32 8, label %bb5127.i
+ i32 9, label %bb5127.i
+ i32 12, label %bb5129.i
+ i32 13, label %bb5129.i
+ ]
+bb5127.i: ; preds = %bb5125.i, %bb5125.i
+ br label %bb5208.i
+bb5129.i: ; preds = %bb5125.i, %bb5125.i
+ br label %bb5208.i
+bb5133.i: ; preds = %bb5103.i, %bb5103.i, %bb5103.i
+ switch i32 %dt4080.0.i, label %bb5208.i [
+ i32 8, label %bb5135.i
+ i32 9, label %bb5135.i
+ i32 10, label %bb5137.i
+ i32 11, label %bb5137.i
+ i32 12, label %bb5139.i
+ i32 13, label %bb5139.i
+ i32 14, label %bb5143.i
+ i32 15, label %bb5143.i
+ ]
+bb5135.i: ; preds = %bb5133.i, %bb5133.i
+ br label %bb5208.i
+bb5137.i: ; preds = %bb5133.i, %bb5133.i
+ br label %bb5208.i
+bb5139.i: ; preds = %bb5133.i, %bb5133.i
+ br label %bb5208.i
+bb5143.i: ; preds = %bb5133.i, %bb5133.i
+ br label %bb5208.i
+bb5146.i: ; preds = %bb5103.i, %bb5103.i
+ switch i32 %dt4080.0.i, label %bb5208.i [
+ i32 0, label %bb5158.i
+ i32 8, label %bb5148.i
+ i32 9, label %bb5148.i
+ i32 10, label %bb5150.i
+ i32 11, label %bb5150.i
+ i32 12, label %bb5152.i
+ i32 13, label %bb5152.i
+ i32 14, label %bb5155.i
+ i32 15, label %bb5155.i
+ i32 16, label %bb5158.i
+ i32 17, label %bb5158.i
+ ]
+bb5148.i: ; preds = %bb5146.i, %bb5146.i
+ br label %bb5208.i
+bb5150.i: ; preds = %bb5146.i, %bb5146.i
+ br label %bb5208.i
+bb5152.i: ; preds = %bb5146.i, %bb5146.i
+ br label %bb5208.i
+bb5155.i: ; preds = %bb5146.i, %bb5146.i
+ br label %bb5208.i
+bb5158.i: ; preds = %bb5146.i, %bb5146.i, %bb5146.i
+ br label %bb5208.i
+bb5162.i: ; preds = %bb5103.i
+ switch i32 %dt4080.0.i, label %bb5208.i [
+ i32 0, label %bb5175.i
+ i32 8, label %bb5164.i
+ i32 9, label %bb5164.i
+ i32 10, label %bb5166.i
+ i32 11, label %bb5166.i
+ i32 12, label %bb5168.i
+ i32 13, label %bb5168.i
+ i32 14, label %bb5172.i
+ i32 15, label %bb5172.i
+ i32 16, label %bb5175.i
+ i32 17, label %bb5175.i
+ i32 18, label %bb5179.i
+ i32 19, label %bb5179.i
+ ]
+bb5164.i: ; preds = %bb5162.i, %bb5162.i
+ br label %bb5208.i
+bb5166.i: ; preds = %bb5162.i, %bb5162.i
+ br label %bb5208.i
+bb5168.i: ; preds = %bb5162.i, %bb5162.i
+ br label %bb5208.i
+bb5172.i: ; preds = %bb5162.i, %bb5162.i
+ br label %bb5208.i
+bb5175.i: ; preds = %bb5162.i, %bb5162.i, %bb5162.i
+ br label %bb5208.i
+bb5179.i: ; preds = %bb5162.i, %bb5162.i
+ br label %bb5208.i
+bb5182.i: ; preds = %bb5103.i
+ switch i32 %dt4080.0.i, label %bb5208.i [
+ i32 0, label %bb5195.i
+ i32 2, label %bb5202.i
+ i32 8, label %bb5184.i
+ i32 9, label %bb5184.i
+ i32 10, label %bb5186.i
+ i32 11, label %bb5186.i
+ i32 12, label %bb5188.i
+ i32 13, label %bb5188.i
+ i32 14, label %bb5192.i
+ i32 15, label %bb5192.i
+ i32 16, label %bb5195.i
+ i32 17, label %bb5195.i
+ i32 18, label %bb5199.i
+ i32 19, label %bb5199.i
+ ]
+bb5184.i: ; preds = %bb5182.i, %bb5182.i
+ br label %bb5208.i
+bb5186.i: ; preds = %bb5182.i, %bb5182.i
+ br label %bb5208.i
+bb5188.i: ; preds = %bb5182.i, %bb5182.i
+ br label %bb5208.i
+bb5192.i: ; preds = %bb5182.i, %bb5182.i
+ br label %bb5208.i
+bb5195.i: ; preds = %bb5182.i, %bb5182.i, %bb5182.i
+ br label %bb5208.i
+bb5199.i: ; preds = %bb5182.i, %bb5182.i
+ br label %bb5208.i
+bb5202.i: ; preds = %bb5182.i
+ br label %bb5208.i
+bb5208.i: ; preds = %bb5202.i, %bb5199.i, %bb5195.i, %bb5192.i, %bb5188.i, %bb5186.i, %bb5184.i, %bb5182.i, %bb5179.i, %bb5175.i, %bb5172.i, %bb5168.i, %bb5166.i, %bb5164.i, %bb5162.i, %bb5158.i, %bb5155.i, %bb5152.i, %bb5150.i, %bb5148.i, %bb5146.i, %bb5143.i, %bb5139.i, %bb5137.i, %bb5135.i, %bb5133.i, %bb5129.i, %bb5127.i, %bb5125.i, %bb5123.i, %bb5121.i, %bb5119.i, %bb5117.i, %bb5115.i, %bb5113.i, %bb5103.i, %bb4819.i
+ switch i32 0, label %bb5221.i [
+ i32 0, label %bb5210.i
+ i32 1, label %bb5211.i
+ i32 2, label %bb5212.i
+ i32 3, label %bb5213.i
+ i32 4, label %bb5214.i
+ i32 5, label %bb5215.i
+ i32 6, label %bb5217.i
+ i32 7, label %bb5216.i
+ i32 12, label %bb5218.i
+ i32 13, label %bb5218.i
+ i32 14, label %bb5219.i
+ i32 15, label %bb5219.i
+ i32 16, label %bb5210.i
+ i32 17, label %bb5210.i
+ i32 22, label %bb5210.i
+ i32 23, label %bb5210.i
+ ]
+bb5210.i: ; preds = %bb5208.i, %bb5208.i, %bb5208.i, %bb5208.i, %bb5208.i
+ br label %bb5224.i
+bb5211.i: ; preds = %bb5208.i
+ br label %bb5224.i
+bb5212.i: ; preds = %bb5208.i
+ br label %bb5224.i
+bb5213.i: ; preds = %bb5208.i
+ br label %bb5224.i
+bb5214.i: ; preds = %bb5208.i
+ br label %bb5224.i
+bb5215.i: ; preds = %bb5208.i
+ br label %bb5224.i
+bb5216.i: ; preds = %bb5208.i
+ br label %bb5224.i
+bb5217.i: ; preds = %bb5208.i
+ br label %bb5224.i
+bb5218.i: ; preds = %bb5208.i, %bb5208.i
+ br label %bb5224.i
+bb5219.i: ; preds = %bb5208.i, %bb5208.i
+ br label %bb5224.i
+bb5221.i: ; preds = %bb5208.i
+ br label %bb5224.i
+bb5224.i: ; preds = %bb5221.i, %bb5219.i, %bb5218.i, %bb5217.i, %bb5216.i, %bb5215.i, %bb5214.i, %bb5213.i, %bb5212.i, %bb5211.i, %bb5210.i
+ br label %bb5235.i
+bb5235.i: ; preds = %bb5224.i, %bb1065.i.i, %bb1027.i.i, %bb1009.i.i, %bb989.i.i, %bb950.i.i, %bb930.i.i
+ br label %bb5272.i
+bb5272.i: ; preds = %bb5235.i
+ br label %bb5276.i
+bb5276.i: ; preds = %bb19808.i, %bb5272.i
+ br label %bb16607.i
+bb5295.i: ; preds = %bb5295.preheader.i, %storeVecColor_RGB_UI.exit
+ br label %loadVecColor_BGRA_UI8888R.exit
+loadVecColor_BGRA_UI8888R.exit: ; preds = %bb5295.i
+ br i1 false, label %bb5325.i, label %bb5351.i
+bb5325.i: ; preds = %loadVecColor_BGRA_UI8888R.exit
+ br i1 false, label %bb4527.i, label %bb.i
+bb.i: ; preds = %bb5325.i
+ switch i32 0, label %bb4527.i [
+ i32 4, label %bb4362.i
+ i32 8, label %bb4448.i
+ ]
+bb4362.i: ; preds = %bb.i
+ br i1 false, label %bb4532.i, label %bb5556.i
+bb4448.i: ; preds = %bb.i
+ br label %bb4527.i
+bb4527.i: ; preds = %bb4448.i, %bb.i, %bb5325.i
+ br i1 false, label %bb4532.i, label %bb5556.i
+bb4532.i: ; preds = %bb4527.i, %bb4362.i
+ switch i32 0, label %bb4997.i [
+ i32 6, label %bb4534.i
+ i32 7, label %bb4982.i
+ ]
+bb4534.i: ; preds = %bb4532.i
+ br i1 false, label %bb4875.i, label %bb4619.i
+bb4619.i: ; preds = %bb4534.i
+ br i1 false, label %bb4875.i, label %bb4663.i
+bb4663.i: ; preds = %bb4619.i
+ br label %bb4855.i
+bb4759.i: ; preds = %bb4855.i
+ br label %bb4855.i
+bb4855.i: ; preds = %bb4759.i, %bb4663.i
+ br i1 false, label %bb4866.i, label %bb4759.i
+bb4866.i: ; preds = %bb4855.i
+ br label %bb4875.i
+bb4875.i: ; preds = %bb4866.i, %bb4619.i, %bb4534.i
+ br i1 false, label %bb4973.i, label %bb4922.i
+bb4922.i: ; preds = %bb4875.i
+ br label %bb4973.i
+bb4973.i: ; preds = %bb4922.i, %bb4875.i
+ br label %bb4982.i
+bb4982.i: ; preds = %bb4973.i, %bb4532.i
+ br label %bb5041.i
+bb4997.i: ; preds = %bb4532.i
+ br label %bb5041.i
+bb5041.i: ; preds = %bb4997.i, %bb4982.i
+ switch i32 0, label %bb5464.i [
+ i32 0, label %bb5344.i
+ i32 1, label %bb5374.i
+ i32 2, label %bb5404.i
+ i32 3, label %bb5434.i
+ i32 11, label %bb5263.i
+ ]
+bb5263.i: ; preds = %bb5041.i
+ br i1 false, label %bb12038.i, label %bb5467.i
+bb5344.i: ; preds = %bb5041.i
+ br i1 false, label %bb12038.i, label %bb5467.i
+bb5374.i: ; preds = %bb5041.i
+ br i1 false, label %bb12038.i, label %bb5467.i
+bb5404.i: ; preds = %bb5041.i
+ br i1 false, label %bb12038.i, label %bb5467.i
+bb5434.i: ; preds = %bb5041.i
+ br label %bb5464.i
+bb5464.i: ; preds = %bb5434.i, %bb5041.i
+ br i1 false, label %bb12038.i, label %bb5467.i
+bb5467.i: ; preds = %bb5464.i, %bb5404.i, %bb5374.i, %bb5344.i, %bb5263.i
+ switch i32 0, label %bb15866.i [
+ i32 3, label %bb13016.i
+ i32 4, label %bb12040.i
+ i32 8, label %bb12514.i
+ i32 10, label %bb12903.i
+ i32 11, label %bb12553.i
+ i32 16, label %bb12514.i
+ ]
+bb5556.i: ; preds = %bb4527.i, %bb4362.i
+ switch i32 0, label %bb8990.i [
+ i32 3, label %bb6403.i
+ i32 4, label %bb6924.i
+ i32 8, label %bb6924.i
+ i32 10, label %bb6403.i
+ i32 11, label %bb5882.i
+ i32 16, label %bb5558.i
+ ]
+bb5558.i: ; preds = %bb5556.i
+ br label %bb8990.i
+bb5882.i: ; preds = %bb5556.i
+ switch i32 0, label %bb6387.i [
+ i32 1, label %bb6332.i
+ i32 3, label %bb6332.i
+ i32 4, label %bb6352.i
+ i32 6, label %bb5884.i
+ i32 7, label %bb8990.i
+ ]
+bb5884.i: ; preds = %bb5882.i
+ br i1 false, label %bb6225.i, label %bb5969.i
+bb5969.i: ; preds = %bb5884.i
+ br i1 false, label %bb6225.i, label %bb6013.i
+bb6013.i: ; preds = %bb5969.i
+ br label %bb6205.i
+bb6109.i: ; preds = %bb6205.i
+ br label %bb6205.i
+bb6205.i: ; preds = %bb6109.i, %bb6013.i
+ br i1 false, label %bb6216.i, label %bb6109.i
+bb6216.i: ; preds = %bb6205.i
+ br label %bb6225.i
+bb6225.i: ; preds = %bb6216.i, %bb5969.i, %bb5884.i
+ br i1 false, label %bb6323.i, label %bb6272.i
+bb6272.i: ; preds = %bb6225.i
+ switch i32 0, label %bb6908.i [
+ i32 1, label %bb6853.i48
+ i32 3, label %bb6853.i48
+ i32 4, label %bb6873.i
+ i32 6, label %bb6405.i
+ i32 7, label %bb8990.i
+ ]
+bb6323.i: ; preds = %bb6225.i
+ switch i32 0, label %bb6908.i [
+ i32 1, label %bb6853.i48
+ i32 3, label %bb6853.i48
+ i32 4, label %bb6873.i
+ i32 6, label %bb6405.i
+ i32 7, label %bb8990.i
+ ]
+bb6332.i: ; preds = %bb5882.i, %bb5882.i
+ switch i32 0, label %bb6908.i [
+ i32 1, label %bb6853.i48
+ i32 3, label %bb6853.i48
+ i32 4, label %bb6873.i
+ i32 6, label %bb6405.i
+ i32 7, label %bb8990.i
+ ]
+bb6352.i: ; preds = %bb5882.i
+ br label %bb6873.i
+bb6387.i: ; preds = %bb5882.i
+ br label %bb6403.i
+bb6403.i: ; preds = %bb6387.i, %bb5556.i, %bb5556.i
+ switch i32 0, label %bb6908.i [
+ i32 1, label %bb6853.i48
+ i32 3, label %bb6853.i48
+ i32 4, label %bb6873.i
+ i32 6, label %bb6405.i
+ i32 7, label %bb8990.i
+ ]
+bb6405.i: ; preds = %bb6403.i, %bb6332.i, %bb6323.i, %bb6272.i
+ br i1 false, label %bb6746.i, label %bb6490.i
+bb6490.i: ; preds = %bb6405.i
+ br i1 false, label %bb6746.i, label %bb6534.i
+bb6534.i: ; preds = %bb6490.i
+ br label %bb6726.i
+bb6630.i: ; preds = %bb6726.i
+ br label %bb6726.i
+bb6726.i: ; preds = %bb6630.i, %bb6534.i
+ br i1 false, label %bb6737.i, label %bb6630.i
+bb6737.i: ; preds = %bb6726.i
+ br label %bb6746.i
+bb6746.i: ; preds = %bb6737.i, %bb6490.i, %bb6405.i
+ br i1 false, label %bb6844.i, label %bb6793.i
+bb6793.i: ; preds = %bb6746.i
+ br label %bb8990.i
+bb6844.i: ; preds = %bb6746.i
+ br label %bb8990.i
+bb6853.i48: ; preds = %bb6403.i, %bb6403.i, %bb6332.i, %bb6332.i, %bb6323.i, %bb6323.i, %bb6272.i, %bb6272.i
+ br label %bb8990.i
+bb6873.i: ; preds = %bb6403.i, %bb6352.i, %bb6332.i, %bb6323.i, %bb6272.i
+ br label %bb8990.i
+bb6908.i: ; preds = %bb6403.i, %bb6332.i, %bb6323.i, %bb6272.i
+ br label %bb8990.i
+bb6924.i: ; preds = %bb5556.i, %bb5556.i
+ switch i32 0, label %bb8929.i [
+ i32 1, label %bb8715.i
+ i32 3, label %bb8715.i
+ i32 4, label %bb8792.i
+ i32 6, label %bb6926.i
+ i32 7, label %bb8990.i
+ ]
+bb6926.i: ; preds = %bb6924.i
+ br i1 false, label %bb7267.i, label %bb7011.i
+bb7011.i: ; preds = %bb6926.i
+ br i1 false, label %bb7267.i, label %bb7055.i
+bb7055.i: ; preds = %bb7011.i
+ br label %bb7247.i
+bb7151.i: ; preds = %bb7247.i
+ br label %bb7247.i
+bb7247.i: ; preds = %bb7151.i, %bb7055.i
+ br i1 false, label %bb7258.i, label %bb7151.i
+bb7258.i: ; preds = %bb7247.i
+ br label %bb7267.i
+bb7267.i: ; preds = %bb7258.i, %bb7011.i, %bb6926.i
+ br i1 false, label %bb7365.i, label %bb7314.i
+bb7314.i: ; preds = %bb7267.i
+ br label %bb7365.i
+bb7365.i: ; preds = %bb7314.i, %bb7267.i
+ br i1 false, label %bb7714.i, label %bb7458.i
+bb7458.i: ; preds = %bb7365.i
+ br i1 false, label %bb7714.i, label %bb7502.i
+bb7502.i: ; preds = %bb7458.i
+ br label %bb7694.i
+bb7598.i: ; preds = %bb7694.i
+ br label %bb7694.i
+bb7694.i: ; preds = %bb7598.i, %bb7502.i
+ br i1 false, label %bb7705.i, label %bb7598.i
+bb7705.i: ; preds = %bb7694.i
+ br label %bb7714.i
+bb7714.i: ; preds = %bb7705.i, %bb7458.i, %bb7365.i
+ br i1 false, label %bb7812.i, label %bb7761.i
+bb7761.i: ; preds = %bb7714.i
+ br label %bb7812.i
+bb7812.i: ; preds = %bb7761.i, %bb7714.i
+ br i1 false, label %bb8161.i, label %bb7905.i
+bb7905.i: ; preds = %bb7812.i
+ br i1 false, label %bb8161.i, label %bb7949.i
+bb7949.i: ; preds = %bb7905.i
+ br label %bb8141.i
+bb8045.i: ; preds = %bb8141.i
+ br label %bb8141.i
+bb8141.i: ; preds = %bb8045.i, %bb7949.i
+ br i1 false, label %bb8152.i, label %bb8045.i
+bb8152.i: ; preds = %bb8141.i
+ br label %bb8161.i
+bb8161.i: ; preds = %bb8152.i, %bb7905.i, %bb7812.i
+ br i1 false, label %bb8259.i, label %bb8208.i
+bb8208.i: ; preds = %bb8161.i
+ br label %bb8259.i
+bb8259.i: ; preds = %bb8208.i, %bb8161.i
+ br i1 false, label %bb8608.i, label %bb8352.i
+bb8352.i: ; preds = %bb8259.i
+ br i1 false, label %bb8608.i, label %bb8396.i
+bb8396.i: ; preds = %bb8352.i
+ br label %bb8588.i63
+bb8492.i: ; preds = %bb8588.i63
+ br label %bb8588.i63
+bb8588.i63: ; preds = %bb8492.i, %bb8396.i
+ br i1 false, label %bb8599.i, label %bb8492.i
+bb8599.i: ; preds = %bb8588.i63
+ br label %bb8608.i
+bb8608.i: ; preds = %bb8599.i, %bb8352.i, %bb8259.i
+ br i1 false, label %bb8706.i, label %bb8655.i
+bb8655.i: ; preds = %bb8608.i
+ br label %bb8990.i
+bb8706.i: ; preds = %bb8608.i
+ br label %bb8990.i
+bb8715.i: ; preds = %bb6924.i, %bb6924.i
+ br label %bb8990.i
+bb8792.i: ; preds = %bb6924.i
+ br label %bb8990.i
+bb8929.i: ; preds = %bb6924.i
+ br label %bb8990.i
+bb8990.i: ; preds = %bb8929.i, %bb8792.i, %bb8715.i, %bb8706.i, %bb8655.i, %bb6924.i, %bb6908.i, %bb6873.i, %bb6853.i48, %bb6844.i, %bb6793.i, %bb6403.i, %bb6332.i, %bb6323.i, %bb6272.i, %bb5882.i, %bb5558.i, %bb5556.i
+ switch i32 %sf4083.0.i, label %bb11184.i [
+ i32 0, label %bb10372.i
+ i32 1, label %bb10609.i
+ i32 2, label %bb10811.i
+ i32 3, label %bb11013.i
+ i32 4, label %bb8992.i
+ i32 5, label %bb8992.i
+ i32 6, label %bb8992.i
+ i32 7, label %bb8992.i
+ i32 8, label %bb9195.i
+ i32 9, label %bb9195.i
+ i32 10, label %bb9965.i
+ i32 11, label %bb9585.i
+ i32 16, label %bb9195.i
+ ]
+bb8992.i: ; preds = %bb8990.i, %bb8990.i, %bb8990.i, %bb8990.i
+ switch i32 0, label %bb11184.i [
+ i32 0, label %bb9075.i
+ i32 1, label %bb9105.i
+ i32 2, label %bb9135.i
+ i32 3, label %bb9165.i
+ i32 11, label %bb8994.i
+ ]
+bb8994.i: ; preds = %bb8992.i
+ br label %bb11247.i
+bb9075.i: ; preds = %bb8992.i
+ br label %bb11247.i
+bb9105.i: ; preds = %bb8992.i
+ br label %bb11247.i
+bb9135.i: ; preds = %bb8992.i
+ br label %bb11247.i
+bb9165.i: ; preds = %bb8992.i
+ br label %bb11247.i
+bb9195.i: ; preds = %bb8990.i, %bb8990.i, %bb8990.i
+ switch i32 0, label %bb11184.i [
+ i32 0, label %bb9491.i
+ i32 1, label %bb9521.i
+ i32 2, label %bb9551.i
+ i32 3, label %bb9581.i
+ i32 4, label %bb9197.i
+ i32 11, label %bb9342.i
+ ]
+bb9197.i: ; preds = %bb9195.i
+ br label %bb11247.i
+bb9342.i: ; preds = %bb9195.i
+ br label %bb11247.i
+bb9491.i: ; preds = %bb9195.i
+ br label %bb11247.i
+bb9521.i: ; preds = %bb9195.i
+ br label %bb11247.i
+bb9551.i: ; preds = %bb9195.i
+ br label %bb11247.i
+bb9581.i: ; preds = %bb9195.i
+ br label %bb11247.i
+bb9585.i: ; preds = %bb8990.i
+ switch i32 0, label %bb11184.i [
+ i32 0, label %bb9879.i
+ i32 1, label %bb9920.i
+ i32 2, label %bb9920.i
+ i32 3, label %bb9924.i
+ i32 4, label %bb9587.i
+ i32 8, label %bb9587.i
+ ]
+bb9587.i: ; preds = %bb9585.i, %bb9585.i
+ br label %bb11247.i
+bb9879.i: ; preds = %bb9585.i
+ br label %bb11247.i
+bb9920.i: ; preds = %bb9585.i, %bb9585.i
+ br label %bb11247.i
+bb9924.i: ; preds = %bb9585.i
+ br label %bb11247.i
+bb9965.i: ; preds = %bb8990.i
+ switch i32 0, label %bb11184.i [
+ i32 1, label %bb10368.i
+ i32 2, label %bb10368.i
+ i32 3, label %bb10364.i
+ i32 4, label %bb9967.i
+ i32 8, label %bb10127.i
+ i32 11, label %bb10287.i
+ ]
+bb9967.i: ; preds = %bb9965.i
+ br label %bb11247.i
+bb10127.i: ; preds = %bb9965.i
+ br label %bb11247.i
+bb10287.i: ; preds = %bb9965.i
+ br label %bb11247.i
+bb10364.i: ; preds = %bb9965.i
+ br label %bb11247.i
+bb10368.i: ; preds = %bb9965.i, %bb9965.i
+ br label %bb11247.i
+bb10372.i: ; preds = %bb8990.i
+ switch i32 0, label %bb11184.i [
+ i32 1, label %bb10605.i
+ i32 2, label %bb10605.i
+ i32 3, label %bb10601.i
+ i32 4, label %bb10374.i
+ i32 8, label %bb10449.i
+ i32 11, label %bb10524.i
+ ]
+bb10374.i: ; preds = %bb10372.i
+ br label %bb11247.i
+bb10449.i: ; preds = %bb10372.i
+ br label %bb11247.i
+bb10524.i: ; preds = %bb10372.i
+ br label %bb11247.i
+bb10601.i: ; preds = %bb10372.i
+ br label %bb11247.i
+bb10605.i: ; preds = %bb10372.i, %bb10372.i
+ br label %bb11247.i
+bb10609.i: ; preds = %bb8990.i
+ switch i32 0, label %bb11184.i [
+ i32 0, label %bb10807.i
+ i32 2, label %bb10807.i
+ i32 3, label %bb10803.i
+ i32 4, label %bb10611.i
+ i32 8, label %bb10686.i
+ i32 11, label %bb10761.i
+ ]
+bb10611.i: ; preds = %bb10609.i
+ br label %bb11247.i
+bb10686.i: ; preds = %bb10609.i
+ br label %bb11247.i
+bb10761.i: ; preds = %bb10609.i
+ br label %bb11247.i
+bb10803.i: ; preds = %bb10609.i
+ br label %bb11247.i
+bb10807.i: ; preds = %bb10609.i, %bb10609.i
+ br label %bb11247.i
+bb10811.i: ; preds = %bb8990.i
+ switch i32 0, label %bb11184.i [
+ i32 0, label %bb11009.i
+ i32 1, label %bb11009.i
+ i32 3, label %bb11005.i
+ i32 4, label %bb10813.i
+ i32 8, label %bb10888.i
+ i32 11, label %bb10963.i
+ ]
+bb10813.i: ; preds = %bb10811.i
+ br label %bb11247.i
+bb10888.i: ; preds = %bb10811.i
+ br label %bb11247.i
+bb10963.i: ; preds = %bb10811.i
+ br label %bb11247.i
+bb11005.i: ; preds = %bb10811.i
+ br label %bb11247.i
+bb11009.i: ; preds = %bb10811.i, %bb10811.i
+ br label %bb11247.i
+bb11013.i: ; preds = %bb8990.i
+ switch i32 0, label %bb11184.i [
+ i32 0, label %bb11180.i
+ i32 1, label %bb11180.i
+ i32 2, label %bb11180.i
+ i32 4, label %bb11015.i
+ i32 8, label %bb11090.i
+ i32 11, label %bb11103.i
+ ]
+bb11015.i: ; preds = %bb11013.i
+ br label %bb11247.i
+bb11090.i: ; preds = %bb11013.i
+ br label %bb11247.i
+bb11103.i: ; preds = %bb11013.i
+ br label %bb11247.i
+bb11180.i: ; preds = %bb11013.i, %bb11013.i, %bb11013.i
+ br label %bb11184.i
+bb11184.i: ; preds = %bb11180.i, %bb11013.i, %bb10811.i, %bb10609.i, %bb10372.i, %bb9965.i, %bb9585.i, %bb9195.i, %bb8992.i, %bb8990.i
+ br label %bb11247.i
+bb11247.i: ; preds = %bb11184.i, %bb11103.i, %bb11090.i, %bb11015.i, %bb11009.i, %bb11005.i, %bb10963.i, %bb10888.i, %bb10813.i, %bb10807.i, %bb10803.i, %bb10761.i, %bb10686.i, %bb10611.i, %bb10605.i, %bb10601.i, %bb10524.i, %bb10449.i, %bb10374.i, %bb10368.i, %bb10364.i, %bb10287.i, %bb10127.i, %bb9967.i, %bb9924.i, %bb9920.i, %bb9879.i, %bb9587.i, %bb9581.i, %bb9551.i, %bb9521.i, %bb9491.i, %bb9342.i, %bb9197.i, %bb9165.i, %bb9135.i, %bb9105.i, %bb9075.i, %bb8994.i
+ br i1 false, label %bb11250.i, label %bb11256.i
+bb11250.i: ; preds = %bb11247.i
+ br label %bb11378.i
+bb11256.i: ; preds = %bb11247.i
+ switch i32 0, label %bb11348.i [
+ i32 4, label %bb11258.i
+ i32 8, label %bb11258.i
+ i32 11, label %bb11318.i
+ ]
+bb11258.i: ; preds = %bb11256.i, %bb11256.i
+ br i1 false, label %bb11273.i, label %bb11261.i
+bb11261.i: ; preds = %bb11258.i
+ br label %bb11273.i
+bb11273.i: ; preds = %bb11261.i, %bb11258.i
+ br i1 false, label %bb11288.i, label %bb11276.i
+bb11276.i: ; preds = %bb11273.i
+ br label %bb11288.i
+bb11288.i: ; preds = %bb11276.i, %bb11273.i
+ br i1 false, label %bb11303.i, label %bb11291.i
+bb11291.i: ; preds = %bb11288.i
+ br label %bb11303.i
+bb11303.i: ; preds = %bb11291.i, %bb11288.i
+ br i1 false, label %bb11318.i, label %bb11306.i
+bb11306.i: ; preds = %bb11303.i
+ br label %bb11318.i
+bb11318.i: ; preds = %bb11306.i, %bb11303.i, %bb11256.i
+ br i1 false, label %bb11333.i, label %bb11321.i
+bb11321.i: ; preds = %bb11318.i
+ br label %bb11333.i
+bb11333.i: ; preds = %bb11321.i, %bb11318.i
+ br i1 false, label %bb11348.i, label %bb11336.i
+bb11336.i: ; preds = %bb11333.i
+ br label %bb11348.i
+bb11348.i: ; preds = %bb11336.i, %bb11333.i, %bb11256.i
+ br i1 false, label %bb11363.i, label %bb11351.i
+bb11351.i: ; preds = %bb11348.i
+ br label %bb11363.i
+bb11363.i: ; preds = %bb11351.i, %bb11348.i
+ br i1 false, label %bb11378.i, label %bb11366.i
+bb11366.i: ; preds = %bb11363.i
+ br label %bb11378.i
+bb11378.i: ; preds = %bb11366.i, %bb11363.i, %bb11250.i
+ br label %bb12038.i
+bb12038.i: ; preds = %bb11378.i, %bb5464.i, %bb5404.i, %bb5374.i, %bb5344.i, %bb5263.i
+ switch i32 0, label %bb15866.i [
+ i32 3, label %bb13016.i
+ i32 4, label %bb12040.i
+ i32 8, label %bb12514.i
+ i32 10, label %bb12903.i
+ i32 11, label %bb12553.i
+ i32 16, label %bb12514.i
+ ]
+bb12040.i: ; preds = %bb12038.i, %bb5467.i
+ br label %bb13026.i
+bb12514.i: ; preds = %bb12038.i, %bb12038.i, %bb5467.i, %bb5467.i
+ br label %bb13026.i
+bb12553.i: ; preds = %bb12038.i, %bb5467.i
+ br i1 false, label %bb12558.i, label %bb12747.i
+bb12558.i: ; preds = %bb12553.i
+ br i1 false, label %bb12666.i, label %bb12654.i
+bb12654.i: ; preds = %bb12558.i
+ br label %bb12666.i
+bb12666.i: ; preds = %bb12654.i, %bb12558.i
+ br label %bb12747.i
+bb12747.i: ; preds = %bb12666.i, %bb12553.i
+ br label %bb13026.i
+bb12903.i: ; preds = %bb12038.i, %bb5467.i
+ br i1 false, label %bb12908.i, label %bb13026.i
+bb12908.i: ; preds = %bb12903.i
+ br i1 false, label %bb13026.i, label %bb13004.i
+bb13004.i: ; preds = %bb12908.i
+ switch i32 0, label %bb15866.i [
+ i32 3, label %bb13752.i
+ i32 4, label %bb14197.i
+ i32 8, label %bb14197.i
+ i32 10, label %bb13752.i
+ i32 11, label %bb13307.i
+ i32 16, label %bb13028.i
+ ]
+bb13016.i: ; preds = %bb12038.i, %bb5467.i
+ br label %bb13026.i
+bb13026.i: ; preds = %bb13016.i, %bb12908.i, %bb12903.i, %bb12747.i, %bb12514.i, %bb12040.i
+ switch i32 0, label %bb15866.i [
+ i32 3, label %bb13752.i
+ i32 4, label %bb14197.i
+ i32 8, label %bb14197.i
+ i32 10, label %bb13752.i
+ i32 11, label %bb13307.i
+ i32 16, label %bb13028.i
+ ]
+bb13028.i: ; preds = %bb13026.i, %bb13004.i
+ br i1 false, label %UnifiedReturnBlock.i177, label %bb15869.i
+bb13307.i: ; preds = %bb13026.i, %bb13004.i
+ switch i32 %dt4080.0.i, label %bb13736.i [
+ i32 6, label %bb13312.i
+ i32 1, label %bb13624.i
+ i32 3, label %bb13624.i
+ i32 5, label %bb13649.i
+ i32 4, label %bb13688.i
+ i32 7, label %bb15866.i
+ ]
+bb13312.i: ; preds = %bb13307.i
+ br i1 false, label %bb13483.i, label %bb13400.i
+bb13400.i: ; preds = %bb13312.i
+ br label %bb13483.i
+bb13483.i: ; preds = %bb13400.i, %bb13312.i
+ br i1 false, label %bb13593.i, label %bb13505.i
+bb13505.i: ; preds = %bb13483.i
+ switch i32 %dt4080.0.i, label %bb14181.i [
+ i32 6, label %bb13757.i
+ i32 1, label %bb14069.i
+ i32 3, label %bb14069.i
+ i32 5, label %bb14094.i
+ i32 4, label %bb14133.i
+ i32 7, label %bb15866.i
+ ]
+bb13593.i: ; preds = %bb13483.i
+ switch i32 %dt4080.0.i, label %bb14181.i [
+ i32 6, label %bb13757.i
+ i32 1, label %bb14069.i
+ i32 3, label %bb14069.i
+ i32 5, label %bb14094.i
+ i32 4, label %bb14133.i
+ i32 7, label %bb15866.i
+ ]
+bb13624.i: ; preds = %bb13307.i, %bb13307.i
+ switch i32 %dt4080.0.i, label %bb14181.i [
+ i32 6, label %bb13757.i
+ i32 1, label %bb14069.i
+ i32 3, label %bb14069.i
+ i32 5, label %bb14094.i
+ i32 4, label %bb14133.i
+ i32 7, label %bb15866.i
+ ]
+bb13649.i: ; preds = %bb13307.i
+ br label %bb14094.i
+bb13688.i: ; preds = %bb13307.i
+ br label %bb14133.i
+bb13736.i: ; preds = %bb13307.i
+ br label %bb13752.i
+bb13752.i: ; preds = %bb13736.i, %bb13026.i, %bb13026.i, %bb13004.i, %bb13004.i
+ switch i32 %dt4080.0.i, label %bb14181.i [
+ i32 6, label %bb13757.i
+ i32 1, label %bb14069.i
+ i32 3, label %bb14069.i
+ i32 5, label %bb14094.i
+ i32 4, label %bb14133.i
+ i32 7, label %bb15866.i
+ ]
+bb13757.i: ; preds = %bb13752.i, %bb13624.i, %bb13593.i, %bb13505.i
+ br i1 false, label %bb13928.i, label %bb13845.i
+bb13845.i: ; preds = %bb13757.i
+ br label %bb13928.i
+bb13928.i: ; preds = %bb13845.i, %bb13757.i
+ br i1 false, label %bb14038.i, label %bb13950.i
+bb13950.i: ; preds = %bb13928.i
+ br i1 false, label %UnifiedReturnBlock.i177, label %bb15869.i
+bb14038.i: ; preds = %bb13928.i
+ br i1 false, label %UnifiedReturnBlock.i177, label %bb15869.i
+bb14069.i: ; preds = %bb13752.i, %bb13752.i, %bb13624.i, %bb13624.i, %bb13593.i, %bb13593.i, %bb13505.i, %bb13505.i
+ br i1 false, label %UnifiedReturnBlock.i177, label %bb15869.i
+bb14094.i: ; preds = %bb13752.i, %bb13649.i, %bb13624.i, %bb13593.i, %bb13505.i
+ br i1 false, label %UnifiedReturnBlock.i177, label %bb15869.i
+bb14133.i: ; preds = %bb13752.i, %bb13688.i, %bb13624.i, %bb13593.i, %bb13505.i
+ br i1 false, label %UnifiedReturnBlock.i177, label %bb15869.i
+bb14181.i: ; preds = %bb13752.i, %bb13624.i, %bb13593.i, %bb13505.i
+ br i1 false, label %UnifiedReturnBlock.i177, label %bb15869.i
+bb14197.i: ; preds = %bb13026.i, %bb13026.i, %bb13004.i, %bb13004.i
+ switch i32 %dt4080.0.i, label %bb15805.i [
+ i32 6, label %bb14202.i
+ i32 1, label %bb15411.i
+ i32 3, label %bb15411.i
+ i32 5, label %bb15493.i
+ i32 4, label %bb15631.i
+ i32 7, label %bb15866.i
+ ]
+bb14202.i: ; preds = %bb14197.i
+ br i1 false, label %bb14373.i, label %bb14290.i
+bb14290.i: ; preds = %bb14202.i
+ br label %bb14373.i
+bb14373.i: ; preds = %bb14290.i, %bb14202.i
+ br i1 false, label %bb14483.i, label %bb14395.i
+bb14395.i: ; preds = %bb14373.i
+ br label %bb14483.i
+bb14483.i: ; preds = %bb14395.i, %bb14373.i
+ br i1 false, label %bb14672.i, label %bb14589.i
+bb14589.i: ; preds = %bb14483.i
+ br label %bb14672.i
+bb14672.i: ; preds = %bb14589.i, %bb14483.i
+ br i1 false, label %bb14782.i, label %bb14694.i
+bb14694.i: ; preds = %bb14672.i
+ br label %bb14782.i
+bb14782.i: ; preds = %bb14694.i, %bb14672.i
+ br i1 false, label %bb14971.i, label %bb14888.i
+bb14888.i: ; preds = %bb14782.i
+ br label %bb14971.i
+bb14971.i: ; preds = %bb14888.i, %bb14782.i
+ br i1 false, label %bb15081.i, label %bb14993.i
+bb14993.i: ; preds = %bb14971.i
+ br label %bb15081.i
+bb15081.i: ; preds = %bb14993.i, %bb14971.i
+ br i1 false, label %bb15270.i, label %bb15187.i
+bb15187.i: ; preds = %bb15081.i
+ br label %bb15270.i
+bb15270.i: ; preds = %bb15187.i, %bb15081.i
+ br i1 false, label %bb15380.i, label %bb15292.i
+bb15292.i: ; preds = %bb15270.i
+ br i1 false, label %UnifiedReturnBlock.i177, label %bb15869.i
+bb15380.i: ; preds = %bb15270.i
+ br i1 false, label %UnifiedReturnBlock.i177, label %bb15869.i
+bb15411.i: ; preds = %bb14197.i, %bb14197.i
+ br i1 false, label %UnifiedReturnBlock.i177, label %bb15869.i
+bb15493.i: ; preds = %bb14197.i
+ br i1 false, label %UnifiedReturnBlock.i177, label %bb15869.i
+bb15631.i: ; preds = %bb14197.i
+ br i1 false, label %UnifiedReturnBlock.i177, label %bb15869.i
+bb15805.i: ; preds = %bb14197.i
+ br label %bb15866.i
+bb15866.i: ; preds = %bb15805.i, %bb14197.i, %bb13752.i, %bb13624.i, %bb13593.i, %bb13505.i, %bb13307.i, %bb13026.i, %bb13004.i, %bb12038.i, %bb5467.i
+ br i1 false, label %UnifiedReturnBlock.i177, label %bb15869.i
+bb15869.i: ; preds = %bb15866.i, %bb15631.i, %bb15493.i, %bb15411.i, %bb15380.i, %bb15292.i, %bb14181.i, %bb14133.i, %bb14094.i, %bb14069.i, %bb14038.i, %bb13950.i, %bb13028.i
+ switch i32 0, label %UnifiedReturnBlock.i177 [
+ i32 4, label %bb15874.i
+ i32 8, label %bb15960.i
+ ]
+bb15874.i: ; preds = %bb15869.i
+ br label %glgVectorFloatConversion.exit
+bb15960.i: ; preds = %bb15869.i
+ br label %glgVectorFloatConversion.exit
+UnifiedReturnBlock.i177: ; preds = %bb15869.i, %bb15866.i, %bb15631.i, %bb15493.i, %bb15411.i, %bb15380.i, %bb15292.i, %bb14181.i, %bb14133.i, %bb14094.i, %bb14069.i, %bb14038.i, %bb13950.i, %bb13028.i
+ br label %glgVectorFloatConversion.exit
+glgVectorFloatConversion.exit: ; preds = %UnifiedReturnBlock.i177, %bb15960.i, %bb15874.i
+ br label %bb16581.i
+bb5351.i: ; preds = %loadVecColor_BGRA_UI8888R.exit
+ br i1 false, label %bb5359.i, label %bb5586.i
+bb5359.i: ; preds = %bb5351.i
+ switch i32 0, label %bb5586.i [
+ i32 0, label %bb5361.i
+ i32 1, label %bb5511.i
+ i32 2, label %bb5511.i
+ ]
+bb5361.i: ; preds = %bb5359.i
+ br i1 false, label %bb5366.i, label %bb5379.i
+bb5366.i: ; preds = %bb5361.i
+ br label %bb7230.i
+bb5379.i: ; preds = %bb5361.i
+ switch i32 %sf4083.0.i, label %bb5415.i [
+ i32 1, label %bb5384.i
+ i32 2, label %bb5402.i
+ ]
+bb5384.i: ; preds = %bb5379.i
+ switch i32 0, label %bb7230.i [
+ i32 4, label %bb5445.i
+ i32 8, label %bb5445.i
+ i32 11, label %bb5445.i
+ ]
+bb5402.i: ; preds = %bb5379.i
+ switch i32 0, label %bb7230.i [
+ i32 4, label %bb5445.i
+ i32 8, label %bb5445.i
+ i32 11, label %bb5445.i
+ ]
+bb5415.i: ; preds = %bb5379.i
+ switch i32 0, label %bb7230.i [
+ i32 4, label %bb5445.i
+ i32 8, label %bb5445.i
+ i32 11, label %bb5445.i
+ ]
+bb5445.i: ; preds = %bb5415.i, %bb5415.i, %bb5415.i, %bb5402.i, %bb5402.i, %bb5402.i, %bb5384.i, %bb5384.i, %bb5384.i
+ switch i32 0, label %bb7230.i [
+ i32 4, label %bb5470.i
+ i32 8, label %bb5470.i
+ i32 11, label %bb6853.i
+ ]
+bb5470.i: ; preds = %bb5445.i, %bb5445.i
+ switch i32 0, label %bb7230.i [
+ i32 4, label %bb5498.i
+ i32 8, label %bb5493.i
+ i32 11, label %bb6853.i
+ ]
+bb5493.i: ; preds = %bb5470.i
+ br i1 false, label %bb5498.i, label %bb5586.i
+bb5498.i: ; preds = %bb5493.i, %bb5470.i
+ switch i32 0, label %bb7230.i [
+ i32 4, label %bb5591.i
+ i32 8, label %bb6153.i
+ i32 11, label %bb6853.i
+ ]
+bb5511.i: ; preds = %bb5359.i, %bb5359.i
+ br i1 false, label %bb5568.i, label %bb5586.i
+bb5568.i: ; preds = %bb5511.i
+ br label %bb5586.i
+bb5586.i: ; preds = %bb5568.i, %bb5511.i, %bb5493.i, %bb5359.i, %bb5351.i
+ switch i32 0, label %bb7230.i [
+ i32 4, label %bb5591.i
+ i32 8, label %bb6153.i
+ i32 11, label %bb6853.i
+ ]
+bb5591.i: ; preds = %bb5586.i, %bb5498.i
+ switch i32 0, label %bb5995.i [
+ i32 4, label %bb5596.i
+ i32 8, label %bb5680.i
+ i32 11, label %bb5842.i
+ ]
+bb5596.i: ; preds = %bb5591.i
+ br i1 false, label %bb8428.i, label %bb5602.i
+bb5602.i: ; preds = %bb5596.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb5680.i: ; preds = %bb5591.i
+ br i1 false, label %bb5692.i, label %bb5764.i
+bb5692.i: ; preds = %bb5680.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb5764.i: ; preds = %bb5680.i
+ br i1 false, label %bb8428.i, label %bb5772.i
+bb5772.i: ; preds = %bb5764.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb5842.i: ; preds = %bb5591.i
+ br i1 false, label %bb5920.i, label %bb5845.i
+bb5845.i: ; preds = %bb5842.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb5920.i: ; preds = %bb5842.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb5995.i: ; preds = %bb5591.i
+ switch i32 %df4081.0.i, label %bb8428.i [
+ i32 0, label %bb6007.i
+ i32 10, label %bb6007.i
+ i32 1, label %bb6042.i
+ i32 2, label %bb6079.i
+ i32 3, label %bb6116.i
+ ]
+bb6007.i: ; preds = %bb5995.i, %bb5995.i
+ br i1 false, label %bb6012.i, label %bb8428.i
+bb6012.i: ; preds = %bb6007.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6042.i: ; preds = %bb5995.i
+ br i1 false, label %bb6049.i, label %bb6045.i
+bb6045.i: ; preds = %bb6042.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6049.i: ; preds = %bb6042.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6079.i: ; preds = %bb5995.i
+ br i1 false, label %bb6086.i, label %bb6082.i
+bb6082.i: ; preds = %bb6079.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6086.i: ; preds = %bb6079.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6116.i: ; preds = %bb5995.i
+ br i1 false, label %bb6123.i, label %bb6119.i
+bb6119.i: ; preds = %bb6116.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6123.i: ; preds = %bb6116.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6153.i: ; preds = %bb5586.i, %bb5498.i
+ switch i32 0, label %bb6724.i [
+ i32 4, label %bb6158.i
+ i32 8, label %bb6459.i
+ i32 11, label %bb6621.i
+ ]
+bb6158.i: ; preds = %bb6153.i
+ br i1 false, label %bb6242.i, label %bb6161.i
+bb6161.i: ; preds = %bb6158.i
+ br i1 false, label %bb6239.i, label %bb6166.i
+bb6166.i: ; preds = %bb6161.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6239.i: ; preds = %bb6161.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6242.i: ; preds = %bb6158.i
+ br i1 false, label %bb6245.i, label %bb6317.i
+bb6245.i: ; preds = %bb6242.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6317.i: ; preds = %bb6242.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6459.i: ; preds = %bb6153.i
+ br i1 false, label %bb6471.i, label %bb6543.i
+bb6471.i: ; preds = %bb6459.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6543.i: ; preds = %bb6459.i
+ br i1 false, label %bb8428.i, label %bb6551.i
+bb6551.i: ; preds = %bb6543.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6621.i: ; preds = %bb6153.i
+ br i1 false, label %bb6626.i, label %bb6651.i
+bb6626.i: ; preds = %bb6621.i
+ br label %bb6651.i
+bb6651.i: ; preds = %bb6626.i, %bb6621.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6724.i: ; preds = %bb6153.i
+ switch i32 %df4081.0.i, label %bb8428.i [
+ i32 0, label %bb6736.i
+ i32 10, label %bb6736.i
+ i32 1, label %bb6771.i
+ i32 2, label %bb6808.i
+ i32 3, label %bb6845.i
+ ]
+bb6736.i: ; preds = %bb6724.i, %bb6724.i
+ br i1 false, label %bb6741.i, label %bb8428.i
+bb6741.i: ; preds = %bb6736.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6771.i: ; preds = %bb6724.i
+ br i1 false, label %bb6778.i, label %bb6774.i
+bb6774.i: ; preds = %bb6771.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6778.i: ; preds = %bb6771.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6808.i: ; preds = %bb6724.i
+ br i1 false, label %bb6815.i, label %bb6811.i
+bb6811.i: ; preds = %bb6808.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6815.i: ; preds = %bb6808.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6845.i: ; preds = %bb6724.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6853.i: ; preds = %bb5586.i, %bb5498.i, %bb5470.i, %bb5445.i
+ switch i32 0, label %bb8428.i [
+ i32 4, label %bb6858.i
+ i32 8, label %bb7072.i
+ i32 10, label %bb7149.i
+ i32 3, label %bb7192.i
+ ]
+bb6858.i: ; preds = %bb6853.i
+ br i1 false, label %bb6942.i, label %bb6861.i
+bb6861.i: ; preds = %bb6858.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb6942.i: ; preds = %bb6858.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7072.i: ; preds = %bb6853.i
+ br i1 false, label %bb7119.i, label %bb7075.i
+bb7075.i: ; preds = %bb7072.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7119.i: ; preds = %bb7072.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7149.i: ; preds = %bb6853.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7192.i: ; preds = %bb6853.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7230.i: ; preds = %bb5586.i, %bb5498.i, %bb5470.i, %bb5445.i, %bb5415.i, %bb5402.i, %bb5384.i, %bb5366.i
+ switch i32 %sf4083.0.i, label %bb8428.i [
+ i32 10, label %bb7235.i
+ i32 0, label %bb7455.i
+ i32 1, label %bb7725.i
+ i32 2, label %bb7978.i
+ i32 3, label %bb8231.i
+ ]
+bb7235.i: ; preds = %bb7230.i
+ switch i32 0, label %bb7442.i [
+ i32 4, label %bb7240.i
+ i32 8, label %bb7329.i
+ i32 11, label %bb7369.i
+ ]
+bb7240.i: ; preds = %bb7235.i
+ br i1 false, label %bb7252.i, label %bb7243.i
+bb7243.i: ; preds = %bb7240.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7252.i: ; preds = %bb7240.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7329.i: ; preds = %bb7235.i
+ br i1 false, label %bb7339.i, label %bb7332.i
+bb7332.i: ; preds = %bb7329.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7339.i: ; preds = %bb7329.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7369.i: ; preds = %bb7235.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7442.i: ; preds = %bb7235.i
+ br i1 false, label %bb7447.i, label %bb8428.i
+bb7447.i: ; preds = %bb7442.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7455.i: ; preds = %bb7230.i
+ switch i32 0, label %bb7703.i [
+ i32 4, label %bb7460.i
+ i32 8, label %bb7546.i
+ i32 11, label %bb7630.i
+ ]
+bb7460.i: ; preds = %bb7455.i
+ br i1 false, label %bb7471.i, label %bb7463.i
+bb7463.i: ; preds = %bb7460.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7471.i: ; preds = %bb7460.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7546.i: ; preds = %bb7455.i
+ br i1 false, label %bb7555.i, label %bb7549.i
+bb7549.i: ; preds = %bb7546.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7555.i: ; preds = %bb7546.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7630.i: ; preds = %bb7455.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7703.i: ; preds = %bb7455.i
+ br i1 false, label %bb7709.i, label %bb7712.i
+bb7709.i: ; preds = %bb7703.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7712.i: ; preds = %bb7703.i
+ br i1 false, label %bb7717.i, label %bb8428.i
+bb7717.i: ; preds = %bb7712.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7725.i: ; preds = %bb7230.i
+ switch i32 0, label %bb7945.i [
+ i32 4, label %bb7730.i
+ i32 8, label %bb7819.i
+ i32 11, label %bb7906.i
+ ]
+bb7730.i: ; preds = %bb7725.i
+ br i1 false, label %bb7744.i, label %bb7733.i
+bb7733.i: ; preds = %bb7730.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7744.i: ; preds = %bb7730.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7819.i: ; preds = %bb7725.i
+ br i1 false, label %bb7831.i, label %bb7822.i
+bb7822.i: ; preds = %bb7819.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7831.i: ; preds = %bb7819.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7906.i: ; preds = %bb7725.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7945.i: ; preds = %bb7725.i
+ switch i32 %df4081.0.i, label %bb8428.i [
+ i32 0, label %bb7962.i
+ i32 2, label %bb7962.i
+ i32 10, label %bb7962.i
+ i32 3, label %bb7970.i
+ ]
+bb7962.i: ; preds = %bb7945.i, %bb7945.i, %bb7945.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7970.i: ; preds = %bb7945.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7978.i: ; preds = %bb7230.i
+ switch i32 0, label %bb8198.i [
+ i32 4, label %bb7983.i
+ i32 8, label %bb8072.i
+ i32 11, label %bb8159.i
+ ]
+bb7983.i: ; preds = %bb7978.i
+ br i1 false, label %bb7997.i, label %bb7986.i
+bb7986.i: ; preds = %bb7983.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb7997.i: ; preds = %bb7983.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb8072.i: ; preds = %bb7978.i
+ br i1 false, label %bb8084.i, label %bb8075.i
+bb8075.i: ; preds = %bb8072.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb8084.i: ; preds = %bb8072.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb8159.i: ; preds = %bb7978.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb8198.i: ; preds = %bb7978.i
+ switch i32 %df4081.0.i, label %bb8428.i [
+ i32 0, label %bb8215.i
+ i32 1, label %bb8215.i
+ i32 10, label %bb8215.i
+ i32 3, label %bb8223.i
+ ]
+bb8215.i: ; preds = %bb8198.i, %bb8198.i, %bb8198.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb8223.i: ; preds = %bb8198.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb8231.i: ; preds = %bb7230.i
+ switch i32 0, label %bb8428.i [
+ i32 4, label %bb8236.i
+ i32 8, label %bb8326.i
+ i32 11, label %bb8347.i
+ i32 10, label %bb8425.i
+ ]
+bb8236.i: ; preds = %bb8231.i
+ br i1 false, label %bb8251.i, label %bb8239.i
+bb8239.i: ; preds = %bb8236.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb8251.i: ; preds = %bb8236.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb8326.i: ; preds = %bb8231.i
+ br i1 false, label %bb8339.i, label %bb8428.i
+bb8339.i: ; preds = %bb8326.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb8347.i: ; preds = %bb8231.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb8425.i: ; preds = %bb8231.i
+ br label %bb8428.i
+bb8428.i: ; preds = %bb8425.i, %bb8326.i, %bb8231.i, %bb8198.i, %bb7945.i, %bb7712.i, %bb7442.i, %bb7230.i, %bb6853.i, %bb6736.i, %bb6724.i, %bb6543.i, %bb6007.i, %bb5995.i, %bb5764.i, %bb5596.i
+ br i1 false, label %bb8668.i, label %bb8434.i
+bb8434.i: ; preds = %bb8428.i, %bb8347.i, %bb8339.i, %bb8251.i, %bb8239.i, %bb8223.i, %bb8215.i, %bb8159.i, %bb8084.i, %bb8075.i, %bb7997.i, %bb7986.i, %bb7970.i, %bb7962.i, %bb7906.i, %bb7831.i, %bb7822.i, %bb7744.i, %bb7733.i, %bb7717.i, %bb7709.i, %bb7630.i, %bb7555.i, %bb7549.i, %bb7471.i, %bb7463.i, %bb7447.i, %bb7369.i, %bb7339.i, %bb7332.i, %bb7252.i, %bb7243.i, %bb7192.i, %bb7149.i, %bb7119.i, %bb7075.i, %bb6942.i, %bb6861.i, %bb6845.i, %bb6815.i, %bb6811.i, %bb6778.i, %bb6774.i, %bb6741.i, %bb6651.i, %bb6551.i, %bb6471.i, %bb6317.i, %bb6245.i, %bb6239.i, %bb6166.i, %bb6123.i, %bb6119.i, %bb6086.i, %bb6082.i, %bb6049.i, %bb6045.i, %bb6012.i, %bb5920.i, %bb5845.i, %bb5772.i, %bb5692.i, %bb5602.i
+ switch i32 0, label %bb8668.i [
+ i32 0, label %bb8436.i
+ i32 1, label %bb8531.i
+ i32 2, label %bb8531.i
+ ]
+bb8436.i: ; preds = %bb8434.i
+ switch i32 0, label %bb9310.i [
+ i32 4, label %bb8465.i
+ i32 8, label %bb8465.i
+ i32 11, label %bb8465.i
+ i32 3, label %bb9301.i
+ ]
+bb8465.i: ; preds = %bb8436.i, %bb8436.i, %bb8436.i
+ switch i32 0, label %bb9310.i [
+ i32 4, label %bb8490.i
+ i32 8, label %bb8490.i
+ i32 3, label %bb9301.i
+ i32 11, label %bb9153.i
+ ]
+bb8490.i: ; preds = %bb8465.i, %bb8465.i
+ switch i32 0, label %bb9310.i [
+ i32 4, label %bb8518.i
+ i32 8, label %bb8513.i
+ i32 3, label %bb9301.i
+ i32 11, label %bb9153.i
+ ]
+bb8513.i: ; preds = %bb8490.i
+ br i1 false, label %bb8518.i, label %bb8668.i
+bb8518.i: ; preds = %bb8513.i, %bb8490.i
+ switch i32 0, label %bb9310.i [
+ i32 3, label %bb9301.i
+ i32 4, label %bb8670.i
+ i32 8, label %bb9112.i
+ i32 11, label %bb9153.i
+ ]
+bb8531.i: ; preds = %bb8434.i, %bb8434.i
+ br i1 false, label %bb8536.i, label %bb8575.i
+bb8536.i: ; preds = %bb8531.i
+ br i1 false, label %bb8557.i, label %bb8588.i
+bb8557.i: ; preds = %bb8536.i
+ switch i32 0, label %bb9310.i [
+ i32 4, label %bb8600.i
+ i32 8, label %bb8600.i
+ i32 3, label %bb9301.i
+ i32 11, label %bb9153.i
+ ]
+bb8575.i: ; preds = %bb8531.i
+ br label %bb8588.i
+bb8588.i: ; preds = %bb8575.i, %bb8536.i
+ switch i32 0, label %bb9310.i [
+ i32 4, label %bb8600.i
+ i32 8, label %bb8600.i
+ i32 3, label %bb9301.i
+ i32 11, label %bb9153.i
+ ]
+bb8600.i: ; preds = %bb8588.i, %bb8588.i, %bb8557.i, %bb8557.i
+ switch i32 0, label %bb9310.i [
+ i32 4, label %bb8629.i
+ i32 3, label %bb9301.i
+ i32 8, label %bb9112.i
+ i32 11, label %bb9153.i
+ ]
+bb8629.i: ; preds = %bb8600.i
+ br i1 false, label %bb8650.i, label %bb8668.i
+bb8650.i: ; preds = %bb8629.i
+ br label %bb8668.i
+bb8668.i: ; preds = %bb8650.i, %bb8629.i, %bb8513.i, %bb8434.i, %bb8428.i, %bb8347.i, %bb8339.i, %bb8251.i, %bb8239.i, %bb8223.i, %bb8215.i, %bb8159.i, %bb8084.i, %bb8075.i, %bb7997.i, %bb7986.i, %bb7970.i, %bb7962.i, %bb7906.i, %bb7831.i, %bb7822.i, %bb7744.i, %bb7733.i, %bb7717.i, %bb7709.i, %bb7630.i, %bb7555.i, %bb7549.i, %bb7471.i, %bb7463.i, %bb7447.i, %bb7369.i, %bb7339.i, %bb7332.i, %bb7252.i, %bb7243.i, %bb7192.i, %bb7149.i, %bb7119.i, %bb7075.i, %bb6942.i, %bb6861.i, %bb6845.i, %bb6815.i, %bb6811.i, %bb6778.i, %bb6774.i, %bb6741.i, %bb6651.i, %bb6551.i, %bb6471.i, %bb6317.i, %bb6245.i, %bb6239.i, %bb6166.i, %bb6123.i, %bb6119.i, %bb6086.i, %bb6082.i, %bb6049.i, %bb6045.i, %bb6012.i, %bb5920.i, %bb5845.i, %bb5772.i, %bb5692.i, %bb5602.i
+ switch i32 0, label %bb9310.i [
+ i32 3, label %bb9301.i
+ i32 4, label %bb8670.i
+ i32 8, label %bb9112.i
+ i32 11, label %bb9153.i
+ ]
+bb8670.i: ; preds = %bb8668.i, %bb8518.i
+ br label %bb9310.i
+bb9112.i: ; preds = %bb8668.i, %bb8600.i, %bb8518.i
+ br label %bb9310.i
+bb9153.i: ; preds = %bb8668.i, %bb8600.i, %bb8588.i, %bb8557.i, %bb8518.i, %bb8490.i, %bb8465.i
+ br label %bb9310.i
+bb9301.i: ; preds = %bb8668.i, %bb8600.i, %bb8588.i, %bb8557.i, %bb8518.i, %bb8490.i, %bb8465.i, %bb8436.i
+ br label %bb9310.i
+bb9310.i: ; preds = %bb9301.i, %bb9153.i, %bb9112.i, %bb8670.i, %bb8668.i, %bb8600.i, %bb8588.i, %bb8557.i, %bb8518.i, %bb8490.i, %bb8465.i, %bb8436.i
+ br i1 false, label %bb16581.i, label %bb9313.i
+bb9313.i: ; preds = %bb9310.i
+ switch i32 %dt4080.0.i, label %bb16578.i [
+ i32 0, label %bb9315.i
+ i32 1, label %bb9890.i
+ i32 2, label %bb10465.i
+ i32 3, label %bb11040.i
+ i32 4, label %bb11615.i
+ i32 5, label %bb11823.i
+ i32 8, label %bb12398.i
+ i32 9, label %bb12833.i
+ i32 10, label %bb13268.i
+ i32 11, label %bb13268.i
+ i32 12, label %bb13703.i
+ i32 13, label %bb13703.i
+ i32 14, label %bb14278.i
+ i32 15, label %bb14853.i
+ i32 16, label %bb9315.i
+ i32 17, label %bb9315.i
+ i32 18, label %bb15428.i
+ i32 19, label %bb16003.i
+ ]
+bb9315.i: ; preds = %bb9313.i, %bb9313.i, %bb9313.i
+ br i1 false, label %bb9535.i, label %bb9323.i
+bb9323.i: ; preds = %bb9315.i
+ br label %bb9535.i
+bb9535.i: ; preds = %bb9323.i, %bb9315.i
+ br label %bb16581.i
+bb9890.i: ; preds = %bb9313.i
+ br i1 false, label %bb10255.i, label %bb9898.i
+bb9898.i: ; preds = %bb9890.i
+ br label %bb10255.i
+bb10255.i: ; preds = %bb9898.i, %bb9890.i
+ br label %bb16581.i
+bb10465.i: ; preds = %bb9313.i
+ br i1 false, label %bb10685.i, label %bb10473.i
+bb10473.i: ; preds = %bb10465.i
+ br label %bb10685.i
+bb10685.i: ; preds = %bb10473.i, %bb10465.i
+ br label %bb16581.i
+bb11040.i: ; preds = %bb9313.i
+ br i1 false, label %bb11405.i, label %bb11048.i
+bb11048.i: ; preds = %bb11040.i
+ br label %bb11405.i
+bb11405.i: ; preds = %bb11048.i, %bb11040.i
+ br label %bb16581.i
+bb11615.i: ; preds = %bb9313.i
+ br i1 false, label %bb16581.i, label %bb11618.i
+bb11618.i: ; preds = %bb11615.i
+ br label %bb16581.i
+bb11823.i: ; preds = %bb9313.i
+ br i1 false, label %bb12188.i, label %bb11831.i
+bb11831.i: ; preds = %bb11823.i
+ br label %bb12188.i
+bb12188.i: ; preds = %bb11831.i, %bb11823.i
+ br label %bb16581.i
+bb12398.i: ; preds = %bb9313.i
+ br i1 false, label %bb12566.i, label %bb12406.i
+bb12406.i: ; preds = %bb12398.i
+ br label %bb12566.i
+bb12566.i: ; preds = %bb12406.i, %bb12398.i
+ br label %bb16581.i
+bb12833.i: ; preds = %bb9313.i
+ br i1 false, label %bb13001.i, label %bb12841.i
+bb12841.i: ; preds = %bb12833.i
+ br label %bb13001.i
+bb13001.i: ; preds = %bb12841.i, %bb12833.i
+ br label %bb16581.i
+bb13268.i: ; preds = %bb9313.i, %bb9313.i
+ br i1 false, label %bb13436.i, label %bb13276.i
+bb13276.i: ; preds = %bb13268.i
+ br label %bb13436.i
+bb13436.i: ; preds = %bb13276.i, %bb13268.i
+ br label %bb16581.i
+bb13703.i: ; preds = %bb9313.i, %bb9313.i
+ br i1 false, label %bb13923.i, label %bb13711.i
+bb13711.i: ; preds = %bb13703.i
+ br label %bb13923.i
+bb13923.i: ; preds = %bb13711.i, %bb13703.i
+ br label %bb16581.i
+bb14278.i: ; preds = %bb9313.i
+ br i1 false, label %bb14498.i, label %bb14286.i
+bb14286.i: ; preds = %bb14278.i
+ br label %bb14498.i
+bb14498.i: ; preds = %bb14286.i, %bb14278.i
+ br label %bb16581.i
+bb14853.i: ; preds = %bb9313.i
+ br i1 false, label %bb15073.i, label %bb14861.i
+bb14861.i: ; preds = %bb14853.i
+ br label %bb15073.i
+bb15073.i: ; preds = %bb14861.i, %bb14853.i
+ br label %bb16581.i
+bb15428.i: ; preds = %bb9313.i
+ br i1 false, label %bb15648.i, label %bb15436.i
+bb15436.i: ; preds = %bb15428.i
+ br label %bb15648.i
+bb15648.i: ; preds = %bb15436.i, %bb15428.i
+ br label %bb16581.i
+bb16003.i: ; preds = %bb9313.i
+ br i1 false, label %bb16223.i, label %bb16011.i
+bb16011.i: ; preds = %bb16003.i
+ br label %bb16223.i
+bb16223.i: ; preds = %bb16011.i, %bb16003.i
+ br label %bb16581.i
+bb16578.i: ; preds = %bb9313.i
+ unreachable
+bb16581.i: ; preds = %bb16223.i, %bb15648.i, %bb15073.i, %bb14498.i, %bb13923.i, %bb13436.i, %bb13001.i, %bb12566.i, %bb12188.i, %bb11618.i, %bb11615.i, %bb11405.i, %bb10685.i, %bb10255.i, %bb9535.i, %bb9310.i, %glgVectorFloatConversion.exit
+ br label %storeVecColor_RGB_UI.exit
+storeVecColor_RGB_UI.exit: ; preds = %bb16581.i
+ br i1 false, label %bb5295.i, label %bb16621.i
+bb16607.i: ; preds = %bb5276.i
+ br i1 false, label %bb5295.preheader.i, label %bb16621.i
+bb5295.preheader.i: ; preds = %bb16607.i
+ br label %bb5295.i
+bb16621.i: ; preds = %bb16607.i, %storeVecColor_RGB_UI.exit
+ br label %bb16650.outer.i
+bb16650.outer.i: ; preds = %bb16621.i
+ br label %bb16650.i
+bb16650.i: ; preds = %storeColor_RGB_UI.exit, %bb16650.outer.i
+ br label %loadColor_BGRA_UI8888R.exit
+loadColor_BGRA_UI8888R.exit: ; preds = %bb16650.i
+ br i1 false, label %bb16671.i, label %bb16697.i
+bb16671.i: ; preds = %loadColor_BGRA_UI8888R.exit
+ br i1 false, label %bb.i179, label %bb662.i
+bb.i179: ; preds = %bb16671.i
+ switch i32 0, label %bb513.i [
+ i32 7, label %bb418.i
+ i32 6, label %bb433.i
+ ]
+bb418.i: ; preds = %bb.i179
+ br label %bb559.i
+bb433.i: ; preds = %bb.i179
+ switch i32 0, label %bb493.i [
+ i32 31744, label %bb455.i
+ i32 0, label %bb471.i
+ ]
+bb455.i: ; preds = %bb433.i
+ br i1 false, label %bb463.i, label %bb504.i
+bb463.i: ; preds = %bb455.i
+ br label %bb559.i
+bb471.i: ; preds = %bb433.i
+ br i1 false, label %bb497.i, label %bb484.preheader.i
+bb484.preheader.i: ; preds = %bb471.i
+ br i1 false, label %bb479.i, label %bb490.i
+bb479.i: ; preds = %bb479.i, %bb484.preheader.i
+ br i1 false, label %bb479.i, label %bb490.i
+bb490.i: ; preds = %bb479.i, %bb484.preheader.i
+ br label %bb559.i
+bb493.i: ; preds = %bb433.i
+ br label %bb497.i
+bb497.i: ; preds = %bb493.i, %bb471.i
+ br label %bb504.i
+bb504.i: ; preds = %bb497.i, %bb455.i
+ br label %bb513.i
+bb513.i: ; preds = %bb504.i, %bb.i179
+ br label %bb559.i
+bb559.i: ; preds = %bb513.i, %bb490.i, %bb463.i, %bb418.i
+ br i1 false, label %bb2793.i, label %bb614.i
+bb614.i: ; preds = %bb559.i
+ br i1 false, label %bb626.i, label %bb620.i
+bb620.i: ; preds = %bb614.i
+ br i1 false, label %bb625.i, label %bb626.i
+bb625.i: ; preds = %bb620.i
+ br label %bb626.i
+bb626.i: ; preds = %bb625.i, %bb620.i, %bb614.i
+ br i1 false, label %bb638.i, label %bb632.i
+bb632.i: ; preds = %bb626.i
+ br i1 false, label %bb637.i, label %bb638.i
+bb637.i: ; preds = %bb632.i
+ br label %bb638.i
+bb638.i: ; preds = %bb637.i, %bb632.i, %bb626.i
+ br i1 false, label %bb650.i, label %bb644.i
+bb644.i: ; preds = %bb638.i
+ br i1 false, label %bb649.i, label %bb650.i
+bb649.i: ; preds = %bb644.i
+ br label %bb650.i
+bb650.i: ; preds = %bb649.i, %bb644.i, %bb638.i
+ br i1 false, label %bb2793.i, label %bb656.i
+bb656.i: ; preds = %bb650.i
+ br i1 false, label %bb661.i, label %bb2793.i
+bb661.i: ; preds = %bb656.i
+ switch i32 0, label %bb2883.i [
+ i32 3, label %bb2874.i
+ i32 4, label %bb2795.i
+ i32 8, label %bb2810.i
+ i32 10, label %bb2834.i
+ i32 11, label %bb2819.i
+ i32 16, label %bb2810.i
+ ]
+bb662.i: ; preds = %bb16671.i
+ switch i32 0, label %bb1937.i [
+ i32 3, label %bb902.i
+ i32 4, label %bb1416.i
+ i32 8, label %bb1020.i
+ i32 10, label %bb902.i
+ i32 11, label %bb784.i
+ i32 16, label %bb664.i
+ ]
+bb664.i: ; preds = %bb662.i
+ br i1 false, label %bb682.i, label %bb669.i
+bb669.i: ; preds = %bb664.i
+ br label %bb710.i
+bb682.i: ; preds = %bb664.i
+ br label %bb710.i
+bb710.i: ; preds = %bb682.i, %bb669.i
+ br i1 false, label %bb760.i, label %bb754.i
+bb754.i: ; preds = %bb710.i
+ br i1 false, label %bb759.i, label %bb760.i
+bb759.i: ; preds = %bb754.i
+ br label %bb760.i
+bb760.i: ; preds = %bb759.i, %bb754.i, %bb710.i
+ br i1 false, label %bb772.i, label %bb766.i
+bb766.i: ; preds = %bb760.i
+ br i1 false, label %bb771.i, label %bb772.i
+bb771.i: ; preds = %bb766.i
+ br label %bb772.i
+bb772.i: ; preds = %bb771.i, %bb766.i, %bb760.i
+ br i1 false, label %bb1937.i, label %bb778.i
+bb778.i: ; preds = %bb772.i
+ br i1 false, label %bb783.i, label %bb1937.i
+bb783.i: ; preds = %bb778.i
+ br label %bb1937.i
+bb784.i: ; preds = %bb662.i
+ switch i32 0, label %bb892.i [
+ i32 1, label %bb868.i
+ i32 3, label %bb868.i
+ i32 4, label %bb882.i
+ i32 6, label %bb792.i
+ i32 7, label %bb786.i
+ ]
+bb786.i: ; preds = %bb784.i
+ br label %bb904.i
+bb792.i: ; preds = %bb784.i
+ switch i32 0, label %bb852.i [
+ i32 31744, label %bb814.i
+ i32 0, label %bb830.i
+ ]
+bb814.i: ; preds = %bb792.i
+ br i1 false, label %bb822.i, label %bb863.i
+bb822.i: ; preds = %bb814.i
+ switch i32 0, label %bb1010.i [
+ i32 1, label %bb986.i
+ i32 3, label %bb986.i
+ i32 4, label %bb1000.i
+ i32 6, label %bb910.i
+ i32 7, label %bb904.i
+ ]
+bb830.i: ; preds = %bb792.i
+ br i1 false, label %bb856.i, label %bb843.preheader.i
+bb843.preheader.i: ; preds = %bb830.i
+ br i1 false, label %bb838.i, label %bb849.i
+bb838.i: ; preds = %bb838.i, %bb843.preheader.i
+ br i1 false, label %bb838.i, label %bb849.i
+bb849.i: ; preds = %bb838.i, %bb843.preheader.i
+ switch i32 0, label %bb1010.i [
+ i32 1, label %bb986.i
+ i32 3, label %bb986.i
+ i32 4, label %bb1000.i
+ i32 6, label %bb910.i
+ i32 7, label %bb904.i
+ ]
+bb852.i: ; preds = %bb792.i
+ br label %bb856.i
+bb856.i: ; preds = %bb852.i, %bb830.i
+ switch i32 0, label %bb1010.i [
+ i32 1, label %bb986.i
+ i32 3, label %bb986.i
+ i32 4, label %bb1000.i
+ i32 6, label %bb910.i
+ i32 7, label %bb904.i
+ ]
+bb863.i: ; preds = %bb814.i
+ switch i32 0, label %bb1010.i [
+ i32 1, label %bb986.i
+ i32 3, label %bb986.i
+ i32 4, label %bb1000.i
+ i32 6, label %bb910.i
+ i32 7, label %bb904.i
+ ]
+bb868.i: ; preds = %bb784.i, %bb784.i
+ switch i32 0, label %bb1010.i [
+ i32 1, label %bb986.i
+ i32 3, label %bb986.i
+ i32 4, label %bb1000.i
+ i32 6, label %bb910.i
+ i32 7, label %bb904.i
+ ]
+bb882.i: ; preds = %bb784.i
+ br label %bb1000.i
+bb892.i: ; preds = %bb784.i
+ br label %bb902.i
+bb902.i: ; preds = %bb892.i, %bb662.i, %bb662.i
+ switch i32 0, label %bb1010.i [
+ i32 1, label %bb986.i
+ i32 3, label %bb986.i
+ i32 4, label %bb1000.i
+ i32 6, label %bb910.i
+ i32 7, label %bb904.i
+ ]
+bb904.i: ; preds = %bb902.i, %bb868.i, %bb863.i, %bb856.i, %bb849.i, %bb822.i, %bb786.i
+ br label %bb1937.i
+bb910.i: ; preds = %bb902.i, %bb868.i, %bb863.i, %bb856.i, %bb849.i, %bb822.i
+ switch i32 0, label %bb970.i [
+ i32 31744, label %bb932.i
+ i32 0, label %bb948.i
+ ]
+bb932.i: ; preds = %bb910.i
+ br i1 false, label %bb940.i, label %bb981.i
+bb940.i: ; preds = %bb932.i
+ br label %bb1937.i
+bb948.i: ; preds = %bb910.i
+ br i1 false, label %bb974.i, label %bb961.preheader.i
+bb961.preheader.i: ; preds = %bb948.i
+ br i1 false, label %bb956.i, label %bb967.i
+bb956.i: ; preds = %bb956.i, %bb961.preheader.i
+ br i1 false, label %bb956.i, label %bb967.i
+bb967.i: ; preds = %bb956.i, %bb961.preheader.i
+ br label %bb1937.i
+bb970.i: ; preds = %bb910.i
+ br label %bb974.i
+bb974.i: ; preds = %bb970.i, %bb948.i
+ br label %bb1937.i
+bb981.i: ; preds = %bb932.i
+ br label %bb1937.i
+bb986.i: ; preds = %bb902.i, %bb902.i, %bb868.i, %bb868.i, %bb863.i, %bb863.i, %bb856.i, %bb856.i, %bb849.i, %bb849.i, %bb822.i, %bb822.i
+ br label %bb1937.i
+bb1000.i: ; preds = %bb902.i, %bb882.i, %bb868.i, %bb863.i, %bb856.i, %bb849.i, %bb822.i
+ br label %bb1937.i
+bb1010.i: ; preds = %bb902.i, %bb868.i, %bb863.i, %bb856.i, %bb849.i, %bb822.i
+ br label %bb1937.i
+bb1020.i: ; preds = %bb662.i
+ switch i32 0, label %bb1388.i [
+ i32 1, label %bb1264.i
+ i32 3, label %bb1264.i
+ i32 4, label %bb1304.i
+ i32 6, label %bb1038.i
+ i32 7, label %bb1022.i
+ i32 8, label %bb1332.i
+ i32 9, label %bb1332.i
+ i32 10, label %bb1360.i
+ i32 11, label %bb1360.i
+ ]
+bb1022.i: ; preds = %bb1020.i
+ br label %bb1937.i
+bb1038.i: ; preds = %bb1020.i
+ switch i32 0, label %bb1098.i [
+ i32 31744, label %bb1060.i
+ i32 0, label %bb1076.i
+ ]
+bb1060.i: ; preds = %bb1038.i
+ br i1 false, label %bb1068.i, label %bb1109.i
+bb1068.i: ; preds = %bb1060.i
+ br label %bb1109.i
+bb1076.i: ; preds = %bb1038.i
+ br i1 false, label %bb1102.i, label %bb1089.preheader.i
+bb1089.preheader.i: ; preds = %bb1076.i
+ br i1 false, label %bb1084.i, label %bb1095.i
+bb1084.i: ; preds = %bb1084.i, %bb1089.preheader.i
+ br i1 false, label %bb1084.i, label %bb1095.i
+bb1095.i: ; preds = %bb1084.i, %bb1089.preheader.i
+ br label %bb1109.i
+bb1098.i: ; preds = %bb1038.i
+ br label %bb1102.i
+bb1102.i: ; preds = %bb1098.i, %bb1076.i
+ br label %bb1109.i
+bb1109.i: ; preds = %bb1102.i, %bb1095.i, %bb1068.i, %bb1060.i
+ switch i32 0, label %bb1173.i [
+ i32 31744, label %bb1135.i
+ i32 0, label %bb1151.i
+ ]
+bb1135.i: ; preds = %bb1109.i
+ br i1 false, label %bb1143.i, label %bb1184.i
+bb1143.i: ; preds = %bb1135.i
+ br label %bb1184.i
+bb1151.i: ; preds = %bb1109.i
+ br i1 false, label %bb1177.i, label %bb1164.preheader.i
+bb1164.preheader.i: ; preds = %bb1151.i
+ br i1 false, label %bb1159.i, label %bb1170.i
+bb1159.i: ; preds = %bb1159.i, %bb1164.preheader.i
+ br i1 false, label %bb1159.i, label %bb1170.i
+bb1170.i: ; preds = %bb1159.i, %bb1164.preheader.i
+ br label %bb1184.i
+bb1173.i: ; preds = %bb1109.i
+ br label %bb1177.i
+bb1177.i: ; preds = %bb1173.i, %bb1151.i
+ br label %bb1184.i
+bb1184.i: ; preds = %bb1177.i, %bb1170.i, %bb1143.i, %bb1135.i
+ switch i32 0, label %bb1248.i [
+ i32 31744, label %bb1210.i
+ i32 0, label %bb1226.i
+ ]
+bb1210.i: ; preds = %bb1184.i
+ br i1 false, label %bb1218.i, label %bb1259.i
+bb1218.i: ; preds = %bb1210.i
+ br label %bb1937.i
+bb1226.i: ; preds = %bb1184.i
+ br i1 false, label %bb1252.i, label %bb1239.preheader.i
+bb1239.preheader.i: ; preds = %bb1226.i
+ br i1 false, label %bb1234.i, label %bb1245.i
+bb1234.i: ; preds = %bb1234.i, %bb1239.preheader.i
+ br i1 false, label %bb1234.i, label %bb1245.i
+bb1245.i: ; preds = %bb1234.i, %bb1239.preheader.i
+ br label %bb1937.i
+bb1248.i: ; preds = %bb1184.i
+ br label %bb1252.i
+bb1252.i: ; preds = %bb1248.i, %bb1226.i
+ br label %bb1937.i
+bb1259.i: ; preds = %bb1210.i
+ br label %bb1937.i
+bb1264.i: ; preds = %bb1020.i, %bb1020.i
+ br label %bb1937.i
+bb1304.i: ; preds = %bb1020.i
+ br label %bb1937.i
+bb1332.i: ; preds = %bb1020.i, %bb1020.i
+ br label %bb1937.i
+bb1360.i: ; preds = %bb1020.i, %bb1020.i
+ br label %bb1937.i
+bb1388.i: ; preds = %bb1020.i
+ br label %bb1937.i
+bb1416.i: ; preds = %bb662.i
+ switch i32 0, label %bb1900.i [
+ i32 1, label %bb1740.i
+ i32 3, label %bb1740.i
+ i32 4, label %bb1793.i
+ i32 6, label %bb1439.i
+ i32 7, label %bb1418.i
+ i32 14, label %bb1830.i
+ i32 15, label %bb1830.i
+ i32 18, label %bb1863.i
+ i32 19, label %bb1863.i
+ ]
+bb1418.i: ; preds = %bb1416.i
+ br label %bb1937.i
+bb1439.i: ; preds = %bb1416.i
+ switch i32 0, label %bb1499.i [
+ i32 31744, label %bb1461.i
+ i32 0, label %bb1477.i
+ ]
+bb1461.i: ; preds = %bb1439.i
+ br i1 false, label %bb1469.i, label %bb1510.i
+bb1469.i: ; preds = %bb1461.i
+ br label %bb1510.i
+bb1477.i: ; preds = %bb1439.i
+ br i1 false, label %bb1503.i, label %bb1490.preheader.i
+bb1490.preheader.i: ; preds = %bb1477.i
+ br i1 false, label %bb1485.i, label %bb1496.i
+bb1485.i: ; preds = %bb1485.i, %bb1490.preheader.i
+ br i1 false, label %bb1485.i, label %bb1496.i
+bb1496.i: ; preds = %bb1485.i, %bb1490.preheader.i
+ br label %bb1510.i
+bb1499.i: ; preds = %bb1439.i
+ br label %bb1503.i
+bb1503.i: ; preds = %bb1499.i, %bb1477.i
+ br label %bb1510.i
+bb1510.i: ; preds = %bb1503.i, %bb1496.i, %bb1469.i, %bb1461.i
+ switch i32 0, label %bb1574.i [
+ i32 31744, label %bb1536.i
+ i32 0, label %bb1552.i
+ ]
+bb1536.i: ; preds = %bb1510.i
+ br i1 false, label %bb1544.i, label %bb1585.i
+bb1544.i: ; preds = %bb1536.i
+ br label %bb1585.i
+bb1552.i: ; preds = %bb1510.i
+ br i1 false, label %bb1578.i, label %bb1565.preheader.i
+bb1565.preheader.i: ; preds = %bb1552.i
+ br i1 false, label %bb1560.i, label %bb1571.i
+bb1560.i: ; preds = %bb1560.i, %bb1565.preheader.i
+ br i1 false, label %bb1560.i, label %bb1571.i
+bb1571.i: ; preds = %bb1560.i, %bb1565.preheader.i
+ br label %bb1585.i
+bb1574.i: ; preds = %bb1510.i
+ br label %bb1578.i
+bb1578.i: ; preds = %bb1574.i, %bb1552.i
+ br label %bb1585.i
+bb1585.i: ; preds = %bb1578.i, %bb1571.i, %bb1544.i, %bb1536.i
+ switch i32 0, label %bb1649.i [
+ i32 31744, label %bb1611.i
+ i32 0, label %bb1627.i
+ ]
+bb1611.i: ; preds = %bb1585.i
+ br i1 false, label %bb1619.i, label %bb1660.i
+bb1619.i: ; preds = %bb1611.i
+ br label %bb1660.i
+bb1627.i: ; preds = %bb1585.i
+ br i1 false, label %bb1653.i, label %bb1640.preheader.i
+bb1640.preheader.i: ; preds = %bb1627.i
+ br i1 false, label %bb1635.i, label %bb1646.i
+bb1635.i: ; preds = %bb1635.i, %bb1640.preheader.i
+ br i1 false, label %bb1635.i, label %bb1646.i
+bb1646.i: ; preds = %bb1635.i, %bb1640.preheader.i
+ br label %bb1660.i
+bb1649.i: ; preds = %bb1585.i
+ br label %bb1653.i
+bb1653.i: ; preds = %bb1649.i, %bb1627.i
+ br label %bb1660.i
+bb1660.i: ; preds = %bb1653.i, %bb1646.i, %bb1619.i, %bb1611.i
+ switch i32 0, label %bb1724.i [
+ i32 31744, label %bb1686.i
+ i32 0, label %bb1702.i
+ ]
+bb1686.i: ; preds = %bb1660.i
+ br i1 false, label %bb1694.i, label %bb1735.i
+bb1694.i: ; preds = %bb1686.i
+ br label %bb1937.i
+bb1702.i: ; preds = %bb1660.i
+ br i1 false, label %bb1728.i, label %bb1715.preheader.i
+bb1715.preheader.i: ; preds = %bb1702.i
+ br i1 false, label %bb1710.i, label %bb1721.i
+bb1710.i: ; preds = %bb1710.i, %bb1715.preheader.i
+ br i1 false, label %bb1710.i, label %bb1721.i
+bb1721.i: ; preds = %bb1710.i, %bb1715.preheader.i
+ br label %bb1937.i
+bb1724.i: ; preds = %bb1660.i
+ br label %bb1728.i
+bb1728.i: ; preds = %bb1724.i, %bb1702.i
+ br label %bb1937.i
+bb1735.i: ; preds = %bb1686.i
+ br label %bb1937.i
+bb1740.i: ; preds = %bb1416.i, %bb1416.i
+ br label %bb1937.i
+bb1793.i: ; preds = %bb1416.i
+ br label %bb1937.i
+bb1830.i: ; preds = %bb1416.i, %bb1416.i
+ br label %bb1937.i
+bb1863.i: ; preds = %bb1416.i, %bb1416.i
+ br label %bb1937.i
+bb1900.i: ; preds = %bb1416.i
+ br label %bb1937.i
+bb1937.i: ; preds = %bb1900.i, %bb1863.i, %bb1830.i, %bb1793.i, %bb1740.i, %bb1735.i, %bb1728.i, %bb1721.i, %bb1694.i, %bb1418.i, %bb1388.i, %bb1360.i, %bb1332.i, %bb1304.i, %bb1264.i, %bb1259.i, %bb1252.i, %bb1245.i, %bb1218.i, %bb1022.i, %bb1010.i, %bb1000.i, %bb986.i, %bb981.i, %bb974.i, %bb967.i, %bb940.i, %bb904.i, %bb783.i, %bb778.i, %bb772.i, %bb662.i
+ switch i32 %sf4083.0.i, label %bb2321.i [
+ i32 0, label %bb2027.i
+ i32 1, label %bb2081.i
+ i32 2, label %bb2161.i
+ i32 3, label %bb2241.i
+ i32 8, label %bb1939.i
+ i32 9, label %bb1939.i
+ i32 10, label %bb1957.i
+ i32 11, label %bb1975.i
+ i32 16, label %bb1939.i
+ ]
+bb1939.i: ; preds = %bb1937.i, %bb1937.i, %bb1937.i
+ switch i32 0, label %bb2321.i [
+ i32 3, label %bb1956.i
+ i32 4, label %bb1956.i
+ i32 11, label %bb1956.i
+ ]
+bb1956.i: ; preds = %bb1939.i, %bb1939.i, %bb1939.i
+ br label %bb2337.i
+bb1957.i: ; preds = %bb1937.i
+ switch i32 0, label %bb1975.i [
+ i32 3, label %bb1974.i
+ i32 4, label %bb1974.i
+ i32 11, label %bb1974.i
+ ]
+bb1974.i: ; preds = %bb1957.i, %bb1957.i, %bb1957.i
+ br label %bb1975.i
+bb1975.i: ; preds = %bb1974.i, %bb1957.i, %bb1937.i
+ switch i32 0, label %bb2001.i [
+ i32 1, label %bb1992.i
+ i32 4, label %bb1992.i
+ i32 8, label %bb1992.i
+ ]
+bb1992.i: ; preds = %bb1975.i, %bb1975.i, %bb1975.i
+ br label %bb2001.i
+bb2001.i: ; preds = %bb1992.i, %bb1975.i
+ switch i32 0, label %bb2321.i [
+ i32 2, label %bb2018.i
+ i32 4, label %bb2018.i
+ i32 8, label %bb2018.i
+ ]
+bb2018.i: ; preds = %bb2001.i, %bb2001.i, %bb2001.i
+ br label %bb2321.i
+bb2027.i: ; preds = %bb1937.i
+ switch i32 0, label %bb2045.i [
+ i32 1, label %bb2044.i
+ i32 4, label %bb2044.i
+ i32 8, label %bb2044.i
+ ]
+bb2044.i: ; preds = %bb2027.i, %bb2027.i, %bb2027.i
+ br label %bb2045.i
+bb2045.i: ; preds = %bb2044.i, %bb2027.i
+ switch i32 0, label %bb2063.i [
+ i32 2, label %bb2062.i
+ i32 4, label %bb2062.i
+ i32 8, label %bb2062.i
+ ]
+bb2062.i: ; preds = %bb2045.i, %bb2045.i, %bb2045.i
+ br label %bb2063.i
+bb2063.i: ; preds = %bb2062.i, %bb2045.i
+ switch i32 0, label %bb2321.i [
+ i32 3, label %bb2080.i
+ i32 4, label %bb2080.i
+ i32 11, label %bb2080.i
+ ]
+bb2080.i: ; preds = %bb2063.i, %bb2063.i, %bb2063.i
+ br label %bb2321.i
+bb2081.i: ; preds = %bb1937.i
+ switch i32 0, label %bb2100.i [
+ i32 1, label %bb2098.i
+ i32 4, label %bb2098.i
+ i32 8, label %bb2098.i
+ ]
+bb2098.i: ; preds = %bb2081.i, %bb2081.i, %bb2081.i
+ br label %bb2100.i
+bb2100.i: ; preds = %bb2098.i, %bb2081.i
+ switch i32 0, label %bb2125.i [
+ i32 4, label %bb2124.i
+ i32 8, label %bb2124.i
+ i32 0, label %bb2124.i
+ i32 11, label %bb2124.i
+ ]
+bb2124.i: ; preds = %bb2100.i, %bb2100.i, %bb2100.i, %bb2100.i
+ br label %bb2125.i
+bb2125.i: ; preds = %bb2124.i, %bb2100.i
+ switch i32 0, label %bb2143.i [
+ i32 2, label %bb2142.i
+ i32 4, label %bb2142.i
+ i32 8, label %bb2142.i
+ ]
+bb2142.i: ; preds = %bb2125.i, %bb2125.i, %bb2125.i
+ br label %bb2143.i
+bb2143.i: ; preds = %bb2142.i, %bb2125.i
+ switch i32 0, label %bb2321.i [
+ i32 3, label %bb2160.i
+ i32 4, label %bb2160.i
+ i32 11, label %bb2160.i
+ ]
+bb2160.i: ; preds = %bb2143.i, %bb2143.i, %bb2143.i
+ br label %bb2321.i
+bb2161.i: ; preds = %bb1937.i
+ switch i32 0, label %bb2180.i [
+ i32 2, label %bb2178.i
+ i32 4, label %bb2178.i
+ i32 8, label %bb2178.i
+ ]
+bb2178.i: ; preds = %bb2161.i, %bb2161.i, %bb2161.i
+ br label %bb2180.i
+bb2180.i: ; preds = %bb2178.i, %bb2161.i
+ switch i32 0, label %bb2205.i [
+ i32 4, label %bb2204.i
+ i32 8, label %bb2204.i
+ i32 0, label %bb2204.i
+ i32 11, label %bb2204.i
+ ]
+bb2204.i: ; preds = %bb2180.i, %bb2180.i, %bb2180.i, %bb2180.i
+ br label %bb2205.i
+bb2205.i: ; preds = %bb2204.i, %bb2180.i
+ switch i32 0, label %bb2223.i [
+ i32 1, label %bb2222.i
+ i32 4, label %bb2222.i
+ i32 8, label %bb2222.i
+ ]
+bb2222.i: ; preds = %bb2205.i, %bb2205.i, %bb2205.i
+ br label %bb2223.i
+bb2223.i: ; preds = %bb2222.i, %bb2205.i
+ switch i32 0, label %bb2321.i [
+ i32 3, label %bb2240.i
+ i32 4, label %bb2240.i
+ i32 11, label %bb2240.i
+ ]
+bb2240.i: ; preds = %bb2223.i, %bb2223.i, %bb2223.i
+ br label %bb2321.i
+bb2241.i: ; preds = %bb1937.i
+ switch i32 0, label %bb2260.i [
+ i32 3, label %bb2258.i
+ i32 4, label %bb2258.i
+ i32 11, label %bb2258.i
+ ]
+bb2258.i: ; preds = %bb2241.i, %bb2241.i, %bb2241.i
+ br label %bb2260.i
+bb2260.i: ; preds = %bb2258.i, %bb2241.i
+ switch i32 0, label %bb2285.i [
+ i32 4, label %bb2284.i
+ i32 11, label %bb2284.i
+ i32 0, label %bb2284.i
+ i32 8, label %bb2284.i
+ ]
+bb2284.i: ; preds = %bb2260.i, %bb2260.i, %bb2260.i, %bb2260.i
+ br label %bb2285.i
+bb2285.i: ; preds = %bb2284.i, %bb2260.i
+ switch i32 0, label %bb2303.i [
+ i32 1, label %bb2302.i
+ i32 4, label %bb2302.i
+ i32 8, label %bb2302.i
+ ]
+bb2302.i: ; preds = %bb2285.i, %bb2285.i, %bb2285.i
+ br label %bb2303.i
+bb2303.i: ; preds = %bb2302.i, %bb2285.i
+ switch i32 0, label %bb2321.i [
+ i32 2, label %bb2320.i
+ i32 4, label %bb2320.i
+ i32 8, label %bb2320.i
+ ]
+bb2320.i: ; preds = %bb2303.i, %bb2303.i, %bb2303.i
+ br label %bb2321.i
+bb2321.i: ; preds = %bb2320.i, %bb2303.i, %bb2240.i, %bb2223.i, %bb2160.i, %bb2143.i, %bb2080.i, %bb2063.i, %bb2018.i, %bb2001.i, %bb1939.i, %bb1937.i
+ br label %bb2337.i
+bb2337.i: ; preds = %bb2321.i, %bb1956.i
+ br label %bb2353.i
+bb2353.i: ; preds = %bb2337.i
+ br label %bb2369.i
+bb2369.i: ; preds = %bb2353.i
+ br label %bb2385.i
+bb2385.i: ; preds = %bb2369.i
+ br i1 false, label %bb2388.i, label %bb2394.i
+bb2388.i: ; preds = %bb2385.i
+ br label %bb2600.i
+bb2394.i: ; preds = %bb2385.i
+ switch i32 0, label %bb2600.i [
+ i32 0, label %bb2504.i
+ i32 1, label %bb2528.i
+ i32 2, label %bb2552.i
+ i32 3, label %bb2576.i
+ i32 4, label %bb2396.i
+ i32 8, label %bb2420.i
+ i32 11, label %bb2480.i
+ ]
+bb2396.i: ; preds = %bb2394.i
+ br i1 false, label %bb2411.i, label %bb2399.i
+bb2399.i: ; preds = %bb2396.i
+ br i1 false, label %bb2420.i, label %bb2405.i
+bb2405.i: ; preds = %bb2399.i
+ br i1 false, label %bb2410.i, label %bb2420.i
+bb2410.i: ; preds = %bb2405.i
+ br i1 false, label %bb2459.i, label %bb2423.i
+bb2411.i: ; preds = %bb2396.i
+ br i1 false, label %bb2420.i, label %bb2414.i
+bb2414.i: ; preds = %bb2411.i
+ br i1 false, label %bb2419.i, label %bb2420.i
+bb2419.i: ; preds = %bb2414.i
+ br label %bb2420.i
+bb2420.i: ; preds = %bb2419.i, %bb2414.i, %bb2411.i, %bb2405.i, %bb2399.i, %bb2394.i
+ br i1 false, label %bb2459.i, label %bb2423.i
+bb2423.i: ; preds = %bb2420.i, %bb2410.i
+ br i1 false, label %bb2435.i, label %bb2429.i
+bb2429.i: ; preds = %bb2423.i
+ br i1 false, label %bb2434.i, label %bb2435.i
+bb2434.i: ; preds = %bb2429.i
+ br label %bb2435.i
+bb2435.i: ; preds = %bb2434.i, %bb2429.i, %bb2423.i
+ br i1 false, label %bb2447.i, label %bb2441.i
+bb2441.i: ; preds = %bb2435.i
+ br i1 false, label %bb2446.i, label %bb2447.i
+bb2446.i: ; preds = %bb2441.i
+ br label %bb2447.i
+bb2447.i: ; preds = %bb2446.i, %bb2441.i, %bb2435.i
+ br i1 false, label %bb2600.i, label %bb2453.i
+bb2453.i: ; preds = %bb2447.i
+ br i1 false, label %bb2458.i, label %bb2600.i
+bb2458.i: ; preds = %bb2453.i
+ br label %bb2793.i
+bb2459.i: ; preds = %bb2420.i, %bb2410.i
+ br i1 false, label %bb2600.i, label %bb2462.i
+bb2462.i: ; preds = %bb2459.i
+ br i1 false, label %bb2479.i, label %bb2600.i
+bb2479.i: ; preds = %bb2462.i
+ br label %bb2600.i
+bb2480.i: ; preds = %bb2394.i
+ br i1 false, label %bb2495.i, label %bb2483.i
+bb2483.i: ; preds = %bb2480.i
+ br i1 false, label %bb2504.i, label %bb2489.i
+bb2489.i: ; preds = %bb2483.i
+ br i1 false, label %bb2494.i, label %bb2504.i
+bb2494.i: ; preds = %bb2489.i
+ br i1 false, label %bb2519.i, label %bb2507.i
+bb2495.i: ; preds = %bb2480.i
+ br i1 false, label %bb2504.i, label %bb2498.i
+bb2498.i: ; preds = %bb2495.i
+ br i1 false, label %bb2503.i, label %bb2504.i
+bb2503.i: ; preds = %bb2498.i
+ br label %bb2504.i
+bb2504.i: ; preds = %bb2503.i, %bb2498.i, %bb2495.i, %bb2489.i, %bb2483.i, %bb2394.i
+ br i1 false, label %bb2519.i, label %bb2507.i
+bb2507.i: ; preds = %bb2504.i, %bb2494.i
+ br i1 false, label %bb2600.i, label %bb2513.i
+bb2513.i: ; preds = %bb2507.i
+ br i1 false, label %bb2518.i, label %bb2600.i
+bb2518.i: ; preds = %bb2513.i
+ br label %bb2600.i
+bb2519.i: ; preds = %bb2504.i, %bb2494.i
+ br i1 false, label %bb2600.i, label %bb2522.i
+bb2522.i: ; preds = %bb2519.i
+ br i1 false, label %bb2527.i, label %bb2600.i
+bb2527.i: ; preds = %bb2522.i
+ br label %bb2600.i
+bb2528.i: ; preds = %bb2394.i
+ br i1 false, label %bb2543.i, label %bb2531.i
+bb2531.i: ; preds = %bb2528.i
+ br i1 false, label %bb2600.i, label %bb2537.i
+bb2537.i: ; preds = %bb2531.i
+ br i1 false, label %bb2542.i, label %bb2600.i
+bb2542.i: ; preds = %bb2537.i
+ br label %bb2600.i
+bb2543.i: ; preds = %bb2528.i
+ br i1 false, label %bb2600.i, label %bb2546.i
+bb2546.i: ; preds = %bb2543.i
+ br i1 false, label %bb2551.i, label %bb2600.i
+bb2551.i: ; preds = %bb2546.i
+ br label %bb2600.i
+bb2552.i: ; preds = %bb2394.i
+ br i1 false, label %bb2567.i, label %bb2555.i
+bb2555.i: ; preds = %bb2552.i
+ br i1 false, label %bb2600.i, label %bb2561.i
+bb2561.i: ; preds = %bb2555.i
+ br i1 false, label %bb2566.i, label %bb2600.i
+bb2566.i: ; preds = %bb2561.i
+ br label %bb2600.i
+bb2567.i: ; preds = %bb2552.i
+ br i1 false, label %bb2600.i, label %bb2570.i
+bb2570.i: ; preds = %bb2567.i
+ br i1 false, label %bb2575.i, label %bb2600.i
+bb2575.i: ; preds = %bb2570.i
+ br label %bb2600.i
+bb2576.i: ; preds = %bb2394.i
+ br i1 false, label %bb2591.i, label %bb2579.i
+bb2579.i: ; preds = %bb2576.i
+ br i1 false, label %bb2600.i, label %bb2585.i
+bb2585.i: ; preds = %bb2579.i
+ br i1 false, label %bb2590.i, label %bb2600.i
+bb2590.i: ; preds = %bb2585.i
+ br label %bb2600.i
+bb2591.i: ; preds = %bb2576.i
+ br i1 false, label %bb2600.i, label %bb2594.i
+bb2594.i: ; preds = %bb2591.i
+ br i1 false, label %bb2599.i, label %bb2600.i
+bb2599.i: ; preds = %bb2594.i
+ br label %bb2600.i
+bb2600.i: ; preds = %bb2599.i, %bb2594.i, %bb2591.i, %bb2590.i, %bb2585.i, %bb2579.i, %bb2575.i, %bb2570.i, %bb2567.i, %bb2566.i, %bb2561.i, %bb2555.i, %bb2551.i, %bb2546.i, %bb2543.i, %bb2542.i, %bb2537.i, %bb2531.i, %bb2527.i, %bb2522.i, %bb2519.i, %bb2518.i, %bb2513.i, %bb2507.i, %bb2479.i, %bb2462.i, %bb2459.i, %bb2453.i, %bb2447.i, %bb2394.i, %bb2388.i
+ br label %bb2793.i
+bb2793.i: ; preds = %bb2600.i, %bb2458.i, %bb656.i, %bb650.i, %bb559.i
+ switch i32 0, label %bb2883.i [
+ i32 3, label %bb2874.i
+ i32 4, label %bb2795.i
+ i32 8, label %bb2810.i
+ i32 10, label %bb2834.i
+ i32 11, label %bb2819.i
+ i32 16, label %bb2810.i
+ ]
+bb2795.i: ; preds = %bb2793.i, %bb661.i
+ br label %bb2810.i
+bb2810.i: ; preds = %bb2795.i, %bb2793.i, %bb2793.i, %bb661.i, %bb661.i
+ br label %bb2883.i
+bb2819.i: ; preds = %bb2793.i, %bb661.i
+ br label %bb2834.i
+bb2834.i: ; preds = %bb2819.i, %bb2793.i, %bb661.i
+ switch i32 0, label %bb2860.i [
+ i32 4, label %bb2846.i
+ i32 8, label %bb2846.i
+ ]
+bb2846.i: ; preds = %bb2834.i, %bb2834.i
+ br i1 false, label %bb2859.i, label %bb2860.i
+bb2859.i: ; preds = %bb2846.i
+ br label %bb2860.i
+bb2860.i: ; preds = %bb2859.i, %bb2846.i, %bb2834.i
+ switch i32 %df4081.0.i, label %bb2867.bb2883_crit_edge.i [
+ i32 1, label %bb2883.i
+ i32 2, label %bb2872.i
+ ]
+bb2867.bb2883_crit_edge.i: ; preds = %bb2860.i
+ br label %bb2883.i
+bb2872.i: ; preds = %bb2860.i
+ switch i32 0, label %UnifiedReturnBlock.i235 [
+ i32 3, label %bb3253.i
+ i32 4, label %bb4173.i
+ i32 8, label %bb3485.i
+ i32 10, label %bb3253.i
+ i32 11, label %bb3021.i
+ i32 16, label %bb2885.i
+ ]
+bb2874.i: ; preds = %bb2793.i, %bb661.i
+ br label %bb2883.i
+bb2883.i: ; preds = %bb2874.i, %bb2867.bb2883_crit_edge.i, %bb2860.i, %bb2810.i, %bb2793.i, %bb661.i
+ %f_alpha.1.i = phi i32 [ 0, %bb2867.bb2883_crit_edge.i ], [ 0, %bb2874.i ], [ 1065353216, %bb661.i ], [ 0, %bb2793.i ], [ 0, %bb2810.i ], [ 0, %bb2860.i ] ; <i32> [#uses=1]
+ switch i32 0, label %UnifiedReturnBlock.i235 [
+ i32 3, label %bb3253.i
+ i32 4, label %bb4173.i
+ i32 8, label %bb3485.i
+ i32 10, label %bb3253.i
+ i32 11, label %bb3021.i
+ i32 16, label %bb2885.i
+ ]
+bb2885.i: ; preds = %bb2883.i, %bb2872.i
+ br i1 false, label %bb3011.i, label %bb2890.i
+bb2890.i: ; preds = %bb2885.i
+ br i1 false, label %bb2960.i, label %bb2954.i
+bb2954.i: ; preds = %bb2890.i
+ br i1 false, label %bb2959.i, label %bb2960.i
+bb2959.i: ; preds = %bb2954.i
+ br label %bb2960.i
+bb2960.i: ; preds = %bb2959.i, %bb2954.i, %bb2890.i
+ br i1 false, label %bb2972.i, label %bb2966.i
+bb2966.i: ; preds = %bb2960.i
+ br i1 false, label %bb2971.i, label %bb2972.i
+bb2971.i: ; preds = %bb2966.i
+ br label %bb2972.i
+bb2972.i: ; preds = %bb2971.i, %bb2966.i, %bb2960.i
+ br label %glgScalarFloatConversion.exit
+bb3011.i: ; preds = %bb2885.i
+ br label %glgScalarFloatConversion.exit
+bb3021.i: ; preds = %bb2883.i, %bb2872.i
+ switch i32 %dt4080.0.i, label %bb3192.i [
+ i32 7, label %bb3026.i
+ i32 6, label %bb3037.i
+ i32 1, label %bb3125.i
+ i32 3, label %bb3125.i
+ i32 5, label %bb3144.i
+ ]
+bb3026.i: ; preds = %bb3021.i
+ br label %bb3258.i
+bb3037.i: ; preds = %bb3021.i
+ br i1 false, label %bb3052.i, label %bb3074.i
+bb3052.i: ; preds = %bb3037.i
+ br i1 false, label %bb3105.i, label %bb3069.i
+bb3069.i: ; preds = %bb3052.i
+ switch i32 %dt4080.0.i, label %bb3424.i [
+ i32 7, label %bb3258.i
+ i32 6, label %bb3269.i
+ i32 1, label %bb3357.i
+ i32 3, label %bb3357.i
+ i32 5, label %bb3376.i
+ ]
+bb3074.i: ; preds = %bb3037.i
+ br i1 false, label %bb3079.i, label %bb3092.i
+bb3079.i: ; preds = %bb3074.i
+ switch i32 %dt4080.0.i, label %bb3424.i [
+ i32 7, label %bb3258.i
+ i32 6, label %bb3269.i
+ i32 1, label %bb3357.i
+ i32 3, label %bb3357.i
+ i32 5, label %bb3376.i
+ ]
+bb3092.i: ; preds = %bb3074.i
+ switch i32 %dt4080.0.i, label %bb3424.i [
+ i32 7, label %bb3258.i
+ i32 6, label %bb3269.i
+ i32 1, label %bb3357.i
+ i32 3, label %bb3357.i
+ i32 5, label %bb3376.i
+ ]
+bb3105.i: ; preds = %bb3052.i
+ switch i32 %dt4080.0.i, label %bb3424.i [
+ i32 7, label %bb3258.i
+ i32 6, label %bb3269.i
+ i32 1, label %bb3357.i
+ i32 3, label %bb3357.i
+ i32 5, label %bb3376.i
+ ]
+bb3125.i: ; preds = %bb3021.i, %bb3021.i
+ switch i32 %dt4080.0.i, label %bb3424.i [
+ i32 7, label %bb3258.i
+ i32 6, label %bb3269.i
+ i32 1, label %bb3357.i
+ i32 3, label %bb3357.i
+ i32 5, label %bb3376.i
+ ]
+bb3144.i: ; preds = %bb3021.i
+ br label %bb3376.i
+bb3192.i: ; preds = %bb3021.i
+ br i1 false, label %bb3197.i, label %bb3243.i
+bb3197.i: ; preds = %bb3192.i
+ br label %bb3424.i
+bb3243.i: ; preds = %bb3192.i
+ br label %bb3253.i
+bb3253.i: ; preds = %bb3243.i, %bb2883.i, %bb2883.i, %bb2872.i, %bb2872.i
+ switch i32 %dt4080.0.i, label %bb3424.i [
+ i32 7, label %bb3258.i
+ i32 6, label %bb3269.i
+ i32 1, label %bb3357.i
+ i32 3, label %bb3357.i
+ i32 5, label %bb3376.i
+ ]
+bb3258.i: ; preds = %bb3253.i, %bb3125.i, %bb3105.i, %bb3092.i, %bb3079.i, %bb3069.i, %bb3026.i
+ br label %glgScalarFloatConversion.exit
+bb3269.i: ; preds = %bb3253.i, %bb3125.i, %bb3105.i, %bb3092.i, %bb3079.i, %bb3069.i
+ br i1 false, label %bb3284.i, label %bb3306.i
+bb3284.i: ; preds = %bb3269.i
+ br i1 false, label %bb3337.i, label %bb3301.i
+bb3301.i: ; preds = %bb3284.i
+ br label %glgScalarFloatConversion.exit
+bb3306.i: ; preds = %bb3269.i
+ br i1 false, label %bb3311.i, label %bb3324.i
+bb3311.i: ; preds = %bb3306.i
+ br label %glgScalarFloatConversion.exit
+bb3324.i: ; preds = %bb3306.i
+ br label %glgScalarFloatConversion.exit
+bb3337.i: ; preds = %bb3284.i
+ br label %glgScalarFloatConversion.exit
+bb3357.i: ; preds = %bb3253.i, %bb3253.i, %bb3125.i, %bb3125.i, %bb3105.i, %bb3105.i, %bb3092.i, %bb3092.i, %bb3079.i, %bb3079.i, %bb3069.i, %bb3069.i
+ br label %glgScalarFloatConversion.exit
+bb3376.i: ; preds = %bb3253.i, %bb3144.i, %bb3125.i, %bb3105.i, %bb3092.i, %bb3079.i, %bb3069.i
+ br label %glgScalarFloatConversion.exit
+bb3424.i: ; preds = %bb3253.i, %bb3197.i, %bb3125.i, %bb3105.i, %bb3092.i, %bb3079.i, %bb3069.i
+ br i1 false, label %bb3429.i, label %bb3475.i
+bb3429.i: ; preds = %bb3424.i
+ br label %glgScalarFloatConversion.exit
+bb3475.i: ; preds = %bb3424.i
+ br label %glgScalarFloatConversion.exit
+bb3485.i: ; preds = %bb2883.i, %bb2872.i
+ switch i32 %dt4080.0.i, label %bb4077.i [
+ i32 7, label %bb3490.i
+ i32 6, label %bb3511.i
+ i32 1, label %bb3749.i
+ i32 3, label %bb3749.i
+ i32 5, label %bb3794.i
+ i32 4, label %bb3941.i
+ ]
+bb3490.i: ; preds = %bb3485.i
+ br label %glgScalarFloatConversion.exit
+bb3511.i: ; preds = %bb3485.i
+ br i1 false, label %bb3526.i, label %bb3548.i
+bb3526.i: ; preds = %bb3511.i
+ br i1 false, label %bb3579.i, label %bb3543.i
+bb3543.i: ; preds = %bb3526.i
+ br label %bb3579.i
+bb3548.i: ; preds = %bb3511.i
+ br i1 false, label %bb3553.i, label %bb3566.i
+bb3553.i: ; preds = %bb3548.i
+ br label %bb3579.i
+bb3566.i: ; preds = %bb3548.i
+ br label %bb3579.i
+bb3579.i: ; preds = %bb3566.i, %bb3553.i, %bb3543.i, %bb3526.i
+ br i1 false, label %bb3601.i, label %bb3623.i
+bb3601.i: ; preds = %bb3579.i
+ br i1 false, label %bb3654.i, label %bb3618.i
+bb3618.i: ; preds = %bb3601.i
+ br label %bb3654.i
+bb3623.i: ; preds = %bb3579.i
+ br i1 false, label %bb3628.i, label %bb3641.i
+bb3628.i: ; preds = %bb3623.i
+ br label %bb3654.i
+bb3641.i: ; preds = %bb3623.i
+ br label %bb3654.i
+bb3654.i: ; preds = %bb3641.i, %bb3628.i, %bb3618.i, %bb3601.i
+ br i1 false, label %bb3676.i, label %bb3698.i
+bb3676.i: ; preds = %bb3654.i
+ br i1 false, label %bb3729.i, label %bb3693.i
+bb3693.i: ; preds = %bb3676.i
+ br label %glgScalarFloatConversion.exit
+bb3698.i: ; preds = %bb3654.i
+ br i1 false, label %bb3703.i, label %bb3716.i
+bb3703.i: ; preds = %bb3698.i
+ br label %glgScalarFloatConversion.exit
+bb3716.i: ; preds = %bb3698.i
+ br label %glgScalarFloatConversion.exit
+bb3729.i: ; preds = %bb3676.i
+ br label %glgScalarFloatConversion.exit
+bb3749.i: ; preds = %bb3485.i, %bb3485.i
+ br label %glgScalarFloatConversion.exit
+bb3794.i: ; preds = %bb3485.i
+ br label %glgScalarFloatConversion.exit
+bb3941.i: ; preds = %bb3485.i
+ br label %glgScalarFloatConversion.exit
+bb4077.i: ; preds = %bb3485.i
+ br i1 false, label %bb4083.i, label %bb4111.i
+bb4083.i: ; preds = %bb4077.i
+ br label %glgScalarFloatConversion.exit
+bb4111.i: ; preds = %bb4077.i
+ br i1 false, label %bb4117.i, label %bb4145.i
+bb4117.i: ; preds = %bb4111.i
+ br label %glgScalarFloatConversion.exit
+bb4145.i: ; preds = %bb4111.i
+ br label %glgScalarFloatConversion.exit
+bb4173.i: ; preds = %bb2883.i, %bb2872.i
+ %f_red.0.reg2mem.4.i = phi i32 [ 0, %bb2872.i ], [ 0, %bb2883.i ] ; <i32> [#uses=2]
+ %f_green.0.reg2mem.2.i = phi i32 [ 0, %bb2872.i ], [ 0, %bb2883.i ] ; <i32> [#uses=1]
+ %f_blue.0.reg2mem.2.i = phi i32 [ 0, %bb2872.i ], [ 0, %bb2883.i ] ; <i32> [#uses=1]
+ %f_alpha.1.reg2mem.1.i = phi i32 [ 0, %bb2872.i ], [ %f_alpha.1.i, %bb2883.i ] ; <i32> [#uses=1]
+ switch i32 %dt4080.0.i, label %bb4950.i [
+ i32 7, label %bb4178.i
+ i32 6, label %bb4204.i
+ i32 1, label %bb4517.i202
+ i32 3, label %bb4517.i202
+ i32 5, label %bb4575.i
+ i32 4, label %bb4769.i
+ ]
+bb4178.i: ; preds = %bb4173.i
+ br label %glgScalarFloatConversion.exit
+bb4204.i: ; preds = %bb4173.i
+ %tmp4210.i = and i32 0, 32768 ; <i32> [#uses=4]
+ %tmp4212.i = and i32 %f_red.0.reg2mem.4.i, 2139095040 ; <i32> [#uses=1]
+ %tmp4214.i = and i32 %f_red.0.reg2mem.4.i, 8388607 ; <i32> [#uses=1]
+ br i1 false, label %bb4219.i, label %bb4241.i
+bb4219.i: ; preds = %bb4204.i
+ br i1 false, label %bb4272.i, label %bb4236.i
+bb4236.i: ; preds = %bb4219.i
+ br label %bb4272.i
+bb4241.i: ; preds = %bb4204.i
+ br i1 false, label %bb4246.i, label %bb4259.i
+bb4246.i: ; preds = %bb4241.i
+ %tmp4253.i = lshr i32 %tmp4214.i, 0 ; <i32> [#uses=1]
+ %tmp4253.masked.i = and i32 %tmp4253.i, 65535 ; <i32> [#uses=1]
+ br label %bb4272.i
+bb4259.i: ; preds = %bb4241.i
+ %tmp4261.i187 = add i32 %tmp4212.i, 134217728 ; <i32> [#uses=1]
+ %tmp4262.i188 = lshr i32 %tmp4261.i187, 13 ; <i32> [#uses=1]
+ %tmp4262.masked.i = and i32 %tmp4262.i188, 64512 ; <i32> [#uses=1]
+ %tmp42665693.masked.i = or i32 %tmp4262.masked.i, %tmp4210.i ; <i32> [#uses=1]
+ br label %bb4272.i
+bb4272.i: ; preds = %bb4259.i, %bb4246.i, %bb4236.i, %bb4219.i
+ %tmp42665693.masked.pn.i = phi i32 [ %tmp42665693.masked.i, %bb4259.i ], [ %tmp4253.masked.i, %bb4246.i ], [ %tmp4210.i, %bb4236.i ], [ %tmp4210.i, %bb4219.i ] ; <i32> [#uses=1]
+ %tmp4268.pn.i = phi i32 [ 0, %bb4259.i ], [ %tmp4210.i, %bb4246.i ], [ 31744, %bb4236.i ], [ 32767, %bb4219.i ] ; <i32> [#uses=1]
+ %tmp100.0.i = or i32 %tmp4268.pn.i, %tmp42665693.masked.pn.i ; <i32> [#uses=0]
+ %tmp4289.i = and i32 %f_green.0.reg2mem.2.i, 8388607 ; <i32> [#uses=1]
+ br i1 false, label %bb4294.i, label %bb4316.i
+bb4294.i: ; preds = %bb4272.i
+ br i1 false, label %bb4347.i, label %bb4311.i
+bb4311.i: ; preds = %bb4294.i
+ br label %bb4347.i
+bb4316.i: ; preds = %bb4272.i
+ br i1 false, label %bb4321.i, label %bb4334.i
+bb4321.i: ; preds = %bb4316.i
+ br label %bb4347.i
+bb4334.i: ; preds = %bb4316.i
+ %tmp4343.i = lshr i32 %tmp4289.i, 13 ; <i32> [#uses=0]
+ br label %bb4347.i
+bb4347.i: ; preds = %bb4334.i, %bb4321.i, %bb4311.i, %bb4294.i
+ %tmp4364.i190 = and i32 %f_blue.0.reg2mem.2.i, 8388607 ; <i32> [#uses=1]
+ br i1 false, label %bb4369.i192, label %bb4391.i
+bb4369.i192: ; preds = %bb4347.i
+ br i1 false, label %bb4422.i, label %bb4386.i
+bb4386.i: ; preds = %bb4369.i192
+ br label %bb4422.i
+bb4391.i: ; preds = %bb4347.i
+ br i1 false, label %bb4396.i, label %bb4409.i
+bb4396.i: ; preds = %bb4391.i
+ br label %bb4422.i
+bb4409.i: ; preds = %bb4391.i
+ %tmp4418.i = lshr i32 %tmp4364.i190, 13 ; <i32> [#uses=0]
+ br label %bb4422.i
+bb4422.i: ; preds = %bb4409.i, %bb4396.i, %bb4386.i, %bb4369.i192
+ %tmp4439.i194 = and i32 %f_alpha.1.reg2mem.1.i, 8388607 ; <i32> [#uses=1]
+ br i1 false, label %bb4444.i, label %bb4466.i
+bb4444.i: ; preds = %bb4422.i
+ br i1 false, label %bb4497.i, label %bb4461.i
+bb4461.i: ; preds = %bb4444.i
+ br label %glgScalarFloatConversion.exit
+bb4466.i: ; preds = %bb4422.i
+ br i1 false, label %bb4471.i, label %bb4484.i
+bb4471.i: ; preds = %bb4466.i
+ br label %glgScalarFloatConversion.exit
+bb4484.i: ; preds = %bb4466.i
+ %tmp4493.i = lshr i32 %tmp4439.i194, 13 ; <i32> [#uses=0]
+ br label %glgScalarFloatConversion.exit
+bb4497.i: ; preds = %bb4444.i
+ br label %glgScalarFloatConversion.exit
+bb4517.i202: ; preds = %bb4173.i, %bb4173.i
+ br label %glgScalarFloatConversion.exit
+bb4575.i: ; preds = %bb4173.i
+ br label %glgScalarFloatConversion.exit
+bb4769.i: ; preds = %bb4173.i
+ br label %glgScalarFloatConversion.exit
+bb4950.i: ; preds = %bb4173.i
+ br i1 false, label %bb4956.i, label %bb4993.i
+bb4956.i: ; preds = %bb4950.i
+ br label %glgScalarFloatConversion.exit
+bb4993.i: ; preds = %bb4950.i
+ br i1 false, label %bb4999.i, label %bb5036.i
+bb4999.i: ; preds = %bb4993.i
+ br label %glgScalarFloatConversion.exit
+bb5036.i: ; preds = %bb4993.i
+ br label %glgScalarFloatConversion.exit
+UnifiedReturnBlock.i235: ; preds = %bb2883.i, %bb2872.i
+ br label %glgScalarFloatConversion.exit
+glgScalarFloatConversion.exit: ; preds = %UnifiedReturnBlock.i235, %bb5036.i, %bb4999.i, %bb4956.i, %bb4769.i, %bb4575.i, %bb4517.i202, %bb4497.i, %bb4484.i, %bb4471.i, %bb4461.i, %bb4178.i, %bb4145.i, %bb4117.i, %bb4083.i, %bb3941.i, %bb3794.i, %bb3749.i, %bb3729.i, %bb3716.i, %bb3703.i, %bb3693.i, %bb3490.i, %bb3475.i, %bb3429.i, %bb3376.i, %bb3357.i, %bb3337.i, %bb3324.i, %bb3311.i, %bb3301.i, %bb3258.i, %bb3011.i, %bb2972.i
+ br label %bb18851.i
+bb16697.i: ; preds = %loadColor_BGRA_UI8888R.exit
+ br i1 false, label %bb17749.i, label %bb16700.i
+bb16700.i: ; preds = %bb16697.i
+ switch i32 0, label %bb16829.i [
+ i32 4, label %bb16705.i
+ i32 8, label %bb16743.i
+ i32 11, label %bb16795.i
+ ]
+bb16705.i: ; preds = %bb16700.i
+ switch i32 %df4081.0.i, label %bb17183.i [
+ i32 1, label %bb16710.i
+ i32 2, label %bb16721.i
+ i32 3, label %bb16732.i
+ ]
+bb16710.i: ; preds = %bb16705.i
+ br label %bb17195.i
+bb16721.i: ; preds = %bb16705.i
+ br label %bb17195.i
+bb16732.i: ; preds = %bb16705.i
+ br label %bb17195.i
+bb16743.i: ; preds = %bb16700.i
+ switch i32 0, label %bb16759.i [
+ i32 4, label %bb16755.i
+ i32 11, label %bb16755.i
+ ]
+bb16755.i: ; preds = %bb16743.i, %bb16743.i
+ br label %bb17195.i
+bb16759.i: ; preds = %bb16743.i
+ switch i32 %df4081.0.i, label %bb17183.i [
+ i32 1, label %bb16764.i
+ i32 2, label %bb16775.i
+ i32 3, label %bb16786.i
+ ]
+bb16764.i: ; preds = %bb16759.i
+ br label %bb17195.i
+bb16775.i: ; preds = %bb16759.i
+ br label %bb17195.i
+bb16786.i: ; preds = %bb16759.i
+ br label %bb17195.i
+bb16795.i: ; preds = %bb16700.i
+ switch i32 0, label %bb17183.i [
+ i32 4, label %bb16807.i
+ i32 8, label %bb16807.i
+ i32 3, label %bb16823.i
+ ]
+bb16807.i: ; preds = %bb16795.i, %bb16795.i
+ br label %bb17195.i
+bb16823.i: ; preds = %bb16795.i
+ br label %bb17195.i
+bb16829.i: ; preds = %bb16700.i
+ switch i32 %sf4083.0.i, label %bb17183.i [
+ i32 10, label %bb16834.i
+ i32 0, label %bb16892.i
+ i32 1, label %bb16953.i
+ i32 2, label %bb17037.i
+ i32 3, label %bb17121.i
+ ]
+bb16834.i: ; preds = %bb16829.i
+ switch i32 0, label %bb16878.i [
+ i32 4, label %bb16839.i
+ i32 8, label %bb16858.i
+ i32 11, label %bb16874.i
+ ]
+bb16839.i: ; preds = %bb16834.i
+ br label %bb17195.i
+bb16858.i: ; preds = %bb16834.i
+ br label %bb17195.i
+bb16874.i: ; preds = %bb16834.i
+ br label %bb17195.i
+bb16878.i: ; preds = %bb16834.i
+ br i1 false, label %bb16883.i, label %bb17183.i
+bb16883.i: ; preds = %bb16878.i
+ br label %bb17195.i
+bb16892.i: ; preds = %bb16829.i
+ switch i32 0, label %bb16930.i [
+ i32 4, label %bb16897.i
+ i32 8, label %bb16913.i
+ i32 11, label %bb16926.i
+ ]
+bb16897.i: ; preds = %bb16892.i
+ br label %bb17195.i
+bb16913.i: ; preds = %bb16892.i
+ br label %bb17195.i
+bb16926.i: ; preds = %bb16892.i
+ br label %bb17195.i
+bb16930.i: ; preds = %bb16892.i
+ br i1 false, label %bb16936.i, label %bb16939.i
+bb16936.i: ; preds = %bb16930.i
+ br label %bb17195.i
+bb16939.i: ; preds = %bb16930.i
+ br i1 false, label %bb16944.i, label %bb17183.i
+bb16944.i: ; preds = %bb16939.i
+ br label %bb17195.i
+bb16953.i: ; preds = %bb16829.i
+ switch i32 0, label %bb17003.i [
+ i32 4, label %bb16958.i
+ i32 8, label %bb16979.i
+ i32 11, label %bb16997.i
+ ]
+bb16958.i: ; preds = %bb16953.i
+ br label %bb17195.i
+bb16979.i: ; preds = %bb16953.i
+ br label %bb17195.i
+bb16997.i: ; preds = %bb16953.i
+ br label %bb17195.i
+bb17003.i: ; preds = %bb16953.i
+ switch i32 %df4081.0.i, label %bb17183.i [
+ i32 0, label %bb17020.i
+ i32 2, label %bb17020.i
+ i32 10, label %bb17020.i
+ i32 3, label %bb17028.i
+ ]
+bb17020.i: ; preds = %bb17003.i, %bb17003.i, %bb17003.i
+ br label %bb17195.i
+bb17028.i: ; preds = %bb17003.i
+ br label %bb17195.i
+bb17037.i: ; preds = %bb16829.i
+ switch i32 0, label %bb17087.i [
+ i32 4, label %bb17042.i
+ i32 8, label %bb17063.i
+ i32 11, label %bb17081.i
+ ]
+bb17042.i: ; preds = %bb17037.i
+ br label %bb17195.i
+bb17063.i: ; preds = %bb17037.i
+ br label %bb17195.i
+bb17081.i: ; preds = %bb17037.i
+ br label %bb17195.i
+bb17087.i: ; preds = %bb17037.i
+ switch i32 %df4081.0.i, label %bb17183.i [
+ i32 0, label %bb17104.i
+ i32 1, label %bb17104.i
+ i32 10, label %bb17104.i
+ i32 3, label %bb17112.i
+ ]
+bb17104.i: ; preds = %bb17087.i, %bb17087.i, %bb17087.i
+ br label %bb17195.i
+bb17112.i: ; preds = %bb17087.i
+ br label %bb17195.i
+bb17121.i: ; preds = %bb16829.i
+ switch i32 0, label %bb17183.i [
+ i32 4, label %bb17126.i
+ i32 8, label %bb17149.i
+ i32 11, label %bb17167.i
+ i32 10, label %bb17180.i
+ ]
+bb17126.i: ; preds = %bb17121.i
+ br label %bb17195.i
+bb17149.i: ; preds = %bb17121.i
+ br label %bb17195.i
+bb17167.i: ; preds = %bb17121.i
+ br label %bb17195.i
+bb17180.i: ; preds = %bb17121.i
+ br label %bb17183.i
+bb17183.i: ; preds = %bb17180.i, %bb17121.i, %bb17087.i, %bb17003.i, %bb16939.i, %bb16878.i, %bb16829.i, %bb16795.i, %bb16759.i, %bb16705.i
+ br label %bb17195.i
+bb17195.i: ; preds = %bb17183.i, %bb17167.i, %bb17149.i, %bb17126.i, %bb17112.i, %bb17104.i, %bb17081.i, %bb17063.i, %bb17042.i, %bb17028.i, %bb17020.i, %bb16997.i, %bb16979.i, %bb16958.i, %bb16944.i, %bb16936.i, %bb16926.i, %bb16913.i, %bb16897.i, %bb16883.i, %bb16874.i, %bb16858.i, %bb16839.i, %bb16823.i, %bb16807.i, %bb16786.i, %bb16775.i, %bb16764.i, %bb16755.i, %bb16732.i, %bb16721.i, %bb16710.i
+ br i1 false, label %bb18845.i, label %bb17225.i
+bb17225.i: ; preds = %bb17195.i
+ switch i32 %dt4080.0.i, label %bb17677.i [
+ i32 4, label %bb17227.i
+ i32 8, label %bb17259.i
+ i32 9, label %bb17309.i
+ i32 10, label %bb17359.i
+ i32 11, label %bb17359.i
+ i32 14, label %bb17409.i
+ i32 15, label %bb17474.i
+ i32 18, label %bb17539.i
+ i32 19, label %bb17604.i
+ i32 0, label %bb17680.i
+ i32 1, label %bb17672.i
+ i32 2, label %bb17673.i
+ i32 3, label %bb17674.i
+ i32 5, label %bb17675.i
+ i32 12, label %bb17676.i
+ i32 13, label %bb17676.i
+ i32 16, label %bb17680.i
+ i32 17, label %bb17680.i
+ ]
+bb17227.i: ; preds = %bb17225.i
+ br i1 false, label %bb18845.i, label %bb17230.i
+bb17230.i: ; preds = %bb17227.i
+ br label %bb18851.i
+bb17259.i: ; preds = %bb17225.i
+ br i1 false, label %bb17284.i, label %bb17262.i
+bb17262.i: ; preds = %bb17259.i
+ br label %bb17284.i
+bb17284.i: ; preds = %bb17262.i, %bb17259.i
+ br label %bb18851.i
+bb17309.i: ; preds = %bb17225.i
+ br i1 false, label %bb17334.i, label %bb17312.i
+bb17312.i: ; preds = %bb17309.i
+ br label %bb17334.i
+bb17334.i: ; preds = %bb17312.i, %bb17309.i
+ br label %bb18851.i
+bb17359.i: ; preds = %bb17225.i, %bb17225.i
+ br i1 false, label %bb17384.i, label %bb17362.i
+bb17362.i: ; preds = %bb17359.i
+ br label %bb17384.i
+bb17384.i: ; preds = %bb17362.i, %bb17359.i
+ br label %bb18851.i
+bb17409.i: ; preds = %bb17225.i
+ br i1 false, label %bb17441.i, label %bb17412.i
+bb17412.i: ; preds = %bb17409.i
+ br label %bb17441.i
+bb17441.i: ; preds = %bb17412.i, %bb17409.i
+ br label %bb18851.i
+bb17474.i: ; preds = %bb17225.i
+ br i1 false, label %bb17506.i, label %bb17477.i
+bb17477.i: ; preds = %bb17474.i
+ br label %bb17506.i
+bb17506.i: ; preds = %bb17477.i, %bb17474.i
+ br label %bb18851.i
+bb17539.i: ; preds = %bb17225.i
+ br i1 false, label %bb17571.i, label %bb17542.i
+bb17542.i: ; preds = %bb17539.i
+ br label %bb17571.i
+bb17571.i: ; preds = %bb17542.i, %bb17539.i
+ br label %bb18851.i
+bb17604.i: ; preds = %bb17225.i
+ br i1 false, label %bb17636.i, label %bb17607.i
+bb17607.i: ; preds = %bb17604.i
+ br label %bb17636.i
+bb17636.i: ; preds = %bb17607.i, %bb17604.i
+ br label %bb18851.i
+bb17672.i: ; preds = %bb17225.i
+ br i1 false, label %bb17716.i, label %bb17683.i
+bb17673.i: ; preds = %bb17225.i
+ br i1 false, label %bb17716.i, label %bb17683.i
+bb17674.i: ; preds = %bb17225.i
+ br i1 false, label %bb17716.i, label %bb17683.i
+bb17675.i: ; preds = %bb17225.i
+ br i1 false, label %bb17716.i, label %bb17683.i
+bb17676.i: ; preds = %bb17225.i, %bb17225.i
+ br i1 false, label %bb17716.i, label %bb17683.i
+bb17677.i: ; preds = %bb17225.i
+ unreachable
+bb17680.i: ; preds = %bb17225.i, %bb17225.i, %bb17225.i
+ br i1 false, label %bb17716.i, label %bb17683.i
+bb17683.i: ; preds = %bb17680.i, %bb17676.i, %bb17675.i, %bb17674.i, %bb17673.i, %bb17672.i
+ br label %bb17716.i
+bb17716.i: ; preds = %bb17683.i, %bb17680.i, %bb17676.i, %bb17675.i, %bb17674.i, %bb17673.i, %bb17672.i
+ br label %bb18851.i
+bb17749.i: ; preds = %bb16697.i
+ br i1 false, label %bb17757.i, label %bb17903.i
+bb17757.i: ; preds = %bb17749.i
+ switch i32 0, label %bb17903.i [
+ i32 0, label %bb17759.i
+ i32 1, label %bb17853.i
+ i32 2, label %bb17853.i
+ ]
+bb17759.i: ; preds = %bb17757.i
+ br i1 false, label %bb17764.i, label %bb17772.i
+bb17764.i: ; preds = %bb17759.i
+ br label %bb18032.i
+bb17772.i: ; preds = %bb17759.i
+ switch i32 %sf4083.0.i, label %bb17798.i [
+ i32 1, label %bb17777.i
+ i32 2, label %bb17790.i
+ ]
+bb17777.i: ; preds = %bb17772.i
+ switch i32 0, label %bb18032.i [
+ i32 4, label %bb17818.i
+ i32 8, label %bb17818.i
+ i32 11, label %bb17845.i
+ ]
+bb17790.i: ; preds = %bb17772.i
+ switch i32 0, label %bb18032.i [
+ i32 4, label %bb17818.i
+ i32 8, label %bb17818.i
+ i32 11, label %bb17845.i
+ ]
+bb17798.i: ; preds = %bb17772.i
+ switch i32 0, label %bb18032.i [
+ i32 4, label %bb17818.i
+ i32 8, label %bb17818.i
+ i32 11, label %bb17845.i
+ ]
+bb17818.i: ; preds = %bb17798.i, %bb17798.i, %bb17790.i, %bb17790.i, %bb17777.i, %bb17777.i
+ switch i32 0, label %bb18032.i [
+ i32 4, label %bb17845.i
+ i32 11, label %bb17845.i
+ i32 8, label %bb17946.i
+ ]
+bb17845.i: ; preds = %bb17818.i, %bb17818.i, %bb17798.i, %bb17790.i, %bb17777.i
+ switch i32 0, label %bb18032.i [
+ i32 4, label %bb17908.i
+ i32 8, label %bb17946.i
+ i32 11, label %bb17998.i
+ ]
+bb17853.i: ; preds = %bb17757.i, %bb17757.i
+ br i1 false, label %bb17890.i, label %bb17903.i
+bb17890.i: ; preds = %bb17853.i
+ br label %bb17903.i
+bb17903.i: ; preds = %bb17890.i, %bb17853.i, %bb17757.i, %bb17749.i
+ switch i32 0, label %bb18032.i [
+ i32 4, label %bb17908.i
+ i32 8, label %bb17946.i
+ i32 11, label %bb17998.i
+ ]
+bb17908.i: ; preds = %bb17903.i, %bb17845.i
+ switch i32 %df4081.0.i, label %bb18386.i [
+ i32 1, label %bb17913.i
+ i32 2, label %bb17924.i
+ i32 3, label %bb17935.i
+ ]
+bb17913.i: ; preds = %bb17908.i
+ br label %bb18398.i
+bb17924.i: ; preds = %bb17908.i
+ br label %bb18398.i
+bb17935.i: ; preds = %bb17908.i
+ br label %bb18398.i
+bb17946.i: ; preds = %bb17903.i, %bb17845.i, %bb17818.i
+ switch i32 0, label %bb17962.i [
+ i32 4, label %bb17958.i
+ i32 11, label %bb17958.i
+ ]
+bb17958.i: ; preds = %bb17946.i, %bb17946.i
+ br label %bb18398.i
+bb17962.i: ; preds = %bb17946.i
+ switch i32 %df4081.0.i, label %bb18386.i [
+ i32 1, label %bb17967.i
+ i32 2, label %bb17978.i
+ i32 3, label %bb17989.i
+ ]
+bb17967.i: ; preds = %bb17962.i
+ br label %bb18398.i
+bb17978.i: ; preds = %bb17962.i
+ br label %bb18398.i
+bb17989.i: ; preds = %bb17962.i
+ br label %bb18398.i
+bb17998.i: ; preds = %bb17903.i, %bb17845.i
+ switch i32 0, label %bb18386.i [
+ i32 4, label %bb18010.i
+ i32 8, label %bb18010.i
+ i32 3, label %bb18026.i
+ ]
+bb18010.i: ; preds = %bb17998.i, %bb17998.i
+ br label %bb18398.i
+bb18026.i: ; preds = %bb17998.i
+ br label %bb18398.i
+bb18032.i: ; preds = %bb17903.i, %bb17845.i, %bb17818.i, %bb17798.i, %bb17790.i, %bb17777.i, %bb17764.i
+ switch i32 %sf4083.0.i, label %bb18386.i [
+ i32 10, label %bb18037.i
+ i32 0, label %bb18095.i
+ i32 1, label %bb18156.i
+ i32 2, label %bb18240.i
+ i32 3, label %bb18324.i
+ ]
+bb18037.i: ; preds = %bb18032.i
+ switch i32 0, label %bb18081.i [
+ i32 4, label %bb18042.i
+ i32 8, label %bb18061.i
+ i32 11, label %bb18077.i
+ ]
+bb18042.i: ; preds = %bb18037.i
+ br label %bb18398.i
+bb18061.i: ; preds = %bb18037.i
+ br label %bb18398.i
+bb18077.i: ; preds = %bb18037.i
+ br label %bb18398.i
+bb18081.i: ; preds = %bb18037.i
+ br i1 false, label %bb18086.i, label %bb18386.i
+bb18086.i: ; preds = %bb18081.i
+ br label %bb18398.i
+bb18095.i: ; preds = %bb18032.i
+ switch i32 0, label %bb18133.i [
+ i32 4, label %bb18100.i
+ i32 8, label %bb18116.i
+ i32 11, label %bb18129.i
+ ]
+bb18100.i: ; preds = %bb18095.i
+ br label %bb18398.i
+bb18116.i: ; preds = %bb18095.i
+ br label %bb18398.i
+bb18129.i: ; preds = %bb18095.i
+ br label %bb18398.i
+bb18133.i: ; preds = %bb18095.i
+ br i1 false, label %bb18139.i, label %bb18142.i
+bb18139.i: ; preds = %bb18133.i
+ br label %bb18398.i
+bb18142.i: ; preds = %bb18133.i
+ br i1 false, label %bb18147.i, label %bb18386.i
+bb18147.i: ; preds = %bb18142.i
+ br label %bb18398.i
+bb18156.i: ; preds = %bb18032.i
+ switch i32 0, label %bb18206.i [
+ i32 4, label %bb18161.i
+ i32 8, label %bb18182.i
+ i32 11, label %bb18200.i
+ ]
+bb18161.i: ; preds = %bb18156.i
+ br label %bb18398.i
+bb18182.i: ; preds = %bb18156.i
+ br label %bb18398.i
+bb18200.i: ; preds = %bb18156.i
+ br label %bb18398.i
+bb18206.i: ; preds = %bb18156.i
+ switch i32 %df4081.0.i, label %bb18386.i [
+ i32 0, label %bb18223.i
+ i32 2, label %bb18223.i
+ i32 10, label %bb18223.i
+ i32 3, label %bb18231.i
+ ]
+bb18223.i: ; preds = %bb18206.i, %bb18206.i, %bb18206.i
+ br label %bb18398.i
+bb18231.i: ; preds = %bb18206.i
+ br label %bb18398.i
+bb18240.i: ; preds = %bb18032.i
+ switch i32 0, label %bb18290.i [
+ i32 4, label %bb18245.i
+ i32 8, label %bb18266.i
+ i32 11, label %bb18284.i
+ ]
+bb18245.i: ; preds = %bb18240.i
+ br label %bb18398.i
+bb18266.i: ; preds = %bb18240.i
+ br label %bb18398.i
+bb18284.i: ; preds = %bb18240.i
+ br label %bb18398.i
+bb18290.i: ; preds = %bb18240.i
+ switch i32 %df4081.0.i, label %bb18386.i [
+ i32 0, label %bb18307.i
+ i32 1, label %bb18307.i
+ i32 10, label %bb18307.i
+ i32 3, label %bb18315.i
+ ]
+bb18307.i: ; preds = %bb18290.i, %bb18290.i, %bb18290.i
+ br label %bb18398.i
+bb18315.i: ; preds = %bb18290.i
+ br label %bb18398.i
+bb18324.i: ; preds = %bb18032.i
+ switch i32 0, label %bb18386.i [
+ i32 4, label %bb18329.i
+ i32 8, label %bb18352.i
+ i32 11, label %bb18370.i
+ i32 10, label %bb18383.i
+ ]
+bb18329.i: ; preds = %bb18324.i
+ br label %bb18398.i
+bb18352.i: ; preds = %bb18324.i
+ br label %bb18398.i
+bb18370.i: ; preds = %bb18324.i
+ br label %bb18398.i
+bb18383.i: ; preds = %bb18324.i
+ br label %bb18386.i
+bb18386.i: ; preds = %bb18383.i, %bb18324.i, %bb18290.i, %bb18206.i, %bb18142.i, %bb18081.i, %bb18032.i, %bb17998.i, %bb17962.i, %bb17908.i
+ br label %bb18398.i
+bb18398.i: ; preds = %bb18386.i, %bb18370.i, %bb18352.i, %bb18329.i, %bb18315.i, %bb18307.i, %bb18284.i, %bb18266.i, %bb18245.i, %bb18231.i, %bb18223.i, %bb18200.i, %bb18182.i, %bb18161.i, %bb18147.i, %bb18139.i, %bb18129.i, %bb18116.i, %bb18100.i, %bb18086.i, %bb18077.i, %bb18061.i, %bb18042.i, %bb18026.i, %bb18010.i, %bb17989.i, %bb17978.i, %bb17967.i, %bb17958.i, %bb17935.i, %bb17924.i, %bb17913.i
+ br i1 false, label %bb18589.i, label %bb18431.i
+bb18431.i: ; preds = %bb18398.i
+ switch i32 0, label %bb18589.i [
+ i32 0, label %bb18433.i
+ i32 1, label %bb18487.i
+ i32 2, label %bb18487.i
+ ]
+bb18433.i: ; preds = %bb18431.i
+ switch i32 0, label %bb18589.i [
+ i32 4, label %bb18452.i
+ i32 8, label %bb18452.i
+ i32 11, label %bb18479.i
+ ]
+bb18452.i: ; preds = %bb18433.i, %bb18433.i
+ switch i32 0, label %bb18589.i [
+ i32 4, label %bb18479.i
+ i32 11, label %bb18479.i
+ ]
+bb18479.i: ; preds = %bb18452.i, %bb18452.i, %bb18433.i
+ br i1 false, label %bb18845.i, label %bb18592.i
+bb18487.i: ; preds = %bb18431.i, %bb18431.i
+ br i1 false, label %bb18492.i, label %bb18521.i
+bb18492.i: ; preds = %bb18487.i
+ br i1 false, label %bb18508.i, label %bb18529.i
+bb18508.i: ; preds = %bb18492.i
+ switch i32 0, label %bb18589.i [
+ i32 4, label %bb18541.i
+ i32 8, label %bb18541.i
+ ]
+bb18521.i: ; preds = %bb18487.i
+ br label %bb18529.i
+bb18529.i: ; preds = %bb18521.i, %bb18492.i
+ switch i32 0, label %bb18589.i [
+ i32 4, label %bb18541.i
+ i32 8, label %bb18541.i
+ ]
+bb18541.i: ; preds = %bb18529.i, %bb18529.i, %bb18508.i, %bb18508.i
+ br i1 false, label %bb18560.i, label %bb18589.i
+bb18560.i: ; preds = %bb18541.i
+ br i1 false, label %bb18576.i, label %bb18589.i
+bb18576.i: ; preds = %bb18560.i
+ br label %bb18589.i
+bb18589.i: ; preds = %bb18576.i, %bb18560.i, %bb18541.i, %bb18529.i, %bb18508.i, %bb18452.i, %bb18433.i, %bb18431.i, %bb18398.i
+ br i1 false, label %bb18845.i, label %bb18592.i
+bb18592.i: ; preds = %bb18589.i, %bb18479.i
+ switch i32 %dt4080.0.i, label %bb18809.i [
+ i32 4, label %bb18845.i
+ i32 8, label %bb18594.i
+ i32 9, label %bb18619.i
+ i32 10, label %bb18644.i
+ i32 11, label %bb18644.i
+ i32 14, label %bb18669.i
+ i32 15, label %bb18702.i
+ i32 18, label %bb18735.i
+ i32 19, label %bb18768.i
+ i32 0, label %bb18812.i
+ i32 1, label %bb18804.i
+ i32 2, label %bb18805.i
+ i32 3, label %bb18806.i
+ i32 5, label %bb18807.i
+ i32 12, label %bb18808.i
+ i32 13, label %bb18808.i
+ i32 16, label %bb18812.i
+ i32 17, label %bb18812.i
+ ]
+bb18594.i: ; preds = %bb18592.i
+ br label %bb18851.i
+bb18619.i: ; preds = %bb18592.i
+ br label %bb18851.i
+bb18644.i: ; preds = %bb18592.i, %bb18592.i
+ br label %bb18851.i
+bb18669.i: ; preds = %bb18592.i
+ br label %bb18851.i
+bb18702.i: ; preds = %bb18592.i
+ br label %bb18851.i
+bb18735.i: ; preds = %bb18592.i
+ br label %bb18851.i
+bb18768.i: ; preds = %bb18592.i
+ br label %bb18851.i
+bb18804.i: ; preds = %bb18592.i
+ br label %bb18812.i
+bb18805.i: ; preds = %bb18592.i
+ br label %bb18812.i
+bb18806.i: ; preds = %bb18592.i
+ br label %bb18812.i
+bb18807.i: ; preds = %bb18592.i
+ br label %bb18812.i
+bb18808.i: ; preds = %bb18592.i, %bb18592.i
+ br label %bb18812.i
+bb18809.i: ; preds = %bb18592.i
+ unreachable
+bb18812.i: ; preds = %bb18808.i, %bb18807.i, %bb18806.i, %bb18805.i, %bb18804.i, %bb18592.i, %bb18592.i, %bb18592.i
+ br label %bb18845.i
+bb18845.i: ; preds = %bb18812.i, %bb18592.i, %bb18589.i, %bb18479.i, %bb17227.i, %bb17195.i
+ br label %bb18851.i
+bb18851.i: ; preds = %bb18845.i, %bb18768.i, %bb18735.i, %bb18702.i, %bb18669.i, %bb18644.i, %bb18619.i, %bb18594.i, %bb17716.i, %bb17636.i, %bb17571.i, %bb17506.i, %bb17441.i, %bb17384.i, %bb17334.i, %bb17284.i, %bb17230.i, %glgScalarFloatConversion.exit
+ br label %storeColor_RGB_UI.exit
+storeColor_RGB_UI.exit: ; preds = %bb18851.i
+ br i1 false, label %bb19786.i, label %bb16650.i
+bb19786.i: ; preds = %storeColor_RGB_UI.exit
+ br label %bb19808.i
+bb19808.i: ; preds = %bb19786.i
+ br i1 false, label %bb19818.i, label %bb5276.i
+bb19818.i: ; preds = %bb19808.i
+ br i1 false, label %bb19840.i, label %bb19821.i
+bb19821.i: ; preds = %bb19818.i
+ br label %bb19840.i
+bb19840.i: ; preds = %bb19821.i, %bb19818.i
+ br i1 false, label %UnifiedReturnBlock.i, label %bb19843.i
+bb19843.i: ; preds = %bb19840.i
+ br label %t.exit
+UnifiedReturnBlock.i: ; preds = %bb19840.i, %bb4501.i
+ br label %t.exit
+t.exit: ; preds = %UnifiedReturnBlock.i, %bb19843.i, %bb4517.i, %bb4354.i
+ ret void
+}
diff --git a/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll b/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll
new file mode 100644
index 0000000..71aa603
--- /dev/null
+++ b/test/CodeGen/ARM/2008-05-19-LiveIntervalsBug.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+ %struct.BiContextType = type { i16, i8, i32 }
+ %struct.Bitstream = type { i32, i32, i8, i32, i32, i8, i8, i32, i32, i8*, i32 }
+ %struct.DataPartition = type { %struct.Bitstream*, %struct.EncodingEnvironment, %struct.EncodingEnvironment }
+ %struct.DecRefPicMarking_t = type { i32, i32, i32, i32, i32, %struct.DecRefPicMarking_t* }
+ %struct.EncodingEnvironment = type { i32, i32, i32, i32, i32, i8*, i32*, i32, i32 }
+ %struct.ImageParameters = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8**, i8**, i32, i32***, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [9 x [16 x [16 x i16]]], [5 x [16 x [16 x i16]]], [9 x [8 x [8 x i16]]], [2 x [4 x [16 x [16 x i16]]]], [16 x [16 x i16]], [16 x [16 x i32]], i32****, i32***, i32***, i32***, i32****, i32****, %struct.Picture*, %struct.Slice*, %struct.Macroblock*, i32*, i32*, i32, i32, i32, i32, [4 x [4 x i32]], i32, i32, i32, i32, i32, double, i32, i32, i32, i32, i16******, i16******, i16******, i16******, [15 x i16], i32, i32, i32, i32, i32, i32, i32, i32, [6 x [32 x i32]], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [1 x i32], i32, i32, [2 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.DecRefPicMarking_t*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, double**, double***, i32***, double**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x [2 x i32]], [2 x i32], i32, i32, i16, i32, i32, i32, i32, i32 }
+ %struct.Macroblock = type { i32, i32, i32, [2 x i32], i32, [8 x i32], %struct.Macroblock*, %struct.Macroblock*, i32, [2 x [4 x [4 x [2 x i32]]]], [16 x i8], [16 x i8], i32, i64, [4 x i32], [4 x i32], i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, double, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.MotionInfoContexts = type { [3 x [11 x %struct.BiContextType]], [2 x [9 x %struct.BiContextType]], [2 x [10 x %struct.BiContextType]], [2 x [6 x %struct.BiContextType]], [4 x %struct.BiContextType], [4 x %struct.BiContextType], [3 x %struct.BiContextType] }
+ %struct.Picture = type { i32, i32, [100 x %struct.Slice*], i32, float, float, float }
+ %struct.Slice = type { i32, i32, i32, i32, i32, i32, %struct.DataPartition*, %struct.MotionInfoContexts*, %struct.TextureInfoContexts*, i32, i32*, i32*, i32*, i32, i32*, i32*, i32*, i32 (i32)*, [3 x [2 x i32]] }
+ %struct.TextureInfoContexts = type { [2 x %struct.BiContextType], [4 x %struct.BiContextType], [3 x [4 x %struct.BiContextType]], [10 x [4 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [5 x %struct.BiContextType]], [10 x [5 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]] }
+@images = external global %struct.ImageParameters ; <%struct.ImageParameters*> [#uses=2]
+
+declare i8* @calloc(i32, i32)
+
+define fastcc void @init_global_buffers() nounwind {
+entry:
+ %tmp50.i.i = mul i32 0, 0 ; <i32> [#uses=2]
+ br i1 false, label %init_orig_buffers.exit, label %cond_true.i29
+
+cond_true.i29: ; preds = %entry
+ %tmp17.i = load i32* getelementptr (%struct.ImageParameters* @images, i32 0, i32 20), align 8 ; <i32> [#uses=1]
+ %tmp20.i27 = load i32* getelementptr (%struct.ImageParameters* @images, i32 0, i32 16), align 8 ; <i32> [#uses=1]
+ %tmp8.i.i = select i1 false, i32 1, i32 0 ; <i32> [#uses=1]
+ br label %bb.i8.us.i
+
+bb.i8.us.i: ; preds = %get_mem2Dpel.exit.i.us.i, %cond_true.i29
+ %j.04.i.us.i = phi i32 [ %indvar.next39.i, %get_mem2Dpel.exit.i.us.i ], [ 0, %cond_true.i29 ] ; <i32> [#uses=2]
+ %tmp13.i.us.i = getelementptr i16*** null, i32 %j.04.i.us.i ; <i16***> [#uses=0]
+ %tmp15.i.i.us.i = tail call i8* @calloc( i32 0, i32 2 ) ; <i8*> [#uses=0]
+ store i16* null, i16** null, align 4
+ br label %bb.i.i.us.i
+
+get_mem2Dpel.exit.i.us.i: ; preds = %bb.i.i.us.i
+ %indvar.next39.i = add i32 %j.04.i.us.i, 1 ; <i32> [#uses=2]
+ %exitcond40.i = icmp eq i32 %indvar.next39.i, 2 ; <i1> [#uses=1]
+ br i1 %exitcond40.i, label %get_mem3Dpel.exit.split.i, label %bb.i8.us.i
+
+bb.i.i.us.i: ; preds = %bb.i.i.us.i, %bb.i8.us.i
+ %exitcond.i = icmp eq i32 0, %tmp8.i.i ; <i1> [#uses=1]
+ br i1 %exitcond.i, label %get_mem2Dpel.exit.i.us.i, label %bb.i.i.us.i
+
+get_mem3Dpel.exit.split.i: ; preds = %get_mem2Dpel.exit.i.us.i
+ %tmp30.i.i = shl i32 %tmp17.i, 2 ; <i32> [#uses=1]
+ %tmp31.i.i = mul i32 %tmp30.i.i, %tmp20.i27 ; <i32> [#uses=1]
+ %tmp23.i31 = add i32 %tmp31.i.i, %tmp50.i.i ; <i32> [#uses=1]
+ br label %init_orig_buffers.exit
+
+init_orig_buffers.exit: ; preds = %get_mem3Dpel.exit.split.i, %entry
+ %memory_size.0.i = phi i32 [ %tmp23.i31, %get_mem3Dpel.exit.split.i ], [ %tmp50.i.i, %entry ] ; <i32> [#uses=1]
+ %tmp41 = add i32 0, %memory_size.0.i ; <i32> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll b/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll
new file mode 100644
index 0000000..aa61d86
--- /dev/null
+++ b/test/CodeGen/ARM/2008-05-19-ScavengerAssert.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+ %struct.Decoders = type { i32**, i16***, i16****, i16***, i16**, i8**, i8** }
+@decoders = external global %struct.Decoders ; <%struct.Decoders*> [#uses=1]
+
+declare i8* @calloc(i32, i32)
+
+declare fastcc i32 @get_mem2Dint(i32***, i32, i32)
+
+define fastcc void @init_global_buffers() nounwind {
+entry:
+ %tmp151 = tail call fastcc i32 @get_mem2Dint( i32*** getelementptr (%struct.Decoders* @decoders, i32 0, i32 0), i32 16, i32 16 ) ; <i32> [#uses=1]
+ %tmp158 = tail call i8* @calloc( i32 0, i32 4 ) ; <i8*> [#uses=0]
+ br i1 false, label %cond_true166, label %bb190.preheader
+
+bb190.preheader: ; preds = %entry
+ %memory_size.3555 = add i32 0, %tmp151 ; <i32> [#uses=0]
+ unreachable
+
+cond_true166: ; preds = %entry
+ unreachable
+}
diff --git a/test/CodeGen/ARM/2008-07-17-Fdiv.ll b/test/CodeGen/ARM/2008-07-17-Fdiv.ll
new file mode 100644
index 0000000..4cb768e
--- /dev/null
+++ b/test/CodeGen/ARM/2008-07-17-Fdiv.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=arm
+
+define float @f(float %a, float %b) nounwind {
+ %tmp = fdiv float %a, %b
+ ret float %tmp
+}
diff --git a/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll b/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll
new file mode 100644
index 0000000..83fde07
--- /dev/null
+++ b/test/CodeGen/ARM/2008-07-24-CodeGenPrepCrash.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=arm
+; PR2589
+
+define void @main({ i32 }*) {
+entry:
+ %sret1 = alloca { i32 } ; <{ i32 }*> [#uses=1]
+ load { i32 }* %sret1 ; <{ i32 }>:1 [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll b/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll
new file mode 100644
index 0000000..adb0112
--- /dev/null
+++ b/test/CodeGen/ARM/2008-08-07-AsmPrintBug.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 -relocation-model=pic | grep comm
+
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.__gcov_var = type { %struct.FILE*, i32, i32, i32, i32, i32, i32, [1025 x i32] }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+@__gcov_var = common global %struct.__gcov_var zeroinitializer ; <%struct.__gcov_var*> [#uses=1]
+
+define i32 @__gcov_close() nounwind {
+entry:
+ load i32* getelementptr (%struct.__gcov_var* @__gcov_var, i32 0, i32 5), align 4 ; <i32>:0 [#uses=1]
+ ret i32 %0
+}
diff --git a/test/CodeGen/ARM/2008-09-14-CoalescerBug.ll b/test/CodeGen/ARM/2008-09-14-CoalescerBug.ll
new file mode 100644
index 0000000..5f9d9ae
--- /dev/null
+++ b/test/CodeGen/ARM/2008-09-14-CoalescerBug.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+@"\01LC1" = external constant [288 x i8] ; <[288 x i8]*> [#uses=1]
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+ br label %bb.i
+
+bb.i: ; preds = %bb.i, %entry
+ %i.01.i = phi i32 [ 0, %entry ], [ %indvar.next52, %bb.i ] ; <i32> [#uses=1]
+ %indvar.next52 = add i32 %i.01.i, 1 ; <i32> [#uses=2]
+ %exitcond53 = icmp eq i32 %indvar.next52, 15 ; <i1> [#uses=1]
+ br i1 %exitcond53, label %bb.i33.loopexit, label %bb.i
+
+bb.i33.loopexit: ; preds = %bb.i
+ %0 = malloc [347 x i8] ; <[347 x i8]*> [#uses=2]
+ %.sub = getelementptr [347 x i8]* %0, i32 0, i32 0 ; <i8*> [#uses=1]
+ call void @llvm.memcpy.i32( i8* %.sub, i8* getelementptr ([288 x i8]* @"\01LC1", i32 0, i32 0), i32 287, i32 1 ) nounwind
+ br label %bb.i28
+
+bb.i28: ; preds = %bb.i28, %bb.i33.loopexit
+ br i1 false, label %repeat_fasta.exit, label %bb.i28
+
+repeat_fasta.exit: ; preds = %bb.i28
+ free [347 x i8]* %0
+ unreachable
+}
diff --git a/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll b/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll
new file mode 100644
index 0000000..d3bc3e1
--- /dev/null
+++ b/test/CodeGen/ARM/2008-09-17-CoalescerBug.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+define void @gcov_exit() nounwind {
+entry:
+ br i1 false, label %bb24, label %bb33.thread
+
+bb24: ; preds = %entry
+ br label %bb39
+
+bb33.thread: ; preds = %entry
+ %0 = alloca i8, i32 0 ; <i8*> [#uses=1]
+ br label %bb39
+
+bb39: ; preds = %bb33.thread, %bb24
+ %.reg2mem.0 = phi i8* [ %0, %bb33.thread ], [ null, %bb24 ] ; <i8*> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/ARM/2008-11-18-ScavengerAssert.ll b/test/CodeGen/ARM/2008-11-18-ScavengerAssert.ll
new file mode 100644
index 0000000..601a516
--- /dev/null
+++ b/test/CodeGen/ARM/2008-11-18-ScavengerAssert.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2
+
+define hidden i64 @__muldi3(i64 %u, i64 %v) nounwind {
+entry:
+ %0 = trunc i64 %u to i32 ; <i32> [#uses=1]
+ %asmtmp = tail call { i32, i32, i32, i32, i32 } asm "@ Inlined umul_ppmm\0A\09mov\09$2, $5, lsr #16\0A\09mov\09$0, $6, lsr #16\0A\09bic\09$3, $5, $2, lsl #16\0A\09bic\09$4, $6, $0, lsl #16\0A\09mul\09$1, $3, $4\0A\09mul\09$4, $2, $4\0A\09mul\09$3, $0, $3\0A\09mul\09$0, $2, $0\0A\09adds\09$3, $4, $3\0A\09addcs\09$0, $0, #65536\0A\09adds\09$1, $1, $3, lsl #16\0A\09adc\09$0, $0, $3, lsr #16", "=&r,=r,=&r,=&r,=r,r,r,~{cc}"(i32 %0, i32 0) nounwind ; <{ i32, i32, i32, i32, i32 }> [#uses=1]
+ %asmresult1 = extractvalue { i32, i32, i32, i32, i32 } %asmtmp, 1 ; <i32> [#uses=1]
+ %asmresult116 = zext i32 %asmresult1 to i64 ; <i64> [#uses=1]
+ %asmresult116.ins = or i64 0, %asmresult116 ; <i64> [#uses=1]
+ %1 = lshr i64 %v, 32 ; <i64> [#uses=1]
+ %2 = mul i64 %1, %u ; <i64> [#uses=1]
+ %3 = add i64 %2, 0 ; <i64> [#uses=1]
+ %4 = shl i64 %3, 32 ; <i64> [#uses=1]
+ %5 = add i64 %asmresult116.ins, %4 ; <i64> [#uses=1]
+ ret i64 %5
+}
diff --git a/test/CodeGen/ARM/2009-02-16-SpillerBug.ll b/test/CodeGen/ARM/2009-02-16-SpillerBug.ll
new file mode 100644
index 0000000..4c0c59c
--- /dev/null
+++ b/test/CodeGen/ARM/2009-02-16-SpillerBug.ll
@@ -0,0 +1,117 @@
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2
+
+target triple = "arm-apple-darwin9"
+ %struct.FILE_POS = type { i8, i8, i16, i32 }
+ %struct.FIRST_UNION = type { %struct.FILE_POS }
+ %struct.FOURTH_UNION = type { %struct.STYLE }
+ %struct.GAP = type { i8, i8, i16 }
+ %struct.LIST = type { %struct.rec*, %struct.rec* }
+ %struct.SECOND_UNION = type { { i16, i8, i8 } }
+ %struct.STYLE = type { { %struct.GAP }, { %struct.GAP }, i16, i16, i32 }
+ %struct.THIRD_UNION = type { { [2 x i32], [2 x i32] } }
+ %struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, %struct.rec*, { %struct.rec* }, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i32 }
+ %struct.rec = type { %struct.head_type }
+@no_file_pos = external global %struct.FILE_POS ; <%struct.FILE_POS*> [#uses=1]
+@"\01LC13423" = external constant [23 x i8] ; <[23 x i8]*> [#uses=1]
+@"\01LC18972" = external constant [13 x i8] ; <[13 x i8]*> [#uses=1]
+
+define fastcc void @FlushGalley(%struct.rec* %hd) nounwind {
+entry:
+ br label %RESUME
+
+RESUME: ; preds = %bb520.preheader, %entry
+ br label %bb396
+
+bb122: ; preds = %bb396
+ switch i32 0, label %bb394 [
+ i32 1, label %bb131
+ i32 2, label %bb244
+ i32 4, label %bb244
+ i32 5, label %bb244
+ i32 6, label %bb244
+ i32 7, label %bb244
+ i32 11, label %bb244
+ i32 12, label %bb244
+ i32 15, label %bb244
+ i32 17, label %bb244
+ i32 18, label %bb244
+ i32 19, label %bb244
+ i32 20, label %bb396
+ i32 21, label %bb396
+ i32 22, label %bb396
+ i32 23, label %bb396
+ i32 24, label %bb244
+ i32 25, label %bb244
+ i32 26, label %bb244
+ i32 27, label %bb244
+ i32 28, label %bb244
+ i32 29, label %bb244
+ i32 30, label %bb244
+ i32 31, label %bb244
+ i32 32, label %bb244
+ i32 33, label %bb244
+ i32 34, label %bb244
+ i32 35, label %bb244
+ i32 36, label %bb244
+ i32 37, label %bb244
+ i32 38, label %bb244
+ i32 39, label %bb244
+ i32 40, label %bb244
+ i32 41, label %bb244
+ i32 42, label %bb244
+ i32 43, label %bb244
+ i32 44, label %bb244
+ i32 45, label %bb244
+ i32 46, label %bb244
+ i32 50, label %bb244
+ i32 51, label %bb244
+ i32 94, label %bb244
+ i32 95, label %bb244
+ i32 96, label %bb244
+ i32 97, label %bb244
+ i32 98, label %bb244
+ i32 99, label %bb244
+ ]
+
+bb131: ; preds = %bb122
+ br label %bb396
+
+bb244: ; preds = %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122
+ %0 = icmp eq %struct.rec* %stop_link.3, null ; <i1> [#uses=1]
+ br i1 %0, label %bb435, label %bb433
+
+bb394: ; preds = %bb122
+ call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 3, i8* getelementptr ([23 x i8]* @"\01LC13423", i32 0, i32 0), i32 0, %struct.FILE_POS* @no_file_pos, i8* getelementptr ([13 x i8]* @"\01LC18972", i32 0, i32 0), i8* null) nounwind
+ br label %bb396
+
+bb396: ; preds = %bb394, %bb131, %bb122, %bb122, %bb122, %bb122, %RESUME
+ %stop_link.3 = phi %struct.rec* [ null, %RESUME ], [ %stop_link.3, %bb394 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %stop_link.3, %bb122 ], [ %link.1, %bb131 ] ; <%struct.rec*> [#uses=7]
+ %headers_seen.1 = phi i32 [ 0, %RESUME ], [ %headers_seen.1, %bb394 ], [ 1, %bb122 ], [ 1, %bb122 ], [ 1, %bb122 ], [ 1, %bb122 ], [ %headers_seen.1, %bb131 ] ; <i32> [#uses=2]
+ %link.1 = load %struct.rec** null ; <%struct.rec*> [#uses=2]
+ %1 = icmp eq %struct.rec* %link.1, %hd ; <i1> [#uses=1]
+ br i1 %1, label %bb398, label %bb122
+
+bb398: ; preds = %bb396
+ unreachable
+
+bb433: ; preds = %bb244
+ call fastcc void @Promote(%struct.rec* %hd, %struct.rec* %stop_link.3, %struct.rec* null, i32 1) nounwind
+ br label %bb435
+
+bb435: ; preds = %bb433, %bb244
+ br i1 false, label %bb491, label %bb499
+
+bb491: ; preds = %bb435
+ br label %bb499
+
+bb499: ; preds = %bb499, %bb491, %bb435
+ %2 = icmp eq %struct.rec* null, null ; <i1> [#uses=1]
+ br i1 %2, label %bb520.preheader, label %bb499
+
+bb520.preheader: ; preds = %bb499
+ br label %RESUME
+}
+
+declare fastcc void @Promote(%struct.rec*, %struct.rec*, %struct.rec* nocapture, i32) nounwind
+
+declare void @Error(i32, i32, i8*, i32, %struct.FILE_POS*, ...) nounwind
diff --git a/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll b/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll
new file mode 100644
index 0000000..a48f003
--- /dev/null
+++ b/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s
+; PR3610
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-s0:0:64-f80:32:32"
+target triple = "arm-elf"
+
+define i32 @main(i8*) nounwind {
+entry:
+ %ap = alloca i8* ; <i8**> [#uses=2]
+ store i8* %0, i8** %ap
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ store i32 0, i32* %retval
+ %tmp = alloca float ; <float*> [#uses=1]
+ %1 = va_arg i8** %ap, float ; <float> [#uses=1]
+ store float %1, float* %tmp
+ br label %return
+
+return: ; preds = %entry
+ %2 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %2
+}
diff --git a/test/CodeGen/ARM/2009-02-27-SpillerBug.ll b/test/CodeGen/ARM/2009-02-27-SpillerBug.ll
new file mode 100644
index 0000000..bc5e602
--- /dev/null
+++ b/test/CodeGen/ARM/2009-02-27-SpillerBug.ll
@@ -0,0 +1,229 @@
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2
+
+target triple = "arm-apple-darwin9"
+@a = external global double ; <double*> [#uses=1]
+@N = external global double ; <double*> [#uses=1]
+
+declare double @llvm.exp.f64(double) nounwind readonly
+
+define fastcc void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind {
+bb.thread:
+ br label %bb52
+
+bb32: ; preds = %bb52
+ %0 = fadd double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ %1 = add i32 %j.1, 1 ; <i32> [#uses=1]
+ br label %bb52
+
+bb52: ; preds = %bb53, %bb32, %bb.thread
+ %i.3494 = phi i32 [ 0, %bb.thread ], [ %3, %bb53 ], [ %i.3494, %bb32 ] ; <i32> [#uses=2]
+ %k.4 = phi double [ %0, %bb32 ], [ 0.000000e+00, %bb53 ], [ 0.000000e+00, %bb.thread ] ; <double> [#uses=2]
+ %j.1 = phi i32 [ %1, %bb32 ], [ 0, %bb53 ], [ 0, %bb.thread ] ; <i32> [#uses=2]
+ %2 = icmp sgt i32 %j.1, 99 ; <i1> [#uses=1]
+ br i1 %2, label %bb53, label %bb32
+
+bb53: ; preds = %bb52
+ %3 = add i32 %i.3494, 1 ; <i32> [#uses=2]
+ %phitmp = icmp sgt i32 %3, 999999 ; <i1> [#uses=1]
+ br i1 %phitmp, label %bb55, label %bb52
+
+bb55: ; preds = %bb53
+ %4 = load double* @a, align 4 ; <double> [#uses=10]
+ %5 = fadd double %4, 0.000000e+00 ; <double> [#uses=16]
+ %6 = fcmp ogt double %k.4, 0.000000e+00 ; <i1> [#uses=1]
+ %.pn404 = fmul double %4, %4 ; <double> [#uses=4]
+ %.pn402 = fmul double %5, %5 ; <double> [#uses=5]
+ %.pn165.in = load double* @N ; <double> [#uses=5]
+ %.pn198 = fmul double 0.000000e+00, %5 ; <double> [#uses=1]
+ %.pn185 = fsub double -0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ %.pn147 = fsub double -0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ %.pn141 = fdiv double 0.000000e+00, %4 ; <double> [#uses=1]
+ %.pn142 = fdiv double 0.000000e+00, %5 ; <double> [#uses=1]
+ %.pn136 = fdiv double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ %.pn132 = fdiv double 0.000000e+00, %5 ; <double> [#uses=1]
+ %.pn123 = fdiv double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ %.pn124 = fdiv double 0.000000e+00, %.pn198 ; <double> [#uses=1]
+ %.pn120 = fdiv double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ %.pn117 = fdiv double 0.000000e+00, %4 ; <double> [#uses=1]
+ %.pn118 = fdiv double %.pn185, %5 ; <double> [#uses=1]
+ %.pn88 = fdiv double %.pn147, %5 ; <double> [#uses=1]
+ %.pn81 = fsub double %.pn141, %.pn142 ; <double> [#uses=1]
+ %.pn77 = fsub double 0.000000e+00, %.pn136 ; <double> [#uses=1]
+ %.pn75 = fsub double 0.000000e+00, %.pn132 ; <double> [#uses=1]
+ %.pn69 = fsub double %.pn123, %.pn124 ; <double> [#uses=1]
+ %.pn67 = fsub double 0.000000e+00, %.pn120 ; <double> [#uses=1]
+ %.pn56 = fsub double %.pn117, %.pn118 ; <double> [#uses=1]
+ %.pn42 = fsub double 0.000000e+00, %.pn88 ; <double> [#uses=1]
+ %.pn60 = fmul double %.pn81, 0.000000e+00 ; <double> [#uses=1]
+ %.pn57 = fadd double %.pn77, 0.000000e+00 ; <double> [#uses=1]
+ %.pn58 = fmul double %.pn75, %.pn165.in ; <double> [#uses=1]
+ %.pn32 = fadd double %.pn69, 0.000000e+00 ; <double> [#uses=1]
+ %.pn33 = fmul double %.pn67, %.pn165.in ; <double> [#uses=1]
+ %.pn17 = fsub double 0.000000e+00, %.pn60 ; <double> [#uses=1]
+ %.pn9 = fadd double %.pn57, %.pn58 ; <double> [#uses=1]
+ %.pn30 = fmul double 0.000000e+00, %.pn56 ; <double> [#uses=1]
+ %.pn24 = fmul double 0.000000e+00, %.pn42 ; <double> [#uses=1]
+ %.pn1 = fadd double %.pn32, %.pn33 ; <double> [#uses=1]
+ %.pn28 = fsub double %.pn30, 0.000000e+00 ; <double> [#uses=1]
+ %.pn26 = fadd double %.pn28, 0.000000e+00 ; <double> [#uses=1]
+ %.pn22 = fsub double %.pn26, 0.000000e+00 ; <double> [#uses=1]
+ %.pn20 = fsub double %.pn24, 0.000000e+00 ; <double> [#uses=1]
+ %.pn18 = fadd double %.pn22, 0.000000e+00 ; <double> [#uses=1]
+ %.pn16 = fadd double %.pn20, 0.000000e+00 ; <double> [#uses=1]
+ %.pn14 = fsub double %.pn18, 0.000000e+00 ; <double> [#uses=1]
+ %.pn12 = fsub double %.pn16, %.pn17 ; <double> [#uses=1]
+ %.pn10 = fadd double %.pn14, 0.000000e+00 ; <double> [#uses=1]
+ %.pn8 = fadd double %.pn12, 0.000000e+00 ; <double> [#uses=1]
+ %.pn6 = fsub double %.pn10, 0.000000e+00 ; <double> [#uses=1]
+ %.pn4 = fsub double %.pn8, %.pn9 ; <double> [#uses=1]
+ %.pn2 = fadd double %.pn6, 0.000000e+00 ; <double> [#uses=1]
+ %.pn = fadd double %.pn4, 0.000000e+00 ; <double> [#uses=1]
+ %N1.0 = fsub double %.pn2, 0.000000e+00 ; <double> [#uses=2]
+ %D1.0 = fsub double %.pn, %.pn1 ; <double> [#uses=2]
+ br i1 %6, label %bb62, label %bb64
+
+bb62: ; preds = %bb55
+ %7 = fmul double 0.000000e+00, %4 ; <double> [#uses=1]
+ %8 = fsub double -0.000000e+00, %7 ; <double> [#uses=3]
+ %9 = fmul double 0.000000e+00, %5 ; <double> [#uses=1]
+ %10 = fsub double -0.000000e+00, %9 ; <double> [#uses=3]
+ %11 = fmul double %.pn404, %4 ; <double> [#uses=5]
+ %12 = fmul double %.pn402, %5 ; <double> [#uses=5]
+ %13 = fmul double 0.000000e+00, -2.000000e+00 ; <double> [#uses=1]
+ %14 = fdiv double 0.000000e+00, %.pn402 ; <double> [#uses=1]
+ %15 = fsub double 0.000000e+00, %14 ; <double> [#uses=1]
+ %16 = fmul double 0.000000e+00, %15 ; <double> [#uses=1]
+ %17 = fadd double %13, %16 ; <double> [#uses=1]
+ %18 = fmul double %.pn165.in, -2.000000e+00 ; <double> [#uses=5]
+ %19 = fmul double %18, 0.000000e+00 ; <double> [#uses=1]
+ %20 = fadd double %17, %19 ; <double> [#uses=1]
+ %21 = fmul double 0.000000e+00, %20 ; <double> [#uses=1]
+ %22 = fadd double 0.000000e+00, %21 ; <double> [#uses=1]
+ %23 = fdiv double 0.000000e+00, %12 ; <double> [#uses=1]
+ %24 = fsub double 0.000000e+00, %23 ; <double> [#uses=0]
+ %25 = fmul double %18, 0.000000e+00 ; <double> [#uses=1]
+ %26 = fadd double 0.000000e+00, %25 ; <double> [#uses=1]
+ %27 = fmul double 0.000000e+00, %26 ; <double> [#uses=1]
+ %28 = fsub double %22, %27 ; <double> [#uses=1]
+ %29 = fmul double %11, %4 ; <double> [#uses=1]
+ %30 = fmul double %12, %5 ; <double> [#uses=3]
+ %31 = fmul double %.pn165.in, -4.000000e+00 ; <double> [#uses=1]
+ %32 = fmul double %.pn165.in, 0x3FF5555555555555 ; <double> [#uses=1]
+ %33 = fmul double %32, 0.000000e+00 ; <double> [#uses=2]
+ %34 = fadd double %28, 0.000000e+00 ; <double> [#uses=1]
+ %35 = fsub double -0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ %36 = fdiv double %35, %11 ; <double> [#uses=1]
+ %37 = fdiv double 0.000000e+00, %12 ; <double> [#uses=1]
+ %38 = fsub double %36, %37 ; <double> [#uses=1]
+ %39 = fmul double 0.000000e+00, %38 ; <double> [#uses=1]
+ %40 = fadd double 0.000000e+00, %39 ; <double> [#uses=1]
+ %41 = fadd double %40, 0.000000e+00 ; <double> [#uses=1]
+ %42 = fadd double %41, 0.000000e+00 ; <double> [#uses=1]
+ %43 = fmul double %42, 0.000000e+00 ; <double> [#uses=1]
+ %44 = fsub double %34, %43 ; <double> [#uses=1]
+ %45 = tail call double @llvm.exp.f64(double %8) nounwind ; <double> [#uses=1]
+ %46 = fsub double -0.000000e+00, %45 ; <double> [#uses=2]
+ %47 = fdiv double %46, 0.000000e+00 ; <double> [#uses=1]
+ %48 = fmul double %30, %5 ; <double> [#uses=1]
+ %49 = fdiv double 0.000000e+00, %48 ; <double> [#uses=1]
+ %50 = fsub double %47, %49 ; <double> [#uses=1]
+ %51 = fmul double %50, -4.000000e+00 ; <double> [#uses=1]
+ %52 = fadd double %51, 0.000000e+00 ; <double> [#uses=1]
+ %53 = fdiv double %46, %11 ; <double> [#uses=1]
+ %54 = fsub double %53, 0.000000e+00 ; <double> [#uses=1]
+ %55 = fmul double %31, %54 ; <double> [#uses=1]
+ %56 = fadd double %52, %55 ; <double> [#uses=1]
+ %57 = fadd double %56, 0.000000e+00 ; <double> [#uses=1]
+ %58 = fadd double %44, %57 ; <double> [#uses=1]
+ %59 = fsub double %58, 0.000000e+00 ; <double> [#uses=1]
+ %60 = tail call double @llvm.exp.f64(double 0.000000e+00) nounwind ; <double> [#uses=1]
+ %61 = fsub double -0.000000e+00, %60 ; <double> [#uses=1]
+ %62 = fdiv double 0.000000e+00, -6.000000e+00 ; <double> [#uses=1]
+ %63 = fdiv double %61, %5 ; <double> [#uses=1]
+ %64 = fsub double 0.000000e+00, %63 ; <double> [#uses=1]
+ %65 = fmul double %62, %64 ; <double> [#uses=1]
+ %66 = fsub double 0.000000e+00, %65 ; <double> [#uses=1]
+ %67 = fsub double -0.000000e+00, 0.000000e+00 ; <double> [#uses=2]
+ %68 = tail call double @llvm.exp.f64(double %10) nounwind ; <double> [#uses=1]
+ %69 = fsub double -0.000000e+00, %68 ; <double> [#uses=2]
+ %70 = fdiv double %67, %.pn404 ; <double> [#uses=1]
+ %71 = fdiv double %69, %.pn402 ; <double> [#uses=1]
+ %72 = fsub double %70, %71 ; <double> [#uses=1]
+ %73 = fmul double %72, -5.000000e-01 ; <double> [#uses=1]
+ %74 = fdiv double %67, %4 ; <double> [#uses=1]
+ %75 = fdiv double %69, %5 ; <double> [#uses=1]
+ %76 = fsub double %74, %75 ; <double> [#uses=1]
+ %77 = fmul double %76, 0.000000e+00 ; <double> [#uses=1]
+ %78 = fadd double %73, %77 ; <double> [#uses=1]
+ %79 = fmul double 0.000000e+00, %78 ; <double> [#uses=1]
+ %80 = fadd double %66, %79 ; <double> [#uses=1]
+ %81 = fdiv double 0.000000e+00, %.pn404 ; <double> [#uses=1]
+ %82 = fdiv double 0.000000e+00, %.pn402 ; <double> [#uses=1]
+ %83 = fsub double %81, %82 ; <double> [#uses=1]
+ %84 = fmul double %83, -5.000000e-01 ; <double> [#uses=1]
+ %85 = fdiv double 0.000000e+00, %4 ; <double> [#uses=1]
+ %86 = fdiv double 0.000000e+00, %5 ; <double> [#uses=1]
+ %87 = fsub double %85, %86 ; <double> [#uses=1]
+ %88 = fmul double %87, 0.000000e+00 ; <double> [#uses=1]
+ %89 = fadd double %84, %88 ; <double> [#uses=1]
+ %90 = fmul double 0.000000e+00, %89 ; <double> [#uses=1]
+ %91 = fsub double %80, %90 ; <double> [#uses=1]
+ %92 = tail call double @llvm.exp.f64(double %8) nounwind ; <double> [#uses=1]
+ %93 = fsub double -0.000000e+00, %92 ; <double> [#uses=1]
+ %94 = tail call double @llvm.exp.f64(double %10) nounwind ; <double> [#uses=1]
+ %95 = fsub double -0.000000e+00, %94 ; <double> [#uses=3]
+ %96 = fdiv double %95, %.pn402 ; <double> [#uses=1]
+ %97 = fsub double 0.000000e+00, %96 ; <double> [#uses=1]
+ %98 = fmul double 0.000000e+00, %97 ; <double> [#uses=1]
+ %99 = fdiv double %93, %11 ; <double> [#uses=1]
+ %100 = fdiv double %95, %12 ; <double> [#uses=1]
+ %101 = fsub double %99, %100 ; <double> [#uses=1]
+ %102 = fsub double %98, %101 ; <double> [#uses=1]
+ %103 = fdiv double %95, %5 ; <double> [#uses=1]
+ %104 = fsub double 0.000000e+00, %103 ; <double> [#uses=1]
+ %105 = fmul double %18, %104 ; <double> [#uses=1]
+ %106 = fadd double %102, %105 ; <double> [#uses=1]
+ %107 = fmul double %106, %k.4 ; <double> [#uses=1]
+ %108 = fadd double %91, %107 ; <double> [#uses=1]
+ %109 = fsub double %108, 0.000000e+00 ; <double> [#uses=1]
+ %110 = tail call double @llvm.exp.f64(double %8) nounwind ; <double> [#uses=1]
+ %111 = fsub double -0.000000e+00, %110 ; <double> [#uses=2]
+ %112 = tail call double @llvm.exp.f64(double %10) nounwind ; <double> [#uses=1]
+ %113 = fsub double -0.000000e+00, %112 ; <double> [#uses=2]
+ %114 = fdiv double %111, %11 ; <double> [#uses=1]
+ %115 = fdiv double %113, %12 ; <double> [#uses=1]
+ %116 = fsub double %114, %115 ; <double> [#uses=1]
+ %117 = fmul double 0.000000e+00, %116 ; <double> [#uses=1]
+ %118 = fdiv double %111, %29 ; <double> [#uses=1]
+ %119 = fdiv double %113, %30 ; <double> [#uses=1]
+ %120 = fsub double %118, %119 ; <double> [#uses=1]
+ %121 = fsub double %117, %120 ; <double> [#uses=1]
+ %122 = fmul double %18, 0.000000e+00 ; <double> [#uses=1]
+ %123 = fadd double %121, %122 ; <double> [#uses=1]
+ %124 = fmul double %33, 0.000000e+00 ; <double> [#uses=1]
+ %125 = fadd double %123, %124 ; <double> [#uses=1]
+ %126 = fadd double %109, %125 ; <double> [#uses=1]
+ %127 = tail call double @llvm.exp.f64(double 0.000000e+00) nounwind ; <double> [#uses=1]
+ %128 = fsub double -0.000000e+00, %127 ; <double> [#uses=2]
+ %129 = fdiv double %128, %30 ; <double> [#uses=1]
+ %130 = fsub double 0.000000e+00, %129 ; <double> [#uses=1]
+ %131 = fsub double 0.000000e+00, %130 ; <double> [#uses=1]
+ %132 = fdiv double 0.000000e+00, %.pn404 ; <double> [#uses=1]
+ %133 = fsub double %132, 0.000000e+00 ; <double> [#uses=1]
+ %134 = fmul double %18, %133 ; <double> [#uses=1]
+ %135 = fadd double %131, %134 ; <double> [#uses=1]
+ %136 = fdiv double %128, %5 ; <double> [#uses=1]
+ %137 = fsub double 0.000000e+00, %136 ; <double> [#uses=1]
+ %138 = fmul double %33, %137 ; <double> [#uses=1]
+ %139 = fadd double %135, %138 ; <double> [#uses=1]
+ %140 = fsub double %126, %139 ; <double> [#uses=1]
+ %141 = fadd double %N1.0, %59 ; <double> [#uses=1]
+ %142 = fadd double %D1.0, %140 ; <double> [#uses=1]
+ br label %bb64
+
+bb64: ; preds = %bb62, %bb55
+ %N1.0.pn = phi double [ %141, %bb62 ], [ %N1.0, %bb55 ] ; <double> [#uses=1]
+ %D1.0.pn = phi double [ %142, %bb62 ], [ %D1.0, %bb55 ] ; <double> [#uses=1]
+ %x.1 = fdiv double %N1.0.pn, %D1.0.pn ; <double> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-03-07-SpillerBug.ll b/test/CodeGen/ARM/2009-03-07-SpillerBug.ll
new file mode 100644
index 0000000..0ec17ae
--- /dev/null
+++ b/test/CodeGen/ARM/2009-03-07-SpillerBug.ll
@@ -0,0 +1,78 @@
+; RUN: llc < %s -mtriple=armv6-apple-darwin9 -mattr=+vfp2
+; rdar://6653182
+
+ %struct.ggBRDF = type { i32 (...)** }
+ %struct.ggPoint2 = type { [2 x double] }
+ %struct.ggPoint3 = type { [3 x double] }
+ %struct.ggSpectrum = type { [8 x float] }
+ %struct.ggSphere = type { %struct.ggPoint3, double }
+ %struct.mrDiffuseAreaSphereLuminaire = type { %struct.mrSphere, %struct.ggSpectrum }
+ %struct.mrDiffuseCosineSphereLuminaire = type { %struct.mrDiffuseAreaSphereLuminaire }
+ %struct.mrSphere = type { %struct.ggBRDF, %struct.ggSphere }
+
+declare void @llvm.memcpy.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind
+
+declare double @llvm.sqrt.f64(double) nounwind readonly
+
+declare double @sin(double) nounwind readonly
+
+declare double @acos(double) nounwind readonly
+
+define i32 @_ZNK34mrDiffuseSolidAngleSphereLuminaire18selectVisiblePointERK8ggPoint3RK9ggVector3RK8ggPoint2dRS0_Rd(%struct.mrDiffuseCosineSphereLuminaire* nocapture %this, %struct.ggPoint3* nocapture %x, %struct.ggPoint3* nocapture %unnamed_arg, %struct.ggPoint2* nocapture %uv, double %unnamed_arg2, %struct.ggPoint3* nocapture %on_light, double* nocapture %invProb) nounwind {
+entry:
+ %0 = call double @llvm.sqrt.f64(double 0.000000e+00) nounwind ; <double> [#uses=4]
+ %1 = fcmp ult double 0.000000e+00, %0 ; <i1> [#uses=1]
+ br i1 %1, label %bb3, label %bb7
+
+bb3: ; preds = %entry
+ %2 = fdiv double 1.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ %3 = fmul double 0.000000e+00, %2 ; <double> [#uses=2]
+ %4 = call double @llvm.sqrt.f64(double 0.000000e+00) nounwind ; <double> [#uses=1]
+ %5 = fdiv double 1.000000e+00, %4 ; <double> [#uses=2]
+ %6 = fmul double %3, %5 ; <double> [#uses=2]
+ %7 = fmul double 0.000000e+00, %5 ; <double> [#uses=2]
+ %8 = fmul double %3, %7 ; <double> [#uses=1]
+ %9 = fsub double %8, 0.000000e+00 ; <double> [#uses=1]
+ %10 = fmul double 0.000000e+00, %6 ; <double> [#uses=1]
+ %11 = fsub double 0.000000e+00, %10 ; <double> [#uses=1]
+ %12 = fsub double -0.000000e+00, %11 ; <double> [#uses=1]
+ %13 = fmul double %0, %0 ; <double> [#uses=2]
+ %14 = fsub double %13, 0.000000e+00 ; <double> [#uses=1]
+ %15 = call double @llvm.sqrt.f64(double %14) ; <double> [#uses=1]
+ %16 = fmul double 0.000000e+00, %15 ; <double> [#uses=1]
+ %17 = fdiv double %16, %0 ; <double> [#uses=1]
+ %18 = fadd double 0.000000e+00, %17 ; <double> [#uses=1]
+ %19 = call double @acos(double %18) nounwind readonly ; <double> [#uses=1]
+ %20 = load double* null, align 4 ; <double> [#uses=1]
+ %21 = fmul double %20, 0x401921FB54442D18 ; <double> [#uses=1]
+ %22 = call double @sin(double %19) nounwind readonly ; <double> [#uses=2]
+ %23 = fmul double %22, 0.000000e+00 ; <double> [#uses=2]
+ %24 = fmul double %6, %23 ; <double> [#uses=1]
+ %25 = fmul double %7, %23 ; <double> [#uses=1]
+ %26 = call double @sin(double %21) nounwind readonly ; <double> [#uses=1]
+ %27 = fmul double %22, %26 ; <double> [#uses=2]
+ %28 = fmul double %9, %27 ; <double> [#uses=1]
+ %29 = fmul double %27, %12 ; <double> [#uses=1]
+ %30 = fadd double %24, %28 ; <double> [#uses=1]
+ %31 = fadd double 0.000000e+00, %29 ; <double> [#uses=1]
+ %32 = fadd double %25, 0.000000e+00 ; <double> [#uses=1]
+ %33 = fadd double %30, 0.000000e+00 ; <double> [#uses=1]
+ %34 = fadd double %31, 0.000000e+00 ; <double> [#uses=1]
+ %35 = fadd double %32, 0.000000e+00 ; <double> [#uses=1]
+ %36 = bitcast %struct.ggPoint3* %x to i8* ; <i8*> [#uses=1]
+ call void @llvm.memcpy.i32(i8* null, i8* %36, i32 24, i32 4) nounwind
+ store double %33, double* null, align 8
+ br i1 false, label %_Z20ggRaySphereIntersectRK6ggRay3RK8ggSphereddRd.exit, label %bb5.i.i.i
+
+bb5.i.i.i: ; preds = %bb3
+ unreachable
+
+_Z20ggRaySphereIntersectRK6ggRay3RK8ggSphereddRd.exit: ; preds = %bb3
+ %37 = fsub double %13, 0.000000e+00 ; <double> [#uses=0]
+ %38 = fsub double -0.000000e+00, %34 ; <double> [#uses=0]
+ %39 = fsub double -0.000000e+00, %35 ; <double> [#uses=0]
+ ret i32 1
+
+bb7: ; preds = %entry
+ ret i32 0
+}
diff --git a/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll b/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll
new file mode 100644
index 0000000..a1ce384
--- /dev/null
+++ b/test/CodeGen/ARM/2009-03-09-AddrModeBug.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=arm
+
+ %struct.hit_t = type { %struct.v_t, double }
+ %struct.node_t = type { %struct.hit_t, %struct.hit_t, i32 }
+ %struct.v_t = type { double, double, double }
+
+define fastcc %struct.node_t* @_ZL6createP6node_tii3v_tS1_d(%struct.node_t* %n, i32 %lvl, i32 %dist, i64 %c.0.0, i64 %c.0.1, i64 %c.0.2, i64 %d.0.0, i64 %d.0.1, i64 %d.0.2, double %r) nounwind {
+entry:
+ %0 = getelementptr %struct.node_t* %n, i32 0, i32 1 ; <%struct.hit_t*> [#uses=1]
+ %1 = bitcast %struct.hit_t* %0 to i256* ; <i256*> [#uses=1]
+ store i256 0, i256* %1, align 4
+ unreachable
+}
diff --git a/test/CodeGen/ARM/2009-04-06-AsmModifier.ll b/test/CodeGen/ARM/2009-04-06-AsmModifier.ll
new file mode 100644
index 0000000..3526722
--- /dev/null
+++ b/test/CodeGen/ARM/2009-04-06-AsmModifier.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=arm | grep {swi 107}
+
+define i32 @_swilseek(i32) nounwind {
+entry:
+ %ptr = alloca i32 ; <i32*> [#uses=2]
+ store i32 %0, i32* %ptr
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ store i32 0, i32* %retval
+ %res = alloca i32 ; <i32*> [#uses=0]
+ %fh = alloca i32 ; <i32*> [#uses=1]
+ %1 = load i32* %fh ; <i32> [#uses=1]
+ %2 = load i32* %ptr ; <i32> [#uses=1]
+ %3 = call i32 asm "mov r0, $2; mov r1, $3; swi ${1:a}; mov $0, r0", "=r,i,r,r,~{r0},~{r1}"(i32 107, i32 %1, i32 %2) nounwind ; <i32> [#uses=1]
+ store i32 %3, i32* %retval
+ br label %return
+
+return: ; preds = %entry
+ %4 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %4
+}
diff --git a/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll b/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll
new file mode 100644
index 0000000..f6b3d2c
--- /dev/null
+++ b/test/CodeGen/ARM/2009-04-08-AggregateAddr.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=arm
+; PR3795
+
+define fastcc void @_D3foo3fooFAriZv({ i32, { double, double }* } %d_arg, i32 %x_arg) {
+entry:
+ %d = alloca { i32, { double, double }* } ; <{ i32, { double, double }* }*> [#uses=2]
+ %x = alloca i32 ; <i32*> [#uses=2]
+ %b = alloca { double, double } ; <{ double, double }*> [#uses=1]
+ store { i32, { double, double }* } %d_arg, { i32, { double, double }* }* %d
+ store i32 %x_arg, i32* %x
+ %tmp = load i32* %x ; <i32> [#uses=1]
+ %tmp1 = getelementptr { i32, { double, double }* }* %d, i32 0, i32 1 ; <{ double, double }**> [#uses=1]
+ %.ptr = load { double, double }** %tmp1 ; <{ double, double }*> [#uses=1]
+ %tmp2 = getelementptr { double, double }* %.ptr, i32 %tmp ; <{ double, double }*> [#uses=1]
+ %tmp3 = load { double, double }* %tmp2 ; <{ double, double }> [#uses=1]
+ store { double, double } %tmp3, { double, double }* %b
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-04-08-FREM.ll b/test/CodeGen/ARM/2009-04-08-FREM.ll
new file mode 100644
index 0000000..99907fc
--- /dev/null
+++ b/test/CodeGen/ARM/2009-04-08-FREM.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=arm
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+ %rem_r = frem double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ %1 = call i32 (i8*, ...)* @printf(i8* null, double %rem_r) ; <i32> [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/ARM/2009-04-08-FloatUndef.ll b/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
new file mode 100644
index 0000000..05d2f26
--- /dev/null
+++ b/test/CodeGen/ARM/2009-04-08-FloatUndef.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=arm
+
+define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>* %CONST) {
+entry:
+ %input2 = load <4 x float>* null, align 16 ; <<4 x float>> [#uses=2]
+ %shuffle7 = shufflevector <4 x float> %input2, <4 x float> <float 0.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00>, <4 x i32> <i32 2, i32 2, i32 2, i32 2> ; <<4 x float>> [#uses=1]
+ %mul1 = fmul <4 x float> %shuffle7, zeroinitializer ; <<4 x float>> [#uses=1]
+ %add2 = fadd <4 x float> %mul1, %input2 ; <<4 x float>> [#uses=1]
+ store <4 x float> %add2, <4 x float>* null, align 16
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll b/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
new file mode 100644
index 0000000..deb092b
--- /dev/null
+++ b/test/CodeGen/ARM/2009-04-09-RegScavengerAsm.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=arm
+; PR3954
+
+define void @foo(...) nounwind {
+entry:
+ %rr = alloca i32 ; <i32*> [#uses=2]
+ %0 = load i32* %rr ; <i32> [#uses=1]
+ %1 = call i32 asm "nop", "=r,0"(i32 %0) nounwind ; <i32> [#uses=1]
+ store i32 %1, i32* %rr
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll b/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
new file mode 100644
index 0000000..670d204
--- /dev/null
+++ b/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=arm-linuxeabi-unknown-gnu -mattr=+v6
+; PR4166
+
+ %"byte[]" = type { i32, i8* }
+ %tango.time.Time.Time = type { i64 }
+
+define fastcc void @t() {
+entry:
+ %tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval null) ; <i1> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll b/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll
new file mode 100644
index 0000000..75610ff
--- /dev/null
+++ b/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=local
+; PR4100
[email protected] = external constant [30 x i8] ; <[30 x i8]*> [#uses=1]
+
+define i16 @fn16(i16 %arg0.0, <2 x i16> %arg1, i16 %arg2.0) nounwind {
+entry:
+ store <2 x i16> %arg1, <2 x i16>* null
+ %0 = call i32 (i8*, ...)* @printf(i8* getelementptr ([30 x i8]* @.str, i32 0, i32 0), i32 0) nounwind ; <i32> [#uses=0]
+ ret i16 0
+}
+
+declare i32 @printf(i8*, ...) nounwind
diff --git a/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll b/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll
new file mode 100644
index 0000000..7046fcc
--- /dev/null
+++ b/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=arm
+ %struct.List = type { %struct.List*, i32 }
+@Node5 = external constant %struct.List ; <%struct.List*> [#uses=1]
+@"\01LC" = external constant [7 x i8] ; <[7 x i8]*> [#uses=1]
+
+define i32 @main() nounwind {
+entry:
+ br label %bb
+
+bb: ; preds = %bb3, %entry
+ %CurL.02 = phi %struct.List* [ @Node5, %entry ], [ %2, %bb3 ] ; <%struct.List*> [#uses=1]
+ %PrevL.01 = phi %struct.List* [ null, %entry ], [ %CurL.02, %bb3 ] ; <%struct.List*> [#uses=1]
+ %0 = icmp eq %struct.List* %PrevL.01, null ; <i1> [#uses=1]
+ br i1 %0, label %bb3, label %bb1
+
+bb1: ; preds = %bb
+ br label %bb3
+
+bb3: ; preds = %bb1, %bb
+ %iftmp.0.0 = phi i32 [ 0, %bb1 ], [ -1, %bb ] ; <i32> [#uses=1]
+ %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([7 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 %iftmp.0.0) nounwind ; <i32> [#uses=0]
+ %2 = load %struct.List** null, align 4 ; <%struct.List*> [#uses=2]
+ %phitmp = icmp eq %struct.List* %2, null ; <i1> [#uses=1]
+ br i1 %phitmp, label %bb5, label %bb
+
+bb5: ; preds = %bb3
+ ret i32 0
+}
+
+declare i32 @printf(i8* nocapture, ...) nounwind
diff --git a/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll b/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll
new file mode 100644
index 0000000..1e2707f
--- /dev/null
+++ b/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+; RUN: llc < %s -march=thumb | FileCheck %s
+; PR4091
+
+define void @foo(i32 %i, i32* %p) nounwind {
+;CHECK: swp r2, r0, [r1]
+ %asmtmp = call i32 asm sideeffect "swp $0, $2, $3", "=&r,=*m,r,*m,~{memory}"(i32* %p, i32 %i, i32* %p) nounwind
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-06-02-ISelCrash.ll b/test/CodeGen/ARM/2009-06-02-ISelCrash.ll
new file mode 100644
index 0000000..403e3f65
--- /dev/null
+++ b/test/CodeGen/ARM/2009-06-02-ISelCrash.ll
@@ -0,0 +1,62 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -mattr=+v6,+vfp2
+
+@"\01LC" = external constant [15 x i8] ; <[15 x i8]*> [#uses=1]
+
+declare i32 @printf(i8* nocapture, ...) nounwind
+
+define i32 @main() nounwind {
+entry:
+ br label %bb.i1.i
+
+bb.i1.i: ; preds = %Cos.exit.i.i, %entry
+ br label %bb.i.i.i
+
+bb.i.i.i: ; preds = %bb.i.i.i, %bb.i1.i
+ br i1 undef, label %Cos.exit.i.i, label %bb.i.i.i
+
+Cos.exit.i.i: ; preds = %bb.i.i.i
+ br i1 undef, label %bb2.i.i, label %bb.i1.i
+
+bb2.i.i: ; preds = %Cos.exit.i.i
+ br label %bb3.i.i
+
+bb3.i.i: ; preds = %bb5.i.i, %bb2.i.i
+ br label %bb4.i.i
+
+bb4.i.i: ; preds = %bb4.i.i, %bb3.i.i
+ br i1 undef, label %bb5.i.i, label %bb4.i.i
+
+bb5.i.i: ; preds = %bb4.i.i
+ br i1 undef, label %bb.i, label %bb3.i.i
+
+bb.i: ; preds = %bb.i, %bb5.i.i
+ br i1 undef, label %bb1.outer2.i.i.outer, label %bb.i
+
+bb1.outer2.i.i.outer: ; preds = %Fft.exit.i, %bb5.i12.i, %bb.i
+ br label %bb1.outer2.i.i
+
+bb1.outer2.i.i: ; preds = %bb2.i9.i, %bb1.outer2.i.i.outer
+ br label %bb1.i.i
+
+bb1.i.i: ; preds = %bb1.i.i, %bb1.outer2.i.i
+ br i1 undef, label %bb2.i9.i, label %bb1.i.i
+
+bb2.i9.i: ; preds = %bb1.i.i
+ br i1 undef, label %bb4.i11.i, label %bb1.outer2.i.i
+
+bb4.i11.i: ; preds = %bb4.i11.i, %bb2.i9.i
+ br i1 undef, label %bb5.i12.i, label %bb4.i11.i
+
+bb5.i12.i: ; preds = %bb4.i11.i
+ br i1 undef, label %bb7.i.i, label %bb1.outer2.i.i.outer
+
+bb7.i.i: ; preds = %bb7.i.i, %bb5.i12.i
+ br i1 undef, label %Fft.exit.i, label %bb7.i.i
+
+Fft.exit.i: ; preds = %bb7.i.i
+ br i1 undef, label %bb5.i, label %bb1.outer2.i.i.outer
+
+bb5.i: ; preds = %Fft.exit.i
+ %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([15 x i8]* @"\01LC", i32 0, i32 0), double undef, double undef) nounwind ; <i32> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll b/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll
new file mode 100644
index 0000000..98e0023
--- /dev/null
+++ b/test/CodeGen/ARM/2009-06-04-MissingLiveIn.ll
@@ -0,0 +1,263 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6
+
+ %struct.anon = type { i16, i16 }
+ %struct.cab_archive = type { i32, i16, i16, i16, i16, i8, %struct.cab_folder*, %struct.cab_file* }
+ %struct.cab_file = type { i32, i16, i64, i8*, i32, i32, i32, %struct.cab_folder*, %struct.cab_file*, %struct.cab_archive*, %struct.cab_state* }
+ %struct.cab_folder = type { i16, i16, %struct.cab_archive*, i64, %struct.cab_folder* }
+ %struct.cab_state = type { i8*, i8*, [38912 x i8], i16, i16, i8*, i16 }
+ %struct.qtm_model = type { i32, i32, %struct.anon* }
+ %struct.qtm_stream = type { i32, i32, i8, i8*, i32, i32, i32, i16, i16, i16, i8, i32, i8*, i8*, i8*, i8*, i8*, i32, i32, i8, [42 x i32], [42 x i8], [27 x i8], [27 x i8], %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, %struct.qtm_model, [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [65 x %struct.anon], [25 x %struct.anon], [37 x %struct.anon], [43 x %struct.anon], [28 x %struct.anon], [8 x %struct.anon], %struct.cab_file*, i32 (%struct.cab_file*, i8*, i32)* }
+
+declare fastcc i32 @qtm_read_input(%struct.qtm_stream* nocapture) nounwind
+
+define fastcc i32 @qtm_decompress(%struct.qtm_stream* %qtm, i64 %out_bytes) nounwind {
+entry:
+ br i1 undef, label %bb245, label %bb3
+
+bb3: ; preds = %entry
+ br i1 undef, label %bb5, label %bb4
+
+bb4: ; preds = %bb3
+ ret i32 undef
+
+bb5: ; preds = %bb3
+ br i1 undef, label %bb245, label %bb14
+
+bb14: ; preds = %bb5
+ br label %bb238
+
+bb28: ; preds = %bb215
+ br label %bb31
+
+bb29: ; preds = %bb31
+ br i1 undef, label %bb31, label %bb32
+
+bb31: ; preds = %bb29, %bb28
+ br i1 undef, label %bb29, label %bb32
+
+bb32: ; preds = %bb31, %bb29
+ br label %bb33
+
+bb33: ; preds = %bb33, %bb32
+ br i1 undef, label %bb34, label %bb33
+
+bb34: ; preds = %bb33
+ br i1 undef, label %bb35, label %bb36
+
+bb35: ; preds = %bb34
+ br label %bb36
+
+bb36: ; preds = %bb46, %bb35, %bb34
+ br i1 undef, label %bb40, label %bb37
+
+bb37: ; preds = %bb36
+ br i1 undef, label %bb77, label %bb60
+
+bb40: ; preds = %bb36
+ br i1 undef, label %bb46, label %bb41
+
+bb41: ; preds = %bb40
+ br i1 undef, label %bb45, label %bb42
+
+bb42: ; preds = %bb41
+ ret i32 undef
+
+bb45: ; preds = %bb41
+ br label %bb46
+
+bb46: ; preds = %bb45, %bb40
+ br label %bb36
+
+bb60: ; preds = %bb60, %bb37
+ br label %bb60
+
+bb77: ; preds = %bb37
+ switch i32 undef, label %bb197 [
+ i32 5, label %bb108
+ i32 6, label %bb138
+ ]
+
+bb108: ; preds = %bb77
+ br label %bb111
+
+bb109: ; preds = %bb111
+ br i1 undef, label %bb111, label %bb112
+
+bb111: ; preds = %bb109, %bb108
+ br i1 undef, label %bb109, label %bb112
+
+bb112: ; preds = %bb111, %bb109
+ br label %bb113
+
+bb113: ; preds = %bb113, %bb112
+ br i1 undef, label %bb114, label %bb113
+
+bb114: ; preds = %bb113
+ br i1 undef, label %bb115, label %bb116
+
+bb115: ; preds = %bb114
+ br label %bb116
+
+bb116: ; preds = %bb115, %bb114
+ br i1 undef, label %bb120, label %bb117
+
+bb117: ; preds = %bb116
+ br label %bb136
+
+bb120: ; preds = %bb116
+ ret i32 undef
+
+bb128: ; preds = %bb136
+ br i1 undef, label %bb134, label %bb129
+
+bb129: ; preds = %bb128
+ br i1 undef, label %bb133, label %bb130
+
+bb130: ; preds = %bb129
+ br i1 undef, label %bb132, label %bb131
+
+bb131: ; preds = %bb130
+ ret i32 undef
+
+bb132: ; preds = %bb130
+ br label %bb133
+
+bb133: ; preds = %bb132, %bb129
+ br label %bb134
+
+bb134: ; preds = %bb133, %bb128
+ br label %bb136
+
+bb136: ; preds = %bb134, %bb117
+ br i1 undef, label %bb198, label %bb128
+
+bb138: ; preds = %bb77
+ %0 = trunc i32 undef to i16 ; <i16> [#uses=1]
+ br label %bb141
+
+bb139: ; preds = %bb141
+ %scevgep441442881 = load i16* undef ; <i16> [#uses=1]
+ %1 = icmp ugt i16 %scevgep441442881, %0 ; <i1> [#uses=1]
+ br i1 %1, label %bb141, label %bb142
+
+bb141: ; preds = %bb139, %bb138
+ br i1 undef, label %bb139, label %bb142
+
+bb142: ; preds = %bb141, %bb139
+ br label %bb143
+
+bb143: ; preds = %bb143, %bb142
+ br i1 undef, label %bb144, label %bb143
+
+bb144: ; preds = %bb143
+ br i1 undef, label %bb145, label %bb146
+
+bb145: ; preds = %bb144
+ unreachable
+
+bb146: ; preds = %bb156, %bb144
+ br i1 undef, label %bb150, label %bb147
+
+bb147: ; preds = %bb146
+ br i1 undef, label %bb157, label %bb148
+
+bb148: ; preds = %bb147
+ br i1 undef, label %bb149, label %bb157
+
+bb149: ; preds = %bb148
+ br label %bb150
+
+bb150: ; preds = %bb149, %bb146
+ br i1 undef, label %bb156, label %bb152
+
+bb152: ; preds = %bb150
+ unreachable
+
+bb156: ; preds = %bb150
+ br label %bb146
+
+bb157: ; preds = %bb148, %bb147
+ br i1 undef, label %bb167, label %bb160
+
+bb160: ; preds = %bb157
+ ret i32 undef
+
+bb167: ; preds = %bb157
+ br label %bb170
+
+bb168: ; preds = %bb170
+ br i1 undef, label %bb170, label %bb171
+
+bb170: ; preds = %bb168, %bb167
+ br i1 undef, label %bb168, label %bb171
+
+bb171: ; preds = %bb170, %bb168
+ br label %bb172
+
+bb172: ; preds = %bb172, %bb171
+ br i1 undef, label %bb173, label %bb172
+
+bb173: ; preds = %bb172
+ br i1 undef, label %bb174, label %bb175
+
+bb174: ; preds = %bb173
+ unreachable
+
+bb175: ; preds = %bb179, %bb173
+ br i1 undef, label %bb179, label %bb176
+
+bb176: ; preds = %bb175
+ br i1 undef, label %bb186, label %bb177
+
+bb177: ; preds = %bb176
+ br i1 undef, label %bb178, label %bb186
+
+bb178: ; preds = %bb177
+ br label %bb179
+
+bb179: ; preds = %bb178, %bb175
+ br label %bb175
+
+bb186: ; preds = %bb177, %bb176
+ br label %bb195
+
+bb187: ; preds = %bb195
+ br i1 undef, label %bb193, label %bb189
+
+bb189: ; preds = %bb187
+ %2 = tail call fastcc i32 @qtm_read_input(%struct.qtm_stream* %qtm) nounwind ; <i32> [#uses=0]
+ ret i32 undef
+
+bb193: ; preds = %bb187
+ br label %bb195
+
+bb195: ; preds = %bb193, %bb186
+ br i1 undef, label %bb198, label %bb187
+
+bb197: ; preds = %bb77
+ ret i32 -124
+
+bb198: ; preds = %bb195, %bb136
+ br i1 undef, label %bb211.preheader, label %bb214
+
+bb211.preheader: ; preds = %bb198
+ br label %bb211
+
+bb211: ; preds = %bb211, %bb211.preheader
+ br i1 undef, label %bb214, label %bb211
+
+bb214: ; preds = %bb211, %bb198
+ br label %bb215
+
+bb215: ; preds = %bb238, %bb214
+ br i1 undef, label %bb28, label %bb216
+
+bb216: ; preds = %bb215
+ br label %bb238
+
+bb238: ; preds = %bb216, %bb14
+ br label %bb215
+
+bb245: ; preds = %bb5, %entry
+ ret i32 undef
+}
diff --git a/test/CodeGen/ARM/2009-06-12-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-06-12-RegScavengerAssert.ll
new file mode 100644
index 0000000..27888d7
--- /dev/null
+++ b/test/CodeGen/ARM/2009-06-12-RegScavengerAssert.ll
@@ -0,0 +1,77 @@
+; RUN: llc < %s -mtriple=armv6-apple-darwin
+
+ type { i32, i32, %struct.D_Sym**, [3 x %struct.D_Sym*] } ; type %0
+ type { i32, %struct.D_Reduction** } ; type %1
+ type { i32, %struct.D_RightEpsilonHint* } ; type %2
+ type { i32, %struct.D_ErrorRecoveryHint* } ; type %3
+ type { i32, i32, %struct.D_Reduction**, [3 x %struct.D_Reduction*] } ; type %4
+ %struct.D_ErrorRecoveryHint = type { i16, i16, i8* }
+ %struct.D_ParseNode = type { i32, %struct.d_loc_t, i8*, i8*, %struct.D_Scope*, void (%struct.D_Parser*, %struct.d_loc_t*, i8**)*, i8*, i8* }
+ %struct.D_Parser = type { i8*, void (%struct.D_Parser*, %struct.d_loc_t*, i8**)*, %struct.D_Scope*, void (%struct.D_Parser*)*, %struct.D_ParseNode* (%struct.D_Parser*, i32, %struct.D_ParseNode**)*, void (%struct.D_ParseNode*)*, %struct.d_loc_t, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.D_ParserTables = type { i32, %struct.D_State*, i16*, i32, i32, %struct.D_Symbol*, void (%struct.D_Parser*, %struct.d_loc_t*, i8**)*, i32, %struct.D_Pass*, i32 }
+ %struct.D_Pass = type { i8*, i32, i32, i32 }
+ %struct.D_Reduction = type { i16, i16, i32 (i8*, i8**, i32, i32, %struct.D_Parser*)*, i32 (i8*, i8**, i32, i32, %struct.D_Parser*)*, i16, i16, i32, i32, i32, i32, i32 (i8*, i8**, i32, i32, %struct.D_Parser*)** }
+ %struct.D_RightEpsilonHint = type { i16, i16, %struct.D_Reduction* }
+ %struct.D_Scope = type { i8, %struct.D_Sym*, %struct.D_SymHash*, %struct.D_Sym*, %struct.D_Scope*, %struct.D_Scope*, %struct.D_Scope*, %struct.D_Scope*, %struct.D_Scope* }
+ %struct.D_Shift = type { i16, i8, i8, i32, i32, i32 (i8*, i8**, i32, i32, %struct.D_Parser*)* }
+ %struct.D_State = type { i8*, i32, %1, %2, %3, %struct.D_Shift**, i32 (i8**, i32*, i32*, i16*, i32*, i8*, i32*)*, i8*, i8, i8, i8, i8*, %struct.D_Shift***, i32 }
+ %struct.D_Sym = type { i8*, i32, i32, %struct.D_Sym*, %struct.D_Sym*, i32 }
+ %struct.D_SymHash = type { i32, i32, %0 }
+ %struct.D_Symbol = type { i32, i8*, i32 }
+ %struct.PNode = type { i32, i32, i32, i32, %struct.D_Reduction*, %struct.D_Shift*, i32, %struct.VecPNode, i32, i8, i8, %struct.PNode*, %struct.PNode*, %struct.PNode*, %struct.PNode*, i8*, i8*, %struct.D_Scope*, i8*, %struct.D_ParseNode }
+ %struct.PNodeHash = type { %struct.PNode**, i32, i32, i32, %struct.PNode* }
+ %struct.Parser = type { %struct.D_Parser, i8*, i8*, %struct.D_ParserTables*, i32, i32, i32, i32, i32, i32, i32, %struct.PNodeHash, %struct.SNodeHash, %struct.Reduction*, %struct.Shift*, %struct.D_Scope*, %struct.SNode*, i32, %struct.Reduction*, %struct.Shift*, i32, %struct.PNode*, %struct.SNode*, %struct.ZNode*, %4, %struct.ShiftResult*, %struct.D_Shift, %struct.Parser*, i8* }
+ %struct.Reduction = type { %struct.ZNode*, %struct.SNode*, %struct.D_Reduction*, %struct.SNode*, i32, %struct.Reduction* }
+ %struct.SNode = type { %struct.D_State*, %struct.D_Scope*, i8*, %struct.d_loc_t, i32, %struct.PNode*, %struct.VecZNode, i32, %struct.SNode*, %struct.SNode* }
+ %struct.SNodeHash = type { %struct.SNode**, i32, i32, i32, %struct.SNode*, %struct.SNode* }
+ %struct.Shift = type { %struct.SNode*, %struct.Shift* }
+ %struct.ShiftResult = type { %struct.D_Shift*, %struct.d_loc_t }
+ %struct.VecPNode = type { i32, i32, %struct.PNode**, [3 x %struct.PNode*] }
+ %struct.VecSNode = type { i32, i32, %struct.SNode**, [3 x %struct.SNode*] }
+ %struct.VecZNode = type { i32, i32, %struct.ZNode**, [3 x %struct.ZNode*] }
+ %struct.ZNode = type { %struct.PNode*, %struct.VecSNode }
+ %struct.d_loc_t = type { i8*, i8*, i32, i32, i32 }
+
+declare void @llvm.memcpy.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind
+
+define fastcc i32 @exhaustive_parse(%struct.Parser* %p, i32 %state) nounwind {
+entry:
+ store i8* undef, i8** undef, align 4
+ %0 = getelementptr %struct.Parser* %p, i32 0, i32 0, i32 6 ; <%struct.d_loc_t*> [#uses=1]
+ %1 = bitcast %struct.d_loc_t* %0 to i8* ; <i8*> [#uses=1]
+ call void @llvm.memcpy.i32(i8* undef, i8* %1, i32 20, i32 4)
+ br label %bb10
+
+bb10: ; preds = %bb30, %bb29, %bb26, %entry
+ br i1 undef, label %bb18, label %bb20
+
+bb18: ; preds = %bb10
+ br i1 undef, label %bb20, label %bb19
+
+bb19: ; preds = %bb18
+ br label %bb20
+
+bb20: ; preds = %bb19, %bb18, %bb10
+ br i1 undef, label %bb21, label %bb22
+
+bb21: ; preds = %bb20
+ unreachable
+
+bb22: ; preds = %bb20
+ br i1 undef, label %bb24, label %bb26
+
+bb24: ; preds = %bb22
+ unreachable
+
+bb26: ; preds = %bb22
+ br i1 undef, label %bb10, label %bb29
+
+bb29: ; preds = %bb26
+ br i1 undef, label %bb10, label %bb30
+
+bb30: ; preds = %bb29
+ br i1 undef, label %bb31, label %bb10
+
+bb31: ; preds = %bb30
+ unreachable
+}
diff --git a/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll
new file mode 100644
index 0000000..a0f903b
--- /dev/null
+++ b/test/CodeGen/ARM/2009-06-15-RegScavengerAssert.ll
@@ -0,0 +1,344 @@
+; RUN: llc < %s -mtriple=armv6-apple-darwin
+
+ %struct.term = type { i32, i32, i32 }
+
+declare fastcc i8* @memory_Malloc(i32) nounwind
+
+define fastcc %struct.term* @t1() nounwind {
+entry:
+ br i1 undef, label %bb, label %bb1
+
+bb: ; preds = %entry
+ ret %struct.term* undef
+
+bb1: ; preds = %entry
+ %0 = tail call fastcc i8* @memory_Malloc(i32 12) nounwind ; <i8*> [#uses=0]
+ %1 = tail call fastcc i8* @memory_Malloc(i32 12) nounwind ; <i8*> [#uses=0]
+ ret %struct.term* undef
+}
+
+
+define i32 @t2(i32 %argc, i8** nocapture %argv) nounwind {
+entry:
+ br label %bb6.i8
+
+bb6.i8: ; preds = %memory_CalculateRealBlockSize1374.exit.i, %entry
+ br i1 undef, label %memory_CalculateRealBlockSize1374.exit.i, label %bb.i.i9
+
+bb.i.i9: ; preds = %bb6.i8
+ br label %memory_CalculateRealBlockSize1374.exit.i
+
+memory_CalculateRealBlockSize1374.exit.i: ; preds = %bb.i.i9, %bb6.i8
+ %0 = phi i32 [ undef, %bb.i.i9 ], [ undef, %bb6.i8 ] ; <i32> [#uses=2]
+ store i32 %0, i32* undef, align 4
+ %1 = urem i32 8184, %0 ; <i32> [#uses=1]
+ %2 = sub i32 8188, %1 ; <i32> [#uses=1]
+ store i32 %2, i32* undef, align 4
+ br i1 undef, label %memory_Init.exit, label %bb6.i8
+
+memory_Init.exit: ; preds = %memory_CalculateRealBlockSize1374.exit.i
+ br label %bb.i.i
+
+bb.i.i: ; preds = %bb.i.i, %memory_Init.exit
+ br i1 undef, label %symbol_Init.exit, label %bb.i.i
+
+symbol_Init.exit: ; preds = %bb.i.i
+ br label %bb.i.i67
+
+bb.i.i67: ; preds = %bb.i.i67, %symbol_Init.exit
+ br i1 undef, label %symbol_CreatePrecedence3522.exit, label %bb.i.i67
+
+symbol_CreatePrecedence3522.exit: ; preds = %bb.i.i67
+ br label %bb.i.i8.i
+
+bb.i.i8.i: ; preds = %bb.i.i8.i, %symbol_CreatePrecedence3522.exit
+ br i1 undef, label %cont_Create.exit9.i, label %bb.i.i8.i
+
+cont_Create.exit9.i: ; preds = %bb.i.i8.i
+ br label %bb.i.i.i72
+
+bb.i.i.i72: ; preds = %bb.i.i.i72, %cont_Create.exit9.i
+ br i1 undef, label %cont_Init.exit, label %bb.i.i.i72
+
+cont_Init.exit: ; preds = %bb.i.i.i72
+ br label %bb.i103
+
+bb.i103: ; preds = %bb.i103, %cont_Init.exit
+ br i1 undef, label %subs_Init.exit, label %bb.i103
+
+subs_Init.exit: ; preds = %bb.i103
+ br i1 undef, label %bb1.i.i.i80, label %cc_Init.exit
+
+bb1.i.i.i80: ; preds = %subs_Init.exit
+ unreachable
+
+cc_Init.exit: ; preds = %subs_Init.exit
+ br label %bb.i.i375
+
+bb.i.i375: ; preds = %bb.i.i375, %cc_Init.exit
+ br i1 undef, label %bb.i439, label %bb.i.i375
+
+bb.i439: ; preds = %bb.i439, %bb.i.i375
+ br i1 undef, label %opts_DeclareSPASSFlagsAsOptions.exit, label %bb.i439
+
+opts_DeclareSPASSFlagsAsOptions.exit: ; preds = %bb.i439
+ br i1 undef, label %opts_TranslateShortOptDeclarations.exit.i, label %bb.i.i82
+
+bb.i.i82: ; preds = %opts_DeclareSPASSFlagsAsOptions.exit
+ unreachable
+
+opts_TranslateShortOptDeclarations.exit.i: ; preds = %opts_DeclareSPASSFlagsAsOptions.exit
+ br i1 undef, label %list_Length.exit.i.thread.i, label %bb.i.i4.i
+
+list_Length.exit.i.thread.i: ; preds = %opts_TranslateShortOptDeclarations.exit.i
+ br i1 undef, label %bb18.i.i.i, label %bb26.i.i.i
+
+bb.i.i4.i: ; preds = %opts_TranslateShortOptDeclarations.exit.i
+ unreachable
+
+bb18.i.i.i: ; preds = %list_Length.exit.i.thread.i
+ unreachable
+
+bb26.i.i.i: ; preds = %list_Length.exit.i.thread.i
+ br i1 undef, label %bb27.i142, label %opts_GetOptLongOnly.exit.thread97.i
+
+opts_GetOptLongOnly.exit.thread97.i: ; preds = %bb26.i.i.i
+ br label %bb27.i142
+
+bb27.i142: ; preds = %opts_GetOptLongOnly.exit.thread97.i, %bb26.i.i.i
+ br label %bb1.i3.i
+
+bb1.i3.i: ; preds = %bb1.i3.i, %bb27.i142
+ br i1 undef, label %opts_FreeLongOptsArray.exit.i, label %bb1.i3.i
+
+opts_FreeLongOptsArray.exit.i: ; preds = %bb1.i3.i
+ br label %bb.i443
+
+bb.i443: ; preds = %bb.i443, %opts_FreeLongOptsArray.exit.i
+ br i1 undef, label %flag_InitStoreByDefaults3542.exit, label %bb.i443
+
+flag_InitStoreByDefaults3542.exit: ; preds = %bb.i443
+ br i1 undef, label %bb6.i449, label %bb.i503
+
+bb6.i449: ; preds = %flag_InitStoreByDefaults3542.exit
+ unreachable
+
+bb.i503: ; preds = %bb.i503, %flag_InitStoreByDefaults3542.exit
+ br i1 undef, label %flag_CleanStore3464.exit, label %bb.i503
+
+flag_CleanStore3464.exit: ; preds = %bb.i503
+ br i1 undef, label %bb1.i81.i.preheader, label %bb.i173
+
+bb.i173: ; preds = %flag_CleanStore3464.exit
+ unreachable
+
+bb1.i81.i.preheader: ; preds = %flag_CleanStore3464.exit
+ br i1 undef, label %bb1.i64.i.preheader, label %bb5.i179
+
+bb5.i179: ; preds = %bb1.i81.i.preheader
+ unreachable
+
+bb1.i64.i.preheader: ; preds = %bb1.i81.i.preheader
+ br i1 undef, label %dfg_DeleteProofList.exit.i, label %bb.i9.i
+
+bb.i9.i: ; preds = %bb1.i64.i.preheader
+ unreachable
+
+dfg_DeleteProofList.exit.i: ; preds = %bb1.i64.i.preheader
+ br i1 undef, label %term_DeleteTermList621.exit.i, label %bb.i.i62.i
+
+bb.i.i62.i: ; preds = %bb.i.i62.i, %dfg_DeleteProofList.exit.i
+ br i1 undef, label %term_DeleteTermList621.exit.i, label %bb.i.i62.i
+
+term_DeleteTermList621.exit.i: ; preds = %bb.i.i62.i, %dfg_DeleteProofList.exit.i
+ br i1 undef, label %dfg_DFGParser.exit, label %bb.i.i211
+
+bb.i.i211: ; preds = %term_DeleteTermList621.exit.i
+ unreachable
+
+dfg_DFGParser.exit: ; preds = %term_DeleteTermList621.exit.i
+ br label %bb.i513
+
+bb.i513: ; preds = %bb2.i516, %dfg_DFGParser.exit
+ br i1 undef, label %bb2.i516, label %bb1.i514
+
+bb1.i514: ; preds = %bb.i513
+ unreachable
+
+bb2.i516: ; preds = %bb.i513
+ br i1 undef, label %bb.i509, label %bb.i513
+
+bb.i509: ; preds = %bb.i509, %bb2.i516
+ br i1 undef, label %symbol_TransferPrecedence3468.exit511, label %bb.i509
+
+symbol_TransferPrecedence3468.exit511: ; preds = %bb.i509
+ br i1 undef, label %bb20, label %bb21
+
+bb20: ; preds = %symbol_TransferPrecedence3468.exit511
+ unreachable
+
+bb21: ; preds = %symbol_TransferPrecedence3468.exit511
+ br i1 undef, label %cnf_Init.exit, label %bb.i498
+
+bb.i498: ; preds = %bb21
+ unreachable
+
+cnf_Init.exit: ; preds = %bb21
+ br i1 undef, label %bb23, label %bb22
+
+bb22: ; preds = %cnf_Init.exit
+ br i1 undef, label %bb2.i.i496, label %bb.i.i494
+
+bb.i.i494: ; preds = %bb22
+ unreachable
+
+bb2.i.i496: ; preds = %bb22
+ unreachable
+
+bb23: ; preds = %cnf_Init.exit
+ br i1 undef, label %bb28, label %bb24
+
+bb24: ; preds = %bb23
+ unreachable
+
+bb28: ; preds = %bb23
+ br i1 undef, label %bb31, label %bb29
+
+bb29: ; preds = %bb28
+ unreachable
+
+bb31: ; preds = %bb28
+ br i1 undef, label %bb34, label %bb32
+
+bb32: ; preds = %bb31
+ unreachable
+
+bb34: ; preds = %bb31
+ br i1 undef, label %bb83, label %bb66
+
+bb66: ; preds = %bb34
+ unreachable
+
+bb83: ; preds = %bb34
+ br i1 undef, label %bb2.i1668, label %bb.i1667
+
+bb.i1667: ; preds = %bb83
+ unreachable
+
+bb2.i1668: ; preds = %bb83
+ br i1 undef, label %bb5.i205, label %bb3.i204
+
+bb3.i204: ; preds = %bb2.i1668
+ unreachable
+
+bb5.i205: ; preds = %bb2.i1668
+ br i1 undef, label %bb.i206.i, label %ana_AnalyzeSortStructure.exit.i
+
+bb.i206.i: ; preds = %bb5.i205
+ br i1 undef, label %bb1.i207.i, label %ana_AnalyzeSortStructure.exit.i
+
+bb1.i207.i: ; preds = %bb.i206.i
+ br i1 undef, label %bb25.i1801.thread, label %bb.i1688
+
+bb.i1688: ; preds = %bb1.i207.i
+ unreachable
+
+bb25.i1801.thread: ; preds = %bb1.i207.i
+ unreachable
+
+ana_AnalyzeSortStructure.exit.i: ; preds = %bb.i206.i, %bb5.i205
+ br i1 undef, label %bb7.i207, label %bb.i1806
+
+bb.i1806: ; preds = %ana_AnalyzeSortStructure.exit.i
+ br i1 undef, label %bb2.i.i.i1811, label %bb.i.i.i1809
+
+bb.i.i.i1809: ; preds = %bb.i1806
+ unreachable
+
+bb2.i.i.i1811: ; preds = %bb.i1806
+ unreachable
+
+bb7.i207: ; preds = %ana_AnalyzeSortStructure.exit.i
+ br i1 undef, label %bb9.i, label %bb8.i
+
+bb8.i: ; preds = %bb7.i207
+ unreachable
+
+bb9.i: ; preds = %bb7.i207
+ br i1 undef, label %bb23.i, label %bb26.i
+
+bb23.i: ; preds = %bb9.i
+ br i1 undef, label %bb25.i, label %bb24.i
+
+bb24.i: ; preds = %bb23.i
+ br i1 undef, label %sort_SortTheoryIsTrivial.exit.i, label %bb.i2093
+
+bb.i2093: ; preds = %bb.i2093, %bb24.i
+ br label %bb.i2093
+
+sort_SortTheoryIsTrivial.exit.i: ; preds = %bb24.i
+ br i1 undef, label %bb3.i2141, label %bb4.i2143
+
+bb3.i2141: ; preds = %sort_SortTheoryIsTrivial.exit.i
+ unreachable
+
+bb4.i2143: ; preds = %sort_SortTheoryIsTrivial.exit.i
+ br i1 undef, label %bb8.i2178, label %bb5.i2144
+
+bb5.i2144: ; preds = %bb4.i2143
+ br i1 undef, label %bb7.i2177, label %bb1.i28.i
+
+bb1.i28.i: ; preds = %bb5.i2144
+ br i1 undef, label %bb4.i43.i, label %bb2.i.i2153
+
+bb2.i.i2153: ; preds = %bb1.i28.i
+ br i1 undef, label %bb4.i.i33.i, label %bb.i.i30.i
+
+bb.i.i30.i: ; preds = %bb2.i.i2153
+ unreachable
+
+bb4.i.i33.i: ; preds = %bb2.i.i2153
+ br i1 undef, label %bb9.i.i36.i, label %bb5.i.i34.i
+
+bb5.i.i34.i: ; preds = %bb4.i.i33.i
+ unreachable
+
+bb9.i.i36.i: ; preds = %bb4.i.i33.i
+ br i1 undef, label %bb14.i.i.i2163, label %bb10.i.i37.i
+
+bb10.i.i37.i: ; preds = %bb9.i.i36.i
+ unreachable
+
+bb14.i.i.i2163: ; preds = %bb9.i.i36.i
+ br i1 undef, label %sort_LinkPrint.exit.i.i, label %bb15.i.i.i2164
+
+bb15.i.i.i2164: ; preds = %bb14.i.i.i2163
+ unreachable
+
+sort_LinkPrint.exit.i.i: ; preds = %bb14.i.i.i2163
+ unreachable
+
+bb4.i43.i: ; preds = %bb1.i28.i
+ unreachable
+
+bb7.i2177: ; preds = %bb5.i2144
+ unreachable
+
+bb8.i2178: ; preds = %bb4.i2143
+ br i1 undef, label %sort_ApproxStaticSortTheory.exit, label %bb.i5.i2185.preheader
+
+bb.i5.i2185.preheader: ; preds = %bb8.i2178
+ br label %bb.i5.i2185
+
+bb.i5.i2185: ; preds = %bb.i5.i2185, %bb.i5.i2185.preheader
+ br i1 undef, label %sort_ApproxStaticSortTheory.exit, label %bb.i5.i2185
+
+sort_ApproxStaticSortTheory.exit: ; preds = %bb.i5.i2185, %bb8.i2178
+ br label %bb25.i
+
+bb25.i: ; preds = %sort_ApproxStaticSortTheory.exit, %bb23.i
+ unreachable
+
+bb26.i: ; preds = %bb9.i
+ unreachable
+}
diff --git a/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll
new file mode 100644
index 0000000..b56b684
--- /dev/null
+++ b/test/CodeGen/ARM/2009-06-19-RegScavengerAssert.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -mtriple=armv6-eabi -mattr=+vfp2 -float-abi=hard
+; PR4419
+
+define float @__ieee754_acosf(float %x) nounwind {
+entry:
+ br i1 undef, label %bb, label %bb4
+
+bb: ; preds = %entry
+ ret float undef
+
+bb4: ; preds = %entry
+ br i1 undef, label %bb5, label %bb6
+
+bb5: ; preds = %bb4
+ ret float undef
+
+bb6: ; preds = %bb4
+ br i1 undef, label %bb11, label %bb12
+
+bb11: ; preds = %bb6
+ %0 = tail call float @__ieee754_sqrtf(float undef) nounwind ; <float> [#uses=1]
+ %1 = fmul float %0, -2.000000e+00 ; <float> [#uses=1]
+ %2 = fadd float %1, 0x400921FB40000000 ; <float> [#uses=1]
+ ret float %2
+
+bb12: ; preds = %bb6
+ ret float undef
+}
+
+declare float @__ieee754_sqrtf(float)
diff --git a/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll b/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll
new file mode 100644
index 0000000..e068be7
--- /dev/null
+++ b/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -mtriple=armv6-apple-darwin
+
+ %struct.rtunion = type { i64 }
+ %struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] }
+
+define arm_apcscc void @simplify_unary_real(i8* nocapture %p) nounwind {
+entry:
+ %tmp121 = load i64* null, align 4 ; <i64> [#uses=1]
+ %0 = getelementptr %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0 ; <i64*> [#uses=1]
+ %tmp122 = load i64* %0, align 4 ; <i64> [#uses=1]
+ %1 = zext i64 undef to i192 ; <i192> [#uses=2]
+ %2 = zext i64 %tmp121 to i192 ; <i192> [#uses=1]
+ %3 = shl i192 %2, 64 ; <i192> [#uses=2]
+ %4 = zext i64 %tmp122 to i192 ; <i192> [#uses=1]
+ %5 = shl i192 %4, 128 ; <i192> [#uses=1]
+ %6 = or i192 %3, %1 ; <i192> [#uses=1]
+ %7 = or i192 %6, %5 ; <i192> [#uses=2]
+ switch i32 undef, label %bb82 [
+ i32 77, label %bb38
+ i32 129, label %bb21
+ i32 130, label %bb20
+ ]
+
+bb20: ; preds = %entry
+ ret void
+
+bb21: ; preds = %entry
+ br i1 undef, label %bb82, label %bb29
+
+bb29: ; preds = %bb21
+ %tmp18.i = and i192 %3, 1208907372870555465154560 ; <i192> [#uses=1]
+ %mask.i = or i192 %tmp18.i, %1 ; <i192> [#uses=1]
+ %mask41.i = or i192 %mask.i, 0 ; <i192> [#uses=1]
+ br label %bb82
+
+bb38: ; preds = %entry
+ br label %bb82
+
+bb82: ; preds = %bb38, %bb29, %bb21, %entry
+ %d.0 = phi i192 [ %mask41.i, %bb29 ], [ undef, %bb38 ], [ %7, %entry ], [ %7, %bb21 ] ; <i192> [#uses=1]
+ %tmp51 = trunc i192 %d.0 to i64 ; <i64> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll
new file mode 100644
index 0000000..17efe00
--- /dev/null
+++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll
@@ -0,0 +1,122 @@
+; RUN: llc < %s -march=arm -mtriple=armv6-apple-darwin9
+
+@nn = external global i32 ; <i32*> [#uses=1]
+@al_len = external global i32 ; <i32*> [#uses=2]
+@no_mat = external global i32 ; <i32*> [#uses=2]
+@no_mis = external global i32 ; <i32*> [#uses=2]
+@"\01LC12" = external constant [29 x i8], align 1 ; <[29 x i8]*> [#uses=1]
+@"\01LC16" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1]
+@"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1]
+
+declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind
+
+declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind
+
+define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
+entry:
+ br i1 undef, label %bb5, label %bb
+
+bb: ; preds = %bb, %entry
+ br label %bb
+
+bb5: ; preds = %entry
+ br i1 undef, label %bb6, label %bb8
+
+bb6: ; preds = %bb6, %bb5
+ br i1 undef, label %bb8, label %bb6
+
+bb8: ; preds = %bb6, %bb5
+ br label %bb15
+
+bb9: ; preds = %bb15
+ br i1 undef, label %bb10, label %bb11
+
+bb10: ; preds = %bb9
+ unreachable
+
+bb11: ; preds = %bb9
+ %0 = load i32* undef, align 4 ; <i32> [#uses=2]
+ %1 = add i32 %0, 1 ; <i32> [#uses=2]
+ store i32 %1, i32* undef, align 4
+ %2 = load i32* undef, align 4 ; <i32> [#uses=1]
+ store i32 %2, i32* @nn, align 4
+ store i32 0, i32* @al_len, align 4
+ store i32 0, i32* @no_mat, align 4
+ store i32 0, i32* @no_mis, align 4
+ %3 = getelementptr i8* %B, i32 %0 ; <i8*> [#uses=1]
+ tail call arm_apcscc void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind
+ %4 = sitofp i32 undef to double ; <double> [#uses=1]
+ %5 = fdiv double %4, 1.000000e+01 ; <double> [#uses=1]
+ %6 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; <i32> [#uses=0]
+ %7 = load i32* @al_len, align 4 ; <i32> [#uses=1]
+ %8 = load i32* @no_mat, align 4 ; <i32> [#uses=1]
+ %9 = load i32* @no_mis, align 4 ; <i32> [#uses=1]
+ %10 = sub i32 %7, %8 ; <i32> [#uses=1]
+ %11 = sub i32 %10, %9 ; <i32> [#uses=1]
+ %12 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; <i32> [#uses=0]
+ %13 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0]
+ br i1 undef, label %bb15, label %bb12
+
+bb12: ; preds = %bb11
+ br label %bb228.i
+
+bb74.i: ; preds = %bb228.i
+ br i1 undef, label %bb138.i, label %bb145.i
+
+bb138.i: ; preds = %bb74.i
+ br label %bb145.i
+
+bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
+ br i1 undef, label %bb146.i, label %bb151.i
+
+bb146.i: ; preds = %bb145.i
+ br i1 undef, label %bb228.i, label %bb151.i
+
+bb151.i: ; preds = %bb146.i, %bb145.i
+ br i1 undef, label %bb153.i, label %bb228.i
+
+bb153.i: ; preds = %bb151.i
+ br i1 undef, label %bb220.i, label %bb.nph.i98
+
+bb.nph.i98: ; preds = %bb153.i
+ br label %bb158.i
+
+bb158.i: ; preds = %bb218.i, %bb.nph.i98
+ br i1 undef, label %bb168.i, label %bb160.i
+
+bb160.i: ; preds = %bb158.i
+ br i1 undef, label %bb161.i, label %bb168.i
+
+bb161.i: ; preds = %bb160.i
+ br i1 undef, label %bb168.i, label %bb163.i
+
+bb163.i: ; preds = %bb161.i
+ br i1 undef, label %bb167.i, label %bb168.i
+
+bb167.i: ; preds = %bb163.i
+ br label %bb168.i
+
+bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
+ br i1 undef, label %bb211.i, label %bb218.i
+
+bb211.i: ; preds = %bb168.i
+ br label %bb218.i
+
+bb218.i: ; preds = %bb211.i, %bb168.i
+ br i1 undef, label %bb220.i, label %bb158.i
+
+bb220.i: ; preds = %bb218.i, %bb153.i
+ br i1 undef, label %bb221.i, label %bb228.i
+
+bb221.i: ; preds = %bb220.i
+ br label %bb228.i
+
+bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
+ br i1 undef, label %bb74.i, label %bb145.i
+
+bb15: ; preds = %bb11, %bb8
+ br i1 undef, label %return, label %bb9
+
+return: ; preds = %bb15
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
new file mode 100644
index 0000000..f520be3
--- /dev/null
+++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
@@ -0,0 +1,116 @@
+; RUN: llc < %s -march=arm -mtriple=armv6-apple-darwin9
+
+@no_mat = external global i32 ; <i32*> [#uses=1]
+@no_mis = external global i32 ; <i32*> [#uses=2]
+@"\01LC11" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1]
+@"\01LC15" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1]
+@"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1]
+
+declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind
+
+declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind
+
+define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
+entry:
+ br i1 undef, label %bb5, label %bb
+
+bb: ; preds = %bb, %entry
+ br label %bb
+
+bb5: ; preds = %entry
+ br i1 undef, label %bb6, label %bb8
+
+bb6: ; preds = %bb6, %bb5
+ br i1 undef, label %bb8, label %bb6
+
+bb8: ; preds = %bb6, %bb5
+ br label %bb15
+
+bb9: ; preds = %bb15
+ br i1 undef, label %bb10, label %bb11
+
+bb10: ; preds = %bb9
+ unreachable
+
+bb11: ; preds = %bb9
+ %0 = load i32* undef, align 4 ; <i32> [#uses=3]
+ %1 = add i32 %0, 1 ; <i32> [#uses=2]
+ store i32 %1, i32* undef, align 4
+ %2 = load i32* undef, align 4 ; <i32> [#uses=2]
+ %3 = sub i32 %2, %0 ; <i32> [#uses=1]
+ store i32 0, i32* @no_mat, align 4
+ store i32 0, i32* @no_mis, align 4
+ %4 = getelementptr i8* %B, i32 %0 ; <i8*> [#uses=1]
+ tail call arm_apcscc void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind
+ %5 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; <i32> [#uses=0]
+ %6 = load i32* @no_mis, align 4 ; <i32> [#uses=1]
+ %7 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; <i32> [#uses=0]
+ %8 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0]
+ br i1 undef, label %bb15, label %bb12
+
+bb12: ; preds = %bb11
+ br label %bb228.i
+
+bb74.i: ; preds = %bb228.i
+ br i1 undef, label %bb138.i, label %bb145.i
+
+bb138.i: ; preds = %bb74.i
+ br label %bb145.i
+
+bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
+ br i1 undef, label %bb146.i, label %bb151.i
+
+bb146.i: ; preds = %bb145.i
+ br i1 undef, label %bb228.i, label %bb151.i
+
+bb151.i: ; preds = %bb146.i, %bb145.i
+ br i1 undef, label %bb153.i, label %bb228.i
+
+bb153.i: ; preds = %bb151.i
+ br i1 undef, label %bb220.i, label %bb.nph.i98
+
+bb.nph.i98: ; preds = %bb153.i
+ br label %bb158.i
+
+bb158.i: ; preds = %bb218.i, %bb.nph.i98
+ br i1 undef, label %bb168.i, label %bb160.i
+
+bb160.i: ; preds = %bb158.i
+ br i1 undef, label %bb161.i, label %bb168.i
+
+bb161.i: ; preds = %bb160.i
+ br i1 undef, label %bb168.i, label %bb163.i
+
+bb163.i: ; preds = %bb161.i
+ br i1 undef, label %bb167.i, label %bb168.i
+
+bb167.i: ; preds = %bb163.i
+ br label %bb168.i
+
+bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
+ br i1 undef, label %bb211.i, label %bb218.i
+
+bb211.i: ; preds = %bb168.i
+ br label %bb218.i
+
+bb218.i: ; preds = %bb211.i, %bb168.i
+ br i1 undef, label %bb220.i, label %bb158.i
+
+bb220.i: ; preds = %bb218.i, %bb153.i
+ br i1 undef, label %bb221.i, label %bb228.i
+
+bb221.i: ; preds = %bb220.i
+ br label %bb228.i
+
+bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
+ br i1 undef, label %bb74.i, label %bb145.i
+
+bb15: ; preds = %bb11, %bb8
+ %indvar11 = phi i32 [ 0, %bb8 ], [ %tmp13, %bb11 ] ; <i32> [#uses=2]
+ %tmp13 = add i32 %indvar11, 1 ; <i32> [#uses=2]
+ %count.0 = sub i32 undef, %indvar11 ; <i32> [#uses=0]
+ br i1 undef, label %return, label %bb9
+
+return: ; preds = %bb15
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll
new file mode 100644
index 0000000..eee6ff9
--- /dev/null
+++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll
@@ -0,0 +1,128 @@
+; RUN: llc < %s -march=arm -mtriple=armv6-apple-darwin9
+
+@JJ = external global i32* ; <i32**> [#uses=1]
+
+define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
+entry:
+ br i1 undef, label %bb5, label %bb
+
+bb: ; preds = %bb, %entry
+ br label %bb
+
+bb5: ; preds = %entry
+ br i1 undef, label %bb6, label %bb8
+
+bb6: ; preds = %bb6, %bb5
+ br i1 undef, label %bb8, label %bb6
+
+bb8: ; preds = %bb6, %bb5
+ br label %bb15
+
+bb9: ; preds = %bb15
+ br i1 undef, label %bb10, label %bb11
+
+bb10: ; preds = %bb9
+ unreachable
+
+bb11: ; preds = %bb9
+ br i1 undef, label %bb15, label %bb12
+
+bb12: ; preds = %bb11
+ %0 = load i32** @JJ, align 4 ; <i32*> [#uses=1]
+ br label %bb228.i
+
+bb74.i: ; preds = %bb228.i
+ br i1 undef, label %bb138.i, label %bb145.i
+
+bb138.i: ; preds = %bb74.i
+ br label %bb145.i
+
+bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
+ %cflag.0.i = phi i16 [ 0, %bb228.i ], [ 0, %bb74.i ], [ 1, %bb138.i ] ; <i16> [#uses=1]
+ br i1 undef, label %bb146.i, label %bb151.i
+
+bb146.i: ; preds = %bb145.i
+ br i1 undef, label %bb228.i, label %bb151.i
+
+bb151.i: ; preds = %bb146.i, %bb145.i
+ %.not297 = icmp ne i16 %cflag.0.i, 0 ; <i1> [#uses=1]
+ %or.cond298 = and i1 undef, %.not297 ; <i1> [#uses=1]
+ br i1 %or.cond298, label %bb153.i, label %bb228.i
+
+bb153.i: ; preds = %bb151.i
+ br i1 undef, label %bb220.i, label %bb.nph.i98
+
+bb.nph.i98: ; preds = %bb153.i
+ br label %bb158.i
+
+bb158.i: ; preds = %bb218.i, %bb.nph.i98
+ %c.1020.i = phi i32 [ 0, %bb.nph.i98 ], [ %c.14.i, %bb218.i ] ; <i32> [#uses=1]
+ %cflag.418.i = phi i16 [ 0, %bb.nph.i98 ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=1]
+ %pj.317.i = phi i32 [ undef, %bb.nph.i98 ], [ %8, %bb218.i ] ; <i32> [#uses=1]
+ %pi.316.i = phi i32 [ undef, %bb.nph.i98 ], [ %7, %bb218.i ] ; <i32> [#uses=1]
+ %fj.515.i = phi i32 [ undef, %bb.nph.i98 ], [ %fj.4.i, %bb218.i ] ; <i32> [#uses=3]
+ %ci.910.i = phi i32 [ undef, %bb.nph.i98 ], [ %ci.12.i, %bb218.i ] ; <i32> [#uses=2]
+ %i.121.i = sub i32 undef, undef ; <i32> [#uses=3]
+ %tmp105.i = sub i32 undef, undef ; <i32> [#uses=1]
+ %1 = sub i32 %c.1020.i, undef ; <i32> [#uses=0]
+ br i1 undef, label %bb168.i, label %bb160.i
+
+bb160.i: ; preds = %bb158.i
+ br i1 undef, label %bb161.i, label %bb168.i
+
+bb161.i: ; preds = %bb160.i
+ br i1 undef, label %bb168.i, label %bb163.i
+
+bb163.i: ; preds = %bb161.i
+ %2 = icmp slt i32 %fj.515.i, undef ; <i1> [#uses=1]
+ %3 = and i1 %2, undef ; <i1> [#uses=1]
+ br i1 %3, label %bb167.i, label %bb168.i
+
+bb167.i: ; preds = %bb163.i
+ br label %bb168.i
+
+bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
+ %fi.5.i = phi i32 [ undef, %bb167.i ], [ %ci.910.i, %bb158.i ], [ undef, %bb160.i ], [ %ci.910.i, %bb161.i ], [ undef, %bb163.i ] ; <i32> [#uses=1]
+ %fj.4.i = phi i32 [ undef, %bb167.i ], [ undef, %bb158.i ], [ %fj.515.i, %bb160.i ], [ undef, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2]
+ %scevgep88.i = getelementptr i32* null, i32 %i.121.i ; <i32*> [#uses=3]
+ %4 = load i32* %scevgep88.i, align 4 ; <i32> [#uses=2]
+ %scevgep89.i = getelementptr i32* %0, i32 %i.121.i ; <i32*> [#uses=3]
+ %5 = load i32* %scevgep89.i, align 4 ; <i32> [#uses=1]
+ %ci.10.i = select i1 undef, i32 %pi.316.i, i32 %i.121.i ; <i32> [#uses=0]
+ %cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; <i32> [#uses=0]
+ %6 = icmp slt i32 undef, 0 ; <i1> [#uses=3]
+ %ci.12.i = select i1 %6, i32 %fi.5.i, i32 %4 ; <i32> [#uses=2]
+ %cj.11.i100 = select i1 %6, i32 %fj.4.i, i32 %5 ; <i32> [#uses=1]
+ %c.14.i = select i1 %6, i32 0, i32 undef ; <i32> [#uses=2]
+ store i32 %c.14.i, i32* undef, align 4
+ %7 = load i32* %scevgep88.i, align 4 ; <i32> [#uses=1]
+ %8 = load i32* %scevgep89.i, align 4 ; <i32> [#uses=1]
+ store i32 %ci.12.i, i32* %scevgep88.i, align 4
+ store i32 %cj.11.i100, i32* %scevgep89.i, align 4
+ store i32 %4, i32* undef, align 4
+ br i1 undef, label %bb211.i, label %bb218.i
+
+bb211.i: ; preds = %bb168.i
+ br label %bb218.i
+
+bb218.i: ; preds = %bb211.i, %bb168.i
+ %cflag.3.i = phi i16 [ %cflag.418.i, %bb168.i ], [ 1, %bb211.i ] ; <i16> [#uses=2]
+ %9 = icmp slt i32 %tmp105.i, undef ; <i1> [#uses=1]
+ br i1 %9, label %bb220.i, label %bb158.i
+
+bb220.i: ; preds = %bb218.i, %bb153.i
+ %cflag.4.lcssa.i = phi i16 [ 0, %bb153.i ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=0]
+ br i1 undef, label %bb221.i, label %bb228.i
+
+bb221.i: ; preds = %bb220.i
+ br label %bb228.i
+
+bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
+ br i1 undef, label %bb74.i, label %bb145.i
+
+bb15: ; preds = %bb11, %bb8
+ br i1 undef, label %return, label %bb9
+
+return: ; preds = %bb15
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll
new file mode 100644
index 0000000..93c92b1
--- /dev/null
+++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll
@@ -0,0 +1,128 @@
+; RUN: llc < %s -march=arm -mtriple=armv6-apple-darwin9
+
+@r = external global i32 ; <i32*> [#uses=1]
+@qr = external global i32 ; <i32*> [#uses=1]
+@II = external global i32* ; <i32**> [#uses=1]
+@no_mis = external global i32 ; <i32*> [#uses=1]
+@name1 = external global i8* ; <i8**> [#uses=1]
+
+declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind
+
+define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
+entry:
+ br i1 undef, label %bb5, label %bb
+
+bb: ; preds = %bb, %entry
+ br label %bb
+
+bb5: ; preds = %entry
+ br i1 undef, label %bb6, label %bb8
+
+bb6: ; preds = %bb6, %bb5
+ br i1 undef, label %bb8, label %bb6
+
+bb8: ; preds = %bb6, %bb5
+ %0 = load i8** @name1, align 4 ; <i8*> [#uses=0]
+ br label %bb15
+
+bb9: ; preds = %bb15
+ br i1 undef, label %bb10, label %bb11
+
+bb10: ; preds = %bb9
+ unreachable
+
+bb11: ; preds = %bb9
+ store i32 0, i32* @no_mis, align 4
+ %1 = getelementptr i8* %A, i32 0 ; <i8*> [#uses=1]
+ %2 = getelementptr i8* %B, i32 0 ; <i8*> [#uses=1]
+ tail call arm_apcscc void @diff(i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind
+ br i1 undef, label %bb15, label %bb12
+
+bb12: ; preds = %bb11
+ %3 = load i32** @II, align 4 ; <i32*> [#uses=1]
+ %4 = load i32* @r, align 4 ; <i32> [#uses=1]
+ %5 = load i32* @qr, align 4 ; <i32> [#uses=1]
+ br label %bb228.i
+
+bb74.i: ; preds = %bb228.i
+ br i1 undef, label %bb138.i, label %bb145.i
+
+bb138.i: ; preds = %bb74.i
+ br label %bb145.i
+
+bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
+ br i1 undef, label %bb146.i, label %bb151.i
+
+bb146.i: ; preds = %bb145.i
+ br i1 undef, label %bb228.i, label %bb151.i
+
+bb151.i: ; preds = %bb146.i, %bb145.i
+ br i1 undef, label %bb153.i, label %bb228.i
+
+bb153.i: ; preds = %bb151.i
+ %6 = add i32 undef, -1 ; <i32> [#uses=3]
+ br i1 undef, label %bb220.i, label %bb.nph.i98
+
+bb.nph.i98: ; preds = %bb153.i
+ br label %bb158.i
+
+bb158.i: ; preds = %bb218.i, %bb.nph.i98
+ %c.1020.i = phi i32 [ 0, %bb.nph.i98 ], [ %c.14.i, %bb218.i ] ; <i32> [#uses=1]
+ %f.419.i = phi i32 [ undef, %bb.nph.i98 ], [ %f.5.i, %bb218.i ] ; <i32> [#uses=1]
+ %pi.316.i = phi i32 [ undef, %bb.nph.i98 ], [ %10, %bb218.i ] ; <i32> [#uses=1]
+ %fj.515.i = phi i32 [ %6, %bb.nph.i98 ], [ %fj.4.i, %bb218.i ] ; <i32> [#uses=2]
+ %fi.614.i = phi i32 [ undef, %bb.nph.i98 ], [ %fi.5.i, %bb218.i ] ; <i32> [#uses=3]
+ %cj.811.i = phi i32 [ %6, %bb.nph.i98 ], [ %cj.11.i100, %bb218.i ] ; <i32> [#uses=3]
+ %ci.910.i = phi i32 [ undef, %bb.nph.i98 ], [ %ci.12.i, %bb218.i ] ; <i32> [#uses=2]
+ %7 = sub i32 %f.419.i, %4 ; <i32> [#uses=5]
+ %8 = sub i32 %c.1020.i, %5 ; <i32> [#uses=2]
+ %9 = icmp slt i32 %7, %8 ; <i1> [#uses=1]
+ br i1 %9, label %bb168.i, label %bb160.i
+
+bb160.i: ; preds = %bb158.i
+ br i1 undef, label %bb161.i, label %bb168.i
+
+bb161.i: ; preds = %bb160.i
+ br i1 undef, label %bb168.i, label %bb163.i
+
+bb163.i: ; preds = %bb161.i
+ br i1 undef, label %bb167.i, label %bb168.i
+
+bb167.i: ; preds = %bb163.i
+ br label %bb168.i
+
+bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
+ %fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; <i32> [#uses=2]
+ %fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2]
+ %f.5.i = phi i32 [ %7, %bb167.i ], [ %8, %bb158.i ], [ %7, %bb160.i ], [ %7, %bb161.i ], [ %7, %bb163.i ] ; <i32> [#uses=2]
+ %scevgep88.i = getelementptr i32* %3, i32 undef ; <i32*> [#uses=1]
+ %ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; <i32> [#uses=0]
+ %ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; <i32> [#uses=1]
+ %cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; <i32> [#uses=1]
+ %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1]
+ %10 = load i32* %scevgep88.i, align 4 ; <i32> [#uses=1]
+ br i1 undef, label %bb211.i, label %bb218.i
+
+bb211.i: ; preds = %bb168.i
+ br label %bb218.i
+
+bb218.i: ; preds = %bb211.i, %bb168.i
+ br i1 undef, label %bb220.i, label %bb158.i
+
+bb220.i: ; preds = %bb218.i, %bb153.i
+ %11 = getelementptr i32* null, i32 %6 ; <i32*> [#uses=1]
+ store i32 undef, i32* %11, align 4
+ br i1 undef, label %bb221.i, label %bb228.i
+
+bb221.i: ; preds = %bb220.i
+ br label %bb228.i
+
+bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
+ br i1 undef, label %bb74.i, label %bb145.i
+
+bb15: ; preds = %bb11, %bb8
+ br i1 undef, label %return, label %bb9
+
+return: ; preds = %bb15
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
new file mode 100644
index 0000000..277283d
--- /dev/null
+++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
@@ -0,0 +1,99 @@
+; RUN: llc < %s -march=arm -mtriple=armv6-apple-darwin9
+
+@XX = external global i32* ; <i32**> [#uses=1]
+
+define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
+entry:
+ br i1 undef, label %bb5, label %bb
+
+bb: ; preds = %bb, %entry
+ br label %bb
+
+bb5: ; preds = %entry
+ br i1 undef, label %bb6, label %bb8
+
+bb6: ; preds = %bb6, %bb5
+ br i1 undef, label %bb8, label %bb6
+
+bb8: ; preds = %bb6, %bb5
+ br label %bb15
+
+bb9: ; preds = %bb15
+ br i1 undef, label %bb10, label %bb11
+
+bb10: ; preds = %bb9
+ unreachable
+
+bb11: ; preds = %bb9
+ br i1 undef, label %bb15, label %bb12
+
+bb12: ; preds = %bb11
+ %0 = load i32** @XX, align 4 ; <i32*> [#uses=0]
+ br label %bb228.i
+
+bb74.i: ; preds = %bb228.i
+ br i1 undef, label %bb138.i, label %bb145.i
+
+bb138.i: ; preds = %bb74.i
+ br label %bb145.i
+
+bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
+ br i1 undef, label %bb146.i, label %bb151.i
+
+bb146.i: ; preds = %bb145.i
+ br i1 undef, label %bb228.i, label %bb151.i
+
+bb151.i: ; preds = %bb146.i, %bb145.i
+ br i1 undef, label %bb153.i, label %bb228.i
+
+bb153.i: ; preds = %bb151.i
+ br i1 undef, label %bb220.i, label %bb.nph.i98
+
+bb.nph.i98: ; preds = %bb153.i
+ br label %bb158.i
+
+bb158.i: ; preds = %bb218.i, %bb.nph.i98
+ %1 = sub i32 undef, undef ; <i32> [#uses=4]
+ %2 = sub i32 undef, undef ; <i32> [#uses=1]
+ br i1 undef, label %bb168.i, label %bb160.i
+
+bb160.i: ; preds = %bb158.i
+ br i1 undef, label %bb161.i, label %bb168.i
+
+bb161.i: ; preds = %bb160.i
+ br i1 undef, label %bb168.i, label %bb163.i
+
+bb163.i: ; preds = %bb161.i
+ br i1 undef, label %bb167.i, label %bb168.i
+
+bb167.i: ; preds = %bb163.i
+ br label %bb168.i
+
+bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
+ %f.5.i = phi i32 [ %1, %bb167.i ], [ %2, %bb158.i ], [ %1, %bb160.i ], [ %1, %bb161.i ], [ %1, %bb163.i ] ; <i32> [#uses=1]
+ %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1]
+ store i32 %c.14.i, i32* undef, align 4
+ store i32 undef, i32* null, align 4
+ br i1 undef, label %bb211.i, label %bb218.i
+
+bb211.i: ; preds = %bb168.i
+ br label %bb218.i
+
+bb218.i: ; preds = %bb211.i, %bb168.i
+ br i1 undef, label %bb220.i, label %bb158.i
+
+bb220.i: ; preds = %bb218.i, %bb153.i
+ br i1 undef, label %bb221.i, label %bb228.i
+
+bb221.i: ; preds = %bb220.i
+ br label %bb228.i
+
+bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
+ br i1 undef, label %bb74.i, label %bb145.i
+
+bb15: ; preds = %bb11, %bb8
+ br i1 undef, label %return, label %bb9
+
+return: ; preds = %bb15
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-07-01-CommuteBug.ll b/test/CodeGen/ARM/2009-07-01-CommuteBug.ll
new file mode 100644
index 0000000..5c0e5fa
--- /dev/null
+++ b/test/CodeGen/ARM/2009-07-01-CommuteBug.ll
@@ -0,0 +1,130 @@
+; RUN: llc < %s -march=arm -mtriple=armv6-apple-darwin9
+
+@qr = external global i32 ; <i32*> [#uses=1]
+@II = external global i32* ; <i32**> [#uses=1]
+@JJ = external global i32* ; <i32**> [#uses=1]
+
+define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
+entry:
+ br i1 undef, label %bb5, label %bb
+
+bb: ; preds = %bb, %entry
+ br label %bb
+
+bb5: ; preds = %entry
+ br i1 undef, label %bb6, label %bb8
+
+bb6: ; preds = %bb6, %bb5
+ br i1 undef, label %bb8, label %bb6
+
+bb8: ; preds = %bb6, %bb5
+ br label %bb15
+
+bb9: ; preds = %bb15
+ br i1 undef, label %bb10, label %bb11
+
+bb10: ; preds = %bb9
+ unreachable
+
+bb11: ; preds = %bb9
+ br i1 undef, label %bb15, label %bb12
+
+bb12: ; preds = %bb11
+ %0 = load i32** @II, align 4 ; <i32*> [#uses=1]
+ %1 = load i32** @JJ, align 4 ; <i32*> [#uses=1]
+ %2 = load i32* @qr, align 4 ; <i32> [#uses=1]
+ br label %bb228.i
+
+bb74.i: ; preds = %bb228.i
+ br i1 undef, label %bb138.i, label %bb145.i
+
+bb138.i: ; preds = %bb74.i
+ br label %bb145.i
+
+bb145.i: ; preds = %bb228.i, %bb138.i, %bb74.i
+ %cflag.0.i = phi i16 [ %cflag.1.i, %bb228.i ], [ %cflag.1.i, %bb74.i ], [ 1, %bb138.i ] ; <i16> [#uses=2]
+ br i1 undef, label %bb146.i, label %bb151.i
+
+bb146.i: ; preds = %bb145.i
+ br i1 undef, label %bb228.i, label %bb151.i
+
+bb151.i: ; preds = %bb146.i, %bb145.i
+ %.not297 = icmp ne i16 %cflag.0.i, 0 ; <i1> [#uses=1]
+ %or.cond298 = and i1 undef, %.not297 ; <i1> [#uses=1]
+ br i1 %or.cond298, label %bb153.i, label %bb228.i
+
+bb153.i: ; preds = %bb151.i
+ br i1 undef, label %bb220.i, label %bb.nph.i98
+
+bb.nph.i98: ; preds = %bb153.i
+ br label %bb158.i
+
+bb158.i: ; preds = %bb218.i, %bb.nph.i98
+ %c.1020.i = phi i32 [ 0, %bb.nph.i98 ], [ %c.14.i, %bb218.i ] ; <i32> [#uses=1]
+ %f.419.i = phi i32 [ undef, %bb.nph.i98 ], [ %f.5.i, %bb218.i ] ; <i32> [#uses=1]
+ %cflag.418.i = phi i16 [ 0, %bb.nph.i98 ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=1]
+ %pj.317.i = phi i32 [ undef, %bb.nph.i98 ], [ %7, %bb218.i ] ; <i32> [#uses=1]
+ %pi.316.i = phi i32 [ undef, %bb.nph.i98 ], [ %6, %bb218.i ] ; <i32> [#uses=1]
+ %fj.515.i = phi i32 [ undef, %bb.nph.i98 ], [ %fj.4.i, %bb218.i ] ; <i32> [#uses=2]
+ %fi.614.i = phi i32 [ undef, %bb.nph.i98 ], [ %fi.5.i, %bb218.i ] ; <i32> [#uses=3]
+ %cj.811.i = phi i32 [ undef, %bb.nph.i98 ], [ %cj.11.i100, %bb218.i ] ; <i32> [#uses=3]
+ %ci.910.i = phi i32 [ undef, %bb.nph.i98 ], [ %ci.12.i, %bb218.i ] ; <i32> [#uses=2]
+ %3 = sub i32 %f.419.i, 0 ; <i32> [#uses=5]
+ %4 = sub i32 %c.1020.i, %2 ; <i32> [#uses=2]
+ %5 = icmp slt i32 %3, %4 ; <i1> [#uses=1]
+ br i1 %5, label %bb168.i, label %bb160.i
+
+bb160.i: ; preds = %bb158.i
+ br i1 undef, label %bb161.i, label %bb168.i
+
+bb161.i: ; preds = %bb160.i
+ br i1 undef, label %bb168.i, label %bb163.i
+
+bb163.i: ; preds = %bb161.i
+ br i1 undef, label %bb167.i, label %bb168.i
+
+bb167.i: ; preds = %bb163.i
+ br label %bb168.i
+
+bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
+ %fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; <i32> [#uses=2]
+ %fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2]
+ %f.5.i = phi i32 [ %3, %bb167.i ], [ %4, %bb158.i ], [ %3, %bb160.i ], [ %3, %bb161.i ], [ %3, %bb163.i ] ; <i32> [#uses=2]
+ %scevgep88.i = getelementptr i32* %0, i32 undef ; <i32*> [#uses=2]
+ %scevgep89.i = getelementptr i32* %1, i32 undef ; <i32*> [#uses=2]
+ %ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; <i32> [#uses=0]
+ %cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; <i32> [#uses=0]
+ %ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; <i32> [#uses=2]
+ %cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; <i32> [#uses=2]
+ %c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1]
+ %6 = load i32* %scevgep88.i, align 4 ; <i32> [#uses=1]
+ %7 = load i32* %scevgep89.i, align 4 ; <i32> [#uses=1]
+ store i32 %ci.12.i, i32* %scevgep88.i, align 4
+ store i32 %cj.11.i100, i32* %scevgep89.i, align 4
+ br i1 undef, label %bb211.i, label %bb218.i
+
+bb211.i: ; preds = %bb168.i
+ br label %bb218.i
+
+bb218.i: ; preds = %bb211.i, %bb168.i
+ %cflag.3.i = phi i16 [ %cflag.418.i, %bb168.i ], [ 1, %bb211.i ] ; <i16> [#uses=2]
+ %8 = icmp slt i32 undef, undef ; <i1> [#uses=1]
+ br i1 %8, label %bb220.i, label %bb158.i
+
+bb220.i: ; preds = %bb218.i, %bb153.i
+ %cflag.4.lcssa.i = phi i16 [ 0, %bb153.i ], [ %cflag.3.i, %bb218.i ] ; <i16> [#uses=2]
+ br i1 undef, label %bb221.i, label %bb228.i
+
+bb221.i: ; preds = %bb220.i
+ br label %bb228.i
+
+bb228.i: ; preds = %bb221.i, %bb220.i, %bb151.i, %bb146.i, %bb12
+ %cflag.1.i = phi i16 [ 0, %bb146.i ], [ %cflag.0.i, %bb151.i ], [ %cflag.4.lcssa.i, %bb220.i ], [ 1, %bb12 ], [ %cflag.4.lcssa.i, %bb221.i ] ; <i16> [#uses=2]
+ br i1 false, label %bb74.i, label %bb145.i
+
+bb15: ; preds = %bb11, %bb8
+ br i1 false, label %return, label %bb9
+
+return: ; preds = %bb15
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll b/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll
new file mode 100644
index 0000000..e1e94b6
--- /dev/null
+++ b/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=arm -mattr=+v6
+
+define void @test(i8* %x) nounwind {
+entry:
+ call void asm sideeffect "pld\09${0:a}", "r,~{cc}"(i8* %x) nounwind
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-07-18-RewriterBug.ll b/test/CodeGen/ARM/2009-07-18-RewriterBug.ll
new file mode 100644
index 0000000..2b7ccd8
--- /dev/null
+++ b/test/CodeGen/ARM/2009-07-18-RewriterBug.ll
@@ -0,0 +1,1323 @@
+; RUN: llc < %s -mtriple=armv6-apple-darwin10 -mattr=+vfp2 | grep vcmpe | count 13
+
+ %struct.EDGE_PAIR = type { %struct.edge_rec*, %struct.edge_rec* }
+ %struct.VEC2 = type { double, double, double }
+ %struct.VERTEX = type { %struct.VEC2, %struct.VERTEX*, %struct.VERTEX* }
+ %struct.edge_rec = type { %struct.VERTEX*, %struct.edge_rec*, i32, i8* }
+@avail_edge = internal global %struct.edge_rec* null ; <%struct.edge_rec**> [#uses=6]
+@_2E_str7 = internal constant [21 x i8] c"ERROR: Only 1 point!\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[21 x i8]*> [#uses=1]
[email protected] = appending global [1 x i8*] [i8* bitcast (void (%struct.EDGE_PAIR*, %struct.VERTEX*, %struct.VERTEX*)* @build_delaunay to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias nocapture sret %agg.result, %struct.VERTEX* %tree, %struct.VERTEX* %extra) nounwind {
+entry:
+ %delright = alloca %struct.EDGE_PAIR, align 8 ; <%struct.EDGE_PAIR*> [#uses=3]
+ %delleft = alloca %struct.EDGE_PAIR, align 8 ; <%struct.EDGE_PAIR*> [#uses=3]
+ %0 = icmp eq %struct.VERTEX* %tree, null ; <i1> [#uses=1]
+ br i1 %0, label %bb8, label %bb
+
+bb: ; preds = %entry
+ %1 = getelementptr %struct.VERTEX* %tree, i32 0, i32 2 ; <%struct.VERTEX**> [#uses=1]
+ %2 = load %struct.VERTEX** %1, align 4 ; <%struct.VERTEX*> [#uses=2]
+ %3 = icmp eq %struct.VERTEX* %2, null ; <i1> [#uses=1]
+ br i1 %3, label %bb7, label %bb1.i
+
+bb1.i: ; preds = %bb1.i, %bb
+ %tree_addr.0.i = phi %struct.VERTEX* [ %5, %bb1.i ], [ %tree, %bb ] ; <%struct.VERTEX*> [#uses=3]
+ %4 = getelementptr %struct.VERTEX* %tree_addr.0.i, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1]
+ %5 = load %struct.VERTEX** %4, align 4 ; <%struct.VERTEX*> [#uses=2]
+ %6 = icmp eq %struct.VERTEX* %5, null ; <i1> [#uses=1]
+ br i1 %6, label %get_low.exit, label %bb1.i
+
+get_low.exit: ; preds = %bb1.i
+ call arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delright, %struct.VERTEX* %2, %struct.VERTEX* %extra) nounwind
+ %7 = getelementptr %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1]
+ %8 = load %struct.VERTEX** %7, align 4 ; <%struct.VERTEX*> [#uses=1]
+ call arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delleft, %struct.VERTEX* %8, %struct.VERTEX* %tree) nounwind
+ %9 = getelementptr %struct.EDGE_PAIR* %delleft, i32 0, i32 0 ; <%struct.edge_rec**> [#uses=1]
+ %10 = load %struct.edge_rec** %9, align 8 ; <%struct.edge_rec*> [#uses=2]
+ %11 = getelementptr %struct.EDGE_PAIR* %delleft, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %12 = load %struct.edge_rec** %11, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %13 = getelementptr %struct.EDGE_PAIR* %delright, i32 0, i32 0 ; <%struct.edge_rec**> [#uses=1]
+ %14 = load %struct.edge_rec** %13, align 8 ; <%struct.edge_rec*> [#uses=1]
+ %15 = getelementptr %struct.EDGE_PAIR* %delright, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %16 = load %struct.edge_rec** %15, align 4 ; <%struct.edge_rec*> [#uses=2]
+ br label %bb.i
+
+bb.i: ; preds = %bb4.i, %get_low.exit
+ %rdi_addr.0.i = phi %struct.edge_rec* [ %14, %get_low.exit ], [ %72, %bb4.i ] ; <%struct.edge_rec*> [#uses=2]
+ %ldi_addr.1.i = phi %struct.edge_rec* [ %12, %get_low.exit ], [ %ldi_addr.0.i, %bb4.i ] ; <%struct.edge_rec*> [#uses=3]
+ %17 = getelementptr %struct.edge_rec* %rdi_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %18 = load %struct.VERTEX** %17, align 4 ; <%struct.VERTEX*> [#uses=3]
+ %19 = ptrtoint %struct.edge_rec* %ldi_addr.1.i to i32 ; <i32> [#uses=1]
+ %20 = getelementptr %struct.VERTEX* %18, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %21 = load double* %20, align 4 ; <double> [#uses=3]
+ %22 = getelementptr %struct.VERTEX* %18, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %23 = load double* %22, align 4 ; <double> [#uses=3]
+ br label %bb2.i
+
+bb1.i1: ; preds = %bb2.i
+ %24 = ptrtoint %struct.edge_rec* %ldi_addr.0.i to i32 ; <i32> [#uses=2]
+ %25 = add i32 %24, 48 ; <i32> [#uses=1]
+ %26 = and i32 %25, 63 ; <i32> [#uses=1]
+ %27 = and i32 %24, -64 ; <i32> [#uses=1]
+ %28 = or i32 %26, %27 ; <i32> [#uses=1]
+ %29 = inttoptr i32 %28 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %30 = getelementptr %struct.edge_rec* %29, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %31 = load %struct.edge_rec** %30, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %32 = ptrtoint %struct.edge_rec* %31 to i32 ; <i32> [#uses=2]
+ %33 = add i32 %32, 16 ; <i32> [#uses=1]
+ %34 = and i32 %33, 63 ; <i32> [#uses=1]
+ %35 = and i32 %32, -64 ; <i32> [#uses=1]
+ %36 = or i32 %34, %35 ; <i32> [#uses=2]
+ %37 = inttoptr i32 %36 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ br label %bb2.i
+
+bb2.i: ; preds = %bb1.i1, %bb.i
+ %ldi_addr.1.pn.i = phi %struct.edge_rec* [ %ldi_addr.1.i, %bb.i ], [ %37, %bb1.i1 ] ; <%struct.edge_rec*> [#uses=1]
+ %.pn6.in.in.i = phi i32 [ %19, %bb.i ], [ %36, %bb1.i1 ] ; <i32> [#uses=1]
+ %ldi_addr.0.i = phi %struct.edge_rec* [ %ldi_addr.1.i, %bb.i ], [ %37, %bb1.i1 ] ; <%struct.edge_rec*> [#uses=4]
+ %.pn6.in.i = xor i32 %.pn6.in.in.i, 32 ; <i32> [#uses=1]
+ %.pn6.i = inttoptr i32 %.pn6.in.i to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %t1.0.in.i = getelementptr %struct.edge_rec* %ldi_addr.1.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %t2.0.in.i = getelementptr %struct.edge_rec* %.pn6.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %t1.0.i = load %struct.VERTEX** %t1.0.in.i ; <%struct.VERTEX*> [#uses=2]
+ %t2.0.i = load %struct.VERTEX** %t2.0.in.i ; <%struct.VERTEX*> [#uses=2]
+ %38 = getelementptr %struct.VERTEX* %t1.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %39 = load double* %38, align 4 ; <double> [#uses=3]
+ %40 = getelementptr %struct.VERTEX* %t1.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %41 = load double* %40, align 4 ; <double> [#uses=3]
+ %42 = getelementptr %struct.VERTEX* %t2.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %43 = load double* %42, align 4 ; <double> [#uses=1]
+ %44 = getelementptr %struct.VERTEX* %t2.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %45 = load double* %44, align 4 ; <double> [#uses=1]
+ %46 = fsub double %39, %21 ; <double> [#uses=1]
+ %47 = fsub double %45, %23 ; <double> [#uses=1]
+ %48 = fmul double %46, %47 ; <double> [#uses=1]
+ %49 = fsub double %43, %21 ; <double> [#uses=1]
+ %50 = fsub double %41, %23 ; <double> [#uses=1]
+ %51 = fmul double %49, %50 ; <double> [#uses=1]
+ %52 = fsub double %48, %51 ; <double> [#uses=1]
+ %53 = fcmp ogt double %52, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %53, label %bb1.i1, label %bb3.i
+
+bb3.i: ; preds = %bb2.i
+ %54 = ptrtoint %struct.edge_rec* %rdi_addr.0.i to i32 ; <i32> [#uses=1]
+ %55 = xor i32 %54, 32 ; <i32> [#uses=3]
+ %56 = inttoptr i32 %55 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %57 = getelementptr %struct.edge_rec* %56, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %58 = load %struct.VERTEX** %57, align 4 ; <%struct.VERTEX*> [#uses=2]
+ %59 = getelementptr %struct.VERTEX* %58, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %60 = load double* %59, align 4 ; <double> [#uses=1]
+ %61 = getelementptr %struct.VERTEX* %58, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %62 = load double* %61, align 4 ; <double> [#uses=1]
+ %63 = fsub double %60, %39 ; <double> [#uses=1]
+ %64 = fsub double %23, %41 ; <double> [#uses=1]
+ %65 = fmul double %63, %64 ; <double> [#uses=1]
+ %66 = fsub double %21, %39 ; <double> [#uses=1]
+ %67 = fsub double %62, %41 ; <double> [#uses=1]
+ %68 = fmul double %66, %67 ; <double> [#uses=1]
+ %69 = fsub double %65, %68 ; <double> [#uses=1]
+ %70 = fcmp ogt double %69, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %70, label %bb4.i, label %bb5.i
+
+bb4.i: ; preds = %bb3.i
+ %71 = getelementptr %struct.edge_rec* %56, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %72 = load %struct.edge_rec** %71, align 4 ; <%struct.edge_rec*> [#uses=1]
+ br label %bb.i
+
+bb5.i: ; preds = %bb3.i
+ %73 = add i32 %55, 48 ; <i32> [#uses=1]
+ %74 = and i32 %73, 63 ; <i32> [#uses=1]
+ %75 = and i32 %55, -64 ; <i32> [#uses=1]
+ %76 = or i32 %74, %75 ; <i32> [#uses=1]
+ %77 = inttoptr i32 %76 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %78 = getelementptr %struct.edge_rec* %77, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %79 = load %struct.edge_rec** %78, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %80 = ptrtoint %struct.edge_rec* %79 to i32 ; <i32> [#uses=2]
+ %81 = add i32 %80, 16 ; <i32> [#uses=1]
+ %82 = and i32 %81, 63 ; <i32> [#uses=1]
+ %83 = and i32 %80, -64 ; <i32> [#uses=1]
+ %84 = or i32 %82, %83 ; <i32> [#uses=1]
+ %85 = inttoptr i32 %84 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %86 = getelementptr %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %87 = load %struct.VERTEX** %86, align 4 ; <%struct.VERTEX*> [#uses=1]
+ %88 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=6]
+ %89 = getelementptr %struct.edge_rec* %88, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4]
+ store %struct.edge_rec* %88, %struct.edge_rec** %89, align 4
+ %90 = getelementptr %struct.edge_rec* %88, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=2]
+ store %struct.VERTEX* %18, %struct.VERTEX** %90, align 4
+ %91 = ptrtoint %struct.edge_rec* %88 to i32 ; <i32> [#uses=5]
+ %92 = add i32 %91, 16 ; <i32> [#uses=2]
+ %93 = inttoptr i32 %92 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %94 = add i32 %91, 48 ; <i32> [#uses=1]
+ %95 = inttoptr i32 %94 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %96 = getelementptr %struct.edge_rec* %93, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %95, %struct.edge_rec** %96, align 4
+ %97 = add i32 %91, 32 ; <i32> [#uses=1]
+ %98 = inttoptr i32 %97 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3]
+ %99 = getelementptr %struct.edge_rec* %98, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %98, %struct.edge_rec** %99, align 4
+ %100 = getelementptr %struct.edge_rec* %98, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ store %struct.VERTEX* %87, %struct.VERTEX** %100, align 4
+ %101 = getelementptr %struct.edge_rec* %95, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %93, %struct.edge_rec** %101, align 4
+ %102 = load %struct.edge_rec** %89, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %103 = ptrtoint %struct.edge_rec* %102 to i32 ; <i32> [#uses=2]
+ %104 = add i32 %103, 16 ; <i32> [#uses=1]
+ %105 = and i32 %104, 63 ; <i32> [#uses=1]
+ %106 = and i32 %103, -64 ; <i32> [#uses=1]
+ %107 = or i32 %105, %106 ; <i32> [#uses=1]
+ %108 = inttoptr i32 %107 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %109 = getelementptr %struct.edge_rec* %85, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %110 = load %struct.edge_rec** %109, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %111 = ptrtoint %struct.edge_rec* %110 to i32 ; <i32> [#uses=2]
+ %112 = add i32 %111, 16 ; <i32> [#uses=1]
+ %113 = and i32 %112, 63 ; <i32> [#uses=1]
+ %114 = and i32 %111, -64 ; <i32> [#uses=1]
+ %115 = or i32 %113, %114 ; <i32> [#uses=1]
+ %116 = inttoptr i32 %115 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %117 = getelementptr %struct.edge_rec* %116, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %118 = load %struct.edge_rec** %117, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %119 = getelementptr %struct.edge_rec* %108, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %120 = load %struct.edge_rec** %119, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %118, %struct.edge_rec** %119, align 4
+ store %struct.edge_rec* %120, %struct.edge_rec** %117, align 4
+ %121 = load %struct.edge_rec** %89, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %122 = load %struct.edge_rec** %109, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %121, %struct.edge_rec** %109, align 4
+ store %struct.edge_rec* %122, %struct.edge_rec** %89, align 4
+ %123 = xor i32 %91, 32 ; <i32> [#uses=1]
+ %124 = inttoptr i32 %123 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3]
+ %125 = getelementptr %struct.edge_rec* %124, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %126 = load %struct.edge_rec** %125, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %127 = ptrtoint %struct.edge_rec* %126 to i32 ; <i32> [#uses=2]
+ %128 = add i32 %127, 16 ; <i32> [#uses=1]
+ %129 = and i32 %128, 63 ; <i32> [#uses=1]
+ %130 = and i32 %127, -64 ; <i32> [#uses=1]
+ %131 = or i32 %129, %130 ; <i32> [#uses=1]
+ %132 = inttoptr i32 %131 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %133 = getelementptr %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %134 = load %struct.edge_rec** %133, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %135 = ptrtoint %struct.edge_rec* %134 to i32 ; <i32> [#uses=2]
+ %136 = add i32 %135, 16 ; <i32> [#uses=1]
+ %137 = and i32 %136, 63 ; <i32> [#uses=1]
+ %138 = and i32 %135, -64 ; <i32> [#uses=1]
+ %139 = or i32 %137, %138 ; <i32> [#uses=1]
+ %140 = inttoptr i32 %139 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %141 = getelementptr %struct.edge_rec* %140, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %142 = load %struct.edge_rec** %141, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %143 = getelementptr %struct.edge_rec* %132, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %144 = load %struct.edge_rec** %143, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %142, %struct.edge_rec** %143, align 4
+ store %struct.edge_rec* %144, %struct.edge_rec** %141, align 4
+ %145 = load %struct.edge_rec** %125, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %146 = load %struct.edge_rec** %133, align 4 ; <%struct.edge_rec*> [#uses=2]
+ store %struct.edge_rec* %145, %struct.edge_rec** %133, align 4
+ store %struct.edge_rec* %146, %struct.edge_rec** %125, align 4
+ %147 = and i32 %92, 63 ; <i32> [#uses=1]
+ %148 = and i32 %91, -64 ; <i32> [#uses=1]
+ %149 = or i32 %147, %148 ; <i32> [#uses=1]
+ %150 = inttoptr i32 %149 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %151 = getelementptr %struct.edge_rec* %150, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %152 = load %struct.edge_rec** %151, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %153 = ptrtoint %struct.edge_rec* %152 to i32 ; <i32> [#uses=2]
+ %154 = add i32 %153, 16 ; <i32> [#uses=1]
+ %155 = and i32 %154, 63 ; <i32> [#uses=1]
+ %156 = and i32 %153, -64 ; <i32> [#uses=1]
+ %157 = or i32 %155, %156 ; <i32> [#uses=1]
+ %158 = inttoptr i32 %157 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %159 = load %struct.VERTEX** %90, align 4 ; <%struct.VERTEX*> [#uses=1]
+ %160 = getelementptr %struct.edge_rec* %124, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %161 = load %struct.VERTEX** %160, align 4 ; <%struct.VERTEX*> [#uses=1]
+ %162 = getelementptr %struct.edge_rec* %16, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %163 = load %struct.VERTEX** %162, align 4 ; <%struct.VERTEX*> [#uses=1]
+ %164 = icmp eq %struct.VERTEX* %163, %159 ; <i1> [#uses=1]
+ %rdo_addr.0.i = select i1 %164, %struct.edge_rec* %88, %struct.edge_rec* %16 ; <%struct.edge_rec*> [#uses=3]
+ %165 = getelementptr %struct.edge_rec* %10, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %166 = load %struct.VERTEX** %165, align 4 ; <%struct.VERTEX*> [#uses=1]
+ %167 = icmp eq %struct.VERTEX* %166, %161 ; <i1> [#uses=1]
+ %ldo_addr.0.ph.i = select i1 %167, %struct.edge_rec* %124, %struct.edge_rec* %10 ; <%struct.edge_rec*> [#uses=3]
+ br label %bb9.i
+
+bb9.i: ; preds = %bb25.i, %bb24.i, %bb5.i
+ %lcand.2.i = phi %struct.edge_rec* [ %146, %bb5.i ], [ %lcand.1.i, %bb24.i ], [ %739, %bb25.i ] ; <%struct.edge_rec*> [#uses=5]
+ %rcand.2.i = phi %struct.edge_rec* [ %158, %bb5.i ], [ %666, %bb24.i ], [ %rcand.1.i, %bb25.i ] ; <%struct.edge_rec*> [#uses=5]
+ %basel.0.i = phi %struct.edge_rec* [ %88, %bb5.i ], [ %595, %bb24.i ], [ %716, %bb25.i ] ; <%struct.edge_rec*> [#uses=2]
+ %168 = getelementptr %struct.edge_rec* %lcand.2.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %169 = load %struct.edge_rec** %168, align 4 ; <%struct.edge_rec*> [#uses=3]
+ %170 = getelementptr %struct.edge_rec* %basel.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3]
+ %171 = load %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=4]
+ %172 = ptrtoint %struct.edge_rec* %basel.0.i to i32 ; <i32> [#uses=3]
+ %173 = xor i32 %172, 32 ; <i32> [#uses=1]
+ %174 = inttoptr i32 %173 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %175 = getelementptr %struct.edge_rec* %174, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3]
+ %176 = load %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=3]
+ %177 = ptrtoint %struct.edge_rec* %169 to i32 ; <i32> [#uses=1]
+ %178 = xor i32 %177, 32 ; <i32> [#uses=1]
+ %179 = inttoptr i32 %178 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %180 = getelementptr %struct.edge_rec* %179, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %181 = load %struct.VERTEX** %180, align 4 ; <%struct.VERTEX*> [#uses=2]
+ %182 = getelementptr %struct.VERTEX* %171, i32 0, i32 0, i32 0 ; <double*> [#uses=2]
+ %183 = load double* %182, align 4 ; <double> [#uses=2]
+ %184 = getelementptr %struct.VERTEX* %171, i32 0, i32 0, i32 1 ; <double*> [#uses=2]
+ %185 = load double* %184, align 4 ; <double> [#uses=2]
+ %186 = getelementptr %struct.VERTEX* %181, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %187 = load double* %186, align 4 ; <double> [#uses=1]
+ %188 = getelementptr %struct.VERTEX* %181, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %189 = load double* %188, align 4 ; <double> [#uses=1]
+ %190 = getelementptr %struct.VERTEX* %176, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %191 = load double* %190, align 4 ; <double> [#uses=2]
+ %192 = getelementptr %struct.VERTEX* %176, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %193 = load double* %192, align 4 ; <double> [#uses=2]
+ %194 = fsub double %183, %191 ; <double> [#uses=1]
+ %195 = fsub double %189, %193 ; <double> [#uses=1]
+ %196 = fmul double %194, %195 ; <double> [#uses=1]
+ %197 = fsub double %187, %191 ; <double> [#uses=1]
+ %198 = fsub double %185, %193 ; <double> [#uses=1]
+ %199 = fmul double %197, %198 ; <double> [#uses=1]
+ %200 = fsub double %196, %199 ; <double> [#uses=1]
+ %201 = fcmp ogt double %200, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %201, label %bb10.i, label %bb13.i
+
+bb10.i: ; preds = %bb9.i
+ %202 = getelementptr %struct.VERTEX* %171, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ %avail_edge.promoted25 = load %struct.edge_rec** @avail_edge ; <%struct.edge_rec*> [#uses=1]
+ br label %bb12.i
+
+bb11.i: ; preds = %bb12.i
+ %203 = ptrtoint %struct.edge_rec* %lcand.0.i to i32 ; <i32> [#uses=3]
+ %204 = add i32 %203, 16 ; <i32> [#uses=1]
+ %205 = and i32 %204, 63 ; <i32> [#uses=1]
+ %206 = and i32 %203, -64 ; <i32> [#uses=3]
+ %207 = or i32 %205, %206 ; <i32> [#uses=1]
+ %208 = inttoptr i32 %207 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %209 = getelementptr %struct.edge_rec* %208, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %210 = load %struct.edge_rec** %209, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %211 = ptrtoint %struct.edge_rec* %210 to i32 ; <i32> [#uses=2]
+ %212 = add i32 %211, 16 ; <i32> [#uses=1]
+ %213 = and i32 %212, 63 ; <i32> [#uses=1]
+ %214 = and i32 %211, -64 ; <i32> [#uses=1]
+ %215 = or i32 %213, %214 ; <i32> [#uses=1]
+ %216 = inttoptr i32 %215 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %217 = getelementptr %struct.edge_rec* %lcand.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %218 = load %struct.edge_rec** %217, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %219 = ptrtoint %struct.edge_rec* %218 to i32 ; <i32> [#uses=2]
+ %220 = add i32 %219, 16 ; <i32> [#uses=1]
+ %221 = and i32 %220, 63 ; <i32> [#uses=1]
+ %222 = and i32 %219, -64 ; <i32> [#uses=1]
+ %223 = or i32 %221, %222 ; <i32> [#uses=1]
+ %224 = inttoptr i32 %223 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %225 = getelementptr %struct.edge_rec* %216, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %226 = load %struct.edge_rec** %225, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %227 = ptrtoint %struct.edge_rec* %226 to i32 ; <i32> [#uses=2]
+ %228 = add i32 %227, 16 ; <i32> [#uses=1]
+ %229 = and i32 %228, 63 ; <i32> [#uses=1]
+ %230 = and i32 %227, -64 ; <i32> [#uses=1]
+ %231 = or i32 %229, %230 ; <i32> [#uses=1]
+ %232 = inttoptr i32 %231 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %233 = getelementptr %struct.edge_rec* %232, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %234 = load %struct.edge_rec** %233, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %235 = getelementptr %struct.edge_rec* %224, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %236 = load %struct.edge_rec** %235, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %234, %struct.edge_rec** %235, align 4
+ store %struct.edge_rec* %236, %struct.edge_rec** %233, align 4
+ %237 = load %struct.edge_rec** %217, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %238 = load %struct.edge_rec** %225, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %237, %struct.edge_rec** %225, align 4
+ store %struct.edge_rec* %238, %struct.edge_rec** %217, align 4
+ %239 = xor i32 %203, 32 ; <i32> [#uses=2]
+ %240 = add i32 %239, 16 ; <i32> [#uses=1]
+ %241 = and i32 %240, 63 ; <i32> [#uses=1]
+ %242 = or i32 %241, %206 ; <i32> [#uses=1]
+ %243 = inttoptr i32 %242 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %244 = getelementptr %struct.edge_rec* %243, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %245 = load %struct.edge_rec** %244, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %246 = ptrtoint %struct.edge_rec* %245 to i32 ; <i32> [#uses=2]
+ %247 = add i32 %246, 16 ; <i32> [#uses=1]
+ %248 = and i32 %247, 63 ; <i32> [#uses=1]
+ %249 = and i32 %246, -64 ; <i32> [#uses=1]
+ %250 = or i32 %248, %249 ; <i32> [#uses=1]
+ %251 = inttoptr i32 %250 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %252 = inttoptr i32 %239 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %253 = getelementptr %struct.edge_rec* %252, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %254 = load %struct.edge_rec** %253, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %255 = ptrtoint %struct.edge_rec* %254 to i32 ; <i32> [#uses=2]
+ %256 = add i32 %255, 16 ; <i32> [#uses=1]
+ %257 = and i32 %256, 63 ; <i32> [#uses=1]
+ %258 = and i32 %255, -64 ; <i32> [#uses=1]
+ %259 = or i32 %257, %258 ; <i32> [#uses=1]
+ %260 = inttoptr i32 %259 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %261 = getelementptr %struct.edge_rec* %251, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %262 = load %struct.edge_rec** %261, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %263 = ptrtoint %struct.edge_rec* %262 to i32 ; <i32> [#uses=2]
+ %264 = add i32 %263, 16 ; <i32> [#uses=1]
+ %265 = and i32 %264, 63 ; <i32> [#uses=1]
+ %266 = and i32 %263, -64 ; <i32> [#uses=1]
+ %267 = or i32 %265, %266 ; <i32> [#uses=1]
+ %268 = inttoptr i32 %267 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %269 = getelementptr %struct.edge_rec* %268, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %270 = load %struct.edge_rec** %269, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %271 = getelementptr %struct.edge_rec* %260, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %272 = load %struct.edge_rec** %271, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %270, %struct.edge_rec** %271, align 4
+ store %struct.edge_rec* %272, %struct.edge_rec** %269, align 4
+ %273 = load %struct.edge_rec** %253, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %274 = load %struct.edge_rec** %261, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %273, %struct.edge_rec** %261, align 4
+ store %struct.edge_rec* %274, %struct.edge_rec** %253, align 4
+ %275 = inttoptr i32 %206 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %276 = getelementptr %struct.edge_rec* %275, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %avail_edge.tmp.026, %struct.edge_rec** %276, align 4
+ %277 = getelementptr %struct.edge_rec* %t.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %278 = load %struct.edge_rec** %277, align 4 ; <%struct.edge_rec*> [#uses=2]
+ %.pre.i = load double* %182, align 4 ; <double> [#uses=1]
+ %.pre22.i = load double* %184, align 4 ; <double> [#uses=1]
+ br label %bb12.i
+
+bb12.i: ; preds = %bb11.i, %bb10.i
+ %avail_edge.tmp.026 = phi %struct.edge_rec* [ %avail_edge.promoted25, %bb10.i ], [ %275, %bb11.i ] ; <%struct.edge_rec*> [#uses=2]
+ %279 = phi double [ %.pre22.i, %bb11.i ], [ %185, %bb10.i ] ; <double> [#uses=3]
+ %280 = phi double [ %.pre.i, %bb11.i ], [ %183, %bb10.i ] ; <double> [#uses=3]
+ %lcand.0.i = phi %struct.edge_rec* [ %lcand.2.i, %bb10.i ], [ %t.0.i, %bb11.i ] ; <%struct.edge_rec*> [#uses=3]
+ %t.0.i = phi %struct.edge_rec* [ %169, %bb10.i ], [ %278, %bb11.i ] ; <%struct.edge_rec*> [#uses=4]
+ %.pn5.in.in.in.i = phi %struct.edge_rec* [ %lcand.2.i, %bb10.i ], [ %t.0.i, %bb11.i ] ; <%struct.edge_rec*> [#uses=1]
+ %.pn4.in.in.in.i = phi %struct.edge_rec* [ %169, %bb10.i ], [ %278, %bb11.i ] ; <%struct.edge_rec*> [#uses=1]
+ %lcand.2.pn.i = phi %struct.edge_rec* [ %lcand.2.i, %bb10.i ], [ %t.0.i, %bb11.i ] ; <%struct.edge_rec*> [#uses=1]
+ %.pn5.in.in.i = ptrtoint %struct.edge_rec* %.pn5.in.in.in.i to i32 ; <i32> [#uses=1]
+ %.pn4.in.in.i = ptrtoint %struct.edge_rec* %.pn4.in.in.in.i to i32 ; <i32> [#uses=1]
+ %.pn5.in.i = xor i32 %.pn5.in.in.i, 32 ; <i32> [#uses=1]
+ %.pn4.in.i = xor i32 %.pn4.in.in.i, 32 ; <i32> [#uses=1]
+ %.pn5.i = inttoptr i32 %.pn5.in.i to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %.pn4.i = inttoptr i32 %.pn4.in.i to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %v1.0.in.i = getelementptr %struct.edge_rec* %.pn5.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %v2.0.in.i = getelementptr %struct.edge_rec* %.pn4.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %v3.0.in.i = getelementptr %struct.edge_rec* %lcand.2.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %v1.0.i = load %struct.VERTEX** %v1.0.in.i ; <%struct.VERTEX*> [#uses=3]
+ %v2.0.i = load %struct.VERTEX** %v2.0.in.i ; <%struct.VERTEX*> [#uses=3]
+ %v3.0.i = load %struct.VERTEX** %v3.0.in.i ; <%struct.VERTEX*> [#uses=3]
+ %281 = load double* %202, align 4 ; <double> [#uses=3]
+ %282 = getelementptr %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %283 = load double* %282, align 4 ; <double> [#uses=1]
+ %284 = fsub double %283, %280 ; <double> [#uses=2]
+ %285 = getelementptr %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %286 = load double* %285, align 4 ; <double> [#uses=1]
+ %287 = fsub double %286, %279 ; <double> [#uses=2]
+ %288 = getelementptr %struct.VERTEX* %v1.0.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ %289 = load double* %288, align 4 ; <double> [#uses=1]
+ %290 = getelementptr %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %291 = load double* %290, align 4 ; <double> [#uses=1]
+ %292 = fsub double %291, %280 ; <double> [#uses=2]
+ %293 = getelementptr %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %294 = load double* %293, align 4 ; <double> [#uses=1]
+ %295 = fsub double %294, %279 ; <double> [#uses=2]
+ %296 = getelementptr %struct.VERTEX* %v2.0.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ %297 = load double* %296, align 4 ; <double> [#uses=1]
+ %298 = getelementptr %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %299 = load double* %298, align 4 ; <double> [#uses=1]
+ %300 = fsub double %299, %280 ; <double> [#uses=2]
+ %301 = getelementptr %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %302 = load double* %301, align 4 ; <double> [#uses=1]
+ %303 = fsub double %302, %279 ; <double> [#uses=2]
+ %304 = getelementptr %struct.VERTEX* %v3.0.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ %305 = load double* %304, align 4 ; <double> [#uses=1]
+ %306 = fsub double %289, %281 ; <double> [#uses=1]
+ %307 = fmul double %292, %303 ; <double> [#uses=1]
+ %308 = fmul double %295, %300 ; <double> [#uses=1]
+ %309 = fsub double %307, %308 ; <double> [#uses=1]
+ %310 = fmul double %306, %309 ; <double> [#uses=1]
+ %311 = fsub double %297, %281 ; <double> [#uses=1]
+ %312 = fmul double %300, %287 ; <double> [#uses=1]
+ %313 = fmul double %303, %284 ; <double> [#uses=1]
+ %314 = fsub double %312, %313 ; <double> [#uses=1]
+ %315 = fmul double %311, %314 ; <double> [#uses=1]
+ %316 = fadd double %315, %310 ; <double> [#uses=1]
+ %317 = fsub double %305, %281 ; <double> [#uses=1]
+ %318 = fmul double %284, %295 ; <double> [#uses=1]
+ %319 = fmul double %287, %292 ; <double> [#uses=1]
+ %320 = fsub double %318, %319 ; <double> [#uses=1]
+ %321 = fmul double %317, %320 ; <double> [#uses=1]
+ %322 = fadd double %321, %316 ; <double> [#uses=1]
+ %323 = fcmp ogt double %322, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %323, label %bb11.i, label %bb13.loopexit.i
+
+bb13.loopexit.i: ; preds = %bb12.i
+ store %struct.edge_rec* %avail_edge.tmp.026, %struct.edge_rec** @avail_edge
+ %.pre23.i = load %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=1]
+ %.pre24.i = load %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=1]
+ br label %bb13.i
+
+bb13.i: ; preds = %bb13.loopexit.i, %bb9.i
+ %324 = phi %struct.VERTEX* [ %.pre24.i, %bb13.loopexit.i ], [ %176, %bb9.i ] ; <%struct.VERTEX*> [#uses=4]
+ %325 = phi %struct.VERTEX* [ %.pre23.i, %bb13.loopexit.i ], [ %171, %bb9.i ] ; <%struct.VERTEX*> [#uses=3]
+ %lcand.1.i = phi %struct.edge_rec* [ %lcand.0.i, %bb13.loopexit.i ], [ %lcand.2.i, %bb9.i ] ; <%struct.edge_rec*> [#uses=3]
+ %326 = ptrtoint %struct.edge_rec* %rcand.2.i to i32 ; <i32> [#uses=2]
+ %327 = add i32 %326, 16 ; <i32> [#uses=1]
+ %328 = and i32 %327, 63 ; <i32> [#uses=1]
+ %329 = and i32 %326, -64 ; <i32> [#uses=1]
+ %330 = or i32 %328, %329 ; <i32> [#uses=1]
+ %331 = inttoptr i32 %330 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %332 = getelementptr %struct.edge_rec* %331, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %333 = load %struct.edge_rec** %332, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %334 = ptrtoint %struct.edge_rec* %333 to i32 ; <i32> [#uses=2]
+ %335 = add i32 %334, 16 ; <i32> [#uses=1]
+ %336 = and i32 %335, 63 ; <i32> [#uses=1]
+ %337 = and i32 %334, -64 ; <i32> [#uses=1]
+ %338 = or i32 %336, %337 ; <i32> [#uses=3]
+ %339 = xor i32 %338, 32 ; <i32> [#uses=1]
+ %340 = inttoptr i32 %339 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %341 = getelementptr %struct.edge_rec* %340, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %342 = load %struct.VERTEX** %341, align 4 ; <%struct.VERTEX*> [#uses=2]
+ %343 = getelementptr %struct.VERTEX* %325, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %344 = load double* %343, align 4 ; <double> [#uses=1]
+ %345 = getelementptr %struct.VERTEX* %325, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %346 = load double* %345, align 4 ; <double> [#uses=1]
+ %347 = getelementptr %struct.VERTEX* %342, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %348 = load double* %347, align 4 ; <double> [#uses=1]
+ %349 = getelementptr %struct.VERTEX* %342, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %350 = load double* %349, align 4 ; <double> [#uses=1]
+ %351 = getelementptr %struct.VERTEX* %324, i32 0, i32 0, i32 0 ; <double*> [#uses=2]
+ %352 = load double* %351, align 4 ; <double> [#uses=3]
+ %353 = getelementptr %struct.VERTEX* %324, i32 0, i32 0, i32 1 ; <double*> [#uses=2]
+ %354 = load double* %353, align 4 ; <double> [#uses=3]
+ %355 = fsub double %344, %352 ; <double> [#uses=1]
+ %356 = fsub double %350, %354 ; <double> [#uses=1]
+ %357 = fmul double %355, %356 ; <double> [#uses=1]
+ %358 = fsub double %348, %352 ; <double> [#uses=1]
+ %359 = fsub double %346, %354 ; <double> [#uses=1]
+ %360 = fmul double %358, %359 ; <double> [#uses=1]
+ %361 = fsub double %357, %360 ; <double> [#uses=1]
+ %362 = fcmp ogt double %361, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %362, label %bb14.i, label %bb17.i
+
+bb14.i: ; preds = %bb13.i
+ %363 = getelementptr %struct.VERTEX* %324, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ %avail_edge.promoted = load %struct.edge_rec** @avail_edge ; <%struct.edge_rec*> [#uses=1]
+ br label %bb16.i
+
+bb15.i: ; preds = %bb16.i
+ %364 = ptrtoint %struct.edge_rec* %rcand.0.i to i32 ; <i32> [#uses=3]
+ %365 = add i32 %364, 16 ; <i32> [#uses=1]
+ %366 = and i32 %365, 63 ; <i32> [#uses=1]
+ %367 = and i32 %364, -64 ; <i32> [#uses=3]
+ %368 = or i32 %366, %367 ; <i32> [#uses=1]
+ %369 = inttoptr i32 %368 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %370 = getelementptr %struct.edge_rec* %369, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %371 = load %struct.edge_rec** %370, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %372 = ptrtoint %struct.edge_rec* %371 to i32 ; <i32> [#uses=2]
+ %373 = add i32 %372, 16 ; <i32> [#uses=1]
+ %374 = and i32 %373, 63 ; <i32> [#uses=1]
+ %375 = and i32 %372, -64 ; <i32> [#uses=1]
+ %376 = or i32 %374, %375 ; <i32> [#uses=1]
+ %377 = inttoptr i32 %376 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %378 = getelementptr %struct.edge_rec* %rcand.0.i, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %379 = load %struct.edge_rec** %378, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %380 = ptrtoint %struct.edge_rec* %379 to i32 ; <i32> [#uses=2]
+ %381 = add i32 %380, 16 ; <i32> [#uses=1]
+ %382 = and i32 %381, 63 ; <i32> [#uses=1]
+ %383 = and i32 %380, -64 ; <i32> [#uses=1]
+ %384 = or i32 %382, %383 ; <i32> [#uses=1]
+ %385 = inttoptr i32 %384 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %386 = getelementptr %struct.edge_rec* %377, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %387 = load %struct.edge_rec** %386, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %388 = ptrtoint %struct.edge_rec* %387 to i32 ; <i32> [#uses=2]
+ %389 = add i32 %388, 16 ; <i32> [#uses=1]
+ %390 = and i32 %389, 63 ; <i32> [#uses=1]
+ %391 = and i32 %388, -64 ; <i32> [#uses=1]
+ %392 = or i32 %390, %391 ; <i32> [#uses=1]
+ %393 = inttoptr i32 %392 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %394 = getelementptr %struct.edge_rec* %393, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %395 = load %struct.edge_rec** %394, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %396 = getelementptr %struct.edge_rec* %385, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %397 = load %struct.edge_rec** %396, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %395, %struct.edge_rec** %396, align 4
+ store %struct.edge_rec* %397, %struct.edge_rec** %394, align 4
+ %398 = load %struct.edge_rec** %378, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %399 = load %struct.edge_rec** %386, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %398, %struct.edge_rec** %386, align 4
+ store %struct.edge_rec* %399, %struct.edge_rec** %378, align 4
+ %400 = xor i32 %364, 32 ; <i32> [#uses=2]
+ %401 = add i32 %400, 16 ; <i32> [#uses=1]
+ %402 = and i32 %401, 63 ; <i32> [#uses=1]
+ %403 = or i32 %402, %367 ; <i32> [#uses=1]
+ %404 = inttoptr i32 %403 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %405 = getelementptr %struct.edge_rec* %404, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %406 = load %struct.edge_rec** %405, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %407 = ptrtoint %struct.edge_rec* %406 to i32 ; <i32> [#uses=2]
+ %408 = add i32 %407, 16 ; <i32> [#uses=1]
+ %409 = and i32 %408, 63 ; <i32> [#uses=1]
+ %410 = and i32 %407, -64 ; <i32> [#uses=1]
+ %411 = or i32 %409, %410 ; <i32> [#uses=1]
+ %412 = inttoptr i32 %411 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %413 = inttoptr i32 %400 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %414 = getelementptr %struct.edge_rec* %413, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %415 = load %struct.edge_rec** %414, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %416 = ptrtoint %struct.edge_rec* %415 to i32 ; <i32> [#uses=2]
+ %417 = add i32 %416, 16 ; <i32> [#uses=1]
+ %418 = and i32 %417, 63 ; <i32> [#uses=1]
+ %419 = and i32 %416, -64 ; <i32> [#uses=1]
+ %420 = or i32 %418, %419 ; <i32> [#uses=1]
+ %421 = inttoptr i32 %420 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %422 = getelementptr %struct.edge_rec* %412, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %423 = load %struct.edge_rec** %422, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %424 = ptrtoint %struct.edge_rec* %423 to i32 ; <i32> [#uses=2]
+ %425 = add i32 %424, 16 ; <i32> [#uses=1]
+ %426 = and i32 %425, 63 ; <i32> [#uses=1]
+ %427 = and i32 %424, -64 ; <i32> [#uses=1]
+ %428 = or i32 %426, %427 ; <i32> [#uses=1]
+ %429 = inttoptr i32 %428 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %430 = getelementptr %struct.edge_rec* %429, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %431 = load %struct.edge_rec** %430, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %432 = getelementptr %struct.edge_rec* %421, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %433 = load %struct.edge_rec** %432, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %431, %struct.edge_rec** %432, align 4
+ store %struct.edge_rec* %433, %struct.edge_rec** %430, align 4
+ %434 = load %struct.edge_rec** %414, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %435 = load %struct.edge_rec** %422, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %434, %struct.edge_rec** %422, align 4
+ store %struct.edge_rec* %435, %struct.edge_rec** %414, align 4
+ %436 = inttoptr i32 %367 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %437 = getelementptr %struct.edge_rec* %436, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %avail_edge.tmp.0, %struct.edge_rec** %437, align 4
+ %438 = add i32 %t.1.in.i, 16 ; <i32> [#uses=1]
+ %439 = and i32 %438, 63 ; <i32> [#uses=1]
+ %440 = and i32 %t.1.in.i, -64 ; <i32> [#uses=1]
+ %441 = or i32 %439, %440 ; <i32> [#uses=1]
+ %442 = inttoptr i32 %441 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %443 = getelementptr %struct.edge_rec* %442, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %444 = load %struct.edge_rec** %443, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %445 = ptrtoint %struct.edge_rec* %444 to i32 ; <i32> [#uses=2]
+ %446 = add i32 %445, 16 ; <i32> [#uses=1]
+ %447 = and i32 %446, 63 ; <i32> [#uses=1]
+ %448 = and i32 %445, -64 ; <i32> [#uses=1]
+ %449 = or i32 %447, %448 ; <i32> [#uses=2]
+ %.pre25.i = load double* %351, align 4 ; <double> [#uses=1]
+ %.pre26.i = load double* %353, align 4 ; <double> [#uses=1]
+ br label %bb16.i
+
+bb16.i: ; preds = %bb15.i, %bb14.i
+ %avail_edge.tmp.0 = phi %struct.edge_rec* [ %avail_edge.promoted, %bb14.i ], [ %436, %bb15.i ] ; <%struct.edge_rec*> [#uses=2]
+ %450 = phi double [ %.pre26.i, %bb15.i ], [ %354, %bb14.i ] ; <double> [#uses=3]
+ %451 = phi double [ %.pre25.i, %bb15.i ], [ %352, %bb14.i ] ; <double> [#uses=3]
+ %rcand.0.i = phi %struct.edge_rec* [ %rcand.2.i, %bb14.i ], [ %t.1.i, %bb15.i ] ; <%struct.edge_rec*> [#uses=3]
+ %t.1.in.i = phi i32 [ %338, %bb14.i ], [ %449, %bb15.i ] ; <i32> [#uses=3]
+ %.pn3.in.in.i = phi i32 [ %338, %bb14.i ], [ %449, %bb15.i ] ; <i32> [#uses=1]
+ %.pn.in.in.in.i = phi %struct.edge_rec* [ %rcand.2.i, %bb14.i ], [ %t.1.i, %bb15.i ] ; <%struct.edge_rec*> [#uses=1]
+ %rcand.2.pn.i = phi %struct.edge_rec* [ %rcand.2.i, %bb14.i ], [ %t.1.i, %bb15.i ] ; <%struct.edge_rec*> [#uses=1]
+ %t.1.i = inttoptr i32 %t.1.in.i to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3]
+ %.pn.in.in.i = ptrtoint %struct.edge_rec* %.pn.in.in.in.i to i32 ; <i32> [#uses=1]
+ %.pn3.in.i = xor i32 %.pn3.in.in.i, 32 ; <i32> [#uses=1]
+ %.pn.in.i = xor i32 %.pn.in.in.i, 32 ; <i32> [#uses=1]
+ %.pn3.i = inttoptr i32 %.pn3.in.i to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %.pn.i = inttoptr i32 %.pn.in.i to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %v1.1.in.i = getelementptr %struct.edge_rec* %.pn3.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %v2.1.in.i = getelementptr %struct.edge_rec* %.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %v3.1.in.i = getelementptr %struct.edge_rec* %rcand.2.pn.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %v1.1.i = load %struct.VERTEX** %v1.1.in.i ; <%struct.VERTEX*> [#uses=3]
+ %v2.1.i = load %struct.VERTEX** %v2.1.in.i ; <%struct.VERTEX*> [#uses=3]
+ %v3.1.i = load %struct.VERTEX** %v3.1.in.i ; <%struct.VERTEX*> [#uses=3]
+ %452 = load double* %363, align 4 ; <double> [#uses=3]
+ %453 = getelementptr %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %454 = load double* %453, align 4 ; <double> [#uses=1]
+ %455 = fsub double %454, %451 ; <double> [#uses=2]
+ %456 = getelementptr %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %457 = load double* %456, align 4 ; <double> [#uses=1]
+ %458 = fsub double %457, %450 ; <double> [#uses=2]
+ %459 = getelementptr %struct.VERTEX* %v1.1.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ %460 = load double* %459, align 4 ; <double> [#uses=1]
+ %461 = getelementptr %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %462 = load double* %461, align 4 ; <double> [#uses=1]
+ %463 = fsub double %462, %451 ; <double> [#uses=2]
+ %464 = getelementptr %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %465 = load double* %464, align 4 ; <double> [#uses=1]
+ %466 = fsub double %465, %450 ; <double> [#uses=2]
+ %467 = getelementptr %struct.VERTEX* %v2.1.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ %468 = load double* %467, align 4 ; <double> [#uses=1]
+ %469 = getelementptr %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %470 = load double* %469, align 4 ; <double> [#uses=1]
+ %471 = fsub double %470, %451 ; <double> [#uses=2]
+ %472 = getelementptr %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %473 = load double* %472, align 4 ; <double> [#uses=1]
+ %474 = fsub double %473, %450 ; <double> [#uses=2]
+ %475 = getelementptr %struct.VERTEX* %v3.1.i, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ %476 = load double* %475, align 4 ; <double> [#uses=1]
+ %477 = fsub double %460, %452 ; <double> [#uses=1]
+ %478 = fmul double %463, %474 ; <double> [#uses=1]
+ %479 = fmul double %466, %471 ; <double> [#uses=1]
+ %480 = fsub double %478, %479 ; <double> [#uses=1]
+ %481 = fmul double %477, %480 ; <double> [#uses=1]
+ %482 = fsub double %468, %452 ; <double> [#uses=1]
+ %483 = fmul double %471, %458 ; <double> [#uses=1]
+ %484 = fmul double %474, %455 ; <double> [#uses=1]
+ %485 = fsub double %483, %484 ; <double> [#uses=1]
+ %486 = fmul double %482, %485 ; <double> [#uses=1]
+ %487 = fadd double %486, %481 ; <double> [#uses=1]
+ %488 = fsub double %476, %452 ; <double> [#uses=1]
+ %489 = fmul double %455, %466 ; <double> [#uses=1]
+ %490 = fmul double %458, %463 ; <double> [#uses=1]
+ %491 = fsub double %489, %490 ; <double> [#uses=1]
+ %492 = fmul double %488, %491 ; <double> [#uses=1]
+ %493 = fadd double %492, %487 ; <double> [#uses=1]
+ %494 = fcmp ogt double %493, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %494, label %bb15.i, label %bb17.loopexit.i
+
+bb17.loopexit.i: ; preds = %bb16.i
+ store %struct.edge_rec* %avail_edge.tmp.0, %struct.edge_rec** @avail_edge
+ %.pre27.i = load %struct.VERTEX** %170, align 4 ; <%struct.VERTEX*> [#uses=1]
+ %.pre28.i = load %struct.VERTEX** %175, align 4 ; <%struct.VERTEX*> [#uses=1]
+ br label %bb17.i
+
+bb17.i: ; preds = %bb17.loopexit.i, %bb13.i
+ %495 = phi %struct.VERTEX* [ %.pre28.i, %bb17.loopexit.i ], [ %324, %bb13.i ] ; <%struct.VERTEX*> [#uses=3]
+ %496 = phi %struct.VERTEX* [ %.pre27.i, %bb17.loopexit.i ], [ %325, %bb13.i ] ; <%struct.VERTEX*> [#uses=3]
+ %rcand.1.i = phi %struct.edge_rec* [ %rcand.0.i, %bb17.loopexit.i ], [ %rcand.2.i, %bb13.i ] ; <%struct.edge_rec*> [#uses=3]
+ %497 = ptrtoint %struct.edge_rec* %lcand.1.i to i32 ; <i32> [#uses=1]
+ %498 = xor i32 %497, 32 ; <i32> [#uses=1]
+ %499 = inttoptr i32 %498 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %500 = getelementptr %struct.edge_rec* %499, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %501 = load %struct.VERTEX** %500, align 4 ; <%struct.VERTEX*> [#uses=4]
+ %502 = getelementptr %struct.VERTEX* %496, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %503 = load double* %502, align 4 ; <double> [#uses=1]
+ %504 = getelementptr %struct.VERTEX* %496, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %505 = load double* %504, align 4 ; <double> [#uses=1]
+ %506 = getelementptr %struct.VERTEX* %501, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %507 = load double* %506, align 4 ; <double> [#uses=2]
+ %508 = getelementptr %struct.VERTEX* %501, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %509 = load double* %508, align 4 ; <double> [#uses=2]
+ %510 = getelementptr %struct.VERTEX* %495, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %511 = load double* %510, align 4 ; <double> [#uses=3]
+ %512 = getelementptr %struct.VERTEX* %495, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %513 = load double* %512, align 4 ; <double> [#uses=3]
+ %514 = fsub double %503, %511 ; <double> [#uses=2]
+ %515 = fsub double %509, %513 ; <double> [#uses=1]
+ %516 = fmul double %514, %515 ; <double> [#uses=1]
+ %517 = fsub double %507, %511 ; <double> [#uses=1]
+ %518 = fsub double %505, %513 ; <double> [#uses=2]
+ %519 = fmul double %517, %518 ; <double> [#uses=1]
+ %520 = fsub double %516, %519 ; <double> [#uses=1]
+ %521 = fcmp ogt double %520, 0.000000e+00 ; <i1> [#uses=2]
+ %522 = ptrtoint %struct.edge_rec* %rcand.1.i to i32 ; <i32> [#uses=3]
+ %523 = xor i32 %522, 32 ; <i32> [#uses=1]
+ %524 = inttoptr i32 %523 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %525 = getelementptr %struct.edge_rec* %524, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %526 = load %struct.VERTEX** %525, align 4 ; <%struct.VERTEX*> [#uses=4]
+ %527 = getelementptr %struct.VERTEX* %526, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %528 = load double* %527, align 4 ; <double> [#uses=4]
+ %529 = getelementptr %struct.VERTEX* %526, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %530 = load double* %529, align 4 ; <double> [#uses=4]
+ %531 = fsub double %530, %513 ; <double> [#uses=1]
+ %532 = fmul double %514, %531 ; <double> [#uses=1]
+ %533 = fsub double %528, %511 ; <double> [#uses=1]
+ %534 = fmul double %533, %518 ; <double> [#uses=1]
+ %535 = fsub double %532, %534 ; <double> [#uses=1]
+ %536 = fcmp ogt double %535, 0.000000e+00 ; <i1> [#uses=2]
+ %537 = or i1 %536, %521 ; <i1> [#uses=1]
+ br i1 %537, label %bb21.i, label %do_merge.exit
+
+bb21.i: ; preds = %bb17.i
+ %538 = getelementptr %struct.edge_rec* %lcand.1.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %539 = load %struct.VERTEX** %538, align 4 ; <%struct.VERTEX*> [#uses=3]
+ %540 = getelementptr %struct.edge_rec* %rcand.1.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %541 = load %struct.VERTEX** %540, align 4 ; <%struct.VERTEX*> [#uses=3]
+ br i1 %521, label %bb22.i, label %bb24.i
+
+bb22.i: ; preds = %bb21.i
+ br i1 %536, label %bb23.i, label %bb25.i
+
+bb23.i: ; preds = %bb22.i
+ %542 = getelementptr %struct.VERTEX* %526, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ %543 = load double* %542, align 4 ; <double> [#uses=3]
+ %544 = fsub double %507, %528 ; <double> [#uses=2]
+ %545 = fsub double %509, %530 ; <double> [#uses=2]
+ %546 = getelementptr %struct.VERTEX* %501, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ %547 = load double* %546, align 4 ; <double> [#uses=1]
+ %548 = getelementptr %struct.VERTEX* %539, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %549 = load double* %548, align 4 ; <double> [#uses=1]
+ %550 = fsub double %549, %528 ; <double> [#uses=2]
+ %551 = getelementptr %struct.VERTEX* %539, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %552 = load double* %551, align 4 ; <double> [#uses=1]
+ %553 = fsub double %552, %530 ; <double> [#uses=2]
+ %554 = getelementptr %struct.VERTEX* %539, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ %555 = load double* %554, align 4 ; <double> [#uses=1]
+ %556 = getelementptr %struct.VERTEX* %541, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %557 = load double* %556, align 4 ; <double> [#uses=1]
+ %558 = fsub double %557, %528 ; <double> [#uses=2]
+ %559 = getelementptr %struct.VERTEX* %541, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %560 = load double* %559, align 4 ; <double> [#uses=1]
+ %561 = fsub double %560, %530 ; <double> [#uses=2]
+ %562 = getelementptr %struct.VERTEX* %541, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ %563 = load double* %562, align 4 ; <double> [#uses=1]
+ %564 = fsub double %547, %543 ; <double> [#uses=1]
+ %565 = fmul double %550, %561 ; <double> [#uses=1]
+ %566 = fmul double %553, %558 ; <double> [#uses=1]
+ %567 = fsub double %565, %566 ; <double> [#uses=1]
+ %568 = fmul double %564, %567 ; <double> [#uses=1]
+ %569 = fsub double %555, %543 ; <double> [#uses=1]
+ %570 = fmul double %558, %545 ; <double> [#uses=1]
+ %571 = fmul double %561, %544 ; <double> [#uses=1]
+ %572 = fsub double %570, %571 ; <double> [#uses=1]
+ %573 = fmul double %569, %572 ; <double> [#uses=1]
+ %574 = fadd double %573, %568 ; <double> [#uses=1]
+ %575 = fsub double %563, %543 ; <double> [#uses=1]
+ %576 = fmul double %544, %553 ; <double> [#uses=1]
+ %577 = fmul double %545, %550 ; <double> [#uses=1]
+ %578 = fsub double %576, %577 ; <double> [#uses=1]
+ %579 = fmul double %575, %578 ; <double> [#uses=1]
+ %580 = fadd double %579, %574 ; <double> [#uses=1]
+ %581 = fcmp ogt double %580, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %581, label %bb24.i, label %bb25.i
+
+bb24.i: ; preds = %bb23.i, %bb21.i
+ %582 = add i32 %522, 48 ; <i32> [#uses=1]
+ %583 = and i32 %582, 63 ; <i32> [#uses=1]
+ %584 = and i32 %522, -64 ; <i32> [#uses=1]
+ %585 = or i32 %583, %584 ; <i32> [#uses=1]
+ %586 = inttoptr i32 %585 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %587 = getelementptr %struct.edge_rec* %586, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %588 = load %struct.edge_rec** %587, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %589 = ptrtoint %struct.edge_rec* %588 to i32 ; <i32> [#uses=2]
+ %590 = add i32 %589, 16 ; <i32> [#uses=1]
+ %591 = and i32 %590, 63 ; <i32> [#uses=1]
+ %592 = and i32 %589, -64 ; <i32> [#uses=1]
+ %593 = or i32 %591, %592 ; <i32> [#uses=1]
+ %594 = inttoptr i32 %593 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %595 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5]
+ %596 = getelementptr %struct.edge_rec* %595, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4]
+ store %struct.edge_rec* %595, %struct.edge_rec** %596, align 4
+ %597 = getelementptr %struct.edge_rec* %595, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ store %struct.VERTEX* %526, %struct.VERTEX** %597, align 4
+ %598 = ptrtoint %struct.edge_rec* %595 to i32 ; <i32> [#uses=5]
+ %599 = add i32 %598, 16 ; <i32> [#uses=1]
+ %600 = inttoptr i32 %599 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %601 = add i32 %598, 48 ; <i32> [#uses=1]
+ %602 = inttoptr i32 %601 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %603 = getelementptr %struct.edge_rec* %600, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %602, %struct.edge_rec** %603, align 4
+ %604 = add i32 %598, 32 ; <i32> [#uses=1]
+ %605 = inttoptr i32 %604 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3]
+ %606 = getelementptr %struct.edge_rec* %605, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %605, %struct.edge_rec** %606, align 4
+ %607 = getelementptr %struct.edge_rec* %605, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ store %struct.VERTEX* %495, %struct.VERTEX** %607, align 4
+ %608 = getelementptr %struct.edge_rec* %602, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %600, %struct.edge_rec** %608, align 4
+ %609 = load %struct.edge_rec** %596, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %610 = ptrtoint %struct.edge_rec* %609 to i32 ; <i32> [#uses=2]
+ %611 = add i32 %610, 16 ; <i32> [#uses=1]
+ %612 = and i32 %611, 63 ; <i32> [#uses=1]
+ %613 = and i32 %610, -64 ; <i32> [#uses=1]
+ %614 = or i32 %612, %613 ; <i32> [#uses=1]
+ %615 = inttoptr i32 %614 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %616 = getelementptr %struct.edge_rec* %594, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %617 = load %struct.edge_rec** %616, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %618 = ptrtoint %struct.edge_rec* %617 to i32 ; <i32> [#uses=2]
+ %619 = add i32 %618, 16 ; <i32> [#uses=1]
+ %620 = and i32 %619, 63 ; <i32> [#uses=1]
+ %621 = and i32 %618, -64 ; <i32> [#uses=1]
+ %622 = or i32 %620, %621 ; <i32> [#uses=1]
+ %623 = inttoptr i32 %622 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %624 = getelementptr %struct.edge_rec* %623, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %625 = load %struct.edge_rec** %624, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %626 = getelementptr %struct.edge_rec* %615, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %627 = load %struct.edge_rec** %626, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %625, %struct.edge_rec** %626, align 4
+ store %struct.edge_rec* %627, %struct.edge_rec** %624, align 4
+ %628 = load %struct.edge_rec** %596, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %629 = load %struct.edge_rec** %616, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %628, %struct.edge_rec** %616, align 4
+ store %struct.edge_rec* %629, %struct.edge_rec** %596, align 4
+ %630 = xor i32 %598, 32 ; <i32> [#uses=2]
+ %631 = inttoptr i32 %630 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %632 = getelementptr %struct.edge_rec* %631, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %633 = load %struct.edge_rec** %632, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %634 = ptrtoint %struct.edge_rec* %633 to i32 ; <i32> [#uses=2]
+ %635 = add i32 %634, 16 ; <i32> [#uses=1]
+ %636 = and i32 %635, 63 ; <i32> [#uses=1]
+ %637 = and i32 %634, -64 ; <i32> [#uses=1]
+ %638 = or i32 %636, %637 ; <i32> [#uses=1]
+ %639 = inttoptr i32 %638 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %640 = getelementptr %struct.edge_rec* %174, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %641 = load %struct.edge_rec** %640, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %642 = ptrtoint %struct.edge_rec* %641 to i32 ; <i32> [#uses=2]
+ %643 = add i32 %642, 16 ; <i32> [#uses=1]
+ %644 = and i32 %643, 63 ; <i32> [#uses=1]
+ %645 = and i32 %642, -64 ; <i32> [#uses=1]
+ %646 = or i32 %644, %645 ; <i32> [#uses=1]
+ %647 = inttoptr i32 %646 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %648 = getelementptr %struct.edge_rec* %647, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %649 = load %struct.edge_rec** %648, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %650 = getelementptr %struct.edge_rec* %639, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %651 = load %struct.edge_rec** %650, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %649, %struct.edge_rec** %650, align 4
+ store %struct.edge_rec* %651, %struct.edge_rec** %648, align 4
+ %652 = load %struct.edge_rec** %632, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %653 = load %struct.edge_rec** %640, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %652, %struct.edge_rec** %640, align 4
+ store %struct.edge_rec* %653, %struct.edge_rec** %632, align 4
+ %654 = add i32 %630, 48 ; <i32> [#uses=1]
+ %655 = and i32 %654, 63 ; <i32> [#uses=1]
+ %656 = and i32 %598, -64 ; <i32> [#uses=1]
+ %657 = or i32 %655, %656 ; <i32> [#uses=1]
+ %658 = inttoptr i32 %657 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %659 = getelementptr %struct.edge_rec* %658, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %660 = load %struct.edge_rec** %659, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %661 = ptrtoint %struct.edge_rec* %660 to i32 ; <i32> [#uses=2]
+ %662 = add i32 %661, 16 ; <i32> [#uses=1]
+ %663 = and i32 %662, 63 ; <i32> [#uses=1]
+ %664 = and i32 %661, -64 ; <i32> [#uses=1]
+ %665 = or i32 %663, %664 ; <i32> [#uses=1]
+ %666 = inttoptr i32 %665 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ br label %bb9.i
+
+bb25.i: ; preds = %bb23.i, %bb22.i
+ %667 = add i32 %172, 16 ; <i32> [#uses=1]
+ %668 = and i32 %667, 63 ; <i32> [#uses=1]
+ %669 = and i32 %172, -64 ; <i32> [#uses=1]
+ %670 = or i32 %668, %669 ; <i32> [#uses=1]
+ %671 = inttoptr i32 %670 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %672 = getelementptr %struct.edge_rec* %671, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %673 = load %struct.edge_rec** %672, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %674 = ptrtoint %struct.edge_rec* %673 to i32 ; <i32> [#uses=2]
+ %675 = add i32 %674, 16 ; <i32> [#uses=1]
+ %676 = and i32 %675, 63 ; <i32> [#uses=1]
+ %677 = and i32 %674, -64 ; <i32> [#uses=1]
+ %678 = or i32 %676, %677 ; <i32> [#uses=1]
+ %679 = inttoptr i32 %678 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %680 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4]
+ %681 = getelementptr %struct.edge_rec* %680, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=5]
+ store %struct.edge_rec* %680, %struct.edge_rec** %681, align 4
+ %682 = getelementptr %struct.edge_rec* %680, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ store %struct.VERTEX* %501, %struct.VERTEX** %682, align 4
+ %683 = ptrtoint %struct.edge_rec* %680 to i32 ; <i32> [#uses=4]
+ %684 = add i32 %683, 16 ; <i32> [#uses=1]
+ %685 = inttoptr i32 %684 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %686 = add i32 %683, 48 ; <i32> [#uses=1]
+ %687 = inttoptr i32 %686 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %688 = getelementptr %struct.edge_rec* %685, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %687, %struct.edge_rec** %688, align 4
+ %689 = add i32 %683, 32 ; <i32> [#uses=1]
+ %690 = inttoptr i32 %689 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3]
+ %691 = getelementptr %struct.edge_rec* %690, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %690, %struct.edge_rec** %691, align 4
+ %692 = getelementptr %struct.edge_rec* %690, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ store %struct.VERTEX* %496, %struct.VERTEX** %692, align 4
+ %693 = getelementptr %struct.edge_rec* %687, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %685, %struct.edge_rec** %693, align 4
+ %694 = load %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %695 = ptrtoint %struct.edge_rec* %694 to i32 ; <i32> [#uses=2]
+ %696 = add i32 %695, 16 ; <i32> [#uses=1]
+ %697 = and i32 %696, 63 ; <i32> [#uses=1]
+ %698 = and i32 %695, -64 ; <i32> [#uses=1]
+ %699 = or i32 %697, %698 ; <i32> [#uses=1]
+ %700 = inttoptr i32 %699 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %701 = getelementptr %struct.edge_rec* %499, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %702 = load %struct.edge_rec** %701, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %703 = ptrtoint %struct.edge_rec* %702 to i32 ; <i32> [#uses=2]
+ %704 = add i32 %703, 16 ; <i32> [#uses=1]
+ %705 = and i32 %704, 63 ; <i32> [#uses=1]
+ %706 = and i32 %703, -64 ; <i32> [#uses=1]
+ %707 = or i32 %705, %706 ; <i32> [#uses=1]
+ %708 = inttoptr i32 %707 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %709 = getelementptr %struct.edge_rec* %708, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %710 = load %struct.edge_rec** %709, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %711 = getelementptr %struct.edge_rec* %700, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %712 = load %struct.edge_rec** %711, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %710, %struct.edge_rec** %711, align 4
+ store %struct.edge_rec* %712, %struct.edge_rec** %709, align 4
+ %713 = load %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %714 = load %struct.edge_rec** %701, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %713, %struct.edge_rec** %701, align 4
+ store %struct.edge_rec* %714, %struct.edge_rec** %681, align 4
+ %715 = xor i32 %683, 32 ; <i32> [#uses=1]
+ %716 = inttoptr i32 %715 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %717 = getelementptr %struct.edge_rec* %716, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %718 = load %struct.edge_rec** %717, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %719 = ptrtoint %struct.edge_rec* %718 to i32 ; <i32> [#uses=2]
+ %720 = add i32 %719, 16 ; <i32> [#uses=1]
+ %721 = and i32 %720, 63 ; <i32> [#uses=1]
+ %722 = and i32 %719, -64 ; <i32> [#uses=1]
+ %723 = or i32 %721, %722 ; <i32> [#uses=1]
+ %724 = inttoptr i32 %723 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %725 = getelementptr %struct.edge_rec* %679, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %726 = load %struct.edge_rec** %725, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %727 = ptrtoint %struct.edge_rec* %726 to i32 ; <i32> [#uses=2]
+ %728 = add i32 %727, 16 ; <i32> [#uses=1]
+ %729 = and i32 %728, 63 ; <i32> [#uses=1]
+ %730 = and i32 %727, -64 ; <i32> [#uses=1]
+ %731 = or i32 %729, %730 ; <i32> [#uses=1]
+ %732 = inttoptr i32 %731 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %733 = getelementptr %struct.edge_rec* %732, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %734 = load %struct.edge_rec** %733, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %735 = getelementptr %struct.edge_rec* %724, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %736 = load %struct.edge_rec** %735, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %734, %struct.edge_rec** %735, align 4
+ store %struct.edge_rec* %736, %struct.edge_rec** %733, align 4
+ %737 = load %struct.edge_rec** %717, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %738 = load %struct.edge_rec** %725, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %737, %struct.edge_rec** %725, align 4
+ store %struct.edge_rec* %738, %struct.edge_rec** %717, align 4
+ %739 = load %struct.edge_rec** %681, align 4 ; <%struct.edge_rec*> [#uses=1]
+ br label %bb9.i
+
+do_merge.exit: ; preds = %bb17.i
+ %740 = getelementptr %struct.edge_rec* %ldo_addr.0.ph.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %741 = load %struct.VERTEX** %740, align 4 ; <%struct.VERTEX*> [#uses=1]
+ %742 = icmp eq %struct.VERTEX* %741, %tree_addr.0.i ; <i1> [#uses=1]
+ br i1 %742, label %bb5.loopexit, label %bb2
+
+bb2: ; preds = %bb2, %do_merge.exit
+ %ldo.07 = phi %struct.edge_rec* [ %747, %bb2 ], [ %ldo_addr.0.ph.i, %do_merge.exit ] ; <%struct.edge_rec*> [#uses=1]
+ %743 = ptrtoint %struct.edge_rec* %ldo.07 to i32 ; <i32> [#uses=1]
+ %744 = xor i32 %743, 32 ; <i32> [#uses=1]
+ %745 = inttoptr i32 %744 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %746 = getelementptr %struct.edge_rec* %745, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %747 = load %struct.edge_rec** %746, align 4 ; <%struct.edge_rec*> [#uses=3]
+ %748 = getelementptr %struct.edge_rec* %747, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %749 = load %struct.VERTEX** %748, align 4 ; <%struct.VERTEX*> [#uses=1]
+ %750 = icmp eq %struct.VERTEX* %749, %tree_addr.0.i ; <i1> [#uses=1]
+ br i1 %750, label %bb5.loopexit, label %bb2
+
+bb4: ; preds = %bb5.loopexit, %bb4
+ %rdo.05 = phi %struct.edge_rec* [ %755, %bb4 ], [ %rdo_addr.0.i, %bb5.loopexit ] ; <%struct.edge_rec*> [#uses=1]
+ %751 = getelementptr %struct.edge_rec* %rdo.05, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %752 = load %struct.edge_rec** %751, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %753 = ptrtoint %struct.edge_rec* %752 to i32 ; <i32> [#uses=1]
+ %754 = xor i32 %753, 32 ; <i32> [#uses=1]
+ %755 = inttoptr i32 %754 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3]
+ %756 = getelementptr %struct.edge_rec* %755, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %757 = load %struct.VERTEX** %756, align 4 ; <%struct.VERTEX*> [#uses=1]
+ %758 = icmp eq %struct.VERTEX* %757, %extra ; <i1> [#uses=1]
+ br i1 %758, label %bb6, label %bb4
+
+bb5.loopexit: ; preds = %bb2, %do_merge.exit
+ %ldo.0.lcssa = phi %struct.edge_rec* [ %ldo_addr.0.ph.i, %do_merge.exit ], [ %747, %bb2 ] ; <%struct.edge_rec*> [#uses=1]
+ %759 = getelementptr %struct.edge_rec* %rdo_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %760 = load %struct.VERTEX** %759, align 4 ; <%struct.VERTEX*> [#uses=1]
+ %761 = icmp eq %struct.VERTEX* %760, %extra ; <i1> [#uses=1]
+ br i1 %761, label %bb6, label %bb4
+
+bb6: ; preds = %bb5.loopexit, %bb4
+ %rdo.0.lcssa = phi %struct.edge_rec* [ %rdo_addr.0.i, %bb5.loopexit ], [ %755, %bb4 ] ; <%struct.edge_rec*> [#uses=1]
+ %tmp16 = ptrtoint %struct.edge_rec* %ldo.0.lcssa to i32 ; <i32> [#uses=1]
+ %tmp4 = ptrtoint %struct.edge_rec* %rdo.0.lcssa to i32 ; <i32> [#uses=1]
+ br label %bb15
+
+bb7: ; preds = %bb
+ %762 = getelementptr %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1]
+ %763 = load %struct.VERTEX** %762, align 4 ; <%struct.VERTEX*> [#uses=4]
+ %764 = icmp eq %struct.VERTEX* %763, null ; <i1> [#uses=1]
+ %765 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5]
+ %766 = getelementptr %struct.edge_rec* %765, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4]
+ store %struct.edge_rec* %765, %struct.edge_rec** %766, align 4
+ %767 = getelementptr %struct.edge_rec* %765, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3]
+ br i1 %764, label %bb10, label %bb11
+
+bb8: ; preds = %entry
+ %768 = call arm_apcscc i32 @puts(i8* getelementptr ([21 x i8]* @_2E_str7, i32 0, i32 0)) nounwind ; <i32> [#uses=0]
+ call arm_apcscc void @exit(i32 -1) noreturn nounwind
+ unreachable
+
+bb10: ; preds = %bb7
+ store %struct.VERTEX* %tree, %struct.VERTEX** %767, align 4
+ %769 = ptrtoint %struct.edge_rec* %765 to i32 ; <i32> [#uses=5]
+ %770 = add i32 %769, 16 ; <i32> [#uses=1]
+ %771 = inttoptr i32 %770 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %772 = add i32 %769, 48 ; <i32> [#uses=1]
+ %773 = inttoptr i32 %772 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %774 = getelementptr %struct.edge_rec* %771, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %773, %struct.edge_rec** %774, align 4
+ %775 = add i32 %769, 32 ; <i32> [#uses=1]
+ %776 = inttoptr i32 %775 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3]
+ %777 = getelementptr %struct.edge_rec* %776, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %776, %struct.edge_rec** %777, align 4
+ %778 = getelementptr %struct.edge_rec* %776, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ store %struct.VERTEX* %extra, %struct.VERTEX** %778, align 4
+ %779 = getelementptr %struct.edge_rec* %773, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %771, %struct.edge_rec** %779, align 4
+ %780 = xor i32 %769, 32 ; <i32> [#uses=1]
+ br label %bb15
+
+bb11: ; preds = %bb7
+ store %struct.VERTEX* %763, %struct.VERTEX** %767, align 4
+ %781 = ptrtoint %struct.edge_rec* %765 to i32 ; <i32> [#uses=6]
+ %782 = add i32 %781, 16 ; <i32> [#uses=1]
+ %783 = inttoptr i32 %782 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %784 = add i32 %781, 48 ; <i32> [#uses=1]
+ %785 = inttoptr i32 %784 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %786 = getelementptr %struct.edge_rec* %783, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %785, %struct.edge_rec** %786, align 4
+ %787 = add i32 %781, 32 ; <i32> [#uses=1]
+ %788 = inttoptr i32 %787 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3]
+ %789 = getelementptr %struct.edge_rec* %788, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %788, %struct.edge_rec** %789, align 4
+ %790 = getelementptr %struct.edge_rec* %788, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ store %struct.VERTEX* %tree, %struct.VERTEX** %790, align 4
+ %791 = getelementptr %struct.edge_rec* %785, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %783, %struct.edge_rec** %791, align 4
+ %792 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4]
+ %793 = getelementptr %struct.edge_rec* %792, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4]
+ store %struct.edge_rec* %792, %struct.edge_rec** %793, align 4
+ %794 = getelementptr %struct.edge_rec* %792, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ store %struct.VERTEX* %tree, %struct.VERTEX** %794, align 4
+ %795 = ptrtoint %struct.edge_rec* %792 to i32 ; <i32> [#uses=5]
+ %796 = add i32 %795, 16 ; <i32> [#uses=1]
+ %797 = inttoptr i32 %796 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %798 = add i32 %795, 48 ; <i32> [#uses=2]
+ %799 = inttoptr i32 %798 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %800 = getelementptr %struct.edge_rec* %797, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %799, %struct.edge_rec** %800, align 4
+ %801 = add i32 %795, 32 ; <i32> [#uses=1]
+ %802 = inttoptr i32 %801 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3]
+ %803 = getelementptr %struct.edge_rec* %802, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %802, %struct.edge_rec** %803, align 4
+ %804 = getelementptr %struct.edge_rec* %802, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ store %struct.VERTEX* %extra, %struct.VERTEX** %804, align 4
+ %805 = getelementptr %struct.edge_rec* %799, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %797, %struct.edge_rec** %805, align 4
+ %806 = xor i32 %781, 32 ; <i32> [#uses=1]
+ %807 = inttoptr i32 %806 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %808 = getelementptr %struct.edge_rec* %807, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %809 = load %struct.edge_rec** %808, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %810 = ptrtoint %struct.edge_rec* %809 to i32 ; <i32> [#uses=2]
+ %811 = add i32 %810, 16 ; <i32> [#uses=1]
+ %812 = and i32 %811, 63 ; <i32> [#uses=1]
+ %813 = and i32 %810, -64 ; <i32> [#uses=1]
+ %814 = or i32 %812, %813 ; <i32> [#uses=1]
+ %815 = inttoptr i32 %814 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %816 = load %struct.edge_rec** %793, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %817 = ptrtoint %struct.edge_rec* %816 to i32 ; <i32> [#uses=2]
+ %818 = add i32 %817, 16 ; <i32> [#uses=1]
+ %819 = and i32 %818, 63 ; <i32> [#uses=1]
+ %820 = and i32 %817, -64 ; <i32> [#uses=1]
+ %821 = or i32 %819, %820 ; <i32> [#uses=1]
+ %822 = inttoptr i32 %821 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %823 = getelementptr %struct.edge_rec* %822, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %824 = load %struct.edge_rec** %823, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %825 = getelementptr %struct.edge_rec* %815, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %826 = load %struct.edge_rec** %825, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %824, %struct.edge_rec** %825, align 4
+ store %struct.edge_rec* %826, %struct.edge_rec** %823, align 4
+ %827 = load %struct.edge_rec** %808, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %828 = load %struct.edge_rec** %793, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %827, %struct.edge_rec** %793, align 4
+ store %struct.edge_rec* %828, %struct.edge_rec** %808, align 4
+ %829 = xor i32 %795, 32 ; <i32> [#uses=3]
+ %830 = inttoptr i32 %829 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %831 = getelementptr %struct.edge_rec* %830, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ %832 = load %struct.VERTEX** %831, align 4 ; <%struct.VERTEX*> [#uses=1]
+ %833 = and i32 %798, 63 ; <i32> [#uses=1]
+ %834 = and i32 %795, -64 ; <i32> [#uses=1]
+ %835 = or i32 %833, %834 ; <i32> [#uses=1]
+ %836 = inttoptr i32 %835 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %837 = getelementptr %struct.edge_rec* %836, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %838 = load %struct.edge_rec** %837, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %839 = ptrtoint %struct.edge_rec* %838 to i32 ; <i32> [#uses=2]
+ %840 = add i32 %839, 16 ; <i32> [#uses=1]
+ %841 = and i32 %840, 63 ; <i32> [#uses=1]
+ %842 = and i32 %839, -64 ; <i32> [#uses=1]
+ %843 = or i32 %841, %842 ; <i32> [#uses=1]
+ %844 = inttoptr i32 %843 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %845 = load %struct.VERTEX** %767, align 4 ; <%struct.VERTEX*> [#uses=1]
+ %846 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4]
+ %847 = getelementptr %struct.edge_rec* %846, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=7]
+ store %struct.edge_rec* %846, %struct.edge_rec** %847, align 4
+ %848 = getelementptr %struct.edge_rec* %846, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ store %struct.VERTEX* %832, %struct.VERTEX** %848, align 4
+ %849 = ptrtoint %struct.edge_rec* %846 to i32 ; <i32> [#uses=6]
+ %850 = add i32 %849, 16 ; <i32> [#uses=2]
+ %851 = inttoptr i32 %850 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %852 = add i32 %849, 48 ; <i32> [#uses=1]
+ %853 = inttoptr i32 %852 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %854 = getelementptr %struct.edge_rec* %851, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %853, %struct.edge_rec** %854, align 4
+ %855 = add i32 %849, 32 ; <i32> [#uses=1]
+ %856 = inttoptr i32 %855 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=3]
+ %857 = getelementptr %struct.edge_rec* %856, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %856, %struct.edge_rec** %857, align 4
+ %858 = getelementptr %struct.edge_rec* %856, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1]
+ store %struct.VERTEX* %845, %struct.VERTEX** %858, align 4
+ %859 = getelementptr %struct.edge_rec* %853, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %851, %struct.edge_rec** %859, align 4
+ %860 = load %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %861 = ptrtoint %struct.edge_rec* %860 to i32 ; <i32> [#uses=2]
+ %862 = add i32 %861, 16 ; <i32> [#uses=1]
+ %863 = and i32 %862, 63 ; <i32> [#uses=1]
+ %864 = and i32 %861, -64 ; <i32> [#uses=1]
+ %865 = or i32 %863, %864 ; <i32> [#uses=1]
+ %866 = inttoptr i32 %865 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %867 = getelementptr %struct.edge_rec* %844, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %868 = load %struct.edge_rec** %867, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %869 = ptrtoint %struct.edge_rec* %868 to i32 ; <i32> [#uses=2]
+ %870 = add i32 %869, 16 ; <i32> [#uses=1]
+ %871 = and i32 %870, 63 ; <i32> [#uses=1]
+ %872 = and i32 %869, -64 ; <i32> [#uses=1]
+ %873 = or i32 %871, %872 ; <i32> [#uses=1]
+ %874 = inttoptr i32 %873 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %875 = getelementptr %struct.edge_rec* %874, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %876 = load %struct.edge_rec** %875, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %877 = getelementptr %struct.edge_rec* %866, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %878 = load %struct.edge_rec** %877, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %876, %struct.edge_rec** %877, align 4
+ store %struct.edge_rec* %878, %struct.edge_rec** %875, align 4
+ %879 = load %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %880 = load %struct.edge_rec** %867, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %879, %struct.edge_rec** %867, align 4
+ store %struct.edge_rec* %880, %struct.edge_rec** %847, align 4
+ %881 = xor i32 %849, 32 ; <i32> [#uses=3]
+ %882 = inttoptr i32 %881 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %883 = getelementptr %struct.edge_rec* %882, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=6]
+ %884 = load %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %885 = ptrtoint %struct.edge_rec* %884 to i32 ; <i32> [#uses=2]
+ %886 = add i32 %885, 16 ; <i32> [#uses=1]
+ %887 = and i32 %886, 63 ; <i32> [#uses=1]
+ %888 = and i32 %885, -64 ; <i32> [#uses=1]
+ %889 = or i32 %887, %888 ; <i32> [#uses=1]
+ %890 = inttoptr i32 %889 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %891 = load %struct.edge_rec** %766, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %892 = ptrtoint %struct.edge_rec* %891 to i32 ; <i32> [#uses=2]
+ %893 = add i32 %892, 16 ; <i32> [#uses=1]
+ %894 = and i32 %893, 63 ; <i32> [#uses=1]
+ %895 = and i32 %892, -64 ; <i32> [#uses=1]
+ %896 = or i32 %894, %895 ; <i32> [#uses=1]
+ %897 = inttoptr i32 %896 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %898 = getelementptr %struct.edge_rec* %897, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %899 = load %struct.edge_rec** %898, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %900 = getelementptr %struct.edge_rec* %890, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %901 = load %struct.edge_rec** %900, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %899, %struct.edge_rec** %900, align 4
+ store %struct.edge_rec* %901, %struct.edge_rec** %898, align 4
+ %902 = load %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %903 = load %struct.edge_rec** %766, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %902, %struct.edge_rec** %766, align 4
+ store %struct.edge_rec* %903, %struct.edge_rec** %883, align 4
+ %904 = getelementptr %struct.VERTEX* %763, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %905 = load double* %904, align 4 ; <double> [#uses=2]
+ %906 = getelementptr %struct.VERTEX* %763, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %907 = load double* %906, align 4 ; <double> [#uses=2]
+ %908 = getelementptr %struct.VERTEX* %extra, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %909 = load double* %908, align 4 ; <double> [#uses=3]
+ %910 = getelementptr %struct.VERTEX* %extra, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %911 = load double* %910, align 4 ; <double> [#uses=3]
+ %912 = getelementptr %struct.VERTEX* %tree, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %913 = load double* %912, align 4 ; <double> [#uses=3]
+ %914 = getelementptr %struct.VERTEX* %tree, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %915 = load double* %914, align 4 ; <double> [#uses=3]
+ %916 = fsub double %905, %913 ; <double> [#uses=1]
+ %917 = fsub double %911, %915 ; <double> [#uses=1]
+ %918 = fmul double %916, %917 ; <double> [#uses=1]
+ %919 = fsub double %909, %913 ; <double> [#uses=1]
+ %920 = fsub double %907, %915 ; <double> [#uses=1]
+ %921 = fmul double %919, %920 ; <double> [#uses=1]
+ %922 = fsub double %918, %921 ; <double> [#uses=1]
+ %923 = fcmp ogt double %922, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %923, label %bb15, label %bb13
+
+bb13: ; preds = %bb11
+ %924 = fsub double %905, %909 ; <double> [#uses=1]
+ %925 = fsub double %915, %911 ; <double> [#uses=1]
+ %926 = fmul double %924, %925 ; <double> [#uses=1]
+ %927 = fsub double %913, %909 ; <double> [#uses=1]
+ %928 = fsub double %907, %911 ; <double> [#uses=1]
+ %929 = fmul double %927, %928 ; <double> [#uses=1]
+ %930 = fsub double %926, %929 ; <double> [#uses=1]
+ %931 = fcmp ogt double %930, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %931, label %bb15, label %bb14
+
+bb14: ; preds = %bb13
+ %932 = and i32 %850, 63 ; <i32> [#uses=1]
+ %933 = and i32 %849, -64 ; <i32> [#uses=3]
+ %934 = or i32 %932, %933 ; <i32> [#uses=1]
+ %935 = inttoptr i32 %934 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %936 = getelementptr %struct.edge_rec* %935, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %937 = load %struct.edge_rec** %936, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %938 = ptrtoint %struct.edge_rec* %937 to i32 ; <i32> [#uses=2]
+ %939 = add i32 %938, 16 ; <i32> [#uses=1]
+ %940 = and i32 %939, 63 ; <i32> [#uses=1]
+ %941 = and i32 %938, -64 ; <i32> [#uses=1]
+ %942 = or i32 %940, %941 ; <i32> [#uses=1]
+ %943 = inttoptr i32 %942 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %944 = load %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %945 = ptrtoint %struct.edge_rec* %944 to i32 ; <i32> [#uses=2]
+ %946 = add i32 %945, 16 ; <i32> [#uses=1]
+ %947 = and i32 %946, 63 ; <i32> [#uses=1]
+ %948 = and i32 %945, -64 ; <i32> [#uses=1]
+ %949 = or i32 %947, %948 ; <i32> [#uses=1]
+ %950 = inttoptr i32 %949 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %951 = getelementptr %struct.edge_rec* %943, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %952 = load %struct.edge_rec** %951, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %953 = ptrtoint %struct.edge_rec* %952 to i32 ; <i32> [#uses=2]
+ %954 = add i32 %953, 16 ; <i32> [#uses=1]
+ %955 = and i32 %954, 63 ; <i32> [#uses=1]
+ %956 = and i32 %953, -64 ; <i32> [#uses=1]
+ %957 = or i32 %955, %956 ; <i32> [#uses=1]
+ %958 = inttoptr i32 %957 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %959 = getelementptr %struct.edge_rec* %958, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %960 = load %struct.edge_rec** %959, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %961 = getelementptr %struct.edge_rec* %950, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %962 = load %struct.edge_rec** %961, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %960, %struct.edge_rec** %961, align 4
+ store %struct.edge_rec* %962, %struct.edge_rec** %959, align 4
+ %963 = load %struct.edge_rec** %847, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %964 = load %struct.edge_rec** %951, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %963, %struct.edge_rec** %951, align 4
+ store %struct.edge_rec* %964, %struct.edge_rec** %847, align 4
+ %965 = add i32 %881, 16 ; <i32> [#uses=1]
+ %966 = and i32 %965, 63 ; <i32> [#uses=1]
+ %967 = or i32 %966, %933 ; <i32> [#uses=1]
+ %968 = inttoptr i32 %967 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %969 = getelementptr %struct.edge_rec* %968, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ %970 = load %struct.edge_rec** %969, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %971 = ptrtoint %struct.edge_rec* %970 to i32 ; <i32> [#uses=2]
+ %972 = add i32 %971, 16 ; <i32> [#uses=1]
+ %973 = and i32 %972, 63 ; <i32> [#uses=1]
+ %974 = and i32 %971, -64 ; <i32> [#uses=1]
+ %975 = or i32 %973, %974 ; <i32> [#uses=1]
+ %976 = inttoptr i32 %975 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %977 = load %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %978 = ptrtoint %struct.edge_rec* %977 to i32 ; <i32> [#uses=2]
+ %979 = add i32 %978, 16 ; <i32> [#uses=1]
+ %980 = and i32 %979, 63 ; <i32> [#uses=1]
+ %981 = and i32 %978, -64 ; <i32> [#uses=1]
+ %982 = or i32 %980, %981 ; <i32> [#uses=1]
+ %983 = inttoptr i32 %982 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %984 = getelementptr %struct.edge_rec* %976, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=3]
+ %985 = load %struct.edge_rec** %984, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %986 = ptrtoint %struct.edge_rec* %985 to i32 ; <i32> [#uses=2]
+ %987 = add i32 %986, 16 ; <i32> [#uses=1]
+ %988 = and i32 %987, 63 ; <i32> [#uses=1]
+ %989 = and i32 %986, -64 ; <i32> [#uses=1]
+ %990 = or i32 %988, %989 ; <i32> [#uses=1]
+ %991 = inttoptr i32 %990 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1]
+ %992 = getelementptr %struct.edge_rec* %991, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %993 = load %struct.edge_rec** %992, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %994 = getelementptr %struct.edge_rec* %983, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=2]
+ %995 = load %struct.edge_rec** %994, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %993, %struct.edge_rec** %994, align 4
+ store %struct.edge_rec* %995, %struct.edge_rec** %992, align 4
+ %996 = load %struct.edge_rec** %883, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %997 = load %struct.edge_rec** %984, align 4 ; <%struct.edge_rec*> [#uses=1]
+ store %struct.edge_rec* %996, %struct.edge_rec** %984, align 4
+ store %struct.edge_rec* %997, %struct.edge_rec** %883, align 4
+ %998 = inttoptr i32 %933 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=2]
+ %999 = load %struct.edge_rec** @avail_edge, align 4 ; <%struct.edge_rec*> [#uses=1]
+ %1000 = getelementptr %struct.edge_rec* %998, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1]
+ store %struct.edge_rec* %999, %struct.edge_rec** %1000, align 4
+ store %struct.edge_rec* %998, %struct.edge_rec** @avail_edge, align 4
+ br label %bb15
+
+bb15: ; preds = %bb14, %bb13, %bb11, %bb10, %bb6
+ %retval.1.0 = phi i32 [ %780, %bb10 ], [ %829, %bb13 ], [ %829, %bb14 ], [ %tmp4, %bb6 ], [ %849, %bb11 ] ; <i32> [#uses=1]
+ %retval.0.0 = phi i32 [ %769, %bb10 ], [ %781, %bb13 ], [ %781, %bb14 ], [ %tmp16, %bb6 ], [ %881, %bb11 ] ; <i32> [#uses=1]
+ %agg.result162 = bitcast %struct.EDGE_PAIR* %agg.result to i64* ; <i64*> [#uses=1]
+ %1001 = zext i32 %retval.0.0 to i64 ; <i64> [#uses=1]
+ %1002 = zext i32 %retval.1.0 to i64 ; <i64> [#uses=1]
+ %1003 = shl i64 %1002, 32 ; <i64> [#uses=1]
+ %1004 = or i64 %1003, %1001 ; <i64> [#uses=1]
+ store i64 %1004, i64* %agg.result162, align 4
+ ret void
+}
+
+declare arm_apcscc i32 @puts(i8* nocapture) nounwind
+
+declare arm_apcscc void @exit(i32) noreturn nounwind
+
+declare arm_apcscc %struct.edge_rec* @alloc_edge() nounwind
diff --git a/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll b/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll
new file mode 100644
index 0000000..b4b989b
--- /dev/null
+++ b/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll
@@ -0,0 +1,94 @@
+; RUN: llc < %s -mtriple=armv6-apple-darwin10
+
+ %struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* }
+ %struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* }
+ %struct.cli_ac_patt = type { i16*, i16*, i16, i16, i8, i32, i32, i8*, i8*, i32, i16, i16, i16, i16, %struct.cli_ac_alt**, i8, i16, %struct.cli_ac_patt*, %struct.cli_ac_patt* }
+ %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 }
+ %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 }
+
+declare arm_apcscc i32 @strlen(i8* nocapture) nounwind readonly
+
+define arm_apcscc i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind {
+entry:
+ br i1 undef, label %bb126, label %bb1
+
+bb1: ; preds = %entry
+ br i1 undef, label %cli_calloc.exit.thread, label %cli_calloc.exit
+
+cli_calloc.exit.thread: ; preds = %bb1
+ ret i32 -114
+
+cli_calloc.exit: ; preds = %bb1
+ store i16 %parts, i16* undef, align 4
+ br i1 undef, label %bb52, label %bb4
+
+bb4: ; preds = %cli_calloc.exit
+ br i1 undef, label %bb.i, label %bb1.i3
+
+bb.i: ; preds = %bb4
+ unreachable
+
+bb1.i3: ; preds = %bb4
+ br i1 undef, label %bb2.i4, label %cli_strdup.exit
+
+bb2.i4: ; preds = %bb1.i3
+ ret i32 -114
+
+cli_strdup.exit: ; preds = %bb1.i3
+ br i1 undef, label %cli_calloc.exit54.thread, label %cli_calloc.exit54
+
+cli_calloc.exit54.thread: ; preds = %cli_strdup.exit
+ ret i32 -114
+
+cli_calloc.exit54: ; preds = %cli_strdup.exit
+ br label %bb45
+
+cli_calloc.exit70.thread: ; preds = %bb45
+ unreachable
+
+cli_calloc.exit70: ; preds = %bb45
+ br i1 undef, label %bb.i83, label %bb1.i84
+
+bb.i83: ; preds = %cli_calloc.exit70
+ unreachable
+
+bb1.i84: ; preds = %cli_calloc.exit70
+ br i1 undef, label %bb2.i85, label %bb17
+
+bb2.i85: ; preds = %bb1.i84
+ unreachable
+
+bb17: ; preds = %bb1.i84
+ br i1 undef, label %bb22, label %bb.nph
+
+bb.nph: ; preds = %bb17
+ br label %bb18
+
+bb18: ; preds = %bb18, %bb.nph
+ br i1 undef, label %bb18, label %bb22
+
+bb22: ; preds = %bb18, %bb17
+ br i1 undef, label %bb25, label %bb43.preheader
+
+bb43.preheader: ; preds = %bb22
+ br i1 undef, label %bb28, label %bb45
+
+bb25: ; preds = %bb22
+ unreachable
+
+bb28: ; preds = %bb43.preheader
+ unreachable
+
+bb45: ; preds = %bb43.preheader, %cli_calloc.exit54
+ br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70
+
+bb52: ; preds = %cli_calloc.exit
+ %0 = load i16* undef, align 4 ; <i16> [#uses=1]
+ %1 = icmp eq i16 %0, 0 ; <i1> [#uses=1]
+ %iftmp.20.0 = select i1 %1, i8* %hexsig, i8* null ; <i8*> [#uses=1]
+ %2 = tail call arm_apcscc i32 @strlen(i8* %iftmp.20.0) nounwind readonly ; <i32> [#uses=0]
+ unreachable
+
+bb126: ; preds = %entry
+ ret i32 -117
+}
diff --git a/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll b/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
new file mode 100644
index 0000000..24f4990
--- /dev/null
+++ b/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
@@ -0,0 +1,95 @@
+; RUN: llc < %s -march=arm
+
+ %struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* }
+ %struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* }
+ %struct.cli_ac_patt = type { i16*, i16*, i16, i16, i8, i32, i32, i8*, i8*, i32, i16, i16, i16, i16, %struct.cli_ac_alt**, i8, i16, %struct.cli_ac_patt*, %struct.cli_ac_patt* }
+ %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 }
+ %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 }
+
+define arm_apcscc i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind {
+entry:
+ br i1 undef, label %bb126, label %bb1
+
+bb1: ; preds = %entry
+ br i1 undef, label %cli_calloc.exit.thread, label %cli_calloc.exit
+
+cli_calloc.exit.thread: ; preds = %bb1
+ ret i32 -114
+
+cli_calloc.exit: ; preds = %bb1
+ br i1 undef, label %bb52, label %bb4
+
+bb4: ; preds = %cli_calloc.exit
+ br i1 undef, label %bb.i, label %bb1.i3
+
+bb.i: ; preds = %bb4
+ unreachable
+
+bb1.i3: ; preds = %bb4
+ br i1 undef, label %bb2.i4, label %cli_strdup.exit
+
+bb2.i4: ; preds = %bb1.i3
+ ret i32 -114
+
+cli_strdup.exit: ; preds = %bb1.i3
+ br i1 undef, label %cli_calloc.exit54.thread, label %cli_calloc.exit54
+
+cli_calloc.exit54.thread: ; preds = %cli_strdup.exit
+ ret i32 -114
+
+cli_calloc.exit54: ; preds = %cli_strdup.exit
+ br label %bb45
+
+cli_calloc.exit70.thread: ; preds = %bb45
+ unreachable
+
+cli_calloc.exit70: ; preds = %bb45
+ br i1 undef, label %bb.i83, label %bb1.i84
+
+bb.i83: ; preds = %cli_calloc.exit70
+ unreachable
+
+bb1.i84: ; preds = %cli_calloc.exit70
+ br i1 undef, label %bb2.i85, label %bb17
+
+bb2.i85: ; preds = %bb1.i84
+ unreachable
+
+bb17: ; preds = %bb1.i84
+ br i1 undef, label %bb22, label %bb.nph
+
+bb.nph: ; preds = %bb17
+ br label %bb18
+
+bb18: ; preds = %bb18, %bb.nph
+ br i1 undef, label %bb18, label %bb22
+
+bb22: ; preds = %bb18, %bb17
+ %0 = getelementptr i8* null, i32 10 ; <i8*> [#uses=1]
+ %1 = bitcast i8* %0 to i16* ; <i16*> [#uses=1]
+ %2 = load i16* %1, align 2 ; <i16> [#uses=1]
+ %3 = add i16 %2, 1 ; <i16> [#uses=1]
+ %4 = zext i16 %3 to i32 ; <i32> [#uses=1]
+ %5 = mul i32 %4, 3 ; <i32> [#uses=1]
+ %6 = add i32 %5, -1 ; <i32> [#uses=1]
+ %7 = icmp eq i32 %6, undef ; <i1> [#uses=1]
+ br i1 %7, label %bb25, label %bb43.preheader
+
+bb43.preheader: ; preds = %bb22
+ br i1 undef, label %bb28, label %bb45
+
+bb25: ; preds = %bb22
+ unreachable
+
+bb28: ; preds = %bb43.preheader
+ unreachable
+
+bb45: ; preds = %bb43.preheader, %cli_calloc.exit54
+ br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70
+
+bb52: ; preds = %cli_calloc.exit
+ unreachable
+
+bb126: ; preds = %entry
+ ret i32 -117
+}
diff --git a/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll b/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll
new file mode 100644
index 0000000..e1d19d1
--- /dev/null
+++ b/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll
@@ -0,0 +1,108 @@
+; RUN: llc < %s -mtriple=armv7-apple-darwin10 -mattr=+vfp3
+
+@a = external global double ; <double*> [#uses=1]
+
+declare double @llvm.exp.f64(double) nounwind readonly
+
+define arm_apcscc void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind {
+entry:
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ br i1 undef, label %bb28, label %bb
+
+bb28: ; preds = %bb
+ %0 = load double* @a, align 4 ; <double> [#uses=2]
+ %1 = fadd double %0, undef ; <double> [#uses=2]
+ br i1 undef, label %bb59, label %bb60
+
+bb59: ; preds = %bb28
+ %2 = fsub double -0.000000e+00, undef ; <double> [#uses=2]
+ br label %bb61
+
+bb60: ; preds = %bb28
+ %3 = tail call double @llvm.exp.f64(double undef) nounwind ; <double> [#uses=1]
+ %4 = fsub double -0.000000e+00, %3 ; <double> [#uses=2]
+ %5 = fsub double -0.000000e+00, undef ; <double> [#uses=1]
+ %6 = fsub double -0.000000e+00, undef ; <double> [#uses=1]
+ br label %bb61
+
+bb61: ; preds = %bb60, %bb59
+ %.pn201 = phi double [ undef, %bb59 ], [ undef, %bb60 ] ; <double> [#uses=1]
+ %.pn111 = phi double [ undef, %bb59 ], [ undef, %bb60 ] ; <double> [#uses=1]
+ %.pn452 = phi double [ undef, %bb59 ], [ undef, %bb60 ] ; <double> [#uses=1]
+ %.pn85 = phi double [ undef, %bb59 ], [ undef, %bb60 ] ; <double> [#uses=1]
+ %.pn238 = phi double [ 0.000000e+00, %bb59 ], [ 0.000000e+00, %bb60 ] ; <double> [#uses=1]
+ %.pn39 = phi double [ undef, %bb59 ], [ undef, %bb60 ] ; <double> [#uses=1]
+ %.pn230 = phi double [ undef, %bb59 ], [ undef, %bb60 ] ; <double> [#uses=1]
+ %.pn228 = phi double [ 0.000000e+00, %bb59 ], [ undef, %bb60 ] ; <double> [#uses=1]
+ %.pn224 = phi double [ undef, %bb59 ], [ undef, %bb60 ] ; <double> [#uses=1]
+ %.pn222 = phi double [ 0.000000e+00, %bb59 ], [ undef, %bb60 ] ; <double> [#uses=1]
+ %.pn218 = phi double [ %2, %bb59 ], [ %4, %bb60 ] ; <double> [#uses=1]
+ %.pn214 = phi double [ 0.000000e+00, %bb59 ], [ undef, %bb60 ] ; <double> [#uses=1]
+ %.pn212 = phi double [ %2, %bb59 ], [ %4, %bb60 ] ; <double> [#uses=1]
+ %.pn213 = phi double [ undef, %bb59 ], [ undef, %bb60 ] ; <double> [#uses=1]
+ %.pn210 = phi double [ undef, %bb59 ], [ %5, %bb60 ] ; <double> [#uses=1]
+ %.pn202 = phi double [ undef, %bb59 ], [ %6, %bb60 ] ; <double> [#uses=0]
+ %.pn390 = fdiv double %.pn452, undef ; <double> [#uses=0]
+ %.pn145 = fdiv double %.pn238, %1 ; <double> [#uses=0]
+ %.pn138 = fdiv double %.pn230, undef ; <double> [#uses=1]
+ %.pn139 = fdiv double %.pn228, undef ; <double> [#uses=1]
+ %.pn134 = fdiv double %.pn224, %0 ; <double> [#uses=1]
+ %.pn135 = fdiv double %.pn222, %1 ; <double> [#uses=1]
+ %.pn133 = fdiv double %.pn218, undef ; <double> [#uses=0]
+ %.pn128 = fdiv double %.pn214, undef ; <double> [#uses=1]
+ %.pn129 = fdiv double %.pn212, %.pn213 ; <double> [#uses=1]
+ %.pn126 = fdiv double %.pn210, undef ; <double> [#uses=0]
+ %.pn54.in = fmul double undef, %.pn201 ; <double> [#uses=1]
+ %.pn42.in = fmul double undef, undef ; <double> [#uses=1]
+ %.pn76 = fsub double %.pn138, %.pn139 ; <double> [#uses=1]
+ %.pn74 = fsub double %.pn134, %.pn135 ; <double> [#uses=1]
+ %.pn70 = fsub double %.pn128, %.pn129 ; <double> [#uses=1]
+ %.pn54 = fdiv double %.pn54.in, 6.000000e+00 ; <double> [#uses=1]
+ %.pn64 = fmul double undef, 0x3FE5555555555555 ; <double> [#uses=1]
+ %.pn65 = fmul double undef, undef ; <double> [#uses=1]
+ %.pn50 = fmul double undef, %.pn111 ; <double> [#uses=0]
+ %.pn42 = fdiv double %.pn42.in, 6.000000e+00 ; <double> [#uses=1]
+ %.pn40 = fmul double undef, %.pn85 ; <double> [#uses=0]
+ %.pn56 = fadd double %.pn76, undef ; <double> [#uses=1]
+ %.pn57 = fmul double %.pn74, undef ; <double> [#uses=1]
+ %.pn36 = fadd double undef, undef ; <double> [#uses=1]
+ %.pn37 = fmul double %.pn70, undef ; <double> [#uses=1]
+ %.pn33 = fmul double undef, 0x3FC5555555555555 ; <double> [#uses=1]
+ %.pn29 = fsub double %.pn64, %.pn65 ; <double> [#uses=1]
+ %.pn21 = fadd double undef, undef ; <double> [#uses=1]
+ %.pn27 = fmul double undef, 0x3FC5555555555555 ; <double> [#uses=1]
+ %.pn11 = fadd double %.pn56, %.pn57 ; <double> [#uses=1]
+ %.pn32 = fmul double %.pn54, undef ; <double> [#uses=1]
+ %.pn26 = fmul double %.pn42, undef ; <double> [#uses=1]
+ %.pn15 = fmul double 0.000000e+00, %.pn39 ; <double> [#uses=1]
+ %.pn7 = fadd double %.pn36, %.pn37 ; <double> [#uses=1]
+ %.pn30 = fsub double %.pn32, %.pn33 ; <double> [#uses=1]
+ %.pn28 = fadd double %.pn30, 0.000000e+00 ; <double> [#uses=1]
+ %.pn24 = fsub double %.pn28, %.pn29 ; <double> [#uses=1]
+ %.pn22 = fsub double %.pn26, %.pn27 ; <double> [#uses=1]
+ %.pn20 = fadd double %.pn24, undef ; <double> [#uses=1]
+ %.pn18 = fadd double %.pn22, 0.000000e+00 ; <double> [#uses=1]
+ %.pn16 = fsub double %.pn20, %.pn21 ; <double> [#uses=1]
+ %.pn14 = fsub double %.pn18, undef ; <double> [#uses=1]
+ %.pn12 = fadd double %.pn16, undef ; <double> [#uses=1]
+ %.pn10 = fadd double %.pn14, %.pn15 ; <double> [#uses=1]
+ %.pn8 = fsub double %.pn12, undef ; <double> [#uses=1]
+ %.pn6 = fsub double %.pn10, %.pn11 ; <double> [#uses=1]
+ %.pn4 = fadd double %.pn8, undef ; <double> [#uses=1]
+ %.pn2 = fadd double %.pn6, %.pn7 ; <double> [#uses=1]
+ %N1.0 = fsub double %.pn4, undef ; <double> [#uses=1]
+ %D1.0 = fsub double %.pn2, undef ; <double> [#uses=2]
+ br i1 undef, label %bb62, label %bb64
+
+bb62: ; preds = %bb61
+ %7 = fadd double %D1.0, undef ; <double> [#uses=1]
+ br label %bb64
+
+bb64: ; preds = %bb62, %bb61
+ %.pn = phi double [ undef, %bb62 ], [ %N1.0, %bb61 ] ; <double> [#uses=1]
+ %.pn1 = phi double [ %7, %bb62 ], [ %D1.0, %bb61 ] ; <double> [#uses=1]
+ %x.1 = fdiv double %.pn, %.pn1 ; <double> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll b/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
new file mode 100644
index 0000000..2d4e58d
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=arm -mattr=+neon
+; PR4657
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv7-apple-darwin9"
+
+define arm_apcscc <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind {
+entry:
+ %v_addr = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
+ %f_addr = alloca i32 ; <i32*> [#uses=2]
+ %retval = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
+ %0 = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store <4 x i32> %v, <4 x i32>* %v_addr
+ store i32 %f, i32* %f_addr
+ %1 = load <4 x i32>* %v_addr, align 16 ; <<4 x i32>> [#uses=1]
+ %2 = load i32* %f_addr, align 4 ; <i32> [#uses=1]
+ %3 = insertelement <4 x i32> undef, i32 %2, i32 0 ; <<4 x i32>> [#uses=1]
+ %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>> [#uses=1]
+ %5 = mul <4 x i32> %1, %4 ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %5, <4 x i32>* %0, align 16
+ %6 = load <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %6, <4 x i32>* %retval, align 16
+ br label %return
+
+return: ; preds = %entry
+ %retval1 = load <4 x i32>* %retval ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %retval1
+}
diff --git a/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll b/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll
new file mode 100644
index 0000000..65ffed2
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -mtriple=armv6-elf
+; PR4528
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv6-elf"
+
+define arm_aapcscc i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize {
+entry:
+ br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i
+
+bb5.i: ; preds = %entry
+ %asmtmp.i = tail call i32 asm sideeffect "1:\09strbt\09$1,[$2]\0A2:\0A\09.section .fixup,\22ax\22\0A\09.align\092\0A3:\09mov\09$0, $3\0A\09b\092b\0A\09.previous\0A\09.section __ex_table,\22a\22\0A\09.align\093\0A\09.long\091b, 3b\0A\09.previous", "=r,r,r,i,0,~{cc}"(i8 0, i32 undef, i32 -14, i32 0) nounwind ; <i32> [#uses=1]
+ %0 = icmp eq i32 %asmtmp.i, 0 ; <i1> [#uses=1]
+ br i1 %0, label %bb6.i, label %fault_in_pages_writeable.exit
+
+bb6.i: ; preds = %bb5.i
+ br i1 undef, label %fault_in_pages_writeable.exit, label %bb7.i
+
+bb7.i: ; preds = %bb6.i
+ unreachable
+
+fault_in_pages_writeable.exit: ; preds = %bb6.i, %bb5.i, %entry
+ br i1 undef, label %bb2, label %bb3
+
+bb2: ; preds = %fault_in_pages_writeable.exit
+ unreachable
+
+bb3: ; preds = %fault_in_pages_writeable.exit
+ %1 = tail call arm_aapcscc i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0]
+ unreachable
+}
+
+declare arm_aapcscc i32 @__copy_to_user(i8*, i8*, i32)
diff --git a/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll
new file mode 100644
index 0000000..9e5372a
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -mtriple=armv6-elf
+; PR4528
+
+define arm_aapcscc i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize {
+entry:
+ br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i
+
+bb5.i: ; preds = %entry
+ %asmtmp.i = tail call i32 asm sideeffect "1:\09strbt\09$1,[$2]\0A2:\0A\09.section .fixup,\22ax\22\0A\09.align\092\0A3:\09mov\09$0, $3\0A\09b\092b\0A\09.previous\0A\09.section __ex_table,\22a\22\0A\09.align\093\0A\09.long\091b, 3b\0A\09.previous", "=r,r,r,i,0,~{cc}"(i8 0, i32 undef, i32 -14, i32 0) nounwind ; <i32> [#uses=1]
+ br label %fault_in_pages_writeable.exit
+
+fault_in_pages_writeable.exit: ; preds = %bb5.i, %entry
+ %0 = phi i32 [ 0, %entry ], [ %asmtmp.i, %bb5.i ] ; <i32> [#uses=1]
+ %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %bb2, label %bb3
+
+bb2: ; preds = %fault_in_pages_writeable.exit
+ unreachable
+
+bb3: ; preds = %fault_in_pages_writeable.exit
+ %2 = tail call arm_aapcscc i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0]
+ unreachable
+}
+
+declare arm_aapcscc i32 @__copy_to_user(i8*, i8*, i32)
diff --git a/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll b/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
new file mode 100644
index 0000000..18d68f7
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=arm
+; PR4528
+
+; Inline asm is allowed to contain operands "=&r", "0".
+
+%struct.device_dma_parameters = type { i32, i32 }
+%struct.iovec = type { i8*, i32 }
+
+define arm_aapcscc i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize {
+entry:
+ br label %bb8
+
+bb: ; preds = %bb8
+ br i1 undef, label %bb10, label %bb2
+
+bb2: ; preds = %bb
+ %asmtmp = tail call %struct.device_dma_parameters asm "adds $1, $2, $3; sbcccs $1, $1, $0; movcc $0, #0", "=&r,=&r,r,Ir,0,~{cc}"(i8* undef, i32 undef, i32 0) nounwind; <%struct.device_dma_parameters> [#uses=1]
+ %asmresult = extractvalue %struct.device_dma_parameters %asmtmp, 0; <i32> [#uses=1]
+ %0 = icmp eq i32 %asmresult, 0 ; <i1> [#uses=1]
+ br i1 %0, label %bb7, label %bb4
+
+bb4: ; preds = %bb2
+ br i1 undef, label %bb10, label %bb9
+
+bb7: ; preds = %bb2
+ %1 = add i32 %2, 1 ; <i32> [#uses=1]
+ br label %bb8
+
+bb8: ; preds = %bb7, %entry
+ %2 = phi i32 [ 0, %entry ], [ %1, %bb7 ] ; <i32> [#uses=3]
+ %scevgep22 = getelementptr %struct.iovec* %iov, i32 %2, i32 0; <i8**> [#uses=0]
+ %3 = load i32* %nr_segs, align 4 ; <i32> [#uses=1]
+ %4 = icmp ult i32 %2, %3 ; <i1> [#uses=1]
+ br i1 %4, label %bb, label %bb9
+
+bb9: ; preds = %bb8, %bb4
+ store i32 undef, i32* %count, align 4
+ ret i32 0
+
+bb10: ; preds = %bb4, %bb
+ ret i32 0
+}
diff --git a/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll
new file mode 100644
index 0000000..a46482c
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=arm
+; PR4716
+
+define arm_aapcscc void @_start() nounwind naked {
+entry:
+ tail call arm_aapcscc void @exit(i32 undef) noreturn nounwind
+ unreachable
+}
+
+declare arm_aapcscc void @exit(i32) noreturn nounwind
diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
new file mode 100644
index 0000000..84915c4
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 -post-RA-scheduler -mcpu=cortex-a8
+
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv7-apple-darwin9"
+
+%struct.tree = type { i32, double, double, %struct.tree*, %struct.tree*, %struct.tree*, %struct.tree* }
+@g = common global %struct.tree* null
+
+define arm_apcscc %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind {
+entry:
+ %t.idx51.val.i = load double* null ; <double> [#uses=1]
+ br i1 undef, label %bb4.i, label %bb.i
+
+bb.i: ; preds = %entry
+ unreachable
+
+bb4.i: ; preds = %entry
+ %0 = load %struct.tree** @g, align 4 ; <%struct.tree*> [#uses=2]
+ %.idx45.i = getelementptr %struct.tree* %0, i32 0, i32 1 ; <double*> [#uses=1]
+ %.idx45.val.i = load double* %.idx45.i ; <double> [#uses=1]
+ %.idx46.i = getelementptr %struct.tree* %0, i32 0, i32 2 ; <double*> [#uses=1]
+ %.idx46.val.i = load double* %.idx46.i ; <double> [#uses=1]
+ %1 = fsub double 0.000000e+00, %.idx45.val.i ; <double> [#uses=2]
+ %2 = fmul double %1, %1 ; <double> [#uses=1]
+ %3 = fsub double %t.idx51.val.i, %.idx46.val.i ; <double> [#uses=2]
+ %4 = fmul double %3, %3 ; <double> [#uses=1]
+ %5 = fadd double %2, %4 ; <double> [#uses=1]
+ %6 = tail call double @llvm.sqrt.f64(double %5) nounwind ; <double> [#uses=1]
+ br i1 undef, label %bb7.i4, label %bb6.i
+
+bb6.i: ; preds = %bb4.i
+ br label %bb7.i4
+
+bb7.i4: ; preds = %bb6.i, %bb4.i
+ %tton1.0.i = phi double [ %6, %bb6.i ], [ undef, %bb4.i ] ; <double> [#uses=0]
+ unreachable
+}
+
+declare double @llvm.sqrt.f64(double) nounwind readonly
diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
new file mode 100644
index 0000000..a21ffc3
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
+
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv7-apple-darwin9"
+
+%struct.anon = type { [3 x double], double, %struct.node*, [64 x %struct.bnode*], [64 x %struct.bnode*] }
+%struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, %struct.bnode*, %struct.bnode* }
+%struct.icstruct = type { [3 x i32], i16 }
+%struct.node = type { i16, double, [3 x double], i32, i32 }
+
+declare arm_apcscc double @floor(double) nounwind readnone
+
+define void @intcoord(%struct.icstruct* noalias nocapture sret %agg.result, i1 %a, double %b) {
+entry:
+ br i1 %a, label %bb3, label %bb1
+
+bb1: ; preds = %entry
+ unreachable
+
+bb3: ; preds = %entry
+ br i1 %a, label %bb7, label %bb5
+
+bb5: ; preds = %bb3
+ unreachable
+
+bb7: ; preds = %bb3
+ br i1 %a, label %bb11, label %bb9
+
+bb9: ; preds = %bb7
+ %0 = tail call arm_apcscc double @floor(double %b) nounwind readnone ; <double> [#uses=0]
+ br label %bb11
+
+bb11: ; preds = %bb9, %bb7
+ %1 = getelementptr %struct.icstruct* %agg.result, i32 0, i32 0, i32 0 ; <i32*> [#uses=1]
+ store i32 0, i32* %1
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
new file mode 100644
index 0000000..e3d8ea60
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
+
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv7-apple-darwin9"
+
+%struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }
+%struct.List = type { %struct.List*, %struct.Patient*, %struct.List* }
+%struct.Patient = type { i32, i32, i32, %struct.Village* }
+%struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 }
+
+define arm_apcscc %struct.Village* @alloc_tree(i32 %level, i32 %label, %struct.Village* %back, i1 %p) nounwind {
+entry:
+ br i1 %p, label %bb8, label %bb1
+
+bb1: ; preds = %entry
+ %0 = malloc %struct.Village ; <%struct.Village*> [#uses=3]
+ %exp2 = call double @ldexp(double 1.000000e+00, i32 %level) nounwind ; <double> [#uses=1]
+ %.c = fptosi double %exp2 to i32 ; <i32> [#uses=1]
+ store i32 %.c, i32* null
+ %1 = getelementptr %struct.Village* %0, i32 0, i32 3, i32 6, i32 0 ; <%struct.List**> [#uses=1]
+ store %struct.List* null, %struct.List** %1
+ %2 = getelementptr %struct.Village* %0, i32 0, i32 3, i32 6, i32 2 ; <%struct.List**> [#uses=1]
+ store %struct.List* null, %struct.List** %2
+ ret %struct.Village* %0
+
+bb8: ; preds = %entry
+ ret %struct.Village* null
+}
+
+declare double @ldexp(double, i32)
diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll
new file mode 100644
index 0000000..9123377
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
+
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv7-apple-darwin9"
+
[email protected] = external constant [36 x i8], align 1 ; <[36 x i8]*> [#uses=0]
[email protected] = external constant [31 x i8], align 1 ; <[31 x i8]*> [#uses=1]
[email protected] = external constant [4 x i8], align 1 ; <[4 x i8]*> [#uses=1]
+
+declare arm_apcscc i32 @getUnknown(i32, ...) nounwind
+
+declare void @llvm.va_start(i8*) nounwind
+
+declare void @llvm.va_end(i8*) nounwind
+
+declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind
+
+define arm_apcscc i32 @main() nounwind {
+entry:
+ %0 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; <i32> [#uses=0]
+ %1 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; <i32> [#uses=0]
+ %2 = tail call arm_apcscc i32 (i32, ...)* @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; <i32> [#uses=1]
+ %3 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/ARM/2009-08-23-linkerprivate.ll b/test/CodeGen/ARM/2009-08-23-linkerprivate.ll
new file mode 100644
index 0000000..0fad533
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-23-linkerprivate.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | FileCheck %s
+
+; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm'
+
+@"\01l_objc_msgSend_fixup_alloc" = linker_private hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16 ; <i32*> [#uses=0]
+
+; CHECK: .globl l_objc_msgSend_fixup_alloc
+; CHECK: .weak_definition l_objc_msgSend_fixup_alloc
diff --git a/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll b/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll
new file mode 100644
index 0000000..c6ef256
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -mattr=+neon | not grep fldmfdd
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+%bar = type { float, float, float }
+%baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 }
+%foo = type { <4 x float> }
+%quux = type { i32 (...)**, %baz*, i32 }
+%quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo }
+
+declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+define arm_apcscc void @_ZN6squish10ClusterFit9Compress3EPv(%quuz* %this, i8* %block) {
+entry:
+ %0 = lshr <4 x i32> zeroinitializer, <i32 31, i32 31, i32 31, i32 31> ; <<4 x i32>> [#uses=1]
+ %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> <i32 2, i32 3> ; <<2 x i32>> [#uses=1]
+ %2 = call <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32> undef, <2 x i32> %1) nounwind ; <<2 x i32>> [#uses=1]
+ %3 = extractelement <2 x i32> %2, i32 0 ; <i32> [#uses=1]
+ %not..i = icmp eq i32 %3, undef ; <i1> [#uses=1]
+ br i1 %not..i, label %return, label %bb221
+
+bb221: ; preds = %bb221, %entry
+ br label %bb221
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll b/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll
new file mode 100644
index 0000000..bc5bfe9
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -mattr=+neon | not grep fldmfdd
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+%bar = type { float, float, float }
+%baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 }
+%foo = type { <4 x float> }
+%quux = type { i32 (...)**, %baz*, i32 }
+%quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo }
+
+define arm_apcscc void @aaaa(%quuz* %this, i8* %block) {
+entry:
+ br i1 undef, label %bb.nph269, label %bb201
+
+bb.nph269: ; preds = %entry
+ br label %bb12
+
+bb12: ; preds = %bb194, %bb.nph269
+ %0 = fmul <4 x float> undef, undef ; <<4 x float>> [#uses=1]
+ %1 = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
+ %2 = shufflevector <2 x float> %1, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %3 = fadd <4 x float> undef, %2 ; <<4 x float>> [#uses=1]
+ br i1 undef, label %bb194, label %bb186
+
+bb186: ; preds = %bb12
+ br label %bb194
+
+bb194: ; preds = %bb186, %bb12
+ %besterror.0.0 = phi <4 x float> [ %3, %bb186 ], [ undef, %bb12 ] ; <<4 x float>> [#uses=0]
+ %indvar.next294 = add i32 undef, 1 ; <i32> [#uses=0]
+ br label %bb12
+
+bb201: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll b/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll
new file mode 100644
index 0000000..d5178b4
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -mattr=+neon
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define arm_apcscc void @foo() nounwind {
+entry:
+ %0 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> undef, <2 x float> undef) nounwind ; <<2 x float>> [#uses=1]
+ %tmp28 = extractelement <2 x float> %0, i32 0 ; <float> [#uses=1]
+ %1 = fcmp une float %tmp28, 4.900000e+01 ; <i1> [#uses=1]
+ br i1 %1, label %bb, label %bb7
+
+bb: ; preds = %entry
+ unreachable
+
+bb7: ; preds = %entry
+ br i1 undef, label %bb8, label %bb9
+
+bb8: ; preds = %bb7
+ unreachable
+
+bb9: ; preds = %bb7
+ ret void
+}
+
+declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
diff --git a/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll b/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll
new file mode 100644
index 0000000..266fce6
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -mattr=+neon
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define arm_apcscc void @aaa() nounwind {
+entry:
+ %0 = fmul <4 x float> undef, <float 1.000000e+00, float 1.000000e+01, float 1.000000e+02, float 0x3EB0C6F7A0000000> ; <<4 x float>> [#uses=1]
+ %tmp31 = extractelement <4 x float> %0, i32 0 ; <float> [#uses=1]
+ %1 = fpext float %tmp31 to double ; <double> [#uses=1]
+ %2 = fsub double 1.000000e+00, %1 ; <double> [#uses=1]
+ %3 = fdiv double %2, 1.000000e+00 ; <double> [#uses=1]
+ %4 = tail call double @fabs(double %3) nounwind readnone ; <double> [#uses=1]
+ %5 = fcmp ogt double %4, 1.000000e-05 ; <i1> [#uses=1]
+ br i1 %5, label %bb, label %bb7
+
+bb: ; preds = %entry
+ unreachable
+
+bb7: ; preds = %entry
+ unreachable
+}
+
+declare double @fabs(double)
diff --git a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll
new file mode 100644
index 0000000..b6cf880
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll
@@ -0,0 +1,103 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin9 -march=arm | FileCheck %s
+
+%struct.A = type { i32* }
+
+define arm_apcscc void @"\01-[MyFunction Name:]"() {
+entry:
+ %save_filt.1 = alloca i32 ; <i32*> [#uses=2]
+ %save_eptr.0 = alloca i8* ; <i8**> [#uses=2]
+ %a = alloca %struct.A ; <%struct.A*> [#uses=3]
+ %eh_exception = alloca i8* ; <i8**> [#uses=5]
+ %eh_selector = alloca i32 ; <i32*> [#uses=3]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ call arm_apcscc void @_ZN1AC1Ev(%struct.A* %a)
+ invoke arm_apcscc void @_Z3barv()
+ to label %invcont unwind label %lpad
+
+invcont: ; preds = %entry
+ call arm_apcscc void @_ZN1AD1Ev(%struct.A* %a) nounwind
+ br label %return
+
+bb: ; preds = %ppad
+ %eh_select = load i32* %eh_selector ; <i32> [#uses=1]
+ store i32 %eh_select, i32* %save_filt.1, align 4
+ %eh_value = load i8** %eh_exception ; <i8*> [#uses=1]
+ store i8* %eh_value, i8** %save_eptr.0, align 4
+ call arm_apcscc void @_ZN1AD1Ev(%struct.A* %a) nounwind
+ %0 = load i8** %save_eptr.0, align 4 ; <i8*> [#uses=1]
+ store i8* %0, i8** %eh_exception, align 4
+ %1 = load i32* %save_filt.1, align 4 ; <i32> [#uses=1]
+ store i32 %1, i32* %eh_selector, align 4
+ br label %Unwind
+
+return: ; preds = %invcont
+ ret void
+
+lpad: ; preds = %entry
+ %eh_ptr = call i8* @llvm.eh.exception() ; <i8*> [#uses=1]
+ store i8* %eh_ptr, i8** %eh_exception
+ %eh_ptr1 = load i8** %eh_exception ; <i8*> [#uses=1]
+ %eh_select2 = call i32 (i8*, i8*, ...)* @llvm.eh.selector.i32(i8* %eh_ptr1, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i32 0) ; <i32> [#uses=1]
+ store i32 %eh_select2, i32* %eh_selector
+ br label %ppad
+
+ppad: ; preds = %lpad
+ br label %bb
+
+Unwind: ; preds = %bb
+ %eh_ptr3 = load i8** %eh_exception ; <i8*> [#uses=1]
+ call arm_apcscc void @_Unwind_SjLj_Resume(i8* %eh_ptr3)
+ unreachable
+}
+
+define linkonce_odr arm_apcscc void @_ZN1AC1Ev(%struct.A* %this) {
+entry:
+ %this_addr = alloca %struct.A* ; <%struct.A**> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store %struct.A* %this, %struct.A** %this_addr
+ %0 = call arm_apcscc i8* @_Znwm(i32 4) ; <i8*> [#uses=1]
+ %1 = bitcast i8* %0 to i32* ; <i32*> [#uses=1]
+ %2 = load %struct.A** %this_addr, align 4 ; <%struct.A*> [#uses=1]
+ %3 = getelementptr inbounds %struct.A* %2, i32 0, i32 0 ; <i32**> [#uses=1]
+ store i32* %1, i32** %3, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare arm_apcscc i8* @_Znwm(i32)
+
+define linkonce_odr arm_apcscc void @_ZN1AD1Ev(%struct.A* %this) nounwind {
+entry:
+ %this_addr = alloca %struct.A* ; <%struct.A**> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store %struct.A* %this, %struct.A** %this_addr
+ %0 = load %struct.A** %this_addr, align 4 ; <%struct.A*> [#uses=1]
+ %1 = getelementptr inbounds %struct.A* %0, i32 0, i32 0 ; <i32**> [#uses=1]
+ %2 = load i32** %1, align 4 ; <i32*> [#uses=1]
+ %3 = bitcast i32* %2 to i8* ; <i8*> [#uses=1]
+ call arm_apcscc void @_ZdlPv(i8* %3) nounwind
+ br label %bb
+
+bb: ; preds = %entry
+ br label %return
+
+return: ; preds = %bb
+ ret void
+}
+;CHECK: L_LSDA_1:
+
+declare arm_apcscc void @_ZdlPv(i8*) nounwind
+
+declare arm_apcscc void @_Z3barv()
+
+declare i8* @llvm.eh.exception() nounwind
+
+declare i32 @llvm.eh.selector.i32(i8*, i8*, ...) nounwind
+
+declare i32 @llvm.eh.typeid.for.i32(i8*) nounwind
+
+declare arm_apcscc i32 @__gxx_personality_sj0(...)
+
+declare arm_apcscc void @_Unwind_SjLj_Resume(i8*)
diff --git a/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll b/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
new file mode 100644
index 0000000..e1e60e6
--- /dev/null
+++ b/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; pr4843
+define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind {
+;CHECK: v2regbug:
+;CHECK: vzip.16
+ %tmp1 = load <4 x i16>* %B
+ %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1>
+ ret <4 x i16> %tmp2
+}
diff --git a/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll b/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll
new file mode 100644
index 0000000..bf91fe0
--- /dev/null
+++ b/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll
@@ -0,0 +1,106 @@
+; RUN: llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 < %s | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-apple-darwin9"
+
+@history = internal global [2 x [56 x i32]] [[56 x i32] [i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0], [56 x i32] [i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 2, i32 5, i32 8, i32 10, i32 8, i32 5, i32 2, i32 -1, i32 1, i32 3, i32 5, i32 7, i32 5, i32 3, i32 1, i32 -1, i32 0, i32 1, i32 2, i32 4, i32 2, i32 1, i32 0]] ; <[2 x [56 x i32]]*> [#uses=3]
+@nodes = internal global i64 0 ; <i64*> [#uses=4]
[email protected] = private constant [9 x i8] c"##-<=>+#\00", align 1 ; <[9 x i8]*> [#uses=2]
[email protected] = private constant [6 x i8] c"%c%d\0A\00", align 1 ; <[6 x i8]*> [#uses=1]
[email protected] = private constant [16 x i8] c"Fhourstones 2.0\00", align 1 ; <[16 x i8]*> [#uses=1]
[email protected] = private constant [54 x i8] c"Using %d transposition table entries with %d probes.\0A\00", align 1 ; <[54 x i8]*> [#uses=1]
[email protected] = private constant [31 x i8] c"Solving %d-ply position after \00", align 1 ; <[31 x i8]*> [#uses=1]
[email protected] = private constant [7 x i8] c" . . .\00", align 1 ; <[7 x i8]*> [#uses=1]
[email protected] = private constant [28 x i8] c"score = %d (%c) work = %d\0A\00", align 1 ; <[28 x i8]*> [#uses=1]
[email protected] = private constant [36 x i8] c"%lu pos / %lu msec = %.1f Kpos/sec\0A\00", align 1 ; <[36 x i8]*> [#uses=1]
+@plycnt = internal global i32 0 ; <i32*> [#uses=21]
+@dias = internal global [19 x i32] zeroinitializer ; <[19 x i32]*> [#uses=43]
+@columns = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=18]
+@height = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=21]
+@rows = internal global [8 x i32] zeroinitializer ; <[8 x i32]*> [#uses=20]
+@colthr = internal global [128 x i32] zeroinitializer ; <[128 x i32]*> [#uses=5]
+@moves = internal global [44 x i32] zeroinitializer ; <[44 x i32]*> [#uses=9]
[email protected] = private constant [3 x i8] c"%d\00", align 1 ; <[3 x i8]*> [#uses=1]
+@he = internal global i8* null ; <i8**> [#uses=9]
+@hits = internal global i64 0 ; <i64*> [#uses=8]
+@posed = internal global i64 0 ; <i64*> [#uses=7]
+@ht = internal global i32* null ; <i32**> [#uses=5]
[email protected] = private constant [19 x i8] c"store rate = %.3f\0A\00", align 1 ; <[19 x i8]*> [#uses=1]
[email protected] = private constant [45 x i8] c"- %5.3f < %5.3f = %5.3f > %5.3f + %5.3f\0A\00", align 1 ; <[45 x i8]*> [#uses=1]
[email protected] = private constant [6 x i8] c"%7d%c\00", align 1 ; <[6 x i8]*> [#uses=1]
[email protected] = private constant [30 x i8] c"Failed to allocate %u bytes.\0A\00", align 1 ; <[30 x i8]*> [#uses=1]
+
+declare arm_apcscc i32 @puts(i8* nocapture) nounwind
+
+declare arm_apcscc i32 @getchar() nounwind
+
+define internal arm_apcscc i32 @transpose() nounwind readonly {
+; CHECK: push
+entry:
+ %0 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 1), align 4 ; <i32> [#uses=1]
+ %1 = shl i32 %0, 7 ; <i32> [#uses=1]
+ %2 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 2), align 4 ; <i32> [#uses=1]
+ %3 = or i32 %1, %2 ; <i32> [#uses=1]
+ %4 = shl i32 %3, 7 ; <i32> [#uses=1]
+ %5 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 3), align 4 ; <i32> [#uses=1]
+ %6 = or i32 %4, %5 ; <i32> [#uses=3]
+ %7 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 7), align 4 ; <i32> [#uses=1]
+ %8 = shl i32 %7, 7 ; <i32> [#uses=1]
+ %9 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 6), align 4 ; <i32> [#uses=1]
+ %10 = or i32 %8, %9 ; <i32> [#uses=1]
+ %11 = shl i32 %10, 7 ; <i32> [#uses=1]
+ %12 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 5), align 4 ; <i32> [#uses=1]
+ %13 = or i32 %11, %12 ; <i32> [#uses=3]
+ %14 = icmp ugt i32 %6, %13 ; <i1> [#uses=2]
+ %.pn2.in.i = select i1 %14, i32 %6, i32 %13 ; <i32> [#uses=1]
+ %.pn1.in.i = select i1 %14, i32 %13, i32 %6 ; <i32> [#uses=1]
+ %.pn2.i = shl i32 %.pn2.in.i, 7 ; <i32> [#uses=1]
+ %.pn3.i = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 4) ; <i32> [#uses=1]
+ %.pn.in.in.i = or i32 %.pn2.i, %.pn3.i ; <i32> [#uses=1]
+ %.pn.in.i = zext i32 %.pn.in.in.i to i64 ; <i64> [#uses=1]
+ %.pn.i = shl i64 %.pn.in.i, 21 ; <i64> [#uses=1]
+ %.pn1.i = zext i32 %.pn1.in.i to i64 ; <i64> [#uses=1]
+ %iftmp.22.0.i = or i64 %.pn.i, %.pn1.i ; <i64> [#uses=2]
+ %15 = lshr i64 %iftmp.22.0.i, 17 ; <i64> [#uses=1]
+ %16 = trunc i64 %15 to i32 ; <i32> [#uses=2]
+ %17 = urem i64 %iftmp.22.0.i, 1050011 ; <i64> [#uses=1]
+ %18 = trunc i64 %17 to i32 ; <i32> [#uses=1]
+ %19 = urem i32 %16, 179 ; <i32> [#uses=1]
+ %20 = or i32 %19, 131072 ; <i32> [#uses=1]
+ %21 = load i32** @ht, align 4 ; <i32*> [#uses=1]
+ br label %bb5
+
+bb: ; preds = %bb5
+ %22 = getelementptr inbounds i32* %21, i32 %x.0 ; <i32*> [#uses=1]
+ %23 = load i32* %22, align 4 ; <i32> [#uses=1]
+ %24 = icmp eq i32 %23, %16 ; <i1> [#uses=1]
+ br i1 %24, label %bb1, label %bb2
+
+bb1: ; preds = %bb
+ %25 = load i8** @he, align 4 ; <i8*> [#uses=1]
+ %26 = getelementptr inbounds i8* %25, i32 %x.0 ; <i8*> [#uses=1]
+ %27 = load i8* %26, align 1 ; <i8> [#uses=1]
+ %28 = sext i8 %27 to i32 ; <i32> [#uses=1]
+ ret i32 %28
+
+bb2: ; preds = %bb
+ %29 = add nsw i32 %20, %x.0 ; <i32> [#uses=3]
+ %30 = add i32 %29, -1050011 ; <i32> [#uses=1]
+ %31 = icmp sgt i32 %29, 1050010 ; <i1> [#uses=1]
+ %. = select i1 %31, i32 %30, i32 %29 ; <i32> [#uses=1]
+ %32 = add i32 %33, 1 ; <i32> [#uses=1]
+ br label %bb5
+
+bb5: ; preds = %bb2, %entry
+ %33 = phi i32 [ 0, %entry ], [ %32, %bb2 ] ; <i32> [#uses=2]
+ %x.0 = phi i32 [ %18, %entry ], [ %., %bb2 ] ; <i32> [#uses=3]
+ %34 = icmp sgt i32 %33, 7 ; <i1> [#uses=1]
+ br i1 %34, label %bb7, label %bb
+
+bb7: ; preds = %bb5
+ ret i32 -128
+}
+
+declare arm_apcscc noalias i8* @calloc(i32, i32) nounwind
+
+declare void @llvm.memset.i64(i8* nocapture, i8, i64, i32) nounwind
diff --git a/test/CodeGen/ARM/2009-09-09-AllOnes.ll b/test/CodeGen/ARM/2009-09-09-AllOnes.ll
new file mode 100644
index 0000000..f654a16
--- /dev/null
+++ b/test/CodeGen/ARM/2009-09-09-AllOnes.ll
@@ -0,0 +1,10 @@
+; RUN: llc -mattr=+neon < %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define arm_apcscc void @foo() {
+entry:
+ %0 = insertelement <4 x i32> undef, i32 -1, i32 3
+ store <4 x i32> %0, <4 x i32>* undef, align 16
+ unreachable
+}
diff --git a/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll b/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
new file mode 100644
index 0000000..3909c6a5
--- /dev/null
+++ b/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
@@ -0,0 +1,18 @@
+; RUN: llc -O1 -march=arm -mattr=+vfp2 < %s | FileCheck %s
+; pr4939
+
+define void @test(double* %x, double* %y) nounwind {
+ %1 = load double* %x, align 4
+ %2 = load double* %y, align 4
+ %3 = fsub double -0.000000e+00, %1
+ %4 = fcmp ugt double %2, %3
+ br i1 %4, label %bb1, label %bb2
+
+bb1:
+;CHECK: vstrhi.64
+ store double %1, double* %y, align 4
+ br label %bb2
+
+bb2:
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-09-10-postdec.ll b/test/CodeGen/ARM/2009-09-10-postdec.ll
new file mode 100644
index 0000000..10653b5
--- /dev/null
+++ b/test/CodeGen/ARM/2009-09-10-postdec.ll
@@ -0,0 +1,11 @@
+; RUN: llc -march=arm < %s | FileCheck %s
+; Radar 7213850
+
+define i32 @test(i8* %d, i32 %x, i32 %y) nounwind {
+ %1 = ptrtoint i8* %d to i32
+;CHECK: sub
+ %2 = sub i32 %x, %1
+ %3 = add nsw i32 %2, %y
+ store i8 0, i8* %d, align 1
+ ret i32 %3
+}
diff --git a/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll b/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll
new file mode 100644
index 0000000..13adb24
--- /dev/null
+++ b/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll
@@ -0,0 +1,61 @@
+; RUN: llc -mattr=+neon < %s
+; PR4965
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv7-eabi"
+
+%struct.fr = type { [6 x %struct.pl] }
+%struct.obb = type { %"struct.m4", %"struct.p3" }
+%struct.pl = type { %"struct.p3" }
+%"struct.m4" = type { %"struct.p3", %"struct.p3", %"struct.p3", %"struct.p3" }
+%"struct.p3" = type { <4 x float> }
+
+declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+define arm_aapcs_vfpcc i8 @foo(%struct.fr* nocapture %this, %struct.obb* %box) nounwind {
+entry:
+ %val.i.i = load <4 x float>* undef ; <<4 x float>> [#uses=1]
+ %val2.i.i = load <4 x float>* null ; <<4 x float>> [#uses=1]
+ %elt3.i.i = getelementptr inbounds %struct.obb* %box, i32 0, i32 0, i32 2, i32 0 ; <<4 x float>*> [#uses=1]
+ %val4.i.i = load <4 x float>* %elt3.i.i ; <<4 x float>> [#uses=1]
+ %0 = shufflevector <2 x float> undef, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
+ %1 = fadd <4 x float> undef, zeroinitializer ; <<4 x float>> [#uses=1]
+ br label %bb33
+
+bb: ; preds = %bb33
+ %2 = fmul <4 x float> %val.i.i, undef ; <<4 x float>> [#uses=1]
+ %3 = fmul <4 x float> %val2.i.i, undef ; <<4 x float>> [#uses=1]
+ %4 = fadd <4 x float> %3, %2 ; <<4 x float>> [#uses=1]
+ %5 = fmul <4 x float> %val4.i.i, undef ; <<4 x float>> [#uses=1]
+ %6 = fadd <4 x float> %5, %4 ; <<4 x float>> [#uses=1]
+ %7 = bitcast <4 x float> %6 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %8 = and <4 x i32> %7, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=1]
+ %9 = or <4 x i32> %8, undef ; <<4 x i32>> [#uses=1]
+ %10 = bitcast <4 x i32> %9 to <4 x float> ; <<4 x float>> [#uses=1]
+ %11 = shufflevector <4 x float> %10, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
+ %12 = shufflevector <2 x float> %11, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %13 = fmul <4 x float> undef, %12 ; <<4 x float>> [#uses=1]
+ %14 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=1]
+ %15 = fadd <4 x float> %14, %13 ; <<4 x float>> [#uses=1]
+ %16 = fadd <4 x float> undef, %15 ; <<4 x float>> [#uses=1]
+ %17 = fadd <4 x float> %1, %16 ; <<4 x float>> [#uses=1]
+ %18 = fmul <4 x float> zeroinitializer, %17 ; <<4 x float>> [#uses=1]
+ %19 = insertelement <4 x float> %18, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=2]
+ %20 = shufflevector <4 x float> %19, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
+ %21 = shufflevector <4 x float> %19, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
+ %22 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %20, <2 x float> %21) nounwind ; <<2 x float>> [#uses=2]
+ %23 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %22, <2 x float> %22) nounwind ; <<2 x float>> [#uses=2]
+ %24 = shufflevector <2 x float> %23, <2 x float> %23, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %25 = fadd <4 x float> %24, zeroinitializer ; <<4 x float>> [#uses=1]
+ %tmp46 = extractelement <4 x float> %25, i32 0 ; <float> [#uses=1]
+ %26 = fcmp olt float %tmp46, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %26, label %bb41, label %bb33
+
+bb33: ; preds = %bb, %entry
+ br i1 undef, label %bb34, label %bb
+
+bb34: ; preds = %bb33
+ ret i8 undef
+
+bb41: ; preds = %bb
+ ret i8 1
+}
diff --git a/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll b/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll
new file mode 100644
index 0000000..758b59a
--- /dev/null
+++ b/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a9
+
+define arm_aapcs_vfpcc <4 x float> @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+ %1 = ptrtoint i8* %pBuffer to i32
+
+ %lsr.iv2641 = inttoptr i32 %1 to float*
+ %tmp29 = add i32 %1, 4
+ %tmp2930 = inttoptr i32 %tmp29 to float*
+ %tmp31 = add i32 %1, 8
+ %tmp3132 = inttoptr i32 %tmp31 to float*
+ %tmp33 = add i32 %1, 12
+ %tmp3334 = inttoptr i32 %tmp33 to float*
+ %tmp35 = add i32 %1, 16
+ %tmp3536 = inttoptr i32 %tmp35 to float*
+ %tmp37 = add i32 %1, 20
+ %tmp3738 = inttoptr i32 %tmp37 to float*
+ %tmp39 = add i32 %1, 24
+ %tmp3940 = inttoptr i32 %tmp39 to float*
+ %2 = load float* %lsr.iv2641, align 4
+ %3 = load float* %tmp2930, align 4
+ %4 = load float* %tmp3132, align 4
+ %5 = load float* %tmp3334, align 4
+ %6 = load float* %tmp3536, align 4
+ %7 = load float* %tmp3738, align 4
+ %8 = load float* %tmp3940, align 4
+ %9 = insertelement <4 x float> undef, float %6, i32 0
+ %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> zeroinitializer
+ %11 = insertelement <4 x float> %10, float %7, i32 1
+ %12 = insertelement <4 x float> %11, float %8, i32 2
+ %13 = insertelement <4 x float> undef, float %2, i32 0
+ %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> zeroinitializer
+ %15 = insertelement <4 x float> %14, float %3, i32 1
+ %16 = insertelement <4 x float> %15, float %4, i32 2
+ %17 = insertelement <4 x float> %16, float %5, i32 3
+ %18 = fsub <4 x float> zeroinitializer, %12
+ %19 = shufflevector <4 x float> %18, <4 x float> undef, <4 x i32> zeroinitializer
+ %20 = shufflevector <4 x float> %17, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+ %21 = shufflevector <2 x float> %20, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+
+ ret <4 x float> %21
+}
diff --git a/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll b/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll
new file mode 100644
index 0000000..980f8ce
--- /dev/null
+++ b/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a9
+
+; PR4986
+
+define arm_aapcs_vfpcc void @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+entry:
+ br i1 undef, label %return, label %bb.preheader
+
+bb.preheader: ; preds = %entry
+ br label %bb
+
+bb: ; preds = %bb, %bb.preheader
+ %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1]
+ %2 = insertelement <4 x float> %1, float undef, i32 2 ; <<4 x float>> [#uses=1]
+ %3 = insertelement <4 x float> %2, float undef, i32 3 ; <<4 x float>> [#uses=1]
+ %4 = fmul <4 x float> undef, %3 ; <<4 x float>> [#uses=1]
+ %5 = extractelement <4 x float> %4, i32 3 ; <float> [#uses=1]
+ store float %5, float* undef, align 4
+ br i1 undef, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ ret void
+}
+
+define arm_aapcs_vfpcc <4 x float> @bar(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+ %1 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %2 = insertelement <4 x float> %1, float undef, i32 1 ; <<4 x float>> [#uses=1]
+ %3 = insertelement <4 x float> %2, float undef, i32 2 ; <<4 x float>> [#uses=1]
+ %4 = insertelement <4 x float> %3, float undef, i32 3 ; <<4 x float>> [#uses=1]
+ %5 = shufflevector <4 x float> %4, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
+ %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1]
+ ret <4 x float> %6
+}
diff --git a/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll b/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll
new file mode 100644
index 0000000..aace475
--- /dev/null
+++ b/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+neon
+
+; PR5024
+
+%bar = type { <4 x float> }
+%foo = type { %bar, %bar, %bar, %bar }
+
+declare arm_aapcs_vfpcc <4 x float> @bbb(%bar*) nounwind
+
+define arm_aapcs_vfpcc void @aaa(%foo* noalias sret %agg.result, %foo* %tfrm) nounwind {
+entry:
+ %0 = call arm_aapcs_vfpcc <4 x float> @bbb(%bar* undef) nounwind ; <<4 x float>> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll b/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll
new file mode 100644
index 0000000..30931a2
--- /dev/null
+++ b/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+neon
+
+; PR5024
+
+%bar = type { %foo, %foo }
+%foo = type { <4 x float> }
+
+declare arm_aapcs_vfpcc float @aaa(%foo* nocapture) nounwind readonly
+
+declare arm_aapcs_vfpcc %bar* @bbb(%bar*, <4 x float>, <4 x float>) nounwind
+
+define arm_aapcs_vfpcc void @ccc(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+entry:
+ br i1 undef, label %return, label %bb.nph
+
+bb.nph: ; preds = %entry
+ %0 = call arm_aapcs_vfpcc %bar* @bbb(%bar* undef, <4 x float> undef, <4 x float> undef) nounwind ; <%bar*> [#uses=0]
+ %1 = call arm_aapcs_vfpcc float @aaa(%foo* undef) nounwind ; <float> [#uses=0]
+ unreachable
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll b/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll
new file mode 100644
index 0000000..2ff479b
--- /dev/null
+++ b/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+neon
+
+; PR5024
+
+%struct.1 = type { %struct.4, %struct.4 }
+%struct.4 = type { <4 x float> }
+
+define arm_aapcs_vfpcc %struct.1* @hhh3(%struct.1* %this, <4 x float> %lenation.0, <4 x float> %legalation.0) nounwind {
+entry:
+ %0 = call arm_aapcs_vfpcc %struct.4* @sss1(%struct.4* undef, float 0.000000e+00) nounwind ; <%struct.4*> [#uses=0]
+ %1 = call arm_aapcs_vfpcc %struct.4* @qqq1(%struct.4* null, float 5.000000e-01) nounwind ; <%struct.4*> [#uses=0]
+ %val92 = load <4 x float>* null ; <<4 x float>> [#uses=1]
+ %2 = call arm_aapcs_vfpcc %struct.4* @zzz2(%struct.4* undef, <4 x float> %val92) nounwind ; <%struct.4*> [#uses=0]
+ ret %struct.1* %this
+}
+
+declare arm_aapcs_vfpcc %struct.4* @qqq1(%struct.4*, float) nounwind
+
+declare arm_aapcs_vfpcc %struct.4* @sss1(%struct.4*, float) nounwind
+
+declare arm_aapcs_vfpcc %struct.4* @zzz2(%struct.4*, <4 x float>) nounwind
diff --git a/test/CodeGen/ARM/2009-09-24-spill-align.ll b/test/CodeGen/ARM/2009-09-24-spill-align.ll
new file mode 100644
index 0000000..5476d5f
--- /dev/null
+++ b/test/CodeGen/ARM/2009-09-24-spill-align.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; pr4926
+
+define arm_apcscc void @test_vget_lanep16() nounwind {
+entry:
+ %arg0_poly16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1]
+ %out_poly16_t = alloca i16 ; <i16*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+; CHECK: vldr.64
+ %0 = load <4 x i16>* %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1]
+ %1 = extractelement <4 x i16> %0, i32 1 ; <i16> [#uses=1]
+ store i16 %1, i16* %out_poly16_t, align 2
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-09-27-CoalescerBug.ll b/test/CodeGen/ARM/2009-09-27-CoalescerBug.ll
new file mode 100644
index 0000000..ea2693a
--- /dev/null
+++ b/test/CodeGen/ARM/2009-09-27-CoalescerBug.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8
+; PR5055
+
+module asm ".globl\09__aeabi_f2lz"
+module asm ".set\09__aeabi_f2lz, __fixsfdi"
+module asm ""
+
+define arm_aapcs_vfpcc i64 @__fixsfdi(float %a) nounwind {
+entry:
+ %0 = fcmp olt float %a, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %0, label %bb, label %bb1
+
+bb: ; preds = %entry
+ %1 = fsub float -0.000000e+00, %a ; <float> [#uses=1]
+ %2 = tail call arm_aapcs_vfpcc i64 @__fixunssfdi(float %1) nounwind ; <i64> [#uses=1]
+ %3 = sub i64 0, %2 ; <i64> [#uses=1]
+ ret i64 %3
+
+bb1: ; preds = %entry
+ %4 = tail call arm_aapcs_vfpcc i64 @__fixunssfdi(float %a) nounwind ; <i64> [#uses=1]
+ ret i64 %4
+}
+
+declare arm_aapcs_vfpcc i64 @__fixunssfdi(float)
diff --git a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
new file mode 100644
index 0000000..53bd668
--- /dev/null
+++ b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -mcpu=arm10tdmi | FileCheck %s
+; PR4687
+
+%0 = type { double, double }
+
+define arm_aapcscc void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind {
+; CHECK: foo:
+; CHECK: bl __adddf3
+; CHECK-NOT: strd
+; CHECK: mov
+ %x76 = fmul double %y.0, 0.000000e+00 ; <double> [#uses=1]
+ %x77 = fadd double %y.0, 0.000000e+00 ; <double> [#uses=1]
+ %tmpr = fadd double %x.0, %x76 ; <double> [#uses=1]
+ %agg.result.0 = getelementptr %0* %agg.result, i32 0, i32 0 ; <double*> [#uses=1]
+ store double %tmpr, double* %agg.result.0, align 8
+ %agg.result.1 = getelementptr %0* %agg.result, i32 0, i32 1 ; <double*> [#uses=1]
+ store double %x77, double* %agg.result.1, align 8
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll b/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll
new file mode 100644
index 0000000..465368b
--- /dev/null
+++ b/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll
@@ -0,0 +1,63 @@
+; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 -enable-unsafe-fp-math < %s
+; PR5367
+
+define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+entry:
+ br i1 undef, label %return, label %bb
+
+bb: ; preds = %bb, %entry
+ %0 = load float* undef, align 4 ; <float> [#uses=1]
+ %1 = load float* null, align 4 ; <float> [#uses=1]
+ %2 = insertelement <4 x float> undef, float undef, i32 1 ; <<4 x float>> [#uses=1]
+ %3 = insertelement <4 x float> %2, float %1, i32 2 ; <<4 x float>> [#uses=2]
+ %4 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1]
+ %5 = insertelement <4 x float> %4, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=4]
+ %6 = fsub <4 x float> zeroinitializer, %3 ; <<4 x float>> [#uses=1]
+ %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=2]
+ %8 = shufflevector <4 x float> %5, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
+ %9 = shufflevector <2 x float> %8, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=2]
+ %10 = fmul <4 x float> %7, %9 ; <<4 x float>> [#uses=1]
+ %11 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %12 = shufflevector <4 x float> %5, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=2]
+ %13 = shufflevector <2 x float> %12, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %14 = fmul <4 x float> %11, %13 ; <<4 x float>> [#uses=1]
+ %15 = fadd <4 x float> %10, %14 ; <<4 x float>> [#uses=1]
+ %16 = shufflevector <2 x float> %12, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1]
+ %17 = fadd <4 x float> %15, zeroinitializer ; <<4 x float>> [#uses=1]
+ %18 = shufflevector <4 x float> %17, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef> ; <<4 x float>> [#uses=1]
+ %19 = fmul <4 x float> %7, %16 ; <<4 x float>> [#uses=1]
+ %20 = fadd <4 x float> %19, zeroinitializer ; <<4 x float>> [#uses=1]
+ %21 = shufflevector <4 x float> %3, <4 x float> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1]
+ %22 = shufflevector <4 x float> %21, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %23 = fmul <4 x float> %22, %9 ; <<4 x float>> [#uses=1]
+ %24 = fadd <4 x float> %20, %23 ; <<4 x float>> [#uses=1]
+ %25 = shufflevector <4 x float> %18, <4 x float> %24, <4 x i32> <i32 0, i32 1, i32 6, i32 undef> ; <<4 x float>> [#uses=1]
+ %26 = shufflevector <4 x float> %25, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 7> ; <<4 x float>> [#uses=1]
+ %27 = fmul <4 x float> %26, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> ; <<4 x float>> [#uses=1]
+ %28 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %5 ; <<4 x float>> [#uses=1]
+ %29 = tail call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]
+ %30 = fmul <4 x float> zeroinitializer, %29 ; <<4 x float>> [#uses=1]
+ %31 = fmul <4 x float> %30, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00> ; <<4 x float>> [#uses=1]
+ %32 = shufflevector <4 x float> %27, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %33 = shufflevector <4 x float> %28, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
+ %34 = shufflevector <2 x float> %33, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1]
+ %35 = fmul <4 x float> %32, %34 ; <<4 x float>> [#uses=1]
+ %36 = fadd <4 x float> %35, zeroinitializer ; <<4 x float>> [#uses=1]
+ %37 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> ; <<4 x float>> [#uses=1]
+ %38 = shufflevector <4 x float> %37, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %39 = fmul <4 x float> zeroinitializer, %38 ; <<4 x float>> [#uses=1]
+ %40 = fadd <4 x float> %36, %39 ; <<4 x float>> [#uses=1]
+ %41 = fadd <4 x float> %40, zeroinitializer ; <<4 x float>> [#uses=1]
+ %42 = shufflevector <4 x float> undef, <4 x float> %41, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1]
+ %43 = fmul <4 x float> %42, %31 ; <<4 x float>> [#uses=1]
+ store float undef, float* undef, align 4
+ store float 0.000000e+00, float* null, align 4
+ %44 = extractelement <4 x float> %43, i32 1 ; <float> [#uses=1]
+ store float %44, float* undef, align 4
+ br i1 undef, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ ret void
+}
+
+declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
diff --git a/test/CodeGen/ARM/2009-10-21-InvalidFNeg.ll b/test/CodeGen/ARM/2009-10-21-InvalidFNeg.ll
new file mode 100644
index 0000000..0f021d2
--- /dev/null
+++ b/test/CodeGen/ARM/2009-10-21-InvalidFNeg.ll
@@ -0,0 +1,48 @@
+; RUN: llc -mcpu=cortex-a8 -mattr=+neon < %s | grep vneg
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv7-eabi"
+
+%aaa = type { %fff, %fff }
+%bbb = type { [6 x %ddd] }
+%ccc = type { %eee, %fff }
+%ddd = type { %fff }
+%eee = type { %fff, %fff, %fff, %fff }
+%fff = type { %struct.vec_float4 }
+%struct.vec_float4 = type { <4 x float> }
+
+define linkonce_odr arm_aapcs_vfpcc void @foo(%eee* noalias sret %agg.result, i64 %tfrm.0.0, i64 %tfrm.0.1, i64 %tfrm.0.2, i64 %tfrm.0.3, i64 %tfrm.0.4, i64 %tfrm.0.5, i64 %tfrm.0.6, i64 %tfrm.0.7) nounwind noinline {
+entry:
+ %tmp104 = zext i64 %tfrm.0.2 to i512 ; <i512> [#uses=1]
+ %tmp105 = shl i512 %tmp104, 128 ; <i512> [#uses=1]
+ %tmp118 = zext i64 %tfrm.0.3 to i512 ; <i512> [#uses=1]
+ %tmp119 = shl i512 %tmp118, 192 ; <i512> [#uses=1]
+ %ins121 = or i512 %tmp119, %tmp105 ; <i512> [#uses=1]
+ %tmp99 = zext i64 %tfrm.0.4 to i512 ; <i512> [#uses=1]
+ %tmp100 = shl i512 %tmp99, 256 ; <i512> [#uses=1]
+ %tmp123 = zext i64 %tfrm.0.5 to i512 ; <i512> [#uses=1]
+ %tmp124 = shl i512 %tmp123, 320 ; <i512> [#uses=1]
+ %tmp96 = zext i64 %tfrm.0.6 to i512 ; <i512> [#uses=1]
+ %tmp97 = shl i512 %tmp96, 384 ; <i512> [#uses=1]
+ %tmp128 = zext i64 %tfrm.0.7 to i512 ; <i512> [#uses=1]
+ %tmp129 = shl i512 %tmp128, 448 ; <i512> [#uses=1]
+ %mask.masked = or i512 %tmp124, %tmp100 ; <i512> [#uses=1]
+ %ins131 = or i512 %tmp129, %tmp97 ; <i512> [#uses=1]
+ %tmp109132 = zext i64 %tfrm.0.0 to i128 ; <i128> [#uses=1]
+ %tmp113134 = zext i64 %tfrm.0.1 to i128 ; <i128> [#uses=1]
+ %tmp114133 = shl i128 %tmp113134, 64 ; <i128> [#uses=1]
+ %tmp94 = or i128 %tmp114133, %tmp109132 ; <i128> [#uses=1]
+ %tmp95 = bitcast i128 %tmp94 to <4 x float> ; <<4 x float>> [#uses=0]
+ %tmp82 = lshr i512 %ins121, 128 ; <i512> [#uses=1]
+ %tmp83 = trunc i512 %tmp82 to i128 ; <i128> [#uses=1]
+ %tmp84 = bitcast i128 %tmp83 to <4 x float> ; <<4 x float>> [#uses=0]
+ %tmp86 = lshr i512 %mask.masked, 256 ; <i512> [#uses=1]
+ %tmp87 = trunc i512 %tmp86 to i128 ; <i128> [#uses=1]
+ %tmp88 = bitcast i128 %tmp87 to <4 x float> ; <<4 x float>> [#uses=0]
+ %tmp90 = lshr i512 %ins131, 384 ; <i512> [#uses=1]
+ %tmp91 = trunc i512 %tmp90 to i128 ; <i128> [#uses=1]
+ %tmp92 = bitcast i128 %tmp91 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %tmp92 ; <<4 x float>> [#uses=1]
+ %tmp28 = getelementptr inbounds %eee* %agg.result, i32 0, i32 3, i32 0, i32 0 ; <<4 x float>*> [#uses=1]
+ store <4 x float> %tmp, <4 x float>* %tmp28, align 16
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-10-27-double-align.ll b/test/CodeGen/ARM/2009-10-27-double-align.ll
new file mode 100644
index 0000000..a4e7685
--- /dev/null
+++ b/test/CodeGen/ARM/2009-10-27-double-align.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
+
[email protected] = private constant [1 x i8] zeroinitializer, align 1
+
+define arm_aapcscc void @g() {
+entry:
+;CHECK: [sp, #+8]
+;CHECK: [sp, #+12]
+;CHECK: [sp]
+ tail call arm_aapcscc void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00)
+ ret void
+}
+
+declare arm_aapcscc void @f(i8*, ...)
diff --git a/test/CodeGen/ARM/2009-10-30.ll b/test/CodeGen/ARM/2009-10-30.ll
new file mode 100644
index 0000000..90a5bd2
--- /dev/null
+++ b/test/CodeGen/ARM/2009-10-30.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
+; This test checks that the address of the varg arguments is correctly
+; computed when there are 5 or more regular arguments.
+
+define void @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, ...) {
+entry:
+;CHECK: sub sp, sp, #4
+;CHECK: add r{{[0-9]+}}, sp, #8
+;CHECK: str r{{[0-9]+}}, [sp], #+4
+;CHECK: bx lr
+ %ap = alloca i8*, align 4
+ %ap1 = bitcast i8** %ap to i8*
+ call void @llvm.va_start(i8* %ap1)
+ ret void
+}
+
+declare void @llvm.va_start(i8*) nounwind
diff --git a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll
new file mode 100644
index 0000000..62f3786
--- /dev/null
+++ b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll
@@ -0,0 +1,40 @@
+; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv7-eabi"
+
+%foo = type { <4 x float> }
+
+define arm_aapcs_vfpcc void @bar(%foo* noalias sret %agg.result, <4 x float> %quat.0) nounwind {
+entry:
+ %quat_addr = alloca %foo, align 16 ; <%foo*> [#uses=2]
+ %0 = getelementptr inbounds %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1]
+ store <4 x float> %quat.0, <4 x float>* %0
+ %1 = call arm_aapcs_vfpcc <4 x float> @quux(%foo* %quat_addr) nounwind ; <<4 x float>> [#uses=3]
+;CHECK: vmov.f32
+;CHECK: vmov.f32
+ %2 = fmul <4 x float> %1, %1 ; <<4 x float>> [#uses=2]
+ %3 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
+ %4 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
+ %5 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %3, <2 x float> %4) nounwind ; <<2 x float>> [#uses=2]
+ %6 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %5, <2 x float> %5) nounwind ; <<2 x float>> [#uses=2]
+ %7 = shufflevector <2 x float> %6, <2 x float> %6, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=2]
+;CHECK: vmov
+ %8 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %7) nounwind ; <<4 x float>> [#uses=3]
+ %9 = fmul <4 x float> %8, %8 ; <<4 x float>> [#uses=1]
+ %10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4 x float>> [#uses=1]
+ %11 = fmul <4 x float> %10, %8 ; <<4 x float>> [#uses=1]
+ %12 = fmul <4 x float> %11, %1 ; <<4 x float>> [#uses=1]
+ %13 = call arm_aapcs_vfpcc %foo* @baz(%foo* %agg.result, <4 x float> %12) nounwind ; <%foo*> [#uses=0]
+ ret void
+}
+
+declare arm_aapcs_vfpcc %foo* @baz(%foo*, <4 x float>) nounwind
+
+declare arm_aapcs_vfpcc <4 x float> @quux(%foo* nocapture) nounwind readonly
+
+declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
+
+declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
diff --git a/test/CodeGen/ARM/2009-11-02-NegativeLane.ll b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll
new file mode 100644
index 0000000..f2288c3
--- /dev/null
+++ b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll
@@ -0,0 +1,20 @@
+; RUN: llc -mcpu=cortex-a8 < %s | grep vdup.32
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv7-eabi"
+
+define arm_aapcs_vfpcc void @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind {
+entry:
+ br i1 undef, label %return, label %bb
+
+bb: ; preds = %bb, %entry
+ %0 = load float* undef, align 4 ; <float> [#uses=1]
+ %1 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1]
+ %2 = insertelement <4 x float> %1, float undef, i32 3 ; <<4 x float>> [#uses=1]
+ %3 = fmul <4 x float> undef, %2 ; <<4 x float>> [#uses=1]
+ %4 = extractelement <4 x float> %3, i32 1 ; <float> [#uses=1]
+ store float %4, float* undef, align 4
+ br i1 undef, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
new file mode 100644
index 0000000..7aae3ac
--- /dev/null
+++ b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
@@ -0,0 +1,66 @@
+; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s
+; PR5423
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv7-eabi"
+
+define arm_aapcs_vfpcc void @foo() {
+entry:
+ %0 = load float* null, align 4 ; <float> [#uses=2]
+ %1 = fmul float %0, undef ; <float> [#uses=2]
+ %2 = fmul float 0.000000e+00, %1 ; <float> [#uses=2]
+ %3 = fmul float %0, %1 ; <float> [#uses=1]
+ %4 = fadd float 0.000000e+00, %3 ; <float> [#uses=1]
+ %5 = fsub float 1.000000e+00, %4 ; <float> [#uses=1]
+; CHECK: foo:
+; CHECK: vmov.f32 s{{[0-9]+}}, #1.000000e+00
+ %6 = fsub float 1.000000e+00, undef ; <float> [#uses=2]
+ %7 = fsub float %2, undef ; <float> [#uses=1]
+ %8 = fsub float 0.000000e+00, undef ; <float> [#uses=3]
+ %9 = fadd float %2, undef ; <float> [#uses=3]
+ %10 = load float* undef, align 8 ; <float> [#uses=3]
+ %11 = fmul float %8, %10 ; <float> [#uses=1]
+ %12 = fadd float undef, %11 ; <float> [#uses=2]
+ %13 = fmul float undef, undef ; <float> [#uses=1]
+ %14 = fmul float %6, 0.000000e+00 ; <float> [#uses=1]
+ %15 = fadd float %13, %14 ; <float> [#uses=1]
+ %16 = fmul float %9, %10 ; <float> [#uses=1]
+ %17 = fadd float %15, %16 ; <float> [#uses=2]
+ %18 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
+ %19 = fadd float %18, 0.000000e+00 ; <float> [#uses=1]
+ %20 = fmul float undef, %10 ; <float> [#uses=1]
+ %21 = fadd float %19, %20 ; <float> [#uses=1]
+ %22 = load float* undef, align 8 ; <float> [#uses=1]
+ %23 = fmul float %5, %22 ; <float> [#uses=1]
+ %24 = fadd float %23, undef ; <float> [#uses=1]
+ %25 = load float* undef, align 8 ; <float> [#uses=2]
+ %26 = fmul float %8, %25 ; <float> [#uses=1]
+ %27 = fadd float %24, %26 ; <float> [#uses=1]
+ %28 = fmul float %9, %25 ; <float> [#uses=1]
+ %29 = fadd float undef, %28 ; <float> [#uses=1]
+ %30 = fmul float %8, undef ; <float> [#uses=1]
+ %31 = fadd float undef, %30 ; <float> [#uses=1]
+ %32 = fmul float %6, undef ; <float> [#uses=1]
+ %33 = fadd float undef, %32 ; <float> [#uses=1]
+ %34 = fmul float %9, undef ; <float> [#uses=1]
+ %35 = fadd float %33, %34 ; <float> [#uses=1]
+ %36 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
+ %37 = fmul float %7, undef ; <float> [#uses=1]
+ %38 = fadd float %36, %37 ; <float> [#uses=1]
+ %39 = fmul float undef, undef ; <float> [#uses=1]
+ %40 = fadd float %38, %39 ; <float> [#uses=1]
+ store float %12, float* undef, align 8
+ store float %17, float* undef, align 4
+ store float %21, float* undef, align 8
+ store float %27, float* undef, align 8
+ store float %29, float* undef, align 4
+ store float %31, float* undef, align 8
+ store float %40, float* undef, align 8
+ store float %12, float* null, align 8
+ %41 = fmul float %17, undef ; <float> [#uses=1]
+ %42 = fadd float %41, undef ; <float> [#uses=1]
+ %43 = fmul float %35, undef ; <float> [#uses=1]
+ %44 = fadd float %42, %43 ; <float> [#uses=1]
+ store float %44, float* null, align 4
+ unreachable
+}
diff --git a/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll b/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll
new file mode 100644
index 0000000..efc4be1
--- /dev/null
+++ b/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll
@@ -0,0 +1,20 @@
+; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
+; PR5410
+
+%0 = type { float, float, float, float }
+%pln = type { %vec, float }
+%vec = type { [4 x float] }
+
+define arm_aapcs_vfpcc float @aaa(%vec* nocapture %ustart, %vec* nocapture %udir, %vec* nocapture %vstart, %vec* nocapture %vdir, %vec* %upoint, %vec* %vpoint) {
+entry:
+ br i1 undef, label %bb81, label %bb48
+
+bb48: ; preds = %entry
+ %0 = call arm_aapcs_vfpcc %0 @bbb(%pln* undef, %vec* %vstart, %vec* undef) nounwind ; <%0> [#uses=0]
+ ret float 0.000000e+00
+
+bb81: ; preds = %entry
+ ret float 0.000000e+00
+}
+
+declare arm_aapcs_vfpcc %0 @bbb(%pln* nocapture, %vec* nocapture, %vec* nocapture) nounwind
diff --git a/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll b/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll
new file mode 100644
index 0000000..6cce02d
--- /dev/null
+++ b/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll
@@ -0,0 +1,42 @@
+; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
+; PR5411
+
+%bar = type { %quad, float, float, [3 x %quux*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 }
+%baz = type { %bar*, i32 }
+%foo = type { i8, %quuz, %quad, float, [64 x %quux], [128 x %bar], i32, %baz, %baz }
+%quad = type { [4 x float] }
+%quux = type { %quad, %quad }
+%quuz = type { [4 x %quux*], [4 x float], i32 }
+
+define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quux* %a, %quux* %b, %quux* %c, i8 zeroext %forced) {
+entry:
+ br i1 undef, label %bb85, label %bb
+
+bb: ; preds = %entry
+ %0 = getelementptr inbounds %bar* null, i32 0, i32 0, i32 0, i32 2 ; <float*> [#uses=2]
+ %1 = load float* undef, align 4 ; <float> [#uses=1]
+ %2 = fsub float 0.000000e+00, undef ; <float> [#uses=2]
+ %3 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
+ %4 = load float* %0, align 4 ; <float> [#uses=3]
+ %5 = fmul float %4, %2 ; <float> [#uses=1]
+ %6 = fsub float %3, %5 ; <float> [#uses=1]
+ %7 = fmul float %4, undef ; <float> [#uses=1]
+ %8 = fsub float %7, undef ; <float> [#uses=1]
+ %9 = fmul float undef, %2 ; <float> [#uses=1]
+ %10 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
+ %11 = fsub float %9, %10 ; <float> [#uses=1]
+ %12 = fmul float undef, %6 ; <float> [#uses=1]
+ %13 = fmul float 0.000000e+00, %8 ; <float> [#uses=1]
+ %14 = fadd float %12, %13 ; <float> [#uses=1]
+ %15 = fmul float %1, %11 ; <float> [#uses=1]
+ %16 = fadd float %14, %15 ; <float> [#uses=1]
+ %17 = select i1 undef, float undef, float %16 ; <float> [#uses=1]
+ %18 = fdiv float %17, 0.000000e+00 ; <float> [#uses=1]
+ store float %18, float* undef, align 4
+ %19 = fmul float %4, undef ; <float> [#uses=1]
+ store float %19, float* %0, align 4
+ ret %bar* null
+
+bb85: ; preds = %entry
+ ret %bar* null
+}
diff --git a/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll b/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll
new file mode 100644
index 0000000..3ff6631
--- /dev/null
+++ b/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll
@@ -0,0 +1,123 @@
+; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
+; PR5412
+
+%bar = type { %quad, float, float, [3 x %quuz*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 }
+%baz = type { %bar*, i32 }
+%foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz }
+%quad = type { [4 x float] }
+%quux = type { [4 x %quuz*], [4 x float], i32 }
+%quuz = type { %quad, %quad }
+
+define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quuz* %a, %quuz* %b, %quuz* %c, i8 zeroext %forced) {
+entry:
+ br i1 undef, label %bb85, label %bb
+
+bb: ; preds = %entry
+ br i1 undef, label %bb3.i, label %bb2.i
+
+bb2.i: ; preds = %bb
+ br label %bb3.i
+
+bb3.i: ; preds = %bb2.i, %bb
+ %0 = getelementptr inbounds %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=0]
+ %1 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
+ %2 = getelementptr inbounds %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2]
+ %3 = load float* %2, align 4 ; <float> [#uses=1]
+ %4 = getelementptr inbounds %quuz* %a, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
+ %5 = fsub float %3, undef ; <float> [#uses=2]
+ %6 = getelementptr inbounds %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=2]
+ %7 = load float* %6, align 4 ; <float> [#uses=1]
+ %8 = fsub float %7, undef ; <float> [#uses=1]
+ %9 = getelementptr inbounds %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=2]
+ %10 = load float* %9, align 4 ; <float> [#uses=1]
+ %11 = fsub float %10, undef ; <float> [#uses=2]
+ %12 = getelementptr inbounds %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2]
+ %13 = load float* %12, align 4 ; <float> [#uses=1]
+ %14 = fsub float %13, undef ; <float> [#uses=1]
+ %15 = load float* undef, align 4 ; <float> [#uses=1]
+ %16 = fsub float %15, undef ; <float> [#uses=1]
+ %17 = fmul float %5, %16 ; <float> [#uses=1]
+ %18 = fsub float %17, 0.000000e+00 ; <float> [#uses=5]
+ %19 = fmul float %8, %11 ; <float> [#uses=1]
+ %20 = fsub float %19, undef ; <float> [#uses=3]
+ %21 = fmul float %1, %14 ; <float> [#uses=1]
+ %22 = fmul float %5, %11 ; <float> [#uses=1]
+ %23 = fsub float %21, %22 ; <float> [#uses=2]
+ store float %18, float* undef
+ %24 = getelementptr inbounds %bar* null, i32 0, i32 0, i32 0, i32 1 ; <float*> [#uses=2]
+ store float %20, float* %24
+ store float %23, float* undef
+ %25 = getelementptr inbounds %bar* null, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=0]
+ %26 = fmul float %18, %18 ; <float> [#uses=1]
+ %27 = fadd float %26, undef ; <float> [#uses=1]
+ %28 = fadd float %27, undef ; <float> [#uses=1]
+ %29 = call arm_aapcs_vfpcc float @sqrtf(float %28) readnone ; <float> [#uses=1]
+ %30 = load float* null, align 4 ; <float> [#uses=2]
+ %31 = load float* %4, align 4 ; <float> [#uses=2]
+ %32 = load float* %2, align 4 ; <float> [#uses=2]
+ %33 = load float* null, align 4 ; <float> [#uses=3]
+ %34 = load float* %6, align 4 ; <float> [#uses=2]
+ %35 = fsub float %33, %34 ; <float> [#uses=2]
+ %36 = fmul float %20, %35 ; <float> [#uses=1]
+ %37 = fsub float %36, undef ; <float> [#uses=1]
+ %38 = fmul float %23, 0.000000e+00 ; <float> [#uses=1]
+ %39 = fmul float %18, %35 ; <float> [#uses=1]
+ %40 = fsub float %38, %39 ; <float> [#uses=1]
+ %41 = fmul float %18, 0.000000e+00 ; <float> [#uses=1]
+ %42 = fmul float %20, 0.000000e+00 ; <float> [#uses=1]
+ %43 = fsub float %41, %42 ; <float> [#uses=1]
+ %44 = fmul float 0.000000e+00, %37 ; <float> [#uses=1]
+ %45 = fmul float %31, %40 ; <float> [#uses=1]
+ %46 = fadd float %44, %45 ; <float> [#uses=1]
+ %47 = fmul float %33, %43 ; <float> [#uses=1]
+ %48 = fadd float %46, %47 ; <float> [#uses=2]
+ %49 = load float* %9, align 4 ; <float> [#uses=2]
+ %50 = fsub float %30, %49 ; <float> [#uses=1]
+ %51 = load float* %12, align 4 ; <float> [#uses=3]
+ %52 = fsub float %32, %51 ; <float> [#uses=2]
+ %53 = load float* undef, align 4 ; <float> [#uses=2]
+ %54 = load float* %24, align 4 ; <float> [#uses=2]
+ %55 = fmul float %54, undef ; <float> [#uses=1]
+ %56 = fmul float undef, %52 ; <float> [#uses=1]
+ %57 = fsub float %55, %56 ; <float> [#uses=1]
+ %58 = fmul float undef, %52 ; <float> [#uses=1]
+ %59 = fmul float %54, %50 ; <float> [#uses=1]
+ %60 = fsub float %58, %59 ; <float> [#uses=1]
+ %61 = fmul float %30, %57 ; <float> [#uses=1]
+ %62 = fmul float %32, 0.000000e+00 ; <float> [#uses=1]
+ %63 = fadd float %61, %62 ; <float> [#uses=1]
+ %64 = fmul float %34, %60 ; <float> [#uses=1]
+ %65 = fadd float %63, %64 ; <float> [#uses=2]
+ %66 = fcmp olt float %48, %65 ; <i1> [#uses=1]
+ %67 = fsub float %49, 0.000000e+00 ; <float> [#uses=1]
+ %68 = fsub float %51, %31 ; <float> [#uses=1]
+ %69 = fsub float %53, %33 ; <float> [#uses=1]
+ %70 = fmul float undef, %67 ; <float> [#uses=1]
+ %71 = load float* undef, align 4 ; <float> [#uses=2]
+ %72 = fmul float %71, %69 ; <float> [#uses=1]
+ %73 = fsub float %70, %72 ; <float> [#uses=1]
+ %74 = fmul float %71, %68 ; <float> [#uses=1]
+ %75 = fsub float %74, 0.000000e+00 ; <float> [#uses=1]
+ %76 = fmul float %51, %73 ; <float> [#uses=1]
+ %77 = fadd float undef, %76 ; <float> [#uses=1]
+ %78 = fmul float %53, %75 ; <float> [#uses=1]
+ %79 = fadd float %77, %78 ; <float> [#uses=1]
+ %80 = select i1 %66, float %48, float %65 ; <float> [#uses=1]
+ %81 = select i1 undef, float %80, float %79 ; <float> [#uses=1]
+ %iftmp.164.0 = select i1 undef, float %29, float 1.000000e+00 ; <float> [#uses=1]
+ %82 = fdiv float %81, %iftmp.164.0 ; <float> [#uses=1]
+ %iftmp.165.0 = select i1 undef, float %82, float 0.000000e+00 ; <float> [#uses=1]
+ store float %iftmp.165.0, float* undef, align 4
+ br i1 false, label %bb4.i97, label %ccc.exit98
+
+bb4.i97: ; preds = %bb3.i
+ br label %ccc.exit98
+
+ccc.exit98: ; preds = %bb4.i97, %bb3.i
+ ret %bar* null
+
+bb85: ; preds = %entry
+ ret %bar* null
+}
+
+declare arm_aapcs_vfpcc float @sqrtf(float) readnone
diff --git a/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll b/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll
new file mode 100644
index 0000000..832ff4f
--- /dev/null
+++ b/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll
@@ -0,0 +1,113 @@
+; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
+; PR5412
+; rdar://7384107
+
+%bar = type { %quad, float, float, [3 x %quuz*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 }
+%baz = type { %bar*, i32 }
+%foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz }
+%quad = type { [4 x float] }
+%quux = type { [4 x %quuz*], [4 x float], i32 }
+%quuz = type { %quad, %quad }
+
+define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quuz* %a, %quuz* %b, %quuz* %c, i8 zeroext %forced) {
+entry:
+ %0 = load %bar** undef, align 4 ; <%bar*> [#uses=2]
+ br i1 false, label %bb85, label %bb
+
+bb: ; preds = %entry
+ br i1 undef, label %bb3.i, label %bb2.i
+
+bb2.i: ; preds = %bb
+ br label %bb3.i
+
+bb3.i: ; preds = %bb2.i, %bb
+ %1 = getelementptr inbounds %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1]
+ %2 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
+ %3 = getelementptr inbounds %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
+ %4 = getelementptr inbounds %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=1]
+ %5 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
+ %6 = getelementptr inbounds %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1]
+ %7 = getelementptr inbounds %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
+ %8 = fsub float undef, undef ; <float> [#uses=1]
+ %9 = fmul float 0.000000e+00, %8 ; <float> [#uses=1]
+ %10 = fmul float %5, 0.000000e+00 ; <float> [#uses=1]
+ %11 = fsub float %9, %10 ; <float> [#uses=3]
+ %12 = fmul float %2, 0.000000e+00 ; <float> [#uses=1]
+ %13 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
+ %14 = fsub float %12, %13 ; <float> [#uses=2]
+ store float %14, float* undef
+ %15 = getelementptr inbounds %bar* %0, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=1]
+ store float 0.000000e+00, float* %15
+ %16 = fmul float %11, %11 ; <float> [#uses=1]
+ %17 = fadd float %16, 0.000000e+00 ; <float> [#uses=1]
+ %18 = fadd float %17, undef ; <float> [#uses=1]
+ %19 = call arm_aapcs_vfpcc float @sqrtf(float %18) readnone ; <float> [#uses=2]
+ %20 = fcmp ogt float %19, 0x3F1A36E2E0000000 ; <i1> [#uses=1]
+ %21 = load float* %1, align 4 ; <float> [#uses=2]
+ %22 = load float* %3, align 4 ; <float> [#uses=2]
+ %23 = load float* undef, align 4 ; <float> [#uses=2]
+ %24 = load float* %4, align 4 ; <float> [#uses=2]
+ %25 = fsub float %23, %24 ; <float> [#uses=2]
+ %26 = fmul float 0.000000e+00, %25 ; <float> [#uses=1]
+ %27 = fsub float %26, undef ; <float> [#uses=1]
+ %28 = fmul float %14, 0.000000e+00 ; <float> [#uses=1]
+ %29 = fmul float %11, %25 ; <float> [#uses=1]
+ %30 = fsub float %28, %29 ; <float> [#uses=1]
+ %31 = fsub float undef, 0.000000e+00 ; <float> [#uses=1]
+ %32 = fmul float %21, %27 ; <float> [#uses=1]
+ %33 = fmul float undef, %30 ; <float> [#uses=1]
+ %34 = fadd float %32, %33 ; <float> [#uses=1]
+ %35 = fmul float %23, %31 ; <float> [#uses=1]
+ %36 = fadd float %34, %35 ; <float> [#uses=1]
+ %37 = load float* %6, align 4 ; <float> [#uses=2]
+ %38 = load float* %7, align 4 ; <float> [#uses=2]
+ %39 = fsub float %22, %38 ; <float> [#uses=2]
+ %40 = load float* undef, align 4 ; <float> [#uses=1]
+ %41 = load float* null, align 4 ; <float> [#uses=2]
+ %42 = fmul float %41, undef ; <float> [#uses=1]
+ %43 = fmul float undef, %39 ; <float> [#uses=1]
+ %44 = fsub float %42, %43 ; <float> [#uses=1]
+ %45 = fmul float undef, %39 ; <float> [#uses=1]
+ %46 = fmul float %41, 0.000000e+00 ; <float> [#uses=1]
+ %47 = fsub float %45, %46 ; <float> [#uses=1]
+ %48 = fmul float 0.000000e+00, %44 ; <float> [#uses=1]
+ %49 = fmul float %22, undef ; <float> [#uses=1]
+ %50 = fadd float %48, %49 ; <float> [#uses=1]
+ %51 = fmul float %24, %47 ; <float> [#uses=1]
+ %52 = fadd float %50, %51 ; <float> [#uses=1]
+ %53 = fsub float %37, %21 ; <float> [#uses=2]
+ %54 = fmul float undef, undef ; <float> [#uses=1]
+ %55 = fmul float undef, undef ; <float> [#uses=1]
+ %56 = fsub float %54, %55 ; <float> [#uses=1]
+ %57 = fmul float undef, %53 ; <float> [#uses=1]
+ %58 = load float* undef, align 4 ; <float> [#uses=2]
+ %59 = fmul float %58, undef ; <float> [#uses=1]
+ %60 = fsub float %57, %59 ; <float> [#uses=1]
+ %61 = fmul float %58, undef ; <float> [#uses=1]
+ %62 = fmul float undef, %53 ; <float> [#uses=1]
+ %63 = fsub float %61, %62 ; <float> [#uses=1]
+ %64 = fmul float %37, %56 ; <float> [#uses=1]
+ %65 = fmul float %38, %60 ; <float> [#uses=1]
+ %66 = fadd float %64, %65 ; <float> [#uses=1]
+ %67 = fmul float %40, %63 ; <float> [#uses=1]
+ %68 = fadd float %66, %67 ; <float> [#uses=1]
+ %69 = select i1 undef, float %36, float %52 ; <float> [#uses=1]
+ %70 = select i1 undef, float %69, float %68 ; <float> [#uses=1]
+ %iftmp.164.0 = select i1 %20, float %19, float 1.000000e+00 ; <float> [#uses=1]
+ %71 = fdiv float %70, %iftmp.164.0 ; <float> [#uses=1]
+ store float %71, float* null, align 4
+ %72 = icmp eq %bar* null, %0 ; <i1> [#uses=1]
+ br i1 %72, label %bb4.i97, label %ccc.exit98
+
+bb4.i97: ; preds = %bb3.i
+ %73 = load %bar** undef, align 4 ; <%bar*> [#uses=0]
+ br label %ccc.exit98
+
+ccc.exit98: ; preds = %bb4.i97, %bb3.i
+ ret %bar* null
+
+bb85: ; preds = %entry
+ ret %bar* null
+}
+
+declare arm_aapcs_vfpcc float @sqrtf(float) readnone
diff --git a/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll b/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll
new file mode 100644
index 0000000..efe74cf
--- /dev/null
+++ b/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll
@@ -0,0 +1,41 @@
+; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
+; PR5614
+
+%"als" = type { i32 (...)** }
+%"av" = type { %"als" }
+%"c" = type { %"lsm", %"Vec3", %"av"*, float, i8, float, %"lsm", i8, %"Vec3", %"Vec3", %"Vec3", float, float, float, %"Vec3", %"Vec3" }
+%"lsm" = type { %"als", %"Vec3", %"Vec3", %"Vec3", %"Vec3" }
+%"Vec3" = type { float, float, float }
+
+define arm_aapcs_vfpcc void @foo(%"c"* %this, %"Vec3"* nocapture %adjustment) {
+entry:
+ switch i32 undef, label %return [
+ i32 1, label %bb
+ i32 2, label %bb72
+ i32 3, label %bb31
+ i32 4, label %bb79
+ i32 5, label %bb104
+ ]
+
+bb: ; preds = %entry
+ ret void
+
+bb31: ; preds = %entry
+ %0 = call arm_aapcs_vfpcc %"Vec3" undef(%"lsm"* undef) ; <%"Vec3"> [#uses=1]
+ %mrv_gr69 = extractvalue %"Vec3" %0, 1 ; <float> [#uses=1]
+ %1 = fsub float %mrv_gr69, undef ; <float> [#uses=1]
+ store float %1, float* undef, align 4
+ ret void
+
+bb72: ; preds = %entry
+ ret void
+
+bb79: ; preds = %entry
+ ret void
+
+bb104: ; preds = %entry
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll b/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll
new file mode 100644
index 0000000..a737591
--- /dev/null
+++ b/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll
@@ -0,0 +1,19 @@
+; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
+target triple = "armv7-apple-darwin10"
+
+%struct.int16x8_t = type { <8 x i16> }
+%struct.int16x8x2_t = type { [2 x %struct.int16x8_t] }
+
+define arm_apcscc void @t(%struct.int16x8x2_t* noalias nocapture sret %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind {
+entry:
+;CHECK: vtrn.16
+ %0 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
+ %1 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
+ %agg.result1218.0 = getelementptr %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 0, i32 0 ; <<8 x i16>*>
+ store <8 x i16> %0, <8 x i16>* %agg.result1218.0, align 16
+ %agg.result12.1.0 = getelementptr %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 1, i32 0 ; <<8 x i16>*>
+ store <8 x i16> %1, <8 x i16>* %agg.result12.1.0, align 16
+ ret void
+}
diff --git a/test/CodeGen/ARM/addrmode.ll b/test/CodeGen/ARM/addrmode.ll
new file mode 100644
index 0000000..9ccff07
--- /dev/null
+++ b/test/CodeGen/ARM/addrmode.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=arm -stats |& grep asm-printer | grep 4
+
+define i32 @t1(i32 %a) {
+ %b = mul i32 %a, 9
+ %c = inttoptr i32 %b to i32*
+ %d = load i32* %c
+ ret i32 %d
+}
+
+define i32 @t2(i32 %a) {
+ %b = mul i32 %a, -7
+ %c = inttoptr i32 %b to i32*
+ %d = load i32* %c
+ ret i32 %d
+}
diff --git a/test/CodeGen/ARM/aliases.ll b/test/CodeGen/ARM/aliases.ll
new file mode 100644
index 0000000..31c5007
--- /dev/null
+++ b/test/CodeGen/ARM/aliases.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi -o %t
+; RUN: grep { = } %t | count 5
+; RUN: grep globl %t | count 4
+; RUN: grep weak %t | count 1
+
+@bar = external global i32
+@foo1 = alias i32* @bar
+@foo2 = alias i32* @bar
+
+%FunTy = type i32()
+
+declare i32 @foo_f()
+@bar_f = alias weak %FunTy* @foo_f
+
+@bar_i = alias internal i32* @bar
+
+@A = alias bitcast (i32* @bar to i64*)
+
+define i32 @test() {
+entry:
+ %tmp = load i32* @foo1
+ %tmp1 = load i32* @foo2
+ %tmp0 = load i32* @bar_i
+ %tmp2 = call i32 @foo_f()
+ %tmp3 = add i32 %tmp, %tmp2
+ %tmp4 = call %FunTy* @bar_f()
+ %tmp5 = add i32 %tmp3, %tmp4
+ %tmp6 = add i32 %tmp1, %tmp5
+ %tmp7 = add i32 %tmp6, %tmp0
+ ret i32 %tmp7
+}
diff --git a/test/CodeGen/ARM/align.ll b/test/CodeGen/ARM/align.ll
new file mode 100644
index 0000000..d4d01288
--- /dev/null
+++ b/test/CodeGen/ARM/align.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=ELF
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
+
+@a = global i1 true
+; no alignment
+
+@b = global i8 1
+; no alignment
+
+@c = global i16 2
+;ELF: .align 1
+;ELF: c:
+;DARWIN: .align 1
+;DARWIN: _c:
+
+@d = global i32 3
+;ELF: .align 2
+;ELF: d:
+;DARWIN: .align 2
+;DARWIN: _d:
+
+@e = global i64 4
+;ELF: .align 3
+;ELF: e
+;DARWIN: .align 2
+;DARWIN: _e:
+
+@f = global float 5.0
+;ELF: .align 2
+;ELF: f:
+;DARWIN: .align 2
+;DARWIN: _f:
+
+@g = global double 6.0
+;ELF: .align 3
+;ELF: g:
+;DARWIN: .align 2
+;DARWIN: _g:
+
+@bar = common global [75 x i8] zeroinitializer, align 128
+;ELF: .comm bar,75,128
+;DARWIN: .comm _bar,75,7
diff --git a/test/CodeGen/ARM/alloca.ll b/test/CodeGen/ARM/alloca.ll
new file mode 100644
index 0000000..82a8c98
--- /dev/null
+++ b/test/CodeGen/ARM/alloca.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | FileCheck %s
+
+define void @f(i32 %a) {
+entry:
+; CHECK: mov r11, sp
+ %tmp = alloca i8, i32 %a ; <i8*> [#uses=1]
+ call void @g( i8* %tmp, i32 %a, i32 1, i32 2, i32 3 )
+ ret void
+; CHECK: mov sp, r11
+}
+
+declare void @g(i8*, i32, i32, i32, i32)
diff --git a/test/CodeGen/ARM/argaddr.ll b/test/CodeGen/ARM/argaddr.ll
new file mode 100644
index 0000000..116a32f
--- /dev/null
+++ b/test/CodeGen/ARM/argaddr.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=arm
+
+define void @f(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
+entry:
+ %a_addr = alloca i32 ; <i32*> [#uses=2]
+ %b_addr = alloca i32 ; <i32*> [#uses=2]
+ %c_addr = alloca i32 ; <i32*> [#uses=2]
+ %d_addr = alloca i32 ; <i32*> [#uses=2]
+ %e_addr = alloca i32 ; <i32*> [#uses=2]
+ store i32 %a, i32* %a_addr
+ store i32 %b, i32* %b_addr
+ store i32 %c, i32* %c_addr
+ store i32 %d, i32* %d_addr
+ store i32 %e, i32* %e_addr
+ call void @g( i32* %a_addr, i32* %b_addr, i32* %c_addr, i32* %d_addr, i32* %e_addr )
+ ret void
+}
+
+declare void @g(i32*, i32*, i32*, i32*, i32*)
diff --git a/test/CodeGen/ARM/arguments-nosplit-double.ll b/test/CodeGen/ARM/arguments-nosplit-double.ll
new file mode 100644
index 0000000..770e41d
--- /dev/null
+++ b/test/CodeGen/ARM/arguments-nosplit-double.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | not grep r3
+; PR4059
+
+define i32 @f(i64 %z, i32 %a, double %b) {
+ %tmp = call i32 @g(double %b)
+ ret i32 %tmp
+}
+
+declare i32 @g(double)
diff --git a/test/CodeGen/ARM/arguments-nosplit-i64.ll b/test/CodeGen/ARM/arguments-nosplit-i64.ll
new file mode 100644
index 0000000..815edfd
--- /dev/null
+++ b/test/CodeGen/ARM/arguments-nosplit-i64.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | not grep r3
+; PR4058
+
+define i32 @f(i64 %z, i32 %a, i64 %b) {
+ %tmp = call i32 @g(i64 %b)
+ ret i32 %tmp
+}
+
+declare i32 @g(i64)
diff --git a/test/CodeGen/ARM/arguments.ll b/test/CodeGen/ARM/arguments.ll
new file mode 100644
index 0000000..cc71839
--- /dev/null
+++ b/test/CodeGen/ARM/arguments.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=ELF
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
+
+define i32 @f(i32 %a, i64 %b) {
+; ELF: mov r0, r2
+; DARWIN: mov r0, r1
+ %tmp = call i32 @g(i64 %b)
+ ret i32 %tmp
+}
+
+declare i32 @g(i64)
diff --git a/test/CodeGen/ARM/arguments2.ll b/test/CodeGen/ARM/arguments2.ll
new file mode 100644
index 0000000..a515ad7
--- /dev/null
+++ b/test/CodeGen/ARM/arguments2.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+define i32 @f(i32 %a, i128 %b) {
+ %tmp = call i32 @g(i128 %b)
+ ret i32 %tmp
+}
+
+declare i32 @g(i128)
diff --git a/test/CodeGen/ARM/arguments3.ll b/test/CodeGen/ARM/arguments3.ll
new file mode 100644
index 0000000..58f64c6
--- /dev/null
+++ b/test/CodeGen/ARM/arguments3.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+define i64 @f(i32 %a, i128 %b) {
+ %tmp = call i64 @g(i128 %b)
+ ret i64 %tmp
+}
+
+declare i64 @g(i128)
diff --git a/test/CodeGen/ARM/arguments4.ll b/test/CodeGen/ARM/arguments4.ll
new file mode 100644
index 0000000..f5f4207
--- /dev/null
+++ b/test/CodeGen/ARM/arguments4.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+define float @f(i32 %a, i128 %b) {
+ %tmp = call float @g(i128 %b)
+ ret float %tmp
+}
+
+declare float @g(i128)
diff --git a/test/CodeGen/ARM/arguments5.ll b/test/CodeGen/ARM/arguments5.ll
new file mode 100644
index 0000000..388a8eb
--- /dev/null
+++ b/test/CodeGen/ARM/arguments5.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+define double @f(i32 %a, i128 %b) {
+ %tmp = call double @g(i128 %b)
+ ret double %tmp
+}
+
+declare double @g(i128)
diff --git a/test/CodeGen/ARM/arguments6.ll b/test/CodeGen/ARM/arguments6.ll
new file mode 100644
index 0000000..3f757fe
--- /dev/null
+++ b/test/CodeGen/ARM/arguments6.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+define i128 @f(i32 %a, i128 %b) {
+ %tmp = call i128 @g(i128 %b)
+ ret i128 %tmp
+}
+
+declare i128 @g(i128)
diff --git a/test/CodeGen/ARM/arguments7.ll b/test/CodeGen/ARM/arguments7.ll
new file mode 100644
index 0000000..038e417
--- /dev/null
+++ b/test/CodeGen/ARM/arguments7.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+define double @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, double %b) {
+ %tmp = call double @g(i32 %a2, i32 %a3, i32 %a4, i32 %a5, double %b)
+ ret double %tmp
+}
+
+declare double @g(double)
diff --git a/test/CodeGen/ARM/arguments8.ll b/test/CodeGen/ARM/arguments8.ll
new file mode 100644
index 0000000..6999a4d
--- /dev/null
+++ b/test/CodeGen/ARM/arguments8.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi
+; RUN: llc < %s -mtriple=arm-apple-darwin
+
+define i64 @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i64 %b) {
+ %tmp = call i64 @g(i32 %a2, i32 %a3, i32 %a4, i32 %a5, i64 %b)
+ ret i64 %tmp
+}
+
+declare i64 @g(i64)
diff --git a/test/CodeGen/ARM/arguments_f64_backfill.ll b/test/CodeGen/ARM/arguments_f64_backfill.ll
new file mode 100644
index 0000000..062133e
--- /dev/null
+++ b/test/CodeGen/ARM/arguments_f64_backfill.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi -mattr=+vfp2 -float-abi=hard | FileCheck %s
+
+define float @f(float %z, double %a, float %b) {
+; CHECK: vmov.f32 s0, s1
+ %tmp = call float @g(float %b)
+ ret float %tmp
+}
+
+declare float @g(float)
diff --git a/test/CodeGen/ARM/arm-asm.ll b/test/CodeGen/ARM/arm-asm.ll
new file mode 100644
index 0000000..2e35e39
--- /dev/null
+++ b/test/CodeGen/ARM/arm-asm.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=arm
+
+define void @frame_dummy() {
+entry:
+ %tmp1 = tail call void (i8*)* (void (i8*)*)* asm "", "=r,0,~{dirflag},~{fpsr},~{flags}"( void (i8*)* null ) ; <void (i8*)*> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/ARM/arm-frameaddr.ll b/test/CodeGen/ARM/arm-frameaddr.ll
new file mode 100644
index 0000000..2739860
--- /dev/null
+++ b/test/CodeGen/ARM/arm-frameaddr.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | grep r7
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | grep r11
+; PR4344
+; PR4416
+
+define arm_aapcscc i8* @t() nounwind {
+entry:
+ %0 = call i8* @llvm.frameaddress(i32 0)
+ ret i8* %0
+}
+
+declare i8* @llvm.frameaddress(i32) nounwind readnone
diff --git a/test/CodeGen/ARM/arm-negative-stride.ll b/test/CodeGen/ARM/arm-negative-stride.ll
new file mode 100644
index 0000000..72ec8ef
--- /dev/null
+++ b/test/CodeGen/ARM/arm-negative-stride.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+
+define void @test(i32* %P, i32 %A, i32 %i) nounwind {
+entry:
+; CHECK: str r1, [{{r.*}}, -{{r.*}}, lsl #2]
+ icmp eq i32 %i, 0 ; <i1>:0 [#uses=1]
+ br i1 %0, label %return, label %bb
+
+bb: ; preds = %bb, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
+ %i_addr.09.0 = sub i32 %i, %indvar ; <i32> [#uses=1]
+ %tmp2 = getelementptr i32* %P, i32 %i_addr.09.0 ; <i32*> [#uses=1]
+ store i32 %A, i32* %tmp2
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
+ icmp eq i32 %indvar.next, %i ; <i1>:1 [#uses=1]
+ br i1 %1, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ ret void
+}
+
diff --git a/test/CodeGen/ARM/bfc.ll b/test/CodeGen/ARM/bfc.ll
new file mode 100644
index 0000000..c4a44b4
--- /dev/null
+++ b/test/CodeGen/ARM/bfc.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
+
+; 4278190095 = 0xff00000f
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: bfc
+ %tmp = and i32 %a, 4278190095
+ ret i32 %tmp
+}
+
+; 4286578688 = 0xff800000
+define i32 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: bfc
+ %tmp = and i32 %a, 4286578688
+ ret i32 %tmp
+}
+
+; 4095 = 0x00000fff
+define i32 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: bfc
+ %tmp = and i32 %a, 4095
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/ARM/bic.ll b/test/CodeGen/ARM/bic.ll
new file mode 100644
index 0000000..1dfd627
--- /dev/null
+++ b/test/CodeGen/ARM/bic.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b) {
+ %tmp = xor i32 %b, 4294967295
+ %tmp1 = and i32 %a, %tmp
+ ret i32 %tmp1
+}
+
+; CHECK: bic r0, r0, r1
+
+define i32 @f2(i32 %a, i32 %b) {
+ %tmp = xor i32 %b, 4294967295
+ %tmp1 = and i32 %tmp, %a
+ ret i32 %tmp1
+}
+
+; CHECK: bic r0, r0, r1
diff --git a/test/CodeGen/ARM/bits.ll b/test/CodeGen/ARM/bits.ll
new file mode 100644
index 0000000..9e94efe
--- /dev/null
+++ b/test/CodeGen/ARM/bits.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -march=arm > %t
+; RUN: grep and %t | count 1
+; RUN: grep orr %t | count 1
+; RUN: grep eor %t | count 1
+; RUN: grep mov.*lsl %t | count 1
+; RUN: grep mov.*asr %t | count 1
+
+define i32 @f1(i32 %a, i32 %b) {
+entry:
+ %tmp2 = and i32 %b, %a ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
+
+define i32 @f2(i32 %a, i32 %b) {
+entry:
+ %tmp2 = or i32 %b, %a ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
+
+define i32 @f3(i32 %a, i32 %b) {
+entry:
+ %tmp2 = xor i32 %b, %a ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
+
+define i32 @f4(i32 %a, i32 %b) {
+entry:
+ %tmp3 = shl i32 %a, %b ; <i32> [#uses=1]
+ ret i32 %tmp3
+}
+
+define i32 @f5(i32 %a, i32 %b) {
+entry:
+ %tmp3 = ashr i32 %a, %b ; <i32> [#uses=1]
+ ret i32 %tmp3
+}
diff --git a/test/CodeGen/ARM/bx_fold.ll b/test/CodeGen/ARM/bx_fold.ll
new file mode 100644
index 0000000..0e3e070
--- /dev/null
+++ b/test/CodeGen/ARM/bx_fold.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm | not grep bx
+
+define void @test(i32 %Ptr, i8* %L) {
+entry:
+ br label %bb1
+
+bb: ; preds = %bb1
+ %gep.upgrd.1 = zext i32 %indvar to i64 ; <i64> [#uses=1]
+ %tmp7 = getelementptr i8* %L, i64 %gep.upgrd.1 ; <i8*> [#uses=1]
+ store i8 0, i8* %tmp7
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br label %bb1
+
+bb1: ; preds = %bb, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
+ %i.0 = bitcast i32 %indvar to i32 ; <i32> [#uses=2]
+ %tmp = tail call i32 (...)* @bar( ) ; <i32> [#uses=1]
+ %tmp2 = add i32 %i.0, %tmp ; <i32> [#uses=1]
+ %Ptr_addr.0 = sub i32 %Ptr, %tmp2 ; <i32> [#uses=0]
+ %tmp12 = icmp eq i32 %i.0, %Ptr ; <i1> [#uses=1]
+ %tmp12.not = xor i1 %tmp12, true ; <i1> [#uses=1]
+ %bothcond = and i1 %tmp12.not, false ; <i1> [#uses=1]
+ br i1 %bothcond, label %bb, label %bb18
+
+bb18: ; preds = %bb1
+ ret void
+}
+
+declare i32 @bar(...)
diff --git a/test/CodeGen/ARM/call.ll b/test/CodeGen/ARM/call.ll
new file mode 100644
index 0000000..3dd66ae
--- /dev/null
+++ b/test/CodeGen/ARM/call.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECKV4
+; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\
+; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF
+
+@t = weak global i32 ()* null ; <i32 ()**> [#uses=1]
+
+declare void @g(i32, i32, i32, i32)
+
+define void @f() {
+; CHECKV4: mov lr, pc
+; CHECKV5: blx
+; CHECKELF: PLT
+ call void @g( i32 1, i32 2, i32 3, i32 4 )
+ ret void
+}
+
+define void @g.upgrd.1() {
+ %tmp = load i32 ()** @t ; <i32 ()*> [#uses=1]
+ %tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/ARM/call_nolink.ll b/test/CodeGen/ARM/call_nolink.ll
new file mode 100644
index 0000000..efe29d8
--- /dev/null
+++ b/test/CodeGen/ARM/call_nolink.ll
@@ -0,0 +1,52 @@
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \
+; RUN: not grep {bx lr}
+
+ %struct.anon = type { i32 (i32, i32, i32)*, i32, i32, [3 x i32], i8*, i8*, i8* }
+@r = external global [14 x i32] ; <[14 x i32]*> [#uses=4]
+@isa = external global [13 x %struct.anon] ; <[13 x %struct.anon]*> [#uses=1]
+@pgm = external global [2 x { i32, [3 x i32] }] ; <[2 x { i32, [3 x i32] }]*> [#uses=4]
+@numi = external global i32 ; <i32*> [#uses=1]
+@counter = external global [2 x i32] ; <[2 x i32]*> [#uses=1]
+
+
+define void @main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i() {
+newFuncRoot:
+ br label %bb115.i.i
+
+bb115.i.i.bb170.i.i_crit_edge.exitStub: ; preds = %bb115.i.i
+ ret void
+
+bb115.i.i.bb115.i.i_crit_edge: ; preds = %bb115.i.i
+ br label %bb115.i.i
+
+bb115.i.i: ; preds = %bb115.i.i.bb115.i.i_crit_edge, %newFuncRoot
+ %i_addr.3210.0.i.i = phi i32 [ %tmp166.i.i, %bb115.i.i.bb115.i.i_crit_edge ], [ 0, %newFuncRoot ] ; <i32> [#uses=7]
+ %tmp124.i.i = getelementptr [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 0 ; <i32*> [#uses=1]
+ %tmp125.i.i = load i32* %tmp124.i.i ; <i32> [#uses=1]
+ %tmp126.i.i = getelementptr [14 x i32]* @r, i32 0, i32 %tmp125.i.i ; <i32*> [#uses=1]
+ %tmp127.i.i = load i32* %tmp126.i.i ; <i32> [#uses=1]
+ %tmp131.i.i = getelementptr [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 1 ; <i32*> [#uses=1]
+ %tmp132.i.i = load i32* %tmp131.i.i ; <i32> [#uses=1]
+ %tmp133.i.i = getelementptr [14 x i32]* @r, i32 0, i32 %tmp132.i.i ; <i32*> [#uses=1]
+ %tmp134.i.i = load i32* %tmp133.i.i ; <i32> [#uses=1]
+ %tmp138.i.i = getelementptr [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 1, i32 2 ; <i32*> [#uses=1]
+ %tmp139.i.i = load i32* %tmp138.i.i ; <i32> [#uses=1]
+ %tmp140.i.i = getelementptr [14 x i32]* @r, i32 0, i32 %tmp139.i.i ; <i32*> [#uses=1]
+ %tmp141.i.i = load i32* %tmp140.i.i ; <i32> [#uses=1]
+ %tmp143.i.i = add i32 %i_addr.3210.0.i.i, 12 ; <i32> [#uses=1]
+ %tmp146.i.i = getelementptr [2 x { i32, [3 x i32] }]* @pgm, i32 0, i32 %i_addr.3210.0.i.i, i32 0 ; <i32*> [#uses=1]
+ %tmp147.i.i = load i32* %tmp146.i.i ; <i32> [#uses=1]
+ %tmp149.i.i = getelementptr [13 x %struct.anon]* @isa, i32 0, i32 %tmp147.i.i, i32 0 ; <i32 (i32, i32, i32)**> [#uses=1]
+ %tmp150.i.i = load i32 (i32, i32, i32)** %tmp149.i.i ; <i32 (i32, i32, i32)*> [#uses=1]
+ %tmp154.i.i = tail call i32 %tmp150.i.i( i32 %tmp127.i.i, i32 %tmp134.i.i, i32 %tmp141.i.i ) ; <i32> [#uses=1]
+ %tmp155.i.i = getelementptr [14 x i32]* @r, i32 0, i32 %tmp143.i.i ; <i32*> [#uses=1]
+ store i32 %tmp154.i.i, i32* %tmp155.i.i
+ %tmp159.i.i = getelementptr [2 x i32]* @counter, i32 0, i32 %i_addr.3210.0.i.i ; <i32*> [#uses=2]
+ %tmp160.i.i = load i32* %tmp159.i.i ; <i32> [#uses=1]
+ %tmp161.i.i = add i32 %tmp160.i.i, 1 ; <i32> [#uses=1]
+ store i32 %tmp161.i.i, i32* %tmp159.i.i
+ %tmp166.i.i = add i32 %i_addr.3210.0.i.i, 1 ; <i32> [#uses=2]
+ %tmp168.i.i = load i32* @numi ; <i32> [#uses=1]
+ icmp slt i32 %tmp166.i.i, %tmp168.i.i ; <i1>:0 [#uses=1]
+ br i1 %0, label %bb115.i.i.bb115.i.i_crit_edge, label %bb115.i.i.bb170.i.i_crit_edge.exitStub
+}
diff --git a/test/CodeGen/ARM/carry.ll b/test/CodeGen/ARM/carry.ll
new file mode 100644
index 0000000..a6a7ed6
--- /dev/null
+++ b/test/CodeGen/ARM/carry.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+
+define i64 @f1(i64 %a, i64 %b) {
+; CHECK: f1:
+; CHECK: subs r
+; CHECK: sbc r
+entry:
+ %tmp = sub i64 %a, %b
+ ret i64 %tmp
+}
+
+define i64 @f2(i64 %a, i64 %b) {
+; CHECK: f2:
+; CHECK: adc r
+; CHECK: subs r
+; CHECK: sbc r
+entry:
+ %tmp1 = shl i64 %a, 1
+ %tmp2 = sub i64 %tmp1, %b
+ ret i64 %tmp2
+}
diff --git a/test/CodeGen/ARM/clz.ll b/test/CodeGen/ARM/clz.ll
new file mode 100644
index 0000000..d2235c9
--- /dev/null
+++ b/test/CodeGen/ARM/clz.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=arm -mattr=+v5t | grep clz
+
+declare i32 @llvm.ctlz.i32(i32)
+
+define i32 @test(i32 %x) {
+ %tmp.1 = call i32 @llvm.ctlz.i32( i32 %x ) ; <i32> [#uses=1]
+ ret i32 %tmp.1
+}
diff --git a/test/CodeGen/ARM/compare-call.ll b/test/CodeGen/ARM/compare-call.ll
new file mode 100644
index 0000000..fac2bc5
--- /dev/null
+++ b/test/CodeGen/ARM/compare-call.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | \
+; RUN: grep vcmpe.f32
+
+define void @test3(float* %glob, i32 %X) {
+entry:
+ %tmp = load float* %glob ; <float> [#uses=1]
+ %tmp2 = getelementptr float* %glob, i32 2 ; <float*> [#uses=1]
+ %tmp3 = load float* %tmp2 ; <float> [#uses=1]
+ %tmp.upgrd.1 = fcmp ogt float %tmp, %tmp3 ; <i1> [#uses=1]
+ br i1 %tmp.upgrd.1, label %cond_true, label %UnifiedReturnBlock
+
+cond_true: ; preds = %entry
+ %tmp.upgrd.2 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+declare i32 @bar(...)
diff --git a/test/CodeGen/ARM/constants.ll b/test/CodeGen/ARM/constants.ll
new file mode 100644
index 0000000..ce91936
--- /dev/null
+++ b/test/CodeGen/ARM/constants.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+
+define i32 @f1() {
+; CHECK: f1
+; CHECK: mov r0, #0
+ ret i32 0
+}
+
+define i32 @f2() {
+; CHECK: f2
+; CHECK: mov r0, #255
+ ret i32 255
+}
+
+define i32 @f3() {
+; CHECK: f3
+; CHECK: mov r0{{.*}}256
+ ret i32 256
+}
+
+define i32 @f4() {
+; CHECK: f4
+; CHECK: orr{{.*}}256
+ ret i32 257
+}
+
+define i32 @f5() {
+; CHECK: f5
+; CHECK: mov r0, {{.*}}-1073741761
+ ret i32 -1073741761
+}
+
+define i32 @f6() {
+; CHECK: f6
+; CHECK: mov r0, {{.*}}1008
+ ret i32 1008
+}
+
+define void @f7(i32 %a) {
+; CHECK: f7
+; CHECK: cmp r0, #1, 16
+ %b = icmp ugt i32 %a, 65536 ; <i1> [#uses=1]
+ br i1 %b, label %r, label %r
+
+r: ; preds = %0, %0
+ ret void
+}
diff --git a/test/CodeGen/ARM/cse-libcalls.ll b/test/CodeGen/ARM/cse-libcalls.ll
new file mode 100644
index 0000000..0dcf9dd
--- /dev/null
+++ b/test/CodeGen/ARM/cse-libcalls.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=arm | grep {bl.\*__ltdf} | count 1
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+
+; Without CSE of libcalls, there are two calls in the output instead of one.
+
+define i32 @u_f_nonbon(double %lambda) nounwind {
+entry:
+ %tmp19.i.i = load double* null, align 4 ; <double> [#uses=2]
+ %tmp6.i = fcmp olt double %tmp19.i.i, 1.000000e+00 ; <i1> [#uses=1]
+ %dielectric.0.i = select i1 %tmp6.i, double 1.000000e+00, double %tmp19.i.i ; <double> [#uses=1]
+ %tmp10.i4 = fdiv double 0x4074C2D71F36262D, %dielectric.0.i ; <double> [#uses=1]
+ br i1 false, label %bb28.i, label %bb508.i
+
+bb28.i: ; preds = %bb28.i, %entry
+ br i1 false, label %bb502.loopexit.i, label %bb28.i
+
+bb.nph53.i: ; preds = %bb502.loopexit.i
+ %tmp354.i = fsub double -0.000000e+00, %tmp10.i4 ; <double> [#uses=0]
+ br label %bb244.i
+
+bb244.i: ; preds = %bb244.i, %bb.nph53.i
+ br label %bb244.i
+
+bb502.loopexit.i: ; preds = %bb28.i
+ br i1 false, label %bb.nph53.i, label %bb508.i
+
+bb508.i: ; preds = %bb502.loopexit.i, %entry
+ ret i32 1
+}
diff --git a/test/CodeGen/ARM/ctors_dtors.ll b/test/CodeGen/ARM/ctors_dtors.ll
new file mode 100644
index 0000000..fb94626
--- /dev/null
+++ b/test/CodeGen/ARM/ctors_dtors.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
+; RUN: llc < %s -mtriple=arm-linux-gnu | FileCheck %s -check-prefix=ELF
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=GNUEABI
+
+; DARWIN: .section __DATA,__mod_init_func,mod_init_funcs
+; DARWIN: .section __DATA,__mod_term_func,mod_term_funcs
+
+; ELF: .section .ctors,"aw",%progbits
+; ELF: .section .dtors,"aw",%progbits
+
+; GNUEABI: .section .init_array,"aw",%init_array
+; GNUEABI: .section .fini_array,"aw",%fini_array
+
[email protected]_ctors = appending global [1 x { i32, void ()* }] [ { i32, void ()* } { i32 65535, void ()* @__mf_init } ] ; <[1 x { i32, void ()* }]*> [#uses=0]
[email protected]_dtors = appending global [1 x { i32, void ()* }] [ { i32, void ()* } { i32 65535, void ()* @__mf_fini } ] ; <[1 x { i32, void ()* }]*> [#uses=0]
+
+define void @__mf_init() {
+entry:
+ ret void
+}
+
+define void @__mf_fini() {
+entry:
+ ret void
+}
diff --git a/test/CodeGen/ARM/ctz.ll b/test/CodeGen/ARM/ctz.ll
new file mode 100644
index 0000000..1d2ced3
--- /dev/null
+++ b/test/CodeGen/ARM/ctz.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
+
+declare i32 @llvm.cttz.i32(i32)
+
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: rbit
+; CHECK: clz
+ %tmp = call i32 @llvm.cttz.i32( i32 %a )
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/ARM/dg.exp b/test/CodeGen/ARM/dg.exp
new file mode 100644
index 0000000..3ff359a
--- /dev/null
+++ b/test/CodeGen/ARM/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target ARM] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/ARM/div.ll b/test/CodeGen/ARM/div.ll
new file mode 100644
index 0000000..2f724e7
--- /dev/null
+++ b/test/CodeGen/ARM/div.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=arm > %t
+; RUN: grep __divsi3 %t
+; RUN: grep __udivsi3 %t
+; RUN: grep __modsi3 %t
+; RUN: grep __umodsi3 %t
+
+define i32 @f1(i32 %a, i32 %b) {
+entry:
+ %tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32 @f2(i32 %a, i32 %b) {
+entry:
+ %tmp1 = udiv i32 %a, %b ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32 @f3(i32 %a, i32 %b) {
+entry:
+ %tmp1 = srem i32 %a, %b ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32 @f4(i32 %a, i32 %b) {
+entry:
+ %tmp1 = urem i32 %a, %b ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
diff --git a/test/CodeGen/ARM/dyn-stackalloc.ll b/test/CodeGen/ARM/dyn-stackalloc.ll
new file mode 100644
index 0000000..92e2d13
--- /dev/null
+++ b/test/CodeGen/ARM/dyn-stackalloc.ll
@@ -0,0 +1,56 @@
+; RUN: llc < %s -march=arm
+
+ %struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
+ %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
+
+define void @t1(%struct.state* %v) {
+ %tmp6 = load i32* null
+ %tmp8 = alloca float, i32 %tmp6
+ store i32 1, i32* null
+ br i1 false, label %bb123.preheader, label %return
+
+bb123.preheader:
+ br i1 false, label %bb43, label %return
+
+bb43:
+ call fastcc void @f1( float* %tmp8, float* null, i32 0 )
+ %tmp70 = load i32* null
+ %tmp85 = getelementptr float* %tmp8, i32 0
+ call fastcc void @f2( float* null, float* null, float* %tmp85, i32 %tmp70 )
+ ret void
+
+return:
+ ret void
+}
+
+declare fastcc void @f1(float*, float*, i32)
+
+declare fastcc void @f2(float*, float*, float*, i32)
+
+ %struct.comment = type { i8**, i32*, i32, i8* }
+@str215 = external global [2 x i8]
+
+define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) {
+ %tmp1 = call i32 @strlen( i8* %tag )
+ %tmp3 = call i32 @strlen( i8* %contents )
+ %tmp4 = add i32 %tmp1, 2
+ %tmp5 = add i32 %tmp4, %tmp3
+ %tmp6 = alloca i8, i32 %tmp5
+ %tmp9 = call i8* @strcpy( i8* %tmp6, i8* %tag )
+ %tmp6.len = call i32 @strlen( i8* %tmp6 )
+ %tmp6.indexed = getelementptr i8* %tmp6, i32 %tmp6.len
+ call void @llvm.memcpy.i32( i8* %tmp6.indexed, i8* getelementptr ([2 x i8]* @str215, i32 0, i32 0), i32 2, i32 1 )
+ %tmp15 = call i8* @strcat( i8* %tmp6, i8* %contents )
+ call fastcc void @comment_add( %struct.comment* %vc, i8* %tmp6 )
+ ret void
+}
+
+declare i32 @strlen(i8*)
+
+declare i8* @strcat(i8*, i8*)
+
+declare fastcc void @comment_add(%struct.comment*, i8*)
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32)
+
+declare i8* @strcpy(i8*, i8*)
diff --git a/test/CodeGen/ARM/extloadi1.ll b/test/CodeGen/ARM/extloadi1.ll
new file mode 100644
index 0000000..dc45ce7
--- /dev/null
+++ b/test/CodeGen/ARM/extloadi1.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=arm
+@handler_installed.6144.b = external global i1 ; <i1*> [#uses=1]
+
+define void @__mf_sigusr1_respond() {
+entry:
+ %tmp8.b = load i1* @handler_installed.6144.b ; <i1> [#uses=1]
+ br i1 false, label %cond_true7, label %cond_next
+
+cond_next: ; preds = %entry
+ br i1 %tmp8.b, label %bb, label %cond_next3
+
+cond_next3: ; preds = %cond_next
+ ret void
+
+bb: ; preds = %cond_next
+ ret void
+
+cond_true7: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/ARM/fabss.ll b/test/CodeGen/ARM/fabss.ll
new file mode 100644
index 0000000..e5b5791
--- /dev/null
+++ b/test/CodeGen/ARM/fabss.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
+
+define float @test(float %a, float %b) {
+entry:
+ %dum = fadd float %a, %b
+ %0 = tail call float @fabsf(float %dum)
+ %dum1 = fadd float %0, %b
+ ret float %dum1
+}
+
+declare float @fabsf(float)
+
+; VFP2: test:
+; VFP2: vabs.f32 s1, s1
+
+; NFP1: test:
+; NFP1: vabs.f32 d1, d1
+; NFP0: test:
+; NFP0: vabs.f32 s1, s1
+
+; CORTEXA8: test:
+; CORTEXA8: vabs.f32 d1, d1
+; CORTEXA9: test:
+; CORTEXA9: vabs.f32 s1, s1
diff --git a/test/CodeGen/ARM/fadds.ll b/test/CodeGen/ARM/fadds.ll
new file mode 100644
index 0000000..db18a86
--- /dev/null
+++ b/test/CodeGen/ARM/fadds.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
+
+define float @test(float %a, float %b) {
+entry:
+ %0 = fadd float %a, %b
+ ret float %0
+}
+
+; VFP2: test:
+; VFP2: vadd.f32 s0, s1, s0
+
+; NFP1: test:
+; NFP1: vadd.f32 d0, d1, d0
+; NFP0: test:
+; NFP0: vadd.f32 s0, s1, s0
+
+; CORTEXA8: test:
+; CORTEXA8: vadd.f32 d0, d1, d0
+; CORTEXA9: test:
+; CORTEXA9: vadd.f32 s0, s1, s0
diff --git a/test/CodeGen/ARM/fcopysign.ll b/test/CodeGen/ARM/fcopysign.ll
new file mode 100644
index 0000000..a6d7410
--- /dev/null
+++ b/test/CodeGen/ARM/fcopysign.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=arm | grep bic | count 2
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | \
+; RUN: grep vneg | count 2
+
+define float @test1(float %x, double %y) {
+ %tmp = fpext float %x to double
+ %tmp2 = tail call double @copysign( double %tmp, double %y )
+ %tmp3 = fptrunc double %tmp2 to float
+ ret float %tmp3
+}
+
+define double @test2(double %x, float %y) {
+ %tmp = fpext float %y to double
+ %tmp2 = tail call double @copysign( double %x, double %tmp )
+ ret double %tmp2
+}
+
+declare double @copysign(double, double)
diff --git a/test/CodeGen/ARM/fdivs.ll b/test/CodeGen/ARM/fdivs.ll
new file mode 100644
index 0000000..a5c86bf
--- /dev/null
+++ b/test/CodeGen/ARM/fdivs.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
+
+define float @test(float %a, float %b) {
+entry:
+ %0 = fdiv float %a, %b
+ ret float %0
+}
+
+; VFP2: test:
+; VFP2: vdiv.f32 s0, s1, s0
+
+; NFP1: test:
+; NFP1: vdiv.f32 s0, s1, s0
+; NFP0: test:
+; NFP0: vdiv.f32 s0, s1, s0
+
+; CORTEXA8: test:
+; CORTEXA8: vdiv.f32 s0, s1, s0
+; CORTEXA9: test:
+; CORTEXA9: vdiv.f32 s0, s1, s0
diff --git a/test/CodeGen/ARM/fixunsdfdi.ll b/test/CodeGen/ARM/fixunsdfdi.ll
new file mode 100644
index 0000000..6db2385
--- /dev/null
+++ b/test/CodeGen/ARM/fixunsdfdi.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2
+; RUN: llc < %s -march=arm -mattr=vfp2 | not grep vstr.64
+
+define hidden i64 @__fixunsdfdi(double %x) nounwind readnone {
+entry:
+ %x14 = bitcast double %x to i64 ; <i64> [#uses=1]
+ br i1 true, label %bb3, label %bb10
+
+bb3: ; preds = %entry
+ br i1 true, label %bb5, label %bb7
+
+bb5: ; preds = %bb3
+ %u.in.mask = and i64 %x14, -4294967296 ; <i64> [#uses=1]
+ %.ins = or i64 0, %u.in.mask ; <i64> [#uses=1]
+ %0 = bitcast i64 %.ins to double ; <double> [#uses=1]
+ %1 = fsub double %x, %0 ; <double> [#uses=1]
+ %2 = fptosi double %1 to i32 ; <i32> [#uses=1]
+ %3 = add i32 %2, 0 ; <i32> [#uses=1]
+ %4 = zext i32 %3 to i64 ; <i64> [#uses=1]
+ %5 = shl i64 %4, 32 ; <i64> [#uses=1]
+ %6 = or i64 %5, 0 ; <i64> [#uses=1]
+ ret i64 %6
+
+bb7: ; preds = %bb3
+ ret i64 0
+
+bb10: ; preds = %entry
+ ret i64 0
+}
diff --git a/test/CodeGen/ARM/fmacs.ll b/test/CodeGen/ARM/fmacs.ll
new file mode 100644
index 0000000..904a587
--- /dev/null
+++ b/test/CodeGen/ARM/fmacs.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
+
+define float @test(float %acc, float %a, float %b) {
+entry:
+ %0 = fmul float %a, %b
+ %1 = fadd float %acc, %0
+ ret float %1
+}
+
+; VFP2: test:
+; VFP2: vmla.f32 s2, s1, s0
+
+; NFP1: test:
+; NFP1: vmul.f32 d0, d1, d0
+; NFP0: test:
+; NFP0: vmla.f32 s2, s1, s0
+
+; CORTEXA8: test:
+; CORTEXA8: vmul.f32 d0, d1, d0
+; CORTEXA9: test:
+; CORTEXA9: vmla.f32 s2, s1, s0
diff --git a/test/CodeGen/ARM/fmdrr-fmrrd.ll b/test/CodeGen/ARM/fmdrr-fmrrd.ll
new file mode 100644
index 0000000..eb72faf
--- /dev/null
+++ b/test/CodeGen/ARM/fmdrr-fmrrd.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=arm -mattr=vfp2 | not grep fmdrr
+; RUN: llc < %s -march=arm -mattr=vfp2 | not grep fmrrd
+
+; naive codegen for this is:
+; _i:
+; fmdrr d0, r0, r1
+; fmrrd r0, r1, d0
+; bx lr
+
+define i64 @test(double %X) {
+ %Y = bitcast double %X to i64
+ ret i64 %Y
+}
diff --git a/test/CodeGen/ARM/fmscs.ll b/test/CodeGen/ARM/fmscs.ll
new file mode 100644
index 0000000..7b9e029
--- /dev/null
+++ b/test/CodeGen/ARM/fmscs.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
+
+define float @test(float %acc, float %a, float %b) {
+entry:
+ %0 = fmul float %a, %b
+ %1 = fsub float %0, %acc
+ ret float %1
+}
+
+; VFP2: test:
+; VFP2: vnmls.f32 s2, s1, s0
+
+; NFP1: test:
+; NFP1: vnmls.f32 s2, s1, s0
+; NFP0: test:
+; NFP0: vnmls.f32 s2, s1, s0
+
+; CORTEXA8: test:
+; CORTEXA8: vnmls.f32 s2, s1, s0
+; CORTEXA9: test:
+; CORTEXA9: vnmls.f32 s2, s1, s0
diff --git a/test/CodeGen/ARM/fmuls.ll b/test/CodeGen/ARM/fmuls.ll
new file mode 100644
index 0000000..d3c9c82
--- /dev/null
+++ b/test/CodeGen/ARM/fmuls.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
+
+define float @test(float %a, float %b) {
+entry:
+ %0 = fmul float %a, %b
+ ret float %0
+}
+
+; VFP2: test:
+; VFP2: vmul.f32 s0, s1, s0
+
+; NFP1: test:
+; NFP1: vmul.f32 d0, d1, d0
+; NFP0: test:
+; NFP0: vmul.f32 s0, s1, s0
+
+; CORTEXA8: test:
+; CORTEXA8: vmul.f32 d0, d1, d0
+; CORTEXA9: test:
+; CORTEXA9: vmul.f32 s0, s1, s0
diff --git a/test/CodeGen/ARM/fnegs.ll b/test/CodeGen/ARM/fnegs.ll
new file mode 100644
index 0000000..d6c22f1
--- /dev/null
+++ b/test/CodeGen/ARM/fnegs.ll
@@ -0,0 +1,54 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
+
+define float @test1(float* %a) {
+entry:
+ %0 = load float* %a, align 4 ; <float> [#uses=2]
+ %1 = fsub float -0.000000e+00, %0 ; <float> [#uses=2]
+ %2 = fpext float %1 to double ; <double> [#uses=1]
+ %3 = fcmp olt double %2, 1.234000e+00 ; <i1> [#uses=1]
+ %retval = select i1 %3, float %1, float %0 ; <float> [#uses=1]
+ ret float %retval
+}
+; VFP2: test1:
+; VFP2: vneg.f32 s1, s0
+
+; NFP1: test1:
+; NFP1: vneg.f32 d1, d0
+
+; NFP0: test1:
+; NFP0: vneg.f32 s1, s0
+
+; CORTEXA8: test1:
+; CORTEXA8: vneg.f32 d1, d0
+
+; CORTEXA9: test1:
+; CORTEXA9: vneg.f32 s1, s0
+
+define float @test2(float* %a) {
+entry:
+ %0 = load float* %a, align 4 ; <float> [#uses=2]
+ %1 = fmul float -1.000000e+00, %0 ; <float> [#uses=2]
+ %2 = fpext float %1 to double ; <double> [#uses=1]
+ %3 = fcmp olt double %2, 1.234000e+00 ; <i1> [#uses=1]
+ %retval = select i1 %3, float %1, float %0 ; <float> [#uses=1]
+ ret float %retval
+}
+; VFP2: test2:
+; VFP2: vneg.f32 s1, s0
+
+; NFP1: test2:
+; NFP1: vneg.f32 d1, d0
+
+; NFP0: test2:
+; NFP0: vneg.f32 s1, s0
+
+; CORTEXA8: test2:
+; CORTEXA8: vneg.f32 d1, d0
+
+; CORTEXA9: test2:
+; CORTEXA9: vneg.f32 s1, s0
+
diff --git a/test/CodeGen/ARM/fnmacs.ll b/test/CodeGen/ARM/fnmacs.ll
new file mode 100644
index 0000000..724947e
--- /dev/null
+++ b/test/CodeGen/ARM/fnmacs.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NEON
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NEONFP
+
+define float @test(float %acc, float %a, float %b) {
+entry:
+; VFP2: vmls.f32
+; NEON: vmls.f32
+
+; NEONFP-NOT: vmls
+; NEONFP-NOT: vmov.f32
+; NEONFP: vmul.f32
+; NEONFP: vsub.f32
+; NEONFP: vmov
+
+ %0 = fmul float %a, %b
+ %1 = fsub float %acc, %0
+ ret float %1
+}
+
diff --git a/test/CodeGen/ARM/fnmscs.ll b/test/CodeGen/ARM/fnmscs.ll
new file mode 100644
index 0000000..ad21882
--- /dev/null
+++ b/test/CodeGen/ARM/fnmscs.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s
+
+define float @test1(float %acc, float %a, float %b) nounwind {
+; CHECK: vnmla.f32 s2, s1, s0
+entry:
+ %0 = fmul float %a, %b
+ %1 = fsub float -0.0, %0
+ %2 = fsub float %1, %acc
+ ret float %2
+}
+
+define float @test2(float %acc, float %a, float %b) nounwind {
+; CHECK: vnmla.f32 s2, s1, s0
+entry:
+ %0 = fmul float %a, %b
+ %1 = fmul float -1.0, %0
+ %2 = fsub float %1, %acc
+ ret float %2
+}
+
diff --git a/test/CodeGen/ARM/fnmul.ll b/test/CodeGen/ARM/fnmul.ll
new file mode 100644
index 0000000..6d7bc05
--- /dev/null
+++ b/test/CodeGen/ARM/fnmul.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | grep vnmul.f64
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -enable-sign-dependent-rounding-fp-math | grep vmul.f64
+
+
+define double @t1(double %a, double %b) {
+entry:
+ %tmp2 = fsub double -0.000000e+00, %a ; <double> [#uses=1]
+ %tmp4 = fmul double %tmp2, %b ; <double> [#uses=1]
+ ret double %tmp4
+}
+
diff --git a/test/CodeGen/ARM/fnmuls.ll b/test/CodeGen/ARM/fnmuls.ll
new file mode 100644
index 0000000..efd87d2
--- /dev/null
+++ b/test/CodeGen/ARM/fnmuls.ll
@@ -0,0 +1,23 @@
+; XFAIL: *
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s
+
+define float @test1(float %a, float %b) nounwind {
+; CHECK: fnmscs s2, s1, s0
+entry:
+ %0 = fmul float %a, %b
+ %1 = fsub float -0.0, %0
+ ret float %1
+}
+
+define float @test2(float %a, float %b) nounwind {
+; CHECK: fnmscs s2, s1, s0
+entry:
+ %0 = fmul float %a, %b
+ %1 = fmul float -1.0, %0
+ ret float %1
+}
+
diff --git a/test/CodeGen/ARM/formal.ll b/test/CodeGen/ARM/formal.ll
new file mode 100644
index 0000000..4ac10ba
--- /dev/null
+++ b/test/CodeGen/ARM/formal.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2
+
+declare void @bar(i64 %x, i64 %y)
+
+define void @foo() {
+ call void @bar(i64 2, i64 3)
+ ret void
+}
diff --git a/test/CodeGen/ARM/fp.ll b/test/CodeGen/ARM/fp.ll
new file mode 100644
index 0000000..8fbd45b
--- /dev/null
+++ b/test/CodeGen/ARM/fp.ll
@@ -0,0 +1,78 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
+
+define float @f(i32 %a) {
+;CHECK: f:
+;CHECK: vmov
+;CHECK-NEXT: vcvt.f32.s32
+;CHECK-NEXT: vmov
+entry:
+ %tmp = sitofp i32 %a to float ; <float> [#uses=1]
+ ret float %tmp
+}
+
+define double @g(i32 %a) {
+;CHECK: g:
+;CHECK: vmov
+;CHECK-NEXT: vcvt.f64.s32
+;CHECK-NEXT: vmov
+entry:
+ %tmp = sitofp i32 %a to double ; <double> [#uses=1]
+ ret double %tmp
+}
+
+define double @uint_to_double(i32 %a) {
+;CHECK: uint_to_double:
+;CHECK: vmov
+;CHECK-NEXT: vcvt.f64.u32
+;CHECK-NEXT: vmov
+entry:
+ %tmp = uitofp i32 %a to double ; <double> [#uses=1]
+ ret double %tmp
+}
+
+define float @uint_to_float(i32 %a) {
+;CHECK: uint_to_float:
+;CHECK: vmov
+;CHECK-NEXT: vcvt.f32.u32
+;CHECK-NEXT: vmov
+entry:
+ %tmp = uitofp i32 %a to float ; <float> [#uses=1]
+ ret float %tmp
+}
+
+define double @h(double* %v) {
+;CHECK: h:
+;CHECK: vldr.64
+;CHECK-NEXT: vmov
+entry:
+ %tmp = load double* %v ; <double> [#uses=1]
+ ret double %tmp
+}
+
+define float @h2() {
+;CHECK: h2:
+;CHECK: 1065353216
+entry:
+ ret float 1.000000e+00
+}
+
+define double @f2(double %a) {
+;CHECK: f2:
+;CHECK-NOT: vmov
+ ret double %a
+}
+
+define void @f3() {
+;CHECK: f3:
+;CHECK-NOT: vmov
+;CHECK: f4
+entry:
+ %tmp = call double @f5( ) ; <double> [#uses=1]
+ call void @f4( double %tmp )
+ ret void
+}
+
+declare void @f4(double)
+
+declare double @f5()
+
diff --git a/test/CodeGen/ARM/fp_convert.ll b/test/CodeGen/ARM/fp_convert.ll
new file mode 100644
index 0000000..2adac78
--- /dev/null
+++ b/test/CodeGen/ARM/fp_convert.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NEON
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2
+
+define i32 @test1(float %a, float %b) {
+; VFP2: test1:
+; VFP2: vcvt.s32.f32 s0, s0
+; NEON: test1:
+; NEON: vcvt.s32.f32 d0, d0
+entry:
+ %0 = fadd float %a, %b
+ %1 = fptosi float %0 to i32
+ ret i32 %1
+}
+
+define i32 @test2(float %a, float %b) {
+; VFP2: test2:
+; VFP2: vcvt.u32.f32 s0, s0
+; NEON: test2:
+; NEON: vcvt.u32.f32 d0, d0
+entry:
+ %0 = fadd float %a, %b
+ %1 = fptoui float %0 to i32
+ ret i32 %1
+}
+
+define float @test3(i32 %a, i32 %b) {
+; VFP2: test3:
+; VFP2: vcvt.f32.u32 s0, s0
+; NEON: test3:
+; NEON: vcvt.f32.u32 d0, d0
+entry:
+ %0 = add i32 %a, %b
+ %1 = uitofp i32 %0 to float
+ ret float %1
+}
+
+define float @test4(i32 %a, i32 %b) {
+; VFP2: test4:
+; VFP2: vcvt.f32.s32 s0, s0
+; NEON: test4:
+; NEON: vcvt.f32.s32 d0, d0
+entry:
+ %0 = add i32 %a, %b
+ %1 = sitofp i32 %0 to float
+ ret float %1
+}
diff --git a/test/CodeGen/ARM/fparith.ll b/test/CodeGen/ARM/fparith.ll
new file mode 100644
index 0000000..ce6d6b2
--- /dev/null
+++ b/test/CodeGen/ARM/fparith.ll
@@ -0,0 +1,101 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
+
+define float @f1(float %a, float %b) {
+;CHECK: f1:
+;CHECK: vadd.f32
+entry:
+ %tmp = fadd float %a, %b ; <float> [#uses=1]
+ ret float %tmp
+}
+
+define double @f2(double %a, double %b) {
+;CHECK: f2:
+;CHECK: vadd.f64
+entry:
+ %tmp = fadd double %a, %b ; <double> [#uses=1]
+ ret double %tmp
+}
+
+define float @f3(float %a, float %b) {
+;CHECK: f3:
+;CHECK: vmul.f32
+entry:
+ %tmp = fmul float %a, %b ; <float> [#uses=1]
+ ret float %tmp
+}
+
+define double @f4(double %a, double %b) {
+;CHECK: f4:
+;CHECK: vmul.f64
+entry:
+ %tmp = fmul double %a, %b ; <double> [#uses=1]
+ ret double %tmp
+}
+
+define float @f5(float %a, float %b) {
+;CHECK: f5:
+;CHECK: vsub.f32
+entry:
+ %tmp = fsub float %a, %b ; <float> [#uses=1]
+ ret float %tmp
+}
+
+define double @f6(double %a, double %b) {
+;CHECK: f6:
+;CHECK: vsub.f64
+entry:
+ %tmp = fsub double %a, %b ; <double> [#uses=1]
+ ret double %tmp
+}
+
+define float @f7(float %a) {
+;CHECK: f7:
+;CHECK: eor
+entry:
+ %tmp1 = fsub float -0.000000e+00, %a ; <float> [#uses=1]
+ ret float %tmp1
+}
+
+define double @f8(double %a) {
+;CHECK: f8:
+;CHECK: vneg.f64
+entry:
+ %tmp1 = fsub double -0.000000e+00, %a ; <double> [#uses=1]
+ ret double %tmp1
+}
+
+define float @f9(float %a, float %b) {
+;CHECK: f9:
+;CHECK: vdiv.f32
+entry:
+ %tmp1 = fdiv float %a, %b ; <float> [#uses=1]
+ ret float %tmp1
+}
+
+define double @f10(double %a, double %b) {
+;CHECK: f10:
+;CHECK: vdiv.f64
+entry:
+ %tmp1 = fdiv double %a, %b ; <double> [#uses=1]
+ ret double %tmp1
+}
+
+define float @f11(float %a) {
+;CHECK: f11:
+;CHECK: bic
+entry:
+ %tmp1 = call float @fabsf( float %a ) ; <float> [#uses=1]
+ ret float %tmp1
+}
+
+declare float @fabsf(float)
+
+define double @f12(double %a) {
+;CHECK: f12:
+;CHECK: vabs.f64
+entry:
+ %tmp1 = call double @fabs( double %a ) ; <double> [#uses=1]
+ ret double %tmp1
+}
+
+declare double @fabs(double)
diff --git a/test/CodeGen/ARM/fpcmp.ll b/test/CodeGen/ARM/fpcmp.ll
new file mode 100644
index 0000000..260ec49
--- /dev/null
+++ b/test/CodeGen/ARM/fpcmp.ll
@@ -0,0 +1,71 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
+
+define i32 @f1(float %a) {
+;CHECK: f1:
+;CHECK: vcmpe.f32
+;CHECK: movmi
+entry:
+ %tmp = fcmp olt float %a, 1.000000e+00 ; <i1> [#uses=1]
+ %tmp1 = zext i1 %tmp to i32 ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32 @f2(float %a) {
+;CHECK: f2:
+;CHECK: vcmpe.f32
+;CHECK: moveq
+entry:
+ %tmp = fcmp oeq float %a, 1.000000e+00 ; <i1> [#uses=1]
+ %tmp2 = zext i1 %tmp to i32 ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
+
+define i32 @f3(float %a) {
+;CHECK: f3:
+;CHECK: vcmpe.f32
+;CHECK: movgt
+entry:
+ %tmp = fcmp ogt float %a, 1.000000e+00 ; <i1> [#uses=1]
+ %tmp3 = zext i1 %tmp to i32 ; <i32> [#uses=1]
+ ret i32 %tmp3
+}
+
+define i32 @f4(float %a) {
+;CHECK: f4:
+;CHECK: vcmpe.f32
+;CHECK: movge
+entry:
+ %tmp = fcmp oge float %a, 1.000000e+00 ; <i1> [#uses=1]
+ %tmp4 = zext i1 %tmp to i32 ; <i32> [#uses=1]
+ ret i32 %tmp4
+}
+
+define i32 @f5(float %a) {
+;CHECK: f5:
+;CHECK: vcmpe.f32
+;CHECK: movls
+entry:
+ %tmp = fcmp ole float %a, 1.000000e+00 ; <i1> [#uses=1]
+ %tmp5 = zext i1 %tmp to i32 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
+define i32 @f6(float %a) {
+;CHECK: f6:
+;CHECK: vcmpe.f32
+;CHECK: movne
+entry:
+ %tmp = fcmp une float %a, 1.000000e+00 ; <i1> [#uses=1]
+ %tmp6 = zext i1 %tmp to i32 ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+define i32 @g1(double %a) {
+;CHECK: g1:
+;CHECK: vcmpe.f64
+;CHECK: movmi
+entry:
+ %tmp = fcmp olt double %a, 1.000000e+00 ; <i1> [#uses=1]
+ %tmp7 = zext i1 %tmp to i32 ; <i32> [#uses=1]
+ ret i32 %tmp7
+}
diff --git a/test/CodeGen/ARM/fpcmp_ueq.ll b/test/CodeGen/ARM/fpcmp_ueq.ll
new file mode 100644
index 0000000..67f70e9e
--- /dev/null
+++ b/test/CodeGen/ARM/fpcmp_ueq.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=arm | grep moveq
+; RUN: llc < %s -march=arm -mattr=+vfp2 | grep movvs
+
+define i32 @f7(float %a, float %b) {
+entry:
+ %tmp = fcmp ueq float %a,%b
+ %retval = select i1 %tmp, i32 666, i32 42
+ ret i32 %retval
+}
+
diff --git a/test/CodeGen/ARM/fpconsts.ll b/test/CodeGen/ARM/fpconsts.ll
new file mode 100644
index 0000000..710994d
--- /dev/null
+++ b/test/CodeGen/ARM/fpconsts.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=arm -mattr=+vfp3 | FileCheck %s
+
+define arm_apcscc float @t1(float %x) nounwind readnone optsize {
+entry:
+; CHECK: t1:
+; CHECK: vmov.f32 s1, #4.000000e+00
+ %0 = fadd float %x, 4.000000e+00
+ ret float %0
+}
+
+define arm_apcscc double @t2(double %x) nounwind readnone optsize {
+entry:
+; CHECK: t2:
+; CHECK: vmov.f64 d1, #3.000000e+00
+ %0 = fadd double %x, 3.000000e+00
+ ret double %0
+}
+
+define arm_apcscc double @t3(double %x) nounwind readnone optsize {
+entry:
+; CHECK: t3:
+; CHECK: vmov.f64 d1, #-1.300000e+01
+ %0 = fmul double %x, -1.300000e+01
+ ret double %0
+}
+
+define arm_apcscc float @t4(float %x) nounwind readnone optsize {
+entry:
+; CHECK: t4:
+; CHECK: vmov.f32 s1, #-2.400000e+01
+ %0 = fmul float %x, -2.400000e+01
+ ret float %0
+}
diff --git a/test/CodeGen/ARM/fpconv.ll b/test/CodeGen/ARM/fpconv.ll
new file mode 100644
index 0000000..bf197a4
--- /dev/null
+++ b/test/CodeGen/ARM/fpconv.ll
@@ -0,0 +1,102 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s --check-prefix=CHECK-VFP
+; RUN: llc < %s -march=arm | FileCheck %s
+
+define float @f1(double %x) {
+;CHECK-VFP: f1:
+;CHECK-VFP: vcvt.f32.f64
+;CHECK: f1:
+;CHECK: truncdfsf2
+entry:
+ %tmp1 = fptrunc double %x to float ; <float> [#uses=1]
+ ret float %tmp1
+}
+
+define double @f2(float %x) {
+;CHECK-VFP: f2:
+;CHECK-VFP: vcvt.f64.f32
+;CHECK: f2:
+;CHECK: extendsfdf2
+entry:
+ %tmp1 = fpext float %x to double ; <double> [#uses=1]
+ ret double %tmp1
+}
+
+define i32 @f3(float %x) {
+;CHECK-VFP: f3:
+;CHECK-VFP: vcvt.s32.f32
+;CHECK: f3:
+;CHECK: fixsfsi
+entry:
+ %tmp = fptosi float %x to i32 ; <i32> [#uses=1]
+ ret i32 %tmp
+}
+
+define i32 @f4(float %x) {
+;CHECK-VFP: f4:
+;CHECK-VFP: vcvt.u32.f32
+;CHECK: f4:
+;CHECK: fixunssfsi
+entry:
+ %tmp = fptoui float %x to i32 ; <i32> [#uses=1]
+ ret i32 %tmp
+}
+
+define i32 @f5(double %x) {
+;CHECK-VFP: f5:
+;CHECK-VFP: vcvt.s32.f64
+;CHECK: f5:
+;CHECK: fixdfsi
+entry:
+ %tmp = fptosi double %x to i32 ; <i32> [#uses=1]
+ ret i32 %tmp
+}
+
+define i32 @f6(double %x) {
+;CHECK-VFP: f6:
+;CHECK-VFP: vcvt.u32.f64
+;CHECK: f6:
+;CHECK: fixunsdfsi
+entry:
+ %tmp = fptoui double %x to i32 ; <i32> [#uses=1]
+ ret i32 %tmp
+}
+
+define float @f7(i32 %a) {
+;CHECK-VFP: f7:
+;CHECK-VFP: vcvt.f32.s32
+;CHECK: f7:
+;CHECK: floatsisf
+entry:
+ %tmp = sitofp i32 %a to float ; <float> [#uses=1]
+ ret float %tmp
+}
+
+define double @f8(i32 %a) {
+;CHECK-VFP: f8:
+;CHECK-VFP: vcvt.f64.s32
+;CHECK: f8:
+;CHECK: floatsidf
+entry:
+ %tmp = sitofp i32 %a to double ; <double> [#uses=1]
+ ret double %tmp
+}
+
+define float @f9(i32 %a) {
+;CHECK-VFP: f9:
+;CHECK-VFP: vcvt.f32.u32
+;CHECK: f9:
+;CHECK: floatunsisf
+entry:
+ %tmp = uitofp i32 %a to float ; <float> [#uses=1]
+ ret float %tmp
+}
+
+define double @f10(i32 %a) {
+;CHECK-VFP: f10:
+;CHECK-VFP: vcvt.f64.u32
+;CHECK: f10:
+;CHECK: floatunsidf
+entry:
+ %tmp = uitofp i32 %a to double ; <double> [#uses=1]
+ ret double %tmp
+}
diff --git a/test/CodeGen/ARM/fpmem.ll b/test/CodeGen/ARM/fpmem.ll
new file mode 100644
index 0000000..c3cff18
--- /dev/null
+++ b/test/CodeGen/ARM/fpmem.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
+
+define float @f1(float %a) {
+; CHECK: f1:
+; CHECK: mov r0, #0
+ ret float 0.000000e+00
+}
+
+define float @f2(float* %v, float %u) {
+; CHECK: f2:
+; CHECK: vldr.32{{.*}}[
+ %tmp = load float* %v ; <float> [#uses=1]
+ %tmp1 = fadd float %tmp, %u ; <float> [#uses=1]
+ ret float %tmp1
+}
+
+define void @f3(float %a, float %b, float* %v) {
+; CHECK: f3:
+; CHECK: vstr.32{{.*}}[
+ %tmp = fadd float %a, %b ; <float> [#uses=1]
+ store float %tmp, float* %v
+ ret void
+}
diff --git a/test/CodeGen/ARM/fpow.ll b/test/CodeGen/ARM/fpow.ll
new file mode 100644
index 0000000..6d48792
--- /dev/null
+++ b/test/CodeGen/ARM/fpow.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=arm
+
+define double @t(double %x, double %y) nounwind optsize {
+entry:
+ %0 = tail call double @llvm.pow.f64( double %x, double %y ) ; <double> [#uses=1]
+ ret double %0
+}
+
+declare double @llvm.pow.f64(double, double) nounwind readonly
diff --git a/test/CodeGen/ARM/fpowi.ll b/test/CodeGen/ARM/fpowi.ll
new file mode 100644
index 0000000..7f9d62a
--- /dev/null
+++ b/test/CodeGen/ARM/fpowi.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep powidf2
+; PR1287
+
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "arm-linux-gnueabi"
+
+define double @_ZSt3powdi(double %__x, i32 %__i) {
+entry:
+ %tmp3 = call double @llvm.powi.f64( double %__x, i32 %__i )
+ ret double %tmp3
+}
+
+declare double @llvm.powi.f64(double, i32)
+
diff --git a/test/CodeGen/ARM/fptoint.ll b/test/CodeGen/ARM/fptoint.ll
new file mode 100644
index 0000000..299cb8f81
--- /dev/null
+++ b/test/CodeGen/ARM/fptoint.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | FileCheck %s
+
+@i = weak global i32 0 ; <i32*> [#uses=2]
+@u = weak global i32 0 ; <i32*> [#uses=2]
+
+define i32 @foo1(float *%x) {
+ %tmp1 = load float* %x
+ %tmp2 = bitcast float %tmp1 to i32
+ ret i32 %tmp2
+}
+
+define i64 @foo2(double *%x) {
+ %tmp1 = load double* %x
+ %tmp2 = bitcast double %tmp1 to i64
+ ret i64 %tmp2
+}
+
+define void @foo5(float %x) {
+ %tmp1 = fptosi float %x to i32
+ store i32 %tmp1, i32* @i
+ ret void
+}
+
+define void @foo6(float %x) {
+ %tmp1 = fptoui float %x to i32
+ store i32 %tmp1, i32* @u
+ ret void
+}
+
+define void @foo7(double %x) {
+ %tmp1 = fptosi double %x to i32
+ store i32 %tmp1, i32* @i
+ ret void
+}
+
+define void @foo8(double %x) {
+ %tmp1 = fptoui double %x to i32
+ store i32 %tmp1, i32* @u
+ ret void
+}
+
+define void @foo9(double %x) {
+ %tmp = fptoui double %x to i16
+ store i16 %tmp, i16* null
+ ret void
+}
+; CHECK: foo9:
+; CHECK: vmov r0, s0
+
diff --git a/test/CodeGen/ARM/fsubs.ll b/test/CodeGen/ARM/fsubs.ll
new file mode 100644
index 0000000..ae98be3
--- /dev/null
+++ b/test/CodeGen/ARM/fsubs.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
+
+define float @test(float %a, float %b) {
+entry:
+ %0 = fsub float %a, %b
+ ret float %0
+}
+
+; VFP2: vsub.f32 s0, s1, s0
+; NFP1: vsub.f32 d0, d1, d0
+; NFP0: vsub.f32 s0, s1, s0
diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll
new file mode 100644
index 0000000..886c0d5
--- /dev/null
+++ b/test/CodeGen/ARM/globals.ll
@@ -0,0 +1,75 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic
+; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC
+; RUN: llc < %s -mtriple=arm-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC
+
+@G = external global i32
+
+define i32 @test1() {
+ %tmp = load i32* @G
+ ret i32 %tmp
+}
+
+; DarwinStatic: _test1:
+; DarwinStatic: ldr r0, LCPI1_0
+; DarwinStatic: ldr r0, [r0]
+; DarwinStatic: bx lr
+
+; DarwinStatic: .align 2
+; DarwinStatic: LCPI1_0:
+; DarwinStatic: .long {{_G$}}
+
+
+; DarwinDynamic: _test1:
+; DarwinDynamic: ldr r0, LCPI1_0
+; DarwinDynamic: ldr r0, [r0]
+; DarwinDynamic: ldr r0, [r0]
+; DarwinDynamic: bx lr
+
+; DarwinDynamic: .align 2
+; DarwinDynamic: LCPI1_0:
+; DarwinDynamic: .long L_G$non_lazy_ptr
+
+; DarwinDynamic: .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers
+; DarwinDynamic: .align 2
+; DarwinDynamic: L_G$non_lazy_ptr:
+; DarwinDynamic: .indirect_symbol _G
+; DarwinDynamic: .long 0
+
+
+
+; DarwinPIC: _test1:
+; DarwinPIC: ldr r0, LCPI1_0
+; DarwinPIC: LPC1_0:
+; DarwinPIC: ldr r0, [pc, +r0]
+; DarwinPIC: ldr r0, [r0]
+; DarwinPIC: bx lr
+
+; DarwinPIC: .align 2
+; DarwinPIC: LCPI1_0:
+; DarwinPIC: .long L_G$non_lazy_ptr-(LPC1_0+8)
+
+; DarwinPIC: .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers
+; DarwinPIC: .align 2
+; DarwinPIC: L_G$non_lazy_ptr:
+; DarwinPIC: .indirect_symbol _G
+; DarwinPIC: .long 0
+
+
+
+; LinuxPIC: test1:
+; LinuxPIC: ldr r0, .LCPI1_0
+; LinuxPIC: ldr r1, .LCPI1_1
+
+; LinuxPIC: .LPC1_0:
+; LinuxPIC: add r0, pc, r0
+; LinuxPIC: ldr r0, [r1, +r0]
+; LinuxPIC: ldr r0, [r0]
+; LinuxPIC: bx lr
+
+; LinuxPIC: .align 2
+; LinuxPIC: .LCPI1_0:
+; LinuxPIC: .long _GLOBAL_OFFSET_TABLE_-(.LPC1_0+8)
+; LinuxPIC: .align 2
+; LinuxPIC: .LCPI1_1:
+; LinuxPIC: .long G(GOT)
diff --git a/test/CodeGen/ARM/hardfloat_neon.ll b/test/CodeGen/ARM/hardfloat_neon.ll
new file mode 100644
index 0000000..4abf04b
--- /dev/null
+++ b/test/CodeGen/ARM/hardfloat_neon.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=arm-linux-gnueabi -mattr=+neon -float-abi=hard
+
+define <16 x i8> @vmulQi8_reg(<16 x i8> %A, <16 x i8> %B) nounwind {
+ %tmp1 = mul <16 x i8> %A, %B
+ ret <16 x i8> %tmp1
+}
+
+define <16 x i8> @f(<16 x i8> %a, <16 x i8> %b) {
+ %tmp = call <16 x i8> @g(<16 x i8> %b)
+ ret <16 x i8> %tmp
+}
+
+declare <16 x i8> @g(<16 x i8>)
diff --git a/test/CodeGen/ARM/hello.ll b/test/CodeGen/ARM/hello.ll
new file mode 100644
index 0000000..ccdc7bf
--- /dev/null
+++ b/test/CodeGen/ARM/hello.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | count 1
+; RUN: llc < %s -mtriple=arm-linux-gnu --disable-fp-elim | \
+; RUN: grep mov | count 3
+; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 2
+
+@str = internal constant [12 x i8] c"Hello World\00"
+
+define i32 @main() {
+ %tmp = call i32 @puts( i8* getelementptr ([12 x i8]* @str, i32 0, i64 0) ) ; <i32> [#uses=0]
+ ret i32 0
+}
+
+declare i32 @puts(i8*)
diff --git a/test/CodeGen/ARM/hidden-vis-2.ll b/test/CodeGen/ARM/hidden-vis-2.ll
new file mode 100644
index 0000000..90f5308
--- /dev/null
+++ b/test/CodeGen/ARM/hidden-vis-2.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
+
+@x = weak hidden global i32 0 ; <i32*> [#uses=1]
+
+define i32 @t() nounwind readonly {
+entry:
+; CHECK: t:
+; CHECK: ldr
+; CHECK-NEXT: ldr
+ %0 = load i32* @x, align 4 ; <i32> [#uses=1]
+ ret i32 %0
+}
diff --git a/test/CodeGen/ARM/hidden-vis-3.ll b/test/CodeGen/ARM/hidden-vis-3.ll
new file mode 100644
index 0000000..3bd710a
--- /dev/null
+++ b/test/CodeGen/ARM/hidden-vis-3.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin9 | FileCheck %s
+
+@x = external hidden global i32 ; <i32*> [#uses=1]
+@y = extern_weak hidden global i32 ; <i32*> [#uses=1]
+
+define i32 @t() nounwind readonly {
+entry:
+; CHECK: LCPI1_0:
+; CHECK-NEXT: .long _x
+; CHECK: LCPI1_1:
+; CHECK-NEXT: .long _y
+
+ %0 = load i32* @x, align 4 ; <i32> [#uses=1]
+ %1 = load i32* @y, align 4 ; <i32> [#uses=1]
+ %2 = add i32 %1, %0 ; <i32> [#uses=1]
+ ret i32 %2
+}
diff --git a/test/CodeGen/ARM/hidden-vis.ll b/test/CodeGen/ARM/hidden-vis.ll
new file mode 100644
index 0000000..3544ae8
--- /dev/null
+++ b/test/CodeGen/ARM/hidden-vis.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -mtriple=arm-linux | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
+
+@a = hidden global i32 0
+@b = external global i32
+
+define weak hidden void @t1() nounwind {
+; LINUX: .hidden t1
+; LINUX: t1:
+
+; DARWIN: .private_extern _t1
+; DARWIN: t1:
+ ret void
+}
+
+define weak void @t2() nounwind {
+; LINUX: t2:
+; LINUX: .hidden a
+
+; DARWIN: t2:
+; DARWIN: .private_extern _a
+ ret void
+}
diff --git a/test/CodeGen/ARM/iabs.ll b/test/CodeGen/ARM/iabs.ll
new file mode 100644
index 0000000..63808b2
--- /dev/null
+++ b/test/CodeGen/ARM/iabs.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+
+;; Integer absolute value, should produce something as good as: ARM:
+;; add r3, r0, r0, asr #31
+;; eor r0, r3, r0, asr #31
+;; bx lr
+
+define i32 @test(i32 %a) {
+ %tmp1neg = sub i32 0, %a
+ %b = icmp sgt i32 %a, -1
+ %abs = select i1 %b, i32 %a, i32 %tmp1neg
+ ret i32 %abs
+; CHECK: add r1, r0, r0, asr #31
+; CHECK: eor r0, r1, r0, asr #31
+; CHECK: bx lr
+}
diff --git a/test/CodeGen/ARM/ifcvt1.ll b/test/CodeGen/ARM/ifcvt1.ll
new file mode 100644
index 0000000..e6aa044
--- /dev/null
+++ b/test/CodeGen/ARM/ifcvt1.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm | grep bx | count 1
+
+define i32 @t1(i32 %a, i32 %b) {
+ %tmp2 = icmp eq i32 %a, 0
+ br i1 %tmp2, label %cond_false, label %cond_true
+
+cond_true:
+ %tmp5 = add i32 %b, 1
+ ret i32 %tmp5
+
+cond_false:
+ %tmp7 = add i32 %b, -1
+ ret i32 %tmp7
+}
diff --git a/test/CodeGen/ARM/ifcvt2.ll b/test/CodeGen/ARM/ifcvt2.ll
new file mode 100644
index 0000000..ce57d73
--- /dev/null
+++ b/test/CodeGen/ARM/ifcvt2.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm | grep bxlt | count 1
+; RUN: llc < %s -march=arm | grep bxgt | count 1
+; RUN: llc < %s -march=arm | grep bxge | count 1
+
+define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
+ %tmp2 = icmp sgt i32 %c, 10
+ %tmp5 = icmp slt i32 %d, 4
+ %tmp8 = or i1 %tmp5, %tmp2
+ %tmp13 = add i32 %b, %a
+ br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock
+
+cond_true:
+ %tmp15 = add i32 %tmp13, %c
+ %tmp1821 = sub i32 %tmp15, %d
+ ret i32 %tmp1821
+
+UnifiedReturnBlock:
+ ret i32 %tmp13
+}
+
+define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) {
+ %tmp2 = icmp sgt i32 %c, 10
+ %tmp5 = icmp slt i32 %d, 4
+ %tmp8 = and i1 %tmp5, %tmp2
+ %tmp13 = add i32 %b, %a
+ br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock
+
+cond_true:
+ %tmp15 = add i32 %tmp13, %c
+ %tmp1821 = sub i32 %tmp15, %d
+ ret i32 %tmp1821
+
+UnifiedReturnBlock:
+ ret i32 %tmp13
+}
diff --git a/test/CodeGen/ARM/ifcvt3.ll b/test/CodeGen/ARM/ifcvt3.ll
new file mode 100644
index 0000000..f7ebac6
--- /dev/null
+++ b/test/CodeGen/ARM/ifcvt3.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm | grep cmpne | count 1
+; RUN: llc < %s -march=arm | grep bx | count 2
+
+define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
+ switch i32 %c, label %cond_next [
+ i32 1, label %cond_true
+ i32 7, label %cond_true
+ ]
+
+cond_true:
+ %tmp12 = add i32 %a, 1
+ %tmp1518 = add i32 %tmp12, %b
+ ret i32 %tmp1518
+
+cond_next:
+ %tmp15 = add i32 %b, %a
+ ret i32 %tmp15
+}
diff --git a/test/CodeGen/ARM/ifcvt4.ll b/test/CodeGen/ARM/ifcvt4.ll
new file mode 100644
index 0000000..f28c61b
--- /dev/null
+++ b/test/CodeGen/ARM/ifcvt4.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm | grep subgt | count 1
+; RUN: llc < %s -march=arm | grep suble | count 1
+; FIXME: Check for # of unconditional branch after adding branch folding post ifcvt.
+
+define i32 @t(i32 %a, i32 %b) {
+entry:
+ %tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1]
+ br i1 %tmp1434, label %bb17, label %bb.outer
+
+bb.outer: ; preds = %cond_false, %entry
+ %b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ] ; <i32> [#uses=5]
+ %a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1]
+ br label %bb
+
+bb: ; preds = %cond_true, %bb.outer
+ %indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ] ; <i32> [#uses=2]
+ %tmp. = sub i32 0, %b_addr.021.0.ph ; <i32> [#uses=1]
+ %tmp.40 = mul i32 %indvar, %tmp. ; <i32> [#uses=1]
+ %a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph ; <i32> [#uses=6]
+ %tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph ; <i1> [#uses=1]
+ br i1 %tmp3, label %cond_true, label %cond_false
+
+cond_true: ; preds = %bb
+ %tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph ; <i32> [#uses=2]
+ %tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph ; <i1> [#uses=1]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br i1 %tmp1437, label %bb17, label %bb
+
+cond_false: ; preds = %bb
+ %tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0 ; <i32> [#uses=2]
+ %tmp14 = icmp eq i32 %a_addr.026.0, %tmp10 ; <i1> [#uses=1]
+ br i1 %tmp14, label %bb17, label %bb.outer
+
+bb17: ; preds = %cond_false, %cond_true, %entry
+ %a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1]
+ ret i32 %a_addr.026.1
+}
diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll
new file mode 100644
index 0000000..623f2cb
--- /dev/null
+++ b/test/CodeGen/ARM/ifcvt5.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
+
+@x = external global i32* ; <i32**> [#uses=1]
+
+define void @foo(i32 %a) {
+entry:
+ %tmp = load i32** @x ; <i32*> [#uses=1]
+ store i32 %a, i32* %tmp
+ ret void
+}
+
+define void @t1(i32 %a, i32 %b) {
+; CHECK: t1:
+; CHECK: ldmfdlt sp!, {r7, pc}
+entry:
+ %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
+ br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
+
+cond_true: ; preds = %entry
+ tail call void @foo( i32 %b )
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/ARM/ifcvt6.ll b/test/CodeGen/ARM/ifcvt6.ll
new file mode 100644
index 0000000..d7fcf7d
--- /dev/null
+++ b/test/CodeGen/ARM/ifcvt6.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
+; RUN: grep cmpne | count 1
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
+; RUN: grep ldmfdhi | count 1
+
+define void @foo(i32 %X, i32 %Y) {
+entry:
+ %tmp1 = icmp ult i32 %X, 4 ; <i1> [#uses=1]
+ %tmp4 = icmp eq i32 %Y, 0 ; <i1> [#uses=1]
+ %tmp7 = or i1 %tmp4, %tmp1 ; <i1> [#uses=1]
+ br i1 %tmp7, label %cond_true, label %UnifiedReturnBlock
+
+cond_true: ; preds = %entry
+ %tmp10 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+declare i32 @bar(...)
diff --git a/test/CodeGen/ARM/ifcvt7.ll b/test/CodeGen/ARM/ifcvt7.ll
new file mode 100644
index 0000000..c60ad93
--- /dev/null
+++ b/test/CodeGen/ARM/ifcvt7.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
+; RUN: grep cmpeq | count 1
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
+; RUN: grep moveq | count 1
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
+; RUN: grep ldmfdeq | count 1
+; FIXME: Need post-ifcvt branch folding to get rid of the extra br at end of BB1.
+
+ %struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }
+
+define fastcc i32 @CountTree(%struct.quad_struct* %tree) {
+entry:
+ br label %tailrecurse
+
+tailrecurse: ; preds = %bb, %entry
+ %tmp6 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1]
+ %tmp9 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=2]
+ %tmp12 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1]
+ %tmp14 = icmp eq %struct.quad_struct* null, null ; <i1> [#uses=1]
+ %tmp17 = icmp eq %struct.quad_struct* %tmp6, null ; <i1> [#uses=1]
+ %tmp23 = icmp eq %struct.quad_struct* %tmp9, null ; <i1> [#uses=1]
+ %tmp29 = icmp eq %struct.quad_struct* %tmp12, null ; <i1> [#uses=1]
+ %bothcond = and i1 %tmp17, %tmp14 ; <i1> [#uses=1]
+ %bothcond1 = and i1 %bothcond, %tmp23 ; <i1> [#uses=1]
+ %bothcond2 = and i1 %bothcond1, %tmp29 ; <i1> [#uses=1]
+ br i1 %bothcond2, label %return, label %bb
+
+bb: ; preds = %tailrecurse
+ %tmp41 = tail call fastcc i32 @CountTree( %struct.quad_struct* %tmp9 ) ; <i32> [#uses=0]
+ br label %tailrecurse
+
+return: ; preds = %tailrecurse
+ ret i32 0
+}
diff --git a/test/CodeGen/ARM/ifcvt8.ll b/test/CodeGen/ARM/ifcvt8.ll
new file mode 100644
index 0000000..a7da834
--- /dev/null
+++ b/test/CodeGen/ARM/ifcvt8.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
+; RUN: grep ldmfdne | count 1
+
+ %struct.SString = type { i8*, i32, i32 }
+
+declare void @abort()
+
+define fastcc void @t(%struct.SString* %word, i8 signext %c) {
+entry:
+ %tmp1 = icmp eq %struct.SString* %word, null ; <i1> [#uses=1]
+ br i1 %tmp1, label %cond_true, label %cond_false
+
+cond_true: ; preds = %entry
+ tail call void @abort( )
+ unreachable
+
+cond_false: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/ARM/ifcvt9.ll b/test/CodeGen/ARM/ifcvt9.ll
new file mode 100644
index 0000000..05bdc459
--- /dev/null
+++ b/test/CodeGen/ARM/ifcvt9.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=arm
+
+define fastcc void @t() nounwind {
+entry:
+ br i1 undef, label %bb.i.i3, label %growMapping.exit
+
+bb.i.i3: ; preds = %entry
+ unreachable
+
+growMapping.exit: ; preds = %entry
+ unreachable
+}
diff --git a/test/CodeGen/ARM/illegal-vector-bitcast.ll b/test/CodeGen/ARM/illegal-vector-bitcast.ll
new file mode 100644
index 0000000..febe6f5
--- /dev/null
+++ b/test/CodeGen/ARM/illegal-vector-bitcast.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -mtriple=arm-linux
+
+define void @foo(<8 x float>* %f, <8 x float>* %g, <4 x i64>* %y)
+{
+ %h = load <8 x float>* %f
+ %i = fmul <8 x float> %h, <float 0x3FF19999A0000000, float 0x400A666660000000, float 0x40119999A0000000, float 0x40159999A0000000, float 0.5, float 0x3FE3333340000000, float 0x3FE6666660000000, float 0x3FE99999A0000000>
+ %m = bitcast <8 x float> %i to <4 x i64>
+ %z = load <4 x i64>* %y
+ %n = mul <4 x i64> %z, %m
+ %p = bitcast <4 x i64> %n to <8 x float>
+ store <8 x float> %p, <8 x float>* %g
+ ret void
+}
diff --git a/test/CodeGen/ARM/imm.ll b/test/CodeGen/ARM/imm.ll
new file mode 100644
index 0000000..6f25f9d
--- /dev/null
+++ b/test/CodeGen/ARM/imm.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=arm | not grep CPI
+
+define i32 @test1(i32 %A) {
+ %B = add i32 %A, -268435441 ; <i32> [#uses=1]
+ ret i32 %B
+}
+
+define i32 @test2() {
+ ret i32 65533
+}
+
+define i32 @test3(i32 %A) {
+ %B = or i32 %A, 65533 ; <i32> [#uses=1]
+ ret i32 %B
+}
+
diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll
new file mode 100644
index 0000000..5135d03
--- /dev/null
+++ b/test/CodeGen/ARM/indirectbr.ll
@@ -0,0 +1,64 @@
+; RUN: llc < %s -relocation-model=pic -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=ARM
+; RUN: llc < %s -relocation-model=pic -mtriple=thumb-apple-darwin | FileCheck %s -check-prefix=THUMB
+; RUN: llc < %s -relocation-model=static -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=THUMB2
+
+@nextaddr = global i8* null ; <i8**> [#uses=2]
[email protected] = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
+
+define internal arm_apcscc i32 @foo(i32 %i) nounwind {
+; ARM: foo:
+; THUMB: foo:
+; THUMB2: foo:
+entry:
+ %0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2]
+ %1 = icmp eq i8* %0, null ; <i1> [#uses=1]
+; indirect branch gets duplicated here
+; ARM: bx
+; THUMB: mov pc, r1
+; THUMB2: mov pc, r1
+ br i1 %1, label %bb3, label %bb2
+
+bb2: ; preds = %entry, %bb3
+ %gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1]
+; ARM: bx
+; THUMB: mov pc, r1
+; THUMB2: mov pc, r1
+ indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
+
+bb3: ; preds = %entry
+ %2 = getelementptr inbounds [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1]
+ %gotovar.4.0.pre = load i8** %2, align 4 ; <i8*> [#uses=1]
+ br label %bb2
+
+L5: ; preds = %bb2
+ br label %L4
+
+L4: ; preds = %L5, %bb2
+ %res.0 = phi i32 [ 385, %L5 ], [ 35, %bb2 ] ; <i32> [#uses=1]
+ br label %L3
+
+L3: ; preds = %L4, %bb2
+ %res.1 = phi i32 [ %res.0, %L4 ], [ 5, %bb2 ] ; <i32> [#uses=1]
+ br label %L2
+
+L2: ; preds = %L3, %bb2
+ %res.2 = phi i32 [ %res.1, %L3 ], [ 1, %bb2 ] ; <i32> [#uses=1]
+ %phitmp = mul i32 %res.2, 6 ; <i32> [#uses=1]
+ br label %L1
+
+L1: ; preds = %L2, %bb2
+ %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1]
+; ARM: ldr r1, LCPI
+; ARM: add r1, pc, r1
+; ARM: str r1
+; THUMB: ldr.n r2, LCPI
+; THUMB: add r2, pc
+; THUMB: str r2
+; THUMB2: ldr.n r2, LCPI
+; THUMB2-NEXT: str r2
+ store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
+ ret i32 %res.3
+}
+; ARM: .long L_BA4__foo_L5-(LPC{{.*}}+8)
+; THUMB: .long L_BA4__foo_L5-(LPC{{.*}}+4)
+; THUMB2: .long L_BA4__foo_L5
diff --git a/test/CodeGen/ARM/inlineasm-imm-arm.ll b/test/CodeGen/ARM/inlineasm-imm-arm.ll
new file mode 100644
index 0000000..45dfcf0
--- /dev/null
+++ b/test/CodeGen/ARM/inlineasm-imm-arm.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=arm
+
+; Test ARM-mode "I" constraint, for any Data Processing immediate.
+define i32 @testI(i32 %x) {
+ %y = call i32 asm "add $0, $1, $2", "=r,r,I"( i32 %x, i32 65280 ) nounwind
+ ret i32 %y
+}
+
+; Test ARM-mode "J" constraint, for compatibility with unknown use in GCC.
+define void @testJ() {
+ tail call void asm sideeffect ".word $0", "J"( i32 4080 ) nounwind
+ ret void
+}
+
+; Test ARM-mode "K" constraint, for bitwise inverted Data Processing immediates.
+define void @testK() {
+ tail call void asm sideeffect ".word $0", "K"( i32 16777215 ) nounwind
+ ret void
+}
+
+; Test ARM-mode "L" constraint, for negated Data Processing immediates.
+define void @testL() {
+ tail call void asm sideeffect ".word $0", "L"( i32 -65280 ) nounwind
+ ret void
+}
+
+; Test ARM-mode "M" constraint, for value between 0 and 32.
+define i32 @testM(i32 %x) {
+ %y = call i32 asm "lsl $0, $1, $2", "=r,r,M"( i32 %x, i32 31 ) nounwind
+ ret i32 %y
+}
diff --git a/test/CodeGen/ARM/inlineasm.ll b/test/CodeGen/ARM/inlineasm.ll
new file mode 100644
index 0000000..d522348
--- /dev/null
+++ b/test/CodeGen/ARM/inlineasm.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=arm -mattr=+v6
+
+define i32 @test1(i32 %tmp54) {
+ %tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 ) ; <i32> [#uses=1]
+ ret i32 %tmp56
+}
+
+define void @test2() {
+ %tmp1 = call i64 asm "ldmia $1!, {$0, ${0:H}}", "=r,=*r,1"( i32** null, i32* null ) ; <i64> [#uses=2]
+ %tmp2 = lshr i64 %tmp1, 32 ; <i64> [#uses=1]
+ %tmp3 = trunc i64 %tmp2 to i32 ; <i32> [#uses=1]
+ %tmp4 = call i32 asm "pkhbt $0, $1, $2, lsl #16", "=r,r,r"( i32 0, i32 %tmp3 ) ; <i32> [#uses=0]
+ ret void
+}
+
+define void @test3() {
+ tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )
+ ret void
+}
diff --git a/test/CodeGen/ARM/inlineasm2.ll b/test/CodeGen/ARM/inlineasm2.ll
new file mode 100644
index 0000000..a99bccf
--- /dev/null
+++ b/test/CodeGen/ARM/inlineasm2.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2
+
+define double @__ieee754_sqrt(double %x) {
+ %tmp2 = tail call double asm "fsqrtd ${0:P}, ${1:P}", "=w,w"( double %x )
+ ret double %tmp2
+}
+
+define float @__ieee754_sqrtf(float %x) {
+ %tmp2 = tail call float asm "fsqrts $0, $1", "=w,w"( float %x )
+ ret float %tmp2
+}
diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll
new file mode 100644
index 0000000..f062772
--- /dev/null
+++ b/test/CodeGen/ARM/inlineasm3.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+; Radar 7449043
+%struct.int32x4_t = type { <4 x i32> }
+
+define arm_apcscc void @t() nounwind {
+entry:
+; CHECK: vmov.I64 q15, #0
+; CHECK: vmov.32 d30[0], r0
+; CHECK: vmov q0, q15
+ %tmp = alloca %struct.int32x4_t, align 16
+ call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind
+ ret void
+}
+
+; Radar 7457110
+%struct.int32x2_t = type { <4 x i32> }
+
+define arm_apcscc void @t2() nounwind {
+entry:
+; CHECK: vmov d30, d0
+; CHECK: vmov.32 r0, d30[0]
+ %asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind
+ ret void
+}
diff --git a/test/CodeGen/ARM/insn-sched1.ll b/test/CodeGen/ARM/insn-sched1.ll
new file mode 100644
index 0000000..59f0d53
--- /dev/null
+++ b/test/CodeGen/ARM/insn-sched1.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=arm -mattr=+v6
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 |\
+; RUN: grep mov | count 3
+
+define i32 @test(i32 %x) {
+ %tmp = trunc i32 %x to i16 ; <i16> [#uses=1]
+ %tmp2 = tail call i32 @f( i32 1, i16 %tmp ) ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
+
+declare i32 @f(i32, i16)
diff --git a/test/CodeGen/ARM/ispositive.ll b/test/CodeGen/ARM/ispositive.ll
new file mode 100644
index 0000000..245ed51
--- /dev/null
+++ b/test/CodeGen/ARM/ispositive.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+
+define i32 @test1(i32 %X) {
+; CHECK: mov r0, r0, lsr #31
+entry:
+ icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]
+ zext i1 %0 to i32 ; <i32>:1 [#uses=1]
+ ret i32 %1
+}
+
diff --git a/test/CodeGen/ARM/large-stack.ll b/test/CodeGen/ARM/large-stack.ll
new file mode 100644
index 0000000..ddf0f0e
--- /dev/null
+++ b/test/CodeGen/ARM/large-stack.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=arm
+
+define void @test1() {
+ %tmp = alloca [ 64 x i32 ] , align 4
+ ret void
+}
+
+define void @test2() {
+ %tmp = alloca [ 4168 x i8 ] , align 4
+ ret void
+}
+
+define i32 @test3() {
+ %retval = alloca i32, align 4
+ %tmp = alloca i32, align 4
+ %a = alloca [805306369 x i8], align 16
+ store i32 0, i32* %tmp
+ %tmp1 = load i32* %tmp
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/ARM/ldm.ll b/test/CodeGen/ARM/ldm.ll
new file mode 100644
index 0000000..1a016a0
--- /dev/null
+++ b/test/CodeGen/ARM/ldm.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
+
+@X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
+
+define i32 @t1() {
+; CHECK: t1:
+; CHECK: ldmia
+ %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1]
+ %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
+ %tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; <i32> [#uses=1]
+ ret i32 %tmp4
+}
+
+define i32 @t2() {
+; CHECK: t2:
+; CHECK: ldmia
+ %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
+ %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
+ %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4) ; <i32> [#uses=1]
+ %tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+define i32 @t3() {
+; CHECK: t3:
+; CHECK: ldmib
+; CHECK: ldmfd sp!
+ %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
+ %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
+ %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
+ %tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+declare i32 @f1(i32, i32)
+
+declare i32 @f2(i32, i32, i32)
diff --git a/test/CodeGen/ARM/ldr.ll b/test/CodeGen/ARM/ldr.ll
new file mode 100644
index 0000000..011e61c
--- /dev/null
+++ b/test/CodeGen/ARM/ldr.ll
@@ -0,0 +1,71 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+
+define i32 @f1(i32* %v) {
+; CHECK: f1:
+; CHECK: ldr r0
+entry:
+ %tmp = load i32* %v
+ ret i32 %tmp
+}
+
+define i32 @f2(i32* %v) {
+; CHECK: f2:
+; CHECK: ldr r0
+entry:
+ %tmp2 = getelementptr i32* %v, i32 1023
+ %tmp = load i32* %tmp2
+ ret i32 %tmp
+}
+
+define i32 @f3(i32* %v) {
+; CHECK: f3:
+; CHECK: mov
+; CHECK: ldr r0
+entry:
+ %tmp2 = getelementptr i32* %v, i32 1024
+ %tmp = load i32* %tmp2
+ ret i32 %tmp
+}
+
+define i32 @f4(i32 %base) {
+; CHECK: f4:
+; CHECK-NOT: mvn
+; CHECK: ldr r0
+entry:
+ %tmp1 = sub i32 %base, 128
+ %tmp2 = inttoptr i32 %tmp1 to i32*
+ %tmp3 = load i32* %tmp2
+ ret i32 %tmp3
+}
+
+define i32 @f5(i32 %base, i32 %offset) {
+; CHECK: f5:
+; CHECK: ldr r0
+entry:
+ %tmp1 = add i32 %base, %offset
+ %tmp2 = inttoptr i32 %tmp1 to i32*
+ %tmp3 = load i32* %tmp2
+ ret i32 %tmp3
+}
+
+define i32 @f6(i32 %base, i32 %offset) {
+; CHECK: f6:
+; CHECK: ldr r0{{.*}}lsl{{.*}}
+entry:
+ %tmp1 = shl i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i32*
+ %tmp4 = load i32* %tmp3
+ ret i32 %tmp4
+}
+
+define i32 @f7(i32 %base, i32 %offset) {
+; CHECK: f7:
+; CHECK: ldr r0{{.*}}lsr{{.*}}
+entry:
+ %tmp1 = lshr i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i32*
+ %tmp4 = load i32* %tmp3
+ ret i32 %tmp4
+}
diff --git a/test/CodeGen/ARM/ldr_ext.ll b/test/CodeGen/ARM/ldr_ext.ll
new file mode 100644
index 0000000..d29eb02
--- /dev/null
+++ b/test/CodeGen/ARM/ldr_ext.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+
+define i32 @test1(i8* %t1) nounwind {
+; CHECK: ldrb
+ %tmp.u = load i8* %t1
+ %tmp1.s = zext i8 %tmp.u to i32
+ ret i32 %tmp1.s
+}
+
+define i32 @test2(i16* %t1) nounwind {
+; CHECK: ldrh
+ %tmp.u = load i16* %t1
+ %tmp1.s = zext i16 %tmp.u to i32
+ ret i32 %tmp1.s
+}
+
+define i32 @test3(i8* %t0) nounwind {
+; CHECK: ldrsb
+ %tmp.s = load i8* %t0
+ %tmp1.s = sext i8 %tmp.s to i32
+ ret i32 %tmp1.s
+}
+
+define i32 @test4(i16* %t0) nounwind {
+; CHECK: ldrsh
+ %tmp.s = load i16* %t0
+ %tmp1.s = sext i16 %tmp.s to i32
+ ret i32 %tmp1.s
+}
+
+define i32 @test5() nounwind {
+; CHECK: mov r0, #0
+; CHECK: ldrsh
+ %tmp.s = load i16* null
+ %tmp1.s = sext i16 %tmp.s to i32
+ ret i32 %tmp1.s
+}
diff --git a/test/CodeGen/ARM/ldr_frame.ll b/test/CodeGen/ARM/ldr_frame.ll
new file mode 100644
index 0000000..a3abdb6
--- /dev/null
+++ b/test/CodeGen/ARM/ldr_frame.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=arm | not grep mov
+
+define i32 @f1() {
+ %buf = alloca [32 x i32], align 4
+ %tmp = getelementptr [32 x i32]* %buf, i32 0, i32 0
+ %tmp1 = load i32* %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f2() {
+ %buf = alloca [32 x i8], align 4
+ %tmp = getelementptr [32 x i8]* %buf, i32 0, i32 0
+ %tmp1 = load i8* %tmp
+ %tmp2 = zext i8 %tmp1 to i32
+ ret i32 %tmp2
+}
+
+define i32 @f3() {
+ %buf = alloca [32 x i32], align 4
+ %tmp = getelementptr [32 x i32]* %buf, i32 0, i32 32
+ %tmp1 = load i32* %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f4() {
+ %buf = alloca [32 x i8], align 4
+ %tmp = getelementptr [32 x i8]* %buf, i32 0, i32 2
+ %tmp1 = load i8* %tmp
+ %tmp2 = zext i8 %tmp1 to i32
+ ret i32 %tmp2
+}
diff --git a/test/CodeGen/ARM/ldr_post.ll b/test/CodeGen/ARM/ldr_post.ll
new file mode 100644
index 0000000..97a48e1
--- /dev/null
+++ b/test/CodeGen/ARM/ldr_post.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=arm | \
+; RUN: grep {ldr.*\\\[.*\],} | count 1
+
+define i32 @test(i32 %a, i32 %b, i32 %c) {
+ %tmp1 = mul i32 %a, %b ; <i32> [#uses=2]
+ %tmp2 = inttoptr i32 %tmp1 to i32* ; <i32*> [#uses=1]
+ %tmp3 = load i32* %tmp2 ; <i32> [#uses=1]
+ %tmp4 = sub i32 %tmp1, %c ; <i32> [#uses=1]
+ %tmp5 = mul i32 %tmp4, %tmp3 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
diff --git a/test/CodeGen/ARM/ldr_pre.ll b/test/CodeGen/ARM/ldr_pre.ll
new file mode 100644
index 0000000..7c44284
--- /dev/null
+++ b/test/CodeGen/ARM/ldr_pre.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=arm | \
+; RUN: grep {ldr.*\\!} | count 2
+
+define i32* @test1(i32* %X, i32* %dest) {
+ %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2]
+ %A = load i32* %Y ; <i32> [#uses=1]
+ store i32 %A, i32* %dest
+ ret i32* %Y
+}
+
+define i32 @test2(i32 %a, i32 %b, i32 %c) {
+ %tmp1 = sub i32 %a, %b ; <i32> [#uses=2]
+ %tmp2 = inttoptr i32 %tmp1 to i32* ; <i32*> [#uses=1]
+ %tmp3 = load i32* %tmp2 ; <i32> [#uses=1]
+ %tmp4 = sub i32 %tmp1, %c ; <i32> [#uses=1]
+ %tmp5 = add i32 %tmp4, %tmp3 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll
new file mode 100644
index 0000000..c366e2d
--- /dev/null
+++ b/test/CodeGen/ARM/ldrd.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=V6
+; RUN: llc < %s -mtriple=armv5-apple-darwin | FileCheck %s -check-prefix=V5
+; RUN: llc < %s -mtriple=armv6-eabi | FileCheck %s -check-prefix=EABI
+; rdar://r6949835
+
+@b = external global i64*
+
+define i64 @t(i64 %a) nounwind readonly {
+entry:
+;V6: ldrd r2, [r2]
+
+;V5: ldr r3, [r2]
+;V5: ldr r2, [r2, #+4]
+
+;EABI: ldr r3, [r2]
+;EABI: ldr r2, [r2, #+4]
+
+ %0 = load i64** @b, align 4
+ %1 = load i64* %0, align 4
+ %2 = mul i64 %1, %a
+ ret i64 %2
+}
diff --git a/test/CodeGen/ARM/load.ll b/test/CodeGen/ARM/load.ll
new file mode 100644
index 0000000..253b0e1
--- /dev/null
+++ b/test/CodeGen/ARM/load.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=arm > %t
+; RUN: grep ldrsb %t
+; RUN: grep ldrb %t
+; RUN: grep ldrsh %t
+; RUN: grep ldrh %t
+
+
+define i32 @f1(i8* %p) {
+entry:
+ %tmp = load i8* %p ; <i8> [#uses=1]
+ %tmp1 = sext i8 %tmp to i32 ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32 @f2(i8* %p) {
+entry:
+ %tmp = load i8* %p ; <i8> [#uses=1]
+ %tmp2 = zext i8 %tmp to i32 ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
+
+define i32 @f3(i16* %p) {
+entry:
+ %tmp = load i16* %p ; <i16> [#uses=1]
+ %tmp3 = sext i16 %tmp to i32 ; <i32> [#uses=1]
+ ret i32 %tmp3
+}
+
+define i32 @f4(i16* %p) {
+entry:
+ %tmp = load i16* %p ; <i16> [#uses=1]
+ %tmp4 = zext i16 %tmp to i32 ; <i32> [#uses=1]
+ ret i32 %tmp4
+}
diff --git a/test/CodeGen/ARM/long-setcc.ll b/test/CodeGen/ARM/long-setcc.ll
new file mode 100644
index 0000000..c76a5e4
--- /dev/null
+++ b/test/CodeGen/ARM/long-setcc.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=arm | grep cmp | count 1
+
+
+define i1 @t1(i64 %x) {
+ %B = icmp slt i64 %x, 0
+ ret i1 %B
+}
+
+define i1 @t2(i64 %x) {
+ %tmp = icmp ult i64 %x, 4294967296
+ ret i1 %tmp
+}
+
+define i1 @t3(i32 %x) {
+ %tmp = icmp ugt i32 %x, -1
+ ret i1 %tmp
+}
diff --git a/test/CodeGen/ARM/long.ll b/test/CodeGen/ARM/long.ll
new file mode 100644
index 0000000..16ef7cc
--- /dev/null
+++ b/test/CodeGen/ARM/long.ll
@@ -0,0 +1,90 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+
+define i64 @f1() {
+; CHECK: f1:
+entry:
+ ret i64 0
+}
+
+define i64 @f2() {
+; CHECK: f2:
+entry:
+ ret i64 1
+}
+
+define i64 @f3() {
+; CHECK: f3:
+; CHECK: mvn{{.*}}-2147483648
+entry:
+ ret i64 2147483647
+}
+
+define i64 @f4() {
+; CHECK: f4:
+; CHECK: -2147483648
+entry:
+ ret i64 2147483648
+}
+
+define i64 @f5() {
+; CHECK: f5:
+; CHECK: mvn
+; CHECK: mvn{{.*}}-2147483648
+entry:
+ ret i64 9223372036854775807
+}
+
+define i64 @f6(i64 %x, i64 %y) {
+; CHECK: f6:
+; CHECK: adds
+; CHECK: adc
+entry:
+ %tmp1 = add i64 %y, 1 ; <i64> [#uses=1]
+ ret i64 %tmp1
+}
+
+define void @f7() {
+; CHECK: f7:
+entry:
+ %tmp = call i64 @f8( ) ; <i64> [#uses=0]
+ ret void
+}
+
+declare i64 @f8()
+
+define i64 @f9(i64 %a, i64 %b) {
+; CHECK: f9:
+; CHECK: subs r
+; CHECK: sbc
+entry:
+ %tmp = sub i64 %a, %b ; <i64> [#uses=1]
+ ret i64 %tmp
+}
+
+define i64 @f(i32 %a, i32 %b) {
+; CHECK: f:
+; CHECK: smull
+entry:
+ %tmp = sext i32 %a to i64 ; <i64> [#uses=1]
+ %tmp1 = sext i32 %b to i64 ; <i64> [#uses=1]
+ %tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
+ ret i64 %tmp2
+}
+
+define i64 @g(i32 %a, i32 %b) {
+; CHECK: g:
+; CHECK: umull
+entry:
+ %tmp = zext i32 %a to i64 ; <i64> [#uses=1]
+ %tmp1 = zext i32 %b to i64 ; <i64> [#uses=1]
+ %tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
+ ret i64 %tmp2
+}
+
+define i64 @f10() {
+; CHECK: f10:
+entry:
+ %a = alloca i64, align 8 ; <i64*> [#uses=1]
+ %retval = load i64* %a ; <i64> [#uses=1]
+ ret i64 %retval
+}
diff --git a/test/CodeGen/ARM/long_shift.ll b/test/CodeGen/ARM/long_shift.ll
new file mode 100644
index 0000000..76332cc
--- /dev/null
+++ b/test/CodeGen/ARM/long_shift.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+
+define i64 @f0(i64 %A, i64 %B) {
+; CHECK: f0
+; CHECK: movs r3, r3, lsr #1
+; CHECK-NEXT: mov r2, r2, rrx
+; CHECK-NEXT: subs r0, r0, r2
+; CHECK-NEXT: sbc r1, r1, r3
+ %tmp = bitcast i64 %A to i64
+ %tmp2 = lshr i64 %B, 1
+ %tmp3 = sub i64 %tmp, %tmp2
+ ret i64 %tmp3
+}
+
+define i32 @f1(i64 %x, i64 %y) {
+; CHECK: f1
+; CHECK: mov r0, r0, lsl r2
+ %a = shl i64 %x, %y
+ %b = trunc i64 %a to i32
+ ret i32 %b
+}
+
+define i32 @f2(i64 %x, i64 %y) {
+; CHECK: f2
+; CHECK: mov r0, r0, lsr r2
+; CHECK-NEXT: rsb r12, r2, #32
+; CHECK-NEXT: sub r2, r2, #32
+; CHECK-NEXT: cmp r2, #0
+; CHECK-NEXT: orr r0, r0, r1, lsl r12
+; CHECK-NEXT: movge r0, r1, asr r2
+ %a = ashr i64 %x, %y
+ %b = trunc i64 %a to i32
+ ret i32 %b
+}
+
+define i32 @f3(i64 %x, i64 %y) {
+; CHECK: f3
+; CHECK: mov r0, r0, lsr r2
+; CHECK-NEXT: rsb r12, r2, #32
+; CHECK-NEXT: sub r2, r2, #32
+; CHECK-NEXT: cmp r2, #0
+; CHECK-NEXT: orr r0, r0, r1, lsl r12
+; CHECK-NEXT: movge r0, r1, lsr r2
+ %a = lshr i64 %x, %y
+ %b = trunc i64 %a to i32
+ ret i32 %b
+}
diff --git a/test/CodeGen/ARM/lsr-code-insertion.ll b/test/CodeGen/ARM/lsr-code-insertion.ll
new file mode 100644
index 0000000..507ec2c
--- /dev/null
+++ b/test/CodeGen/ARM/lsr-code-insertion.ll
@@ -0,0 +1,60 @@
+; RUN: llc < %s -stats |& grep {40.*Number of machine instrs printed}
+; RUN: llc < %s -stats |& grep {.*Number of re-materialization}
+; This test really wants to check that the resultant "cond_true" block only
+; has a single store in it, and that cond_true55 only has code to materialize
+; the constant and do a store. We do *not* want something like this:
+;
+;LBB1_3: @cond_true
+; add r8, r0, r6
+; str r10, [r8, #+4]
+;
+target triple = "arm-apple-darwin8"
+
+define void @foo(i32* %mc, i32* %mpp, i32* %ip, i32* %dpp, i32* %tpmm, i32 %M, i32* %tpim, i32* %tpdm, i32* %bp, i32* %ms, i32 %xmb) {
+entry:
+ %tmp6584 = icmp slt i32 %M, 1 ; <i1> [#uses=1]
+ br i1 %tmp6584, label %return, label %bb
+
+bb: ; preds = %cond_next59, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %k.069.0, %cond_next59 ] ; <i32> [#uses=6]
+ %k.069.0 = add i32 %indvar, 1 ; <i32> [#uses=3]
+ %tmp3 = getelementptr i32* %mpp, i32 %indvar ; <i32*> [#uses=1]
+ %tmp4 = load i32* %tmp3 ; <i32> [#uses=1]
+ %tmp8 = getelementptr i32* %tpmm, i32 %indvar ; <i32*> [#uses=1]
+ %tmp9 = load i32* %tmp8 ; <i32> [#uses=1]
+ %tmp10 = add i32 %tmp9, %tmp4 ; <i32> [#uses=2]
+ %tmp13 = getelementptr i32* %mc, i32 %k.069.0 ; <i32*> [#uses=5]
+ store i32 %tmp10, i32* %tmp13
+ %tmp17 = getelementptr i32* %ip, i32 %indvar ; <i32*> [#uses=1]
+ %tmp18 = load i32* %tmp17 ; <i32> [#uses=1]
+ %tmp22 = getelementptr i32* %tpim, i32 %indvar ; <i32*> [#uses=1]
+ %tmp23 = load i32* %tmp22 ; <i32> [#uses=1]
+ %tmp24 = add i32 %tmp23, %tmp18 ; <i32> [#uses=2]
+ %tmp30 = icmp sgt i32 %tmp24, %tmp10 ; <i1> [#uses=1]
+ br i1 %tmp30, label %cond_true, label %cond_next
+
+cond_true: ; preds = %bb
+ store i32 %tmp24, i32* %tmp13
+ br label %cond_next
+
+cond_next: ; preds = %cond_true, %bb
+ %tmp39 = load i32* %tmp13 ; <i32> [#uses=1]
+ %tmp42 = getelementptr i32* %ms, i32 %k.069.0 ; <i32*> [#uses=1]
+ %tmp43 = load i32* %tmp42 ; <i32> [#uses=1]
+ %tmp44 = add i32 %tmp43, %tmp39 ; <i32> [#uses=2]
+ store i32 %tmp44, i32* %tmp13
+ %tmp52 = icmp slt i32 %tmp44, -987654321 ; <i1> [#uses=1]
+ br i1 %tmp52, label %cond_true55, label %cond_next59
+
+cond_true55: ; preds = %cond_next
+ store i32 -987654321, i32* %tmp13
+ br label %cond_next59
+
+cond_next59: ; preds = %cond_true55, %cond_next
+ %tmp61 = add i32 %indvar, 2 ; <i32> [#uses=1]
+ %tmp65 = icmp sgt i32 %tmp61, %M ; <i1> [#uses=1]
+ br i1 %tmp65, label %return, label %bb
+
+return: ; preds = %cond_next59, %entry
+ ret void
+}
diff --git a/test/CodeGen/ARM/lsr-scale-addr-mode.ll b/test/CodeGen/ARM/lsr-scale-addr-mode.ll
new file mode 100644
index 0000000..8130019
--- /dev/null
+++ b/test/CodeGen/ARM/lsr-scale-addr-mode.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=arm | grep lsl | grep -F {lsl #2\]}
+; Should use scaled addressing mode.
+
+define void @sintzero(i32* %a) nounwind {
+entry:
+ store i32 0, i32* %a
+ br label %cond_next
+
+cond_next: ; preds = %cond_next, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %tmp25, %cond_next ] ; <i32> [#uses=1]
+ %tmp25 = add i32 %indvar, 1 ; <i32> [#uses=3]
+ %tmp36 = getelementptr i32* %a, i32 %tmp25 ; <i32*> [#uses=1]
+ store i32 0, i32* %tmp36
+ icmp eq i32 %tmp25, -1 ; <i1>:0 [#uses=1]
+ br i1 %0, label %return, label %cond_next
+
+return: ; preds = %cond_next
+ ret void
+}
diff --git a/test/CodeGen/ARM/mem.ll b/test/CodeGen/ARM/mem.ll
new file mode 100644
index 0000000..f46c7a5
--- /dev/null
+++ b/test/CodeGen/ARM/mem.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=arm | grep strb
+; RUN: llc < %s -march=arm | grep strh
+
+define void @f1() {
+entry:
+ store i8 0, i8* null
+ ret void
+}
+
+define void @f2() {
+entry:
+ store i16 0, i16* null
+ ret void
+}
diff --git a/test/CodeGen/ARM/memcpy-inline.ll b/test/CodeGen/ARM/memcpy-inline.ll
new file mode 100644
index 0000000..ed20c32
--- /dev/null
+++ b/test/CodeGen/ARM/memcpy-inline.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin | grep ldmia
+; RUN: llc < %s -mtriple=arm-apple-darwin | grep stmia
+; RUN: llc < %s -mtriple=arm-apple-darwin | grep ldrb
+; RUN: llc < %s -mtriple=arm-apple-darwin | grep ldrh
+
+ %struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
+@src = external global %struct.x
+@dst = external global %struct.x
+
+define i32 @t() {
+entry:
+ call void @llvm.memcpy.i32( i8* getelementptr (%struct.x* @dst, i32 0, i32 0), i8* getelementptr (%struct.x* @src, i32 0, i32 0), i32 11, i32 8 )
+ ret i32 0
+}
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32)
diff --git a/test/CodeGen/ARM/memfunc.ll b/test/CodeGen/ARM/memfunc.ll
new file mode 100644
index 0000000..41d5944
--- /dev/null
+++ b/test/CodeGen/ARM/memfunc.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=arm
+
+define void @f() {
+entry:
+ call void @llvm.memmove.i32( i8* null, i8* null, i32 64, i32 0 )
+ call void @llvm.memcpy.i32( i8* null, i8* null, i32 64, i32 0 )
+ call void @llvm.memset.i32( i8* null, i8 64, i32 0, i32 0 )
+ unreachable
+}
+
+declare void @llvm.memmove.i32(i8*, i8*, i32, i32)
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32)
+
+declare void @llvm.memset.i32(i8*, i8, i32, i32)
+
diff --git a/test/CodeGen/ARM/mls.ll b/test/CodeGen/ARM/mls.ll
new file mode 100644
index 0000000..a6cdba4
--- /dev/null
+++ b/test/CodeGen/ARM/mls.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+ %tmp1 = mul i32 %a, %b
+ %tmp2 = sub i32 %c, %tmp1
+ ret i32 %tmp2
+}
+
+; sub doesn't commute, so no mls for this one
+define i32 @f2(i32 %a, i32 %b, i32 %c) {
+ %tmp1 = mul i32 %a, %b
+ %tmp2 = sub i32 %tmp1, %c
+ ret i32 %tmp2
+}
+
+; CHECK: mls r0, r0, r1, r2
diff --git a/test/CodeGen/ARM/movt-movw-global.ll b/test/CodeGen/ARM/movt-movw-global.ll
new file mode 100644
index 0000000..886ff3f
--- /dev/null
+++ b/test/CodeGen/ARM/movt-movw-global.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv7-eabi"
+
+@foo = common global i32 0 ; <i32*> [#uses=1]
+
+define arm_aapcs_vfpcc i32* @bar1() nounwind readnone {
+entry:
+; CHECK: movw r0, :lower16:foo
+; CHECK-NEXT: movt r0, :upper16:foo
+ ret i32* @foo
+}
+
+define arm_aapcs_vfpcc void @bar2(i32 %baz) nounwind {
+entry:
+; CHECK: movw r1, :lower16:foo
+; CHECK-NEXT: movt r1, :upper16:foo
+ store i32 %baz, i32* @foo, align 4
+ ret void
+}
diff --git a/test/CodeGen/ARM/movt.ll b/test/CodeGen/ARM/movt.ll
new file mode 100644
index 0000000..e82aca0
--- /dev/null
+++ b/test/CodeGen/ARM/movt.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s
+; rdar://7317664
+
+define i32 @t(i32 %X) nounwind {
+; CHECK: t:
+; CHECK: movt r0, #65535
+entry:
+ %0 = or i32 %X, -65536
+ ret i32 %0
+}
+
+define i32 @t2(i32 %X) nounwind {
+; CHECK: t2:
+; CHECK: movt r0, #65534
+entry:
+ %0 = or i32 %X, -131072
+ %1 = and i32 %0, -65537
+ ret i32 %1
+}
diff --git a/test/CodeGen/ARM/mul.ll b/test/CodeGen/ARM/mul.ll
new file mode 100644
index 0000000..466a802
--- /dev/null
+++ b/test/CodeGen/ARM/mul.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=arm | grep mul | count 2
+; RUN: llc < %s -march=arm | grep lsl | count 2
+
+define i32 @f1(i32 %u) {
+ %tmp = mul i32 %u, %u
+ ret i32 %tmp
+}
+
+define i32 @f2(i32 %u, i32 %v) {
+ %tmp = mul i32 %u, %v
+ ret i32 %tmp
+}
+
+define i32 @f3(i32 %u) {
+ %tmp = mul i32 %u, 5
+ ret i32 %tmp
+}
+
+define i32 @f4(i32 %u) {
+ %tmp = mul i32 %u, 4
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/ARM/mul_const.ll b/test/CodeGen/ARM/mul_const.ll
new file mode 100644
index 0000000..93188cd
--- /dev/null
+++ b/test/CodeGen/ARM/mul_const.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+
+define i32 @t1(i32 %v) nounwind readnone {
+entry:
+; CHECK: t1:
+; CHECK: add r0, r0, r0, lsl #3
+ %0 = mul i32 %v, 9
+ ret i32 %0
+}
+
+define i32 @t2(i32 %v) nounwind readnone {
+entry:
+; CHECK: t2:
+; CHECK: rsb r0, r0, r0, lsl #3
+ %0 = mul i32 %v, 7
+ ret i32 %0
+}
diff --git a/test/CodeGen/ARM/mulhi.ll b/test/CodeGen/ARM/mulhi.ll
new file mode 100644
index 0000000..148f291
--- /dev/null
+++ b/test/CodeGen/ARM/mulhi.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=arm -mattr=+v6
+; RUN: llc < %s -march=arm -mattr=+v6 | \
+; RUN: grep smmul | count 1
+; RUN: llc < %s -march=arm | grep umull | count 1
+
+define i32 @smulhi(i32 %x, i32 %y) {
+ %tmp = sext i32 %x to i64 ; <i64> [#uses=1]
+ %tmp1 = sext i32 %y to i64 ; <i64> [#uses=1]
+ %tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
+ %tmp3 = lshr i64 %tmp2, 32 ; <i64> [#uses=1]
+ %tmp3.upgrd.1 = trunc i64 %tmp3 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp3.upgrd.1
+}
+
+define i32 @umulhi(i32 %x, i32 %y) {
+ %tmp = zext i32 %x to i64 ; <i64> [#uses=1]
+ %tmp1 = zext i32 %y to i64 ; <i64> [#uses=1]
+ %tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
+ %tmp3 = lshr i64 %tmp2, 32 ; <i64> [#uses=1]
+ %tmp3.upgrd.2 = trunc i64 %tmp3 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp3.upgrd.2
+}
diff --git a/test/CodeGen/ARM/mvn.ll b/test/CodeGen/ARM/mvn.ll
new file mode 100644
index 0000000..571c21a
--- /dev/null
+++ b/test/CodeGen/ARM/mvn.ll
@@ -0,0 +1,74 @@
+; RUN: llc < %s -march=arm | grep mvn | count 8
+
+define i32 @f1() {
+entry:
+ ret i32 -1
+}
+
+define i32 @f2(i32 %a) {
+entry:
+ %tmpnot = xor i32 %a, -1 ; <i32> [#uses=1]
+ ret i32 %tmpnot
+}
+
+define i32 @f3(i32 %a) {
+entry:
+ %tmp1 = shl i32 %a, 2 ; <i32> [#uses=1]
+ %tmp1not = xor i32 %tmp1, -1 ; <i32> [#uses=1]
+ ret i32 %tmp1not
+}
+
+define i32 @f4(i32 %a, i8 %b) {
+entry:
+ %shift.upgrd.1 = zext i8 %b to i32 ; <i32> [#uses=1]
+ %tmp3 = shl i32 %a, %shift.upgrd.1 ; <i32> [#uses=1]
+ %tmp3not = xor i32 %tmp3, -1 ; <i32> [#uses=1]
+ ret i32 %tmp3not
+}
+
+define i32 @f5(i32 %a) {
+entry:
+ %tmp1 = lshr i32 %a, 2 ; <i32> [#uses=1]
+ %tmp1not = xor i32 %tmp1, -1 ; <i32> [#uses=1]
+ ret i32 %tmp1not
+}
+
+define i32 @f6(i32 %a, i8 %b) {
+entry:
+ %shift.upgrd.2 = zext i8 %b to i32 ; <i32> [#uses=1]
+ %tmp2 = lshr i32 %a, %shift.upgrd.2 ; <i32> [#uses=1]
+ %tmp2not = xor i32 %tmp2, -1 ; <i32> [#uses=1]
+ ret i32 %tmp2not
+}
+
+define i32 @f7(i32 %a) {
+entry:
+ %tmp1 = ashr i32 %a, 2 ; <i32> [#uses=1]
+ %tmp1not = xor i32 %tmp1, -1 ; <i32> [#uses=1]
+ ret i32 %tmp1not
+}
+
+define i32 @f8(i32 %a, i8 %b) {
+entry:
+ %shift.upgrd.3 = zext i8 %b to i32 ; <i32> [#uses=1]
+ %tmp3 = ashr i32 %a, %shift.upgrd.3 ; <i32> [#uses=1]
+ %tmp3not = xor i32 %tmp3, -1 ; <i32> [#uses=1]
+ ret i32 %tmp3not
+}
+
+define i32 @f9() {
+entry:
+ %tmp4845 = add i32 0, 0 ; <i32> [#uses=1]
+ br label %cond_true4848
+
+cond_true4848: ; preds = %entry
+ %tmp4851 = sub i32 -3, 0 ; <i32> [#uses=1]
+ %abc = add i32 %tmp4851, %tmp4845 ; <i32> [#uses=1]
+ ret i32 %abc
+}
+
+define i1 @f10(i32 %a) {
+entry:
+ %tmp102 = icmp eq i32 -2, %a ; <i1> [#uses=1]
+ ret i1 %tmp102
+}
diff --git a/test/CodeGen/ARM/neon_arith1.ll b/test/CodeGen/ARM/neon_arith1.ll
new file mode 100644
index 0000000..5892737
--- /dev/null
+++ b/test/CodeGen/ARM/neon_arith1.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=arm -mattr=+neon | grep vadd
+
+define <8 x i8> @t_i8x8(<8 x i8> %a, <8 x i8> %b) nounwind {
+entry:
+ %0 = add <8 x i8> %a, %b
+ ret <8 x i8> %0
+}
diff --git a/test/CodeGen/ARM/neon_ld1.ll b/test/CodeGen/ARM/neon_ld1.ll
new file mode 100644
index 0000000..c78872a
--- /dev/null
+++ b/test/CodeGen/ARM/neon_ld1.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=arm -mattr=+neon | grep vldr.64 | count 4
+; RUN: llc < %s -march=arm -mattr=+neon | grep vstr.64
+; RUN: llc < %s -march=arm -mattr=+neon | grep vmov
+
+define void @t1(<2 x i32>* %r, <4 x i16>* %a, <4 x i16>* %b) nounwind {
+entry:
+ %0 = load <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1]
+ %1 = load <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1]
+ %2 = add <4 x i16> %0, %1 ; <<4 x i16>> [#uses=1]
+ %3 = bitcast <4 x i16> %2 to <2 x i32> ; <<2 x i32>> [#uses=1]
+ store <2 x i32> %3, <2 x i32>* %r, align 8
+ ret void
+}
+
+define <2 x i32> @t2(<4 x i16>* %a, <4 x i16>* %b) nounwind readonly {
+entry:
+ %0 = load <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1]
+ %1 = load <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1]
+ %2 = sub <4 x i16> %0, %1 ; <<4 x i16>> [#uses=1]
+ %3 = bitcast <4 x i16> %2 to <2 x i32> ; <<2 x i32>> [#uses=1]
+ ret <2 x i32> %3
+}
diff --git a/test/CodeGen/ARM/neon_ld2.ll b/test/CodeGen/ARM/neon_ld2.ll
new file mode 100644
index 0000000..130277b
--- /dev/null
+++ b/test/CodeGen/ARM/neon_ld2.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=arm -mattr=+neon | grep vldmia | count 4
+; RUN: llc < %s -march=arm -mattr=+neon | grep vstmia | count 1
+; RUN: llc < %s -march=arm -mattr=+neon | grep vmov | count 2
+
+define void @t1(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+entry:
+ %0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1]
+ %1 = load <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1]
+ %2 = add <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1]
+ %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %3, <4 x i32>* %r, align 16
+ ret void
+}
+
+define <4 x i32> @t2(<2 x i64>* %a, <2 x i64>* %b) nounwind readonly {
+entry:
+ %0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1]
+ %1 = load <2 x i64>* %b, align 16 ; <<2 x i64>> [#uses=1]
+ %2 = sub <2 x i64> %0, %1 ; <<2 x i64>> [#uses=1]
+ %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %3
+}
+
diff --git a/test/CodeGen/ARM/pack.ll b/test/CodeGen/ARM/pack.ll
new file mode 100644
index 0000000..1e2e7aa
--- /dev/null
+++ b/test/CodeGen/ARM/pack.ll
@@ -0,0 +1,73 @@
+; RUN: llc < %s -march=arm -mattr=+v6 | \
+; RUN: grep pkhbt | count 5
+; RUN: llc < %s -march=arm -mattr=+v6 | \
+; RUN: grep pkhtb | count 4
+
+define i32 @test1(i32 %X, i32 %Y) {
+ %tmp1 = and i32 %X, 65535 ; <i32> [#uses=1]
+ %tmp4 = shl i32 %Y, 16 ; <i32> [#uses=1]
+ %tmp5 = or i32 %tmp4, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
+define i32 @test1a(i32 %X, i32 %Y) {
+ %tmp19 = and i32 %X, 65535 ; <i32> [#uses=1]
+ %tmp37 = shl i32 %Y, 16 ; <i32> [#uses=1]
+ %tmp5 = or i32 %tmp37, %tmp19 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
+define i32 @test2(i32 %X, i32 %Y) {
+ %tmp1 = and i32 %X, 65535 ; <i32> [#uses=1]
+ %tmp3 = shl i32 %Y, 12 ; <i32> [#uses=1]
+ %tmp4 = and i32 %tmp3, -65536 ; <i32> [#uses=1]
+ %tmp57 = or i32 %tmp4, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp57
+}
+
+define i32 @test3(i32 %X, i32 %Y) {
+ %tmp19 = and i32 %X, 65535 ; <i32> [#uses=1]
+ %tmp37 = shl i32 %Y, 18 ; <i32> [#uses=1]
+ %tmp5 = or i32 %tmp37, %tmp19 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
+define i32 @test4(i32 %X, i32 %Y) {
+ %tmp1 = and i32 %X, 65535 ; <i32> [#uses=1]
+ %tmp3 = and i32 %Y, -65536 ; <i32> [#uses=1]
+ %tmp46 = or i32 %tmp3, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp46
+}
+
+define i32 @test5(i32 %X, i32 %Y) {
+ %tmp17 = and i32 %X, -65536 ; <i32> [#uses=1]
+ %tmp2 = bitcast i32 %Y to i32 ; <i32> [#uses=1]
+ %tmp4 = lshr i32 %tmp2, 16 ; <i32> [#uses=2]
+ %tmp5 = or i32 %tmp4, %tmp17 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
+define i32 @test5a(i32 %X, i32 %Y) {
+ %tmp110 = and i32 %X, -65536 ; <i32> [#uses=1]
+ %tmp37 = lshr i32 %Y, 16 ; <i32> [#uses=1]
+ %tmp39 = bitcast i32 %tmp37 to i32 ; <i32> [#uses=1]
+ %tmp5 = or i32 %tmp39, %tmp110 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
+define i32 @test6(i32 %X, i32 %Y) {
+ %tmp1 = and i32 %X, -65536 ; <i32> [#uses=1]
+ %tmp37 = lshr i32 %Y, 12 ; <i32> [#uses=1]
+ %tmp38 = bitcast i32 %tmp37 to i32 ; <i32> [#uses=1]
+ %tmp4 = and i32 %tmp38, 65535 ; <i32> [#uses=1]
+ %tmp59 = or i32 %tmp4, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp59
+}
+
+define i32 @test7(i32 %X, i32 %Y) {
+ %tmp1 = and i32 %X, -65536 ; <i32> [#uses=1]
+ %tmp3 = ashr i32 %Y, 18 ; <i32> [#uses=1]
+ %tmp4 = and i32 %tmp3, 65535 ; <i32> [#uses=1]
+ %tmp57 = or i32 %tmp4, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp57
+}
diff --git a/test/CodeGen/ARM/pr3502.ll b/test/CodeGen/ARM/pr3502.ll
new file mode 100644
index 0000000..606d969
--- /dev/null
+++ b/test/CodeGen/ARM/pr3502.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=arm-none-linux-gnueabi
+;pr3502
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+ %struct.ArmPTD = type { i32 }
+ %struct.RegisterSave = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.SHARED_AREA = type { i32, %struct.SHARED_AREA*, %struct.SHARED_AREA*, %struct.SHARED_AREA*, %struct.ArmPTD, void (%struct.RegisterSave*)*, void (%struct.RegisterSave*)*, i32, [1024 x i8], i32, i32, i32, i32, i32, i8, i8, i16, i32, i32, i32, i32, [16 x i8], i32, i32, i32, i8, i8, i8, i32, i16, i32, i64, i32, i32, i32, i32, i32, i32, i8*, i32, [256 x i8], i32, i32, i32, [20 x i8], %struct.RegisterSave, { %struct.WorldSwitchV5 }, [4 x i32] }
+ %struct.WorldSwitchV5 = type { i32, i32, i32, i32, i32, i32, i32 }
+
+define void @SomeCall(i32 %num) nounwind {
+entry:
+ tail call void asm sideeffect "mcr p15, 0, $0, c7, c10, 4 \0A\09", "r,~{memory}"(i32 0) nounwind
+ tail call void asm sideeffect "mcr p15,0,$0,c7,c14,0", "r,~{memory}"(i32 0) nounwind
+ %0 = load %struct.SHARED_AREA** null, align 4 ; <%struct.SHARED_AREA*> [#uses=1]
+ %1 = ptrtoint %struct.SHARED_AREA* %0 to i32 ; <i32> [#uses=1]
+ %2 = lshr i32 %1, 20 ; <i32> [#uses=1]
+ %3 = tail call i32 @SetCurrEntry(i32 %2, i32 0) nounwind ; <i32> [#uses=0]
+ tail call void @ClearStuff(i32 0) nounwind
+ ret void
+}
+
+declare i32 @SetCurrEntry(i32, i32)
+
+declare void @ClearStuff(i32)
diff --git a/test/CodeGen/ARM/private.ll b/test/CodeGen/ARM/private.ll
new file mode 100644
index 0000000..fba56b4
--- /dev/null
+++ b/test/CodeGen/ARM/private.ll
@@ -0,0 +1,22 @@
+; Test to make sure that the 'private' is used correctly.
+;
+; RUN: llc < %s -mtriple=arm-linux-gnueabi > %t
+; RUN: grep .Lfoo: %t
+; RUN: egrep bl.*\.Lfoo %t
+; RUN: grep .Lbaz: %t
+; RUN: grep long.*\.Lbaz %t
+
+declare void @foo()
+
+define private void @foo() {
+ ret void
+}
+
+@baz = private global i32 4
+
+define i32 @bar() {
+ call void @foo()
+ %1 = load i32* @baz, align 4
+ ret i32 %1
+}
+
diff --git a/test/CodeGen/ARM/remat.ll b/test/CodeGen/ARM/remat.ll
new file mode 100644
index 0000000..367f782
--- /dev/null
+++ b/test/CodeGen/ARM/remat.ll
@@ -0,0 +1,65 @@
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -stats -info-output-file - | grep "Number of re-materialization"
+
+define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv, double %d1, double %d2) nounwind {
+entry:
+ br i1 undef, label %smvp.exit, label %bb.i3
+
+bb.i3: ; preds = %bb.i3, %bb134
+ br i1 undef, label %smvp.exit, label %bb.i3
+
+smvp.exit: ; preds = %bb.i3
+ %0 = fmul double %d1, 2.400000e-03 ; <double> [#uses=2]
+ br i1 undef, label %bb138.preheader, label %bb159
+
+bb138.preheader: ; preds = %smvp.exit
+ br label %bb138
+
+bb138: ; preds = %bb138, %bb138.preheader
+ br i1 undef, label %bb138, label %bb145.loopexit
+
+bb142: ; preds = %bb.nph218.bb.nph218.split_crit_edge, %phi0.exit
+ %1 = fmul double %d1, -1.200000e-03 ; <double> [#uses=1]
+ %2 = fadd double %d2, %1 ; <double> [#uses=1]
+ %3 = fmul double %2, %d2 ; <double> [#uses=1]
+ %4 = fsub double 0.000000e+00, %3 ; <double> [#uses=1]
+ br i1 %14, label %phi1.exit, label %bb.i35
+
+bb.i35: ; preds = %bb142
+ %5 = call arm_apcscc double @sin(double %15) nounwind readonly ; <double> [#uses=1]
+ %6 = fmul double %5, 0x4031740AFA84AD8A ; <double> [#uses=1]
+ %7 = fsub double 1.000000e+00, undef ; <double> [#uses=1]
+ %8 = fdiv double %7, 6.000000e-01 ; <double> [#uses=1]
+ br label %phi1.exit
+
+phi1.exit: ; preds = %bb.i35, %bb142
+ %.pn = phi double [ %6, %bb.i35 ], [ 0.000000e+00, %bb142 ] ; <double> [#uses=0]
+ %9 = phi double [ %8, %bb.i35 ], [ 0.000000e+00, %bb142 ] ; <double> [#uses=1]
+ %10 = fmul double undef, %9 ; <double> [#uses=0]
+ br i1 %14, label %phi0.exit, label %bb.i
+
+bb.i: ; preds = %phi1.exit
+ unreachable
+
+phi0.exit: ; preds = %phi1.exit
+ %11 = fsub double %4, undef ; <double> [#uses=1]
+ %12 = fadd double 0.000000e+00, %11 ; <double> [#uses=1]
+ store double %12, double* undef, align 4
+ br label %bb142
+
+bb145.loopexit: ; preds = %bb138
+ br i1 undef, label %bb.nph218.bb.nph218.split_crit_edge, label %bb159
+
+bb.nph218.bb.nph218.split_crit_edge: ; preds = %bb145.loopexit
+ %13 = fmul double %0, 0x401921FB54442D18 ; <double> [#uses=1]
+ %14 = fcmp ugt double %0, 6.000000e-01 ; <i1> [#uses=2]
+ %15 = fdiv double %13, 6.000000e-01 ; <double> [#uses=1]
+ br label %bb142
+
+bb159: ; preds = %bb145.loopexit, %smvp.exit, %bb134
+ unreachable
+
+bb166: ; preds = %bb127
+ unreachable
+}
+
+declare arm_apcscc double @sin(double) nounwind readonly
diff --git a/test/CodeGen/ARM/ret0.ll b/test/CodeGen/ARM/ret0.ll
new file mode 100644
index 0000000..5c312eb
--- /dev/null
+++ b/test/CodeGen/ARM/ret0.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=arm
+
+define i32 @test() {
+ ret i32 0
+}
diff --git a/test/CodeGen/ARM/ret_arg1.ll b/test/CodeGen/ARM/ret_arg1.ll
new file mode 100644
index 0000000..1ab947b
--- /dev/null
+++ b/test/CodeGen/ARM/ret_arg1.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=arm
+
+define i32 @test(i32 %a1) {
+ ret i32 %a1
+}
diff --git a/test/CodeGen/ARM/ret_arg2.ll b/test/CodeGen/ARM/ret_arg2.ll
new file mode 100644
index 0000000..84477d0
--- /dev/null
+++ b/test/CodeGen/ARM/ret_arg2.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=arm
+
+define i32 @test(i32 %a1, i32 %a2) {
+ ret i32 %a2
+}
+
diff --git a/test/CodeGen/ARM/ret_arg3.ll b/test/CodeGen/ARM/ret_arg3.ll
new file mode 100644
index 0000000..f7f9057
--- /dev/null
+++ b/test/CodeGen/ARM/ret_arg3.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=arm
+define i32 @test(i32 %a1, i32 %a2, i32 %a3) {
+ ret i32 %a3
+}
+
diff --git a/test/CodeGen/ARM/ret_arg4.ll b/test/CodeGen/ARM/ret_arg4.ll
new file mode 100644
index 0000000..f7b3e4a
--- /dev/null
+++ b/test/CodeGen/ARM/ret_arg4.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=arm
+
+define i32 @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
+ ret i32 %a4
+}
diff --git a/test/CodeGen/ARM/ret_arg5.ll b/test/CodeGen/ARM/ret_arg5.ll
new file mode 100644
index 0000000..c4f9fb5e
--- /dev/null
+++ b/test/CodeGen/ARM/ret_arg5.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=arm
+
+define i32 @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5) {
+ ret i32 %a5
+}
diff --git a/test/CodeGen/ARM/ret_f32_arg2.ll b/test/CodeGen/ARM/ret_f32_arg2.ll
new file mode 100644
index 0000000..2bafea6
--- /dev/null
+++ b/test/CodeGen/ARM/ret_f32_arg2.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2
+
+define float @test_f32(float %a1, float %a2) {
+ ret float %a2
+}
+
diff --git a/test/CodeGen/ARM/ret_f32_arg5.ll b/test/CodeGen/ARM/ret_f32_arg5.ll
new file mode 100644
index 0000000..c6ce60e
--- /dev/null
+++ b/test/CodeGen/ARM/ret_f32_arg5.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2
+
+define float @test_f32_arg5(float %a1, float %a2, float %a3, float %a4, float %a5) {
+ ret float %a5
+}
+
diff --git a/test/CodeGen/ARM/ret_f64_arg2.ll b/test/CodeGen/ARM/ret_f64_arg2.ll
new file mode 100644
index 0000000..386e85f
--- /dev/null
+++ b/test/CodeGen/ARM/ret_f64_arg2.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2
+
+define double @test_f64(double %a1, double %a2) {
+ ret double %a2
+}
+
diff --git a/test/CodeGen/ARM/ret_f64_arg_reg_split.ll b/test/CodeGen/ARM/ret_f64_arg_reg_split.ll
new file mode 100644
index 0000000..bdb0a60
--- /dev/null
+++ b/test/CodeGen/ARM/ret_f64_arg_reg_split.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=arm -mcpu=arm8 -mattr=+vfp2
+
+define double @test_double_arg_reg_split(i32 %a1, double %a2) {
+ ret double %a2
+}
+
diff --git a/test/CodeGen/ARM/ret_f64_arg_split.ll b/test/CodeGen/ARM/ret_f64_arg_split.ll
new file mode 100644
index 0000000..4f841a3
--- /dev/null
+++ b/test/CodeGen/ARM/ret_f64_arg_split.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2
+
+define double @test_double_arg_split(i64 %a1, i32 %a2, double %a3) {
+ ret double %a3
+}
+
diff --git a/test/CodeGen/ARM/ret_f64_arg_stack.ll b/test/CodeGen/ARM/ret_f64_arg_stack.ll
new file mode 100644
index 0000000..2144317
--- /dev/null
+++ b/test/CodeGen/ARM/ret_f64_arg_stack.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2
+
+define double @test_double_arg_stack(i64 %a1, i32 %a2, i32 %a3, double %a4) {
+ ret double %a4
+}
+
diff --git a/test/CodeGen/ARM/ret_i128_arg2.ll b/test/CodeGen/ARM/ret_i128_arg2.ll
new file mode 100644
index 0000000..908c34f
--- /dev/null
+++ b/test/CodeGen/ARM/ret_i128_arg2.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2
+
+define i128 @test_i128(i128 %a1, i128 %a2, i128 %a3) {
+ ret i128 %a3
+}
+
diff --git a/test/CodeGen/ARM/ret_i64_arg2.ll b/test/CodeGen/ARM/ret_i64_arg2.ll
new file mode 100644
index 0000000..b1a1024
--- /dev/null
+++ b/test/CodeGen/ARM/ret_i64_arg2.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2
+
+define i64 @test_i64(i64 %a1, i64 %a2) {
+ ret i64 %a2
+}
+
diff --git a/test/CodeGen/ARM/ret_i64_arg3.ll b/test/CodeGen/ARM/ret_i64_arg3.ll
new file mode 100644
index 0000000..ffc1d2f
--- /dev/null
+++ b/test/CodeGen/ARM/ret_i64_arg3.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2
+
+define i64 @test_i64_arg3(i64 %a1, i64 %a2, i64 %a3) {
+ ret i64 %a3
+}
+
diff --git a/test/CodeGen/ARM/ret_i64_arg_split.ll b/test/CodeGen/ARM/ret_i64_arg_split.ll
new file mode 100644
index 0000000..956bce5
--- /dev/null
+++ b/test/CodeGen/ARM/ret_i64_arg_split.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2
+
+define i64 @test_i64_arg_split(i64 %a1, i32 %a2, i64 %a3) {
+ ret i64 %a3
+}
+
diff --git a/test/CodeGen/ARM/ret_void.ll b/test/CodeGen/ARM/ret_void.ll
new file mode 100644
index 0000000..2b7ae05
--- /dev/null
+++ b/test/CodeGen/ARM/ret_void.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=arm
+
+define void @test() {
+ ret void
+}
+
diff --git a/test/CodeGen/ARM/rev.ll b/test/CodeGen/ARM/rev.ll
new file mode 100644
index 0000000..1c12268
--- /dev/null
+++ b/test/CodeGen/ARM/rev.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=arm -mattr=+v6 | grep rev16
+; RUN: llc < %s -march=arm -mattr=+v6 | grep revsh
+
+define i32 @test1(i32 %X) {
+ %tmp1 = lshr i32 %X, 8 ; <i32> [#uses=3]
+ %X15 = bitcast i32 %X to i32 ; <i32> [#uses=1]
+ %tmp4 = shl i32 %X15, 8 ; <i32> [#uses=2]
+ %tmp2 = and i32 %tmp1, 16711680 ; <i32> [#uses=1]
+ %tmp5 = and i32 %tmp4, -16777216 ; <i32> [#uses=1]
+ %tmp9 = and i32 %tmp1, 255 ; <i32> [#uses=1]
+ %tmp13 = and i32 %tmp4, 65280 ; <i32> [#uses=1]
+ %tmp6 = or i32 %tmp5, %tmp2 ; <i32> [#uses=1]
+ %tmp10 = or i32 %tmp6, %tmp13 ; <i32> [#uses=1]
+ %tmp14 = or i32 %tmp10, %tmp9 ; <i32> [#uses=1]
+ ret i32 %tmp14
+}
+
+define i32 @test2(i32 %X) {
+ %tmp1 = lshr i32 %X, 8 ; <i32> [#uses=1]
+ %tmp1.upgrd.1 = trunc i32 %tmp1 to i16 ; <i16> [#uses=1]
+ %tmp3 = trunc i32 %X to i16 ; <i16> [#uses=1]
+ %tmp2 = and i16 %tmp1.upgrd.1, 255 ; <i16> [#uses=1]
+ %tmp4 = shl i16 %tmp3, 8 ; <i16> [#uses=1]
+ %tmp5 = or i16 %tmp2, %tmp4 ; <i16> [#uses=1]
+ %tmp5.upgrd.2 = sext i16 %tmp5 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp5.upgrd.2
+}
diff --git a/test/CodeGen/ARM/sbfx.ll b/test/CodeGen/ARM/sbfx.ll
new file mode 100644
index 0000000..6f1d87d
--- /dev/null
+++ b/test/CodeGen/ARM/sbfx.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
+
+define i32 @f1(i32 %a) {
+entry:
+; CHECK: f1:
+; CHECK: sbfx r0, r0, #0, #20
+ %tmp = shl i32 %a, 12
+ %tmp2 = ashr i32 %tmp, 12
+ ret i32 %tmp2
+}
+
+define i32 @f2(i32 %a) {
+entry:
+; CHECK: f2:
+; CHECK: ubfx r0, r0, #0, #20
+ %tmp = shl i32 %a, 12
+ %tmp2 = lshr i32 %tmp, 12
+ ret i32 %tmp2
+}
+
+define i32 @f3(i32 %a) {
+entry:
+; CHECK: f3:
+; CHECK: sbfx r0, r0, #5, #3
+ %tmp = shl i32 %a, 24
+ %tmp2 = ashr i32 %tmp, 29
+ ret i32 %tmp2
+}
+
+define i32 @f4(i32 %a) {
+entry:
+; CHECK: f4:
+; CHECK: ubfx r0, r0, #5, #3
+ %tmp = shl i32 %a, 24
+ %tmp2 = lshr i32 %tmp, 29
+ ret i32 %tmp2
+}
+
+define i32 @f5(i32 %a) {
+entry:
+; CHECK: f5:
+; CHECK-NOT: sbfx
+; CHECK: bx
+ %tmp = shl i32 %a, 3
+ %tmp2 = ashr i32 %tmp, 1
+ ret i32 %tmp2
+}
diff --git a/test/CodeGen/ARM/section.ll b/test/CodeGen/ARM/section.ll
new file mode 100644
index 0000000..7a566d4
--- /dev/null
+++ b/test/CodeGen/ARM/section.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -mtriple=arm-linux | \
+; RUN: grep {__DTOR_END__:}
+; RUN: llc < %s -mtriple=arm-linux | \
+; RUN: grep {\\.section.\\.dtors,"aw",.progbits}
+
+@__DTOR_END__ = internal global [1 x i32] zeroinitializer, section ".dtors" ; <[1 x i32]*> [#uses=0]
+
diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll
new file mode 100644
index 0000000..07edc91
--- /dev/null
+++ b/test/CodeGen/ARM/select-imm.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s --check-prefix=T2
+
+define arm_apcscc i32 @t1(i32 %c) nounwind readnone {
+entry:
+; ARM: t1:
+; ARM: mov r1, #101
+; ARM: orr r1, r1, #1, 24
+; ARM: movgt r0, #123
+
+; T2: t1:
+; T2: movw r0, #357
+; T2: movgt r0, #123
+
+ %0 = icmp sgt i32 %c, 1
+ %1 = select i1 %0, i32 123, i32 357
+ ret i32 %1
+}
+
+define arm_apcscc i32 @t2(i32 %c) nounwind readnone {
+entry:
+; ARM: t2:
+; ARM: mov r1, #101
+; ARM: orr r1, r1, #1, 24
+; ARM: movle r0, #123
+
+; T2: t2:
+; T2: movw r0, #357
+; T2: movle r0, #123
+
+ %0 = icmp sgt i32 %c, 1
+ %1 = select i1 %0, i32 357, i32 123
+ ret i32 %1
+}
+
+define arm_apcscc i32 @t3(i32 %a) nounwind readnone {
+entry:
+; ARM: t3:
+; ARM: mov r0, #0
+; ARM: moveq r0, #1
+
+; T2: t3:
+; T2: mov r0, #0
+; T2: moveq r0, #1
+ %0 = icmp eq i32 %a, 160
+ %1 = zext i1 %0 to i32
+ ret i32 %1
+}
diff --git a/test/CodeGen/ARM/select.ll b/test/CodeGen/ARM/select.ll
new file mode 100644
index 0000000..29c55c6
--- /dev/null
+++ b/test/CodeGen/ARM/select.ll
@@ -0,0 +1,67 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s --check-prefix=CHECK-VFP
+
+define i32 @f1(i32 %a.s) {
+;CHECK: f1:
+;CHECK: moveq
+entry:
+ %tmp = icmp eq i32 %a.s, 4
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f2(i32 %a.s) {
+;CHECK: f2:
+;CHECK: movgt
+entry:
+ %tmp = icmp sgt i32 %a.s, 4
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f3(i32 %a.s, i32 %b.s) {
+;CHECK: f3:
+;CHECK: movlt
+entry:
+ %tmp = icmp slt i32 %a.s, %b.s
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f4(i32 %a.s, i32 %b.s) {
+;CHECK: f4:
+;CHECK: movle
+entry:
+ %tmp = icmp sle i32 %a.s, %b.s
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f5(i32 %a.u, i32 %b.u) {
+;CHECK: f5:
+;CHECK: movls
+entry:
+ %tmp = icmp ule i32 %a.u, %b.u
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f6(i32 %a.u, i32 %b.u) {
+;CHECK: f6:
+;CHECK: movhi
+entry:
+ %tmp = icmp ugt i32 %a.u, %b.u
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define double @f7(double %a, double %b) {
+;CHECK: f7:
+;CHECK: movlt
+;CHECK: movlt
+;CHECK-VFP: f7:
+;CHECK-VFP: vmovmi
+ %tmp = fcmp olt double %a, 1.234e+00
+ %tmp1 = select i1 %tmp, double -1.000e+00, double %b
+ ret double %tmp1
+}
diff --git a/test/CodeGen/ARM/select_xform.ll b/test/CodeGen/ARM/select_xform.ll
new file mode 100644
index 0000000..7fd91ce
--- /dev/null
+++ b/test/CodeGen/ARM/select_xform.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=arm | grep mov | count 2
+
+define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
+ %tmp1 = icmp sgt i32 %c, 10
+ %tmp2 = select i1 %tmp1, i32 0, i32 2147483647
+ %tmp3 = add i32 %tmp2, %b
+ ret i32 %tmp3
+}
+
+define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
+ %tmp1 = icmp sgt i32 %c, 10
+ %tmp2 = select i1 %tmp1, i32 0, i32 10
+ %tmp3 = sub i32 %b, %tmp2
+ ret i32 %tmp3
+}
diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll
new file mode 100644
index 0000000..2bbe9fd
--- /dev/null
+++ b/test/CodeGen/ARM/shifter_operand.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=arm | grep add | grep lsl
+; RUN: llc < %s -march=arm | grep bic | grep asr
+
+
+define i32 @test1(i32 %X, i32 %Y, i8 %sh) {
+ %shift.upgrd.1 = zext i8 %sh to i32 ; <i32> [#uses=1]
+ %A = shl i32 %Y, %shift.upgrd.1 ; <i32> [#uses=1]
+ %B = add i32 %X, %A ; <i32> [#uses=1]
+ ret i32 %B
+}
+
+define i32 @test2(i32 %X, i32 %Y, i8 %sh) {
+ %shift.upgrd.2 = zext i8 %sh to i32 ; <i32> [#uses=1]
+ %A = ashr i32 %Y, %shift.upgrd.2 ; <i32> [#uses=1]
+ %B = xor i32 %A, -1 ; <i32> [#uses=1]
+ %C = and i32 %X, %B ; <i32> [#uses=1]
+ ret i32 %C
+}
diff --git a/test/CodeGen/ARM/smul.ll b/test/CodeGen/ARM/smul.ll
new file mode 100644
index 0000000..b7ab2e7
--- /dev/null
+++ b/test/CodeGen/ARM/smul.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm -mattr=+v5TE
+; RUN: llc < %s -march=arm -mattr=+v5TE | \
+; RUN: grep smulbt | count 1
+; RUN: llc < %s -march=arm -mattr=+v5TE | \
+; RUN: grep smultt | count 1
+; RUN: llc < %s -march=arm -mattr=+v5TE | \
+; RUN: grep smlabt | count 1
+
+@x = weak global i16 0 ; <i16*> [#uses=1]
+@y = weak global i16 0 ; <i16*> [#uses=0]
+
+define i32 @f1(i32 %y) {
+ %tmp = load i16* @x ; <i16> [#uses=1]
+ %tmp1 = add i16 %tmp, 2 ; <i16> [#uses=1]
+ %tmp2 = sext i16 %tmp1 to i32 ; <i32> [#uses=1]
+ %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1]
+ %tmp4 = mul i32 %tmp2, %tmp3 ; <i32> [#uses=1]
+ ret i32 %tmp4
+}
+
+define i32 @f2(i32 %x, i32 %y) {
+ %tmp1 = ashr i32 %x, 16 ; <i32> [#uses=1]
+ %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1]
+ %tmp4 = mul i32 %tmp3, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp4
+}
+
+define i32 @f3(i32 %a, i16 %x, i32 %y) {
+ %tmp = sext i16 %x to i32 ; <i32> [#uses=1]
+ %tmp2 = ashr i32 %y, 16 ; <i32> [#uses=1]
+ %tmp3 = mul i32 %tmp2, %tmp ; <i32> [#uses=1]
+ %tmp5 = add i32 %tmp3, %a ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll
new file mode 100644
index 0000000..5ad7ecc
--- /dev/null
+++ b/test/CodeGen/ARM/spill-q.ll
@@ -0,0 +1,58 @@
+; RUN: llc < %s -mtriple=armv7-elf -mattr=+neon | FileCheck %s
+; PR4789
+
+%bar = type { float, float, float }
+%baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 }
+%foo = type { <4 x float> }
+%quux = type { i32 (...)**, %baz*, i32 }
+%quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo }
+
+declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly
+
+define arm_apcscc void @aaa(%quuz* %this, i8* %block) {
+; CHECK: aaa:
+; CHECK: bic sp, sp, #15
+; CHECK: vst1.64 {{.*}}sp, :128
+; CHECK: vld1.64 {{.*}}sp, :128
+entry:
+ %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1]
+ store float 6.300000e+01, float* undef, align 4
+ %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1]
+ store float 0.000000e+00, float* undef, align 4
+ %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1]
+ %val173 = load <4 x float>* undef ; <<4 x float>> [#uses=1]
+ br label %bb4
+
+bb4: ; preds = %bb193, %entry
+ %besterror.0.2264 = phi <4 x float> [ undef, %entry ], [ %besterror.0.0, %bb193 ] ; <<4 x float>> [#uses=2]
+ %part0.0.0261 = phi <4 x float> [ zeroinitializer, %entry ], [ %23, %bb193 ] ; <<4 x float>> [#uses=2]
+ %3 = fmul <4 x float> zeroinitializer, %0 ; <<4 x float>> [#uses=2]
+ %4 = fadd <4 x float> %3, %part0.0.0261 ; <<4 x float>> [#uses=1]
+ %5 = shufflevector <4 x float> %3, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
+ %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1]
+ %7 = fmul <4 x float> %1, undef ; <<4 x float>> [#uses=1]
+ %8 = fadd <4 x float> %7, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> ; <<4 x float>> [#uses=1]
+ %9 = fptosi <4 x float> %8 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %10 = sitofp <4 x i32> %9 to <4 x float> ; <<4 x float>> [#uses=1]
+ %11 = fmul <4 x float> %10, %2 ; <<4 x float>> [#uses=1]
+ %12 = fmul <4 x float> undef, %6 ; <<4 x float>> [#uses=1]
+ %13 = fmul <4 x float> %11, %4 ; <<4 x float>> [#uses=1]
+ %14 = fsub <4 x float> %12, %13 ; <<4 x float>> [#uses=1]
+ %15 = fsub <4 x float> %14, undef ; <<4 x float>> [#uses=1]
+ %16 = fmul <4 x float> %15, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00> ; <<4 x float>> [#uses=1]
+ %17 = fadd <4 x float> %16, undef ; <<4 x float>> [#uses=1]
+ %18 = fmul <4 x float> %17, %val173 ; <<4 x float>> [#uses=1]
+ %19 = shufflevector <4 x float> %18, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
+ %20 = shufflevector <2 x float> %19, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %21 = fadd <4 x float> zeroinitializer, %20 ; <<4 x float>> [#uses=2]
+ %22 = fcmp ogt <4 x float> %besterror.0.2264, %21 ; <<4 x i1>> [#uses=0]
+ br i1 undef, label %bb193, label %bb186
+
+bb186: ; preds = %bb4
+ br label %bb193
+
+bb193: ; preds = %bb186, %bb4
+ %besterror.0.0 = phi <4 x float> [ %21, %bb186 ], [ %besterror.0.2264, %bb4 ] ; <<4 x float>> [#uses=1]
+ %23 = fadd <4 x float> %part0.0.0261, zeroinitializer ; <<4 x float>> [#uses=1]
+ br label %bb4
+}
diff --git a/test/CodeGen/ARM/stack-frame.ll b/test/CodeGen/ARM/stack-frame.ll
new file mode 100644
index 0000000..1dd57dd
--- /dev/null
+++ b/test/CodeGen/ARM/stack-frame.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm | grep add | count 1
+
+define void @f1() {
+ %c = alloca i8, align 1
+ ret void
+}
+
+define i32 @f2() {
+ ret i32 1
+}
+
+
diff --git a/test/CodeGen/ARM/stm.ll b/test/CodeGen/ARM/stm.ll
new file mode 100644
index 0000000..22a7ecb
--- /dev/null
+++ b/test/CodeGen/ARM/stm.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | grep stm | count 2
+
+@"\01LC" = internal constant [32 x i8] c"Boolean Not: %d %d %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[32 x i8]*> [#uses=1]
+@"\01LC1" = internal constant [26 x i8] c"Bitwise Not: %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[26 x i8]*> [#uses=1]
+
+declare i32 @printf(i8* nocapture, ...) nounwind
+
+define i32 @main() nounwind {
+entry:
+ %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([26 x i8]* @"\01LC1", i32 0, i32 0), i32 -2, i32 -3, i32 2, i32 -6) nounwind ; <i32> [#uses=0]
+ %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([32 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 1, i32 0, i32 1, i32 0, i32 1) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/ARM/str_post.ll b/test/CodeGen/ARM/str_post.ll
new file mode 100644
index 0000000..97916f1
--- /dev/null
+++ b/test/CodeGen/ARM/str_post.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=arm | FileCheck %s
+
+define i16 @test1(i32* %X, i16* %A) {
+; CHECK: test1:
+; CHECK: strh {{.*}}[{{.*}}], #-4
+ %Y = load i32* %X ; <i32> [#uses=1]
+ %tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1]
+ store i16 %tmp1, i16* %A
+ %tmp2 = ptrtoint i16* %A to i16 ; <i16> [#uses=1]
+ %tmp3 = sub i16 %tmp2, 4 ; <i16> [#uses=1]
+ ret i16 %tmp3
+}
+
+define i32 @test2(i32* %X, i32* %A) {
+; CHECK: test2:
+; CHECK: str {{.*}}[{{.*}}],
+ %Y = load i32* %X ; <i32> [#uses=1]
+ store i32 %Y, i32* %A
+ %tmp1 = ptrtoint i32* %A to i32 ; <i32> [#uses=1]
+ %tmp2 = sub i32 %tmp1, 4 ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
diff --git a/test/CodeGen/ARM/str_pre-2.ll b/test/CodeGen/ARM/str_pre-2.ll
new file mode 100644
index 0000000..f8d3df2
--- /dev/null
+++ b/test/CodeGen/ARM/str_pre-2.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=arm-linux-gnu | grep {str.*\\!}
+; RUN: llc < %s -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #+4}
+
+@b = external global i64*
+
+define i64 @t(i64 %a) nounwind readonly {
+entry:
+ %0 = load i64** @b, align 4
+ %1 = load i64* %0, align 4
+ %2 = mul i64 %1, %a
+ ret i64 %2
+}
diff --git a/test/CodeGen/ARM/str_pre.ll b/test/CodeGen/ARM/str_pre.ll
new file mode 100644
index 0000000..e56e3f2
--- /dev/null
+++ b/test/CodeGen/ARM/str_pre.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=arm | \
+; RUN: grep {str.*\\!} | count 2
+
+define void @test1(i32* %X, i32* %A, i32** %dest) {
+ %B = load i32* %A ; <i32> [#uses=1]
+ %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2]
+ store i32 %B, i32* %Y
+ store i32* %Y, i32** %dest
+ ret void
+}
+
+define i16* @test2(i16* %X, i32* %A) {
+ %B = load i32* %A ; <i32> [#uses=1]
+ %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2]
+ %tmp = trunc i32 %B to i16 ; <i16> [#uses=1]
+ store i16 %tmp, i16* %Y
+ ret i16* %Y
+}
diff --git a/test/CodeGen/ARM/str_trunc.ll b/test/CodeGen/ARM/str_trunc.ll
new file mode 100644
index 0000000..2f1166b
--- /dev/null
+++ b/test/CodeGen/ARM/str_trunc.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=arm | \
+; RUN: grep strb | count 1
+; RUN: llc < %s -march=arm | \
+; RUN: grep strh | count 1
+
+define void @test1(i32 %v, i16* %ptr) {
+ %tmp = trunc i32 %v to i16 ; <i16> [#uses=1]
+ store i16 %tmp, i16* %ptr
+ ret void
+}
+
+define void @test2(i32 %v, i8* %ptr) {
+ %tmp = trunc i32 %v to i8 ; <i8> [#uses=1]
+ store i8 %tmp, i8* %ptr
+ ret void
+}
diff --git a/test/CodeGen/ARM/sxt_rot.ll b/test/CodeGen/ARM/sxt_rot.ll
new file mode 100644
index 0000000..4752f17
--- /dev/null
+++ b/test/CodeGen/ARM/sxt_rot.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=arm -mattr=+v6 | \
+; RUN: grep sxtb | count 2
+; RUN: llc < %s -march=arm -mattr=+v6 | \
+; RUN: grep sxtb | grep ror | count 1
+; RUN: llc < %s -march=arm -mattr=+v6 | \
+; RUN: grep sxtab | count 1
+
+define i32 @test0(i8 %A) {
+ %B = sext i8 %A to i32
+ ret i32 %B
+}
+
+define i8 @test1(i32 %A) signext {
+ %B = lshr i32 %A, 8
+ %C = shl i32 %A, 24
+ %D = or i32 %B, %C
+ %E = trunc i32 %D to i8
+ ret i8 %E
+}
+
+define i32 @test2(i32 %A, i32 %X) signext {
+ %B = lshr i32 %A, 8
+ %C = shl i32 %A, 24
+ %D = or i32 %B, %C
+ %E = trunc i32 %D to i8
+ %F = sext i8 %E to i32
+ %G = add i32 %F, %X
+ ret i32 %G
+}
diff --git a/test/CodeGen/ARM/t2-imm.ll b/test/CodeGen/ARM/t2-imm.ll
new file mode 100644
index 0000000..848a4df
--- /dev/null
+++ b/test/CodeGen/ARM/t2-imm.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s
+
+define i32 @f6(i32 %a) {
+; CHECK:f6
+; CHECK: movw r0, #:lower16:65537123
+; CHECK: movt r0, #:upper16:65537123
+ %tmp = add i32 0, 65537123
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/ARM/tail-opts.ll b/test/CodeGen/ARM/tail-opts.ll
new file mode 100644
index 0000000..17c8bae
--- /dev/null
+++ b/test/CodeGen/ARM/tail-opts.ll
@@ -0,0 +1,64 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 -asm-verbose=false | FileCheck %s
+
+declare void @bar(i32)
+declare void @car(i32)
+declare void @dar(i32)
+declare void @ear(i32)
+declare void @far(i32)
+declare i1 @qux()
+
+@GHJK = global i32 0
+
+declare i8* @choose(i8*, i8*)
+
+; BranchFolding should tail-duplicate the indirect jump to avoid
+; redundant branching.
+
+; CHECK: tail_duplicate_me:
+; CHECK: qux
+; CHECK: qux
+; CHECK: ldr r{{.}}, LCPI
+; CHECK: str r
+; CHECK-NEXT: bx r
+; CHECK: ldr r{{.}}, LCPI
+; CHECK: str r
+; CHECK-NEXT: bx r
+; CHECK: ldr r{{.}}, LCPI
+; CHECK: str r
+; CHECK-NEXT: bx r
+
+define void @tail_duplicate_me() nounwind {
+entry:
+ %a = call i1 @qux()
+ %c = call i8* @choose(i8* blockaddress(@tail_duplicate_me, %return),
+ i8* blockaddress(@tail_duplicate_me, %altret))
+ br i1 %a, label %A, label %next
+next:
+ %b = call i1 @qux()
+ br i1 %b, label %B, label %C
+
+A:
+ call void @bar(i32 0)
+ store i32 0, i32* @GHJK
+ br label %M
+
+B:
+ call void @car(i32 1)
+ store i32 0, i32* @GHJK
+ br label %M
+
+C:
+ call void @dar(i32 2)
+ store i32 0, i32* @GHJK
+ br label %M
+
+M:
+ indirectbr i8* %c, [label %return, label %altret]
+
+return:
+ call void @ear(i32 1000)
+ ret void
+altret:
+ call void @far(i32 1001)
+ ret void
+}
diff --git a/test/CodeGen/ARM/thread_pointer.ll b/test/CodeGen/ARM/thread_pointer.ll
new file mode 100644
index 0000000..3143387
--- /dev/null
+++ b/test/CodeGen/ARM/thread_pointer.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \
+; RUN: grep {__aeabi_read_tp}
+
+define i8* @test() {
+entry:
+ %tmp1 = call i8* @llvm.arm.thread.pointer( ) ; <i8*> [#uses=0]
+ ret i8* %tmp1
+}
+
+declare i8* @llvm.arm.thread.pointer()
diff --git a/test/CodeGen/ARM/tls1.ll b/test/CodeGen/ARM/tls1.ll
new file mode 100644
index 0000000..1087094
--- /dev/null
+++ b/test/CodeGen/ARM/tls1.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \
+; RUN: grep {i(tpoff)}
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \
+; RUN: grep {__aeabi_read_tp}
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \
+; RUN: -relocation-model=pic | grep {__tls_get_addr}
+
+
+@i = thread_local global i32 15 ; <i32*> [#uses=2]
+
+define i32 @f() {
+entry:
+ %tmp1 = load i32* @i ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32* @g() {
+entry:
+ ret i32* @i
+}
diff --git a/test/CodeGen/ARM/tls2.ll b/test/CodeGen/ARM/tls2.ll
new file mode 100644
index 0000000..d932f90
--- /dev/null
+++ b/test/CodeGen/ARM/tls2.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \
+; RUN: | FileCheck %s -check-prefix=CHECK-NONPIC
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \
+; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC
+
+@i = external thread_local global i32 ; <i32*> [#uses=2]
+
+define i32 @f() {
+; CHECK-NONPIC: f:
+; CHECK-NONPIC: ldr {{r.}}, [pc, +{{r.}}]
+; CHECK-NONPIC: i(gottpoff)
+; CHECK-PIC: f:
+; CHECK-PIC: __tls_get_addr
+entry:
+ %tmp1 = load i32* @i ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32* @g() {
+; CHECK-NONPIC: g:
+; CHECK-NONPIC: ldr {{r.}}, [pc, +{{r.}}]
+; CHECK-NONPIC: i(gottpoff)
+; CHECK-PIC: g:
+; CHECK-PIC: __tls_get_addr
+entry:
+ ret i32* @i
+}
diff --git a/test/CodeGen/ARM/tls3.ll b/test/CodeGen/ARM/tls3.ll
new file mode 100644
index 0000000..df7a4ca
--- /dev/null
+++ b/test/CodeGen/ARM/tls3.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \
+; RUN: grep {tbss}
+
+%struct.anon = type { i32, i32 }
+@teste = internal thread_local global %struct.anon zeroinitializer ; <%struct.anon*> [#uses=1]
+
+define i32 @main() {
+entry:
+ %tmp2 = load i32* getelementptr (%struct.anon* @teste, i32 0, i32 0), align 8 ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
diff --git a/test/CodeGen/ARM/trunc_ldr.ll b/test/CodeGen/ARM/trunc_ldr.ll
new file mode 100644
index 0000000..3033c2b
--- /dev/null
+++ b/test/CodeGen/ARM/trunc_ldr.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=arm | grep ldrb.*7 | count 1
+; RUN: llc < %s -march=arm | grep ldrsb.*7 | count 1
+
+ %struct.A = type { i8, i8, i8, i8, i16, i8, i8, %struct.B** }
+ %struct.B = type { float, float, i32, i32, i32, [0 x i8] }
+
+define i8 @f1(%struct.A* %d) {
+ %tmp2 = getelementptr %struct.A* %d, i32 0, i32 4
+ %tmp23 = bitcast i16* %tmp2 to i32*
+ %tmp4 = load i32* %tmp23
+ %tmp512 = lshr i32 %tmp4, 24
+ %tmp56 = trunc i32 %tmp512 to i8
+ ret i8 %tmp56
+}
+
+define i32 @f2(%struct.A* %d) {
+ %tmp2 = getelementptr %struct.A* %d, i32 0, i32 4
+ %tmp23 = bitcast i16* %tmp2 to i32*
+ %tmp4 = load i32* %tmp23
+ %tmp512 = lshr i32 %tmp4, 24
+ %tmp56 = trunc i32 %tmp512 to i8
+ %tmp57 = sext i8 %tmp56 to i32
+ ret i32 %tmp57
+}
diff --git a/test/CodeGen/ARM/truncstore-dag-combine.ll b/test/CodeGen/ARM/truncstore-dag-combine.ll
new file mode 100644
index 0000000..2da08b6
--- /dev/null
+++ b/test/CodeGen/ARM/truncstore-dag-combine.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=arm | not grep orr
+; RUN: llc < %s -march=arm | not grep mov
+
+define void @bar(i8* %P, i16* %Q) {
+entry:
+ %P1 = bitcast i8* %P to i16* ; <i16*> [#uses=1]
+ %tmp = load i16* %Q, align 1 ; <i16> [#uses=1]
+ store i16 %tmp, i16* %P1, align 1
+ ret void
+}
+
+define void @foo(i8* %P, i32* %Q) {
+entry:
+ %P1 = bitcast i8* %P to i32* ; <i32*> [#uses=1]
+ %tmp = load i32* %Q, align 1 ; <i32> [#uses=1]
+ store i32 %tmp, i32* %P1, align 1
+ ret void
+}
diff --git a/test/CodeGen/ARM/tst_teq.ll b/test/CodeGen/ARM/tst_teq.ll
new file mode 100644
index 0000000..c83111e
--- /dev/null
+++ b/test/CodeGen/ARM/tst_teq.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=arm | grep tst
+; RUN: llc < %s -march=arm | grep teq
+
+define i32 @f(i32 %a) {
+entry:
+ %tmp2 = and i32 %a, 255 ; <i32> [#uses=1]
+ icmp eq i32 %tmp2, 0 ; <i1>:0 [#uses=1]
+ %retval = select i1 %0, i32 20, i32 10 ; <i32> [#uses=1]
+ ret i32 %retval
+}
+
+define i32 @g(i32 %a) {
+entry:
+ %tmp2 = xor i32 %a, 255
+ icmp eq i32 %tmp2, 0 ; <i1>:0 [#uses=1]
+ %retval = select i1 %0, i32 20, i32 10 ; <i32> [#uses=1]
+ ret i32 %retval
+}
diff --git a/test/CodeGen/ARM/uint64tof64.ll b/test/CodeGen/ARM/uint64tof64.ll
new file mode 100644
index 0000000..32eb225
--- /dev/null
+++ b/test/CodeGen/ARM/uint64tof64.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+vfp2
+
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+@"\01LC10" = external constant [54 x i8] ; <[54 x i8]*> [#uses=1]
+
+define fastcc void @t() {
+entry:
+ %0 = load i64* null, align 4 ; <i64> [#uses=1]
+ %1 = uitofp i64 %0 to double ; <double> [#uses=1]
+ %2 = fdiv double 0.000000e+00, %1 ; <double> [#uses=1]
+ %3 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* null, i8* getelementptr ([54 x i8]* @"\01LC10", i32 0, i32 0), i64 0, double %2) ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @fprintf(%struct.FILE*, i8*, ...)
diff --git a/test/CodeGen/ARM/unaligned_load_store.ll b/test/CodeGen/ARM/unaligned_load_store.ll
new file mode 100644
index 0000000..a4494f3
--- /dev/null
+++ b/test/CodeGen/ARM/unaligned_load_store.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=GENERIC
+; RUN: llc < %s -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=DARWIN_V6
+; RUN: llc < %s -mtriple=armv6-linux | FileCheck %s -check-prefix=GENERIC
+
+; rdar://7113725
+
+define arm_apcscc void @t(i8* nocapture %a, i8* nocapture %b) nounwind {
+entry:
+; GENERIC: t:
+; GENERIC: ldrb r2
+; GENERIC: ldrb r3
+; GENERIC: ldrb r12
+; GENERIC: ldrb r1
+; GENERIC: strb r1
+; GENERIC: strb r12
+; GENERIC: strb r3
+; GENERIC: strb r2
+
+; DARWIN_V6: t:
+; DARWIN_V6: ldr r1
+; DARWIN_V6: str r1
+
+ %__src1.i = bitcast i8* %b to i32* ; <i32*> [#uses=1]
+ %__dest2.i = bitcast i8* %a to i32* ; <i32*> [#uses=1]
+ %tmp.i = load i32* %__src1.i, align 1 ; <i32> [#uses=1]
+ store i32 %tmp.i, i32* %__dest2.i, align 1
+ ret void
+}
diff --git a/test/CodeGen/ARM/unord.ll b/test/CodeGen/ARM/unord.ll
new file mode 100644
index 0000000..bd28034
--- /dev/null
+++ b/test/CodeGen/ARM/unord.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=arm | grep movne | count 1
+; RUN: llc < %s -march=arm | grep moveq | count 1
+
+define i32 @f1(float %X, float %Y) {
+ %tmp = fcmp uno float %X, %Y
+ %retval = select i1 %tmp, i32 1, i32 -1
+ ret i32 %retval
+}
+
+define i32 @f2(float %X, float %Y) {
+ %tmp = fcmp ord float %X, %Y
+ %retval = select i1 %tmp, i32 1, i32 -1
+ ret i32 %retval
+}
diff --git a/test/CodeGen/ARM/uxt_rot.ll b/test/CodeGen/ARM/uxt_rot.ll
new file mode 100644
index 0000000..6307795
--- /dev/null
+++ b/test/CodeGen/ARM/uxt_rot.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=arm -mattr=+v6 | grep uxtb | count 1
+; RUN: llc < %s -march=arm -mattr=+v6 | grep uxtab | count 1
+; RUN: llc < %s -march=arm -mattr=+v6 | grep uxth | count 1
+
+define i8 @test1(i32 %A.u) zeroext {
+ %B.u = trunc i32 %A.u to i8
+ ret i8 %B.u
+}
+
+define i32 @test2(i32 %A.u, i32 %B.u) zeroext {
+ %C.u = trunc i32 %B.u to i8
+ %D.u = zext i8 %C.u to i32
+ %E.u = add i32 %A.u, %D.u
+ ret i32 %E.u
+}
+
+define i32 @test3(i32 %A.u) zeroext {
+ %B.u = lshr i32 %A.u, 8
+ %C.u = shl i32 %A.u, 24
+ %D.u = or i32 %B.u, %C.u
+ %E.u = trunc i32 %D.u to i16
+ %F.u = zext i16 %E.u to i32
+ ret i32 %F.u
+}
diff --git a/test/CodeGen/ARM/uxtb.ll b/test/CodeGen/ARM/uxtb.ll
new file mode 100644
index 0000000..9d6e4bd
--- /dev/null
+++ b/test/CodeGen/ARM/uxtb.ll
@@ -0,0 +1,74 @@
+; RUN: llc < %s -mtriple=armv6-apple-darwin | \
+; RUN: grep uxt | count 10
+
+define i32 @test1(i32 %x) {
+ %tmp1 = and i32 %x, 16711935 ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32 @test2(i32 %x) {
+ %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
+
+define i32 @test3(i32 %x) {
+ %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
+
+define i32 @test4(i32 %x) {
+ %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
+ %tmp6 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+define i32 @test5(i32 %x) {
+ %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
+
+define i32 @test6(i32 %x) {
+ %tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1]
+ %tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
+ %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
+ %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+define i32 @test7(i32 %x) {
+ %tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1]
+ %tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
+ %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
+ %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+define i32 @test8(i32 %x) {
+ %tmp1 = shl i32 %x, 8 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 16711680 ; <i32> [#uses=1]
+ %tmp5 = lshr i32 %x, 24 ; <i32> [#uses=1]
+ %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+define i32 @test9(i32 %x) {
+ %tmp1 = lshr i32 %x, 24 ; <i32> [#uses=1]
+ %tmp4 = shl i32 %x, 8 ; <i32> [#uses=1]
+ %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
+ %tmp6 = or i32 %tmp5, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+define i32 @test10(i32 %p0) {
+ %tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2]
+ %tmp4 = lshr i32 %tmp2, 5 ; <i32> [#uses=1]
+ %tmp5 = and i32 %tmp4, 458759 ; <i32> [#uses=1]
+ %tmp7 = or i32 %tmp5, %tmp2 ; <i32> [#uses=1]
+ ret i32 %tmp7
+}
diff --git a/test/CodeGen/ARM/vaba.ll b/test/CodeGen/ARM/vaba.ll
new file mode 100644
index 0000000..e2dca46
--- /dev/null
+++ b/test/CodeGen/ARM/vaba.ll
@@ -0,0 +1,205 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+;CHECK: vabas8:
+;CHECK: vaba.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = load <8 x i8>* %C
+ %tmp4 = call <8 x i8> @llvm.arm.neon.vabas.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+;CHECK: vabas16:
+;CHECK: vaba.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i16>* %C
+ %tmp4 = call <4 x i16> @llvm.arm.neon.vabas.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+;CHECK: vabas32:
+;CHECK: vaba.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i32>* %C
+ %tmp4 = call <2 x i32> @llvm.arm.neon.vabas.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
+ ret <2 x i32> %tmp4
+}
+
+define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+;CHECK: vabau8:
+;CHECK: vaba.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = load <8 x i8>* %C
+ %tmp4 = call <8 x i8> @llvm.arm.neon.vabau.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+;CHECK: vabau16:
+;CHECK: vaba.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i16>* %C
+ %tmp4 = call <4 x i16> @llvm.arm.neon.vabau.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+;CHECK: vabau32:
+;CHECK: vaba.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i32>* %C
+ %tmp4 = call <2 x i32> @llvm.arm.neon.vabau.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
+ ret <2 x i32> %tmp4
+}
+
+define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
+;CHECK: vabaQs8:
+;CHECK: vaba.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = load <16 x i8>* %C
+ %tmp4 = call <16 x i8> @llvm.arm.neon.vabas.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> %tmp3)
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
+;CHECK: vabaQs16:
+;CHECK: vaba.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = load <8 x i16>* %C
+ %tmp4 = call <8 x i16> @llvm.arm.neon.vabas.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> %tmp3)
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
+;CHECK: vabaQs32:
+;CHECK: vaba.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = call <4 x i32> @llvm.arm.neon.vabas.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
+;CHECK: vabaQu8:
+;CHECK: vaba.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = load <16 x i8>* %C
+ %tmp4 = call <16 x i8> @llvm.arm.neon.vabau.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> %tmp3)
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
+;CHECK: vabaQu16:
+;CHECK: vaba.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = load <8 x i16>* %C
+ %tmp4 = call <8 x i16> @llvm.arm.neon.vabau.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> %tmp3)
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vabaQu32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
+;CHECK: vabaQu32:
+;CHECK: vaba.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = call <4 x i32> @llvm.arm.neon.vabau.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+declare <8 x i8> @llvm.arm.neon.vabas.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vabas.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vabas.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vabau.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vabau.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vabau.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vabas.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vabas.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vabas.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vabau.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vabau.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vabau.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+;CHECK: vabals8:
+;CHECK: vabal.s8
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = load <8 x i8>* %C
+ %tmp4 = call <8 x i16> @llvm.arm.neon.vabals.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+;CHECK: vabals16:
+;CHECK: vabal.s16
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i16>* %C
+ %tmp4 = call <4 x i32> @llvm.arm.neon.vabals.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+;CHECK: vabals32:
+;CHECK: vabal.s32
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i32>* %C
+ %tmp4 = call <2 x i64> @llvm.arm.neon.vabals.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
+ ret <2 x i64> %tmp4
+}
+
+define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+;CHECK: vabalu8:
+;CHECK: vabal.u8
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = load <8 x i8>* %C
+ %tmp4 = call <8 x i16> @llvm.arm.neon.vabalu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+;CHECK: vabalu16:
+;CHECK: vabal.u16
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i16>* %C
+ %tmp4 = call <4 x i32> @llvm.arm.neon.vabalu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vabalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+;CHECK: vabalu32:
+;CHECK: vabal.u32
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i32>* %C
+ %tmp4 = call <2 x i64> @llvm.arm.neon.vabalu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
+ ret <2 x i64> %tmp4
+}
+
+declare <8 x i16> @llvm.arm.neon.vabals.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vabals.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vabals.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vabalu.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vabalu.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vabalu.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vabd.ll b/test/CodeGen/ARM/vabd.ll
new file mode 100644
index 0000000..2b45393
--- /dev/null
+++ b/test/CodeGen/ARM/vabd.ll
@@ -0,0 +1,209 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vabds8:
+;CHECK: vabd.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vabds16:
+;CHECK: vabd.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vabds32:
+;CHECK: vabd.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vabdu8:
+;CHECK: vabd.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vabdu16:
+;CHECK: vabd.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vabdu32:
+;CHECK: vabd.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vabdf32:
+;CHECK: vabd.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm.neon.vabds.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vabdQs8:
+;CHECK: vabd.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vabdQs16:
+;CHECK: vabd.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vabdQs32:
+;CHECK: vabd.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vabdQu8:
+;CHECK: vabd.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vabdQu16:
+;CHECK: vabd.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vabdQu32:
+;CHECK: vabd.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <4 x float> @vabdQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vabdQf32:
+;CHECK: vabd.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <2 x float> @llvm.arm.neon.vabds.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>) nounwind readnone
+
+define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vabdls8:
+;CHECK: vabdl.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vabdls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vabdls16:
+;CHECK: vabdl.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vabdls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vabdls32:
+;CHECK: vabdl.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vabdls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vabdlu8:
+;CHECK: vabdl.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vabdlu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vabdlu16:
+;CHECK: vabdl.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vabdlu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vabdlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vabdlu32:
+;CHECK: vabdl.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vabdlu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i16> @llvm.arm.neon.vabdls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vabdls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vabdls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vabdlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vabdlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vabdlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vabs.ll b/test/CodeGen/ARM/vabs.ll
new file mode 100644
index 0000000..18ba61f
--- /dev/null
+++ b/test/CodeGen/ARM/vabs.ll
@@ -0,0 +1,131 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
+;CHECK: vabss8:
+;CHECK: vabs.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
+;CHECK: vabss16:
+;CHECK: vabs.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
+;CHECK: vabss32:
+;CHECK: vabs.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
+;CHECK: vabsf32:
+;CHECK: vabs.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = call <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float> %tmp1)
+ ret <2 x float> %tmp2
+}
+
+define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind {
+;CHECK: vabsQs8:
+;CHECK: vabs.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1)
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind {
+;CHECK: vabsQs16:
+;CHECK: vabs.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind {
+;CHECK: vabsQs32:
+;CHECK: vabs.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1)
+ ret <4 x i32> %tmp2
+}
+
+define <4 x float> @vabsQf32(<4 x float>* %A) nounwind {
+;CHECK: vabsQf32:
+;CHECK: vabs.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = call <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float> %tmp1)
+ ret <4 x float> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32>) nounwind readnone
+declare <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float>) nounwind readnone
+
+define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind {
+;CHECK: vqabss8:
+;CHECK: vqabs.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind {
+;CHECK: vqabss16:
+;CHECK: vqabs.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind {
+;CHECK: vqabss32:
+;CHECK: vqabs.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind {
+;CHECK: vqabsQs8:
+;CHECK: vqabs.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1)
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind {
+;CHECK: vqabsQs16:
+;CHECK: vqabs.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind {
+;CHECK: vqabsQs32:
+;CHECK: vqabs.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1)
+ ret <4 x i32> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vadd.ll b/test/CodeGen/ARM/vadd.ll
new file mode 100644
index 0000000..9fa5307
--- /dev/null
+++ b/test/CodeGen/ARM/vadd.ll
@@ -0,0 +1,277 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vaddi8:
+;CHECK: vadd.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = add <8 x i8> %tmp1, %tmp2
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vaddi16:
+;CHECK: vadd.i16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = add <4 x i16> %tmp1, %tmp2
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vaddi32:
+;CHECK: vadd.i32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = add <2 x i32> %tmp1, %tmp2
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vaddi64:
+;CHECK: vadd.i64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = add <1 x i64> %tmp1, %tmp2
+ ret <1 x i64> %tmp3
+}
+
+define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vaddf32:
+;CHECK: vadd.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = add <2 x float> %tmp1, %tmp2
+ ret <2 x float> %tmp3
+}
+
+define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vaddQi8:
+;CHECK: vadd.i8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = add <16 x i8> %tmp1, %tmp2
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vaddQi16:
+;CHECK: vadd.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = add <8 x i16> %tmp1, %tmp2
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vaddQi32:
+;CHECK: vadd.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = add <4 x i32> %tmp1, %tmp2
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vaddQi64:
+;CHECK: vadd.i64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = add <2 x i64> %tmp1, %tmp2
+ ret <2 x i64> %tmp3
+}
+
+define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vaddQf32:
+;CHECK: vadd.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = add <4 x float> %tmp1, %tmp2
+ ret <4 x float> %tmp3
+}
+
+define <8 x i8> @vaddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vaddhni16:
+;CHECK: vaddhn.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vaddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vaddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vaddhni32:
+;CHECK: vaddhn.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vaddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vaddhni64:
+;CHECK: vaddhn.i64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vaddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vraddhni16:
+;CHECK: vraddhn.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vraddhni32:
+;CHECK: vraddhn.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vraddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vraddhni64:
+;CHECK: vraddhn.i64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vaddls8:
+;CHECK: vaddl.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vaddls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vaddls16:
+;CHECK: vaddl.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vaddls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vaddls32:
+;CHECK: vaddl.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vaddls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vaddlu8:
+;CHECK: vaddl.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vaddlu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vaddlu16:
+;CHECK: vaddl.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vaddlu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vaddlu32:
+;CHECK: vaddl.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vaddlu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i16> @llvm.arm.neon.vaddls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vaddls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vaddls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vaddlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vaddlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vaddlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vaddws8:
+;CHECK: vaddw.s8
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vaddws.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vaddws16:
+;CHECK: vaddw.s16
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vaddws.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vaddws32:
+;CHECK: vaddw.s32
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vaddws.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vaddwu8:
+;CHECK: vaddw.u8
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vaddwu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vaddwu16:
+;CHECK: vaddw.u16
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vaddwu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vaddwu32:
+;CHECK: vaddw.u32
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vaddwu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i16> @llvm.arm.neon.vaddws.v8i16(<8 x i16>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vaddws.v4i32(<4 x i32>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vaddws.v2i64(<2 x i64>, <2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vaddwu.v8i16(<8 x i16>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vaddwu.v4i32(<4 x i32>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vaddwu.v2i64(<2 x i64>, <2 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vargs.ll b/test/CodeGen/ARM/vargs.ll
new file mode 100644
index 0000000..5f3536c
--- /dev/null
+++ b/test/CodeGen/ARM/vargs.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=arm
+@str = internal constant [43 x i8] c"Hello World %d %d %d %d %d %d %d %d %d %d\0A\00" ; <[43 x i8]*> [#uses=1]
+
+define i32 @main() {
+entry:
+ %tmp = call i32 (i8*, ...)* @printf( i8* getelementptr ([43 x i8]* @str, i32 0, i64 0), i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10 ) ; <i32> [#uses=0]
+ %tmp2 = call i32 (i8*, ...)* @printf( i8* getelementptr ([43 x i8]* @str, i32 0, i64 0), i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1 ) ; <i32> [#uses=0]
+ ret i32 11
+}
+
+declare i32 @printf(i8*, ...)
+
diff --git a/test/CodeGen/ARM/vargs_align.ll b/test/CodeGen/ARM/vargs_align.ll
new file mode 100644
index 0000000..e4ef9e3
--- /dev/null
+++ b/test/CodeGen/ARM/vargs_align.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=EABI
+; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | FileCheck %s -check-prefix=OABI
+
+define i32 @f(i32 %a, ...) {
+entry:
+ %a_addr = alloca i32 ; <i32*> [#uses=1]
+ %retval = alloca i32, align 4 ; <i32*> [#uses=2]
+ %tmp = alloca i32, align 4 ; <i32*> [#uses=2]
+ "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %a, i32* %a_addr
+ store i32 0, i32* %tmp
+ %tmp1 = load i32* %tmp ; <i32> [#uses=1]
+ store i32 %tmp1, i32* %retval
+ br label %return
+
+return: ; preds = %entry
+ %retval2 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval2
+; EABI: add sp, sp, #12
+; EABI: add sp, sp, #16
+; OABI: add sp, sp, #12
+; OABI: add sp, sp, #12
+}
diff --git a/test/CodeGen/ARM/vbits.ll b/test/CodeGen/ARM/vbits.ll
new file mode 100644
index 0000000..293d229
--- /dev/null
+++ b/test/CodeGen/ARM/vbits.ll
@@ -0,0 +1,507 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: v_andi8:
+;CHECK: vand
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = and <8 x i8> %tmp1, %tmp2
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: v_andi16:
+;CHECK: vand
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = and <4 x i16> %tmp1, %tmp2
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: v_andi32:
+;CHECK: vand
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = and <2 x i32> %tmp1, %tmp2
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: v_andi64:
+;CHECK: vand
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = and <1 x i64> %tmp1, %tmp2
+ ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: v_andQi8:
+;CHECK: vand
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = and <16 x i8> %tmp1, %tmp2
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: v_andQi16:
+;CHECK: vand
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = and <8 x i16> %tmp1, %tmp2
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: v_andQi32:
+;CHECK: vand
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = and <4 x i32> %tmp1, %tmp2
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: v_andQi64:
+;CHECK: vand
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = and <2 x i64> %tmp1, %tmp2
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: v_bici8:
+;CHECK: vbic
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+ %tmp4 = and <8 x i8> %tmp1, %tmp3
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: v_bici16:
+;CHECK: vbic
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 >
+ %tmp4 = and <4 x i16> %tmp1, %tmp3
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: v_bici32:
+;CHECK: vbic
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 >
+ %tmp4 = and <2 x i32> %tmp1, %tmp3
+ ret <2 x i32> %tmp4
+}
+
+define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: v_bici64:
+;CHECK: vbic
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = xor <1 x i64> %tmp2, < i64 -1 >
+ %tmp4 = and <1 x i64> %tmp1, %tmp3
+ ret <1 x i64> %tmp4
+}
+
+define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: v_bicQi8:
+;CHECK: vbic
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+ %tmp4 = and <16 x i8> %tmp1, %tmp3
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: v_bicQi16:
+;CHECK: vbic
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
+ %tmp4 = and <8 x i16> %tmp1, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: v_bicQi32:
+;CHECK: vbic
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ %tmp4 = and <4 x i32> %tmp1, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: v_bicQi64:
+;CHECK: vbic
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 >
+ %tmp4 = and <2 x i64> %tmp1, %tmp3
+ ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: v_eori8:
+;CHECK: veor
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = xor <8 x i8> %tmp1, %tmp2
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: v_eori16:
+;CHECK: veor
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = xor <4 x i16> %tmp1, %tmp2
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: v_eori32:
+;CHECK: veor
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = xor <2 x i32> %tmp1, %tmp2
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: v_eori64:
+;CHECK: veor
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = xor <1 x i64> %tmp1, %tmp2
+ ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: v_eorQi8:
+;CHECK: veor
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = xor <16 x i8> %tmp1, %tmp2
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: v_eorQi16:
+;CHECK: veor
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = xor <8 x i16> %tmp1, %tmp2
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: v_eorQi32:
+;CHECK: veor
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = xor <4 x i32> %tmp1, %tmp2
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: v_eorQi64:
+;CHECK: veor
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = xor <2 x i64> %tmp1, %tmp2
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind {
+;CHECK: v_mvni8:
+;CHECK: vmvn
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind {
+;CHECK: v_mvni16:
+;CHECK: vmvn
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 >
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind {
+;CHECK: v_mvni32:
+;CHECK: vmvn
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 >
+ ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind {
+;CHECK: v_mvni64:
+;CHECK: vmvn
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = xor <1 x i64> %tmp1, < i64 -1 >
+ ret <1 x i64> %tmp2
+}
+
+define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind {
+;CHECK: v_mvnQi8:
+;CHECK: vmvn
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind {
+;CHECK: v_mvnQi16:
+;CHECK: vmvn
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind {
+;CHECK: v_mvnQi32:
+;CHECK: vmvn
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind {
+;CHECK: v_mvnQi64:
+;CHECK: vmvn
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 >
+ ret <2 x i64> %tmp2
+}
+
+define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: v_orri8:
+;CHECK: vorr
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = or <8 x i8> %tmp1, %tmp2
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: v_orri16:
+;CHECK: vorr
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = or <4 x i16> %tmp1, %tmp2
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: v_orri32:
+;CHECK: vorr
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = or <2 x i32> %tmp1, %tmp2
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: v_orri64:
+;CHECK: vorr
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = or <1 x i64> %tmp1, %tmp2
+ ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: v_orrQi8:
+;CHECK: vorr
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = or <16 x i8> %tmp1, %tmp2
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: v_orrQi16:
+;CHECK: vorr
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = or <8 x i16> %tmp1, %tmp2
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: v_orrQi32:
+;CHECK: vorr
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = or <4 x i32> %tmp1, %tmp2
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: v_orrQi64:
+;CHECK: vorr
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = or <2 x i64> %tmp1, %tmp2
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: v_orni8:
+;CHECK: vorn
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+ %tmp4 = or <8 x i8> %tmp1, %tmp3
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: v_orni16:
+;CHECK: vorn
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 >
+ %tmp4 = or <4 x i16> %tmp1, %tmp3
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: v_orni32:
+;CHECK: vorn
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 >
+ %tmp4 = or <2 x i32> %tmp1, %tmp3
+ ret <2 x i32> %tmp4
+}
+
+define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: v_orni64:
+;CHECK: vorn
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = xor <1 x i64> %tmp2, < i64 -1 >
+ %tmp4 = or <1 x i64> %tmp1, %tmp3
+ ret <1 x i64> %tmp4
+}
+
+define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: v_ornQi8:
+;CHECK: vorn
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+ %tmp4 = or <16 x i8> %tmp1, %tmp3
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: v_ornQi16:
+;CHECK: vorn
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
+ %tmp4 = or <8 x i16> %tmp1, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: v_ornQi32:
+;CHECK: vorn
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ %tmp4 = or <4 x i32> %tmp1, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: v_ornQi64:
+;CHECK: vorn
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 >
+ %tmp4 = or <2 x i64> %tmp1, %tmp3
+ ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vtsti8:
+;CHECK: vtst.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = and <8 x i8> %tmp1, %tmp2
+ %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
+ %tmp5 = sext <8 x i1> %tmp4 to <8 x i8>
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vtsti16:
+;CHECK: vtst.16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = and <4 x i16> %tmp1, %tmp2
+ %tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer
+ %tmp5 = sext <4 x i1> %tmp4 to <4 x i16>
+ ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vtsti32:
+;CHECK: vtst.32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = and <2 x i32> %tmp1, %tmp2
+ %tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer
+ %tmp5 = sext <2 x i1> %tmp4 to <2 x i32>
+ ret <2 x i32> %tmp5
+}
+
+define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vtstQi8:
+;CHECK: vtst.8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = and <16 x i8> %tmp1, %tmp2
+ %tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer
+ %tmp5 = sext <16 x i1> %tmp4 to <16 x i8>
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vtstQi16:
+;CHECK: vtst.16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = and <8 x i16> %tmp1, %tmp2
+ %tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer
+ %tmp5 = sext <8 x i1> %tmp4 to <8 x i16>
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vtstQi32:
+;CHECK: vtst.32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = and <4 x i32> %tmp1, %tmp2
+ %tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer
+ %tmp5 = sext <4 x i1> %tmp4 to <4 x i32>
+ ret <4 x i32> %tmp5
+}
diff --git a/test/CodeGen/ARM/vbsl.ll b/test/CodeGen/ARM/vbsl.ll
new file mode 100644
index 0000000..9f3bb4e
--- /dev/null
+++ b/test/CodeGen/ARM/vbsl.ll
@@ -0,0 +1,105 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+;CHECK: v_bsli8:
+;CHECK: vbsl
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = load <8 x i8>* %C
+ %tmp4 = and <8 x i8> %tmp1, %tmp2
+ %tmp5 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+ %tmp6 = and <8 x i8> %tmp5, %tmp3
+ %tmp7 = or <8 x i8> %tmp4, %tmp6
+ ret <8 x i8> %tmp7
+}
+
+define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+;CHECK: v_bsli16:
+;CHECK: vbsl
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i16>* %C
+ %tmp4 = and <4 x i16> %tmp1, %tmp2
+ %tmp5 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 >
+ %tmp6 = and <4 x i16> %tmp5, %tmp3
+ %tmp7 = or <4 x i16> %tmp4, %tmp6
+ ret <4 x i16> %tmp7
+}
+
+define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+;CHECK: v_bsli32:
+;CHECK: vbsl
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i32>* %C
+ %tmp4 = and <2 x i32> %tmp1, %tmp2
+ %tmp5 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 >
+ %tmp6 = and <2 x i32> %tmp5, %tmp3
+ %tmp7 = or <2 x i32> %tmp4, %tmp6
+ ret <2 x i32> %tmp7
+}
+
+define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
+;CHECK: v_bsli64:
+;CHECK: vbsl
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = load <1 x i64>* %C
+ %tmp4 = and <1 x i64> %tmp1, %tmp2
+ %tmp5 = xor <1 x i64> %tmp1, < i64 -1 >
+ %tmp6 = and <1 x i64> %tmp5, %tmp3
+ %tmp7 = or <1 x i64> %tmp4, %tmp6
+ ret <1 x i64> %tmp7
+}
+
+define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
+;CHECK: v_bslQi8:
+;CHECK: vbsl
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = load <16 x i8>* %C
+ %tmp4 = and <16 x i8> %tmp1, %tmp2
+ %tmp5 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+ %tmp6 = and <16 x i8> %tmp5, %tmp3
+ %tmp7 = or <16 x i8> %tmp4, %tmp6
+ ret <16 x i8> %tmp7
+}
+
+define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
+;CHECK: v_bslQi16:
+;CHECK: vbsl
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = load <8 x i16>* %C
+ %tmp4 = and <8 x i16> %tmp1, %tmp2
+ %tmp5 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
+ %tmp6 = and <8 x i16> %tmp5, %tmp3
+ %tmp7 = or <8 x i16> %tmp4, %tmp6
+ ret <8 x i16> %tmp7
+}
+
+define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
+;CHECK: v_bslQi32:
+;CHECK: vbsl
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = and <4 x i32> %tmp1, %tmp2
+ %tmp5 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ %tmp6 = and <4 x i32> %tmp5, %tmp3
+ %tmp7 = or <4 x i32> %tmp4, %tmp6
+ ret <4 x i32> %tmp7
+}
+
+define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
+;CHECK: v_bslQi64:
+;CHECK: vbsl
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp4 = and <2 x i64> %tmp1, %tmp2
+ %tmp5 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 >
+ %tmp6 = and <2 x i64> %tmp5, %tmp3
+ %tmp7 = or <2 x i64> %tmp4, %tmp6
+ ret <2 x i64> %tmp7
+}
diff --git a/test/CodeGen/ARM/vceq.ll b/test/CodeGen/ARM/vceq.ll
new file mode 100644
index 0000000..e478751
--- /dev/null
+++ b/test/CodeGen/ARM/vceq.ll
@@ -0,0 +1,81 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vceqi8:
+;CHECK: vceq.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = icmp eq <8 x i8> %tmp1, %tmp2
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vceqi16:
+;CHECK: vceq.i16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = icmp eq <4 x i16> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vceqi32:
+;CHECK: vceq.i32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = icmp eq <2 x i32> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vceqf32:
+;CHECK: vceq.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = fcmp oeq <2 x float> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vceqQi8:
+;CHECK: vceq.i8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = icmp eq <16 x i8> %tmp1, %tmp2
+ %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vceqQi16:
+;CHECK: vceq.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = icmp eq <8 x i16> %tmp1, %tmp2
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vceqQi32:
+;CHECK: vceq.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = icmp eq <4 x i32> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
+
+define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vceqQf32:
+;CHECK: vceq.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = fcmp oeq <4 x float> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
diff --git a/test/CodeGen/ARM/vcge.ll b/test/CodeGen/ARM/vcge.ll
new file mode 100644
index 0000000..2c16111
--- /dev/null
+++ b/test/CodeGen/ARM/vcge.ll
@@ -0,0 +1,162 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vcges8:
+;CHECK: vcge.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = icmp sge <8 x i8> %tmp1, %tmp2
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vcges16:
+;CHECK: vcge.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = icmp sge <4 x i16> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vcges32:
+;CHECK: vcge.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = icmp sge <2 x i32> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vcgeu8:
+;CHECK: vcge.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = icmp uge <8 x i8> %tmp1, %tmp2
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vcgeu16:
+;CHECK: vcge.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = icmp uge <4 x i16> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vcgeu32:
+;CHECK: vcge.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = icmp uge <2 x i32> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcgef32:
+;CHECK: vcge.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = fcmp oge <2 x float> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vcgeQs8:
+;CHECK: vcge.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = icmp sge <16 x i8> %tmp1, %tmp2
+ %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vcgeQs16:
+;CHECK: vcge.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = icmp sge <8 x i16> %tmp1, %tmp2
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vcgeQs32:
+;CHECK: vcge.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = icmp sge <4 x i32> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
+
+define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vcgeQu8:
+;CHECK: vcge.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = icmp uge <16 x i8> %tmp1, %tmp2
+ %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vcgeQu16:
+;CHECK: vcge.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = icmp uge <8 x i16> %tmp1, %tmp2
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vcgeQu32:
+;CHECK: vcge.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = icmp uge <4 x i32> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
+
+define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vcgeQf32:
+;CHECK: vcge.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = fcmp oge <4 x float> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vacgef32:
+;CHECK: vacge.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vacged(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vacgeQf32:
+;CHECK: vacge.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vacgeq(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>) nounwind readnone
diff --git a/test/CodeGen/ARM/vcgt.ll b/test/CodeGen/ARM/vcgt.ll
new file mode 100644
index 0000000..6b11ba5
--- /dev/null
+++ b/test/CodeGen/ARM/vcgt.ll
@@ -0,0 +1,162 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vcgts8:
+;CHECK: vcgt.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = icmp sgt <8 x i8> %tmp1, %tmp2
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vcgts16:
+;CHECK: vcgt.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = icmp sgt <4 x i16> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vcgts32:
+;CHECK: vcgt.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = icmp sgt <2 x i32> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vcgtu8:
+;CHECK: vcgt.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = icmp ugt <8 x i8> %tmp1, %tmp2
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vcgtu16:
+;CHECK: vcgt.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = icmp ugt <4 x i16> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vcgtu32:
+;CHECK: vcgt.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = icmp ugt <2 x i32> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcgtf32:
+;CHECK: vcgt.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = fcmp ogt <2 x float> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vcgtQs8:
+;CHECK: vcgt.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = icmp sgt <16 x i8> %tmp1, %tmp2
+ %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vcgtQs16:
+;CHECK: vcgt.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = icmp sgt <8 x i16> %tmp1, %tmp2
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vcgtQs32:
+;CHECK: vcgt.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = icmp sgt <4 x i32> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
+
+define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vcgtQu8:
+;CHECK: vcgt.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = icmp ugt <16 x i8> %tmp1, %tmp2
+ %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vcgtQu16:
+;CHECK: vcgt.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = icmp ugt <8 x i16> %tmp1, %tmp2
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vcgtQu32:
+;CHECK: vcgt.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = icmp ugt <4 x i32> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
+
+define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vcgtQf32:
+;CHECK: vcgt.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vacgtf32:
+;CHECK: vacgt.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vacgtd(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vacgtQf32:
+;CHECK: vacgt.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vacgtq(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone
diff --git a/test/CodeGen/ARM/vcnt.ll b/test/CodeGen/ARM/vcnt.ll
new file mode 100644
index 0000000..450f90d
--- /dev/null
+++ b/test/CodeGen/ARM/vcnt.ll
@@ -0,0 +1,132 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
+;CHECK: vcnt8:
+;CHECK: vcnt.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1)
+ ret <8 x i8> %tmp2
+}
+
+define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
+;CHECK: vcntQ8:
+;CHECK: vcnt.8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8> %tmp1)
+ ret <16 x i8> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8>) nounwind readnone
+declare <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8>) nounwind readnone
+
+define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
+;CHECK: vclz8:
+;CHECK: vclz.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vclz.v8i8(<8 x i8> %tmp1)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
+;CHECK: vclz16:
+;CHECK: vclz.i16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
+;CHECK: vclz32:
+;CHECK: vclz.i32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vclz.v2i32(<2 x i32> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
+;CHECK: vclzQ8:
+;CHECK: vclz.i8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <16 x i8> @llvm.arm.neon.vclz.v16i8(<16 x i8> %tmp1)
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
+;CHECK: vclzQ16:
+;CHECK: vclz.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16> %tmp1)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
+;CHECK: vclzQ32:
+;CHECK: vclz.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vclz.v4i32(<4 x i32> %tmp1)
+ ret <4 x i32> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vclz.v8i8(<8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vclz.v2i32(<2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vclz.v16i8(<16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vclz.v4i32(<4 x i32>) nounwind readnone
+
+define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
+;CHECK: vclss8:
+;CHECK: vcls.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
+;CHECK: vclss16:
+;CHECK: vcls.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
+;CHECK: vclss32:
+;CHECK: vcls.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
+;CHECK: vclsQs8:
+;CHECK: vcls.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
+;CHECK: vclsQs16:
+;CHECK: vcls.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
+;CHECK: vclsQs32:
+;CHECK: vcls.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
+ ret <4 x i32> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vcombine.ll b/test/CodeGen/ARM/vcombine.ll
new file mode 100644
index 0000000..e673305
--- /dev/null
+++ b/test/CodeGen/ARM/vcombine.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -march=arm -mattr=+neon
+
+define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vcombine16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vcombine32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %tmp3
+}
+
+define <4 x float> @vcombinefloat(<2 x float>* %A, <2 x float>* %B) nounwind {
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x float> %tmp3
+}
+
+define <2 x i64> @vcombine64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = shufflevector <1 x i64> %tmp1, <1 x i64> %tmp2, <2 x i32> <i32 0, i32 1>
+ ret <2 x i64> %tmp3
+}
diff --git a/test/CodeGen/ARM/vcvt.ll b/test/CodeGen/ARM/vcvt.ll
new file mode 100644
index 0000000..f4cc536
--- /dev/null
+++ b/test/CodeGen/ARM/vcvt.ll
@@ -0,0 +1,140 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
+;CHECK: vcvt_f32tos32:
+;CHECK: vcvt.s32.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = fptosi <2 x float> %tmp1 to <2 x i32>
+ ret <2 x i32> %tmp2
+}
+
+define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
+;CHECK: vcvt_f32tou32:
+;CHECK: vcvt.u32.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = fptoui <2 x float> %tmp1 to <2 x i32>
+ ret <2 x i32> %tmp2
+}
+
+define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
+;CHECK: vcvt_s32tof32:
+;CHECK: vcvt.f32.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = sitofp <2 x i32> %tmp1 to <2 x float>
+ ret <2 x float> %tmp2
+}
+
+define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
+;CHECK: vcvt_u32tof32:
+;CHECK: vcvt.f32.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = uitofp <2 x i32> %tmp1 to <2 x float>
+ ret <2 x float> %tmp2
+}
+
+define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
+;CHECK: vcvtQ_f32tos32:
+;CHECK: vcvt.s32.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = fptosi <4 x float> %tmp1 to <4 x i32>
+ ret <4 x i32> %tmp2
+}
+
+define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
+;CHECK: vcvtQ_f32tou32:
+;CHECK: vcvt.u32.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = fptoui <4 x float> %tmp1 to <4 x i32>
+ ret <4 x i32> %tmp2
+}
+
+define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
+;CHECK: vcvtQ_s32tof32:
+;CHECK: vcvt.f32.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = sitofp <4 x i32> %tmp1 to <4 x float>
+ ret <4 x float> %tmp2
+}
+
+define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
+;CHECK: vcvtQ_u32tof32:
+;CHECK: vcvt.f32.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = uitofp <4 x i32> %tmp1 to <4 x float>
+ ret <4 x float> %tmp2
+}
+
+define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
+;CHECK: vcvt_n_f32tos32:
+;CHECK: vcvt.s32.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
+ ret <2 x i32> %tmp2
+}
+
+define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
+;CHECK: vcvt_n_f32tou32:
+;CHECK: vcvt.u32.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
+ ret <2 x i32> %tmp2
+}
+
+define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
+;CHECK: vcvt_n_s32tof32:
+;CHECK: vcvt.f32.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
+ ret <2 x float> %tmp2
+}
+
+define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind {
+;CHECK: vcvt_n_u32tof32:
+;CHECK: vcvt.f32.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
+ ret <2 x float> %tmp2
+}
+
+declare <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone
+declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
+declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
+
+define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
+;CHECK: vcvtQ_n_f32tos32:
+;CHECK: vcvt.s32.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
+ ret <4 x i32> %tmp2
+}
+
+define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
+;CHECK: vcvtQ_n_f32tou32:
+;CHECK: vcvt.u32.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
+ ret <4 x i32> %tmp2
+}
+
+define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
+;CHECK: vcvtQ_n_s32tof32:
+;CHECK: vcvt.f32.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
+ ret <4 x float> %tmp2
+}
+
+define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind {
+;CHECK: vcvtQ_n_u32tof32:
+;CHECK: vcvt.f32.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
+ ret <4 x float> %tmp2
+}
+
+declare <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
+
diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll
new file mode 100644
index 0000000..c9a68ca
--- /dev/null
+++ b/test/CodeGen/ARM/vdup.ll
@@ -0,0 +1,269 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @v_dup8(i8 %A) nounwind {
+;CHECK: v_dup8:
+;CHECK: vdup.8
+ %tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
+ %tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1
+ %tmp3 = insertelement <8 x i8> %tmp2, i8 %A, i32 2
+ %tmp4 = insertelement <8 x i8> %tmp3, i8 %A, i32 3
+ %tmp5 = insertelement <8 x i8> %tmp4, i8 %A, i32 4
+ %tmp6 = insertelement <8 x i8> %tmp5, i8 %A, i32 5
+ %tmp7 = insertelement <8 x i8> %tmp6, i8 %A, i32 6
+ %tmp8 = insertelement <8 x i8> %tmp7, i8 %A, i32 7
+ ret <8 x i8> %tmp8
+}
+
+define <4 x i16> @v_dup16(i16 %A) nounwind {
+;CHECK: v_dup16:
+;CHECK: vdup.16
+ %tmp1 = insertelement <4 x i16> zeroinitializer, i16 %A, i32 0
+ %tmp2 = insertelement <4 x i16> %tmp1, i16 %A, i32 1
+ %tmp3 = insertelement <4 x i16> %tmp2, i16 %A, i32 2
+ %tmp4 = insertelement <4 x i16> %tmp3, i16 %A, i32 3
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @v_dup32(i32 %A) nounwind {
+;CHECK: v_dup32:
+;CHECK: vdup.32
+ %tmp1 = insertelement <2 x i32> zeroinitializer, i32 %A, i32 0
+ %tmp2 = insertelement <2 x i32> %tmp1, i32 %A, i32 1
+ ret <2 x i32> %tmp2
+}
+
+define <2 x float> @v_dupfloat(float %A) nounwind {
+;CHECK: v_dupfloat:
+;CHECK: vdup.32
+ %tmp1 = insertelement <2 x float> zeroinitializer, float %A, i32 0
+ %tmp2 = insertelement <2 x float> %tmp1, float %A, i32 1
+ ret <2 x float> %tmp2
+}
+
+define <16 x i8> @v_dupQ8(i8 %A) nounwind {
+;CHECK: v_dupQ8:
+;CHECK: vdup.8
+ %tmp1 = insertelement <16 x i8> zeroinitializer, i8 %A, i32 0
+ %tmp2 = insertelement <16 x i8> %tmp1, i8 %A, i32 1
+ %tmp3 = insertelement <16 x i8> %tmp2, i8 %A, i32 2
+ %tmp4 = insertelement <16 x i8> %tmp3, i8 %A, i32 3
+ %tmp5 = insertelement <16 x i8> %tmp4, i8 %A, i32 4
+ %tmp6 = insertelement <16 x i8> %tmp5, i8 %A, i32 5
+ %tmp7 = insertelement <16 x i8> %tmp6, i8 %A, i32 6
+ %tmp8 = insertelement <16 x i8> %tmp7, i8 %A, i32 7
+ %tmp9 = insertelement <16 x i8> %tmp8, i8 %A, i32 8
+ %tmp10 = insertelement <16 x i8> %tmp9, i8 %A, i32 9
+ %tmp11 = insertelement <16 x i8> %tmp10, i8 %A, i32 10
+ %tmp12 = insertelement <16 x i8> %tmp11, i8 %A, i32 11
+ %tmp13 = insertelement <16 x i8> %tmp12, i8 %A, i32 12
+ %tmp14 = insertelement <16 x i8> %tmp13, i8 %A, i32 13
+ %tmp15 = insertelement <16 x i8> %tmp14, i8 %A, i32 14
+ %tmp16 = insertelement <16 x i8> %tmp15, i8 %A, i32 15
+ ret <16 x i8> %tmp16
+}
+
+define <8 x i16> @v_dupQ16(i16 %A) nounwind {
+;CHECK: v_dupQ16:
+;CHECK: vdup.16
+ %tmp1 = insertelement <8 x i16> zeroinitializer, i16 %A, i32 0
+ %tmp2 = insertelement <8 x i16> %tmp1, i16 %A, i32 1
+ %tmp3 = insertelement <8 x i16> %tmp2, i16 %A, i32 2
+ %tmp4 = insertelement <8 x i16> %tmp3, i16 %A, i32 3
+ %tmp5 = insertelement <8 x i16> %tmp4, i16 %A, i32 4
+ %tmp6 = insertelement <8 x i16> %tmp5, i16 %A, i32 5
+ %tmp7 = insertelement <8 x i16> %tmp6, i16 %A, i32 6
+ %tmp8 = insertelement <8 x i16> %tmp7, i16 %A, i32 7
+ ret <8 x i16> %tmp8
+}
+
+define <4 x i32> @v_dupQ32(i32 %A) nounwind {
+;CHECK: v_dupQ32:
+;CHECK: vdup.32
+ %tmp1 = insertelement <4 x i32> zeroinitializer, i32 %A, i32 0
+ %tmp2 = insertelement <4 x i32> %tmp1, i32 %A, i32 1
+ %tmp3 = insertelement <4 x i32> %tmp2, i32 %A, i32 2
+ %tmp4 = insertelement <4 x i32> %tmp3, i32 %A, i32 3
+ ret <4 x i32> %tmp4
+}
+
+define <4 x float> @v_dupQfloat(float %A) nounwind {
+;CHECK: v_dupQfloat:
+;CHECK: vdup.32
+ %tmp1 = insertelement <4 x float> zeroinitializer, float %A, i32 0
+ %tmp2 = insertelement <4 x float> %tmp1, float %A, i32 1
+ %tmp3 = insertelement <4 x float> %tmp2, float %A, i32 2
+ %tmp4 = insertelement <4 x float> %tmp3, float %A, i32 3
+ ret <4 x float> %tmp4
+}
+
+; Check to make sure it works with shuffles, too.
+
+define <8 x i8> @v_shuffledup8(i8 %A) nounwind {
+;CHECK: v_shuffledup8:
+;CHECK: vdup.8
+ %tmp1 = insertelement <8 x i8> undef, i8 %A, i32 0
+ %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @v_shuffledup16(i16 %A) nounwind {
+;CHECK: v_shuffledup16:
+;CHECK: vdup.16
+ %tmp1 = insertelement <4 x i16> undef, i16 %A, i32 0
+ %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @v_shuffledup32(i32 %A) nounwind {
+;CHECK: v_shuffledup32:
+;CHECK: vdup.32
+ %tmp1 = insertelement <2 x i32> undef, i32 %A, i32 0
+ %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
+ ret <2 x i32> %tmp2
+}
+
+define <2 x float> @v_shuffledupfloat(float %A) nounwind {
+;CHECK: v_shuffledupfloat:
+;CHECK: vdup.32
+ %tmp1 = insertelement <2 x float> undef, float %A, i32 0
+ %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
+ ret <2 x float> %tmp2
+}
+
+define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind {
+;CHECK: v_shuffledupQ8:
+;CHECK: vdup.8
+ %tmp1 = insertelement <16 x i8> undef, i8 %A, i32 0
+ %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> zeroinitializer
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind {
+;CHECK: v_shuffledupQ16:
+;CHECK: vdup.16
+ %tmp1 = insertelement <8 x i16> undef, i16 %A, i32 0
+ %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> zeroinitializer
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind {
+;CHECK: v_shuffledupQ32:
+;CHECK: vdup.32
+ %tmp1 = insertelement <4 x i32> undef, i32 %A, i32 0
+ %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> zeroinitializer
+ ret <4 x i32> %tmp2
+}
+
+define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
+;CHECK: v_shuffledupQfloat:
+;CHECK: vdup.32
+ %tmp1 = insertelement <4 x float> undef, float %A, i32 0
+ %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
+ ret <4 x float> %tmp2
+}
+
+define <2 x float> @v_shuffledupfloat2(float* %A) nounwind {
+;CHECK: v_shuffledupfloat2:
+;CHECK: vdup.32
+ %tmp0 = load float* %A
+ %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
+ %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
+ ret <2 x float> %tmp2
+}
+
+define <4 x float> @v_shuffledupQfloat2(float* %A) nounwind {
+;CHECK: v_shuffledupQfloat2:
+;CHECK: vdup.32
+ %tmp0 = load float* %A
+ %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
+ %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
+ ret <4 x float> %tmp2
+}
+
+define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
+;CHECK: vduplane8:
+;CHECK: vdup.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
+;CHECK: vduplane16:
+;CHECK: vdup.16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
+;CHECK: vduplane32:
+;CHECK: vdup.32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
+ ret <2 x i32> %tmp2
+}
+
+define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
+;CHECK: vduplanefloat:
+;CHECK: vdup.32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
+ ret <2 x float> %tmp2
+}
+
+define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
+;CHECK: vduplaneQ8:
+;CHECK: vdup.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
+;CHECK: vduplaneQ16:
+;CHECK: vdup.16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
+;CHECK: vduplaneQ32:
+;CHECK: vdup.32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
+ ret <4 x i32> %tmp2
+}
+
+define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
+;CHECK: vduplaneQfloat:
+;CHECK: vdup.32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
+ ret <4 x float> %tmp2
+}
+
+define arm_apcscc <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone {
+entry:
+ %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
+ ret <2 x i64> %0
+}
+
+define arm_apcscc <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone {
+entry:
+ %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+ ret <2 x i64> %0
+}
+
+define arm_apcscc <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone {
+entry:
+ %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 1, i32 1>
+ ret <2 x double> %0
+}
+
+define arm_apcscc <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone {
+entry:
+ %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0>
+ ret <2 x double> %0
+}
diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll
new file mode 100644
index 0000000..20d953b
--- /dev/null
+++ b/test/CodeGen/ARM/vext.ll
@@ -0,0 +1,56 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define arm_apcscc <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: test_vextd:
+;CHECK: vext
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
+ ret <8 x i8> %tmp3
+}
+
+define arm_apcscc <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: test_vextRd:
+;CHECK: vext
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
+ ret <8 x i8> %tmp3
+}
+
+define arm_apcscc <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: test_vextq:
+;CHECK: vext
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
+ ret <16 x i8> %tmp3
+}
+
+define arm_apcscc <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: test_vextRq:
+;CHECK: vext
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
+ ret <16 x i8> %tmp3
+}
+
+define arm_apcscc <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: test_vextd16:
+;CHECK: vext
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
+ ret <4 x i16> %tmp3
+}
+
+define arm_apcscc <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: test_vextq32:
+;CHECK: vext
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
+ ret <4 x i32> %tmp3
+}
+
diff --git a/test/CodeGen/ARM/vfcmp.ll b/test/CodeGen/ARM/vfcmp.ll
new file mode 100644
index 0000000..6946d02
--- /dev/null
+++ b/test/CodeGen/ARM/vfcmp.ll
@@ -0,0 +1,139 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+; This tests fcmp operations that do not map directly to NEON instructions.
+
+; une is implemented with VCEQ/VMVN
+define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcunef32:
+;CHECK: vceq.f32
+;CHECK-NEXT: vmvn
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = fcmp une <2 x float> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+; olt is implemented with VCGT
+define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcoltf32:
+;CHECK: vcgt.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = fcmp olt <2 x float> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+; ole is implemented with VCGE
+define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcolef32:
+;CHECK: vcge.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = fcmp ole <2 x float> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+; uge is implemented with VCGT/VMVN
+define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcugef32:
+;CHECK: vcgt.f32
+;CHECK-NEXT: vmvn
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = fcmp uge <2 x float> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+; ule is implemented with VCGT/VMVN
+define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vculef32:
+;CHECK: vcgt.f32
+;CHECK-NEXT: vmvn
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = fcmp ule <2 x float> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+; ugt is implemented with VCGE/VMVN
+define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcugtf32:
+;CHECK: vcge.f32
+;CHECK-NEXT: vmvn
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = fcmp ugt <2 x float> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+; ult is implemented with VCGE/VMVN
+define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcultf32:
+;CHECK: vcge.f32
+;CHECK-NEXT: vmvn
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = fcmp ult <2 x float> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+; ueq is implemented with VCGT/VCGT/VORR/VMVN
+define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcueqf32:
+;CHECK: vcgt.f32
+;CHECK-NEXT: vcgt.f32
+;CHECK-NEXT: vorr
+;CHECK-NEXT: vmvn
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = fcmp ueq <2 x float> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+; one is implemented with VCGT/VCGT/VORR
+define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vconef32:
+;CHECK: vcgt.f32
+;CHECK-NEXT: vcgt.f32
+;CHECK-NEXT: vorr
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = fcmp one <2 x float> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+; uno is implemented with VCGT/VCGE/VORR/VMVN
+define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcunof32:
+;CHECK: vcge.f32
+;CHECK-NEXT: vcgt.f32
+;CHECK-NEXT: vorr
+;CHECK-NEXT: vmvn
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = fcmp uno <2 x float> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+; ord is implemented with VCGT/VCGE/VORR
+define <2 x i32> @vcordf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vcordf32:
+;CHECK: vcge.f32
+;CHECK-NEXT: vcgt.f32
+;CHECK-NEXT: vorr
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = fcmp ord <2 x float> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
diff --git a/test/CodeGen/ARM/vfp.ll b/test/CodeGen/ARM/vfp.ll
new file mode 100644
index 0000000..44a44af
--- /dev/null
+++ b/test/CodeGen/ARM/vfp.ll
@@ -0,0 +1,155 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
+
+define void @test(float* %P, double* %D) {
+ %A = load float* %P ; <float> [#uses=1]
+ %B = load double* %D ; <double> [#uses=1]
+ store float %A, float* %P
+ store double %B, double* %D
+ ret void
+}
+
+declare float @fabsf(float)
+
+declare double @fabs(double)
+
+define void @test_abs(float* %P, double* %D) {
+;CHECK: test_abs:
+ %a = load float* %P ; <float> [#uses=1]
+;CHECK: vabs.f32
+ %b = call float @fabsf( float %a ) ; <float> [#uses=1]
+ store float %b, float* %P
+ %A = load double* %D ; <double> [#uses=1]
+;CHECK: vabs.f64
+ %B = call double @fabs( double %A ) ; <double> [#uses=1]
+ store double %B, double* %D
+ ret void
+}
+
+define void @test_add(float* %P, double* %D) {
+;CHECK: test_add:
+ %a = load float* %P ; <float> [#uses=2]
+ %b = fadd float %a, %a ; <float> [#uses=1]
+ store float %b, float* %P
+ %A = load double* %D ; <double> [#uses=2]
+ %B = fadd double %A, %A ; <double> [#uses=1]
+ store double %B, double* %D
+ ret void
+}
+
+define void @test_ext_round(float* %P, double* %D) {
+;CHECK: test_ext_round:
+ %a = load float* %P ; <float> [#uses=1]
+;CHECK: vcvt.f64.f32
+ %b = fpext float %a to double ; <double> [#uses=1]
+ %A = load double* %D ; <double> [#uses=1]
+;CHECK: vcvt.f32.f64
+ %B = fptrunc double %A to float ; <float> [#uses=1]
+ store double %b, double* %D
+ store float %B, float* %P
+ ret void
+}
+
+define void @test_fma(float* %P1, float* %P2, float* %P3) {
+;CHECK: test_fma:
+ %a1 = load float* %P1 ; <float> [#uses=1]
+ %a2 = load float* %P2 ; <float> [#uses=1]
+ %a3 = load float* %P3 ; <float> [#uses=1]
+;CHECK: vnmls.f32
+ %X = fmul float %a1, %a2 ; <float> [#uses=1]
+ %Y = fsub float %X, %a3 ; <float> [#uses=1]
+ store float %Y, float* %P1
+ ret void
+}
+
+define i32 @test_ftoi(float* %P1) {
+;CHECK: test_ftoi:
+ %a1 = load float* %P1 ; <float> [#uses=1]
+;CHECK: vcvt.s32.f32
+ %b1 = fptosi float %a1 to i32 ; <i32> [#uses=1]
+ ret i32 %b1
+}
+
+define i32 @test_ftou(float* %P1) {
+;CHECK: test_ftou:
+ %a1 = load float* %P1 ; <float> [#uses=1]
+;CHECK: vcvt.u32.f32
+ %b1 = fptoui float %a1 to i32 ; <i32> [#uses=1]
+ ret i32 %b1
+}
+
+define i32 @test_dtoi(double* %P1) {
+;CHECK: test_dtoi:
+ %a1 = load double* %P1 ; <double> [#uses=1]
+;CHECK: vcvt.s32.f64
+ %b1 = fptosi double %a1 to i32 ; <i32> [#uses=1]
+ ret i32 %b1
+}
+
+define i32 @test_dtou(double* %P1) {
+;CHECK: test_dtou:
+ %a1 = load double* %P1 ; <double> [#uses=1]
+;CHECK: vcvt.u32.f64
+ %b1 = fptoui double %a1 to i32 ; <i32> [#uses=1]
+ ret i32 %b1
+}
+
+define void @test_utod(double* %P1, i32 %X) {
+;CHECK: test_utod:
+;CHECK: vcvt.f64.u32
+ %b1 = uitofp i32 %X to double ; <double> [#uses=1]
+ store double %b1, double* %P1
+ ret void
+}
+
+define void @test_utod2(double* %P1, i8 %X) {
+;CHECK: test_utod2:
+;CHECK: vcvt.f64.u32
+ %b1 = uitofp i8 %X to double ; <double> [#uses=1]
+ store double %b1, double* %P1
+ ret void
+}
+
+define void @test_cmp(float* %glob, i32 %X) {
+;CHECK: test_cmp:
+entry:
+ %tmp = load float* %glob ; <float> [#uses=2]
+ %tmp3 = getelementptr float* %glob, i32 2 ; <float*> [#uses=1]
+ %tmp4 = load float* %tmp3 ; <float> [#uses=2]
+ %tmp.upgrd.1 = fcmp oeq float %tmp, %tmp4 ; <i1> [#uses=1]
+ %tmp5 = fcmp uno float %tmp, %tmp4 ; <i1> [#uses=1]
+ %tmp6 = or i1 %tmp.upgrd.1, %tmp5 ; <i1> [#uses=1]
+;CHECK: bmi
+;CHECK-NEXT: bgt
+ br i1 %tmp6, label %cond_true, label %cond_false
+
+cond_true: ; preds = %entry
+ %tmp.upgrd.2 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ ret void
+
+cond_false: ; preds = %entry
+ %tmp7 = tail call i32 (...)* @baz( ) ; <i32> [#uses=0]
+ ret void
+}
+
+declare i1 @llvm.isunordered.f32(float, float)
+
+declare i32 @bar(...)
+
+declare i32 @baz(...)
+
+define void @test_cmpfp0(float* %glob, i32 %X) {
+;CHECK: test_cmpfp0:
+entry:
+ %tmp = load float* %glob ; <float> [#uses=1]
+;CHECK: vcmpe.f32
+ %tmp.upgrd.3 = fcmp ogt float %tmp, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %tmp.upgrd.3, label %cond_true, label %cond_false
+
+cond_true: ; preds = %entry
+ %tmp.upgrd.4 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ ret void
+
+cond_false: ; preds = %entry
+ %tmp1 = tail call i32 (...)* @baz( ) ; <i32> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/ARM/vget_lane.ll b/test/CodeGen/ARM/vget_lane.ll
new file mode 100644
index 0000000..5dd87d6
--- /dev/null
+++ b/test/CodeGen/ARM/vget_lane.ll
@@ -0,0 +1,212 @@
+; RUN: llc < %s -mattr=+neon | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
+;CHECK: vget_lanes8:
+;CHECK: vmov.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = extractelement <8 x i8> %tmp1, i32 1
+ %tmp3 = sext i8 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
+;CHECK: vget_lanes16:
+;CHECK: vmov.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = extractelement <4 x i16> %tmp1, i32 1
+ %tmp3 = sext i16 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
+;CHECK: vget_laneu8:
+;CHECK: vmov.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = extractelement <8 x i8> %tmp1, i32 1
+ %tmp3 = zext i8 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
+;CHECK: vget_laneu16:
+;CHECK: vmov.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = extractelement <4 x i16> %tmp1, i32 1
+ %tmp3 = zext i16 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+; Do a vector add to keep the extraction from being done directly from memory.
+define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
+;CHECK: vget_lanei32:
+;CHECK: vmov.32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = add <2 x i32> %tmp1, %tmp1
+ %tmp3 = extractelement <2 x i32> %tmp2, i32 1
+ ret i32 %tmp3
+}
+
+define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
+;CHECK: vgetQ_lanes8:
+;CHECK: vmov.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = extractelement <16 x i8> %tmp1, i32 1
+ %tmp3 = sext i8 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
+;CHECK: vgetQ_lanes16:
+;CHECK: vmov.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = extractelement <8 x i16> %tmp1, i32 1
+ %tmp3 = sext i16 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
+;CHECK: vgetQ_laneu8:
+;CHECK: vmov.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = extractelement <16 x i8> %tmp1, i32 1
+ %tmp3 = zext i8 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
+;CHECK: vgetQ_laneu16:
+;CHECK: vmov.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = extractelement <8 x i16> %tmp1, i32 1
+ %tmp3 = zext i16 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+; Do a vector add to keep the extraction from being done directly from memory.
+define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind {
+;CHECK: vgetQ_lanei32:
+;CHECK: vmov.32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = add <4 x i32> %tmp1, %tmp1
+ %tmp3 = extractelement <4 x i32> %tmp2, i32 1
+ ret i32 %tmp3
+}
+
+define arm_aapcs_vfpcc void @test_vget_laneu16() nounwind {
+entry:
+; CHECK: vmov.u16 r0, d0[1]
+ %arg0_uint16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1]
+ %out_uint16_t = alloca i16 ; <i16*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %0 = load <4 x i16>* %arg0_uint16x4_t, align 8 ; <<4 x i16>> [#uses=1]
+ %1 = extractelement <4 x i16> %0, i32 1 ; <i16> [#uses=1]
+ store i16 %1, i16* %out_uint16_t, align 2
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define arm_aapcs_vfpcc void @test_vget_laneu8() nounwind {
+entry:
+; CHECK: vmov.u8 r0, d0[1]
+ %arg0_uint8x8_t = alloca <8 x i8> ; <<8 x i8>*> [#uses=1]
+ %out_uint8_t = alloca i8 ; <i8*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %0 = load <8 x i8>* %arg0_uint8x8_t, align 8 ; <<8 x i8>> [#uses=1]
+ %1 = extractelement <8 x i8> %0, i32 1 ; <i8> [#uses=1]
+ store i8 %1, i8* %out_uint8_t, align 1
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define arm_aapcs_vfpcc void @test_vgetQ_laneu16() nounwind {
+entry:
+; CHECK: vmov.u16 r0, d0[1]
+ %arg0_uint16x8_t = alloca <8 x i16> ; <<8 x i16>*> [#uses=1]
+ %out_uint16_t = alloca i16 ; <i16*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %0 = load <8 x i16>* %arg0_uint16x8_t, align 16 ; <<8 x i16>> [#uses=1]
+ %1 = extractelement <8 x i16> %0, i32 1 ; <i16> [#uses=1]
+ store i16 %1, i16* %out_uint16_t, align 2
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define arm_aapcs_vfpcc void @test_vgetQ_laneu8() nounwind {
+entry:
+; CHECK: vmov.u8 r0, d0[1]
+ %arg0_uint8x16_t = alloca <16 x i8> ; <<16 x i8>*> [#uses=1]
+ %out_uint8_t = alloca i8 ; <i8*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %0 = load <16 x i8>* %arg0_uint8x16_t, align 16 ; <<16 x i8>> [#uses=1]
+ %1 = extractelement <16 x i8> %0, i32 1 ; <i8> [#uses=1]
+ store i8 %1, i8* %out_uint8_t, align 1
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind {
+;CHECK: vset_lane8:
+;CHECK: vmov.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = insertelement <8 x i8> %tmp1, i8 %B, i32 1
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind {
+;CHECK: vset_lane16:
+;CHECK: vmov.16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = insertelement <4 x i16> %tmp1, i16 %B, i32 1
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind {
+;CHECK: vset_lane32:
+;CHECK: vmov.32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = insertelement <2 x i32> %tmp1, i32 %B, i32 1
+ ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind {
+;CHECK: vsetQ_lane8:
+;CHECK: vmov.8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = insertelement <16 x i8> %tmp1, i8 %B, i32 1
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
+;CHECK: vsetQ_lane16:
+;CHECK: vmov.16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = insertelement <8 x i16> %tmp1, i16 %B, i32 1
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
+;CHECK: vsetQ_lane32:
+;CHECK: vmov.32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1
+ ret <4 x i32> %tmp2
+}
+
+define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind {
+;CHECK: test_vset_lanef32:
+;CHECK: vmov.f32
+;CHECK: vmov.f32
+entry:
+ %0 = insertelement <2 x float> %arg1_float32x2_t, float %arg0_float32_t, i32 1 ; <<2 x float>> [#uses=1]
+ ret <2 x float> %0
+}
diff --git a/test/CodeGen/ARM/vhadd.ll b/test/CodeGen/ARM/vhadd.ll
new file mode 100644
index 0000000..379e062
--- /dev/null
+++ b/test/CodeGen/ARM/vhadd.ll
@@ -0,0 +1,249 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vhadds8:
+;CHECK: vhadd.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vhadds16:
+;CHECK: vhadd.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vhadds32:
+;CHECK: vhadd.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vhaddu8:
+;CHECK: vhadd.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vhaddu16:
+;CHECK: vhadd.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vhaddu32:
+;CHECK: vhadd.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vhaddQs8:
+;CHECK: vhadd.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vhaddQs16:
+;CHECK: vhadd.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vhaddQs32:
+;CHECK: vhadd.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vhaddQu8:
+;CHECK: vhadd.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vhaddQu16:
+;CHECK: vhadd.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vhaddQu32:
+;CHECK: vhadd.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vrhadds8:
+;CHECK: vrhadd.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vrhadds16:
+;CHECK: vrhadd.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vrhadds32:
+;CHECK: vrhadd.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vrhadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vrhaddu8:
+;CHECK: vrhadd.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vrhaddu16:
+;CHECK: vrhadd.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vrhaddu32:
+;CHECK: vrhadd.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vrhaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vrhaddQs8:
+;CHECK: vrhadd.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vrhaddQs16:
+;CHECK: vrhadd.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vrhaddQs32:
+;CHECK: vrhadd.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vrhaddQu8:
+;CHECK: vrhadd.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vrhaddQu16:
+;CHECK: vrhadd.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vrhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vrhaddQu32:
+;CHECK: vrhadd.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vrhadds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vrhaddu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vhsub.ll b/test/CodeGen/ARM/vhsub.ll
new file mode 100644
index 0000000..0f0d027
--- /dev/null
+++ b/test/CodeGen/ARM/vhsub.ll
@@ -0,0 +1,125 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vhsubs8:
+;CHECK: vhsub.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vhsubs16:
+;CHECK: vhsub.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vhsubs32:
+;CHECK: vhsub.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vhsubu8:
+;CHECK: vhsub.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vhsubu16:
+;CHECK: vhsub.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vhsubu32:
+;CHECK: vhsub.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vhsubQs8:
+;CHECK: vhsub.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vhsubQs16:
+;CHECK: vhsub.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vhsubQs32:
+;CHECK: vhsub.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vhsubQu8:
+;CHECK: vhsub.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vhsubQu16:
+;CHECK: vhsub.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vhsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vhsubQu32:
+;CHECK: vhsub.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vicmp.ll b/test/CodeGen/ARM/vicmp.ll
new file mode 100644
index 0000000..2d8cb89
--- /dev/null
+++ b/test/CodeGen/ARM/vicmp.ll
@@ -0,0 +1,113 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+; This tests icmp operations that do not map directly to NEON instructions.
+; Not-equal (ne) operations are implemented by VCEQ/VMVN. Less-than (lt/ult)
+; and less-than-or-equal (le/ule) are implemented by swapping the arguments
+; to VCGT and VCGE. Test all the operand types for not-equal but only sample
+; the other operations.
+
+define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vcnei8:
+;CHECK: vceq.i8
+;CHECK-NEXT: vmvn
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = icmp ne <8 x i8> %tmp1, %tmp2
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vcnei16:
+;CHECK: vceq.i16
+;CHECK-NEXT: vmvn
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = icmp ne <4 x i16> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vcnei32:
+;CHECK: vceq.i32
+;CHECK-NEXT: vmvn
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = icmp ne <2 x i32> %tmp1, %tmp2
+ %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+ ret <2 x i32> %tmp4
+}
+
+define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vcneQi8:
+;CHECK: vceq.i8
+;CHECK-NEXT: vmvn
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = icmp ne <16 x i8> %tmp1, %tmp2
+ %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vcneQi16:
+;CHECK: vceq.i16
+;CHECK-NEXT: vmvn
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = icmp ne <8 x i16> %tmp1, %tmp2
+ %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vcneQi32:
+;CHECK: vceq.i32
+;CHECK-NEXT: vmvn
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = icmp ne <4 x i32> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
+
+define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vcltQs8:
+;CHECK: vcgt.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = icmp slt <16 x i8> %tmp1, %tmp2
+ %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+ ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vcles16:
+;CHECK: vcge.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = icmp sle <4 x i16> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+ ret <4 x i16> %tmp4
+}
+
+define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vcltu16:
+;CHECK: vcgt.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = icmp ult <4 x i16> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+ ret <4 x i16> %tmp4
+}
+
+define <4 x i32> @vcleQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vcleQu32:
+;CHECK: vcge.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = icmp ule <4 x i32> %tmp1, %tmp2
+ %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+ ret <4 x i32> %tmp4
+}
diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll
new file mode 100644
index 0000000..f5383aa
--- /dev/null
+++ b/test/CodeGen/ARM/vld1.ll
@@ -0,0 +1,83 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vld1i8(i8* %A) nounwind {
+;CHECK: vld1i8:
+;CHECK: vld1.8
+ %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A)
+ ret <8 x i8> %tmp1
+}
+
+define <4 x i16> @vld1i16(i16* %A) nounwind {
+;CHECK: vld1i16:
+;CHECK: vld1.16
+ %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i16* %A)
+ ret <4 x i16> %tmp1
+}
+
+define <2 x i32> @vld1i32(i32* %A) nounwind {
+;CHECK: vld1i32:
+;CHECK: vld1.32
+ %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i32* %A)
+ ret <2 x i32> %tmp1
+}
+
+define <2 x float> @vld1f(float* %A) nounwind {
+;CHECK: vld1f:
+;CHECK: vld1.32
+ %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(float* %A)
+ ret <2 x float> %tmp1
+}
+
+define <1 x i64> @vld1i64(i64* %A) nounwind {
+;CHECK: vld1i64:
+;CHECK: vld1.64
+ %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i64* %A)
+ ret <1 x i64> %tmp1
+}
+
+define <16 x i8> @vld1Qi8(i8* %A) nounwind {
+;CHECK: vld1Qi8:
+;CHECK: vld1.8
+ %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A)
+ ret <16 x i8> %tmp1
+}
+
+define <8 x i16> @vld1Qi16(i16* %A) nounwind {
+;CHECK: vld1Qi16:
+;CHECK: vld1.16
+ %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i16* %A)
+ ret <8 x i16> %tmp1
+}
+
+define <4 x i32> @vld1Qi32(i32* %A) nounwind {
+;CHECK: vld1Qi32:
+;CHECK: vld1.32
+ %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i32* %A)
+ ret <4 x i32> %tmp1
+}
+
+define <4 x float> @vld1Qf(float* %A) nounwind {
+;CHECK: vld1Qf:
+;CHECK: vld1.32
+ %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(float* %A)
+ ret <4 x float> %tmp1
+}
+
+define <2 x i64> @vld1Qi64(i64* %A) nounwind {
+;CHECK: vld1Qi64:
+;CHECK: vld1.64
+ %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i64* %A)
+ ret <2 x i64> %tmp1
+}
+
+declare <8 x i8> @llvm.arm.neon.vld1.v8i8(i8*) nounwind readonly
+declare <4 x i16> @llvm.arm.neon.vld1.v4i16(i8*) nounwind readonly
+declare <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*) nounwind readonly
+declare <2 x float> @llvm.arm.neon.vld1.v2f32(i8*) nounwind readonly
+declare <1 x i64> @llvm.arm.neon.vld1.v1i64(i8*) nounwind readonly
+
+declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8*) nounwind readonly
+declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*) nounwind readonly
+declare <4 x i32> @llvm.arm.neon.vld1.v4i32(i8*) nounwind readonly
+declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly
+declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*) nounwind readonly
diff --git a/test/CodeGen/ARM/vld2.ll b/test/CodeGen/ARM/vld2.ll
new file mode 100644
index 0000000..23f7d2c
--- /dev/null
+++ b/test/CodeGen/ARM/vld2.ll
@@ -0,0 +1,113 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
+%struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> }
+%struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> }
+%struct.__neon_float32x2x2_t = type { <2 x float>, <2 x float> }
+%struct.__neon_int64x1x2_t = type { <1 x i64>, <1 x i64> }
+
+%struct.__neon_int8x16x2_t = type { <16 x i8>, <16 x i8> }
+%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> }
+%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
+%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
+
+define <8 x i8> @vld2i8(i8* %A) nounwind {
+;CHECK: vld2i8:
+;CHECK: vld2.8
+ %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A)
+ %tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1
+ %tmp4 = add <8 x i8> %tmp2, %tmp3
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vld2i16(i16* %A) nounwind {
+;CHECK: vld2i16:
+;CHECK: vld2.16
+ %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i16* %A)
+ %tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 1
+ %tmp4 = add <4 x i16> %tmp2, %tmp3
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vld2i32(i32* %A) nounwind {
+;CHECK: vld2i32:
+;CHECK: vld2.32
+ %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i32* %A)
+ %tmp2 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 1
+ %tmp4 = add <2 x i32> %tmp2, %tmp3
+ ret <2 x i32> %tmp4
+}
+
+define <2 x float> @vld2f(float* %A) nounwind {
+;CHECK: vld2f:
+;CHECK: vld2.32
+ %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(float* %A)
+ %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
+ %tmp4 = add <2 x float> %tmp2, %tmp3
+ ret <2 x float> %tmp4
+}
+
+define <1 x i64> @vld2i64(i64* %A) nounwind {
+;CHECK: vld2i64:
+;CHECK: vld1.64
+ %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i64* %A)
+ %tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1
+ %tmp4 = add <1 x i64> %tmp2, %tmp3
+ ret <1 x i64> %tmp4
+}
+
+define <16 x i8> @vld2Qi8(i8* %A) nounwind {
+;CHECK: vld2Qi8:
+;CHECK: vld2.8
+ %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A)
+ %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
+ %tmp4 = add <16 x i8> %tmp2, %tmp3
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vld2Qi16(i16* %A) nounwind {
+;CHECK: vld2Qi16:
+;CHECK: vld2.16
+ %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i16* %A)
+ %tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 1
+ %tmp4 = add <8 x i16> %tmp2, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vld2Qi32(i32* %A) nounwind {
+;CHECK: vld2Qi32:
+;CHECK: vld2.32
+ %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i32* %A)
+ %tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 1
+ %tmp4 = add <4 x i32> %tmp2, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <4 x float> @vld2Qf(float* %A) nounwind {
+;CHECK: vld2Qf:
+;CHECK: vld2.32
+ %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(float* %A)
+ %tmp2 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 1
+ %tmp4 = add <4 x float> %tmp2, %tmp3
+ ret <4 x float> %tmp4
+}
+
+declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8*) nounwind readonly
+declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8*) nounwind readonly
+declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8*) nounwind readonly
+declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8*) nounwind readonly
+declare %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8*) nounwind readonly
+
+declare %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8*) nounwind readonly
+declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8*) nounwind readonly
+declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8*) nounwind readonly
+declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(i8*) nounwind readonly
diff --git a/test/CodeGen/ARM/vld3.ll b/test/CodeGen/ARM/vld3.ll
new file mode 100644
index 0000000..207dc6a2
--- /dev/null
+++ b/test/CodeGen/ARM/vld3.ll
@@ -0,0 +1,117 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
+%struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> }
+%struct.__neon_int32x2x3_t = type { <2 x i32>, <2 x i32>, <2 x i32> }
+%struct.__neon_float32x2x3_t = type { <2 x float>, <2 x float>, <2 x float> }
+%struct.__neon_int64x1x3_t = type { <1 x i64>, <1 x i64>, <1 x i64> }
+
+%struct.__neon_int8x16x3_t = type { <16 x i8>, <16 x i8>, <16 x i8> }
+%struct.__neon_int16x8x3_t = type { <8 x i16>, <8 x i16>, <8 x i16> }
+%struct.__neon_int32x4x3_t = type { <4 x i32>, <4 x i32>, <4 x i32> }
+%struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
+
+define <8 x i8> @vld3i8(i8* %A) nounwind {
+;CHECK: vld3i8:
+;CHECK: vld3.8
+ %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A)
+ %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2
+ %tmp4 = add <8 x i8> %tmp2, %tmp3
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vld3i16(i16* %A) nounwind {
+;CHECK: vld3i16:
+;CHECK: vld3.16
+ %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i16* %A)
+ %tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2
+ %tmp4 = add <4 x i16> %tmp2, %tmp3
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vld3i32(i32* %A) nounwind {
+;CHECK: vld3i32:
+;CHECK: vld3.32
+ %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i32* %A)
+ %tmp2 = extractvalue %struct.__neon_int32x2x3_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp1, 2
+ %tmp4 = add <2 x i32> %tmp2, %tmp3
+ ret <2 x i32> %tmp4
+}
+
+define <2 x float> @vld3f(float* %A) nounwind {
+;CHECK: vld3f:
+;CHECK: vld3.32
+ %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(float* %A)
+ %tmp2 = extractvalue %struct.__neon_float32x2x3_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp1, 2
+ %tmp4 = add <2 x float> %tmp2, %tmp3
+ ret <2 x float> %tmp4
+}
+
+define <1 x i64> @vld3i64(i64* %A) nounwind {
+;CHECK: vld3i64:
+;CHECK: vld1.64
+ %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i64* %A)
+ %tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2
+ %tmp4 = add <1 x i64> %tmp2, %tmp3
+ ret <1 x i64> %tmp4
+}
+
+define <16 x i8> @vld3Qi8(i8* %A) nounwind {
+;CHECK: vld3Qi8:
+;CHECK: vld3.8
+;CHECK: vld3.8
+ %tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8* %A)
+ %tmp2 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 2
+ %tmp4 = add <16 x i8> %tmp2, %tmp3
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vld3Qi16(i16* %A) nounwind {
+;CHECK: vld3Qi16:
+;CHECK: vld3.16
+;CHECK: vld3.16
+ %tmp1 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16(i16* %A)
+ %tmp2 = extractvalue %struct.__neon_int16x8x3_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp1, 2
+ %tmp4 = add <8 x i16> %tmp2, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vld3Qi32(i32* %A) nounwind {
+;CHECK: vld3Qi32:
+;CHECK: vld3.32
+;CHECK: vld3.32
+ %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i32* %A)
+ %tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2
+ %tmp4 = add <4 x i32> %tmp2, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <4 x float> @vld3Qf(float* %A) nounwind {
+;CHECK: vld3Qf:
+;CHECK: vld3.32
+;CHECK: vld3.32
+ %tmp1 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32(float* %A)
+ %tmp2 = extractvalue %struct.__neon_float32x4x3_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp1, 2
+ %tmp4 = add <4 x float> %tmp2, %tmp3
+ ret <4 x float> %tmp4
+}
+
+declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*) nounwind readonly
+declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8*) nounwind readonly
+declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8*) nounwind readonly
+declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8*) nounwind readonly
+declare %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8*) nounwind readonly
+
+declare %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8*) nounwind readonly
+declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16(i8*) nounwind readonly
+declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8*) nounwind readonly
+declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32(i8*) nounwind readonly
diff --git a/test/CodeGen/ARM/vld4.ll b/test/CodeGen/ARM/vld4.ll
new file mode 100644
index 0000000..0624f29
--- /dev/null
+++ b/test/CodeGen/ARM/vld4.ll
@@ -0,0 +1,117 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
+%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
+%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
+%struct.__neon_float32x2x4_t = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> }
+%struct.__neon_int64x1x4_t = type { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> }
+
+%struct.__neon_int8x16x4_t = type { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }
+%struct.__neon_int16x8x4_t = type { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }
+%struct.__neon_int32x4x4_t = type { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> }
+%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
+
+define <8 x i8> @vld4i8(i8* %A) nounwind {
+;CHECK: vld4i8:
+;CHECK: vld4.8
+ %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A)
+ %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
+ %tmp4 = add <8 x i8> %tmp2, %tmp3
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vld4i16(i16* %A) nounwind {
+;CHECK: vld4i16:
+;CHECK: vld4.16
+ %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i16* %A)
+ %tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 2
+ %tmp4 = add <4 x i16> %tmp2, %tmp3
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vld4i32(i32* %A) nounwind {
+;CHECK: vld4i32:
+;CHECK: vld4.32
+ %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i32* %A)
+ %tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 2
+ %tmp4 = add <2 x i32> %tmp2, %tmp3
+ ret <2 x i32> %tmp4
+}
+
+define <2 x float> @vld4f(float* %A) nounwind {
+;CHECK: vld4f:
+;CHECK: vld4.32
+ %tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(float* %A)
+ %tmp2 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 2
+ %tmp4 = add <2 x float> %tmp2, %tmp3
+ ret <2 x float> %tmp4
+}
+
+define <1 x i64> @vld4i64(i64* %A) nounwind {
+;CHECK: vld4i64:
+;CHECK: vld1.64
+ %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i64* %A)
+ %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2
+ %tmp4 = add <1 x i64> %tmp2, %tmp3
+ ret <1 x i64> %tmp4
+}
+
+define <16 x i8> @vld4Qi8(i8* %A) nounwind {
+;CHECK: vld4Qi8:
+;CHECK: vld4.8
+;CHECK: vld4.8
+ %tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8* %A)
+ %tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2
+ %tmp4 = add <16 x i8> %tmp2, %tmp3
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vld4Qi16(i16* %A) nounwind {
+;CHECK: vld4Qi16:
+;CHECK: vld4.16
+;CHECK: vld4.16
+ %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i16* %A)
+ %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2
+ %tmp4 = add <8 x i16> %tmp2, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vld4Qi32(i32* %A) nounwind {
+;CHECK: vld4Qi32:
+;CHECK: vld4.32
+;CHECK: vld4.32
+ %tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32(i32* %A)
+ %tmp2 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 2
+ %tmp4 = add <4 x i32> %tmp2, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <4 x float> @vld4Qf(float* %A) nounwind {
+;CHECK: vld4Qf:
+;CHECK: vld4.32
+;CHECK: vld4.32
+ %tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(float* %A)
+ %tmp2 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 2
+ %tmp4 = add <4 x float> %tmp2, %tmp3
+ ret <4 x float> %tmp4
+}
+
+declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8*) nounwind readonly
+declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8*) nounwind readonly
+declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8*) nounwind readonly
+declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8*) nounwind readonly
+declare %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8*) nounwind readonly
+
+declare %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8*) nounwind readonly
+declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8*) nounwind readonly
+declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32(i8*) nounwind readonly
+declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(i8*) nounwind readonly
diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll
new file mode 100644
index 0000000..53881a3
--- /dev/null
+++ b/test/CodeGen/ARM/vldlane.ll
@@ -0,0 +1,328 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
+%struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> }
+%struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> }
+%struct.__neon_float32x2x2_t = type { <2 x float>, <2 x float> }
+
+%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> }
+%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
+%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
+
+define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vld2lanei8:
+;CHECK: vld2.8
+ %tmp1 = load <8 x i8>* %B
+ %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vld2lanei16:
+;CHECK: vld2.16
+ %tmp1 = load <4 x i16>* %B
+ %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 1
+ %tmp5 = add <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vld2lanei32:
+;CHECK: vld2.32
+ %tmp1 = load <2 x i32>* %B
+ %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1
+ %tmp5 = add <2 x i32> %tmp3, %tmp4
+ ret <2 x i32> %tmp5
+}
+
+define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vld2lanef:
+;CHECK: vld2.32
+ %tmp1 = load <2 x float>* %B
+ %tmp2 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 1
+ %tmp5 = add <2 x float> %tmp3, %tmp4
+ ret <2 x float> %tmp5
+}
+
+define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+;CHECK: vld2laneQi16:
+;CHECK: vld2.16
+ %tmp1 = load <8 x i16>* %B
+ %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+;CHECK: vld2laneQi32:
+;CHECK: vld2.32
+ %tmp1 = load <4 x i32>* %B
+ %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2)
+ %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind {
+;CHECK: vld2laneQf:
+;CHECK: vld2.32
+ %tmp1 = load <4 x float>* %B
+ %tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 1
+ %tmp5 = add <4 x float> %tmp3, %tmp4
+ ret <4 x float> %tmp5
+}
+
+declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind readonly
+declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8*, <4 x i16>, <4 x i16>, i32) nounwind readonly
+declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32) nounwind readonly
+declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(i8*, <2 x float>, <2 x float>, i32) nounwind readonly
+
+declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32) nounwind readonly
+declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32) nounwind readonly
+declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind readonly
+
+%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
+%struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> }
+%struct.__neon_int32x2x3_t = type { <2 x i32>, <2 x i32>, <2 x i32> }
+%struct.__neon_float32x2x3_t = type { <2 x float>, <2 x float>, <2 x float> }
+
+%struct.__neon_int16x8x3_t = type { <8 x i16>, <8 x i16>, <8 x i16> }
+%struct.__neon_int32x4x3_t = type { <4 x i32>, <4 x i32>, <4 x i32> }
+%struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
+
+define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vld3lanei8:
+;CHECK: vld3.8
+ %tmp1 = load <8 x i8>* %B
+ %tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2
+ %tmp6 = add <8 x i8> %tmp3, %tmp4
+ %tmp7 = add <8 x i8> %tmp5, %tmp6
+ ret <8 x i8> %tmp7
+}
+
+define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vld3lanei16:
+;CHECK: vld3.16
+ %tmp1 = load <4 x i16>* %B
+ %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 2
+ %tmp6 = add <4 x i16> %tmp3, %tmp4
+ %tmp7 = add <4 x i16> %tmp5, %tmp6
+ ret <4 x i16> %tmp7
+}
+
+define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vld3lanei32:
+;CHECK: vld3.32
+ %tmp1 = load <2 x i32>* %B
+ %tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 2
+ %tmp6 = add <2 x i32> %tmp3, %tmp4
+ %tmp7 = add <2 x i32> %tmp5, %tmp6
+ ret <2 x i32> %tmp7
+}
+
+define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vld3lanef:
+;CHECK: vld3.32
+ %tmp1 = load <2 x float>* %B
+ %tmp2 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 2
+ %tmp6 = add <2 x float> %tmp3, %tmp4
+ %tmp7 = add <2 x float> %tmp5, %tmp6
+ ret <2 x float> %tmp7
+}
+
+define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+;CHECK: vld3laneQi16:
+;CHECK: vld3.16
+ %tmp1 = load <8 x i16>* %B
+ %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2
+ %tmp6 = add <8 x i16> %tmp3, %tmp4
+ %tmp7 = add <8 x i16> %tmp5, %tmp6
+ ret <8 x i16> %tmp7
+}
+
+define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+;CHECK: vld3laneQi32:
+;CHECK: vld3.32
+ %tmp1 = load <4 x i32>* %B
+ %tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3)
+ %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 2
+ %tmp6 = add <4 x i32> %tmp3, %tmp4
+ %tmp7 = add <4 x i32> %tmp5, %tmp6
+ ret <4 x i32> %tmp7
+}
+
+define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind {
+;CHECK: vld3laneQf:
+;CHECK: vld3.32
+ %tmp1 = load <4 x float>* %B
+ %tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 2
+ %tmp6 = add <4 x float> %tmp3, %tmp4
+ %tmp7 = add <4 x float> %tmp5, %tmp6
+ ret <4 x float> %tmp7
+}
+
+declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind readonly
+declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind readonly
+declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind readonly
+declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32) nounwind readonly
+
+declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind readonly
+declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind readonly
+declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32) nounwind readonly
+
+%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
+%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
+%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
+%struct.__neon_float32x2x4_t = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> }
+
+%struct.__neon_int16x8x4_t = type { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }
+%struct.__neon_int32x4x4_t = type { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> }
+%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
+
+define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vld4lanei8:
+;CHECK: vld4.8
+ %tmp1 = load <8 x i8>* %B
+ %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
+ %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
+ %tmp7 = add <8 x i8> %tmp3, %tmp4
+ %tmp8 = add <8 x i8> %tmp5, %tmp6
+ %tmp9 = add <8 x i8> %tmp7, %tmp8
+ ret <8 x i8> %tmp9
+}
+
+define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vld4lanei16:
+;CHECK: vld4.16
+ %tmp1 = load <4 x i16>* %B
+ %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 2
+ %tmp6 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 3
+ %tmp7 = add <4 x i16> %tmp3, %tmp4
+ %tmp8 = add <4 x i16> %tmp5, %tmp6
+ %tmp9 = add <4 x i16> %tmp7, %tmp8
+ ret <4 x i16> %tmp9
+}
+
+define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vld4lanei32:
+;CHECK: vld4.32
+ %tmp1 = load <2 x i32>* %B
+ %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 2
+ %tmp6 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 3
+ %tmp7 = add <2 x i32> %tmp3, %tmp4
+ %tmp8 = add <2 x i32> %tmp5, %tmp6
+ %tmp9 = add <2 x i32> %tmp7, %tmp8
+ ret <2 x i32> %tmp9
+}
+
+define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vld4lanef:
+;CHECK: vld4.32
+ %tmp1 = load <2 x float>* %B
+ %tmp2 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 2
+ %tmp6 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 3
+ %tmp7 = add <2 x float> %tmp3, %tmp4
+ %tmp8 = add <2 x float> %tmp5, %tmp6
+ %tmp9 = add <2 x float> %tmp7, %tmp8
+ ret <2 x float> %tmp9
+}
+
+define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+;CHECK: vld4laneQi16:
+;CHECK: vld4.16
+ %tmp1 = load <8 x i16>* %B
+ %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 2
+ %tmp6 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 3
+ %tmp7 = add <8 x i16> %tmp3, %tmp4
+ %tmp8 = add <8 x i16> %tmp5, %tmp6
+ %tmp9 = add <8 x i16> %tmp7, %tmp8
+ ret <8 x i16> %tmp9
+}
+
+define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+;CHECK: vld4laneQi32:
+;CHECK: vld4.32
+ %tmp1 = load <4 x i32>* %B
+ %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 2
+ %tmp6 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 3
+ %tmp7 = add <4 x i32> %tmp3, %tmp4
+ %tmp8 = add <4 x i32> %tmp5, %tmp6
+ %tmp9 = add <4 x i32> %tmp7, %tmp8
+ ret <4 x i32> %tmp9
+}
+
+define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind {
+;CHECK: vld4laneQf:
+;CHECK: vld4.32
+ %tmp1 = load <4 x float>* %B
+ %tmp2 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
+ %tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 2
+ %tmp6 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 3
+ %tmp7 = add <4 x float> %tmp3, %tmp4
+ %tmp8 = add <4 x float> %tmp5, %tmp6
+ %tmp9 = add <4 x float> %tmp7, %tmp8
+ ret <4 x float> %tmp9
+}
+
+declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind readonly
+declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind readonly
+declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind readonly
+declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32) nounwind readonly
+
+declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind readonly
+declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind readonly
+declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) nounwind readonly
diff --git a/test/CodeGen/ARM/vminmax.ll b/test/CodeGen/ARM/vminmax.ll
new file mode 100644
index 0000000..e3527c1
--- /dev/null
+++ b/test/CodeGen/ARM/vminmax.ll
@@ -0,0 +1,293 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vmins8:
+;CHECK: vmin.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vmins16:
+;CHECK: vmin.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vmins32:
+;CHECK: vmin.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vminu8:
+;CHECK: vmin.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vminu16:
+;CHECK: vmin.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vminu32:
+;CHECK: vmin.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vminf32:
+;CHECK: vmin.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vminQs8:
+;CHECK: vmin.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vminQs16:
+;CHECK: vmin.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vminQs32:
+;CHECK: vmin.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vminQu8:
+;CHECK: vmin.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vminQu16:
+;CHECK: vmin.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vminQu32:
+;CHECK: vmin.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <4 x float> @vminQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vminQf32:
+;CHECK: vmin.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
+
+define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vmaxs8:
+;CHECK: vmax.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vmaxs16:
+;CHECK: vmax.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vmaxs32:
+;CHECK: vmax.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vmaxu8:
+;CHECK: vmax.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vmaxu16:
+;CHECK: vmax.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vmaxu32:
+;CHECK: vmax.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vmaxf32:
+;CHECK: vmax.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vmaxQs8:
+;CHECK: vmax.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vmaxQs16:
+;CHECK: vmax.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vmaxQs32:
+;CHECK: vmax.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vmaxQu8:
+;CHECK: vmax.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vmaxQu16:
+;CHECK: vmax.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vmaxQu32:
+;CHECK: vmax.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <4 x float> @vmaxQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vmaxQf32:
+;CHECK: vmax.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
diff --git a/test/CodeGen/ARM/vmla.ll b/test/CodeGen/ARM/vmla.ll
new file mode 100644
index 0000000..8405218
--- /dev/null
+++ b/test/CodeGen/ARM/vmla.ll
@@ -0,0 +1,193 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
+;CHECK: vmlai8:
+;CHECK: vmla.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = load <8 x i8>* %C
+ %tmp4 = mul <8 x i8> %tmp2, %tmp3
+ %tmp5 = add <8 x i8> %tmp1, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+;CHECK: vmlai16:
+;CHECK: vmla.i16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i16>* %C
+ %tmp4 = mul <4 x i16> %tmp2, %tmp3
+ %tmp5 = add <4 x i16> %tmp1, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+;CHECK: vmlai32:
+;CHECK: vmla.i32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i32>* %C
+ %tmp4 = mul <2 x i32> %tmp2, %tmp3
+ %tmp5 = add <2 x i32> %tmp1, %tmp4
+ ret <2 x i32> %tmp5
+}
+
+define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
+;CHECK: vmlaf32:
+;CHECK: vmla.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = load <2 x float>* %C
+ %tmp4 = mul <2 x float> %tmp2, %tmp3
+ %tmp5 = add <2 x float> %tmp1, %tmp4
+ ret <2 x float> %tmp5
+}
+
+define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
+;CHECK: vmlaQi8:
+;CHECK: vmla.i8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = load <16 x i8>* %C
+ %tmp4 = mul <16 x i8> %tmp2, %tmp3
+ %tmp5 = add <16 x i8> %tmp1, %tmp4
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
+;CHECK: vmlaQi16:
+;CHECK: vmla.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = load <8 x i16>* %C
+ %tmp4 = mul <8 x i16> %tmp2, %tmp3
+ %tmp5 = add <8 x i16> %tmp1, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
+;CHECK: vmlaQi32:
+;CHECK: vmla.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = mul <4 x i32> %tmp2, %tmp3
+ %tmp5 = add <4 x i32> %tmp1, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
+;CHECK: vmlaQf32:
+;CHECK: vmla.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = load <4 x float>* %C
+ %tmp4 = mul <4 x float> %tmp2, %tmp3
+ %tmp5 = add <4 x float> %tmp1, %tmp4
+ ret <4 x float> %tmp5
+}
+
+define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+;CHECK: vmlals8:
+;CHECK: vmlal.s8
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = load <8 x i8>* %C
+ %tmp4 = call <8 x i16> @llvm.arm.neon.vmlals.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+;CHECK: vmlals16:
+;CHECK: vmlal.s16
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i16>* %C
+ %tmp4 = call <4 x i32> @llvm.arm.neon.vmlals.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+;CHECK: vmlals32:
+;CHECK: vmlal.s32
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i32>* %C
+ %tmp4 = call <2 x i64> @llvm.arm.neon.vmlals.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
+ ret <2 x i64> %tmp4
+}
+
+define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+;CHECK: vmlalu8:
+;CHECK: vmlal.u8
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = load <8 x i8>* %C
+ %tmp4 = call <8 x i16> @llvm.arm.neon.vmlalu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+;CHECK: vmlalu16:
+;CHECK: vmlal.u16
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i16>* %C
+ %tmp4 = call <4 x i32> @llvm.arm.neon.vmlalu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vmlalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+;CHECK: vmlalu32:
+;CHECK: vmlal.u32
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i32>* %C
+ %tmp4 = call <2 x i64> @llvm.arm.neon.vmlalu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
+ ret <2 x i64> %tmp4
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlal_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmlal_lanes16
+; CHECK: vmlal.s16 q0, d2, d3[1]
+ %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vmlals.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmlal_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmlal_lanes32
+; CHECK: vmlal.s32 q0, d2, d3[1]
+ %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vmlals.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlal_laneu16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmlal_laneu16
+; CHECK: vmlal.u16 q0, d2, d3[1]
+ %0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vmlalu.v4i32(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmlal_laneu32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmlal_laneu32
+; CHECK: vmlal.u32 q0, d2, d3[1]
+ %0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vmlalu.v2i64(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <8 x i16> @llvm.arm.neon.vmlals.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmlals.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vmlals.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vmlalu.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmlalu.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vmlalu.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vmls.ll b/test/CodeGen/ARM/vmls.ll
new file mode 100644
index 0000000..c89552e
--- /dev/null
+++ b/test/CodeGen/ARM/vmls.ll
@@ -0,0 +1,193 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
+;CHECK: vmlsi8:
+;CHECK: vmls.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = load <8 x i8>* %C
+ %tmp4 = mul <8 x i8> %tmp2, %tmp3
+ %tmp5 = sub <8 x i8> %tmp1, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+;CHECK: vmlsi16:
+;CHECK: vmls.i16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i16>* %C
+ %tmp4 = mul <4 x i16> %tmp2, %tmp3
+ %tmp5 = sub <4 x i16> %tmp1, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+;CHECK: vmlsi32:
+;CHECK: vmls.i32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i32>* %C
+ %tmp4 = mul <2 x i32> %tmp2, %tmp3
+ %tmp5 = sub <2 x i32> %tmp1, %tmp4
+ ret <2 x i32> %tmp5
+}
+
+define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
+;CHECK: vmlsf32:
+;CHECK: vmls.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = load <2 x float>* %C
+ %tmp4 = mul <2 x float> %tmp2, %tmp3
+ %tmp5 = sub <2 x float> %tmp1, %tmp4
+ ret <2 x float> %tmp5
+}
+
+define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
+;CHECK: vmlsQi8:
+;CHECK: vmls.i8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = load <16 x i8>* %C
+ %tmp4 = mul <16 x i8> %tmp2, %tmp3
+ %tmp5 = sub <16 x i8> %tmp1, %tmp4
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
+;CHECK: vmlsQi16:
+;CHECK: vmls.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = load <8 x i16>* %C
+ %tmp4 = mul <8 x i16> %tmp2, %tmp3
+ %tmp5 = sub <8 x i16> %tmp1, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
+;CHECK: vmlsQi32:
+;CHECK: vmls.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = mul <4 x i32> %tmp2, %tmp3
+ %tmp5 = sub <4 x i32> %tmp1, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
+;CHECK: vmlsQf32:
+;CHECK: vmls.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = load <4 x float>* %C
+ %tmp4 = mul <4 x float> %tmp2, %tmp3
+ %tmp5 = sub <4 x float> %tmp1, %tmp4
+ ret <4 x float> %tmp5
+}
+
+define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+;CHECK: vmlsls8:
+;CHECK: vmlsl.s8
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = load <8 x i8>* %C
+ %tmp4 = call <8 x i16> @llvm.arm.neon.vmlsls.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+;CHECK: vmlsls16:
+;CHECK: vmlsl.s16
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i16>* %C
+ %tmp4 = call <4 x i32> @llvm.arm.neon.vmlsls.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+;CHECK: vmlsls32:
+;CHECK: vmlsl.s32
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i32>* %C
+ %tmp4 = call <2 x i64> @llvm.arm.neon.vmlsls.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
+ ret <2 x i64> %tmp4
+}
+
+define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+;CHECK: vmlslu8:
+;CHECK: vmlsl.u8
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = load <8 x i8>* %C
+ %tmp4 = call <8 x i16> @llvm.arm.neon.vmlslu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+;CHECK: vmlslu16:
+;CHECK: vmlsl.u16
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i16>* %C
+ %tmp4 = call <4 x i32> @llvm.arm.neon.vmlslu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vmlslu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+;CHECK: vmlslu32:
+;CHECK: vmlsl.u32
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i32>* %C
+ %tmp4 = call <2 x i64> @llvm.arm.neon.vmlslu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
+ ret <2 x i64> %tmp4
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlsl_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmlsl_lanes16
+; CHECK: vmlsl.s16 q0, d2, d3[1]
+ %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vmlsls.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmlsl_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmlsl_lanes32
+; CHECK: vmlsl.s32 q0, d2, d3[1]
+ %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vmlsls.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlsl_laneu16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmlsl_laneu16
+; CHECK: vmlsl.u16 q0, d2, d3[1]
+ %0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vmlslu.v4i32(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmlsl_laneu32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmlsl_laneu32
+; CHECK: vmlsl.u32 q0, d2, d3[1]
+ %0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vmlslu.v2i64(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <8 x i16> @llvm.arm.neon.vmlsls.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmlsls.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vmlsls.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vmlslu.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmlslu.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vmlslu.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll
new file mode 100644
index 0000000..e4368d6
--- /dev/null
+++ b/test/CodeGen/ARM/vmov.ll
@@ -0,0 +1,323 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @v_movi8() nounwind {
+;CHECK: v_movi8:
+;CHECK: vmov.i8
+ ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+}
+
+define <4 x i16> @v_movi16a() nounwind {
+;CHECK: v_movi16a:
+;CHECK: vmov.i16
+ ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
+}
+
+; 0x1000 = 4096
+define <4 x i16> @v_movi16b() nounwind {
+;CHECK: v_movi16b:
+;CHECK: vmov.i16
+ ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
+}
+
+define <2 x i32> @v_movi32a() nounwind {
+;CHECK: v_movi32a:
+;CHECK: vmov.i32
+ ret <2 x i32> < i32 32, i32 32 >
+}
+
+; 0x2000 = 8192
+define <2 x i32> @v_movi32b() nounwind {
+;CHECK: v_movi32b:
+;CHECK: vmov.i32
+ ret <2 x i32> < i32 8192, i32 8192 >
+}
+
+; 0x200000 = 2097152
+define <2 x i32> @v_movi32c() nounwind {
+;CHECK: v_movi32c:
+;CHECK: vmov.i32
+ ret <2 x i32> < i32 2097152, i32 2097152 >
+}
+
+; 0x20000000 = 536870912
+define <2 x i32> @v_movi32d() nounwind {
+;CHECK: v_movi32d:
+;CHECK: vmov.i32
+ ret <2 x i32> < i32 536870912, i32 536870912 >
+}
+
+; 0x20ff = 8447
+define <2 x i32> @v_movi32e() nounwind {
+;CHECK: v_movi32e:
+;CHECK: vmov.i32
+ ret <2 x i32> < i32 8447, i32 8447 >
+}
+
+; 0x20ffff = 2162687
+define <2 x i32> @v_movi32f() nounwind {
+;CHECK: v_movi32f:
+;CHECK: vmov.i32
+ ret <2 x i32> < i32 2162687, i32 2162687 >
+}
+
+; 0xff0000ff0000ffff = 18374687574888349695
+define <1 x i64> @v_movi64() nounwind {
+;CHECK: v_movi64:
+;CHECK: vmov.i64
+ ret <1 x i64> < i64 18374687574888349695 >
+}
+
+define <16 x i8> @v_movQi8() nounwind {
+;CHECK: v_movQi8:
+;CHECK: vmov.i8
+ ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+}
+
+define <8 x i16> @v_movQi16a() nounwind {
+;CHECK: v_movQi16a:
+;CHECK: vmov.i16
+ ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+}
+
+; 0x1000 = 4096
+define <8 x i16> @v_movQi16b() nounwind {
+;CHECK: v_movQi16b:
+;CHECK: vmov.i16
+ ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
+}
+
+define <4 x i32> @v_movQi32a() nounwind {
+;CHECK: v_movQi32a:
+;CHECK: vmov.i32
+ ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
+}
+
+; 0x2000 = 8192
+define <4 x i32> @v_movQi32b() nounwind {
+;CHECK: v_movQi32b:
+;CHECK: vmov.i32
+ ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
+}
+
+; 0x200000 = 2097152
+define <4 x i32> @v_movQi32c() nounwind {
+;CHECK: v_movQi32c:
+;CHECK: vmov.i32
+ ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
+}
+
+; 0x20000000 = 536870912
+define <4 x i32> @v_movQi32d() nounwind {
+;CHECK: v_movQi32d:
+;CHECK: vmov.i32
+ ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
+}
+
+; 0x20ff = 8447
+define <4 x i32> @v_movQi32e() nounwind {
+;CHECK: v_movQi32e:
+;CHECK: vmov.i32
+ ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
+}
+
+; 0x20ffff = 2162687
+define <4 x i32> @v_movQi32f() nounwind {
+;CHECK: v_movQi32f:
+;CHECK: vmov.i32
+ ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
+}
+
+; 0xff0000ff0000ffff = 18374687574888349695
+define <2 x i64> @v_movQi64() nounwind {
+;CHECK: v_movQi64:
+;CHECK: vmov.i64
+ ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
+}
+
+; Check for correct assembler printing for immediate values.
+%struct.int8x8_t = type { <8 x i8> }
+define arm_apcscc void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
+entry:
+;CHECK: vdupn128:
+;CHECK: vmov.i8 d0, #0x80
+ %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
+ store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, <8 x i8>* %0, align 8
+ ret void
+}
+
+define arm_apcscc void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
+entry:
+;CHECK: vdupnneg75:
+;CHECK: vmov.i8 d0, #0xB5
+ %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
+ store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, <8 x i8>* %0, align 8
+ ret void
+}
+
+define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
+;CHECK: vmovls8:
+;CHECK: vmovl.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vmovls.v8i16(<8 x i8> %tmp1)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
+;CHECK: vmovls16:
+;CHECK: vmovl.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16> %tmp1)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
+;CHECK: vmovls32:
+;CHECK: vmovl.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vmovls.v2i64(<2 x i32> %tmp1)
+ ret <2 x i64> %tmp2
+}
+
+define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
+;CHECK: vmovlu8:
+;CHECK: vmovl.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vmovlu.v8i16(<8 x i8> %tmp1)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
+;CHECK: vmovlu16:
+;CHECK: vmovl.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vmovlu.v4i32(<4 x i16> %tmp1)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
+;CHECK: vmovlu32:
+;CHECK: vmovl.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vmovlu.v2i64(<2 x i32> %tmp1)
+ ret <2 x i64> %tmp2
+}
+
+declare <8 x i16> @llvm.arm.neon.vmovls.v8i16(<8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmovls.v4i32(<4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vmovls.v2i64(<2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vmovlu.v8i16(<8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmovlu.v4i32(<4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vmovlu.v2i64(<2 x i32>) nounwind readnone
+
+define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
+;CHECK: vmovni16:
+;CHECK: vmovn.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vmovn.v8i8(<8 x i16> %tmp1)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
+;CHECK: vmovni32:
+;CHECK: vmovn.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vmovn.v4i16(<4 x i32> %tmp1)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
+;CHECK: vmovni64:
+;CHECK: vmovn.i64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vmovn.v2i32(<2 x i64> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vmovn.v8i8(<8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vmovn.v4i16(<4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vmovn.v2i32(<2 x i64>) nounwind readnone
+
+define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
+;CHECK: vqmovns16:
+;CHECK: vqmovn.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
+;CHECK: vqmovns32:
+;CHECK: vqmovn.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
+;CHECK: vqmovns64:
+;CHECK: vqmovn.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
+;CHECK: vqmovnu16:
+;CHECK: vqmovn.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
+;CHECK: vqmovnu32:
+;CHECK: vqmovn.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
+;CHECK: vqmovnu64:
+;CHECK: vqmovn.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
+;CHECK: vqmovuns16:
+;CHECK: vqmovun.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
+;CHECK: vqmovuns32:
+;CHECK: vqmovun.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
+;CHECK: vqmovuns64:
+;CHECK: vqmovun.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone
diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll
new file mode 100644
index 0000000..325da5d
--- /dev/null
+++ b/test/CodeGen/ARM/vmul.ll
@@ -0,0 +1,257 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vmuli8:
+;CHECK: vmul.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = mul <8 x i8> %tmp1, %tmp2
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vmuli16:
+;CHECK: vmul.i16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = mul <4 x i16> %tmp1, %tmp2
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vmuli32:
+;CHECK: vmul.i32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = mul <2 x i32> %tmp1, %tmp2
+ ret <2 x i32> %tmp3
+}
+
+define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vmulf32:
+;CHECK: vmul.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = mul <2 x float> %tmp1, %tmp2
+ ret <2 x float> %tmp3
+}
+
+define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vmulp8:
+;CHECK: vmul.p8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vmulQi8:
+;CHECK: vmul.i8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = mul <16 x i8> %tmp1, %tmp2
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vmulQi16:
+;CHECK: vmul.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = mul <8 x i16> %tmp1, %tmp2
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vmulQi32:
+;CHECK: vmul.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = mul <4 x i32> %tmp1, %tmp2
+ ret <4 x i32> %tmp3
+}
+
+define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vmulQf32:
+;CHECK: vmul.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = mul <4 x float> %tmp1, %tmp2
+ ret <4 x float> %tmp3
+}
+
+define <16 x i8> @vmulQp8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vmulQp8:
+;CHECK: vmul.p8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+
+define arm_aapcs_vfpcc <2 x float> @test_vmul_lanef32(<2 x float> %arg0_float32x2_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmul_lanef32:
+; CHECK: vmul.f32 d0, d0, d1[0]
+ %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <2 x i32> zeroinitializer ; <<2 x float>> [#uses=1]
+ %1 = fmul <2 x float> %0, %arg0_float32x2_t ; <<2 x float>> [#uses=1]
+ ret <2 x float> %1
+}
+
+define arm_aapcs_vfpcc <4 x i16> @test_vmul_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmul_lanes16:
+; CHECK: vmul.i16 d0, d0, d1[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses$
+ %1 = mul <4 x i16> %0, %arg0_int16x4_t ; <<4 x i16>> [#uses=1]
+ ret <4 x i16> %1
+}
+
+define arm_aapcs_vfpcc <2 x i32> @test_vmul_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmul_lanes32:
+; CHECK: vmul.i32 d0, d0, d1[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = mul <2 x i32> %0, %arg0_int32x2_t ; <<2 x i32>> [#uses=1]
+ ret <2 x i32> %1
+}
+
+define arm_aapcs_vfpcc <4 x float> @test_vmulQ_lanef32(<4 x float> %arg0_float32x4_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmulQ_lanef32:
+; CHECK: vmul.f32 q0, q0, d2[1]
+ %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>$
+ %1 = fmul <4 x float> %0, %arg0_float32x4_t ; <<4 x float>> [#uses=1]
+ ret <4 x float> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vmulQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmulQ_lanes16:
+; CHECK: vmul.i16 q0, q0, d2[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+ %1 = mul <8 x i16> %0, %arg0_int16x8_t ; <<8 x i16>> [#uses=1]
+ ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmulQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmulQ_lanes32:
+; CHECK: vmul.i32 q0, q0, d2[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses$
+ %1 = mul <4 x i32> %0, %arg0_int32x4_t ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vmulls8:
+;CHECK: vmull.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vmulls16:
+;CHECK: vmull.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vmulls32:
+;CHECK: vmull.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vmullu8:
+;CHECK: vmull.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vmullu16:
+;CHECK: vmull.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vmullu32:
+;CHECK: vmull.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vmullp8:
+;CHECK: vmull.p8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmull_lanes16
+; CHECK: vmull.s16 q0, d0, d1[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmull_lanes32
+; CHECK: vmull.s32 q0, d0, d1[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vmull_laneu16
+; CHECK: vmull.u16 q0, d0, d1[1]
+ %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %arg0_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vmull_laneu32
+; CHECK: vmull.u32 q0, d0, d1[1]
+ %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %arg0_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
diff --git a/test/CodeGen/ARM/vneg.ll b/test/CodeGen/ARM/vneg.ll
new file mode 100644
index 0000000..7764e87
--- /dev/null
+++ b/test/CodeGen/ARM/vneg.ll
@@ -0,0 +1,121 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
+;CHECK: vnegs8:
+;CHECK: vneg.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = sub <8 x i8> zeroinitializer, %tmp1
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
+;CHECK: vnegs16:
+;CHECK: vneg.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = sub <4 x i16> zeroinitializer, %tmp1
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
+;CHECK: vnegs32:
+;CHECK: vneg.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = sub <2 x i32> zeroinitializer, %tmp1
+ ret <2 x i32> %tmp2
+}
+
+define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
+;CHECK: vnegf32:
+;CHECK: vneg.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = sub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
+ ret <2 x float> %tmp2
+}
+
+define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
+;CHECK: vnegQs8:
+;CHECK: vneg.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = sub <16 x i8> zeroinitializer, %tmp1
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
+;CHECK: vnegQs16:
+;CHECK: vneg.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = sub <8 x i16> zeroinitializer, %tmp1
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
+;CHECK: vnegQs32:
+;CHECK: vneg.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = sub <4 x i32> zeroinitializer, %tmp1
+ ret <4 x i32> %tmp2
+}
+
+define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
+;CHECK: vnegQf32:
+;CHECK: vneg.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = sub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1
+ ret <4 x float> %tmp2
+}
+
+define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
+;CHECK: vqnegs8:
+;CHECK: vqneg.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
+;CHECK: vqnegs16:
+;CHECK: vqneg.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
+;CHECK: vqnegs32:
+;CHECK: vqneg.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
+;CHECK: vqnegQs8:
+;CHECK: vqneg.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
+;CHECK: vqnegQs16:
+;CHECK: vqneg.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind {
+;CHECK: vqnegQs32:
+;CHECK: vqneg.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1)
+ ret <4 x i32> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vpadal.ll b/test/CodeGen/ARM/vpadal.ll
new file mode 100644
index 0000000..7296e936
--- /dev/null
+++ b/test/CodeGen/ARM/vpadal.ll
@@ -0,0 +1,125 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vpadals8:
+;CHECK: vpadal.s8
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vpadals16:
+;CHECK: vpadal.s16
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vpadals32:
+;CHECK: vpadal.s32
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
+ ret <1 x i64> %tmp3
+}
+
+define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vpadalu8:
+;CHECK: vpadal.u8
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vpadalu16:
+;CHECK: vpadal.u16
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vpadalu32:
+;CHECK: vpadal.u32
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
+ ret <1 x i64> %tmp3
+}
+
+define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vpadalQs8:
+;CHECK: vpadal.s8
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vpadalQs16:
+;CHECK: vpadal.s16
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vpadalQs32:
+;CHECK: vpadal.s32
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vpadalQu8:
+;CHECK: vpadal.u8
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vpadalQu16:
+;CHECK: vpadal.u16
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vpadalQu32:
+;CHECK: vpadal.u32
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone
+
+declare <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vpadd.ll b/test/CodeGen/ARM/vpadd.ll
new file mode 100644
index 0000000..2125573
--- /dev/null
+++ b/test/CodeGen/ARM/vpadd.ll
@@ -0,0 +1,155 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vpaddi8:
+;CHECK: vpadd.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vpaddi16:
+;CHECK: vpadd.i16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vpaddi32:
+;CHECK: vpadd.i32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vpaddf32:
+;CHECK: vpadd.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
+;CHECK: vpaddls8:
+;CHECK: vpaddl.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
+;CHECK: vpaddls16:
+;CHECK: vpaddl.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
+;CHECK: vpaddls32:
+;CHECK: vpaddl.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1)
+ ret <1 x i64> %tmp2
+}
+
+define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
+;CHECK: vpaddlu8:
+;CHECK: vpaddl.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
+;CHECK: vpaddlu16:
+;CHECK: vpaddl.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
+;CHECK: vpaddlu32:
+;CHECK: vpaddl.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1)
+ ret <1 x i64> %tmp2
+}
+
+define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
+;CHECK: vpaddlQs8:
+;CHECK: vpaddl.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
+;CHECK: vpaddlQs16:
+;CHECK: vpaddl.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
+;CHECK: vpaddlQs32:
+;CHECK: vpaddl.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1)
+ ret <2 x i64> %tmp2
+}
+
+define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
+;CHECK: vpaddlQu8:
+;CHECK: vpaddl.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
+;CHECK: vpaddlQu16:
+;CHECK: vpaddl.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind {
+;CHECK: vpaddlQu32:
+;CHECK: vpaddl.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
+ ret <2 x i64> %tmp2
+}
+
+declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) nounwind readnone
+
+declare <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vpminmax.ll b/test/CodeGen/ARM/vpminmax.ll
new file mode 100644
index 0000000..b75bcc9
--- /dev/null
+++ b/test/CodeGen/ARM/vpminmax.ll
@@ -0,0 +1,147 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vpmins8:
+;CHECK: vpmin.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vpmins16:
+;CHECK: vpmin.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vpmins32:
+;CHECK: vpmin.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vpminu8:
+;CHECK: vpmin.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vpminu16:
+;CHECK: vpmin.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vpminu32:
+;CHECK: vpmin.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <2 x float> @vpminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vpminf32:
+;CHECK: vpmin.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vpmaxs8:
+;CHECK: vpmax.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vpmaxs16:
+;CHECK: vpmax.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vpmaxs32:
+;CHECK: vpmax.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vpmaxu8:
+;CHECK: vpmax.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vpmaxu16:
+;CHECK: vpmax.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vpmaxu32:
+;CHECK: vpmax.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <2 x float> @vpmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vpmaxf32:
+;CHECK: vpmax.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float>, <2 x float>) nounwind readnone
diff --git a/test/CodeGen/ARM/vqadd.ll b/test/CodeGen/ARM/vqadd.ll
new file mode 100644
index 0000000..a1669b6
--- /dev/null
+++ b/test/CodeGen/ARM/vqadd.ll
@@ -0,0 +1,165 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vqadds8:
+;CHECK: vqadd.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vqadds16:
+;CHECK: vqadd.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vqadds32:
+;CHECK: vqadd.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vqadds64:
+;CHECK: vqadd.s64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+ ret <1 x i64> %tmp3
+}
+
+define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vqaddu8:
+;CHECK: vqadd.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vqaddu16:
+;CHECK: vqadd.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vqaddu32:
+;CHECK: vqadd.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vqaddu64:
+;CHECK: vqadd.u64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+ ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vqaddQs8:
+;CHECK: vqadd.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vqaddQs16:
+;CHECK: vqadd.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vqaddQs32:
+;CHECK: vqadd.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vqaddQs64:
+;CHECK: vqadd.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vqaddQu8:
+;CHECK: vqadd.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vqaddQu16:
+;CHECK: vqadd.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vqaddQu32:
+;CHECK: vqadd.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vqaddQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vqaddQu64:
+;CHECK: vqadd.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
diff --git a/test/CodeGen/ARM/vqdmul.ll b/test/CodeGen/ARM/vqdmul.ll
new file mode 100644
index 0000000..8dcc7f7
--- /dev/null
+++ b/test/CodeGen/ARM/vqdmul.ll
@@ -0,0 +1,281 @@
+; RUN: llc -mattr=+neon < %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv7-elf"
+
+define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vqdmulhs16:
+;CHECK: vqdmulh.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vqdmulhs32:
+;CHECK: vqdmulh.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vqdmulhQs16:
+;CHECK: vqdmulh.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vqdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vqdmulhQs32:
+;CHECK: vqdmulh.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqdmulhQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmulhQ_lanes16
+; CHECK: vqdmulh.s16 q0, q0, d2[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> ; <<8 x i16>> [#uses=1]
+ %1 = tail call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %arg0_int16x8_t, <8 x i16> %0) ; <<8 x i16>> [#uses=1]
+ ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmulhQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmulhQ_lanes32
+; CHECK: vqdmulh.s32 q0, q0, d2[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <4 x i16> @test_vqdmulh_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmulh_lanes16
+; CHECK: vqdmulh.s16 d0, d0, d1[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i16>> [#uses=1]
+ ret <4 x i16> %1
+}
+
+define arm_aapcs_vfpcc <2 x i32> @test_vqdmulh_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmulh_lanes32
+; CHECK: vqdmulh.s32 d0, d0, d1[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i32>> [#uses=1]
+ ret <2 x i32> %1
+}
+
+declare <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vqrdmulhs16:
+;CHECK: vqrdmulh.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vqrdmulhs32:
+;CHECK: vqrdmulh.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vqrdmulhQs16:
+;CHECK: vqrdmulh.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vqrdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vqrdmulhQs32:
+;CHECK: vqrdmulh.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vqRdmulhQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vqRdmulhQ_lanes16
+; CHECK: vqrdmulh.s16 q0, q0, d2[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> ; <<8 x i16>> [#uses=1]
+ %1 = tail call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %arg0_int16x8_t, <8 x i16> %0) ; <<8 x i16>> [#uses=1]
+ ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqRdmulhQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vqRdmulhQ_lanes32
+; CHECK: vqrdmulh.s32 q0, q0, d2[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <4 x i16> @test_vqRdmulh_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vqRdmulh_lanes16
+; CHECK: vqrdmulh.s16 d0, d0, d1[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i16>> [#uses=1]
+ ret <4 x i16> %1
+}
+
+define arm_aapcs_vfpcc <2 x i32> @test_vqRdmulh_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vqRdmulh_lanes32
+; CHECK: vqrdmulh.s32 d0, d0, d1[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i32>> [#uses=1]
+ ret <2 x i32> %1
+}
+
+declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vqdmulls16:
+;CHECK: vqdmull.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vqdmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vqdmulls32:
+;CHECK: vqdmull.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmull_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmull_lanes16
+; CHECK: vqdmull.s16 q0, d0, d1[1]
+ %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vqdmull_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmull_lanes32
+; CHECK: vqdmull.s32 q0, d0, d1[1]
+ %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+define <4 x i32> @vqdmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+;CHECK: vqdmlals16:
+;CHECK: vqdmlal.s16
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i16>* %C
+ %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmlal.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vqdmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+;CHECK: vqdmlals32:
+;CHECK: vqdmlal.s32
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i32>* %C
+ %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmlal.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
+ ret <2 x i64> %tmp4
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmlal_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmlal_lanes16
+; CHECK: vqdmlal.s16 q0, d2, d3[1]
+ %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vqdmlal.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vqdmlal_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmlal_lanes32
+; CHECK: vqdmlal.s32 q0, d2, d3[1]
+ %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vqdmlal.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <4 x i32> @llvm.arm.neon.vqdmlal.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqdmlal.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
+
+define <4 x i32> @vqdmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+;CHECK: vqdmlsls16:
+;CHECK: vqdmlsl.s16
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i16>* %C
+ %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vqdmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+;CHECK: vqdmlsls32:
+;CHECK: vqdmlsl.s32
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i32>* %C
+ %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3)
+ ret <2 x i64> %tmp4
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vqdmlsl_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmlsl_lanes16
+; CHECK: vqdmlsl.s16 q0, d2, d3[1]
+ %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+ %1 = tail call <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vqdmlsl_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {
+entry:
+; CHECK: test_vqdmlsl_lanes32
+; CHECK: vqdmlsl.s32 q0, d2, d3[1]
+ %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+ %1 = tail call <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %1
+}
+
+declare <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vqshl.ll b/test/CodeGen/ARM/vqshl.ll
new file mode 100644
index 0000000..e4d29a3
--- /dev/null
+++ b/test/CodeGen/ARM/vqshl.ll
@@ -0,0 +1,531 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vqshls8:
+;CHECK: vqshl.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vqshls16:
+;CHECK: vqshl.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vqshls32:
+;CHECK: vqshl.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vqshls64:
+;CHECK: vqshl.s64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+ ret <1 x i64> %tmp3
+}
+
+define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vqshlu8:
+;CHECK: vqshl.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vqshlu16:
+;CHECK: vqshl.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vqshlu32:
+;CHECK: vqshl.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vqshlu64:
+;CHECK: vqshl.u64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+ ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vqshlQs8:
+;CHECK: vqshl.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vqshlQs16:
+;CHECK: vqshl.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vqshlQs32:
+;CHECK: vqshl.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vqshlQs64:
+;CHECK: vqshl.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vqshlQu8:
+;CHECK: vqshl.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vqshlQu16:
+;CHECK: vqshl.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vqshlQu32:
+;CHECK: vqshl.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vqshlQu64:
+;CHECK: vqshl.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind {
+;CHECK: vqshls_n8:
+;CHECK: vqshl.s8{{.*#7}}
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind {
+;CHECK: vqshls_n16:
+;CHECK: vqshl.s16{{.*#15}}
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind {
+;CHECK: vqshls_n32:
+;CHECK: vqshl.s32{{.*#31}}
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
+ ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind {
+;CHECK: vqshls_n64:
+;CHECK: vqshl.s64{{.*#63}}
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
+ ret <1 x i64> %tmp2
+}
+
+define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind {
+;CHECK: vqshlu_n8:
+;CHECK: vqshl.u8{{.*#7}}
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind {
+;CHECK: vqshlu_n16:
+;CHECK: vqshl.u16{{.*#15}}
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind {
+;CHECK: vqshlu_n32:
+;CHECK: vqshl.u32{{.*#31}}
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
+ ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind {
+;CHECK: vqshlu_n64:
+;CHECK: vqshl.u64{{.*#63}}
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
+ ret <1 x i64> %tmp2
+}
+
+define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind {
+;CHECK: vqshlsu_n8:
+;CHECK: vqshlu.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind {
+;CHECK: vqshlsu_n16:
+;CHECK: vqshlu.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind {
+;CHECK: vqshlsu_n32:
+;CHECK: vqshlu.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
+ ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind {
+;CHECK: vqshlsu_n64:
+;CHECK: vqshlu.s64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
+ ret <1 x i64> %tmp2
+}
+
+define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind {
+;CHECK: vqshlQs_n8:
+;CHECK: vqshl.s8{{.*#7}}
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind {
+;CHECK: vqshlQs_n16:
+;CHECK: vqshl.s16{{.*#15}}
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind {
+;CHECK: vqshlQs_n32:
+;CHECK: vqshl.s32{{.*#31}}
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind {
+;CHECK: vqshlQs_n64:
+;CHECK: vqshl.s64{{.*#63}}
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
+ ret <2 x i64> %tmp2
+}
+
+define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind {
+;CHECK: vqshlQu_n8:
+;CHECK: vqshl.u8{{.*#7}}
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind {
+;CHECK: vqshlQu_n16:
+;CHECK: vqshl.u16{{.*#15}}
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind {
+;CHECK: vqshlQu_n32:
+;CHECK: vqshl.u32{{.*#31}}
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind {
+;CHECK: vqshlQu_n64:
+;CHECK: vqshl.u64{{.*#63}}
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
+ ret <2 x i64> %tmp2
+}
+
+define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind {
+;CHECK: vqshlQsu_n8:
+;CHECK: vqshlu.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind {
+;CHECK: vqshlQsu_n16:
+;CHECK: vqshlu.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind {
+;CHECK: vqshlQsu_n32:
+;CHECK: vqshlu.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vqshlQsu_n64(<2 x i64>* %A) nounwind {
+;CHECK: vqshlQsu_n64:
+;CHECK: vqshlu.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
+ ret <2 x i64> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vqrshls8:
+;CHECK: vqrshl.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vqrshls16:
+;CHECK: vqrshl.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vqrshls32:
+;CHECK: vqrshl.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vqrshls64:
+;CHECK: vqrshl.s64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+ ret <1 x i64> %tmp3
+}
+
+define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vqrshlu8:
+;CHECK: vqrshl.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vqrshlu16:
+;CHECK: vqrshl.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vqrshlu32:
+;CHECK: vqrshl.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vqrshlu64:
+;CHECK: vqrshl.u64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+ ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vqrshlQs8:
+;CHECK: vqrshl.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vqrshlQs16:
+;CHECK: vqrshl.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vqrshlQs32:
+;CHECK: vqrshl.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vqrshlQs64:
+;CHECK: vqrshl.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vqrshlQu8:
+;CHECK: vqrshl.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vqrshlQu16:
+;CHECK: vqrshl.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vqrshlQu32:
+;CHECK: vqrshl.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vqrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vqrshlQu64:
+;CHECK: vqrshl.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
diff --git a/test/CodeGen/ARM/vqshrn.ll b/test/CodeGen/ARM/vqshrn.ll
new file mode 100644
index 0000000..5da7943
--- /dev/null
+++ b/test/CodeGen/ARM/vqshrn.ll
@@ -0,0 +1,169 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
+;CHECK: vqshrns8:
+;CHECK: vqshrn.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
+;CHECK: vqshrns16:
+;CHECK: vqshrn.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
+;CHECK: vqshrns32:
+;CHECK: vqshrn.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+ ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
+;CHECK: vqshrnu8:
+;CHECK: vqshrn.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
+;CHECK: vqshrnu16:
+;CHECK: vqshrn.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
+;CHECK: vqshrnu32:
+;CHECK: vqshrn.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+ ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
+;CHECK: vqshruns8:
+;CHECK: vqshrun.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
+;CHECK: vqshruns16:
+;CHECK: vqshrun.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind {
+;CHECK: vqshruns32:
+;CHECK: vqshrun.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+ ret <2 x i32> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
+;CHECK: vqrshrns8:
+;CHECK: vqrshrn.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
+;CHECK: vqrshrns16:
+;CHECK: vqrshrn.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
+;CHECK: vqrshrns32:
+;CHECK: vqrshrn.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+ ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
+;CHECK: vqrshrnu8:
+;CHECK: vqrshrn.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
+;CHECK: vqrshrnu16:
+;CHECK: vqrshrn.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
+;CHECK: vqrshrnu32:
+;CHECK: vqrshrn.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+ ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
+;CHECK: vqrshruns8:
+;CHECK: vqrshrun.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
+;CHECK: vqrshruns16:
+;CHECK: vqrshrun.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind {
+;CHECK: vqrshruns32:
+;CHECK: vqrshrun.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+ ret <2 x i32> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
diff --git a/test/CodeGen/ARM/vqsub.ll b/test/CodeGen/ARM/vqsub.ll
new file mode 100644
index 0000000..4231fca
--- /dev/null
+++ b/test/CodeGen/ARM/vqsub.ll
@@ -0,0 +1,165 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vqsubs8:
+;CHECK: vqsub.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vqsubs16:
+;CHECK: vqsub.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vqsubs32:
+;CHECK: vqsub.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vqsubs64:
+;CHECK: vqsub.s64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+ ret <1 x i64> %tmp3
+}
+
+define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vqsubu8:
+;CHECK: vqsub.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vqsubu16:
+;CHECK: vqsub.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vqsubu32:
+;CHECK: vqsub.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vqsubu64:
+;CHECK: vqsub.u64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+ ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vqsubQs8:
+;CHECK: vqsub.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vqsubQs16:
+;CHECK: vqsub.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vqsubQs32:
+;CHECK: vqsub.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vqsubQs64:
+;CHECK: vqsub.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vqsubQu8:
+;CHECK: vqsub.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vqsubQu16:
+;CHECK: vqsub.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vqsubQu32:
+;CHECK: vqsub.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vqsubQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vqsubQu64:
+;CHECK: vqsub.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
diff --git a/test/CodeGen/ARM/vrec.ll b/test/CodeGen/ARM/vrec.ll
new file mode 100644
index 0000000..99989e9
--- /dev/null
+++ b/test/CodeGen/ARM/vrec.ll
@@ -0,0 +1,119 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind {
+;CHECK: vrecpei32:
+;CHECK: vrecpe.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind {
+;CHECK: vrecpeQi32:
+;CHECK: vrecpe.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x float> @vrecpef32(<2 x float>* %A) nounwind {
+;CHECK: vrecpef32:
+;CHECK: vrecpe.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
+ ret <2 x float> %tmp2
+}
+
+define <4 x float> @vrecpeQf32(<4 x float>* %A) nounwind {
+;CHECK: vrecpeQf32:
+;CHECK: vrecpe.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
+ ret <4 x float> %tmp2
+}
+
+declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone
+
+declare <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
+
+define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vrecpsf32:
+;CHECK: vrecps.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+define <4 x float> @vrecpsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vrecpsQf32:
+;CHECK: vrecps.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
+}
+
+declare <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
+
+define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
+;CHECK: vrsqrtei32:
+;CHECK: vrsqrte.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
+;CHECK: vrsqrteQi32:
+;CHECK: vrsqrte.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
+;CHECK: vrsqrtef32:
+;CHECK: vrsqrte.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
+ ret <2 x float> %tmp2
+}
+
+define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind {
+;CHECK: vrsqrteQf32:
+;CHECK: vrsqrte.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
+ ret <4 x float> %tmp2
+}
+
+declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>) nounwind readnone
+
+declare <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
+
+define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vrsqrtsf32:
+;CHECK: vrsqrts.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+define <4 x float> @vrsqrtsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vrsqrtsQf32:
+;CHECK: vrsqrts.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
+}
+
+declare <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
diff --git a/test/CodeGen/ARM/vrev.ll b/test/CodeGen/ARM/vrev.ll
new file mode 100644
index 0000000..f0a04a4
--- /dev/null
+++ b/test/CodeGen/ARM/vrev.ll
@@ -0,0 +1,113 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define arm_apcscc <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
+;CHECK: test_vrev64D8:
+;CHECK: vrev64.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x i8> %tmp2
+}
+
+define arm_apcscc <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
+;CHECK: test_vrev64D16:
+;CHECK: vrev64.16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x i16> %tmp2
+}
+
+define arm_apcscc <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
+;CHECK: test_vrev64D32:
+;CHECK: vrev64.32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
+ ret <2 x i32> %tmp2
+}
+
+define arm_apcscc <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
+;CHECK: test_vrev64Df:
+;CHECK: vrev64.32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
+ ret <2 x float> %tmp2
+}
+
+define arm_apcscc <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
+;CHECK: test_vrev64Q8:
+;CHECK: vrev64.8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
+ ret <16 x i8> %tmp2
+}
+
+define arm_apcscc <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
+;CHECK: test_vrev64Q16:
+;CHECK: vrev64.16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+ ret <8 x i16> %tmp2
+}
+
+define arm_apcscc <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
+;CHECK: test_vrev64Q32:
+;CHECK: vrev64.32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+ ret <4 x i32> %tmp2
+}
+
+define arm_apcscc <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
+;CHECK: test_vrev64Qf:
+;CHECK: vrev64.32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+ ret <4 x float> %tmp2
+}
+
+define arm_apcscc <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
+;CHECK: test_vrev32D8:
+;CHECK: vrev32.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+ ret <8 x i8> %tmp2
+}
+
+define arm_apcscc <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
+;CHECK: test_vrev32D16:
+;CHECK: vrev32.16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+ ret <4 x i16> %tmp2
+}
+
+define arm_apcscc <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
+;CHECK: test_vrev32Q8:
+;CHECK: vrev32.8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
+ ret <16 x i8> %tmp2
+}
+
+define arm_apcscc <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
+;CHECK: test_vrev32Q16:
+;CHECK: vrev32.16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+ ret <8 x i16> %tmp2
+}
+
+define arm_apcscc <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
+;CHECK: test_vrev16D8:
+;CHECK: vrev16.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+ ret <8 x i8> %tmp2
+}
+
+define arm_apcscc <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
+;CHECK: test_vrev16Q8:
+;CHECK: vrev16.8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
+ ret <16 x i8> %tmp2
+}
diff --git a/test/CodeGen/ARM/vshift.ll b/test/CodeGen/ARM/vshift.ll
new file mode 100644
index 0000000..f3cbec7
--- /dev/null
+++ b/test/CodeGen/ARM/vshift.ll
@@ -0,0 +1,432 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vshls8:
+;CHECK: vshl.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = shl <8 x i8> %tmp1, %tmp2
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vshls16:
+;CHECK: vshl.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = shl <4 x i16> %tmp1, %tmp2
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vshls32:
+;CHECK: vshl.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = shl <2 x i32> %tmp1, %tmp2
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vshls64:
+;CHECK: vshl.u64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = shl <1 x i64> %tmp1, %tmp2
+ ret <1 x i64> %tmp3
+}
+
+define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
+;CHECK: vshli8:
+;CHECK: vshl.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
+;CHECK: vshli16:
+;CHECK: vshl.i16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
+;CHECK: vshli32:
+;CHECK: vshl.i32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 >
+ ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
+;CHECK: vshli64:
+;CHECK: vshl.i64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = shl <1 x i64> %tmp1, < i64 63 >
+ ret <1 x i64> %tmp2
+}
+
+define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vshlQs8:
+;CHECK: vshl.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = shl <16 x i8> %tmp1, %tmp2
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vshlQs16:
+;CHECK: vshl.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = shl <8 x i16> %tmp1, %tmp2
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vshlQs32:
+;CHECK: vshl.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = shl <4 x i32> %tmp1, %tmp2
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vshlQs64:
+;CHECK: vshl.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = shl <2 x i64> %tmp1, %tmp2
+ ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
+;CHECK: vshlQi8:
+;CHECK: vshl.i8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
+;CHECK: vshlQi16:
+;CHECK: vshl.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
+;CHECK: vshlQi32:
+;CHECK: vshl.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
+;CHECK: vshlQi64:
+;CHECK: vshl.i64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 >
+ ret <2 x i64> %tmp2
+}
+
+define <8 x i8> @vlshru8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vlshru8:
+;CHECK: vneg.s8
+;CHECK: vshl.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = lshr <8 x i8> %tmp1, %tmp2
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vlshru16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vlshru16:
+;CHECK: vneg.s16
+;CHECK: vshl.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = lshr <4 x i16> %tmp1, %tmp2
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vlshru32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vlshru32:
+;CHECK: vneg.s32
+;CHECK: vshl.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = lshr <2 x i32> %tmp1, %tmp2
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vlshru64:
+;CHECK: vsub.i64
+;CHECK: vshl.u64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = lshr <1 x i64> %tmp1, %tmp2
+ ret <1 x i64> %tmp3
+}
+
+define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind {
+;CHECK: vlshri8:
+;CHECK: vshr.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = lshr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind {
+;CHECK: vlshri16:
+;CHECK: vshr.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = lshr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind {
+;CHECK: vlshri32:
+;CHECK: vshr.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = lshr <2 x i32> %tmp1, < i32 32, i32 32 >
+ ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vlshri64(<1 x i64>* %A) nounwind {
+;CHECK: vlshri64:
+;CHECK: vshr.u64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = lshr <1 x i64> %tmp1, < i64 64 >
+ ret <1 x i64> %tmp2
+}
+
+define <16 x i8> @vlshrQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vlshrQu8:
+;CHECK: vneg.s8
+;CHECK: vshl.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = lshr <16 x i8> %tmp1, %tmp2
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vlshrQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vlshrQu16:
+;CHECK: vneg.s16
+;CHECK: vshl.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = lshr <8 x i16> %tmp1, %tmp2
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vlshrQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vlshrQu32:
+;CHECK: vneg.s32
+;CHECK: vshl.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = lshr <4 x i32> %tmp1, %tmp2
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vlshrQu64:
+;CHECK: vsub.i64
+;CHECK: vshl.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = lshr <2 x i64> %tmp1, %tmp2
+ ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind {
+;CHECK: vlshrQi8:
+;CHECK: vshr.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = lshr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind {
+;CHECK: vlshrQi16:
+;CHECK: vshr.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = lshr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind {
+;CHECK: vlshrQi32:
+;CHECK: vshr.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = lshr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vlshrQi64(<2 x i64>* %A) nounwind {
+;CHECK: vlshrQi64:
+;CHECK: vshr.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = lshr <2 x i64> %tmp1, < i64 64, i64 64 >
+ ret <2 x i64> %tmp2
+}
+
+; Example that requires splitting and expanding a vector shift.
+define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
+entry:
+ %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %shr
+}
+
+define <8 x i8> @vashrs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vashrs8:
+;CHECK: vneg.s8
+;CHECK: vshl.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = ashr <8 x i8> %tmp1, %tmp2
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vashrs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vashrs16:
+;CHECK: vneg.s16
+;CHECK: vshl.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = ashr <4 x i16> %tmp1, %tmp2
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vashrs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vashrs32:
+;CHECK: vneg.s32
+;CHECK: vshl.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = ashr <2 x i32> %tmp1, %tmp2
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vashrs64:
+;CHECK: vsub.i64
+;CHECK: vshl.s64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = ashr <1 x i64> %tmp1, %tmp2
+ ret <1 x i64> %tmp3
+}
+
+define <8 x i8> @vashri8(<8 x i8>* %A) nounwind {
+;CHECK: vashri8:
+;CHECK: vshr.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = ashr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vashri16(<4 x i16>* %A) nounwind {
+;CHECK: vashri16:
+;CHECK: vshr.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = ashr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vashri32(<2 x i32>* %A) nounwind {
+;CHECK: vashri32:
+;CHECK: vshr.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = ashr <2 x i32> %tmp1, < i32 32, i32 32 >
+ ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vashri64(<1 x i64>* %A) nounwind {
+;CHECK: vashri64:
+;CHECK: vshr.s64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = ashr <1 x i64> %tmp1, < i64 64 >
+ ret <1 x i64> %tmp2
+}
+
+define <16 x i8> @vashrQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vashrQs8:
+;CHECK: vneg.s8
+;CHECK: vshl.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = ashr <16 x i8> %tmp1, %tmp2
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vashrQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vashrQs16:
+;CHECK: vneg.s16
+;CHECK: vshl.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = ashr <8 x i16> %tmp1, %tmp2
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vashrQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vashrQs32:
+;CHECK: vneg.s32
+;CHECK: vshl.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = ashr <4 x i32> %tmp1, %tmp2
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vashrQs64:
+;CHECK: vsub.i64
+;CHECK: vshl.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = ashr <2 x i64> %tmp1, %tmp2
+ ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind {
+;CHECK: vashrQi8:
+;CHECK: vshr.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = ashr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind {
+;CHECK: vashrQi16:
+;CHECK: vshr.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = ashr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind {
+;CHECK: vashrQi32:
+;CHECK: vshr.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = ashr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vashrQi64(<2 x i64>* %A) nounwind {
+;CHECK: vashrQi64:
+;CHECK: vshr.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = ashr <2 x i64> %tmp1, < i64 64, i64 64 >
+ ret <2 x i64> %tmp2
+}
diff --git a/test/CodeGen/ARM/vshiftins.ll b/test/CodeGen/ARM/vshiftins.ll
new file mode 100644
index 0000000..3a4f857
--- /dev/null
+++ b/test/CodeGen/ARM/vshiftins.ll
@@ -0,0 +1,155 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vsli8:
+;CHECK: vsli.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vsli16:
+;CHECK: vsli.16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vsli32:
+;CHECK: vsli.32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 31, i32 31 >)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vsli64:
+;CHECK: vsli.64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 63 >)
+ ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vsliQ8:
+;CHECK: vsli.8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vsliQ16:
+;CHECK: vsli.16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vsliQ32:
+;CHECK: vsli.32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vsliQ64:
+;CHECK: vsli.64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 63, i64 63 >)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vsri8:
+;CHECK: vsri.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vsri16:
+;CHECK: vsri.16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vsri32:
+;CHECK: vsri.32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vsri64:
+;CHECK: vsri.64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 -64 >)
+ ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vsriQ8:
+;CHECK: vsri.8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vsriQ16:
+;CHECK: vsri.16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vsriQ32:
+;CHECK: vsri.32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vsriQ64:
+;CHECK: vsri.64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64>, <1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
diff --git a/test/CodeGen/ARM/vshl.ll b/test/CodeGen/ARM/vshl.ll
new file mode 100644
index 0000000..818e71b
--- /dev/null
+++ b/test/CodeGen/ARM/vshl.ll
@@ -0,0 +1,654 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vshls8:
+;CHECK: vshl.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vshls16:
+;CHECK: vshl.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vshls32:
+;CHECK: vshl.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vshls64:
+;CHECK: vshl.s64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+ ret <1 x i64> %tmp3
+}
+
+define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vshlu8:
+;CHECK: vshl.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vshlu16:
+;CHECK: vshl.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vshlu32:
+;CHECK: vshl.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vshlu64:
+;CHECK: vshl.u64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+ ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vshlQs8:
+;CHECK: vshl.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vshlQs16:
+;CHECK: vshl.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vshlQs32:
+;CHECK: vshl.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vshlQs64:
+;CHECK: vshl.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vshlQu8:
+;CHECK: vshl.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vshlQu16:
+;CHECK: vshl.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vshlQu32:
+;CHECK: vshl.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vshlQu64:
+;CHECK: vshl.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+; For left shifts by immediates, the signedness is irrelevant.
+; Test a mix of both signed and unsigned intrinsics.
+
+define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
+;CHECK: vshli8:
+;CHECK: vshl.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
+;CHECK: vshli16:
+;CHECK: vshl.i16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
+;CHECK: vshli32:
+;CHECK: vshl.i32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
+ ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
+;CHECK: vshli64:
+;CHECK: vshl.i64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
+ ret <1 x i64> %tmp2
+}
+
+define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
+;CHECK: vshlQi8:
+;CHECK: vshl.i8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
+;CHECK: vshlQi16:
+;CHECK: vshl.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
+;CHECK: vshlQi32:
+;CHECK: vshl.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
+;CHECK: vshlQi64:
+;CHECK: vshl.i64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
+ ret <2 x i64> %tmp2
+}
+
+; Right shift by immediate:
+
+define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind {
+;CHECK: vshrs8:
+;CHECK: vshr.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind {
+;CHECK: vshrs16:
+;CHECK: vshr.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind {
+;CHECK: vshrs32:
+;CHECK: vshr.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
+ ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind {
+;CHECK: vshrs64:
+;CHECK: vshr.s64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
+ ret <1 x i64> %tmp2
+}
+
+define <8 x i8> @vshru8(<8 x i8>* %A) nounwind {
+;CHECK: vshru8:
+;CHECK: vshr.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vshru16(<4 x i16>* %A) nounwind {
+;CHECK: vshru16:
+;CHECK: vshr.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vshru32(<2 x i32>* %A) nounwind {
+;CHECK: vshru32:
+;CHECK: vshr.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
+ ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vshru64(<1 x i64>* %A) nounwind {
+;CHECK: vshru64:
+;CHECK: vshr.u64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
+ ret <1 x i64> %tmp2
+}
+
+define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind {
+;CHECK: vshrQs8:
+;CHECK: vshr.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind {
+;CHECK: vshrQs16:
+;CHECK: vshr.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind {
+;CHECK: vshrQs32:
+;CHECK: vshr.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind {
+;CHECK: vshrQs64:
+;CHECK: vshr.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
+ ret <2 x i64> %tmp2
+}
+
+define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind {
+;CHECK: vshrQu8:
+;CHECK: vshr.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind {
+;CHECK: vshrQu16:
+;CHECK: vshr.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind {
+;CHECK: vshrQu32:
+;CHECK: vshr.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vshrQu64(<2 x i64>* %A) nounwind {
+;CHECK: vshrQu64:
+;CHECK: vshr.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
+ ret <2 x i64> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vrshls8:
+;CHECK: vrshl.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vrshls16:
+;CHECK: vrshl.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vrshls32:
+;CHECK: vrshl.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vrshls64:
+;CHECK: vrshl.s64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+ ret <1 x i64> %tmp3
+}
+
+define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vrshlu8:
+;CHECK: vrshl.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vrshlu16:
+;CHECK: vrshl.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vrshlu32:
+;CHECK: vrshl.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vrshlu64:
+;CHECK: vrshl.u64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
+ ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vrshlQs8:
+;CHECK: vrshl.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vrshlQs16:
+;CHECK: vrshl.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vrshlQs32:
+;CHECK: vrshl.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vrshlQs64:
+;CHECK: vrshl.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vrshlQu8:
+;CHECK: vrshl.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vrshlQu16:
+;CHECK: vrshl.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vrshlQu32:
+;CHECK: vrshl.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vrshlQu64:
+;CHECK: vrshl.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind {
+;CHECK: vrshrs8:
+;CHECK: vrshr.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind {
+;CHECK: vrshrs16:
+;CHECK: vrshr.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind {
+;CHECK: vrshrs32:
+;CHECK: vrshr.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
+ ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind {
+;CHECK: vrshrs64:
+;CHECK: vrshr.s64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
+ ret <1 x i64> %tmp2
+}
+
+define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind {
+;CHECK: vrshru8:
+;CHECK: vrshr.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind {
+;CHECK: vrshru16:
+;CHECK: vrshr.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind {
+;CHECK: vrshru32:
+;CHECK: vrshr.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
+ ret <2 x i32> %tmp2
+}
+
+define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind {
+;CHECK: vrshru64:
+;CHECK: vrshr.u64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
+ ret <1 x i64> %tmp2
+}
+
+define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind {
+;CHECK: vrshrQs8:
+;CHECK: vrshr.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind {
+;CHECK: vrshrQs16:
+;CHECK: vrshr.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind {
+;CHECK: vrshrQs32:
+;CHECK: vrshr.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind {
+;CHECK: vrshrQs64:
+;CHECK: vrshr.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
+ ret <2 x i64> %tmp2
+}
+
+define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind {
+;CHECK: vrshrQu8:
+;CHECK: vrshr.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind {
+;CHECK: vrshrQu16:
+;CHECK: vrshr.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind {
+;CHECK: vrshrQu32:
+;CHECK: vrshr.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vrshrQu64(<2 x i64>* %A) nounwind {
+;CHECK: vrshrQu64:
+;CHECK: vrshr.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
+ ret <2 x i64> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
diff --git a/test/CodeGen/ARM/vshll.ll b/test/CodeGen/ARM/vshll.ll
new file mode 100644
index 0000000..8e85b98
--- /dev/null
+++ b/test/CodeGen/ARM/vshll.ll
@@ -0,0 +1,83 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind {
+;CHECK: vshlls8:
+;CHECK: vshll.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind {
+;CHECK: vshlls16:
+;CHECK: vshll.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind {
+;CHECK: vshlls32:
+;CHECK: vshll.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
+ ret <2 x i64> %tmp2
+}
+
+define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind {
+;CHECK: vshllu8:
+;CHECK: vshll.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind {
+;CHECK: vshllu16:
+;CHECK: vshll.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
+;CHECK: vshllu32:
+;CHECK: vshll.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
+ ret <2 x i64> %tmp2
+}
+
+; The following tests use the maximum shift count, so the signedness is
+; irrelevant. Test both signed and unsigned versions.
+define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind {
+;CHECK: vshlli8:
+;CHECK: vshll.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >)
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind {
+;CHECK: vshlli16:
+;CHECK: vshll.i16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 16, i16 16, i16 16, i16 16 >)
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind {
+;CHECK: vshlli32:
+;CHECK: vshll.i32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >)
+ ret <2 x i64> %tmp2
+}
+
+declare <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vshrn.ll b/test/CodeGen/ARM/vshrn.ll
new file mode 100644
index 0000000..e2544f4
--- /dev/null
+++ b/test/CodeGen/ARM/vshrn.ll
@@ -0,0 +1,57 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind {
+;CHECK: vshrns8:
+;CHECK: vshrn.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind {
+;CHECK: vshrns16:
+;CHECK: vshrn.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vshrns32(<2 x i64>* %A) nounwind {
+;CHECK: vshrns32:
+;CHECK: vshrn.i64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+ ret <2 x i32> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind {
+;CHECK: vrshrns8:
+;CHECK: vrshrn.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind {
+;CHECK: vrshrns16:
+;CHECK: vrshrn.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vrshrns32(<2 x i64>* %A) nounwind {
+;CHECK: vrshrns32:
+;CHECK: vrshrn.i64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
+ ret <2 x i32> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
diff --git a/test/CodeGen/ARM/vsra.ll b/test/CodeGen/ARM/vsra.ll
new file mode 100644
index 0000000..acb672d
--- /dev/null
+++ b/test/CodeGen/ARM/vsra.ll
@@ -0,0 +1,341 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vsras8:
+;CHECK: vsra.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = ashr <8 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+ %tmp4 = add <8 x i8> %tmp1, %tmp3
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vsras16:
+;CHECK: vsra.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = ashr <4 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16 >
+ %tmp4 = add <4 x i16> %tmp1, %tmp3
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vsras32:
+;CHECK: vsra.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = ashr <2 x i32> %tmp2, < i32 32, i32 32 >
+ %tmp4 = add <2 x i32> %tmp1, %tmp3
+ ret <2 x i32> %tmp4
+}
+
+define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vsras64:
+;CHECK: vsra.s64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = ashr <1 x i64> %tmp2, < i64 64 >
+ %tmp4 = add <1 x i64> %tmp1, %tmp3
+ ret <1 x i64> %tmp4
+}
+
+define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vsraQs8:
+;CHECK: vsra.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = ashr <16 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+ %tmp4 = add <16 x i8> %tmp1, %tmp3
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vsraQs16:
+;CHECK: vsra.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = ashr <8 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+ %tmp4 = add <8 x i16> %tmp1, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vsraQs32:
+;CHECK: vsra.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = ashr <4 x i32> %tmp2, < i32 32, i32 32, i32 32, i32 32 >
+ %tmp4 = add <4 x i32> %tmp1, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vsraQs64:
+;CHECK: vsra.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = ashr <2 x i64> %tmp2, < i64 64, i64 64 >
+ %tmp4 = add <2 x i64> %tmp1, %tmp3
+ ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vsrau8:
+;CHECK: vsra.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = lshr <8 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+ %tmp4 = add <8 x i8> %tmp1, %tmp3
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vsrau16:
+;CHECK: vsra.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = lshr <4 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16 >
+ %tmp4 = add <4 x i16> %tmp1, %tmp3
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vsrau32:
+;CHECK: vsra.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = lshr <2 x i32> %tmp2, < i32 32, i32 32 >
+ %tmp4 = add <2 x i32> %tmp1, %tmp3
+ ret <2 x i32> %tmp4
+}
+
+define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vsrau64:
+;CHECK: vsra.u64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = lshr <1 x i64> %tmp2, < i64 64 >
+ %tmp4 = add <1 x i64> %tmp1, %tmp3
+ ret <1 x i64> %tmp4
+}
+
+define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vsraQu8:
+;CHECK: vsra.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = lshr <16 x i8> %tmp2, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+ %tmp4 = add <16 x i8> %tmp1, %tmp3
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vsraQu16:
+;CHECK: vsra.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = lshr <8 x i16> %tmp2, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+ %tmp4 = add <8 x i16> %tmp1, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vsraQu32:
+;CHECK: vsra.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = lshr <4 x i32> %tmp2, < i32 32, i32 32, i32 32, i32 32 >
+ %tmp4 = add <4 x i32> %tmp1, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vsraQu64:
+;CHECK: vsra.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = lshr <2 x i64> %tmp2, < i64 64, i64 64 >
+ %tmp4 = add <2 x i64> %tmp1, %tmp3
+ ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vrsras8:
+;CHECK: vrsra.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+ %tmp4 = add <8 x i8> %tmp1, %tmp3
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vrsras16:
+;CHECK: vrsra.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
+ %tmp4 = add <4 x i16> %tmp1, %tmp3
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vrsras32:
+;CHECK: vrsra.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
+ %tmp4 = add <2 x i32> %tmp1, %tmp3
+ ret <2 x i32> %tmp4
+}
+
+define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vrsras64:
+;CHECK: vrsra.s64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
+ %tmp4 = add <1 x i64> %tmp1, %tmp3
+ ret <1 x i64> %tmp4
+}
+
+define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vrsrau8:
+;CHECK: vrsra.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+ %tmp4 = add <8 x i8> %tmp1, %tmp3
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vrsrau16:
+;CHECK: vrsra.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
+ %tmp4 = add <4 x i16> %tmp1, %tmp3
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vrsrau32:
+;CHECK: vrsra.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
+ %tmp4 = add <2 x i32> %tmp1, %tmp3
+ ret <2 x i32> %tmp4
+}
+
+define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vrsrau64:
+;CHECK: vrsra.u64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)
+ %tmp4 = add <1 x i64> %tmp1, %tmp3
+ ret <1 x i64> %tmp4
+}
+
+define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vrsraQs8:
+;CHECK: vrsra.s8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+ %tmp4 = add <16 x i8> %tmp1, %tmp3
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vrsraQs16:
+;CHECK: vrsra.s16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
+ %tmp4 = add <8 x i16> %tmp1, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vrsraQs32:
+;CHECK: vrsra.s32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
+ %tmp4 = add <4 x i32> %tmp1, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vrsraQs64:
+;CHECK: vrsra.s64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
+ %tmp4 = add <2 x i64> %tmp1, %tmp3
+ ret <2 x i64> %tmp4
+}
+
+define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vrsraQu8:
+;CHECK: vrsra.u8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
+ %tmp4 = add <16 x i8> %tmp1, %tmp3
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vrsraQu16:
+;CHECK: vrsra.u16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
+ %tmp4 = add <8 x i16> %tmp1, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vrsraQu32:
+;CHECK: vrsra.u32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
+ %tmp4 = add <4 x i32> %tmp1, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vrsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vrsraQu64:
+;CHECK: vrsra.u64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
+ %tmp4 = add <2 x i64> %tmp1, %tmp3
+ ret <2 x i64> %tmp4
+}
+
+declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
diff --git a/test/CodeGen/ARM/vst1.ll b/test/CodeGen/ARM/vst1.ll
new file mode 100644
index 0000000..602b124
--- /dev/null
+++ b/test/CodeGen/ARM/vst1.ll
@@ -0,0 +1,93 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vst1i8:
+;CHECK: vst1.8
+ %tmp1 = load <8 x i8>* %B
+ call void @llvm.arm.neon.vst1.v8i8(i8* %A, <8 x i8> %tmp1)
+ ret void
+}
+
+define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vst1i16:
+;CHECK: vst1.16
+ %tmp1 = load <4 x i16>* %B
+ call void @llvm.arm.neon.vst1.v4i16(i16* %A, <4 x i16> %tmp1)
+ ret void
+}
+
+define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vst1i32:
+;CHECK: vst1.32
+ %tmp1 = load <2 x i32>* %B
+ call void @llvm.arm.neon.vst1.v2i32(i32* %A, <2 x i32> %tmp1)
+ ret void
+}
+
+define void @vst1f(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vst1f:
+;CHECK: vst1.32
+ %tmp1 = load <2 x float>* %B
+ call void @llvm.arm.neon.vst1.v2f32(float* %A, <2 x float> %tmp1)
+ ret void
+}
+
+define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind {
+;CHECK: vst1i64:
+;CHECK: vst1.64
+ %tmp1 = load <1 x i64>* %B
+ call void @llvm.arm.neon.vst1.v1i64(i64* %A, <1 x i64> %tmp1)
+ ret void
+}
+
+define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
+;CHECK: vst1Qi8:
+;CHECK: vst1.8
+ %tmp1 = load <16 x i8>* %B
+ call void @llvm.arm.neon.vst1.v16i8(i8* %A, <16 x i8> %tmp1)
+ ret void
+}
+
+define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
+;CHECK: vst1Qi16:
+;CHECK: vst1.16
+ %tmp1 = load <8 x i16>* %B
+ call void @llvm.arm.neon.vst1.v8i16(i16* %A, <8 x i16> %tmp1)
+ ret void
+}
+
+define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind {
+;CHECK: vst1Qi32:
+;CHECK: vst1.32
+ %tmp1 = load <4 x i32>* %B
+ call void @llvm.arm.neon.vst1.v4i32(i32* %A, <4 x i32> %tmp1)
+ ret void
+}
+
+define void @vst1Qf(float* %A, <4 x float>* %B) nounwind {
+;CHECK: vst1Qf:
+;CHECK: vst1.32
+ %tmp1 = load <4 x float>* %B
+ call void @llvm.arm.neon.vst1.v4f32(float* %A, <4 x float> %tmp1)
+ ret void
+}
+
+define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind {
+;CHECK: vst1Qi64:
+;CHECK: vst1.64
+ %tmp1 = load <2 x i64>* %B
+ call void @llvm.arm.neon.vst1.v2i64(i64* %A, <2 x i64> %tmp1)
+ ret void
+}
+
+declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>) nounwind
+declare void @llvm.arm.neon.vst1.v4i16(i8*, <4 x i16>) nounwind
+declare void @llvm.arm.neon.vst1.v2i32(i8*, <2 x i32>) nounwind
+declare void @llvm.arm.neon.vst1.v2f32(i8*, <2 x float>) nounwind
+declare void @llvm.arm.neon.vst1.v1i64(i8*, <1 x i64>) nounwind
+
+declare void @llvm.arm.neon.vst1.v16i8(i8*, <16 x i8>) nounwind
+declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>) nounwind
+declare void @llvm.arm.neon.vst1.v4i32(i8*, <4 x i32>) nounwind
+declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>) nounwind
+declare void @llvm.arm.neon.vst1.v2i64(i8*, <2 x i64>) nounwind
diff --git a/test/CodeGen/ARM/vst2.ll b/test/CodeGen/ARM/vst2.ll
new file mode 100644
index 0000000..17d6bee
--- /dev/null
+++ b/test/CodeGen/ARM/vst2.ll
@@ -0,0 +1,84 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vst2i8:
+;CHECK: vst2.8
+ %tmp1 = load <8 x i8>* %B
+ call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1)
+ ret void
+}
+
+define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vst2i16:
+;CHECK: vst2.16
+ %tmp1 = load <4 x i16>* %B
+ call void @llvm.arm.neon.vst2.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1)
+ ret void
+}
+
+define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vst2i32:
+;CHECK: vst2.32
+ %tmp1 = load <2 x i32>* %B
+ call void @llvm.arm.neon.vst2.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1)
+ ret void
+}
+
+define void @vst2f(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vst2f:
+;CHECK: vst2.32
+ %tmp1 = load <2 x float>* %B
+ call void @llvm.arm.neon.vst2.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1)
+ ret void
+}
+
+define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind {
+;CHECK: vst2i64:
+;CHECK: vst1.64
+ %tmp1 = load <1 x i64>* %B
+ call void @llvm.arm.neon.vst2.v1i64(i64* %A, <1 x i64> %tmp1, <1 x i64> %tmp1)
+ ret void
+}
+
+define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind {
+;CHECK: vst2Qi8:
+;CHECK: vst2.8
+ %tmp1 = load <16 x i8>* %B
+ call void @llvm.arm.neon.vst2.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1)
+ ret void
+}
+
+define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind {
+;CHECK: vst2Qi16:
+;CHECK: vst2.16
+ %tmp1 = load <8 x i16>* %B
+ call void @llvm.arm.neon.vst2.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1)
+ ret void
+}
+
+define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind {
+;CHECK: vst2Qi32:
+;CHECK: vst2.32
+ %tmp1 = load <4 x i32>* %B
+ call void @llvm.arm.neon.vst2.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1)
+ ret void
+}
+
+define void @vst2Qf(float* %A, <4 x float>* %B) nounwind {
+;CHECK: vst2Qf:
+;CHECK: vst2.32
+ %tmp1 = load <4 x float>* %B
+ call void @llvm.arm.neon.vst2.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1)
+ ret void
+}
+
+declare void @llvm.arm.neon.vst2.v8i8(i8*, <8 x i8>, <8 x i8>) nounwind
+declare void @llvm.arm.neon.vst2.v4i16(i8*, <4 x i16>, <4 x i16>) nounwind
+declare void @llvm.arm.neon.vst2.v2i32(i8*, <2 x i32>, <2 x i32>) nounwind
+declare void @llvm.arm.neon.vst2.v2f32(i8*, <2 x float>, <2 x float>) nounwind
+declare void @llvm.arm.neon.vst2.v1i64(i8*, <1 x i64>, <1 x i64>) nounwind
+
+declare void @llvm.arm.neon.vst2.v16i8(i8*, <16 x i8>, <16 x i8>) nounwind
+declare void @llvm.arm.neon.vst2.v8i16(i8*, <8 x i16>, <8 x i16>) nounwind
+declare void @llvm.arm.neon.vst2.v4i32(i8*, <4 x i32>, <4 x i32>) nounwind
+declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>) nounwind
diff --git a/test/CodeGen/ARM/vst3.ll b/test/CodeGen/ARM/vst3.ll
new file mode 100644
index 0000000..a831a0c
--- /dev/null
+++ b/test/CodeGen/ARM/vst3.ll
@@ -0,0 +1,88 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vst3i8:
+;CHECK: vst3.8
+ %tmp1 = load <8 x i8>* %B
+ call void @llvm.arm.neon.vst3.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1)
+ ret void
+}
+
+define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vst3i16:
+;CHECK: vst3.16
+ %tmp1 = load <4 x i16>* %B
+ call void @llvm.arm.neon.vst3.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1)
+ ret void
+}
+
+define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vst3i32:
+;CHECK: vst3.32
+ %tmp1 = load <2 x i32>* %B
+ call void @llvm.arm.neon.vst3.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1)
+ ret void
+}
+
+define void @vst3f(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vst3f:
+;CHECK: vst3.32
+ %tmp1 = load <2 x float>* %B
+ call void @llvm.arm.neon.vst3.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1)
+ ret void
+}
+
+define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind {
+;CHECK: vst3i64:
+;CHECK: vst1.64
+ %tmp1 = load <1 x i64>* %B
+ call void @llvm.arm.neon.vst3.v1i64(i64* %A, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1)
+ ret void
+}
+
+define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind {
+;CHECK: vst3Qi8:
+;CHECK: vst3.8
+;CHECK: vst3.8
+ %tmp1 = load <16 x i8>* %B
+ call void @llvm.arm.neon.vst3.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1)
+ ret void
+}
+
+define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind {
+;CHECK: vst3Qi16:
+;CHECK: vst3.16
+;CHECK: vst3.16
+ %tmp1 = load <8 x i16>* %B
+ call void @llvm.arm.neon.vst3.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1)
+ ret void
+}
+
+define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind {
+;CHECK: vst3Qi32:
+;CHECK: vst3.32
+;CHECK: vst3.32
+ %tmp1 = load <4 x i32>* %B
+ call void @llvm.arm.neon.vst3.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1)
+ ret void
+}
+
+define void @vst3Qf(float* %A, <4 x float>* %B) nounwind {
+;CHECK: vst3Qf:
+;CHECK: vst3.32
+;CHECK: vst3.32
+ %tmp1 = load <4 x float>* %B
+ call void @llvm.arm.neon.vst3.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1)
+ ret void
+}
+
+declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>) nounwind
+declare void @llvm.arm.neon.vst3.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>) nounwind
+declare void @llvm.arm.neon.vst3.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>) nounwind
+declare void @llvm.arm.neon.vst3.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>) nounwind
+declare void @llvm.arm.neon.vst3.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>) nounwind
+
+declare void @llvm.arm.neon.vst3.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>) nounwind
+declare void @llvm.arm.neon.vst3.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>) nounwind
+declare void @llvm.arm.neon.vst3.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>) nounwind
+declare void @llvm.arm.neon.vst3.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>) nounwind
diff --git a/test/CodeGen/ARM/vst4.ll b/test/CodeGen/ARM/vst4.ll
new file mode 100644
index 0000000..d92c017
--- /dev/null
+++ b/test/CodeGen/ARM/vst4.ll
@@ -0,0 +1,88 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vst4i8:
+;CHECK: vst4.8
+ %tmp1 = load <8 x i8>* %B
+ call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1)
+ ret void
+}
+
+define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vst4i16:
+;CHECK: vst4.16
+ %tmp1 = load <4 x i16>* %B
+ call void @llvm.arm.neon.vst4.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1)
+ ret void
+}
+
+define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vst4i32:
+;CHECK: vst4.32
+ %tmp1 = load <2 x i32>* %B
+ call void @llvm.arm.neon.vst4.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1)
+ ret void
+}
+
+define void @vst4f(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vst4f:
+;CHECK: vst4.32
+ %tmp1 = load <2 x float>* %B
+ call void @llvm.arm.neon.vst4.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1)
+ ret void
+}
+
+define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind {
+;CHECK: vst4i64:
+;CHECK: vst1.64
+ %tmp1 = load <1 x i64>* %B
+ call void @llvm.arm.neon.vst4.v1i64(i64* %A, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1)
+ ret void
+}
+
+define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind {
+;CHECK: vst4Qi8:
+;CHECK: vst4.8
+;CHECK: vst4.8
+ %tmp1 = load <16 x i8>* %B
+ call void @llvm.arm.neon.vst4.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1)
+ ret void
+}
+
+define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind {
+;CHECK: vst4Qi16:
+;CHECK: vst4.16
+;CHECK: vst4.16
+ %tmp1 = load <8 x i16>* %B
+ call void @llvm.arm.neon.vst4.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1)
+ ret void
+}
+
+define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind {
+;CHECK: vst4Qi32:
+;CHECK: vst4.32
+;CHECK: vst4.32
+ %tmp1 = load <4 x i32>* %B
+ call void @llvm.arm.neon.vst4.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1)
+ ret void
+}
+
+define void @vst4Qf(float* %A, <4 x float>* %B) nounwind {
+;CHECK: vst4Qf:
+;CHECK: vst4.32
+;CHECK: vst4.32
+ %tmp1 = load <4 x float>* %B
+ call void @llvm.arm.neon.vst4.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1)
+ ret void
+}
+
+declare void @llvm.arm.neon.vst4.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind
+declare void @llvm.arm.neon.vst4.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>) nounwind
+declare void @llvm.arm.neon.vst4.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>) nounwind
+declare void @llvm.arm.neon.vst4.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>) nounwind
+declare void @llvm.arm.neon.vst4.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>) nounwind
+
+declare void @llvm.arm.neon.vst4.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) nounwind
+declare void @llvm.arm.neon.vst4.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>) nounwind
+declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>) nounwind
+declare void @llvm.arm.neon.vst4.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>) nounwind
diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll
new file mode 100644
index 0000000..3bfb14f
--- /dev/null
+++ b/test/CodeGen/ARM/vstlane.ll
@@ -0,0 +1,197 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vst2lanei8:
+;CHECK: vst2.8
+ %tmp1 = load <8 x i8>* %B
+ call void @llvm.arm.neon.vst2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vst2lanei16:
+;CHECK: vst2.16
+ %tmp1 = load <4 x i16>* %B
+ call void @llvm.arm.neon.vst2lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vst2lanei32:
+;CHECK: vst2.32
+ %tmp1 = load <2 x i32>* %B
+ call void @llvm.arm.neon.vst2lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst2lanef(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vst2lanef:
+;CHECK: vst2.32
+ %tmp1 = load <2 x float>* %B
+ call void @llvm.arm.neon.vst2lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+;CHECK: vst2laneQi16:
+;CHECK: vst2.16
+ %tmp1 = load <8 x i16>* %B
+ call void @llvm.arm.neon.vst2lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+;CHECK: vst2laneQi32:
+;CHECK: vst2.32
+ %tmp1 = load <4 x i32>* %B
+ call void @llvm.arm.neon.vst2lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2)
+ ret void
+}
+
+define void @vst2laneQf(float* %A, <4 x float>* %B) nounwind {
+;CHECK: vst2laneQf:
+;CHECK: vst2.32
+ %tmp1 = load <4 x float>* %B
+ call void @llvm.arm.neon.vst2lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, i32 3)
+ ret void
+}
+
+declare void @llvm.arm.neon.vst2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.v4i16(i8*, <4 x i16>, <4 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.v2f32(i8*, <2 x float>, <2 x float>, i32) nounwind
+
+declare void @llvm.arm.neon.vst2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst2lane.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
+
+define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vst3lanei8:
+;CHECK: vst3.8
+ %tmp1 = load <8 x i8>* %B
+ call void @llvm.arm.neon.vst3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vst3lanei16:
+;CHECK: vst3.16
+ %tmp1 = load <4 x i16>* %B
+ call void @llvm.arm.neon.vst3lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vst3lanei32:
+;CHECK: vst3.32
+ %tmp1 = load <2 x i32>* %B
+ call void @llvm.arm.neon.vst3lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vst3lanef:
+;CHECK: vst3.32
+ %tmp1 = load <2 x float>* %B
+ call void @llvm.arm.neon.vst3lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+;CHECK: vst3laneQi16:
+;CHECK: vst3.16
+ %tmp1 = load <8 x i16>* %B
+ call void @llvm.arm.neon.vst3lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6)
+ ret void
+}
+
+define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+;CHECK: vst3laneQi32:
+;CHECK: vst3.32
+ %tmp1 = load <4 x i32>* %B
+ call void @llvm.arm.neon.vst3lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0)
+ ret void
+}
+
+define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind {
+;CHECK: vst3laneQf:
+;CHECK: vst3.32
+ %tmp1 = load <4 x float>* %B
+ call void @llvm.arm.neon.vst3lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
+ ret void
+}
+
+declare void @llvm.arm.neon.vst3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32) nounwind
+
+declare void @llvm.arm.neon.vst3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32) nounwind
+
+
+define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
+;CHECK: vst4lanei8:
+;CHECK: vst4.8
+ %tmp1 = load <8 x i8>* %B
+ call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
+;CHECK: vst4lanei16:
+;CHECK: vst4.16
+ %tmp1 = load <4 x i16>* %B
+ call void @llvm.arm.neon.vst4lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
+;CHECK: vst4lanei32:
+;CHECK: vst4.32
+ %tmp1 = load <2 x i32>* %B
+ call void @llvm.arm.neon.vst4lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst4lanef(float* %A, <2 x float>* %B) nounwind {
+;CHECK: vst4lanef:
+;CHECK: vst4.32
+ %tmp1 = load <2 x float>* %B
+ call void @llvm.arm.neon.vst4lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
+ ret void
+}
+
+define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
+;CHECK: vst4laneQi16:
+;CHECK: vst4.16
+ %tmp1 = load <8 x i16>* %B
+ call void @llvm.arm.neon.vst4lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7)
+ ret void
+}
+
+define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
+;CHECK: vst4laneQi32:
+;CHECK: vst4.32
+ %tmp1 = load <4 x i32>* %B
+ call void @llvm.arm.neon.vst4lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2)
+ ret void
+}
+
+define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind {
+;CHECK: vst4laneQf:
+;CHECK: vst4.32
+ %tmp1 = load <4 x float>* %B
+ call void @llvm.arm.neon.vst4lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
+ ret void
+}
+
+declare void @llvm.arm.neon.vst4lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32) nounwind
+
+declare void @llvm.arm.neon.vst4lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
+declare void @llvm.arm.neon.vst4lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) nounwind
diff --git a/test/CodeGen/ARM/vsub.ll b/test/CodeGen/ARM/vsub.ll
new file mode 100644
index 0000000..8f0055f
--- /dev/null
+++ b/test/CodeGen/ARM/vsub.ll
@@ -0,0 +1,277 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vsubi8:
+;CHECK: vsub.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = sub <8 x i8> %tmp1, %tmp2
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vsubi16:
+;CHECK: vsub.i16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = sub <4 x i16> %tmp1, %tmp2
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vsubi32:
+;CHECK: vsub.i32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = sub <2 x i32> %tmp1, %tmp2
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK: vsubi64:
+;CHECK: vsub.i64
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = sub <1 x i64> %tmp1, %tmp2
+ ret <1 x i64> %tmp3
+}
+
+define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vsubf32:
+;CHECK: vsub.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = sub <2 x float> %tmp1, %tmp2
+ ret <2 x float> %tmp3
+}
+
+define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vsubQi8:
+;CHECK: vsub.i8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = sub <16 x i8> %tmp1, %tmp2
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vsubQi16:
+;CHECK: vsub.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = sub <8 x i16> %tmp1, %tmp2
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vsubQi32:
+;CHECK: vsub.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = sub <4 x i32> %tmp1, %tmp2
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vsubQi64:
+;CHECK: vsub.i64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = sub <2 x i64> %tmp1, %tmp2
+ ret <2 x i64> %tmp3
+}
+
+define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vsubQf32:
+;CHECK: vsub.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = sub <4 x float> %tmp1, %tmp2
+ ret <4 x float> %tmp3
+}
+
+define <8 x i8> @vsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vsubhni16:
+;CHECK: vsubhn.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vsubhni32:
+;CHECK: vsubhn.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vsubhni64:
+;CHECK: vsubhn.i64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vrsubhni16:
+;CHECK: vrsubhn.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vrsubhni32:
+;CHECK: vrsubhn.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vrsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK: vrsubhni64:
+;CHECK: vrsubhn.i64
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vsubls8:
+;CHECK: vsubl.s8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vsubls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vsubls16:
+;CHECK: vsubl.s16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vsubls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vsubls32:
+;CHECK: vsubl.s32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vsubls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vsublu8:
+;CHECK: vsubl.u8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vsublu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vsublu16:
+;CHECK: vsubl.u16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vsublu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vsublu32:
+;CHECK: vsubl.u32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vsublu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i16> @llvm.arm.neon.vsubls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vsubls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vsubls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vsublu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vsublu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vsublu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vsubws8:
+;CHECK: vsubw.s8
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vsubws.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vsubws16:
+;CHECK: vsubw.s16
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vsubws.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vsubws32:
+;CHECK: vsubw.s32
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vsubws.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vsubwu8:
+;CHECK: vsubw.u8
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm.neon.vsubwu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vsubwu16:
+;CHECK: vsubw.u16
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm.neon.vsubwu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vsubwu32:
+;CHECK: vsubw.u32
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm.neon.vsubwu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i16> @llvm.arm.neon.vsubws.v8i16(<8 x i16>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vsubws.v4i32(<4 x i32>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vsubws.v2i64(<2 x i64>, <2 x i32>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vsubwu.v8i16(<8 x i16>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vsubwu.v4i32(<4 x i32>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm.neon.vsubwu.v2i64(<2 x i64>, <2 x i32>) nounwind readnone
diff --git a/test/CodeGen/ARM/vtbl.ll b/test/CodeGen/ARM/vtbl.ll
new file mode 100644
index 0000000..9264987
--- /dev/null
+++ b/test/CodeGen/ARM/vtbl.ll
@@ -0,0 +1,109 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
+%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
+%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
+
+define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vtbl1:
+;CHECK: vtbl.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind {
+;CHECK: vtbl2:
+;CHECK: vtbl.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load %struct.__neon_int8x8x2_t* %B
+ %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
+ %tmp5 = call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4)
+ ret <8 x i8> %tmp5
+}
+
+define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind {
+;CHECK: vtbl3:
+;CHECK: vtbl.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load %struct.__neon_int8x8x3_t* %B
+ %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2
+ %tmp6 = call <8 x i8> @llvm.arm.neon.vtbl3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5)
+ ret <8 x i8> %tmp6
+}
+
+define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind {
+;CHECK: vtbl4:
+;CHECK: vtbl.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load %struct.__neon_int8x8x4_t* %B
+ %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
+ %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
+ %tmp7 = call <8 x i8> @llvm.arm.neon.vtbl4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6)
+ ret <8 x i8> %tmp7
+}
+
+define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+;CHECK: vtbx1:
+;CHECK: vtbx.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = load <8 x i8>* %C
+ %tmp4 = call <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
+ ret <8 x i8> %tmp4
+}
+
+define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C) nounwind {
+;CHECK: vtbx2:
+;CHECK: vtbx.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load %struct.__neon_int8x8x2_t* %B
+ %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
+ %tmp5 = load <8 x i8>* %C
+ %tmp6 = call <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5)
+ ret <8 x i8> %tmp6
+}
+
+define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C) nounwind {
+;CHECK: vtbx3:
+;CHECK: vtbx.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load %struct.__neon_int8x8x3_t* %B
+ %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2
+ %tmp6 = load <8 x i8>* %C
+ %tmp7 = call <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6)
+ ret <8 x i8> %tmp7
+}
+
+define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
+;CHECK: vtbx4:
+;CHECK: vtbx.8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load %struct.__neon_int8x8x4_t* %B
+ %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
+ %tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
+ %tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
+ %tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
+ %tmp7 = load <8 x i8>* %C
+ %tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
+ ret <8 x i8> %tmp8
+}
+
+declare <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8>, <8 x i8>) nounwind readnone
+declare <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <8 x i8> @llvm.arm.neon.vtbl3(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <8 x i8> @llvm.arm.neon.vtbl4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
+declare <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
diff --git a/test/CodeGen/ARM/vtrn.ll b/test/CodeGen/ARM/vtrn.ll
new file mode 100644
index 0000000..5122b09
--- /dev/null
+++ b/test/CodeGen/ARM/vtrn.ll
@@ -0,0 +1,97 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vtrni8:
+;CHECK: vtrn.8
+;CHECK-NEXT: vadd.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
+ %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vtrni16:
+;CHECK: vtrn.16
+;CHECK-NEXT: vadd.i16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+ %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+ %tmp5 = add <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK: vtrni32:
+;CHECK: vtrn.32
+;CHECK-NEXT: vadd.i32
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>
+ %tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>
+ %tmp5 = add <2 x i32> %tmp3, %tmp4
+ ret <2 x i32> %tmp5
+}
+
+define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK: vtrnf:
+;CHECK: vtrn.32
+;CHECK-NEXT: vadd.f32
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>
+ %tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>
+ %tmp5 = add <2 x float> %tmp3, %tmp4
+ ret <2 x float> %tmp5
+}
+
+define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vtrnQi8:
+;CHECK: vtrn.8
+;CHECK-NEXT: vadd.i8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
+ %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
+ %tmp5 = add <16 x i8> %tmp3, %tmp4
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vtrnQi16:
+;CHECK: vtrn.16
+;CHECK-NEXT: vadd.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
+ %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vtrnQi32:
+;CHECK: vtrn.32
+;CHECK-NEXT: vadd.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+ %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vtrnQf:
+;CHECK: vtrn.32
+;CHECK-NEXT: vadd.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+ %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+ %tmp5 = add <4 x float> %tmp3, %tmp4
+ ret <4 x float> %tmp5
+}
diff --git a/test/CodeGen/ARM/vuzp.ll b/test/CodeGen/ARM/vuzp.ll
new file mode 100644
index 0000000..e531718
--- /dev/null
+++ b/test/CodeGen/ARM/vuzp.ll
@@ -0,0 +1,75 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vuzpi8:
+;CHECK: vuzp.8
+;CHECK-NEXT: vadd.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+ %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vuzpi16:
+;CHECK: vuzp.16
+;CHECK-NEXT: vadd.i16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+ %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ %tmp5 = add <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
+
+define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vuzpQi8:
+;CHECK: vuzp.8
+;CHECK-NEXT: vadd.i8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
+ %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
+ %tmp5 = add <16 x i8> %tmp3, %tmp4
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vuzpQi16:
+;CHECK: vuzp.16
+;CHECK-NEXT: vadd.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+ %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vuzpQi32:
+;CHECK: vuzp.32
+;CHECK-NEXT: vadd.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+ %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vuzpQf:
+;CHECK: vuzp.32
+;CHECK-NEXT: vadd.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+ %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ %tmp5 = add <4 x float> %tmp3, %tmp4
+ ret <4 x float> %tmp5
+}
diff --git a/test/CodeGen/ARM/vzip.ll b/test/CodeGen/ARM/vzip.ll
new file mode 100644
index 0000000..32f7e0d
--- /dev/null
+++ b/test/CodeGen/ARM/vzip.ll
@@ -0,0 +1,75 @@
+; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+
+define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK: vzipi8:
+;CHECK: vzip.8
+;CHECK-NEXT: vadd.i8
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+ %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK: vzipi16:
+;CHECK: vzip.16
+;CHECK-NEXT: vadd.i16
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+ %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+ %tmp5 = add <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
+
+define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK: vzipQi8:
+;CHECK: vzip.8
+;CHECK-NEXT: vadd.i8
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+ %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
+ %tmp5 = add <16 x i8> %tmp3, %tmp4
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK: vzipQi16:
+;CHECK: vzip.16
+;CHECK-NEXT: vadd.i16
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+ %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK: vzipQi32:
+;CHECK: vzip.32
+;CHECK-NEXT: vadd.i32
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+ %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK: vzipQf:
+;CHECK: vzip.32
+;CHECK-NEXT: vadd.f32
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+ %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+ %tmp5 = add <4 x float> %tmp3, %tmp4
+ ret <4 x float> %tmp5
+}
diff --git a/test/CodeGen/ARM/weak.ll b/test/CodeGen/ARM/weak.ll
new file mode 100644
index 0000000..5ac4b8c
--- /dev/null
+++ b/test/CodeGen/ARM/weak.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=arm | grep .weak.*f
+; RUN: llc < %s -march=arm | grep .weak.*h
+
+define weak i32 @f() {
+entry:
+ unreachable
+}
+
+define void @g() {
+entry:
+ tail call void @h( )
+ ret void
+}
+
+declare extern_weak void @h()
+
diff --git a/test/CodeGen/ARM/weak2.ll b/test/CodeGen/ARM/weak2.ll
new file mode 100644
index 0000000..cf327bb
--- /dev/null
+++ b/test/CodeGen/ARM/weak2.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=arm | grep .weak
+
+define i32 @f(i32 %a) {
+entry:
+ %tmp2 = icmp eq i32 %a, 0 ; <i1> [#uses=1]
+ %t.0 = select i1 %tmp2, i32 (...)* null, i32 (...)* @test_weak ; <i32 (...)*> [#uses=2]
+ %tmp5 = icmp eq i32 (...)* %t.0, null ; <i1> [#uses=1]
+ br i1 %tmp5, label %UnifiedReturnBlock, label %cond_true8
+
+cond_true8: ; preds = %entry
+ %tmp10 = tail call i32 (...)* %t.0( ) ; <i32> [#uses=1]
+ ret i32 %tmp10
+
+UnifiedReturnBlock: ; preds = %entry
+ ret i32 250
+}
+
+declare extern_weak i32 @test_weak(...)
diff --git a/test/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll b/test/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll
new file mode 100644
index 0000000..87d9928
--- /dev/null
+++ b/test/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll
@@ -0,0 +1,17 @@
+; There should be exactly two calls here (memset and malloc), no more.
+; RUN: llc < %s -march=alpha | grep jsr | count 2
+
+%typedef.bc_struct = type opaque
+declare void @llvm.memset.i64(i8*, i8, i64, i32)
+
+define i1 @l12_l94_bc_divide_endif_2E_3_2E_ce(i32* %tmp.71.reload, i32 %scale2.1.3, i32 %extra.0, %typedef.bc_struct* %n1, %typedef.bc_struct* %n2, i32* %tmp.92.reload, i32 %tmp.94.reload, i32* %tmp.98.reload, i32 %tmp.100.reload, i8** %tmp.112.out, i32* %tmp.157.out, i8** %tmp.158.out) {
+newFuncRoot:
+ %tmp.120 = add i32 %extra.0, 2 ; <i32> [#uses=1]
+ %tmp.122 = add i32 %tmp.120, %tmp.94.reload ; <i32> [#uses=1]
+ %tmp.123 = add i32 %tmp.122, %tmp.100.reload ; <i32> [#uses=2]
+ %tmp.112 = malloc i8, i32 %tmp.123 ; <i8*> [#uses=1]
+ %tmp.137 = zext i32 %tmp.123 to i64 ; <i64> [#uses=1]
+ tail call void @llvm.memset.i64( i8* %tmp.112, i8 0, i64 %tmp.137, i32 0 )
+ ret i1 true
+}
+
diff --git a/test/CodeGen/Alpha/2005-12-12-MissingFCMov.ll b/test/CodeGen/Alpha/2005-12-12-MissingFCMov.ll
new file mode 100644
index 0000000..4b3d022
--- /dev/null
+++ b/test/CodeGen/Alpha/2005-12-12-MissingFCMov.ll
@@ -0,0 +1,40 @@
+; This shouldn't crash
+; RUN: llc < %s -march=alpha
+
[email protected]_4 = external global [44 x i8] ; <[44 x i8]*> [#uses=0]
+
+declare void @printf(i32, ...)
+
+define void @main() {
+entry:
+ %tmp.11861 = icmp slt i64 0, 1 ; <i1> [#uses=1]
+ %tmp.19466 = icmp slt i64 0, 1 ; <i1> [#uses=1]
+ %tmp.21571 = icmp slt i64 0, 1 ; <i1> [#uses=1]
+ %tmp.36796 = icmp slt i64 0, 1 ; <i1> [#uses=1]
+ br i1 %tmp.11861, label %loopexit.2, label %no_exit.2
+
+no_exit.2: ; preds = %entry
+ ret void
+
+loopexit.2: ; preds = %entry
+ br i1 %tmp.19466, label %loopexit.3, label %no_exit.3.preheader
+
+no_exit.3.preheader: ; preds = %loopexit.2
+ ret void
+
+loopexit.3: ; preds = %loopexit.2
+ br i1 %tmp.21571, label %no_exit.6, label %no_exit.4
+
+no_exit.4: ; preds = %loopexit.3
+ ret void
+
+no_exit.6: ; preds = %no_exit.6, %loopexit.3
+ %tmp.30793 = icmp sgt i64 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp.30793, label %loopexit.6, label %no_exit.6
+
+loopexit.6: ; preds = %no_exit.6
+ %Z.1 = select i1 %tmp.36796, double 1.000000e+00, double 0x3FEFFF7CEDE74EAE; <double> [#uses=2]
+ tail call void (i32, ...)* @printf( i32 0, i64 0, i64 0, i64 0, double 1.000000e+00, double 1.000000e+00, double %Z.1, double %Z.1 )
+ ret void
+}
+
diff --git a/test/CodeGen/Alpha/2006-01-18-MissedGlobal.ll b/test/CodeGen/Alpha/2006-01-18-MissedGlobal.ll
new file mode 100644
index 0000000..65d2a8d
--- /dev/null
+++ b/test/CodeGen/Alpha/2006-01-18-MissedGlobal.ll
@@ -0,0 +1,27 @@
+; The global symbol should be legalized
+; RUN: llc < %s -march=alpha
+
+target datalayout = "e-p:64:64"
+ %struct.LIST_HELP = type { %struct.LIST_HELP*, i8* }
+ %struct._IO_FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct._IO_FILE*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i32, [44 x i8] }
+ %struct._IO_marker = type { %struct._IO_marker*, %struct._IO_FILE*, i32 }
+@clause_SORT = external global [21 x %struct.LIST_HELP*] ; <[21 x %struct.LIST_HELP*]*> [#uses=0]
+@ia_in = external global %struct._IO_FILE* ; <%struct._IO_FILE**> [#uses=1]
+@multvec_j = external global [100 x i32] ; <[100 x i32]*> [#uses=0]
+
+define void @main(i32 %argc) {
+clock_Init.exit:
+ %tmp.5.i575 = load i32* null ; <i32> [#uses=1]
+ %tmp.309 = icmp eq i32 %tmp.5.i575, 0 ; <i1> [#uses=1]
+ br i1 %tmp.309, label %UnifiedReturnBlock, label %then.17
+
+then.17: ; preds = %clock_Init.exit
+ store %struct._IO_FILE* null, %struct._IO_FILE** @ia_in
+ %savedstack = call i8* @llvm.stacksave( ) ; <i8*> [#uses=0]
+ ret void
+
+UnifiedReturnBlock: ; preds = %clock_Init.exit
+ ret void
+}
+
+declare i8* @llvm.stacksave()
diff --git a/test/CodeGen/Alpha/2006-01-26-VaargBreak.ll b/test/CodeGen/Alpha/2006-01-26-VaargBreak.ll
new file mode 100644
index 0000000..45587f0
--- /dev/null
+++ b/test/CodeGen/Alpha/2006-01-26-VaargBreak.ll
@@ -0,0 +1,14 @@
+; This shouldn't crash
+; RUN: llc < %s -march=alpha
+
+target datalayout = "e-p:64:64"
+target triple = "alphaev6-unknown-linux-gnu"
+deplibs = [ "c", "crtend", "stdc++" ]
+ %struct.__va_list_tag = type { i8*, i32 }
+
+define i32 @emit_library_call_value(i32 %nargs, ...) {
+entry:
+ %tmp.223 = va_arg %struct.__va_list_tag* null, i32 ; <i32> [#uses=1]
+ ret i32 %tmp.223
+}
+
diff --git a/test/CodeGen/Alpha/2006-04-04-zextload.ll b/test/CodeGen/Alpha/2006-04-04-zextload.ll
new file mode 100644
index 0000000..2b28903
--- /dev/null
+++ b/test/CodeGen/Alpha/2006-04-04-zextload.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=alpha
+
+target datalayout = "e-p:64:64"
+target triple = "alphaev67-unknown-linux-gnu"
+ %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i32, i8*, i8*, i8* }
+ %struct._Callback_list = type { %struct._Callback_list*, void (i32, %struct.ios_base*, i32)*, i32, i32 }
+ %struct._Impl = type { i32, %struct.facet**, i64, %struct.facet**, i8** }
+ %struct._Words = type { i8*, i64 }
+ %"struct.__codecvt_abstract_base<char,char,__mbstate_t>" = type { %struct.facet }
+ %"struct.basic_streambuf<char,std::char_traits<char> >" = type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %struct.locale }
+ %struct.facet = type { i32 (...)**, i32 }
+ %struct.ios_base = type { i32 (...)**, i64, i64, i32, i32, i32, %struct._Callback_list*, %struct._Words, [8 x %struct._Words], i32, %struct._Words*, %struct.locale }
+ %struct.locale = type { %struct._Impl* }
+ %"struct.ostreambuf_iterator<char,std::char_traits<char> >" = type { %"struct.basic_streambuf<char,std::char_traits<char> >"*, i1 }
[email protected]_unit1047 = external global %llvm.dbg.compile_unit.type ; <%llvm.dbg.compile_unit.type*> [#uses=1]
+
+define void @_ZNKSt7num_putIcSt19ostreambuf_iteratorIcSt11char_traitsIcEEE15_M_insert_floatIdEES3_S3_RSt8ios_baseccT_() {
+entry:
+ %tmp234 = icmp eq i8 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp234, label %cond_next243, label %cond_true235
+
+cond_true235: ; preds = %entry
+ ret void
+
+cond_next243: ; preds = %entry
+ %tmp428 = load i64* null ; <i64> [#uses=1]
+ %tmp428.upgrd.1 = trunc i64 %tmp428 to i32 ; <i32> [#uses=1]
+ %tmp429 = alloca i8, i32 %tmp428.upgrd.1 ; <i8*> [#uses=0]
+ call void @llvm.dbg.stoppoint( i32 1146, i32 0, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit1047 to { }*) )
+ unreachable
+}
+
+declare void @llvm.dbg.stoppoint(i32, i32, { }*)
+
diff --git a/test/CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll b/test/CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll
new file mode 100644
index 0000000..5d31bc3
--- /dev/null
+++ b/test/CodeGen/Alpha/2006-07-03-ASMFormalLowering.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=alpha
+
+target datalayout = "e-p:64:64"
+target triple = "alphaev67-unknown-linux-gnu"
+
+define i32 @_ZN9__gnu_cxx18__exchange_and_addEPVii(i32* %__mem, i32 %__val) {
+entry:
+ %__tmp = alloca i32, align 4 ; <i32*> [#uses=1]
+ %tmp3 = call i32 asm sideeffect "\0A$$Lxadd_0:\0A\09ldl_l $0,$3\0A\09addl $0,$4,$1\0A\09stl_c $1,$2\0A\09beq $1,$$Lxadd_0\0A\09mb", "=&r,=*&r,=*m,m,r"( i32* %__tmp, i32* %__mem, i32* %__mem, i32 %__val ) ; <i32> [#uses=1]
+ ret i32 %tmp3
+}
+
+define void @_ZN9__gnu_cxx12__atomic_addEPVii(i32* %__mem, i32 %__val) {
+entry:
+ %tmp2 = call i32 asm sideeffect "\0A$$Ladd_1:\0A\09ldl_l $0,$2\0A\09addl $0,$3,$0\0A\09stl_c $0,$1\0A\09beq $0,$$Ladd_1\0A\09mb", "=&r,=*m,m,r"( i32* %__mem, i32* %__mem, i32 %__val ) ; <i32> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/Alpha/2006-11-01-vastart.ll b/test/CodeGen/Alpha/2006-11-01-vastart.ll
new file mode 100644
index 0000000..14e0bcc
--- /dev/null
+++ b/test/CodeGen/Alpha/2006-11-01-vastart.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=alpha
+
+target datalayout = "e-p:64:64"
+target triple = "alphaev67-unknown-linux-gnu"
+ %struct.va_list = type { i8*, i32, i32 }
+
+define void @yyerror(i32, ...) {
+entry:
+ %va.upgrd.1 = bitcast %struct.va_list* null to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_start( i8* %va.upgrd.1 )
+ ret void
+}
+
+declare void @llvm.va_start(i8*)
+
diff --git a/test/CodeGen/Alpha/2007-11-27-mulneg3.ll b/test/CodeGen/Alpha/2007-11-27-mulneg3.ll
new file mode 100644
index 0000000..b537e25
--- /dev/null
+++ b/test/CodeGen/Alpha/2007-11-27-mulneg3.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=alpha
+
+;FIXME: this should produce no mul inst. But not crashing will have to do for now
+
+; ModuleID = 'Output/bugpoint-train/bugpoint-reduced-simplified.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128"
+target triple = "alphaev6-unknown-linux-gnu"
+
+define fastcc i32 @getcount(i32 %s) {
+cond_next43: ; preds = %bb27
+ %tmp431 = mul i32 %s, -3
+ ret i32 %tmp431
+}
diff --git a/test/CodeGen/Alpha/2008-11-10-smul_lohi.ll b/test/CodeGen/Alpha/2008-11-10-smul_lohi.ll
new file mode 100644
index 0000000..1a4b40e
--- /dev/null
+++ b/test/CodeGen/Alpha/2008-11-10-smul_lohi.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=alpha
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128"
+target triple = "alphaev6-unknown-linux-gnu"
+
+define i64 @__mulvdi3(i64 %a, i64 %b) nounwind {
+entry:
+ %0 = sext i64 %a to i128 ; <i128> [#uses=1]
+ %1 = sext i64 %b to i128 ; <i128> [#uses=1]
+ %2 = mul i128 %1, %0 ; <i128> [#uses=2]
+ %3 = lshr i128 %2, 64 ; <i128> [#uses=1]
+ %4 = trunc i128 %3 to i64 ; <i64> [#uses=1]
+ %5 = trunc i128 %2 to i64 ; <i64> [#uses=1]
+ %6 = icmp eq i64 %4, 0 ; <i1> [#uses=1]
+ br i1 %6, label %bb1, label %bb
+
+bb: ; preds = %entry
+ unreachable
+
+bb1: ; preds = %entry
+ ret i64 %5
+}
diff --git a/test/CodeGen/Alpha/2008-11-12-Add128.ll b/test/CodeGen/Alpha/2008-11-12-Add128.ll
new file mode 100644
index 0000000..8b9b603
--- /dev/null
+++ b/test/CodeGen/Alpha/2008-11-12-Add128.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s
+; PR3044
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128"
+target triple = "alphaev6-unknown-linux-gnu"
+
+define i128 @__mulvti3(i128 %u, i128 %v) nounwind {
+entry:
+ %0 = load i128* null, align 16 ; <i128> [#uses=1]
+ %1 = load i64* null, align 8 ; <i64> [#uses=1]
+ %2 = zext i64 %1 to i128 ; <i128> [#uses=1]
+ %3 = add i128 %2, %0 ; <i128> [#uses=1]
+ store i128 %3, i128* null, align 16
+ unreachable
+}
diff --git a/test/CodeGen/Alpha/2009-07-16-PromoteFloatCompare.ll b/test/CodeGen/Alpha/2009-07-16-PromoteFloatCompare.ll
new file mode 100644
index 0000000..cfbf7fc
--- /dev/null
+++ b/test/CodeGen/Alpha/2009-07-16-PromoteFloatCompare.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=alpha
+
+define i1 @a(float %x) {
+ %r = fcmp ult float %x, 1.0
+ ret i1 %r
+}
diff --git a/test/CodeGen/Alpha/add.ll b/test/CodeGen/Alpha/add.ll
new file mode 100644
index 0000000..24a7418
--- /dev/null
+++ b/test/CodeGen/Alpha/add.ll
@@ -0,0 +1,179 @@
+;test all the shifted and signextending adds and subs with and without consts
+;
+; RUN: llc < %s -march=alpha -o %t.s
+; RUN: grep { addl} %t.s | count 2
+; RUN: grep { addq} %t.s | count 2
+; RUN: grep { subl} %t.s | count 2
+; RUN: grep { subq} %t.s | count 1
+;
+; RUN: grep {lda \$0,-100(\$16)} %t.s | count 1
+; RUN: grep {s4addl} %t.s | count 2
+; RUN: grep {s8addl} %t.s | count 2
+; RUN: grep {s4addq} %t.s | count 2
+; RUN: grep {s8addq} %t.s | count 2
+;
+; RUN: grep {s4subl} %t.s | count 2
+; RUN: grep {s8subl} %t.s | count 2
+; RUN: grep {s4subq} %t.s | count 2
+; RUN: grep {s8subq} %t.s | count 2
+
+
+define i32 @al(i32 signext %x.s, i32 signext %y.s) signext {
+entry:
+ %tmp.3.s = add i32 %y.s, %x.s ; <i32> [#uses=1]
+ ret i32 %tmp.3.s
+}
+
+define i32 @ali(i32 signext %x.s) signext {
+entry:
+ %tmp.3.s = add i32 100, %x.s ; <i32> [#uses=1]
+ ret i32 %tmp.3.s
+}
+
+define i64 @aq(i64 signext %x.s, i64 signext %y.s) signext {
+entry:
+ %tmp.3.s = add i64 %y.s, %x.s ; <i64> [#uses=1]
+ ret i64 %tmp.3.s
+}
+
+define i64 @aqi(i64 %x.s) {
+entry:
+ %tmp.3.s = add i64 100, %x.s ; <i64> [#uses=1]
+ ret i64 %tmp.3.s
+}
+
+define i32 @sl(i32 signext %x.s, i32 signext %y.s) signext {
+entry:
+ %tmp.3.s = sub i32 %y.s, %x.s ; <i32> [#uses=1]
+ ret i32 %tmp.3.s
+}
+
+define i32 @sli(i32 signext %x.s) signext {
+entry:
+ %tmp.3.s = sub i32 %x.s, 100 ; <i32> [#uses=1]
+ ret i32 %tmp.3.s
+}
+
+define i64 @sq(i64 %x.s, i64 %y.s) {
+entry:
+ %tmp.3.s = sub i64 %y.s, %x.s ; <i64> [#uses=1]
+ ret i64 %tmp.3.s
+}
+
+define i64 @sqi(i64 %x.s) {
+entry:
+ %tmp.3.s = sub i64 %x.s, 100 ; <i64> [#uses=1]
+ ret i64 %tmp.3.s
+}
+
+define i32 @a4l(i32 signext %x.s, i32 signext %y.s) signext {
+entry:
+ %tmp.1.s = shl i32 %y.s, 2 ; <i32> [#uses=1]
+ %tmp.3.s = add i32 %tmp.1.s, %x.s ; <i32> [#uses=1]
+ ret i32 %tmp.3.s
+}
+
+define i32 @a8l(i32 signext %x.s, i32 signext %y.s) signext {
+entry:
+ %tmp.1.s = shl i32 %y.s, 3 ; <i32> [#uses=1]
+ %tmp.3.s = add i32 %tmp.1.s, %x.s ; <i32> [#uses=1]
+ ret i32 %tmp.3.s
+}
+
+define i64 @a4q(i64 %x.s, i64 %y.s) {
+entry:
+ %tmp.1.s = shl i64 %y.s, 2 ; <i64> [#uses=1]
+ %tmp.3.s = add i64 %tmp.1.s, %x.s ; <i64> [#uses=1]
+ ret i64 %tmp.3.s
+}
+
+define i64 @a8q(i64 %x.s, i64 %y.s) {
+entry:
+ %tmp.1.s = shl i64 %y.s, 3 ; <i64> [#uses=1]
+ %tmp.3.s = add i64 %tmp.1.s, %x.s ; <i64> [#uses=1]
+ ret i64 %tmp.3.s
+}
+
+define i32 @a4li(i32 signext %y.s) signext {
+entry:
+ %tmp.1.s = shl i32 %y.s, 2 ; <i32> [#uses=1]
+ %tmp.3.s = add i32 100, %tmp.1.s ; <i32> [#uses=1]
+ ret i32 %tmp.3.s
+}
+
+define i32 @a8li(i32 signext %y.s) signext {
+entry:
+ %tmp.1.s = shl i32 %y.s, 3 ; <i32> [#uses=1]
+ %tmp.3.s = add i32 100, %tmp.1.s ; <i32> [#uses=1]
+ ret i32 %tmp.3.s
+}
+
+define i64 @a4qi(i64 %y.s) {
+entry:
+ %tmp.1.s = shl i64 %y.s, 2 ; <i64> [#uses=1]
+ %tmp.3.s = add i64 100, %tmp.1.s ; <i64> [#uses=1]
+ ret i64 %tmp.3.s
+}
+
+define i64 @a8qi(i64 %y.s) {
+entry:
+ %tmp.1.s = shl i64 %y.s, 3 ; <i64> [#uses=1]
+ %tmp.3.s = add i64 100, %tmp.1.s ; <i64> [#uses=1]
+ ret i64 %tmp.3.s
+}
+
+define i32 @s4l(i32 signext %x.s, i32 signext %y.s) signext {
+entry:
+ %tmp.1.s = shl i32 %y.s, 2 ; <i32> [#uses=1]
+ %tmp.3.s = sub i32 %tmp.1.s, %x.s ; <i32> [#uses=1]
+ ret i32 %tmp.3.s
+}
+
+define i32 @s8l(i32 signext %x.s, i32 signext %y.s) signext {
+entry:
+ %tmp.1.s = shl i32 %y.s, 3 ; <i32> [#uses=1]
+ %tmp.3.s = sub i32 %tmp.1.s, %x.s ; <i32> [#uses=1]
+ ret i32 %tmp.3.s
+}
+
+define i64 @s4q(i64 %x.s, i64 %y.s) {
+entry:
+ %tmp.1.s = shl i64 %y.s, 2 ; <i64> [#uses=1]
+ %tmp.3.s = sub i64 %tmp.1.s, %x.s ; <i64> [#uses=1]
+ ret i64 %tmp.3.s
+}
+
+define i64 @s8q(i64 %x.s, i64 %y.s) {
+entry:
+ %tmp.1.s = shl i64 %y.s, 3 ; <i64> [#uses=1]
+ %tmp.3.s = sub i64 %tmp.1.s, %x.s ; <i64> [#uses=1]
+ ret i64 %tmp.3.s
+}
+
+define i32 @s4li(i32 signext %y.s) signext {
+entry:
+ %tmp.1.s = shl i32 %y.s, 2 ; <i32> [#uses=1]
+ %tmp.3.s = sub i32 %tmp.1.s, 100 ; <i32> [#uses=1]
+ ret i32 %tmp.3.s
+}
+
+define i32 @s8li(i32 signext %y.s) signext {
+entry:
+ %tmp.1.s = shl i32 %y.s, 3 ; <i32> [#uses=1]
+ %tmp.3.s = sub i32 %tmp.1.s, 100 ; <i32> [#uses=1]
+ ret i32 %tmp.3.s
+}
+
+define i64 @s4qi(i64 %y.s) {
+entry:
+ %tmp.1.s = shl i64 %y.s, 2 ; <i64> [#uses=1]
+ %tmp.3.s = sub i64 %tmp.1.s, 100 ; <i64> [#uses=1]
+ ret i64 %tmp.3.s
+}
+
+define i64 @s8qi(i64 %y.s) {
+entry:
+ %tmp.1.s = shl i64 %y.s, 3 ; <i64> [#uses=1]
+ %tmp.3.s = sub i64 %tmp.1.s, 100 ; <i64> [#uses=1]
+ ret i64 %tmp.3.s
+}
diff --git a/test/CodeGen/Alpha/add128.ll b/test/CodeGen/Alpha/add128.ll
new file mode 100644
index 0000000..fa3b949
--- /dev/null
+++ b/test/CodeGen/Alpha/add128.ll
@@ -0,0 +1,9 @@
+;test for ADDC and ADDE expansion
+;
+; RUN: llc < %s -march=alpha
+
+define i128 @add128(i128 %x, i128 %y) {
+entry:
+ %tmp = add i128 %y, %x
+ ret i128 %tmp
+}
diff --git a/test/CodeGen/Alpha/bic.ll b/test/CodeGen/Alpha/bic.ll
new file mode 100644
index 0000000..9f00350
--- /dev/null
+++ b/test/CodeGen/Alpha/bic.ll
@@ -0,0 +1,9 @@
+; Make sure this testcase codegens to the bic instruction
+; RUN: llc < %s -march=alpha | grep {bic}
+
+define i64 @bar(i64 %x, i64 %y) {
+entry:
+ %tmp.1 = xor i64 %x, -1 ; <i64> [#uses=1]
+ %tmp.2 = and i64 %y, %tmp.1 ; <i64> [#uses=1]
+ ret i64 %tmp.2
+}
diff --git a/test/CodeGen/Alpha/bsr.ll b/test/CodeGen/Alpha/bsr.ll
new file mode 100644
index 0000000..14f6b46
--- /dev/null
+++ b/test/CodeGen/Alpha/bsr.ll
@@ -0,0 +1,12 @@
+; Make sure this testcase codegens the bsr instruction
+; RUN: llc < %s -march=alpha | grep bsr
+
+define internal i64 @abc(i32 %x) {
+ %tmp.2 = add i32 %x, -1 ; <i32> [#uses=1]
+ %tmp.0 = call i64 @abc( i32 %tmp.2 ) ; <i64> [#uses=1]
+ %tmp.5 = add i32 %x, -2 ; <i32> [#uses=1]
+ %tmp.3 = call i64 @abc( i32 %tmp.5 ) ; <i64> [#uses=1]
+ %tmp.6 = add i64 %tmp.0, %tmp.3 ; <i64> [#uses=1]
+ ret i64 %tmp.6
+}
+
diff --git a/test/CodeGen/Alpha/call_adj.ll b/test/CodeGen/Alpha/call_adj.ll
new file mode 100644
index 0000000..24e97a9
--- /dev/null
+++ b/test/CodeGen/Alpha/call_adj.ll
@@ -0,0 +1,13 @@
+;All this should do is not crash
+;RUN: llc < %s -march=alpha
+
+target datalayout = "e-p:64:64"
+target triple = "alphaev67-unknown-linux-gnu"
+
+define void @_ZNSt13basic_filebufIcSt11char_traitsIcEE22_M_convert_to_externalEPcl(i32 %f) {
+entry:
+ %tmp49 = alloca i8, i32 %f ; <i8*> [#uses=0]
+ %tmp = call i32 null( i8* null, i8* null, i8* null, i8* null, i8* null, i8* null, i8* null ) ; <i32> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/Alpha/cmov.ll b/test/CodeGen/Alpha/cmov.ll
new file mode 100644
index 0000000..9b655f0
--- /dev/null
+++ b/test/CodeGen/Alpha/cmov.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=alpha | not grep cmovlt
+; RUN: llc < %s -march=alpha | grep cmoveq
+
+define i64 @cmov_lt(i64 %a, i64 %c) {
+entry:
+ %tmp.1 = icmp slt i64 %c, 0 ; <i1> [#uses=1]
+ %retval = select i1 %tmp.1, i64 %a, i64 10 ; <i64> [#uses=1]
+ ret i64 %retval
+}
+
+define i64 @cmov_const(i64 %a, i64 %b, i64 %c) {
+entry:
+ %tmp.1 = icmp slt i64 %a, %b ; <i1> [#uses=1]
+ %retval = select i1 %tmp.1, i64 %c, i64 10 ; <i64> [#uses=1]
+ ret i64 %retval
+}
+
+define i64 @cmov_lt2(i64 %a, i64 %c) {
+entry:
+ %tmp.1 = icmp sgt i64 %c, 0 ; <i1> [#uses=1]
+ %retval = select i1 %tmp.1, i64 10, i64 %a ; <i64> [#uses=1]
+ ret i64 %retval
+}
diff --git a/test/CodeGen/Alpha/cmpbge.ll b/test/CodeGen/Alpha/cmpbge.ll
new file mode 100644
index 0000000..e88d2ee
--- /dev/null
+++ b/test/CodeGen/Alpha/cmpbge.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=alpha | grep cmpbge | count 2
+
+define i1 @test1(i64 %A, i64 %B) {
+ %C = and i64 %A, 255 ; <i64> [#uses=1]
+ %D = and i64 %B, 255 ; <i64> [#uses=1]
+ %E = icmp uge i64 %C, %D ; <i1> [#uses=1]
+ ret i1 %E
+}
+
+define i1 @test2(i64 %a, i64 %B) {
+ %A = shl i64 %a, 1 ; <i64> [#uses=1]
+ %C = and i64 %A, 254 ; <i64> [#uses=1]
+ %D = and i64 %B, 255 ; <i64> [#uses=1]
+ %E = icmp uge i64 %C, %D ; <i1> [#uses=1]
+ ret i1 %E
+}
diff --git a/test/CodeGen/Alpha/ctlz.ll b/test/CodeGen/Alpha/ctlz.ll
new file mode 100644
index 0000000..aa1588a
--- /dev/null
+++ b/test/CodeGen/Alpha/ctlz.ll
@@ -0,0 +1,14 @@
+; Make sure this testcase codegens to the ctlz instruction
+; RUN: llc < %s -march=alpha -mcpu=ev67 | grep -i ctlz
+; RUN: llc < %s -march=alpha -mattr=+CIX | grep -i ctlz
+; RUN: llc < %s -march=alpha -mcpu=ev6 | not grep -i ctlz
+; RUN: llc < %s -march=alpha -mattr=-CIX | not grep -i ctlz
+
+declare i8 @llvm.ctlz.i8(i8)
+
+define i32 @bar(i8 %x) {
+entry:
+ %tmp.1 = call i8 @llvm.ctlz.i8( i8 %x )
+ %tmp.2 = sext i8 %tmp.1 to i32
+ ret i32 %tmp.2
+}
diff --git a/test/CodeGen/Alpha/ctlz_e.ll b/test/CodeGen/Alpha/ctlz_e.ll
new file mode 100644
index 0000000..230e096
--- /dev/null
+++ b/test/CodeGen/Alpha/ctlz_e.ll
@@ -0,0 +1,11 @@
+; Make sure this testcase does not use ctpop
+; RUN: llc < %s -march=alpha | not grep -i ctpop
+
+declare i64 @llvm.ctlz.i64(i64)
+
+define i64 @bar(i64 %x) {
+entry:
+ %tmp.1 = call i64 @llvm.ctlz.i64( i64 %x ) ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
diff --git a/test/CodeGen/Alpha/ctpop.ll b/test/CodeGen/Alpha/ctpop.ll
new file mode 100644
index 0000000..f887882
--- /dev/null
+++ b/test/CodeGen/Alpha/ctpop.ll
@@ -0,0 +1,17 @@
+; Make sure this testcase codegens to the ctpop instruction
+; RUN: llc < %s -march=alpha -mcpu=ev67 | grep -i ctpop
+; RUN: llc < %s -march=alpha -mattr=+CIX | \
+; RUN: grep -i ctpop
+; RUN: llc < %s -march=alpha -mcpu=ev6 | \
+; RUN: not grep -i ctpop
+; RUN: llc < %s -march=alpha -mattr=-CIX | \
+; RUN: not grep -i ctpop
+
+declare i64 @llvm.ctpop.i64(i64)
+
+define i64 @bar(i64 %x) {
+entry:
+ %tmp.1 = call i64 @llvm.ctpop.i64( i64 %x ) ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
diff --git a/test/CodeGen/Alpha/dg.exp b/test/CodeGen/Alpha/dg.exp
new file mode 100644
index 0000000..fb9f710
--- /dev/null
+++ b/test/CodeGen/Alpha/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target Alpha] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll}]]
+}
diff --git a/test/CodeGen/Alpha/eqv.ll b/test/CodeGen/Alpha/eqv.ll
new file mode 100644
index 0000000..b3413d6
--- /dev/null
+++ b/test/CodeGen/Alpha/eqv.ll
@@ -0,0 +1,10 @@
+; Make sure this testcase codegens to the eqv instruction
+; RUN: llc < %s -march=alpha | grep eqv
+
+define i64 @bar(i64 %x, i64 %y) {
+entry:
+ %tmp.1 = xor i64 %x, -1 ; <i64> [#uses=1]
+ %tmp.2 = xor i64 %y, %tmp.1 ; <i64> [#uses=1]
+ ret i64 %tmp.2
+}
+
diff --git a/test/CodeGen/Alpha/i32_sub_1.ll b/test/CodeGen/Alpha/i32_sub_1.ll
new file mode 100644
index 0000000..ffeafbd
--- /dev/null
+++ b/test/CodeGen/Alpha/i32_sub_1.ll
@@ -0,0 +1,9 @@
+; Make sure this testcase codegens to the ctpop instruction
+; RUN: llc < %s -march=alpha | grep -i {subl \$16,1,\$0}
+
+
+define i32 @foo(i32 signext %x) signext {
+entry:
+ %tmp.1 = add i32 %x, -1 ; <int> [#uses=1]
+ ret i32 %tmp.1
+}
diff --git a/test/CodeGen/Alpha/illegal-element-type.ll b/test/CodeGen/Alpha/illegal-element-type.ll
new file mode 100644
index 0000000..4cf80de
--- /dev/null
+++ b/test/CodeGen/Alpha/illegal-element-type.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -mtriple=alphaev6-unknown-linux-gnu
+
+define void @foo() {
+entry:
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ br i1 false, label %bb26, label %bb
+
+bb19: ; preds = %bb26
+ ret void
+
+bb26: ; preds = %bb
+ br i1 false, label %bb30, label %bb19
+
+bb30: ; preds = %bb26
+ br label %bb45
+
+bb45: ; preds = %bb45, %bb30
+ %V.0 = phi <8 x i16> [ %tmp42, %bb45 ], [ zeroinitializer, %bb30 ] ; <<8 x i16>> [#uses=1]
+ %tmp42 = mul <8 x i16> zeroinitializer, %V.0 ; <<8 x i16>> [#uses=1]
+ br label %bb45
+}
diff --git a/test/CodeGen/Alpha/jmp_table.ll b/test/CodeGen/Alpha/jmp_table.ll
new file mode 100644
index 0000000..917c932
--- /dev/null
+++ b/test/CodeGen/Alpha/jmp_table.ll
@@ -0,0 +1,99 @@
+; try to check that we have the most important instructions, which shouldn't
+; appear otherwise
+; RUN: llc < %s -march=alpha | grep jmp
+; RUN: llc < %s -march=alpha | grep gprel32
+; RUN: llc < %s -march=alpha | grep ldl
+; RUN: llc < %s -march=alpha | grep rodata
+; END.
+
+target datalayout = "e-p:64:64"
+target triple = "alphaev67-unknown-linux-gnu"
+@str = internal constant [2 x i8] c"1\00" ; <[2 x i8]*> [#uses=1]
+@str1 = internal constant [2 x i8] c"2\00" ; <[2 x i8]*> [#uses=1]
+@str2 = internal constant [2 x i8] c"3\00" ; <[2 x i8]*> [#uses=1]
+@str3 = internal constant [2 x i8] c"4\00" ; <[2 x i8]*> [#uses=1]
+@str4 = internal constant [2 x i8] c"5\00" ; <[2 x i8]*> [#uses=1]
+@str5 = internal constant [2 x i8] c"6\00" ; <[2 x i8]*> [#uses=1]
+@str6 = internal constant [2 x i8] c"7\00" ; <[2 x i8]*> [#uses=1]
+@str7 = internal constant [2 x i8] c"8\00" ; <[2 x i8]*> [#uses=1]
+
+define i32 @main(i32 %x, i8** %y) {
+entry:
+ %x_addr = alloca i32 ; <i32*> [#uses=2]
+ %y_addr = alloca i8** ; <i8***> [#uses=1]
+ %retval = alloca i32, align 4 ; <i32*> [#uses=2]
+ %tmp = alloca i32, align 4 ; <i32*> [#uses=2]
+ %foo = alloca i8*, align 8 ; <i8**> [#uses=9]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %x, i32* %x_addr
+ store i8** %y, i8*** %y_addr
+ %tmp.upgrd.1 = load i32* %x_addr ; <i32> [#uses=1]
+ switch i32 %tmp.upgrd.1, label %bb15 [
+ i32 1, label %bb
+ i32 2, label %bb1
+ i32 3, label %bb3
+ i32 4, label %bb5
+ i32 5, label %bb7
+ i32 6, label %bb9
+ i32 7, label %bb11
+ i32 8, label %bb13
+ ]
+
+bb: ; preds = %entry
+ %tmp.upgrd.2 = getelementptr [2 x i8]* @str, i32 0, i64 0 ; <i8*> [#uses=1]
+ store i8* %tmp.upgrd.2, i8** %foo
+ br label %bb16
+
+bb1: ; preds = %entry
+ %tmp2 = getelementptr [2 x i8]* @str1, i32 0, i64 0 ; <i8*> [#uses=1]
+ store i8* %tmp2, i8** %foo
+ br label %bb16
+
+bb3: ; preds = %entry
+ %tmp4 = getelementptr [2 x i8]* @str2, i32 0, i64 0 ; <i8*> [#uses=1]
+ store i8* %tmp4, i8** %foo
+ br label %bb16
+
+bb5: ; preds = %entry
+ %tmp6 = getelementptr [2 x i8]* @str3, i32 0, i64 0 ; <i8*> [#uses=1]
+ store i8* %tmp6, i8** %foo
+ br label %bb16
+
+bb7: ; preds = %entry
+ %tmp8 = getelementptr [2 x i8]* @str4, i32 0, i64 0 ; <i8*> [#uses=1]
+ store i8* %tmp8, i8** %foo
+ br label %bb16
+
+bb9: ; preds = %entry
+ %tmp10 = getelementptr [2 x i8]* @str5, i32 0, i64 0 ; <i8*> [#uses=1]
+ store i8* %tmp10, i8** %foo
+ br label %bb16
+
+bb11: ; preds = %entry
+ %tmp12 = getelementptr [2 x i8]* @str6, i32 0, i64 0 ; <i8*> [#uses=1]
+ store i8* %tmp12, i8** %foo
+ br label %bb16
+
+bb13: ; preds = %entry
+ %tmp14 = getelementptr [2 x i8]* @str7, i32 0, i64 0 ; <i8*> [#uses=1]
+ store i8* %tmp14, i8** %foo
+ br label %bb16
+
+bb15: ; preds = %entry
+ br label %bb16
+
+bb16: ; preds = %bb15, %bb13, %bb11, %bb9, %bb7, %bb5, %bb3, %bb1, %bb
+ %tmp17 = load i8** %foo ; <i8*> [#uses=1]
+ %tmp18 = call i32 (...)* @print( i8* %tmp17 ) ; <i32> [#uses=0]
+ store i32 0, i32* %tmp
+ %tmp19 = load i32* %tmp ; <i32> [#uses=1]
+ store i32 %tmp19, i32* %retval
+ br label %return
+
+return: ; preds = %bb16
+ %retval.upgrd.3 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval.upgrd.3
+}
+
+declare i32 @print(...)
+
diff --git a/test/CodeGen/Alpha/mb.ll b/test/CodeGen/Alpha/mb.ll
new file mode 100644
index 0000000..93e8b1b
--- /dev/null
+++ b/test/CodeGen/Alpha/mb.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=alpha | grep mb
+
+declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1)
+
+define void @test() {
+ call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true , i1 true)
+ ret void
+}
diff --git a/test/CodeGen/Alpha/mul128.ll b/test/CodeGen/Alpha/mul128.ll
new file mode 100644
index 0000000..daf8409
--- /dev/null
+++ b/test/CodeGen/Alpha/mul128.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=alpha
+
+define i128 @__mulvdi3(i128 %a, i128 %b) nounwind {
+entry:
+ %r = mul i128 %a, %b
+ ret i128 %r
+}
diff --git a/test/CodeGen/Alpha/mul5.ll b/test/CodeGen/Alpha/mul5.ll
new file mode 100644
index 0000000..4075dd6
--- /dev/null
+++ b/test/CodeGen/Alpha/mul5.ll
@@ -0,0 +1,33 @@
+; Make sure this testcase does not use mulq
+; RUN: llc < %s -march=alpha | not grep -i mul
+
+define i64 @foo1(i64 %x) {
+entry:
+ %tmp.1 = mul i64 %x, 9 ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
+define i64 @foo3(i64 %x) {
+entry:
+ %tmp.1 = mul i64 %x, 259 ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
+define i64 @foo4l(i64 %x) {
+entry:
+ %tmp.1 = mul i64 %x, 260 ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
+define i64 @foo8l(i64 %x) {
+entry:
+ %tmp.1 = mul i64 %x, 768 ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
+define i64 @bar(i64 %x) {
+entry:
+ %tmp.1 = mul i64 %x, 5 ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
diff --git a/test/CodeGen/Alpha/neg1.ll b/test/CodeGen/Alpha/neg1.ll
new file mode 100644
index 0000000..0db767f
--- /dev/null
+++ b/test/CodeGen/Alpha/neg1.ll
@@ -0,0 +1,7 @@
+; Make sure this testcase codegens to the lda -1 instruction
+; RUN: llc < %s -march=alpha | grep {\\-1}
+
+define i64 @bar() {
+entry:
+ ret i64 -1
+}
diff --git a/test/CodeGen/Alpha/not.ll b/test/CodeGen/Alpha/not.ll
new file mode 100644
index 0000000..4f0a5c2
--- /dev/null
+++ b/test/CodeGen/Alpha/not.ll
@@ -0,0 +1,8 @@
+; Make sure this testcase codegens to the ornot instruction
+; RUN: llc < %s -march=alpha | grep eqv
+
+define i64 @bar(i64 %x) {
+entry:
+ %tmp.1 = xor i64 %x, -1 ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
diff --git a/test/CodeGen/Alpha/ornot.ll b/test/CodeGen/Alpha/ornot.ll
new file mode 100644
index 0000000..f930e34
--- /dev/null
+++ b/test/CodeGen/Alpha/ornot.ll
@@ -0,0 +1,10 @@
+; Make sure this testcase codegens to the ornot instruction
+; RUN: llc < %s -march=alpha | grep ornot
+
+define i64 @bar(i64 %x, i64 %y) {
+entry:
+ %tmp.1 = xor i64 %x, -1 ; <i64> [#uses=1]
+ %tmp.2 = or i64 %y, %tmp.1 ; <i64> [#uses=1]
+ ret i64 %tmp.2
+}
+
diff --git a/test/CodeGen/Alpha/private.ll b/test/CodeGen/Alpha/private.ll
new file mode 100644
index 0000000..26076e0
--- /dev/null
+++ b/test/CodeGen/Alpha/private.ll
@@ -0,0 +1,21 @@
+; Test to make sure that the 'private' is used correctly.
+;
+; RUN: llc < %s -march=alpha > %t
+; RUN: grep \\\$foo: %t
+; RUN: grep bsr.*\\\$\\\$foo %t
+; RUN: grep \\\$baz: %t
+; RUN: grep ldah.*\\\$baz %t
+
+declare void @foo()
+
+define private void @foo() {
+ ret void
+}
+
+@baz = private global i32 4
+
+define i32 @bar() {
+ call void @foo()
+ %1 = load i32* @baz, align 4
+ ret i32 %1
+}
diff --git a/test/CodeGen/Alpha/rpcc.ll b/test/CodeGen/Alpha/rpcc.ll
new file mode 100644
index 0000000..d6665b5
--- /dev/null
+++ b/test/CodeGen/Alpha/rpcc.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=alpha | grep rpcc
+
+declare i64 @llvm.readcyclecounter()
+
+define i64 @foo() {
+entry:
+ %tmp.1 = call i64 @llvm.readcyclecounter( ) ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
diff --git a/test/CodeGen/Alpha/srl_and.ll b/test/CodeGen/Alpha/srl_and.ll
new file mode 100644
index 0000000..3042ef3
--- /dev/null
+++ b/test/CodeGen/Alpha/srl_and.ll
@@ -0,0 +1,10 @@
+; Make sure this testcase codegens to the zapnot instruction
+; RUN: llc < %s -march=alpha | grep zapnot
+
+define i64 @foo(i64 %y) {
+entry:
+ %tmp = lshr i64 %y, 3 ; <i64> [#uses=1]
+ %tmp2 = and i64 %tmp, 8191 ; <i64> [#uses=1]
+ ret i64 %tmp2
+}
+
diff --git a/test/CodeGen/Alpha/sub128.ll b/test/CodeGen/Alpha/sub128.ll
new file mode 100644
index 0000000..d26404b
--- /dev/null
+++ b/test/CodeGen/Alpha/sub128.ll
@@ -0,0 +1,9 @@
+;test for SUBC and SUBE expansion
+;
+; RUN: llc < %s -march=alpha
+
+define i128 @sub128(i128 %x, i128 %y) {
+entry:
+ %tmp = sub i128 %y, %x
+ ret i128 %tmp
+}
diff --git a/test/CodeGen/Alpha/weak.ll b/test/CodeGen/Alpha/weak.ll
new file mode 100644
index 0000000..ff04de9
--- /dev/null
+++ b/test/CodeGen/Alpha/weak.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=alpha | grep .weak.*f
+; RUN: llc < %s -march=alpha | grep .weak.*h
+
+define weak i32 @f() {
+entry:
+ unreachable
+}
+
+define void @g() {
+entry:
+ tail call void @h( )
+ ret void
+}
+
+declare extern_weak void @h()
+
diff --git a/test/CodeGen/Alpha/wmb.ll b/test/CodeGen/Alpha/wmb.ll
new file mode 100644
index 0000000..a3e2ccf
--- /dev/null
+++ b/test/CodeGen/Alpha/wmb.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=alpha | grep wmb
+
+declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1)
+
+define void @test() {
+ call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true , i1 true)
+ ret void
+}
diff --git a/test/CodeGen/Alpha/zapnot.ll b/test/CodeGen/Alpha/zapnot.ll
new file mode 100644
index 0000000..d00984a
--- /dev/null
+++ b/test/CodeGen/Alpha/zapnot.ll
@@ -0,0 +1,9 @@
+; Make sure this testcase codegens to the bic instruction
+; RUN: llc < %s -march=alpha | grep zapnot
+
+
+define i16 @foo(i64 %y) zeroext {
+entry:
+ %tmp.1 = trunc i64 %y to i16 ; <ushort> [#uses=1]
+ ret i16 %tmp.1
+}
diff --git a/test/CodeGen/Alpha/zapnot2.ll b/test/CodeGen/Alpha/zapnot2.ll
new file mode 100644
index 0000000..cd3caae
--- /dev/null
+++ b/test/CodeGen/Alpha/zapnot2.ll
@@ -0,0 +1,9 @@
+; Make sure this testcase codegens to the zapnot instruction
+; RUN: llc < %s -march=alpha | grep zapnot
+
+define i64 @bar(i64 %x) {
+entry:
+ %tmp.1 = and i64 %x, 16711935 ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
diff --git a/test/CodeGen/Alpha/zapnot3.ll b/test/CodeGen/Alpha/zapnot3.ll
new file mode 100644
index 0000000..f02961f
--- /dev/null
+++ b/test/CodeGen/Alpha/zapnot3.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=alpha | grep zapnot
+
+;demanded bits mess up this mask in a hard to fix way
+;define i64 @foo(i64 %y) {
+; %tmp = and i64 %y, 65535
+; %tmp2 = shr i64 %tmp, i8 3
+; ret i64 %tmp2
+;}
+
+define i64 @foo2(i64 %y) {
+ %tmp = lshr i64 %y, 3 ; <i64> [#uses=1]
+ %tmp2 = and i64 %tmp, 8191 ; <i64> [#uses=1]
+ ret i64 %tmp2
+}
+
diff --git a/test/CodeGen/Alpha/zapnot4.ll b/test/CodeGen/Alpha/zapnot4.ll
new file mode 100644
index 0000000..89beeef
--- /dev/null
+++ b/test/CodeGen/Alpha/zapnot4.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=alpha | grep zapnot
+
+define i64 @foo(i64 %y) {
+ %tmp = shl i64 %y, 3 ; <i64> [#uses=1]
+ %tmp2 = and i64 %tmp, 65535 ; <i64> [#uses=1]
+ ret i64 %tmp2
+}
diff --git a/test/CodeGen/Blackfin/2009-08-04-LowerExtract-Live.ll b/test/CodeGen/Blackfin/2009-08-04-LowerExtract-Live.ll
new file mode 100644
index 0000000..3ee5e8d
--- /dev/null
+++ b/test/CodeGen/Blackfin/2009-08-04-LowerExtract-Live.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=bfin -join-liveintervals=0 -verify-machineinstrs
+
+; Provoke an error in LowerSubregsPass::LowerExtract where the live range of a
+; super-register is illegally extended.
+
+define i16 @f(i16 %x1, i16 %x2, i16 %x3, i16 %x4) {
+ %y1 = add i16 %x1, 1
+ %y2 = add i16 %x2, 2
+ %y3 = add i16 %x3, 3
+ %y4 = add i16 %x4, 4
+ %z12 = add i16 %y1, %y2
+ %z34 = add i16 %y3, %y4
+ %p = add i16 %z12, %z34
+ ret i16 %p
+}
diff --git a/test/CodeGen/Blackfin/2009-08-11-RegScavenger-CSR.ll b/test/CodeGen/Blackfin/2009-08-11-RegScavenger-CSR.ll
new file mode 100644
index 0000000..e5d1637
--- /dev/null
+++ b/test/CodeGen/Blackfin/2009-08-11-RegScavenger-CSR.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+
+declare i64 @llvm.cttz.i64(i64) nounwind readnone
+
+declare i16 @llvm.cttz.i16(i16) nounwind readnone
+
+declare i8 @llvm.cttz.i8(i8) nounwind readnone
+
+define void @cttztest(i8 %A, i16 %B, i32 %C, i64 %D, i8* %AP, i16* %BP, i32* %CP, i64* %DP) {
+ %a = call i8 @llvm.cttz.i8(i8 %A) ; <i8> [#uses=1]
+ %b = call i16 @llvm.cttz.i16(i16 %B) ; <i16> [#uses=1]
+ %d = call i64 @llvm.cttz.i64(i64 %D) ; <i64> [#uses=1]
+ store i8 %a, i8* %AP
+ store i16 %b, i16* %BP
+ store i64 %d, i64* %DP
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll b/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll
new file mode 100644
index 0000000..0b731dc
--- /dev/null
+++ b/test/CodeGen/Blackfin/2009-08-15-LiveIn-SubReg.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+
+; When joining live intervals of sub-registers, an MBB live-in list is not
+; updated properly. The register scavenger asserts on an undefined register.
+
+define i32 @foo(i8 %bar) {
+entry:
+ switch i8 %bar, label %bb1203 [
+ i8 117, label %bb1204
+ i8 85, label %bb1204
+ i8 106, label %bb1204
+ ]
+
+bb1203: ; preds = %entry
+ ret i32 1
+
+bb1204: ; preds = %entry, %entry, %entry
+ ret i32 2
+}
diff --git a/test/CodeGen/Blackfin/2009-08-15-MissingDead.ll b/test/CodeGen/Blackfin/2009-08-15-MissingDead.ll
new file mode 100644
index 0000000..dcc3ea0
--- /dev/null
+++ b/test/CodeGen/Blackfin/2009-08-15-MissingDead.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+
+; LocalRewriter can forget to transfer a <def,dead> flag when setting up call
+; argument registers. This then causes register scavenger asserts.
+
+declare i32 @printf(i8*, i32, float)
+
+define i32 @testissue(i32 %i, float %x, float %y) {
+ br label %bb1
+
+bb1: ; preds = %bb1, %0
+ %x2 = fmul float %x, 5.000000e-01 ; <float> [#uses=1]
+ %y2 = fmul float %y, 0x3FECCCCCC0000000 ; <float> [#uses=1]
+ %z2 = fadd float %x2, %y2 ; <float> [#uses=1]
+ %z3 = fadd float undef, %z2 ; <float> [#uses=1]
+ %i1 = shl i32 %i, 3 ; <i32> [#uses=1]
+ %j1 = add i32 %i, 7 ; <i32> [#uses=1]
+ %m1 = add i32 %i1, %j1 ; <i32> [#uses=2]
+ %b = icmp sle i32 %m1, 6 ; <i1> [#uses=1]
+ br i1 %b, label %bb1, label %bb2
+
+bb2: ; preds = %bb1
+ %1 = call i32 @printf(i8* undef, i32 %m1, float %z3); <i32> [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/Blackfin/2009-08-15-SetCC-Undef.ll b/test/CodeGen/Blackfin/2009-08-15-SetCC-Undef.ll
new file mode 100644
index 0000000..b6cd2d4
--- /dev/null
+++ b/test/CodeGen/Blackfin/2009-08-15-SetCC-Undef.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+
+; An undef argument causes a setugt node to escape instruction selection.
+
+define void @bugt() {
+cond_next305:
+ %tmp306307 = trunc i32 undef to i8 ; <i8> [#uses=1]
+ %tmp308 = icmp ugt i8 %tmp306307, 6 ; <i1> [#uses=1]
+ br i1 %tmp308, label %bb311, label %bb314
+
+bb311: ; preds = %cond_next305
+ unreachable
+
+bb314: ; preds = %cond_next305
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/add-overflow.ll b/test/CodeGen/Blackfin/add-overflow.ll
new file mode 100644
index 0000000..e982e43
--- /dev/null
+++ b/test/CodeGen/Blackfin/add-overflow.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs > %t
+
+ type { i24, i1 } ; type %0
+
+define i1 @func2(i24 zeroext %v1, i24 zeroext %v2) nounwind {
+entry:
+ %t = call %0 @llvm.uadd.with.overflow.i24(i24 %v1, i24 %v2) ; <%0> [#uses=1]
+ %obit = extractvalue %0 %t, 1 ; <i1> [#uses=1]
+ br i1 %obit, label %carry, label %normal
+
+normal: ; preds = %entry
+ ret i1 true
+
+carry: ; preds = %entry
+ ret i1 false
+}
+
+declare %0 @llvm.uadd.with.overflow.i24(i24, i24) nounwind
diff --git a/test/CodeGen/Blackfin/add.ll b/test/CodeGen/Blackfin/add.ll
new file mode 100644
index 0000000..3311c03
--- /dev/null
+++ b/test/CodeGen/Blackfin/add.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+define i32 @add(i32 %A, i32 %B) {
+ %R = add i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
diff --git a/test/CodeGen/Blackfin/addsub-i128.ll b/test/CodeGen/Blackfin/addsub-i128.ll
new file mode 100644
index 0000000..dd56101
--- /dev/null
+++ b/test/CodeGen/Blackfin/addsub-i128.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+
+; These functions have just the right size to annoy the register scavenger: They
+; use all the scratch registers, but not all the callee-saved registers.
+
+define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
+entry:
+ %tmp1 = zext i64 %AL to i128 ; <i128> [#uses=1]
+ %tmp23 = zext i64 %AH to i128 ; <i128> [#uses=1]
+ %tmp4 = shl i128 %tmp23, 64 ; <i128> [#uses=1]
+ %tmp5 = or i128 %tmp4, %tmp1 ; <i128> [#uses=1]
+ %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1]
+ %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
+ %tmp11 = shl i128 %tmp89, 64 ; <i128> [#uses=1]
+ %tmp12 = or i128 %tmp11, %tmp67 ; <i128> [#uses=1]
+ %tmp15 = add i128 %tmp12, %tmp5 ; <i128> [#uses=2]
+ %tmp1617 = trunc i128 %tmp15 to i64 ; <i64> [#uses=1]
+ store i64 %tmp1617, i64* %RL
+ %tmp21 = lshr i128 %tmp15, 64 ; <i128> [#uses=1]
+ %tmp2122 = trunc i128 %tmp21 to i64 ; <i64> [#uses=1]
+ store i64 %tmp2122, i64* %RH
+ ret void
+}
+
+define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
+entry:
+ %tmp1 = zext i64 %AL to i128 ; <i128> [#uses=1]
+ %tmp23 = zext i64 %AH to i128 ; <i128> [#uses=1]
+ %tmp4 = shl i128 %tmp23, 64 ; <i128> [#uses=1]
+ %tmp5 = or i128 %tmp4, %tmp1 ; <i128> [#uses=1]
+ %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1]
+ %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
+ %tmp11 = shl i128 %tmp89, 64 ; <i128> [#uses=1]
+ %tmp12 = or i128 %tmp11, %tmp67 ; <i128> [#uses=1]
+ %tmp15 = sub i128 %tmp5, %tmp12 ; <i128> [#uses=2]
+ %tmp1617 = trunc i128 %tmp15 to i64 ; <i64> [#uses=1]
+ store i64 %tmp1617, i64* %RL
+ %tmp21 = lshr i128 %tmp15, 64 ; <i128> [#uses=1]
+ %tmp2122 = trunc i128 %tmp21 to i64 ; <i64> [#uses=1]
+ store i64 %tmp2122, i64* %RH
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/basic-i1.ll b/test/CodeGen/Blackfin/basic-i1.ll
new file mode 100644
index 0000000..c63adab
--- /dev/null
+++ b/test/CodeGen/Blackfin/basic-i1.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -march=bfin > %t
+
+define i1 @add(i1 %A, i1 %B) {
+ %R = add i1 %A, %B ; <i1> [#uses=1]
+ ret i1 %R
+}
+
+define i1 @sub(i1 %A, i1 %B) {
+ %R = sub i1 %A, %B ; <i1> [#uses=1]
+ ret i1 %R
+}
+
+define i1 @mul(i1 %A, i1 %B) {
+ %R = mul i1 %A, %B ; <i1> [#uses=1]
+ ret i1 %R
+}
+
+define i1 @sdiv(i1 %A, i1 %B) {
+ %R = sdiv i1 %A, %B ; <i1> [#uses=1]
+ ret i1 %R
+}
+
+define i1 @udiv(i1 %A, i1 %B) {
+ %R = udiv i1 %A, %B ; <i1> [#uses=1]
+ ret i1 %R
+}
+
+define i1 @srem(i1 %A, i1 %B) {
+ %R = srem i1 %A, %B ; <i1> [#uses=1]
+ ret i1 %R
+}
+
+define i1 @urem(i1 %A, i1 %B) {
+ %R = urem i1 %A, %B ; <i1> [#uses=1]
+ ret i1 %R
+}
+
+define i1 @and(i1 %A, i1 %B) {
+ %R = and i1 %A, %B ; <i1> [#uses=1]
+ ret i1 %R
+}
+
+define i1 @or(i1 %A, i1 %B) {
+ %R = or i1 %A, %B ; <i1> [#uses=1]
+ ret i1 %R
+}
+
+define i1 @xor(i1 %A, i1 %B) {
+ %R = xor i1 %A, %B ; <i1> [#uses=1]
+ ret i1 %R
+}
diff --git a/test/CodeGen/Blackfin/basic-i16.ll b/test/CodeGen/Blackfin/basic-i16.ll
new file mode 100644
index 0000000..541e9a8
--- /dev/null
+++ b/test/CodeGen/Blackfin/basic-i16.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -march=bfin
+
+define i16 @add(i16 %A, i16 %B) {
+ %R = add i16 %A, %B ; <i16> [#uses=1]
+ ret i16 %R
+}
+
+define i16 @sub(i16 %A, i16 %B) {
+ %R = sub i16 %A, %B ; <i16> [#uses=1]
+ ret i16 %R
+}
+
+define i16 @mul(i16 %A, i16 %B) {
+ %R = mul i16 %A, %B ; <i16> [#uses=1]
+ ret i16 %R
+}
+
+define i16 @sdiv(i16 %A, i16 %B) {
+ %R = sdiv i16 %A, %B ; <i16> [#uses=1]
+ ret i16 %R
+}
+
+define i16 @udiv(i16 %A, i16 %B) {
+ %R = udiv i16 %A, %B ; <i16> [#uses=1]
+ ret i16 %R
+}
+
+define i16 @srem(i16 %A, i16 %B) {
+ %R = srem i16 %A, %B ; <i16> [#uses=1]
+ ret i16 %R
+}
+
+define i16 @urem(i16 %A, i16 %B) {
+ %R = urem i16 %A, %B ; <i16> [#uses=1]
+ ret i16 %R
+}
diff --git a/test/CodeGen/Blackfin/basic-i32.ll b/test/CodeGen/Blackfin/basic-i32.ll
new file mode 100644
index 0000000..4b5dbfcb
--- /dev/null
+++ b/test/CodeGen/Blackfin/basic-i32.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+
+define i32 @add(i32 %A, i32 %B) {
+ %R = add i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @sub(i32 %A, i32 %B) {
+ %R = sub i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @mul(i32 %A, i32 %B) {
+ %R = mul i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @sdiv(i32 %A, i32 %B) {
+ %R = sdiv i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @udiv(i32 %A, i32 %B) {
+ %R = udiv i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @srem(i32 %A, i32 %B) {
+ %R = srem i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @urem(i32 %A, i32 %B) {
+ %R = urem i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @and(i32 %A, i32 %B) {
+ %R = and i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @or(i32 %A, i32 %B) {
+ %R = or i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @xor(i32 %A, i32 %B) {
+ %R = xor i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
diff --git a/test/CodeGen/Blackfin/basic-i64.ll b/test/CodeGen/Blackfin/basic-i64.ll
new file mode 100644
index 0000000..d4dd8e2
--- /dev/null
+++ b/test/CodeGen/Blackfin/basic-i64.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+
+define i64 @add(i64 %A, i64 %B) {
+ %R = add i64 %A, %B ; <i64> [#uses=1]
+ ret i64 %R
+}
+
+define i64 @sub(i64 %A, i64 %B) {
+ %R = sub i64 %A, %B ; <i64> [#uses=1]
+ ret i64 %R
+}
+
+define i64 @mul(i64 %A, i64 %B) {
+ %R = mul i64 %A, %B ; <i64> [#uses=1]
+ ret i64 %R
+}
+
+define i64 @sdiv(i64 %A, i64 %B) {
+ %R = sdiv i64 %A, %B ; <i64> [#uses=1]
+ ret i64 %R
+}
+
+define i64 @udiv(i64 %A, i64 %B) {
+ %R = udiv i64 %A, %B ; <i64> [#uses=1]
+ ret i64 %R
+}
+
+define i64 @srem(i64 %A, i64 %B) {
+ %R = srem i64 %A, %B ; <i64> [#uses=1]
+ ret i64 %R
+}
+
+define i64 @urem(i64 %A, i64 %B) {
+ %R = urem i64 %A, %B ; <i64> [#uses=1]
+ ret i64 %R
+}
+
+define i64 @and(i64 %A, i64 %B) {
+ %R = and i64 %A, %B ; <i64> [#uses=1]
+ ret i64 %R
+}
+
+define i64 @or(i64 %A, i64 %B) {
+ %R = or i64 %A, %B ; <i64> [#uses=1]
+ ret i64 %R
+}
+
+define i64 @xor(i64 %A, i64 %B) {
+ %R = xor i64 %A, %B ; <i64> [#uses=1]
+ ret i64 %R
+}
diff --git a/test/CodeGen/Blackfin/basic-i8.ll b/test/CodeGen/Blackfin/basic-i8.ll
new file mode 100644
index 0000000..2c7ce9d
--- /dev/null
+++ b/test/CodeGen/Blackfin/basic-i8.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -march=bfin
+
+define i8 @add(i8 %A, i8 %B) {
+ %R = add i8 %A, %B ; <i8> [#uses=1]
+ ret i8 %R
+}
+
+define i8 @sub(i8 %A, i8 %B) {
+ %R = sub i8 %A, %B ; <i8> [#uses=1]
+ ret i8 %R
+}
+
+define i8 @mul(i8 %A, i8 %B) {
+ %R = mul i8 %A, %B ; <i8> [#uses=1]
+ ret i8 %R
+}
+
+define i8 @sdiv(i8 %A, i8 %B) {
+ %R = sdiv i8 %A, %B ; <i8> [#uses=1]
+ ret i8 %R
+}
+
+define i8 @udiv(i8 %A, i8 %B) {
+ %R = udiv i8 %A, %B ; <i8> [#uses=1]
+ ret i8 %R
+}
+
+define i8 @srem(i8 %A, i8 %B) {
+ %R = srem i8 %A, %B ; <i8> [#uses=1]
+ ret i8 %R
+}
+
+define i8 @urem(i8 %A, i8 %B) {
+ %R = urem i8 %A, %B ; <i8> [#uses=1]
+ ret i8 %R
+}
+
+define i8 @and(i8 %A, i8 %B) {
+ %R = and i8 %A, %B ; <i8> [#uses=1]
+ ret i8 %R
+}
+
+define i8 @or(i8 %A, i8 %B) {
+ %R = or i8 %A, %B ; <i8> [#uses=1]
+ ret i8 %R
+}
+
+define i8 @xor(i8 %A, i8 %B) {
+ %R = xor i8 %A, %B ; <i8> [#uses=1]
+ ret i8 %R
+}
diff --git a/test/CodeGen/Blackfin/basictest.ll b/test/CodeGen/Blackfin/basictest.ll
new file mode 100644
index 0000000..85040df
--- /dev/null
+++ b/test/CodeGen/Blackfin/basictest.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+
+define void @void(i32, i32) {
+ add i32 0, 0 ; <i32>:3 [#uses=2]
+ sub i32 0, 4 ; <i32>:4 [#uses=2]
+ br label %5
+
+; <label>:5 ; preds = %5, %2
+ add i32 %0, %1 ; <i32>:6 [#uses=2]
+ sub i32 %6, %4 ; <i32>:7 [#uses=1]
+ icmp sle i32 %7, %3 ; <i1>:8 [#uses=1]
+ br i1 %8, label %9, label %5
+
+; <label>:9 ; preds = %5
+ add i32 %0, %1 ; <i32>:10 [#uses=0]
+ sub i32 %6, %4 ; <i32>:11 [#uses=1]
+ icmp sle i32 %11, %3 ; <i1>:12 [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/burg.ll b/test/CodeGen/Blackfin/burg.ll
new file mode 100644
index 0000000..8cc3713
--- /dev/null
+++ b/test/CodeGen/Blackfin/burg.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs > %t
+
+ %IntList = type %struct.intlist*
+ %ReadFn = type i32 ()*
+ %YYSTYPE = type { %IntList }
+ %struct.intlist = type { i32, %IntList }
+@yyval = external global %YYSTYPE ; <%YYSTYPE*> [#uses=1]
+
+define i32 @yyparse() {
+bb0:
+ %reg254 = load i16* null ; <i16> [#uses=1]
+ %reg254-idxcast = sext i16 %reg254 to i64 ; <i64> [#uses=1]
+ %reg254-idxcast-scale = mul i64 %reg254-idxcast, -1 ; <i64> [#uses=1]
+ %reg254-idxcast-scale-offset = add i64 %reg254-idxcast-scale, 1 ; <i64> [#uses=1]
+ %reg261.idx1 = getelementptr %YYSTYPE* null, i64 %reg254-idxcast-scale-offset, i32 0 ; <%IntList*> [#uses=1]
+ %reg261 = load %IntList* %reg261.idx1 ; <%IntList> [#uses=1]
+ store %IntList %reg261, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ unreachable
+}
diff --git a/test/CodeGen/Blackfin/cmp-small-imm.ll b/test/CodeGen/Blackfin/cmp-small-imm.ll
new file mode 100644
index 0000000..e1732a8
--- /dev/null
+++ b/test/CodeGen/Blackfin/cmp-small-imm.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=bfin > %t
+
+define i1 @cmp3(i32 %A) {
+ %R = icmp uge i32 %A, 2
+ ret i1 %R
+}
diff --git a/test/CodeGen/Blackfin/cmp64.ll b/test/CodeGen/Blackfin/cmp64.ll
new file mode 100644
index 0000000..ef5bf45
--- /dev/null
+++ b/test/CodeGen/Blackfin/cmp64.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=bfin
+
+; This test tries to use a JustCC register as a data operand for MOVEcc. It
+; calls copyRegToReg(JustCC -> DP), failing because JustCC can only be copied to
+; D. The proper solution would be to restrict the virtual register to D only.
+
+define i32 @main() {
+entry:
+ br label %loopentry
+
+loopentry:
+ %done = icmp sle i64 undef, 5
+ br i1 %done, label %loopentry, label %exit.1
+
+exit.1:
+ ret i32 0
+}
diff --git a/test/CodeGen/Blackfin/ct32.ll b/test/CodeGen/Blackfin/ct32.ll
new file mode 100644
index 0000000..363286d
--- /dev/null
+++ b/test/CodeGen/Blackfin/ct32.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=bfin
+
+declare i32 @llvm.ctlz.i32(i32)
+declare i32 @llvm.cttz.i32(i32)
+declare i32 @llvm.ctpop.i32(i32)
+
+define i32 @ctlztest(i32 %B) {
+ %b = call i32 @llvm.ctlz.i32( i32 %B )
+ ret i32 %b
+}
+
+define i32 @cttztest(i32 %B) {
+ %b = call i32 @llvm.cttz.i32( i32 %B )
+ ret i32 %b
+}
+
+define i32 @ctpoptest(i32 %B) {
+ %b = call i32 @llvm.ctpop.i32( i32 %B )
+ ret i32 %b
+}
diff --git a/test/CodeGen/Blackfin/ct64.ll b/test/CodeGen/Blackfin/ct64.ll
new file mode 100644
index 0000000..7502434
--- /dev/null
+++ b/test/CodeGen/Blackfin/ct64.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=bfin
+
+declare i64 @llvm.ctlz.i64(i64)
+declare i64 @llvm.cttz.i64(i64)
+declare i64 @llvm.ctpop.i64(i64)
+
+define i64 @ctlztest(i64 %B) {
+ %b = call i64 @llvm.ctlz.i64( i64 %B )
+ ret i64 %b
+}
+
+define i64 @cttztest(i64 %B) {
+ %b = call i64 @llvm.cttz.i64( i64 %B )
+ ret i64 %b
+}
+
+define i64 @ctpoptest(i64 %B) {
+ %b = call i64 @llvm.ctpop.i64( i64 %B )
+ ret i64 %b
+}
diff --git a/test/CodeGen/Blackfin/ctlz16.ll b/test/CodeGen/Blackfin/ctlz16.ll
new file mode 100644
index 0000000..eb4af23
--- /dev/null
+++ b/test/CodeGen/Blackfin/ctlz16.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=bfin
+
+declare i16 @llvm.ctlz.i16(i16)
+
+define i16 @ctlztest(i16 %B) {
+ %b = call i16 @llvm.ctlz.i16( i16 %B ) ; <i16> [#uses=1]
+ ret i16 %b
+}
+define i16 @ctlztest_z(i16 zeroext %B) {
+ %b = call i16 @llvm.ctlz.i16( i16 %B ) ; <i16> [#uses=1]
+ ret i16 %b
+}
+
+define i16 @ctlztest_s(i16 signext %B) {
+ %b = call i16 @llvm.ctlz.i16( i16 %B ) ; <i16> [#uses=1]
+ ret i16 %b
+}
+
diff --git a/test/CodeGen/Blackfin/ctlz64.ll b/test/CodeGen/Blackfin/ctlz64.ll
new file mode 100644
index 0000000..3e22f88
--- /dev/null
+++ b/test/CodeGen/Blackfin/ctlz64.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs > %t
+
[email protected] = external constant [14 x i8] ; <[14 x i8]*> [#uses=1]
+
+define i32 @main(i64 %arg) nounwind {
+entry:
+ %tmp47 = tail call i64 @llvm.cttz.i64(i64 %arg) ; <i64> [#uses=1]
+ %tmp48 = trunc i64 %tmp47 to i32 ; <i32> [#uses=1]
+ %tmp40 = tail call i32 (i8*, ...)* @printf(i8* noalias getelementptr ([14 x i8]* @.str, i32 0, i32 0), i64 %arg, i32 0, i32 %tmp48, i32 0) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
+
+declare i32 @printf(i8* noalias, ...) nounwind
+
+declare i64 @llvm.cttz.i64(i64) nounwind readnone
diff --git a/test/CodeGen/Blackfin/ctpop16.ll b/test/CodeGen/Blackfin/ctpop16.ll
new file mode 100644
index 0000000..8b6c07e
--- /dev/null
+++ b/test/CodeGen/Blackfin/ctpop16.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=bfin
+
+declare i16 @llvm.ctpop.i16(i16)
+
+define i16 @ctpoptest(i16 %B) {
+ %b = call i16 @llvm.ctpop.i16( i16 %B ) ; <i16> [#uses=1]
+ ret i16 %b
+}
+define i16 @ctpoptest_z(i16 zeroext %B) {
+ %b = call i16 @llvm.ctpop.i16( i16 %B ) ; <i16> [#uses=1]
+ ret i16 %b
+}
+
+define i16 @ctpoptest_s(i16 signext %B) {
+ %b = call i16 @llvm.ctpop.i16( i16 %B ) ; <i16> [#uses=1]
+ ret i16 %b
+}
+
diff --git a/test/CodeGen/Blackfin/cttz16.ll b/test/CodeGen/Blackfin/cttz16.ll
new file mode 100644
index 0000000..510882a
--- /dev/null
+++ b/test/CodeGen/Blackfin/cttz16.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=bfin
+
+declare i16 @llvm.cttz.i16(i16)
+
+define i16 @cttztest(i16 %B) {
+ %b = call i16 @llvm.cttz.i16( i16 %B ) ; <i16> [#uses=1]
+ ret i16 %b
+}
+define i16 @cttztest_z(i16 zeroext %B) {
+ %b = call i16 @llvm.cttz.i16( i16 %B ) ; <i16> [#uses=1]
+ ret i16 %b
+}
+
+define i16 @cttztest_s(i16 signext %B) {
+ %b = call i16 @llvm.cttz.i16( i16 %B ) ; <i16> [#uses=1]
+ ret i16 %b
+}
+
diff --git a/test/CodeGen/Blackfin/cycles.ll b/test/CodeGen/Blackfin/cycles.ll
new file mode 100644
index 0000000..6451c74
--- /dev/null
+++ b/test/CodeGen/Blackfin/cycles.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=bfin | FileCheck %s
+
+declare i64 @llvm.readcyclecounter()
+
+; CHECK: cycles
+; CHECK: cycles2
+define i64 @cyc64() {
+ %tmp.1 = call i64 @llvm.readcyclecounter()
+ ret i64 %tmp.1
+}
+
+; CHECK: cycles
+define i32@cyc32() {
+ %tmp.1 = call i64 @llvm.readcyclecounter()
+ %s = trunc i64 %tmp.1 to i32
+ ret i32 %s
+}
diff --git a/test/CodeGen/Blackfin/dg.exp b/test/CodeGen/Blackfin/dg.exp
new file mode 100644
index 0000000..5fdbe5f
--- /dev/null
+++ b/test/CodeGen/Blackfin/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target Blackfin] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/Blackfin/double-cast.ll b/test/CodeGen/Blackfin/double-cast.ll
new file mode 100644
index 0000000..815ca79
--- /dev/null
+++ b/test/CodeGen/Blackfin/double-cast.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=bfin
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+ %1 = call i32 (i8*, ...)* @printf(i8* undef, double undef)
+ ret i32 0
+}
diff --git a/test/CodeGen/Blackfin/frameindex.ll b/test/CodeGen/Blackfin/frameindex.ll
new file mode 100644
index 0000000..7e677fb
--- /dev/null
+++ b/test/CodeGen/Blackfin/frameindex.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+
+declare i32 @SIM(i8*, i8*, i32, i32, i32, [256 x i32]*, i32, i32, i32)
+
+define void @foo() {
+bb0:
+ %V = alloca [256 x i32], i32 256 ; <[256 x i32]*> [#uses=1]
+ %0 = call i32 @SIM(i8* null, i8* null, i32 0, i32 0, i32 0, [256 x i32]* %V, i32 0, i32 0, i32 2) ; <i32> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/i17mem.ll b/test/CodeGen/Blackfin/i17mem.ll
new file mode 100644
index 0000000..bc5ade7
--- /dev/null
+++ b/test/CodeGen/Blackfin/i17mem.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+@i17_l = external global i17 ; <i17*> [#uses=1]
+@i17_s = external global i17 ; <i17*> [#uses=1]
+
+define void @i17_ls() nounwind {
+ %tmp = load i17* @i17_l ; <i17> [#uses=1]
+ store i17 %tmp, i17* @i17_s
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/i1mem.ll b/test/CodeGen/Blackfin/i1mem.ll
new file mode 100644
index 0000000..cb03e3d
--- /dev/null
+++ b/test/CodeGen/Blackfin/i1mem.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+@i1_l = external global i1 ; <i1*> [#uses=1]
+@i1_s = external global i1 ; <i1*> [#uses=1]
+
+define void @i1_ls() nounwind {
+ %tmp = load i1* @i1_l ; <i1> [#uses=1]
+ store i1 %tmp, i1* @i1_s
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/i1ops.ll b/test/CodeGen/Blackfin/i1ops.ll
new file mode 100644
index 0000000..6b5612c
--- /dev/null
+++ b/test/CodeGen/Blackfin/i1ops.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+
+define i32 @adj(i32 %d.1, i32 %ct.1) {
+entry:
+ %tmp.22.not = trunc i32 %ct.1 to i1 ; <i1> [#uses=1]
+ %tmp.221 = xor i1 %tmp.22.not, true ; <i1> [#uses=1]
+ %tmp.26 = or i1 false, %tmp.221 ; <i1> [#uses=1]
+ %tmp.27 = zext i1 %tmp.26 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp.27
+}
diff --git a/test/CodeGen/Blackfin/i216mem.ll b/test/CodeGen/Blackfin/i216mem.ll
new file mode 100644
index 0000000..9f8cf48
--- /dev/null
+++ b/test/CodeGen/Blackfin/i216mem.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+@i216_l = external global i216 ; <i216*> [#uses=1]
+@i216_s = external global i216 ; <i216*> [#uses=1]
+
+define void @i216_ls() nounwind {
+ %tmp = load i216* @i216_l ; <i216> [#uses=1]
+ store i216 %tmp, i216* @i216_s
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/i248mem.ll b/test/CodeGen/Blackfin/i248mem.ll
new file mode 100644
index 0000000..db23f54
--- /dev/null
+++ b/test/CodeGen/Blackfin/i248mem.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=bfin
+@i248_l = external global i248 ; <i248*> [#uses=1]
+@i248_s = external global i248 ; <i248*> [#uses=1]
+
+define void @i248_ls() nounwind {
+ %tmp = load i248* @i248_l ; <i248> [#uses=1]
+ store i248 %tmp, i248* @i248_s
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/i256mem.ll b/test/CodeGen/Blackfin/i256mem.ll
new file mode 100644
index 0000000..bc5ade7
--- /dev/null
+++ b/test/CodeGen/Blackfin/i256mem.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+@i17_l = external global i17 ; <i17*> [#uses=1]
+@i17_s = external global i17 ; <i17*> [#uses=1]
+
+define void @i17_ls() nounwind {
+ %tmp = load i17* @i17_l ; <i17> [#uses=1]
+ store i17 %tmp, i17* @i17_s
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/i256param.ll b/test/CodeGen/Blackfin/i256param.ll
new file mode 100644
index 0000000..df74c9a
--- /dev/null
+++ b/test/CodeGen/Blackfin/i256param.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+@i256_s = external global i256 ; <i256*> [#uses=1]
+
+define void @i256_ls(i256 %x) nounwind {
+ store i256 %x, i256* @i256_s
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/i56param.ll b/test/CodeGen/Blackfin/i56param.ll
new file mode 100644
index 0000000..ca02563
--- /dev/null
+++ b/test/CodeGen/Blackfin/i56param.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+@i56_l = external global i56 ; <i56*> [#uses=1]
+@i56_s = external global i56 ; <i56*> [#uses=1]
+
+define void @i56_ls(i56 %x) nounwind {
+ store i56 %x, i56* @i56_s
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/i8mem.ll b/test/CodeGen/Blackfin/i8mem.ll
new file mode 100644
index 0000000..ea3a67e
--- /dev/null
+++ b/test/CodeGen/Blackfin/i8mem.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=bfin
+
+@i8_l = external global i8 ; <i8*> [#uses=1]
+@i8_s = external global i8 ; <i8*> [#uses=1]
+
+define void @i8_ls() nounwind {
+ %tmp = load i8* @i8_l ; <i8> [#uses=1]
+ store i8 %tmp, i8* @i8_s
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/inline-asm.ll b/test/CodeGen/Blackfin/inline-asm.ll
new file mode 100644
index 0000000..d623f6b
--- /dev/null
+++ b/test/CodeGen/Blackfin/inline-asm.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -march=bfin | FileCheck %s
+
+; Standard "r"
+; CHECK: r0 = r0 + r1;
+define i32 @add_r(i32 %A, i32 %B) {
+ %R = call i32 asm "$0 = $1 + $2;", "=r,r,r"( i32 %A, i32 %B ) nounwind
+ ret i32 %R
+}
+
+; Target "d"
+; CHECK: r0 = r0 - r1;
+define i32 @add_d(i32 %A, i32 %B) {
+ %R = call i32 asm "$0 = $1 - $2;", "=d,d,d"( i32 %A, i32 %B ) nounwind
+ ret i32 %R
+}
+
+; Target "a" for P-regs
+; CHECK: p0 = (p0 + p1) << 1;
+define i32 @add_a(i32 %A, i32 %B) {
+ %R = call i32 asm "$0 = ($1 + $2) << 1;", "=a,a,a"( i32 %A, i32 %B ) nounwind
+ ret i32 %R
+}
+
+; Target "z" for P0, P1, P2. This is not a real regclass
+; CHECK: p0 = (p0 + p1) << 2;
+define i32 @add_Z(i32 %A, i32 %B) {
+ %R = call i32 asm "$0 = ($1 + $2) << 2;", "=z,z,z"( i32 %A, i32 %B ) nounwind
+ ret i32 %R
+}
+
+; Target "C" for CC. This is a single register
+; CHECK: cc = p0 < p1;
+; CHECK: r0 = cc;
+define i32 @add_C(i32 %A, i32 %B) {
+ %R = call i32 asm "$0 = $1 < $2;", "=C,z,z"( i32 %A, i32 %B ) nounwind
+ ret i32 %R
+}
+
diff --git a/test/CodeGen/Blackfin/int-setcc.ll b/test/CodeGen/Blackfin/int-setcc.ll
new file mode 100644
index 0000000..6bd9f86
--- /dev/null
+++ b/test/CodeGen/Blackfin/int-setcc.ll
@@ -0,0 +1,80 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs > %t
+
+define fastcc void @Evaluate() {
+entry:
+ br i1 false, label %cond_false186, label %cond_true
+
+cond_true: ; preds = %entry
+ ret void
+
+cond_false186: ; preds = %entry
+ br i1 false, label %cond_true293, label %bb203
+
+bb203: ; preds = %cond_false186
+ ret void
+
+cond_true293: ; preds = %cond_false186
+ br i1 false, label %cond_true298, label %cond_next317
+
+cond_true298: ; preds = %cond_true293
+ br i1 false, label %cond_next518, label %cond_true397.preheader
+
+cond_next317: ; preds = %cond_true293
+ ret void
+
+cond_true397.preheader: ; preds = %cond_true298
+ ret void
+
+cond_next518: ; preds = %cond_true298
+ br i1 false, label %bb1069, label %cond_true522
+
+cond_true522: ; preds = %cond_next518
+ ret void
+
+bb1069: ; preds = %cond_next518
+ br i1 false, label %cond_next1131, label %bb1096
+
+bb1096: ; preds = %bb1069
+ ret void
+
+cond_next1131: ; preds = %bb1069
+ br i1 false, label %cond_next1207, label %cond_true1150
+
+cond_true1150: ; preds = %cond_next1131
+ ret void
+
+cond_next1207: ; preds = %cond_next1131
+ br i1 false, label %cond_next1219, label %cond_true1211
+
+cond_true1211: ; preds = %cond_next1207
+ ret void
+
+cond_next1219: ; preds = %cond_next1207
+ br i1 false, label %cond_true1223, label %cond_next1283
+
+cond_true1223: ; preds = %cond_next1219
+ br i1 false, label %cond_true1254, label %cond_true1264
+
+cond_true1254: ; preds = %cond_true1223
+ br i1 false, label %bb1567, label %cond_true1369.preheader
+
+cond_true1264: ; preds = %cond_true1223
+ ret void
+
+cond_next1283: ; preds = %cond_next1219
+ ret void
+
+cond_true1369.preheader: ; preds = %cond_true1254
+ ret void
+
+bb1567: ; preds = %cond_true1254
+ %tmp1605 = load i8* null ; <i8> [#uses=1]
+ %tmp1606 = icmp eq i8 %tmp1605, 0 ; <i1> [#uses=1]
+ br i1 %tmp1606, label %cond_next1637, label %cond_true1607
+
+cond_true1607: ; preds = %bb1567
+ ret void
+
+cond_next1637: ; preds = %bb1567
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/invalid-apint.ll b/test/CodeGen/Blackfin/invalid-apint.ll
new file mode 100644
index 0000000..a8c01ba
--- /dev/null
+++ b/test/CodeGen/Blackfin/invalid-apint.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=bfin
+
+; Assertion failed: (width < BitWidth && "Invalid APInt Truncate request"),
+; function trunc, file APInt.cpp, line 956.
+
+@str2 = external global [29 x i8]
+
+define void @printArgsNoRet(i32 %a1, float %a2, i8 %a3, double %a4, i8* %a5, i32 %a6, float %a7, i8 %a8, double %a9, i8* %a10, i32 %a11, float %a12, i8 %a13, double %a14, i8* %a15) {
+entry:
+ %tmp17 = sext i8 %a13 to i32
+ %tmp23 = call i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @str2, i32 0, i64 0), i32 %a11, double 0.000000e+00, i32 %tmp17, double %a14, i32 0)
+ ret void
+}
+
+declare i32 @printf(i8*, ...)
diff --git a/test/CodeGen/Blackfin/jumptable.ll b/test/CodeGen/Blackfin/jumptable.ll
new file mode 100644
index 0000000..5f49e9d
--- /dev/null
+++ b/test/CodeGen/Blackfin/jumptable.ll
@@ -0,0 +1,53 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs | FileCheck %s
+
+; CHECK: .section .rodata
+; CHECK: JTI1_0:
+; CHECK: .long .BB1_1
+
+define i32 @oper(i32 %op, i32 %A, i32 %B) {
+entry:
+ switch i32 %op, label %bbx [
+ i32 1 , label %bb1
+ i32 2 , label %bb2
+ i32 3 , label %bb3
+ i32 4 , label %bb4
+ i32 5 , label %bb5
+ i32 6 , label %bb6
+ i32 7 , label %bb7
+ i32 8 , label %bb8
+ i32 9 , label %bb9
+ i32 10, label %bb10
+ ]
+bb1:
+ %R1 = add i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R1
+bb2:
+ %R2 = sub i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R2
+bb3:
+ %R3 = mul i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R3
+bb4:
+ %R4 = sdiv i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R4
+bb5:
+ %R5 = udiv i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R5
+bb6:
+ %R6 = srem i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R6
+bb7:
+ %R7 = urem i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R7
+bb8:
+ %R8 = and i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R8
+bb9:
+ %R9 = or i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R9
+bb10:
+ %R10 = xor i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R10
+bbx:
+ ret i32 0
+}
diff --git a/test/CodeGen/Blackfin/large-switch.ll b/test/CodeGen/Blackfin/large-switch.ll
new file mode 100644
index 0000000..02d32ef
--- /dev/null
+++ b/test/CodeGen/Blackfin/large-switch.ll
@@ -0,0 +1,187 @@
+; RUN: llc < %s -march=bfin
+
+; The switch expansion uses a dynamic shl, and it produces a jumptable
+
+define void @athlon_fp_unit_ready_cost() {
+entry:
+ switch i32 0, label %UnifiedReturnBlock [
+ i32 -1, label %bb2063
+ i32 19, label %bb2035
+ i32 20, label %bb2035
+ i32 21, label %bb2035
+ i32 23, label %bb2035
+ i32 24, label %bb2035
+ i32 27, label %bb2035
+ i32 32, label %bb2035
+ i32 33, label %bb1994
+ i32 35, label %bb2035
+ i32 36, label %bb1994
+ i32 90, label %bb1948
+ i32 94, label %bb1948
+ i32 95, label %bb1948
+ i32 133, label %bb1419
+ i32 135, label %bb1238
+ i32 136, label %bb1238
+ i32 137, label %bb1238
+ i32 138, label %bb1238
+ i32 139, label %bb1201
+ i32 140, label %bb1201
+ i32 141, label %bb1154
+ i32 142, label %bb1126
+ i32 144, label %bb1201
+ i32 145, label %bb1126
+ i32 146, label %bb1201
+ i32 147, label %bb1126
+ i32 148, label %bb1201
+ i32 149, label %bb1126
+ i32 150, label %bb1201
+ i32 151, label %bb1126
+ i32 152, label %bb1096
+ i32 153, label %bb1096
+ i32 154, label %bb1096
+ i32 157, label %bb1096
+ i32 158, label %bb1096
+ i32 159, label %bb1096
+ i32 162, label %bb1096
+ i32 163, label %bb1096
+ i32 164, label %bb1096
+ i32 167, label %bb1201
+ i32 168, label %bb1201
+ i32 170, label %bb1201
+ i32 171, label %bb1201
+ i32 173, label %bb1201
+ i32 174, label %bb1201
+ i32 176, label %bb1201
+ i32 177, label %bb1201
+ i32 179, label %bb993
+ i32 180, label %bb993
+ i32 181, label %bb993
+ i32 182, label %bb993
+ i32 183, label %bb993
+ i32 184, label %bb993
+ i32 365, label %bb1126
+ i32 366, label %bb1126
+ i32 367, label %bb1126
+ i32 368, label %bb1126
+ i32 369, label %bb1126
+ i32 370, label %bb1126
+ i32 371, label %bb1126
+ i32 372, label %bb1126
+ i32 373, label %bb1126
+ i32 384, label %bb1126
+ i32 385, label %bb1126
+ i32 386, label %bb1126
+ i32 387, label %bb1126
+ i32 388, label %bb1126
+ i32 389, label %bb1126
+ i32 390, label %bb1126
+ i32 391, label %bb1126
+ i32 392, label %bb1126
+ i32 525, label %bb919
+ i32 526, label %bb839
+ i32 528, label %bb919
+ i32 529, label %bb839
+ i32 532, label %cond_next6.i97
+ i32 533, label %cond_next6.i81
+ i32 534, label %bb495
+ i32 536, label %cond_next6.i81
+ i32 537, label %cond_next6.i81
+ i32 538, label %bb396
+ i32 539, label %bb288
+ i32 541, label %bb396
+ i32 542, label %bb396
+ i32 543, label %bb396
+ i32 544, label %bb396
+ i32 545, label %bb189
+ i32 546, label %cond_next6.i
+ i32 547, label %bb189
+ i32 548, label %cond_next6.i
+ i32 549, label %bb189
+ i32 550, label %cond_next6.i
+ i32 551, label %bb189
+ i32 552, label %cond_next6.i
+ i32 553, label %bb189
+ i32 554, label %cond_next6.i
+ i32 555, label %bb189
+ i32 556, label %cond_next6.i
+ i32 557, label %bb189
+ i32 558, label %cond_next6.i
+ i32 618, label %bb40
+ i32 619, label %bb18
+ i32 620, label %bb40
+ i32 621, label %bb10
+ i32 622, label %bb10
+ ]
+
+bb10:
+ ret void
+
+bb18:
+ ret void
+
+bb40:
+ ret void
+
+cond_next6.i:
+ ret void
+
+bb189:
+ ret void
+
+bb288:
+ ret void
+
+bb396:
+ ret void
+
+bb495:
+ ret void
+
+cond_next6.i81:
+ ret void
+
+cond_next6.i97:
+ ret void
+
+bb839:
+ ret void
+
+bb919:
+ ret void
+
+bb993:
+ ret void
+
+bb1096:
+ ret void
+
+bb1126:
+ ret void
+
+bb1154:
+ ret void
+
+bb1201:
+ ret void
+
+bb1238:
+ ret void
+
+bb1419:
+ ret void
+
+bb1948:
+ ret void
+
+bb1994:
+ ret void
+
+bb2035:
+ ret void
+
+bb2063:
+ ret void
+
+UnifiedReturnBlock:
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/load-i16.ll b/test/CodeGen/Blackfin/load-i16.ll
new file mode 100644
index 0000000..eb18d41
--- /dev/null
+++ b/test/CodeGen/Blackfin/load-i16.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+
+; This somewhat contrived function heavily exercises register classes
+; It can trick -join-cross-class-copies into making illegal joins
+
+define void @f(i16** nocapture %p) nounwind readonly {
+entry:
+ %tmp1 = load i16** %p ; <i16*> [#uses=1]
+ %tmp2 = load i16* %tmp1 ; <i16> [#uses=1]
+ %ptr = getelementptr i16* %tmp1, i16 %tmp2
+ store i16 %tmp2, i16* %ptr
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/logic-i16.ll b/test/CodeGen/Blackfin/logic-i16.ll
new file mode 100644
index 0000000..e44672f
--- /dev/null
+++ b/test/CodeGen/Blackfin/logic-i16.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=bfin
+
+define i16 @and(i16 %A, i16 %B) {
+ %R = and i16 %A, %B ; <i16> [#uses=1]
+ ret i16 %R
+}
+
+define i16 @or(i16 %A, i16 %B) {
+ %R = or i16 %A, %B ; <i16> [#uses=1]
+ ret i16 %R
+}
+
+define i16 @xor(i16 %A, i16 %B) {
+ %R = xor i16 %A, %B ; <i16> [#uses=1]
+ ret i16 %R
+}
diff --git a/test/CodeGen/Blackfin/many-args.ll b/test/CodeGen/Blackfin/many-args.ll
new file mode 100644
index 0000000..8c52874
--- /dev/null
+++ b/test/CodeGen/Blackfin/many-args.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+
+ type { i32, float, float, float, float, float, float, float, float, float, float } ; type %0
+ %struct..s_segment_inf = type { float, i32, i16, i16, float, float, i32, float, float }
+
+define i32 @main(i32 %argc.1, i8** %argv.1) {
+entry:
+ %tmp.218 = load float* null ; <float> [#uses=1]
+ %tmp.219 = getelementptr %0* null, i64 0, i32 6 ; <float*> [#uses=1]
+ %tmp.220 = load float* %tmp.219 ; <float> [#uses=1]
+ %tmp.221 = getelementptr %0* null, i64 0, i32 7 ; <float*> [#uses=1]
+ %tmp.222 = load float* %tmp.221 ; <float> [#uses=1]
+ %tmp.223 = getelementptr %0* null, i64 0, i32 8 ; <float*> [#uses=1]
+ %tmp.224 = load float* %tmp.223 ; <float> [#uses=1]
+ %tmp.225 = getelementptr %0* null, i64 0, i32 9 ; <float*> [#uses=1]
+ %tmp.226 = load float* %tmp.225 ; <float> [#uses=1]
+ %tmp.227 = getelementptr %0* null, i64 0, i32 10 ; <float*> [#uses=1]
+ %tmp.228 = load float* %tmp.227 ; <float> [#uses=1]
+ call void @place_and_route(i32 0, i32 0, float 0.000000e+00, i32 0, i32 0, i8* null, i32 0, i32 0, i8* null, i8* null, i8* null, i8* null, i32 0, i32 0, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, i32 0, i32 0, i32 0, i32 0, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, i32 0, i32 0, i16 0, i16 0, i16 0, float 0.000000e+00, float 0.000000e+00, %struct..s_segment_inf* null, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float %tmp.218, float %tmp.220, float %tmp.222, float %tmp.224, float %tmp.226, float %tmp.228)
+ ret i32 0
+}
+
+declare void @place_and_route(i32, i32, float, i32, i32, i8*, i32, i32, i8*, i8*, i8*, i8*, i32, i32, i32, float, float, float, float, float, float, float, float, float, i32, i32, i32, i32, i32, float, float, float, i32, i32, i16, i16, i16, float, float, %struct..s_segment_inf*, i32, float, float, float, float, float, float, float, float, float, float)
diff --git a/test/CodeGen/Blackfin/mulhu.ll b/test/CodeGen/Blackfin/mulhu.ll
new file mode 100644
index 0000000..72bacee
--- /dev/null
+++ b/test/CodeGen/Blackfin/mulhu.ll
@@ -0,0 +1,106 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs > %t
+
+ %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.VEC_edge = type { i32, i32, [1 x %struct.edge_def*] }
+ %struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
+ %struct.basic_block_def = type { %struct.rtx_def*, %struct.rtx_def*, %struct.tree_node*, %struct.VEC_edge*, %struct.VEC_edge*, %struct.bitmap_head_def*, %struct.bitmap_head_def*, i8*, %struct.loop*, [2 x %struct.et_node*], %struct.basic_block_def*, %struct.basic_block_def*, %struct.reorder_block_def*, %struct.bb_ann_d*, i64, i32, i32, i32, i32 }
+ %struct.bb_ann_d = type { %struct.tree_node*, i8, %struct.edge_prediction* }
+ %struct.bitmap_element_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, [4 x i32] }
+ %struct.bitmap_head_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, %struct.bitmap_obstack* }
+ %struct.bitmap_obstack = type { %struct.bitmap_element_def*, %struct.bitmap_head_def*, %struct.obstack }
+ %struct.cost_pair = type { %struct.iv_cand*, i32, %struct.bitmap_head_def* }
+ %struct.dataflow_d = type { %struct.varray_head_tag*, [2 x %struct.tree_node*] }
+ %struct.def_operand_ptr = type { %struct.tree_node** }
+ %struct.def_optype_d = type { i32, [1 x %struct.def_operand_ptr] }
+ %struct.edge_def = type { %struct.basic_block_def*, %struct.basic_block_def*, %struct.edge_def_insns, i8*, %struct.location_t*, i32, i32, i64, i32 }
+ %struct.edge_def_insns = type { %struct.rtx_def* }
+ %struct.edge_prediction = type { %struct.edge_prediction*, %struct.edge_def*, i32, i32 }
+ %struct.eh_status = type opaque
+ %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }
+ %struct.et_node = type opaque
+ %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+ %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i1, i1, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 }
+ %struct.htab = type { i32 (i8*)*, i32 (i8*, i8*)*, void (i8*)*, i8**, i32, i32, i32, i32, i32, i8* (i32, i32)*, void (i8*)*, i8*, i8* (i8*, i32, i32)*, void (i8*, i8*)*, i32 }
+ %struct.initial_value_struct = type opaque
+ %struct.iv = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i1, i1, i32 }
+ %struct.iv_cand = type { i32, i1, i32, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.iv*, i32 }
+ %struct.iv_use = type { i32, i32, %struct.iv*, %struct.tree_node*, %struct.tree_node**, %struct.bitmap_head_def*, i32, %struct.cost_pair*, %struct.iv_cand* }
+ %struct.ivopts_data = type { %struct.loop*, %struct.htab*, i32, %struct.version_info*, %struct.bitmap_head_def*, i32, %struct.varray_head_tag*, %struct.varray_head_tag*, %struct.bitmap_head_def*, i1 }
+ %struct.lang_decl = type opaque
+ %struct.language_function = type opaque
+ %struct.location_t = type { i8*, i32 }
+ %struct.loop = type { i32, %struct.basic_block_def*, %struct.basic_block_def*, %struct.basic_block_def*, %struct.lpt_decision, i32, i32, %struct.edge_def**, i32, %struct.basic_block_def*, %struct.basic_block_def*, i32, %struct.edge_def**, i32, %struct.edge_def**, i32, %struct.simple_bitmap_def*, i32, %struct.loop**, i32, %struct.loop*, %struct.loop*, %struct.loop*, %struct.loop*, i32, i8*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i32, %struct.tree_node*, %struct.tree_node*, %struct.nb_iter_bound*, %struct.edge_def*, i1 }
+ %struct.lpt_decision = type { i32, i32 }
+ %struct.machine_function = type { %struct.stack_local_entry*, i8*, %struct.rtx_def*, i32, i32, i32, i32, i32 }
+ %struct.nb_iter_bound = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.nb_iter_bound* }
+ %struct.obstack = type { i32, %struct._obstack_chunk*, i8*, i8*, i8*, i32, i32, %struct._obstack_chunk* (i8*, i32)*, void (i8*, %struct._obstack_chunk*)*, i8*, i8 }
+ %struct.reorder_block_def = type { %struct.rtx_def*, %struct.rtx_def*, %struct.basic_block_def*, %struct.basic_block_def*, %struct.basic_block_def*, i32, i32, i32 }
+ %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }
+ %struct.rtx_def = type { i16, i8, i8, %struct.u }
+ %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
+ %struct.simple_bitmap_def = type { i32, i32, i32, [1 x i64] }
+ %struct.stack_local_entry = type opaque
+ %struct.stmt_ann_d = type { %struct.tree_ann_common_d, i8, %struct.basic_block_def*, %struct.stmt_operands_d, %struct.dataflow_d*, %struct.bitmap_head_def*, i32 }
+ %struct.stmt_operands_d = type { %struct.def_optype_d*, %struct.def_optype_d*, %struct.v_may_def_optype_d*, %struct.vuse_optype_d*, %struct.v_may_def_optype_d* }
+ %struct.temp_slot = type opaque
+ %struct.tree_ann_common_d = type { i32, i8*, %struct.tree_node* }
+ %struct.tree_ann_d = type { %struct.stmt_ann_d }
+ %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_ann_d*, i8, i8, i8, i8, i8 }
+ %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_decl_u1 = type { i64 }
+ %struct.tree_decl_u2 = type { %struct.function* }
+ %struct.tree_node = type { %struct.tree_decl }
+ %struct.u = type { [1 x i64] }
+ %struct.v_def_use_operand_type_t = type { %struct.tree_node*, %struct.tree_node* }
+ %struct.v_may_def_optype_d = type { i32, [1 x %struct.v_def_use_operand_type_t] }
+ %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+ %struct.varasm_status = type opaque
+ %struct.varray_head_tag = type { i32, i32, i32, i8*, %struct.u }
+ %struct.version_info = type { %struct.tree_node*, %struct.iv*, i1, i32, i1 }
+ %struct.vuse_optype_d = type { i32, [1 x %struct.tree_node*] }
+
+define i1 @determine_use_iv_cost(%struct.ivopts_data* %data, %struct.iv_use* %use, %struct.iv_cand* %cand) {
+entry:
+ switch i32 0, label %bb91 [
+ i32 0, label %bb
+ i32 1, label %bb6
+ i32 3, label %cond_next135
+ ]
+
+bb: ; preds = %entry
+ ret i1 false
+
+bb6: ; preds = %entry
+ br i1 false, label %bb87, label %cond_next27
+
+cond_next27: ; preds = %bb6
+ br i1 false, label %cond_true30, label %cond_next55
+
+cond_true30: ; preds = %cond_next27
+ br i1 false, label %cond_next41, label %cond_true35
+
+cond_true35: ; preds = %cond_true30
+ ret i1 false
+
+cond_next41: ; preds = %cond_true30
+ %tmp44 = call i32 @force_var_cost(%struct.ivopts_data* %data, %struct.tree_node* null, %struct.bitmap_head_def** null) ; <i32> [#uses=1]
+ %tmp46 = udiv i32 %tmp44, 5 ; <i32> [#uses=1]
+ call void @set_use_iv_cost(%struct.ivopts_data* %data, %struct.iv_use* %use, %struct.iv_cand* %cand, i32 %tmp46, %struct.bitmap_head_def* null)
+ br label %bb87
+
+cond_next55: ; preds = %cond_next27
+ ret i1 false
+
+bb87: ; preds = %cond_next41, %bb6
+ ret i1 false
+
+bb91: ; preds = %entry
+ ret i1 false
+
+cond_next135: ; preds = %entry
+ ret i1 false
+}
+
+declare void @set_use_iv_cost(%struct.ivopts_data*, %struct.iv_use*, %struct.iv_cand*, i32, %struct.bitmap_head_def*)
+
+declare i32 @force_var_cost(%struct.ivopts_data*, %struct.tree_node*, %struct.bitmap_head_def**)
diff --git a/test/CodeGen/Blackfin/printf.ll b/test/CodeGen/Blackfin/printf.ll
new file mode 100644
index 0000000..9e54b73
--- /dev/null
+++ b/test/CodeGen/Blackfin/printf.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
[email protected]_1 = external constant [42 x i8] ; <[42 x i8]*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main(i32 %argc.1, i8** %argv.1) {
+entry:
+ %tmp.16 = call i32 (i8*, ...)* @printf(i8* getelementptr ([42 x i8]* @.str_1, i64 0, i64 0), i32 0, i32 0, i64 0, i64 0)
+ ret i32 0
+}
diff --git a/test/CodeGen/Blackfin/printf2.ll b/test/CodeGen/Blackfin/printf2.ll
new file mode 100644
index 0000000..7ac7e80
--- /dev/null
+++ b/test/CodeGen/Blackfin/printf2.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=bfin
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+ %1 = call i32 (i8*, ...)* @printf(i8* undef, i1 undef)
+ ret i32 0
+}
diff --git a/test/CodeGen/Blackfin/promote-logic.ll b/test/CodeGen/Blackfin/promote-logic.ll
new file mode 100644
index 0000000..46da566
--- /dev/null
+++ b/test/CodeGen/Blackfin/promote-logic.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -march=bfin > %t
+; XFAIL: *
+
+; DAGCombiner::SimplifyBinOpWithSameOpcodeHands can produce an illegal i16 OR
+; operation after LegalizeOps.
+
+define void @mng_display_bgr565() {
+entry:
+ br i1 false, label %bb.preheader, label %return
+
+bb.preheader:
+ br i1 false, label %cond_true48, label %cond_next80
+
+cond_true48:
+ %tmp = load i8* null
+ %tmp51 = zext i8 %tmp to i16
+ %tmp99 = load i8* null
+ %tmp54 = bitcast i8 %tmp99 to i8
+ %tmp54.upgrd.1 = zext i8 %tmp54 to i32
+ %tmp55 = lshr i32 %tmp54.upgrd.1, 3
+ %tmp55.upgrd.2 = trunc i32 %tmp55 to i16
+ %tmp52 = shl i16 %tmp51, 5
+ %tmp56 = and i16 %tmp55.upgrd.2, 28
+ %tmp57 = or i16 %tmp56, %tmp52
+ %tmp60 = zext i16 %tmp57 to i32
+ %tmp62 = xor i32 0, 65535
+ %tmp63 = mul i32 %tmp60, %tmp62
+ %tmp65 = add i32 0, %tmp63
+ %tmp69 = add i32 0, %tmp65
+ %tmp70 = lshr i32 %tmp69, 16
+ %tmp70.upgrd.3 = trunc i32 %tmp70 to i16
+ %tmp75 = lshr i16 %tmp70.upgrd.3, 8
+ %tmp75.upgrd.4 = trunc i16 %tmp75 to i8
+ %tmp76 = lshr i8 %tmp75.upgrd.4, 5
+ store i8 %tmp76, i8* null
+ ret void
+
+cond_next80:
+ ret void
+
+return:
+ ret void
+}
diff --git a/test/CodeGen/Blackfin/promote-setcc.ll b/test/CodeGen/Blackfin/promote-setcc.ll
new file mode 100644
index 0000000..d344fad
--- /dev/null
+++ b/test/CodeGen/Blackfin/promote-setcc.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=bfin > %t
+
+; The DAG combiner may sometimes create illegal i16 SETCC operations when run
+; after LegalizeOps. Try to tease out all the optimizations in
+; TargetLowering::SimplifySetCC.
+
+@x = external global i16
+@y = external global i16
+
+declare i16 @llvm.ctlz.i16(i16)
+
+; Case (srl (ctlz x), 5) == const
+; Note: ctlz is promoted, so this test does not catch the DAG combiner
+define i1 @srl_ctlz_const() {
+ %x = load i16* @x
+ %c = call i16 @llvm.ctlz.i16(i16 %x)
+ %s = lshr i16 %c, 4
+ %r = icmp eq i16 %s, 1
+ ret i1 %r
+}
+
+; Case (zext x) == const
+define i1 @zext_const() {
+ %x = load i16* @x
+ %r = icmp ugt i16 %x, 1
+ ret i1 %r
+}
+
+; Case (sext x) == const
+define i1 @sext_const() {
+ %x = load i16* @x
+ %y = add i16 %x, 1
+ %x2 = sext i16 %y to i32
+ %r = icmp ne i32 %x2, -1
+ ret i1 %r
+}
+
diff --git a/test/CodeGen/Blackfin/sdiv.ll b/test/CodeGen/Blackfin/sdiv.ll
new file mode 100644
index 0000000..1426655
--- /dev/null
+++ b/test/CodeGen/Blackfin/sdiv.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs
+define i32 @sdiv(i32 %A, i32 %B) {
+ %R = sdiv i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
diff --git a/test/CodeGen/Blackfin/simple-select.ll b/test/CodeGen/Blackfin/simple-select.ll
new file mode 100644
index 0000000..0f7f270
--- /dev/null
+++ b/test/CodeGen/Blackfin/simple-select.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs > %t
+
+declare i1 @foo()
+
+define i32 @test(i32* %A, i32* %B) {
+ %a = load i32* %A
+ %b = load i32* %B
+ %cond = call i1 @foo()
+ %c = select i1 %cond, i32 %a, i32 %b
+ ret i32 %c
+}
diff --git a/test/CodeGen/Blackfin/switch.ll b/test/CodeGen/Blackfin/switch.ll
new file mode 100644
index 0000000..3680ec6
--- /dev/null
+++ b/test/CodeGen/Blackfin/switch.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs > %t
+
+define i32 @foo(i32 %A, i32 %B, i32 %C) {
+entry:
+ switch i32 %A, label %out [
+ i32 1, label %bb
+ i32 0, label %bb13
+ ]
+
+bb: ; preds = %entry
+ ret i32 1
+
+bb13: ; preds = %entry
+ ret i32 1
+
+out: ; preds = %entry
+ ret i32 0
+}
diff --git a/test/CodeGen/Blackfin/switch2.ll b/test/CodeGen/Blackfin/switch2.ll
new file mode 100644
index 0000000..7877bce
--- /dev/null
+++ b/test/CodeGen/Blackfin/switch2.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs > %t
+
+define i8* @FindChar(i8* %CurPtr) {
+entry:
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %tmp = load i8* null ; <i8> [#uses=1]
+ switch i8 %tmp, label %bb [
+ i8 0, label %bb7
+ i8 120, label %bb7
+ ]
+
+bb7: ; preds = %bb, %bb
+ ret i8* null
+}
diff --git a/test/CodeGen/Blackfin/sync-intr.ll b/test/CodeGen/Blackfin/sync-intr.ll
new file mode 100644
index 0000000..0b103a3
--- /dev/null
+++ b/test/CodeGen/Blackfin/sync-intr.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=bfin -verify-machineinstrs | FileCheck %s
+
+define void @f() nounwind {
+entry:
+ ; CHECK-NOT: llvm.bfin
+ ; CHECK: csync;
+ call void @llvm.bfin.csync()
+
+ ; CHECK-NOT: llvm.bfin
+ ; CHECK: ssync;
+ call void @llvm.bfin.ssync()
+ ret void
+}
+
+declare void @llvm.bfin.csync() nounwind
+declare void @llvm.bfin.ssync() nounwind
diff --git a/test/CodeGen/CBackend/2002-05-16-NameCollide.ll b/test/CodeGen/CBackend/2002-05-16-NameCollide.ll
new file mode 100644
index 0000000..0b06041
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-05-16-NameCollide.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=c
+
+; Make sure that global variables do not collide if they have the same name,
+; but different types.
+
+@X = global i32 5 ; <i32*> [#uses=0]
[email protected] = global i64 7 ; <i64*> [#uses=0]
+
diff --git a/test/CodeGen/CBackend/2002-05-21-MissingReturn.ll b/test/CodeGen/CBackend/2002-05-21-MissingReturn.ll
new file mode 100644
index 0000000..a9f54e4
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-05-21-MissingReturn.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=c
+
+; This case was emitting code that looked like this:
+; ...
+; llvm_BB1: /* no statement here */
+; }
+;
+; Which the Sun C compiler rejected, so now we are sure to put a return
+; instruction in there if the basic block is otherwise empty.
+;
+define void @test() {
+ br label %BB1
+
+BB2: ; preds = %BB2
+ br label %BB2
+
+BB1: ; preds = %0
+ ret void
+}
+
diff --git a/test/CodeGen/CBackend/2002-08-19-ConstPointerRef.ll b/test/CodeGen/CBackend/2002-08-19-ConstPointerRef.ll
new file mode 100644
index 0000000..2afb1a0
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-08-19-ConstPointerRef.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=c
+
+; Test const pointer refs & forward references
+
+@t3 = global i32* @t1 ; <i32**> [#uses=0]
+@t1 = global i32 4 ; <i32*> [#uses=1]
+
diff --git a/test/CodeGen/CBackend/2002-08-19-ConstantExpr.ll b/test/CodeGen/CBackend/2002-08-19-ConstantExpr.ll
new file mode 100644
index 0000000..b71cf07
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-08-19-ConstantExpr.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=c
+
+global i32* bitcast (float* @2 to i32*) ;; Forward numeric reference
+global float* @2 ;; Duplicate forward numeric reference
+global float 0.0
+
+@array = constant [2 x i32] [ i32 12, i32 52 ]
+@arrayPtr = global i32* getelementptr ([2 x i32]* @array, i64 0, i64 0)
diff --git a/test/CodeGen/CBackend/2002-08-19-DataPointer.ll b/test/CodeGen/CBackend/2002-08-19-DataPointer.ll
new file mode 100644
index 0000000..b5a1f0b
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-08-19-DataPointer.ll
@@ -0,0 +1,4 @@
+; RUN: llc < %s -march=c
+
+@sptr1 = global [11 x i8]* @somestr ;; Forward ref to a constant
+@somestr = constant [11 x i8] c"hello world"
diff --git a/test/CodeGen/CBackend/2002-08-19-FunctionPointer.ll b/test/CodeGen/CBackend/2002-08-19-FunctionPointer.ll
new file mode 100644
index 0000000..10b9fe2
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-08-19-FunctionPointer.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=c
+
+@fptr = global void ()* @f ;; Forward ref method defn
+declare void @f() ;; External method
+
diff --git a/test/CodeGen/CBackend/2002-08-19-HardConstantExpr.ll b/test/CodeGen/CBackend/2002-08-19-HardConstantExpr.ll
new file mode 100644
index 0000000..0827423
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-08-19-HardConstantExpr.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=c
+
+@array = constant [2 x i32] [ i32 12, i32 52 ] ; <[2 x i32]*> [#uses=1]
+@arrayPtr = global i32* getelementptr ([2 x i32]* @array, i64 0, i64 0) ; <i32**> [#uses=0]
+
diff --git a/test/CodeGen/CBackend/2002-08-20-RecursiveTypes.ll b/test/CodeGen/CBackend/2002-08-20-RecursiveTypes.ll
new file mode 100644
index 0000000..3b2085c
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-08-20-RecursiveTypes.ll
@@ -0,0 +1,3 @@
+; RUN: llc < %s -march=c
+
+@MyIntList = external global { \2*, i32 }
diff --git a/test/CodeGen/CBackend/2002-08-20-UnnamedArgument.ll b/test/CodeGen/CBackend/2002-08-20-UnnamedArgument.ll
new file mode 100644
index 0000000..59aafd5
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-08-20-UnnamedArgument.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=c
+
+; The C Writer bombs on this testcase because it tries the print the prototype
+; for the test function, which tries to print the argument name. The function
+; has not been incorporated into the slot calculator, so after it does the name
+; lookup, it tries a slot calculator lookup, which fails.
+
+define i32 @test(i32) {
+ ret i32 0
+}
diff --git a/test/CodeGen/CBackend/2002-08-26-IndirectCallTest.ll b/test/CodeGen/CBackend/2002-08-26-IndirectCallTest.ll
new file mode 100644
index 0000000..6c4d629
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-08-26-IndirectCallTest.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=c
+
+; Indirect function call test... found by Joel & Brian
+;
+
+@taskArray = external global i32* ; <i32**> [#uses=1]
+
+define void @test(i32 %X) {
+ %Y = add i32 %X, -1 ; <i32> [#uses=1]
+ %cast100 = sext i32 %Y to i64 ; <i64> [#uses=1]
+ %gep100 = getelementptr i32** @taskArray, i64 %cast100 ; <i32**> [#uses=1]
+ %fooPtr = load i32** %gep100 ; <i32*> [#uses=1]
+ %cast101 = bitcast i32* %fooPtr to void (i32)* ; <void (i32)*> [#uses=1]
+ call void %cast101( i32 1000 )
+ ret void
+}
+
diff --git a/test/CodeGen/CBackend/2002-08-30-StructureOrderingTest.ll b/test/CodeGen/CBackend/2002-08-30-StructureOrderingTest.ll
new file mode 100644
index 0000000..1187a37
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-08-30-StructureOrderingTest.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=c
+
+; This testcase fails because the C backend does not arrange to output the
+; contents of a structure type before it outputs the structure type itself.
+
+@Y = external global { { i32 } } ; <{ { i32 } }*> [#uses=0]
+@X = external global { float } ; <{ float }*> [#uses=0]
+
diff --git a/test/CodeGen/CBackend/2002-09-20-ArrayTypeFailure.ll b/test/CodeGen/CBackend/2002-09-20-ArrayTypeFailure.ll
new file mode 100644
index 0000000..021adb9
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-09-20-ArrayTypeFailure.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=c
+
+define void @test() {
+ %X = alloca [4 x i32] ; <[4 x i32]*> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/CBackend/2002-09-20-VarArgPrototypes.ll b/test/CodeGen/CBackend/2002-09-20-VarArgPrototypes.ll
new file mode 100644
index 0000000..e915cd2
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-09-20-VarArgPrototypes.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=c
+
+
+declare void @foo(...)
+
+
diff --git a/test/CodeGen/CBackend/2002-10-15-OpaqueTypeProblem.ll b/test/CodeGen/CBackend/2002-10-15-OpaqueTypeProblem.ll
new file mode 100644
index 0000000..2563d8c
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-10-15-OpaqueTypeProblem.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=c
+
+%MPI_Comm = type %struct.Comm*
+%struct.Comm = type opaque
+@thing = global %MPI_Comm* null ; <%MPI_Comm**> [#uses=0]
+
diff --git a/test/CodeGen/CBackend/2002-10-16-External.ll b/test/CodeGen/CBackend/2002-10-16-External.ll
new file mode 100644
index 0000000..2cdd15c
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-10-16-External.ll
@@ -0,0 +1,4 @@
+; RUN: llc < %s -march=c
+
+@bob = external global i32 ; <i32*> [#uses=0]
+
diff --git a/test/CodeGen/CBackend/2002-10-30-FunctionPointerAlloca.ll b/test/CodeGen/CBackend/2002-10-30-FunctionPointerAlloca.ll
new file mode 100644
index 0000000..54e0aa6
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-10-30-FunctionPointerAlloca.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=c
+
+ %BitField = type i32
+ %tokenptr = type i32*
+
+define void @test() {
+ %pmf1 = alloca %tokenptr (%tokenptr, i8*)* ; <%tokenptr (%tokenptr, i8*)**> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/CBackend/2002-11-06-PrintEscaped.ll b/test/CodeGen/CBackend/2002-11-06-PrintEscaped.ll
new file mode 100644
index 0000000..82d594f
--- /dev/null
+++ b/test/CodeGen/CBackend/2002-11-06-PrintEscaped.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=c
+
+@testString = internal constant [18 x i8] c"Escaped newline\5Cn\00" ; <[18 x i8]*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+ call i32 (i8*, ...)* @printf( i8* getelementptr ([18 x i8]* @testString, i64 0, i64 0) ) ; <i32>:1 [#uses=0]
+ ret i32 0
+}
+
diff --git a/test/CodeGen/CBackend/2003-05-12-IntegerSizeWarning.ll b/test/CodeGen/CBackend/2003-05-12-IntegerSizeWarning.ll
new file mode 100644
index 0000000..92d582d
--- /dev/null
+++ b/test/CodeGen/CBackend/2003-05-12-IntegerSizeWarning.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=c
+
+; Apparently this constant was unsigned in ISO C 90, but not in C 99.
+
+define i32 @foo() {
+ ret i32 -2147483648
+}
+
diff --git a/test/CodeGen/CBackend/2003-05-13-VarArgFunction.ll b/test/CodeGen/CBackend/2003-05-13-VarArgFunction.ll
new file mode 100644
index 0000000..a42dc27
--- /dev/null
+++ b/test/CodeGen/CBackend/2003-05-13-VarArgFunction.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=c
+
+; This testcase breaks the C backend, because gcc doesn't like (...) functions
+; with no arguments at all.
+
+define void @test(i64 %Ptr) {
+ %P = inttoptr i64 %Ptr to void (...)* ; <void (...)*> [#uses=1]
+ call void (...)* %P( i64 %Ptr )
+ ret void
+}
+
diff --git a/test/CodeGen/CBackend/2003-05-31-MissingStructName.ll b/test/CodeGen/CBackend/2003-05-31-MissingStructName.ll
new file mode 100644
index 0000000..19c7840
--- /dev/null
+++ b/test/CodeGen/CBackend/2003-05-31-MissingStructName.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=c
+
+; The C backend was dying when there was no typename for a struct type!
+
+declare i32 @test(i32, { [32 x i32] }*)
diff --git a/test/CodeGen/CBackend/2003-06-01-NullPointerType.ll b/test/CodeGen/CBackend/2003-06-01-NullPointerType.ll
new file mode 100644
index 0000000..048e045
--- /dev/null
+++ b/test/CodeGen/CBackend/2003-06-01-NullPointerType.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=c
+
+%X = type { i32, float }
+
+define void @test() {
+ getelementptr %X* null, i64 0, i32 1 ; <float*>:1 [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/CBackend/2003-06-11-HexConstant.ll b/test/CodeGen/CBackend/2003-06-11-HexConstant.ll
new file mode 100644
index 0000000..6197b30
--- /dev/null
+++ b/test/CodeGen/CBackend/2003-06-11-HexConstant.ll
@@ -0,0 +1,4 @@
+; RUN: llc < %s -march=c
+
+; Make sure hex constant does not continue into a valid hexadecimal letter/number
+@version = global [3 x i8] c"\001\00"
diff --git a/test/CodeGen/CBackend/2003-06-11-LiteralStringProblem.ll b/test/CodeGen/CBackend/2003-06-11-LiteralStringProblem.ll
new file mode 100644
index 0000000..f6177ea
--- /dev/null
+++ b/test/CodeGen/CBackend/2003-06-11-LiteralStringProblem.ll
@@ -0,0 +1,3 @@
+; RUN: llc < %s -march=c
+
+@version = global [3 x i8] c"1\00\00"
diff --git a/test/CodeGen/CBackend/2003-06-28-InvokeSupport.ll b/test/CodeGen/CBackend/2003-06-28-InvokeSupport.ll
new file mode 100644
index 0000000..f0b1bbc
--- /dev/null
+++ b/test/CodeGen/CBackend/2003-06-28-InvokeSupport.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=c
+
+declare i32 @callee(i32, i32)
+
+define i32 @test(i32 %X) {
+; <label>:0
+ %A = invoke i32 @callee( i32 %X, i32 5 )
+ to label %Ok unwind label %Threw ; <i32> [#uses=1]
+
+Ok: ; preds = %Threw, %0
+ %B = phi i32 [ %A, %0 ], [ -1, %Threw ] ; <i32> [#uses=1]
+ ret i32 %B
+
+Threw: ; preds = %0
+ br label %Ok
+}
+
diff --git a/test/CodeGen/CBackend/2003-06-28-LinkOnceGlobalVars.ll b/test/CodeGen/CBackend/2003-06-28-LinkOnceGlobalVars.ll
new file mode 100644
index 0000000..4bd1da2
--- /dev/null
+++ b/test/CodeGen/CBackend/2003-06-28-LinkOnceGlobalVars.ll
@@ -0,0 +1,3 @@
+; RUN: llc < %s -march=c | grep common | grep X
+
+@X = linkonce global i32 5
diff --git a/test/CodeGen/CBackend/2003-10-12-NANGlobalInits.ll b/test/CodeGen/CBackend/2003-10-12-NANGlobalInits.ll
new file mode 100644
index 0000000..0fbb3fe
--- /dev/null
+++ b/test/CodeGen/CBackend/2003-10-12-NANGlobalInits.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=c
+
+; This is a non-normal FP value: it's a nan.
+@NAN = global { float } { float 0x7FF8000000000000 } ; <{ float }*> [#uses=0]
+@NANs = global { float } { float 0x7FFC000000000000 } ; <{ float }*> [#uses=0]
diff --git a/test/CodeGen/CBackend/2003-10-23-UnusedType.ll b/test/CodeGen/CBackend/2003-10-23-UnusedType.ll
new file mode 100644
index 0000000..9195634
--- /dev/null
+++ b/test/CodeGen/CBackend/2003-10-23-UnusedType.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=c
+
+%A = type { i32, i8*, { i32, i32, i32, i32, i32, i32, i32, i32 }*, i16 }
+
+define void @test(%A*) {
+ ret void
+}
+
diff --git a/test/CodeGen/CBackend/2003-10-28-CastToPtrToStruct.ll b/test/CodeGen/CBackend/2003-10-28-CastToPtrToStruct.ll
new file mode 100644
index 0000000..b4389ff
--- /dev/null
+++ b/test/CodeGen/CBackend/2003-10-28-CastToPtrToStruct.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=c
+
+; reduced from DOOM.
+ %union._XEvent = type { i32 }
[email protected]_event_9 = global %union._XEvent zeroinitializer ; <%union._XEvent*> [#uses=1]
+
+define void @I_InitGraphics() {
+shortcirc_next.3:
+ %tmp.319 = load i32* getelementptr ({ i32, i32 }* bitcast (%union._XEvent* @.X_event_9 to { i32, i32 }*), i64 0, i32 1) ; <i32> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/CBackend/2003-11-21-ConstantShiftExpr.ll b/test/CodeGen/CBackend/2003-11-21-ConstantShiftExpr.ll
new file mode 100644
index 0000000..6a26291
--- /dev/null
+++ b/test/CodeGen/CBackend/2003-11-21-ConstantShiftExpr.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=c
+@y = weak global i8 0 ; <i8*> [#uses=1]
+
+define i32 @testcaseshr() {
+entry:
+ ret i32 lshr (i32 ptrtoint (i8* @y to i32), i32 4)
+}
+
+define i32 @testcaseshl() {
+entry:
+ ret i32 shl (i32 ptrtoint (i8* @y to i32), i32 4)
+}
+
diff --git a/test/CodeGen/CBackend/2004-02-13-FrameReturnAddress.ll b/test/CodeGen/CBackend/2004-02-13-FrameReturnAddress.ll
new file mode 100644
index 0000000..142fbd8
--- /dev/null
+++ b/test/CodeGen/CBackend/2004-02-13-FrameReturnAddress.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=c | grep builtin_return_address
+
+declare i8* @llvm.returnaddress(i32)
+
+declare i8* @llvm.frameaddress(i32)
+
+define i8* @test1() {
+ %X = call i8* @llvm.returnaddress( i32 0 ) ; <i8*> [#uses=1]
+ ret i8* %X
+}
+
+define i8* @test2() {
+ %X = call i8* @llvm.frameaddress( i32 0 ) ; <i8*> [#uses=1]
+ ret i8* %X
+}
+
diff --git a/test/CodeGen/CBackend/2004-02-15-PreexistingExternals.ll b/test/CodeGen/CBackend/2004-02-15-PreexistingExternals.ll
new file mode 100644
index 0000000..d1c6861
--- /dev/null
+++ b/test/CodeGen/CBackend/2004-02-15-PreexistingExternals.ll
@@ -0,0 +1,18 @@
+; The intrinsic lowering pass was lowering intrinsics like llvm.memcpy to
+; explicitly specified prototypes, inserting a new function if the old one
+; didn't exist. This caused there to be two external memcpy functions in
+; this testcase for example, which caused the CBE to mangle one, screwing
+; everything up. :( Test that this does not happen anymore.
+;
+; RUN: llc < %s -march=c | not grep _memcpy
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32)
+
+declare float* @memcpy(i32*, i32, i32)
+
+define i32 @test(i8* %A, i8* %B, i32* %C) {
+ call float* @memcpy( i32* %C, i32 4, i32 17 ) ; <float*>:1 [#uses=0]
+ call void @llvm.memcpy.i32( i8* %A, i8* %B, i32 123, i32 14 )
+ ret i32 7
+}
+
diff --git a/test/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.ll b/test/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.ll
new file mode 100644
index 0000000..6fceb08
--- /dev/null
+++ b/test/CodeGen/CBackend/2004-02-26-FPNotPrintableConstants.ll
@@ -0,0 +1,11 @@
+; This is a non-normal FP value
+; RUN: llc < %s -march=c | grep FPConstant | grep static
+
+define float @func() {
+ ret float 0xFFF0000000000000
+}
+
+define double @func2() {
+ ret double 0xFF20000000000000
+}
+
diff --git a/test/CodeGen/CBackend/2004-02-26-LinkOnceFunctions.ll b/test/CodeGen/CBackend/2004-02-26-LinkOnceFunctions.ll
new file mode 100644
index 0000000..cf59634
--- /dev/null
+++ b/test/CodeGen/CBackend/2004-02-26-LinkOnceFunctions.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=c | grep func1 | grep WEAK
+
+define linkonce i32 @func1() {
+ ret i32 5
+}
+
diff --git a/test/CodeGen/CBackend/2004-08-09-va-end-null.ll b/test/CodeGen/CBackend/2004-08-09-va-end-null.ll
new file mode 100644
index 0000000..3ee23d1
--- /dev/null
+++ b/test/CodeGen/CBackend/2004-08-09-va-end-null.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=c
+
+declare void @llvm.va_end(i8*)
+
+define void @test() {
+ %va.upgrd.1 = bitcast i8* null to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_end( i8* %va.upgrd.1 )
+ ret void
+}
+
diff --git a/test/CodeGen/CBackend/2004-11-13-FunctionPointerCast.ll b/test/CodeGen/CBackend/2004-11-13-FunctionPointerCast.ll
new file mode 100644
index 0000000..af8f441
--- /dev/null
+++ b/test/CodeGen/CBackend/2004-11-13-FunctionPointerCast.ll
@@ -0,0 +1,12 @@
+; The CBE should not emit code that casts the function pointer. This causes
+; GCC to get testy and insert trap instructions instead of doing the right
+; thing. :(
+; RUN: llc < %s -march=c
+
+declare void @external(i8*)
+
+define i32 @test(i32* %X) {
+ %RV = call i32 bitcast (void (i8*)* @external to i32 (i32*)*)( i32* %X ) ; <i32> [#uses=1]
+ ret i32 %RV
+}
+
diff --git a/test/CodeGen/CBackend/2004-12-03-ExternStatics.ll b/test/CodeGen/CBackend/2004-12-03-ExternStatics.ll
new file mode 100644
index 0000000..78e9bac
--- /dev/null
+++ b/test/CodeGen/CBackend/2004-12-03-ExternStatics.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=c | not grep extern.*msg
+; PR472
+
+@msg = internal global [6 x i8] c"hello\00" ; <[6 x i8]*> [#uses=1]
+
+define i8* @foo() {
+entry:
+ ret i8* getelementptr ([6 x i8]* @msg, i32 0, i32 0)
+}
+
diff --git a/test/CodeGen/CBackend/2004-12-28-LogicalConstantExprs.ll b/test/CodeGen/CBackend/2004-12-28-LogicalConstantExprs.ll
new file mode 100644
index 0000000..57a9adc
--- /dev/null
+++ b/test/CodeGen/CBackend/2004-12-28-LogicalConstantExprs.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=c
+
+define i32 @foo() {
+ ret i32 and (i32 123456, i32 ptrtoint (i32 ()* @foo to i32))
+}
diff --git a/test/CodeGen/CBackend/2005-02-14-VolatileOperations.ll b/test/CodeGen/CBackend/2005-02-14-VolatileOperations.ll
new file mode 100644
index 0000000..dd505af
--- /dev/null
+++ b/test/CodeGen/CBackend/2005-02-14-VolatileOperations.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=c | grep volatile
+
+define void @test(i32* %P) {
+ %X = volatile load i32* %P ; <i32> [#uses=1]
+ volatile store i32 %X, i32* %P
+ ret void
+}
+
diff --git a/test/CodeGen/CBackend/2005-03-08-RecursiveTypeCrash.ll b/test/CodeGen/CBackend/2005-03-08-RecursiveTypeCrash.ll
new file mode 100644
index 0000000..1c5f506
--- /dev/null
+++ b/test/CodeGen/CBackend/2005-03-08-RecursiveTypeCrash.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=c
+
+ %JNIEnv = type %struct.JNINa*
+ %struct.JNINa = type { i8*, i8*, i8*, void (%JNIEnv*)* }
+
diff --git a/test/CodeGen/CBackend/2005-07-14-NegationToMinusMinus.ll b/test/CodeGen/CBackend/2005-07-14-NegationToMinusMinus.ll
new file mode 100644
index 0000000..808b8f9
--- /dev/null
+++ b/test/CodeGen/CBackend/2005-07-14-NegationToMinusMinus.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=c | not grep -- --65535
+; PR596
+
+target datalayout = "e-p:32:32"
+target triple = "i686-pc-linux-gnu"
+
+declare void @func(i32)
+
+define void @funcb() {
+entry:
+ %tmp.1 = sub i32 0, -65535 ; <i32> [#uses=1]
+ call void @func( i32 %tmp.1 )
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
diff --git a/test/CodeGen/CBackend/2005-08-23-Fmod.ll b/test/CodeGen/CBackend/2005-08-23-Fmod.ll
new file mode 100644
index 0000000..6e650eb
--- /dev/null
+++ b/test/CodeGen/CBackend/2005-08-23-Fmod.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=c | grep fmod
+
+define double @test(double %A, double %B) {
+ %C = frem double %A, %B ; <double> [#uses=1]
+ ret double %C
+}
+
diff --git a/test/CodeGen/CBackend/2005-09-27-VolatileFuncPtr.ll b/test/CodeGen/CBackend/2005-09-27-VolatileFuncPtr.ll
new file mode 100644
index 0000000..99de837
--- /dev/null
+++ b/test/CodeGen/CBackend/2005-09-27-VolatileFuncPtr.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=c | grep {\\* *volatile *\\*}
+
+@G = external global void ()* ; <void ()**> [#uses=2]
+
+define void @test() {
+ volatile store void ()* @test, void ()** @G
+ volatile load void ()** @G ; <void ()*>:1 [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/CBackend/2006-12-11-Float-Bitcast.ll b/test/CodeGen/CBackend/2006-12-11-Float-Bitcast.ll
new file mode 100644
index 0000000..c9df800
--- /dev/null
+++ b/test/CodeGen/CBackend/2006-12-11-Float-Bitcast.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=c | \
+; RUN: grep __BITCAST | count 14
+
+define i32 @test1(float %F) {
+ %X = bitcast float %F to i32 ; <i32> [#uses=1]
+ ret i32 %X
+}
+
+define float @test2(i32 %I) {
+ %X = bitcast i32 %I to float ; <float> [#uses=1]
+ ret float %X
+}
+
+define i64 @test3(double %D) {
+ %X = bitcast double %D to i64 ; <i64> [#uses=1]
+ ret i64 %X
+}
+
+define double @test4(i64 %L) {
+ %X = bitcast i64 %L to double ; <double> [#uses=1]
+ ret double %X
+}
+
+define double @test5(double %D) {
+ %X = bitcast double %D to double ; <double> [#uses=1]
+ %Y = fadd double %X, 2.000000e+00 ; <double> [#uses=1]
+ %Z = bitcast double %Y to i64 ; <i64> [#uses=1]
+ %res = bitcast i64 %Z to double ; <double> [#uses=1]
+ ret double %res
+}
+
+define float @test6(float %F) {
+ %X = bitcast float %F to float ; <float> [#uses=1]
+ %Y = fadd float %X, 2.000000e+00 ; <float> [#uses=1]
+ %Z = bitcast float %Y to i32 ; <i32> [#uses=1]
+ %res = bitcast i32 %Z to float ; <float> [#uses=1]
+ ret float %res
+}
+
+define i32 @main(i32 %argc, i8** %argv) {
+ %a = call i32 @test1( float 0x400921FB40000000 ) ; <i32> [#uses=2]
+ %b = call float @test2( i32 %a ) ; <float> [#uses=0]
+ %c = call i64 @test3( double 0x400921FB4D12D84A ) ; <i64> [#uses=1]
+ %d = call double @test4( i64 %c ) ; <double> [#uses=0]
+ %e = call double @test5( double 7.000000e+00 ) ; <double> [#uses=0]
+ %f = call float @test6( float 7.000000e+00 ) ; <float> [#uses=0]
+ ret i32 %a
+}
+
diff --git a/test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll b/test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll
new file mode 100644
index 0000000..da36e78
--- /dev/null
+++ b/test/CodeGen/CBackend/2007-01-08-ParamAttr-ICmp.ll
@@ -0,0 +1,26 @@
+; For PR1099
+; RUN: llc < %s -march=c | grep {(llvm_cbe_tmp2 == llvm_cbe_b_2e_0_2e_0_2e_val)}
+
+target datalayout = "e-p:32:32"
+target triple = "i686-apple-darwin8"
+ %struct.Connector = type { i16, i16, i8, i8, %struct.Connector*, i8* }
+
+
+define i1 @prune_match_entry_2E_ce(%struct.Connector* %a, i16 %b.0.0.val) {
+newFuncRoot:
+ br label %entry.ce
+
+cond_next.exitStub: ; preds = %entry.ce
+ ret i1 true
+
+entry.return_crit_edge.exitStub: ; preds = %entry.ce
+ ret i1 false
+
+entry.ce: ; preds = %newFuncRoot
+ %tmp1 = getelementptr %struct.Connector* %a, i32 0, i32 0 ; <i16*> [#uses=1]
+ %tmp2 = load i16* %tmp1 ; <i16> [#uses=1]
+ %tmp3 = icmp eq i16 %tmp2, %b.0.0.val ; <i1> [#uses=1]
+ br i1 %tmp3, label %cond_next.exitStub, label %entry.return_crit_edge.exitStub
+}
+
+
diff --git a/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll b/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll
new file mode 100644
index 0000000..8a5f253
--- /dev/null
+++ b/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll
@@ -0,0 +1,11 @@
+; PR918
+; RUN: llc < %s -march=c | not grep {l_structtype_s l_fixarray_array3}
+
+%structtype_s = type { i32 }
+%fixarray_array3 = type [3 x %structtype_s]
+
+define i32 @witness(%fixarray_array3* %p) {
+ %q = getelementptr %fixarray_array3* %p, i32 0, i32 0, i32 0
+ %v = load i32* %q
+ ret i32 %v
+}
diff --git a/test/CodeGen/CBackend/2007-01-17-StackSaveNRestore.ll b/test/CodeGen/CBackend/2007-01-17-StackSaveNRestore.ll
new file mode 100644
index 0000000..4f699b7
--- /dev/null
+++ b/test/CodeGen/CBackend/2007-01-17-StackSaveNRestore.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=c | grep __builtin_stack_save
+; RUN: llc < %s -march=c | grep __builtin_stack_restore
+; PR1028
+
+declare i8* @llvm.stacksave()
+declare void @llvm.stackrestore(i8*)
+
+define i8* @test() {
+ %s = call i8* @llvm.stacksave()
+ call void @llvm.stackrestore(i8* %s)
+ ret i8* %s
+}
diff --git a/test/CodeGen/CBackend/2007-02-05-memset.ll b/test/CodeGen/CBackend/2007-02-05-memset.ll
new file mode 100644
index 0000000..7d508e4
--- /dev/null
+++ b/test/CodeGen/CBackend/2007-02-05-memset.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=c
+; PR1181
+target datalayout = "e-p:64:64"
+target triple = "x86_64-apple-darwin8"
+
+
+declare void @llvm.memset.i64(i8*, i8, i64, i32)
+
+define fastcc void @InitUser_data_unregistered() {
+entry:
+ tail call void @llvm.memset.i64( i8* null, i8 0, i64 65496, i32 1 )
+ ret void
+}
diff --git a/test/CodeGen/CBackend/2007-02-23-NameConflicts.ll b/test/CodeGen/CBackend/2007-02-23-NameConflicts.ll
new file mode 100644
index 0000000..7e1ff2a
--- /dev/null
+++ b/test/CodeGen/CBackend/2007-02-23-NameConflicts.ll
@@ -0,0 +1,14 @@
+; PR1164
+; RUN: llc < %s -march=c | grep {llvm_cbe_A = \\*llvm_cbe_G;}
+; RUN: llc < %s -march=c | grep {llvm_cbe_B = \\*(<mp_0_1);}
+; RUN: llc < %s -march=c | grep {return (((unsigned int )(((unsigned int )llvm_cbe_A) + ((unsigned int )llvm_cbe_B))));}
+
+@G = global i32 123
+@ltmp_0_1 = global i32 123
+
+define i32 @test(i32 *%G) {
+ %A = load i32* %G
+ %B = load i32* @ltmp_0_1
+ %C = add i32 %A, %B
+ ret i32 %C
+}
diff --git a/test/CodeGen/CBackend/2007-07-11-PackedStruct.ll b/test/CodeGen/CBackend/2007-07-11-PackedStruct.ll
new file mode 100644
index 0000000..c8bfdd6
--- /dev/null
+++ b/test/CodeGen/CBackend/2007-07-11-PackedStruct.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=c | grep {packed}
+
+ %struct.p = type <{ i16 }>
+
+define i32 @main() {
+entry:
+ %t = alloca %struct.p, align 2
+ ret i32 5
+}
diff --git a/test/CodeGen/CBackend/2008-02-01-UnalignedLoadStore.ll b/test/CodeGen/CBackend/2008-02-01-UnalignedLoadStore.ll
new file mode 100644
index 0000000..6e0cf68
--- /dev/null
+++ b/test/CodeGen/CBackend/2008-02-01-UnalignedLoadStore.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=c | \
+; RUN: grep {struct __attribute__ ((packed, aligned(} | count 4
+
+define void @test(i32* %P) {
+ %X = load i32* %P, align 1
+ store i32 %X, i32* %P, align 1
+ ret void
+}
+
+define void @test2(i32* %P) {
+ %X = volatile load i32* %P, align 2
+ volatile store i32 %X, i32* %P, align 2
+ ret void
+}
+
diff --git a/test/CodeGen/CBackend/2008-05-21-MRV-InlineAsm.ll b/test/CodeGen/CBackend/2008-05-21-MRV-InlineAsm.ll
new file mode 100644
index 0000000..8db3167
--- /dev/null
+++ b/test/CodeGen/CBackend/2008-05-21-MRV-InlineAsm.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=c
+
+declare {i32, i32} @foo()
+
+define i32 @test() {
+ %A = call {i32, i32} @foo()
+ %B = getresult {i32, i32} %A, 0
+ %C = getresult {i32, i32} %A, 1
+ %D = add i32 %B, %C
+ ret i32 %D
+}
+
+define i32 @test2() {
+ %A = call {i32, i32} asm sideeffect "...", "={cx},={di},~{dirflag},~{fpsr},~{flags},~{memory}"()
+ %B = getresult {i32, i32} %A, 0
+ %C = getresult {i32, i32} %A, 1
+ %D = add i32 %B, %C
+ ret i32 %D
+}
diff --git a/test/CodeGen/CBackend/2008-05-31-BoolOverflow.ll b/test/CodeGen/CBackend/2008-05-31-BoolOverflow.ll
new file mode 100644
index 0000000..e9fa552
--- /dev/null
+++ b/test/CodeGen/CBackend/2008-05-31-BoolOverflow.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=c | grep {llvm_cbe_t.*&1}
+define i32 @test(i32 %r) {
+ %s = icmp eq i32 %r, 0
+ %t = add i1 %s, %s
+ %u = zext i1 %t to i32
+ br i1 %t, label %A, label %B
+A:
+
+ ret i32 %u
+B:
+
+ %v = select i1 %t, i32 %r, i32 %u
+ ret i32 %v
+}
diff --git a/test/CodeGen/CBackend/2008-06-04-IndirectMem.ll b/test/CodeGen/CBackend/2008-06-04-IndirectMem.ll
new file mode 100644
index 0000000..054a3ca
--- /dev/null
+++ b/test/CodeGen/CBackend/2008-06-04-IndirectMem.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=c | grep {"m"(llvm_cbe_newcw))}
+; PR2407
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+
+define void @foo() {
+ %newcw = alloca i16 ; <i16*> [#uses=2]
+ call void asm sideeffect "fldcw $0", "*m,~{dirflag},~{fpsr},~{flags}"( i16*
+%newcw ) nounwind
+ ret void
+}
diff --git a/test/CodeGen/CBackend/2008-10-21-PPCLongDoubleConstant.ll b/test/CodeGen/CBackend/2008-10-21-PPCLongDoubleConstant.ll
new file mode 100644
index 0000000..b72b573
--- /dev/null
+++ b/test/CodeGen/CBackend/2008-10-21-PPCLongDoubleConstant.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=c
+; PR2907
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin9.5"
+ %"struct.Point<0>" = type { %"struct.Tensor<1,0>" }
+ %"struct.QGauss2<1>" = type { %"struct.Quadrature<0>" }
+ %"struct.Quadrature<0>" = type { %struct.Subscriptor, i32, %"struct.std::vector<Point<0>,std::allocator<Point<0> > >", %"struct.std::vector<double,std::allocator<double> >" }
+ %struct.Subscriptor = type { i32 (...)**, i32, %"struct.std::type_info"* }
+ %"struct.Tensor<1,0>" = type { [1 x double] }
+ %"struct.std::_Vector_base<Point<0>,std::allocator<Point<0> > >" = type { %"struct.std::_Vector_base<Point<0>,std::allocator<Point<0> > >::_Vector_impl" }
+ %"struct.std::_Vector_base<Point<0>,std::allocator<Point<0> > >::_Vector_impl" = type { %"struct.Point<0>"*, %"struct.Point<0>"*, %"struct.Point<0>"* }
+ %"struct.std::_Vector_base<double,std::allocator<double> >" = type { %"struct.std::_Vector_base<double,std::allocator<double> >::_Vector_impl" }
+ %"struct.std::_Vector_base<double,std::allocator<double> >::_Vector_impl" = type { double*, double*, double* }
+ %"struct.std::type_info" = type { i32 (...)**, i8* }
+ %"struct.std::vector<Point<0>,std::allocator<Point<0> > >" = type { %"struct.std::_Vector_base<Point<0>,std::allocator<Point<0> > >" }
+ %"struct.std::vector<double,std::allocator<double> >" = type { %"struct.std::_Vector_base<double,std::allocator<double> >" }
+
+define fastcc void @_ZN6QGaussILi1EEC1Ej(%"struct.QGauss2<1>"* %this, i32 %n) {
+entry:
+ br label %bb4
+
+bb4: ; preds = %bb5.split, %bb4, %entry
+ %0 = fcmp ogt ppc_fp128 0xM00000000000000000000000000000000, select (i1 fcmp olt (ppc_fp128 fpext (double 0x3C447AE147AE147B to ppc_fp128), ppc_fp128 fmul (ppc_fp128 0xM00000000000000010000000000000000, ppc_fp128 0xM40140000000000000000000000000000)), ppc_fp128 fmul (ppc_fp128 0xM00000000000000010000000000000000, ppc_fp128 0xM40140000000000000000000000000000), ppc_fp128 fpext (double 0x3C447AE147AE147B to ppc_fp128)) ; <i1> [#uses=1]
+ br i1 %0, label %bb4, label %bb5.split
+
+bb5.split: ; preds = %bb4
+ %1 = getelementptr double* null, i32 0 ; <double*> [#uses=0]
+ br label %bb4
+}
diff --git a/test/CodeGen/CBackend/dg.exp b/test/CodeGen/CBackend/dg.exp
new file mode 100644
index 0000000..9d78940
--- /dev/null
+++ b/test/CodeGen/CBackend/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target CBackend] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/CBackend/fneg.ll b/test/CodeGen/CBackend/fneg.ll
new file mode 100644
index 0000000..7dec3d9
--- /dev/null
+++ b/test/CodeGen/CBackend/fneg.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=c
+
+define void @func() nounwind {
+ entry:
+ %0 = fsub double -0.0, undef
+ ret void
+}
diff --git a/test/CodeGen/CBackend/pr2408.ll b/test/CodeGen/CBackend/pr2408.ll
new file mode 100644
index 0000000..bf8477b
--- /dev/null
+++ b/test/CodeGen/CBackend/pr2408.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=c | grep {\\* ((unsigned int )}
+; PR2408
+
+define i32 @a(i32 %a) {
+entry:
+ %shr = ashr i32 %a, 0 ; <i32> [#uses=1]
+ %shr2 = ashr i32 2, 0 ; <i32> [#uses=1]
+ %mul = mul i32 %shr, %shr2 ; <i32> [#uses=1]
+ %shr4 = ashr i32 2, 0 ; <i32> [#uses=1]
+ %div = sdiv i32 %mul, %shr4 ; <i32> [#uses=1]
+ ret i32 %div
+}
diff --git a/test/CodeGen/CBackend/vectors.ll b/test/CodeGen/CBackend/vectors.ll
new file mode 100644
index 0000000..b7b7677
--- /dev/null
+++ b/test/CodeGen/CBackend/vectors.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=c
[email protected] = external global [2 x i8]
+
+define <4 x i32> @foo(<4 x i32> %a, i32 %b) {
+ %c = insertelement <4 x i32> %a, i32 1, i32 %b
+
+ ret <4 x i32> %c
+}
+
+define i32 @test2(<4 x i32> %a, i32 %b) {
+ %c = extractelement <4 x i32> %a, i32 1
+
+ ret i32 %c
+}
+
+define <4 x float> @test3(<4 x float> %Y) {
+ %Z = fadd <4 x float> %Y, %Y
+ %X = shufflevector <4 x float> zeroinitializer, <4 x float> %Z, <4 x i32> < i32 0, i32 5, i32 6, i32 7 >
+ ret <4 x float> %X
+}
+
+define void @test4() {
+ %x = alloca <4 x float>
+ %tmp3.i16 = getelementptr <4 x float>* %x, i32 0, i32 0
+ store float 1.0, float* %tmp3.i16
+ ret void
+}
+
+define i32* @test5({i32, i32} * %P) {
+ %x = getelementptr {i32, i32} * %P, i32 0, i32 1
+ ret i32* %x
+}
+
+define i8* @test6() {
+ ret i8* getelementptr ([2 x i8]* @.str15, i32 0, i32 0)
+}
+
diff --git a/test/CodeGen/CPP/2007-06-16-Funcname.ll b/test/CodeGen/CPP/2007-06-16-Funcname.ll
new file mode 100644
index 0000000..71fea12
--- /dev/null
+++ b/test/CodeGen/CPP/2007-06-16-Funcname.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=cpp -cppfname=WAKKA | not grep makeLLVMModule
+; PR1515
+
+define void @foo() {
+ ret void
+}
+
diff --git a/test/CodeGen/CPP/2009-05-01-Long-Double.ll b/test/CodeGen/CPP/2009-05-01-Long-Double.ll
new file mode 100644
index 0000000..0b2d882
--- /dev/null
+++ b/test/CodeGen/CPP/2009-05-01-Long-Double.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=cpp -cppgen=program -o %t
+
+define x86_fp80 @some_func() nounwind {
+entry:
+ %retval = alloca x86_fp80 ; <x86_fp80*> [#uses=2]
+ %call = call i32 (...)* @other_func() ; <i32> [#uses=1]
+ %conv = sitofp i32 %call to x86_fp80 ; <x86_fp80> [#uses=1]
+ store x86_fp80 %conv, x86_fp80* %retval
+ %0 = load x86_fp80* %retval ; <x86_fp80> [#uses=1]
+ ret x86_fp80 %0
+}
+
+declare i32 @other_func(...)
diff --git a/test/CodeGen/CPP/2009-05-04-CondBr.ll b/test/CodeGen/CPP/2009-05-04-CondBr.ll
new file mode 100644
index 0000000..feb2cf7
--- /dev/null
+++ b/test/CodeGen/CPP/2009-05-04-CondBr.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=cpp -cppgen=program -o %t
+; RUN: grep "BranchInst::Create(label_if_then, label_if_end, int1_cmp, label_entry);" %t
+
+define i32 @some_func(i32 %a) nounwind {
+entry:
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ %a.addr = alloca i32 ; <i32*> [#uses=8]
+ store i32 %a, i32* %a.addr
+ %tmp = load i32* %a.addr ; <i32> [#uses=1]
+ %inc = add i32 %tmp, 1 ; <i32> [#uses=1]
+ store i32 %inc, i32* %a.addr
+ %tmp1 = load i32* %a.addr ; <i32> [#uses=1]
+ %cmp = icmp slt i32 %tmp1, 3 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ store i32 7, i32* %a.addr
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ %tmp2 = load i32* %a.addr ; <i32> [#uses=1]
+ %inc3 = add i32 %tmp2, 1 ; <i32> [#uses=1]
+ store i32 %inc3, i32* %a.addr
+ %tmp4 = load i32* %a.addr ; <i32> [#uses=1]
+ store i32 %tmp4, i32* %retval
+ %0 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %0
+}
diff --git a/test/CodeGen/CPP/dg.exp b/test/CodeGen/CPP/dg.exp
new file mode 100644
index 0000000..3276dcc
--- /dev/null
+++ b/test/CodeGen/CPP/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target CppBackend] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/CPP/llvm2cpp.ll b/test/CodeGen/CPP/llvm2cpp.ll
new file mode 100644
index 0000000..d0ba0cf
--- /dev/null
+++ b/test/CodeGen/CPP/llvm2cpp.ll
@@ -0,0 +1,756 @@
+; RUN: llvm-as < %s | llvm-dis > /dev/null
+; RUN: llc < %s -march=cpp -cppgen=program -o -
+
+@X = global i32 4, align 16 ; <i32*> [#uses=0]
+
+define i32* @test1012() align 32 {
+ %X = alloca i32, align 4 ; <i32*> [#uses=1]
+ %Y = alloca i32, i32 42, align 16 ; <i32*> [#uses=0]
+ %Z = alloca i32 ; <i32*> [#uses=0]
+ ret i32* %X
+}
+
+define i32* @test1013() {
+ %X = malloc i32, align 4 ; <i32*> [#uses=1]
+ %Y = malloc i32, i32 42, align 16 ; <i32*> [#uses=0]
+ %Z = malloc i32 ; <i32*> [#uses=0]
+ ret i32* %X
+}
+
+define void @void(i32, i32) {
+ add i32 0, 0 ; <i32>:3 [#uses=2]
+ sub i32 0, 4 ; <i32>:4 [#uses=2]
+ br label %5
+
+; <label>:5 ; preds = %5, %2
+ add i32 %0, %1 ; <i32>:6 [#uses=2]
+ sub i32 %6, %4 ; <i32>:7 [#uses=1]
+ icmp sle i32 %7, %3 ; <i1>:8 [#uses=1]
+ br i1 %8, label %9, label %5
+
+; <label>:9 ; preds = %5
+ add i32 %0, %1 ; <i32>:10 [#uses=0]
+ sub i32 %6, %4 ; <i32>:11 [#uses=1]
+ icmp sle i32 %11, %3 ; <i1>:12 [#uses=0]
+ ret void
+}
+
+define i32 @zarro() {
+Startup:
+ ret i32 0
+}
+
+define fastcc void @foo() {
+ ret void
+}
+
+define coldcc void @bar() {
+ call fastcc void @foo( )
+ ret void
+}
+
+define void @structret({ i8 }* sret %P) {
+ call void @structret( { i8 }* %P sret )
+ ret void
+}
+
+define void @foo4() {
+ ret void
+}
+
+define coldcc void @bar2() {
+ call fastcc void @foo( )
+ ret void
+}
+
+define cc42 void @bar3() {
+ invoke fastcc void @foo( )
+ to label %Ok unwind label %U
+
+Ok: ; preds = %0
+ ret void
+
+U: ; preds = %0
+ unwind
+}
+
+define void @bar4() {
+ call cc42 void @bar( )
+ invoke cc42 void @bar3( )
+ to label %Ok unwind label %U
+
+Ok: ; preds = %0
+ ret void
+
+U: ; preds = %0
+ unwind
+}
+; ModuleID = 'calltest.ll'
+ %FunTy = type i32 (i32)
+
+define i32 @test1000(i32 %i0) {
+ ret i32 %i0
+}
+
+define void @invoke(%FunTy* %x) {
+ %foo = call i32 %x( i32 123 ) ; <i32> [#uses=0]
+ %foo2 = tail call i32 %x( i32 123 ) ; <i32> [#uses=0]
+ ret void
+}
+
+define i32 @main(i32 %argc) {
+ %retval = call i32 @test1000( i32 %argc ) ; <i32> [#uses=2]
+ %two = add i32 %retval, %retval ; <i32> [#uses=1]
+ %retval2 = invoke i32 @test1000( i32 %argc )
+ to label %Next unwind label %Error ; <i32> [#uses=1]
+
+Next: ; preds = %0
+ %two2 = add i32 %two, %retval2 ; <i32> [#uses=1]
+ call void @invoke( %FunTy* @test1000 )
+ ret i32 %two2
+
+Error: ; preds = %0
+ ret i32 -1
+}
+; ModuleID = 'casttest.ll'
+
+define i16 @FunFunc(i64 %x, i8 %z) {
+bb0:
+ %cast110 = sext i8 %z to i16 ; <i16> [#uses=1]
+ %cast10 = trunc i64 %x to i16 ; <i16> [#uses=1]
+ %reg109 = add i16 %cast110, %cast10 ; <i16> [#uses=1]
+ ret i16 %reg109
+}
+; ModuleID = 'cfgstructures.ll'
+
+define void @irreducible(i1 %cond) {
+ br i1 %cond, label %X, label %Y
+
+X: ; preds = %Y, %0
+ br label %Y
+
+Y: ; preds = %X, %0
+ br label %X
+}
+
+define void @sharedheader(i1 %cond) {
+ br label %A
+
+A: ; preds = %Y, %X, %0
+ br i1 %cond, label %X, label %Y
+
+X: ; preds = %A
+ br label %A
+
+Y: ; preds = %A
+ br label %A
+}
+
+define void @nested(i1 %cond1, i1 %cond2, i1 %cond3) {
+ br label %Loop1
+
+Loop1: ; preds = %L2Exit, %0
+ br label %Loop2
+
+Loop2: ; preds = %L3Exit, %Loop1
+ br label %Loop3
+
+Loop3: ; preds = %Loop3, %Loop2
+ br i1 %cond3, label %Loop3, label %L3Exit
+
+L3Exit: ; preds = %Loop3
+ br i1 %cond2, label %Loop2, label %L2Exit
+
+L2Exit: ; preds = %L3Exit
+ br i1 %cond1, label %Loop1, label %L1Exit
+
+L1Exit: ; preds = %L2Exit
+ ret void
+}
+; ModuleID = 'constexpr.ll'
+ %SAType = type { i32, { [2 x float], i64 } }
+ %SType = type { i32, { float, { i8 } }, i64 }
+global i64 1 ; <i64*>:0 [#uses=0]
+global i64 74514 ; <i64*>:1 [#uses=0]
+@t2 = global i32* @t1 ; <i32**> [#uses=0]
+@t3 = global i32* @t1 ; <i32**> [#uses=2]
+@t1 = global i32 4 ; <i32*> [#uses=2]
+@t4 = global i32** @t3 ; <i32***> [#uses=1]
+@t5 = global i32** @t3 ; <i32***> [#uses=0]
+@t6 = global i32*** @t4 ; <i32****> [#uses=0]
+@t7 = global float* inttoptr (i32 12345678 to float*) ; <float**> [#uses=0]
+@t9 = global i32 8 ; <i32*> [#uses=0]
+global i32* bitcast (float* @4 to i32*) ; <i32**>:2 [#uses=0]
+global float* @4 ; <float**>:3 [#uses=0]
+global float 0.000000e+00 ; <float*>:4 [#uses=2]
+@array = constant [2 x i32] [ i32 12, i32 52 ] ; <[2 x i32]*> [#uses=1]
+@arrayPtr = global i32* getelementptr ([2 x i32]* @array, i64 0, i64 0) ; <i32**> [#uses=1]
+@arrayPtr5 = global i32** getelementptr (i32** @arrayPtr, i64 5) ; <i32***> [#uses=0]
+@somestr = constant [11 x i8] c"hello world" ; <[11 x i8]*> [#uses=2]
+@char5 = global i8* getelementptr ([11 x i8]* @somestr, i64 0, i64 5) ; <i8**> [#uses=0]
+@char8a = global i32* bitcast (i8* getelementptr ([11 x i8]* @somestr, i64 0, i64 8) to i32*) ; <i32**> [#uses=0]
+@char8b = global i8* getelementptr ([11 x i8]* @somestr, i64 0, i64 8) ; <i8**> [#uses=0]
+@S1 = global %SType* null ; <%SType**> [#uses=1]
+@S2c = constant %SType {
+ i32 1,
+ { float, { i8 } } { float 2.000000e+00, { i8 } { i8 3 } },
+ i64 4 } ; <%SType*> [#uses=3]
+@S3c = constant %SAType { i32 1, { [2 x float], i64 } { [2 x float] [ float 2.000000e+00, float 3.000000e+00 ], i64 4 } } ; <%SAType*> [#uses=1]
+@S1ptr = global %SType** @S1 ; <%SType***> [#uses=0]
+@S2 = global %SType* @S2c ; <%SType**> [#uses=0]
+@S3 = global %SAType* @S3c ; <%SAType**> [#uses=0]
+@S1fld1a = global float* getelementptr (%SType* @S2c, i64 0, i32 1, i32 0) ; <float**> [#uses=0]
+@S1fld1b = global float* getelementptr (%SType* @S2c, i64 0, i32 1, i32 0) ; <float**> [#uses=1]
+@S1fld1bptr = global float** @S1fld1b ; <float***> [#uses=0]
+@S2fld3 = global i8* getelementptr (%SType* @S2c, i64 0, i32 1, i32 1, i32 0) ; <i8**> [#uses=0]
+
+; ModuleID = 'constpointer.ll'
+@cpt3 = global i32* @cpt1 ; <i32**> [#uses=1]
+@cpt1 = global i32 4 ; <i32*> [#uses=2]
+@cpt4 = global i32** @cpt3 ; <i32***> [#uses=0]
+@cpt2 = global i32* @cpt1 ; <i32**> [#uses=0]
+global float* @7 ; <float**>:0 [#uses=0]
+global float* @7 ; <float**>:1 [#uses=0]
+global float 0.000000e+00 ; <float*>:2 [#uses=3]
+global float* @7 ; <float**>:3 [#uses=0]
+@fptr = global void ()* @f ; <void ()**> [#uses=0]
+@sptr1 = global [11 x i8]* @somestr ; <[11 x i8]**> [#uses=0]
+@somestr2 = constant [11 x i8] c"hello world" ; <[11 x i8]*> [#uses=2]
+@sptr2 = global [11 x i8]* @somestr2 ; <[11 x i8]**> [#uses=0]
+
+declare void @f()
+; ModuleID = 'escaped_label.ll'
+
+define i32 @foo3() {
+ br label "foo`~!@#$%^&*()-_=+{}[]\\|;:',<.>/?"
+
+"foo`~!@#$%^&*()-_=+{}[]\\|;:',<.>/?": ; preds = %0
+ ret i32 17
+}
+; ModuleID = 'float.ll'
+@F1 = global float 4.000000e+00 ; <float*> [#uses=0]
+@D1 = global double 4.000000e+00 ; <double*> [#uses=0]
+; ModuleID = 'fold-fpcast.ll'
+
+define i32 @test1() {
+ ret i32 1080872141
+}
+
+define float @test1002() {
+ ret float 0x36E1000000000000
+}
+
+define i64 @test3() {
+ ret i64 4614256656431372362
+}
+
+define double @test4() {
+ ret double 2.075076e-322
+}
+; ModuleID = 'forwardreftest.ll'
+ %myfn = type float (i32, double, i32, i16)
+ %myty = type i32
+ %thisfuncty = type i32 (i32)*
+
+declare void @F(%thisfuncty, %thisfuncty, %thisfuncty)
+
+define i32 @zarro2(i32 %Func) {
+Startup:
+ add i32 0, 10 ; <i32>:0 [#uses=0]
+ ret i32 0
+}
+
+define i32 @test1004(i32) {
+ call void @F( %thisfuncty @zarro2, %thisfuncty @test1004, %thisfuncty @foozball )
+ ret i32 0
+}
+
+define i32 @foozball(i32) {
+ ret i32 0
+}
+
+; ModuleID = 'globalredefinition.ll'
+@A = global i32* @B ; <i32**> [#uses=0]
+@B = global i32 7 ; <i32*> [#uses=1]
+
+define void @test12312() {
+ ret void
+}
+; ModuleID = 'global_section.ll'
+@GlobSec = global i32 4, section "foo", align 16
+
+define void @test1005() section "bar" {
+ ret void
+}
+
+; ModuleID = 'globalvars.ll'
+@MyVar = external global i32 ; <i32*> [#uses=1]
+@MyIntList = external global { \2*, i32 } ; <{ \2*, i32 }*> [#uses=1]
+external global i32 ; <i32*>:0 [#uses=0]
+@AConst = constant i32 123 ; <i32*> [#uses=0]
+@AString = constant [4 x i8] c"test" ; <[4 x i8]*> [#uses=0]
+@ZeroInit = global { [100 x i32], [40 x float] } zeroinitializer ; <{ [100 x i32], [40 x float] }*> [#uses=0]
+
+define i32 @foo10015(i32 %blah) {
+ store i32 5, i32* @MyVar
+ %idx = getelementptr { \2*, i32 }* @MyIntList, i64 0, i32 1 ; <i32*> [#uses=1]
+ store i32 12, i32* %idx
+ ret i32 %blah
+}
+; ModuleID = 'indirectcall2.ll'
+
+define i64 @test1006(i64 %X) {
+ ret i64 %X
+}
+
+define i64 @fib(i64 %n) {
+; <label>:0
+ %T = icmp ult i64 %n, 2 ; <i1> [#uses=1]
+ br i1 %T, label %BaseCase, label %RecurseCase
+
+RecurseCase: ; preds = %0
+ %result = call i64 @test1006( i64 %n ) ; <i64> [#uses=0]
+ br label %BaseCase
+
+BaseCase: ; preds = %RecurseCase, %0
+ %X = phi i64 [ 1, %0 ], [ 2, %RecurseCase ] ; <i64> [#uses=1]
+ ret i64 %X
+}
+; ModuleID = 'indirectcall.ll'
+
+declare i32 @atoi(i8*)
+
+define i64 @fibonacc(i64 %n) {
+ icmp ult i64 %n, 2 ; <i1>:1 [#uses=1]
+ br i1 %1, label %BaseCase, label %RecurseCase
+
+BaseCase: ; preds = %0
+ ret i64 1
+
+RecurseCase: ; preds = %0
+ %n2 = sub i64 %n, 2 ; <i64> [#uses=1]
+ %n1 = sub i64 %n, 1 ; <i64> [#uses=1]
+ %f2 = call i64 @fibonacc( i64 %n2 ) ; <i64> [#uses=1]
+ %f1 = call i64 @fibonacc( i64 %n1 ) ; <i64> [#uses=1]
+ %result = add i64 %f2, %f1 ; <i64> [#uses=1]
+ ret i64 %result
+}
+
+define i64 @realmain(i32 %argc, i8** %argv) {
+; <label>:0
+ icmp eq i32 %argc, 2 ; <i1>:1 [#uses=1]
+ br i1 %1, label %HasArg, label %Continue
+
+HasArg: ; preds = %0
+ %n1 = add i32 1, 1 ; <i32> [#uses=1]
+ br label %Continue
+
+Continue: ; preds = %HasArg, %0
+ %n = phi i32 [ %n1, %HasArg ], [ 1, %0 ] ; <i32> [#uses=1]
+ %N = sext i32 %n to i64 ; <i64> [#uses=1]
+ %F = call i64 @fib( i64 %N ) ; <i64> [#uses=1]
+ ret i64 %F
+}
+
+define i64 @trampoline(i64 %n, i64 (i64)* %fibfunc) {
+ %F = call i64 %fibfunc( i64 %n ) ; <i64> [#uses=1]
+ ret i64 %F
+}
+
+define i32 @main2() {
+ %Result = call i64 @trampoline( i64 10, i64 (i64)* @fib ) ; <i64> [#uses=1]
+ %Result.upgrd.1 = trunc i64 %Result to i32 ; <i32> [#uses=1]
+ ret i32 %Result.upgrd.1
+}
+; ModuleID = 'inlineasm.ll'
+module asm "this is an inline asm block"
+module asm "this is another inline asm block"
+
+define i32 @test1007() {
+ %X = call i32 asm "tricky here $0, $1", "=r,r"( i32 4 ) ; <i32> [#uses=1]
+ call void asm sideeffect "eieio", ""( )
+ ret i32 %X
+}
+; ModuleID = 'instructions.ll'
+
+define i32 @test_extractelement(<4 x i32> %V) {
+ %R = extractelement <4 x i32> %V, i32 1 ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define <4 x i32> @test_insertelement(<4 x i32> %V) {
+ %R = insertelement <4 x i32> %V, i32 0, i32 0 ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %R
+}
+
+define <4 x i32> @test_shufflevector_u(<4 x i32> %V) {
+ %R = shufflevector <4 x i32> %V, <4 x i32> %V, <4 x i32> < i32 1, i32 undef, i32 7, i32 2 > ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %R
+}
+
+define <4 x float> @test_shufflevector_f(<4 x float> %V) {
+ %R = shufflevector <4 x float> %V, <4 x float> undef, <4 x i32> < i32 1, i32 undef, i32 7, i32 2 > ; <<4 x float>> [#uses=1]
+ ret <4 x float> %R
+}
+; ModuleID = 'intrinsics.ll'
+
+declare i1 @llvm.isunordered.f32(float, float)
+
+declare i1 @llvm.isunordered.f64(double, double)
+
+declare void @llvm.prefetch(i8*, i32, i32)
+
+declare float @llvm.sqrt.f32(float)
+
+declare double @llvm.sqrt.f64(double)
+
+define void @libm() {
+ fcmp uno float 1.000000e+00, 2.000000e+00 ; <i1>:1 [#uses=0]
+ fcmp uno double 3.000000e+00, 4.000000e+00 ; <i1>:2 [#uses=0]
+ call void @llvm.prefetch( i8* null, i32 1, i32 3 )
+ call float @llvm.sqrt.f32( float 5.000000e+00 ) ; <float>:3 [#uses=0]
+ call double @llvm.sqrt.f64( double 6.000000e+00 ) ; <double>:4 [#uses=0]
+ call i8 @llvm.ctpop.i8( i8 10 ) ; <i32>:5 [#uses=1]
+ call i16 @llvm.ctpop.i16( i16 11 ) ; <i32>:7 [#uses=1]
+ call i32 @llvm.ctpop.i32( i32 12 ) ; <i32>:9 [#uses=1]
+ call i64 @llvm.ctpop.i64( i64 13 ) ; <i32>:11 [#uses=1]
+ call i8 @llvm.ctlz.i8( i8 14 ) ; <i32>:13 [#uses=1]
+ call i16 @llvm.ctlz.i16( i16 15 ) ; <i32>:15 [#uses=1]
+ call i32 @llvm.ctlz.i32( i32 16 ) ; <i32>:17 [#uses=1]
+ call i64 @llvm.ctlz.i64( i64 17 ) ; <i32>:19 [#uses=1]
+ call i8 @llvm.cttz.i8( i8 18 ) ; <i32>:21 [#uses=1]
+ call i16 @llvm.cttz.i16( i16 19 ) ; <i32>:23 [#uses=1]
+ call i32 @llvm.cttz.i32( i32 20 ) ; <i32>:25 [#uses=1]
+ call i64 @llvm.cttz.i64( i64 21 ) ; <i32>:27 [#uses=1]
+ ret void
+}
+
+declare i8 @llvm.ctpop.i8(i8)
+
+declare i16 @llvm.ctpop.i16(i16)
+
+declare i32 @llvm.ctpop.i32(i32)
+
+declare i64 @llvm.ctpop.i64(i64)
+
+declare i8 @llvm.ctlz.i8(i8)
+
+declare i16 @llvm.ctlz.i16(i16)
+
+declare i32 @llvm.ctlz.i32(i32)
+
+declare i64 @llvm.ctlz.i64(i64)
+
+declare i8 @llvm.cttz.i8(i8)
+
+declare i16 @llvm.cttz.i16(i16)
+
+declare i32 @llvm.cttz.i32(i32)
+
+declare i64 @llvm.cttz.i64(i64)
+
+; ModuleID = 'packed.ll'
+@foo1 = external global <4 x float> ; <<4 x float>*> [#uses=2]
+@foo102 = external global <2 x i32> ; <<2 x i32>*> [#uses=2]
+
+define void @main3() {
+ store <4 x float> < float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00 >, <4 x float>* @foo1
+ store <2 x i32> < i32 4, i32 4 >, <2 x i32>* @foo102
+ %l1 = load <4 x float>* @foo1 ; <<4 x float>> [#uses=0]
+ %l2 = load <2 x i32>* @foo102 ; <<2 x i32>> [#uses=0]
+ ret void
+}
+
+; ModuleID = 'properties.ll'
+target datalayout = "e-p:32:32"
+target triple = "proc-vend-sys"
+deplibs = [ "m", "c" ]
+; ModuleID = 'prototype.ll'
+
+declare i32 @bar1017(i32 %in)
+
+define i32 @foo1016(i32 %blah) {
+ %xx = call i32 @bar1017( i32 %blah ) ; <i32> [#uses=1]
+ ret i32 %xx
+}
+
+; ModuleID = 'recursivetype.ll'
+ %list = type { %list*, i32 }
+
+declare i8* @malloc(i32)
+
+define void @InsertIntoListTail(%list** %L, i32 %Data) {
+bb1:
+ %reg116 = load %list** %L ; <%list*> [#uses=1]
+ %cast1004 = inttoptr i64 0 to %list* ; <%list*> [#uses=1]
+ %cond1000 = icmp eq %list* %reg116, %cast1004 ; <i1> [#uses=1]
+ br i1 %cond1000, label %bb3, label %bb2
+
+bb2: ; preds = %bb2, %bb1
+ %reg117 = phi %list** [ %reg118, %bb2 ], [ %L, %bb1 ] ; <%list**> [#uses=1]
+ %cast1010 = bitcast %list** %reg117 to %list*** ; <%list***> [#uses=1]
+ %reg118 = load %list*** %cast1010 ; <%list**> [#uses=3]
+ %reg109 = load %list** %reg118 ; <%list*> [#uses=1]
+ %cast1005 = inttoptr i64 0 to %list* ; <%list*> [#uses=1]
+ %cond1001 = icmp ne %list* %reg109, %cast1005 ; <i1> [#uses=1]
+ br i1 %cond1001, label %bb2, label %bb3
+
+bb3: ; preds = %bb2, %bb1
+ %reg119 = phi %list** [ %reg118, %bb2 ], [ %L, %bb1 ] ; <%list**> [#uses=1]
+ %cast1006 = bitcast %list** %reg119 to i8** ; <i8**> [#uses=1]
+ %reg111 = call i8* @malloc( i32 16 ) ; <i8*> [#uses=3]
+ store i8* %reg111, i8** %cast1006
+ %reg111.upgrd.1 = ptrtoint i8* %reg111 to i64 ; <i64> [#uses=1]
+ %reg1002 = add i64 %reg111.upgrd.1, 8 ; <i64> [#uses=1]
+ %reg1002.upgrd.2 = inttoptr i64 %reg1002 to i8* ; <i8*> [#uses=1]
+ %cast1008 = bitcast i8* %reg1002.upgrd.2 to i32* ; <i32*> [#uses=1]
+ store i32 %Data, i32* %cast1008
+ %cast1003 = inttoptr i64 0 to i64* ; <i64*> [#uses=1]
+ %cast1009 = bitcast i8* %reg111 to i64** ; <i64**> [#uses=1]
+ store i64* %cast1003, i64** %cast1009
+ ret void
+}
+
+define %list* @FindData(%list* %L, i32 %Data) {
+bb1:
+ br label %bb2
+
+bb2: ; preds = %bb6, %bb1
+ %reg115 = phi %list* [ %reg116, %bb6 ], [ %L, %bb1 ] ; <%list*> [#uses=4]
+ %cast1014 = inttoptr i64 0 to %list* ; <%list*> [#uses=1]
+ %cond1011 = icmp ne %list* %reg115, %cast1014 ; <i1> [#uses=1]
+ br i1 %cond1011, label %bb4, label %bb3
+
+bb3: ; preds = %bb2
+ ret %list* null
+
+bb4: ; preds = %bb2
+ %idx = getelementptr %list* %reg115, i64 0, i32 1 ; <i32*> [#uses=1]
+ %reg111 = load i32* %idx ; <i32> [#uses=1]
+ %cond1013 = icmp ne i32 %reg111, %Data ; <i1> [#uses=1]
+ br i1 %cond1013, label %bb6, label %bb5
+
+bb5: ; preds = %bb4
+ ret %list* %reg115
+
+bb6: ; preds = %bb4
+ %idx2 = getelementptr %list* %reg115, i64 0, i32 0 ; <%list**> [#uses=1]
+ %reg116 = load %list** %idx2 ; <%list*> [#uses=1]
+ br label %bb2
+}
+; ModuleID = 'simplecalltest.ll'
+ %FunTy = type i32 (i32)
+
+define void @invoke1019(%FunTy* %x) {
+ %foo = call i32 %x( i32 123 ) ; <i32> [#uses=0]
+ ret void
+}
+
+define i32 @main4(i32 %argc, i8** %argv, i8** %envp) {
+ %retval = call i32 @test1008( i32 %argc ) ; <i32> [#uses=2]
+ %two = add i32 %retval, %retval ; <i32> [#uses=1]
+ %retval2 = call i32 @test1008( i32 %argc ) ; <i32> [#uses=1]
+ %two2 = add i32 %two, %retval2 ; <i32> [#uses=1]
+ call void @invoke1019( %FunTy* @test1008 )
+ ret i32 %two2
+}
+
+define i32 @test1008(i32 %i0) {
+ ret i32 %i0
+}
+; ModuleID = 'smallest.ll'
+; ModuleID = 'small.ll'
+ %x = type i32
+
+define i32 @foo1020(i32 %in) {
+label:
+ ret i32 2
+}
+; ModuleID = 'testalloca.ll'
+ %inners = type { float, { i8 } }
+ %struct = type { i32, %inners, i64 }
+
+define i32 @testfunction(i32 %i0, i32 %j0) {
+ alloca i8, i32 5 ; <i8*>:1 [#uses=0]
+ %ptr = alloca i32 ; <i32*> [#uses=2]
+ store i32 3, i32* %ptr
+ %val = load i32* %ptr ; <i32> [#uses=0]
+ %sptr = alloca %struct ; <%struct*> [#uses=2]
+ %nsptr = getelementptr %struct* %sptr, i64 0, i32 1 ; <%inners*> [#uses=1]
+ %ubsptr = getelementptr %inners* %nsptr, i64 0, i32 1 ; <{ i8 }*> [#uses=1]
+ %idx = getelementptr { i8 }* %ubsptr, i64 0, i32 0 ; <i8*> [#uses=1]
+ store i8 4, i8* %idx
+ %fptr = getelementptr %struct* %sptr, i64 0, i32 1, i32 0 ; <float*> [#uses=1]
+ store float 4.000000e+00, float* %fptr
+ ret i32 3
+}
+; ModuleID = 'testconstants.ll'
+@somestr3 = constant [11 x i8] c"hello world"
+@array99 = constant [2 x i32] [ i32 12, i32 52 ]
+constant { i32, i32 } { i32 4, i32 3 } ; <{ i32, i32 }*>:0 [#uses=0]
+
+define [2 x i32]* @testfunction99(i32 %i0, i32 %j0) {
+ ret [2 x i32]* @array
+}
+
+define i8* @otherfunc(i32, double) {
+ %somestr = getelementptr [11 x i8]* @somestr3, i64 0, i64 0 ; <i8*> [#uses=1]
+ ret i8* %somestr
+}
+
+define i8* @yetanotherfunc(i32, double) {
+ ret i8* null
+}
+
+define i32 @negativeUnsigned() {
+ ret i32 -1
+}
+
+define i32 @largeSigned() {
+ ret i32 -394967296
+}
+; ModuleID = 'testlogical.ll'
+
+define i32 @simpleAdd(i32 %i0, i32 %j0) {
+ %t1 = xor i32 %i0, %j0 ; <i32> [#uses=1]
+ %t2 = or i32 %i0, %j0 ; <i32> [#uses=1]
+ %t3 = and i32 %t1, %t2 ; <i32> [#uses=1]
+ ret i32 %t3
+}
+; ModuleID = 'testmemory.ll'
+ %complexty = type { i32, { [4 x i8*], float }, double }
+ %struct = type { i32, { float, { i8 } }, i64 }
+
+define i32 @main6() {
+ call i32 @testfunction98( i64 0, i64 1 )
+ ret i32 0
+}
+
+define i32 @testfunction98(i64 %i0, i64 %j0) {
+ %array0 = malloc [4 x i8] ; <[4 x i8]*> [#uses=2]
+ %size = add i32 2, 2 ; <i32> [#uses=1]
+ %array1 = malloc i8, i32 4 ; <i8*> [#uses=1]
+ %array2 = malloc i8, i32 %size ; <i8*> [#uses=1]
+ %idx = getelementptr [4 x i8]* %array0, i64 0, i64 2 ; <i8*> [#uses=1]
+ store i8 123, i8* %idx
+ free [4 x i8]* %array0
+ free i8* %array1
+ free i8* %array2
+ %aa = alloca %complexty, i32 5 ; <%complexty*> [#uses=1]
+ %idx2 = getelementptr %complexty* %aa, i64 %i0, i32 1, i32 0, i64 %j0 ; <i8**> [#uses=1]
+ store i8* null, i8** %idx2
+ %ptr = alloca i32 ; <i32*> [#uses=2]
+ store i32 3, i32* %ptr
+ %val = load i32* %ptr ; <i32> [#uses=0]
+ %sptr = alloca %struct ; <%struct*> [#uses=1]
+ %ubsptr = getelementptr %struct* %sptr, i64 0, i32 1, i32 1 ; <{ i8 }*> [#uses=1]
+ %idx3 = getelementptr { i8 }* %ubsptr, i64 0, i32 0 ; <i8*> [#uses=1]
+ store i8 4, i8* %idx3
+ ret i32 3
+}
+; ModuleID = 'testswitch.ll'
+ %int = type i32
+
+define i32 @squared(i32 %i0) {
+ switch i32 %i0, label %Default [
+ i32 1, label %Case1
+ i32 2, label %Case2
+ i32 4, label %Case4
+ ]
+
+Default: ; preds = %0
+ ret i32 -1
+
+Case1: ; preds = %0
+ ret i32 1
+
+Case2: ; preds = %0
+ ret i32 4
+
+Case4: ; preds = %0
+ ret i32 16
+}
+; ModuleID = 'testvarargs.ll'
+
+declare i32 @printf(i8*, ...)
+
+define i32 @testvarar() {
+ call i32 (i8*, ...)* @printf( i8* null, i32 12, i8 42 ) ; <i32>:1 [#uses=1]
+ ret i32 %1
+}
+; ModuleID = 'undefined.ll'
+@X2 = global i32 undef ; <i32*> [#uses=0]
+
+declare i32 @atoi(i8*)
+
+define i32 @test1009() {
+ ret i32 undef
+}
+
+define i32 @test1003() {
+ %X = add i32 undef, 1 ; <i32> [#uses=1]
+ ret i32 %X
+}
+; ModuleID = 'unreachable.ll'
+
+declare void @bar()
+
+define i32 @foo1021() {
+ unreachable
+}
+
+define double @xyz() {
+ call void @bar( )
+ unreachable
+}
+; ModuleID = 'varargs.ll'
+
+declare void @llvm.va_start(i8* %ap)
+
+declare void @llvm.va_copy(i8* %aq, i8* %ap)
+
+declare void @llvm.va_end(i8* %ap)
+
+define i32 @test1010(i32 %X, ...) {
+ %ap = alloca i8* ; <i8**> [#uses=4]
+ %va.upgrd.1 = bitcast i8** %ap to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_start( i8* %va.upgrd.1 )
+ %tmp = va_arg i8** %ap, i32 ; <i32> [#uses=1]
+ %aq = alloca i8* ; <i8**> [#uses=2]
+ %va0.upgrd.2 = bitcast i8** %aq to i8* ; <i8*> [#uses=1]
+ %va1.upgrd.3 = bitcast i8** %ap to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_copy( i8* %va0.upgrd.2, i8* %va1.upgrd.3 )
+ %va.upgrd.4 = bitcast i8** %aq to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_end( i8* %va.upgrd.4 )
+ %va.upgrd.5 = bitcast i8** %ap to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_end( i8* %va.upgrd.5 )
+ ret i32 %tmp
+}
+; ModuleID = 'varargs_new.ll'
+
+declare void @llvm.va_start(i8*)
+
+declare void @llvm.va_copy(i8*, i8*)
+
+declare void @llvm.va_end(i8*)
+
+define i32 @test1011(i32 %X, ...) {
+ %ap = alloca i8* ; <i8**> [#uses=4]
+ %aq = alloca i8* ; <i8**> [#uses=2]
+ %va.upgrd.1 = bitcast i8** %ap to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_start( i8* %va.upgrd.1 )
+ %tmp = va_arg i8** %ap, i32 ; <i32> [#uses=1]
+ %apv = load i8** %ap ; <i8*> [#uses=1]
+ %va0.upgrd.2 = bitcast i8** %aq to i8* ; <i8*> [#uses=1]
+ %va1.upgrd.3 = bitcast i8* %apv to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_copy( i8* %va0.upgrd.2, i8* %va1.upgrd.3 )
+ %va.upgrd.4 = bitcast i8** %aq to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_end( i8* %va.upgrd.4 )
+ %va.upgrd.5 = bitcast i8** %ap to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_end( i8* %va.upgrd.5 )
+ ret i32 %tmp
+}
+; ModuleID = 'weirdnames.ll'
+ "&^ " = type { i32 }
+@"%.*+ foo" = global "&^ " { i32 5 } ; <"&^ "*> [#uses=0]
+@"0" = global float 0.000000e+00 ; <float*> [#uses=0]
diff --git a/test/CodeGen/CellSPU/2009-01-01-BrCond.ll b/test/CodeGen/CellSPU/2009-01-01-BrCond.ll
new file mode 100644
index 0000000..58e3190
--- /dev/null
+++ b/test/CodeGen/CellSPU/2009-01-01-BrCond.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=cellspu -o - | grep brnz
+; PR3274
+
+target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:64:64-v128:128:128-a0:0:128-s0:128:128"
+target triple = "spu"
+ %struct.anon = type { i64 }
+ %struct.fp_number_type = type { i32, i32, i32, [4 x i8], %struct.anon }
+
+define double @__floatunsidf(i32 %arg_a) nounwind {
+entry:
+ %in = alloca %struct.fp_number_type, align 16
+ %0 = getelementptr %struct.fp_number_type* %in, i32 0, i32 1
+ store i32 0, i32* %0, align 4
+ %1 = icmp eq i32 %arg_a, 0
+ %2 = getelementptr %struct.fp_number_type* %in, i32 0, i32 0
+ br i1 %1, label %bb, label %bb1
+
+bb: ; preds = %entry
+ store i32 2, i32* %2, align 8
+ br label %bb7
+
+bb1: ; preds = %entry
+ ret double 0.0
+
+bb7: ; preds = %bb5, %bb1, %bb
+ ret double 1.0
+}
+
+; declare i32 @llvm.ctlz.i32(i32) nounwind readnone
+
+declare double @__pack_d(%struct.fp_number_type*)
diff --git a/test/CodeGen/CellSPU/and_ops.ll b/test/CodeGen/CellSPU/and_ops.ll
new file mode 100644
index 0000000..139e97b
--- /dev/null
+++ b/test/CodeGen/CellSPU/and_ops.ll
@@ -0,0 +1,279 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep and %t1.s | count 234
+; RUN: grep andc %t1.s | count 85
+; RUN: grep andi %t1.s | count 37
+; RUN: grep andhi %t1.s | count 30
+; RUN: grep andbi %t1.s | count 4
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; AND instruction generation:
+define <4 x i32> @and_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %A = and <4 x i32> %arg1, %arg2
+ ret <4 x i32> %A
+}
+
+define <4 x i32> @and_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %A = and <4 x i32> %arg2, %arg1
+ ret <4 x i32> %A
+}
+
+define <8 x i16> @and_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
+ %A = and <8 x i16> %arg1, %arg2
+ ret <8 x i16> %A
+}
+
+define <8 x i16> @and_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
+ %A = and <8 x i16> %arg2, %arg1
+ ret <8 x i16> %A
+}
+
+define <16 x i8> @and_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
+ %A = and <16 x i8> %arg2, %arg1
+ ret <16 x i8> %A
+}
+
+define <16 x i8> @and_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
+ %A = and <16 x i8> %arg1, %arg2
+ ret <16 x i8> %A
+}
+
+define i32 @and_i32_1(i32 %arg1, i32 %arg2) {
+ %A = and i32 %arg2, %arg1
+ ret i32 %A
+}
+
+define i32 @and_i32_2(i32 %arg1, i32 %arg2) {
+ %A = and i32 %arg1, %arg2
+ ret i32 %A
+}
+
+define i16 @and_i16_1(i16 %arg1, i16 %arg2) {
+ %A = and i16 %arg2, %arg1
+ ret i16 %A
+}
+
+define i16 @and_i16_2(i16 %arg1, i16 %arg2) {
+ %A = and i16 %arg1, %arg2
+ ret i16 %A
+}
+
+define i8 @and_i8_1(i8 %arg1, i8 %arg2) {
+ %A = and i8 %arg2, %arg1
+ ret i8 %A
+}
+
+define i8 @and_i8_2(i8 %arg1, i8 %arg2) {
+ %A = and i8 %arg1, %arg2
+ ret i8 %A
+}
+
+; ANDC instruction generation:
+define <4 x i32> @andc_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %A = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ %B = and <4 x i32> %arg1, %A
+ ret <4 x i32> %B
+}
+
+define <4 x i32> @andc_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ %B = and <4 x i32> %arg2, %A
+ ret <4 x i32> %B
+}
+
+define <4 x i32> @andc_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ %B = and <4 x i32> %A, %arg2
+ ret <4 x i32> %B
+}
+
+define <8 x i16> @andc_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
+ %A = xor <8 x i16> %arg2, < i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1, i16 -1 >
+ %B = and <8 x i16> %arg1, %A
+ ret <8 x i16> %B
+}
+
+define <8 x i16> @andc_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
+ %A = xor <8 x i16> %arg1, < i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1, i16 -1 >
+ %B = and <8 x i16> %arg2, %A
+ ret <8 x i16> %B
+}
+
+define <16 x i8> @andc_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
+ %A = xor <16 x i8> %arg1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ %B = and <16 x i8> %arg2, %A
+ ret <16 x i8> %B
+}
+
+define <16 x i8> @andc_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
+ %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ %B = and <16 x i8> %arg1, %A
+ ret <16 x i8> %B
+}
+
+define <16 x i8> @andc_v16i8_3(<16 x i8> %arg1, <16 x i8> %arg2) {
+ %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ %B = and <16 x i8> %A, %arg1
+ ret <16 x i8> %B
+}
+
+define i32 @andc_i32_1(i32 %arg1, i32 %arg2) {
+ %A = xor i32 %arg2, -1
+ %B = and i32 %A, %arg1
+ ret i32 %B
+}
+
+define i32 @andc_i32_2(i32 %arg1, i32 %arg2) {
+ %A = xor i32 %arg1, -1
+ %B = and i32 %A, %arg2
+ ret i32 %B
+}
+
+define i32 @andc_i32_3(i32 %arg1, i32 %arg2) {
+ %A = xor i32 %arg2, -1
+ %B = and i32 %arg1, %A
+ ret i32 %B
+}
+
+define i16 @andc_i16_1(i16 %arg1, i16 %arg2) {
+ %A = xor i16 %arg2, -1
+ %B = and i16 %A, %arg1
+ ret i16 %B
+}
+
+define i16 @andc_i16_2(i16 %arg1, i16 %arg2) {
+ %A = xor i16 %arg1, -1
+ %B = and i16 %A, %arg2
+ ret i16 %B
+}
+
+define i16 @andc_i16_3(i16 %arg1, i16 %arg2) {
+ %A = xor i16 %arg2, -1
+ %B = and i16 %arg1, %A
+ ret i16 %B
+}
+
+define i8 @andc_i8_1(i8 %arg1, i8 %arg2) {
+ %A = xor i8 %arg2, -1
+ %B = and i8 %A, %arg1
+ ret i8 %B
+}
+
+define i8 @andc_i8_2(i8 %arg1, i8 %arg2) {
+ %A = xor i8 %arg1, -1
+ %B = and i8 %A, %arg2
+ ret i8 %B
+}
+
+define i8 @andc_i8_3(i8 %arg1, i8 %arg2) {
+ %A = xor i8 %arg2, -1
+ %B = and i8 %arg1, %A
+ ret i8 %B
+}
+
+; ANDI instruction generation (i32 data type):
+define <4 x i32> @andi_v4i32_1(<4 x i32> %in) {
+ %tmp2 = and <4 x i32> %in, < i32 511, i32 511, i32 511, i32 511 >
+ ret <4 x i32> %tmp2
+}
+
+define <4 x i32> @andi_v4i32_2(<4 x i32> %in) {
+ %tmp2 = and <4 x i32> %in, < i32 510, i32 510, i32 510, i32 510 >
+ ret <4 x i32> %tmp2
+}
+
+define <4 x i32> @andi_v4i32_3(<4 x i32> %in) {
+ %tmp2 = and <4 x i32> %in, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ ret <4 x i32> %tmp2
+}
+
+define <4 x i32> @andi_v4i32_4(<4 x i32> %in) {
+ %tmp2 = and <4 x i32> %in, < i32 -512, i32 -512, i32 -512, i32 -512 >
+ ret <4 x i32> %tmp2
+}
+
+define i32 @andi_u32(i32 zeroext %in) zeroext {
+ %tmp37 = and i32 %in, 37
+ ret i32 %tmp37
+}
+
+define i32 @andi_i32(i32 signext %in) signext {
+ %tmp38 = and i32 %in, 37
+ ret i32 %tmp38
+}
+
+define i32 @andi_i32_1(i32 %in) {
+ %tmp37 = and i32 %in, 37
+ ret i32 %tmp37
+}
+
+; ANDHI instruction generation (i16 data type):
+define <8 x i16> @andhi_v8i16_1(<8 x i16> %in) {
+ %tmp2 = and <8 x i16> %in, < i16 511, i16 511, i16 511, i16 511,
+ i16 511, i16 511, i16 511, i16 511 >
+ ret <8 x i16> %tmp2
+}
+
+define <8 x i16> @andhi_v8i16_2(<8 x i16> %in) {
+ %tmp2 = and <8 x i16> %in, < i16 510, i16 510, i16 510, i16 510,
+ i16 510, i16 510, i16 510, i16 510 >
+ ret <8 x i16> %tmp2
+}
+
+define <8 x i16> @andhi_v8i16_3(<8 x i16> %in) {
+ %tmp2 = and <8 x i16> %in, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1 >
+ ret <8 x i16> %tmp2
+}
+
+define <8 x i16> @andhi_v8i16_4(<8 x i16> %in) {
+ %tmp2 = and <8 x i16> %in, < i16 -512, i16 -512, i16 -512, i16 -512,
+ i16 -512, i16 -512, i16 -512, i16 -512 >
+ ret <8 x i16> %tmp2
+}
+
+define i16 @andhi_u16(i16 zeroext %in) zeroext {
+ %tmp37 = and i16 %in, 37 ; <i16> [#uses=1]
+ ret i16 %tmp37
+}
+
+define i16 @andhi_i16(i16 signext %in) signext {
+ %tmp38 = and i16 %in, 37 ; <i16> [#uses=1]
+ ret i16 %tmp38
+}
+
+; i8 data type (s/b ANDBI if 8-bit registers were supported):
+define <16 x i8> @and_v16i8(<16 x i8> %in) {
+ ; ANDBI generated for vector types
+ %tmp2 = and <16 x i8> %in, < i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
+ i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
+ i8 42, i8 42, i8 42, i8 42 >
+ ret <16 x i8> %tmp2
+}
+
+define i8 @and_u8(i8 zeroext %in) zeroext {
+ ; ANDBI generated:
+ %tmp37 = and i8 %in, 37
+ ret i8 %tmp37
+}
+
+define i8 @and_sext8(i8 signext %in) signext {
+ ; ANDBI generated
+ %tmp38 = and i8 %in, 37
+ ret i8 %tmp38
+}
+
+define i8 @and_i8(i8 %in) {
+ ; ANDBI generated
+ %tmp38 = and i8 %in, 205
+ ret i8 %tmp38
+}
diff --git a/test/CodeGen/CellSPU/call.ll b/test/CodeGen/CellSPU/call.ll
new file mode 100644
index 0000000..960d2fe
--- /dev/null
+++ b/test/CodeGen/CellSPU/call.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep brsl %t1.s | count 1
+; RUN: grep brasl %t1.s | count 1
+; RUN: grep stqd %t1.s | count 80
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define i32 @main() {
+entry:
+ %a = call i32 @stub_1(i32 1, float 0x400921FA00000000)
+ call void @extern_stub_1(i32 %a, i32 4)
+ ret i32 %a
+}
+
+declare void @extern_stub_1(i32, i32)
+
+define i32 @stub_1(i32 %x, float %y) {
+entry:
+ ret i32 0
+}
+
+; vararg call: ensure that all caller-saved registers are spilled to the
+; stack:
+define i32 @stub_2(...) {
+entry:
+ ret i32 0
+}
diff --git a/test/CodeGen/CellSPU/call_indirect.ll b/test/CodeGen/CellSPU/call_indirect.ll
new file mode 100644
index 0000000..08dad74
--- /dev/null
+++ b/test/CodeGen/CellSPU/call_indirect.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=cellspu -asm-verbose=0 > %t1.s
+; RUN: llc < %s -march=cellspu -mattr=large_mem -asm-verbose=0 > %t2.s
+; RUN: grep bisl %t1.s | count 7
+; RUN: grep ila %t1.s | count 1
+; RUN: grep rotqby %t1.s | count 5
+; RUN: grep lqa %t1.s | count 1
+; RUN: grep lqd %t1.s | count 12
+; RUN: grep dispatch_tab %t1.s | count 5
+; RUN: grep bisl %t2.s | count 7
+; RUN: grep ilhu %t2.s | count 2
+; RUN: grep iohl %t2.s | count 2
+; RUN: grep rotqby %t2.s | count 5
+; RUN: grep lqd %t2.s | count 13
+; RUN: grep ilhu %t2.s | count 2
+; RUN: grep ai %t2.s | count 8
+; RUN: grep dispatch_tab %t2.s | count 6
+
+; ModuleID = 'call_indirect.bc'
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
+target triple = "spu-unknown-elf"
+
+@dispatch_tab = global [6 x void (i32, float)*] zeroinitializer, align 16
+
+define void @dispatcher(i32 %i_arg, float %f_arg) {
+entry:
+ %tmp2 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 0), align 16
+ tail call void %tmp2( i32 %i_arg, float %f_arg )
+ %tmp2.1 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 1), align 4
+ tail call void %tmp2.1( i32 %i_arg, float %f_arg )
+ %tmp2.2 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 2), align 4
+ tail call void %tmp2.2( i32 %i_arg, float %f_arg )
+ %tmp2.3 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 3), align 4
+ tail call void %tmp2.3( i32 %i_arg, float %f_arg )
+ %tmp2.4 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 4), align 4
+ tail call void %tmp2.4( i32 %i_arg, float %f_arg )
+ %tmp2.5 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 5), align 4
+ tail call void %tmp2.5( i32 %i_arg, float %f_arg )
+ ret void
+}
+
+@ptr_list = internal global [1 x void ()*] [ void ()* inttoptr (i64 4294967295 to void ()*) ], align 4
[email protected] = internal global void ()** getelementptr ([1 x void ()*]* @ptr_list, i32 0, i32 1), align 16
+
+define void @double_indirect_call() {
+ %a = load void ()*** @ptr.a, align 16
+ %b = load void ()** %a, align 4
+ tail call void %b()
+ ret void
+}
diff --git a/test/CodeGen/CellSPU/ctpop.ll b/test/CodeGen/CellSPU/ctpop.ll
new file mode 100644
index 0000000..e1a6cd8
--- /dev/null
+++ b/test/CodeGen/CellSPU/ctpop.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep cntb %t1.s | count 3
+; RUN: grep andi %t1.s | count 3
+; RUN: grep rotmi %t1.s | count 2
+; RUN: grep rothmi %t1.s | count 1
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+declare i8 @llvm.ctpop.i8(i8)
+declare i16 @llvm.ctpop.i16(i16)
+declare i32 @llvm.ctpop.i32(i32)
+
+define i32 @test_i8(i8 %X) {
+ call i8 @llvm.ctpop.i8(i8 %X)
+ %Y = zext i8 %1 to i32
+ ret i32 %Y
+}
+
+define i32 @test_i16(i16 %X) {
+ call i16 @llvm.ctpop.i16(i16 %X)
+ %Y = zext i16 %1 to i32
+ ret i32 %Y
+}
+
+define i32 @test_i32(i32 %X) {
+ call i32 @llvm.ctpop.i32(i32 %X)
+ %Y = bitcast i32 %1 to i32
+ ret i32 %Y
+}
+
diff --git a/test/CodeGen/CellSPU/dg.exp b/test/CodeGen/CellSPU/dg.exp
new file mode 100644
index 0000000..d416479
--- /dev/null
+++ b/test/CodeGen/CellSPU/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target CellSPU] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/CellSPU/dp_farith.ll b/test/CodeGen/CellSPU/dp_farith.ll
new file mode 100644
index 0000000..66bff3eb
--- /dev/null
+++ b/test/CodeGen/CellSPU/dp_farith.ll
@@ -0,0 +1,102 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep dfa %t1.s | count 2
+; RUN: grep dfs %t1.s | count 2
+; RUN: grep dfm %t1.s | count 6
+; RUN: grep dfma %t1.s | count 2
+; RUN: grep dfms %t1.s | count 2
+; RUN: grep dfnms %t1.s | count 4
+;
+; This file includes double precision floating point arithmetic instructions
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define double @fadd(double %arg1, double %arg2) {
+ %A = fadd double %arg1, %arg2
+ ret double %A
+}
+
+define <2 x double> @fadd_vec(<2 x double> %arg1, <2 x double> %arg2) {
+ %A = fadd <2 x double> %arg1, %arg2
+ ret <2 x double> %A
+}
+
+define double @fsub(double %arg1, double %arg2) {
+ %A = fsub double %arg1, %arg2
+ ret double %A
+}
+
+define <2 x double> @fsub_vec(<2 x double> %arg1, <2 x double> %arg2) {
+ %A = fsub <2 x double> %arg1, %arg2
+ ret <2 x double> %A
+}
+
+define double @fmul(double %arg1, double %arg2) {
+ %A = fmul double %arg1, %arg2
+ ret double %A
+}
+
+define <2 x double> @fmul_vec(<2 x double> %arg1, <2 x double> %arg2) {
+ %A = fmul <2 x double> %arg1, %arg2
+ ret <2 x double> %A
+}
+
+define double @fma(double %arg1, double %arg2, double %arg3) {
+ %A = fmul double %arg1, %arg2
+ %B = fadd double %A, %arg3
+ ret double %B
+}
+
+define <2 x double> @fma_vec(<2 x double> %arg1, <2 x double> %arg2, <2 x double> %arg3) {
+ %A = fmul <2 x double> %arg1, %arg2
+ %B = fadd <2 x double> %A, %arg3
+ ret <2 x double> %B
+}
+
+define double @fms(double %arg1, double %arg2, double %arg3) {
+ %A = fmul double %arg1, %arg2
+ %B = fsub double %A, %arg3
+ ret double %B
+}
+
+define <2 x double> @fms_vec(<2 x double> %arg1, <2 x double> %arg2, <2 x double> %arg3) {
+ %A = fmul <2 x double> %arg1, %arg2
+ %B = fsub <2 x double> %A, %arg3
+ ret <2 x double> %B
+}
+
+; - (a * b - c)
+define double @d_fnms_1(double %arg1, double %arg2, double %arg3) {
+ %A = fmul double %arg1, %arg2
+ %B = fsub double %A, %arg3
+ %C = fsub double -0.000000e+00, %B ; <double> [#uses=1]
+ ret double %C
+}
+
+; Annother way of getting fnms
+; - ( a * b ) + c => c - (a * b)
+define double @d_fnms_2(double %arg1, double %arg2, double %arg3) {
+ %A = fmul double %arg1, %arg2
+ %B = fsub double %arg3, %A
+ ret double %B
+}
+
+; FNMS: - (a * b - c) => c - (a * b)
+define <2 x double> @d_fnms_vec_1(<2 x double> %arg1, <2 x double> %arg2, <2 x double> %arg3) {
+ %A = fmul <2 x double> %arg1, %arg2
+ %B = fsub <2 x double> %arg3, %A
+ ret <2 x double> %B
+}
+
+; Another way to get fnms using a constant vector
+; - ( a * b - c)
+define <2 x double> @d_fnms_vec_2(<2 x double> %arg1, <2 x double> %arg2, <2 x double> %arg3) {
+ %A = fmul <2 x double> %arg1, %arg2 ; <<2 x double>> [#uses=1]
+ %B = fsub <2 x double> %A, %arg3 ; <<2 x double>> [#uses=1]
+ %C = fsub <2 x double> < double -0.00000e+00, double -0.00000e+00 >, %B
+ ret <2 x double> %C
+}
+
+;define double @fdiv_1(double %arg1, double %arg2) {
+; %A = fdiv double %arg1, %arg2 ; <double> [#uses=1]
+; ret double %A
+;}
diff --git a/test/CodeGen/CellSPU/eqv.ll b/test/CodeGen/CellSPU/eqv.ll
new file mode 100644
index 0000000..22c8c3b
--- /dev/null
+++ b/test/CodeGen/CellSPU/eqv.ll
@@ -0,0 +1,152 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep eqv %t1.s | count 18
+; RUN: grep xshw %t1.s | count 6
+; RUN: grep xsbh %t1.s | count 3
+; RUN: grep andi %t1.s | count 3
+
+; Test the 'eqv' instruction, whose boolean expression is:
+; (a & b) | (~a & ~b), which simplifies to
+; (a & b) | ~(a | b)
+; Alternatively, a ^ ~b, which the compiler will also match.
+
+; ModuleID = 'eqv.bc'
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define <4 x i32> @equiv_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %A = and <4 x i32> %arg1, %arg2
+ %B = or <4 x i32> %arg1, %arg2
+ %Bnot = xor <4 x i32> %B, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ %C = or <4 x i32> %A, %Bnot
+ ret <4 x i32> %C
+}
+
+define <4 x i32> @equiv_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %B = or <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1]
+ %Bnot = xor <4 x i32> %B, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %A = and <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1]
+ %C = or <4 x i32> %A, %Bnot ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %C
+}
+
+define <4 x i32> @equiv_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %B = or <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1]
+ %A = and <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1]
+ %Bnot = xor <4 x i32> %B, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %C = or <4 x i32> %A, %Bnot ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %C
+}
+
+define <4 x i32> @equiv_v4i32_4(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %arg2not = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ %C = xor <4 x i32> %arg1, %arg2not
+ ret <4 x i32> %C
+}
+
+define i32 @equiv_i32_1(i32 %arg1, i32 %arg2) {
+ %A = and i32 %arg1, %arg2 ; <i32> [#uses=1]
+ %B = or i32 %arg1, %arg2 ; <i32> [#uses=1]
+ %Bnot = xor i32 %B, -1 ; <i32> [#uses=1]
+ %C = or i32 %A, %Bnot ; <i32> [#uses=1]
+ ret i32 %C
+}
+
+define i32 @equiv_i32_2(i32 %arg1, i32 %arg2) {
+ %B = or i32 %arg1, %arg2 ; <i32> [#uses=1]
+ %Bnot = xor i32 %B, -1 ; <i32> [#uses=1]
+ %A = and i32 %arg1, %arg2 ; <i32> [#uses=1]
+ %C = or i32 %A, %Bnot ; <i32> [#uses=1]
+ ret i32 %C
+}
+
+define i32 @equiv_i32_3(i32 %arg1, i32 %arg2) {
+ %B = or i32 %arg1, %arg2 ; <i32> [#uses=1]
+ %A = and i32 %arg1, %arg2 ; <i32> [#uses=1]
+ %Bnot = xor i32 %B, -1 ; <i32> [#uses=1]
+ %C = or i32 %A, %Bnot ; <i32> [#uses=1]
+ ret i32 %C
+}
+
+define i32 @equiv_i32_4(i32 %arg1, i32 %arg2) {
+ %arg2not = xor i32 %arg2, -1
+ %C = xor i32 %arg1, %arg2not
+ ret i32 %C
+}
+
+define i32 @equiv_i32_5(i32 %arg1, i32 %arg2) {
+ %arg1not = xor i32 %arg1, -1
+ %C = xor i32 %arg2, %arg1not
+ ret i32 %C
+}
+
+define i16 @equiv_i16_1(i16 signext %arg1, i16 signext %arg2) signext {
+ %A = and i16 %arg1, %arg2 ; <i16> [#uses=1]
+ %B = or i16 %arg1, %arg2 ; <i16> [#uses=1]
+ %Bnot = xor i16 %B, -1 ; <i16> [#uses=1]
+ %C = or i16 %A, %Bnot ; <i16> [#uses=1]
+ ret i16 %C
+}
+
+define i16 @equiv_i16_2(i16 signext %arg1, i16 signext %arg2) signext {
+ %B = or i16 %arg1, %arg2 ; <i16> [#uses=1]
+ %Bnot = xor i16 %B, -1 ; <i16> [#uses=1]
+ %A = and i16 %arg1, %arg2 ; <i16> [#uses=1]
+ %C = or i16 %A, %Bnot ; <i16> [#uses=1]
+ ret i16 %C
+}
+
+define i16 @equiv_i16_3(i16 signext %arg1, i16 signext %arg2) signext {
+ %B = or i16 %arg1, %arg2 ; <i16> [#uses=1]
+ %A = and i16 %arg1, %arg2 ; <i16> [#uses=1]
+ %Bnot = xor i16 %B, -1 ; <i16> [#uses=1]
+ %C = or i16 %A, %Bnot ; <i16> [#uses=1]
+ ret i16 %C
+}
+
+define i8 @equiv_i8_1(i8 signext %arg1, i8 signext %arg2) signext {
+ %A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %B = or i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %Bnot = xor i8 %B, -1 ; <i8> [#uses=1]
+ %C = or i8 %A, %Bnot ; <i8> [#uses=1]
+ ret i8 %C
+}
+
+define i8 @equiv_i8_2(i8 signext %arg1, i8 signext %arg2) signext {
+ %B = or i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %Bnot = xor i8 %B, -1 ; <i8> [#uses=1]
+ %A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %C = or i8 %A, %Bnot ; <i8> [#uses=1]
+ ret i8 %C
+}
+
+define i8 @equiv_i8_3(i8 signext %arg1, i8 signext %arg2) signext {
+ %B = or i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %Bnot = xor i8 %B, -1 ; <i8> [#uses=1]
+ %C = or i8 %A, %Bnot ; <i8> [#uses=1]
+ ret i8 %C
+}
+
+define i8 @equiv_u8_1(i8 zeroext %arg1, i8 zeroext %arg2) zeroext {
+ %A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %B = or i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %Bnot = xor i8 %B, -1 ; <i8> [#uses=1]
+ %C = or i8 %A, %Bnot ; <i8> [#uses=1]
+ ret i8 %C
+}
+
+define i8 @equiv_u8_2(i8 zeroext %arg1, i8 zeroext %arg2) zeroext {
+ %B = or i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %Bnot = xor i8 %B, -1 ; <i8> [#uses=1]
+ %A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %C = or i8 %A, %Bnot ; <i8> [#uses=1]
+ ret i8 %C
+}
+
+define i8 @equiv_u8_3(i8 zeroext %arg1, i8 zeroext %arg2) zeroext {
+ %B = or i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %Bnot = xor i8 %B, -1 ; <i8> [#uses=1]
+ %C = or i8 %A, %Bnot ; <i8> [#uses=1]
+ ret i8 %C
+}
diff --git a/test/CodeGen/CellSPU/extract_elt.ll b/test/CodeGen/CellSPU/extract_elt.ll
new file mode 100644
index 0000000..0ac971c
--- /dev/null
+++ b/test/CodeGen/CellSPU/extract_elt.ll
@@ -0,0 +1,277 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep shufb %t1.s | count 39
+; RUN: grep ilhu %t1.s | count 27
+; RUN: grep iohl %t1.s | count 27
+; RUN: grep lqa %t1.s | count 10
+; RUN: grep shlqby %t1.s | count 12
+; RUN: grep 515 %t1.s | count 1
+; RUN: grep 1029 %t1.s | count 2
+; RUN: grep 1543 %t1.s | count 2
+; RUN: grep 2057 %t1.s | count 2
+; RUN: grep 2571 %t1.s | count 2
+; RUN: grep 3085 %t1.s | count 2
+; RUN: grep 3599 %t1.s | count 2
+; RUN: grep 32768 %t1.s | count 1
+; RUN: grep 32769 %t1.s | count 1
+; RUN: grep 32770 %t1.s | count 1
+; RUN: grep 32771 %t1.s | count 1
+; RUN: grep 32772 %t1.s | count 1
+; RUN: grep 32773 %t1.s | count 1
+; RUN: grep 32774 %t1.s | count 1
+; RUN: grep 32775 %t1.s | count 1
+; RUN: grep 32776 %t1.s | count 1
+; RUN: grep 32777 %t1.s | count 1
+; RUN: grep 32778 %t1.s | count 1
+; RUN: grep 32779 %t1.s | count 1
+; RUN: grep 32780 %t1.s | count 1
+; RUN: grep 32781 %t1.s | count 1
+; RUN: grep 32782 %t1.s | count 1
+; RUN: grep 32783 %t1.s | count 1
+; RUN: grep 32896 %t1.s | count 24
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define i32 @i32_extract_0(<4 x i32> %v) {
+entry:
+ %a = extractelement <4 x i32> %v, i32 0
+ ret i32 %a
+}
+
+define i32 @i32_extract_1(<4 x i32> %v) {
+entry:
+ %a = extractelement <4 x i32> %v, i32 1
+ ret i32 %a
+}
+
+define i32 @i32_extract_2(<4 x i32> %v) {
+entry:
+ %a = extractelement <4 x i32> %v, i32 2
+ ret i32 %a
+}
+
+define i32 @i32_extract_3(<4 x i32> %v) {
+entry:
+ %a = extractelement <4 x i32> %v, i32 3
+ ret i32 %a
+}
+
+define i16 @i16_extract_0(<8 x i16> %v) {
+entry:
+ %a = extractelement <8 x i16> %v, i32 0
+ ret i16 %a
+}
+
+define i16 @i16_extract_1(<8 x i16> %v) {
+entry:
+ %a = extractelement <8 x i16> %v, i32 1
+ ret i16 %a
+}
+
+define i16 @i16_extract_2(<8 x i16> %v) {
+entry:
+ %a = extractelement <8 x i16> %v, i32 2
+ ret i16 %a
+}
+
+define i16 @i16_extract_3(<8 x i16> %v) {
+entry:
+ %a = extractelement <8 x i16> %v, i32 3
+ ret i16 %a
+}
+
+define i16 @i16_extract_4(<8 x i16> %v) {
+entry:
+ %a = extractelement <8 x i16> %v, i32 4
+ ret i16 %a
+}
+
+define i16 @i16_extract_5(<8 x i16> %v) {
+entry:
+ %a = extractelement <8 x i16> %v, i32 5
+ ret i16 %a
+}
+
+define i16 @i16_extract_6(<8 x i16> %v) {
+entry:
+ %a = extractelement <8 x i16> %v, i32 6
+ ret i16 %a
+}
+
+define i16 @i16_extract_7(<8 x i16> %v) {
+entry:
+ %a = extractelement <8 x i16> %v, i32 7
+ ret i16 %a
+}
+
+define i8 @i8_extract_0(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 0
+ ret i8 %a
+}
+
+define i8 @i8_extract_1(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 1
+ ret i8 %a
+}
+
+define i8 @i8_extract_2(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 2
+ ret i8 %a
+}
+
+define i8 @i8_extract_3(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 3
+ ret i8 %a
+}
+
+define i8 @i8_extract_4(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 4
+ ret i8 %a
+}
+
+define i8 @i8_extract_5(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 5
+ ret i8 %a
+}
+
+define i8 @i8_extract_6(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 6
+ ret i8 %a
+}
+
+define i8 @i8_extract_7(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 7
+ ret i8 %a
+}
+
+define i8 @i8_extract_8(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 8
+ ret i8 %a
+}
+
+define i8 @i8_extract_9(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 9
+ ret i8 %a
+}
+
+define i8 @i8_extract_10(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 10
+ ret i8 %a
+}
+
+define i8 @i8_extract_11(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 11
+ ret i8 %a
+}
+
+define i8 @i8_extract_12(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 12
+ ret i8 %a
+}
+
+define i8 @i8_extract_13(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 13
+ ret i8 %a
+}
+
+define i8 @i8_extract_14(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 14
+ ret i8 %a
+}
+
+define i8 @i8_extract_15(<16 x i8> %v) {
+entry:
+ %a = extractelement <16 x i8> %v, i32 15
+ ret i8 %a
+}
+
+;;--------------------------------------------------------------------------
+;; extract element, variable index:
+;;--------------------------------------------------------------------------
+
+define i8 @extract_varadic_i8(i32 %i) nounwind readnone {
+entry:
+ %0 = extractelement <16 x i8> < i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, i32 %i
+ ret i8 %0
+}
+
+define i8 @extract_varadic_i8_1(<16 x i8> %v, i32 %i) nounwind readnone {
+entry:
+ %0 = extractelement <16 x i8> %v, i32 %i
+ ret i8 %0
+}
+
+define i16 @extract_varadic_i16(i32 %i) nounwind readnone {
+entry:
+ %0 = extractelement <8 x i16> < i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, i32 %i
+ ret i16 %0
+}
+
+define i16 @extract_varadic_i16_1(<8 x i16> %v, i32 %i) nounwind readnone {
+entry:
+ %0 = extractelement <8 x i16> %v, i32 %i
+ ret i16 %0
+}
+
+define i32 @extract_varadic_i32(i32 %i) nounwind readnone {
+entry:
+ %0 = extractelement <4 x i32> < i32 0, i32 1, i32 2, i32 3>, i32 %i
+ ret i32 %0
+}
+
+define i32 @extract_varadic_i32_1(<4 x i32> %v, i32 %i) nounwind readnone {
+entry:
+ %0 = extractelement <4 x i32> %v, i32 %i
+ ret i32 %0
+}
+
+define float @extract_varadic_f32(i32 %i) nounwind readnone {
+entry:
+ %0 = extractelement <4 x float> < float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00 >, i32 %i
+ ret float %0
+}
+
+define float @extract_varadic_f32_1(<4 x float> %v, i32 %i) nounwind readnone {
+entry:
+ %0 = extractelement <4 x float> %v, i32 %i
+ ret float %0
+}
+
+define i64 @extract_varadic_i64(i32 %i) nounwind readnone {
+entry:
+ %0 = extractelement <2 x i64> < i64 0, i64 1>, i32 %i
+ ret i64 %0
+}
+
+define i64 @extract_varadic_i64_1(<2 x i64> %v, i32 %i) nounwind readnone {
+entry:
+ %0 = extractelement <2 x i64> %v, i32 %i
+ ret i64 %0
+}
+
+define double @extract_varadic_f64(i32 %i) nounwind readnone {
+entry:
+ %0 = extractelement <2 x double> < double 1.000000e+00, double 2.000000e+00>, i32 %i
+ ret double %0
+}
+
+define double @extract_varadic_f64_1(<2 x double> %v, i32 %i) nounwind readnone {
+entry:
+ %0 = extractelement <2 x double> %v, i32 %i
+ ret double %0
+}
diff --git a/test/CodeGen/CellSPU/fcmp32.ll b/test/CodeGen/CellSPU/fcmp32.ll
new file mode 100644
index 0000000..f07fe6f
--- /dev/null
+++ b/test/CodeGen/CellSPU/fcmp32.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep fceq %t1.s | count 1
+; RUN: grep fcmeq %t1.s | count 1
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; Exercise the floating point comparison operators for f32:
+
+declare double @fabs(double)
+declare float @fabsf(float)
+
+define i1 @fcmp_eq(float %arg1, float %arg2) {
+ %A = fcmp oeq float %arg1, %arg2
+ ret i1 %A
+}
+
+define i1 @fcmp_mag_eq(float %arg1, float %arg2) {
+ %1 = call float @fabsf(float %arg1)
+ %2 = call float @fabsf(float %arg2)
+ %3 = fcmp oeq float %1, %2
+ ret i1 %3
+}
diff --git a/test/CodeGen/CellSPU/fcmp64.ll b/test/CodeGen/CellSPU/fcmp64.ll
new file mode 100644
index 0000000..2b61fa6
--- /dev/null
+++ b/test/CodeGen/CellSPU/fcmp64.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+
+define i1 @fcmp_eq_setcc_f64(double %arg1, double %arg2) nounwind {
+entry:
+ %A = fcmp oeq double %arg1, %arg2
+ ret i1 %A
+}
diff --git a/test/CodeGen/CellSPU/fdiv.ll b/test/CodeGen/CellSPU/fdiv.ll
new file mode 100644
index 0000000..9921626
--- /dev/null
+++ b/test/CodeGen/CellSPU/fdiv.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep frest %t1.s | count 2
+; RUN: grep -w fi %t1.s | count 2
+; RUN: grep -w fm %t1.s | count 2
+; RUN: grep fma %t1.s | count 2
+; RUN: grep fnms %t1.s | count 4
+; RUN: grep cgti %t1.s | count 2
+; RUN: grep selb %t1.s | count 2
+;
+; This file includes standard floating point arithmetic instructions
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define float @fdiv32(float %arg1, float %arg2) {
+ %A = fdiv float %arg1, %arg2
+ ret float %A
+}
+
+define <4 x float> @fdiv_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
+ %A = fdiv <4 x float> %arg1, %arg2
+ ret <4 x float> %A
+}
diff --git a/test/CodeGen/CellSPU/fneg-fabs.ll b/test/CodeGen/CellSPU/fneg-fabs.ll
new file mode 100644
index 0000000..1e5e3b3
--- /dev/null
+++ b/test/CodeGen/CellSPU/fneg-fabs.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep 32768 %t1.s | count 2
+; RUN: grep xor %t1.s | count 4
+; RUN: grep and %t1.s | count 2
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define double @fneg_dp(double %X) {
+ %Y = fsub double -0.000000e+00, %X
+ ret double %Y
+}
+
+define <2 x double> @fneg_dp_vec(<2 x double> %X) {
+ %Y = fsub <2 x double> < double -0.0000e+00, double -0.0000e+00 >, %X
+ ret <2 x double> %Y
+}
+
+define float @fneg_sp(float %X) {
+ %Y = fsub float -0.000000e+00, %X
+ ret float %Y
+}
+
+define <4 x float> @fneg_sp_vec(<4 x float> %X) {
+ %Y = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00,
+ float -0.000000e+00, float -0.000000e+00>, %X
+ ret <4 x float> %Y
+}
+
+declare double @fabs(double)
+
+declare float @fabsf(float)
+
+define double @fabs_dp(double %X) {
+ %Y = call double @fabs( double %X )
+ ret double %Y
+}
+
+define float @fabs_sp(float %X) {
+ %Y = call float @fabsf( float %X )
+ ret float %Y
+}
diff --git a/test/CodeGen/CellSPU/i64ops.ll b/test/CodeGen/CellSPU/i64ops.ll
new file mode 100644
index 0000000..3553cbb
--- /dev/null
+++ b/test/CodeGen/CellSPU/i64ops.ll
@@ -0,0 +1,57 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep xswd %t1.s | count 3
+; RUN: grep xsbh %t1.s | count 1
+; RUN: grep xshw %t1.s | count 2
+; RUN: grep shufb %t1.s | count 7
+; RUN: grep cg %t1.s | count 4
+; RUN: grep addx %t1.s | count 4
+; RUN: grep fsmbi %t1.s | count 3
+; RUN: grep il %t1.s | count 2
+; RUN: grep mpy %t1.s | count 10
+; RUN: grep mpyh %t1.s | count 6
+; RUN: grep mpyhhu %t1.s | count 2
+; RUN: grep mpyu %t1.s | count 4
+
+; ModuleID = 'stores.bc'
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define i64 @sext_i64_i8(i8 %a) nounwind {
+ %1 = sext i8 %a to i64
+ ret i64 %1
+}
+
+define i64 @sext_i64_i16(i16 %a) nounwind {
+ %1 = sext i16 %a to i64
+ ret i64 %1
+}
+
+define i64 @sext_i64_i32(i32 %a) nounwind {
+ %1 = sext i32 %a to i64
+ ret i64 %1
+}
+
+define i64 @zext_i64_i8(i8 %a) nounwind {
+ %1 = zext i8 %a to i64
+ ret i64 %1
+}
+
+define i64 @zext_i64_i16(i16 %a) nounwind {
+ %1 = zext i16 %a to i64
+ ret i64 %1
+}
+
+define i64 @zext_i64_i32(i32 %a) nounwind {
+ %1 = zext i32 %a to i64
+ ret i64 %1
+}
+
+define i64 @add_i64(i64 %a, i64 %b) nounwind {
+ %1 = add i64 %a, %b
+ ret i64 %1
+}
+
+define i64 @mul_i64(i64 %a, i64 %b) nounwind {
+ %1 = mul i64 %a, %b
+ ret i64 %1
+}
diff --git a/test/CodeGen/CellSPU/i8ops.ll b/test/CodeGen/CellSPU/i8ops.ll
new file mode 100644
index 0000000..57a2aa8
--- /dev/null
+++ b/test/CodeGen/CellSPU/i8ops.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+
+; ModuleID = 'i8ops.bc'
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define i8 @add_i8(i8 %a, i8 %b) nounwind {
+ %1 = add i8 %a, %b
+ ret i8 %1
+}
+
+define i8 @add_i8_imm(i8 %a, i8 %b) nounwind {
+ %1 = add i8 %a, 15
+ ret i8 %1
+}
+
+define i8 @sub_i8(i8 %a, i8 %b) nounwind {
+ %1 = sub i8 %a, %b
+ ret i8 %1
+}
+
+define i8 @sub_i8_imm(i8 %a, i8 %b) nounwind {
+ %1 = sub i8 %a, 15
+ ret i8 %1
+}
diff --git a/test/CodeGen/CellSPU/icmp16.ll b/test/CodeGen/CellSPU/icmp16.ll
new file mode 100644
index 0000000..32b1261
--- /dev/null
+++ b/test/CodeGen/CellSPU/icmp16.ll
@@ -0,0 +1,350 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep ilh %t1.s | count 15
+; RUN: grep ceqh %t1.s | count 29
+; RUN: grep ceqhi %t1.s | count 13
+; RUN: grep clgth %t1.s | count 15
+; RUN: grep cgth %t1.s | count 14
+; RUN: grep cgthi %t1.s | count 6
+; RUN: grep {selb\t\\\$3, \\\$6, \\\$5, \\\$3} %t1.s | count 7
+; RUN: grep {selb\t\\\$3, \\\$5, \\\$6, \\\$3} %t1.s | count 3
+; RUN: grep {selb\t\\\$3, \\\$5, \\\$4, \\\$3} %t1.s | count 17
+; RUN: grep {selb\t\\\$3, \\\$4, \\\$5, \\\$3} %t1.s | count 6
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
+; $3 = %arg1, $4 = %val1, $5 = %val2
+;
+; For "positive" comparisons:
+; selb $3, $6, $5, <i1>
+; selb $3, $5, $4, <i1>
+;
+; For "negative" comparisons, i.e., those where the result of the comparison
+; must be inverted (setne, for example):
+; selb $3, $5, $6, <i1>
+; selb $3, $4, $5, <i1>
+
+; i16 integer comparisons:
+define i16 @icmp_eq_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp eq i16 %arg1, %arg2
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i1 @icmp_eq_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp eq i16 %arg1, %arg2
+ ret i1 %A
+}
+
+define i16 @icmp_eq_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp eq i16 %arg1, 511
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_eq_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp eq i16 %arg1, -512
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_eq_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp eq i16 %arg1, -1
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_eq_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp eq i16 %arg1, 32768
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_ne_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ne i16 %arg1, %arg2
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i1 @icmp_ne_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ne i16 %arg1, %arg2
+ ret i1 %A
+}
+
+define i16 @icmp_ne_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ne i16 %arg1, 511
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_ne_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ne i16 %arg1, -512
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_ne_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ne i16 %arg1, -1
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_ne_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ne i16 %arg1, 32768
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_ugt_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ugt i16 %arg1, %arg2
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i1 @icmp_ugt_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ugt i16 %arg1, %arg2
+ ret i1 %A
+}
+
+define i16 @icmp_ugt_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ugt i16 %arg1, 500
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_ugt_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ugt i16 %arg1, 0
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_ugt_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ugt i16 %arg1, 65024
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_ugt_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ugt i16 %arg1, 32768
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_uge_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp uge i16 %arg1, %arg2
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i1 @icmp_uge_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp uge i16 %arg1, %arg2
+ ret i1 %A
+}
+
+;; Note: icmp uge i16 %arg1, <immed> can always be transformed into
+;; icmp ugt i16 %arg1, <immed>-1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i16 @icmp_ult_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ult i16 %arg1, %arg2
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i1 @icmp_ult_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ult i16 %arg1, %arg2
+ ret i1 %A
+}
+
+define i16 @icmp_ult_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ult i16 %arg1, 511
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_ult_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ult i16 %arg1, 65534
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_ult_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ult i16 %arg1, 65024
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_ult_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ult i16 %arg1, 32769
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_ule_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ule i16 %arg1, %arg2
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i1 @icmp_ule_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp ule i16 %arg1, %arg2
+ ret i1 %A
+}
+
+;; Note: icmp ule i16 %arg1, <immed> can always be transformed into
+;; icmp ult i16 %arg1, <immed>+1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i16 @icmp_sgt_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp sgt i16 %arg1, %arg2
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i1 @icmp_sgt_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp sgt i16 %arg1, %arg2
+ ret i1 %A
+}
+
+define i16 @icmp_sgt_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp sgt i16 %arg1, 511
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_sgt_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp sgt i16 %arg1, -1
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_sgt_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp sgt i16 %arg1, -512
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_sgt_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp sgt i16 %arg1, 32768
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_sge_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp sge i16 %arg1, %arg2
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i1 @icmp_sge_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp sge i16 %arg1, %arg2
+ ret i1 %A
+}
+
+;; Note: icmp sge i16 %arg1, <immed> can always be transformed into
+;; icmp sgt i16 %arg1, <immed>-1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i16 @icmp_slt_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp slt i16 %arg1, %arg2
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i1 @icmp_slt_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp slt i16 %arg1, %arg2
+ ret i1 %A
+}
+
+define i16 @icmp_slt_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp slt i16 %arg1, 511
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_slt_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp slt i16 %arg1, -512
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_slt_immed03_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp slt i16 %arg1, -1
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_slt_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp slt i16 %arg1, 32768
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i16 @icmp_sle_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp sle i16 %arg1, %arg2
+ %B = select i1 %A, i16 %val1, i16 %val2
+ ret i16 %B
+}
+
+define i1 @icmp_sle_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
+entry:
+ %A = icmp sle i16 %arg1, %arg2
+ ret i1 %A
+}
+
+;; Note: icmp sle i16 %arg1, <immed> can always be transformed into
+;; icmp slt i16 %arg1, <immed>+1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
diff --git a/test/CodeGen/CellSPU/icmp32.ll b/test/CodeGen/CellSPU/icmp32.ll
new file mode 100644
index 0000000..ccbb5f7
--- /dev/null
+++ b/test/CodeGen/CellSPU/icmp32.ll
@@ -0,0 +1,350 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep ila %t1.s | count 6
+; RUN: grep ceq %t1.s | count 28
+; RUN: grep ceqi %t1.s | count 12
+; RUN: grep clgt %t1.s | count 16
+; RUN: grep clgti %t1.s | count 6
+; RUN: grep cgt %t1.s | count 16
+; RUN: grep cgti %t1.s | count 6
+; RUN: grep {selb\t\\\$3, \\\$6, \\\$5, \\\$3} %t1.s | count 7
+; RUN: grep {selb\t\\\$3, \\\$5, \\\$6, \\\$3} %t1.s | count 3
+; RUN: grep {selb\t\\\$3, \\\$5, \\\$4, \\\$3} %t1.s | count 20
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
+; $3 = %arg1, $4 = %val1, $5 = %val2
+;
+; For "positive" comparisons:
+; selb $3, $6, $5, <i1>
+; selb $3, $5, $4, <i1>
+;
+; For "negative" comparisons, i.e., those where the result of the comparison
+; must be inverted (setne, for example):
+; selb $3, $5, $6, <i1>
+; selb $3, $4, $5, <i1>
+
+; i32 integer comparisons:
+define i32 @icmp_eq_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp eq i32 %arg1, %arg2
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i1 @icmp_eq_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp eq i32 %arg1, %arg2
+ ret i1 %A
+}
+
+define i32 @icmp_eq_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp eq i32 %arg1, 511
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_eq_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp eq i32 %arg1, -512
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_eq_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp eq i32 %arg1, -1
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_eq_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp eq i32 %arg1, 32768
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_ne_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ne i32 %arg1, %arg2
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i1 @icmp_ne_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ne i32 %arg1, %arg2
+ ret i1 %A
+}
+
+define i32 @icmp_ne_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ne i32 %arg1, 511
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_ne_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ne i32 %arg1, -512
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_ne_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ne i32 %arg1, -1
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_ne_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ne i32 %arg1, 32768
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_ugt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ugt i32 %arg1, %arg2
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i1 @icmp_ugt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ugt i32 %arg1, %arg2
+ ret i1 %A
+}
+
+define i32 @icmp_ugt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ugt i32 %arg1, 511
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_ugt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ugt i32 %arg1, 4294966784
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_ugt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ugt i32 %arg1, 4294967293
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_ugt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ugt i32 %arg1, 32768
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_uge_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp uge i32 %arg1, %arg2
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i1 @icmp_uge_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp uge i32 %arg1, %arg2
+ ret i1 %A
+}
+
+;; Note: icmp uge i32 %arg1, <immed> can always be transformed into
+;; icmp ugt i32 %arg1, <immed>-1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i32 @icmp_ult_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ult i32 %arg1, %arg2
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i1 @icmp_ult_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ult i32 %arg1, %arg2
+ ret i1 %A
+}
+
+define i32 @icmp_ult_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ult i32 %arg1, 511
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_ult_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ult i32 %arg1, 4294966784
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_ult_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ult i32 %arg1, 4294967293
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_ult_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ult i32 %arg1, 32768
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_ule_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ule i32 %arg1, %arg2
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i1 @icmp_ule_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp ule i32 %arg1, %arg2
+ ret i1 %A
+}
+
+;; Note: icmp ule i32 %arg1, <immed> can always be transformed into
+;; icmp ult i32 %arg1, <immed>+1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i32 @icmp_sgt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp sgt i32 %arg1, %arg2
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i1 @icmp_sgt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp sgt i32 %arg1, %arg2
+ ret i1 %A
+}
+
+define i32 @icmp_sgt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp sgt i32 %arg1, 511
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_sgt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp sgt i32 %arg1, 4294966784
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_sgt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp sgt i32 %arg1, 4294967293
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_sgt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp sgt i32 %arg1, 32768
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_sge_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp sge i32 %arg1, %arg2
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i1 @icmp_sge_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp sge i32 %arg1, %arg2
+ ret i1 %A
+}
+
+;; Note: icmp sge i32 %arg1, <immed> can always be transformed into
+;; icmp sgt i32 %arg1, <immed>-1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i32 @icmp_slt_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp slt i32 %arg1, %arg2
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i1 @icmp_slt_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp slt i32 %arg1, %arg2
+ ret i1 %A
+}
+
+define i32 @icmp_slt_immed01_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp slt i32 %arg1, 511
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_slt_immed02_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp slt i32 %arg1, -512
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_slt_immed03_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp slt i32 %arg1, -1
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_slt_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp slt i32 %arg1, 32768
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i32 @icmp_sle_select_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp sle i32 %arg1, %arg2
+ %B = select i1 %A, i32 %val1, i32 %val2
+ ret i32 %B
+}
+
+define i1 @icmp_sle_setcc_i32(i32 %arg1, i32 %arg2, i32 %val1, i32 %val2) nounwind {
+entry:
+ %A = icmp sle i32 %arg1, %arg2
+ ret i1 %A
+}
+
+;; Note: icmp sle i32 %arg1, <immed> can always be transformed into
+;; icmp slt i32 %arg1, <immed>+1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
diff --git a/test/CodeGen/CellSPU/icmp64.ll b/test/CodeGen/CellSPU/icmp64.ll
new file mode 100644
index 0000000..9dd2cdc
--- /dev/null
+++ b/test/CodeGen/CellSPU/icmp64.ll
@@ -0,0 +1,146 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep ceq %t1.s | count 20
+; RUN: grep cgti %t1.s | count 12
+; RUN: grep cgt %t1.s | count 16
+; RUN: grep clgt %t1.s | count 12
+; RUN: grep gb %t1.s | count 12
+; RUN: grep fsm %t1.s | count 10
+; RUN: grep xori %t1.s | count 5
+; RUN: grep selb %t1.s | count 18
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
+; $3 = %arg1, $4 = %val1, $5 = %val2
+;
+; i64 integer comparisons:
+define i64 @icmp_eq_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp eq i64 %arg1, %arg2
+ %B = select i1 %A, i64 %val1, i64 %val2
+ ret i64 %B
+}
+
+define i1 @icmp_eq_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp eq i64 %arg1, %arg2
+ ret i1 %A
+}
+
+define i64 @icmp_ne_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp ne i64 %arg1, %arg2
+ %B = select i1 %A, i64 %val1, i64 %val2
+ ret i64 %B
+}
+
+define i1 @icmp_ne_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp ne i64 %arg1, %arg2
+ ret i1 %A
+}
+
+define i64 @icmp_ugt_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp ugt i64 %arg1, %arg2
+ %B = select i1 %A, i64 %val1, i64 %val2
+ ret i64 %B
+}
+
+define i1 @icmp_ugt_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp ugt i64 %arg1, %arg2
+ ret i1 %A
+}
+
+define i64 @icmp_uge_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp uge i64 %arg1, %arg2
+ %B = select i1 %A, i64 %val1, i64 %val2
+ ret i64 %B
+}
+
+define i1 @icmp_uge_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp uge i64 %arg1, %arg2
+ ret i1 %A
+}
+
+define i64 @icmp_ult_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp ult i64 %arg1, %arg2
+ %B = select i1 %A, i64 %val1, i64 %val2
+ ret i64 %B
+}
+
+define i1 @icmp_ult_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp ult i64 %arg1, %arg2
+ ret i1 %A
+}
+
+define i64 @icmp_ule_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp ule i64 %arg1, %arg2
+ %B = select i1 %A, i64 %val1, i64 %val2
+ ret i64 %B
+}
+
+define i1 @icmp_ule_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp ule i64 %arg1, %arg2
+ ret i1 %A
+}
+
+define i64 @icmp_sgt_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp sgt i64 %arg1, %arg2
+ %B = select i1 %A, i64 %val1, i64 %val2
+ ret i64 %B
+}
+
+define i1 @icmp_sgt_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp sgt i64 %arg1, %arg2
+ ret i1 %A
+}
+
+define i64 @icmp_sge_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp sge i64 %arg1, %arg2
+ %B = select i1 %A, i64 %val1, i64 %val2
+ ret i64 %B
+}
+
+define i1 @icmp_sge_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp sge i64 %arg1, %arg2
+ ret i1 %A
+}
+
+define i64 @icmp_slt_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp slt i64 %arg1, %arg2
+ %B = select i1 %A, i64 %val1, i64 %val2
+ ret i64 %B
+}
+
+define i1 @icmp_slt_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp slt i64 %arg1, %arg2
+ ret i1 %A
+}
+
+define i64 @icmp_sle_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp sle i64 %arg1, %arg2
+ %B = select i1 %A, i64 %val1, i64 %val2
+ ret i64 %B
+}
+
+define i1 @icmp_sle_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp sle i64 %arg1, %arg2
+ ret i1 %A
+}
diff --git a/test/CodeGen/CellSPU/icmp8.ll b/test/CodeGen/CellSPU/icmp8.ll
new file mode 100644
index 0000000..5517d10
--- /dev/null
+++ b/test/CodeGen/CellSPU/icmp8.ll
@@ -0,0 +1,286 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep ceqb %t1.s | count 24
+; RUN: grep ceqbi %t1.s | count 12
+; RUN: grep clgtb %t1.s | count 11
+; RUN: grep cgtb %t1.s | count 13
+; RUN: grep cgtbi %t1.s | count 5
+; RUN: grep {selb\t\\\$3, \\\$6, \\\$5, \\\$3} %t1.s | count 7
+; RUN: grep {selb\t\\\$3, \\\$5, \\\$6, \\\$3} %t1.s | count 3
+; RUN: grep {selb\t\\\$3, \\\$5, \\\$4, \\\$3} %t1.s | count 11
+; RUN: grep {selb\t\\\$3, \\\$4, \\\$5, \\\$3} %t1.s | count 4
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; $3 = %arg1, $4 = %arg2, $5 = %val1, $6 = %val2
+; $3 = %arg1, $4 = %val1, $5 = %val2
+;
+; For "positive" comparisons:
+; selb $3, $6, $5, <i1>
+; selb $3, $5, $4, <i1>
+;
+; For "negative" comparisons, i.e., those where the result of the comparison
+; must be inverted (setne, for example):
+; selb $3, $5, $6, <i1>
+; selb $3, $4, $5, <i1>
+
+; i8 integer comparisons:
+define i8 @icmp_eq_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp eq i8 %arg1, %arg2
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i1 @icmp_eq_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp eq i8 %arg1, %arg2
+ ret i1 %A
+}
+
+define i8 @icmp_eq_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp eq i8 %arg1, 127
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_eq_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp eq i8 %arg1, -128
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_eq_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp eq i8 %arg1, -1
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_ne_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp ne i8 %arg1, %arg2
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i1 @icmp_ne_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp ne i8 %arg1, %arg2
+ ret i1 %A
+}
+
+define i8 @icmp_ne_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp ne i8 %arg1, 127
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_ne_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp ne i8 %arg1, -128
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_ne_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp ne i8 %arg1, -1
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_ugt_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp ugt i8 %arg1, %arg2
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i1 @icmp_ugt_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp ugt i8 %arg1, %arg2
+ ret i1 %A
+}
+
+define i8 @icmp_ugt_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp ugt i8 %arg1, 126
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_uge_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp uge i8 %arg1, %arg2
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i1 @icmp_uge_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp uge i8 %arg1, %arg2
+ ret i1 %A
+}
+
+;; Note: icmp uge i8 %arg1, <immed> can always be transformed into
+;; icmp ugt i8 %arg1, <immed>-1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i8 @icmp_ult_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp ult i8 %arg1, %arg2
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i1 @icmp_ult_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp ult i8 %arg1, %arg2
+ ret i1 %A
+}
+
+define i8 @icmp_ult_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp ult i8 %arg1, 253
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_ult_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp ult i8 %arg1, 129
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_ule_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp ule i8 %arg1, %arg2
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i1 @icmp_ule_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp ule i8 %arg1, %arg2
+ ret i1 %A
+}
+
+;; Note: icmp ule i8 %arg1, <immed> can always be transformed into
+;; icmp ult i8 %arg1, <immed>+1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i8 @icmp_sgt_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp sgt i8 %arg1, %arg2
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i1 @icmp_sgt_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp sgt i8 %arg1, %arg2
+ ret i1 %A
+}
+
+define i8 @icmp_sgt_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp sgt i8 %arg1, 96
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_sgt_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp sgt i8 %arg1, -1
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_sgt_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp sgt i8 %arg1, -128
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_sge_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp sge i8 %arg1, %arg2
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i1 @icmp_sge_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp sge i8 %arg1, %arg2
+ ret i1 %A
+}
+
+;; Note: icmp sge i8 %arg1, <immed> can always be transformed into
+;; icmp sgt i8 %arg1, <immed>-1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
+define i8 @icmp_slt_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp slt i8 %arg1, %arg2
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i1 @icmp_slt_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp slt i8 %arg1, %arg2
+ ret i1 %A
+}
+
+define i8 @icmp_slt_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp slt i8 %arg1, 96
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_slt_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp slt i8 %arg1, -120
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_slt_immed03_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp slt i8 %arg1, -1
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i8 @icmp_sle_select_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp sle i8 %arg1, %arg2
+ %B = select i1 %A, i8 %val1, i8 %val2
+ ret i8 %B
+}
+
+define i1 @icmp_sle_setcc_i8(i8 %arg1, i8 %arg2, i8 %val1, i8 %val2) nounwind {
+entry:
+ %A = icmp sle i8 %arg1, %arg2
+ ret i1 %A
+}
+
+;; Note: icmp sle i8 %arg1, <immed> can always be transformed into
+;; icmp slt i8 %arg1, <immed>+1
+;;
+;; Consequently, even though the patterns exist to match, it's unlikely
+;; they'll ever be generated.
+
diff --git a/test/CodeGen/CellSPU/immed16.ll b/test/CodeGen/CellSPU/immed16.ll
new file mode 100644
index 0000000..077d071
--- /dev/null
+++ b/test/CodeGen/CellSPU/immed16.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep "ilh" %t1.s | count 11
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define i16 @test_1() {
+ %x = alloca i16, align 16
+ store i16 419, i16* %x ;; ILH via pattern
+ ret i16 0
+}
+
+define i16 @test_2() {
+ %x = alloca i16, align 16
+ store i16 1023, i16* %x ;; ILH via pattern
+ ret i16 0
+}
+
+define i16 @test_3() {
+ %x = alloca i16, align 16
+ store i16 -1023, i16* %x ;; ILH via pattern
+ ret i16 0
+}
+
+define i16 @test_4() {
+ %x = alloca i16, align 16
+ store i16 32767, i16* %x ;; ILH via pattern
+ ret i16 0
+}
+
+define i16 @test_5() {
+ %x = alloca i16, align 16
+ store i16 -32768, i16* %x ;; ILH via pattern
+ ret i16 0
+}
+
+define i16 @test_6() {
+ ret i16 0
+}
+
+
diff --git a/test/CodeGen/CellSPU/immed32.ll b/test/CodeGen/CellSPU/immed32.ll
new file mode 100644
index 0000000..119f526
--- /dev/null
+++ b/test/CodeGen/CellSPU/immed32.ll
@@ -0,0 +1,72 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep ilhu %t1.s | count 8
+; RUN: grep iohl %t1.s | count 6
+; RUN: grep -w il %t1.s | count 3
+; RUN: grep 16429 %t1.s | count 1
+; RUN: grep 63572 %t1.s | count 1
+; RUN: grep 128 %t1.s | count 1
+; RUN: grep 32639 %t1.s | count 1
+; RUN: grep 65535 %t1.s | count 1
+; RUN: grep 16457 %t1.s | count 1
+; RUN: grep 4059 %t1.s | count 1
+; RUN: grep 49077 %t1.s | count 1
+; RUN: grep 1267 %t1.s | count 2
+; RUN: grep 16309 %t1.s | count 1
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define i32 @test_1() {
+ ret i32 4784128 ;; ILHU via pattern (0x49000)
+}
+
+define i32 @test_2() {
+ ret i32 5308431 ;; ILHU/IOHL via pattern (0x5100f)
+}
+
+define i32 @test_3() {
+ ret i32 511 ;; IL via pattern
+}
+
+define i32 @test_4() {
+ ret i32 -512 ;; IL via pattern
+}
+
+;; double float floatval
+;; 0x4005bf0a80000000 0x402d|f854 2.718282
+define float @float_const_1() {
+ ret float 0x4005BF0A80000000 ;; ILHU/IOHL
+}
+
+;; double float floatval
+;; 0x3810000000000000 0x0080|0000 0.000000
+define float @float_const_2() {
+ ret float 0x3810000000000000 ;; IL 128
+}
+
+;; double float floatval
+;; 0x47efffffe0000000 0x7f7f|ffff NaN
+define float @float_const_3() {
+ ret float 0x47EFFFFFE0000000 ;; ILHU/IOHL via pattern
+}
+
+;; double float floatval
+;; 0x400921fb60000000 0x4049|0fdb 3.141593
+define float @float_const_4() {
+ ret float 0x400921FB60000000 ;; ILHU/IOHL via pattern
+}
+
+;; double float floatval
+;; 0xbff6a09e60000000 0xbfb5|04f3 -1.414214
+define float @float_const_5() {
+ ret float 0xBFF6A09E60000000 ;; ILHU/IOHL via pattern
+}
+
+;; double float floatval
+;; 0x3ff6a09e60000000 0x3fb5|04f3 1.414214
+define float @float_const_6() {
+ ret float 0x3FF6A09E60000000 ;; ILHU/IOHL via pattern
+}
+
+define float @float_const_7() {
+ ret float 0.000000e+00 ;; IL 0 via pattern
+}
diff --git a/test/CodeGen/CellSPU/immed64.ll b/test/CodeGen/CellSPU/immed64.ll
new file mode 100644
index 0000000..fd48365
--- /dev/null
+++ b/test/CodeGen/CellSPU/immed64.ll
@@ -0,0 +1,95 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep lqa %t1.s | count 13
+; RUN: grep ilhu %t1.s | count 15
+; RUN: grep ila %t1.s | count 1
+; RUN: grep -w il %t1.s | count 6
+; RUN: grep shufb %t1.s | count 13
+; RUN: grep 65520 %t1.s | count 1
+; RUN: grep 43981 %t1.s | count 1
+; RUN: grep 13702 %t1.s | count 1
+; RUN: grep 28225 %t1.s | count 1
+; RUN: grep 30720 %t1.s | count 1
+; RUN: grep 3233857728 %t1.s | count 8
+; RUN: grep 2155905152 %t1.s | count 6
+; RUN: grep 66051 %t1.s | count 7
+; RUN: grep 471670303 %t1.s | count 11
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; 1311768467750121234 => 0x 12345678 abcdef12 (4660,22136/43981,61202)
+; 18446744073709551591 => 0x ffffffff ffffffe7 (-25)
+; 18446744073708516742 => 0x ffffffff fff03586 (-1034874)
+; 5308431 => 0x 00000000 0051000F
+; 9223372038704560128 => 0x 80000000 6e417800
+
+define i64 @i64_const_1() {
+ ret i64 1311768467750121234 ;; Constant pool spill
+}
+
+define i64 @i64_const_2() {
+ ret i64 18446744073709551591 ;; IL/SHUFB
+}
+
+define i64 @i64_const_3() {
+ ret i64 18446744073708516742 ;; IHLU/IOHL/SHUFB
+}
+
+define i64 @i64_const_4() {
+ ret i64 5308431 ;; ILHU/IOHL/SHUFB
+}
+
+define i64 @i64_const_5() {
+ ret i64 511 ;; IL/SHUFB
+}
+
+define i64 @i64_const_6() {
+ ret i64 -512 ;; IL/SHUFB
+}
+
+define i64 @i64_const_7() {
+ ret i64 9223372038704560128 ;; IHLU/IOHL/SHUFB
+}
+
+define i64 @i64_const_8() {
+ ret i64 0 ;; IL
+}
+
+define i64 @i64_const_9() {
+ ret i64 -1 ;; IL
+}
+
+define i64 @i64_const_10() {
+ ret i64 281470681808895 ;; IL 65535
+}
+
+; 0x4005bf0a8b145769 ->
+; (ILHU 0x4005 [16389]/IOHL 0xbf0a [48906])
+; (ILHU 0x8b14 [35604]/IOHL 0x5769 [22377])
+define double @f64_const_1() {
+ ret double 0x4005bf0a8b145769 ;; ILHU/IOHL via pattern
+}
+
+define double @f64_const_2() {
+ ret double 0x0010000000000000
+}
+
+define double @f64_const_3() {
+ ret double 0x7fefffffffffffff
+}
+
+define double @f64_const_4() {
+ ret double 0x400921fb54442d18
+}
+
+define double @f64_const_5() {
+ ret double 0xbff6a09e667f3bcd ;; ILHU/IOHL via pattern
+}
+
+define double @f64_const_6() {
+ ret double 0x3ff6a09e667f3bcd
+}
+
+define double @f64_const_7() {
+ ret double 0.000000e+00
+}
diff --git a/test/CodeGen/CellSPU/int2fp.ll b/test/CodeGen/CellSPU/int2fp.ll
new file mode 100644
index 0000000..984c017
--- /dev/null
+++ b/test/CodeGen/CellSPU/int2fp.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep csflt %t1.s | count 5
+; RUN: grep cuflt %t1.s | count 1
+; RUN: grep xshw %t1.s | count 2
+; RUN: grep xsbh %t1.s | count 1
+; RUN: grep and %t1.s | count 2
+; RUN: grep andi %t1.s | count 1
+; RUN: grep ila %t1.s | count 1
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define float @sitofp_i32(i32 %arg1) {
+ %A = sitofp i32 %arg1 to float ; <float> [#uses=1]
+ ret float %A
+}
+
+define float @uitofp_u32(i32 %arg1) {
+ %A = uitofp i32 %arg1 to float ; <float> [#uses=1]
+ ret float %A
+}
+
+define float @sitofp_i16(i16 %arg1) {
+ %A = sitofp i16 %arg1 to float ; <float> [#uses=1]
+ ret float %A
+}
+
+define float @uitofp_i16(i16 %arg1) {
+ %A = uitofp i16 %arg1 to float ; <float> [#uses=1]
+ ret float %A
+}
+
+define float @sitofp_i8(i8 %arg1) {
+ %A = sitofp i8 %arg1 to float ; <float> [#uses=1]
+ ret float %A
+}
+
+define float @uitofp_i8(i8 %arg1) {
+ %A = uitofp i8 %arg1 to float ; <float> [#uses=1]
+ ret float %A
+}
diff --git a/test/CodeGen/CellSPU/intrinsics_branch.ll b/test/CodeGen/CellSPU/intrinsics_branch.ll
new file mode 100644
index 0000000..b0f6a62
--- /dev/null
+++ b/test/CodeGen/CellSPU/intrinsics_branch.ll
@@ -0,0 +1,150 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep ceq %t1.s | count 30
+; RUN: grep ceqb %t1.s | count 10
+; RUN: grep ceqhi %t1.s | count 5
+; RUN: grep ceqi %t1.s | count 5
+; RUN: grep cgt %t1.s | count 30
+; RUN: grep cgtb %t1.s | count 10
+; RUN: grep cgthi %t1.s | count 5
+; RUN: grep cgti %t1.s | count 5
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+declare <4 x i32> @llvm.spu.si.shli(<4 x i32>, i8)
+
+declare <4 x i32> @llvm.spu.si.ceq(<4 x i32>, <4 x i32>)
+declare <16 x i8> @llvm.spu.si.ceqb(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.spu.si.ceqh(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.spu.si.ceqi(<4 x i32>, i16)
+declare <8 x i16> @llvm.spu.si.ceqhi(<8 x i16>, i16)
+declare <16 x i8> @llvm.spu.si.ceqbi(<16 x i8>, i8)
+
+declare <4 x i32> @llvm.spu.si.cgt(<4 x i32>, <4 x i32>)
+declare <16 x i8> @llvm.spu.si.cgtb(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.spu.si.cgth(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.spu.si.cgti(<4 x i32>, i16)
+declare <8 x i16> @llvm.spu.si.cgthi(<8 x i16>, i16)
+declare <16 x i8> @llvm.spu.si.cgtbi(<16 x i8>, i8)
+
+declare <4 x i32> @llvm.spu.si.clgt(<4 x i32>, <4 x i32>)
+declare <16 x i8> @llvm.spu.si.clgtb(<16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.spu.si.clgth(<8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.spu.si.clgti(<4 x i32>, i16)
+declare <8 x i16> @llvm.spu.si.clgthi(<8 x i16>, i16)
+declare <16 x i8> @llvm.spu.si.clgtbi(<16 x i8>, i8)
+
+
+
+define <4 x i32> @test(<4 x i32> %A) {
+ call <4 x i32> @llvm.spu.si.shli(<4 x i32> %A, i8 3)
+ %Y = bitcast <4 x i32> %1 to <4 x i32>
+ ret <4 x i32> %Y
+}
+
+define <4 x i32> @ceqtest(<4 x i32> %A, <4 x i32> %B) {
+ call <4 x i32> @llvm.spu.si.ceq(<4 x i32> %A, <4 x i32> %B)
+ %Y = bitcast <4 x i32> %1 to <4 x i32>
+ ret <4 x i32> %Y
+}
+
+define <8 x i16> @ceqhtest(<8 x i16> %A, <8 x i16> %B) {
+ call <8 x i16> @llvm.spu.si.ceqh(<8 x i16> %A, <8 x i16> %B)
+ %Y = bitcast <8 x i16> %1 to <8 x i16>
+ ret <8 x i16> %Y
+}
+
+define <16 x i8> @ceqbtest(<16 x i8> %A, <16 x i8> %B) {
+ call <16 x i8> @llvm.spu.si.ceqb(<16 x i8> %A, <16 x i8> %B)
+ %Y = bitcast <16 x i8> %1 to <16 x i8>
+ ret <16 x i8> %Y
+}
+
+define <4 x i32> @ceqitest(<4 x i32> %A) {
+ call <4 x i32> @llvm.spu.si.ceqi(<4 x i32> %A, i16 65)
+ %Y = bitcast <4 x i32> %1 to <4 x i32>
+ ret <4 x i32> %Y
+}
+
+define <8 x i16> @ceqhitest(<8 x i16> %A) {
+ call <8 x i16> @llvm.spu.si.ceqhi(<8 x i16> %A, i16 65)
+ %Y = bitcast <8 x i16> %1 to <8 x i16>
+ ret <8 x i16> %Y
+}
+
+define <16 x i8> @ceqbitest(<16 x i8> %A) {
+ call <16 x i8> @llvm.spu.si.ceqbi(<16 x i8> %A, i8 65)
+ %Y = bitcast <16 x i8> %1 to <16 x i8>
+ ret <16 x i8> %Y
+}
+
+define <4 x i32> @cgttest(<4 x i32> %A, <4 x i32> %B) {
+ call <4 x i32> @llvm.spu.si.cgt(<4 x i32> %A, <4 x i32> %B)
+ %Y = bitcast <4 x i32> %1 to <4 x i32>
+ ret <4 x i32> %Y
+}
+
+define <8 x i16> @cgthtest(<8 x i16> %A, <8 x i16> %B) {
+ call <8 x i16> @llvm.spu.si.cgth(<8 x i16> %A, <8 x i16> %B)
+ %Y = bitcast <8 x i16> %1 to <8 x i16>
+ ret <8 x i16> %Y
+}
+
+define <16 x i8> @cgtbtest(<16 x i8> %A, <16 x i8> %B) {
+ call <16 x i8> @llvm.spu.si.cgtb(<16 x i8> %A, <16 x i8> %B)
+ %Y = bitcast <16 x i8> %1 to <16 x i8>
+ ret <16 x i8> %Y
+}
+
+define <4 x i32> @cgtitest(<4 x i32> %A) {
+ call <4 x i32> @llvm.spu.si.cgti(<4 x i32> %A, i16 65)
+ %Y = bitcast <4 x i32> %1 to <4 x i32>
+ ret <4 x i32> %Y
+}
+
+define <8 x i16> @cgthitest(<8 x i16> %A) {
+ call <8 x i16> @llvm.spu.si.cgthi(<8 x i16> %A, i16 65)
+ %Y = bitcast <8 x i16> %1 to <8 x i16>
+ ret <8 x i16> %Y
+}
+
+define <16 x i8> @cgtbitest(<16 x i8> %A) {
+ call <16 x i8> @llvm.spu.si.cgtbi(<16 x i8> %A, i8 65)
+ %Y = bitcast <16 x i8> %1 to <16 x i8>
+ ret <16 x i8> %Y
+}
+
+define <4 x i32> @clgttest(<4 x i32> %A, <4 x i32> %B) {
+ call <4 x i32> @llvm.spu.si.clgt(<4 x i32> %A, <4 x i32> %B)
+ %Y = bitcast <4 x i32> %1 to <4 x i32>
+ ret <4 x i32> %Y
+}
+
+define <8 x i16> @clgthtest(<8 x i16> %A, <8 x i16> %B) {
+ call <8 x i16> @llvm.spu.si.clgth(<8 x i16> %A, <8 x i16> %B)
+ %Y = bitcast <8 x i16> %1 to <8 x i16>
+ ret <8 x i16> %Y
+}
+
+define <16 x i8> @clgtbtest(<16 x i8> %A, <16 x i8> %B) {
+ call <16 x i8> @llvm.spu.si.clgtb(<16 x i8> %A, <16 x i8> %B)
+ %Y = bitcast <16 x i8> %1 to <16 x i8>
+ ret <16 x i8> %Y
+}
+
+define <4 x i32> @clgtitest(<4 x i32> %A) {
+ call <4 x i32> @llvm.spu.si.clgti(<4 x i32> %A, i16 65)
+ %Y = bitcast <4 x i32> %1 to <4 x i32>
+ ret <4 x i32> %Y
+}
+
+define <8 x i16> @clgthitest(<8 x i16> %A) {
+ call <8 x i16> @llvm.spu.si.clgthi(<8 x i16> %A, i16 65)
+ %Y = bitcast <8 x i16> %1 to <8 x i16>
+ ret <8 x i16> %Y
+}
+
+define <16 x i8> @clgtbitest(<16 x i8> %A) {
+ call <16 x i8> @llvm.spu.si.clgtbi(<16 x i8> %A, i8 65)
+ %Y = bitcast <16 x i8> %1 to <16 x i8>
+ ret <16 x i8> %Y
+}
diff --git a/test/CodeGen/CellSPU/intrinsics_float.ll b/test/CodeGen/CellSPU/intrinsics_float.ll
new file mode 100644
index 0000000..8137347
--- /dev/null
+++ b/test/CodeGen/CellSPU/intrinsics_float.ll
@@ -0,0 +1,94 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep fa %t1.s | count 5
+; RUN: grep fs %t1.s | count 5
+; RUN: grep fm %t1.s | count 15
+; RUN: grep fceq %t1.s | count 5
+; RUN: grep fcmeq %t1.s | count 5
+; RUN: grep fcgt %t1.s | count 5
+; RUN: grep fcmgt %t1.s | count 5
+; RUN: grep fma %t1.s | count 5
+; RUN: grep fnms %t1.s | count 5
+; RUN: grep fms %t1.s | count 5
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+declare <4 x i32> @llvm.spu.si.shli(<4 x i32>, i8)
+
+declare <4 x float> @llvm.spu.si.fa(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.spu.si.fs(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.spu.si.fm(<4 x float>, <4 x float>)
+
+declare <4 x float> @llvm.spu.si.fceq(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.spu.si.fcmeq(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.spu.si.fcgt(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.spu.si.fcmgt(<4 x float>, <4 x float>)
+
+declare <4 x float> @llvm.spu.si.fma(<4 x float>, <4 x float>, <4 x float>)
+declare <4 x float> @llvm.spu.si.fnms(<4 x float>, <4 x float>, <4 x float>)
+declare <4 x float> @llvm.spu.si.fms(<4 x float>, <4 x float>, <4 x float>)
+
+define <4 x i32> @test(<4 x i32> %A) {
+ call <4 x i32> @llvm.spu.si.shli(<4 x i32> %A, i8 3)
+ %Y = bitcast <4 x i32> %1 to <4 x i32>
+ ret <4 x i32> %Y
+}
+
+define <4 x float> @fatest(<4 x float> %A, <4 x float> %B) {
+ call <4 x float> @llvm.spu.si.fa(<4 x float> %A, <4 x float> %B)
+ %Y = bitcast <4 x float> %1 to <4 x float>
+ ret <4 x float> %Y
+}
+
+define <4 x float> @fstest(<4 x float> %A, <4 x float> %B) {
+ call <4 x float> @llvm.spu.si.fs(<4 x float> %A, <4 x float> %B)
+ %Y = bitcast <4 x float> %1 to <4 x float>
+ ret <4 x float> %Y
+}
+
+define <4 x float> @fmtest(<4 x float> %A, <4 x float> %B) {
+ call <4 x float> @llvm.spu.si.fm(<4 x float> %A, <4 x float> %B)
+ %Y = bitcast <4 x float> %1 to <4 x float>
+ ret <4 x float> %Y
+}
+
+define <4 x float> @fceqtest(<4 x float> %A, <4 x float> %B) {
+ call <4 x float> @llvm.spu.si.fceq(<4 x float> %A, <4 x float> %B)
+ %Y = bitcast <4 x float> %1 to <4 x float>
+ ret <4 x float> %Y
+}
+
+define <4 x float> @fcmeqtest(<4 x float> %A, <4 x float> %B) {
+ call <4 x float> @llvm.spu.si.fcmeq(<4 x float> %A, <4 x float> %B)
+ %Y = bitcast <4 x float> %1 to <4 x float>
+ ret <4 x float> %Y
+}
+
+define <4 x float> @fcgttest(<4 x float> %A, <4 x float> %B) {
+ call <4 x float> @llvm.spu.si.fcgt(<4 x float> %A, <4 x float> %B)
+ %Y = bitcast <4 x float> %1 to <4 x float>
+ ret <4 x float> %Y
+}
+
+define <4 x float> @fcmgttest(<4 x float> %A, <4 x float> %B) {
+ call <4 x float> @llvm.spu.si.fcmgt(<4 x float> %A, <4 x float> %B)
+ %Y = bitcast <4 x float> %1 to <4 x float>
+ ret <4 x float> %Y
+}
+
+define <4 x float> @fmatest(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
+ call <4 x float> @llvm.spu.si.fma(<4 x float> %A, <4 x float> %B, <4 x float> %C)
+ %Y = bitcast <4 x float> %1 to <4 x float>
+ ret <4 x float> %Y
+}
+
+define <4 x float> @fnmstest(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
+ call <4 x float> @llvm.spu.si.fnms(<4 x float> %A, <4 x float> %B, <4 x float> %C)
+ %Y = bitcast <4 x float> %1 to <4 x float>
+ ret <4 x float> %Y
+}
+
+define <4 x float> @fmstest(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
+ call <4 x float> @llvm.spu.si.fms(<4 x float> %A, <4 x float> %B, <4 x float> %C)
+ %Y = bitcast <4 x float> %1 to <4 x float>
+ ret <4 x float> %Y
+}
diff --git a/test/CodeGen/CellSPU/intrinsics_logical.ll b/test/CodeGen/CellSPU/intrinsics_logical.ll
new file mode 100644
index 0000000..a29ee4c
--- /dev/null
+++ b/test/CodeGen/CellSPU/intrinsics_logical.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep and %t1.s | count 20
+; RUN: grep andc %t1.s | count 5
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+declare <4 x i32> @llvm.spu.si.and(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.spu.si.andc(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.spu.si.andi(<4 x i32>, i16)
+declare <8 x i16> @llvm.spu.si.andhi(<8 x i16>, i16)
+declare <16 x i8> @llvm.spu.si.andbi(<16 x i8>, i8)
+
+declare <4 x i32> @llvm.spu.si.or(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.spu.si.orc(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.spu.si.ori(<4 x i32>, i16)
+declare <8 x i16> @llvm.spu.si.orhi(<8 x i16>, i16)
+declare <16 x i8> @llvm.spu.si.orbi(<16 x i8>, i8)
+
+declare <4 x i32> @llvm.spu.si.xor(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.spu.si.xori(<4 x i32>, i16)
+declare <8 x i16> @llvm.spu.si.xorhi(<8 x i16>, i16)
+declare <16 x i8> @llvm.spu.si.xorbi(<16 x i8>, i8)
+
+declare <4 x i32> @llvm.spu.si.nand(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.spu.si.nor(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @andtest(<4 x i32> %A, <4 x i32> %B) {
+ call <4 x i32> @llvm.spu.si.and(<4 x i32> %A, <4 x i32> %B)
+ %Y = bitcast <4 x i32> %1 to <4 x i32>
+ ret <4 x i32> %Y
+}
+
+define <4 x i32> @andctest(<4 x i32> %A, <4 x i32> %B) {
+ call <4 x i32> @llvm.spu.si.andc(<4 x i32> %A, <4 x i32> %B)
+ %Y = bitcast <4 x i32> %1 to <4 x i32>
+ ret <4 x i32> %Y
+}
+
+define <4 x i32> @anditest(<4 x i32> %A) {
+ call <4 x i32> @llvm.spu.si.andi(<4 x i32> %A, i16 65)
+ %Y = bitcast <4 x i32> %1 to <4 x i32>
+ ret <4 x i32> %Y
+}
+
+define <8 x i16> @andhitest(<8 x i16> %A) {
+ call <8 x i16> @llvm.spu.si.andhi(<8 x i16> %A, i16 65)
+ %Y = bitcast <8 x i16> %1 to <8 x i16>
+ ret <8 x i16> %Y
+}
diff --git a/test/CodeGen/CellSPU/loads.ll b/test/CodeGen/CellSPU/loads.ll
new file mode 100644
index 0000000..8e5422c
--- /dev/null
+++ b/test/CodeGen/CellSPU/loads.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=cellspu | FileCheck %s
+
+; ModuleID = 'loads.bc'
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define <4 x float> @load_v4f32_1(<4 x float>* %a) nounwind readonly {
+entry:
+ %tmp1 = load <4 x float>* %a
+ ret <4 x float> %tmp1
+; CHECK: lqd $3, 0($3)
+}
+
+define <4 x float> @load_v4f32_2(<4 x float>* %a) nounwind readonly {
+entry:
+ %arrayidx = getelementptr <4 x float>* %a, i32 1
+ %tmp1 = load <4 x float>* %arrayidx
+ ret <4 x float> %tmp1
+; CHECK: lqd $3, 16($3)
+}
diff --git a/test/CodeGen/CellSPU/mul-with-overflow.ll b/test/CodeGen/CellSPU/mul-with-overflow.ll
new file mode 100644
index 0000000..d15da12
--- /dev/null
+++ b/test/CodeGen/CellSPU/mul-with-overflow.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=cellspu
+
+declare {i16, i1} @llvm.smul.with.overflow.i16(i16 %a, i16 %b)
+define i1 @a(i16 %x) zeroext nounwind {
+ %res = call {i16, i1} @llvm.smul.with.overflow.i16(i16 %x, i16 3)
+ %obil = extractvalue {i16, i1} %res, 1
+ ret i1 %obil
+}
+
+declare {i16, i1} @llvm.umul.with.overflow.i16(i16 %a, i16 %b)
+define i1 @b(i16 %x) zeroext nounwind {
+ %res = call {i16, i1} @llvm.umul.with.overflow.i16(i16 %x, i16 3)
+ %obil = extractvalue {i16, i1} %res, 1
+ ret i1 %obil
+}
diff --git a/test/CodeGen/CellSPU/mul_ops.ll b/test/CodeGen/CellSPU/mul_ops.ll
new file mode 100644
index 0000000..1e28fc7
--- /dev/null
+++ b/test/CodeGen/CellSPU/mul_ops.ll
@@ -0,0 +1,88 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep mpy %t1.s | count 44
+; RUN: grep mpyu %t1.s | count 4
+; RUN: grep mpyh %t1.s | count 10
+; RUN: grep mpyhh %t1.s | count 2
+; RUN: grep rotma %t1.s | count 12
+; RUN: grep rotmahi %t1.s | count 4
+; RUN: grep and %t1.s | count 2
+; RUN: grep selb %t1.s | count 6
+; RUN: grep fsmbi %t1.s | count 4
+; RUN: grep shli %t1.s | count 4
+; RUN: grep shlhi %t1.s | count 4
+; RUN: grep ila %t1.s | count 2
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; 32-bit multiply instruction generation:
+define <4 x i32> @mpy_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
+entry:
+ %A = mul <4 x i32> %arg1, %arg2
+ ret <4 x i32> %A
+}
+
+define <4 x i32> @mpy_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
+entry:
+ %A = mul <4 x i32> %arg2, %arg1
+ ret <4 x i32> %A
+}
+
+define <8 x i16> @mpy_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
+entry:
+ %A = mul <8 x i16> %arg1, %arg2
+ ret <8 x i16> %A
+}
+
+define <8 x i16> @mpy_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
+entry:
+ %A = mul <8 x i16> %arg2, %arg1
+ ret <8 x i16> %A
+}
+
+define <16 x i8> @mul_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
+entry:
+ %A = mul <16 x i8> %arg2, %arg1
+ ret <16 x i8> %A
+}
+
+define <16 x i8> @mul_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
+entry:
+ %A = mul <16 x i8> %arg1, %arg2
+ ret <16 x i8> %A
+}
+
+define i32 @mul_i32_1(i32 %arg1, i32 %arg2) {
+entry:
+ %A = mul i32 %arg2, %arg1
+ ret i32 %A
+}
+
+define i32 @mul_i32_2(i32 %arg1, i32 %arg2) {
+entry:
+ %A = mul i32 %arg1, %arg2
+ ret i32 %A
+}
+
+define i16 @mul_i16_1(i16 %arg1, i16 %arg2) {
+entry:
+ %A = mul i16 %arg2, %arg1
+ ret i16 %A
+}
+
+define i16 @mul_i16_2(i16 %arg1, i16 %arg2) {
+entry:
+ %A = mul i16 %arg1, %arg2
+ ret i16 %A
+}
+
+define i8 @mul_i8_1(i8 %arg1, i8 %arg2) {
+entry:
+ %A = mul i8 %arg2, %arg1
+ ret i8 %A
+}
+
+define i8 @mul_i8_2(i8 %arg1, i8 %arg2) {
+entry:
+ %A = mul i8 %arg1, %arg2
+ ret i8 %A
+}
diff --git a/test/CodeGen/CellSPU/nand.ll b/test/CodeGen/CellSPU/nand.ll
new file mode 100644
index 0000000..e141923
--- /dev/null
+++ b/test/CodeGen/CellSPU/nand.ll
@@ -0,0 +1,121 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep nand %t1.s | count 90
+; RUN: grep and %t1.s | count 94
+; RUN: grep xsbh %t1.s | count 2
+; RUN: grep xshw %t1.s | count 4
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define <4 x i32> @nand_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %A = and <4 x i32> %arg2, %arg1 ; <<4 x i32>> [#uses=1]
+ %B = xor <4 x i32> %A, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ ret <4 x i32> %B
+}
+
+define <4 x i32> @nand_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %A = and <4 x i32> %arg1, %arg2 ; <<4 x i32>> [#uses=1]
+ %B = xor <4 x i32> %A, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ ret <4 x i32> %B
+}
+
+define <8 x i16> @nand_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
+ %A = and <8 x i16> %arg2, %arg1 ; <<8 x i16>> [#uses=1]
+ %B = xor <8 x i16> %A, < i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1, i16 -1 >
+ ret <8 x i16> %B
+}
+
+define <8 x i16> @nand_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
+ %A = and <8 x i16> %arg1, %arg2 ; <<8 x i16>> [#uses=1]
+ %B = xor <8 x i16> %A, < i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1, i16 -1 >
+ ret <8 x i16> %B
+}
+
+define <16 x i8> @nand_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
+ %A = and <16 x i8> %arg2, %arg1 ; <<16 x i8>> [#uses=1]
+ %B = xor <16 x i8> %A, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ ret <16 x i8> %B
+}
+
+define <16 x i8> @nand_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
+ %A = and <16 x i8> %arg1, %arg2 ; <<16 x i8>> [#uses=1]
+ %B = xor <16 x i8> %A, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ ret <16 x i8> %B
+}
+
+define i32 @nand_i32_1(i32 %arg1, i32 %arg2) {
+ %A = and i32 %arg2, %arg1 ; <i32> [#uses=1]
+ %B = xor i32 %A, -1 ; <i32> [#uses=1]
+ ret i32 %B
+}
+
+define i32 @nand_i32_2(i32 %arg1, i32 %arg2) {
+ %A = and i32 %arg1, %arg2 ; <i32> [#uses=1]
+ %B = xor i32 %A, -1 ; <i32> [#uses=1]
+ ret i32 %B
+}
+
+define i16 @nand_i16_1(i16 signext %arg1, i16 signext %arg2) signext {
+ %A = and i16 %arg2, %arg1 ; <i16> [#uses=1]
+ %B = xor i16 %A, -1 ; <i16> [#uses=1]
+ ret i16 %B
+}
+
+define i16 @nand_i16_2(i16 signext %arg1, i16 signext %arg2) signext {
+ %A = and i16 %arg1, %arg2 ; <i16> [#uses=1]
+ %B = xor i16 %A, -1 ; <i16> [#uses=1]
+ ret i16 %B
+}
+
+define i16 @nand_i16u_1(i16 zeroext %arg1, i16 zeroext %arg2) zeroext {
+ %A = and i16 %arg2, %arg1 ; <i16> [#uses=1]
+ %B = xor i16 %A, -1 ; <i16> [#uses=1]
+ ret i16 %B
+}
+
+define i16 @nand_i16u_2(i16 zeroext %arg1, i16 zeroext %arg2) zeroext {
+ %A = and i16 %arg1, %arg2 ; <i16> [#uses=1]
+ %B = xor i16 %A, -1 ; <i16> [#uses=1]
+ ret i16 %B
+}
+
+define i8 @nand_i8u_1(i8 zeroext %arg1, i8 zeroext %arg2) zeroext {
+ %A = and i8 %arg2, %arg1 ; <i8> [#uses=1]
+ %B = xor i8 %A, -1 ; <i8> [#uses=1]
+ ret i8 %B
+}
+
+define i8 @nand_i8u_2(i8 zeroext %arg1, i8 zeroext %arg2) zeroext {
+ %A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %B = xor i8 %A, -1 ; <i8> [#uses=1]
+ ret i8 %B
+}
+
+define i8 @nand_i8_1(i8 signext %arg1, i8 signext %arg2) signext {
+ %A = and i8 %arg2, %arg1 ; <i8> [#uses=1]
+ %B = xor i8 %A, -1 ; <i8> [#uses=1]
+ ret i8 %B
+}
+
+define i8 @nand_i8_2(i8 signext %arg1, i8 signext %arg2) signext {
+ %A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %B = xor i8 %A, -1 ; <i8> [#uses=1]
+ ret i8 %B
+}
+
+define i8 @nand_i8_3(i8 %arg1, i8 %arg2) {
+ %A = and i8 %arg2, %arg1 ; <i8> [#uses=1]
+ %B = xor i8 %A, -1 ; <i8> [#uses=1]
+ ret i8 %B
+}
+
+define i8 @nand_i8_4(i8 %arg1, i8 %arg2) {
+ %A = and i8 %arg1, %arg2 ; <i8> [#uses=1]
+ %B = xor i8 %A, -1 ; <i8> [#uses=1]
+ ret i8 %B
+}
diff --git a/test/CodeGen/CellSPU/or_ops.ll b/test/CodeGen/CellSPU/or_ops.ll
new file mode 100644
index 0000000..8aa1e99
--- /dev/null
+++ b/test/CodeGen/CellSPU/or_ops.ll
@@ -0,0 +1,264 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep and %t1.s | count 2
+; RUN: grep orc %t1.s | count 85
+; RUN: grep ori %t1.s | count 30
+; RUN: grep orhi %t1.s | count 30
+; RUN: grep orbi %t1.s | count 15
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; OR instruction generation:
+define <4 x i32> @or_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %A = or <4 x i32> %arg1, %arg2
+ ret <4 x i32> %A
+}
+
+define <4 x i32> @or_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %A = or <4 x i32> %arg2, %arg1
+ ret <4 x i32> %A
+}
+
+define <8 x i16> @or_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
+ %A = or <8 x i16> %arg1, %arg2
+ ret <8 x i16> %A
+}
+
+define <8 x i16> @or_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
+ %A = or <8 x i16> %arg2, %arg1
+ ret <8 x i16> %A
+}
+
+define <16 x i8> @or_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
+ %A = or <16 x i8> %arg2, %arg1
+ ret <16 x i8> %A
+}
+
+define <16 x i8> @or_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
+ %A = or <16 x i8> %arg1, %arg2
+ ret <16 x i8> %A
+}
+
+define i32 @or_i32_1(i32 %arg1, i32 %arg2) {
+ %A = or i32 %arg2, %arg1
+ ret i32 %A
+}
+
+define i32 @or_i32_2(i32 %arg1, i32 %arg2) {
+ %A = or i32 %arg1, %arg2
+ ret i32 %A
+}
+
+define i16 @or_i16_1(i16 %arg1, i16 %arg2) {
+ %A = or i16 %arg2, %arg1
+ ret i16 %A
+}
+
+define i16 @or_i16_2(i16 %arg1, i16 %arg2) {
+ %A = or i16 %arg1, %arg2
+ ret i16 %A
+}
+
+define i8 @or_i8_1(i8 %arg1, i8 %arg2) {
+ %A = or i8 %arg2, %arg1
+ ret i8 %A
+}
+
+define i8 @or_i8_2(i8 %arg1, i8 %arg2) {
+ %A = or i8 %arg1, %arg2
+ ret i8 %A
+}
+
+; ORC instruction generation:
+define <4 x i32> @orc_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %A = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ %B = or <4 x i32> %arg1, %A
+ ret <4 x i32> %B
+}
+
+define <4 x i32> @orc_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ %B = or <4 x i32> %arg2, %A
+ ret <4 x i32> %B
+}
+
+define <4 x i32> @orc_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) {
+ %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ %B = or <4 x i32> %A, %arg2
+ ret <4 x i32> %B
+}
+
+define <8 x i16> @orc_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
+ %A = xor <8 x i16> %arg2, < i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1, i16 -1 >
+ %B = or <8 x i16> %arg1, %A
+ ret <8 x i16> %B
+}
+
+define <8 x i16> @orc_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
+ %A = xor <8 x i16> %arg1, < i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1, i16 -1 >
+ %B = or <8 x i16> %arg2, %A
+ ret <8 x i16> %B
+}
+
+define <16 x i8> @orc_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
+ %A = xor <16 x i8> %arg1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ %B = or <16 x i8> %arg2, %A
+ ret <16 x i8> %B
+}
+
+define <16 x i8> @orc_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
+ %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ %B = or <16 x i8> %arg1, %A
+ ret <16 x i8> %B
+}
+
+define <16 x i8> @orc_v16i8_3(<16 x i8> %arg1, <16 x i8> %arg2) {
+ %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ %B = or <16 x i8> %A, %arg1
+ ret <16 x i8> %B
+}
+
+define i32 @orc_i32_1(i32 %arg1, i32 %arg2) {
+ %A = xor i32 %arg2, -1
+ %B = or i32 %A, %arg1
+ ret i32 %B
+}
+
+define i32 @orc_i32_2(i32 %arg1, i32 %arg2) {
+ %A = xor i32 %arg1, -1
+ %B = or i32 %A, %arg2
+ ret i32 %B
+}
+
+define i32 @orc_i32_3(i32 %arg1, i32 %arg2) {
+ %A = xor i32 %arg2, -1
+ %B = or i32 %arg1, %A
+ ret i32 %B
+}
+
+define i16 @orc_i16_1(i16 %arg1, i16 %arg2) {
+ %A = xor i16 %arg2, -1
+ %B = or i16 %A, %arg1
+ ret i16 %B
+}
+
+define i16 @orc_i16_2(i16 %arg1, i16 %arg2) {
+ %A = xor i16 %arg1, -1
+ %B = or i16 %A, %arg2
+ ret i16 %B
+}
+
+define i16 @orc_i16_3(i16 %arg1, i16 %arg2) {
+ %A = xor i16 %arg2, -1
+ %B = or i16 %arg1, %A
+ ret i16 %B
+}
+
+define i8 @orc_i8_1(i8 %arg1, i8 %arg2) {
+ %A = xor i8 %arg2, -1
+ %B = or i8 %A, %arg1
+ ret i8 %B
+}
+
+define i8 @orc_i8_2(i8 %arg1, i8 %arg2) {
+ %A = xor i8 %arg1, -1
+ %B = or i8 %A, %arg2
+ ret i8 %B
+}
+
+define i8 @orc_i8_3(i8 %arg1, i8 %arg2) {
+ %A = xor i8 %arg2, -1
+ %B = or i8 %arg1, %A
+ ret i8 %B
+}
+
+; ORI instruction generation (i32 data type):
+define <4 x i32> @ori_v4i32_1(<4 x i32> %in) {
+ %tmp2 = or <4 x i32> %in, < i32 511, i32 511, i32 511, i32 511 >
+ ret <4 x i32> %tmp2
+}
+
+define <4 x i32> @ori_v4i32_2(<4 x i32> %in) {
+ %tmp2 = or <4 x i32> %in, < i32 510, i32 510, i32 510, i32 510 >
+ ret <4 x i32> %tmp2
+}
+
+define <4 x i32> @ori_v4i32_3(<4 x i32> %in) {
+ %tmp2 = or <4 x i32> %in, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ ret <4 x i32> %tmp2
+}
+
+define <4 x i32> @ori_v4i32_4(<4 x i32> %in) {
+ %tmp2 = or <4 x i32> %in, < i32 -512, i32 -512, i32 -512, i32 -512 >
+ ret <4 x i32> %tmp2
+}
+
+define i32 @ori_u32(i32 zeroext %in) zeroext {
+ %tmp37 = or i32 %in, 37 ; <i32> [#uses=1]
+ ret i32 %tmp37
+}
+
+define i32 @ori_i32(i32 signext %in) signext {
+ %tmp38 = or i32 %in, 37 ; <i32> [#uses=1]
+ ret i32 %tmp38
+}
+
+; ORHI instruction generation (i16 data type):
+define <8 x i16> @orhi_v8i16_1(<8 x i16> %in) {
+ %tmp2 = or <8 x i16> %in, < i16 511, i16 511, i16 511, i16 511,
+ i16 511, i16 511, i16 511, i16 511 >
+ ret <8 x i16> %tmp2
+}
+
+define <8 x i16> @orhi_v8i16_2(<8 x i16> %in) {
+ %tmp2 = or <8 x i16> %in, < i16 510, i16 510, i16 510, i16 510,
+ i16 510, i16 510, i16 510, i16 510 >
+ ret <8 x i16> %tmp2
+}
+
+define <8 x i16> @orhi_v8i16_3(<8 x i16> %in) {
+ %tmp2 = or <8 x i16> %in, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1 >
+ ret <8 x i16> %tmp2
+}
+
+define <8 x i16> @orhi_v8i16_4(<8 x i16> %in) {
+ %tmp2 = or <8 x i16> %in, < i16 -512, i16 -512, i16 -512, i16 -512,
+ i16 -512, i16 -512, i16 -512, i16 -512 >
+ ret <8 x i16> %tmp2
+}
+
+define i16 @orhi_u16(i16 zeroext %in) zeroext {
+ %tmp37 = or i16 %in, 37 ; <i16> [#uses=1]
+ ret i16 %tmp37
+}
+
+define i16 @orhi_i16(i16 signext %in) signext {
+ %tmp38 = or i16 %in, 37 ; <i16> [#uses=1]
+ ret i16 %tmp38
+}
+
+; ORBI instruction generation (i8 data type):
+define <16 x i8> @orbi_v16i8(<16 x i8> %in) {
+ %tmp2 = or <16 x i8> %in, < i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
+ i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
+ i8 42, i8 42, i8 42, i8 42 >
+ ret <16 x i8> %tmp2
+}
+
+define i8 @orbi_u8(i8 zeroext %in) zeroext {
+ %tmp37 = or i8 %in, 37 ; <i8> [#uses=1]
+ ret i8 %tmp37
+}
+
+define i8 @orbi_i8(i8 signext %in) signext {
+ %tmp38 = or i8 %in, 37 ; <i8> [#uses=1]
+ ret i8 %tmp38
+}
diff --git a/test/CodeGen/CellSPU/private.ll b/test/CodeGen/CellSPU/private.ll
new file mode 100644
index 0000000..56f72e7
--- /dev/null
+++ b/test/CodeGen/CellSPU/private.ll
@@ -0,0 +1,22 @@
+; Test to make sure that the 'private' is used correctly.
+;
+; RUN: llc < %s -march=cellspu > %t
+; RUN: grep .Lfoo: %t
+; RUN: grep brsl.*\.Lfoo %t
+; RUN: grep .Lbaz: %t
+; RUN: grep ila.*\.Lbaz %t
+
+
+declare void @foo()
+
+define private void @foo() {
+ ret void
+}
+
+@baz = private global i32 4
+
+define i32 @bar() {
+ call void @foo()
+ %1 = load i32* @baz, align 4
+ ret i32 %1
+}
diff --git a/test/CodeGen/CellSPU/rotate_ops.ll b/test/CodeGen/CellSPU/rotate_ops.ll
new file mode 100644
index 0000000..a504c00
--- /dev/null
+++ b/test/CodeGen/CellSPU/rotate_ops.ll
@@ -0,0 +1,160 @@
+; RUN: llc < %s -march=cellspu -o %t1.s
+; RUN: grep rot %t1.s | count 85
+; RUN: grep roth %t1.s | count 8
+; RUN: grep roti.*5 %t1.s | count 1
+; RUN: grep roti.*27 %t1.s | count 1
+; RUN grep rothi.*5 %t1.s | count 2
+; RUN grep rothi.*11 %t1.s | count 1
+; RUN grep rothi.*,.3 %t1.s | count 1
+; RUN: grep andhi %t1.s | count 4
+; RUN: grep shlhi %t1.s | count 4
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; Vector rotates are not currently supported in gcc or llvm assembly. These are
+; not tested.
+
+; 32-bit rotates:
+define i32 @rotl32_1a(i32 %arg1, i8 %arg2) {
+ %tmp1 = zext i8 %arg2 to i32 ; <i32> [#uses=1]
+ %B = shl i32 %arg1, %tmp1 ; <i32> [#uses=1]
+ %arg22 = sub i8 32, %arg2 ; <i8> [#uses=1]
+ %tmp2 = zext i8 %arg22 to i32 ; <i32> [#uses=1]
+ %C = lshr i32 %arg1, %tmp2 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+define i32 @rotl32_1b(i32 %arg1, i16 %arg2) {
+ %tmp1 = zext i16 %arg2 to i32 ; <i32> [#uses=1]
+ %B = shl i32 %arg1, %tmp1 ; <i32> [#uses=1]
+ %arg22 = sub i16 32, %arg2 ; <i8> [#uses=1]
+ %tmp2 = zext i16 %arg22 to i32 ; <i32> [#uses=1]
+ %C = lshr i32 %arg1, %tmp2 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+define i32 @rotl32_2(i32 %arg1, i32 %arg2) {
+ %B = shl i32 %arg1, %arg2 ; <i32> [#uses=1]
+ %tmp1 = sub i32 32, %arg2 ; <i32> [#uses=1]
+ %C = lshr i32 %arg1, %tmp1 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+define i32 @rotl32_3(i32 %arg1, i32 %arg2) {
+ %tmp1 = sub i32 32, %arg2 ; <i32> [#uses=1]
+ %B = shl i32 %arg1, %arg2 ; <i32> [#uses=1]
+ %C = lshr i32 %arg1, %tmp1 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+define i32 @rotl32_4(i32 %arg1, i32 %arg2) {
+ %tmp1 = sub i32 32, %arg2 ; <i32> [#uses=1]
+ %C = lshr i32 %arg1, %tmp1 ; <i32> [#uses=1]
+ %B = shl i32 %arg1, %arg2 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+define i32 @rotr32_1(i32 %A, i8 %Amt) {
+ %tmp1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
+ %B = lshr i32 %A, %tmp1 ; <i32> [#uses=1]
+ %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
+ %tmp2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
+ %C = shl i32 %A, %tmp2 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+define i32 @rotr32_2(i32 %A, i8 %Amt) {
+ %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
+ %tmp1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
+ %B = lshr i32 %A, %tmp1 ; <i32> [#uses=1]
+ %tmp2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
+ %C = shl i32 %A, %tmp2 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+; Rotate left with immediate
+define i32 @rotli32(i32 %A) {
+ %B = shl i32 %A, 5 ; <i32> [#uses=1]
+ %C = lshr i32 %A, 27 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+; Rotate right with immediate
+define i32 @rotri32(i32 %A) {
+ %B = lshr i32 %A, 5 ; <i32> [#uses=1]
+ %C = shl i32 %A, 27 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+; 16-bit rotates:
+define i16 @rotr16_1(i16 %arg1, i8 %arg) {
+ %tmp1 = zext i8 %arg to i16 ; <i16> [#uses=1]
+ %B = lshr i16 %arg1, %tmp1 ; <i16> [#uses=1]
+ %arg2 = sub i8 16, %arg ; <i8> [#uses=1]
+ %tmp2 = zext i8 %arg2 to i16 ; <i16> [#uses=1]
+ %C = shl i16 %arg1, %tmp2 ; <i16> [#uses=1]
+ %D = or i16 %B, %C ; <i16> [#uses=1]
+ ret i16 %D
+}
+
+define i16 @rotr16_2(i16 %arg1, i16 %arg) {
+ %B = lshr i16 %arg1, %arg ; <i16> [#uses=1]
+ %tmp1 = sub i16 16, %arg ; <i16> [#uses=1]
+ %C = shl i16 %arg1, %tmp1 ; <i16> [#uses=1]
+ %D = or i16 %B, %C ; <i16> [#uses=1]
+ ret i16 %D
+}
+
+define i16 @rotli16(i16 %A) {
+ %B = shl i16 %A, 5 ; <i16> [#uses=1]
+ %C = lshr i16 %A, 11 ; <i16> [#uses=1]
+ %D = or i16 %B, %C ; <i16> [#uses=1]
+ ret i16 %D
+}
+
+define i16 @rotri16(i16 %A) {
+ %B = lshr i16 %A, 5 ; <i16> [#uses=1]
+ %C = shl i16 %A, 11 ; <i16> [#uses=1]
+ %D = or i16 %B, %C ; <i16> [#uses=1]
+ ret i16 %D
+}
+
+define i8 @rotl8(i8 %A, i8 %Amt) {
+ %B = shl i8 %A, %Amt ; <i8> [#uses=1]
+ %Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
+ %C = lshr i8 %A, %Amt2 ; <i8> [#uses=1]
+ %D = or i8 %B, %C ; <i8> [#uses=1]
+ ret i8 %D
+}
+
+define i8 @rotr8(i8 %A, i8 %Amt) {
+ %B = lshr i8 %A, %Amt ; <i8> [#uses=1]
+ %Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
+ %C = shl i8 %A, %Amt2 ; <i8> [#uses=1]
+ %D = or i8 %B, %C ; <i8> [#uses=1]
+ ret i8 %D
+}
+
+define i8 @rotli8(i8 %A) {
+ %B = shl i8 %A, 5 ; <i8> [#uses=1]
+ %C = lshr i8 %A, 3 ; <i8> [#uses=1]
+ %D = or i8 %B, %C ; <i8> [#uses=1]
+ ret i8 %D
+}
+
+define i8 @rotri8(i8 %A) {
+ %B = lshr i8 %A, 5 ; <i8> [#uses=1]
+ %C = shl i8 %A, 3 ; <i8> [#uses=1]
+ %D = or i8 %B, %C ; <i8> [#uses=1]
+ ret i8 %D
+}
diff --git a/test/CodeGen/CellSPU/select_bits.ll b/test/CodeGen/CellSPU/select_bits.ll
new file mode 100644
index 0000000..c804256
--- /dev/null
+++ b/test/CodeGen/CellSPU/select_bits.ll
@@ -0,0 +1,569 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep selb %t1.s | count 56
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+; v2i64
+;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+
+; (or (and rC, rB), (and (not rC), rA))
+define <2 x i64> @selectbits_v2i64_01(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
+ %C = and <2 x i64> %rC, %rB
+ %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
+ %B = and <2 x i64> %A, %rA
+ %D = or <2 x i64> %C, %B
+ ret <2 x i64> %D
+}
+
+; (or (and rB, rC), (and (not rC), rA))
+define <2 x i64> @selectbits_v2i64_02(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
+ %C = and <2 x i64> %rB, %rC
+ %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
+ %B = and <2 x i64> %A, %rA
+ %D = or <2 x i64> %C, %B
+ ret <2 x i64> %D
+}
+
+; (or (and (not rC), rA), (and rB, rC))
+define <2 x i64> @selectbits_v2i64_03(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
+ %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
+ %B = and <2 x i64> %A, %rA
+ %C = and <2 x i64> %rB, %rC
+ %D = or <2 x i64> %C, %B
+ ret <2 x i64> %D
+}
+
+; (or (and (not rC), rA), (and rC, rB))
+define <2 x i64> @selectbits_v2i64_04(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
+ %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
+ %B = and <2 x i64> %A, %rA
+ %C = and <2 x i64> %rC, %rB
+ %D = or <2 x i64> %C, %B
+ ret <2 x i64> %D
+}
+
+; (or (and rC, rB), (and rA, (not rC)))
+define <2 x i64> @selectbits_v2i64_05(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
+ %C = and <2 x i64> %rC, %rB
+ %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
+ %B = and <2 x i64> %rA, %A
+ %D = or <2 x i64> %C, %B
+ ret <2 x i64> %D
+}
+
+; (or (and rB, rC), (and rA, (not rC)))
+define <2 x i64> @selectbits_v2i64_06(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
+ %C = and <2 x i64> %rB, %rC
+ %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
+ %B = and <2 x i64> %rA, %A
+ %D = or <2 x i64> %C, %B
+ ret <2 x i64> %D
+}
+
+; (or (and rA, (not rC)), (and rB, rC))
+define <2 x i64> @selectbits_v2i64_07(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
+ %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
+ %B = and <2 x i64> %rA, %A
+ %C = and <2 x i64> %rB, %rC
+ %D = or <2 x i64> %C, %B
+ ret <2 x i64> %D
+}
+
+; (or (and rA, (not rC)), (and rC, rB))
+define <2 x i64> @selectbits_v2i64_08(<2 x i64> %rA, <2 x i64> %rB, <2 x i64> %rC) {
+ %A = xor <2 x i64> %rC, < i64 -1, i64 -1 >
+ %B = and <2 x i64> %rA, %A
+ %C = and <2 x i64> %rC, %rB
+ %D = or <2 x i64> %C, %B
+ ret <2 x i64> %D
+}
+
+;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+; v4i32
+;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+
+; (or (and rC, rB), (and (not rC), rA))
+define <4 x i32> @selectbits_v4i32_01(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
+ %C = and <4 x i32> %rC, %rB
+ %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ %B = and <4 x i32> %A, %rA
+ %D = or <4 x i32> %C, %B
+ ret <4 x i32> %D
+}
+
+; (or (and rB, rC), (and (not rC), rA))
+define <4 x i32> @selectbits_v4i32_02(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
+ %C = and <4 x i32> %rB, %rC
+ %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ %B = and <4 x i32> %A, %rA
+ %D = or <4 x i32> %C, %B
+ ret <4 x i32> %D
+}
+
+; (or (and (not rC), rA), (and rB, rC))
+define <4 x i32> @selectbits_v4i32_03(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
+ %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1 >
+ %B = and <4 x i32> %A, %rA
+ %C = and <4 x i32> %rB, %rC
+ %D = or <4 x i32> %C, %B
+ ret <4 x i32> %D
+}
+
+; (or (and (not rC), rA), (and rC, rB))
+define <4 x i32> @selectbits_v4i32_04(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
+ %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
+ %B = and <4 x i32> %A, %rA
+ %C = and <4 x i32> %rC, %rB
+ %D = or <4 x i32> %C, %B
+ ret <4 x i32> %D
+}
+
+; (or (and rC, rB), (and rA, (not rC)))
+define <4 x i32> @selectbits_v4i32_05(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
+ %C = and <4 x i32> %rC, %rB
+ %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
+ %B = and <4 x i32> %rA, %A
+ %D = or <4 x i32> %C, %B
+ ret <4 x i32> %D
+}
+
+; (or (and rB, rC), (and rA, (not rC)))
+define <4 x i32> @selectbits_v4i32_06(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
+ %C = and <4 x i32> %rB, %rC
+ %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
+ %B = and <4 x i32> %rA, %A
+ %D = or <4 x i32> %C, %B
+ ret <4 x i32> %D
+}
+
+; (or (and rA, (not rC)), (and rB, rC))
+define <4 x i32> @selectbits_v4i32_07(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
+ %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
+ %B = and <4 x i32> %rA, %A
+ %C = and <4 x i32> %rB, %rC
+ %D = or <4 x i32> %C, %B
+ ret <4 x i32> %D
+}
+
+; (or (and rA, (not rC)), (and rC, rB))
+define <4 x i32> @selectbits_v4i32_08(<4 x i32> %rA, <4 x i32> %rB, <4 x i32> %rC) {
+ %A = xor <4 x i32> %rC, < i32 -1, i32 -1, i32 -1, i32 -1>
+ %B = and <4 x i32> %rA, %A
+ %C = and <4 x i32> %rC, %rB
+ %D = or <4 x i32> %C, %B
+ ret <4 x i32> %D
+}
+
+;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+; v8i16
+;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+
+; (or (and rC, rB), (and (not rC), rA))
+define <8 x i16> @selectbits_v8i16_01(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
+ %C = and <8 x i16> %rC, %rB
+ %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1, i16 -1 >
+ %B = and <8 x i16> %A, %rA
+ %D = or <8 x i16> %C, %B
+ ret <8 x i16> %D
+}
+
+; (or (and rB, rC), (and (not rC), rA))
+define <8 x i16> @selectbits_v8i16_02(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
+ %C = and <8 x i16> %rB, %rC
+ %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1, i16 -1 >
+ %B = and <8 x i16> %A, %rA
+ %D = or <8 x i16> %C, %B
+ ret <8 x i16> %D
+}
+
+; (or (and (not rC), rA), (and rB, rC))
+define <8 x i16> @selectbits_v8i16_03(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
+ %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1, i16 -1 >
+ %B = and <8 x i16> %A, %rA
+ %C = and <8 x i16> %rB, %rC
+ %D = or <8 x i16> %C, %B
+ ret <8 x i16> %D
+}
+
+; (or (and (not rC), rA), (and rC, rB))
+define <8 x i16> @selectbits_v8i16_04(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
+ %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1, i16 -1 >
+ %B = and <8 x i16> %A, %rA
+ %C = and <8 x i16> %rC, %rB
+ %D = or <8 x i16> %C, %B
+ ret <8 x i16> %D
+}
+
+; (or (and rC, rB), (and rA, (not rC)))
+define <8 x i16> @selectbits_v8i16_05(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
+ %C = and <8 x i16> %rC, %rB
+ %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1, i16 -1 >
+ %B = and <8 x i16> %rA, %A
+ %D = or <8 x i16> %C, %B
+ ret <8 x i16> %D
+}
+
+; (or (and rB, rC), (and rA, (not rC)))
+define <8 x i16> @selectbits_v8i16_06(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
+ %C = and <8 x i16> %rB, %rC
+ %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1, i16 -1 >
+ %B = and <8 x i16> %rA, %A
+ %D = or <8 x i16> %C, %B
+ ret <8 x i16> %D
+}
+
+; (or (and rA, (not rC)), (and rB, rC))
+define <8 x i16> @selectbits_v8i16_07(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
+ %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1, i16 -1 >
+ %B = and <8 x i16> %rA, %A
+ %C = and <8 x i16> %rB, %rC
+ %D = or <8 x i16> %C, %B
+ ret <8 x i16> %D
+}
+
+; (or (and rA, (not rC)), (and rC, rB))
+define <8 x i16> @selectbits_v8i16_08(<8 x i16> %rA, <8 x i16> %rB, <8 x i16> %rC) {
+ %A = xor <8 x i16> %rC, < i16 -1, i16 -1, i16 -1, i16 -1,
+ i16 -1, i16 -1, i16 -1, i16 -1 >
+ %B = and <8 x i16> %rA, %A
+ %C = and <8 x i16> %rC, %rB
+ %D = or <8 x i16> %C, %B
+ ret <8 x i16> %D
+}
+
+;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+; v16i8
+;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+
+; (or (and rC, rB), (and (not rC), rA))
+define <16 x i8> @selectbits_v16i8_01(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
+ %C = and <16 x i8> %rC, %rB
+ %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ %B = and <16 x i8> %A, %rA
+ %D = or <16 x i8> %C, %B
+ ret <16 x i8> %D
+}
+
+; (or (and rB, rC), (and (not rC), rA))
+define <16 x i8> @selectbits_v16i8_02(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
+ %C = and <16 x i8> %rB, %rC
+ %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ %B = and <16 x i8> %A, %rA
+ %D = or <16 x i8> %C, %B
+ ret <16 x i8> %D
+}
+
+; (or (and (not rC), rA), (and rB, rC))
+define <16 x i8> @selectbits_v16i8_03(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
+ %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ %B = and <16 x i8> %A, %rA
+ %C = and <16 x i8> %rB, %rC
+ %D = or <16 x i8> %C, %B
+ ret <16 x i8> %D
+}
+
+; (or (and (not rC), rA), (and rC, rB))
+define <16 x i8> @selectbits_v16i8_04(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
+ %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ %B = and <16 x i8> %A, %rA
+ %C = and <16 x i8> %rC, %rB
+ %D = or <16 x i8> %C, %B
+ ret <16 x i8> %D
+}
+
+; (or (and rC, rB), (and rA, (not rC)))
+define <16 x i8> @selectbits_v16i8_05(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
+ %C = and <16 x i8> %rC, %rB
+ %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ %B = and <16 x i8> %rA, %A
+ %D = or <16 x i8> %C, %B
+ ret <16 x i8> %D
+}
+
+; (or (and rB, rC), (and rA, (not rC)))
+define <16 x i8> @selectbits_v16i8_06(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
+ %C = and <16 x i8> %rB, %rC
+ %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ %B = and <16 x i8> %rA, %A
+ %D = or <16 x i8> %C, %B
+ ret <16 x i8> %D
+}
+
+; (or (and rA, (not rC)), (and rB, rC))
+define <16 x i8> @selectbits_v16i8_07(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
+ %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ %B = and <16 x i8> %rA, %A
+ %C = and <16 x i8> %rB, %rC
+ %D = or <16 x i8> %C, %B
+ ret <16 x i8> %D
+}
+
+; (or (and rA, (not rC)), (and rC, rB))
+define <16 x i8> @selectbits_v16i8_08(<16 x i8> %rA, <16 x i8> %rB, <16 x i8> %rC) {
+ %A = xor <16 x i8> %rC, < i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1,
+ i8 -1, i8 -1, i8 -1, i8 -1 >
+ %B = and <16 x i8> %rA, %A
+ %C = and <16 x i8> %rC, %rB
+ %D = or <16 x i8> %C, %B
+ ret <16 x i8> %D
+}
+
+;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+; i32
+;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+
+; (or (and rC, rB), (and (not rC), rA))
+define i32 @selectbits_i32_01(i32 %rA, i32 %rB, i32 %rC) {
+ %C = and i32 %rC, %rB
+ %A = xor i32 %rC, -1
+ %B = and i32 %A, %rA
+ %D = or i32 %C, %B
+ ret i32 %D
+}
+
+; (or (and rB, rC), (and (not rC), rA))
+define i32 @selectbits_i32_02(i32 %rA, i32 %rB, i32 %rC) {
+ %C = and i32 %rB, %rC
+ %A = xor i32 %rC, -1
+ %B = and i32 %A, %rA
+ %D = or i32 %C, %B
+ ret i32 %D
+}
+
+; (or (and (not rC), rA), (and rB, rC))
+define i32 @selectbits_i32_03(i32 %rA, i32 %rB, i32 %rC) {
+ %A = xor i32 %rC, -1
+ %B = and i32 %A, %rA
+ %C = and i32 %rB, %rC
+ %D = or i32 %C, %B
+ ret i32 %D
+}
+
+; (or (and (not rC), rA), (and rC, rB))
+define i32 @selectbits_i32_04(i32 %rA, i32 %rB, i32 %rC) {
+ %A = xor i32 %rC, -1
+ %B = and i32 %A, %rA
+ %C = and i32 %rC, %rB
+ %D = or i32 %C, %B
+ ret i32 %D
+}
+
+; (or (and rC, rB), (and rA, (not rC)))
+define i32 @selectbits_i32_05(i32 %rA, i32 %rB, i32 %rC) {
+ %C = and i32 %rC, %rB
+ %A = xor i32 %rC, -1
+ %B = and i32 %rA, %A
+ %D = or i32 %C, %B
+ ret i32 %D
+}
+
+; (or (and rB, rC), (and rA, (not rC)))
+define i32 @selectbits_i32_06(i32 %rA, i32 %rB, i32 %rC) {
+ %C = and i32 %rB, %rC
+ %A = xor i32 %rC, -1
+ %B = and i32 %rA, %A
+ %D = or i32 %C, %B
+ ret i32 %D
+}
+
+; (or (and rA, (not rC)), (and rB, rC))
+define i32 @selectbits_i32_07(i32 %rA, i32 %rB, i32 %rC) {
+ %A = xor i32 %rC, -1
+ %B = and i32 %rA, %A
+ %C = and i32 %rB, %rC
+ %D = or i32 %C, %B
+ ret i32 %D
+}
+
+; (or (and rA, (not rC)), (and rC, rB))
+define i32 @selectbits_i32_08(i32 %rA, i32 %rB, i32 %rC) {
+ %A = xor i32 %rC, -1
+ %B = and i32 %rA, %A
+ %C = and i32 %rC, %rB
+ %D = or i32 %C, %B
+ ret i32 %D
+}
+
+;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+; i16
+;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+
+; (or (and rC, rB), (and (not rC), rA))
+define i16 @selectbits_i16_01(i16 %rA, i16 %rB, i16 %rC) {
+ %C = and i16 %rC, %rB
+ %A = xor i16 %rC, -1
+ %B = and i16 %A, %rA
+ %D = or i16 %C, %B
+ ret i16 %D
+}
+
+; (or (and rB, rC), (and (not rC), rA))
+define i16 @selectbits_i16_02(i16 %rA, i16 %rB, i16 %rC) {
+ %C = and i16 %rB, %rC
+ %A = xor i16 %rC, -1
+ %B = and i16 %A, %rA
+ %D = or i16 %C, %B
+ ret i16 %D
+}
+
+; (or (and (not rC), rA), (and rB, rC))
+define i16 @selectbits_i16_03(i16 %rA, i16 %rB, i16 %rC) {
+ %A = xor i16 %rC, -1
+ %B = and i16 %A, %rA
+ %C = and i16 %rB, %rC
+ %D = or i16 %C, %B
+ ret i16 %D
+}
+
+; (or (and (not rC), rA), (and rC, rB))
+define i16 @selectbits_i16_04(i16 %rA, i16 %rB, i16 %rC) {
+ %A = xor i16 %rC, -1
+ %B = and i16 %A, %rA
+ %C = and i16 %rC, %rB
+ %D = or i16 %C, %B
+ ret i16 %D
+}
+
+; (or (and rC, rB), (and rA, (not rC)))
+define i16 @selectbits_i16_05(i16 %rA, i16 %rB, i16 %rC) {
+ %C = and i16 %rC, %rB
+ %A = xor i16 %rC, -1
+ %B = and i16 %rA, %A
+ %D = or i16 %C, %B
+ ret i16 %D
+}
+
+; (or (and rB, rC), (and rA, (not rC)))
+define i16 @selectbits_i16_06(i16 %rA, i16 %rB, i16 %rC) {
+ %C = and i16 %rB, %rC
+ %A = xor i16 %rC, -1
+ %B = and i16 %rA, %A
+ %D = or i16 %C, %B
+ ret i16 %D
+}
+
+; (or (and rA, (not rC)), (and rB, rC))
+define i16 @selectbits_i16_07(i16 %rA, i16 %rB, i16 %rC) {
+ %A = xor i16 %rC, -1
+ %B = and i16 %rA, %A
+ %C = and i16 %rB, %rC
+ %D = or i16 %C, %B
+ ret i16 %D
+}
+
+; (or (and rA, (not rC)), (and rC, rB))
+define i16 @selectbits_i16_08(i16 %rA, i16 %rB, i16 %rC) {
+ %A = xor i16 %rC, -1
+ %B = and i16 %rA, %A
+ %C = and i16 %rC, %rB
+ %D = or i16 %C, %B
+ ret i16 %D
+}
+
+;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+; i8
+;-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
+
+; (or (and rC, rB), (and (not rC), rA))
+define i8 @selectbits_i8_01(i8 %rA, i8 %rB, i8 %rC) {
+ %C = and i8 %rC, %rB
+ %A = xor i8 %rC, -1
+ %B = and i8 %A, %rA
+ %D = or i8 %C, %B
+ ret i8 %D
+}
+
+; (or (and rB, rC), (and (not rC), rA))
+define i8 @selectbits_i8_02(i8 %rA, i8 %rB, i8 %rC) {
+ %C = and i8 %rB, %rC
+ %A = xor i8 %rC, -1
+ %B = and i8 %A, %rA
+ %D = or i8 %C, %B
+ ret i8 %D
+}
+
+; (or (and (not rC), rA), (and rB, rC))
+define i8 @selectbits_i8_03(i8 %rA, i8 %rB, i8 %rC) {
+ %A = xor i8 %rC, -1
+ %B = and i8 %A, %rA
+ %C = and i8 %rB, %rC
+ %D = or i8 %C, %B
+ ret i8 %D
+}
+
+; (or (and (not rC), rA), (and rC, rB))
+define i8 @selectbits_i8_04(i8 %rA, i8 %rB, i8 %rC) {
+ %A = xor i8 %rC, -1
+ %B = and i8 %A, %rA
+ %C = and i8 %rC, %rB
+ %D = or i8 %C, %B
+ ret i8 %D
+}
+
+; (or (and rC, rB), (and rA, (not rC)))
+define i8 @selectbits_i8_05(i8 %rA, i8 %rB, i8 %rC) {
+ %C = and i8 %rC, %rB
+ %A = xor i8 %rC, -1
+ %B = and i8 %rA, %A
+ %D = or i8 %C, %B
+ ret i8 %D
+}
+
+; (or (and rB, rC), (and rA, (not rC)))
+define i8 @selectbits_i8_06(i8 %rA, i8 %rB, i8 %rC) {
+ %C = and i8 %rB, %rC
+ %A = xor i8 %rC, -1
+ %B = and i8 %rA, %A
+ %D = or i8 %C, %B
+ ret i8 %D
+}
+
+; (or (and rA, (not rC)), (and rB, rC))
+define i8 @selectbits_i8_07(i8 %rA, i8 %rB, i8 %rC) {
+ %A = xor i8 %rC, -1
+ %B = and i8 %rA, %A
+ %C = and i8 %rB, %rC
+ %D = or i8 %C, %B
+ ret i8 %D
+}
+
+; (or (and rA, (not rC)), (and rC, rB))
+define i8 @selectbits_i8_08(i8 %rA, i8 %rB, i8 %rC) {
+ %A = xor i8 %rC, -1
+ %B = and i8 %rA, %A
+ %C = and i8 %rC, %rB
+ %D = or i8 %C, %B
+ ret i8 %D
+}
diff --git a/test/CodeGen/CellSPU/sext128.ll b/test/CodeGen/CellSPU/sext128.ll
new file mode 100644
index 0000000..0c0b359
--- /dev/null
+++ b/test/CodeGen/CellSPU/sext128.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s -march=cellspu | FileCheck %s
+
+; ModuleID = 'sext128.bc'
+target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:128:128-v128:128:128-a0:0:128-s0:128:128"
+target triple = "spu"
+
+define i128 @sext_i64_i128(i64 %a) {
+entry:
+ %0 = sext i64 %a to i128
+ ret i128 %0
+; CHECK: long 269488144
+; CHECK: long 269488144
+; CHECK: long 66051
+; CHECK: long 67438087
+; CHECK: rotmai
+; CHECK: lqa
+; CHECK: shufb
+}
+
+define i128 @sext_i32_i128(i32 %a) {
+entry:
+ %0 = sext i32 %a to i128
+ ret i128 %0
+; CHECK: long 269488144
+; CHECK: long 269488144
+; CHECK: long 269488144
+; CHECK: long 66051
+; CHECK: rotmai
+; CHECK: lqa
+; CHECK: shufb
+}
+
+define i128 @sext_i32_i128a(float %a) {
+entry:
+ %0 = call i32 @myfunc(float %a)
+ %1 = sext i32 %0 to i128
+ ret i128 %1
+; CHECK: long 269488144
+; CHECK: long 269488144
+; CHECK: long 269488144
+; CHECK: long 66051
+; CHECK: rotmai
+; CHECK: lqa
+; CHECK: shufb
+}
+
+declare i32 @myfunc(float)
diff --git a/test/CodeGen/CellSPU/shift_ops.ll b/test/CodeGen/CellSPU/shift_ops.ll
new file mode 100644
index 0000000..0264fc8
--- /dev/null
+++ b/test/CodeGen/CellSPU/shift_ops.ll
@@ -0,0 +1,283 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep {shlh } %t1.s | count 9
+; RUN: grep {shlhi } %t1.s | count 3
+; RUN: grep {shl } %t1.s | count 9
+; RUN: grep {shli } %t1.s | count 3
+; RUN: grep {xshw } %t1.s | count 5
+; RUN: grep {and } %t1.s | count 5
+; RUN: grep {andi } %t1.s | count 2
+; RUN: grep {rotmi } %t1.s | count 2
+; RUN: grep {rotqmbyi } %t1.s | count 1
+; RUN: grep {rotqmbii } %t1.s | count 2
+; RUN: grep {rotqmby } %t1.s | count 1
+; RUN: grep {rotqmbi } %t1.s | count 1
+; RUN: grep {rotqbyi } %t1.s | count 1
+; RUN: grep {rotqbii } %t1.s | count 2
+; RUN: grep {rotqbybi } %t1.s | count 1
+; RUN: grep {sfi } %t1.s | count 3
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; Vector shifts are not currently supported in gcc or llvm assembly. These are
+; not tested.
+
+; Shift left i16 via register, note that the second operand to shl is promoted
+; to a 32-bit type:
+
+define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) {
+ %A = shl i16 %arg1, %arg2
+ ret i16 %A
+}
+
+define i16 @shlh_i16_2(i16 %arg1, i16 %arg2) {
+ %A = shl i16 %arg2, %arg1
+ ret i16 %A
+}
+
+define i16 @shlh_i16_3(i16 signext %arg1, i16 signext %arg2) signext {
+ %A = shl i16 %arg1, %arg2
+ ret i16 %A
+}
+
+define i16 @shlh_i16_4(i16 signext %arg1, i16 signext %arg2) signext {
+ %A = shl i16 %arg2, %arg1
+ ret i16 %A
+}
+
+define i16 @shlh_i16_5(i16 zeroext %arg1, i16 zeroext %arg2) zeroext {
+ %A = shl i16 %arg1, %arg2
+ ret i16 %A
+}
+
+define i16 @shlh_i16_6(i16 zeroext %arg1, i16 zeroext %arg2) zeroext {
+ %A = shl i16 %arg2, %arg1
+ ret i16 %A
+}
+
+; Shift left i16 with immediate:
+define i16 @shlhi_i16_1(i16 %arg1) {
+ %A = shl i16 %arg1, 12
+ ret i16 %A
+}
+
+; Should not generate anything other than the return, arg1 << 0 = arg1
+define i16 @shlhi_i16_2(i16 %arg1) {
+ %A = shl i16 %arg1, 0
+ ret i16 %A
+}
+
+define i16 @shlhi_i16_3(i16 %arg1) {
+ %A = shl i16 16383, %arg1
+ ret i16 %A
+}
+
+; Should generate 0, 0 << arg1 = 0
+define i16 @shlhi_i16_4(i16 %arg1) {
+ %A = shl i16 0, %arg1
+ ret i16 %A
+}
+
+define i16 @shlhi_i16_5(i16 signext %arg1) signext {
+ %A = shl i16 %arg1, 12
+ ret i16 %A
+}
+
+; Should not generate anything other than the return, arg1 << 0 = arg1
+define i16 @shlhi_i16_6(i16 signext %arg1) signext {
+ %A = shl i16 %arg1, 0
+ ret i16 %A
+}
+
+define i16 @shlhi_i16_7(i16 signext %arg1) signext {
+ %A = shl i16 16383, %arg1
+ ret i16 %A
+}
+
+; Should generate 0, 0 << arg1 = 0
+define i16 @shlhi_i16_8(i16 signext %arg1) signext {
+ %A = shl i16 0, %arg1
+ ret i16 %A
+}
+
+define i16 @shlhi_i16_9(i16 zeroext %arg1) zeroext {
+ %A = shl i16 %arg1, 12
+ ret i16 %A
+}
+
+; Should not generate anything other than the return, arg1 << 0 = arg1
+define i16 @shlhi_i16_10(i16 zeroext %arg1) zeroext {
+ %A = shl i16 %arg1, 0
+ ret i16 %A
+}
+
+define i16 @shlhi_i16_11(i16 zeroext %arg1) zeroext {
+ %A = shl i16 16383, %arg1
+ ret i16 %A
+}
+
+; Should generate 0, 0 << arg1 = 0
+define i16 @shlhi_i16_12(i16 zeroext %arg1) zeroext {
+ %A = shl i16 0, %arg1
+ ret i16 %A
+}
+
+; Shift left i32 via register, note that the second operand to shl is promoted
+; to a 32-bit type:
+
+define i32 @shl_i32_1(i32 %arg1, i32 %arg2) {
+ %A = shl i32 %arg1, %arg2
+ ret i32 %A
+}
+
+define i32 @shl_i32_2(i32 %arg1, i32 %arg2) {
+ %A = shl i32 %arg2, %arg1
+ ret i32 %A
+}
+
+define i32 @shl_i32_3(i32 signext %arg1, i32 signext %arg2) signext {
+ %A = shl i32 %arg1, %arg2
+ ret i32 %A
+}
+
+define i32 @shl_i32_4(i32 signext %arg1, i32 signext %arg2) signext {
+ %A = shl i32 %arg2, %arg1
+ ret i32 %A
+}
+
+define i32 @shl_i32_5(i32 zeroext %arg1, i32 zeroext %arg2) zeroext {
+ %A = shl i32 %arg1, %arg2
+ ret i32 %A
+}
+
+define i32 @shl_i32_6(i32 zeroext %arg1, i32 zeroext %arg2) zeroext {
+ %A = shl i32 %arg2, %arg1
+ ret i32 %A
+}
+
+; Shift left i32 with immediate:
+define i32 @shli_i32_1(i32 %arg1) {
+ %A = shl i32 %arg1, 12
+ ret i32 %A
+}
+
+; Should not generate anything other than the return, arg1 << 0 = arg1
+define i32 @shli_i32_2(i32 %arg1) {
+ %A = shl i32 %arg1, 0
+ ret i32 %A
+}
+
+define i32 @shli_i32_3(i32 %arg1) {
+ %A = shl i32 16383, %arg1
+ ret i32 %A
+}
+
+; Should generate 0, 0 << arg1 = 0
+define i32 @shli_i32_4(i32 %arg1) {
+ %A = shl i32 0, %arg1
+ ret i32 %A
+}
+
+define i32 @shli_i32_5(i32 signext %arg1) signext {
+ %A = shl i32 %arg1, 12
+ ret i32 %A
+}
+
+; Should not generate anything other than the return, arg1 << 0 = arg1
+define i32 @shli_i32_6(i32 signext %arg1) signext {
+ %A = shl i32 %arg1, 0
+ ret i32 %A
+}
+
+define i32 @shli_i32_7(i32 signext %arg1) signext {
+ %A = shl i32 16383, %arg1
+ ret i32 %A
+}
+
+; Should generate 0, 0 << arg1 = 0
+define i32 @shli_i32_8(i32 signext %arg1) signext {
+ %A = shl i32 0, %arg1
+ ret i32 %A
+}
+
+define i32 @shli_i32_9(i32 zeroext %arg1) zeroext {
+ %A = shl i32 %arg1, 12
+ ret i32 %A
+}
+
+; Should not generate anything other than the return, arg1 << 0 = arg1
+define i32 @shli_i32_10(i32 zeroext %arg1) zeroext {
+ %A = shl i32 %arg1, 0
+ ret i32 %A
+}
+
+define i32 @shli_i32_11(i32 zeroext %arg1) zeroext {
+ %A = shl i32 16383, %arg1
+ ret i32 %A
+}
+
+; Should generate 0, 0 << arg1 = 0
+define i32 @shli_i32_12(i32 zeroext %arg1) zeroext {
+ %A = shl i32 0, %arg1
+ ret i32 %A
+}
+
+;; i64 shift left
+
+define i64 @shl_i64_1(i64 %arg1) {
+ %A = shl i64 %arg1, 9
+ ret i64 %A
+}
+
+define i64 @shl_i64_2(i64 %arg1) {
+ %A = shl i64 %arg1, 3
+ ret i64 %A
+}
+
+define i64 @shl_i64_3(i64 %arg1, i32 %shift) {
+ %1 = zext i32 %shift to i64
+ %2 = shl i64 %arg1, %1
+ ret i64 %2
+}
+
+;; i64 shift right logical (shift 0s from the right)
+
+define i64 @lshr_i64_1(i64 %arg1) {
+ %1 = lshr i64 %arg1, 9
+ ret i64 %1
+}
+
+define i64 @lshr_i64_2(i64 %arg1) {
+ %1 = lshr i64 %arg1, 3
+ ret i64 %1
+}
+
+define i64 @lshr_i64_3(i64 %arg1, i32 %shift) {
+ %1 = zext i32 %shift to i64
+ %2 = lshr i64 %arg1, %1
+ ret i64 %2
+}
+
+;; i64 shift right arithmetic (shift 1s from the right)
+
+define i64 @ashr_i64_1(i64 %arg) {
+ %1 = ashr i64 %arg, 9
+ ret i64 %1
+}
+
+define i64 @ashr_i64_2(i64 %arg) {
+ %1 = ashr i64 %arg, 3
+ ret i64 %1
+}
+
+define i64 @ashr_i64_3(i64 %arg1, i32 %shift) {
+ %1 = zext i32 %shift to i64
+ %2 = ashr i64 %arg1, %1
+ ret i64 %2
+}
+
+define i32 @hi32_i64(i64 %arg) {
+ %1 = lshr i64 %arg, 32
+ %2 = trunc i64 %1 to i32
+ ret i32 %2
+}
diff --git a/test/CodeGen/CellSPU/sp_farith.ll b/test/CodeGen/CellSPU/sp_farith.ll
new file mode 100644
index 0000000..80bf47c
--- /dev/null
+++ b/test/CodeGen/CellSPU/sp_farith.ll
@@ -0,0 +1,90 @@
+; RUN: llc < %s -march=cellspu -enable-unsafe-fp-math > %t1.s
+; RUN: grep fa %t1.s | count 2
+; RUN: grep fs %t1.s | count 2
+; RUN: grep fm %t1.s | count 6
+; RUN: grep fma %t1.s | count 2
+; RUN: grep fms %t1.s | count 2
+; RUN: grep fnms %t1.s | count 3
+;
+; This file includes standard floating point arithmetic instructions
+; NOTE fdiv is tested separately since it is a compound operation
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define float @fp_add(float %arg1, float %arg2) {
+ %A = fadd float %arg1, %arg2 ; <float> [#uses=1]
+ ret float %A
+}
+
+define <4 x float> @fp_add_vec(<4 x float> %arg1, <4 x float> %arg2) {
+ %A = fadd <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1]
+ ret <4 x float> %A
+}
+
+define float @fp_sub(float %arg1, float %arg2) {
+ %A = fsub float %arg1, %arg2 ; <float> [#uses=1]
+ ret float %A
+}
+
+define <4 x float> @fp_sub_vec(<4 x float> %arg1, <4 x float> %arg2) {
+ %A = fsub <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1]
+ ret <4 x float> %A
+}
+
+define float @fp_mul(float %arg1, float %arg2) {
+ %A = fmul float %arg1, %arg2 ; <float> [#uses=1]
+ ret float %A
+}
+
+define <4 x float> @fp_mul_vec(<4 x float> %arg1, <4 x float> %arg2) {
+ %A = fmul <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1]
+ ret <4 x float> %A
+}
+
+define float @fp_mul_add(float %arg1, float %arg2, float %arg3) {
+ %A = fmul float %arg1, %arg2 ; <float> [#uses=1]
+ %B = fadd float %A, %arg3 ; <float> [#uses=1]
+ ret float %B
+}
+
+define <4 x float> @fp_mul_add_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) {
+ %A = fmul <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1]
+ %B = fadd <4 x float> %A, %arg3 ; <<4 x float>> [#uses=1]
+ ret <4 x float> %B
+}
+
+define float @fp_mul_sub(float %arg1, float %arg2, float %arg3) {
+ %A = fmul float %arg1, %arg2 ; <float> [#uses=1]
+ %B = fsub float %A, %arg3 ; <float> [#uses=1]
+ ret float %B
+}
+
+define <4 x float> @fp_mul_sub_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) {
+ %A = fmul <4 x float> %arg1, %arg2 ; <<4 x float>> [#uses=1]
+ %B = fsub <4 x float> %A, %arg3 ; <<4 x float>> [#uses=1]
+ ret <4 x float> %B
+}
+
+; Test the straightforward way of getting fnms
+; c - a * b
+define float @fp_neg_mul_sub_1(float %arg1, float %arg2, float %arg3) {
+ %A = fmul float %arg1, %arg2
+ %B = fsub float %arg3, %A
+ ret float %B
+}
+
+; Test another way of getting fnms
+; - ( a *b -c ) = c - a * b
+define float @fp_neg_mul_sub_2(float %arg1, float %arg2, float %arg3) {
+ %A = fmul float %arg1, %arg2
+ %B = fsub float %A, %arg3
+ %C = fsub float -0.0, %B
+ ret float %C
+}
+
+define <4 x float> @fp_neg_mul_sub_vec(<4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3) {
+ %A = fmul <4 x float> %arg1, %arg2
+ %B = fsub <4 x float> %A, %arg3
+ %D = fsub <4 x float> < float -0.0, float -0.0, float -0.0, float -0.0 >, %B
+ ret <4 x float> %D
+}
diff --git a/test/CodeGen/CellSPU/stores.ll b/test/CodeGen/CellSPU/stores.ll
new file mode 100644
index 0000000..05f44f4
--- /dev/null
+++ b/test/CodeGen/CellSPU/stores.ll
@@ -0,0 +1,151 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep {stqd.*0(\$3)} %t1.s | count 4
+; RUN: grep {stqd.*16(\$3)} %t1.s | count 4
+; RUN: grep 16256 %t1.s | count 2
+; RUN: grep 16384 %t1.s | count 1
+; RUN: grep 771 %t1.s | count 4
+; RUN: grep 515 %t1.s | count 2
+; RUN: grep 1799 %t1.s | count 2
+; RUN: grep 1543 %t1.s | count 5
+; RUN: grep 1029 %t1.s | count 3
+; RUN: grep {shli.*, 4} %t1.s | count 4
+; RUN: grep stqx %t1.s | count 4
+; RUN: grep ilhu %t1.s | count 11
+; RUN: grep iohl %t1.s | count 8
+; RUN: grep shufb %t1.s | count 15
+; RUN: grep frds %t1.s | count 1
+
+; ModuleID = 'stores.bc'
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define void @store_v16i8_1(<16 x i8>* %a) nounwind {
+entry:
+ store <16 x i8> < i8 1, i8 2, i8 1, i8 1, i8 1, i8 2, i8 1, i8 1, i8 1, i8 2, i8 1, i8 1, i8 1, i8 2, i8 1, i8 1 >, <16 x i8>* %a
+ ret void
+}
+
+define void @store_v16i8_2(<16 x i8>* %a) nounwind {
+entry:
+ %arrayidx = getelementptr <16 x i8>* %a, i32 1
+ store <16 x i8> < i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2 >, <16 x i8>* %arrayidx
+ ret void
+}
+
+define void @store_v16i8_3(<16 x i8>* %a, i32 %i) nounwind {
+entry:
+ %arrayidx = getelementptr <16 x i8>* %a, i32 %i
+ store <16 x i8> < i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1 >, <16 x i8>* %arrayidx
+ ret void
+}
+
+define void @store_v8i16_1(<8 x i16>* %a) nounwind {
+entry:
+ store <8 x i16> < i16 1, i16 2, i16 1, i16 1, i16 1, i16 2, i16 1, i16 1 >, <8 x i16>* %a
+ ret void
+}
+
+define void @store_v8i16_2(<8 x i16>* %a) nounwind {
+entry:
+ %arrayidx = getelementptr <8 x i16>* %a, i16 1
+ store <8 x i16> < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2 >, <8 x i16>* %arrayidx
+ ret void
+}
+
+define void @store_v8i16_3(<8 x i16>* %a, i32 %i) nounwind {
+entry:
+ %arrayidx = getelementptr <8 x i16>* %a, i32 %i
+ store <8 x i16> < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1 >, <8 x i16>* %arrayidx
+ ret void
+}
+
+define void @store_v4i32_1(<4 x i32>* %a) nounwind {
+entry:
+ store <4 x i32> < i32 1, i32 2, i32 1, i32 1 >, <4 x i32>* %a
+ ret void
+}
+
+define void @store_v4i32_2(<4 x i32>* %a) nounwind {
+entry:
+ %arrayidx = getelementptr <4 x i32>* %a, i32 1
+ store <4 x i32> < i32 2, i32 2, i32 2, i32 2 >, <4 x i32>* %arrayidx
+ ret void
+}
+
+define void @store_v4i32_3(<4 x i32>* %a, i32 %i) nounwind {
+entry:
+ %arrayidx = getelementptr <4 x i32>* %a, i32 %i
+ store <4 x i32> < i32 1, i32 1, i32 1, i32 1 >, <4 x i32>* %arrayidx
+ ret void
+}
+
+define void @store_v4f32_1(<4 x float>* %a) nounwind {
+entry:
+ store <4 x float> < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 >, <4 x float>* %a
+ ret void
+}
+
+define void @store_v4f32_2(<4 x float>* %a) nounwind {
+entry:
+ %arrayidx = getelementptr <4 x float>* %a, i32 1
+ store <4 x float> < float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00 >, <4 x float>* %arrayidx
+ ret void
+}
+
+define void @store_v4f32_3(<4 x float>* %a, i32 %i) nounwind {
+entry:
+ %arrayidx = getelementptr <4 x float>* %a, i32 %i
+ store <4 x float> < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 >, <4 x float>* %arrayidx
+ ret void
+}
+
+; Test truncating stores:
+
+define zeroext i8 @tstore_i16_i8(i16 signext %val, i8* %dest) nounwind {
+entry:
+ %conv = trunc i16 %val to i8
+ store i8 %conv, i8* %dest
+ ret i8 %conv
+}
+
+define zeroext i8 @tstore_i32_i8(i32 %val, i8* %dest) nounwind {
+entry:
+ %conv = trunc i32 %val to i8
+ store i8 %conv, i8* %dest
+ ret i8 %conv
+}
+
+define signext i16 @tstore_i32_i16(i32 %val, i16* %dest) nounwind {
+entry:
+ %conv = trunc i32 %val to i16
+ store i16 %conv, i16* %dest
+ ret i16 %conv
+}
+
+define zeroext i8 @tstore_i64_i8(i64 %val, i8* %dest) nounwind {
+entry:
+ %conv = trunc i64 %val to i8
+ store i8 %conv, i8* %dest
+ ret i8 %conv
+}
+
+define signext i16 @tstore_i64_i16(i64 %val, i16* %dest) nounwind {
+entry:
+ %conv = trunc i64 %val to i16
+ store i16 %conv, i16* %dest
+ ret i16 %conv
+}
+
+define i32 @tstore_i64_i32(i64 %val, i32* %dest) nounwind {
+entry:
+ %conv = trunc i64 %val to i32
+ store i32 %conv, i32* %dest
+ ret i32 %conv
+}
+
+define float @tstore_f64_f32(double %val, float* %dest) nounwind {
+entry:
+ %conv = fptrunc double %val to float
+ store float %conv, float* %dest
+ ret float %conv
+}
diff --git a/test/CodeGen/CellSPU/struct_1.ll b/test/CodeGen/CellSPU/struct_1.ll
new file mode 100644
index 0000000..8ee7d93
--- /dev/null
+++ b/test/CodeGen/CellSPU/struct_1.ll
@@ -0,0 +1,144 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: llc < %s -march=cellspu -mattr=large_mem > %t2.s
+; RUN: grep lqa %t1.s | count 5
+; RUN: grep lqd %t1.s | count 11
+; RUN: grep rotqbyi %t1.s | count 7
+; RUN: grep xshw %t1.s | count 1
+; RUN: grep andi %t1.s | count 5
+; RUN: grep cbd %t1.s | count 3
+; RUN: grep chd %t1.s | count 1
+; RUN: grep cwd %t1.s | count 3
+; RUN: grep shufb %t1.s | count 7
+; RUN: grep stqd %t1.s | count 7
+; RUN: grep iohl %t2.s | count 16
+; RUN: grep ilhu %t2.s | count 16
+; RUN: grep lqd %t2.s | count 16
+; RUN: grep rotqbyi %t2.s | count 7
+; RUN: grep xshw %t2.s | count 1
+; RUN: grep andi %t2.s | count 5
+; RUN: grep cbd %t2.s | count 3
+; RUN: grep chd %t2.s | count 1
+; RUN: grep cwd %t2.s | count 3
+; RUN: grep shufb %t2.s | count 7
+; RUN: grep stqd %t2.s | count 7
+
+; ModuleID = 'struct_1.bc'
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; struct hackstate {
+; unsigned char c1; // offset 0 (rotate left by 13 bytes to byte 3)
+; unsigned char c2; // offset 1 (rotate left by 14 bytes to byte 3)
+; unsigned char c3; // offset 2 (rotate left by 15 bytes to byte 3)
+; int i1; // offset 4 (rotate left by 4 bytes to byte 0)
+; short s1; // offset 8 (rotate left by 6 bytes to byte 2)
+; int i2; // offset 12 [ignored]
+; unsigned char c4; // offset 16 [ignored]
+; unsigned char c5; // offset 17 [ignored]
+; unsigned char c6; // offset 18 (rotate left by 14 bytes to byte 3)
+; unsigned char c7; // offset 19 (no rotate, in preferred slot)
+; int i3; // offset 20 [ignored]
+; int i4; // offset 24 [ignored]
+; int i5; // offset 28 [ignored]
+; int i6; // offset 32 (no rotate, in preferred slot)
+; }
+%struct.hackstate = type { i8, i8, i8, i32, i16, i32, i8, i8, i8, i8, i32, i32, i32, i32 }
+
+; struct hackstate state = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+@state = global %struct.hackstate zeroinitializer, align 16
+
+define i8 @get_hackstate_c1() zeroext nounwind {
+entry:
+ %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 0), align 16
+ ret i8 %tmp2
+}
+
+define i8 @get_hackstate_c2() zeroext nounwind {
+entry:
+ %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 1), align 16
+ ret i8 %tmp2
+}
+
+define i8 @get_hackstate_c3() zeroext nounwind {
+entry:
+ %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 2), align 16
+ ret i8 %tmp2
+}
+
+define i32 @get_hackstate_i1() nounwind {
+entry:
+ %tmp2 = load i32* getelementptr (%struct.hackstate* @state, i32 0, i32 3), align 16
+ ret i32 %tmp2
+}
+
+define i16 @get_hackstate_s1() signext nounwind {
+entry:
+ %tmp2 = load i16* getelementptr (%struct.hackstate* @state, i32 0, i32 4), align 16
+ ret i16 %tmp2
+}
+
+define i8 @get_hackstate_c6() zeroext nounwind {
+entry:
+ %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 8), align 16
+ ret i8 %tmp2
+}
+
+define i8 @get_hackstate_c7() zeroext nounwind {
+entry:
+ %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 9), align 16
+ ret i8 %tmp2
+}
+
+define i32 @get_hackstate_i3() nounwind {
+entry:
+ %tmp2 = load i32* getelementptr (%struct.hackstate* @state, i32 0, i32 10), align 16
+ ret i32 %tmp2
+}
+
+define i32 @get_hackstate_i6() nounwind {
+entry:
+ %tmp2 = load i32* getelementptr (%struct.hackstate* @state, i32 0, i32 13), align 16
+ ret i32 %tmp2
+}
+
+define void @set_hackstate_c1(i8 zeroext %c) nounwind {
+entry:
+ store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 0), align 16
+ ret void
+}
+
+define void @set_hackstate_c2(i8 zeroext %c) nounwind {
+entry:
+ store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 1), align 16
+ ret void
+}
+
+define void @set_hackstate_c3(i8 zeroext %c) nounwind {
+entry:
+ store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 2), align 16
+ ret void
+}
+
+define void @set_hackstate_i1(i32 %i) nounwind {
+entry:
+ store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 3), align 16
+ ret void
+}
+
+define void @set_hackstate_s1(i16 signext %s) nounwind {
+entry:
+ store i16 %s, i16* getelementptr (%struct.hackstate* @state, i32 0, i32 4), align 16
+ ret void
+}
+
+define void @set_hackstate_i3(i32 %i) nounwind {
+entry:
+ store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 10), align 16
+ ret void
+}
+
+define void @set_hackstate_i6(i32 %i) nounwind {
+entry:
+ store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 13), align 16
+ ret void
+}
diff --git a/test/CodeGen/CellSPU/trunc.ll b/test/CodeGen/CellSPU/trunc.ll
new file mode 100644
index 0000000..d161852
--- /dev/null
+++ b/test/CodeGen/CellSPU/trunc.ll
@@ -0,0 +1,94 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep shufb %t1.s | count 19
+; RUN: grep {ilhu.*1799} %t1.s | count 1
+; RUN: grep {ilhu.*771} %t1.s | count 2
+; RUN: grep {ilhu.*1543} %t1.s | count 1
+; RUN: grep {ilhu.*1029} %t1.s | count 1
+; RUN: grep {ilhu.*515} %t1.s | count 1
+; RUN: grep {ilhu.*3855} %t1.s | count 1
+; RUN: grep {ilhu.*3599} %t1.s | count 1
+; RUN: grep {ilhu.*3085} %t1.s | count 1
+; RUN: grep {iohl.*3855} %t1.s | count 1
+; RUN: grep {iohl.*3599} %t1.s | count 2
+; RUN: grep {iohl.*1543} %t1.s | count 2
+; RUN: grep {iohl.*771} %t1.s | count 2
+; RUN: grep {iohl.*515} %t1.s | count 1
+; RUN: grep {iohl.*1799} %t1.s | count 1
+; RUN: grep lqa %t1.s | count 1
+; RUN: grep cbd %t1.s | count 4
+; RUN: grep chd %t1.s | count 3
+; RUN: grep cwd %t1.s | count 1
+; RUN: grep cdd %t1.s | count 1
+
+; ModuleID = 'trunc.bc'
+target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:64:64-v128:128:128-a0:0:128-s0:128:128"
+target triple = "spu"
+
+define <16 x i8> @trunc_i128_i8(i128 %u, <16 x i8> %v) {
+entry:
+ %0 = trunc i128 %u to i8
+ %tmp1 = insertelement <16 x i8> %v, i8 %0, i32 15
+ ret <16 x i8> %tmp1
+}
+
+define <8 x i16> @trunc_i128_i16(i128 %u, <8 x i16> %v) {
+entry:
+ %0 = trunc i128 %u to i16
+ %tmp1 = insertelement <8 x i16> %v, i16 %0, i32 8
+ ret <8 x i16> %tmp1
+}
+
+define <4 x i32> @trunc_i128_i32(i128 %u, <4 x i32> %v) {
+entry:
+ %0 = trunc i128 %u to i32
+ %tmp1 = insertelement <4 x i32> %v, i32 %0, i32 2
+ ret <4 x i32> %tmp1
+}
+
+define <2 x i64> @trunc_i128_i64(i128 %u, <2 x i64> %v) {
+entry:
+ %0 = trunc i128 %u to i64
+ %tmp1 = insertelement <2 x i64> %v, i64 %0, i32 1
+ ret <2 x i64> %tmp1
+}
+
+define <16 x i8> @trunc_i64_i8(i64 %u, <16 x i8> %v) {
+entry:
+ %0 = trunc i64 %u to i8
+ %tmp1 = insertelement <16 x i8> %v, i8 %0, i32 10
+ ret <16 x i8> %tmp1
+}
+
+define <8 x i16> @trunc_i64_i16(i64 %u, <8 x i16> %v) {
+entry:
+ %0 = trunc i64 %u to i16
+ %tmp1 = insertelement <8 x i16> %v, i16 %0, i32 6
+ ret <8 x i16> %tmp1
+}
+
+define i32 @trunc_i64_i32(i64 %u) {
+entry:
+ %0 = trunc i64 %u to i32
+ ret i32 %0
+}
+
+define <16 x i8> @trunc_i32_i8(i32 %u, <16 x i8> %v) {
+entry:
+ %0 = trunc i32 %u to i8
+ %tmp1 = insertelement <16 x i8> %v, i8 %0, i32 7
+ ret <16 x i8> %tmp1
+}
+
+define <8 x i16> @trunc_i32_i16(i32 %u, <8 x i16> %v) {
+entry:
+ %0 = trunc i32 %u to i16
+ %tmp1 = insertelement <8 x i16> %v, i16 %0, i32 3
+ ret <8 x i16> %tmp1
+}
+
+define <16 x i8> @trunc_i16_i8(i16 %u, <16 x i8> %v) {
+entry:
+ %0 = trunc i16 %u to i8
+ %tmp1 = insertelement <16 x i8> %v, i8 %0, i32 5
+ ret <16 x i8> %tmp1
+}
diff --git a/test/CodeGen/CellSPU/useful-harnesses/README.txt b/test/CodeGen/CellSPU/useful-harnesses/README.txt
new file mode 100644
index 0000000..d87b398
--- /dev/null
+++ b/test/CodeGen/CellSPU/useful-harnesses/README.txt
@@ -0,0 +1,5 @@
+This directory contains code that's not part of the DejaGNU test suite,
+but is generally useful as various test harnesses.
+
+vecoperations.c: Various vector operation sanity checks, e.g., shuffles,
+ 8-bit vector add and multiply.
diff --git a/test/CodeGen/CellSPU/useful-harnesses/i32operations.c b/test/CodeGen/CellSPU/useful-harnesses/i32operations.c
new file mode 100644
index 0000000..12fc30b
--- /dev/null
+++ b/test/CodeGen/CellSPU/useful-harnesses/i32operations.c
@@ -0,0 +1,69 @@
+#include <stdio.h>
+
+typedef unsigned int uint32_t;
+typedef int int32_t;
+
+const char *boolstring(int val) {
+ return val ? "true" : "false";
+}
+
+int i32_eq(int32_t a, int32_t b) {
+ return (a == b);
+}
+
+int i32_neq(int32_t a, int32_t b) {
+ return (a != b);
+}
+
+int32_t i32_eq_select(int32_t a, int32_t b, int32_t c, int32_t d) {
+ return ((a == b) ? c : d);
+}
+
+int32_t i32_neq_select(int32_t a, int32_t b, int32_t c, int32_t d) {
+ return ((a != b) ? c : d);
+}
+
+struct pred_s {
+ const char *name;
+ int (*predfunc)(int32_t, int32_t);
+ int (*selfunc)(int32_t, int32_t, int32_t, int32_t);
+};
+
+struct pred_s preds[] = {
+ { "eq", i32_eq, i32_eq_select },
+ { "neq", i32_neq, i32_neq_select }
+};
+
+int main(void) {
+ int i;
+ int32_t a = 1234567890;
+ int32_t b = 345678901;
+ int32_t c = 1234500000;
+ int32_t d = 10001;
+ int32_t e = 10000;
+
+ printf("a = %12d (0x%08x)\n", a, a);
+ printf("b = %12d (0x%08x)\n", b, b);
+ printf("c = %12d (0x%08x)\n", c, c);
+ printf("d = %12d (0x%08x)\n", d, d);
+ printf("e = %12d (0x%08x)\n", e, e);
+ printf("----------------------------------------\n");
+
+ for (i = 0; i < sizeof(preds)/sizeof(preds[0]); ++i) {
+ printf("a %s a = %s\n", preds[i].name, boolstring((*preds[i].predfunc)(a, a)));
+ printf("a %s a = %s\n", preds[i].name, boolstring((*preds[i].predfunc)(a, a)));
+ printf("a %s b = %s\n", preds[i].name, boolstring((*preds[i].predfunc)(a, b)));
+ printf("a %s c = %s\n", preds[i].name, boolstring((*preds[i].predfunc)(a, c)));
+ printf("d %s e = %s\n", preds[i].name, boolstring((*preds[i].predfunc)(d, e)));
+ printf("e %s e = %s\n", preds[i].name, boolstring((*preds[i].predfunc)(e, e)));
+
+ printf("a %s a ? c : d = %d\n", preds[i].name, (*preds[i].selfunc)(a, a, c, d));
+ printf("a %s a ? c : d == c (%s)\n", preds[i].name, boolstring((*preds[i].selfunc)(a, a, c, d) == c));
+ printf("a %s b ? c : d = %d\n", preds[i].name, (*preds[i].selfunc)(a, b, c, d));
+ printf("a %s b ? c : d == d (%s)\n", preds[i].name, boolstring((*preds[i].selfunc)(a, b, c, d) == d));
+
+ printf("----------------------------------------\n");
+ }
+
+ return 0;
+}
diff --git a/test/CodeGen/CellSPU/useful-harnesses/i64operations.c b/test/CodeGen/CellSPU/useful-harnesses/i64operations.c
new file mode 100644
index 0000000..b613bd8
--- /dev/null
+++ b/test/CodeGen/CellSPU/useful-harnesses/i64operations.c
@@ -0,0 +1,673 @@
+#include <stdio.h>
+#include "i64operations.h"
+
+int64_t tval_a = 1234567890003LL;
+int64_t tval_b = 2345678901235LL;
+int64_t tval_c = 1234567890001LL;
+int64_t tval_d = 10001LL;
+int64_t tval_e = 10000LL;
+uint64_t tval_f = 0xffffff0750135eb9;
+int64_t tval_g = -1;
+
+/* ~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~- */
+
+int
+i64_eq(int64_t a, int64_t b)
+{
+ return (a == b);
+}
+
+int
+i64_neq(int64_t a, int64_t b)
+{
+ return (a != b);
+}
+
+int
+i64_gt(int64_t a, int64_t b)
+{
+ return (a > b);
+}
+
+int
+i64_le(int64_t a, int64_t b)
+{
+ return (a <= b);
+}
+
+int
+i64_ge(int64_t a, int64_t b) {
+ return (a >= b);
+}
+
+int
+i64_lt(int64_t a, int64_t b) {
+ return (a < b);
+}
+
+int
+i64_uge(uint64_t a, uint64_t b)
+{
+ return (a >= b);
+}
+
+int
+i64_ult(uint64_t a, uint64_t b)
+{
+ return (a < b);
+}
+
+int
+i64_ugt(uint64_t a, uint64_t b)
+{
+ return (a > b);
+}
+
+int
+i64_ule(uint64_t a, uint64_t b)
+{
+ return (a <= b);
+}
+
+int64_t
+i64_eq_select(int64_t a, int64_t b, int64_t c, int64_t d)
+{
+ return ((a == b) ? c : d);
+}
+
+int64_t
+i64_neq_select(int64_t a, int64_t b, int64_t c, int64_t d)
+{
+ return ((a != b) ? c : d);
+}
+
+int64_t
+i64_gt_select(int64_t a, int64_t b, int64_t c, int64_t d) {
+ return ((a > b) ? c : d);
+}
+
+int64_t
+i64_le_select(int64_t a, int64_t b, int64_t c, int64_t d) {
+ return ((a <= b) ? c : d);
+}
+
+int64_t
+i64_ge_select(int64_t a, int64_t b, int64_t c, int64_t d) {
+ return ((a >= b) ? c : d);
+}
+
+int64_t
+i64_lt_select(int64_t a, int64_t b, int64_t c, int64_t d) {
+ return ((a < b) ? c : d);
+}
+
+uint64_t
+i64_ugt_select(uint64_t a, uint64_t b, uint64_t c, uint64_t d)
+{
+ return ((a > b) ? c : d);
+}
+
+uint64_t
+i64_ule_select(uint64_t a, uint64_t b, uint64_t c, uint64_t d)
+{
+ return ((a <= b) ? c : d);
+}
+
+uint64_t
+i64_uge_select(uint64_t a, uint64_t b, uint64_t c, uint64_t d) {
+ return ((a >= b) ? c : d);
+}
+
+uint64_t
+i64_ult_select(uint64_t a, uint64_t b, uint64_t c, uint64_t d) {
+ return ((a < b) ? c : d);
+}
+
+/* ~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~- */
+
+struct harness_int64_pred int64_tests_eq[] = {
+ {"a %s a", &tval_a, &tval_a, &tval_c, &tval_d, TRUE_VAL, &tval_c},
+ {"a %s b", &tval_a, &tval_b, &tval_c, &tval_d, FALSE_VAL, &tval_d},
+ {"a %s c", &tval_a, &tval_c, &tval_c, &tval_d, FALSE_VAL, &tval_d},
+ {"d %s e", &tval_d, &tval_e, &tval_c, &tval_d, FALSE_VAL, &tval_d},
+ {"e %s e", &tval_e, &tval_e, &tval_c, &tval_d, TRUE_VAL, &tval_c}
+};
+
+struct harness_int64_pred int64_tests_neq[] = {
+ {"a %s a", &tval_a, &tval_a, &tval_c, &tval_d, FALSE_VAL, &tval_d},
+ {"a %s b", &tval_a, &tval_b, &tval_c, &tval_d, TRUE_VAL, &tval_c},
+ {"a %s c", &tval_a, &tval_c, &tval_c, &tval_d, TRUE_VAL, &tval_c},
+ {"d %s e", &tval_d, &tval_e, &tval_c, &tval_d, TRUE_VAL, &tval_c},
+ {"e %s e", &tval_e, &tval_e, &tval_c, &tval_d, FALSE_VAL, &tval_d}
+};
+
+struct harness_int64_pred int64_tests_sgt[] = {
+ {"a %s a", &tval_a, &tval_a, &tval_c, &tval_d, FALSE_VAL, &tval_d},
+ {"a %s b", &tval_a, &tval_b, &tval_c, &tval_d, FALSE_VAL, &tval_d},
+ {"a %s c", &tval_a, &tval_c, &tval_c, &tval_d, TRUE_VAL, &tval_c},
+ {"d %s e", &tval_d, &tval_e, &tval_c, &tval_d, TRUE_VAL, &tval_c},
+ {"e %s e", &tval_e, &tval_e, &tval_c, &tval_d, FALSE_VAL, &tval_d}
+};
+
+struct harness_int64_pred int64_tests_sle[] = {
+ {"a %s a", &tval_a, &tval_a, &tval_c, &tval_d, TRUE_VAL, &tval_c},
+ {"a %s b", &tval_a, &tval_b, &tval_c, &tval_d, TRUE_VAL, &tval_c},
+ {"a %s c", &tval_a, &tval_c, &tval_c, &tval_d, FALSE_VAL, &tval_d},
+ {"d %s e", &tval_d, &tval_e, &tval_c, &tval_d, FALSE_VAL, &tval_d},
+ {"e %s e", &tval_e, &tval_e, &tval_c, &tval_d, TRUE_VAL, &tval_c}
+};
+
+struct harness_int64_pred int64_tests_sge[] = {
+ {"a %s a", &tval_a, &tval_a, &tval_c, &tval_d, TRUE_VAL, &tval_c},
+ {"a %s b", &tval_a, &tval_b, &tval_c, &tval_d, FALSE_VAL, &tval_d},
+ {"a %s c", &tval_a, &tval_c, &tval_c, &tval_d, TRUE_VAL, &tval_c},
+ {"d %s e", &tval_d, &tval_e, &tval_c, &tval_d, TRUE_VAL, &tval_c},
+ {"e %s e", &tval_e, &tval_e, &tval_c, &tval_d, TRUE_VAL, &tval_c}
+};
+
+struct harness_int64_pred int64_tests_slt[] = {
+ {"a %s a", &tval_a, &tval_a, &tval_c, &tval_d, FALSE_VAL, &tval_d},
+ {"a %s b", &tval_a, &tval_b, &tval_c, &tval_d, TRUE_VAL, &tval_c},
+ {"a %s c", &tval_a, &tval_c, &tval_c, &tval_d, FALSE_VAL, &tval_d},
+ {"d %s e", &tval_d, &tval_e, &tval_c, &tval_d, FALSE_VAL, &tval_d},
+ {"e %s e", &tval_e, &tval_e, &tval_c, &tval_d, FALSE_VAL, &tval_d}
+};
+
+struct int64_pred_s int64_preds[] = {
+ {"eq", i64_eq, i64_eq_select,
+ int64_tests_eq, ARR_SIZE(int64_tests_eq)},
+ {"neq", i64_neq, i64_neq_select,
+ int64_tests_neq, ARR_SIZE(int64_tests_neq)},
+ {"gt", i64_gt, i64_gt_select,
+ int64_tests_sgt, ARR_SIZE(int64_tests_sgt)},
+ {"le", i64_le, i64_le_select,
+ int64_tests_sle, ARR_SIZE(int64_tests_sle)},
+ {"ge", i64_ge, i64_ge_select,
+ int64_tests_sge, ARR_SIZE(int64_tests_sge)},
+ {"lt", i64_lt, i64_lt_select,
+ int64_tests_slt, ARR_SIZE(int64_tests_slt)}
+};
+
+/* ~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~- */
+
+struct harness_uint64_pred uint64_tests_ugt[] = {
+ {"a %s a", (uint64_t *) &tval_a, (uint64_t *) &tval_a, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, FALSE_VAL, (uint64_t *) &tval_d},
+ {"a %s b", (uint64_t *) &tval_a, (uint64_t *) &tval_b, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, FALSE_VAL, (uint64_t *) &tval_d },
+ {"a %s c", (uint64_t *) &tval_a, (uint64_t *) &tval_c, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, TRUE_VAL, (uint64_t *) &tval_c },
+ {"d %s e", (uint64_t *) &tval_d, (uint64_t *) &tval_e, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, TRUE_VAL, (uint64_t *) &tval_c },
+ {"e %s e", (uint64_t *) &tval_e, (uint64_t *) &tval_e, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, FALSE_VAL, (uint64_t *) &tval_d }
+};
+
+struct harness_uint64_pred uint64_tests_ule[] = {
+ {"a %s a", (uint64_t *) &tval_a, (uint64_t *) &tval_a, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, TRUE_VAL, (uint64_t *) &tval_c},
+ {"a %s b", (uint64_t *) &tval_a, (uint64_t *) &tval_b, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, TRUE_VAL, (uint64_t *) &tval_c},
+ {"a %s c", (uint64_t *) &tval_a, (uint64_t *) &tval_c, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, FALSE_VAL, (uint64_t *) &tval_d},
+ {"d %s e", (uint64_t *) &tval_d, (uint64_t *) &tval_e, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, FALSE_VAL, (uint64_t *) &tval_d},
+ {"e %s e", (uint64_t *) &tval_e, (uint64_t *) &tval_e, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, TRUE_VAL, (uint64_t *) &tval_c}
+};
+
+struct harness_uint64_pred uint64_tests_uge[] = {
+ {"a %s a", (uint64_t *) &tval_a, (uint64_t *) &tval_a, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, TRUE_VAL, (uint64_t *) &tval_c},
+ {"a %s b", (uint64_t *) &tval_a, (uint64_t *) &tval_b, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, FALSE_VAL, (uint64_t *) &tval_d},
+ {"a %s c", (uint64_t *) &tval_a, (uint64_t *) &tval_c, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, TRUE_VAL, (uint64_t *) &tval_c},
+ {"d %s e", (uint64_t *) &tval_d, (uint64_t *) &tval_e, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, TRUE_VAL, (uint64_t *) &tval_c},
+ {"e %s e", (uint64_t *) &tval_e, (uint64_t *) &tval_e, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, TRUE_VAL, (uint64_t *) &tval_c}
+};
+
+struct harness_uint64_pred uint64_tests_ult[] = {
+ {"a %s a", (uint64_t *) &tval_a, (uint64_t *) &tval_a, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, FALSE_VAL, (uint64_t *) &tval_d},
+ {"a %s b", (uint64_t *) &tval_a, (uint64_t *) &tval_b, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, TRUE_VAL, (uint64_t *) &tval_c},
+ {"a %s c", (uint64_t *) &tval_a, (uint64_t *) &tval_c, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, FALSE_VAL, (uint64_t *) &tval_d},
+ {"d %s e", (uint64_t *) &tval_d, (uint64_t *) &tval_e, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, FALSE_VAL, (uint64_t *) &tval_d},
+ {"e %s e", (uint64_t *) &tval_e, (uint64_t *) &tval_e, (uint64_t *) &tval_c,
+ (uint64_t *) &tval_d, FALSE_VAL, (uint64_t *) &tval_d}
+};
+
+struct uint64_pred_s uint64_preds[] = {
+ {"ugt", i64_ugt, i64_ugt_select,
+ uint64_tests_ugt, ARR_SIZE(uint64_tests_ugt)},
+ {"ule", i64_ule, i64_ule_select,
+ uint64_tests_ule, ARR_SIZE(uint64_tests_ule)},
+ {"uge", i64_uge, i64_uge_select,
+ uint64_tests_uge, ARR_SIZE(uint64_tests_uge)},
+ {"ult", i64_ult, i64_ult_select,
+ uint64_tests_ult, ARR_SIZE(uint64_tests_ult)}
+};
+
+int
+compare_expect_int64(const struct int64_pred_s * pred)
+{
+ int j, failed = 0;
+
+ for (j = 0; j < pred->n_tests; ++j) {
+ int pred_result;
+
+ pred_result = (*pred->predfunc) (*pred->tests[j].lhs, *pred->tests[j].rhs);
+
+ if (pred_result != pred->tests[j].expected) {
+ char str[64];
+
+ sprintf(str, pred->tests[j].fmt_string, pred->name);
+ printf("%s: returned value is %d, expecting %d\n", str,
+ pred_result, pred->tests[j].expected);
+ printf(" lhs = %19lld (0x%016llx)\n", *pred->tests[j].lhs,
+ *pred->tests[j].lhs);
+ printf(" rhs = %19lld (0x%016llx)\n", *pred->tests[j].rhs,
+ *pred->tests[j].rhs);
+ ++failed;
+ } else {
+ int64_t selresult;
+
+ selresult = (pred->selfunc) (*pred->tests[j].lhs, *pred->tests[j].rhs,
+ *pred->tests[j].select_a,
+ *pred->tests[j].select_b);
+
+ if (selresult != *pred->tests[j].select_expected) {
+ char str[64];
+
+ sprintf(str, pred->tests[j].fmt_string, pred->name);
+ printf("%s select: returned value is %d, expecting %d\n", str,
+ pred_result, pred->tests[j].expected);
+ printf(" lhs = %19lld (0x%016llx)\n", *pred->tests[j].lhs,
+ *pred->tests[j].lhs);
+ printf(" rhs = %19lld (0x%016llx)\n", *pred->tests[j].rhs,
+ *pred->tests[j].rhs);
+ printf(" true = %19lld (0x%016llx)\n", *pred->tests[j].select_a,
+ *pred->tests[j].select_a);
+ printf(" false = %19lld (0x%016llx)\n", *pred->tests[j].select_b,
+ *pred->tests[j].select_b);
+ ++failed;
+ }
+ }
+ }
+
+ printf(" %d tests performed, should be %d.\n", j, pred->n_tests);
+
+ return failed;
+}
+
+int
+compare_expect_uint64(const struct uint64_pred_s * pred)
+{
+ int j, failed = 0;
+
+ for (j = 0; j < pred->n_tests; ++j) {
+ int pred_result;
+
+ pred_result = (*pred->predfunc) (*pred->tests[j].lhs, *pred->tests[j].rhs);
+ if (pred_result != pred->tests[j].expected) {
+ char str[64];
+
+ sprintf(str, pred->tests[j].fmt_string, pred->name);
+ printf("%s: returned value is %d, expecting %d\n", str,
+ pred_result, pred->tests[j].expected);
+ printf(" lhs = %19llu (0x%016llx)\n", *pred->tests[j].lhs,
+ *pred->tests[j].lhs);
+ printf(" rhs = %19llu (0x%016llx)\n", *pred->tests[j].rhs,
+ *pred->tests[j].rhs);
+ ++failed;
+ } else {
+ uint64_t selresult;
+
+ selresult = (pred->selfunc) (*pred->tests[j].lhs, *pred->tests[j].rhs,
+ *pred->tests[j].select_a,
+ *pred->tests[j].select_b);
+ if (selresult != *pred->tests[j].select_expected) {
+ char str[64];
+
+ sprintf(str, pred->tests[j].fmt_string, pred->name);
+ printf("%s select: returned value is %d, expecting %d\n", str,
+ pred_result, pred->tests[j].expected);
+ printf(" lhs = %19llu (0x%016llx)\n", *pred->tests[j].lhs,
+ *pred->tests[j].lhs);
+ printf(" rhs = %19llu (0x%016llx)\n", *pred->tests[j].rhs,
+ *pred->tests[j].rhs);
+ printf(" true = %19llu (0x%016llx)\n", *pred->tests[j].select_a,
+ *pred->tests[j].select_a);
+ printf(" false = %19llu (0x%016llx)\n", *pred->tests[j].select_b,
+ *pred->tests[j].select_b);
+ ++failed;
+ }
+ }
+ }
+
+ printf(" %d tests performed, should be %d.\n", j, pred->n_tests);
+
+ return failed;
+}
+
+/* ~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~- */
+
+int
+test_i64_sext_i32(int in, int64_t expected) {
+ int64_t result = (int64_t) in;
+
+ if (result != expected) {
+ char str[64];
+ sprintf(str, "i64_sext_i32(%d) returns %lld\n", in, result);
+ return 1;
+ }
+
+ return 0;
+}
+
+int
+test_i64_sext_i16(short in, int64_t expected) {
+ int64_t result = (int64_t) in;
+
+ if (result != expected) {
+ char str[64];
+ sprintf(str, "i64_sext_i16(%hd) returns %lld\n", in, result);
+ return 1;
+ }
+
+ return 0;
+}
+
+int
+test_i64_sext_i8(signed char in, int64_t expected) {
+ int64_t result = (int64_t) in;
+
+ if (result != expected) {
+ char str[64];
+ sprintf(str, "i64_sext_i8(%d) returns %lld\n", in, result);
+ return 1;
+ }
+
+ return 0;
+}
+
+int
+test_i64_zext_i32(unsigned int in, uint64_t expected) {
+ uint64_t result = (uint64_t) in;
+
+ if (result != expected) {
+ char str[64];
+ sprintf(str, "i64_zext_i32(%u) returns %llu\n", in, result);
+ return 1;
+ }
+
+ return 0;
+}
+
+int
+test_i64_zext_i16(unsigned short in, uint64_t expected) {
+ uint64_t result = (uint64_t) in;
+
+ if (result != expected) {
+ char str[64];
+ sprintf(str, "i64_zext_i16(%hu) returns %llu\n", in, result);
+ return 1;
+ }
+
+ return 0;
+}
+
+int
+test_i64_zext_i8(unsigned char in, uint64_t expected) {
+ uint64_t result = (uint64_t) in;
+
+ if (result != expected) {
+ char str[64];
+ sprintf(str, "i64_zext_i8(%u) returns %llu\n", in, result);
+ return 1;
+ }
+
+ return 0;
+}
+
+/* ~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~- */
+
+int64_t
+i64_shl_const(int64_t a) {
+ return a << 10;
+}
+
+int64_t
+i64_shl(int64_t a, int amt) {
+ return a << amt;
+}
+
+uint64_t
+u64_shl_const(uint64_t a) {
+ return a << 10;
+}
+
+uint64_t
+u64_shl(uint64_t a, int amt) {
+ return a << amt;
+}
+
+int64_t
+i64_srl_const(int64_t a) {
+ return a >> 10;
+}
+
+int64_t
+i64_srl(int64_t a, int amt) {
+ return a >> amt;
+}
+
+uint64_t
+u64_srl_const(uint64_t a) {
+ return a >> 10;
+}
+
+uint64_t
+u64_srl(uint64_t a, int amt) {
+ return a >> amt;
+}
+
+int64_t
+i64_sra_const(int64_t a) {
+ return a >> 10;
+}
+
+int64_t
+i64_sra(int64_t a, int amt) {
+ return a >> amt;
+}
+
+uint64_t
+u64_sra_const(uint64_t a) {
+ return a >> 10;
+}
+
+uint64_t
+u64_sra(uint64_t a, int amt) {
+ return a >> amt;
+}
+
+int
+test_u64_constant_shift(const char *func_name, uint64_t (*func)(uint64_t), uint64_t a, uint64_t expected) {
+ uint64_t result = (*func)(a);
+
+ if (result != expected) {
+ printf("%s(0x%016llx) returns 0x%016llx, expected 0x%016llx\n", func_name, a, result, expected);
+ return 1;
+ }
+
+ return 0;
+}
+
+int
+test_i64_constant_shift(const char *func_name, int64_t (*func)(int64_t), int64_t a, int64_t expected) {
+ int64_t result = (*func)(a);
+
+ if (result != expected) {
+ printf("%s(0x%016llx) returns 0x%016llx, expected 0x%016llx\n", func_name, a, result, expected);
+ return 1;
+ }
+
+ return 0;
+}
+
+int
+test_u64_variable_shift(const char *func_name, uint64_t (*func)(uint64_t, int), uint64_t a, unsigned int b, uint64_t expected) {
+ uint64_t result = (*func)(a, b);
+
+ if (result != expected) {
+ printf("%s(0x%016llx, %d) returns 0x%016llx, expected 0x%016llx\n", func_name, a, b, result, expected);
+ return 1;
+ }
+
+ return 0;
+}
+
+int
+test_i64_variable_shift(const char *func_name, int64_t (*func)(int64_t, int), int64_t a, unsigned int b, int64_t expected) {
+ int64_t result = (*func)(a, b);
+
+ if (result != expected) {
+ printf("%s(0x%016llx, %d) returns 0x%016llx, expected 0x%016llx\n", func_name, a, b, result, expected);
+ return 1;
+ }
+
+ return 0;
+}
+
+/* ~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~- */
+
+int64_t i64_mul(int64_t a, int64_t b) {
+ return a * b;
+}
+
+/* ~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~- */
+
+int
+main(void)
+{
+ int i, j, failed = 0;
+ const char *something_failed = " %d tests failed.\n";
+ const char *all_tests_passed = " All tests passed.\n";
+
+ printf("tval_a = %20lld (0x%016llx)\n", tval_a, tval_a);
+ printf("tval_b = %20lld (0x%016llx)\n", tval_b, tval_b);
+ printf("tval_c = %20lld (0x%016llx)\n", tval_c, tval_c);
+ printf("tval_d = %20lld (0x%016llx)\n", tval_d, tval_d);
+ printf("tval_e = %20lld (0x%016llx)\n", tval_e, tval_e);
+ printf("tval_f = %20llu (0x%016llx)\n", tval_f, tval_f);
+ printf("tval_g = %20llu (0x%016llx)\n", tval_g, tval_g);
+ printf("----------------------------------------\n");
+
+ for (i = 0; i < ARR_SIZE(int64_preds); ++i) {
+ printf("%s series:\n", int64_preds[i].name);
+ if ((failed = compare_expect_int64(int64_preds + i)) > 0) {
+ printf(something_failed, failed);
+ } else {
+ printf(all_tests_passed);
+ }
+
+ printf("----------------------------------------\n");
+ }
+
+ for (i = 0; i < ARR_SIZE(uint64_preds); ++i) {
+ printf("%s series:\n", uint64_preds[i].name);
+ if ((failed = compare_expect_uint64(uint64_preds + i)) > 0) {
+ printf(something_failed, failed);
+ } else {
+ printf(all_tests_passed);
+ }
+
+ printf("----------------------------------------\n");
+ }
+
+ /*----------------------------------------------------------------------*/
+
+ puts("signed/zero-extend tests:");
+
+ failed = 0;
+ failed += test_i64_sext_i32(-1, -1LL);
+ failed += test_i64_sext_i32(10, 10LL);
+ failed += test_i64_sext_i32(0x7fffffff, 0x7fffffffLL);
+ failed += test_i64_sext_i16(-1, -1LL);
+ failed += test_i64_sext_i16(10, 10LL);
+ failed += test_i64_sext_i16(0x7fff, 0x7fffLL);
+ failed += test_i64_sext_i8(-1, -1LL);
+ failed += test_i64_sext_i8(10, 10LL);
+ failed += test_i64_sext_i8(0x7f, 0x7fLL);
+
+ failed += test_i64_zext_i32(0xffffffff, 0x00000000ffffffffLLU);
+ failed += test_i64_zext_i32(0x01234567, 0x0000000001234567LLU);
+ failed += test_i64_zext_i16(0xffff, 0x000000000000ffffLLU);
+ failed += test_i64_zext_i16(0x569a, 0x000000000000569aLLU);
+ failed += test_i64_zext_i8(0xff, 0x00000000000000ffLLU);
+ failed += test_i64_zext_i8(0xa0, 0x00000000000000a0LLU);
+
+ if (failed > 0) {
+ printf(" %d tests failed.\n", failed);
+ } else {
+ printf(" All tests passed.\n");
+ }
+
+ printf("----------------------------------------\n");
+
+ failed = 0;
+ puts("signed left/right shift tests:");
+ failed += test_i64_constant_shift("i64_shl_const", i64_shl_const, tval_a, 0x00047dc7ec114c00LL);
+ failed += test_i64_variable_shift("i64_shl", i64_shl, tval_a, 10, 0x00047dc7ec114c00LL);
+ failed += test_i64_constant_shift("i64_srl_const", i64_srl_const, tval_a, 0x0000000047dc7ec1LL);
+ failed += test_i64_variable_shift("i64_srl", i64_srl, tval_a, 10, 0x0000000047dc7ec1LL);
+ failed += test_i64_constant_shift("i64_sra_const", i64_sra_const, tval_a, 0x0000000047dc7ec1LL);
+ failed += test_i64_variable_shift("i64_sra", i64_sra, tval_a, 10, 0x0000000047dc7ec1LL);
+
+ if (failed > 0) {
+ printf(" %d tests ailed.\n", failed);
+ } else {
+ printf(" All tests passed.\n");
+ }
+
+ printf("----------------------------------------\n");
+
+ failed = 0;
+ puts("unsigned left/right shift tests:");
+ failed += test_u64_constant_shift("u64_shl_const", u64_shl_const, tval_f, 0xfffc1d404d7ae400LL);
+ failed += test_u64_variable_shift("u64_shl", u64_shl, tval_f, 10, 0xfffc1d404d7ae400LL);
+ failed += test_u64_constant_shift("u64_srl_const", u64_srl_const, tval_f, 0x003fffffc1d404d7LL);
+ failed += test_u64_variable_shift("u64_srl", u64_srl, tval_f, 10, 0x003fffffc1d404d7LL);
+ failed += test_i64_constant_shift("i64_sra_const", i64_sra_const, tval_f, 0xffffffffc1d404d7LL);
+ failed += test_i64_variable_shift("i64_sra", i64_sra, tval_f, 10, 0xffffffffc1d404d7LL);
+ failed += test_u64_constant_shift("u64_sra_const", u64_sra_const, tval_f, 0x003fffffc1d404d7LL);
+ failed += test_u64_variable_shift("u64_sra", u64_sra, tval_f, 10, 0x003fffffc1d404d7LL);
+
+ if (failed > 0) {
+ printf(" %d tests ailed.\n", failed);
+ } else {
+ printf(" All tests passed.\n");
+ }
+
+ printf("----------------------------------------\n");
+
+ int64_t result;
+
+ result = i64_mul(tval_g, tval_g);
+ printf("%20lld * %20lld = %20lld (0x%016llx)\n", tval_g, tval_g, result, result);
+ result = i64_mul(tval_d, tval_e);
+ printf("%20lld * %20lld = %20lld (0x%016llx)\n", tval_d, tval_e, result, result);
+ /* 0xba7a664f13077c9 */
+ result = i64_mul(tval_a, tval_b);
+ printf("%20lld * %20lld = %20lld (0x%016llx)\n", tval_a, tval_b, result, result);
+
+ printf("----------------------------------------\n");
+
+ return 0;
+}
diff --git a/test/CodeGen/CellSPU/useful-harnesses/i64operations.h b/test/CodeGen/CellSPU/useful-harnesses/i64operations.h
new file mode 100644
index 0000000..7a02794
--- /dev/null
+++ b/test/CodeGen/CellSPU/useful-harnesses/i64operations.h
@@ -0,0 +1,43 @@
+#define TRUE_VAL (!0)
+#define FALSE_VAL 0
+#define ARR_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
+
+typedef unsigned long long int uint64_t;
+typedef long long int int64_t;
+
+/* ~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~- */
+struct harness_int64_pred {
+ const char *fmt_string;
+ int64_t *lhs;
+ int64_t *rhs;
+ int64_t *select_a;
+ int64_t *select_b;
+ int expected;
+ int64_t *select_expected;
+};
+
+struct harness_uint64_pred {
+ const char *fmt_string;
+ uint64_t *lhs;
+ uint64_t *rhs;
+ uint64_t *select_a;
+ uint64_t *select_b;
+ int expected;
+ uint64_t *select_expected;
+};
+
+struct int64_pred_s {
+ const char *name;
+ int (*predfunc) (int64_t, int64_t);
+ int64_t (*selfunc) (int64_t, int64_t, int64_t, int64_t);
+ struct harness_int64_pred *tests;
+ int n_tests;
+};
+
+struct uint64_pred_s {
+ const char *name;
+ int (*predfunc) (uint64_t, uint64_t);
+ uint64_t (*selfunc) (uint64_t, uint64_t, uint64_t, uint64_t);
+ struct harness_uint64_pred *tests;
+ int n_tests;
+};
diff --git a/test/CodeGen/CellSPU/useful-harnesses/lit.local.cfg b/test/CodeGen/CellSPU/useful-harnesses/lit.local.cfg
new file mode 100644
index 0000000..e6f55ee
--- /dev/null
+++ b/test/CodeGen/CellSPU/useful-harnesses/lit.local.cfg
@@ -0,0 +1 @@
+config.suffixes = []
diff --git a/test/CodeGen/CellSPU/useful-harnesses/vecoperations.c b/test/CodeGen/CellSPU/useful-harnesses/vecoperations.c
new file mode 100644
index 0000000..c4c86e3
--- /dev/null
+++ b/test/CodeGen/CellSPU/useful-harnesses/vecoperations.c
@@ -0,0 +1,179 @@
+#include <stdio.h>
+
+typedef unsigned char v16i8 __attribute__((ext_vector_type(16)));
+typedef short v8i16 __attribute__((ext_vector_type(16)));
+typedef int v4i32 __attribute__((ext_vector_type(4)));
+typedef float v4f32 __attribute__((ext_vector_type(4)));
+typedef long long v2i64 __attribute__((ext_vector_type(2)));
+typedef double v2f64 __attribute__((ext_vector_type(2)));
+
+void print_v16i8(const char *str, const v16i8 v) {
+ union {
+ unsigned char elts[16];
+ v16i8 vec;
+ } tv;
+ tv.vec = v;
+ printf("%s = { %hhu, %hhu, %hhu, %hhu, %hhu, %hhu, %hhu, "
+ "%hhu, %hhu, %hhu, %hhu, %hhu, %hhu, %hhu, "
+ "%hhu, %hhu }\n",
+ str, tv.elts[0], tv.elts[1], tv.elts[2], tv.elts[3], tv.elts[4], tv.elts[5],
+ tv.elts[6], tv.elts[7], tv.elts[8], tv.elts[9], tv.elts[10], tv.elts[11],
+ tv.elts[12], tv.elts[13], tv.elts[14], tv.elts[15]);
+}
+
+void print_v16i8_hex(const char *str, const v16i8 v) {
+ union {
+ unsigned char elts[16];
+ v16i8 vec;
+ } tv;
+ tv.vec = v;
+ printf("%s = { 0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, "
+ "0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, "
+ "0x%02hhx, 0x%02hhx }\n",
+ str, tv.elts[0], tv.elts[1], tv.elts[2], tv.elts[3], tv.elts[4], tv.elts[5],
+ tv.elts[6], tv.elts[7], tv.elts[8], tv.elts[9], tv.elts[10], tv.elts[11],
+ tv.elts[12], tv.elts[13], tv.elts[14], tv.elts[15]);
+}
+
+void print_v8i16_hex(const char *str, v8i16 v) {
+ union {
+ short elts[8];
+ v8i16 vec;
+ } tv;
+ tv.vec = v;
+ printf("%s = { 0x%04hx, 0x%04hx, 0x%04hx, 0x%04hx, 0x%04hx, "
+ "0x%04hx, 0x%04hx, 0x%04hx }\n",
+ str, tv.elts[0], tv.elts[1], tv.elts[2], tv.elts[3], tv.elts[4],
+ tv.elts[5], tv.elts[6], tv.elts[7]);
+}
+
+void print_v4i32(const char *str, v4i32 v) {
+ printf("%s = { %d, %d, %d, %d }\n", str, v.x, v.y, v.z, v.w);
+}
+
+void print_v4f32(const char *str, v4f32 v) {
+ printf("%s = { %f, %f, %f, %f }\n", str, v.x, v.y, v.z, v.w);
+}
+
+void print_v2i64(const char *str, v2i64 v) {
+ printf("%s = { %lld, %lld }\n", str, v.x, v.y);
+}
+
+void print_v2f64(const char *str, v2f64 v) {
+ printf("%s = { %g, %g }\n", str, v.x, v.y);
+}
+
+/*----------------------------------------------------------------------*/
+
+v16i8 v16i8_mpy(v16i8 v1, v16i8 v2) {
+ return v1 * v2;
+}
+
+v16i8 v16i8_add(v16i8 v1, v16i8 v2) {
+ return v1 + v2;
+}
+
+v4i32 v4i32_shuffle_1(v4i32 a) {
+ v4i32 c2 = a.yzwx;
+ return c2;
+}
+
+v4i32 v4i32_shuffle_2(v4i32 a) {
+ v4i32 c2 = a.zwxy;
+ return c2;
+}
+
+v4i32 v4i32_shuffle_3(v4i32 a) {
+ v4i32 c2 = a.wxyz;
+ return c2;
+}
+
+v4i32 v4i32_shuffle_4(v4i32 a) {
+ v4i32 c2 = a.xyzw;
+ return c2;
+}
+
+v4i32 v4i32_shuffle_5(v4i32 a) {
+ v4i32 c2 = a.xwzy;
+ return c2;
+}
+
+v4f32 v4f32_shuffle_1(v4f32 a) {
+ v4f32 c2 = a.yzwx;
+ return c2;
+}
+
+v4f32 v4f32_shuffle_2(v4f32 a) {
+ v4f32 c2 = a.zwxy;
+ return c2;
+}
+
+v4f32 v4f32_shuffle_3(v4f32 a) {
+ v4f32 c2 = a.wxyz;
+ return c2;
+}
+
+v4f32 v4f32_shuffle_4(v4f32 a) {
+ v4f32 c2 = a.xyzw;
+ return c2;
+}
+
+v4f32 v4f32_shuffle_5(v4f32 a) {
+ v4f32 c2 = a.xwzy;
+ return c2;
+}
+
+v2i64 v2i64_shuffle(v2i64 a) {
+ v2i64 c2 = a.yx;
+ return c2;
+}
+
+v2f64 v2f64_shuffle(v2f64 a) {
+ v2f64 c2 = a.yx;
+ return c2;
+}
+
+int main(void) {
+ v16i8 v00 = { 0xf4, 0xad, 0x01, 0xe9, 0x51, 0x78, 0xc1, 0x8a,
+ 0x94, 0x7c, 0x49, 0x6c, 0x21, 0x32, 0xb2, 0x04 };
+ v16i8 va0 = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 };
+ v16i8 va1 = { 0x11, 0x83, 0x4b, 0x63, 0xff, 0x90, 0x32, 0xe5,
+ 0x5a, 0xaa, 0x20, 0x01, 0x0d, 0x15, 0x77, 0x05 };
+ v8i16 v01 = { 0x1a87, 0x0a14, 0x5014, 0xfff0,
+ 0xe194, 0x0184, 0x801e, 0x5940 };
+ v4i32 v1 = { 1, 2, 3, 4 };
+ v4f32 v2 = { 1.0, 2.0, 3.0, 4.0 };
+ v2i64 v3 = { 691043ll, 910301513ll };
+ v2f64 v4 = { 5.8e56, 9.103e-62 };
+
+ puts("---- vector tests start ----");
+
+ print_v16i8_hex("v00 ", v00);
+ print_v16i8_hex("va0 ", va0);
+ print_v16i8_hex("va1 ", va1);
+ print_v16i8_hex("va0 x va1 ", v16i8_mpy(va0, va1));
+ print_v16i8_hex("va0 + va1 ", v16i8_add(va0, va1));
+ print_v8i16_hex("v01 ", v01);
+
+ print_v4i32("v4i32_shuffle_1(1, 2, 3, 4)", v4i32_shuffle_1(v1));
+ print_v4i32("v4i32_shuffle_2(1, 2, 3, 4)", v4i32_shuffle_2(v1));
+ print_v4i32("v4i32_shuffle_3(1, 2, 3, 4)", v4i32_shuffle_3(v1));
+ print_v4i32("v4i32_shuffle_4(1, 2, 3, 4)", v4i32_shuffle_4(v1));
+ print_v4i32("v4i32_shuffle_5(1, 2, 3, 4)", v4i32_shuffle_5(v1));
+
+ print_v4f32("v4f32_shuffle_1(1, 2, 3, 4)", v4f32_shuffle_1(v2));
+ print_v4f32("v4f32_shuffle_2(1, 2, 3, 4)", v4f32_shuffle_2(v2));
+ print_v4f32("v4f32_shuffle_3(1, 2, 3, 4)", v4f32_shuffle_3(v2));
+ print_v4f32("v4f32_shuffle_4(1, 2, 3, 4)", v4f32_shuffle_4(v2));
+ print_v4f32("v4f32_shuffle_5(1, 2, 3, 4)", v4f32_shuffle_5(v2));
+
+ print_v2i64("v3 ", v3);
+ print_v2i64("v2i64_shuffle ", v2i64_shuffle(v3));
+ print_v2f64("v4 ", v4);
+ print_v2f64("v2f64_shuffle ", v2f64_shuffle(v4));
+
+ puts("---- vector tests end ----");
+
+ return 0;
+}
diff --git a/test/CodeGen/CellSPU/vec_const.ll b/test/CodeGen/CellSPU/vec_const.ll
new file mode 100644
index 0000000..24c05c6
--- /dev/null
+++ b/test/CodeGen/CellSPU/vec_const.ll
@@ -0,0 +1,154 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: llc < %s -march=cellspu -mattr=large_mem > %t2.s
+; RUN: grep -w il %t1.s | count 3
+; RUN: grep ilhu %t1.s | count 8
+; RUN: grep -w ilh %t1.s | count 5
+; RUN: grep iohl %t1.s | count 7
+; RUN: grep lqa %t1.s | count 6
+; RUN: grep 24672 %t1.s | count 2
+; RUN: grep 16429 %t1.s | count 1
+; RUN: grep 63572 %t1.s | count 1
+; RUN: grep 4660 %t1.s | count 1
+; RUN: grep 22136 %t1.s | count 1
+; RUN: grep 43981 %t1.s | count 1
+; RUN: grep 61202 %t1.s | count 1
+; RUN: grep 16393 %t1.s | count 1
+; RUN: grep 8699 %t1.s | count 1
+; RUN: grep 21572 %t1.s | count 1
+; RUN: grep 11544 %t1.s | count 1
+; RUN: grep 1311768467750121234 %t1.s | count 1
+; RUN: grep lqd %t2.s | count 6
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
+target triple = "spu-unknown-elf"
+
+; Vector constant load tests:
+
+; IL <reg>, 2
+define <4 x i32> @v4i32_constvec() {
+ ret <4 x i32> < i32 2, i32 2, i32 2, i32 2 >
+}
+
+; Spill to constant pool
+define <4 x i32> @v4i32_constpool() {
+ ret <4 x i32> < i32 2, i32 1, i32 1, i32 2 >
+}
+
+; Max negative range for IL
+define <4 x i32> @v4i32_constvec_2() {
+ ret <4 x i32> < i32 -32768, i32 -32768, i32 -32768, i32 -32768 >
+}
+
+; ILHU <reg>, 73 (0x49)
+; 4784128 = 0x490000
+define <4 x i32> @v4i32_constvec_3() {
+ ret <4 x i32> < i32 4784128, i32 4784128,
+ i32 4784128, i32 4784128 >
+}
+
+; ILHU <reg>, 61 (0x3d)
+; IOHL <reg>, 15395 (0x3c23)
+define <4 x i32> @v4i32_constvec_4() {
+ ret <4 x i32> < i32 4013091, i32 4013091,
+ i32 4013091, i32 4013091 >
+}
+
+; ILHU <reg>, 0x5050 (20560)
+; IOHL <reg>, 0x5050 (20560)
+; Tests for whether we expand the size of the bit pattern properly, because
+; this could be interpreted as an i8 pattern (0x50)
+define <4 x i32> @v4i32_constvec_5() {
+ ret <4 x i32> < i32 1347440720, i32 1347440720,
+ i32 1347440720, i32 1347440720 >
+}
+
+; ILH
+define <8 x i16> @v8i16_constvec_1() {
+ ret <8 x i16> < i16 32767, i16 32767, i16 32767, i16 32767,
+ i16 32767, i16 32767, i16 32767, i16 32767 >
+}
+
+; ILH
+define <8 x i16> @v8i16_constvec_2() {
+ ret <8 x i16> < i16 511, i16 511, i16 511, i16 511, i16 511,
+ i16 511, i16 511, i16 511 >
+}
+
+; ILH
+define <8 x i16> @v8i16_constvec_3() {
+ ret <8 x i16> < i16 -512, i16 -512, i16 -512, i16 -512, i16 -512,
+ i16 -512, i16 -512, i16 -512 >
+}
+
+; ILH <reg>, 24672 (0x6060)
+; Tests whether we expand the size of the bit pattern properly, because
+; this could be interpreted as an i8 pattern (0x60)
+define <8 x i16> @v8i16_constvec_4() {
+ ret <8 x i16> < i16 24672, i16 24672, i16 24672, i16 24672, i16 24672,
+ i16 24672, i16 24672, i16 24672 >
+}
+
+; ILH <reg>, 24672 (0x6060)
+; Tests whether we expand the size of the bit pattern properly, because
+; this is an i8 pattern but has to be expanded out to i16 to load it
+; properly into the vector register.
+define <16 x i8> @v16i8_constvec_1() {
+ ret <16 x i8> < i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96,
+ i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96 >
+}
+
+define <4 x float> @v4f32_constvec_1() {
+entry:
+ ret <4 x float> < float 0x4005BF0A80000000,
+ float 0x4005BF0A80000000,
+ float 0x4005BF0A80000000,
+ float 0x4005BF0A80000000 >
+}
+
+define <4 x float> @v4f32_constvec_2() {
+entry:
+ ret <4 x float> < float 0.000000e+00,
+ float 0.000000e+00,
+ float 0.000000e+00,
+ float 0.000000e+00 >
+}
+
+
+define <4 x float> @v4f32_constvec_3() {
+entry:
+ ret <4 x float> < float 0x4005BF0A80000000,
+ float 0x3810000000000000,
+ float 0x47EFFFFFE0000000,
+ float 0x400921FB60000000 >
+}
+
+; 1311768467750121234 => 0x 12345678 abcdef12
+; HI32_hi: 4660
+; HI32_lo: 22136
+; LO32_hi: 43981
+; LO32_lo: 61202
+define <2 x i64> @i64_constvec_1() {
+entry:
+ ret <2 x i64> < i64 1311768467750121234,
+ i64 1311768467750121234 >
+}
+
+define <2 x i64> @i64_constvec_2() {
+entry:
+ ret <2 x i64> < i64 1, i64 1311768467750121234 >
+}
+
+define <2 x double> @f64_constvec_1() {
+entry:
+ ret <2 x double> < double 0x400921fb54442d18,
+ double 0xbff6a09e667f3bcd >
+}
+
+; 0x400921fb 54442d18 ->
+; (ILHU 0x4009 [16393]/IOHL 0x21fb [ 8699])
+; (ILHU 0x5444 [21572]/IOHL 0x2d18 [11544])
+define <2 x double> @f64_constvec_2() {
+entry:
+ ret <2 x double> < double 0x400921fb54442d18,
+ double 0x400921fb54442d18 >
+}
diff --git a/test/CodeGen/CellSPU/vecinsert.ll b/test/CodeGen/CellSPU/vecinsert.ll
new file mode 100644
index 0000000..9a00c1f
--- /dev/null
+++ b/test/CodeGen/CellSPU/vecinsert.ll
@@ -0,0 +1,120 @@
+; RUN: llc < %s -march=cellspu > %t1.s
+; RUN: grep cbd %t1.s | count 5
+; RUN: grep chd %t1.s | count 5
+; RUN: grep cwd %t1.s | count 10
+; RUN: grep -w il %t1.s | count 5
+; RUN: grep -w ilh %t1.s | count 6
+; RUN: grep iohl %t1.s | count 1
+; RUN: grep ilhu %t1.s | count 4
+; RUN: grep shufb %t1.s | count 26
+; RUN: grep 17219 %t1.s | count 1
+; RUN: grep 22598 %t1.s | count 1
+; RUN: grep -- -39 %t1.s | count 1
+; RUN: grep 24 %t1.s | count 1
+; RUN: grep 1159 %t1.s | count 1
+; ModuleID = 'vecinsert.bc'
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
+target triple = "spu-unknown-elf"
+
+; 67 -> 0x43, as 8-bit vector constant load = 0x4343 (17219)0x4343
+define <16 x i8> @test_v16i8(<16 x i8> %P, i8 %x) {
+entry:
+ %tmp1 = insertelement <16 x i8> %P, i8 %x, i32 10
+ %tmp1.1 = insertelement <16 x i8> %tmp1, i8 67, i32 7
+ %tmp1.2 = insertelement <16 x i8> %tmp1.1, i8 %x, i32 15
+ ret <16 x i8> %tmp1.2
+}
+
+; 22598 -> 0x5846
+define <8 x i16> @test_v8i16(<8 x i16> %P, i16 %x) {
+entry:
+ %tmp1 = insertelement <8 x i16> %P, i16 %x, i32 5
+ %tmp1.1 = insertelement <8 x i16> %tmp1, i16 22598, i32 7
+ %tmp1.2 = insertelement <8 x i16> %tmp1.1, i16 %x, i32 2
+ ret <8 x i16> %tmp1.2
+}
+
+; 1574023 -> 0x180487 (ILHU 24/IOHL 1159)
+define <4 x i32> @test_v4i32_1(<4 x i32> %P, i32 %x) {
+entry:
+ %tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2
+ %tmp1.1 = insertelement <4 x i32> %tmp1, i32 1574023, i32 1
+ %tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3
+ ret <4 x i32> %tmp1.2
+}
+
+; Should generate IL for the load
+define <4 x i32> @test_v4i32_2(<4 x i32> %P, i32 %x) {
+entry:
+ %tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2
+ %tmp1.1 = insertelement <4 x i32> %tmp1, i32 -39, i32 1
+ %tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3
+ ret <4 x i32> %tmp1.2
+}
+
+define void @variable_v16i8_1(<16 x i8>* %a, i32 %i) nounwind {
+entry:
+ %arrayidx = getelementptr <16 x i8>* %a, i32 %i
+ %tmp2 = load <16 x i8>* %arrayidx
+ %tmp3 = insertelement <16 x i8> %tmp2, i8 1, i32 1
+ %tmp8 = insertelement <16 x i8> %tmp3, i8 2, i32 11
+ store <16 x i8> %tmp8, <16 x i8>* %arrayidx
+ ret void
+}
+
+define void @variable_v8i16_1(<8 x i16>* %a, i32 %i) nounwind {
+entry:
+ %arrayidx = getelementptr <8 x i16>* %a, i32 %i
+ %tmp2 = load <8 x i16>* %arrayidx
+ %tmp3 = insertelement <8 x i16> %tmp2, i16 1, i32 1
+ %tmp8 = insertelement <8 x i16> %tmp3, i16 2, i32 6
+ store <8 x i16> %tmp8, <8 x i16>* %arrayidx
+ ret void
+}
+
+define void @variable_v4i32_1(<4 x i32>* %a, i32 %i) nounwind {
+entry:
+ %arrayidx = getelementptr <4 x i32>* %a, i32 %i
+ %tmp2 = load <4 x i32>* %arrayidx
+ %tmp3 = insertelement <4 x i32> %tmp2, i32 1, i32 1
+ %tmp8 = insertelement <4 x i32> %tmp3, i32 2, i32 2
+ store <4 x i32> %tmp8, <4 x i32>* %arrayidx
+ ret void
+}
+
+define void @variable_v4f32_1(<4 x float>* %a, i32 %i) nounwind {
+entry:
+ %arrayidx = getelementptr <4 x float>* %a, i32 %i
+ %tmp2 = load <4 x float>* %arrayidx
+ %tmp3 = insertelement <4 x float> %tmp2, float 1.000000e+00, i32 1
+ %tmp8 = insertelement <4 x float> %tmp3, float 2.000000e+00, i32 2
+ store <4 x float> %tmp8, <4 x float>* %arrayidx
+ ret void
+}
+
+define void @variable_v2i64_1(<2 x i64>* %a, i32 %i) nounwind {
+entry:
+ %arrayidx = getelementptr <2 x i64>* %a, i32 %i
+ %tmp2 = load <2 x i64>* %arrayidx
+ %tmp3 = insertelement <2 x i64> %tmp2, i64 615, i32 0
+ store <2 x i64> %tmp3, <2 x i64>* %arrayidx
+ ret void
+}
+
+define void @variable_v2i64_2(<2 x i64>* %a, i32 %i) nounwind {
+entry:
+ %arrayidx = getelementptr <2 x i64>* %a, i32 %i
+ %tmp2 = load <2 x i64>* %arrayidx
+ %tmp3 = insertelement <2 x i64> %tmp2, i64 615, i32 1
+ store <2 x i64> %tmp3, <2 x i64>* %arrayidx
+ ret void
+}
+
+define void @variable_v2f64_1(<2 x double>* %a, i32 %i) nounwind {
+entry:
+ %arrayidx = getelementptr <2 x double>* %a, i32 %i
+ %tmp2 = load <2 x double>* %arrayidx
+ %tmp3 = insertelement <2 x double> %tmp2, double 1.000000e+00, i32 1
+ store <2 x double> %tmp3, <2 x double>* %arrayidx
+ ret void
+}
diff --git a/test/CodeGen/Generic/2002-04-14-UnexpectedUnsignedType.ll b/test/CodeGen/Generic/2002-04-14-UnexpectedUnsignedType.ll
new file mode 100644
index 0000000..dd382cf
--- /dev/null
+++ b/test/CodeGen/Generic/2002-04-14-UnexpectedUnsignedType.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s
+
+; This caused the backend to assert out with:
+; SparcInstrInfo.cpp:103: failed assertion `0 && "Unexpected unsigned type"'
+;
+
+declare void @bar(i8*)
+
+define void @foo() {
+ %cast225 = inttoptr i64 123456 to i8* ; <i8*> [#uses=1]
+ call void @bar( i8* %cast225 )
+ ret void
+}
diff --git a/test/CodeGen/Generic/2002-04-16-StackFrameSizeAlignment.ll b/test/CodeGen/Generic/2002-04-16-StackFrameSizeAlignment.ll
new file mode 100644
index 0000000..751ed40
--- /dev/null
+++ b/test/CodeGen/Generic/2002-04-16-StackFrameSizeAlignment.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s
+
+; Compiling this file produces:
+; Sparc.cpp:91: failed assertion `(offset - OFFSET) % getStackFrameSizeAlignment() == 0'
+;
+declare i32 @SIM(i8*, i8*, i32, i32, i32, [256 x i32]*, i32, i32, i32)
+
+define void @foo() {
+bb0:
+ %V = alloca [256 x i32], i32 256 ; <[256 x i32]*> [#uses=1]
+ call i32 @SIM( i8* null, i8* null, i32 0, i32 0, i32 0, [256 x i32]* %V, i32 0, i32 0, i32 2 ) ; <i32>:0 [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/Generic/2003-05-27-phifcmpd.ll b/test/CodeGen/Generic/2003-05-27-phifcmpd.ll
new file mode 100644
index 0000000..6fb1799
--- /dev/null
+++ b/test/CodeGen/Generic/2003-05-27-phifcmpd.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s
+
+define void @QRiterate(i32 %p.1, double %tmp.212) {
+entry:
+ %tmp.184 = icmp sgt i32 %p.1, 0 ; <i1> [#uses=1]
+ br i1 %tmp.184, label %shortcirc_next.1, label %shortcirc_done.1
+
+shortcirc_next.1: ; preds = %shortcirc_done.1, %entry
+ %tmp.213 = fcmp une double %tmp.212, 0.000000e+00 ; <i1> [#uses=1]
+ br label %shortcirc_done.1
+
+shortcirc_done.1: ; preds = %shortcirc_next.1, %entry
+ %val.1 = phi i1 [ false, %entry ], [ %tmp.213, %shortcirc_next.1 ] ; <i1> [#uses=1]
+ br i1 %val.1, label %shortcirc_next.1, label %exit.1
+
+exit.1: ; preds = %shortcirc_done.1
+ ret void
+}
+
diff --git a/test/CodeGen/Generic/2003-05-27-useboolinotherbb.ll b/test/CodeGen/Generic/2003-05-27-useboolinotherbb.ll
new file mode 100644
index 0000000..14bb000
--- /dev/null
+++ b/test/CodeGen/Generic/2003-05-27-useboolinotherbb.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s
+
+define void @QRiterate(double %tmp.212) {
+ %tmp.213 = fcmp une double %tmp.212, 0.000000e+00 ; <i1> [#uses=1]
+ br label %shortcirc_next.1
+
+shortcirc_next.1: ; preds = %shortcirc_next.1, %0
+ br i1 %tmp.213, label %shortcirc_next.1, label %exit.1
+
+exit.1: ; preds = %shortcirc_next.1
+ ret void
+}
+
diff --git a/test/CodeGen/Generic/2003-05-27-usefsubasbool.ll b/test/CodeGen/Generic/2003-05-27-usefsubasbool.ll
new file mode 100644
index 0000000..cc0eb5c
--- /dev/null
+++ b/test/CodeGen/Generic/2003-05-27-usefsubasbool.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s
+
+define void @QRiterate(double %tmp.212) {
+entry:
+ br label %shortcirc_next.1
+
+shortcirc_next.1: ; preds = %shortcirc_next.1, %entry
+ %tmp.213 = fcmp une double %tmp.212, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %tmp.213, label %shortcirc_next.1, label %exit.1
+
+exit.1: ; preds = %shortcirc_next.1
+ ret void
+}
+
diff --git a/test/CodeGen/Generic/2003-05-28-ManyArgs.ll b/test/CodeGen/Generic/2003-05-28-ManyArgs.ll
new file mode 100644
index 0000000..c6fbdae
--- /dev/null
+++ b/test/CodeGen/Generic/2003-05-28-ManyArgs.ll
@@ -0,0 +1,153 @@
+; RUN: llc < %s
+
+;; Date: May 28, 2003.
+;; From: test/Programs/External/SPEC/CINT2000/175.vpr.llvm.bc
+;; Function: int %main(int %argc.1, sbyte** %argv.1)
+;;
+;; Error: A function call with about 56 arguments causes an assertion failure
+;; in llc because the register allocator cannot find a register
+;; not used explicitly by the call instruction.
+;;
+;; Cause: Regalloc was not keeping track of free registers correctly.
+;; It was counting the registers allocated to all outgoing arguments,
+;; even though most of those are copied to the stack (so those
+;; registers are not actually used by the call instruction).
+;;
+;; Fixed: By rewriting selection and allocation so that selection explicitly
+;; inserts all copy operations required for passing arguments and
+;; for the return value of a call, copying to/from registers
+;; and/or to stack locations as needed.
+;;
+ %struct..s_annealing_sched = type { i32, float, float, float, float }
+ %struct..s_chan = type { i32, float, float, float, float }
+ %struct..s_det_routing_arch = type { i32, float, float, float, i32, i32, i16, i16, i16, float, float }
+ %struct..s_placer_opts = type { i32, float, i32, i32, i8*, i32, i32 }
+ %struct..s_router_opts = type { float, float, float, float, float, i32, i32, i32, i32 }
+ %struct..s_segment_inf = type { float, i32, i16, i16, float, float, i32, float, float }
+ %struct..s_switch_inf = type { i32, float, float, float, float }
+
+define i32 @main(i32 %argc.1, i8** %argv.1) {
+entry:
+ %net_file = alloca [300 x i8] ; <[300 x i8]*> [#uses=1]
+ %place_file = alloca [300 x i8] ; <[300 x i8]*> [#uses=1]
+ %arch_file = alloca [300 x i8] ; <[300 x i8]*> [#uses=1]
+ %route_file = alloca [300 x i8] ; <[300 x i8]*> [#uses=1]
+ %full_stats = alloca i32 ; <i32*> [#uses=1]
+ %operation = alloca i32 ; <i32*> [#uses=1]
+ %verify_binary_search = alloca i32 ; <i32*> [#uses=1]
+ %show_graphics = alloca i32 ; <i32*> [#uses=1]
+ %annealing_sched = alloca %struct..s_annealing_sched ; <%struct..s_annealing_sched*> [#uses=5]
+ %placer_opts = alloca %struct..s_placer_opts ; <%struct..s_placer_opts*> [#uses=7]
+ %router_opts = alloca %struct..s_router_opts ; <%struct..s_router_opts*> [#uses=9]
+ %det_routing_arch = alloca %struct..s_det_routing_arch ; <%struct..s_det_routing_arch*> [#uses=11]
+ %segment_inf = alloca %struct..s_segment_inf* ; <%struct..s_segment_inf**> [#uses=1]
+ %timing_inf = alloca { i32, float, float, float, float, float, float, float, float, float, float } ; <{ i32, float, float, float, float, float, float, float, float, float, float }*> [#uses=11]
+ %tmp.101 = getelementptr %struct..s_placer_opts* %placer_opts, i64 0, i32 4 ; <i8**> [#uses=1]
+ %tmp.105 = getelementptr [300 x i8]* %net_file, i64 0, i64 0 ; <i8*> [#uses=1]
+ %tmp.106 = getelementptr [300 x i8]* %arch_file, i64 0, i64 0 ; <i8*> [#uses=1]
+ %tmp.107 = getelementptr [300 x i8]* %place_file, i64 0, i64 0 ; <i8*> [#uses=1]
+ %tmp.108 = getelementptr [300 x i8]* %route_file, i64 0, i64 0 ; <i8*> [#uses=1]
+ %tmp.109 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 0 ; <i32*> [#uses=1]
+ %tmp.112 = getelementptr %struct..s_placer_opts* %placer_opts, i64 0, i32 0 ; <i32*> [#uses=1]
+ %tmp.114 = getelementptr %struct..s_placer_opts* %placer_opts, i64 0, i32 6 ; <i32*> [#uses=1]
+ %tmp.118 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 7 ; <i32*> [#uses=1]
+ %tmp.135 = load i32* %operation ; <i32> [#uses=1]
+ %tmp.137 = load i32* %tmp.112 ; <i32> [#uses=1]
+ %tmp.138 = getelementptr %struct..s_placer_opts* %placer_opts, i64 0, i32 1 ; <float*> [#uses=1]
+ %tmp.139 = load float* %tmp.138 ; <float> [#uses=1]
+ %tmp.140 = getelementptr %struct..s_placer_opts* %placer_opts, i64 0, i32 2 ; <i32*> [#uses=1]
+ %tmp.141 = load i32* %tmp.140 ; <i32> [#uses=1]
+ %tmp.142 = getelementptr %struct..s_placer_opts* %placer_opts, i64 0, i32 3 ; <i32*> [#uses=1]
+ %tmp.143 = load i32* %tmp.142 ; <i32> [#uses=1]
+ %tmp.145 = load i8** %tmp.101 ; <i8*> [#uses=1]
+ %tmp.146 = getelementptr %struct..s_placer_opts* %placer_opts, i64 0, i32 5 ; <i32*> [#uses=1]
+ %tmp.147 = load i32* %tmp.146 ; <i32> [#uses=1]
+ %tmp.149 = load i32* %tmp.114 ; <i32> [#uses=1]
+ %tmp.154 = load i32* %full_stats ; <i32> [#uses=1]
+ %tmp.155 = load i32* %verify_binary_search ; <i32> [#uses=1]
+ %tmp.156 = getelementptr %struct..s_annealing_sched* %annealing_sched, i64 0, i32 0 ; <i32*> [#uses=1]
+ %tmp.157 = load i32* %tmp.156 ; <i32> [#uses=1]
+ %tmp.158 = getelementptr %struct..s_annealing_sched* %annealing_sched, i64 0, i32 1 ; <float*> [#uses=1]
+ %tmp.159 = load float* %tmp.158 ; <float> [#uses=1]
+ %tmp.160 = getelementptr %struct..s_annealing_sched* %annealing_sched, i64 0, i32 2 ; <float*> [#uses=1]
+ %tmp.161 = load float* %tmp.160 ; <float> [#uses=1]
+ %tmp.162 = getelementptr %struct..s_annealing_sched* %annealing_sched, i64 0, i32 3 ; <float*> [#uses=1]
+ %tmp.163 = load float* %tmp.162 ; <float> [#uses=1]
+ %tmp.164 = getelementptr %struct..s_annealing_sched* %annealing_sched, i64 0, i32 4 ; <float*> [#uses=1]
+ %tmp.165 = load float* %tmp.164 ; <float> [#uses=1]
+ %tmp.166 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 0 ; <float*> [#uses=1]
+ %tmp.167 = load float* %tmp.166 ; <float> [#uses=1]
+ %tmp.168 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 1 ; <float*> [#uses=1]
+ %tmp.169 = load float* %tmp.168 ; <float> [#uses=1]
+ %tmp.170 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 2 ; <float*> [#uses=1]
+ %tmp.171 = load float* %tmp.170 ; <float> [#uses=1]
+ %tmp.172 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 3 ; <float*> [#uses=1]
+ %tmp.173 = load float* %tmp.172 ; <float> [#uses=1]
+ %tmp.174 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 4 ; <float*> [#uses=1]
+ %tmp.175 = load float* %tmp.174 ; <float> [#uses=1]
+ %tmp.176 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 5 ; <i32*> [#uses=1]
+ %tmp.177 = load i32* %tmp.176 ; <i32> [#uses=1]
+ %tmp.178 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 6 ; <i32*> [#uses=1]
+ %tmp.179 = load i32* %tmp.178 ; <i32> [#uses=1]
+ %tmp.181 = load i32* %tmp.118 ; <i32> [#uses=1]
+ %tmp.182 = getelementptr %struct..s_router_opts* %router_opts, i64 0, i32 8 ; <i32*> [#uses=1]
+ %tmp.183 = load i32* %tmp.182 ; <i32> [#uses=1]
+ %tmp.184 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 0 ; <i32*> [#uses=1]
+ %tmp.185 = load i32* %tmp.184 ; <i32> [#uses=1]
+ %tmp.186 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 1 ; <float*> [#uses=1]
+ %tmp.187 = load float* %tmp.186 ; <float> [#uses=1]
+ %tmp.188 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 2 ; <float*> [#uses=1]
+ %tmp.189 = load float* %tmp.188 ; <float> [#uses=1]
+ %tmp.190 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 3 ; <float*> [#uses=1]
+ %tmp.191 = load float* %tmp.190 ; <float> [#uses=1]
+ %tmp.192 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 4 ; <i32*> [#uses=1]
+ %tmp.193 = load i32* %tmp.192 ; <i32> [#uses=1]
+ %tmp.194 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 5 ; <i32*> [#uses=1]
+ %tmp.195 = load i32* %tmp.194 ; <i32> [#uses=1]
+ %tmp.196 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 6 ; <i16*> [#uses=1]
+ %tmp.197 = load i16* %tmp.196 ; <i16> [#uses=1]
+ %tmp.198 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 7 ; <i16*> [#uses=1]
+ %tmp.199 = load i16* %tmp.198 ; <i16> [#uses=1]
+ %tmp.200 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 8 ; <i16*> [#uses=1]
+ %tmp.201 = load i16* %tmp.200 ; <i16> [#uses=1]
+ %tmp.202 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 9 ; <float*> [#uses=1]
+ %tmp.203 = load float* %tmp.202 ; <float> [#uses=1]
+ %tmp.204 = getelementptr %struct..s_det_routing_arch* %det_routing_arch, i64 0, i32 10 ; <float*> [#uses=1]
+ %tmp.205 = load float* %tmp.204 ; <float> [#uses=1]
+ %tmp.206 = load %struct..s_segment_inf** %segment_inf ; <%struct..s_segment_inf*> [#uses=1]
+ %tmp.208 = load i32* %tmp.109 ; <i32> [#uses=1]
+ %tmp.209 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 1 ; <float*> [#uses=1]
+ %tmp.210 = load float* %tmp.209 ; <float> [#uses=1]
+ %tmp.211 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 2 ; <float*> [#uses=1]
+ %tmp.212 = load float* %tmp.211 ; <float> [#uses=1]
+ %tmp.213 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 3 ; <float*> [#uses=1]
+ %tmp.214 = load float* %tmp.213 ; <float> [#uses=1]
+ %tmp.215 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 4 ; <float*> [#uses=1]
+ %tmp.216 = load float* %tmp.215 ; <float> [#uses=1]
+ %tmp.217 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 5 ; <float*> [#uses=1]
+ %tmp.218 = load float* %tmp.217 ; <float> [#uses=1]
+ %tmp.219 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 6 ; <float*> [#uses=1]
+ %tmp.220 = load float* %tmp.219 ; <float> [#uses=1]
+ %tmp.221 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 7 ; <float*> [#uses=1]
+ %tmp.222 = load float* %tmp.221 ; <float> [#uses=1]
+ %tmp.223 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 8 ; <float*> [#uses=1]
+ %tmp.224 = load float* %tmp.223 ; <float> [#uses=1]
+ %tmp.225 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 9 ; <float*> [#uses=1]
+ %tmp.226 = load float* %tmp.225 ; <float> [#uses=1]
+ %tmp.227 = getelementptr { i32, float, float, float, float, float, float, float, float, float, float }* %timing_inf, i64 0, i32 10 ; <float*> [#uses=1]
+ %tmp.228 = load float* %tmp.227 ; <float> [#uses=1]
+ call void @place_and_route( i32 %tmp.135, i32 %tmp.137, float %tmp.139, i32 %tmp.141, i32 %tmp.143, i8* %tmp.145, i32 %tmp.147, i32 %tmp.149, i8* %tmp.107, i8* %tmp.105, i8* %tmp.106, i8* %tmp.108, i32 %tmp.154, i32 %tmp.155, i32 %tmp.157, float %tmp.159, float %tmp.161, float %tmp.163, float %tmp.165, float %tmp.167, float %tmp.169, float %tmp.171, float %tmp.173, float %tmp.175, i32 %tmp.177, i32 %tmp.179, i32 %tmp.181, i32 %tmp.183, i32 %tmp.185, float %tmp.187, float %tmp.189, float %tmp.191, i32 %tmp.193, i32 %tmp.195, i16 %tmp.197, i16 %tmp.199, i16 %tmp.201, float %tmp.203, float %tmp.205, %struct..s_segment_inf* %tmp.206, i32 %tmp.208, float %tmp.210, float %tmp.212, float %tmp.214, float %tmp.216, float %tmp.218, float %tmp.220, float %tmp.222, float %tmp.224, float %tmp.226, float %tmp.228 )
+ %tmp.231 = load i32* %show_graphics ; <i32> [#uses=1]
+ %tmp.232 = icmp ne i32 %tmp.231, 0 ; <i1> [#uses=1]
+ br i1 %tmp.232, label %then.2, label %endif.2
+
+then.2: ; preds = %entry
+ br label %endif.2
+
+endif.2: ; preds = %then.2, %entry
+ ret i32 0
+}
+
+declare i32 @printf(i8*, ...)
+
+declare void @place_and_route(i32, i32, float, i32, i32, i8*, i32, i32, i8*, i8*, i8*, i8*, i32, i32, i32, float, float, float, float, float, float, float, float, float, i32, i32, i32, i32, i32, float, float, float, i32, i32, i16, i16, i16, float, float, %struct..s_segment_inf*, i32, float, float, float, float, float, float, float, float, float, float)
diff --git a/test/CodeGen/Generic/2003-05-30-BadFoldGEP.ll b/test/CodeGen/Generic/2003-05-30-BadFoldGEP.ll
new file mode 100644
index 0000000..10d3a11
--- /dev/null
+++ b/test/CodeGen/Generic/2003-05-30-BadFoldGEP.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s
+
+;; Date: May 28, 2003.
+;; From: test/Programs/External/SPEC/CINT2000/254.gap.llvm.bc
+;; Function: int %OpenOutput(sbyte* %filename.1)
+;;
+;; Error: A sequence of GEPs is folded incorrectly by llc during selection
+;; causing an assertion about a dynamic casting error.
+;; This code sequence was produced (correctly) by preselection
+;; from a nested pair of ConstantExpr getelementptrs.
+;; The code below is the output of preselection.
+;; The original ConstantExprs are included in a comment.
+;;
+;; Cause: FoldGetElemChain() was inserting an extra leading 0 even though
+;; the first instruction in the sequence contributes no indices.
+;; The next instruction contributes a leading non-zero so another
+;; zero should not be added before it!
+;;
+ %FileType = type { i32, [256 x i8], i32, i32, i32, i32 }
+@OutputFiles = external global [16 x %FileType] ; <[16 x %FileType]*> [#uses=1]
+@Output = internal global %FileType* null ; <%FileType**> [#uses=1]
+
+define internal i32 @OpenOutput(i8* %filename.1) {
+entry:
+ %tmp.0 = load %FileType** @Output ; <%FileType*> [#uses=1]
+ %tmp.4 = getelementptr %FileType* %tmp.0, i64 1 ; <%FileType*> [#uses=1]
+ %addrOfGlobal = getelementptr [16 x %FileType]* @OutputFiles, i64 0 ; <[16 x %FileType]*> [#uses=1]
+ %constantGEP = getelementptr [16 x %FileType]* %addrOfGlobal, i64 1 ; <[16 x %FileType]*> [#uses=1]
+ %constantGEP.upgrd.1 = getelementptr [16 x %FileType]* %constantGEP, i64 0, i64 0 ; <%FileType*> [#uses=1]
+ %tmp.10 = icmp eq %FileType* %tmp.4, %constantGEP.upgrd.1 ; <i1> [#uses=1]
+ br i1 %tmp.10, label %return, label %endif.0
+
+endif.0: ; preds = %entry
+ ret i32 0
+
+return: ; preds = %entry
+ ret i32 1
+}
+
diff --git a/test/CodeGen/Generic/2003-05-30-BadPreselectPhi.ll b/test/CodeGen/Generic/2003-05-30-BadPreselectPhi.ll
new file mode 100644
index 0000000..f7c3e42
--- /dev/null
+++ b/test/CodeGen/Generic/2003-05-30-BadPreselectPhi.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s
+
+;; Date: May 28, 2003.
+;; From: test/Programs/SingleSource/richards_benchmark.c
+;; Function: struct task *handlerfn(struct packet *pkt)
+;;
+;; Error: PreSelection puts the arguments of the Phi just before
+;; the Phi instead of in predecessor blocks. This later
+;; causes llc to produces an invalid register <NULL VALUE>
+;; for the phi arguments.
+
+ %struct..packet = type { %struct..packet*, i32, i32, i32, [4 x i8] }
+ %struct..task = type { %struct..task*, i32, i32, %struct..packet*, i32, %struct..task* (%struct..packet*)*, i32, i32 }
+@v1 = external global i32 ; <i32*> [#uses=1]
+@v2 = external global i32 ; <i32*> [#uses=1]
+
+define %struct..task* @handlerfn(%struct..packet* %pkt.2) {
+entry:
+ %tmp.1 = icmp ne %struct..packet* %pkt.2, null ; <i1> [#uses=1]
+ br i1 %tmp.1, label %cond_false, label %cond_continue
+
+cond_false: ; preds = %entry
+ br label %cond_continue
+
+cond_continue: ; preds = %cond_false, %entry
+ %mem_tmp.0 = phi i32* [ @v2, %cond_false ], [ @v1, %entry ] ; <i32*> [#uses=1]
+ %tmp.12 = bitcast i32* %mem_tmp.0 to %struct..packet* ; <%struct..packet*> [#uses=1]
+ call void @append( %struct..packet* %pkt.2, %struct..packet* %tmp.12 )
+ ret %struct..task* null
+}
+
+declare void @append(%struct..packet*, %struct..packet*)
+
diff --git a/test/CodeGen/Generic/2003-07-06-BadIntCmp.ll b/test/CodeGen/Generic/2003-07-06-BadIntCmp.ll
new file mode 100644
index 0000000..1d1aad5
--- /dev/null
+++ b/test/CodeGen/Generic/2003-07-06-BadIntCmp.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s
+
+;; Date: May 28, 2003.
+;; From: test/Programs/MultiSource/Olden-perimeter/maketree.c
+;; Function: int CheckOutside(int x, int y)
+;;
+;; Note: The .ll code below for this regression test has identical
+;; behavior to the above function up to the error, but then prints
+;; true/false on the two branches.
+;;
+;; Error: llc generates a branch-on-xcc instead of branch-on-icc, which
+;; is wrong because the value being compared (int euclid = x*x + y*y)
+;; overflows, so that the 64-bit and 32-bit compares are not equal.
+
[email protected]_1 = internal constant [6 x i8] c"true\0A\00" ; <[6 x i8]*> [#uses=1]
[email protected]_2 = internal constant [7 x i8] c"false\0A\00" ; <[7 x i8]*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define internal void @__main() {
+entry:
+ ret void
+}
+
+define internal void @CheckOutside(i32 %x.1, i32 %y.1) {
+entry:
+ %tmp.2 = mul i32 %x.1, %x.1 ; <i32> [#uses=1]
+ %tmp.5 = mul i32 %y.1, %y.1 ; <i32> [#uses=1]
+ %tmp.6 = add i32 %tmp.2, %tmp.5 ; <i32> [#uses=1]
+ %tmp.8 = icmp sle i32 %tmp.6, 4194304 ; <i1> [#uses=1]
+ br i1 %tmp.8, label %then, label %else
+
+then: ; preds = %entry
+ %tmp.11 = call i32 (i8*, ...)* @printf( i8* getelementptr ([6 x i8]* @.str_1, i64 0, i64 0) ) ; <i32> [#uses=0]
+ br label %UnifiedExitNode
+
+else: ; preds = %entry
+ %tmp.13 = call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8]* @.str_2, i64 0, i64 0) ) ; <i32> [#uses=0]
+ br label %UnifiedExitNode
+
+UnifiedExitNode: ; preds = %else, %then
+ ret void
+}
+
+define i32 @main() {
+entry:
+ call void @__main( )
+ call void @CheckOutside( i32 2097152, i32 2097152 )
+ ret i32 0
+}
+
diff --git a/test/CodeGen/Generic/2003-07-07-BadLongConst.ll b/test/CodeGen/Generic/2003-07-07-BadLongConst.ll
new file mode 100644
index 0000000..64312ba
--- /dev/null
+++ b/test/CodeGen/Generic/2003-07-07-BadLongConst.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s
+
[email protected]_1 = internal constant [42 x i8] c" ui = %u (0x%x)\09\09UL-ui = %lld (0x%llx)\0A\00" ; <[42 x i8]*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define internal i64 @getL() {
+entry:
+ ret i64 -5787213826675591005
+}
+
+define i32 @main(i32 %argc.1, i8** %argv.1) {
+entry:
+ %tmp.11 = call i64 @getL( ) ; <i64> [#uses=2]
+ %tmp.5 = trunc i64 %tmp.11 to i32 ; <i32> [#uses=2]
+ %tmp.23 = and i64 %tmp.11, -4294967296 ; <i64> [#uses=2]
+ %tmp.16 = call i32 (i8*, ...)* @printf( i8* getelementptr ([42 x i8]* @.str_1, i64 0, i64 0), i32 %tmp.5, i32 %tmp.5, i64 %tmp.23, i64 %tmp.23 ) ; <i32> [#uses=0]
+ ret i32 0
+}
+
diff --git a/test/CodeGen/Generic/2003-07-08-BadCastToBool.ll b/test/CodeGen/Generic/2003-07-08-BadCastToBool.ll
new file mode 100644
index 0000000..8019caa
--- /dev/null
+++ b/test/CodeGen/Generic/2003-07-08-BadCastToBool.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s
+
+;; Date: Jul 8, 2003.
+;; From: test/Programs/MultiSource/Olden-perimeter
+;; Function: int %adj(uint %d.1, uint %ct.1)
+;;
+;; Errors: (1) cast-int-to-bool was being treated as a NOP (i.e., the int
+;; register was treated as effectively true if non-zero).
+;; This cannot be used for later boolean operations.
+;; (2) (A or NOT(B)) was being folded into A orn B, which is ok
+;; for bitwise operations but not booleans! For booleans,
+;; the result has to be compared with 0.
+
[email protected]_1 = internal constant [30 x i8] c"d = %d, ct = %d, d ^ ct = %d\0A\00"
+
+declare i32 @printf(i8*, ...)
+
+define i32 @adj(i32 %d.1, i32 %ct.1) {
+entry:
+ %tmp.19 = icmp eq i32 %ct.1, 2 ; <i1> [#uses=1]
+ %tmp.22.not = trunc i32 %ct.1 to i1 ; <i1> [#uses=1]
+ %tmp.221 = xor i1 %tmp.22.not, true ; <i1> [#uses=1]
+ %tmp.26 = or i1 %tmp.19, %tmp.221 ; <i1> [#uses=1]
+ %tmp.27 = zext i1 %tmp.26 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp.27
+}
+
+define i32 @main() {
+entry:
+ %result = call i32 @adj( i32 3, i32 2 ) ; <i32> [#uses=1]
+ %tmp.0 = call i32 (i8*, ...)* @printf( i8* getelementptr ([30 x i8]* @.str_1, i64 0, i64 0), i32 3, i32 2, i32 %result ) ; <i32> [#uses=0]
+ ret i32 0
+}
+
diff --git a/test/CodeGen/Generic/2003-07-29-BadConstSbyte.ll b/test/CodeGen/Generic/2003-07-29-BadConstSbyte.ll
new file mode 100644
index 0000000..4e6fe1cf
--- /dev/null
+++ b/test/CodeGen/Generic/2003-07-29-BadConstSbyte.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s
+
+;; Date: Jul 29, 2003.
+;; From: test/Programs/MultiSource/Ptrdist-bc
+;; Function: ---
+;; Global: %yy_ec = internal constant [256 x sbyte] ...
+;; A subset of this array is used in the test below.
+;;
+;; Error: Character '\07' was being emitted as '\a', at yy_ec[38].
+;; When loaded, this returned the value 97 ('a'), instead of 7.
+;;
+;; Incorrect LLC Output for the array yy_ec was:
+;; yy_ec_1094:
+;; .ascii "\000\001\001\001\001\001\001\001\001\002\003\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\002\004\005\001\001\006\a\001\b\t\n\v\f\r\016\017\020\020\020\020\020\020\020\020\020\020\001\021\022\023\024\001\001\025\025\025\025\025\025\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\026\027\030\031\032\001\033\034\035\036\037 !\"#$%&'()*+,-./$0$1$234\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001\001"
+;;
+
+@yy_ec = internal constant [6 x i8] c"\06\07\01\08\01\09" ; <[6 x i8]*> [#uses=1]
[email protected]_3 = internal constant [8 x i8] c"[%d] = \00" ; <[8 x i8]*> [#uses=1]
[email protected]_4 = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+entry:
+ br label %loopentry
+
+loopentry: ; preds = %loopentry, %entry
+ %i = phi i64 [ 0, %entry ], [ %inc.i, %loopentry ] ; <i64> [#uses=3]
+ %cptr = getelementptr [6 x i8]* @yy_ec, i64 0, i64 %i ; <i8*> [#uses=1]
+ %c = load i8* %cptr ; <i8> [#uses=1]
+ %ignore = call i32 (i8*, ...)* @printf( i8* getelementptr ([8 x i8]* @.str_3, i64 0, i64 0), i64 %i ) ; <i32> [#uses=0]
+ %ignore2 = call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @.str_4, i64 0, i64 0), i8 %c ) ; <i32> [#uses=0]
+ %inc.i = add i64 %i, 1 ; <i64> [#uses=2]
+ %done = icmp sle i64 %inc.i, 5 ; <i1> [#uses=1]
+ br i1 %done, label %loopentry, label %exit.1
+
+exit.1: ; preds = %loopentry
+ ret i32 0
+}
+
diff --git a/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll b/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll
new file mode 100644
index 0000000..393062a
--- /dev/null
+++ b/test/CodeGen/Generic/2004-02-08-UnwindSupport.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -enable-correct-eh-support
+
+define i32 @test() {
+ unwind
+}
+
+define i32 @main() {
+ %X = invoke i32 @test( )
+ to label %cont unwind label %EH ; <i32> [#uses=0]
+
+cont: ; preds = %0
+ ret i32 1
+
+EH: ; preds = %0
+ ret i32 0
+}
+
diff --git a/test/CodeGen/Generic/2004-05-09-LiveVarPartialRegister.ll b/test/CodeGen/Generic/2004-05-09-LiveVarPartialRegister.ll
new file mode 100644
index 0000000..d4a4cf8
--- /dev/null
+++ b/test/CodeGen/Generic/2004-05-09-LiveVarPartialRegister.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s
+@global_long_1 = linkonce global i64 7 ; <i64*> [#uses=1]
+@global_long_2 = linkonce global i64 49 ; <i64*> [#uses=1]
+
+define i32 @main() {
+ %l1 = load i64* @global_long_1 ; <i64> [#uses=1]
+ %l2 = load i64* @global_long_2 ; <i64> [#uses=1]
+ %cond = icmp sle i64 %l1, %l2 ; <i1> [#uses=1]
+ %cast2 = zext i1 %cond to i32 ; <i32> [#uses=1]
+ %RV = sub i32 1, %cast2 ; <i32> [#uses=1]
+ ret i32 %RV
+}
+
diff --git a/test/CodeGen/Generic/2005-01-18-SetUO-InfLoop.ll b/test/CodeGen/Generic/2005-01-18-SetUO-InfLoop.ll
new file mode 100644
index 0000000..7fd2361
--- /dev/null
+++ b/test/CodeGen/Generic/2005-01-18-SetUO-InfLoop.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s
+
+define void @intersect_pixel() {
+entry:
+ %tmp125 = fcmp uno double 0.000000e+00, 0.000000e+00 ; <i1> [#uses=1]
+ %tmp126 = or i1 %tmp125, false ; <i1> [#uses=1]
+ %tmp126.not = xor i1 %tmp126, true ; <i1> [#uses=1]
+ %brmerge1 = or i1 %tmp126.not, false ; <i1> [#uses=1]
+ br i1 %brmerge1, label %bb154, label %cond_false133
+
+cond_false133: ; preds = %entry
+ ret void
+
+bb154: ; preds = %entry
+ %tmp164 = icmp eq i32 0, 0 ; <i1> [#uses=0]
+ ret void
+}
+
+declare i1 @llvm.isunordered.f64(double, double)
+
diff --git a/test/CodeGen/Generic/2005-04-09-GlobalInPHI.ll b/test/CodeGen/Generic/2005-04-09-GlobalInPHI.ll
new file mode 100644
index 0000000..353e411
--- /dev/null
+++ b/test/CodeGen/Generic/2005-04-09-GlobalInPHI.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s
+ %struct.TypHeader = type { i32, %struct.TypHeader**, [3 x i8], i8 }
[email protected]_67 = external global [4 x i8] ; <[4 x i8]*> [#uses=1]
[email protected]_87 = external global [17 x i8] ; <[17 x i8]*> [#uses=1]
+
+define void @PrBinop() {
+entry:
+ br i1 false, label %cond_true, label %else.0
+
+cond_true: ; preds = %entry
+ br label %else.0
+
+else.0: ; preds = %cond_true, %entry
+ %tmp.167.1 = phi i32 [ ptrtoint ([17 x i8]* @.str_87 to i32), %entry ], [ 0, %cond_true ] ; <i32> [#uses=0]
+ call void @Pr( i8* getelementptr ([4 x i8]* @.str_67, i32 0, i32 0), i32 0, i32 0 )
+ ret void
+}
+
+declare void @Pr(i8*, i32, i32)
+
diff --git a/test/CodeGen/Generic/2005-07-12-memcpy-i64-length.ll b/test/CodeGen/Generic/2005-07-12-memcpy-i64-length.ll
new file mode 100644
index 0000000..733202c
--- /dev/null
+++ b/test/CodeGen/Generic/2005-07-12-memcpy-i64-length.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+; Test that llvm.memcpy works with a i64 length operand on all targets.
+
+declare void @llvm.memcpy.i64(i8*, i8*, i64, i32)
+
+define void @l12_l94_bc_divide_endif_2E_3_2E_ce() {
+newFuncRoot:
+ tail call void @llvm.memcpy.i64( i8* null, i8* null, i64 0, i32 1 )
+ unreachable
+}
+
diff --git a/test/CodeGen/Generic/2005-10-18-ZeroSizeStackObject.ll b/test/CodeGen/Generic/2005-10-18-ZeroSizeStackObject.ll
new file mode 100644
index 0000000..08060bf
--- /dev/null
+++ b/test/CodeGen/Generic/2005-10-18-ZeroSizeStackObject.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s
+
+define void @test() {
+ %X = alloca { } ; <{ }*> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/Generic/2005-10-21-longlonggtu.ll b/test/CodeGen/Generic/2005-10-21-longlonggtu.ll
new file mode 100644
index 0000000..53a9cd0f
--- /dev/null
+++ b/test/CodeGen/Generic/2005-10-21-longlonggtu.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s
+
+define float @t(i64 %u_arg) {
+ %u = bitcast i64 %u_arg to i64 ; <i64> [#uses=1]
+ %tmp5 = add i64 %u, 9007199254740991 ; <i64> [#uses=1]
+ %tmp = icmp ugt i64 %tmp5, 18014398509481982 ; <i1> [#uses=1]
+ br i1 %tmp, label %T, label %F
+
+T: ; preds = %0
+ ret float 1.000000e+00
+
+F: ; preds = %0
+ call float @t( i64 0 ) ; <float>:1 [#uses=0]
+ ret float 0.000000e+00
+}
+
diff --git a/test/CodeGen/Generic/2005-12-01-Crash.ll b/test/CodeGen/Generic/2005-12-01-Crash.ll
new file mode 100644
index 0000000..a9eedde
--- /dev/null
+++ b/test/CodeGen/Generic/2005-12-01-Crash.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s
+@str = external global [36 x i8] ; <[36 x i8]*> [#uses=0]
[email protected] = external global [29 x i8] ; <[29 x i8]*> [#uses=0]
+@str1 = external global [29 x i8] ; <[29 x i8]*> [#uses=0]
+@str2 = external global [29 x i8] ; <[29 x i8]*> [#uses=1]
[email protected] = external global [2 x i8] ; <[2 x i8]*> [#uses=0]
+@str3 = external global [2 x i8] ; <[2 x i8]*> [#uses=0]
+@str4 = external global [2 x i8] ; <[2 x i8]*> [#uses=0]
+@str5 = external global [2 x i8] ; <[2 x i8]*> [#uses=0]
+
+define void @printArgsNoRet(i32 %a1, float %a2, i8 %a3, double %a4, i8* %a5, i32 %a6, float %a7, i8 %a8, double %a9, i8* %a10, i32 %a11, float %a12, i8 %a13, double %a14, i8* %a15) {
+entry:
+ %tmp17 = sext i8 %a13 to i32 ; <i32> [#uses=1]
+ %tmp23 = call i32 (i8*, ...)* @printf( i8* getelementptr ([29 x i8]* @str2, i32 0, i64 0), i32 %a11, double 0.000000e+00, i32 %tmp17, double %a14, i32 0 ) ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @printf(i8*, ...)
+
+declare i32 @main(i32, i8**)
diff --git a/test/CodeGen/Generic/2005-12-12-ExpandSextInreg.ll b/test/CodeGen/Generic/2005-12-12-ExpandSextInreg.ll
new file mode 100644
index 0000000..349540f
--- /dev/null
+++ b/test/CodeGen/Generic/2005-12-12-ExpandSextInreg.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s
+
+define i64 @test(i64 %A) {
+ %B = trunc i64 %A to i8 ; <i8> [#uses=1]
+ %C = sext i8 %B to i64 ; <i64> [#uses=1]
+ ret i64 %C
+}
diff --git a/test/CodeGen/Generic/2006-01-12-BadSetCCFold.ll b/test/CodeGen/Generic/2006-01-12-BadSetCCFold.ll
new file mode 100644
index 0000000..42e8ed0
--- /dev/null
+++ b/test/CodeGen/Generic/2006-01-12-BadSetCCFold.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s
+; ModuleID = '2006-01-12-BadSetCCFold.ll'
+ %struct.node_t = type { double*, %struct.node_t*, %struct.node_t**, double**, double*, i32, i32 }
+
+define void @main() {
+entry:
+ br i1 false, label %then.2.i, label %endif.2.i
+
+then.2.i: ; preds = %entry
+ br label %dealwithargs.exit
+
+endif.2.i: ; preds = %entry
+ br i1 false, label %then.3.i, label %dealwithargs.exit
+
+then.3.i: ; preds = %endif.2.i
+ br label %dealwithargs.exit
+
+dealwithargs.exit: ; preds = %then.3.i, %endif.2.i, %then.2.i
+ %n_nodes.4 = phi i32 [ 64, %then.3.i ], [ 64, %then.2.i ], [ 64, %endif.2.i ] ; <i32> [#uses=1]
+ %tmp.14.i1134.i.i = icmp sgt i32 %n_nodes.4, 1 ; <i1> [#uses=2]
+ br i1 %tmp.14.i1134.i.i, label %no_exit.i12.i.i, label %fill_table.exit22.i.i
+
+no_exit.i12.i.i: ; preds = %no_exit.i12.i.i, %dealwithargs.exit
+ br i1 false, label %fill_table.exit22.i.i, label %no_exit.i12.i.i
+
+fill_table.exit22.i.i: ; preds = %no_exit.i12.i.i, %dealwithargs.exit
+ %cur_node.0.i8.1.i.i = phi %struct.node_t* [ undef, %dealwithargs.exit ], [ null, %no_exit.i12.i.i ] ; <%struct.node_t*> [#uses=0]
+ br i1 %tmp.14.i1134.i.i, label %no_exit.i.preheader.i.i, label %make_tables.exit.i
+
+no_exit.i.preheader.i.i: ; preds = %fill_table.exit22.i.i
+ ret void
+
+make_tables.exit.i: ; preds = %fill_table.exit22.i.i
+ ret void
+}
diff --git a/test/CodeGen/Generic/2006-01-18-InvalidBranchOpcodeAssert.ll b/test/CodeGen/Generic/2006-01-18-InvalidBranchOpcodeAssert.ll
new file mode 100644
index 0000000..f06d341
--- /dev/null
+++ b/test/CodeGen/Generic/2006-01-18-InvalidBranchOpcodeAssert.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s
+; This crashed the PPC backend.
+
+define void @test() {
+ %tmp125 = fcmp uno double 0.000000e+00, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %tmp125, label %bb154, label %cond_false133
+
+cond_false133: ; preds = %0
+ ret void
+
+bb154: ; preds = %0
+ %tmp164 = icmp eq i32 0, 0 ; <i1> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/Generic/2006-02-12-InsertLibcall.ll b/test/CodeGen/Generic/2006-02-12-InsertLibcall.ll
new file mode 100644
index 0000000..5508272
--- /dev/null
+++ b/test/CodeGen/Generic/2006-02-12-InsertLibcall.ll
@@ -0,0 +1,60 @@
+; RUN: llc < %s
+@G = external global i32 ; <i32*> [#uses=1]
+
+define void @encode_one_frame(i64 %tmp.2i) {
+entry:
+ %tmp.9 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp.9, label %endif.0, label %shortcirc_next.0
+
+then.5.i: ; preds = %shortcirc_next.i
+ %tmp.114.i = sdiv i64 %tmp.2i, 3 ; <i64> [#uses=1]
+ %tmp.111.i = call i64 @lseek( i32 0, i64 %tmp.114.i, i32 1 ) ; <i64> [#uses=0]
+ ret void
+
+shortcirc_next.0: ; preds = %entry
+ ret void
+
+endif.0: ; preds = %entry
+ %tmp.324.i = icmp eq i32 0, 0 ; <i1> [#uses=2]
+ %tmp.362.i = icmp slt i32 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp.324.i, label %else.4.i, label %then.11.i37
+
+then.11.i37: ; preds = %endif.0
+ ret void
+
+else.4.i: ; preds = %endif.0
+ br i1 %tmp.362.i, label %else.5.i, label %then.12.i
+
+then.12.i: ; preds = %else.4.i
+ ret void
+
+else.5.i: ; preds = %else.4.i
+ br i1 %tmp.324.i, label %then.0.i40, label %then.17.i
+
+then.17.i: ; preds = %else.5.i
+ ret void
+
+then.0.i40: ; preds = %else.5.i
+ %tmp.8.i42 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp.8.i42, label %else.1.i56, label %then.1.i52
+
+then.1.i52: ; preds = %then.0.i40
+ ret void
+
+else.1.i56: ; preds = %then.0.i40
+ %tmp.28.i = load i32* @G ; <i32> [#uses=1]
+ %tmp.29.i = icmp eq i32 %tmp.28.i, 1 ; <i1> [#uses=1]
+ br i1 %tmp.29.i, label %shortcirc_next.i, label %shortcirc_done.i
+
+shortcirc_next.i: ; preds = %else.1.i56
+ %tmp.34.i = icmp eq i32 0, 3 ; <i1> [#uses=1]
+ br i1 %tmp.34.i, label %then.5.i, label %endif.5.i
+
+shortcirc_done.i: ; preds = %else.1.i56
+ ret void
+
+endif.5.i: ; preds = %shortcirc_next.i
+ ret void
+}
+
+declare i64 @lseek(i32, i64, i32)
diff --git a/test/CodeGen/Generic/2006-03-01-dagcombineinfloop.ll b/test/CodeGen/Generic/2006-03-01-dagcombineinfloop.ll
new file mode 100644
index 0000000..2a6cc0c
--- /dev/null
+++ b/test/CodeGen/Generic/2006-03-01-dagcombineinfloop.ll
@@ -0,0 +1,95 @@
+; RUN: llc < %s
+; Infinite loop in the dag combiner, reduced from 176.gcc.
+%struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
+ %struct.anon = type { i32 }
+ %struct.lang_decl = type opaque
+ %struct.lang_type = type { i32, [1 x %struct.tree_node*] }
+ %struct.obstack = type { i32, %struct._obstack_chunk*, i8*, i8*, i8*, i32, i32, %struct._obstack_chunk* (...)*, void (...)*, i8*, i8 }
+ %struct.rtx_def = type { i16, i8, i8, [1 x %struct.anon] }
+ %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, i8, i8, i8, i8 }
+ %struct.tree_decl = type { [12 x i8], i8*, i32, %struct.tree_node*, i32, i8, i8, i8, i8, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.anon, { %struct.rtx_def* }, %struct.tree_node*, %struct.lang_decl* }
+ %struct.tree_list = type { [12 x i8], %struct.tree_node*, %struct.tree_node* }
+ %struct.tree_node = type { %struct.tree_decl }
+ %struct.tree_type = type { [12 x i8], %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i32, i8, i8, i8, i8, i32, %struct.tree_node*, %struct.tree_node*, %struct.anon, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.obstack*, %struct.lang_type* }
+@void_type_node = external global %struct.tree_node* ; <%struct.tree_node**> [#uses=1]
+@char_type_node = external global %struct.tree_node* ; <%struct.tree_node**> [#uses=1]
+@short_integer_type_node = external global %struct.tree_node* ; <%struct.tree_node**> [#uses=1]
+@short_unsigned_type_node = external global %struct.tree_node* ; <%struct.tree_node**> [#uses=1]
+@float_type_node = external global %struct.tree_node* ; <%struct.tree_node**> [#uses=1]
+@signed_char_type_node = external global %struct.tree_node* ; <%struct.tree_node**> [#uses=1]
+@unsigned_char_type_node = external global %struct.tree_node* ; <%struct.tree_node**> [#uses=1]
+
+define fastcc i32 @self_promoting_args_p(%struct.tree_node* %parms) {
+entry:
+ %tmp915 = icmp eq %struct.tree_node* %parms, null ; <i1> [#uses=1]
+ br i1 %tmp915, label %return, label %cond_true92.preheader
+
+cond_true: ; preds = %cond_true92
+ %tmp9.not = icmp ne %struct.tree_node* %tmp2, %tmp7 ; <i1> [#uses=1]
+ %tmp14 = icmp eq %struct.tree_node* %tmp2, null ; <i1> [#uses=1]
+ %bothcond = or i1 %tmp9.not, %tmp14 ; <i1> [#uses=1]
+ br i1 %bothcond, label %return, label %cond_next18
+
+cond_next12: ; preds = %cond_true92
+ %tmp14.old = icmp eq %struct.tree_node* %tmp2, null ; <i1> [#uses=1]
+ br i1 %tmp14.old, label %return, label %cond_next18
+
+cond_next18: ; preds = %cond_next12, %cond_true
+ %tmp20 = bitcast %struct.tree_node* %tmp2 to %struct.tree_type* ; <%struct.tree_type*> [#uses=1]
+ %tmp21 = getelementptr %struct.tree_type* %tmp20, i32 0, i32 17 ; <%struct.tree_node**> [#uses=1]
+ %tmp22 = load %struct.tree_node** %tmp21 ; <%struct.tree_node*> [#uses=6]
+ %tmp24 = icmp eq %struct.tree_node* %tmp22, %tmp23 ; <i1> [#uses=1]
+ br i1 %tmp24, label %return, label %cond_next28
+
+cond_next28: ; preds = %cond_next18
+ %tmp30 = bitcast %struct.tree_node* %tmp2 to %struct.tree_common* ; <%struct.tree_common*> [#uses=1]
+ %tmp = getelementptr %struct.tree_common* %tmp30, i32 0, i32 2 ; <i8*> [#uses=1]
+ %tmp.upgrd.1 = bitcast i8* %tmp to i32* ; <i32*> [#uses=1]
+ %tmp.upgrd.2 = load i32* %tmp.upgrd.1 ; <i32> [#uses=1]
+ %tmp32 = trunc i32 %tmp.upgrd.2 to i8 ; <i8> [#uses=1]
+ %tmp33 = icmp eq i8 %tmp32, 7 ; <i1> [#uses=1]
+ br i1 %tmp33, label %cond_true34, label %cond_next84
+
+cond_true34: ; preds = %cond_next28
+ %tmp40 = icmp eq %struct.tree_node* %tmp22, %tmp39 ; <i1> [#uses=1]
+ %tmp49 = icmp eq %struct.tree_node* %tmp22, %tmp48 ; <i1> [#uses=1]
+ %bothcond6 = or i1 %tmp40, %tmp49 ; <i1> [#uses=1]
+ %tmp58 = icmp eq %struct.tree_node* %tmp22, %tmp57 ; <i1> [#uses=1]
+ %bothcond7 = or i1 %bothcond6, %tmp58 ; <i1> [#uses=1]
+ %tmp67 = icmp eq %struct.tree_node* %tmp22, %tmp66 ; <i1> [#uses=1]
+ %bothcond8 = or i1 %bothcond7, %tmp67 ; <i1> [#uses=1]
+ %tmp76 = icmp eq %struct.tree_node* %tmp22, %tmp75 ; <i1> [#uses=1]
+ %bothcond9 = or i1 %bothcond8, %tmp76 ; <i1> [#uses=2]
+ %brmerge = or i1 %bothcond9, %tmp.upgrd.6 ; <i1> [#uses=1]
+ %bothcond9.upgrd.3 = zext i1 %bothcond9 to i32 ; <i32> [#uses=1]
+ %.mux = xor i32 %bothcond9.upgrd.3, 1 ; <i32> [#uses=1]
+ br i1 %brmerge, label %return, label %cond_true92
+
+cond_next84: ; preds = %cond_next28
+ br i1 %tmp.upgrd.6, label %return, label %cond_true92
+
+cond_true92.preheader: ; preds = %entry
+ %tmp7 = load %struct.tree_node** @void_type_node ; <%struct.tree_node*> [#uses=1]
+ %tmp23 = load %struct.tree_node** @float_type_node ; <%struct.tree_node*> [#uses=1]
+ %tmp39 = load %struct.tree_node** @char_type_node ; <%struct.tree_node*> [#uses=1]
+ %tmp48 = load %struct.tree_node** @signed_char_type_node ; <%struct.tree_node*> [#uses=1]
+ %tmp57 = load %struct.tree_node** @unsigned_char_type_node ; <%struct.tree_node*> [#uses=1]
+ %tmp66 = load %struct.tree_node** @short_integer_type_node ; <%struct.tree_node*> [#uses=1]
+ %tmp75 = load %struct.tree_node** @short_unsigned_type_node ; <%struct.tree_node*> [#uses=1]
+ br label %cond_true92
+
+cond_true92: ; preds = %cond_true92.preheader, %cond_next84, %cond_true34
+ %t.0.0 = phi %struct.tree_node* [ %parms, %cond_true92.preheader ], [ %tmp6, %cond_true34 ], [ %tmp6, %cond_next84 ] ; <%struct.tree_node*> [#uses=2]
+ %tmp.upgrd.4 = bitcast %struct.tree_node* %t.0.0 to %struct.tree_list* ; <%struct.tree_list*> [#uses=1]
+ %tmp.upgrd.5 = getelementptr %struct.tree_list* %tmp.upgrd.4, i32 0, i32 2 ; <%struct.tree_node**> [#uses=1]
+ %tmp2 = load %struct.tree_node** %tmp.upgrd.5 ; <%struct.tree_node*> [#uses=5]
+ %tmp4 = bitcast %struct.tree_node* %t.0.0 to %struct.tree_common* ; <%struct.tree_common*> [#uses=1]
+ %tmp5 = getelementptr %struct.tree_common* %tmp4, i32 0, i32 0 ; <%struct.tree_node**> [#uses=1]
+ %tmp6 = load %struct.tree_node** %tmp5 ; <%struct.tree_node*> [#uses=3]
+ %tmp.upgrd.6 = icmp eq %struct.tree_node* %tmp6, null ; <i1> [#uses=3]
+ br i1 %tmp.upgrd.6, label %cond_true, label %cond_next12
+
+return: ; preds = %cond_next84, %cond_true34, %cond_next18, %cond_next12, %cond_true, %entry
+ %retval.0 = phi i32 [ 1, %entry ], [ 1, %cond_next84 ], [ %.mux, %cond_true34 ], [ 0, %cond_next18 ], [ 0, %cond_next12 ], [ 0, %cond_true ] ; <i32> [#uses=1]
+ ret i32 %retval.0
+}
diff --git a/test/CodeGen/Generic/2006-04-26-SetCCAnd.ll b/test/CodeGen/Generic/2006-04-26-SetCCAnd.ll
new file mode 100644
index 0000000..8465b82
--- /dev/null
+++ b/test/CodeGen/Generic/2006-04-26-SetCCAnd.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s
+; PR748
+@G = external global i16 ; <i16*> [#uses=1]
+
+define void @OmNewObjHdr() {
+entry:
+ br i1 false, label %endif.4, label %then.0
+
+then.0: ; preds = %entry
+ ret void
+
+endif.4: ; preds = %entry
+ br i1 false, label %else.3, label %shortcirc_next.3
+
+shortcirc_next.3: ; preds = %endif.4
+ ret void
+
+else.3: ; preds = %endif.4
+ switch i32 0, label %endif.10 [
+ i32 5001, label %then.10
+ i32 -5008, label %then.10
+ ]
+
+then.10: ; preds = %else.3, %else.3
+ %tmp.112 = load i16* null ; <i16> [#uses=2]
+ %tmp.113 = load i16* @G ; <i16> [#uses=2]
+ %tmp.114 = icmp ugt i16 %tmp.112, %tmp.113 ; <i1> [#uses=1]
+ %tmp.120 = icmp ult i16 %tmp.112, %tmp.113 ; <i1> [#uses=1]
+ %bothcond = and i1 %tmp.114, %tmp.120 ; <i1> [#uses=1]
+ br i1 %bothcond, label %else.4, label %then.11
+
+then.11: ; preds = %then.10
+ ret void
+
+else.4: ; preds = %then.10
+ ret void
+
+endif.10: ; preds = %else.3
+ ret void
+}
diff --git a/test/CodeGen/Generic/2006-04-28-Sign-extend-bool.ll b/test/CodeGen/Generic/2006-04-28-Sign-extend-bool.ll
new file mode 100644
index 0000000..22d8f99
--- /dev/null
+++ b/test/CodeGen/Generic/2006-04-28-Sign-extend-bool.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s
+
+define i32 @test(i32 %tmp93) {
+ %tmp98 = shl i32 %tmp93, 31 ; <i32> [#uses=1]
+ %tmp99 = ashr i32 %tmp98, 31 ; <i32> [#uses=1]
+ %tmp99.upgrd.1 = trunc i32 %tmp99 to i8 ; <i8> [#uses=1]
+ %tmp99100 = sext i8 %tmp99.upgrd.1 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp99100
+}
diff --git a/test/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll b/test/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
new file mode 100644
index 0000000..1a9fa9f
--- /dev/null
+++ b/test/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s
+%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.SYMBOL_TABLE_ENTRY = type { [9 x i8], [9 x i8], i32, i32, i32, %struct.SYMBOL_TABLE_ENTRY* }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+@str14 = external global [6 x i8] ; <[6 x i8]*> [#uses=0]
+
+declare void @fprintf(i32, ...)
+
+define void @OUTPUT_TABLE(%struct.SYMBOL_TABLE_ENTRY* %SYM_TAB) {
+entry:
+ %tmp11 = getelementptr %struct.SYMBOL_TABLE_ENTRY* %SYM_TAB, i32 0, i32 1, i32 0 ; <i8*> [#uses=2]
+ %tmp.i = bitcast i8* %tmp11 to i8* ; <i8*> [#uses=1]
+ br label %bb.i
+
+bb.i: ; preds = %cond_next.i, %entry
+ %s1.0.i = phi i8* [ %tmp.i, %entry ], [ null, %cond_next.i ] ; <i8*> [#uses=0]
+ br i1 false, label %cond_true.i31, label %cond_next.i
+
+cond_true.i31: ; preds = %bb.i
+ call void (i32, ...)* @fprintf( i32 0, i8* %tmp11, i8* null )
+ ret void
+
+cond_next.i: ; preds = %bb.i
+ br i1 false, label %bb.i, label %bb19.i
+
+bb19.i: ; preds = %cond_next.i
+ ret void
+}
diff --git a/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll b/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
new file mode 100644
index 0000000..a3720a9
--- /dev/null
+++ b/test/CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -O0
+
+define float @test(i32 %tmp12771278) {
+ switch i32 %tmp12771278, label %bb1279 [
+ ]
+
+bb1279: ; preds = %0
+ ret float 1.000000e+00
+}
+
diff --git a/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll b/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll
new file mode 100644
index 0000000..bd922b3
--- /dev/null
+++ b/test/CodeGen/Generic/2006-06-13-ComputeMaskedBitsCrash.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -O0
+
+%struct.cl_perfunc_opts = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32 }
+@cl_pf_opts = external global %struct.cl_perfunc_opts ; <%struct.cl_perfunc_opts*> [#uses=2]
+
+define void @set_flags_from_O() {
+entry:
+ %tmp22 = icmp sgt i32 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp22, label %cond_true23, label %cond_next159
+
+cond_true23: ; preds = %entry
+ %tmp138 = getelementptr %struct.cl_perfunc_opts* @cl_pf_opts, i32 0, i32 8 ; <i8*> [#uses=1]
+ %tmp138.upgrd.1 = bitcast i8* %tmp138 to i32* ; <i32*> [#uses=2]
+ %tmp139 = load i32* %tmp138.upgrd.1 ; <i32> [#uses=1]
+ %tmp140 = shl i32 1, 27 ; <i32> [#uses=1]
+ %tmp141 = and i32 %tmp140, 134217728 ; <i32> [#uses=1]
+ %tmp142 = and i32 %tmp139, -134217729 ; <i32> [#uses=1]
+ %tmp143 = or i32 %tmp142, %tmp141 ; <i32> [#uses=1]
+ store i32 %tmp143, i32* %tmp138.upgrd.1
+ %tmp144 = getelementptr %struct.cl_perfunc_opts* @cl_pf_opts, i32 0, i32 8 ; <i8*> [#uses=1]
+ %tmp144.upgrd.2 = bitcast i8* %tmp144 to i32* ; <i32*> [#uses=1]
+ %tmp145 = load i32* %tmp144.upgrd.2 ; <i32> [#uses=1]
+ %tmp146 = shl i32 %tmp145, 22 ; <i32> [#uses=1]
+ %tmp147 = lshr i32 %tmp146, 31 ; <i32> [#uses=1]
+ %tmp147.upgrd.3 = trunc i32 %tmp147 to i8 ; <i8> [#uses=1]
+ %tmp148 = icmp eq i8 %tmp147.upgrd.3, 0 ; <i1> [#uses=1]
+ br i1 %tmp148, label %cond_true149, label %cond_next159
+
+cond_true149: ; preds = %cond_true23
+ %tmp150 = bitcast i8* null to i32* ; <i32*> [#uses=0]
+ ret void
+
+cond_next159: ; preds = %cond_true23, %entry
+ ret void
+}
diff --git a/test/CodeGen/Generic/2006-06-28-SimplifySetCCCrash.ll b/test/CodeGen/Generic/2006-06-28-SimplifySetCCCrash.ll
new file mode 100644
index 0000000..c4f2fb0
--- /dev/null
+++ b/test/CodeGen/Generic/2006-06-28-SimplifySetCCCrash.ll
@@ -0,0 +1,279 @@
+; RUN: llc < %s
+%struct.rtunion = type { i64 }
+ %struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] }
+@ix86_cpu = external global i32 ; <i32*> [#uses=1]
+@which_alternative = external global i32 ; <i32*> [#uses=3]
+
+declare fastcc i32 @recog()
+
+define void @athlon_fp_unit_ready_cost() {
+entry:
+ %tmp = icmp slt i32 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp, label %cond_true.i, label %cond_true
+
+cond_true: ; preds = %entry
+ ret void
+
+cond_true.i: ; preds = %entry
+ %tmp8.i = tail call fastcc i32 @recog( ) ; <i32> [#uses=1]
+ switch i32 %tmp8.i, label %UnifiedReturnBlock [
+ i32 -1, label %bb2063
+ i32 19, label %bb2035
+ i32 20, label %bb2035
+ i32 21, label %bb2035
+ i32 23, label %bb2035
+ i32 24, label %bb2035
+ i32 27, label %bb2035
+ i32 32, label %bb2035
+ i32 33, label %bb1994
+ i32 35, label %bb2035
+ i32 36, label %bb1994
+ i32 90, label %bb1948
+ i32 94, label %bb1948
+ i32 95, label %bb1948
+ i32 101, label %bb1648
+ i32 102, label %bb1648
+ i32 103, label %bb1648
+ i32 104, label %bb1648
+ i32 133, label %bb1419
+ i32 135, label %bb1238
+ i32 136, label %bb1238
+ i32 137, label %bb1238
+ i32 138, label %bb1238
+ i32 139, label %bb1201
+ i32 140, label %bb1201
+ i32 141, label %bb1154
+ i32 142, label %bb1126
+ i32 144, label %bb1201
+ i32 145, label %bb1126
+ i32 146, label %bb1201
+ i32 147, label %bb1126
+ i32 148, label %bb1201
+ i32 149, label %bb1126
+ i32 150, label %bb1201
+ i32 151, label %bb1126
+ i32 152, label %bb1096
+ i32 153, label %bb1096
+ i32 154, label %bb1096
+ i32 157, label %bb1096
+ i32 158, label %bb1096
+ i32 159, label %bb1096
+ i32 162, label %bb1096
+ i32 163, label %bb1096
+ i32 164, label %bb1096
+ i32 167, label %bb1201
+ i32 168, label %bb1201
+ i32 170, label %bb1201
+ i32 171, label %bb1201
+ i32 173, label %bb1201
+ i32 174, label %bb1201
+ i32 176, label %bb1201
+ i32 177, label %bb1201
+ i32 179, label %bb993
+ i32 180, label %bb993
+ i32 181, label %bb993
+ i32 182, label %bb993
+ i32 183, label %bb993
+ i32 184, label %bb993
+ i32 365, label %bb1126
+ i32 366, label %bb1126
+ i32 367, label %bb1126
+ i32 368, label %bb1126
+ i32 369, label %bb1126
+ i32 370, label %bb1126
+ i32 371, label %bb1126
+ i32 372, label %bb1126
+ i32 373, label %bb1126
+ i32 384, label %bb1126
+ i32 385, label %bb1126
+ i32 386, label %bb1126
+ i32 387, label %bb1126
+ i32 388, label %bb1126
+ i32 389, label %bb1126
+ i32 390, label %bb1126
+ i32 391, label %bb1126
+ i32 392, label %bb1126
+ i32 525, label %bb919
+ i32 526, label %bb839
+ i32 528, label %bb919
+ i32 529, label %bb839
+ i32 531, label %cond_next6.i119
+ i32 532, label %cond_next6.i97
+ i32 533, label %cond_next6.i81
+ i32 534, label %bb495
+ i32 536, label %cond_next6.i81
+ i32 537, label %cond_next6.i81
+ i32 538, label %bb396
+ i32 539, label %bb288
+ i32 541, label %bb396
+ i32 542, label %bb396
+ i32 543, label %bb396
+ i32 544, label %bb396
+ i32 545, label %bb189
+ i32 546, label %cond_next6.i
+ i32 547, label %bb189
+ i32 548, label %cond_next6.i
+ i32 549, label %bb189
+ i32 550, label %cond_next6.i
+ i32 551, label %bb189
+ i32 552, label %cond_next6.i
+ i32 553, label %bb189
+ i32 554, label %cond_next6.i
+ i32 555, label %bb189
+ i32 556, label %cond_next6.i
+ i32 557, label %bb189
+ i32 558, label %cond_next6.i
+ i32 618, label %bb40
+ i32 619, label %bb18
+ i32 620, label %bb40
+ i32 621, label %bb10
+ i32 622, label %bb10
+ ]
+
+bb10: ; preds = %cond_true.i, %cond_true.i
+ ret void
+
+bb18: ; preds = %cond_true.i
+ ret void
+
+bb40: ; preds = %cond_true.i, %cond_true.i
+ ret void
+
+cond_next6.i: ; preds = %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i
+ ret void
+
+bb189: ; preds = %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i
+ ret void
+
+bb288: ; preds = %cond_true.i
+ ret void
+
+bb396: ; preds = %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i
+ ret void
+
+bb495: ; preds = %cond_true.i
+ ret void
+
+cond_next6.i81: ; preds = %cond_true.i, %cond_true.i, %cond_true.i
+ ret void
+
+cond_next6.i97: ; preds = %cond_true.i
+ ret void
+
+cond_next6.i119: ; preds = %cond_true.i
+ %tmp.i126 = icmp eq i16 0, 78 ; <i1> [#uses=1]
+ br i1 %tmp.i126, label %cond_next778, label %bb802
+
+cond_next778: ; preds = %cond_next6.i119
+ %tmp781 = icmp eq i32 0, 1 ; <i1> [#uses=1]
+ br i1 %tmp781, label %cond_next784, label %bb790
+
+cond_next784: ; preds = %cond_next778
+ %tmp785 = load i32* @ix86_cpu ; <i32> [#uses=1]
+ %tmp786 = icmp eq i32 %tmp785, 5 ; <i1> [#uses=1]
+ br i1 %tmp786, label %UnifiedReturnBlock, label %bb790
+
+bb790: ; preds = %cond_next784, %cond_next778
+ %tmp793 = icmp eq i32 0, 1 ; <i1> [#uses=0]
+ ret void
+
+bb802: ; preds = %cond_next6.i119
+ ret void
+
+bb839: ; preds = %cond_true.i, %cond_true.i
+ ret void
+
+bb919: ; preds = %cond_true.i, %cond_true.i
+ ret void
+
+bb993: ; preds = %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i
+ ret void
+
+bb1096: ; preds = %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i
+ ret void
+
+bb1126: ; preds = %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i
+ ret void
+
+bb1154: ; preds = %cond_true.i
+ ret void
+
+bb1201: ; preds = %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i
+ ret void
+
+bb1238: ; preds = %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i
+ ret void
+
+bb1419: ; preds = %cond_true.i
+ ret void
+
+bb1648: ; preds = %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i
+ %tmp1650 = load i32* @which_alternative ; <i32> [#uses=1]
+ switch i32 %tmp1650, label %bb1701 [
+ i32 0, label %cond_next1675
+ i32 1, label %cond_next1675
+ i32 2, label %cond_next1675
+ ]
+
+cond_next1675: ; preds = %bb1648, %bb1648, %bb1648
+ ret void
+
+bb1701: ; preds = %bb1648
+ %tmp1702 = load i32* @which_alternative ; <i32> [#uses=1]
+ switch i32 %tmp1702, label %bb1808 [
+ i32 0, label %cond_next1727
+ i32 1, label %cond_next1727
+ i32 2, label %cond_next1727
+ ]
+
+cond_next1727: ; preds = %bb1701, %bb1701, %bb1701
+ ret void
+
+bb1808: ; preds = %bb1701
+ %bothcond696 = or i1 false, false ; <i1> [#uses=1]
+ br i1 %bothcond696, label %bb1876, label %cond_next1834
+
+cond_next1834: ; preds = %bb1808
+ ret void
+
+bb1876: ; preds = %bb1808
+ %tmp1877signed = load i32* @which_alternative ; <i32> [#uses=4]
+ %tmp1877 = bitcast i32 %tmp1877signed to i32 ; <i32> [#uses=1]
+ %bothcond699 = icmp ult i32 %tmp1877, 2 ; <i1> [#uses=1]
+ %tmp1888 = icmp eq i32 %tmp1877signed, 2 ; <i1> [#uses=1]
+ %bothcond700 = or i1 %bothcond699, %tmp1888 ; <i1> [#uses=1]
+ %bothcond700.not = xor i1 %bothcond700, true ; <i1> [#uses=1]
+ %tmp1894 = icmp eq i32 %tmp1877signed, 3 ; <i1> [#uses=1]
+ %bothcond701 = or i1 %tmp1894, %bothcond700.not ; <i1> [#uses=1]
+ %bothcond702 = or i1 %bothcond701, false ; <i1> [#uses=1]
+ br i1 %bothcond702, label %UnifiedReturnBlock, label %cond_next1902
+
+cond_next1902: ; preds = %bb1876
+ switch i32 %tmp1877signed, label %cond_next1937 [
+ i32 0, label %bb1918
+ i32 1, label %bb1918
+ i32 2, label %bb1918
+ ]
+
+bb1918: ; preds = %cond_next1902, %cond_next1902, %cond_next1902
+ ret void
+
+cond_next1937: ; preds = %cond_next1902
+ ret void
+
+bb1948: ; preds = %cond_true.i, %cond_true.i, %cond_true.i
+ ret void
+
+bb1994: ; preds = %cond_true.i, %cond_true.i
+ ret void
+
+bb2035: ; preds = %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i, %cond_true.i
+ ret void
+
+bb2063: ; preds = %cond_true.i
+ ret void
+
+UnifiedReturnBlock: ; preds = %bb1876, %cond_next784, %cond_true.i
+ %UnifiedRetVal = phi i32 [ 100, %bb1876 ], [ 100, %cond_true.i ], [ 4, %cond_next784 ] ; <i32> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/Generic/2006-07-03-schedulers.ll b/test/CodeGen/Generic/2006-07-03-schedulers.ll
new file mode 100644
index 0000000..756bd5d
--- /dev/null
+++ b/test/CodeGen/Generic/2006-07-03-schedulers.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -pre-RA-sched=default
+; RUN: llc < %s -pre-RA-sched=list-burr
+; RUN: llc < %s -pre-RA-sched=fast
+; PR859
+
+; The top-down schedulers are excluded here because they don't yet support
+; targets that use physreg defs.
+
+declare i32 @printf(i8*, i32, float)
+
+define i32 @testissue(i32 %i, float %x, float %y) {
+ br label %bb1
+
+bb1: ; preds = %bb1, %0
+ %x1 = fmul float %x, %y ; <float> [#uses=1]
+ %y1 = fmul float %y, 7.500000e-01 ; <float> [#uses=1]
+ %z1 = fadd float %x1, %y1 ; <float> [#uses=1]
+ %x2 = fmul float %x, 5.000000e-01 ; <float> [#uses=1]
+ %y2 = fmul float %y, 0x3FECCCCCC0000000 ; <float> [#uses=1]
+ %z2 = fadd float %x2, %y2 ; <float> [#uses=1]
+ %z3 = fadd float %z1, %z2 ; <float> [#uses=1]
+ %i1 = shl i32 %i, 3 ; <i32> [#uses=1]
+ %j1 = add i32 %i, 7 ; <i32> [#uses=1]
+ %m1 = add i32 %i1, %j1 ; <i32> [#uses=2]
+ %b = icmp sle i32 %m1, 6 ; <i1> [#uses=1]
+ br i1 %b, label %bb1, label %bb2
+
+bb2: ; preds = %bb1
+ %Msg = inttoptr i64 0 to i8* ; <i8*> [#uses=1]
+ call i32 @printf( i8* %Msg, i32 %m1, float %z3 ) ; <i32>:1 [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/Generic/2006-08-30-CoalescerCrash.ll b/test/CodeGen/Generic/2006-08-30-CoalescerCrash.ll
new file mode 100644
index 0000000..cbe8b15
--- /dev/null
+++ b/test/CodeGen/Generic/2006-08-30-CoalescerCrash.ll
@@ -0,0 +1,112 @@
+; RUN: llc < %s
+%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.VEC_edge = type { i32, i32, [1 x %struct.edge_def*] }
+ %struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
+ %struct.basic_block_def = type { %struct.rtx_def*, %struct.rtx_def*, %struct.tree_node*, %struct.VEC_edge*, %struct.VEC_edge*, %struct.bitmap_head_def*, %struct.bitmap_head_def*, i8*, %struct.loop*, [2 x %struct.et_node*], %struct.basic_block_def*, %struct.basic_block_def*, %struct.reorder_block_def*, %struct.bb_ann_d*, i64, i32, i32, i32, i32 }
+ %struct.bb_ann_d = type { %struct.tree_node*, i8, %struct.edge_prediction* }
+ %struct.bitmap_element_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, [4 x i32] }
+ %struct.bitmap_head_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, %struct.bitmap_obstack* }
+ %struct.bitmap_obstack = type { %struct.bitmap_element_def*, %struct.bitmap_head_def*, %struct.obstack }
+ %struct.cost_pair = type { %struct.iv_cand*, i32, %struct.bitmap_head_def* }
+ %struct.dataflow_d = type { %struct.varray_head_tag*, [2 x %struct.tree_node*] }
+ %struct.def_operand_ptr = type { %struct.tree_node** }
+ %struct.def_optype_d = type { i32, [1 x %struct.def_operand_ptr] }
+ %struct.edge_def = type { %struct.basic_block_def*, %struct.basic_block_def*, %struct.edge_def_insns, i8*, %struct.location_t*, i32, i32, i64, i32 }
+ %struct.edge_def_insns = type { %struct.rtx_def* }
+ %struct.edge_prediction = type { %struct.edge_prediction*, %struct.edge_def*, i32, i32 }
+ %struct.eh_status = type opaque
+ %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }
+ %struct.et_node = type opaque
+ %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+ %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i1, i1, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 }
+ %struct.htab = type { i32 (i8*)*, i32 (i8*, i8*)*, void (i8*)*, i8**, i32, i32, i32, i32, i32, i8* (i32, i32)*, void (i8*)*, i8*, i8* (i8*, i32, i32)*, void (i8*, i8*)*, i32 }
+ %struct.initial_value_struct = type opaque
+ %struct.iv = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i1, i1, i32 }
+ %struct.iv_cand = type { i32, i1, i32, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.iv*, i32 }
+ %struct.iv_use = type { i32, i32, %struct.iv*, %struct.tree_node*, %struct.tree_node**, %struct.bitmap_head_def*, i32, %struct.cost_pair*, %struct.iv_cand* }
+ %struct.ivopts_data = type { %struct.loop*, %struct.htab*, i32, %struct.version_info*, %struct.bitmap_head_def*, i32, %struct.varray_head_tag*, %struct.varray_head_tag*, %struct.bitmap_head_def*, i1 }
+ %struct.lang_decl = type opaque
+ %struct.language_function = type opaque
+ %struct.location_t = type { i8*, i32 }
+ %struct.loop = type { i32, %struct.basic_block_def*, %struct.basic_block_def*, %struct.basic_block_def*, %struct.lpt_decision, i32, i32, %struct.edge_def**, i32, %struct.basic_block_def*, %struct.basic_block_def*, i32, %struct.edge_def**, i32, %struct.edge_def**, i32, %struct.simple_bitmap_def*, i32, %struct.loop**, i32, %struct.loop*, %struct.loop*, %struct.loop*, %struct.loop*, i32, i8*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i32, %struct.tree_node*, %struct.tree_node*, %struct.nb_iter_bound*, %struct.edge_def*, i1 }
+ %struct.lpt_decision = type { i32, i32 }
+ %struct.machine_function = type { %struct.stack_local_entry*, i8*, %struct.rtx_def*, i32, i32, i32, i32, i32 }
+ %struct.nb_iter_bound = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.nb_iter_bound* }
+ %struct.obstack = type { i32, %struct._obstack_chunk*, i8*, i8*, i8*, i32, i32, %struct._obstack_chunk* (i8*, i32)*, void (i8*, %struct._obstack_chunk*)*, i8*, i8 }
+ %struct.reorder_block_def = type { %struct.rtx_def*, %struct.rtx_def*, %struct.basic_block_def*, %struct.basic_block_def*, %struct.basic_block_def*, i32, i32, i32 }
+ %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }
+ %struct.rtx_def = type { i16, i8, i8, %struct.u }
+ %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
+ %struct.simple_bitmap_def = type { i32, i32, i32, [1 x i64] }
+ %struct.stack_local_entry = type opaque
+ %struct.stmt_ann_d = type { %struct.tree_ann_common_d, i8, %struct.basic_block_def*, %struct.stmt_operands_d, %struct.dataflow_d*, %struct.bitmap_head_def*, i32 }
+ %struct.stmt_operands_d = type { %struct.def_optype_d*, %struct.def_optype_d*, %struct.v_may_def_optype_d*, %struct.vuse_optype_d*, %struct.v_may_def_optype_d* }
+ %struct.temp_slot = type opaque
+ %struct.tree_ann_common_d = type { i32, i8*, %struct.tree_node* }
+ %struct.tree_ann_d = type { %struct.stmt_ann_d }
+ %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_ann_d*, i8, i8, i8, i8, i8 }
+ %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_decl_u1 = type { i64 }
+ %struct.tree_decl_u2 = type { %struct.function* }
+ %struct.tree_node = type { %struct.tree_decl }
+ %struct.u = type { [1 x i64] }
+ %struct.v_def_use_operand_type_t = type { %struct.tree_node*, %struct.tree_node* }
+ %struct.v_may_def_optype_d = type { i32, [1 x %struct.v_def_use_operand_type_t] }
+ %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+ %struct.varasm_status = type opaque
+ %struct.varray_head_tag = type { i32, i32, i32, i8*, %struct.u }
+ %struct.version_info = type { %struct.tree_node*, %struct.iv*, i1, i32, i1 }
+ %struct.vuse_optype_d = type { i32, [1 x %struct.tree_node*] }
+
+define i1 @determine_use_iv_cost(%struct.ivopts_data* %data, %struct.iv_use* %use, %struct.iv_cand* %cand) {
+entry:
+ switch i32 0, label %bb91 [
+ i32 0, label %bb
+ i32 1, label %bb6
+ i32 3, label %cond_next135
+ ]
+
+bb: ; preds = %entry
+ ret i1 false
+
+bb6: ; preds = %entry
+ br i1 false, label %bb87, label %cond_next27
+
+cond_next27: ; preds = %bb6
+ br i1 false, label %cond_true30, label %cond_next55
+
+cond_true30: ; preds = %cond_next27
+ br i1 false, label %cond_next41, label %cond_true35
+
+cond_true35: ; preds = %cond_true30
+ ret i1 false
+
+cond_next41: ; preds = %cond_true30
+ %tmp44 = call i32 @force_var_cost( %struct.ivopts_data* %data, %struct.tree_node* null, %struct.bitmap_head_def** null ) ; <i32> [#uses=2]
+ %tmp46 = udiv i32 %tmp44, 5 ; <i32> [#uses=1]
+ call void @set_use_iv_cost( %struct.ivopts_data* %data, %struct.iv_use* %use, %struct.iv_cand* %cand, i32 %tmp46, %struct.bitmap_head_def* null )
+ %tmp44.off = add i32 %tmp44, -50000000 ; <i32> [#uses=1]
+ %tmp52 = icmp ugt i32 %tmp44.off, 4 ; <i1> [#uses=1]
+ %tmp52.upgrd.1 = zext i1 %tmp52 to i32 ; <i32> [#uses=1]
+ br label %bb87
+
+cond_next55: ; preds = %cond_next27
+ ret i1 false
+
+bb87: ; preds = %cond_next41, %bb6
+ %tmp2.0 = phi i32 [ %tmp52.upgrd.1, %cond_next41 ], [ 1, %bb6 ] ; <i32> [#uses=0]
+ ret i1 false
+
+bb91: ; preds = %entry
+ ret i1 false
+
+cond_next135: ; preds = %entry
+ %tmp193 = call i1 @determine_use_iv_cost_generic( %struct.ivopts_data* %data, %struct.iv_use* %use, %struct.iv_cand* %cand ) ; <i1> [#uses=0]
+ ret i1 false
+}
+
+declare void @set_use_iv_cost(%struct.ivopts_data*, %struct.iv_use*, %struct.iv_cand*, i32, %struct.bitmap_head_def*)
+
+declare i32 @force_var_cost(%struct.ivopts_data*, %struct.tree_node*, %struct.bitmap_head_def**)
+
+declare i1 @determine_use_iv_cost_generic(%struct.ivopts_data*, %struct.iv_use*, %struct.iv_cand*)
diff --git a/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll b/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll
new file mode 100644
index 0000000..4b332b3
--- /dev/null
+++ b/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll
@@ -0,0 +1,117 @@
+; RUN: llc < %s -regalloc=local
+
+%struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 }
+@search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=2]
+@bishop_shift_rl45 = external global [64 x i32] ; <[64 x i32]*> [#uses=1]
+@bishop_shift_rr45 = external global [64 x i32] ; <[64 x i32]*> [#uses=1]
+@black_outpost = external global [64 x i8] ; <[64 x i8]*> [#uses=1]
+@bishop_mobility_rl45 = external global [64 x [256 x i32]] ; <[64 x [256 x i32]]*> [#uses=1]
+@bishop_mobility_rr45 = external global [64 x [256 x i32]] ; <[64 x [256 x i32]]*> [#uses=1]
+
+declare fastcc i32 @FirstOne()
+
+define fastcc void @Evaluate() {
+entry:
+ br i1 false, label %cond_false186, label %cond_true
+
+cond_true: ; preds = %entry
+ ret void
+
+cond_false186: ; preds = %entry
+ br i1 false, label %cond_true293, label %bb203
+
+bb203: ; preds = %cond_false186
+ ret void
+
+cond_true293: ; preds = %cond_false186
+ br i1 false, label %cond_true298, label %cond_next317
+
+cond_true298: ; preds = %cond_true293
+ br i1 false, label %cond_next518, label %cond_true397.preheader
+
+cond_next317: ; preds = %cond_true293
+ ret void
+
+cond_true397.preheader: ; preds = %cond_true298
+ ret void
+
+cond_next518: ; preds = %cond_true298
+ br i1 false, label %bb1069, label %cond_true522
+
+cond_true522: ; preds = %cond_next518
+ ret void
+
+bb1069: ; preds = %cond_next518
+ br i1 false, label %cond_next1131, label %bb1096
+
+bb1096: ; preds = %bb1069
+ ret void
+
+cond_next1131: ; preds = %bb1069
+ br i1 false, label %cond_next1207, label %cond_true1150
+
+cond_true1150: ; preds = %cond_next1131
+ ret void
+
+cond_next1207: ; preds = %cond_next1131
+ br i1 false, label %cond_next1219, label %cond_true1211
+
+cond_true1211: ; preds = %cond_next1207
+ ret void
+
+cond_next1219: ; preds = %cond_next1207
+ br i1 false, label %cond_true1223, label %cond_next1283
+
+cond_true1223: ; preds = %cond_next1219
+ br i1 false, label %cond_true1254, label %cond_true1264
+
+cond_true1254: ; preds = %cond_true1223
+ br i1 false, label %bb1567, label %cond_true1369.preheader
+
+cond_true1264: ; preds = %cond_true1223
+ ret void
+
+cond_next1283: ; preds = %cond_next1219
+ ret void
+
+cond_true1369.preheader: ; preds = %cond_true1254
+ ret void
+
+bb1567: ; preds = %cond_true1254
+ %tmp1580 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 3) ; <i64> [#uses=1]
+ %tmp1591 = load i64* getelementptr (%struct.CHESS_POSITION* @search, i32 0, i32 4) ; <i64> [#uses=1]
+ %tmp1572 = tail call fastcc i32 @FirstOne( ) ; <i32> [#uses=5]
+ %tmp1582 = getelementptr [64 x i32]* @bishop_shift_rl45, i32 0, i32 %tmp1572 ; <i32*> [#uses=1]
+ %tmp1583 = load i32* %tmp1582 ; <i32> [#uses=1]
+ %tmp1583.upgrd.1 = trunc i32 %tmp1583 to i8 ; <i8> [#uses=1]
+ %shift.upgrd.2 = zext i8 %tmp1583.upgrd.1 to i64 ; <i64> [#uses=1]
+ %tmp1584 = lshr i64 %tmp1580, %shift.upgrd.2 ; <i64> [#uses=1]
+ %tmp1584.upgrd.3 = trunc i64 %tmp1584 to i32 ; <i32> [#uses=1]
+ %tmp1585 = and i32 %tmp1584.upgrd.3, 255 ; <i32> [#uses=1]
+ %gep.upgrd.4 = zext i32 %tmp1585 to i64 ; <i64> [#uses=1]
+ %tmp1587 = getelementptr [64 x [256 x i32]]* @bishop_mobility_rl45, i32 0, i32 %tmp1572, i64 %gep.upgrd.4 ; <i32*> [#uses=1]
+ %tmp1588 = load i32* %tmp1587 ; <i32> [#uses=1]
+ %tmp1593 = getelementptr [64 x i32]* @bishop_shift_rr45, i32 0, i32 %tmp1572 ; <i32*> [#uses=1]
+ %tmp1594 = load i32* %tmp1593 ; <i32> [#uses=1]
+ %tmp1594.upgrd.5 = trunc i32 %tmp1594 to i8 ; <i8> [#uses=1]
+ %shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64 ; <i64> [#uses=1]
+ %tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6 ; <i64> [#uses=1]
+ %tmp1595.upgrd.7 = trunc i64 %tmp1595 to i32 ; <i32> [#uses=1]
+ %tmp1596 = and i32 %tmp1595.upgrd.7, 255 ; <i32> [#uses=1]
+ %gep.upgrd.8 = zext i32 %tmp1596 to i64 ; <i64> [#uses=1]
+ %tmp1598 = getelementptr [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; <i32*> [#uses=1]
+ %tmp1599 = load i32* %tmp1598 ; <i32> [#uses=1]
+ %tmp1600.neg = sub i32 0, %tmp1588 ; <i32> [#uses=1]
+ %tmp1602 = sub i32 %tmp1600.neg, %tmp1599 ; <i32> [#uses=1]
+ %tmp1604 = getelementptr [64 x i8]* @black_outpost, i32 0, i32 %tmp1572 ; <i8*> [#uses=1]
+ %tmp1605 = load i8* %tmp1604 ; <i8> [#uses=1]
+ %tmp1606 = icmp eq i8 %tmp1605, 0 ; <i1> [#uses=1]
+ br i1 %tmp1606, label %cond_next1637, label %cond_true1607
+
+cond_true1607: ; preds = %bb1567
+ ret void
+
+cond_next1637: ; preds = %bb1567
+ %tmp1662 = sub i32 %tmp1602, 0 ; <i32> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/Generic/2006-09-06-SwitchLowering.ll b/test/CodeGen/Generic/2006-09-06-SwitchLowering.ll
new file mode 100644
index 0000000..3d592b3
--- /dev/null
+++ b/test/CodeGen/Generic/2006-09-06-SwitchLowering.ll
@@ -0,0 +1,96 @@
+; RUN: llc < %s
+
+define void @foo() {
+ br label %cond_true813.i
+
+cond_true813.i: ; preds = %0
+ br i1 false, label %cond_true818.i, label %cond_next1146.i
+
+cond_true818.i: ; preds = %cond_true813.i
+ br i1 false, label %recog_memoized.exit52, label %cond_next1146.i
+
+recog_memoized.exit52: ; preds = %cond_true818.i
+ switch i32 0, label %bb886.i.preheader [
+ i32 0, label %bb907.i
+ i32 44, label %bb866.i
+ i32 103, label %bb874.i
+ i32 114, label %bb874.i
+ ]
+
+bb857.i: ; preds = %bb886.i, %bb866.i
+ %tmp862.i494.24 = phi i8* [ null, %bb866.i ], [ %tmp862.i494.26, %bb886.i ] ; <i8*> [#uses=4]
+ switch i32 0, label %bb886.i.preheader [
+ i32 0, label %bb907.i
+ i32 44, label %bb866.i
+ i32 103, label %bb874.i
+ i32 114, label %bb874.i
+ ]
+
+bb866.i.loopexit: ; preds = %bb874.i
+ br label %bb866.i
+
+bb866.i.loopexit31: ; preds = %cond_true903.i
+ br label %bb866.i
+
+bb866.i: ; preds = %bb866.i.loopexit31, %bb866.i.loopexit, %bb857.i, %recog_memoized.exit52
+ br i1 false, label %bb907.i, label %bb857.i
+
+bb874.i.preheader.loopexit: ; preds = %cond_true903.i, %cond_true903.i
+ ret void
+
+bb874.i: ; preds = %bb857.i, %bb857.i, %recog_memoized.exit52, %recog_memoized.exit52
+ %tmp862.i494.25 = phi i8* [ %tmp862.i494.24, %bb857.i ], [ %tmp862.i494.24, %bb857.i ], [ undef, %recog_memoized.exit52 ], [ undef, %recog_memoized.exit52 ] ; <i8*> [#uses=1]
+ switch i32 0, label %bb886.i.preheader.loopexit [
+ i32 0, label %bb907.i
+ i32 44, label %bb866.i.loopexit
+ i32 103, label %bb874.i.backedge
+ i32 114, label %bb874.i.backedge
+ ]
+
+bb874.i.backedge: ; preds = %bb874.i, %bb874.i
+ ret void
+
+bb886.i.preheader.loopexit: ; preds = %bb874.i
+ ret void
+
+bb886.i.preheader: ; preds = %bb857.i, %recog_memoized.exit52
+ %tmp862.i494.26 = phi i8* [ undef, %recog_memoized.exit52 ], [ %tmp862.i494.24, %bb857.i ] ; <i8*> [#uses=1]
+ br label %bb886.i
+
+bb886.i: ; preds = %cond_true903.i, %bb886.i.preheader
+ br i1 false, label %bb857.i, label %cond_true903.i
+
+cond_true903.i: ; preds = %bb886.i
+ switch i32 0, label %bb886.i [
+ i32 0, label %bb907.i
+ i32 44, label %bb866.i.loopexit31
+ i32 103, label %bb874.i.preheader.loopexit
+ i32 114, label %bb874.i.preheader.loopexit
+ ]
+
+bb907.i: ; preds = %cond_true903.i, %bb874.i, %bb866.i, %bb857.i, %recog_memoized.exit52
+ %tmp862.i494.0 = phi i8* [ %tmp862.i494.24, %bb857.i ], [ null, %bb866.i ], [ undef, %recog_memoized.exit52 ], [ %tmp862.i494.25, %bb874.i ], [ null, %cond_true903.i ] ; <i8*> [#uses=1]
+ br i1 false, label %cond_next1146.i, label %cond_true910.i
+
+cond_true910.i: ; preds = %bb907.i
+ ret void
+
+cond_next1146.i: ; preds = %bb907.i, %cond_true818.i, %cond_true813.i
+ %tmp862.i494.1 = phi i8* [ %tmp862.i494.0, %bb907.i ], [ undef, %cond_true818.i ], [ undef, %cond_true813.i ] ; <i8*> [#uses=0]
+ ret void
+
+bb2060.i: ; No predecessors!
+ br i1 false, label %cond_true2064.i, label %bb2067.i
+
+cond_true2064.i: ; preds = %bb2060.i
+ unreachable
+
+bb2067.i: ; preds = %bb2060.i
+ ret void
+
+cond_next3473: ; No predecessors!
+ ret void
+
+cond_next3521: ; No predecessors!
+ ret void
+}
diff --git a/test/CodeGen/Generic/2006-10-27-CondFolding.ll b/test/CodeGen/Generic/2006-10-27-CondFolding.ll
new file mode 100644
index 0000000..51902c8
--- /dev/null
+++ b/test/CodeGen/Generic/2006-10-27-CondFolding.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s
+
+define void @start_pass_huff(i32 %gather_statistics) {
+entry:
+ %tmp = icmp eq i32 %gather_statistics, 0 ; <i1> [#uses=1]
+ br i1 false, label %cond_next22, label %bb166
+
+cond_next22: ; preds = %entry
+ %bothcond = and i1 false, %tmp ; <i1> [#uses=1]
+ br i1 %bothcond, label %bb34, label %bb46
+
+bb34: ; preds = %cond_next22
+ ret void
+
+bb46: ; preds = %cond_next22
+ ret void
+
+bb166: ; preds = %entry
+ ret void
+}
+
diff --git a/test/CodeGen/Generic/2006-10-29-Crash.ll b/test/CodeGen/Generic/2006-10-29-Crash.ll
new file mode 100644
index 0000000..7dcb52c
--- /dev/null
+++ b/test/CodeGen/Generic/2006-10-29-Crash.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s
+
+define void @form_component_prediction(i32 %dy) {
+entry:
+ %tmp7 = and i32 %dy, 1 ; <i32> [#uses=1]
+ %tmp27 = icmp eq i32 %tmp7, 0 ; <i1> [#uses=1]
+ br i1 false, label %cond_next30, label %bb115
+
+cond_next30: ; preds = %entry
+ ret void
+
+bb115: ; preds = %entry
+ %bothcond1 = or i1 %tmp27, false ; <i1> [#uses=1]
+ br i1 %bothcond1, label %bb228, label %cond_next125
+
+cond_next125: ; preds = %bb115
+ ret void
+
+bb228: ; preds = %bb115
+ ret void
+}
+
diff --git a/test/CodeGen/Generic/2006-11-20-DAGCombineCrash.ll b/test/CodeGen/Generic/2006-11-20-DAGCombineCrash.ll
new file mode 100644
index 0000000..26d0f4f
--- /dev/null
+++ b/test/CodeGen/Generic/2006-11-20-DAGCombineCrash.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s
+; PR1011
+%struct.mng_data = type { i8* (%struct.mng_data*, i32)*, i32, i32, i32, i8, i8, i32, i32, i32, i32, i32 }
+
+define void @mng_display_bgr565() {
+entry:
+ br i1 false, label %bb.preheader, label %return
+
+bb.preheader: ; preds = %entry
+ br i1 false, label %cond_true48, label %cond_next80
+
+cond_true48: ; preds = %bb.preheader
+ %tmp = load i8* null ; <i8> [#uses=1]
+ %tmp51 = zext i8 %tmp to i16 ; <i16> [#uses=1]
+ %tmp99 = load i8* null ; <i8> [#uses=1]
+ %tmp54 = bitcast i8 %tmp99 to i8 ; <i8> [#uses=1]
+ %tmp54.upgrd.1 = zext i8 %tmp54 to i32 ; <i32> [#uses=1]
+ %tmp55 = lshr i32 %tmp54.upgrd.1, 3 ; <i32> [#uses=1]
+ %tmp55.upgrd.2 = trunc i32 %tmp55 to i16 ; <i16> [#uses=1]
+ %tmp52 = shl i16 %tmp51, 5 ; <i16> [#uses=1]
+ %tmp56 = and i16 %tmp55.upgrd.2, 28 ; <i16> [#uses=1]
+ %tmp57 = or i16 %tmp56, %tmp52 ; <i16> [#uses=1]
+ %tmp60 = zext i16 %tmp57 to i32 ; <i32> [#uses=1]
+ %tmp62 = xor i32 0, 65535 ; <i32> [#uses=1]
+ %tmp63 = mul i32 %tmp60, %tmp62 ; <i32> [#uses=1]
+ %tmp65 = add i32 0, %tmp63 ; <i32> [#uses=1]
+ %tmp69 = add i32 0, %tmp65 ; <i32> [#uses=1]
+ %tmp70 = lshr i32 %tmp69, 16 ; <i32> [#uses=1]
+ %tmp70.upgrd.3 = trunc i32 %tmp70 to i16 ; <i16> [#uses=1]
+ %tmp75 = lshr i16 %tmp70.upgrd.3, 8 ; <i16> [#uses=1]
+ %tmp75.upgrd.4 = trunc i16 %tmp75 to i8 ; <i8> [#uses=1]
+ %tmp76 = lshr i8 %tmp75.upgrd.4, 5 ; <i8> [#uses=1]
+ store i8 %tmp76, i8* null
+ ret void
+
+cond_next80: ; preds = %bb.preheader
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/Generic/2007-01-15-LoadSelectCycle.ll b/test/CodeGen/Generic/2007-01-15-LoadSelectCycle.ll
new file mode 100644
index 0000000..255b120
--- /dev/null
+++ b/test/CodeGen/Generic/2007-01-15-LoadSelectCycle.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s
+; PR1114
+
+declare i1 @foo()
+
+define i32 @test(i32* %A, i32* %B) {
+ %a = load i32* %A
+ %b = load i32* %B
+ %cond = call i1 @foo()
+ %c = select i1 %cond, i32 %a, i32 %b
+ ret i32 %c
+}
diff --git a/test/CodeGen/Generic/2007-02-16-BranchFold.ll b/test/CodeGen/Generic/2007-02-16-BranchFold.ll
new file mode 100644
index 0000000..6bf5631
--- /dev/null
+++ b/test/CodeGen/Generic/2007-02-16-BranchFold.ll
@@ -0,0 +1,95 @@
+; PR 1200
+; RUN: llc < %s -enable-tail-merge=0 | not grep jmp
+
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32"
+target triple = "i686-apple-darwin8"
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.Index_Map = type { i32, %struct.item_set** }
+ %struct.Item = type { [4 x i16], %struct.rule* }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+ %struct.dimension = type { i16*, %struct.Index_Map, %struct.mapping*, i32, %struct.plankMap* }
+ %struct.item_set = type { i32, i32, %struct.operator*, [2 x %struct.item_set*], %struct.item_set*, i16*, %struct.Item*, %struct.Item* }
+ %struct.list = type { i8*, %struct.list* }
+ %struct.mapping = type { %struct.list**, i32, i32, i32, %struct.item_set** }
+ %struct.nonterminal = type { i8*, i32, i32, i32, %struct.plankMap*, %struct.rule* }
+ %struct.operator = type { i8*, i8, i32, i32, i32, i32, %struct.table* }
+ %struct.pattern = type { %struct.nonterminal*, %struct.operator*, [2 x %struct.nonterminal*] }
+ %struct.plank = type { i8*, %struct.list*, i32 }
+ %struct.plankMap = type { %struct.list*, i32, %struct.stateMap* }
+ %struct.rule = type { [4 x i16], i32, i32, i32, %struct.nonterminal*, %struct.pattern*, i8 }
+ %struct.stateMap = type { i8*, %struct.plank*, i32, i16* }
+ %struct.table = type { %struct.operator*, %struct.list*, i16*, [2 x %struct.dimension*], %struct.item_set** }
+@outfile = external global %struct.FILE* ; <%struct.FILE**> [#uses=1]
+@str1 = external global [11 x i8] ; <[11 x i8]*> [#uses=1]
+
+declare i32 @fprintf(%struct.FILE*, i8*, ...)
+
+define i16 @main_bb_2E_i9_2E_i_2E_i932_2E_ce(%struct.list* %l_addr.01.0.i2.i.i929, %struct.operator** %tmp66.i62.i.out) {
+newFuncRoot:
+ br label %bb.i9.i.i932.ce
+
+NewDefault: ; preds = %LeafBlock, %LeafBlock1, %LeafBlock2, %LeafBlock3
+ br label %bb36.i.i.exitStub
+
+bb36.i.i.exitStub: ; preds = %NewDefault
+ store %struct.operator* %tmp66.i62.i, %struct.operator** %tmp66.i62.i.out
+ ret i16 0
+
+bb.i14.i.exitStub: ; preds = %LeafBlock
+ store %struct.operator* %tmp66.i62.i, %struct.operator** %tmp66.i62.i.out
+ ret i16 1
+
+bb12.i.i935.exitStub: ; preds = %LeafBlock1
+ store %struct.operator* %tmp66.i62.i, %struct.operator** %tmp66.i62.i.out
+ ret i16 2
+
+bb20.i.i937.exitStub: ; preds = %LeafBlock2
+ store %struct.operator* %tmp66.i62.i, %struct.operator** %tmp66.i62.i.out
+ ret i16 3
+
+bb28.i.i938.exitStub: ; preds = %LeafBlock3
+ store %struct.operator* %tmp66.i62.i, %struct.operator** %tmp66.i62.i.out
+ ret i16 4
+
+bb.i9.i.i932.ce: ; preds = %newFuncRoot
+ %tmp1.i3.i.i930 = getelementptr %struct.list* %l_addr.01.0.i2.i.i929, i32 0, i32 0 ; <i8**> [#uses=1]
+ %tmp2.i4.i.i931 = load i8** %tmp1.i3.i.i930 ; <i8*> [#uses=1]
+ %tmp66.i62.i = bitcast i8* %tmp2.i4.i.i931 to %struct.operator* ; <%struct.operator*> [#uses=7]
+ %tmp1.i6.i = getelementptr %struct.operator* %tmp66.i62.i, i32 0, i32 2 ; <i32*> [#uses=1]
+ %tmp2.i7.i = load i32* %tmp1.i6.i ; <i32> [#uses=1]
+ %tmp3.i8.i = load %struct.FILE** @outfile ; <%struct.FILE*> [#uses=1]
+ %tmp5.i9.i = call i32 (%struct.FILE*, i8*, ...)* @fprintf( %struct.FILE* %tmp3.i8.i, i8* getelementptr ([11 x i8]* @str1, i32 0, i32 0), i32 %tmp2.i7.i ) ; <i32> [#uses=0]
+ %tmp7.i10.i = getelementptr %struct.operator* %tmp66.i62.i, i32 0, i32 5 ; <i32*> [#uses=1]
+ %tmp8.i11.i = load i32* %tmp7.i10.i ; <i32> [#uses=7]
+ br label %NodeBlock5
+
+NodeBlock5: ; preds = %bb.i9.i.i932.ce
+ icmp slt i32 %tmp8.i11.i, 1 ; <i1>:0 [#uses=1]
+ br i1 %0, label %NodeBlock, label %NodeBlock4
+
+NodeBlock4: ; preds = %NodeBlock5
+ icmp slt i32 %tmp8.i11.i, 2 ; <i1>:1 [#uses=1]
+ br i1 %1, label %LeafBlock2, label %LeafBlock3
+
+LeafBlock3: ; preds = %NodeBlock4
+ icmp eq i32 %tmp8.i11.i, 2 ; <i1>:2 [#uses=1]
+ br i1 %2, label %bb28.i.i938.exitStub, label %NewDefault
+
+LeafBlock2: ; preds = %NodeBlock4
+ icmp eq i32 %tmp8.i11.i, 1 ; <i1>:3 [#uses=1]
+ br i1 %3, label %bb20.i.i937.exitStub, label %NewDefault
+
+NodeBlock: ; preds = %NodeBlock5
+ icmp slt i32 %tmp8.i11.i, 0 ; <i1>:4 [#uses=1]
+ br i1 %4, label %LeafBlock, label %LeafBlock1
+
+LeafBlock1: ; preds = %NodeBlock
+ icmp eq i32 %tmp8.i11.i, 0 ; <i1>:5 [#uses=1]
+ br i1 %5, label %bb12.i.i935.exitStub, label %NewDefault
+
+LeafBlock: ; preds = %NodeBlock
+ icmp eq i32 %tmp8.i11.i, -1 ; <i1>:6 [#uses=1]
+ br i1 %6, label %bb.i14.i.exitStub, label %NewDefault
+}
diff --git a/test/CodeGen/Generic/2007-02-25-invoke.ll b/test/CodeGen/Generic/2007-02-25-invoke.ll
new file mode 100644
index 0000000..6e20eaa
--- /dev/null
+++ b/test/CodeGen/Generic/2007-02-25-invoke.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s
+
+; PR1224
+
+declare i32 @test()
+define i32 @test2() {
+ %A = invoke i32 @test() to label %invcont unwind label %blat
+invcont:
+ ret i32 %A
+blat:
+ ret i32 0
+}
diff --git a/test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll b/test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll
new file mode 100644
index 0000000..339f0f7
--- /dev/null
+++ b/test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+; XFAIL: sparc-sun-solaris2
+; PR1308
+; PR1557
+
+define i32 @stuff(i32, ...) {
+ %foo = alloca i8*
+ %bar = alloca i32*
+ %A = call i32 asm sideeffect "inline asm $0 $2 $3 $4", "=r,0,i,m,m"( i32 0, i32 1, i8** %foo, i32** %bar )
+ ret i32 %A
+}
diff --git a/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll b/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
new file mode 100644
index 0000000..a0b1403
--- /dev/null
+++ b/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -O0
+; PR 1323
+
+; ModuleID = 'test.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+ %struct.comp = type { i8*, i32, i8*, [3 x i8], i32 }
+
+define void @regbranch() {
+cond_next240.i:
+ br i1 false, label %cond_true251.i, label %cond_next272.i
+
+cond_true251.i: ; preds = %cond_next240.i
+ switch i8 0, label %cond_next272.i [
+ i8 42, label %bb268.i
+ i8 43, label %bb268.i
+ i8 63, label %bb268.i
+ ]
+
+bb268.i: ; preds = %cond_true251.i, %cond_true251.i, %cond_true251.i
+ br label %cond_next272.i
+
+cond_next272.i: ; preds = %bb268.i, %cond_true251.i, %cond_next240.i
+ %len.2.i = phi i32 [ 0, %bb268.i ], [ 0, %cond_next240.i ], [ 0, %cond_true251.i ] ; <i32> [#uses=1]
+ %tmp278.i = icmp eq i32 %len.2.i, 1 ; <i1> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/Generic/2007-04-17-lsr-crash.ll b/test/CodeGen/Generic/2007-04-17-lsr-crash.ll
new file mode 100644
index 0000000..98f87e5
--- /dev/null
+++ b/test/CodeGen/Generic/2007-04-17-lsr-crash.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s
+
+define void @foo(i32 %inTextSize) {
+entry:
+ br label %bb236.outer
+
+cond_next193: ; preds = %bb236
+ %tmp211 = add i32 %inTextSize_addr.1.ph17, -2 ; <i32> [#uses=1]
+ br i1 false, label %cond_next232, label %cond_true227
+
+cond_true227: ; preds = %cond_next193
+ ret void
+
+cond_next232: ; preds = %cond_next193
+ %indvar.next49 = add i32 %indvar48, 1 ; <i32> [#uses=1]
+ br label %bb236.outer
+
+bb236.outer: ; preds = %cond_next232, %entry
+ %indvar48 = phi i32 [ %indvar.next49, %cond_next232 ], [ 0, %entry ] ; <i32> [#uses=2]
+ %inTextSize_addr.1.ph17 = phi i32 [ %tmp211, %cond_next232 ], [ %inTextSize, %entry ] ; <i32> [#uses=3]
+ %tmp.50 = sub i32 0, %indvar48 ; <i32> [#uses=1]
+ %tmp219 = icmp eq i32 %tmp.50, 0 ; <i1> [#uses=1]
+ br i1 %tmp219, label %bb236.us, label %bb236
+
+bb236.us: ; preds = %bb236.outer
+ %inTextSize_addr.1.us = add i32 0, %inTextSize_addr.1.ph17 ; <i32> [#uses=0]
+ ret void
+
+bb236: ; preds = %bb236.outer
+ %tmp238 = icmp eq i32 %inTextSize_addr.1.ph17, 0 ; <i1> [#uses=1]
+ br i1 %tmp238, label %exit, label %cond_next193
+
+exit: ; preds = %bb236
+ ret void
+}
diff --git a/test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll b/test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
new file mode 100644
index 0000000..af522dc
--- /dev/null
+++ b/test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s
+
+; Test that we can have an "X" output constraint.
+
+define void @test(i16 * %t) {
+ call void asm sideeffect "foo $0", "=*X,~{dirflag},~{fpsr},~{flags},~{memory}"( i16* %t )
+ ret void
+}
diff --git a/test/CodeGen/Generic/2007-04-27-LargeMemObject.ll b/test/CodeGen/Generic/2007-04-27-LargeMemObject.ll
new file mode 100644
index 0000000..f2c9b7f
--- /dev/null
+++ b/test/CodeGen/Generic/2007-04-27-LargeMemObject.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s
+
+ %struct..0anon = type { [100 x i32] }
+
+define void @test() {
+entry:
+ %currfpu = alloca %struct..0anon, align 16 ; <%struct..0anon*> [#uses=2]
+ %mxcsr = alloca %struct..0anon, align 16 ; <%struct..0anon*> [#uses=1]
+ call void asm sideeffect "fnstenv $0", "=*m,~{dirflag},~{fpsr},~{flags}"( %struct..0anon* %currfpu )
+ call void asm sideeffect "$0 $1", "=*m,*m,~{dirflag},~{fpsr},~{flags}"( %struct..0anon* %mxcsr, %struct..0anon* %currfpu )
+ ret void
+}
+
diff --git a/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll b/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll
new file mode 100644
index 0000000..568b88f
--- /dev/null
+++ b/test/CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll
@@ -0,0 +1,59 @@
+; RUN: llc < %s
+; PR1228
+
+ "struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Alloc_hider" = type { i8* }
+ "struct.std::locale" = type { "struct.std::locale::_Impl"* }
+ "struct.std::locale::_Impl" = type { i32, "struct.std::locale::facet"**, i32, "struct.std::locale::facet"**, i8** }
+ "struct.std::locale::facet" = type { i32 (...)**, i32 }
+ "struct.std::string" = type { "struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Alloc_hider" }
+
+define void @_ZNKSt6locale4nameEv("struct.std::string"* %agg.result) {
+entry:
+ %tmp105 = icmp eq i8* null, null ; <i1> [#uses=1]
+ br i1 %tmp105, label %cond_true, label %cond_true222
+
+cond_true: ; preds = %entry
+ invoke void @_ZNSs14_M_replace_auxEjjjc( )
+ to label %cond_next1328 unwind label %cond_true1402
+
+cond_true222: ; preds = %cond_true222, %entry
+ %tmp207 = call i32 @strcmp( ) ; <i32> [#uses=1]
+ %tmp208 = icmp eq i32 %tmp207, 0 ; <i1> [#uses=2]
+ %bothcond1480 = and i1 %tmp208, false ; <i1> [#uses=1]
+ br i1 %bothcond1480, label %cond_true222, label %cond_next226.loopexit
+
+cond_next226.loopexit: ; preds = %cond_true222
+ %phitmp = xor i1 %tmp208, true ; <i1> [#uses=1]
+ br i1 %phitmp, label %cond_false280, label %cond_true235
+
+cond_true235: ; preds = %cond_next226.loopexit
+ invoke void @_ZNSs6assignEPKcj( )
+ to label %cond_next1328 unwind label %cond_true1402
+
+cond_false280: ; preds = %cond_next226.loopexit
+ invoke void @_ZNSs7reserveEj( )
+ to label %invcont282 unwind label %cond_true1402
+
+invcont282: ; preds = %cond_false280
+ invoke void @_ZNSs6appendEPKcj( )
+ to label %invcont317 unwind label %cond_true1402
+
+invcont317: ; preds = %invcont282
+ ret void
+
+cond_next1328: ; preds = %cond_true235, %cond_true
+ ret void
+
+cond_true1402: ; preds = %invcont282, %cond_false280, %cond_true235, %cond_true
+ ret void
+}
+
+declare void @_ZNSs14_M_replace_auxEjjjc()
+
+declare i32 @strcmp()
+
+declare void @_ZNSs6assignEPKcj()
+
+declare void @_ZNSs7reserveEj()
+
+declare void @_ZNSs6appendEPKcj()
diff --git a/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll b/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll
new file mode 100644
index 0000000..bb774b4
--- /dev/null
+++ b/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -enable-eh
+
+ %struct.exception = type { i8, i8, i32, i8*, i8*, i32, i8* }
+@program_error = external global %struct.exception ; <%struct.exception*> [#uses=1]
+
+define void @typeinfo() {
+entry:
+ %eh_typeid = tail call i32 @llvm.eh.typeid.for.i32( i8* getelementptr (%struct.exception* @program_error, i32 0, i32 0) ) ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @llvm.eh.typeid.for.i32(i8*)
diff --git a/test/CodeGen/Generic/2007-05-05-Personality.ll b/test/CodeGen/Generic/2007-05-05-Personality.ll
new file mode 100644
index 0000000..2749326
--- /dev/null
+++ b/test/CodeGen/Generic/2007-05-05-Personality.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu -enable-eh -o - | grep zPLR
+
+@error = external global i8 ; <i8*> [#uses=2]
+
+define void @_ada_x() {
+entry:
+ invoke void @raise( )
+ to label %eh_then unwind label %unwind
+
+unwind: ; preds = %entry
+ %eh_ptr = tail call i8* @llvm.eh.exception( ) ; <i8*> [#uses=2]
+ %eh_select = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector.i32( i8* %eh_ptr, i8* bitcast (i32 (...)* @__gnat_eh_personality to i8*), i8* @error ) ; <i32> [#uses=1]
+ %eh_typeid = tail call i32 @llvm.eh.typeid.for.i32( i8* @error ) ; <i32> [#uses=1]
+ %tmp2 = icmp eq i32 %eh_select, %eh_typeid ; <i1> [#uses=1]
+ br i1 %tmp2, label %eh_then, label %Unwind
+
+eh_then: ; preds = %unwind, %entry
+ ret void
+
+Unwind: ; preds = %unwind
+ tail call i32 (...)* @_Unwind_Resume( i8* %eh_ptr ) ; <i32>:0 [#uses=0]
+ unreachable
+}
+
+declare void @raise()
+
+declare i8* @llvm.eh.exception()
+
+declare i32 @llvm.eh.selector.i32(i8*, i8*, ...)
+
+declare i32 @llvm.eh.typeid.for.i32(i8*)
+
+declare i32 @__gnat_eh_personality(...)
+
+declare i32 @_Unwind_Resume(...)
diff --git a/test/CodeGen/Generic/2007-05-15-InfiniteRecursion.ll b/test/CodeGen/Generic/2007-05-15-InfiniteRecursion.ll
new file mode 100644
index 0000000..b989819
--- /dev/null
+++ b/test/CodeGen/Generic/2007-05-15-InfiniteRecursion.ll
@@ -0,0 +1,90 @@
+; RUN: llc < %s
+
+ %struct.AVClass = type { i8*, i8* (i8*)*, %struct.AVOption* }
+ %struct.AVCodec = type { i8*, i32, i32, i32, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32, i8*)*, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32*, i8*, i32)*, i32, %struct.AVCodec*, void (%struct.AVCodecContext*)*, %struct.AVRational*, i32* }
+ %struct.AVCodecContext = type { %struct.AVClass*, i32, i32, i32, i32, i32, i8*, i32, %struct.AVRational, i32, i32, i32, i32, i32, void (%struct.AVCodecContext*, %struct.AVFrame*, i32*, i32, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32, i32, i32, %struct.AVCodec*, i8*, i32, i32, void (%struct.AVCodecContext*, i8*, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, [32 x i8], i32, i32, i32, i32, i32, i32, i32, float, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, void (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i8*, i8*, float, float, i32, %struct.RcOverride*, i32, i8*, i32, i32, i32, float, float, float, float, i32, float, float, float, float, float, i32, i32, i32, i32*, i32, i32, i32, i32, %struct.AVRational, %struct.AVFrame*, i32, i32, [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32*)*, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i16*, i16*, i32, i32, i32, i32, %struct.AVPaletteControl*, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32 (%struct.AVCodecContext*, i8*)*, i8**, i32*, i32)*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64 }
+ %struct.AVEvalExpr = type opaque
+ %struct.AVFrame = type { [4 x i8*], [4 x i32], [4 x i8*], i32, i32, i64, i32, i32, i32, i32, i32, i8*, i32, i8*, [2 x [2 x i16]*], i32*, i8, i8*, [4 x i64], i32, i32, i32, i32, i32, %struct.AVPanScan*, i32, i32, i16*, [2 x i8*] }
+ %struct.AVOption = type opaque
+ %struct.AVPaletteControl = type { i32, [256 x i32] }
+ %struct.AVPanScan = type { i32, i32, i32, [3 x [2 x i16]] }
+ %struct.AVRational = type { i32, i32 }
+ %struct.DSPContext = type { void (i16*, i8*, i32)*, void (i16*, i8*, i8*, i32)*, void (i16*, i8*, i32)*, void (i16*, i8*, i32)*, void (i16*, i8*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void (i8*, i8*, i32, i32, i32, i32, i32)*, void (i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)*, void (i16*)*, i32 (i8*, i32)*, i32 (i8*, i32)*, [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], [5 x i32 (i8*, i8*, i8*, i32, i32)*], i32 (i8*, i16*, i32)*, [4 x [4 x void (i8*, i8*, i32, i32)*]], [4 x [4 x void (i8*, i8*, i32, i32)*]], [4 x [4 x void (i8*, i8*, i32, i32)*]], [4 x [4 x void (i8*, i8*, i32, i32)*]], [2 x void (i8*, i8*, i8*, i32, i32)*], [11 x void (i8*, i8*, i32, i32, i32)*], [11 x void (i8*, i8*, i32, i32, i32)*], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], [8 x void (i8*, i8*, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [10 x void (i8*, i32, i32, i32, i32)*], [10 x void (i8*, i8*, i32, i32, i32, i32, i32)*], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i16*, i32)*, [2 x [4 x i32 (i8*, i8*, i8*, i32, i32)*]], void (i8*, i8*, i32)*, void (i8*, i8*, i8*, i32)*, void (i8*, i8*, i8*, i32, i32*, i32*)*, void (i32*, i32*, i32)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32)*, void (i8*, i32, i32, i32)*, void ([4 x [4 x i16]]*, i8*, [40 x i8]*, [40 x [2 x i16]]*, i32, i32, i32, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32)*, void (float*, float*, i32)*, void (float*, float*, i32)*, void (float*, float*, float*, i32)*, void (float*, float*, float*, float*, i32, i32, i32)*, void (i16*, float*, i32)*, void (i16*)*, void (i16*)*, void (i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, [64 x i8], i32, i32 (i16*, i16*, i16*, i32)*, void (i16*, i16*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void ([4 x i16]*)*, void (i32*, i32*, i32*, i32*, i32*, i32*, i32)*, void (i32*, i32)*, void (i8*, i32, i8**, i32, i32, i32, i32, i32, %struct.slice_buffer*, i32, i8*)*, void (i8*, i32, i32)*, [4 x void (i8*, i32, i8*, i32, i32, i32)*], void (i16*)*, void (i16*, i32)*, void (i16*, i32)*, void (i16*, i32)*, void (i8*, i32)*, void (i8*, i32)*, [16 x void (i8*, i8*, i32, i32)*] }
+ %struct.FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct.FILE*, i32, i32, i32, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i32, i32, [40 x i8] }
+ %struct.GetBitContext = type { i8*, i8*, i32*, i32, i32, i32, i32 }
+ %struct.MJpegContext = type opaque
+ %struct.MotionEstContext = type { %struct.AVCodecContext*, i32, [4 x [2 x i32]], [4 x [2 x i32]], i8*, i8*, [2 x i8*], i8*, i32, i32*, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x [4 x i8*]], [4 x [4 x i8*]], i32, i32, i32, i32, i32, [4 x void (i8*, i8*, i32, i32)*]*, [4 x void (i8*, i8*, i32, i32)*]*, [16 x void (i8*, i8*, i32)*]*, [16 x void (i8*, i8*, i32)*]*, [4097 x i8]*, i8*, i32 (%struct.MpegEncContext*, i32*, i32*, i32, i32, i32, i32, i32)* }
+ %struct.MpegEncContext = type { %struct.AVCodecContext*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.PutBitContext, i32, i32, i32, i32, i32, i32, i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.Picture*, %struct.Picture**, %struct.Picture**, i32, i32, [8 x %struct.MpegEncContext*], %struct.Picture, %struct.Picture, %struct.Picture, %struct.Picture, %struct.Picture*, %struct.Picture*, %struct.Picture*, [3 x i8*], [3 x i32], i16*, [3 x i16*], [20 x i16], i32, i32, i8*, i8*, i8*, i8*, i8*, [16 x i16]*, [3 x [16 x i16]*], i32, i8*, i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32*, i32, i32, i32, i32, i32, i32, i32, [5 x i32], i32, i32, i32, i32, %struct.DSPContext, i32, i32, [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x [2 x [2 x i16]*]], [2 x [2 x [2 x [2 x i16]*]]], [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x i16]*, [2 x [2 x [2 x i16]*]], [2 x [2 x [2 x [2 x i16]*]]], [2 x i8*], [2 x [2 x i8*]], i32, i32, i32, [2 x [4 x [2 x i32]]], [2 x [2 x i32]], [2 x [2 x [2 x i32]]], i8*, [2 x [64 x i16]], %struct.MotionEstContext, i32, i32, i32, i32, i32, i32, i16*, [6 x i32], [6 x i32], [3 x i8*], i32*, [64 x i16], [64 x i16], [64 x i16], [64 x i16], i32, i32, i32, i32, i32, i8*, i8*, i8*, i8*, i8*, i8*, [8 x i32], [64 x i32]*, [64 x i32]*, [2 x [64 x i16]]*, [2 x [64 x i16]]*, [12 x i32], %struct.ScanTable, %struct.ScanTable, %struct.ScanTable, %struct.ScanTable, [64 x i32]*, [2 x i32], [64 x i16]*, i8*, i64, i64, i32, i32, %struct.RateControlContext, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i32, i32, %struct.GetBitContext, i32, i32, i32, %struct.ParseContext, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i16, i16, i16, i16, i32, i32, i32, i32, i32, i32, i32, i32, i32, [2 x [2 x i32]], [2 x [2 x i32]], [2 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.PutBitContext, %struct.PutBitContext, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, i32, [3 x i32], %struct.MJpegContext*, [3 x i32], [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [2 x [65 x [65 x [2 x i32]]]]*, i32, i32, %struct.GetBitContext, i32, i32, i32, i8*, i32, [2 x [2 x i32]], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [2 x i32], i32, i32, i32, i32, i8*, i32, [12 x i16*], [64 x i16]*, [8 x [64 x i16]]*, i32 (%struct.MpegEncContext*, [64 x i16]*)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, void (%struct.MpegEncContext*, i16*, i32, i32)*, i32 (%struct.MpegEncContext*, i16*, i32, i32, i32*)*, i32 (%struct.MpegEncContext*, i16*, i32, i32, i32*)*, void (%struct.MpegEncContext*, i16*)* }
+ %struct.ParseContext = type { i8*, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.Picture = type { [4 x i8*], [4 x i32], [4 x i8*], i32, i32, i64, i32, i32, i32, i32, i32, i8*, i32, i8*, [2 x [2 x i16]*], i32*, i8, i8*, [4 x i64], i32, i32, i32, i32, i32, %struct.AVPanScan*, i32, i32, i16*, [2 x i8*], [3 x i8*], [2 x [2 x i16]*], i32*, [2 x i32], i32, i32, i32, i32, [2 x [16 x i32]], [2 x i32], i32, i32, i16*, i16*, i8*, i32*, i32 }
+ %struct.Predictor = type { double, double, double }
+ %struct.PutBitContext = type { i32, i32, i8*, i8*, i8* }
+ %struct.RateControlContext = type { %struct.FILE*, i32, %struct.RateControlEntry*, double, [5 x %struct.Predictor], double, double, double, double, double, [5 x double], i32, i32, [5 x i64], [5 x i64], [5 x i64], [5 x i64], [5 x i32], i32, i8*, float, i32, %struct.AVEvalExpr* }
+ %struct.RateControlEntry = type { i32, float, i32, i32, i32, i32, i32, i64, i32, float, i32, i32, i32, i32, i32, i32 }
+ %struct.RcOverride = type { i32, i32, i32, float }
+ %struct.ScanTable = type { i8*, [64 x i8], [64 x i8] }
+ %struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 }
+ %struct.slice_buffer = type opaque
+
+define float @ff_rate_estimate_qscale(%struct.MpegEncContext* %s, i32 %dry_run) {
+entry:
+ br i1 false, label %cond_false163, label %cond_true135
+
+cond_true135: ; preds = %entry
+ ret float 0.000000e+00
+
+cond_false163: ; preds = %entry
+ br i1 false, label %cond_true203, label %cond_next211
+
+cond_true203: ; preds = %cond_false163
+ ret float 0.000000e+00
+
+cond_next211: ; preds = %cond_false163
+ br i1 false, label %cond_false243, label %cond_true220
+
+cond_true220: ; preds = %cond_next211
+ br i1 false, label %cond_next237, label %cond_true225
+
+cond_true225: ; preds = %cond_true220
+ ret float 0.000000e+00
+
+cond_next237: ; preds = %cond_true220
+ br i1 false, label %cond_false785, label %cond_true735
+
+cond_false243: ; preds = %cond_next211
+ ret float 0.000000e+00
+
+cond_true735: ; preds = %cond_next237
+ ret float 0.000000e+00
+
+cond_false785: ; preds = %cond_next237
+ br i1 false, label %cond_true356.i.preheader, label %bb359.i
+
+cond_true356.i.preheader: ; preds = %cond_false785
+ %tmp116117.i = zext i8 0 to i32 ; <i32> [#uses=1]
+ br i1 false, label %cond_false.i, label %cond_next159.i
+
+cond_false.i: ; preds = %cond_true356.i.preheader
+ ret float 0.000000e+00
+
+cond_next159.i: ; preds = %cond_true356.i.preheader
+ %tmp178.i = add i32 %tmp116117.i, -128 ; <i32> [#uses=2]
+ %tmp181.i = mul i32 %tmp178.i, %tmp178.i ; <i32> [#uses=1]
+ %tmp181182.i = sitofp i32 %tmp181.i to float ; <float> [#uses=1]
+ %tmp199200.pn.in.i = fmul float %tmp181182.i, 0.000000e+00 ; <float> [#uses=1]
+ %tmp199200.pn.i = fpext float %tmp199200.pn.in.i to double ; <double> [#uses=1]
+ %tmp201.pn.i = fsub double 1.000000e+00, %tmp199200.pn.i ; <double> [#uses=1]
+ %factor.2.in.i = fmul double 0.000000e+00, %tmp201.pn.i ; <double> [#uses=1]
+ %factor.2.i = fptrunc double %factor.2.in.i to float ; <float> [#uses=1]
+ br i1 false, label %cond_next312.i, label %cond_false222.i
+
+cond_false222.i: ; preds = %cond_next159.i
+ ret float 0.000000e+00
+
+cond_next312.i: ; preds = %cond_next159.i
+ %tmp313314.i = fpext float %factor.2.i to double ; <double> [#uses=0]
+ ret float 0.000000e+00
+
+bb359.i: ; preds = %cond_false785
+ ret float 0.000000e+00
+}
diff --git a/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll b/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll
new file mode 100644
index 0000000..e220be6
--- /dev/null
+++ b/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll
@@ -0,0 +1,159 @@
+; RUN: llc < %s -o -
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i686-pc-linux-gnu"
+ %struct.RETURN = type { i32, i32 }
+ %struct.ada__finalization__controlled = type { %struct.system__finalization_root__root_controlled }
+ %struct.ada__streams__root_stream_type = type { %struct.ada__tags__dispatch_table* }
+ %struct.ada__strings__unbounded__string_access = type { i8*, %struct.RETURN* }
+ %struct.ada__strings__unbounded__unbounded_string = type { %struct.ada__finalization__controlled, %struct.ada__strings__unbounded__string_access, i32 }
+ %struct.ada__tags__dispatch_table = type { [1 x i32] }
+ %struct.exception = type { i8, i8, i32, i8*, i8*, i32, i8* }
+ %struct.system__finalization_root__root_controlled = type { %struct.ada__streams__root_stream_type, %struct.system__finalization_root__root_controlled*, %struct.system__finalization_root__root_controlled* }
+ %struct.system__standard_library__exception_data = type { i8, i8, i32, i32, %struct.system__standard_library__exception_data*, i32, void ()* }
[email protected] = internal constant %struct.RETURN { i32 1, i32 16 } ; <%struct.RETURN*> [#uses=1]
+@ada__strings__index_error = external global %struct.exception ; <%struct.exception*> [#uses=1]
[email protected] = internal constant [16 x i8] c"a-strunb.adb:690" ; <[16 x i8]*> [#uses=1]
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32)
+
+declare void @ada__strings__unbounded__realloc_for_chunk(%struct.ada__strings__unbounded__unbounded_string*, i32)
+
+declare void @__gnat_raise_exception(%struct.system__standard_library__exception_data*, i64)
+
+define void @ada__strings__unbounded__insert__2(%struct.ada__strings__unbounded__unbounded_string* %source, i32 %before, i64 %new_item.0.0) {
+entry:
+ %tmp24636 = lshr i64 %new_item.0.0, 32 ; <i64> [#uses=1]
+ %tmp24637 = trunc i64 %tmp24636 to i32 ; <i32> [#uses=1]
+ %tmp24638 = inttoptr i32 %tmp24637 to %struct.RETURN* ; <%struct.RETURN*> [#uses=2]
+ %tmp25 = getelementptr %struct.RETURN* %tmp24638, i32 0, i32 0 ; <i32*> [#uses=1]
+ %tmp26 = load i32* %tmp25, align 4 ; <i32> [#uses=1]
+ %tmp29 = getelementptr %struct.RETURN* %tmp24638, i32 0, i32 1 ; <i32*> [#uses=1]
+ %tmp30 = load i32* %tmp29, align 4 ; <i32> [#uses=1]
+ %tmp63 = getelementptr %struct.ada__strings__unbounded__unbounded_string* %source, i32 0, i32 1, i32 1 ; <%struct.RETURN**> [#uses=5]
+ %tmp64 = load %struct.RETURN** %tmp63, align 4 ; <%struct.RETURN*> [#uses=1]
+ %tmp65 = getelementptr %struct.RETURN* %tmp64, i32 0, i32 0 ; <i32*> [#uses=1]
+ %tmp66 = load i32* %tmp65, align 4 ; <i32> [#uses=1]
+ %tmp67 = icmp sgt i32 %tmp66, %before ; <i1> [#uses=1]
+ br i1 %tmp67, label %bb77, label %bb
+
+bb: ; preds = %entry
+ %tmp71 = getelementptr %struct.ada__strings__unbounded__unbounded_string* %source, i32 0, i32 2 ; <i32*> [#uses=4]
+ %tmp72 = load i32* %tmp71, align 4 ; <i32> [#uses=1]
+ %tmp73 = add i32 %tmp72, 1 ; <i32> [#uses=1]
+ %tmp74 = icmp slt i32 %tmp73, %before ; <i1> [#uses=1]
+ br i1 %tmp74, label %bb77, label %bb84
+
+bb77: ; preds = %bb, %entry
+ tail call void @__gnat_raise_exception( %struct.system__standard_library__exception_data* bitcast (%struct.exception* @ada__strings__index_error to %struct.system__standard_library__exception_data*), i64 or (i64 zext (i32 ptrtoint ([16 x i8]* @.str5 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.RETURN* @C.495.7639 to i32) to i64), i64 32)) )
+ unreachable
+
+bb84: ; preds = %bb
+ %tmp93 = sub i32 %tmp30, %tmp26 ; <i32> [#uses=2]
+ %tmp9394 = sext i32 %tmp93 to i36 ; <i36> [#uses=1]
+ %tmp95 = shl i36 %tmp9394, 3 ; <i36> [#uses=1]
+ %tmp96 = add i36 %tmp95, 8 ; <i36> [#uses=2]
+ %tmp97 = icmp sgt i36 %tmp96, -1 ; <i1> [#uses=1]
+ %tmp100 = select i1 %tmp97, i36 %tmp96, i36 0 ; <i36> [#uses=2]
+ %tmp101 = icmp slt i36 %tmp100, 17179869177 ; <i1> [#uses=1]
+ %tmp100.cast = trunc i36 %tmp100 to i32 ; <i32> [#uses=1]
+ %min102 = select i1 %tmp101, i32 %tmp100.cast, i32 -8 ; <i32> [#uses=1]
+ tail call void @ada__strings__unbounded__realloc_for_chunk( %struct.ada__strings__unbounded__unbounded_string* %source, i32 %min102 )
+ %tmp148 = load i32* %tmp71, align 4 ; <i32> [#uses=4]
+ %tmp152 = add i32 %tmp93, 1 ; <i32> [#uses=2]
+ %tmp153 = icmp sgt i32 %tmp152, -1 ; <i1> [#uses=1]
+ %max154 = select i1 %tmp153, i32 %tmp152, i32 0 ; <i32> [#uses=5]
+ %tmp155 = add i32 %tmp148, %max154 ; <i32> [#uses=5]
+ %tmp315 = getelementptr %struct.ada__strings__unbounded__unbounded_string* %source, i32 0, i32 1, i32 0 ; <i8**> [#uses=4]
+ %tmp328 = load %struct.RETURN** %tmp63, align 4 ; <%struct.RETURN*> [#uses=1]
+ %tmp329 = getelementptr %struct.RETURN* %tmp328, i32 0, i32 0 ; <i32*> [#uses=1]
+ %tmp330 = load i32* %tmp329, align 4 ; <i32> [#uses=4]
+ %tmp324 = add i32 %max154, %before ; <i32> [#uses=3]
+ %tmp331 = sub i32 %tmp324, %tmp330 ; <i32> [#uses=1]
+ %tmp349 = sub i32 %before, %tmp330 ; <i32> [#uses=1]
+ %tmp356 = icmp sgt i32 %tmp331, %tmp349 ; <i1> [#uses=1]
+ %tmp431 = icmp sgt i32 %tmp324, %tmp155 ; <i1> [#uses=2]
+ br i1 %tmp356, label %bb420, label %bb359
+
+bb359: ; preds = %bb84
+ br i1 %tmp431, label %bb481, label %bb382
+
+bb382: ; preds = %bb382, %bb359
+ %indvar = phi i32 [ 0, %bb359 ], [ %indvar.next, %bb382 ] ; <i32> [#uses=2]
+ %max379.pn = phi i32 [ %max154, %bb359 ], [ %L492b.0, %bb382 ] ; <i32> [#uses=1]
+ %before.pn = phi i32 [ %before, %bb359 ], [ 1, %bb382 ] ; <i32> [#uses=1]
+ %L492b.0 = add i32 %before.pn, %max379.pn ; <i32> [#uses=3]
+ %tmp386 = load %struct.RETURN** %tmp63, align 4 ; <%struct.RETURN*> [#uses=1]
+ %tmp387 = getelementptr %struct.RETURN* %tmp386, i32 0, i32 0 ; <i32*> [#uses=1]
+ %tmp388 = load i32* %tmp387, align 4 ; <i32> [#uses=2]
+ %tmp392 = load i8** %tmp315, align 4 ; <i8*> [#uses=2]
+ %R493b.0 = add i32 %indvar, %before ; <i32> [#uses=1]
+ %tmp405 = sub i32 %R493b.0, %tmp388 ; <i32> [#uses=1]
+ %tmp406 = getelementptr i8* %tmp392, i32 %tmp405 ; <i8*> [#uses=1]
+ %tmp407 = load i8* %tmp406, align 1 ; <i8> [#uses=1]
+ %tmp408 = sub i32 %L492b.0, %tmp388 ; <i32> [#uses=1]
+ %tmp409 = getelementptr i8* %tmp392, i32 %tmp408 ; <i8*> [#uses=1]
+ store i8 %tmp407, i8* %tmp409, align 1
+ %tmp414 = icmp eq i32 %L492b.0, %tmp155 ; <i1> [#uses=1]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br i1 %tmp414, label %bb481, label %bb382
+
+bb420: ; preds = %bb84
+ br i1 %tmp431, label %bb481, label %bb436.preheader
+
+bb436.preheader: ; preds = %bb420
+ %tmp4468 = load i8** %tmp315, align 4 ; <i8*> [#uses=2]
+ %tmp4599 = sub i32 %tmp148, %tmp330 ; <i32> [#uses=1]
+ %tmp46010 = getelementptr i8* %tmp4468, i32 %tmp4599 ; <i8*> [#uses=1]
+ %tmp46111 = load i8* %tmp46010, align 1 ; <i8> [#uses=1]
+ %tmp46212 = sub i32 %tmp155, %tmp330 ; <i32> [#uses=1]
+ %tmp46313 = getelementptr i8* %tmp4468, i32 %tmp46212 ; <i8*> [#uses=1]
+ store i8 %tmp46111, i8* %tmp46313, align 1
+ %exitcond14 = icmp eq i32 %tmp155, %tmp324 ; <i1> [#uses=1]
+ br i1 %exitcond14, label %bb481, label %bb.nph
+
+bb.nph: ; preds = %bb436.preheader
+ %tmp5 = sub i32 %tmp148, %before ; <i32> [#uses=1]
+ br label %bb478
+
+bb478: ; preds = %bb478, %bb.nph
+ %indvar6422 = phi i32 [ 0, %bb.nph ], [ %indvar.next643, %bb478 ] ; <i32> [#uses=1]
+ %indvar.next643 = add i32 %indvar6422, 1 ; <i32> [#uses=4]
+ %L490b.0 = sub i32 %tmp155, %indvar.next643 ; <i32> [#uses=1]
+ %R491b.0 = sub i32 %tmp148, %indvar.next643 ; <i32> [#uses=1]
+ %tmp440 = load %struct.RETURN** %tmp63, align 4 ; <%struct.RETURN*> [#uses=1]
+ %tmp441 = getelementptr %struct.RETURN* %tmp440, i32 0, i32 0 ; <i32*> [#uses=1]
+ %tmp442 = load i32* %tmp441, align 4 ; <i32> [#uses=2]
+ %tmp446 = load i8** %tmp315, align 4 ; <i8*> [#uses=2]
+ %tmp459 = sub i32 %R491b.0, %tmp442 ; <i32> [#uses=1]
+ %tmp460 = getelementptr i8* %tmp446, i32 %tmp459 ; <i8*> [#uses=1]
+ %tmp461 = load i8* %tmp460, align 1 ; <i8> [#uses=1]
+ %tmp462 = sub i32 %L490b.0, %tmp442 ; <i32> [#uses=1]
+ %tmp463 = getelementptr i8* %tmp446, i32 %tmp462 ; <i8*> [#uses=1]
+ store i8 %tmp461, i8* %tmp463, align 1
+ %exitcond = icmp eq i32 %indvar.next643, %tmp5 ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb481, label %bb478
+
+bb481: ; preds = %bb478, %bb436.preheader, %bb420, %bb382, %bb359
+ %tmp577 = add i32 %before, -1 ; <i32> [#uses=3]
+ %tmp578 = add i32 %max154, %tmp577 ; <i32> [#uses=2]
+ %tmp581 = icmp sge i32 %tmp578, %tmp577 ; <i1> [#uses=1]
+ %max582 = select i1 %tmp581, i32 %tmp578, i32 %tmp577 ; <i32> [#uses=1]
+ %tmp584 = sub i32 %max582, %before ; <i32> [#uses=1]
+ %tmp585 = add i32 %tmp584, 1 ; <i32> [#uses=2]
+ %tmp586 = icmp sgt i32 %tmp585, -1 ; <i1> [#uses=1]
+ %max587 = select i1 %tmp586, i32 %tmp585, i32 0 ; <i32> [#uses=1]
+ %tmp591 = load %struct.RETURN** %tmp63, align 4 ; <%struct.RETURN*> [#uses=1]
+ %tmp592 = getelementptr %struct.RETURN* %tmp591, i32 0, i32 0 ; <i32*> [#uses=1]
+ %tmp593 = load i32* %tmp592, align 4 ; <i32> [#uses=1]
+ %tmp597 = load i8** %tmp315, align 4 ; <i8*> [#uses=1]
+ %tmp600621 = trunc i64 %new_item.0.0 to i32 ; <i32> [#uses=1]
+ %tmp600622 = inttoptr i32 %tmp600621 to i8* ; <i8*> [#uses=1]
+ %tmp601 = sub i32 %before, %tmp593 ; <i32> [#uses=1]
+ %tmp602 = getelementptr i8* %tmp597, i32 %tmp601 ; <i8*> [#uses=1]
+ tail call void @llvm.memcpy.i32( i8* %tmp602, i8* %tmp600622, i32 %max587, i32 1 )
+ %tmp606 = load i32* %tmp71, align 4 ; <i32> [#uses=1]
+ %tmp613 = add i32 %tmp606, %max154 ; <i32> [#uses=1]
+ store i32 %tmp613, i32* %tmp71, align 4
+ ret void
+}
diff --git a/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll b/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll
new file mode 100644
index 0000000..bd26481
--- /dev/null
+++ b/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -enable-eh
+
+target triple = "i686-pc-linux-gnu"
+
+define fastcc void @bc__support__high_resolution_time__initialize_clock_rate() {
+entry:
+ invoke void asm "rdtsc\0A\09movl %eax, $0\0A\09movl %edx, $1", "=*imr,=*imr,~{dirflag},~{fpsr},~{flags},~{dx},~{ax}"( i32* null, i32* null )
+ to label %.noexc unwind label %cleanup144
+
+.noexc: ; preds = %entry
+ ret void
+
+cleanup144: ; preds = %entry
+ unwind
+}
diff --git a/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll b/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll
new file mode 100644
index 0000000..fc9164f
--- /dev/null
+++ b/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -enable-eh
+; PR1833
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i686-pc-linux-gnu"
+ %struct.__class_type_info_pseudo = type { %struct.__type_info_pseudo }
+ %struct.__type_info_pseudo = type { i8*, i8* }
+@_ZTI2e1 = external constant %struct.__class_type_info_pseudo ; <%struct.__class_type_info_pseudo*> [#uses=1]
+
+define void @_Z7ex_testv() {
+entry:
+ invoke void @__cxa_throw( i8* null, i8* bitcast (%struct.__class_type_info_pseudo* @_ZTI2e1 to i8*), void (i8*)* null ) noreturn
+ to label %UnifiedUnreachableBlock unwind label %lpad
+
+bb14: ; preds = %lpad
+ unreachable
+
+lpad: ; preds = %entry
+ invoke void @__cxa_end_catch( )
+ to label %bb14 unwind label %lpad17
+
+lpad17: ; preds = %lpad
+ %eh_select20 = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector.i32( i8* null, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* null ) ; <i32> [#uses=0]
+ unreachable
+
+UnifiedUnreachableBlock: ; preds = %entry
+ unreachable
+}
+
+declare void @__cxa_throw(i8*, i8*, void (i8*)*) noreturn
+
+declare i32 @llvm.eh.selector.i32(i8*, i8*, ...)
+
+declare void @__cxa_end_catch()
+
+declare i32 @__gxx_personality_v0(...)
diff --git a/test/CodeGen/Generic/2008-01-25-dag-combine-mul.ll b/test/CodeGen/Generic/2008-01-25-dag-combine-mul.ll
new file mode 100644
index 0000000..314bb05
--- /dev/null
+++ b/test/CodeGen/Generic/2008-01-25-dag-combine-mul.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s
+; rdar://5707064
+
+define i32 @f(i16* %pc) {
+entry:
+ %acc = alloca i64, align 8 ; <i64*> [#uses=4]
+ %tmp97 = load i64* %acc, align 8 ; <i64> [#uses=1]
+ %tmp98 = and i64 %tmp97, 4294967295 ; <i64> [#uses=1]
+ %tmp99 = load i64* null, align 8 ; <i64> [#uses=1]
+ %tmp100 = and i64 %tmp99, 4294967295 ; <i64> [#uses=1]
+ %tmp101 = mul i64 %tmp98, %tmp100 ; <i64> [#uses=1]
+ %tmp103 = lshr i64 %tmp101, 0 ; <i64> [#uses=1]
+ %tmp104 = load i64* %acc, align 8 ; <i64> [#uses=1]
+ %.cast105 = zext i32 32 to i64 ; <i64> [#uses=1]
+ %tmp106 = lshr i64 %tmp104, %.cast105 ; <i64> [#uses=1]
+ %tmp107 = load i64* null, align 8 ; <i64> [#uses=1]
+ %tmp108 = and i64 %tmp107, 4294967295 ; <i64> [#uses=1]
+ %tmp109 = mul i64 %tmp106, %tmp108 ; <i64> [#uses=1]
+ %tmp112 = add i64 %tmp109, 0 ; <i64> [#uses=1]
+ %tmp116 = add i64 %tmp112, 0 ; <i64> [#uses=1]
+ %tmp117 = add i64 %tmp103, %tmp116 ; <i64> [#uses=1]
+ %tmp118 = load i64* %acc, align 8 ; <i64> [#uses=1]
+ %tmp120 = lshr i64 %tmp118, 0 ; <i64> [#uses=1]
+ %tmp121 = load i64* null, align 8 ; <i64> [#uses=1]
+ %tmp123 = lshr i64 %tmp121, 0 ; <i64> [#uses=1]
+ %tmp124 = mul i64 %tmp120, %tmp123 ; <i64> [#uses=1]
+ %tmp126 = shl i64 %tmp124, 0 ; <i64> [#uses=1]
+ %tmp127 = add i64 %tmp117, %tmp126 ; <i64> [#uses=1]
+ store i64 %tmp127, i64* %acc, align 8
+ ret i32 0
+}
diff --git a/test/CodeGen/Generic/2008-01-30-LoadCrash.ll b/test/CodeGen/Generic/2008-01-30-LoadCrash.ll
new file mode 100644
index 0000000..70c3aaa
--- /dev/null
+++ b/test/CodeGen/Generic/2008-01-30-LoadCrash.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s
+
[email protected] = external constant [63 x i8] ; <[63 x i8]*> [#uses=2]
+
+define i32 @mkstemps(i8* %pattern, i32 %suffix_len, i64 %tmp42.rle) nounwind {
+bb20:
+ br label %bb41
+
+bb41: ; preds = %bb20
+ %tmp8182 = trunc i64 %tmp42.rle to i32 ; <i32> [#uses=1]
+ %tmp83 = getelementptr [63 x i8]* @letters.3100, i32 0, i32 %tmp8182 ; <i8*> [#uses=1]
+ %tmp84 = load i8* %tmp83, align 1 ; <i8> [#uses=1]
+ store i8 %tmp84, i8* null, align 1
+ %tmp90 = urem i64 %tmp42.rle, 62 ; <i64> [#uses=1]
+ %tmp9091 = trunc i64 %tmp90 to i32 ; <i32> [#uses=1]
+ %tmp92 = getelementptr [63 x i8]* @letters.3100, i32 0, i32 %tmp9091 ; <i8*> [#uses=1]
+ store i8* %tmp92, i8** null, align 1
+ ret i32 -1
+}
diff --git a/test/CodeGen/Generic/2008-02-04-Ctlz.ll b/test/CodeGen/Generic/2008-02-04-Ctlz.ll
new file mode 100644
index 0000000..288bfd2
--- /dev/null
+++ b/test/CodeGen/Generic/2008-02-04-Ctlz.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s
+
[email protected] = internal constant [14 x i8] c"%lld %d %d %d\00"
+
+define i32 @main(i64 %arg) nounwind {
+entry:
+ %tmp37 = tail call i64 @llvm.ctlz.i64( i64 %arg ) ; <i64> [#uses=1]
+ %tmp47 = tail call i64 @llvm.cttz.i64( i64 %arg ) ; <i64> [#uses=1]
+ %tmp57 = tail call i64 @llvm.ctpop.i64( i64 %arg ) ; <i64> [#uses=1]
+ %tmp38 = trunc i64 %tmp37 to i32 ; <i32>:0 [#uses=1]
+ %tmp48 = trunc i64 %tmp47 to i32 ; <i32>:0 [#uses=1]
+ %tmp58 = trunc i64 %tmp57 to i32 ; <i32>:0 [#uses=1]
+ %tmp40 = tail call i32 (i8*, ...)* @printf( i8* noalias getelementptr ([14 x i8]* @.str, i32 0, i32 0), i64 %arg, i32 %tmp38, i32 %tmp48, i32 %tmp58 ) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
+
+declare i32 @printf(i8* noalias , ...) nounwind
+
+declare i64 @llvm.ctlz.i64(i64) nounwind readnone
+declare i64 @llvm.cttz.i64(i64) nounwind readnone
+declare i64 @llvm.ctpop.i64(i64) nounwind readnone
diff --git a/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll b/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll
new file mode 100644
index 0000000..8bf82df
--- /dev/null
+++ b/test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s
+
+define i32 @main() nounwind {
+entry:
+ br label %bb15
+
+bb15: ; preds = %bb15, %entry
+ %tmp21 = fadd <8 x double> zeroinitializer, zeroinitializer ; <<8 x double>> [#uses=1]
+ br i1 false, label %bb30, label %bb15
+
+bb30: ; preds = %bb15
+ store <8 x double> %tmp21, <8 x double>* null, align 64
+ ret i32 0
+}
diff --git a/test/CodeGen/Generic/2008-02-20-MatchingMem.ll b/test/CodeGen/Generic/2008-02-20-MatchingMem.ll
new file mode 100644
index 0000000..da1aeb5
--- /dev/null
+++ b/test/CodeGen/Generic/2008-02-20-MatchingMem.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s
+; PR1133
+define void @test(i32* %X) nounwind {
+entry:
+ %tmp1 = getelementptr i32* %X, i32 10 ; <i32*> [#uses=2]
+ tail call void asm sideeffect " $0 $1 ", "=*im,*im,~{memory}"( i32* %tmp1, i32* %tmp1 ) nounwind
+ ret void
+}
+
diff --git a/test/CodeGen/Generic/2008-02-25-NegateZero.ll b/test/CodeGen/Generic/2008-02-25-NegateZero.ll
new file mode 100644
index 0000000..97db667
--- /dev/null
+++ b/test/CodeGen/Generic/2008-02-25-NegateZero.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s
+; rdar://5763967
+
+define void @test() {
+entry:
+ %tmp98 = load float* null, align 4 ; <float> [#uses=1]
+ %tmp106 = load float* null, align 4 ; <float> [#uses=1]
+ %tmp113 = fadd float %tmp98, %tmp106 ; <float> [#uses=1]
+ %tmp119 = fsub float %tmp113, 0.000000e+00 ; <float> [#uses=1]
+ call void (i32, ...)* @foo( i32 0, float 0.000000e+00, float %tmp119 ) nounwind
+ ret void
+}
+
+declare void @foo(i32, ...)
diff --git a/test/CodeGen/Generic/2008-02-26-NegatableCrash.ll b/test/CodeGen/Generic/2008-02-26-NegatableCrash.ll
new file mode 100644
index 0000000..10b3d44
--- /dev/null
+++ b/test/CodeGen/Generic/2008-02-26-NegatableCrash.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s
+; PR2096
+ %struct.AVClass = type { i8*, i8* (i8*)*, %struct.AVOption* }
+ %struct.AVCodec = type { i8*, i32, i32, i32, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32, i8*)*, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32*, i8*, i32)*, i32, %struct.AVCodec*, void (%struct.AVCodecContext*)*, %struct.AVRational*, i32* }
+ %struct.AVCodecContext = type { %struct.AVClass*, i32, i32, i32, i32, i32, i8*, i32, %struct.AVRational, i32, i32, i32, i32, i32, void (%struct.AVCodecContext*, %struct.AVFrame*, i32*, i32, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32, i32, i32, %struct.AVCodec*, i8*, i32, i32, void (%struct.AVCodecContext*, i8*, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, [32 x i8], i32, i32, i32, i32, i32, i32, i32, float, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, void (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i8*, i8*, float, float, i32, %struct.RcOverride*, i32, i8*, i32, i32, i32, float, float, float, float, i32, float, float, float, float, float, i32, i32, i32, i32*, i32, i32, i32, i32, %struct.AVRational, %struct.AVFrame*, i32, i32, [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32*)*, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i16*, i16*, i32, i32, i32, i32, %struct.AVPaletteControl*, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32 (%struct.AVCodecContext*, i8*)*, i8**, i32*, i32)*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i32, float }
+ %struct.AVFrame = type { [4 x i8*], [4 x i32], [4 x i8*], i32, i32, i64, i32, i32, i32, i32, i32, i8*, i32, i8*, [2 x [2 x i16]*], i32*, i8, i8*, [4 x i64], i32, i32, i32, i32, i32, %struct.AVPanScan*, i32, i32, i16*, [2 x i8*] }
+ %struct.AVOption = type opaque
+ %struct.AVPaletteControl = type { i32, [256 x i32] }
+ %struct.AVPanScan = type { i32, i32, i32, [3 x [2 x i16]] }
+ %struct.AVRational = type { i32, i32 }
+ %struct.RcOverride = type { i32, i32, i32, float }
+
+define i32 @sonic_encode_frame(%struct.AVCodecContext* %avctx, i8* %buf, i32 %buf_size, i8* %data) {
+entry:
+ switch i32 0, label %bb429 [
+ i32 0, label %bb244.preheader
+ i32 1, label %bb279.preheader
+ ]
+
+bb279.preheader: ; preds = %entry
+ ret i32 0
+
+bb244.preheader: ; preds = %entry
+ ret i32 0
+
+bb429: ; preds = %entry
+ br i1 false, label %bb.nph1770, label %bb627
+
+bb.nph1770: ; preds = %bb429
+ br i1 false, label %bb471, label %bb505
+
+bb471: ; preds = %bb471, %bb.nph1770
+ %tmp487 = fadd double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ br i1 false, label %bb505, label %bb471
+
+bb505: ; preds = %bb471, %bb.nph1770
+ %xy.0.lcssa = phi double [ 0.000000e+00, %bb.nph1770 ], [ %tmp487, %bb471 ] ; <double> [#uses=1]
+ %tmp507 = fsub double -0.000000e+00, %xy.0.lcssa ; <double> [#uses=1]
+ %tmp509 = fdiv double %tmp507, 0.000000e+00 ; <double> [#uses=1]
+ %tmp510 = fmul double %tmp509, 1.024000e+03 ; <double> [#uses=1]
+ %tmp516 = fdiv double %tmp510, 0.000000e+00 ; <double> [#uses=1]
+ %tmp517 = fadd double %tmp516, 5.000000e-01 ; <double> [#uses=1]
+ %tmp518 = tail call double @floor( double %tmp517 ) nounwind readnone ; <double> [#uses=0]
+ ret i32 0
+
+bb627: ; preds = %bb429
+ ret i32 0
+}
+
+declare double @floor(double) nounwind readnone
diff --git a/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll b/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll
new file mode 100644
index 0000000..4f95dfe
--- /dev/null
+++ b/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s
+; PR2603
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+ %struct.A = type { i8 }
+ %struct.B = type { i8, [1 x i8] }
+@Foo = constant %struct.A { i8 ptrtoint (i8* getelementptr ([1 x i8]* inttoptr (i32 17 to [1 x i8]*), i32 0, i32 -16) to i8) } ; <%struct.A*> [#uses=0]
diff --git a/test/CodeGen/Generic/2009-03-17-LSR-APInt.ll b/test/CodeGen/Generic/2009-03-17-LSR-APInt.ll
new file mode 100644
index 0000000..6281ada
--- /dev/null
+++ b/test/CodeGen/Generic/2009-03-17-LSR-APInt.ll
@@ -0,0 +1,92 @@
+; RUN: llc < %s
+; PR3806
+
+ %struct..0__pthread_mutex_s = type { i32, i32, i32, i32, i32, i32, %struct.__pthread_list_t }
+ %struct.Alignment = type { i32 }
+ %struct.QDesignerFormWindowInterface = type { %struct.QWidget }
+ %struct.QFont = type { %struct.QFontPrivate*, i32 }
+ %struct.QFontPrivate = type opaque
+ %"struct.QHash<QString,QList<QAbstractExtensionFactory*> >" = type { %"struct.QHash<QString,QList<QAbstractExtensionFactory*> >::._120" }
+ %"struct.QHash<QString,QList<QAbstractExtensionFactory*> >::._120" = type { %struct.QHashData* }
+ %struct.QHashData = type { %"struct.QHashData::Node"*, %"struct.QHashData::Node"**, %struct.Alignment, i32, i32, i16, i16, i32, i8 }
+ %"struct.QHashData::Node" = type { %"struct.QHashData::Node"*, i32 }
+ %"struct.QList<QAbstractExtensionFactory*>" = type { %"struct.QList<QAbstractExtensionFactory*>::._101" }
+ %"struct.QList<QAbstractExtensionFactory*>::._101" = type { %struct.QListData }
+ %struct.QListData = type { %"struct.QListData::Data"* }
+ %"struct.QListData::Data" = type { %struct.Alignment, i32, i32, i32, i8, [1 x i8*] }
+ %struct.QObject = type { i32 (...)**, %struct.QObjectData* }
+ %struct.QObjectData = type { i32 (...)**, %struct.QObject*, %struct.QObject*, %"struct.QList<QAbstractExtensionFactory*>", i32, i32 }
+ %struct.QPaintDevice.base = type { i32 (...)**, i16 }
+ %"struct.QPair<int,int>" = type { i32, i32 }
+ %struct.QPalette = type { %struct.QPalettePrivate*, i32 }
+ %struct.QPalettePrivate = type opaque
+ %struct.QRect = type { i32, i32, i32, i32 }
+ %struct.QWidget = type { %struct.QObject, %struct.QPaintDevice.base, %struct.QWidgetData* }
+ %struct.QWidgetData = type { i64, i32, %struct.Alignment, i8, i8, i16, %struct.QRect, %struct.QPalette, %struct.QFont, %struct.QRect }
+ %struct.__pthread_list_t = type { %struct.__pthread_list_t*, %struct.__pthread_list_t* }
+ %struct.pthread_attr_t = type { i64, [48 x i8] }
+ %struct.pthread_mutex_t = type { %struct..0__pthread_mutex_s }
+ %"struct.qdesigner_internal::Grid" = type { i32, i32, %struct.QWidget**, i8*, i8* }
+ %"struct.qdesigner_internal::GridLayout" = type { %"struct.qdesigner_internal::Layout", %"struct.QPair<int,int>", %"struct.qdesigner_internal::Grid"* }
+ %"struct.qdesigner_internal::Layout" = type { %struct.QObject, %"struct.QList<QAbstractExtensionFactory*>", %struct.QWidget*, %"struct.QHash<QString,QList<QAbstractExtensionFactory*> >", %struct.QWidget*, %struct.QDesignerFormWindowInterface*, i8, %"struct.QPair<int,int>", %struct.QRect, i8 }
+
+@_ZL20__gthrw_pthread_oncePiPFvvE = alias weak i32 (i32*, void ()*)* @pthread_once ; <i32 (i32*, void ()*)*> [#uses=0]
+@_ZL27__gthrw_pthread_getspecificj = alias weak i8* (i32)* @pthread_getspecific ; <i8* (i32)*> [#uses=0]
+@_ZL27__gthrw_pthread_setspecificjPKv = alias weak i32 (i32, i8*)* @pthread_setspecific ; <i32 (i32, i8*)*> [#uses=0]
+@_ZL22__gthrw_pthread_createPmPK14pthread_attr_tPFPvS3_ES3_ = alias weak i32 (i64*, %struct.pthread_attr_t*, i8* (i8*)*, i8*)* @pthread_create ; <i32 (i64*, %struct.pthread_attr_t*, i8* (i8*)*, i8*)*> [#uses=0]
+@_ZL22__gthrw_pthread_cancelm = alias weak i32 (i64)* @pthread_cancel ; <i32 (i64)*> [#uses=0]
+@_ZL26__gthrw_pthread_mutex_lockP15pthread_mutex_t = alias weak i32 (%struct.pthread_mutex_t*)* @pthread_mutex_lock ; <i32 (%struct.pthread_mutex_t*)*> [#uses=0]
+@_ZL29__gthrw_pthread_mutex_trylockP15pthread_mutex_t = alias weak i32 (%struct.pthread_mutex_t*)* @pthread_mutex_trylock ; <i32 (%struct.pthread_mutex_t*)*> [#uses=0]
+@_ZL28__gthrw_pthread_mutex_unlockP15pthread_mutex_t = alias weak i32 (%struct.pthread_mutex_t*)* @pthread_mutex_unlock ; <i32 (%struct.pthread_mutex_t*)*> [#uses=0]
+@_ZL26__gthrw_pthread_mutex_initP15pthread_mutex_tPK19pthread_mutexattr_t = alias weak i32 (%struct.pthread_mutex_t*, %struct.Alignment*)* @pthread_mutex_init ; <i32 (%struct.pthread_mutex_t*, %struct.Alignment*)*> [#uses=0]
+@_ZL26__gthrw_pthread_key_createPjPFvPvE = alias weak i32 (i32*, void (i8*)*)* @pthread_key_create ; <i32 (i32*, void (i8*)*)*> [#uses=0]
+@_ZL26__gthrw_pthread_key_deletej = alias weak i32 (i32)* @pthread_key_delete ; <i32 (i32)*> [#uses=0]
+@_ZL30__gthrw_pthread_mutexattr_initP19pthread_mutexattr_t = alias weak i32 (%struct.Alignment*)* @pthread_mutexattr_init ; <i32 (%struct.Alignment*)*> [#uses=0]
+@_ZL33__gthrw_pthread_mutexattr_settypeP19pthread_mutexattr_ti = alias weak i32 (%struct.Alignment*, i32)* @pthread_mutexattr_settype ; <i32 (%struct.Alignment*, i32)*> [#uses=0]
+@_ZL33__gthrw_pthread_mutexattr_destroyP19pthread_mutexattr_t = alias weak i32 (%struct.Alignment*)* @pthread_mutexattr_destroy ; <i32 (%struct.Alignment*)*> [#uses=0]
+
+define void @_ZN18qdesigner_internal10GridLayout9buildGridEv(%"struct.qdesigner_internal::GridLayout"* %this) nounwind {
+entry:
+ br label %bb44
+
+bb44: ; preds = %bb47, %entry
+ %indvar = phi i128 [ %indvar.next144, %bb47 ], [ 0, %entry ] ; <i128> [#uses=2]
+ br i1 false, label %bb46, label %bb47
+
+bb46: ; preds = %bb44
+ %tmp = shl i128 %indvar, 64 ; <i128> [#uses=1]
+ %tmp96 = and i128 %tmp, 79228162495817593519834398720 ; <i128> [#uses=0]
+ br label %bb47
+
+bb47: ; preds = %bb46, %bb44
+ %indvar.next144 = add i128 %indvar, 1 ; <i128> [#uses=1]
+ br label %bb44
+}
+
+declare i32 @pthread_once(i32*, void ()*)
+
+declare i8* @pthread_getspecific(i32)
+
+declare i32 @pthread_setspecific(i32, i8*)
+
+declare i32 @pthread_create(i64*, %struct.pthread_attr_t*, i8* (i8*)*, i8*)
+
+declare i32 @pthread_cancel(i64)
+
+declare i32 @pthread_mutex_lock(%struct.pthread_mutex_t*)
+
+declare i32 @pthread_mutex_trylock(%struct.pthread_mutex_t*)
+
+declare i32 @pthread_mutex_unlock(%struct.pthread_mutex_t*)
+
+declare i32 @pthread_mutex_init(%struct.pthread_mutex_t*, %struct.Alignment*)
+
+declare i32 @pthread_key_create(i32*, void (i8*)*)
+
+declare i32 @pthread_key_delete(i32)
+
+declare i32 @pthread_mutexattr_init(%struct.Alignment*)
+
+declare i32 @pthread_mutexattr_settype(%struct.Alignment*, i32)
+
+declare i32 @pthread_mutexattr_destroy(%struct.Alignment*)
diff --git a/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll b/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll
new file mode 100644
index 0000000..45b561a
--- /dev/null
+++ b/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -soft-float
+; PR3899
+
+@m = external global <2 x double>
+
+define double @vector_ex() nounwind {
+ %v = load <2 x double>* @m
+ %x = extractelement <2 x double> %v, i32 1
+ ret double %x
+}
diff --git a/test/CodeGen/Generic/2009-04-10-SinkCrash.ll b/test/CodeGen/Generic/2009-04-10-SinkCrash.ll
new file mode 100644
index 0000000..125f875
--- /dev/null
+++ b/test/CodeGen/Generic/2009-04-10-SinkCrash.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s
+
+define void @QRiterate(i32 %p.1, double %tmp.212) nounwind {
+entry:
+ br i1 false, label %shortcirc_next.1, label %exit.1.critedge
+
+shortcirc_next.1: ; preds = %shortcirc_next.1, %entry
+ %tmp.213 = fcmp une double %tmp.212, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %tmp.213, label %shortcirc_next.1, label %exit.1
+
+exit.1.critedge: ; preds = %entry
+ ret void
+
+exit.1: ; preds = %shortcirc_next.1
+ ret void
+}
diff --git a/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll b/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
new file mode 100644
index 0000000..b62f811
--- /dev/null
+++ b/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s
+; rdar://6836460
+; rdar://7516906
+; PR5963
+
+define i32 @test(i128* %P) nounwind {
+entry:
+ %tmp48 = load i128* %P
+ %and49 = and i128 %tmp48, 18446744073709551616 ; <i128> [#uses=1]
+ %tobool = icmp ne i128 %and49, 0 ; <i1> [#uses=1]
+ br i1 %tobool, label %if.then50, label %if.end61
+
+if.then50: ; preds = %if.then20
+ ret i32 1241
+
+if.end61: ; preds = %if.then50, %if.then20, %entry
+ ret i32 123
+}
+
+define i32 @test2(i320* %P) nounwind {
+entry:
+ %tmp48 = load i320* %P
+ %and49 = and i320 %tmp48, 25108406941546723055343157692830665664409421777856138051584
+ %tobool = icmp ne i320 %and49, 0 ; <i1> [#uses=1]
+ br i1 %tobool, label %if.then50, label %if.end61
+
+if.then50: ; preds = %if.then20
+ ret i32 1241
+
+if.end61: ; preds = %if.then50, %if.then20, %entry
+ ret i32 123
+}
diff --git a/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll b/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll
new file mode 100644
index 0000000..112cac4
--- /dev/null
+++ b/test/CodeGen/Generic/2009-06-03-UnreachableSplitPad.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s
+; PR4317
+
+declare i32 @b()
+
+define void @a() {
+entry:
+ ret void
+
+dummy:
+ invoke i32 @b() to label %reg unwind label %reg
+
+reg:
+ ret void
+}
diff --git a/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll b/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll
new file mode 100644
index 0000000..a51c75d
--- /dev/null
+++ b/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll
@@ -0,0 +1,75 @@
+; RUN: llc < %s
+; PR5495
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
+target triple = "i386-pc-linux-gnu"
+
+%"struct.std::__ctype_abstract_base<wchar_t>" = type { %"struct.std::locale::facet" }
+%"struct.std::basic_ios<char,std::char_traits<char> >" = type { %"struct.std::ios_base", %"struct.std::basic_ostream<char,std::char_traits<char> >"*, i8, i8, %"struct.std::basic_streambuf<char,std::char_traits<char> >"*, %"struct.std::ctype<char>"*, %"struct.std::__ctype_abstract_base<wchar_t>"*, %"struct.std::__ctype_abstract_base<wchar_t>"* }
+%"struct.std::basic_istream<char,std::char_traits<char> >" = type { i32 (...)**, i32, %"struct.std::basic_ios<char,std::char_traits<char> >" }
+%"struct.std::basic_ostream<char,std::char_traits<char> >" = type { i32 (...)**, %"struct.std::basic_ios<char,std::char_traits<char> >" }
+%"struct.std::basic_streambuf<char,std::char_traits<char> >" = type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %"struct.std::locale" }
+%"struct.std::ctype<char>" = type { %"struct.std::locale::facet", i32*, i8, i32*, i32*, i16*, i8, [256 x i8], [256 x i8], i8 }
+%"struct.std::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, %"struct.std::ios_base::_Callback_list"*, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, %"struct.std::ios_base::_Words"*, %"struct.std::locale" }
+%"struct.std::ios_base::_Callback_list" = type { %"struct.std::ios_base::_Callback_list"*, void (i32, %"struct.std::ios_base"*, i32)*, i32, i32 }
+%"struct.std::ios_base::_Words" = type { i8*, i32 }
+%"struct.std::locale" = type { %"struct.std::locale::_Impl"* }
+%"struct.std::locale::_Impl" = type { i32, %"struct.std::locale::facet"**, i32, %"struct.std::locale::facet"**, i8** }
+%"struct.std::locale::facet" = type { i32 (...)**, i32 }
+%union..0._15 = type { i32 }
+
+declare i8* @llvm.eh.exception() nounwind readonly
+
+declare i8* @__cxa_begin_catch(i8*) nounwind
+
+declare %"struct.std::ctype<char>"* @_ZSt9use_facetISt5ctypeIcEERKT_RKSt6locale(%"struct.std::locale"*)
+
+define %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_(%"struct.std::basic_istream<char,std::char_traits<char> >"* %__in, i8* nocapture %__s) {
+entry:
+ %0 = invoke %"struct.std::ctype<char>"* @_ZSt9use_facetISt5ctypeIcEERKT_RKSt6locale(%"struct.std::locale"* undef)
+ to label %invcont8 unwind label %lpad74 ; <%"struct.std::ctype<char>"*> [#uses=0]
+
+invcont8: ; preds = %entry
+ %1 = invoke i32 undef(%"struct.std::basic_streambuf<char,std::char_traits<char> >"* undef)
+ to label %bb26.preheader unwind label %lpad ; <i32> [#uses=0]
+
+bb26.preheader: ; preds = %invcont8
+ br label %invcont38
+
+bb1.i100: ; preds = %invcont38
+ %2 = add nsw i32 1, %__extracted.0 ; <i32> [#uses=3]
+ br i1 undef, label %bb.i97, label %bb1.i
+
+bb.i97: ; preds = %bb1.i100
+ br label %invcont38
+
+bb1.i: ; preds = %bb1.i100
+ %3 = invoke i32 undef(%"struct.std::basic_streambuf<char,std::char_traits<char> >"* undef)
+ to label %invcont38 unwind label %lpad ; <i32> [#uses=0]
+
+invcont24: ; preds = %invcont38
+ %4 = invoke i32 undef(%"struct.std::basic_streambuf<char,std::char_traits<char> >"* undef)
+ to label %_ZNSt15basic_streambufIcSt11char_traitsIcEE6sbumpcEv.exit.i unwind label %lpad ; <i32> [#uses=0]
+
+_ZNSt15basic_streambufIcSt11char_traitsIcEE6sbumpcEv.exit.i: ; preds = %invcont24
+ br i1 undef, label %invcont25, label %bb.i93
+
+bb.i93: ; preds = %_ZNSt15basic_streambufIcSt11char_traitsIcEE6sbumpcEv.exit.i
+ %5 = invoke i32 undef(%"struct.std::basic_streambuf<char,std::char_traits<char> >"* undef)
+ to label %invcont25 unwind label %lpad ; <i32> [#uses=0]
+
+invcont25: ; preds = %bb.i93, %_ZNSt15basic_streambufIcSt11char_traitsIcEE6sbumpcEv.exit.i
+ br label %invcont38
+
+invcont38: ; preds = %invcont25, %bb1.i, %bb.i97, %bb26.preheader
+ %__extracted.0 = phi i32 [ 0, %bb26.preheader ], [ undef, %invcont25 ], [ %2, %bb.i97 ], [ %2, %bb1.i ] ; <i32> [#uses=1]
+ br i1 false, label %bb1.i100, label %invcont24
+
+lpad: ; preds = %bb.i93, %invcont24, %bb1.i, %invcont8
+ %__extracted.1 = phi i32 [ 0, %invcont8 ], [ %2, %bb1.i ], [ undef, %bb.i93 ], [ undef, %invcont24 ] ; <i32> [#uses=0]
+ %eh_ptr = call i8* @llvm.eh.exception() ; <i8*> [#uses=1]
+ %6 = call i8* @__cxa_begin_catch(i8* %eh_ptr) nounwind ; <i8*> [#uses=0]
+ unreachable
+
+lpad74: ; preds = %entry
+ unreachable
+}
diff --git a/test/CodeGen/Generic/APIntLoadStore.ll b/test/CodeGen/Generic/APIntLoadStore.ll
new file mode 100644
index 0000000..7c71a33
--- /dev/null
+++ b/test/CodeGen/Generic/APIntLoadStore.ll
@@ -0,0 +1,2049 @@
+; RUN: llc < %s > %t
+@i1_l = external global i1 ; <i1*> [#uses=1]
+@i1_s = external global i1 ; <i1*> [#uses=1]
+@i2_l = external global i2 ; <i2*> [#uses=1]
+@i2_s = external global i2 ; <i2*> [#uses=1]
+@i3_l = external global i3 ; <i3*> [#uses=1]
+@i3_s = external global i3 ; <i3*> [#uses=1]
+@i4_l = external global i4 ; <i4*> [#uses=1]
+@i4_s = external global i4 ; <i4*> [#uses=1]
+@i5_l = external global i5 ; <i5*> [#uses=1]
+@i5_s = external global i5 ; <i5*> [#uses=1]
+@i6_l = external global i6 ; <i6*> [#uses=1]
+@i6_s = external global i6 ; <i6*> [#uses=1]
+@i7_l = external global i7 ; <i7*> [#uses=1]
+@i7_s = external global i7 ; <i7*> [#uses=1]
+@i8_l = external global i8 ; <i8*> [#uses=1]
+@i8_s = external global i8 ; <i8*> [#uses=1]
+@i9_l = external global i9 ; <i9*> [#uses=1]
+@i9_s = external global i9 ; <i9*> [#uses=1]
+@i10_l = external global i10 ; <i10*> [#uses=1]
+@i10_s = external global i10 ; <i10*> [#uses=1]
+@i11_l = external global i11 ; <i11*> [#uses=1]
+@i11_s = external global i11 ; <i11*> [#uses=1]
+@i12_l = external global i12 ; <i12*> [#uses=1]
+@i12_s = external global i12 ; <i12*> [#uses=1]
+@i13_l = external global i13 ; <i13*> [#uses=1]
+@i13_s = external global i13 ; <i13*> [#uses=1]
+@i14_l = external global i14 ; <i14*> [#uses=1]
+@i14_s = external global i14 ; <i14*> [#uses=1]
+@i15_l = external global i15 ; <i15*> [#uses=1]
+@i15_s = external global i15 ; <i15*> [#uses=1]
+@i16_l = external global i16 ; <i16*> [#uses=1]
+@i16_s = external global i16 ; <i16*> [#uses=1]
+@i17_l = external global i17 ; <i17*> [#uses=1]
+@i17_s = external global i17 ; <i17*> [#uses=1]
+@i18_l = external global i18 ; <i18*> [#uses=1]
+@i18_s = external global i18 ; <i18*> [#uses=1]
+@i19_l = external global i19 ; <i19*> [#uses=1]
+@i19_s = external global i19 ; <i19*> [#uses=1]
+@i20_l = external global i20 ; <i20*> [#uses=1]
+@i20_s = external global i20 ; <i20*> [#uses=1]
+@i21_l = external global i21 ; <i21*> [#uses=1]
+@i21_s = external global i21 ; <i21*> [#uses=1]
+@i22_l = external global i22 ; <i22*> [#uses=1]
+@i22_s = external global i22 ; <i22*> [#uses=1]
+@i23_l = external global i23 ; <i23*> [#uses=1]
+@i23_s = external global i23 ; <i23*> [#uses=1]
+@i24_l = external global i24 ; <i24*> [#uses=1]
+@i24_s = external global i24 ; <i24*> [#uses=1]
+@i25_l = external global i25 ; <i25*> [#uses=1]
+@i25_s = external global i25 ; <i25*> [#uses=1]
+@i26_l = external global i26 ; <i26*> [#uses=1]
+@i26_s = external global i26 ; <i26*> [#uses=1]
+@i27_l = external global i27 ; <i27*> [#uses=1]
+@i27_s = external global i27 ; <i27*> [#uses=1]
+@i28_l = external global i28 ; <i28*> [#uses=1]
+@i28_s = external global i28 ; <i28*> [#uses=1]
+@i29_l = external global i29 ; <i29*> [#uses=1]
+@i29_s = external global i29 ; <i29*> [#uses=1]
+@i30_l = external global i30 ; <i30*> [#uses=1]
+@i30_s = external global i30 ; <i30*> [#uses=1]
+@i31_l = external global i31 ; <i31*> [#uses=1]
+@i31_s = external global i31 ; <i31*> [#uses=1]
+@i32_l = external global i32 ; <i32*> [#uses=1]
+@i32_s = external global i32 ; <i32*> [#uses=1]
+@i33_l = external global i33 ; <i33*> [#uses=1]
+@i33_s = external global i33 ; <i33*> [#uses=1]
+@i34_l = external global i34 ; <i34*> [#uses=1]
+@i34_s = external global i34 ; <i34*> [#uses=1]
+@i35_l = external global i35 ; <i35*> [#uses=1]
+@i35_s = external global i35 ; <i35*> [#uses=1]
+@i36_l = external global i36 ; <i36*> [#uses=1]
+@i36_s = external global i36 ; <i36*> [#uses=1]
+@i37_l = external global i37 ; <i37*> [#uses=1]
+@i37_s = external global i37 ; <i37*> [#uses=1]
+@i38_l = external global i38 ; <i38*> [#uses=1]
+@i38_s = external global i38 ; <i38*> [#uses=1]
+@i39_l = external global i39 ; <i39*> [#uses=1]
+@i39_s = external global i39 ; <i39*> [#uses=1]
+@i40_l = external global i40 ; <i40*> [#uses=1]
+@i40_s = external global i40 ; <i40*> [#uses=1]
+@i41_l = external global i41 ; <i41*> [#uses=1]
+@i41_s = external global i41 ; <i41*> [#uses=1]
+@i42_l = external global i42 ; <i42*> [#uses=1]
+@i42_s = external global i42 ; <i42*> [#uses=1]
+@i43_l = external global i43 ; <i43*> [#uses=1]
+@i43_s = external global i43 ; <i43*> [#uses=1]
+@i44_l = external global i44 ; <i44*> [#uses=1]
+@i44_s = external global i44 ; <i44*> [#uses=1]
+@i45_l = external global i45 ; <i45*> [#uses=1]
+@i45_s = external global i45 ; <i45*> [#uses=1]
+@i46_l = external global i46 ; <i46*> [#uses=1]
+@i46_s = external global i46 ; <i46*> [#uses=1]
+@i47_l = external global i47 ; <i47*> [#uses=1]
+@i47_s = external global i47 ; <i47*> [#uses=1]
+@i48_l = external global i48 ; <i48*> [#uses=1]
+@i48_s = external global i48 ; <i48*> [#uses=1]
+@i49_l = external global i49 ; <i49*> [#uses=1]
+@i49_s = external global i49 ; <i49*> [#uses=1]
+@i50_l = external global i50 ; <i50*> [#uses=1]
+@i50_s = external global i50 ; <i50*> [#uses=1]
+@i51_l = external global i51 ; <i51*> [#uses=1]
+@i51_s = external global i51 ; <i51*> [#uses=1]
+@i52_l = external global i52 ; <i52*> [#uses=1]
+@i52_s = external global i52 ; <i52*> [#uses=1]
+@i53_l = external global i53 ; <i53*> [#uses=1]
+@i53_s = external global i53 ; <i53*> [#uses=1]
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+@i230_l = external global i230 ; <i230*> [#uses=1]
+@i230_s = external global i230 ; <i230*> [#uses=1]
+@i231_l = external global i231 ; <i231*> [#uses=1]
+@i231_s = external global i231 ; <i231*> [#uses=1]
+@i232_l = external global i232 ; <i232*> [#uses=1]
+@i232_s = external global i232 ; <i232*> [#uses=1]
+@i233_l = external global i233 ; <i233*> [#uses=1]
+@i233_s = external global i233 ; <i233*> [#uses=1]
+@i234_l = external global i234 ; <i234*> [#uses=1]
+@i234_s = external global i234 ; <i234*> [#uses=1]
+@i235_l = external global i235 ; <i235*> [#uses=1]
+@i235_s = external global i235 ; <i235*> [#uses=1]
+@i236_l = external global i236 ; <i236*> [#uses=1]
+@i236_s = external global i236 ; <i236*> [#uses=1]
+@i237_l = external global i237 ; <i237*> [#uses=1]
+@i237_s = external global i237 ; <i237*> [#uses=1]
+@i238_l = external global i238 ; <i238*> [#uses=1]
+@i238_s = external global i238 ; <i238*> [#uses=1]
+@i239_l = external global i239 ; <i239*> [#uses=1]
+@i239_s = external global i239 ; <i239*> [#uses=1]
+@i240_l = external global i240 ; <i240*> [#uses=1]
+@i240_s = external global i240 ; <i240*> [#uses=1]
+@i241_l = external global i241 ; <i241*> [#uses=1]
+@i241_s = external global i241 ; <i241*> [#uses=1]
+@i242_l = external global i242 ; <i242*> [#uses=1]
+@i242_s = external global i242 ; <i242*> [#uses=1]
+@i243_l = external global i243 ; <i243*> [#uses=1]
+@i243_s = external global i243 ; <i243*> [#uses=1]
+@i244_l = external global i244 ; <i244*> [#uses=1]
+@i244_s = external global i244 ; <i244*> [#uses=1]
+@i245_l = external global i245 ; <i245*> [#uses=1]
+@i245_s = external global i245 ; <i245*> [#uses=1]
+@i246_l = external global i246 ; <i246*> [#uses=1]
+@i246_s = external global i246 ; <i246*> [#uses=1]
+@i247_l = external global i247 ; <i247*> [#uses=1]
+@i247_s = external global i247 ; <i247*> [#uses=1]
+@i248_l = external global i248 ; <i248*> [#uses=1]
+@i248_s = external global i248 ; <i248*> [#uses=1]
+@i249_l = external global i249 ; <i249*> [#uses=1]
+@i249_s = external global i249 ; <i249*> [#uses=1]
+@i250_l = external global i250 ; <i250*> [#uses=1]
+@i250_s = external global i250 ; <i250*> [#uses=1]
+@i251_l = external global i251 ; <i251*> [#uses=1]
+@i251_s = external global i251 ; <i251*> [#uses=1]
+@i252_l = external global i252 ; <i252*> [#uses=1]
+@i252_s = external global i252 ; <i252*> [#uses=1]
+@i253_l = external global i253 ; <i253*> [#uses=1]
+@i253_s = external global i253 ; <i253*> [#uses=1]
+@i254_l = external global i254 ; <i254*> [#uses=1]
+@i254_s = external global i254 ; <i254*> [#uses=1]
+@i255_l = external global i255 ; <i255*> [#uses=1]
+@i255_s = external global i255 ; <i255*> [#uses=1]
+@i256_l = external global i256 ; <i256*> [#uses=1]
+@i256_s = external global i256 ; <i256*> [#uses=1]
+
+define void @i1_ls() nounwind {
+ %tmp = load i1* @i1_l ; <i1> [#uses=1]
+ store i1 %tmp, i1* @i1_s
+ ret void
+}
+
+define void @i2_ls() nounwind {
+ %tmp = load i2* @i2_l ; <i2> [#uses=1]
+ store i2 %tmp, i2* @i2_s
+ ret void
+}
+
+define void @i3_ls() nounwind {
+ %tmp = load i3* @i3_l ; <i3> [#uses=1]
+ store i3 %tmp, i3* @i3_s
+ ret void
+}
+
+define void @i4_ls() nounwind {
+ %tmp = load i4* @i4_l ; <i4> [#uses=1]
+ store i4 %tmp, i4* @i4_s
+ ret void
+}
+
+define void @i5_ls() nounwind {
+ %tmp = load i5* @i5_l ; <i5> [#uses=1]
+ store i5 %tmp, i5* @i5_s
+ ret void
+}
+
+define void @i6_ls() nounwind {
+ %tmp = load i6* @i6_l ; <i6> [#uses=1]
+ store i6 %tmp, i6* @i6_s
+ ret void
+}
+
+define void @i7_ls() nounwind {
+ %tmp = load i7* @i7_l ; <i7> [#uses=1]
+ store i7 %tmp, i7* @i7_s
+ ret void
+}
+
+define void @i8_ls() nounwind {
+ %tmp = load i8* @i8_l ; <i8> [#uses=1]
+ store i8 %tmp, i8* @i8_s
+ ret void
+}
+
+define void @i9_ls() nounwind {
+ %tmp = load i9* @i9_l ; <i9> [#uses=1]
+ store i9 %tmp, i9* @i9_s
+ ret void
+}
+
+define void @i10_ls() nounwind {
+ %tmp = load i10* @i10_l ; <i10> [#uses=1]
+ store i10 %tmp, i10* @i10_s
+ ret void
+}
+
+define void @i11_ls() nounwind {
+ %tmp = load i11* @i11_l ; <i11> [#uses=1]
+ store i11 %tmp, i11* @i11_s
+ ret void
+}
+
+define void @i12_ls() nounwind {
+ %tmp = load i12* @i12_l ; <i12> [#uses=1]
+ store i12 %tmp, i12* @i12_s
+ ret void
+}
+
+define void @i13_ls() nounwind {
+ %tmp = load i13* @i13_l ; <i13> [#uses=1]
+ store i13 %tmp, i13* @i13_s
+ ret void
+}
+
+define void @i14_ls() nounwind {
+ %tmp = load i14* @i14_l ; <i14> [#uses=1]
+ store i14 %tmp, i14* @i14_s
+ ret void
+}
+
+define void @i15_ls() nounwind {
+ %tmp = load i15* @i15_l ; <i15> [#uses=1]
+ store i15 %tmp, i15* @i15_s
+ ret void
+}
+
+define void @i16_ls() nounwind {
+ %tmp = load i16* @i16_l ; <i16> [#uses=1]
+ store i16 %tmp, i16* @i16_s
+ ret void
+}
+
+define void @i17_ls() nounwind {
+ %tmp = load i17* @i17_l ; <i17> [#uses=1]
+ store i17 %tmp, i17* @i17_s
+ ret void
+}
+
+define void @i18_ls() nounwind {
+ %tmp = load i18* @i18_l ; <i18> [#uses=1]
+ store i18 %tmp, i18* @i18_s
+ ret void
+}
+
+define void @i19_ls() nounwind {
+ %tmp = load i19* @i19_l ; <i19> [#uses=1]
+ store i19 %tmp, i19* @i19_s
+ ret void
+}
+
+define void @i20_ls() nounwind {
+ %tmp = load i20* @i20_l ; <i20> [#uses=1]
+ store i20 %tmp, i20* @i20_s
+ ret void
+}
+
+define void @i21_ls() nounwind {
+ %tmp = load i21* @i21_l ; <i21> [#uses=1]
+ store i21 %tmp, i21* @i21_s
+ ret void
+}
+
+define void @i22_ls() nounwind {
+ %tmp = load i22* @i22_l ; <i22> [#uses=1]
+ store i22 %tmp, i22* @i22_s
+ ret void
+}
+
+define void @i23_ls() nounwind {
+ %tmp = load i23* @i23_l ; <i23> [#uses=1]
+ store i23 %tmp, i23* @i23_s
+ ret void
+}
+
+define void @i24_ls() nounwind {
+ %tmp = load i24* @i24_l ; <i24> [#uses=1]
+ store i24 %tmp, i24* @i24_s
+ ret void
+}
+
+define void @i25_ls() nounwind {
+ %tmp = load i25* @i25_l ; <i25> [#uses=1]
+ store i25 %tmp, i25* @i25_s
+ ret void
+}
+
+define void @i26_ls() nounwind {
+ %tmp = load i26* @i26_l ; <i26> [#uses=1]
+ store i26 %tmp, i26* @i26_s
+ ret void
+}
+
+define void @i27_ls() nounwind {
+ %tmp = load i27* @i27_l ; <i27> [#uses=1]
+ store i27 %tmp, i27* @i27_s
+ ret void
+}
+
+define void @i28_ls() nounwind {
+ %tmp = load i28* @i28_l ; <i28> [#uses=1]
+ store i28 %tmp, i28* @i28_s
+ ret void
+}
+
+define void @i29_ls() nounwind {
+ %tmp = load i29* @i29_l ; <i29> [#uses=1]
+ store i29 %tmp, i29* @i29_s
+ ret void
+}
+
+define void @i30_ls() nounwind {
+ %tmp = load i30* @i30_l ; <i30> [#uses=1]
+ store i30 %tmp, i30* @i30_s
+ ret void
+}
+
+define void @i31_ls() nounwind {
+ %tmp = load i31* @i31_l ; <i31> [#uses=1]
+ store i31 %tmp, i31* @i31_s
+ ret void
+}
+
+define void @i32_ls() nounwind {
+ %tmp = load i32* @i32_l ; <i32> [#uses=1]
+ store i32 %tmp, i32* @i32_s
+ ret void
+}
+
+define void @i33_ls() nounwind {
+ %tmp = load i33* @i33_l ; <i33> [#uses=1]
+ store i33 %tmp, i33* @i33_s
+ ret void
+}
+
+define void @i34_ls() nounwind {
+ %tmp = load i34* @i34_l ; <i34> [#uses=1]
+ store i34 %tmp, i34* @i34_s
+ ret void
+}
+
+define void @i35_ls() nounwind {
+ %tmp = load i35* @i35_l ; <i35> [#uses=1]
+ store i35 %tmp, i35* @i35_s
+ ret void
+}
+
+define void @i36_ls() nounwind {
+ %tmp = load i36* @i36_l ; <i36> [#uses=1]
+ store i36 %tmp, i36* @i36_s
+ ret void
+}
+
+define void @i37_ls() nounwind {
+ %tmp = load i37* @i37_l ; <i37> [#uses=1]
+ store i37 %tmp, i37* @i37_s
+ ret void
+}
+
+define void @i38_ls() nounwind {
+ %tmp = load i38* @i38_l ; <i38> [#uses=1]
+ store i38 %tmp, i38* @i38_s
+ ret void
+}
+
+define void @i39_ls() nounwind {
+ %tmp = load i39* @i39_l ; <i39> [#uses=1]
+ store i39 %tmp, i39* @i39_s
+ ret void
+}
+
+define void @i40_ls() nounwind {
+ %tmp = load i40* @i40_l ; <i40> [#uses=1]
+ store i40 %tmp, i40* @i40_s
+ ret void
+}
+
+define void @i41_ls() nounwind {
+ %tmp = load i41* @i41_l ; <i41> [#uses=1]
+ store i41 %tmp, i41* @i41_s
+ ret void
+}
+
+define void @i42_ls() nounwind {
+ %tmp = load i42* @i42_l ; <i42> [#uses=1]
+ store i42 %tmp, i42* @i42_s
+ ret void
+}
+
+define void @i43_ls() nounwind {
+ %tmp = load i43* @i43_l ; <i43> [#uses=1]
+ store i43 %tmp, i43* @i43_s
+ ret void
+}
+
+define void @i44_ls() nounwind {
+ %tmp = load i44* @i44_l ; <i44> [#uses=1]
+ store i44 %tmp, i44* @i44_s
+ ret void
+}
+
+define void @i45_ls() nounwind {
+ %tmp = load i45* @i45_l ; <i45> [#uses=1]
+ store i45 %tmp, i45* @i45_s
+ ret void
+}
+
+define void @i46_ls() nounwind {
+ %tmp = load i46* @i46_l ; <i46> [#uses=1]
+ store i46 %tmp, i46* @i46_s
+ ret void
+}
+
+define void @i47_ls() nounwind {
+ %tmp = load i47* @i47_l ; <i47> [#uses=1]
+ store i47 %tmp, i47* @i47_s
+ ret void
+}
+
+define void @i48_ls() nounwind {
+ %tmp = load i48* @i48_l ; <i48> [#uses=1]
+ store i48 %tmp, i48* @i48_s
+ ret void
+}
+
+define void @i49_ls() nounwind {
+ %tmp = load i49* @i49_l ; <i49> [#uses=1]
+ store i49 %tmp, i49* @i49_s
+ ret void
+}
+
+define void @i50_ls() nounwind {
+ %tmp = load i50* @i50_l ; <i50> [#uses=1]
+ store i50 %tmp, i50* @i50_s
+ ret void
+}
+
+define void @i51_ls() nounwind {
+ %tmp = load i51* @i51_l ; <i51> [#uses=1]
+ store i51 %tmp, i51* @i51_s
+ ret void
+}
+
+define void @i52_ls() nounwind {
+ %tmp = load i52* @i52_l ; <i52> [#uses=1]
+ store i52 %tmp, i52* @i52_s
+ ret void
+}
+
+define void @i53_ls() nounwind {
+ %tmp = load i53* @i53_l ; <i53> [#uses=1]
+ store i53 %tmp, i53* @i53_s
+ ret void
+}
+
+define void @i54_ls() nounwind {
+ %tmp = load i54* @i54_l ; <i54> [#uses=1]
+ store i54 %tmp, i54* @i54_s
+ ret void
+}
+
+define void @i55_ls() nounwind {
+ %tmp = load i55* @i55_l ; <i55> [#uses=1]
+ store i55 %tmp, i55* @i55_s
+ ret void
+}
+
+define void @i56_ls() nounwind {
+ %tmp = load i56* @i56_l ; <i56> [#uses=1]
+ store i56 %tmp, i56* @i56_s
+ ret void
+}
+
+define void @i57_ls() nounwind {
+ %tmp = load i57* @i57_l ; <i57> [#uses=1]
+ store i57 %tmp, i57* @i57_s
+ ret void
+}
+
+define void @i58_ls() nounwind {
+ %tmp = load i58* @i58_l ; <i58> [#uses=1]
+ store i58 %tmp, i58* @i58_s
+ ret void
+}
+
+define void @i59_ls() nounwind {
+ %tmp = load i59* @i59_l ; <i59> [#uses=1]
+ store i59 %tmp, i59* @i59_s
+ ret void
+}
+
+define void @i60_ls() nounwind {
+ %tmp = load i60* @i60_l ; <i60> [#uses=1]
+ store i60 %tmp, i60* @i60_s
+ ret void
+}
+
+define void @i61_ls() nounwind {
+ %tmp = load i61* @i61_l ; <i61> [#uses=1]
+ store i61 %tmp, i61* @i61_s
+ ret void
+}
+
+define void @i62_ls() nounwind {
+ %tmp = load i62* @i62_l ; <i62> [#uses=1]
+ store i62 %tmp, i62* @i62_s
+ ret void
+}
+
+define void @i63_ls() nounwind {
+ %tmp = load i63* @i63_l ; <i63> [#uses=1]
+ store i63 %tmp, i63* @i63_s
+ ret void
+}
+
+define void @i64_ls() nounwind {
+ %tmp = load i64* @i64_l ; <i64> [#uses=1]
+ store i64 %tmp, i64* @i64_s
+ ret void
+}
+
+define void @i65_ls() nounwind {
+ %tmp = load i65* @i65_l ; <i65> [#uses=1]
+ store i65 %tmp, i65* @i65_s
+ ret void
+}
+
+define void @i66_ls() nounwind {
+ %tmp = load i66* @i66_l ; <i66> [#uses=1]
+ store i66 %tmp, i66* @i66_s
+ ret void
+}
+
+define void @i67_ls() nounwind {
+ %tmp = load i67* @i67_l ; <i67> [#uses=1]
+ store i67 %tmp, i67* @i67_s
+ ret void
+}
+
+define void @i68_ls() nounwind {
+ %tmp = load i68* @i68_l ; <i68> [#uses=1]
+ store i68 %tmp, i68* @i68_s
+ ret void
+}
+
+define void @i69_ls() nounwind {
+ %tmp = load i69* @i69_l ; <i69> [#uses=1]
+ store i69 %tmp, i69* @i69_s
+ ret void
+}
+
+define void @i70_ls() nounwind {
+ %tmp = load i70* @i70_l ; <i70> [#uses=1]
+ store i70 %tmp, i70* @i70_s
+ ret void
+}
+
+define void @i71_ls() nounwind {
+ %tmp = load i71* @i71_l ; <i71> [#uses=1]
+ store i71 %tmp, i71* @i71_s
+ ret void
+}
+
+define void @i72_ls() nounwind {
+ %tmp = load i72* @i72_l ; <i72> [#uses=1]
+ store i72 %tmp, i72* @i72_s
+ ret void
+}
+
+define void @i73_ls() nounwind {
+ %tmp = load i73* @i73_l ; <i73> [#uses=1]
+ store i73 %tmp, i73* @i73_s
+ ret void
+}
+
+define void @i74_ls() nounwind {
+ %tmp = load i74* @i74_l ; <i74> [#uses=1]
+ store i74 %tmp, i74* @i74_s
+ ret void
+}
+
+define void @i75_ls() nounwind {
+ %tmp = load i75* @i75_l ; <i75> [#uses=1]
+ store i75 %tmp, i75* @i75_s
+ ret void
+}
+
+define void @i76_ls() nounwind {
+ %tmp = load i76* @i76_l ; <i76> [#uses=1]
+ store i76 %tmp, i76* @i76_s
+ ret void
+}
+
+define void @i77_ls() nounwind {
+ %tmp = load i77* @i77_l ; <i77> [#uses=1]
+ store i77 %tmp, i77* @i77_s
+ ret void
+}
+
+define void @i78_ls() nounwind {
+ %tmp = load i78* @i78_l ; <i78> [#uses=1]
+ store i78 %tmp, i78* @i78_s
+ ret void
+}
+
+define void @i79_ls() nounwind {
+ %tmp = load i79* @i79_l ; <i79> [#uses=1]
+ store i79 %tmp, i79* @i79_s
+ ret void
+}
+
+define void @i80_ls() nounwind {
+ %tmp = load i80* @i80_l ; <i80> [#uses=1]
+ store i80 %tmp, i80* @i80_s
+ ret void
+}
+
+define void @i81_ls() nounwind {
+ %tmp = load i81* @i81_l ; <i81> [#uses=1]
+ store i81 %tmp, i81* @i81_s
+ ret void
+}
+
+define void @i82_ls() nounwind {
+ %tmp = load i82* @i82_l ; <i82> [#uses=1]
+ store i82 %tmp, i82* @i82_s
+ ret void
+}
+
+define void @i83_ls() nounwind {
+ %tmp = load i83* @i83_l ; <i83> [#uses=1]
+ store i83 %tmp, i83* @i83_s
+ ret void
+}
+
+define void @i84_ls() nounwind {
+ %tmp = load i84* @i84_l ; <i84> [#uses=1]
+ store i84 %tmp, i84* @i84_s
+ ret void
+}
+
+define void @i85_ls() nounwind {
+ %tmp = load i85* @i85_l ; <i85> [#uses=1]
+ store i85 %tmp, i85* @i85_s
+ ret void
+}
+
+define void @i86_ls() nounwind {
+ %tmp = load i86* @i86_l ; <i86> [#uses=1]
+ store i86 %tmp, i86* @i86_s
+ ret void
+}
+
+define void @i87_ls() nounwind {
+ %tmp = load i87* @i87_l ; <i87> [#uses=1]
+ store i87 %tmp, i87* @i87_s
+ ret void
+}
+
+define void @i88_ls() nounwind {
+ %tmp = load i88* @i88_l ; <i88> [#uses=1]
+ store i88 %tmp, i88* @i88_s
+ ret void
+}
+
+define void @i89_ls() nounwind {
+ %tmp = load i89* @i89_l ; <i89> [#uses=1]
+ store i89 %tmp, i89* @i89_s
+ ret void
+}
+
+define void @i90_ls() nounwind {
+ %tmp = load i90* @i90_l ; <i90> [#uses=1]
+ store i90 %tmp, i90* @i90_s
+ ret void
+}
+
+define void @i91_ls() nounwind {
+ %tmp = load i91* @i91_l ; <i91> [#uses=1]
+ store i91 %tmp, i91* @i91_s
+ ret void
+}
+
+define void @i92_ls() nounwind {
+ %tmp = load i92* @i92_l ; <i92> [#uses=1]
+ store i92 %tmp, i92* @i92_s
+ ret void
+}
+
+define void @i93_ls() nounwind {
+ %tmp = load i93* @i93_l ; <i93> [#uses=1]
+ store i93 %tmp, i93* @i93_s
+ ret void
+}
+
+define void @i94_ls() nounwind {
+ %tmp = load i94* @i94_l ; <i94> [#uses=1]
+ store i94 %tmp, i94* @i94_s
+ ret void
+}
+
+define void @i95_ls() nounwind {
+ %tmp = load i95* @i95_l ; <i95> [#uses=1]
+ store i95 %tmp, i95* @i95_s
+ ret void
+}
+
+define void @i96_ls() nounwind {
+ %tmp = load i96* @i96_l ; <i96> [#uses=1]
+ store i96 %tmp, i96* @i96_s
+ ret void
+}
+
+define void @i97_ls() nounwind {
+ %tmp = load i97* @i97_l ; <i97> [#uses=1]
+ store i97 %tmp, i97* @i97_s
+ ret void
+}
+
+define void @i98_ls() nounwind {
+ %tmp = load i98* @i98_l ; <i98> [#uses=1]
+ store i98 %tmp, i98* @i98_s
+ ret void
+}
+
+define void @i99_ls() nounwind {
+ %tmp = load i99* @i99_l ; <i99> [#uses=1]
+ store i99 %tmp, i99* @i99_s
+ ret void
+}
+
+define void @i100_ls() nounwind {
+ %tmp = load i100* @i100_l ; <i100> [#uses=1]
+ store i100 %tmp, i100* @i100_s
+ ret void
+}
+
+define void @i101_ls() nounwind {
+ %tmp = load i101* @i101_l ; <i101> [#uses=1]
+ store i101 %tmp, i101* @i101_s
+ ret void
+}
+
+define void @i102_ls() nounwind {
+ %tmp = load i102* @i102_l ; <i102> [#uses=1]
+ store i102 %tmp, i102* @i102_s
+ ret void
+}
+
+define void @i103_ls() nounwind {
+ %tmp = load i103* @i103_l ; <i103> [#uses=1]
+ store i103 %tmp, i103* @i103_s
+ ret void
+}
+
+define void @i104_ls() nounwind {
+ %tmp = load i104* @i104_l ; <i104> [#uses=1]
+ store i104 %tmp, i104* @i104_s
+ ret void
+}
+
+define void @i105_ls() nounwind {
+ %tmp = load i105* @i105_l ; <i105> [#uses=1]
+ store i105 %tmp, i105* @i105_s
+ ret void
+}
+
+define void @i106_ls() nounwind {
+ %tmp = load i106* @i106_l ; <i106> [#uses=1]
+ store i106 %tmp, i106* @i106_s
+ ret void
+}
+
+define void @i107_ls() nounwind {
+ %tmp = load i107* @i107_l ; <i107> [#uses=1]
+ store i107 %tmp, i107* @i107_s
+ ret void
+}
+
+define void @i108_ls() nounwind {
+ %tmp = load i108* @i108_l ; <i108> [#uses=1]
+ store i108 %tmp, i108* @i108_s
+ ret void
+}
+
+define void @i109_ls() nounwind {
+ %tmp = load i109* @i109_l ; <i109> [#uses=1]
+ store i109 %tmp, i109* @i109_s
+ ret void
+}
+
+define void @i110_ls() nounwind {
+ %tmp = load i110* @i110_l ; <i110> [#uses=1]
+ store i110 %tmp, i110* @i110_s
+ ret void
+}
+
+define void @i111_ls() nounwind {
+ %tmp = load i111* @i111_l ; <i111> [#uses=1]
+ store i111 %tmp, i111* @i111_s
+ ret void
+}
+
+define void @i112_ls() nounwind {
+ %tmp = load i112* @i112_l ; <i112> [#uses=1]
+ store i112 %tmp, i112* @i112_s
+ ret void
+}
+
+define void @i113_ls() nounwind {
+ %tmp = load i113* @i113_l ; <i113> [#uses=1]
+ store i113 %tmp, i113* @i113_s
+ ret void
+}
+
+define void @i114_ls() nounwind {
+ %tmp = load i114* @i114_l ; <i114> [#uses=1]
+ store i114 %tmp, i114* @i114_s
+ ret void
+}
+
+define void @i115_ls() nounwind {
+ %tmp = load i115* @i115_l ; <i115> [#uses=1]
+ store i115 %tmp, i115* @i115_s
+ ret void
+}
+
+define void @i116_ls() nounwind {
+ %tmp = load i116* @i116_l ; <i116> [#uses=1]
+ store i116 %tmp, i116* @i116_s
+ ret void
+}
+
+define void @i117_ls() nounwind {
+ %tmp = load i117* @i117_l ; <i117> [#uses=1]
+ store i117 %tmp, i117* @i117_s
+ ret void
+}
+
+define void @i118_ls() nounwind {
+ %tmp = load i118* @i118_l ; <i118> [#uses=1]
+ store i118 %tmp, i118* @i118_s
+ ret void
+}
+
+define void @i119_ls() nounwind {
+ %tmp = load i119* @i119_l ; <i119> [#uses=1]
+ store i119 %tmp, i119* @i119_s
+ ret void
+}
+
+define void @i120_ls() nounwind {
+ %tmp = load i120* @i120_l ; <i120> [#uses=1]
+ store i120 %tmp, i120* @i120_s
+ ret void
+}
+
+define void @i121_ls() nounwind {
+ %tmp = load i121* @i121_l ; <i121> [#uses=1]
+ store i121 %tmp, i121* @i121_s
+ ret void
+}
+
+define void @i122_ls() nounwind {
+ %tmp = load i122* @i122_l ; <i122> [#uses=1]
+ store i122 %tmp, i122* @i122_s
+ ret void
+}
+
+define void @i123_ls() nounwind {
+ %tmp = load i123* @i123_l ; <i123> [#uses=1]
+ store i123 %tmp, i123* @i123_s
+ ret void
+}
+
+define void @i124_ls() nounwind {
+ %tmp = load i124* @i124_l ; <i124> [#uses=1]
+ store i124 %tmp, i124* @i124_s
+ ret void
+}
+
+define void @i125_ls() nounwind {
+ %tmp = load i125* @i125_l ; <i125> [#uses=1]
+ store i125 %tmp, i125* @i125_s
+ ret void
+}
+
+define void @i126_ls() nounwind {
+ %tmp = load i126* @i126_l ; <i126> [#uses=1]
+ store i126 %tmp, i126* @i126_s
+ ret void
+}
+
+define void @i127_ls() nounwind {
+ %tmp = load i127* @i127_l ; <i127> [#uses=1]
+ store i127 %tmp, i127* @i127_s
+ ret void
+}
+
+define void @i128_ls() nounwind {
+ %tmp = load i128* @i128_l ; <i128> [#uses=1]
+ store i128 %tmp, i128* @i128_s
+ ret void
+}
+
+define void @i129_ls() nounwind {
+ %tmp = load i129* @i129_l ; <i129> [#uses=1]
+ store i129 %tmp, i129* @i129_s
+ ret void
+}
+
+define void @i130_ls() nounwind {
+ %tmp = load i130* @i130_l ; <i130> [#uses=1]
+ store i130 %tmp, i130* @i130_s
+ ret void
+}
+
+define void @i131_ls() nounwind {
+ %tmp = load i131* @i131_l ; <i131> [#uses=1]
+ store i131 %tmp, i131* @i131_s
+ ret void
+}
+
+define void @i132_ls() nounwind {
+ %tmp = load i132* @i132_l ; <i132> [#uses=1]
+ store i132 %tmp, i132* @i132_s
+ ret void
+}
+
+define void @i133_ls() nounwind {
+ %tmp = load i133* @i133_l ; <i133> [#uses=1]
+ store i133 %tmp, i133* @i133_s
+ ret void
+}
+
+define void @i134_ls() nounwind {
+ %tmp = load i134* @i134_l ; <i134> [#uses=1]
+ store i134 %tmp, i134* @i134_s
+ ret void
+}
+
+define void @i135_ls() nounwind {
+ %tmp = load i135* @i135_l ; <i135> [#uses=1]
+ store i135 %tmp, i135* @i135_s
+ ret void
+}
+
+define void @i136_ls() nounwind {
+ %tmp = load i136* @i136_l ; <i136> [#uses=1]
+ store i136 %tmp, i136* @i136_s
+ ret void
+}
+
+define void @i137_ls() nounwind {
+ %tmp = load i137* @i137_l ; <i137> [#uses=1]
+ store i137 %tmp, i137* @i137_s
+ ret void
+}
+
+define void @i138_ls() nounwind {
+ %tmp = load i138* @i138_l ; <i138> [#uses=1]
+ store i138 %tmp, i138* @i138_s
+ ret void
+}
+
+define void @i139_ls() nounwind {
+ %tmp = load i139* @i139_l ; <i139> [#uses=1]
+ store i139 %tmp, i139* @i139_s
+ ret void
+}
+
+define void @i140_ls() nounwind {
+ %tmp = load i140* @i140_l ; <i140> [#uses=1]
+ store i140 %tmp, i140* @i140_s
+ ret void
+}
+
+define void @i141_ls() nounwind {
+ %tmp = load i141* @i141_l ; <i141> [#uses=1]
+ store i141 %tmp, i141* @i141_s
+ ret void
+}
+
+define void @i142_ls() nounwind {
+ %tmp = load i142* @i142_l ; <i142> [#uses=1]
+ store i142 %tmp, i142* @i142_s
+ ret void
+}
+
+define void @i143_ls() nounwind {
+ %tmp = load i143* @i143_l ; <i143> [#uses=1]
+ store i143 %tmp, i143* @i143_s
+ ret void
+}
+
+define void @i144_ls() nounwind {
+ %tmp = load i144* @i144_l ; <i144> [#uses=1]
+ store i144 %tmp, i144* @i144_s
+ ret void
+}
+
+define void @i145_ls() nounwind {
+ %tmp = load i145* @i145_l ; <i145> [#uses=1]
+ store i145 %tmp, i145* @i145_s
+ ret void
+}
+
+define void @i146_ls() nounwind {
+ %tmp = load i146* @i146_l ; <i146> [#uses=1]
+ store i146 %tmp, i146* @i146_s
+ ret void
+}
+
+define void @i147_ls() nounwind {
+ %tmp = load i147* @i147_l ; <i147> [#uses=1]
+ store i147 %tmp, i147* @i147_s
+ ret void
+}
+
+define void @i148_ls() nounwind {
+ %tmp = load i148* @i148_l ; <i148> [#uses=1]
+ store i148 %tmp, i148* @i148_s
+ ret void
+}
+
+define void @i149_ls() nounwind {
+ %tmp = load i149* @i149_l ; <i149> [#uses=1]
+ store i149 %tmp, i149* @i149_s
+ ret void
+}
+
+define void @i150_ls() nounwind {
+ %tmp = load i150* @i150_l ; <i150> [#uses=1]
+ store i150 %tmp, i150* @i150_s
+ ret void
+}
+
+define void @i151_ls() nounwind {
+ %tmp = load i151* @i151_l ; <i151> [#uses=1]
+ store i151 %tmp, i151* @i151_s
+ ret void
+}
+
+define void @i152_ls() nounwind {
+ %tmp = load i152* @i152_l ; <i152> [#uses=1]
+ store i152 %tmp, i152* @i152_s
+ ret void
+}
+
+define void @i153_ls() nounwind {
+ %tmp = load i153* @i153_l ; <i153> [#uses=1]
+ store i153 %tmp, i153* @i153_s
+ ret void
+}
+
+define void @i154_ls() nounwind {
+ %tmp = load i154* @i154_l ; <i154> [#uses=1]
+ store i154 %tmp, i154* @i154_s
+ ret void
+}
+
+define void @i155_ls() nounwind {
+ %tmp = load i155* @i155_l ; <i155> [#uses=1]
+ store i155 %tmp, i155* @i155_s
+ ret void
+}
+
+define void @i156_ls() nounwind {
+ %tmp = load i156* @i156_l ; <i156> [#uses=1]
+ store i156 %tmp, i156* @i156_s
+ ret void
+}
+
+define void @i157_ls() nounwind {
+ %tmp = load i157* @i157_l ; <i157> [#uses=1]
+ store i157 %tmp, i157* @i157_s
+ ret void
+}
+
+define void @i158_ls() nounwind {
+ %tmp = load i158* @i158_l ; <i158> [#uses=1]
+ store i158 %tmp, i158* @i158_s
+ ret void
+}
+
+define void @i159_ls() nounwind {
+ %tmp = load i159* @i159_l ; <i159> [#uses=1]
+ store i159 %tmp, i159* @i159_s
+ ret void
+}
+
+define void @i160_ls() nounwind {
+ %tmp = load i160* @i160_l ; <i160> [#uses=1]
+ store i160 %tmp, i160* @i160_s
+ ret void
+}
+
+define void @i161_ls() nounwind {
+ %tmp = load i161* @i161_l ; <i161> [#uses=1]
+ store i161 %tmp, i161* @i161_s
+ ret void
+}
+
+define void @i162_ls() nounwind {
+ %tmp = load i162* @i162_l ; <i162> [#uses=1]
+ store i162 %tmp, i162* @i162_s
+ ret void
+}
+
+define void @i163_ls() nounwind {
+ %tmp = load i163* @i163_l ; <i163> [#uses=1]
+ store i163 %tmp, i163* @i163_s
+ ret void
+}
+
+define void @i164_ls() nounwind {
+ %tmp = load i164* @i164_l ; <i164> [#uses=1]
+ store i164 %tmp, i164* @i164_s
+ ret void
+}
+
+define void @i165_ls() nounwind {
+ %tmp = load i165* @i165_l ; <i165> [#uses=1]
+ store i165 %tmp, i165* @i165_s
+ ret void
+}
+
+define void @i166_ls() nounwind {
+ %tmp = load i166* @i166_l ; <i166> [#uses=1]
+ store i166 %tmp, i166* @i166_s
+ ret void
+}
+
+define void @i167_ls() nounwind {
+ %tmp = load i167* @i167_l ; <i167> [#uses=1]
+ store i167 %tmp, i167* @i167_s
+ ret void
+}
+
+define void @i168_ls() nounwind {
+ %tmp = load i168* @i168_l ; <i168> [#uses=1]
+ store i168 %tmp, i168* @i168_s
+ ret void
+}
+
+define void @i169_ls() nounwind {
+ %tmp = load i169* @i169_l ; <i169> [#uses=1]
+ store i169 %tmp, i169* @i169_s
+ ret void
+}
+
+define void @i170_ls() nounwind {
+ %tmp = load i170* @i170_l ; <i170> [#uses=1]
+ store i170 %tmp, i170* @i170_s
+ ret void
+}
+
+define void @i171_ls() nounwind {
+ %tmp = load i171* @i171_l ; <i171> [#uses=1]
+ store i171 %tmp, i171* @i171_s
+ ret void
+}
+
+define void @i172_ls() nounwind {
+ %tmp = load i172* @i172_l ; <i172> [#uses=1]
+ store i172 %tmp, i172* @i172_s
+ ret void
+}
+
+define void @i173_ls() nounwind {
+ %tmp = load i173* @i173_l ; <i173> [#uses=1]
+ store i173 %tmp, i173* @i173_s
+ ret void
+}
+
+define void @i174_ls() nounwind {
+ %tmp = load i174* @i174_l ; <i174> [#uses=1]
+ store i174 %tmp, i174* @i174_s
+ ret void
+}
+
+define void @i175_ls() nounwind {
+ %tmp = load i175* @i175_l ; <i175> [#uses=1]
+ store i175 %tmp, i175* @i175_s
+ ret void
+}
+
+define void @i176_ls() nounwind {
+ %tmp = load i176* @i176_l ; <i176> [#uses=1]
+ store i176 %tmp, i176* @i176_s
+ ret void
+}
+
+define void @i177_ls() nounwind {
+ %tmp = load i177* @i177_l ; <i177> [#uses=1]
+ store i177 %tmp, i177* @i177_s
+ ret void
+}
+
+define void @i178_ls() nounwind {
+ %tmp = load i178* @i178_l ; <i178> [#uses=1]
+ store i178 %tmp, i178* @i178_s
+ ret void
+}
+
+define void @i179_ls() nounwind {
+ %tmp = load i179* @i179_l ; <i179> [#uses=1]
+ store i179 %tmp, i179* @i179_s
+ ret void
+}
+
+define void @i180_ls() nounwind {
+ %tmp = load i180* @i180_l ; <i180> [#uses=1]
+ store i180 %tmp, i180* @i180_s
+ ret void
+}
+
+define void @i181_ls() nounwind {
+ %tmp = load i181* @i181_l ; <i181> [#uses=1]
+ store i181 %tmp, i181* @i181_s
+ ret void
+}
+
+define void @i182_ls() nounwind {
+ %tmp = load i182* @i182_l ; <i182> [#uses=1]
+ store i182 %tmp, i182* @i182_s
+ ret void
+}
+
+define void @i183_ls() nounwind {
+ %tmp = load i183* @i183_l ; <i183> [#uses=1]
+ store i183 %tmp, i183* @i183_s
+ ret void
+}
+
+define void @i184_ls() nounwind {
+ %tmp = load i184* @i184_l ; <i184> [#uses=1]
+ store i184 %tmp, i184* @i184_s
+ ret void
+}
+
+define void @i185_ls() nounwind {
+ %tmp = load i185* @i185_l ; <i185> [#uses=1]
+ store i185 %tmp, i185* @i185_s
+ ret void
+}
+
+define void @i186_ls() nounwind {
+ %tmp = load i186* @i186_l ; <i186> [#uses=1]
+ store i186 %tmp, i186* @i186_s
+ ret void
+}
+
+define void @i187_ls() nounwind {
+ %tmp = load i187* @i187_l ; <i187> [#uses=1]
+ store i187 %tmp, i187* @i187_s
+ ret void
+}
+
+define void @i188_ls() nounwind {
+ %tmp = load i188* @i188_l ; <i188> [#uses=1]
+ store i188 %tmp, i188* @i188_s
+ ret void
+}
+
+define void @i189_ls() nounwind {
+ %tmp = load i189* @i189_l ; <i189> [#uses=1]
+ store i189 %tmp, i189* @i189_s
+ ret void
+}
+
+define void @i190_ls() nounwind {
+ %tmp = load i190* @i190_l ; <i190> [#uses=1]
+ store i190 %tmp, i190* @i190_s
+ ret void
+}
+
+define void @i191_ls() nounwind {
+ %tmp = load i191* @i191_l ; <i191> [#uses=1]
+ store i191 %tmp, i191* @i191_s
+ ret void
+}
+
+define void @i192_ls() nounwind {
+ %tmp = load i192* @i192_l ; <i192> [#uses=1]
+ store i192 %tmp, i192* @i192_s
+ ret void
+}
+
+define void @i193_ls() nounwind {
+ %tmp = load i193* @i193_l ; <i193> [#uses=1]
+ store i193 %tmp, i193* @i193_s
+ ret void
+}
+
+define void @i194_ls() nounwind {
+ %tmp = load i194* @i194_l ; <i194> [#uses=1]
+ store i194 %tmp, i194* @i194_s
+ ret void
+}
+
+define void @i195_ls() nounwind {
+ %tmp = load i195* @i195_l ; <i195> [#uses=1]
+ store i195 %tmp, i195* @i195_s
+ ret void
+}
+
+define void @i196_ls() nounwind {
+ %tmp = load i196* @i196_l ; <i196> [#uses=1]
+ store i196 %tmp, i196* @i196_s
+ ret void
+}
+
+define void @i197_ls() nounwind {
+ %tmp = load i197* @i197_l ; <i197> [#uses=1]
+ store i197 %tmp, i197* @i197_s
+ ret void
+}
+
+define void @i198_ls() nounwind {
+ %tmp = load i198* @i198_l ; <i198> [#uses=1]
+ store i198 %tmp, i198* @i198_s
+ ret void
+}
+
+define void @i199_ls() nounwind {
+ %tmp = load i199* @i199_l ; <i199> [#uses=1]
+ store i199 %tmp, i199* @i199_s
+ ret void
+}
+
+define void @i200_ls() nounwind {
+ %tmp = load i200* @i200_l ; <i200> [#uses=1]
+ store i200 %tmp, i200* @i200_s
+ ret void
+}
+
+define void @i201_ls() nounwind {
+ %tmp = load i201* @i201_l ; <i201> [#uses=1]
+ store i201 %tmp, i201* @i201_s
+ ret void
+}
+
+define void @i202_ls() nounwind {
+ %tmp = load i202* @i202_l ; <i202> [#uses=1]
+ store i202 %tmp, i202* @i202_s
+ ret void
+}
+
+define void @i203_ls() nounwind {
+ %tmp = load i203* @i203_l ; <i203> [#uses=1]
+ store i203 %tmp, i203* @i203_s
+ ret void
+}
+
+define void @i204_ls() nounwind {
+ %tmp = load i204* @i204_l ; <i204> [#uses=1]
+ store i204 %tmp, i204* @i204_s
+ ret void
+}
+
+define void @i205_ls() nounwind {
+ %tmp = load i205* @i205_l ; <i205> [#uses=1]
+ store i205 %tmp, i205* @i205_s
+ ret void
+}
+
+define void @i206_ls() nounwind {
+ %tmp = load i206* @i206_l ; <i206> [#uses=1]
+ store i206 %tmp, i206* @i206_s
+ ret void
+}
+
+define void @i207_ls() nounwind {
+ %tmp = load i207* @i207_l ; <i207> [#uses=1]
+ store i207 %tmp, i207* @i207_s
+ ret void
+}
+
+define void @i208_ls() nounwind {
+ %tmp = load i208* @i208_l ; <i208> [#uses=1]
+ store i208 %tmp, i208* @i208_s
+ ret void
+}
+
+define void @i209_ls() nounwind {
+ %tmp = load i209* @i209_l ; <i209> [#uses=1]
+ store i209 %tmp, i209* @i209_s
+ ret void
+}
+
+define void @i210_ls() nounwind {
+ %tmp = load i210* @i210_l ; <i210> [#uses=1]
+ store i210 %tmp, i210* @i210_s
+ ret void
+}
+
+define void @i211_ls() nounwind {
+ %tmp = load i211* @i211_l ; <i211> [#uses=1]
+ store i211 %tmp, i211* @i211_s
+ ret void
+}
+
+define void @i212_ls() nounwind {
+ %tmp = load i212* @i212_l ; <i212> [#uses=1]
+ store i212 %tmp, i212* @i212_s
+ ret void
+}
+
+define void @i213_ls() nounwind {
+ %tmp = load i213* @i213_l ; <i213> [#uses=1]
+ store i213 %tmp, i213* @i213_s
+ ret void
+}
+
+define void @i214_ls() nounwind {
+ %tmp = load i214* @i214_l ; <i214> [#uses=1]
+ store i214 %tmp, i214* @i214_s
+ ret void
+}
+
+define void @i215_ls() nounwind {
+ %tmp = load i215* @i215_l ; <i215> [#uses=1]
+ store i215 %tmp, i215* @i215_s
+ ret void
+}
+
+define void @i216_ls() nounwind {
+ %tmp = load i216* @i216_l ; <i216> [#uses=1]
+ store i216 %tmp, i216* @i216_s
+ ret void
+}
+
+define void @i217_ls() nounwind {
+ %tmp = load i217* @i217_l ; <i217> [#uses=1]
+ store i217 %tmp, i217* @i217_s
+ ret void
+}
+
+define void @i218_ls() nounwind {
+ %tmp = load i218* @i218_l ; <i218> [#uses=1]
+ store i218 %tmp, i218* @i218_s
+ ret void
+}
+
+define void @i219_ls() nounwind {
+ %tmp = load i219* @i219_l ; <i219> [#uses=1]
+ store i219 %tmp, i219* @i219_s
+ ret void
+}
+
+define void @i220_ls() nounwind {
+ %tmp = load i220* @i220_l ; <i220> [#uses=1]
+ store i220 %tmp, i220* @i220_s
+ ret void
+}
+
+define void @i221_ls() nounwind {
+ %tmp = load i221* @i221_l ; <i221> [#uses=1]
+ store i221 %tmp, i221* @i221_s
+ ret void
+}
+
+define void @i222_ls() nounwind {
+ %tmp = load i222* @i222_l ; <i222> [#uses=1]
+ store i222 %tmp, i222* @i222_s
+ ret void
+}
+
+define void @i223_ls() nounwind {
+ %tmp = load i223* @i223_l ; <i223> [#uses=1]
+ store i223 %tmp, i223* @i223_s
+ ret void
+}
+
+define void @i224_ls() nounwind {
+ %tmp = load i224* @i224_l ; <i224> [#uses=1]
+ store i224 %tmp, i224* @i224_s
+ ret void
+}
+
+define void @i225_ls() nounwind {
+ %tmp = load i225* @i225_l ; <i225> [#uses=1]
+ store i225 %tmp, i225* @i225_s
+ ret void
+}
+
+define void @i226_ls() nounwind {
+ %tmp = load i226* @i226_l ; <i226> [#uses=1]
+ store i226 %tmp, i226* @i226_s
+ ret void
+}
+
+define void @i227_ls() nounwind {
+ %tmp = load i227* @i227_l ; <i227> [#uses=1]
+ store i227 %tmp, i227* @i227_s
+ ret void
+}
+
+define void @i228_ls() nounwind {
+ %tmp = load i228* @i228_l ; <i228> [#uses=1]
+ store i228 %tmp, i228* @i228_s
+ ret void
+}
+
+define void @i229_ls() nounwind {
+ %tmp = load i229* @i229_l ; <i229> [#uses=1]
+ store i229 %tmp, i229* @i229_s
+ ret void
+}
+
+define void @i230_ls() nounwind {
+ %tmp = load i230* @i230_l ; <i230> [#uses=1]
+ store i230 %tmp, i230* @i230_s
+ ret void
+}
+
+define void @i231_ls() nounwind {
+ %tmp = load i231* @i231_l ; <i231> [#uses=1]
+ store i231 %tmp, i231* @i231_s
+ ret void
+}
+
+define void @i232_ls() nounwind {
+ %tmp = load i232* @i232_l ; <i232> [#uses=1]
+ store i232 %tmp, i232* @i232_s
+ ret void
+}
+
+define void @i233_ls() nounwind {
+ %tmp = load i233* @i233_l ; <i233> [#uses=1]
+ store i233 %tmp, i233* @i233_s
+ ret void
+}
+
+define void @i234_ls() nounwind {
+ %tmp = load i234* @i234_l ; <i234> [#uses=1]
+ store i234 %tmp, i234* @i234_s
+ ret void
+}
+
+define void @i235_ls() nounwind {
+ %tmp = load i235* @i235_l ; <i235> [#uses=1]
+ store i235 %tmp, i235* @i235_s
+ ret void
+}
+
+define void @i236_ls() nounwind {
+ %tmp = load i236* @i236_l ; <i236> [#uses=1]
+ store i236 %tmp, i236* @i236_s
+ ret void
+}
+
+define void @i237_ls() nounwind {
+ %tmp = load i237* @i237_l ; <i237> [#uses=1]
+ store i237 %tmp, i237* @i237_s
+ ret void
+}
+
+define void @i238_ls() nounwind {
+ %tmp = load i238* @i238_l ; <i238> [#uses=1]
+ store i238 %tmp, i238* @i238_s
+ ret void
+}
+
+define void @i239_ls() nounwind {
+ %tmp = load i239* @i239_l ; <i239> [#uses=1]
+ store i239 %tmp, i239* @i239_s
+ ret void
+}
+
+define void @i240_ls() nounwind {
+ %tmp = load i240* @i240_l ; <i240> [#uses=1]
+ store i240 %tmp, i240* @i240_s
+ ret void
+}
+
+define void @i241_ls() nounwind {
+ %tmp = load i241* @i241_l ; <i241> [#uses=1]
+ store i241 %tmp, i241* @i241_s
+ ret void
+}
+
+define void @i242_ls() nounwind {
+ %tmp = load i242* @i242_l ; <i242> [#uses=1]
+ store i242 %tmp, i242* @i242_s
+ ret void
+}
+
+define void @i243_ls() nounwind {
+ %tmp = load i243* @i243_l ; <i243> [#uses=1]
+ store i243 %tmp, i243* @i243_s
+ ret void
+}
+
+define void @i244_ls() nounwind {
+ %tmp = load i244* @i244_l ; <i244> [#uses=1]
+ store i244 %tmp, i244* @i244_s
+ ret void
+}
+
+define void @i245_ls() nounwind {
+ %tmp = load i245* @i245_l ; <i245> [#uses=1]
+ store i245 %tmp, i245* @i245_s
+ ret void
+}
+
+define void @i246_ls() nounwind {
+ %tmp = load i246* @i246_l ; <i246> [#uses=1]
+ store i246 %tmp, i246* @i246_s
+ ret void
+}
+
+define void @i247_ls() nounwind {
+ %tmp = load i247* @i247_l ; <i247> [#uses=1]
+ store i247 %tmp, i247* @i247_s
+ ret void
+}
+
+define void @i248_ls() nounwind {
+ %tmp = load i248* @i248_l ; <i248> [#uses=1]
+ store i248 %tmp, i248* @i248_s
+ ret void
+}
+
+define void @i249_ls() nounwind {
+ %tmp = load i249* @i249_l ; <i249> [#uses=1]
+ store i249 %tmp, i249* @i249_s
+ ret void
+}
+
+define void @i250_ls() nounwind {
+ %tmp = load i250* @i250_l ; <i250> [#uses=1]
+ store i250 %tmp, i250* @i250_s
+ ret void
+}
+
+define void @i251_ls() nounwind {
+ %tmp = load i251* @i251_l ; <i251> [#uses=1]
+ store i251 %tmp, i251* @i251_s
+ ret void
+}
+
+define void @i252_ls() nounwind {
+ %tmp = load i252* @i252_l ; <i252> [#uses=1]
+ store i252 %tmp, i252* @i252_s
+ ret void
+}
+
+define void @i253_ls() nounwind {
+ %tmp = load i253* @i253_l ; <i253> [#uses=1]
+ store i253 %tmp, i253* @i253_s
+ ret void
+}
+
+define void @i254_ls() nounwind {
+ %tmp = load i254* @i254_l ; <i254> [#uses=1]
+ store i254 %tmp, i254* @i254_s
+ ret void
+}
+
+define void @i255_ls() nounwind {
+ %tmp = load i255* @i255_l ; <i255> [#uses=1]
+ store i255 %tmp, i255* @i255_s
+ ret void
+}
+
+define void @i256_ls() nounwind {
+ %tmp = load i256* @i256_l ; <i256> [#uses=1]
+ store i256 %tmp, i256* @i256_s
+ ret void
+}
diff --git a/test/CodeGen/Generic/APIntParam.ll b/test/CodeGen/Generic/APIntParam.ll
new file mode 100644
index 0000000..8aa0b49
--- /dev/null
+++ b/test/CodeGen/Generic/APIntParam.ll
@@ -0,0 +1,1537 @@
+; RUN: llc < %s > %t
+@i1_s = external global i1 ; <i1*> [#uses=1]
+@i2_s = external global i2 ; <i2*> [#uses=1]
+@i3_s = external global i3 ; <i3*> [#uses=1]
+@i4_s = external global i4 ; <i4*> [#uses=1]
+@i5_s = external global i5 ; <i5*> [#uses=1]
+@i6_s = external global i6 ; <i6*> [#uses=1]
+@i7_s = external global i7 ; <i7*> [#uses=1]
+@i8_s = external global i8 ; <i8*> [#uses=1]
+@i9_s = external global i9 ; <i9*> [#uses=1]
+@i10_s = external global i10 ; <i10*> [#uses=1]
+@i11_s = external global i11 ; <i11*> [#uses=1]
+@i12_s = external global i12 ; <i12*> [#uses=1]
+@i13_s = external global i13 ; <i13*> [#uses=1]
+@i14_s = external global i14 ; <i14*> [#uses=1]
+@i15_s = external global i15 ; <i15*> [#uses=1]
+@i16_s = external global i16 ; <i16*> [#uses=1]
+@i17_s = external global i17 ; <i17*> [#uses=1]
+@i18_s = external global i18 ; <i18*> [#uses=1]
+@i19_s = external global i19 ; <i19*> [#uses=1]
+@i20_s = external global i20 ; <i20*> [#uses=1]
+@i21_s = external global i21 ; <i21*> [#uses=1]
+@i22_s = external global i22 ; <i22*> [#uses=1]
+@i23_s = external global i23 ; <i23*> [#uses=1]
+@i24_s = external global i24 ; <i24*> [#uses=1]
+@i25_s = external global i25 ; <i25*> [#uses=1]
+@i26_s = external global i26 ; <i26*> [#uses=1]
+@i27_s = external global i27 ; <i27*> [#uses=1]
+@i28_s = external global i28 ; <i28*> [#uses=1]
+@i29_s = external global i29 ; <i29*> [#uses=1]
+@i30_s = external global i30 ; <i30*> [#uses=1]
+@i31_s = external global i31 ; <i31*> [#uses=1]
+@i32_s = external global i32 ; <i32*> [#uses=1]
+@i33_s = external global i33 ; <i33*> [#uses=1]
+@i34_s = external global i34 ; <i34*> [#uses=1]
+@i35_s = external global i35 ; <i35*> [#uses=1]
+@i36_s = external global i36 ; <i36*> [#uses=1]
+@i37_s = external global i37 ; <i37*> [#uses=1]
+@i38_s = external global i38 ; <i38*> [#uses=1]
+@i39_s = external global i39 ; <i39*> [#uses=1]
+@i40_s = external global i40 ; <i40*> [#uses=1]
+@i41_s = external global i41 ; <i41*> [#uses=1]
+@i42_s = external global i42 ; <i42*> [#uses=1]
+@i43_s = external global i43 ; <i43*> [#uses=1]
+@i44_s = external global i44 ; <i44*> [#uses=1]
+@i45_s = external global i45 ; <i45*> [#uses=1]
+@i46_s = external global i46 ; <i46*> [#uses=1]
+@i47_s = external global i47 ; <i47*> [#uses=1]
+@i48_s = external global i48 ; <i48*> [#uses=1]
+@i49_s = external global i49 ; <i49*> [#uses=1]
+@i50_s = external global i50 ; <i50*> [#uses=1]
+@i51_s = external global i51 ; <i51*> [#uses=1]
+@i52_s = external global i52 ; <i52*> [#uses=1]
+@i53_s = external global i53 ; <i53*> [#uses=1]
+@i54_s = external global i54 ; <i54*> [#uses=1]
+@i55_s = external global i55 ; <i55*> [#uses=1]
+@i56_s = external global i56 ; <i56*> [#uses=1]
+@i57_s = external global i57 ; <i57*> [#uses=1]
+@i58_s = external global i58 ; <i58*> [#uses=1]
+@i59_s = external global i59 ; <i59*> [#uses=1]
+@i60_s = external global i60 ; <i60*> [#uses=1]
+@i61_s = external global i61 ; <i61*> [#uses=1]
+@i62_s = external global i62 ; <i62*> [#uses=1]
+@i63_s = external global i63 ; <i63*> [#uses=1]
+@i64_s = external global i64 ; <i64*> [#uses=1]
+@i65_s = external global i65 ; <i65*> [#uses=1]
+@i66_s = external global i66 ; <i66*> [#uses=1]
+@i67_s = external global i67 ; <i67*> [#uses=1]
+@i68_s = external global i68 ; <i68*> [#uses=1]
+@i69_s = external global i69 ; <i69*> [#uses=1]
+@i70_s = external global i70 ; <i70*> [#uses=1]
+@i71_s = external global i71 ; <i71*> [#uses=1]
+@i72_s = external global i72 ; <i72*> [#uses=1]
+@i73_s = external global i73 ; <i73*> [#uses=1]
+@i74_s = external global i74 ; <i74*> [#uses=1]
+@i75_s = external global i75 ; <i75*> [#uses=1]
+@i76_s = external global i76 ; <i76*> [#uses=1]
+@i77_s = external global i77 ; <i77*> [#uses=1]
+@i78_s = external global i78 ; <i78*> [#uses=1]
+@i79_s = external global i79 ; <i79*> [#uses=1]
+@i80_s = external global i80 ; <i80*> [#uses=1]
+@i81_s = external global i81 ; <i81*> [#uses=1]
+@i82_s = external global i82 ; <i82*> [#uses=1]
+@i83_s = external global i83 ; <i83*> [#uses=1]
+@i84_s = external global i84 ; <i84*> [#uses=1]
+@i85_s = external global i85 ; <i85*> [#uses=1]
+@i86_s = external global i86 ; <i86*> [#uses=1]
+@i87_s = external global i87 ; <i87*> [#uses=1]
+@i88_s = external global i88 ; <i88*> [#uses=1]
+@i89_s = external global i89 ; <i89*> [#uses=1]
+@i90_s = external global i90 ; <i90*> [#uses=1]
+@i91_s = external global i91 ; <i91*> [#uses=1]
+@i92_s = external global i92 ; <i92*> [#uses=1]
+@i93_s = external global i93 ; <i93*> [#uses=1]
+@i94_s = external global i94 ; <i94*> [#uses=1]
+@i95_s = external global i95 ; <i95*> [#uses=1]
+@i96_s = external global i96 ; <i96*> [#uses=1]
+@i97_s = external global i97 ; <i97*> [#uses=1]
+@i98_s = external global i98 ; <i98*> [#uses=1]
+@i99_s = external global i99 ; <i99*> [#uses=1]
+@i100_s = external global i100 ; <i100*> [#uses=1]
+@i101_s = external global i101 ; <i101*> [#uses=1]
+@i102_s = external global i102 ; <i102*> [#uses=1]
+@i103_s = external global i103 ; <i103*> [#uses=1]
+@i104_s = external global i104 ; <i104*> [#uses=1]
+@i105_s = external global i105 ; <i105*> [#uses=1]
+@i106_s = external global i106 ; <i106*> [#uses=1]
+@i107_s = external global i107 ; <i107*> [#uses=1]
+@i108_s = external global i108 ; <i108*> [#uses=1]
+@i109_s = external global i109 ; <i109*> [#uses=1]
+@i110_s = external global i110 ; <i110*> [#uses=1]
+@i111_s = external global i111 ; <i111*> [#uses=1]
+@i112_s = external global i112 ; <i112*> [#uses=1]
+@i113_s = external global i113 ; <i113*> [#uses=1]
+@i114_s = external global i114 ; <i114*> [#uses=1]
+@i115_s = external global i115 ; <i115*> [#uses=1]
+@i116_s = external global i116 ; <i116*> [#uses=1]
+@i117_s = external global i117 ; <i117*> [#uses=1]
+@i118_s = external global i118 ; <i118*> [#uses=1]
+@i119_s = external global i119 ; <i119*> [#uses=1]
+@i120_s = external global i120 ; <i120*> [#uses=1]
+@i121_s = external global i121 ; <i121*> [#uses=1]
+@i122_s = external global i122 ; <i122*> [#uses=1]
+@i123_s = external global i123 ; <i123*> [#uses=1]
+@i124_s = external global i124 ; <i124*> [#uses=1]
+@i125_s = external global i125 ; <i125*> [#uses=1]
+@i126_s = external global i126 ; <i126*> [#uses=1]
+@i127_s = external global i127 ; <i127*> [#uses=1]
+@i128_s = external global i128 ; <i128*> [#uses=1]
+@i129_s = external global i129 ; <i129*> [#uses=1]
+@i130_s = external global i130 ; <i130*> [#uses=1]
+@i131_s = external global i131 ; <i131*> [#uses=1]
+@i132_s = external global i132 ; <i132*> [#uses=1]
+@i133_s = external global i133 ; <i133*> [#uses=1]
+@i134_s = external global i134 ; <i134*> [#uses=1]
+@i135_s = external global i135 ; <i135*> [#uses=1]
+@i136_s = external global i136 ; <i136*> [#uses=1]
+@i137_s = external global i137 ; <i137*> [#uses=1]
+@i138_s = external global i138 ; <i138*> [#uses=1]
+@i139_s = external global i139 ; <i139*> [#uses=1]
+@i140_s = external global i140 ; <i140*> [#uses=1]
+@i141_s = external global i141 ; <i141*> [#uses=1]
+@i142_s = external global i142 ; <i142*> [#uses=1]
+@i143_s = external global i143 ; <i143*> [#uses=1]
+@i144_s = external global i144 ; <i144*> [#uses=1]
+@i145_s = external global i145 ; <i145*> [#uses=1]
+@i146_s = external global i146 ; <i146*> [#uses=1]
+@i147_s = external global i147 ; <i147*> [#uses=1]
+@i148_s = external global i148 ; <i148*> [#uses=1]
+@i149_s = external global i149 ; <i149*> [#uses=1]
+@i150_s = external global i150 ; <i150*> [#uses=1]
+@i151_s = external global i151 ; <i151*> [#uses=1]
+@i152_s = external global i152 ; <i152*> [#uses=1]
+@i153_s = external global i153 ; <i153*> [#uses=1]
+@i154_s = external global i154 ; <i154*> [#uses=1]
+@i155_s = external global i155 ; <i155*> [#uses=1]
+@i156_s = external global i156 ; <i156*> [#uses=1]
+@i157_s = external global i157 ; <i157*> [#uses=1]
+@i158_s = external global i158 ; <i158*> [#uses=1]
+@i159_s = external global i159 ; <i159*> [#uses=1]
+@i160_s = external global i160 ; <i160*> [#uses=1]
+@i161_s = external global i161 ; <i161*> [#uses=1]
+@i162_s = external global i162 ; <i162*> [#uses=1]
+@i163_s = external global i163 ; <i163*> [#uses=1]
+@i164_s = external global i164 ; <i164*> [#uses=1]
+@i165_s = external global i165 ; <i165*> [#uses=1]
+@i166_s = external global i166 ; <i166*> [#uses=1]
+@i167_s = external global i167 ; <i167*> [#uses=1]
+@i168_s = external global i168 ; <i168*> [#uses=1]
+@i169_s = external global i169 ; <i169*> [#uses=1]
+@i170_s = external global i170 ; <i170*> [#uses=1]
+@i171_s = external global i171 ; <i171*> [#uses=1]
+@i172_s = external global i172 ; <i172*> [#uses=1]
+@i173_s = external global i173 ; <i173*> [#uses=1]
+@i174_s = external global i174 ; <i174*> [#uses=1]
+@i175_s = external global i175 ; <i175*> [#uses=1]
+@i176_s = external global i176 ; <i176*> [#uses=1]
+@i177_s = external global i177 ; <i177*> [#uses=1]
+@i178_s = external global i178 ; <i178*> [#uses=1]
+@i179_s = external global i179 ; <i179*> [#uses=1]
+@i180_s = external global i180 ; <i180*> [#uses=1]
+@i181_s = external global i181 ; <i181*> [#uses=1]
+@i182_s = external global i182 ; <i182*> [#uses=1]
+@i183_s = external global i183 ; <i183*> [#uses=1]
+@i184_s = external global i184 ; <i184*> [#uses=1]
+@i185_s = external global i185 ; <i185*> [#uses=1]
+@i186_s = external global i186 ; <i186*> [#uses=1]
+@i187_s = external global i187 ; <i187*> [#uses=1]
+@i188_s = external global i188 ; <i188*> [#uses=1]
+@i189_s = external global i189 ; <i189*> [#uses=1]
+@i190_s = external global i190 ; <i190*> [#uses=1]
+@i191_s = external global i191 ; <i191*> [#uses=1]
+@i192_s = external global i192 ; <i192*> [#uses=1]
+@i193_s = external global i193 ; <i193*> [#uses=1]
+@i194_s = external global i194 ; <i194*> [#uses=1]
+@i195_s = external global i195 ; <i195*> [#uses=1]
+@i196_s = external global i196 ; <i196*> [#uses=1]
+@i197_s = external global i197 ; <i197*> [#uses=1]
+@i198_s = external global i198 ; <i198*> [#uses=1]
+@i199_s = external global i199 ; <i199*> [#uses=1]
+@i200_s = external global i200 ; <i200*> [#uses=1]
+@i201_s = external global i201 ; <i201*> [#uses=1]
+@i202_s = external global i202 ; <i202*> [#uses=1]
+@i203_s = external global i203 ; <i203*> [#uses=1]
+@i204_s = external global i204 ; <i204*> [#uses=1]
+@i205_s = external global i205 ; <i205*> [#uses=1]
+@i206_s = external global i206 ; <i206*> [#uses=1]
+@i207_s = external global i207 ; <i207*> [#uses=1]
+@i208_s = external global i208 ; <i208*> [#uses=1]
+@i209_s = external global i209 ; <i209*> [#uses=1]
+@i210_s = external global i210 ; <i210*> [#uses=1]
+@i211_s = external global i211 ; <i211*> [#uses=1]
+@i212_s = external global i212 ; <i212*> [#uses=1]
+@i213_s = external global i213 ; <i213*> [#uses=1]
+@i214_s = external global i214 ; <i214*> [#uses=1]
+@i215_s = external global i215 ; <i215*> [#uses=1]
+@i216_s = external global i216 ; <i216*> [#uses=1]
+@i217_s = external global i217 ; <i217*> [#uses=1]
+@i218_s = external global i218 ; <i218*> [#uses=1]
+@i219_s = external global i219 ; <i219*> [#uses=1]
+@i220_s = external global i220 ; <i220*> [#uses=1]
+@i221_s = external global i221 ; <i221*> [#uses=1]
+@i222_s = external global i222 ; <i222*> [#uses=1]
+@i223_s = external global i223 ; <i223*> [#uses=1]
+@i224_s = external global i224 ; <i224*> [#uses=1]
+@i225_s = external global i225 ; <i225*> [#uses=1]
+@i226_s = external global i226 ; <i226*> [#uses=1]
+@i227_s = external global i227 ; <i227*> [#uses=1]
+@i228_s = external global i228 ; <i228*> [#uses=1]
+@i229_s = external global i229 ; <i229*> [#uses=1]
+@i230_s = external global i230 ; <i230*> [#uses=1]
+@i231_s = external global i231 ; <i231*> [#uses=1]
+@i232_s = external global i232 ; <i232*> [#uses=1]
+@i233_s = external global i233 ; <i233*> [#uses=1]
+@i234_s = external global i234 ; <i234*> [#uses=1]
+@i235_s = external global i235 ; <i235*> [#uses=1]
+@i236_s = external global i236 ; <i236*> [#uses=1]
+@i237_s = external global i237 ; <i237*> [#uses=1]
+@i238_s = external global i238 ; <i238*> [#uses=1]
+@i239_s = external global i239 ; <i239*> [#uses=1]
+@i240_s = external global i240 ; <i240*> [#uses=1]
+@i241_s = external global i241 ; <i241*> [#uses=1]
+@i242_s = external global i242 ; <i242*> [#uses=1]
+@i243_s = external global i243 ; <i243*> [#uses=1]
+@i244_s = external global i244 ; <i244*> [#uses=1]
+@i245_s = external global i245 ; <i245*> [#uses=1]
+@i246_s = external global i246 ; <i246*> [#uses=1]
+@i247_s = external global i247 ; <i247*> [#uses=1]
+@i248_s = external global i248 ; <i248*> [#uses=1]
+@i249_s = external global i249 ; <i249*> [#uses=1]
+@i250_s = external global i250 ; <i250*> [#uses=1]
+@i251_s = external global i251 ; <i251*> [#uses=1]
+@i252_s = external global i252 ; <i252*> [#uses=1]
+@i253_s = external global i253 ; <i253*> [#uses=1]
+@i254_s = external global i254 ; <i254*> [#uses=1]
+@i255_s = external global i255 ; <i255*> [#uses=1]
+@i256_s = external global i256 ; <i256*> [#uses=1]
+
+define void @i1_ls(i1 %x) nounwind {
+ store i1 %x, i1* @i1_s
+ ret void
+}
+
+define void @i2_ls(i2 %x) nounwind {
+ store i2 %x, i2* @i2_s
+ ret void
+}
+
+define void @i3_ls(i3 %x) nounwind {
+ store i3 %x, i3* @i3_s
+ ret void
+}
+
+define void @i4_ls(i4 %x) nounwind {
+ store i4 %x, i4* @i4_s
+ ret void
+}
+
+define void @i5_ls(i5 %x) nounwind {
+ store i5 %x, i5* @i5_s
+ ret void
+}
+
+define void @i6_ls(i6 %x) nounwind {
+ store i6 %x, i6* @i6_s
+ ret void
+}
+
+define void @i7_ls(i7 %x) nounwind {
+ store i7 %x, i7* @i7_s
+ ret void
+}
+
+define void @i8_ls(i8 %x) nounwind {
+ store i8 %x, i8* @i8_s
+ ret void
+}
+
+define void @i9_ls(i9 %x) nounwind {
+ store i9 %x, i9* @i9_s
+ ret void
+}
+
+define void @i10_ls(i10 %x) nounwind {
+ store i10 %x, i10* @i10_s
+ ret void
+}
+
+define void @i11_ls(i11 %x) nounwind {
+ store i11 %x, i11* @i11_s
+ ret void
+}
+
+define void @i12_ls(i12 %x) nounwind {
+ store i12 %x, i12* @i12_s
+ ret void
+}
+
+define void @i13_ls(i13 %x) nounwind {
+ store i13 %x, i13* @i13_s
+ ret void
+}
+
+define void @i14_ls(i14 %x) nounwind {
+ store i14 %x, i14* @i14_s
+ ret void
+}
+
+define void @i15_ls(i15 %x) nounwind {
+ store i15 %x, i15* @i15_s
+ ret void
+}
+
+define void @i16_ls(i16 %x) nounwind {
+ store i16 %x, i16* @i16_s
+ ret void
+}
+
+define void @i17_ls(i17 %x) nounwind {
+ store i17 %x, i17* @i17_s
+ ret void
+}
+
+define void @i18_ls(i18 %x) nounwind {
+ store i18 %x, i18* @i18_s
+ ret void
+}
+
+define void @i19_ls(i19 %x) nounwind {
+ store i19 %x, i19* @i19_s
+ ret void
+}
+
+define void @i20_ls(i20 %x) nounwind {
+ store i20 %x, i20* @i20_s
+ ret void
+}
+
+define void @i21_ls(i21 %x) nounwind {
+ store i21 %x, i21* @i21_s
+ ret void
+}
+
+define void @i22_ls(i22 %x) nounwind {
+ store i22 %x, i22* @i22_s
+ ret void
+}
+
+define void @i23_ls(i23 %x) nounwind {
+ store i23 %x, i23* @i23_s
+ ret void
+}
+
+define void @i24_ls(i24 %x) nounwind {
+ store i24 %x, i24* @i24_s
+ ret void
+}
+
+define void @i25_ls(i25 %x) nounwind {
+ store i25 %x, i25* @i25_s
+ ret void
+}
+
+define void @i26_ls(i26 %x) nounwind {
+ store i26 %x, i26* @i26_s
+ ret void
+}
+
+define void @i27_ls(i27 %x) nounwind {
+ store i27 %x, i27* @i27_s
+ ret void
+}
+
+define void @i28_ls(i28 %x) nounwind {
+ store i28 %x, i28* @i28_s
+ ret void
+}
+
+define void @i29_ls(i29 %x) nounwind {
+ store i29 %x, i29* @i29_s
+ ret void
+}
+
+define void @i30_ls(i30 %x) nounwind {
+ store i30 %x, i30* @i30_s
+ ret void
+}
+
+define void @i31_ls(i31 %x) nounwind {
+ store i31 %x, i31* @i31_s
+ ret void
+}
+
+define void @i32_ls(i32 %x) nounwind {
+ store i32 %x, i32* @i32_s
+ ret void
+}
+
+define void @i33_ls(i33 %x) nounwind {
+ store i33 %x, i33* @i33_s
+ ret void
+}
+
+define void @i34_ls(i34 %x) nounwind {
+ store i34 %x, i34* @i34_s
+ ret void
+}
+
+define void @i35_ls(i35 %x) nounwind {
+ store i35 %x, i35* @i35_s
+ ret void
+}
+
+define void @i36_ls(i36 %x) nounwind {
+ store i36 %x, i36* @i36_s
+ ret void
+}
+
+define void @i37_ls(i37 %x) nounwind {
+ store i37 %x, i37* @i37_s
+ ret void
+}
+
+define void @i38_ls(i38 %x) nounwind {
+ store i38 %x, i38* @i38_s
+ ret void
+}
+
+define void @i39_ls(i39 %x) nounwind {
+ store i39 %x, i39* @i39_s
+ ret void
+}
+
+define void @i40_ls(i40 %x) nounwind {
+ store i40 %x, i40* @i40_s
+ ret void
+}
+
+define void @i41_ls(i41 %x) nounwind {
+ store i41 %x, i41* @i41_s
+ ret void
+}
+
+define void @i42_ls(i42 %x) nounwind {
+ store i42 %x, i42* @i42_s
+ ret void
+}
+
+define void @i43_ls(i43 %x) nounwind {
+ store i43 %x, i43* @i43_s
+ ret void
+}
+
+define void @i44_ls(i44 %x) nounwind {
+ store i44 %x, i44* @i44_s
+ ret void
+}
+
+define void @i45_ls(i45 %x) nounwind {
+ store i45 %x, i45* @i45_s
+ ret void
+}
+
+define void @i46_ls(i46 %x) nounwind {
+ store i46 %x, i46* @i46_s
+ ret void
+}
+
+define void @i47_ls(i47 %x) nounwind {
+ store i47 %x, i47* @i47_s
+ ret void
+}
+
+define void @i48_ls(i48 %x) nounwind {
+ store i48 %x, i48* @i48_s
+ ret void
+}
+
+define void @i49_ls(i49 %x) nounwind {
+ store i49 %x, i49* @i49_s
+ ret void
+}
+
+define void @i50_ls(i50 %x) nounwind {
+ store i50 %x, i50* @i50_s
+ ret void
+}
+
+define void @i51_ls(i51 %x) nounwind {
+ store i51 %x, i51* @i51_s
+ ret void
+}
+
+define void @i52_ls(i52 %x) nounwind {
+ store i52 %x, i52* @i52_s
+ ret void
+}
+
+define void @i53_ls(i53 %x) nounwind {
+ store i53 %x, i53* @i53_s
+ ret void
+}
+
+define void @i54_ls(i54 %x) nounwind {
+ store i54 %x, i54* @i54_s
+ ret void
+}
+
+define void @i55_ls(i55 %x) nounwind {
+ store i55 %x, i55* @i55_s
+ ret void
+}
+
+define void @i56_ls(i56 %x) nounwind {
+ store i56 %x, i56* @i56_s
+ ret void
+}
+
+define void @i57_ls(i57 %x) nounwind {
+ store i57 %x, i57* @i57_s
+ ret void
+}
+
+define void @i58_ls(i58 %x) nounwind {
+ store i58 %x, i58* @i58_s
+ ret void
+}
+
+define void @i59_ls(i59 %x) nounwind {
+ store i59 %x, i59* @i59_s
+ ret void
+}
+
+define void @i60_ls(i60 %x) nounwind {
+ store i60 %x, i60* @i60_s
+ ret void
+}
+
+define void @i61_ls(i61 %x) nounwind {
+ store i61 %x, i61* @i61_s
+ ret void
+}
+
+define void @i62_ls(i62 %x) nounwind {
+ store i62 %x, i62* @i62_s
+ ret void
+}
+
+define void @i63_ls(i63 %x) nounwind {
+ store i63 %x, i63* @i63_s
+ ret void
+}
+
+define void @i64_ls(i64 %x) nounwind {
+ store i64 %x, i64* @i64_s
+ ret void
+}
+
+define void @i65_ls(i65 %x) nounwind {
+ store i65 %x, i65* @i65_s
+ ret void
+}
+
+define void @i66_ls(i66 %x) nounwind {
+ store i66 %x, i66* @i66_s
+ ret void
+}
+
+define void @i67_ls(i67 %x) nounwind {
+ store i67 %x, i67* @i67_s
+ ret void
+}
+
+define void @i68_ls(i68 %x) nounwind {
+ store i68 %x, i68* @i68_s
+ ret void
+}
+
+define void @i69_ls(i69 %x) nounwind {
+ store i69 %x, i69* @i69_s
+ ret void
+}
+
+define void @i70_ls(i70 %x) nounwind {
+ store i70 %x, i70* @i70_s
+ ret void
+}
+
+define void @i71_ls(i71 %x) nounwind {
+ store i71 %x, i71* @i71_s
+ ret void
+}
+
+define void @i72_ls(i72 %x) nounwind {
+ store i72 %x, i72* @i72_s
+ ret void
+}
+
+define void @i73_ls(i73 %x) nounwind {
+ store i73 %x, i73* @i73_s
+ ret void
+}
+
+define void @i74_ls(i74 %x) nounwind {
+ store i74 %x, i74* @i74_s
+ ret void
+}
+
+define void @i75_ls(i75 %x) nounwind {
+ store i75 %x, i75* @i75_s
+ ret void
+}
+
+define void @i76_ls(i76 %x) nounwind {
+ store i76 %x, i76* @i76_s
+ ret void
+}
+
+define void @i77_ls(i77 %x) nounwind {
+ store i77 %x, i77* @i77_s
+ ret void
+}
+
+define void @i78_ls(i78 %x) nounwind {
+ store i78 %x, i78* @i78_s
+ ret void
+}
+
+define void @i79_ls(i79 %x) nounwind {
+ store i79 %x, i79* @i79_s
+ ret void
+}
+
+define void @i80_ls(i80 %x) nounwind {
+ store i80 %x, i80* @i80_s
+ ret void
+}
+
+define void @i81_ls(i81 %x) nounwind {
+ store i81 %x, i81* @i81_s
+ ret void
+}
+
+define void @i82_ls(i82 %x) nounwind {
+ store i82 %x, i82* @i82_s
+ ret void
+}
+
+define void @i83_ls(i83 %x) nounwind {
+ store i83 %x, i83* @i83_s
+ ret void
+}
+
+define void @i84_ls(i84 %x) nounwind {
+ store i84 %x, i84* @i84_s
+ ret void
+}
+
+define void @i85_ls(i85 %x) nounwind {
+ store i85 %x, i85* @i85_s
+ ret void
+}
+
+define void @i86_ls(i86 %x) nounwind {
+ store i86 %x, i86* @i86_s
+ ret void
+}
+
+define void @i87_ls(i87 %x) nounwind {
+ store i87 %x, i87* @i87_s
+ ret void
+}
+
+define void @i88_ls(i88 %x) nounwind {
+ store i88 %x, i88* @i88_s
+ ret void
+}
+
+define void @i89_ls(i89 %x) nounwind {
+ store i89 %x, i89* @i89_s
+ ret void
+}
+
+define void @i90_ls(i90 %x) nounwind {
+ store i90 %x, i90* @i90_s
+ ret void
+}
+
+define void @i91_ls(i91 %x) nounwind {
+ store i91 %x, i91* @i91_s
+ ret void
+}
+
+define void @i92_ls(i92 %x) nounwind {
+ store i92 %x, i92* @i92_s
+ ret void
+}
+
+define void @i93_ls(i93 %x) nounwind {
+ store i93 %x, i93* @i93_s
+ ret void
+}
+
+define void @i94_ls(i94 %x) nounwind {
+ store i94 %x, i94* @i94_s
+ ret void
+}
+
+define void @i95_ls(i95 %x) nounwind {
+ store i95 %x, i95* @i95_s
+ ret void
+}
+
+define void @i96_ls(i96 %x) nounwind {
+ store i96 %x, i96* @i96_s
+ ret void
+}
+
+define void @i97_ls(i97 %x) nounwind {
+ store i97 %x, i97* @i97_s
+ ret void
+}
+
+define void @i98_ls(i98 %x) nounwind {
+ store i98 %x, i98* @i98_s
+ ret void
+}
+
+define void @i99_ls(i99 %x) nounwind {
+ store i99 %x, i99* @i99_s
+ ret void
+}
+
+define void @i100_ls(i100 %x) nounwind {
+ store i100 %x, i100* @i100_s
+ ret void
+}
+
+define void @i101_ls(i101 %x) nounwind {
+ store i101 %x, i101* @i101_s
+ ret void
+}
+
+define void @i102_ls(i102 %x) nounwind {
+ store i102 %x, i102* @i102_s
+ ret void
+}
+
+define void @i103_ls(i103 %x) nounwind {
+ store i103 %x, i103* @i103_s
+ ret void
+}
+
+define void @i104_ls(i104 %x) nounwind {
+ store i104 %x, i104* @i104_s
+ ret void
+}
+
+define void @i105_ls(i105 %x) nounwind {
+ store i105 %x, i105* @i105_s
+ ret void
+}
+
+define void @i106_ls(i106 %x) nounwind {
+ store i106 %x, i106* @i106_s
+ ret void
+}
+
+define void @i107_ls(i107 %x) nounwind {
+ store i107 %x, i107* @i107_s
+ ret void
+}
+
+define void @i108_ls(i108 %x) nounwind {
+ store i108 %x, i108* @i108_s
+ ret void
+}
+
+define void @i109_ls(i109 %x) nounwind {
+ store i109 %x, i109* @i109_s
+ ret void
+}
+
+define void @i110_ls(i110 %x) nounwind {
+ store i110 %x, i110* @i110_s
+ ret void
+}
+
+define void @i111_ls(i111 %x) nounwind {
+ store i111 %x, i111* @i111_s
+ ret void
+}
+
+define void @i112_ls(i112 %x) nounwind {
+ store i112 %x, i112* @i112_s
+ ret void
+}
+
+define void @i113_ls(i113 %x) nounwind {
+ store i113 %x, i113* @i113_s
+ ret void
+}
+
+define void @i114_ls(i114 %x) nounwind {
+ store i114 %x, i114* @i114_s
+ ret void
+}
+
+define void @i115_ls(i115 %x) nounwind {
+ store i115 %x, i115* @i115_s
+ ret void
+}
+
+define void @i116_ls(i116 %x) nounwind {
+ store i116 %x, i116* @i116_s
+ ret void
+}
+
+define void @i117_ls(i117 %x) nounwind {
+ store i117 %x, i117* @i117_s
+ ret void
+}
+
+define void @i118_ls(i118 %x) nounwind {
+ store i118 %x, i118* @i118_s
+ ret void
+}
+
+define void @i119_ls(i119 %x) nounwind {
+ store i119 %x, i119* @i119_s
+ ret void
+}
+
+define void @i120_ls(i120 %x) nounwind {
+ store i120 %x, i120* @i120_s
+ ret void
+}
+
+define void @i121_ls(i121 %x) nounwind {
+ store i121 %x, i121* @i121_s
+ ret void
+}
+
+define void @i122_ls(i122 %x) nounwind {
+ store i122 %x, i122* @i122_s
+ ret void
+}
+
+define void @i123_ls(i123 %x) nounwind {
+ store i123 %x, i123* @i123_s
+ ret void
+}
+
+define void @i124_ls(i124 %x) nounwind {
+ store i124 %x, i124* @i124_s
+ ret void
+}
+
+define void @i125_ls(i125 %x) nounwind {
+ store i125 %x, i125* @i125_s
+ ret void
+}
+
+define void @i126_ls(i126 %x) nounwind {
+ store i126 %x, i126* @i126_s
+ ret void
+}
+
+define void @i127_ls(i127 %x) nounwind {
+ store i127 %x, i127* @i127_s
+ ret void
+}
+
+define void @i128_ls(i128 %x) nounwind {
+ store i128 %x, i128* @i128_s
+ ret void
+}
+
+define void @i129_ls(i129 %x) nounwind {
+ store i129 %x, i129* @i129_s
+ ret void
+}
+
+define void @i130_ls(i130 %x) nounwind {
+ store i130 %x, i130* @i130_s
+ ret void
+}
+
+define void @i131_ls(i131 %x) nounwind {
+ store i131 %x, i131* @i131_s
+ ret void
+}
+
+define void @i132_ls(i132 %x) nounwind {
+ store i132 %x, i132* @i132_s
+ ret void
+}
+
+define void @i133_ls(i133 %x) nounwind {
+ store i133 %x, i133* @i133_s
+ ret void
+}
+
+define void @i134_ls(i134 %x) nounwind {
+ store i134 %x, i134* @i134_s
+ ret void
+}
+
+define void @i135_ls(i135 %x) nounwind {
+ store i135 %x, i135* @i135_s
+ ret void
+}
+
+define void @i136_ls(i136 %x) nounwind {
+ store i136 %x, i136* @i136_s
+ ret void
+}
+
+define void @i137_ls(i137 %x) nounwind {
+ store i137 %x, i137* @i137_s
+ ret void
+}
+
+define void @i138_ls(i138 %x) nounwind {
+ store i138 %x, i138* @i138_s
+ ret void
+}
+
+define void @i139_ls(i139 %x) nounwind {
+ store i139 %x, i139* @i139_s
+ ret void
+}
+
+define void @i140_ls(i140 %x) nounwind {
+ store i140 %x, i140* @i140_s
+ ret void
+}
+
+define void @i141_ls(i141 %x) nounwind {
+ store i141 %x, i141* @i141_s
+ ret void
+}
+
+define void @i142_ls(i142 %x) nounwind {
+ store i142 %x, i142* @i142_s
+ ret void
+}
+
+define void @i143_ls(i143 %x) nounwind {
+ store i143 %x, i143* @i143_s
+ ret void
+}
+
+define void @i144_ls(i144 %x) nounwind {
+ store i144 %x, i144* @i144_s
+ ret void
+}
+
+define void @i145_ls(i145 %x) nounwind {
+ store i145 %x, i145* @i145_s
+ ret void
+}
+
+define void @i146_ls(i146 %x) nounwind {
+ store i146 %x, i146* @i146_s
+ ret void
+}
+
+define void @i147_ls(i147 %x) nounwind {
+ store i147 %x, i147* @i147_s
+ ret void
+}
+
+define void @i148_ls(i148 %x) nounwind {
+ store i148 %x, i148* @i148_s
+ ret void
+}
+
+define void @i149_ls(i149 %x) nounwind {
+ store i149 %x, i149* @i149_s
+ ret void
+}
+
+define void @i150_ls(i150 %x) nounwind {
+ store i150 %x, i150* @i150_s
+ ret void
+}
+
+define void @i151_ls(i151 %x) nounwind {
+ store i151 %x, i151* @i151_s
+ ret void
+}
+
+define void @i152_ls(i152 %x) nounwind {
+ store i152 %x, i152* @i152_s
+ ret void
+}
+
+define void @i153_ls(i153 %x) nounwind {
+ store i153 %x, i153* @i153_s
+ ret void
+}
+
+define void @i154_ls(i154 %x) nounwind {
+ store i154 %x, i154* @i154_s
+ ret void
+}
+
+define void @i155_ls(i155 %x) nounwind {
+ store i155 %x, i155* @i155_s
+ ret void
+}
+
+define void @i156_ls(i156 %x) nounwind {
+ store i156 %x, i156* @i156_s
+ ret void
+}
+
+define void @i157_ls(i157 %x) nounwind {
+ store i157 %x, i157* @i157_s
+ ret void
+}
+
+define void @i158_ls(i158 %x) nounwind {
+ store i158 %x, i158* @i158_s
+ ret void
+}
+
+define void @i159_ls(i159 %x) nounwind {
+ store i159 %x, i159* @i159_s
+ ret void
+}
+
+define void @i160_ls(i160 %x) nounwind {
+ store i160 %x, i160* @i160_s
+ ret void
+}
+
+define void @i161_ls(i161 %x) nounwind {
+ store i161 %x, i161* @i161_s
+ ret void
+}
+
+define void @i162_ls(i162 %x) nounwind {
+ store i162 %x, i162* @i162_s
+ ret void
+}
+
+define void @i163_ls(i163 %x) nounwind {
+ store i163 %x, i163* @i163_s
+ ret void
+}
+
+define void @i164_ls(i164 %x) nounwind {
+ store i164 %x, i164* @i164_s
+ ret void
+}
+
+define void @i165_ls(i165 %x) nounwind {
+ store i165 %x, i165* @i165_s
+ ret void
+}
+
+define void @i166_ls(i166 %x) nounwind {
+ store i166 %x, i166* @i166_s
+ ret void
+}
+
+define void @i167_ls(i167 %x) nounwind {
+ store i167 %x, i167* @i167_s
+ ret void
+}
+
+define void @i168_ls(i168 %x) nounwind {
+ store i168 %x, i168* @i168_s
+ ret void
+}
+
+define void @i169_ls(i169 %x) nounwind {
+ store i169 %x, i169* @i169_s
+ ret void
+}
+
+define void @i170_ls(i170 %x) nounwind {
+ store i170 %x, i170* @i170_s
+ ret void
+}
+
+define void @i171_ls(i171 %x) nounwind {
+ store i171 %x, i171* @i171_s
+ ret void
+}
+
+define void @i172_ls(i172 %x) nounwind {
+ store i172 %x, i172* @i172_s
+ ret void
+}
+
+define void @i173_ls(i173 %x) nounwind {
+ store i173 %x, i173* @i173_s
+ ret void
+}
+
+define void @i174_ls(i174 %x) nounwind {
+ store i174 %x, i174* @i174_s
+ ret void
+}
+
+define void @i175_ls(i175 %x) nounwind {
+ store i175 %x, i175* @i175_s
+ ret void
+}
+
+define void @i176_ls(i176 %x) nounwind {
+ store i176 %x, i176* @i176_s
+ ret void
+}
+
+define void @i177_ls(i177 %x) nounwind {
+ store i177 %x, i177* @i177_s
+ ret void
+}
+
+define void @i178_ls(i178 %x) nounwind {
+ store i178 %x, i178* @i178_s
+ ret void
+}
+
+define void @i179_ls(i179 %x) nounwind {
+ store i179 %x, i179* @i179_s
+ ret void
+}
+
+define void @i180_ls(i180 %x) nounwind {
+ store i180 %x, i180* @i180_s
+ ret void
+}
+
+define void @i181_ls(i181 %x) nounwind {
+ store i181 %x, i181* @i181_s
+ ret void
+}
+
+define void @i182_ls(i182 %x) nounwind {
+ store i182 %x, i182* @i182_s
+ ret void
+}
+
+define void @i183_ls(i183 %x) nounwind {
+ store i183 %x, i183* @i183_s
+ ret void
+}
+
+define void @i184_ls(i184 %x) nounwind {
+ store i184 %x, i184* @i184_s
+ ret void
+}
+
+define void @i185_ls(i185 %x) nounwind {
+ store i185 %x, i185* @i185_s
+ ret void
+}
+
+define void @i186_ls(i186 %x) nounwind {
+ store i186 %x, i186* @i186_s
+ ret void
+}
+
+define void @i187_ls(i187 %x) nounwind {
+ store i187 %x, i187* @i187_s
+ ret void
+}
+
+define void @i188_ls(i188 %x) nounwind {
+ store i188 %x, i188* @i188_s
+ ret void
+}
+
+define void @i189_ls(i189 %x) nounwind {
+ store i189 %x, i189* @i189_s
+ ret void
+}
+
+define void @i190_ls(i190 %x) nounwind {
+ store i190 %x, i190* @i190_s
+ ret void
+}
+
+define void @i191_ls(i191 %x) nounwind {
+ store i191 %x, i191* @i191_s
+ ret void
+}
+
+define void @i192_ls(i192 %x) nounwind {
+ store i192 %x, i192* @i192_s
+ ret void
+}
+
+define void @i193_ls(i193 %x) nounwind {
+ store i193 %x, i193* @i193_s
+ ret void
+}
+
+define void @i194_ls(i194 %x) nounwind {
+ store i194 %x, i194* @i194_s
+ ret void
+}
+
+define void @i195_ls(i195 %x) nounwind {
+ store i195 %x, i195* @i195_s
+ ret void
+}
+
+define void @i196_ls(i196 %x) nounwind {
+ store i196 %x, i196* @i196_s
+ ret void
+}
+
+define void @i197_ls(i197 %x) nounwind {
+ store i197 %x, i197* @i197_s
+ ret void
+}
+
+define void @i198_ls(i198 %x) nounwind {
+ store i198 %x, i198* @i198_s
+ ret void
+}
+
+define void @i199_ls(i199 %x) nounwind {
+ store i199 %x, i199* @i199_s
+ ret void
+}
+
+define void @i200_ls(i200 %x) nounwind {
+ store i200 %x, i200* @i200_s
+ ret void
+}
+
+define void @i201_ls(i201 %x) nounwind {
+ store i201 %x, i201* @i201_s
+ ret void
+}
+
+define void @i202_ls(i202 %x) nounwind {
+ store i202 %x, i202* @i202_s
+ ret void
+}
+
+define void @i203_ls(i203 %x) nounwind {
+ store i203 %x, i203* @i203_s
+ ret void
+}
+
+define void @i204_ls(i204 %x) nounwind {
+ store i204 %x, i204* @i204_s
+ ret void
+}
+
+define void @i205_ls(i205 %x) nounwind {
+ store i205 %x, i205* @i205_s
+ ret void
+}
+
+define void @i206_ls(i206 %x) nounwind {
+ store i206 %x, i206* @i206_s
+ ret void
+}
+
+define void @i207_ls(i207 %x) nounwind {
+ store i207 %x, i207* @i207_s
+ ret void
+}
+
+define void @i208_ls(i208 %x) nounwind {
+ store i208 %x, i208* @i208_s
+ ret void
+}
+
+define void @i209_ls(i209 %x) nounwind {
+ store i209 %x, i209* @i209_s
+ ret void
+}
+
+define void @i210_ls(i210 %x) nounwind {
+ store i210 %x, i210* @i210_s
+ ret void
+}
+
+define void @i211_ls(i211 %x) nounwind {
+ store i211 %x, i211* @i211_s
+ ret void
+}
+
+define void @i212_ls(i212 %x) nounwind {
+ store i212 %x, i212* @i212_s
+ ret void
+}
+
+define void @i213_ls(i213 %x) nounwind {
+ store i213 %x, i213* @i213_s
+ ret void
+}
+
+define void @i214_ls(i214 %x) nounwind {
+ store i214 %x, i214* @i214_s
+ ret void
+}
+
+define void @i215_ls(i215 %x) nounwind {
+ store i215 %x, i215* @i215_s
+ ret void
+}
+
+define void @i216_ls(i216 %x) nounwind {
+ store i216 %x, i216* @i216_s
+ ret void
+}
+
+define void @i217_ls(i217 %x) nounwind {
+ store i217 %x, i217* @i217_s
+ ret void
+}
+
+define void @i218_ls(i218 %x) nounwind {
+ store i218 %x, i218* @i218_s
+ ret void
+}
+
+define void @i219_ls(i219 %x) nounwind {
+ store i219 %x, i219* @i219_s
+ ret void
+}
+
+define void @i220_ls(i220 %x) nounwind {
+ store i220 %x, i220* @i220_s
+ ret void
+}
+
+define void @i221_ls(i221 %x) nounwind {
+ store i221 %x, i221* @i221_s
+ ret void
+}
+
+define void @i222_ls(i222 %x) nounwind {
+ store i222 %x, i222* @i222_s
+ ret void
+}
+
+define void @i223_ls(i223 %x) nounwind {
+ store i223 %x, i223* @i223_s
+ ret void
+}
+
+define void @i224_ls(i224 %x) nounwind {
+ store i224 %x, i224* @i224_s
+ ret void
+}
+
+define void @i225_ls(i225 %x) nounwind {
+ store i225 %x, i225* @i225_s
+ ret void
+}
+
+define void @i226_ls(i226 %x) nounwind {
+ store i226 %x, i226* @i226_s
+ ret void
+}
+
+define void @i227_ls(i227 %x) nounwind {
+ store i227 %x, i227* @i227_s
+ ret void
+}
+
+define void @i228_ls(i228 %x) nounwind {
+ store i228 %x, i228* @i228_s
+ ret void
+}
+
+define void @i229_ls(i229 %x) nounwind {
+ store i229 %x, i229* @i229_s
+ ret void
+}
+
+define void @i230_ls(i230 %x) nounwind {
+ store i230 %x, i230* @i230_s
+ ret void
+}
+
+define void @i231_ls(i231 %x) nounwind {
+ store i231 %x, i231* @i231_s
+ ret void
+}
+
+define void @i232_ls(i232 %x) nounwind {
+ store i232 %x, i232* @i232_s
+ ret void
+}
+
+define void @i233_ls(i233 %x) nounwind {
+ store i233 %x, i233* @i233_s
+ ret void
+}
+
+define void @i234_ls(i234 %x) nounwind {
+ store i234 %x, i234* @i234_s
+ ret void
+}
+
+define void @i235_ls(i235 %x) nounwind {
+ store i235 %x, i235* @i235_s
+ ret void
+}
+
+define void @i236_ls(i236 %x) nounwind {
+ store i236 %x, i236* @i236_s
+ ret void
+}
+
+define void @i237_ls(i237 %x) nounwind {
+ store i237 %x, i237* @i237_s
+ ret void
+}
+
+define void @i238_ls(i238 %x) nounwind {
+ store i238 %x, i238* @i238_s
+ ret void
+}
+
+define void @i239_ls(i239 %x) nounwind {
+ store i239 %x, i239* @i239_s
+ ret void
+}
+
+define void @i240_ls(i240 %x) nounwind {
+ store i240 %x, i240* @i240_s
+ ret void
+}
+
+define void @i241_ls(i241 %x) nounwind {
+ store i241 %x, i241* @i241_s
+ ret void
+}
+
+define void @i242_ls(i242 %x) nounwind {
+ store i242 %x, i242* @i242_s
+ ret void
+}
+
+define void @i243_ls(i243 %x) nounwind {
+ store i243 %x, i243* @i243_s
+ ret void
+}
+
+define void @i244_ls(i244 %x) nounwind {
+ store i244 %x, i244* @i244_s
+ ret void
+}
+
+define void @i245_ls(i245 %x) nounwind {
+ store i245 %x, i245* @i245_s
+ ret void
+}
+
+define void @i246_ls(i246 %x) nounwind {
+ store i246 %x, i246* @i246_s
+ ret void
+}
+
+define void @i247_ls(i247 %x) nounwind {
+ store i247 %x, i247* @i247_s
+ ret void
+}
+
+define void @i248_ls(i248 %x) nounwind {
+ store i248 %x, i248* @i248_s
+ ret void
+}
+
+define void @i249_ls(i249 %x) nounwind {
+ store i249 %x, i249* @i249_s
+ ret void
+}
+
+define void @i250_ls(i250 %x) nounwind {
+ store i250 %x, i250* @i250_s
+ ret void
+}
+
+define void @i251_ls(i251 %x) nounwind {
+ store i251 %x, i251* @i251_s
+ ret void
+}
+
+define void @i252_ls(i252 %x) nounwind {
+ store i252 %x, i252* @i252_s
+ ret void
+}
+
+define void @i253_ls(i253 %x) nounwind {
+ store i253 %x, i253* @i253_s
+ ret void
+}
+
+define void @i254_ls(i254 %x) nounwind {
+ store i254 %x, i254* @i254_s
+ ret void
+}
+
+define void @i255_ls(i255 %x) nounwind {
+ store i255 %x, i255* @i255_s
+ ret void
+}
+
+define void @i256_ls(i256 %x) nounwind {
+ store i256 %x, i256* @i256_s
+ ret void
+}
diff --git a/test/CodeGen/Generic/APIntSextParam.ll b/test/CodeGen/Generic/APIntSextParam.ll
new file mode 100644
index 0000000..acc0eeb
--- /dev/null
+++ b/test/CodeGen/Generic/APIntSextParam.ll
@@ -0,0 +1,1537 @@
+; RUN: llc < %s > %t
+@i1_s = external global i1 ; <i1*> [#uses=1]
+@i2_s = external global i2 ; <i2*> [#uses=1]
+@i3_s = external global i3 ; <i3*> [#uses=1]
+@i4_s = external global i4 ; <i4*> [#uses=1]
+@i5_s = external global i5 ; <i5*> [#uses=1]
+@i6_s = external global i6 ; <i6*> [#uses=1]
+@i7_s = external global i7 ; <i7*> [#uses=1]
+@i8_s = external global i8 ; <i8*> [#uses=1]
+@i9_s = external global i9 ; <i9*> [#uses=1]
+@i10_s = external global i10 ; <i10*> [#uses=1]
+@i11_s = external global i11 ; <i11*> [#uses=1]
+@i12_s = external global i12 ; <i12*> [#uses=1]
+@i13_s = external global i13 ; <i13*> [#uses=1]
+@i14_s = external global i14 ; <i14*> [#uses=1]
+@i15_s = external global i15 ; <i15*> [#uses=1]
+@i16_s = external global i16 ; <i16*> [#uses=1]
+@i17_s = external global i17 ; <i17*> [#uses=1]
+@i18_s = external global i18 ; <i18*> [#uses=1]
+@i19_s = external global i19 ; <i19*> [#uses=1]
+@i20_s = external global i20 ; <i20*> [#uses=1]
+@i21_s = external global i21 ; <i21*> [#uses=1]
+@i22_s = external global i22 ; <i22*> [#uses=1]
+@i23_s = external global i23 ; <i23*> [#uses=1]
+@i24_s = external global i24 ; <i24*> [#uses=1]
+@i25_s = external global i25 ; <i25*> [#uses=1]
+@i26_s = external global i26 ; <i26*> [#uses=1]
+@i27_s = external global i27 ; <i27*> [#uses=1]
+@i28_s = external global i28 ; <i28*> [#uses=1]
+@i29_s = external global i29 ; <i29*> [#uses=1]
+@i30_s = external global i30 ; <i30*> [#uses=1]
+@i31_s = external global i31 ; <i31*> [#uses=1]
+@i32_s = external global i32 ; <i32*> [#uses=1]
+@i33_s = external global i33 ; <i33*> [#uses=1]
+@i34_s = external global i34 ; <i34*> [#uses=1]
+@i35_s = external global i35 ; <i35*> [#uses=1]
+@i36_s = external global i36 ; <i36*> [#uses=1]
+@i37_s = external global i37 ; <i37*> [#uses=1]
+@i38_s = external global i38 ; <i38*> [#uses=1]
+@i39_s = external global i39 ; <i39*> [#uses=1]
+@i40_s = external global i40 ; <i40*> [#uses=1]
+@i41_s = external global i41 ; <i41*> [#uses=1]
+@i42_s = external global i42 ; <i42*> [#uses=1]
+@i43_s = external global i43 ; <i43*> [#uses=1]
+@i44_s = external global i44 ; <i44*> [#uses=1]
+@i45_s = external global i45 ; <i45*> [#uses=1]
+@i46_s = external global i46 ; <i46*> [#uses=1]
+@i47_s = external global i47 ; <i47*> [#uses=1]
+@i48_s = external global i48 ; <i48*> [#uses=1]
+@i49_s = external global i49 ; <i49*> [#uses=1]
+@i50_s = external global i50 ; <i50*> [#uses=1]
+@i51_s = external global i51 ; <i51*> [#uses=1]
+@i52_s = external global i52 ; <i52*> [#uses=1]
+@i53_s = external global i53 ; <i53*> [#uses=1]
+@i54_s = external global i54 ; <i54*> [#uses=1]
+@i55_s = external global i55 ; <i55*> [#uses=1]
+@i56_s = external global i56 ; <i56*> [#uses=1]
+@i57_s = external global i57 ; <i57*> [#uses=1]
+@i58_s = external global i58 ; <i58*> [#uses=1]
+@i59_s = external global i59 ; <i59*> [#uses=1]
+@i60_s = external global i60 ; <i60*> [#uses=1]
+@i61_s = external global i61 ; <i61*> [#uses=1]
+@i62_s = external global i62 ; <i62*> [#uses=1]
+@i63_s = external global i63 ; <i63*> [#uses=1]
+@i64_s = external global i64 ; <i64*> [#uses=1]
+@i65_s = external global i65 ; <i65*> [#uses=1]
+@i66_s = external global i66 ; <i66*> [#uses=1]
+@i67_s = external global i67 ; <i67*> [#uses=1]
+@i68_s = external global i68 ; <i68*> [#uses=1]
+@i69_s = external global i69 ; <i69*> [#uses=1]
+@i70_s = external global i70 ; <i70*> [#uses=1]
+@i71_s = external global i71 ; <i71*> [#uses=1]
+@i72_s = external global i72 ; <i72*> [#uses=1]
+@i73_s = external global i73 ; <i73*> [#uses=1]
+@i74_s = external global i74 ; <i74*> [#uses=1]
+@i75_s = external global i75 ; <i75*> [#uses=1]
+@i76_s = external global i76 ; <i76*> [#uses=1]
+@i77_s = external global i77 ; <i77*> [#uses=1]
+@i78_s = external global i78 ; <i78*> [#uses=1]
+@i79_s = external global i79 ; <i79*> [#uses=1]
+@i80_s = external global i80 ; <i80*> [#uses=1]
+@i81_s = external global i81 ; <i81*> [#uses=1]
+@i82_s = external global i82 ; <i82*> [#uses=1]
+@i83_s = external global i83 ; <i83*> [#uses=1]
+@i84_s = external global i84 ; <i84*> [#uses=1]
+@i85_s = external global i85 ; <i85*> [#uses=1]
+@i86_s = external global i86 ; <i86*> [#uses=1]
+@i87_s = external global i87 ; <i87*> [#uses=1]
+@i88_s = external global i88 ; <i88*> [#uses=1]
+@i89_s = external global i89 ; <i89*> [#uses=1]
+@i90_s = external global i90 ; <i90*> [#uses=1]
+@i91_s = external global i91 ; <i91*> [#uses=1]
+@i92_s = external global i92 ; <i92*> [#uses=1]
+@i93_s = external global i93 ; <i93*> [#uses=1]
+@i94_s = external global i94 ; <i94*> [#uses=1]
+@i95_s = external global i95 ; <i95*> [#uses=1]
+@i96_s = external global i96 ; <i96*> [#uses=1]
+@i97_s = external global i97 ; <i97*> [#uses=1]
+@i98_s = external global i98 ; <i98*> [#uses=1]
+@i99_s = external global i99 ; <i99*> [#uses=1]
+@i100_s = external global i100 ; <i100*> [#uses=1]
+@i101_s = external global i101 ; <i101*> [#uses=1]
+@i102_s = external global i102 ; <i102*> [#uses=1]
+@i103_s = external global i103 ; <i103*> [#uses=1]
+@i104_s = external global i104 ; <i104*> [#uses=1]
+@i105_s = external global i105 ; <i105*> [#uses=1]
+@i106_s = external global i106 ; <i106*> [#uses=1]
+@i107_s = external global i107 ; <i107*> [#uses=1]
+@i108_s = external global i108 ; <i108*> [#uses=1]
+@i109_s = external global i109 ; <i109*> [#uses=1]
+@i110_s = external global i110 ; <i110*> [#uses=1]
+@i111_s = external global i111 ; <i111*> [#uses=1]
+@i112_s = external global i112 ; <i112*> [#uses=1]
+@i113_s = external global i113 ; <i113*> [#uses=1]
+@i114_s = external global i114 ; <i114*> [#uses=1]
+@i115_s = external global i115 ; <i115*> [#uses=1]
+@i116_s = external global i116 ; <i116*> [#uses=1]
+@i117_s = external global i117 ; <i117*> [#uses=1]
+@i118_s = external global i118 ; <i118*> [#uses=1]
+@i119_s = external global i119 ; <i119*> [#uses=1]
+@i120_s = external global i120 ; <i120*> [#uses=1]
+@i121_s = external global i121 ; <i121*> [#uses=1]
+@i122_s = external global i122 ; <i122*> [#uses=1]
+@i123_s = external global i123 ; <i123*> [#uses=1]
+@i124_s = external global i124 ; <i124*> [#uses=1]
+@i125_s = external global i125 ; <i125*> [#uses=1]
+@i126_s = external global i126 ; <i126*> [#uses=1]
+@i127_s = external global i127 ; <i127*> [#uses=1]
+@i128_s = external global i128 ; <i128*> [#uses=1]
+@i129_s = external global i129 ; <i129*> [#uses=1]
+@i130_s = external global i130 ; <i130*> [#uses=1]
+@i131_s = external global i131 ; <i131*> [#uses=1]
+@i132_s = external global i132 ; <i132*> [#uses=1]
+@i133_s = external global i133 ; <i133*> [#uses=1]
+@i134_s = external global i134 ; <i134*> [#uses=1]
+@i135_s = external global i135 ; <i135*> [#uses=1]
+@i136_s = external global i136 ; <i136*> [#uses=1]
+@i137_s = external global i137 ; <i137*> [#uses=1]
+@i138_s = external global i138 ; <i138*> [#uses=1]
+@i139_s = external global i139 ; <i139*> [#uses=1]
+@i140_s = external global i140 ; <i140*> [#uses=1]
+@i141_s = external global i141 ; <i141*> [#uses=1]
+@i142_s = external global i142 ; <i142*> [#uses=1]
+@i143_s = external global i143 ; <i143*> [#uses=1]
+@i144_s = external global i144 ; <i144*> [#uses=1]
+@i145_s = external global i145 ; <i145*> [#uses=1]
+@i146_s = external global i146 ; <i146*> [#uses=1]
+@i147_s = external global i147 ; <i147*> [#uses=1]
+@i148_s = external global i148 ; <i148*> [#uses=1]
+@i149_s = external global i149 ; <i149*> [#uses=1]
+@i150_s = external global i150 ; <i150*> [#uses=1]
+@i151_s = external global i151 ; <i151*> [#uses=1]
+@i152_s = external global i152 ; <i152*> [#uses=1]
+@i153_s = external global i153 ; <i153*> [#uses=1]
+@i154_s = external global i154 ; <i154*> [#uses=1]
+@i155_s = external global i155 ; <i155*> [#uses=1]
+@i156_s = external global i156 ; <i156*> [#uses=1]
+@i157_s = external global i157 ; <i157*> [#uses=1]
+@i158_s = external global i158 ; <i158*> [#uses=1]
+@i159_s = external global i159 ; <i159*> [#uses=1]
+@i160_s = external global i160 ; <i160*> [#uses=1]
+@i161_s = external global i161 ; <i161*> [#uses=1]
+@i162_s = external global i162 ; <i162*> [#uses=1]
+@i163_s = external global i163 ; <i163*> [#uses=1]
+@i164_s = external global i164 ; <i164*> [#uses=1]
+@i165_s = external global i165 ; <i165*> [#uses=1]
+@i166_s = external global i166 ; <i166*> [#uses=1]
+@i167_s = external global i167 ; <i167*> [#uses=1]
+@i168_s = external global i168 ; <i168*> [#uses=1]
+@i169_s = external global i169 ; <i169*> [#uses=1]
+@i170_s = external global i170 ; <i170*> [#uses=1]
+@i171_s = external global i171 ; <i171*> [#uses=1]
+@i172_s = external global i172 ; <i172*> [#uses=1]
+@i173_s = external global i173 ; <i173*> [#uses=1]
+@i174_s = external global i174 ; <i174*> [#uses=1]
+@i175_s = external global i175 ; <i175*> [#uses=1]
+@i176_s = external global i176 ; <i176*> [#uses=1]
+@i177_s = external global i177 ; <i177*> [#uses=1]
+@i178_s = external global i178 ; <i178*> [#uses=1]
+@i179_s = external global i179 ; <i179*> [#uses=1]
+@i180_s = external global i180 ; <i180*> [#uses=1]
+@i181_s = external global i181 ; <i181*> [#uses=1]
+@i182_s = external global i182 ; <i182*> [#uses=1]
+@i183_s = external global i183 ; <i183*> [#uses=1]
+@i184_s = external global i184 ; <i184*> [#uses=1]
+@i185_s = external global i185 ; <i185*> [#uses=1]
+@i186_s = external global i186 ; <i186*> [#uses=1]
+@i187_s = external global i187 ; <i187*> [#uses=1]
+@i188_s = external global i188 ; <i188*> [#uses=1]
+@i189_s = external global i189 ; <i189*> [#uses=1]
+@i190_s = external global i190 ; <i190*> [#uses=1]
+@i191_s = external global i191 ; <i191*> [#uses=1]
+@i192_s = external global i192 ; <i192*> [#uses=1]
+@i193_s = external global i193 ; <i193*> [#uses=1]
+@i194_s = external global i194 ; <i194*> [#uses=1]
+@i195_s = external global i195 ; <i195*> [#uses=1]
+@i196_s = external global i196 ; <i196*> [#uses=1]
+@i197_s = external global i197 ; <i197*> [#uses=1]
+@i198_s = external global i198 ; <i198*> [#uses=1]
+@i199_s = external global i199 ; <i199*> [#uses=1]
+@i200_s = external global i200 ; <i200*> [#uses=1]
+@i201_s = external global i201 ; <i201*> [#uses=1]
+@i202_s = external global i202 ; <i202*> [#uses=1]
+@i203_s = external global i203 ; <i203*> [#uses=1]
+@i204_s = external global i204 ; <i204*> [#uses=1]
+@i205_s = external global i205 ; <i205*> [#uses=1]
+@i206_s = external global i206 ; <i206*> [#uses=1]
+@i207_s = external global i207 ; <i207*> [#uses=1]
+@i208_s = external global i208 ; <i208*> [#uses=1]
+@i209_s = external global i209 ; <i209*> [#uses=1]
+@i210_s = external global i210 ; <i210*> [#uses=1]
+@i211_s = external global i211 ; <i211*> [#uses=1]
+@i212_s = external global i212 ; <i212*> [#uses=1]
+@i213_s = external global i213 ; <i213*> [#uses=1]
+@i214_s = external global i214 ; <i214*> [#uses=1]
+@i215_s = external global i215 ; <i215*> [#uses=1]
+@i216_s = external global i216 ; <i216*> [#uses=1]
+@i217_s = external global i217 ; <i217*> [#uses=1]
+@i218_s = external global i218 ; <i218*> [#uses=1]
+@i219_s = external global i219 ; <i219*> [#uses=1]
+@i220_s = external global i220 ; <i220*> [#uses=1]
+@i221_s = external global i221 ; <i221*> [#uses=1]
+@i222_s = external global i222 ; <i222*> [#uses=1]
+@i223_s = external global i223 ; <i223*> [#uses=1]
+@i224_s = external global i224 ; <i224*> [#uses=1]
+@i225_s = external global i225 ; <i225*> [#uses=1]
+@i226_s = external global i226 ; <i226*> [#uses=1]
+@i227_s = external global i227 ; <i227*> [#uses=1]
+@i228_s = external global i228 ; <i228*> [#uses=1]
+@i229_s = external global i229 ; <i229*> [#uses=1]
+@i230_s = external global i230 ; <i230*> [#uses=1]
+@i231_s = external global i231 ; <i231*> [#uses=1]
+@i232_s = external global i232 ; <i232*> [#uses=1]
+@i233_s = external global i233 ; <i233*> [#uses=1]
+@i234_s = external global i234 ; <i234*> [#uses=1]
+@i235_s = external global i235 ; <i235*> [#uses=1]
+@i236_s = external global i236 ; <i236*> [#uses=1]
+@i237_s = external global i237 ; <i237*> [#uses=1]
+@i238_s = external global i238 ; <i238*> [#uses=1]
+@i239_s = external global i239 ; <i239*> [#uses=1]
+@i240_s = external global i240 ; <i240*> [#uses=1]
+@i241_s = external global i241 ; <i241*> [#uses=1]
+@i242_s = external global i242 ; <i242*> [#uses=1]
+@i243_s = external global i243 ; <i243*> [#uses=1]
+@i244_s = external global i244 ; <i244*> [#uses=1]
+@i245_s = external global i245 ; <i245*> [#uses=1]
+@i246_s = external global i246 ; <i246*> [#uses=1]
+@i247_s = external global i247 ; <i247*> [#uses=1]
+@i248_s = external global i248 ; <i248*> [#uses=1]
+@i249_s = external global i249 ; <i249*> [#uses=1]
+@i250_s = external global i250 ; <i250*> [#uses=1]
+@i251_s = external global i251 ; <i251*> [#uses=1]
+@i252_s = external global i252 ; <i252*> [#uses=1]
+@i253_s = external global i253 ; <i253*> [#uses=1]
+@i254_s = external global i254 ; <i254*> [#uses=1]
+@i255_s = external global i255 ; <i255*> [#uses=1]
+@i256_s = external global i256 ; <i256*> [#uses=1]
+
+define void @i1_ls(i1 signext %x) nounwind {
+ store i1 %x, i1* @i1_s
+ ret void
+}
+
+define void @i2_ls(i2 signext %x) nounwind {
+ store i2 %x, i2* @i2_s
+ ret void
+}
+
+define void @i3_ls(i3 signext %x) nounwind {
+ store i3 %x, i3* @i3_s
+ ret void
+}
+
+define void @i4_ls(i4 signext %x) nounwind {
+ store i4 %x, i4* @i4_s
+ ret void
+}
+
+define void @i5_ls(i5 signext %x) nounwind {
+ store i5 %x, i5* @i5_s
+ ret void
+}
+
+define void @i6_ls(i6 signext %x) nounwind {
+ store i6 %x, i6* @i6_s
+ ret void
+}
+
+define void @i7_ls(i7 signext %x) nounwind {
+ store i7 %x, i7* @i7_s
+ ret void
+}
+
+define void @i8_ls(i8 signext %x) nounwind {
+ store i8 %x, i8* @i8_s
+ ret void
+}
+
+define void @i9_ls(i9 signext %x) nounwind {
+ store i9 %x, i9* @i9_s
+ ret void
+}
+
+define void @i10_ls(i10 signext %x) nounwind {
+ store i10 %x, i10* @i10_s
+ ret void
+}
+
+define void @i11_ls(i11 signext %x) nounwind {
+ store i11 %x, i11* @i11_s
+ ret void
+}
+
+define void @i12_ls(i12 signext %x) nounwind {
+ store i12 %x, i12* @i12_s
+ ret void
+}
+
+define void @i13_ls(i13 signext %x) nounwind {
+ store i13 %x, i13* @i13_s
+ ret void
+}
+
+define void @i14_ls(i14 signext %x) nounwind {
+ store i14 %x, i14* @i14_s
+ ret void
+}
+
+define void @i15_ls(i15 signext %x) nounwind {
+ store i15 %x, i15* @i15_s
+ ret void
+}
+
+define void @i16_ls(i16 signext %x) nounwind {
+ store i16 %x, i16* @i16_s
+ ret void
+}
+
+define void @i17_ls(i17 signext %x) nounwind {
+ store i17 %x, i17* @i17_s
+ ret void
+}
+
+define void @i18_ls(i18 signext %x) nounwind {
+ store i18 %x, i18* @i18_s
+ ret void
+}
+
+define void @i19_ls(i19 signext %x) nounwind {
+ store i19 %x, i19* @i19_s
+ ret void
+}
+
+define void @i20_ls(i20 signext %x) nounwind {
+ store i20 %x, i20* @i20_s
+ ret void
+}
+
+define void @i21_ls(i21 signext %x) nounwind {
+ store i21 %x, i21* @i21_s
+ ret void
+}
+
+define void @i22_ls(i22 signext %x) nounwind {
+ store i22 %x, i22* @i22_s
+ ret void
+}
+
+define void @i23_ls(i23 signext %x) nounwind {
+ store i23 %x, i23* @i23_s
+ ret void
+}
+
+define void @i24_ls(i24 signext %x) nounwind {
+ store i24 %x, i24* @i24_s
+ ret void
+}
+
+define void @i25_ls(i25 signext %x) nounwind {
+ store i25 %x, i25* @i25_s
+ ret void
+}
+
+define void @i26_ls(i26 signext %x) nounwind {
+ store i26 %x, i26* @i26_s
+ ret void
+}
+
+define void @i27_ls(i27 signext %x) nounwind {
+ store i27 %x, i27* @i27_s
+ ret void
+}
+
+define void @i28_ls(i28 signext %x) nounwind {
+ store i28 %x, i28* @i28_s
+ ret void
+}
+
+define void @i29_ls(i29 signext %x) nounwind {
+ store i29 %x, i29* @i29_s
+ ret void
+}
+
+define void @i30_ls(i30 signext %x) nounwind {
+ store i30 %x, i30* @i30_s
+ ret void
+}
+
+define void @i31_ls(i31 signext %x) nounwind {
+ store i31 %x, i31* @i31_s
+ ret void
+}
+
+define void @i32_ls(i32 signext %x) nounwind {
+ store i32 %x, i32* @i32_s
+ ret void
+}
+
+define void @i33_ls(i33 signext %x) nounwind {
+ store i33 %x, i33* @i33_s
+ ret void
+}
+
+define void @i34_ls(i34 signext %x) nounwind {
+ store i34 %x, i34* @i34_s
+ ret void
+}
+
+define void @i35_ls(i35 signext %x) nounwind {
+ store i35 %x, i35* @i35_s
+ ret void
+}
+
+define void @i36_ls(i36 signext %x) nounwind {
+ store i36 %x, i36* @i36_s
+ ret void
+}
+
+define void @i37_ls(i37 signext %x) nounwind {
+ store i37 %x, i37* @i37_s
+ ret void
+}
+
+define void @i38_ls(i38 signext %x) nounwind {
+ store i38 %x, i38* @i38_s
+ ret void
+}
+
+define void @i39_ls(i39 signext %x) nounwind {
+ store i39 %x, i39* @i39_s
+ ret void
+}
+
+define void @i40_ls(i40 signext %x) nounwind {
+ store i40 %x, i40* @i40_s
+ ret void
+}
+
+define void @i41_ls(i41 signext %x) nounwind {
+ store i41 %x, i41* @i41_s
+ ret void
+}
+
+define void @i42_ls(i42 signext %x) nounwind {
+ store i42 %x, i42* @i42_s
+ ret void
+}
+
+define void @i43_ls(i43 signext %x) nounwind {
+ store i43 %x, i43* @i43_s
+ ret void
+}
+
+define void @i44_ls(i44 signext %x) nounwind {
+ store i44 %x, i44* @i44_s
+ ret void
+}
+
+define void @i45_ls(i45 signext %x) nounwind {
+ store i45 %x, i45* @i45_s
+ ret void
+}
+
+define void @i46_ls(i46 signext %x) nounwind {
+ store i46 %x, i46* @i46_s
+ ret void
+}
+
+define void @i47_ls(i47 signext %x) nounwind {
+ store i47 %x, i47* @i47_s
+ ret void
+}
+
+define void @i48_ls(i48 signext %x) nounwind {
+ store i48 %x, i48* @i48_s
+ ret void
+}
+
+define void @i49_ls(i49 signext %x) nounwind {
+ store i49 %x, i49* @i49_s
+ ret void
+}
+
+define void @i50_ls(i50 signext %x) nounwind {
+ store i50 %x, i50* @i50_s
+ ret void
+}
+
+define void @i51_ls(i51 signext %x) nounwind {
+ store i51 %x, i51* @i51_s
+ ret void
+}
+
+define void @i52_ls(i52 signext %x) nounwind {
+ store i52 %x, i52* @i52_s
+ ret void
+}
+
+define void @i53_ls(i53 signext %x) nounwind {
+ store i53 %x, i53* @i53_s
+ ret void
+}
+
+define void @i54_ls(i54 signext %x) nounwind {
+ store i54 %x, i54* @i54_s
+ ret void
+}
+
+define void @i55_ls(i55 signext %x) nounwind {
+ store i55 %x, i55* @i55_s
+ ret void
+}
+
+define void @i56_ls(i56 signext %x) nounwind {
+ store i56 %x, i56* @i56_s
+ ret void
+}
+
+define void @i57_ls(i57 signext %x) nounwind {
+ store i57 %x, i57* @i57_s
+ ret void
+}
+
+define void @i58_ls(i58 signext %x) nounwind {
+ store i58 %x, i58* @i58_s
+ ret void
+}
+
+define void @i59_ls(i59 signext %x) nounwind {
+ store i59 %x, i59* @i59_s
+ ret void
+}
+
+define void @i60_ls(i60 signext %x) nounwind {
+ store i60 %x, i60* @i60_s
+ ret void
+}
+
+define void @i61_ls(i61 signext %x) nounwind {
+ store i61 %x, i61* @i61_s
+ ret void
+}
+
+define void @i62_ls(i62 signext %x) nounwind {
+ store i62 %x, i62* @i62_s
+ ret void
+}
+
+define void @i63_ls(i63 signext %x) nounwind {
+ store i63 %x, i63* @i63_s
+ ret void
+}
+
+define void @i64_ls(i64 signext %x) nounwind {
+ store i64 %x, i64* @i64_s
+ ret void
+}
+
+define void @i65_ls(i65 signext %x) nounwind {
+ store i65 %x, i65* @i65_s
+ ret void
+}
+
+define void @i66_ls(i66 signext %x) nounwind {
+ store i66 %x, i66* @i66_s
+ ret void
+}
+
+define void @i67_ls(i67 signext %x) nounwind {
+ store i67 %x, i67* @i67_s
+ ret void
+}
+
+define void @i68_ls(i68 signext %x) nounwind {
+ store i68 %x, i68* @i68_s
+ ret void
+}
+
+define void @i69_ls(i69 signext %x) nounwind {
+ store i69 %x, i69* @i69_s
+ ret void
+}
+
+define void @i70_ls(i70 signext %x) nounwind {
+ store i70 %x, i70* @i70_s
+ ret void
+}
+
+define void @i71_ls(i71 signext %x) nounwind {
+ store i71 %x, i71* @i71_s
+ ret void
+}
+
+define void @i72_ls(i72 signext %x) nounwind {
+ store i72 %x, i72* @i72_s
+ ret void
+}
+
+define void @i73_ls(i73 signext %x) nounwind {
+ store i73 %x, i73* @i73_s
+ ret void
+}
+
+define void @i74_ls(i74 signext %x) nounwind {
+ store i74 %x, i74* @i74_s
+ ret void
+}
+
+define void @i75_ls(i75 signext %x) nounwind {
+ store i75 %x, i75* @i75_s
+ ret void
+}
+
+define void @i76_ls(i76 signext %x) nounwind {
+ store i76 %x, i76* @i76_s
+ ret void
+}
+
+define void @i77_ls(i77 signext %x) nounwind {
+ store i77 %x, i77* @i77_s
+ ret void
+}
+
+define void @i78_ls(i78 signext %x) nounwind {
+ store i78 %x, i78* @i78_s
+ ret void
+}
+
+define void @i79_ls(i79 signext %x) nounwind {
+ store i79 %x, i79* @i79_s
+ ret void
+}
+
+define void @i80_ls(i80 signext %x) nounwind {
+ store i80 %x, i80* @i80_s
+ ret void
+}
+
+define void @i81_ls(i81 signext %x) nounwind {
+ store i81 %x, i81* @i81_s
+ ret void
+}
+
+define void @i82_ls(i82 signext %x) nounwind {
+ store i82 %x, i82* @i82_s
+ ret void
+}
+
+define void @i83_ls(i83 signext %x) nounwind {
+ store i83 %x, i83* @i83_s
+ ret void
+}
+
+define void @i84_ls(i84 signext %x) nounwind {
+ store i84 %x, i84* @i84_s
+ ret void
+}
+
+define void @i85_ls(i85 signext %x) nounwind {
+ store i85 %x, i85* @i85_s
+ ret void
+}
+
+define void @i86_ls(i86 signext %x) nounwind {
+ store i86 %x, i86* @i86_s
+ ret void
+}
+
+define void @i87_ls(i87 signext %x) nounwind {
+ store i87 %x, i87* @i87_s
+ ret void
+}
+
+define void @i88_ls(i88 signext %x) nounwind {
+ store i88 %x, i88* @i88_s
+ ret void
+}
+
+define void @i89_ls(i89 signext %x) nounwind {
+ store i89 %x, i89* @i89_s
+ ret void
+}
+
+define void @i90_ls(i90 signext %x) nounwind {
+ store i90 %x, i90* @i90_s
+ ret void
+}
+
+define void @i91_ls(i91 signext %x) nounwind {
+ store i91 %x, i91* @i91_s
+ ret void
+}
+
+define void @i92_ls(i92 signext %x) nounwind {
+ store i92 %x, i92* @i92_s
+ ret void
+}
+
+define void @i93_ls(i93 signext %x) nounwind {
+ store i93 %x, i93* @i93_s
+ ret void
+}
+
+define void @i94_ls(i94 signext %x) nounwind {
+ store i94 %x, i94* @i94_s
+ ret void
+}
+
+define void @i95_ls(i95 signext %x) nounwind {
+ store i95 %x, i95* @i95_s
+ ret void
+}
+
+define void @i96_ls(i96 signext %x) nounwind {
+ store i96 %x, i96* @i96_s
+ ret void
+}
+
+define void @i97_ls(i97 signext %x) nounwind {
+ store i97 %x, i97* @i97_s
+ ret void
+}
+
+define void @i98_ls(i98 signext %x) nounwind {
+ store i98 %x, i98* @i98_s
+ ret void
+}
+
+define void @i99_ls(i99 signext %x) nounwind {
+ store i99 %x, i99* @i99_s
+ ret void
+}
+
+define void @i100_ls(i100 signext %x) nounwind {
+ store i100 %x, i100* @i100_s
+ ret void
+}
+
+define void @i101_ls(i101 signext %x) nounwind {
+ store i101 %x, i101* @i101_s
+ ret void
+}
+
+define void @i102_ls(i102 signext %x) nounwind {
+ store i102 %x, i102* @i102_s
+ ret void
+}
+
+define void @i103_ls(i103 signext %x) nounwind {
+ store i103 %x, i103* @i103_s
+ ret void
+}
+
+define void @i104_ls(i104 signext %x) nounwind {
+ store i104 %x, i104* @i104_s
+ ret void
+}
+
+define void @i105_ls(i105 signext %x) nounwind {
+ store i105 %x, i105* @i105_s
+ ret void
+}
+
+define void @i106_ls(i106 signext %x) nounwind {
+ store i106 %x, i106* @i106_s
+ ret void
+}
+
+define void @i107_ls(i107 signext %x) nounwind {
+ store i107 %x, i107* @i107_s
+ ret void
+}
+
+define void @i108_ls(i108 signext %x) nounwind {
+ store i108 %x, i108* @i108_s
+ ret void
+}
+
+define void @i109_ls(i109 signext %x) nounwind {
+ store i109 %x, i109* @i109_s
+ ret void
+}
+
+define void @i110_ls(i110 signext %x) nounwind {
+ store i110 %x, i110* @i110_s
+ ret void
+}
+
+define void @i111_ls(i111 signext %x) nounwind {
+ store i111 %x, i111* @i111_s
+ ret void
+}
+
+define void @i112_ls(i112 signext %x) nounwind {
+ store i112 %x, i112* @i112_s
+ ret void
+}
+
+define void @i113_ls(i113 signext %x) nounwind {
+ store i113 %x, i113* @i113_s
+ ret void
+}
+
+define void @i114_ls(i114 signext %x) nounwind {
+ store i114 %x, i114* @i114_s
+ ret void
+}
+
+define void @i115_ls(i115 signext %x) nounwind {
+ store i115 %x, i115* @i115_s
+ ret void
+}
+
+define void @i116_ls(i116 signext %x) nounwind {
+ store i116 %x, i116* @i116_s
+ ret void
+}
+
+define void @i117_ls(i117 signext %x) nounwind {
+ store i117 %x, i117* @i117_s
+ ret void
+}
+
+define void @i118_ls(i118 signext %x) nounwind {
+ store i118 %x, i118* @i118_s
+ ret void
+}
+
+define void @i119_ls(i119 signext %x) nounwind {
+ store i119 %x, i119* @i119_s
+ ret void
+}
+
+define void @i120_ls(i120 signext %x) nounwind {
+ store i120 %x, i120* @i120_s
+ ret void
+}
+
+define void @i121_ls(i121 signext %x) nounwind {
+ store i121 %x, i121* @i121_s
+ ret void
+}
+
+define void @i122_ls(i122 signext %x) nounwind {
+ store i122 %x, i122* @i122_s
+ ret void
+}
+
+define void @i123_ls(i123 signext %x) nounwind {
+ store i123 %x, i123* @i123_s
+ ret void
+}
+
+define void @i124_ls(i124 signext %x) nounwind {
+ store i124 %x, i124* @i124_s
+ ret void
+}
+
+define void @i125_ls(i125 signext %x) nounwind {
+ store i125 %x, i125* @i125_s
+ ret void
+}
+
+define void @i126_ls(i126 signext %x) nounwind {
+ store i126 %x, i126* @i126_s
+ ret void
+}
+
+define void @i127_ls(i127 signext %x) nounwind {
+ store i127 %x, i127* @i127_s
+ ret void
+}
+
+define void @i128_ls(i128 signext %x) nounwind {
+ store i128 %x, i128* @i128_s
+ ret void
+}
+
+define void @i129_ls(i129 signext %x) nounwind {
+ store i129 %x, i129* @i129_s
+ ret void
+}
+
+define void @i130_ls(i130 signext %x) nounwind {
+ store i130 %x, i130* @i130_s
+ ret void
+}
+
+define void @i131_ls(i131 signext %x) nounwind {
+ store i131 %x, i131* @i131_s
+ ret void
+}
+
+define void @i132_ls(i132 signext %x) nounwind {
+ store i132 %x, i132* @i132_s
+ ret void
+}
+
+define void @i133_ls(i133 signext %x) nounwind {
+ store i133 %x, i133* @i133_s
+ ret void
+}
+
+define void @i134_ls(i134 signext %x) nounwind {
+ store i134 %x, i134* @i134_s
+ ret void
+}
+
+define void @i135_ls(i135 signext %x) nounwind {
+ store i135 %x, i135* @i135_s
+ ret void
+}
+
+define void @i136_ls(i136 signext %x) nounwind {
+ store i136 %x, i136* @i136_s
+ ret void
+}
+
+define void @i137_ls(i137 signext %x) nounwind {
+ store i137 %x, i137* @i137_s
+ ret void
+}
+
+define void @i138_ls(i138 signext %x) nounwind {
+ store i138 %x, i138* @i138_s
+ ret void
+}
+
+define void @i139_ls(i139 signext %x) nounwind {
+ store i139 %x, i139* @i139_s
+ ret void
+}
+
+define void @i140_ls(i140 signext %x) nounwind {
+ store i140 %x, i140* @i140_s
+ ret void
+}
+
+define void @i141_ls(i141 signext %x) nounwind {
+ store i141 %x, i141* @i141_s
+ ret void
+}
+
+define void @i142_ls(i142 signext %x) nounwind {
+ store i142 %x, i142* @i142_s
+ ret void
+}
+
+define void @i143_ls(i143 signext %x) nounwind {
+ store i143 %x, i143* @i143_s
+ ret void
+}
+
+define void @i144_ls(i144 signext %x) nounwind {
+ store i144 %x, i144* @i144_s
+ ret void
+}
+
+define void @i145_ls(i145 signext %x) nounwind {
+ store i145 %x, i145* @i145_s
+ ret void
+}
+
+define void @i146_ls(i146 signext %x) nounwind {
+ store i146 %x, i146* @i146_s
+ ret void
+}
+
+define void @i147_ls(i147 signext %x) nounwind {
+ store i147 %x, i147* @i147_s
+ ret void
+}
+
+define void @i148_ls(i148 signext %x) nounwind {
+ store i148 %x, i148* @i148_s
+ ret void
+}
+
+define void @i149_ls(i149 signext %x) nounwind {
+ store i149 %x, i149* @i149_s
+ ret void
+}
+
+define void @i150_ls(i150 signext %x) nounwind {
+ store i150 %x, i150* @i150_s
+ ret void
+}
+
+define void @i151_ls(i151 signext %x) nounwind {
+ store i151 %x, i151* @i151_s
+ ret void
+}
+
+define void @i152_ls(i152 signext %x) nounwind {
+ store i152 %x, i152* @i152_s
+ ret void
+}
+
+define void @i153_ls(i153 signext %x) nounwind {
+ store i153 %x, i153* @i153_s
+ ret void
+}
+
+define void @i154_ls(i154 signext %x) nounwind {
+ store i154 %x, i154* @i154_s
+ ret void
+}
+
+define void @i155_ls(i155 signext %x) nounwind {
+ store i155 %x, i155* @i155_s
+ ret void
+}
+
+define void @i156_ls(i156 signext %x) nounwind {
+ store i156 %x, i156* @i156_s
+ ret void
+}
+
+define void @i157_ls(i157 signext %x) nounwind {
+ store i157 %x, i157* @i157_s
+ ret void
+}
+
+define void @i158_ls(i158 signext %x) nounwind {
+ store i158 %x, i158* @i158_s
+ ret void
+}
+
+define void @i159_ls(i159 signext %x) nounwind {
+ store i159 %x, i159* @i159_s
+ ret void
+}
+
+define void @i160_ls(i160 signext %x) nounwind {
+ store i160 %x, i160* @i160_s
+ ret void
+}
+
+define void @i161_ls(i161 signext %x) nounwind {
+ store i161 %x, i161* @i161_s
+ ret void
+}
+
+define void @i162_ls(i162 signext %x) nounwind {
+ store i162 %x, i162* @i162_s
+ ret void
+}
+
+define void @i163_ls(i163 signext %x) nounwind {
+ store i163 %x, i163* @i163_s
+ ret void
+}
+
+define void @i164_ls(i164 signext %x) nounwind {
+ store i164 %x, i164* @i164_s
+ ret void
+}
+
+define void @i165_ls(i165 signext %x) nounwind {
+ store i165 %x, i165* @i165_s
+ ret void
+}
+
+define void @i166_ls(i166 signext %x) nounwind {
+ store i166 %x, i166* @i166_s
+ ret void
+}
+
+define void @i167_ls(i167 signext %x) nounwind {
+ store i167 %x, i167* @i167_s
+ ret void
+}
+
+define void @i168_ls(i168 signext %x) nounwind {
+ store i168 %x, i168* @i168_s
+ ret void
+}
+
+define void @i169_ls(i169 signext %x) nounwind {
+ store i169 %x, i169* @i169_s
+ ret void
+}
+
+define void @i170_ls(i170 signext %x) nounwind {
+ store i170 %x, i170* @i170_s
+ ret void
+}
+
+define void @i171_ls(i171 signext %x) nounwind {
+ store i171 %x, i171* @i171_s
+ ret void
+}
+
+define void @i172_ls(i172 signext %x) nounwind {
+ store i172 %x, i172* @i172_s
+ ret void
+}
+
+define void @i173_ls(i173 signext %x) nounwind {
+ store i173 %x, i173* @i173_s
+ ret void
+}
+
+define void @i174_ls(i174 signext %x) nounwind {
+ store i174 %x, i174* @i174_s
+ ret void
+}
+
+define void @i175_ls(i175 signext %x) nounwind {
+ store i175 %x, i175* @i175_s
+ ret void
+}
+
+define void @i176_ls(i176 signext %x) nounwind {
+ store i176 %x, i176* @i176_s
+ ret void
+}
+
+define void @i177_ls(i177 signext %x) nounwind {
+ store i177 %x, i177* @i177_s
+ ret void
+}
+
+define void @i178_ls(i178 signext %x) nounwind {
+ store i178 %x, i178* @i178_s
+ ret void
+}
+
+define void @i179_ls(i179 signext %x) nounwind {
+ store i179 %x, i179* @i179_s
+ ret void
+}
+
+define void @i180_ls(i180 signext %x) nounwind {
+ store i180 %x, i180* @i180_s
+ ret void
+}
+
+define void @i181_ls(i181 signext %x) nounwind {
+ store i181 %x, i181* @i181_s
+ ret void
+}
+
+define void @i182_ls(i182 signext %x) nounwind {
+ store i182 %x, i182* @i182_s
+ ret void
+}
+
+define void @i183_ls(i183 signext %x) nounwind {
+ store i183 %x, i183* @i183_s
+ ret void
+}
+
+define void @i184_ls(i184 signext %x) nounwind {
+ store i184 %x, i184* @i184_s
+ ret void
+}
+
+define void @i185_ls(i185 signext %x) nounwind {
+ store i185 %x, i185* @i185_s
+ ret void
+}
+
+define void @i186_ls(i186 signext %x) nounwind {
+ store i186 %x, i186* @i186_s
+ ret void
+}
+
+define void @i187_ls(i187 signext %x) nounwind {
+ store i187 %x, i187* @i187_s
+ ret void
+}
+
+define void @i188_ls(i188 signext %x) nounwind {
+ store i188 %x, i188* @i188_s
+ ret void
+}
+
+define void @i189_ls(i189 signext %x) nounwind {
+ store i189 %x, i189* @i189_s
+ ret void
+}
+
+define void @i190_ls(i190 signext %x) nounwind {
+ store i190 %x, i190* @i190_s
+ ret void
+}
+
+define void @i191_ls(i191 signext %x) nounwind {
+ store i191 %x, i191* @i191_s
+ ret void
+}
+
+define void @i192_ls(i192 signext %x) nounwind {
+ store i192 %x, i192* @i192_s
+ ret void
+}
+
+define void @i193_ls(i193 signext %x) nounwind {
+ store i193 %x, i193* @i193_s
+ ret void
+}
+
+define void @i194_ls(i194 signext %x) nounwind {
+ store i194 %x, i194* @i194_s
+ ret void
+}
+
+define void @i195_ls(i195 signext %x) nounwind {
+ store i195 %x, i195* @i195_s
+ ret void
+}
+
+define void @i196_ls(i196 signext %x) nounwind {
+ store i196 %x, i196* @i196_s
+ ret void
+}
+
+define void @i197_ls(i197 signext %x) nounwind {
+ store i197 %x, i197* @i197_s
+ ret void
+}
+
+define void @i198_ls(i198 signext %x) nounwind {
+ store i198 %x, i198* @i198_s
+ ret void
+}
+
+define void @i199_ls(i199 signext %x) nounwind {
+ store i199 %x, i199* @i199_s
+ ret void
+}
+
+define void @i200_ls(i200 signext %x) nounwind {
+ store i200 %x, i200* @i200_s
+ ret void
+}
+
+define void @i201_ls(i201 signext %x) nounwind {
+ store i201 %x, i201* @i201_s
+ ret void
+}
+
+define void @i202_ls(i202 signext %x) nounwind {
+ store i202 %x, i202* @i202_s
+ ret void
+}
+
+define void @i203_ls(i203 signext %x) nounwind {
+ store i203 %x, i203* @i203_s
+ ret void
+}
+
+define void @i204_ls(i204 signext %x) nounwind {
+ store i204 %x, i204* @i204_s
+ ret void
+}
+
+define void @i205_ls(i205 signext %x) nounwind {
+ store i205 %x, i205* @i205_s
+ ret void
+}
+
+define void @i206_ls(i206 signext %x) nounwind {
+ store i206 %x, i206* @i206_s
+ ret void
+}
+
+define void @i207_ls(i207 signext %x) nounwind {
+ store i207 %x, i207* @i207_s
+ ret void
+}
+
+define void @i208_ls(i208 signext %x) nounwind {
+ store i208 %x, i208* @i208_s
+ ret void
+}
+
+define void @i209_ls(i209 signext %x) nounwind {
+ store i209 %x, i209* @i209_s
+ ret void
+}
+
+define void @i210_ls(i210 signext %x) nounwind {
+ store i210 %x, i210* @i210_s
+ ret void
+}
+
+define void @i211_ls(i211 signext %x) nounwind {
+ store i211 %x, i211* @i211_s
+ ret void
+}
+
+define void @i212_ls(i212 signext %x) nounwind {
+ store i212 %x, i212* @i212_s
+ ret void
+}
+
+define void @i213_ls(i213 signext %x) nounwind {
+ store i213 %x, i213* @i213_s
+ ret void
+}
+
+define void @i214_ls(i214 signext %x) nounwind {
+ store i214 %x, i214* @i214_s
+ ret void
+}
+
+define void @i215_ls(i215 signext %x) nounwind {
+ store i215 %x, i215* @i215_s
+ ret void
+}
+
+define void @i216_ls(i216 signext %x) nounwind {
+ store i216 %x, i216* @i216_s
+ ret void
+}
+
+define void @i217_ls(i217 signext %x) nounwind {
+ store i217 %x, i217* @i217_s
+ ret void
+}
+
+define void @i218_ls(i218 signext %x) nounwind {
+ store i218 %x, i218* @i218_s
+ ret void
+}
+
+define void @i219_ls(i219 signext %x) nounwind {
+ store i219 %x, i219* @i219_s
+ ret void
+}
+
+define void @i220_ls(i220 signext %x) nounwind {
+ store i220 %x, i220* @i220_s
+ ret void
+}
+
+define void @i221_ls(i221 signext %x) nounwind {
+ store i221 %x, i221* @i221_s
+ ret void
+}
+
+define void @i222_ls(i222 signext %x) nounwind {
+ store i222 %x, i222* @i222_s
+ ret void
+}
+
+define void @i223_ls(i223 signext %x) nounwind {
+ store i223 %x, i223* @i223_s
+ ret void
+}
+
+define void @i224_ls(i224 signext %x) nounwind {
+ store i224 %x, i224* @i224_s
+ ret void
+}
+
+define void @i225_ls(i225 signext %x) nounwind {
+ store i225 %x, i225* @i225_s
+ ret void
+}
+
+define void @i226_ls(i226 signext %x) nounwind {
+ store i226 %x, i226* @i226_s
+ ret void
+}
+
+define void @i227_ls(i227 signext %x) nounwind {
+ store i227 %x, i227* @i227_s
+ ret void
+}
+
+define void @i228_ls(i228 signext %x) nounwind {
+ store i228 %x, i228* @i228_s
+ ret void
+}
+
+define void @i229_ls(i229 signext %x) nounwind {
+ store i229 %x, i229* @i229_s
+ ret void
+}
+
+define void @i230_ls(i230 signext %x) nounwind {
+ store i230 %x, i230* @i230_s
+ ret void
+}
+
+define void @i231_ls(i231 signext %x) nounwind {
+ store i231 %x, i231* @i231_s
+ ret void
+}
+
+define void @i232_ls(i232 signext %x) nounwind {
+ store i232 %x, i232* @i232_s
+ ret void
+}
+
+define void @i233_ls(i233 signext %x) nounwind {
+ store i233 %x, i233* @i233_s
+ ret void
+}
+
+define void @i234_ls(i234 signext %x) nounwind {
+ store i234 %x, i234* @i234_s
+ ret void
+}
+
+define void @i235_ls(i235 signext %x) nounwind {
+ store i235 %x, i235* @i235_s
+ ret void
+}
+
+define void @i236_ls(i236 signext %x) nounwind {
+ store i236 %x, i236* @i236_s
+ ret void
+}
+
+define void @i237_ls(i237 signext %x) nounwind {
+ store i237 %x, i237* @i237_s
+ ret void
+}
+
+define void @i238_ls(i238 signext %x) nounwind {
+ store i238 %x, i238* @i238_s
+ ret void
+}
+
+define void @i239_ls(i239 signext %x) nounwind {
+ store i239 %x, i239* @i239_s
+ ret void
+}
+
+define void @i240_ls(i240 signext %x) nounwind {
+ store i240 %x, i240* @i240_s
+ ret void
+}
+
+define void @i241_ls(i241 signext %x) nounwind {
+ store i241 %x, i241* @i241_s
+ ret void
+}
+
+define void @i242_ls(i242 signext %x) nounwind {
+ store i242 %x, i242* @i242_s
+ ret void
+}
+
+define void @i243_ls(i243 signext %x) nounwind {
+ store i243 %x, i243* @i243_s
+ ret void
+}
+
+define void @i244_ls(i244 signext %x) nounwind {
+ store i244 %x, i244* @i244_s
+ ret void
+}
+
+define void @i245_ls(i245 signext %x) nounwind {
+ store i245 %x, i245* @i245_s
+ ret void
+}
+
+define void @i246_ls(i246 signext %x) nounwind {
+ store i246 %x, i246* @i246_s
+ ret void
+}
+
+define void @i247_ls(i247 signext %x) nounwind {
+ store i247 %x, i247* @i247_s
+ ret void
+}
+
+define void @i248_ls(i248 signext %x) nounwind {
+ store i248 %x, i248* @i248_s
+ ret void
+}
+
+define void @i249_ls(i249 signext %x) nounwind {
+ store i249 %x, i249* @i249_s
+ ret void
+}
+
+define void @i250_ls(i250 signext %x) nounwind {
+ store i250 %x, i250* @i250_s
+ ret void
+}
+
+define void @i251_ls(i251 signext %x) nounwind {
+ store i251 %x, i251* @i251_s
+ ret void
+}
+
+define void @i252_ls(i252 signext %x) nounwind {
+ store i252 %x, i252* @i252_s
+ ret void
+}
+
+define void @i253_ls(i253 signext %x) nounwind {
+ store i253 %x, i253* @i253_s
+ ret void
+}
+
+define void @i254_ls(i254 signext %x) nounwind {
+ store i254 %x, i254* @i254_s
+ ret void
+}
+
+define void @i255_ls(i255 signext %x) nounwind {
+ store i255 %x, i255* @i255_s
+ ret void
+}
+
+define void @i256_ls(i256 signext %x) nounwind {
+ store i256 %x, i256* @i256_s
+ ret void
+}
diff --git a/test/CodeGen/Generic/APIntZextParam.ll b/test/CodeGen/Generic/APIntZextParam.ll
new file mode 100644
index 0000000..173b9fd
--- /dev/null
+++ b/test/CodeGen/Generic/APIntZextParam.ll
@@ -0,0 +1,1537 @@
+; RUN: llc < %s > %t
+@i1_s = external global i1 ; <i1*> [#uses=1]
+@i2_s = external global i2 ; <i2*> [#uses=1]
+@i3_s = external global i3 ; <i3*> [#uses=1]
+@i4_s = external global i4 ; <i4*> [#uses=1]
+@i5_s = external global i5 ; <i5*> [#uses=1]
+@i6_s = external global i6 ; <i6*> [#uses=1]
+@i7_s = external global i7 ; <i7*> [#uses=1]
+@i8_s = external global i8 ; <i8*> [#uses=1]
+@i9_s = external global i9 ; <i9*> [#uses=1]
+@i10_s = external global i10 ; <i10*> [#uses=1]
+@i11_s = external global i11 ; <i11*> [#uses=1]
+@i12_s = external global i12 ; <i12*> [#uses=1]
+@i13_s = external global i13 ; <i13*> [#uses=1]
+@i14_s = external global i14 ; <i14*> [#uses=1]
+@i15_s = external global i15 ; <i15*> [#uses=1]
+@i16_s = external global i16 ; <i16*> [#uses=1]
+@i17_s = external global i17 ; <i17*> [#uses=1]
+@i18_s = external global i18 ; <i18*> [#uses=1]
+@i19_s = external global i19 ; <i19*> [#uses=1]
+@i20_s = external global i20 ; <i20*> [#uses=1]
+@i21_s = external global i21 ; <i21*> [#uses=1]
+@i22_s = external global i22 ; <i22*> [#uses=1]
+@i23_s = external global i23 ; <i23*> [#uses=1]
+@i24_s = external global i24 ; <i24*> [#uses=1]
+@i25_s = external global i25 ; <i25*> [#uses=1]
+@i26_s = external global i26 ; <i26*> [#uses=1]
+@i27_s = external global i27 ; <i27*> [#uses=1]
+@i28_s = external global i28 ; <i28*> [#uses=1]
+@i29_s = external global i29 ; <i29*> [#uses=1]
+@i30_s = external global i30 ; <i30*> [#uses=1]
+@i31_s = external global i31 ; <i31*> [#uses=1]
+@i32_s = external global i32 ; <i32*> [#uses=1]
+@i33_s = external global i33 ; <i33*> [#uses=1]
+@i34_s = external global i34 ; <i34*> [#uses=1]
+@i35_s = external global i35 ; <i35*> [#uses=1]
+@i36_s = external global i36 ; <i36*> [#uses=1]
+@i37_s = external global i37 ; <i37*> [#uses=1]
+@i38_s = external global i38 ; <i38*> [#uses=1]
+@i39_s = external global i39 ; <i39*> [#uses=1]
+@i40_s = external global i40 ; <i40*> [#uses=1]
+@i41_s = external global i41 ; <i41*> [#uses=1]
+@i42_s = external global i42 ; <i42*> [#uses=1]
+@i43_s = external global i43 ; <i43*> [#uses=1]
+@i44_s = external global i44 ; <i44*> [#uses=1]
+@i45_s = external global i45 ; <i45*> [#uses=1]
+@i46_s = external global i46 ; <i46*> [#uses=1]
+@i47_s = external global i47 ; <i47*> [#uses=1]
+@i48_s = external global i48 ; <i48*> [#uses=1]
+@i49_s = external global i49 ; <i49*> [#uses=1]
+@i50_s = external global i50 ; <i50*> [#uses=1]
+@i51_s = external global i51 ; <i51*> [#uses=1]
+@i52_s = external global i52 ; <i52*> [#uses=1]
+@i53_s = external global i53 ; <i53*> [#uses=1]
+@i54_s = external global i54 ; <i54*> [#uses=1]
+@i55_s = external global i55 ; <i55*> [#uses=1]
+@i56_s = external global i56 ; <i56*> [#uses=1]
+@i57_s = external global i57 ; <i57*> [#uses=1]
+@i58_s = external global i58 ; <i58*> [#uses=1]
+@i59_s = external global i59 ; <i59*> [#uses=1]
+@i60_s = external global i60 ; <i60*> [#uses=1]
+@i61_s = external global i61 ; <i61*> [#uses=1]
+@i62_s = external global i62 ; <i62*> [#uses=1]
+@i63_s = external global i63 ; <i63*> [#uses=1]
+@i64_s = external global i64 ; <i64*> [#uses=1]
+@i65_s = external global i65 ; <i65*> [#uses=1]
+@i66_s = external global i66 ; <i66*> [#uses=1]
+@i67_s = external global i67 ; <i67*> [#uses=1]
+@i68_s = external global i68 ; <i68*> [#uses=1]
+@i69_s = external global i69 ; <i69*> [#uses=1]
+@i70_s = external global i70 ; <i70*> [#uses=1]
+@i71_s = external global i71 ; <i71*> [#uses=1]
+@i72_s = external global i72 ; <i72*> [#uses=1]
+@i73_s = external global i73 ; <i73*> [#uses=1]
+@i74_s = external global i74 ; <i74*> [#uses=1]
+@i75_s = external global i75 ; <i75*> [#uses=1]
+@i76_s = external global i76 ; <i76*> [#uses=1]
+@i77_s = external global i77 ; <i77*> [#uses=1]
+@i78_s = external global i78 ; <i78*> [#uses=1]
+@i79_s = external global i79 ; <i79*> [#uses=1]
+@i80_s = external global i80 ; <i80*> [#uses=1]
+@i81_s = external global i81 ; <i81*> [#uses=1]
+@i82_s = external global i82 ; <i82*> [#uses=1]
+@i83_s = external global i83 ; <i83*> [#uses=1]
+@i84_s = external global i84 ; <i84*> [#uses=1]
+@i85_s = external global i85 ; <i85*> [#uses=1]
+@i86_s = external global i86 ; <i86*> [#uses=1]
+@i87_s = external global i87 ; <i87*> [#uses=1]
+@i88_s = external global i88 ; <i88*> [#uses=1]
+@i89_s = external global i89 ; <i89*> [#uses=1]
+@i90_s = external global i90 ; <i90*> [#uses=1]
+@i91_s = external global i91 ; <i91*> [#uses=1]
+@i92_s = external global i92 ; <i92*> [#uses=1]
+@i93_s = external global i93 ; <i93*> [#uses=1]
+@i94_s = external global i94 ; <i94*> [#uses=1]
+@i95_s = external global i95 ; <i95*> [#uses=1]
+@i96_s = external global i96 ; <i96*> [#uses=1]
+@i97_s = external global i97 ; <i97*> [#uses=1]
+@i98_s = external global i98 ; <i98*> [#uses=1]
+@i99_s = external global i99 ; <i99*> [#uses=1]
+@i100_s = external global i100 ; <i100*> [#uses=1]
+@i101_s = external global i101 ; <i101*> [#uses=1]
+@i102_s = external global i102 ; <i102*> [#uses=1]
+@i103_s = external global i103 ; <i103*> [#uses=1]
+@i104_s = external global i104 ; <i104*> [#uses=1]
+@i105_s = external global i105 ; <i105*> [#uses=1]
+@i106_s = external global i106 ; <i106*> [#uses=1]
+@i107_s = external global i107 ; <i107*> [#uses=1]
+@i108_s = external global i108 ; <i108*> [#uses=1]
+@i109_s = external global i109 ; <i109*> [#uses=1]
+@i110_s = external global i110 ; <i110*> [#uses=1]
+@i111_s = external global i111 ; <i111*> [#uses=1]
+@i112_s = external global i112 ; <i112*> [#uses=1]
+@i113_s = external global i113 ; <i113*> [#uses=1]
+@i114_s = external global i114 ; <i114*> [#uses=1]
+@i115_s = external global i115 ; <i115*> [#uses=1]
+@i116_s = external global i116 ; <i116*> [#uses=1]
+@i117_s = external global i117 ; <i117*> [#uses=1]
+@i118_s = external global i118 ; <i118*> [#uses=1]
+@i119_s = external global i119 ; <i119*> [#uses=1]
+@i120_s = external global i120 ; <i120*> [#uses=1]
+@i121_s = external global i121 ; <i121*> [#uses=1]
+@i122_s = external global i122 ; <i122*> [#uses=1]
+@i123_s = external global i123 ; <i123*> [#uses=1]
+@i124_s = external global i124 ; <i124*> [#uses=1]
+@i125_s = external global i125 ; <i125*> [#uses=1]
+@i126_s = external global i126 ; <i126*> [#uses=1]
+@i127_s = external global i127 ; <i127*> [#uses=1]
+@i128_s = external global i128 ; <i128*> [#uses=1]
+@i129_s = external global i129 ; <i129*> [#uses=1]
+@i130_s = external global i130 ; <i130*> [#uses=1]
+@i131_s = external global i131 ; <i131*> [#uses=1]
+@i132_s = external global i132 ; <i132*> [#uses=1]
+@i133_s = external global i133 ; <i133*> [#uses=1]
+@i134_s = external global i134 ; <i134*> [#uses=1]
+@i135_s = external global i135 ; <i135*> [#uses=1]
+@i136_s = external global i136 ; <i136*> [#uses=1]
+@i137_s = external global i137 ; <i137*> [#uses=1]
+@i138_s = external global i138 ; <i138*> [#uses=1]
+@i139_s = external global i139 ; <i139*> [#uses=1]
+@i140_s = external global i140 ; <i140*> [#uses=1]
+@i141_s = external global i141 ; <i141*> [#uses=1]
+@i142_s = external global i142 ; <i142*> [#uses=1]
+@i143_s = external global i143 ; <i143*> [#uses=1]
+@i144_s = external global i144 ; <i144*> [#uses=1]
+@i145_s = external global i145 ; <i145*> [#uses=1]
+@i146_s = external global i146 ; <i146*> [#uses=1]
+@i147_s = external global i147 ; <i147*> [#uses=1]
+@i148_s = external global i148 ; <i148*> [#uses=1]
+@i149_s = external global i149 ; <i149*> [#uses=1]
+@i150_s = external global i150 ; <i150*> [#uses=1]
+@i151_s = external global i151 ; <i151*> [#uses=1]
+@i152_s = external global i152 ; <i152*> [#uses=1]
+@i153_s = external global i153 ; <i153*> [#uses=1]
+@i154_s = external global i154 ; <i154*> [#uses=1]
+@i155_s = external global i155 ; <i155*> [#uses=1]
+@i156_s = external global i156 ; <i156*> [#uses=1]
+@i157_s = external global i157 ; <i157*> [#uses=1]
+@i158_s = external global i158 ; <i158*> [#uses=1]
+@i159_s = external global i159 ; <i159*> [#uses=1]
+@i160_s = external global i160 ; <i160*> [#uses=1]
+@i161_s = external global i161 ; <i161*> [#uses=1]
+@i162_s = external global i162 ; <i162*> [#uses=1]
+@i163_s = external global i163 ; <i163*> [#uses=1]
+@i164_s = external global i164 ; <i164*> [#uses=1]
+@i165_s = external global i165 ; <i165*> [#uses=1]
+@i166_s = external global i166 ; <i166*> [#uses=1]
+@i167_s = external global i167 ; <i167*> [#uses=1]
+@i168_s = external global i168 ; <i168*> [#uses=1]
+@i169_s = external global i169 ; <i169*> [#uses=1]
+@i170_s = external global i170 ; <i170*> [#uses=1]
+@i171_s = external global i171 ; <i171*> [#uses=1]
+@i172_s = external global i172 ; <i172*> [#uses=1]
+@i173_s = external global i173 ; <i173*> [#uses=1]
+@i174_s = external global i174 ; <i174*> [#uses=1]
+@i175_s = external global i175 ; <i175*> [#uses=1]
+@i176_s = external global i176 ; <i176*> [#uses=1]
+@i177_s = external global i177 ; <i177*> [#uses=1]
+@i178_s = external global i178 ; <i178*> [#uses=1]
+@i179_s = external global i179 ; <i179*> [#uses=1]
+@i180_s = external global i180 ; <i180*> [#uses=1]
+@i181_s = external global i181 ; <i181*> [#uses=1]
+@i182_s = external global i182 ; <i182*> [#uses=1]
+@i183_s = external global i183 ; <i183*> [#uses=1]
+@i184_s = external global i184 ; <i184*> [#uses=1]
+@i185_s = external global i185 ; <i185*> [#uses=1]
+@i186_s = external global i186 ; <i186*> [#uses=1]
+@i187_s = external global i187 ; <i187*> [#uses=1]
+@i188_s = external global i188 ; <i188*> [#uses=1]
+@i189_s = external global i189 ; <i189*> [#uses=1]
+@i190_s = external global i190 ; <i190*> [#uses=1]
+@i191_s = external global i191 ; <i191*> [#uses=1]
+@i192_s = external global i192 ; <i192*> [#uses=1]
+@i193_s = external global i193 ; <i193*> [#uses=1]
+@i194_s = external global i194 ; <i194*> [#uses=1]
+@i195_s = external global i195 ; <i195*> [#uses=1]
+@i196_s = external global i196 ; <i196*> [#uses=1]
+@i197_s = external global i197 ; <i197*> [#uses=1]
+@i198_s = external global i198 ; <i198*> [#uses=1]
+@i199_s = external global i199 ; <i199*> [#uses=1]
+@i200_s = external global i200 ; <i200*> [#uses=1]
+@i201_s = external global i201 ; <i201*> [#uses=1]
+@i202_s = external global i202 ; <i202*> [#uses=1]
+@i203_s = external global i203 ; <i203*> [#uses=1]
+@i204_s = external global i204 ; <i204*> [#uses=1]
+@i205_s = external global i205 ; <i205*> [#uses=1]
+@i206_s = external global i206 ; <i206*> [#uses=1]
+@i207_s = external global i207 ; <i207*> [#uses=1]
+@i208_s = external global i208 ; <i208*> [#uses=1]
+@i209_s = external global i209 ; <i209*> [#uses=1]
+@i210_s = external global i210 ; <i210*> [#uses=1]
+@i211_s = external global i211 ; <i211*> [#uses=1]
+@i212_s = external global i212 ; <i212*> [#uses=1]
+@i213_s = external global i213 ; <i213*> [#uses=1]
+@i214_s = external global i214 ; <i214*> [#uses=1]
+@i215_s = external global i215 ; <i215*> [#uses=1]
+@i216_s = external global i216 ; <i216*> [#uses=1]
+@i217_s = external global i217 ; <i217*> [#uses=1]
+@i218_s = external global i218 ; <i218*> [#uses=1]
+@i219_s = external global i219 ; <i219*> [#uses=1]
+@i220_s = external global i220 ; <i220*> [#uses=1]
+@i221_s = external global i221 ; <i221*> [#uses=1]
+@i222_s = external global i222 ; <i222*> [#uses=1]
+@i223_s = external global i223 ; <i223*> [#uses=1]
+@i224_s = external global i224 ; <i224*> [#uses=1]
+@i225_s = external global i225 ; <i225*> [#uses=1]
+@i226_s = external global i226 ; <i226*> [#uses=1]
+@i227_s = external global i227 ; <i227*> [#uses=1]
+@i228_s = external global i228 ; <i228*> [#uses=1]
+@i229_s = external global i229 ; <i229*> [#uses=1]
+@i230_s = external global i230 ; <i230*> [#uses=1]
+@i231_s = external global i231 ; <i231*> [#uses=1]
+@i232_s = external global i232 ; <i232*> [#uses=1]
+@i233_s = external global i233 ; <i233*> [#uses=1]
+@i234_s = external global i234 ; <i234*> [#uses=1]
+@i235_s = external global i235 ; <i235*> [#uses=1]
+@i236_s = external global i236 ; <i236*> [#uses=1]
+@i237_s = external global i237 ; <i237*> [#uses=1]
+@i238_s = external global i238 ; <i238*> [#uses=1]
+@i239_s = external global i239 ; <i239*> [#uses=1]
+@i240_s = external global i240 ; <i240*> [#uses=1]
+@i241_s = external global i241 ; <i241*> [#uses=1]
+@i242_s = external global i242 ; <i242*> [#uses=1]
+@i243_s = external global i243 ; <i243*> [#uses=1]
+@i244_s = external global i244 ; <i244*> [#uses=1]
+@i245_s = external global i245 ; <i245*> [#uses=1]
+@i246_s = external global i246 ; <i246*> [#uses=1]
+@i247_s = external global i247 ; <i247*> [#uses=1]
+@i248_s = external global i248 ; <i248*> [#uses=1]
+@i249_s = external global i249 ; <i249*> [#uses=1]
+@i250_s = external global i250 ; <i250*> [#uses=1]
+@i251_s = external global i251 ; <i251*> [#uses=1]
+@i252_s = external global i252 ; <i252*> [#uses=1]
+@i253_s = external global i253 ; <i253*> [#uses=1]
+@i254_s = external global i254 ; <i254*> [#uses=1]
+@i255_s = external global i255 ; <i255*> [#uses=1]
+@i256_s = external global i256 ; <i256*> [#uses=1]
+
+define void @i1_ls(i1 zeroext %x) nounwind {
+ store i1 %x, i1* @i1_s
+ ret void
+}
+
+define void @i2_ls(i2 zeroext %x) nounwind {
+ store i2 %x, i2* @i2_s
+ ret void
+}
+
+define void @i3_ls(i3 zeroext %x) nounwind {
+ store i3 %x, i3* @i3_s
+ ret void
+}
+
+define void @i4_ls(i4 zeroext %x) nounwind {
+ store i4 %x, i4* @i4_s
+ ret void
+}
+
+define void @i5_ls(i5 zeroext %x) nounwind {
+ store i5 %x, i5* @i5_s
+ ret void
+}
+
+define void @i6_ls(i6 zeroext %x) nounwind {
+ store i6 %x, i6* @i6_s
+ ret void
+}
+
+define void @i7_ls(i7 zeroext %x) nounwind {
+ store i7 %x, i7* @i7_s
+ ret void
+}
+
+define void @i8_ls(i8 zeroext %x) nounwind {
+ store i8 %x, i8* @i8_s
+ ret void
+}
+
+define void @i9_ls(i9 zeroext %x) nounwind {
+ store i9 %x, i9* @i9_s
+ ret void
+}
+
+define void @i10_ls(i10 zeroext %x) nounwind {
+ store i10 %x, i10* @i10_s
+ ret void
+}
+
+define void @i11_ls(i11 zeroext %x) nounwind {
+ store i11 %x, i11* @i11_s
+ ret void
+}
+
+define void @i12_ls(i12 zeroext %x) nounwind {
+ store i12 %x, i12* @i12_s
+ ret void
+}
+
+define void @i13_ls(i13 zeroext %x) nounwind {
+ store i13 %x, i13* @i13_s
+ ret void
+}
+
+define void @i14_ls(i14 zeroext %x) nounwind {
+ store i14 %x, i14* @i14_s
+ ret void
+}
+
+define void @i15_ls(i15 zeroext %x) nounwind {
+ store i15 %x, i15* @i15_s
+ ret void
+}
+
+define void @i16_ls(i16 zeroext %x) nounwind {
+ store i16 %x, i16* @i16_s
+ ret void
+}
+
+define void @i17_ls(i17 zeroext %x) nounwind {
+ store i17 %x, i17* @i17_s
+ ret void
+}
+
+define void @i18_ls(i18 zeroext %x) nounwind {
+ store i18 %x, i18* @i18_s
+ ret void
+}
+
+define void @i19_ls(i19 zeroext %x) nounwind {
+ store i19 %x, i19* @i19_s
+ ret void
+}
+
+define void @i20_ls(i20 zeroext %x) nounwind {
+ store i20 %x, i20* @i20_s
+ ret void
+}
+
+define void @i21_ls(i21 zeroext %x) nounwind {
+ store i21 %x, i21* @i21_s
+ ret void
+}
+
+define void @i22_ls(i22 zeroext %x) nounwind {
+ store i22 %x, i22* @i22_s
+ ret void
+}
+
+define void @i23_ls(i23 zeroext %x) nounwind {
+ store i23 %x, i23* @i23_s
+ ret void
+}
+
+define void @i24_ls(i24 zeroext %x) nounwind {
+ store i24 %x, i24* @i24_s
+ ret void
+}
+
+define void @i25_ls(i25 zeroext %x) nounwind {
+ store i25 %x, i25* @i25_s
+ ret void
+}
+
+define void @i26_ls(i26 zeroext %x) nounwind {
+ store i26 %x, i26* @i26_s
+ ret void
+}
+
+define void @i27_ls(i27 zeroext %x) nounwind {
+ store i27 %x, i27* @i27_s
+ ret void
+}
+
+define void @i28_ls(i28 zeroext %x) nounwind {
+ store i28 %x, i28* @i28_s
+ ret void
+}
+
+define void @i29_ls(i29 zeroext %x) nounwind {
+ store i29 %x, i29* @i29_s
+ ret void
+}
+
+define void @i30_ls(i30 zeroext %x) nounwind {
+ store i30 %x, i30* @i30_s
+ ret void
+}
+
+define void @i31_ls(i31 zeroext %x) nounwind {
+ store i31 %x, i31* @i31_s
+ ret void
+}
+
+define void @i32_ls(i32 zeroext %x) nounwind {
+ store i32 %x, i32* @i32_s
+ ret void
+}
+
+define void @i33_ls(i33 zeroext %x) nounwind {
+ store i33 %x, i33* @i33_s
+ ret void
+}
+
+define void @i34_ls(i34 zeroext %x) nounwind {
+ store i34 %x, i34* @i34_s
+ ret void
+}
+
+define void @i35_ls(i35 zeroext %x) nounwind {
+ store i35 %x, i35* @i35_s
+ ret void
+}
+
+define void @i36_ls(i36 zeroext %x) nounwind {
+ store i36 %x, i36* @i36_s
+ ret void
+}
+
+define void @i37_ls(i37 zeroext %x) nounwind {
+ store i37 %x, i37* @i37_s
+ ret void
+}
+
+define void @i38_ls(i38 zeroext %x) nounwind {
+ store i38 %x, i38* @i38_s
+ ret void
+}
+
+define void @i39_ls(i39 zeroext %x) nounwind {
+ store i39 %x, i39* @i39_s
+ ret void
+}
+
+define void @i40_ls(i40 zeroext %x) nounwind {
+ store i40 %x, i40* @i40_s
+ ret void
+}
+
+define void @i41_ls(i41 zeroext %x) nounwind {
+ store i41 %x, i41* @i41_s
+ ret void
+}
+
+define void @i42_ls(i42 zeroext %x) nounwind {
+ store i42 %x, i42* @i42_s
+ ret void
+}
+
+define void @i43_ls(i43 zeroext %x) nounwind {
+ store i43 %x, i43* @i43_s
+ ret void
+}
+
+define void @i44_ls(i44 zeroext %x) nounwind {
+ store i44 %x, i44* @i44_s
+ ret void
+}
+
+define void @i45_ls(i45 zeroext %x) nounwind {
+ store i45 %x, i45* @i45_s
+ ret void
+}
+
+define void @i46_ls(i46 zeroext %x) nounwind {
+ store i46 %x, i46* @i46_s
+ ret void
+}
+
+define void @i47_ls(i47 zeroext %x) nounwind {
+ store i47 %x, i47* @i47_s
+ ret void
+}
+
+define void @i48_ls(i48 zeroext %x) nounwind {
+ store i48 %x, i48* @i48_s
+ ret void
+}
+
+define void @i49_ls(i49 zeroext %x) nounwind {
+ store i49 %x, i49* @i49_s
+ ret void
+}
+
+define void @i50_ls(i50 zeroext %x) nounwind {
+ store i50 %x, i50* @i50_s
+ ret void
+}
+
+define void @i51_ls(i51 zeroext %x) nounwind {
+ store i51 %x, i51* @i51_s
+ ret void
+}
+
+define void @i52_ls(i52 zeroext %x) nounwind {
+ store i52 %x, i52* @i52_s
+ ret void
+}
+
+define void @i53_ls(i53 zeroext %x) nounwind {
+ store i53 %x, i53* @i53_s
+ ret void
+}
+
+define void @i54_ls(i54 zeroext %x) nounwind {
+ store i54 %x, i54* @i54_s
+ ret void
+}
+
+define void @i55_ls(i55 zeroext %x) nounwind {
+ store i55 %x, i55* @i55_s
+ ret void
+}
+
+define void @i56_ls(i56 zeroext %x) nounwind {
+ store i56 %x, i56* @i56_s
+ ret void
+}
+
+define void @i57_ls(i57 zeroext %x) nounwind {
+ store i57 %x, i57* @i57_s
+ ret void
+}
+
+define void @i58_ls(i58 zeroext %x) nounwind {
+ store i58 %x, i58* @i58_s
+ ret void
+}
+
+define void @i59_ls(i59 zeroext %x) nounwind {
+ store i59 %x, i59* @i59_s
+ ret void
+}
+
+define void @i60_ls(i60 zeroext %x) nounwind {
+ store i60 %x, i60* @i60_s
+ ret void
+}
+
+define void @i61_ls(i61 zeroext %x) nounwind {
+ store i61 %x, i61* @i61_s
+ ret void
+}
+
+define void @i62_ls(i62 zeroext %x) nounwind {
+ store i62 %x, i62* @i62_s
+ ret void
+}
+
+define void @i63_ls(i63 zeroext %x) nounwind {
+ store i63 %x, i63* @i63_s
+ ret void
+}
+
+define void @i64_ls(i64 zeroext %x) nounwind {
+ store i64 %x, i64* @i64_s
+ ret void
+}
+
+define void @i65_ls(i65 zeroext %x) nounwind {
+ store i65 %x, i65* @i65_s
+ ret void
+}
+
+define void @i66_ls(i66 zeroext %x) nounwind {
+ store i66 %x, i66* @i66_s
+ ret void
+}
+
+define void @i67_ls(i67 zeroext %x) nounwind {
+ store i67 %x, i67* @i67_s
+ ret void
+}
+
+define void @i68_ls(i68 zeroext %x) nounwind {
+ store i68 %x, i68* @i68_s
+ ret void
+}
+
+define void @i69_ls(i69 zeroext %x) nounwind {
+ store i69 %x, i69* @i69_s
+ ret void
+}
+
+define void @i70_ls(i70 zeroext %x) nounwind {
+ store i70 %x, i70* @i70_s
+ ret void
+}
+
+define void @i71_ls(i71 zeroext %x) nounwind {
+ store i71 %x, i71* @i71_s
+ ret void
+}
+
+define void @i72_ls(i72 zeroext %x) nounwind {
+ store i72 %x, i72* @i72_s
+ ret void
+}
+
+define void @i73_ls(i73 zeroext %x) nounwind {
+ store i73 %x, i73* @i73_s
+ ret void
+}
+
+define void @i74_ls(i74 zeroext %x) nounwind {
+ store i74 %x, i74* @i74_s
+ ret void
+}
+
+define void @i75_ls(i75 zeroext %x) nounwind {
+ store i75 %x, i75* @i75_s
+ ret void
+}
+
+define void @i76_ls(i76 zeroext %x) nounwind {
+ store i76 %x, i76* @i76_s
+ ret void
+}
+
+define void @i77_ls(i77 zeroext %x) nounwind {
+ store i77 %x, i77* @i77_s
+ ret void
+}
+
+define void @i78_ls(i78 zeroext %x) nounwind {
+ store i78 %x, i78* @i78_s
+ ret void
+}
+
+define void @i79_ls(i79 zeroext %x) nounwind {
+ store i79 %x, i79* @i79_s
+ ret void
+}
+
+define void @i80_ls(i80 zeroext %x) nounwind {
+ store i80 %x, i80* @i80_s
+ ret void
+}
+
+define void @i81_ls(i81 zeroext %x) nounwind {
+ store i81 %x, i81* @i81_s
+ ret void
+}
+
+define void @i82_ls(i82 zeroext %x) nounwind {
+ store i82 %x, i82* @i82_s
+ ret void
+}
+
+define void @i83_ls(i83 zeroext %x) nounwind {
+ store i83 %x, i83* @i83_s
+ ret void
+}
+
+define void @i84_ls(i84 zeroext %x) nounwind {
+ store i84 %x, i84* @i84_s
+ ret void
+}
+
+define void @i85_ls(i85 zeroext %x) nounwind {
+ store i85 %x, i85* @i85_s
+ ret void
+}
+
+define void @i86_ls(i86 zeroext %x) nounwind {
+ store i86 %x, i86* @i86_s
+ ret void
+}
+
+define void @i87_ls(i87 zeroext %x) nounwind {
+ store i87 %x, i87* @i87_s
+ ret void
+}
+
+define void @i88_ls(i88 zeroext %x) nounwind {
+ store i88 %x, i88* @i88_s
+ ret void
+}
+
+define void @i89_ls(i89 zeroext %x) nounwind {
+ store i89 %x, i89* @i89_s
+ ret void
+}
+
+define void @i90_ls(i90 zeroext %x) nounwind {
+ store i90 %x, i90* @i90_s
+ ret void
+}
+
+define void @i91_ls(i91 zeroext %x) nounwind {
+ store i91 %x, i91* @i91_s
+ ret void
+}
+
+define void @i92_ls(i92 zeroext %x) nounwind {
+ store i92 %x, i92* @i92_s
+ ret void
+}
+
+define void @i93_ls(i93 zeroext %x) nounwind {
+ store i93 %x, i93* @i93_s
+ ret void
+}
+
+define void @i94_ls(i94 zeroext %x) nounwind {
+ store i94 %x, i94* @i94_s
+ ret void
+}
+
+define void @i95_ls(i95 zeroext %x) nounwind {
+ store i95 %x, i95* @i95_s
+ ret void
+}
+
+define void @i96_ls(i96 zeroext %x) nounwind {
+ store i96 %x, i96* @i96_s
+ ret void
+}
+
+define void @i97_ls(i97 zeroext %x) nounwind {
+ store i97 %x, i97* @i97_s
+ ret void
+}
+
+define void @i98_ls(i98 zeroext %x) nounwind {
+ store i98 %x, i98* @i98_s
+ ret void
+}
+
+define void @i99_ls(i99 zeroext %x) nounwind {
+ store i99 %x, i99* @i99_s
+ ret void
+}
+
+define void @i100_ls(i100 zeroext %x) nounwind {
+ store i100 %x, i100* @i100_s
+ ret void
+}
+
+define void @i101_ls(i101 zeroext %x) nounwind {
+ store i101 %x, i101* @i101_s
+ ret void
+}
+
+define void @i102_ls(i102 zeroext %x) nounwind {
+ store i102 %x, i102* @i102_s
+ ret void
+}
+
+define void @i103_ls(i103 zeroext %x) nounwind {
+ store i103 %x, i103* @i103_s
+ ret void
+}
+
+define void @i104_ls(i104 zeroext %x) nounwind {
+ store i104 %x, i104* @i104_s
+ ret void
+}
+
+define void @i105_ls(i105 zeroext %x) nounwind {
+ store i105 %x, i105* @i105_s
+ ret void
+}
+
+define void @i106_ls(i106 zeroext %x) nounwind {
+ store i106 %x, i106* @i106_s
+ ret void
+}
+
+define void @i107_ls(i107 zeroext %x) nounwind {
+ store i107 %x, i107* @i107_s
+ ret void
+}
+
+define void @i108_ls(i108 zeroext %x) nounwind {
+ store i108 %x, i108* @i108_s
+ ret void
+}
+
+define void @i109_ls(i109 zeroext %x) nounwind {
+ store i109 %x, i109* @i109_s
+ ret void
+}
+
+define void @i110_ls(i110 zeroext %x) nounwind {
+ store i110 %x, i110* @i110_s
+ ret void
+}
+
+define void @i111_ls(i111 zeroext %x) nounwind {
+ store i111 %x, i111* @i111_s
+ ret void
+}
+
+define void @i112_ls(i112 zeroext %x) nounwind {
+ store i112 %x, i112* @i112_s
+ ret void
+}
+
+define void @i113_ls(i113 zeroext %x) nounwind {
+ store i113 %x, i113* @i113_s
+ ret void
+}
+
+define void @i114_ls(i114 zeroext %x) nounwind {
+ store i114 %x, i114* @i114_s
+ ret void
+}
+
+define void @i115_ls(i115 zeroext %x) nounwind {
+ store i115 %x, i115* @i115_s
+ ret void
+}
+
+define void @i116_ls(i116 zeroext %x) nounwind {
+ store i116 %x, i116* @i116_s
+ ret void
+}
+
+define void @i117_ls(i117 zeroext %x) nounwind {
+ store i117 %x, i117* @i117_s
+ ret void
+}
+
+define void @i118_ls(i118 zeroext %x) nounwind {
+ store i118 %x, i118* @i118_s
+ ret void
+}
+
+define void @i119_ls(i119 zeroext %x) nounwind {
+ store i119 %x, i119* @i119_s
+ ret void
+}
+
+define void @i120_ls(i120 zeroext %x) nounwind {
+ store i120 %x, i120* @i120_s
+ ret void
+}
+
+define void @i121_ls(i121 zeroext %x) nounwind {
+ store i121 %x, i121* @i121_s
+ ret void
+}
+
+define void @i122_ls(i122 zeroext %x) nounwind {
+ store i122 %x, i122* @i122_s
+ ret void
+}
+
+define void @i123_ls(i123 zeroext %x) nounwind {
+ store i123 %x, i123* @i123_s
+ ret void
+}
+
+define void @i124_ls(i124 zeroext %x) nounwind {
+ store i124 %x, i124* @i124_s
+ ret void
+}
+
+define void @i125_ls(i125 zeroext %x) nounwind {
+ store i125 %x, i125* @i125_s
+ ret void
+}
+
+define void @i126_ls(i126 zeroext %x) nounwind {
+ store i126 %x, i126* @i126_s
+ ret void
+}
+
+define void @i127_ls(i127 zeroext %x) nounwind {
+ store i127 %x, i127* @i127_s
+ ret void
+}
+
+define void @i128_ls(i128 zeroext %x) nounwind {
+ store i128 %x, i128* @i128_s
+ ret void
+}
+
+define void @i129_ls(i129 zeroext %x) nounwind {
+ store i129 %x, i129* @i129_s
+ ret void
+}
+
+define void @i130_ls(i130 zeroext %x) nounwind {
+ store i130 %x, i130* @i130_s
+ ret void
+}
+
+define void @i131_ls(i131 zeroext %x) nounwind {
+ store i131 %x, i131* @i131_s
+ ret void
+}
+
+define void @i132_ls(i132 zeroext %x) nounwind {
+ store i132 %x, i132* @i132_s
+ ret void
+}
+
+define void @i133_ls(i133 zeroext %x) nounwind {
+ store i133 %x, i133* @i133_s
+ ret void
+}
+
+define void @i134_ls(i134 zeroext %x) nounwind {
+ store i134 %x, i134* @i134_s
+ ret void
+}
+
+define void @i135_ls(i135 zeroext %x) nounwind {
+ store i135 %x, i135* @i135_s
+ ret void
+}
+
+define void @i136_ls(i136 zeroext %x) nounwind {
+ store i136 %x, i136* @i136_s
+ ret void
+}
+
+define void @i137_ls(i137 zeroext %x) nounwind {
+ store i137 %x, i137* @i137_s
+ ret void
+}
+
+define void @i138_ls(i138 zeroext %x) nounwind {
+ store i138 %x, i138* @i138_s
+ ret void
+}
+
+define void @i139_ls(i139 zeroext %x) nounwind {
+ store i139 %x, i139* @i139_s
+ ret void
+}
+
+define void @i140_ls(i140 zeroext %x) nounwind {
+ store i140 %x, i140* @i140_s
+ ret void
+}
+
+define void @i141_ls(i141 zeroext %x) nounwind {
+ store i141 %x, i141* @i141_s
+ ret void
+}
+
+define void @i142_ls(i142 zeroext %x) nounwind {
+ store i142 %x, i142* @i142_s
+ ret void
+}
+
+define void @i143_ls(i143 zeroext %x) nounwind {
+ store i143 %x, i143* @i143_s
+ ret void
+}
+
+define void @i144_ls(i144 zeroext %x) nounwind {
+ store i144 %x, i144* @i144_s
+ ret void
+}
+
+define void @i145_ls(i145 zeroext %x) nounwind {
+ store i145 %x, i145* @i145_s
+ ret void
+}
+
+define void @i146_ls(i146 zeroext %x) nounwind {
+ store i146 %x, i146* @i146_s
+ ret void
+}
+
+define void @i147_ls(i147 zeroext %x) nounwind {
+ store i147 %x, i147* @i147_s
+ ret void
+}
+
+define void @i148_ls(i148 zeroext %x) nounwind {
+ store i148 %x, i148* @i148_s
+ ret void
+}
+
+define void @i149_ls(i149 zeroext %x) nounwind {
+ store i149 %x, i149* @i149_s
+ ret void
+}
+
+define void @i150_ls(i150 zeroext %x) nounwind {
+ store i150 %x, i150* @i150_s
+ ret void
+}
+
+define void @i151_ls(i151 zeroext %x) nounwind {
+ store i151 %x, i151* @i151_s
+ ret void
+}
+
+define void @i152_ls(i152 zeroext %x) nounwind {
+ store i152 %x, i152* @i152_s
+ ret void
+}
+
+define void @i153_ls(i153 zeroext %x) nounwind {
+ store i153 %x, i153* @i153_s
+ ret void
+}
+
+define void @i154_ls(i154 zeroext %x) nounwind {
+ store i154 %x, i154* @i154_s
+ ret void
+}
+
+define void @i155_ls(i155 zeroext %x) nounwind {
+ store i155 %x, i155* @i155_s
+ ret void
+}
+
+define void @i156_ls(i156 zeroext %x) nounwind {
+ store i156 %x, i156* @i156_s
+ ret void
+}
+
+define void @i157_ls(i157 zeroext %x) nounwind {
+ store i157 %x, i157* @i157_s
+ ret void
+}
+
+define void @i158_ls(i158 zeroext %x) nounwind {
+ store i158 %x, i158* @i158_s
+ ret void
+}
+
+define void @i159_ls(i159 zeroext %x) nounwind {
+ store i159 %x, i159* @i159_s
+ ret void
+}
+
+define void @i160_ls(i160 zeroext %x) nounwind {
+ store i160 %x, i160* @i160_s
+ ret void
+}
+
+define void @i161_ls(i161 zeroext %x) nounwind {
+ store i161 %x, i161* @i161_s
+ ret void
+}
+
+define void @i162_ls(i162 zeroext %x) nounwind {
+ store i162 %x, i162* @i162_s
+ ret void
+}
+
+define void @i163_ls(i163 zeroext %x) nounwind {
+ store i163 %x, i163* @i163_s
+ ret void
+}
+
+define void @i164_ls(i164 zeroext %x) nounwind {
+ store i164 %x, i164* @i164_s
+ ret void
+}
+
+define void @i165_ls(i165 zeroext %x) nounwind {
+ store i165 %x, i165* @i165_s
+ ret void
+}
+
+define void @i166_ls(i166 zeroext %x) nounwind {
+ store i166 %x, i166* @i166_s
+ ret void
+}
+
+define void @i167_ls(i167 zeroext %x) nounwind {
+ store i167 %x, i167* @i167_s
+ ret void
+}
+
+define void @i168_ls(i168 zeroext %x) nounwind {
+ store i168 %x, i168* @i168_s
+ ret void
+}
+
+define void @i169_ls(i169 zeroext %x) nounwind {
+ store i169 %x, i169* @i169_s
+ ret void
+}
+
+define void @i170_ls(i170 zeroext %x) nounwind {
+ store i170 %x, i170* @i170_s
+ ret void
+}
+
+define void @i171_ls(i171 zeroext %x) nounwind {
+ store i171 %x, i171* @i171_s
+ ret void
+}
+
+define void @i172_ls(i172 zeroext %x) nounwind {
+ store i172 %x, i172* @i172_s
+ ret void
+}
+
+define void @i173_ls(i173 zeroext %x) nounwind {
+ store i173 %x, i173* @i173_s
+ ret void
+}
+
+define void @i174_ls(i174 zeroext %x) nounwind {
+ store i174 %x, i174* @i174_s
+ ret void
+}
+
+define void @i175_ls(i175 zeroext %x) nounwind {
+ store i175 %x, i175* @i175_s
+ ret void
+}
+
+define void @i176_ls(i176 zeroext %x) nounwind {
+ store i176 %x, i176* @i176_s
+ ret void
+}
+
+define void @i177_ls(i177 zeroext %x) nounwind {
+ store i177 %x, i177* @i177_s
+ ret void
+}
+
+define void @i178_ls(i178 zeroext %x) nounwind {
+ store i178 %x, i178* @i178_s
+ ret void
+}
+
+define void @i179_ls(i179 zeroext %x) nounwind {
+ store i179 %x, i179* @i179_s
+ ret void
+}
+
+define void @i180_ls(i180 zeroext %x) nounwind {
+ store i180 %x, i180* @i180_s
+ ret void
+}
+
+define void @i181_ls(i181 zeroext %x) nounwind {
+ store i181 %x, i181* @i181_s
+ ret void
+}
+
+define void @i182_ls(i182 zeroext %x) nounwind {
+ store i182 %x, i182* @i182_s
+ ret void
+}
+
+define void @i183_ls(i183 zeroext %x) nounwind {
+ store i183 %x, i183* @i183_s
+ ret void
+}
+
+define void @i184_ls(i184 zeroext %x) nounwind {
+ store i184 %x, i184* @i184_s
+ ret void
+}
+
+define void @i185_ls(i185 zeroext %x) nounwind {
+ store i185 %x, i185* @i185_s
+ ret void
+}
+
+define void @i186_ls(i186 zeroext %x) nounwind {
+ store i186 %x, i186* @i186_s
+ ret void
+}
+
+define void @i187_ls(i187 zeroext %x) nounwind {
+ store i187 %x, i187* @i187_s
+ ret void
+}
+
+define void @i188_ls(i188 zeroext %x) nounwind {
+ store i188 %x, i188* @i188_s
+ ret void
+}
+
+define void @i189_ls(i189 zeroext %x) nounwind {
+ store i189 %x, i189* @i189_s
+ ret void
+}
+
+define void @i190_ls(i190 zeroext %x) nounwind {
+ store i190 %x, i190* @i190_s
+ ret void
+}
+
+define void @i191_ls(i191 zeroext %x) nounwind {
+ store i191 %x, i191* @i191_s
+ ret void
+}
+
+define void @i192_ls(i192 zeroext %x) nounwind {
+ store i192 %x, i192* @i192_s
+ ret void
+}
+
+define void @i193_ls(i193 zeroext %x) nounwind {
+ store i193 %x, i193* @i193_s
+ ret void
+}
+
+define void @i194_ls(i194 zeroext %x) nounwind {
+ store i194 %x, i194* @i194_s
+ ret void
+}
+
+define void @i195_ls(i195 zeroext %x) nounwind {
+ store i195 %x, i195* @i195_s
+ ret void
+}
+
+define void @i196_ls(i196 zeroext %x) nounwind {
+ store i196 %x, i196* @i196_s
+ ret void
+}
+
+define void @i197_ls(i197 zeroext %x) nounwind {
+ store i197 %x, i197* @i197_s
+ ret void
+}
+
+define void @i198_ls(i198 zeroext %x) nounwind {
+ store i198 %x, i198* @i198_s
+ ret void
+}
+
+define void @i199_ls(i199 zeroext %x) nounwind {
+ store i199 %x, i199* @i199_s
+ ret void
+}
+
+define void @i200_ls(i200 zeroext %x) nounwind {
+ store i200 %x, i200* @i200_s
+ ret void
+}
+
+define void @i201_ls(i201 zeroext %x) nounwind {
+ store i201 %x, i201* @i201_s
+ ret void
+}
+
+define void @i202_ls(i202 zeroext %x) nounwind {
+ store i202 %x, i202* @i202_s
+ ret void
+}
+
+define void @i203_ls(i203 zeroext %x) nounwind {
+ store i203 %x, i203* @i203_s
+ ret void
+}
+
+define void @i204_ls(i204 zeroext %x) nounwind {
+ store i204 %x, i204* @i204_s
+ ret void
+}
+
+define void @i205_ls(i205 zeroext %x) nounwind {
+ store i205 %x, i205* @i205_s
+ ret void
+}
+
+define void @i206_ls(i206 zeroext %x) nounwind {
+ store i206 %x, i206* @i206_s
+ ret void
+}
+
+define void @i207_ls(i207 zeroext %x) nounwind {
+ store i207 %x, i207* @i207_s
+ ret void
+}
+
+define void @i208_ls(i208 zeroext %x) nounwind {
+ store i208 %x, i208* @i208_s
+ ret void
+}
+
+define void @i209_ls(i209 zeroext %x) nounwind {
+ store i209 %x, i209* @i209_s
+ ret void
+}
+
+define void @i210_ls(i210 zeroext %x) nounwind {
+ store i210 %x, i210* @i210_s
+ ret void
+}
+
+define void @i211_ls(i211 zeroext %x) nounwind {
+ store i211 %x, i211* @i211_s
+ ret void
+}
+
+define void @i212_ls(i212 zeroext %x) nounwind {
+ store i212 %x, i212* @i212_s
+ ret void
+}
+
+define void @i213_ls(i213 zeroext %x) nounwind {
+ store i213 %x, i213* @i213_s
+ ret void
+}
+
+define void @i214_ls(i214 zeroext %x) nounwind {
+ store i214 %x, i214* @i214_s
+ ret void
+}
+
+define void @i215_ls(i215 zeroext %x) nounwind {
+ store i215 %x, i215* @i215_s
+ ret void
+}
+
+define void @i216_ls(i216 zeroext %x) nounwind {
+ store i216 %x, i216* @i216_s
+ ret void
+}
+
+define void @i217_ls(i217 zeroext %x) nounwind {
+ store i217 %x, i217* @i217_s
+ ret void
+}
+
+define void @i218_ls(i218 zeroext %x) nounwind {
+ store i218 %x, i218* @i218_s
+ ret void
+}
+
+define void @i219_ls(i219 zeroext %x) nounwind {
+ store i219 %x, i219* @i219_s
+ ret void
+}
+
+define void @i220_ls(i220 zeroext %x) nounwind {
+ store i220 %x, i220* @i220_s
+ ret void
+}
+
+define void @i221_ls(i221 zeroext %x) nounwind {
+ store i221 %x, i221* @i221_s
+ ret void
+}
+
+define void @i222_ls(i222 zeroext %x) nounwind {
+ store i222 %x, i222* @i222_s
+ ret void
+}
+
+define void @i223_ls(i223 zeroext %x) nounwind {
+ store i223 %x, i223* @i223_s
+ ret void
+}
+
+define void @i224_ls(i224 zeroext %x) nounwind {
+ store i224 %x, i224* @i224_s
+ ret void
+}
+
+define void @i225_ls(i225 zeroext %x) nounwind {
+ store i225 %x, i225* @i225_s
+ ret void
+}
+
+define void @i226_ls(i226 zeroext %x) nounwind {
+ store i226 %x, i226* @i226_s
+ ret void
+}
+
+define void @i227_ls(i227 zeroext %x) nounwind {
+ store i227 %x, i227* @i227_s
+ ret void
+}
+
+define void @i228_ls(i228 zeroext %x) nounwind {
+ store i228 %x, i228* @i228_s
+ ret void
+}
+
+define void @i229_ls(i229 zeroext %x) nounwind {
+ store i229 %x, i229* @i229_s
+ ret void
+}
+
+define void @i230_ls(i230 zeroext %x) nounwind {
+ store i230 %x, i230* @i230_s
+ ret void
+}
+
+define void @i231_ls(i231 zeroext %x) nounwind {
+ store i231 %x, i231* @i231_s
+ ret void
+}
+
+define void @i232_ls(i232 zeroext %x) nounwind {
+ store i232 %x, i232* @i232_s
+ ret void
+}
+
+define void @i233_ls(i233 zeroext %x) nounwind {
+ store i233 %x, i233* @i233_s
+ ret void
+}
+
+define void @i234_ls(i234 zeroext %x) nounwind {
+ store i234 %x, i234* @i234_s
+ ret void
+}
+
+define void @i235_ls(i235 zeroext %x) nounwind {
+ store i235 %x, i235* @i235_s
+ ret void
+}
+
+define void @i236_ls(i236 zeroext %x) nounwind {
+ store i236 %x, i236* @i236_s
+ ret void
+}
+
+define void @i237_ls(i237 zeroext %x) nounwind {
+ store i237 %x, i237* @i237_s
+ ret void
+}
+
+define void @i238_ls(i238 zeroext %x) nounwind {
+ store i238 %x, i238* @i238_s
+ ret void
+}
+
+define void @i239_ls(i239 zeroext %x) nounwind {
+ store i239 %x, i239* @i239_s
+ ret void
+}
+
+define void @i240_ls(i240 zeroext %x) nounwind {
+ store i240 %x, i240* @i240_s
+ ret void
+}
+
+define void @i241_ls(i241 zeroext %x) nounwind {
+ store i241 %x, i241* @i241_s
+ ret void
+}
+
+define void @i242_ls(i242 zeroext %x) nounwind {
+ store i242 %x, i242* @i242_s
+ ret void
+}
+
+define void @i243_ls(i243 zeroext %x) nounwind {
+ store i243 %x, i243* @i243_s
+ ret void
+}
+
+define void @i244_ls(i244 zeroext %x) nounwind {
+ store i244 %x, i244* @i244_s
+ ret void
+}
+
+define void @i245_ls(i245 zeroext %x) nounwind {
+ store i245 %x, i245* @i245_s
+ ret void
+}
+
+define void @i246_ls(i246 zeroext %x) nounwind {
+ store i246 %x, i246* @i246_s
+ ret void
+}
+
+define void @i247_ls(i247 zeroext %x) nounwind {
+ store i247 %x, i247* @i247_s
+ ret void
+}
+
+define void @i248_ls(i248 zeroext %x) nounwind {
+ store i248 %x, i248* @i248_s
+ ret void
+}
+
+define void @i249_ls(i249 zeroext %x) nounwind {
+ store i249 %x, i249* @i249_s
+ ret void
+}
+
+define void @i250_ls(i250 zeroext %x) nounwind {
+ store i250 %x, i250* @i250_s
+ ret void
+}
+
+define void @i251_ls(i251 zeroext %x) nounwind {
+ store i251 %x, i251* @i251_s
+ ret void
+}
+
+define void @i252_ls(i252 zeroext %x) nounwind {
+ store i252 %x, i252* @i252_s
+ ret void
+}
+
+define void @i253_ls(i253 zeroext %x) nounwind {
+ store i253 %x, i253* @i253_s
+ ret void
+}
+
+define void @i254_ls(i254 zeroext %x) nounwind {
+ store i254 %x, i254* @i254_s
+ ret void
+}
+
+define void @i255_ls(i255 zeroext %x) nounwind {
+ store i255 %x, i255* @i255_s
+ ret void
+}
+
+define void @i256_ls(i256 zeroext %x) nounwind {
+ store i256 %x, i256* @i256_s
+ ret void
+}
diff --git a/test/CodeGen/Generic/BasicInstrs.ll b/test/CodeGen/Generic/BasicInstrs.ll
new file mode 100644
index 0000000..578431e
--- /dev/null
+++ b/test/CodeGen/Generic/BasicInstrs.ll
@@ -0,0 +1,54 @@
+; New testcase, this contains a bunch of simple instructions that should be
+; handled by a code generator.
+
+; RUN: llc < %s
+
+define i32 @add(i32 %A, i32 %B) {
+ %R = add i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @sub(i32 %A, i32 %B) {
+ %R = sub i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @mul(i32 %A, i32 %B) {
+ %R = mul i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @sdiv(i32 %A, i32 %B) {
+ %R = sdiv i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @udiv(i32 %A, i32 %B) {
+ %R = udiv i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @srem(i32 %A, i32 %B) {
+ %R = srem i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @urem(i32 %A, i32 %B) {
+ %R = urem i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @and(i32 %A, i32 %B) {
+ %R = and i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @or(i32 %A, i32 %B) {
+ %R = or i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @xor(i32 %A, i32 %B) {
+ %R = xor i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %R
+}
diff --git a/test/CodeGen/Generic/BurgBadRegAlloc.ll b/test/CodeGen/Generic/BurgBadRegAlloc.ll
new file mode 100644
index 0000000..99d856a
--- /dev/null
+++ b/test/CodeGen/Generic/BurgBadRegAlloc.ll
@@ -0,0 +1,829 @@
+; RUN: llc < %s
+
+;; Register allocation is doing a very poor job on this routine from yyparse
+;; in Burg:
+;; -- at least two long-lived values are being allocated to %o? registers
+;; -- even worse, those registers are being saved and restored repeatedly
+;; at function calls, even though there are no intervening uses.
+;; -- outgoing args of some function calls have to be swapped, causing
+;; another write/read from stack to do the exchange (use -dregalloc=y).
+;;
+%Arity = type %struct.arity*
+ %Binding = type %struct.binding*
+ %DeltaCost = type [4 x i16]
+ %Dimension = type %struct.dimension*
+ %Index_Map = type { i32, %Item_Set* }
+ %IntList = type %struct.intlist*
+ %Item = type { %DeltaCost, %Rule }
+ %ItemArray = type %Item*
+ %Item_Set = type %struct.item_set*
+ %List = type %struct.list*
+ %Mapping = type %struct.mapping*
+ %NonTerminal = type %struct.nonterminal*
+ %Operator = type %struct.operator*
+ %Pattern = type %struct.pattern*
+ %PatternAST = type %struct.patternAST*
+ %Plank = type %struct.plank*
+ %PlankMap = type %struct.plankMap*
+ %ReadFn = type i32 ()*
+ %Rule = type %struct.rule*
+ %RuleAST = type %struct.ruleAST*
+ %StateMap = type %struct.stateMap*
+ %StrTableElement = type %struct.strTableElement*
+ %Symbol = type %struct.symbol*
+ %Table = type %struct.table*
+ %YYSTYPE = type { %IntList }
+ %struct.arity = type { i32, %List }
+ %struct.binding = type { i8*, i32 }
+ %struct.dimension = type { i16*, %Index_Map, %Mapping, i32, %PlankMap }
+ %struct.index_map = type { i32, %Item_Set* }
+ %struct.intlist = type { i32, %IntList }
+ %struct.item = type { %DeltaCost, %Rule }
+ %struct.item_set = type { i32, i32, %Operator, [2 x %Item_Set], %Item_Set, i16*, %ItemArray, %ItemArray }
+ %struct.list = type { i8*, %List }
+ %struct.mapping = type { %List*, i32, i32, i32, %Item_Set* }
+ %struct.nonterminal = type { i8*, i32, i32, i32, %PlankMap, %Rule }
+ %struct.operator = type { i8*, i32, i32, i32, i32, i32, %Table }
+ %struct.pattern = type { %NonTerminal, %Operator, [2 x %NonTerminal] }
+ %struct.patternAST = type { %Symbol, i8*, %List }
+ %struct.plank = type { i8*, %List, i32 }
+ %struct.plankMap = type { %List, i32, %StateMap }
+ %struct.rule = type { %DeltaCost, i32, i32, i32, %NonTerminal, %Pattern, i32 }
+ %struct.ruleAST = type { i8*, %PatternAST, i32, %IntList, %Rule, %StrTableElement, %StrTableElement }
+ %struct.stateMap = type { i8*, %Plank, i32, i16* }
+ %struct.strTableElement = type { i8*, %IntList, i8* }
+ %struct.symbol = type { i8*, i32, { %Operator } }
+ %struct.table = type { %Operator, %List, i16*, [2 x %Dimension], %Item_Set* }
+@yylval = external global %YYSTYPE ; <%YYSTYPE*> [#uses=1]
+@yylhs = external global [25 x i16] ; <[25 x i16]*> [#uses=1]
+@yylen = external global [25 x i16] ; <[25 x i16]*> [#uses=1]
+@yydefred = external global [43 x i16] ; <[43 x i16]*> [#uses=1]
+@yydgoto = external global [12 x i16] ; <[12 x i16]*> [#uses=1]
+@yysindex = external global [43 x i16] ; <[43 x i16]*> [#uses=2]
+@yyrindex = external global [43 x i16] ; <[43 x i16]*> [#uses=1]
+@yygindex = external global [12 x i16] ; <[12 x i16]*> [#uses=1]
+@yytable = external global [263 x i16] ; <[263 x i16]*> [#uses=4]
+@yycheck = external global [263 x i16] ; <[263 x i16]*> [#uses=4]
+@yynerrs = external global i32 ; <i32*> [#uses=3]
+@yyerrflag = external global i32 ; <i32*> [#uses=6]
+@yychar = external global i32 ; <i32*> [#uses=15]
+@yyssp = external global i16* ; <i16**> [#uses=15]
+@yyvsp = external global %YYSTYPE* ; <%YYSTYPE**> [#uses=30]
+@yyval = external global %YYSTYPE ; <%YYSTYPE*> [#uses=1]
+@yyss = external global i16* ; <i16**> [#uses=3]
+@yysslim = external global i16* ; <i16**> [#uses=3]
+@yyvs = external global %YYSTYPE* ; <%YYSTYPE**> [#uses=1]
[email protected] = external global [13 x i8] ; <[13 x i8]*> [#uses=1]
[email protected] = external global [20 x i8] ; <[20 x i8]*> [#uses=1]
+
+define i32 @yyparse() {
+bb0:
+ store i32 0, i32* @yynerrs
+ store i32 0, i32* @yyerrflag
+ store i32 -1, i32* @yychar
+ %reg113 = load i16** @yyss ; <i16*> [#uses=1]
+ %cond581 = icmp ne i16* %reg113, null ; <i1> [#uses=1]
+ br i1 %cond581, label %bb3, label %bb2
+
+bb2: ; preds = %bb0
+ %reg584 = call i32 @yygrowstack( ) ; <i32> [#uses=1]
+ %cond584 = icmp ne i32 %reg584, 0 ; <i1> [#uses=1]
+ br i1 %cond584, label %bb113, label %bb3
+
+bb3: ; preds = %bb2, %bb0
+ %reg115 = load i16** @yyss ; <i16*> [#uses=1]
+ store i16* %reg115, i16** @yyssp
+ %reg116 = load %YYSTYPE** @yyvs ; <%YYSTYPE*> [#uses=1]
+ store %YYSTYPE* %reg116, %YYSTYPE** @yyvsp
+ %reg117 = load i16** @yyssp ; <i16*> [#uses=1]
+ store i16 0, i16* %reg117
+ br label %bb4
+
+bb4: ; preds = %bb112, %bb102, %bb35, %bb31, %bb15, %bb14, %bb3
+ %reg458 = phi i32 [ %reg476, %bb112 ], [ 1, %bb102 ], [ %reg458, %bb35 ], [ %cast768, %bb31 ], [ %cast658, %bb15 ], [ %cast658, %bb14 ], [ 0, %bb3 ] ; <i32> [#uses=2]
+ %reg458-idxcast = zext i32 %reg458 to i64 ; <i64> [#uses=3]
+ %reg594 = getelementptr [43 x i16]* @yydefred, i64 0, i64 %reg458-idxcast ; <i16*> [#uses=1]
+ %reg125 = load i16* %reg594 ; <i16> [#uses=1]
+ %cast599 = sext i16 %reg125 to i32 ; <i32> [#uses=2]
+ %cond600 = icmp ne i32 %cast599, 0 ; <i1> [#uses=1]
+ br i1 %cond600, label %bb36, label %bb5
+
+bb5: ; preds = %bb4
+ %reg127 = load i32* @yychar ; <i32> [#uses=1]
+ %cond603 = icmp sge i32 %reg127, 0 ; <i1> [#uses=1]
+ br i1 %cond603, label %bb8, label %bb6
+
+bb6: ; preds = %bb5
+ %reg607 = call i32 @yylex( ) ; <i32> [#uses=1]
+ store i32 %reg607, i32* @yychar
+ %reg129 = load i32* @yychar ; <i32> [#uses=1]
+ %cond609 = icmp sge i32 %reg129, 0 ; <i1> [#uses=1]
+ br i1 %cond609, label %bb8, label %bb7
+
+bb7: ; preds = %bb6
+ store i32 0, i32* @yychar
+ br label %bb8
+
+bb8: ; preds = %bb7, %bb6, %bb5
+ %reg615 = getelementptr [43 x i16]* @yysindex, i64 0, i64 %reg458-idxcast ; <i16*> [#uses=1]
+ %reg137 = load i16* %reg615 ; <i16> [#uses=1]
+ %cast620 = sext i16 %reg137 to i32 ; <i32> [#uses=2]
+ %cond621 = icmp eq i32 %cast620, 0 ; <i1> [#uses=1]
+ br i1 %cond621, label %bb16, label %bb9
+
+bb9: ; preds = %bb8
+ %reg139 = load i32* @yychar ; <i32> [#uses=2]
+ %reg460 = add i32 %cast620, %reg139 ; <i32> [#uses=3]
+ %cond624 = icmp slt i32 %reg460, 0 ; <i1> [#uses=1]
+ br i1 %cond624, label %bb16, label %bb10
+
+bb10: ; preds = %bb9
+ %cond627 = icmp sgt i32 %reg460, 262 ; <i1> [#uses=1]
+ br i1 %cond627, label %bb16, label %bb11
+
+bb11: ; preds = %bb10
+ %reg460-idxcast = sext i32 %reg460 to i64 ; <i64> [#uses=2]
+ %reg632 = getelementptr [263 x i16]* @yycheck, i64 0, i64 %reg460-idxcast ; <i16*> [#uses=1]
+ %reg148 = load i16* %reg632 ; <i16> [#uses=1]
+ %cast637 = sext i16 %reg148 to i32 ; <i32> [#uses=1]
+ %cond639 = icmp ne i32 %cast637, %reg139 ; <i1> [#uses=1]
+ br i1 %cond639, label %bb16, label %bb12
+
+bb12: ; preds = %bb11
+ %reg150 = load i16** @yyssp ; <i16*> [#uses=1]
+ %cast640 = bitcast i16* %reg150 to i8* ; <i8*> [#uses=1]
+ %reg151 = load i16** @yysslim ; <i16*> [#uses=1]
+ %cast641 = bitcast i16* %reg151 to i8* ; <i8*> [#uses=1]
+ %cond642 = icmp ult i8* %cast640, %cast641 ; <i1> [#uses=1]
+ br i1 %cond642, label %bb14, label %bb13
+
+bb13: ; preds = %bb12
+ %reg644 = call i32 @yygrowstack( ) ; <i32> [#uses=1]
+ %cond644 = icmp ne i32 %reg644, 0 ; <i1> [#uses=1]
+ br i1 %cond644, label %bb113, label %bb14
+
+bb14: ; preds = %bb13, %bb12
+ %reg153 = load i16** @yyssp ; <i16*> [#uses=1]
+ %reg647 = getelementptr i16* %reg153, i64 1 ; <i16*> [#uses=2]
+ store i16* %reg647, i16** @yyssp
+ %reg653 = getelementptr [263 x i16]* @yytable, i64 0, i64 %reg460-idxcast ; <i16*> [#uses=1]
+ %reg162 = load i16* %reg653 ; <i16> [#uses=2]
+ %cast658 = sext i16 %reg162 to i32 ; <i32> [#uses=2]
+ store i16 %reg162, i16* %reg647
+ %reg164 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2]
+ %reg661 = getelementptr %YYSTYPE* %reg164, i64 1 ; <%YYSTYPE*> [#uses=1]
+ store %YYSTYPE* %reg661, %YYSTYPE** @yyvsp
+ %reg167 = load %IntList* getelementptr (%YYSTYPE* @yylval, i64 0, i32 0) ; <%IntList> [#uses=1]
+ %reg661.idx1 = getelementptr %YYSTYPE* %reg164, i64 1, i32 0 ; <%IntList*> [#uses=1]
+ store %IntList %reg167, %IntList* %reg661.idx1
+ store i32 -1, i32* @yychar
+ %reg169 = load i32* @yyerrflag ; <i32> [#uses=2]
+ %cond669 = icmp sle i32 %reg169, 0 ; <i1> [#uses=1]
+ br i1 %cond669, label %bb4, label %bb15
+
+bb15: ; preds = %bb14
+ %reg171 = add i32 %reg169, -1 ; <i32> [#uses=1]
+ store i32 %reg171, i32* @yyerrflag
+ br label %bb4
+
+bb16: ; preds = %bb11, %bb10, %bb9, %bb8
+ %reg677 = getelementptr [43 x i16]* @yyrindex, i64 0, i64 %reg458-idxcast ; <i16*> [#uses=1]
+ %reg178 = load i16* %reg677 ; <i16> [#uses=1]
+ %cast682 = sext i16 %reg178 to i32 ; <i32> [#uses=2]
+ %cond683 = icmp eq i32 %cast682, 0 ; <i1> [#uses=1]
+ br i1 %cond683, label %bb21, label %bb17
+
+bb17: ; preds = %bb16
+ %reg180 = load i32* @yychar ; <i32> [#uses=2]
+ %reg463 = add i32 %cast682, %reg180 ; <i32> [#uses=3]
+ %cond686 = icmp slt i32 %reg463, 0 ; <i1> [#uses=1]
+ br i1 %cond686, label %bb21, label %bb18
+
+bb18: ; preds = %bb17
+ %cond689 = icmp sgt i32 %reg463, 262 ; <i1> [#uses=1]
+ br i1 %cond689, label %bb21, label %bb19
+
+bb19: ; preds = %bb18
+ %reg463-idxcast = sext i32 %reg463 to i64 ; <i64> [#uses=2]
+ %reg694 = getelementptr [263 x i16]* @yycheck, i64 0, i64 %reg463-idxcast ; <i16*> [#uses=1]
+ %reg189 = load i16* %reg694 ; <i16> [#uses=1]
+ %cast699 = sext i16 %reg189 to i32 ; <i32> [#uses=1]
+ %cond701 = icmp ne i32 %cast699, %reg180 ; <i1> [#uses=1]
+ br i1 %cond701, label %bb21, label %bb20
+
+bb20: ; preds = %bb19
+ %reg704 = getelementptr [263 x i16]* @yytable, i64 0, i64 %reg463-idxcast ; <i16*> [#uses=1]
+ %reg197 = load i16* %reg704 ; <i16> [#uses=1]
+ %cast709 = sext i16 %reg197 to i32 ; <i32> [#uses=1]
+ br label %bb36
+
+bb21: ; preds = %bb19, %bb18, %bb17, %bb16
+ %reg198 = load i32* @yyerrflag ; <i32> [#uses=1]
+ %cond711 = icmp ne i32 %reg198, 0 ; <i1> [#uses=1]
+ br i1 %cond711, label %bb23, label %bb22
+
+bb22: ; preds = %bb21
+ call void @yyerror( i8* getelementptr ([13 x i8]* @.LC01, i64 0, i64 0) )
+ %reg200 = load i32* @yynerrs ; <i32> [#uses=1]
+ %reg201 = add i32 %reg200, 1 ; <i32> [#uses=1]
+ store i32 %reg201, i32* @yynerrs
+ br label %bb23
+
+bb23: ; preds = %bb22, %bb21
+ %reg202 = load i32* @yyerrflag ; <i32> [#uses=1]
+ %cond719 = icmp sgt i32 %reg202, 2 ; <i1> [#uses=1]
+ br i1 %cond719, label %bb34, label %bb24
+
+bb24: ; preds = %bb23
+ store i32 3, i32* @yyerrflag
+ %reg241 = load i16** @yyss ; <i16*> [#uses=1]
+ %cast778 = bitcast i16* %reg241 to i8* ; <i8*> [#uses=1]
+ br label %bb25
+
+bb25: ; preds = %bb33, %bb24
+ %reg204 = load i16** @yyssp ; <i16*> [#uses=4]
+ %reg206 = load i16* %reg204 ; <i16> [#uses=1]
+ %reg206-idxcast = sext i16 %reg206 to i64 ; <i64> [#uses=1]
+ %reg727 = getelementptr [43 x i16]* @yysindex, i64 0, i64 %reg206-idxcast ; <i16*> [#uses=1]
+ %reg212 = load i16* %reg727 ; <i16> [#uses=2]
+ %cast732 = sext i16 %reg212 to i32 ; <i32> [#uses=2]
+ %cond733 = icmp eq i32 %cast732, 0 ; <i1> [#uses=1]
+ br i1 %cond733, label %bb32, label %bb26
+
+bb26: ; preds = %bb25
+ %reg466 = add i32 %cast732, 256 ; <i32> [#uses=2]
+ %cond736 = icmp slt i32 %reg466, 0 ; <i1> [#uses=1]
+ br i1 %cond736, label %bb32, label %bb27
+
+bb27: ; preds = %bb26
+ %cond739 = icmp sgt i32 %reg466, 262 ; <i1> [#uses=1]
+ br i1 %cond739, label %bb32, label %bb28
+
+bb28: ; preds = %bb27
+ %reg212-idxcast = sext i16 %reg212 to i64 ; <i64> [#uses=1]
+ %reg212-idxcast-offset = add i64 %reg212-idxcast, 256 ; <i64> [#uses=2]
+ %reg744 = getelementptr [263 x i16]* @yycheck, i64 0, i64 %reg212-idxcast-offset ; <i16*> [#uses=1]
+ %reg221 = load i16* %reg744 ; <i16> [#uses=1]
+ %cond748 = icmp ne i16 %reg221, 256 ; <i1> [#uses=1]
+ br i1 %cond748, label %bb32, label %bb29
+
+bb29: ; preds = %bb28
+ %cast750 = bitcast i16* %reg204 to i8* ; <i8*> [#uses=1]
+ %reg223 = load i16** @yysslim ; <i16*> [#uses=1]
+ %cast751 = bitcast i16* %reg223 to i8* ; <i8*> [#uses=1]
+ %cond752 = icmp ult i8* %cast750, %cast751 ; <i1> [#uses=1]
+ br i1 %cond752, label %bb31, label %bb30
+
+bb30: ; preds = %bb29
+ %reg754 = call i32 @yygrowstack( ) ; <i32> [#uses=1]
+ %cond754 = icmp ne i32 %reg754, 0 ; <i1> [#uses=1]
+ br i1 %cond754, label %bb113, label %bb31
+
+bb31: ; preds = %bb30, %bb29
+ %reg225 = load i16** @yyssp ; <i16*> [#uses=1]
+ %reg757 = getelementptr i16* %reg225, i64 1 ; <i16*> [#uses=2]
+ store i16* %reg757, i16** @yyssp
+ %reg763 = getelementptr [263 x i16]* @yytable, i64 0, i64 %reg212-idxcast-offset ; <i16*> [#uses=1]
+ %reg234 = load i16* %reg763 ; <i16> [#uses=2]
+ %cast768 = sext i16 %reg234 to i32 ; <i32> [#uses=1]
+ store i16 %reg234, i16* %reg757
+ %reg236 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2]
+ %reg771 = getelementptr %YYSTYPE* %reg236, i64 1 ; <%YYSTYPE*> [#uses=1]
+ store %YYSTYPE* %reg771, %YYSTYPE** @yyvsp
+ %reg239 = load %IntList* getelementptr (%YYSTYPE* @yylval, i64 0, i32 0) ; <%IntList> [#uses=1]
+ %reg771.idx1 = getelementptr %YYSTYPE* %reg236, i64 1, i32 0 ; <%IntList*> [#uses=1]
+ store %IntList %reg239, %IntList* %reg771.idx1
+ br label %bb4
+
+bb32: ; preds = %bb28, %bb27, %bb26, %bb25
+ %cast777 = bitcast i16* %reg204 to i8* ; <i8*> [#uses=1]
+ %cond779 = icmp ule i8* %cast777, %cast778 ; <i1> [#uses=1]
+ br i1 %cond779, label %UnifiedExitNode, label %bb33
+
+bb33: ; preds = %bb32
+ %reg781 = getelementptr i16* %reg204, i64 -1 ; <i16*> [#uses=1]
+ store i16* %reg781, i16** @yyssp
+ %reg244 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1]
+ %reg786 = getelementptr %YYSTYPE* %reg244, i64 -1 ; <%YYSTYPE*> [#uses=1]
+ store %YYSTYPE* %reg786, %YYSTYPE** @yyvsp
+ br label %bb25
+
+bb34: ; preds = %bb23
+ %reg246 = load i32* @yychar ; <i32> [#uses=1]
+ %cond791 = icmp eq i32 %reg246, 0 ; <i1> [#uses=1]
+ br i1 %cond791, label %UnifiedExitNode, label %bb35
+
+bb35: ; preds = %bb34
+ store i32 -1, i32* @yychar
+ br label %bb4
+
+bb36: ; preds = %bb20, %bb4
+ %reg468 = phi i32 [ %cast709, %bb20 ], [ %cast599, %bb4 ] ; <i32> [#uses=31]
+ %reg468-idxcast = sext i32 %reg468 to i64 ; <i64> [#uses=2]
+ %reg796 = getelementptr [25 x i16]* @yylen, i64 0, i64 %reg468-idxcast ; <i16*> [#uses=1]
+ %reg254 = load i16* %reg796 ; <i16> [#uses=2]
+ %reg259 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1]
+ %reg254-idxcast = sext i16 %reg254 to i64 ; <i64> [#uses=1]
+ %reg254-idxcast-scale = mul i64 %reg254-idxcast, -1 ; <i64> [#uses=1]
+ %reg254-idxcast-scale-offset = add i64 %reg254-idxcast-scale, 1 ; <i64> [#uses=1]
+ %reg261.idx1 = getelementptr %YYSTYPE* %reg259, i64 %reg254-idxcast-scale-offset, i32 0 ; <%IntList*> [#uses=1]
+ %reg261 = load %IntList* %reg261.idx1 ; <%IntList> [#uses=1]
+ store %IntList %reg261, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ %cond812 = icmp eq i32 %reg468, 13 ; <i1> [#uses=1]
+ br i1 %cond812, label %bb85, label %bb37
+
+bb37: ; preds = %bb36
+ %cond814 = icmp sgt i32 %reg468, 13 ; <i1> [#uses=1]
+ br i1 %cond814, label %bb56, label %bb38
+
+bb38: ; preds = %bb37
+ %cond817 = icmp eq i32 %reg468, 7 ; <i1> [#uses=1]
+ br i1 %cond817, label %bb79, label %bb39
+
+bb39: ; preds = %bb38
+ %cond819 = icmp sgt i32 %reg468, 7 ; <i1> [#uses=1]
+ br i1 %cond819, label %bb48, label %bb40
+
+bb40: ; preds = %bb39
+ %cond822 = icmp eq i32 %reg468, 4 ; <i1> [#uses=1]
+ br i1 %cond822, label %bb76, label %bb41
+
+bb41: ; preds = %bb40
+ %cond824 = icmp sgt i32 %reg468, 4 ; <i1> [#uses=1]
+ br i1 %cond824, label %bb45, label %bb42
+
+bb42: ; preds = %bb41
+ %cond827 = icmp eq i32 %reg468, 2 ; <i1> [#uses=1]
+ br i1 %cond827, label %bb74, label %bb43
+
+bb43: ; preds = %bb42
+ %cond829 = icmp eq i32 %reg468, 3 ; <i1> [#uses=1]
+ br i1 %cond829, label %bb75, label %bb97
+
+bb45: ; preds = %bb41
+ %cond831 = icmp eq i32 %reg468, 5 ; <i1> [#uses=1]
+ br i1 %cond831, label %bb77, label %bb46
+
+bb46: ; preds = %bb45
+ %cond833 = icmp eq i32 %reg468, 6 ; <i1> [#uses=1]
+ br i1 %cond833, label %bb78, label %bb97
+
+bb48: ; preds = %bb39
+ %cond835 = icmp eq i32 %reg468, 10 ; <i1> [#uses=1]
+ br i1 %cond835, label %bb82, label %bb49
+
+bb49: ; preds = %bb48
+ %cond837 = icmp sgt i32 %reg468, 10 ; <i1> [#uses=1]
+ br i1 %cond837, label %bb53, label %bb50
+
+bb50: ; preds = %bb49
+ %cond840 = icmp eq i32 %reg468, 8 ; <i1> [#uses=1]
+ br i1 %cond840, label %bb80, label %bb51
+
+bb51: ; preds = %bb50
+ %cond842 = icmp eq i32 %reg468, 9 ; <i1> [#uses=1]
+ br i1 %cond842, label %bb81, label %bb97
+
+bb53: ; preds = %bb49
+ %cond844 = icmp eq i32 %reg468, 11 ; <i1> [#uses=1]
+ br i1 %cond844, label %bb83, label %bb54
+
+bb54: ; preds = %bb53
+ %cond846 = icmp eq i32 %reg468, 12 ; <i1> [#uses=1]
+ br i1 %cond846, label %bb84, label %bb97
+
+bb56: ; preds = %bb37
+ %cond848 = icmp eq i32 %reg468, 19 ; <i1> [#uses=1]
+ br i1 %cond848, label %bb91, label %bb57
+
+bb57: ; preds = %bb56
+ %cond850 = icmp sgt i32 %reg468, 19 ; <i1> [#uses=1]
+ br i1 %cond850, label %bb66, label %bb58
+
+bb58: ; preds = %bb57
+ %cond853 = icmp eq i32 %reg468, 16 ; <i1> [#uses=1]
+ br i1 %cond853, label %bb88, label %bb59
+
+bb59: ; preds = %bb58
+ %cond855 = icmp sgt i32 %reg468, 16 ; <i1> [#uses=1]
+ br i1 %cond855, label %bb63, label %bb60
+
+bb60: ; preds = %bb59
+ %cond858 = icmp eq i32 %reg468, 14 ; <i1> [#uses=1]
+ br i1 %cond858, label %bb86, label %bb61
+
+bb61: ; preds = %bb60
+ %cond860 = icmp eq i32 %reg468, 15 ; <i1> [#uses=1]
+ br i1 %cond860, label %bb87, label %bb97
+
+bb63: ; preds = %bb59
+ %cond862 = icmp eq i32 %reg468, 17 ; <i1> [#uses=1]
+ br i1 %cond862, label %bb89, label %bb64
+
+bb64: ; preds = %bb63
+ %cond864 = icmp eq i32 %reg468, 18 ; <i1> [#uses=1]
+ br i1 %cond864, label %bb90, label %bb97
+
+bb66: ; preds = %bb57
+ %cond866 = icmp eq i32 %reg468, 22 ; <i1> [#uses=1]
+ br i1 %cond866, label %bb94, label %bb67
+
+bb67: ; preds = %bb66
+ %cond868 = icmp sgt i32 %reg468, 22 ; <i1> [#uses=1]
+ br i1 %cond868, label %bb71, label %bb68
+
+bb68: ; preds = %bb67
+ %cond871 = icmp eq i32 %reg468, 20 ; <i1> [#uses=1]
+ br i1 %cond871, label %bb92, label %bb69
+
+bb69: ; preds = %bb68
+ %cond873 = icmp eq i32 %reg468, 21 ; <i1> [#uses=1]
+ br i1 %cond873, label %bb93, label %bb97
+
+bb71: ; preds = %bb67
+ %cond875 = icmp eq i32 %reg468, 23 ; <i1> [#uses=1]
+ br i1 %cond875, label %bb95, label %bb72
+
+bb72: ; preds = %bb71
+ %cond877 = icmp eq i32 %reg468, 24 ; <i1> [#uses=1]
+ br i1 %cond877, label %bb96, label %bb97
+
+bb74: ; preds = %bb42
+ call void @yyfinished( )
+ br label %bb97
+
+bb75: ; preds = %bb43
+ %reg262 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2]
+ %reg264.idx1 = getelementptr %YYSTYPE* %reg262, i64 -2, i32 0 ; <%IntList*> [#uses=1]
+ %reg264 = load %IntList* %reg264.idx1 ; <%IntList> [#uses=1]
+ %reg265.idx = getelementptr %YYSTYPE* %reg262, i64 0, i32 0 ; <%IntList*> [#uses=1]
+ %reg265 = load %IntList* %reg265.idx ; <%IntList> [#uses=1]
+ %cast889 = bitcast %IntList %reg265 to %List ; <%List> [#uses=1]
+ %cast890 = bitcast %IntList %reg264 to %List ; <%List> [#uses=1]
+ call void @doSpec( %List %cast890, %List %cast889 )
+ br label %bb97
+
+bb76: ; preds = %bb40
+ store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb77: ; preds = %bb45
+ %reg269 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2]
+ %cast894 = getelementptr %YYSTYPE* %reg269, i64 0, i32 0 ; <%IntList*> [#uses=1]
+ %reg271 = load %IntList* %cast894 ; <%IntList> [#uses=1]
+ %reg271.upgrd.1 = bitcast %IntList %reg271 to i8* ; <i8*> [#uses=1]
+ %reg272.idx1 = getelementptr %YYSTYPE* %reg269, i64 -1, i32 0 ; <%IntList*> [#uses=1]
+ %reg272 = load %IntList* %reg272.idx1 ; <%IntList> [#uses=1]
+ %cast901 = bitcast %IntList %reg272 to %List ; <%List> [#uses=1]
+ %reg901 = call %List @newList( i8* %reg271.upgrd.1, %List %cast901 ) ; <%List> [#uses=1]
+ bitcast %List %reg901 to %IntList ; <%IntList>:0 [#uses=1]
+ store %IntList %0, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb78: ; preds = %bb46
+ %reg275 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1]
+ %reg277.idx = getelementptr %YYSTYPE* %reg275, i64 0, i32 0 ; <%IntList*> [#uses=1]
+ %reg277 = load %IntList* %reg277.idx ; <%IntList> [#uses=1]
+ %cast907 = bitcast %IntList %reg277 to %List ; <%List> [#uses=1]
+ %reg907 = call %Arity @newArity( i32 -1, %List %cast907 ) ; <%Arity> [#uses=1]
+ bitcast %Arity %reg907 to %IntList ; <%IntList>:1 [#uses=1]
+ store %IntList %1, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb79: ; preds = %bb38
+ store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ %reg281 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1]
+ %cast912 = getelementptr %YYSTYPE* %reg281, i64 0, i32 0 ; <%IntList*> [#uses=1]
+ %reg282 = load %IntList* %cast912 ; <%IntList> [#uses=1]
+ %reg282.upgrd.2 = bitcast %IntList %reg282 to %List ; <%List> [#uses=1]
+ call void @doGram( %List %reg282.upgrd.2 )
+ br label %bb97
+
+bb80: ; preds = %bb50
+ store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ %reg285 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1]
+ %cast917 = getelementptr %YYSTYPE* %reg285, i64 0, i32 0 ; <%IntList*> [#uses=1]
+ %reg286 = load %IntList* %cast917 ; <%IntList> [#uses=1]
+ %reg286.upgrd.3 = bitcast %IntList %reg286 to i8* ; <i8*> [#uses=1]
+ call void @doStart( i8* %reg286.upgrd.3 )
+ br label %bb97
+
+bb81: ; preds = %bb51
+ store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb82: ; preds = %bb48
+ %reg290 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2]
+ %cast923 = getelementptr %YYSTYPE* %reg290, i64 0, i32 0 ; <%IntList*> [#uses=1]
+ %reg292 = load %IntList* %cast923 ; <%IntList> [#uses=1]
+ %reg292.upgrd.4 = bitcast %IntList %reg292 to i8* ; <i8*> [#uses=1]
+ %reg293.idx1 = getelementptr %YYSTYPE* %reg290, i64 -1, i32 0 ; <%IntList*> [#uses=1]
+ %reg293 = load %IntList* %reg293.idx1 ; <%IntList> [#uses=1]
+ %cast930 = bitcast %IntList %reg293 to %List ; <%List> [#uses=1]
+ %reg930 = call %List @newList( i8* %reg292.upgrd.4, %List %cast930 ) ; <%List> [#uses=1]
+ bitcast %List %reg930 to %IntList ; <%IntList>:2 [#uses=1]
+ store %IntList %2, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb83: ; preds = %bb53
+ store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb84: ; preds = %bb54
+ %reg298 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2]
+ %cast936 = getelementptr %YYSTYPE* %reg298, i64 0, i32 0 ; <%IntList*> [#uses=1]
+ %reg300 = load %IntList* %cast936 ; <%IntList> [#uses=1]
+ %reg300.upgrd.5 = bitcast %IntList %reg300 to i8* ; <i8*> [#uses=1]
+ %reg301.idx1 = getelementptr %YYSTYPE* %reg298, i64 -1, i32 0 ; <%IntList*> [#uses=1]
+ %reg301 = load %IntList* %reg301.idx1 ; <%IntList> [#uses=1]
+ %cast943 = bitcast %IntList %reg301 to %List ; <%List> [#uses=1]
+ %reg943 = call %List @newList( i8* %reg300.upgrd.5, %List %cast943 ) ; <%List> [#uses=1]
+ bitcast %List %reg943 to %IntList ; <%IntList>:3 [#uses=1]
+ store %IntList %3, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb85: ; preds = %bb36
+ %reg304 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2]
+ %cast9521 = getelementptr %YYSTYPE* %reg304, i64 -2, i32 0 ; <%IntList*> [#uses=1]
+ %reg306 = load %IntList* %cast9521 ; <%IntList> [#uses=1]
+ %reg306.upgrd.6 = bitcast %IntList %reg306 to i8* ; <i8*> [#uses=1]
+ %cast953 = bitcast %YYSTYPE* %reg304 to i32* ; <i32*> [#uses=1]
+ %reg307 = load i32* %cast953 ; <i32> [#uses=1]
+ %reg955 = call %Binding @newBinding( i8* %reg306.upgrd.6, i32 %reg307 ) ; <%Binding> [#uses=1]
+ bitcast %Binding %reg955 to %IntList ; <%IntList>:4 [#uses=1]
+ store %IntList %4, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb86: ; preds = %bb60
+ store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb87: ; preds = %bb61
+ %reg312 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2]
+ %cast961 = getelementptr %YYSTYPE* %reg312, i64 0, i32 0 ; <%IntList*> [#uses=1]
+ %reg314 = load %IntList* %cast961 ; <%IntList> [#uses=1]
+ %reg314.upgrd.7 = bitcast %IntList %reg314 to i8* ; <i8*> [#uses=1]
+ %reg315.idx1 = getelementptr %YYSTYPE* %reg312, i64 -1, i32 0 ; <%IntList*> [#uses=1]
+ %reg315 = load %IntList* %reg315.idx1 ; <%IntList> [#uses=1]
+ %cast968 = bitcast %IntList %reg315 to %List ; <%List> [#uses=1]
+ %reg968 = call %List @newList( i8* %reg314.upgrd.7, %List %cast968 ) ; <%List> [#uses=1]
+ bitcast %List %reg968 to %IntList ; <%IntList>:5 [#uses=1]
+ store %IntList %5, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb88: ; preds = %bb58
+ %reg318 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=4]
+ %cast9791 = getelementptr %YYSTYPE* %reg318, i64 -6, i32 0 ; <%IntList*> [#uses=1]
+ %reg322 = load %IntList* %cast9791 ; <%IntList> [#uses=1]
+ %reg322.upgrd.8 = bitcast %IntList %reg322 to i8* ; <i8*> [#uses=1]
+ %reg323.idx1 = getelementptr %YYSTYPE* %reg318, i64 -4, i32 0 ; <%IntList*> [#uses=1]
+ %reg323 = load %IntList* %reg323.idx1 ; <%IntList> [#uses=1]
+ %reg987 = getelementptr %YYSTYPE* %reg318, i64 -2 ; <%YYSTYPE*> [#uses=1]
+ %cast989 = bitcast %YYSTYPE* %reg987 to i32* ; <i32*> [#uses=1]
+ %reg324 = load i32* %cast989 ; <i32> [#uses=1]
+ %reg325.idx1 = getelementptr %YYSTYPE* %reg318, i64 -1, i32 0 ; <%IntList*> [#uses=1]
+ %reg325 = load %IntList* %reg325.idx1 ; <%IntList> [#uses=1]
+ %cast998 = bitcast %IntList %reg323 to %PatternAST ; <%PatternAST> [#uses=1]
+ %reg996 = call %RuleAST @newRuleAST( i8* %reg322.upgrd.8, %PatternAST %cast998, i32 %reg324, %IntList %reg325 ) ; <%RuleAST> [#uses=1]
+ bitcast %RuleAST %reg996 to %IntList ; <%IntList>:6 [#uses=1]
+ store %IntList %6, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb89: ; preds = %bb63
+ %reg328 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1]
+ %cast1002 = getelementptr %YYSTYPE* %reg328, i64 0, i32 0 ; <%IntList*> [#uses=1]
+ %reg329 = load %IntList* %cast1002 ; <%IntList> [#uses=1]
+ %reg329.upgrd.9 = bitcast %IntList %reg329 to i8* ; <i8*> [#uses=1]
+ %reg1004 = call %PatternAST @newPatternAST( i8* %reg329.upgrd.9, %List null ) ; <%PatternAST> [#uses=1]
+ bitcast %PatternAST %reg1004 to %IntList ; <%IntList>:7 [#uses=1]
+ store %IntList %7, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb90: ; preds = %bb64
+ %reg333 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2]
+ %cast10131 = getelementptr %YYSTYPE* %reg333, i64 -1, i32 0 ; <%IntList*> [#uses=1]
+ %reg335 = load %IntList* %cast10131 ; <%IntList> [#uses=1]
+ %reg335.upgrd.10 = bitcast %IntList %reg335 to i8* ; <i8*> [#uses=1]
+ %reg1015 = call %List @newList( i8* %reg335.upgrd.10, %List null ) ; <%List> [#uses=1]
+ %cast10211 = getelementptr %YYSTYPE* %reg333, i64 -3, i32 0 ; <%IntList*> [#uses=1]
+ %reg338 = load %IntList* %cast10211 ; <%IntList> [#uses=1]
+ %reg338.upgrd.11 = bitcast %IntList %reg338 to i8* ; <i8*> [#uses=1]
+ %reg1023 = call %PatternAST @newPatternAST( i8* %reg338.upgrd.11, %List %reg1015 ) ; <%PatternAST> [#uses=1]
+ bitcast %PatternAST %reg1023 to %IntList ; <%IntList>:8 [#uses=1]
+ store %IntList %8, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb91: ; preds = %bb56
+ %reg341 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=3]
+ %cast10331 = getelementptr %YYSTYPE* %reg341, i64 -1, i32 0 ; <%IntList*> [#uses=1]
+ %reg344 = load %IntList* %cast10331 ; <%IntList> [#uses=1]
+ %reg344.upgrd.12 = bitcast %IntList %reg344 to i8* ; <i8*> [#uses=1]
+ %reg1035 = call %List @newList( i8* %reg344.upgrd.12, %List null ) ; <%List> [#uses=1]
+ %cast10411 = getelementptr %YYSTYPE* %reg341, i64 -3, i32 0 ; <%IntList*> [#uses=1]
+ %reg347 = load %IntList* %cast10411 ; <%IntList> [#uses=1]
+ %reg347.upgrd.13 = bitcast %IntList %reg347 to i8* ; <i8*> [#uses=1]
+ %reg1043 = call %List @newList( i8* %reg347.upgrd.13, %List %reg1035 ) ; <%List> [#uses=1]
+ %cast10491 = getelementptr %YYSTYPE* %reg341, i64 -5, i32 0 ; <%IntList*> [#uses=1]
+ %reg349 = load %IntList* %cast10491 ; <%IntList> [#uses=1]
+ %reg349.upgrd.14 = bitcast %IntList %reg349 to i8* ; <i8*> [#uses=1]
+ %reg1051 = call %PatternAST @newPatternAST( i8* %reg349.upgrd.14, %List %reg1043 ) ; <%PatternAST> [#uses=1]
+ bitcast %PatternAST %reg1051 to %IntList ; <%IntList>:9 [#uses=1]
+ store %IntList %9, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb92: ; preds = %bb68
+ store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb93: ; preds = %bb69
+ %reg354 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2]
+ %reg1059 = getelementptr %YYSTYPE* %reg354, i64 -2 ; <%YYSTYPE*> [#uses=1]
+ %cast1061 = bitcast %YYSTYPE* %reg1059 to i32* ; <i32*> [#uses=1]
+ %reg356 = load i32* %cast1061 ; <i32> [#uses=1]
+ %reg357.idx1 = getelementptr %YYSTYPE* %reg354, i64 -1, i32 0 ; <%IntList*> [#uses=1]
+ %reg357 = load %IntList* %reg357.idx1 ; <%IntList> [#uses=1]
+ %reg1068 = call %IntList @newIntList( i32 %reg356, %IntList %reg357 ) ; <%IntList> [#uses=1]
+ store %IntList %reg1068, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb94: ; preds = %bb66
+ store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb95: ; preds = %bb71
+ %reg362 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2]
+ %reg1076 = getelementptr %YYSTYPE* %reg362, i64 -1 ; <%YYSTYPE*> [#uses=1]
+ %cast1078 = bitcast %YYSTYPE* %reg1076 to i32* ; <i32*> [#uses=1]
+ %reg364 = load i32* %cast1078 ; <i32> [#uses=1]
+ %reg365.idx = getelementptr %YYSTYPE* %reg362, i64 0, i32 0 ; <%IntList*> [#uses=1]
+ %reg365 = load %IntList* %reg365.idx ; <%IntList> [#uses=1]
+ %reg1081 = call %IntList @newIntList( i32 %reg364, %IntList %reg365 ) ; <%IntList> [#uses=1]
+ store %IntList %reg1081, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb96: ; preds = %bb72
+ %reg368 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2]
+ %reg1088 = getelementptr %YYSTYPE* %reg368, i64 -1 ; <%YYSTYPE*> [#uses=1]
+ %cast1090 = bitcast %YYSTYPE* %reg1088 to i32* ; <i32*> [#uses=1]
+ %reg370 = load i32* %cast1090 ; <i32> [#uses=1]
+ %reg371.idx = getelementptr %YYSTYPE* %reg368, i64 0, i32 0 ; <%IntList*> [#uses=1]
+ %reg371 = load %IntList* %reg371.idx ; <%IntList> [#uses=1]
+ %reg1093 = call %IntList @newIntList( i32 %reg370, %IntList %reg371 ) ; <%IntList> [#uses=1]
+ store %IntList %reg1093, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0)
+ br label %bb97
+
+bb97: ; preds = %bb96, %bb95, %bb94, %bb93, %bb92, %bb91, %bb90, %bb89, %bb88, %bb87, %bb86, %bb85, %bb84, %bb83, %bb82, %bb81, %bb80, %bb79, %bb78, %bb77, %bb76, %bb75, %bb74, %bb72, %bb69, %bb64, %bb61, %bb54, %bb51, %bb46, %bb43
+ %cast1097 = sext i16 %reg254 to i64 ; <i64> [#uses=3]
+ %reg375 = add i64 %cast1097, %cast1097 ; <i64> [#uses=1]
+ %reg377 = load i16** @yyssp ; <i16*> [#uses=1]
+ %cast379 = ptrtoint i16* %reg377 to i64 ; <i64> [#uses=1]
+ %reg381 = sub i64 %cast379, %reg375 ; <i64> [#uses=1]
+ %cast1099 = inttoptr i64 %reg381 to i16* ; <i16*> [#uses=1]
+ store i16* %cast1099, i16** @yyssp
+ %reg382 = load i16** @yyssp ; <i16*> [#uses=3]
+ %reg383 = load i16* %reg382 ; <i16> [#uses=1]
+ %cast1103 = sext i16 %reg383 to i32 ; <i32> [#uses=3]
+ %reg385 = mul i64 %cast1097, 8 ; <i64> [#uses=1]
+ %reg387 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1]
+ %cast389 = ptrtoint %YYSTYPE* %reg387 to i64 ; <i64> [#uses=1]
+ %reg391 = sub i64 %cast389, %reg385 ; <i64> [#uses=1]
+ %cast1108 = inttoptr i64 %reg391 to %YYSTYPE* ; <%YYSTYPE*> [#uses=1]
+ store %YYSTYPE* %cast1108, %YYSTYPE** @yyvsp
+ %reg1111 = getelementptr [25 x i16]* @yylhs, i64 0, i64 %reg468-idxcast ; <i16*> [#uses=1]
+ %reg398 = load i16* %reg1111 ; <i16> [#uses=2]
+ %cast1116 = sext i16 %reg398 to i32 ; <i32> [#uses=1]
+ %cond1117 = icmp ne i32 %cast1103, 0 ; <i1> [#uses=1]
+ br i1 %cond1117, label %bb104, label %bb98
+
+bb98: ; preds = %bb97
+ %cond1119 = icmp ne i32 %cast1116, 0 ; <i1> [#uses=1]
+ br i1 %cond1119, label %bb104, label %bb99
+
+bb99: ; preds = %bb98
+ %reg1122 = getelementptr i16* %reg382, i64 1 ; <i16*> [#uses=2]
+ store i16* %reg1122, i16** @yyssp
+ store i16 1, i16* %reg1122
+ %reg403 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2]
+ %reg1128 = getelementptr %YYSTYPE* %reg403, i64 1 ; <%YYSTYPE*> [#uses=1]
+ store %YYSTYPE* %reg1128, %YYSTYPE** @yyvsp
+ %reg406 = load %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) ; <%IntList> [#uses=1]
+ %reg1128.idx1 = getelementptr %YYSTYPE* %reg403, i64 1, i32 0 ; <%IntList*> [#uses=1]
+ store %IntList %reg406, %IntList* %reg1128.idx1
+ %reg407 = load i32* @yychar ; <i32> [#uses=1]
+ %cond1135 = icmp sge i32 %reg407, 0 ; <i1> [#uses=1]
+ br i1 %cond1135, label %bb102, label %bb100
+
+bb100: ; preds = %bb99
+ %reg1139 = call i32 @yylex( ) ; <i32> [#uses=1]
+ store i32 %reg1139, i32* @yychar
+ %reg409 = load i32* @yychar ; <i32> [#uses=1]
+ %cond1141 = icmp sge i32 %reg409, 0 ; <i1> [#uses=1]
+ br i1 %cond1141, label %bb102, label %bb101
+
+bb101: ; preds = %bb100
+ store i32 0, i32* @yychar
+ br label %bb102
+
+bb102: ; preds = %bb101, %bb100, %bb99
+ %reg411 = load i32* @yychar ; <i32> [#uses=1]
+ %cond1146 = icmp ne i32 %reg411, 0 ; <i1> [#uses=1]
+ br i1 %cond1146, label %bb4, label %UnifiedExitNode
+
+bb104: ; preds = %bb98, %bb97
+ %reg398-idxcast = sext i16 %reg398 to i64 ; <i64> [#uses=2]
+ %reg1150 = getelementptr [12 x i16]* @yygindex, i64 0, i64 %reg398-idxcast ; <i16*> [#uses=1]
+ %reg418 = load i16* %reg1150 ; <i16> [#uses=1]
+ %cast1155 = sext i16 %reg418 to i32 ; <i32> [#uses=2]
+ %cond1156 = icmp eq i32 %cast1155, 0 ; <i1> [#uses=1]
+ br i1 %cond1156, label %bb109, label %bb105
+
+bb105: ; preds = %bb104
+ %reg473 = add i32 %cast1155, %cast1103 ; <i32> [#uses=3]
+ %cond1158 = icmp slt i32 %reg473, 0 ; <i1> [#uses=1]
+ br i1 %cond1158, label %bb109, label %bb106
+
+bb106: ; preds = %bb105
+ %cond1161 = icmp sgt i32 %reg473, 262 ; <i1> [#uses=1]
+ br i1 %cond1161, label %bb109, label %bb107
+
+bb107: ; preds = %bb106
+ %reg473-idxcast = sext i32 %reg473 to i64 ; <i64> [#uses=2]
+ %reg1166 = getelementptr [263 x i16]* @yycheck, i64 0, i64 %reg473-idxcast ; <i16*> [#uses=1]
+ %reg428 = load i16* %reg1166 ; <i16> [#uses=1]
+ %cast1171 = sext i16 %reg428 to i32 ; <i32> [#uses=1]
+ %cond1172 = icmp ne i32 %cast1171, %cast1103 ; <i1> [#uses=1]
+ br i1 %cond1172, label %bb109, label %bb108
+
+bb108: ; preds = %bb107
+ %reg1175 = getelementptr [263 x i16]* @yytable, i64 0, i64 %reg473-idxcast ; <i16*> [#uses=1]
+ %reg435 = load i16* %reg1175 ; <i16> [#uses=1]
+ %cast1180 = sext i16 %reg435 to i32 ; <i32> [#uses=1]
+ br label %bb110
+
+bb109: ; preds = %bb107, %bb106, %bb105, %bb104
+ %reg1183 = getelementptr [12 x i16]* @yydgoto, i64 0, i64 %reg398-idxcast ; <i16*> [#uses=1]
+ %reg442 = load i16* %reg1183 ; <i16> [#uses=1]
+ %cast1188 = sext i16 %reg442 to i32 ; <i32> [#uses=1]
+ br label %bb110
+
+bb110: ; preds = %bb109, %bb108
+ %reg476 = phi i32 [ %cast1188, %bb109 ], [ %cast1180, %bb108 ] ; <i32> [#uses=2]
+ %cast1189 = bitcast i16* %reg382 to i8* ; <i8*> [#uses=1]
+ %reg444 = load i16** @yysslim ; <i16*> [#uses=1]
+ %cast1190 = bitcast i16* %reg444 to i8* ; <i8*> [#uses=1]
+ %cond1191 = icmp ult i8* %cast1189, %cast1190 ; <i1> [#uses=1]
+ br i1 %cond1191, label %bb112, label %bb111
+
+bb111: ; preds = %bb110
+ %reg1193 = call i32 @yygrowstack( ) ; <i32> [#uses=1]
+ %cond1193 = icmp ne i32 %reg1193, 0 ; <i1> [#uses=1]
+ br i1 %cond1193, label %bb113, label %bb112
+
+bb112: ; preds = %bb111, %bb110
+ %reg446 = load i16** @yyssp ; <i16*> [#uses=1]
+ %reg1196 = getelementptr i16* %reg446, i64 1 ; <i16*> [#uses=2]
+ store i16* %reg1196, i16** @yyssp
+ %cast1357 = trunc i32 %reg476 to i16 ; <i16> [#uses=1]
+ store i16 %cast1357, i16* %reg1196
+ %reg449 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2]
+ %reg1202 = getelementptr %YYSTYPE* %reg449, i64 1 ; <%YYSTYPE*> [#uses=1]
+ store %YYSTYPE* %reg1202, %YYSTYPE** @yyvsp
+ %reg452 = load %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) ; <%IntList> [#uses=1]
+ %reg1202.idx1 = getelementptr %YYSTYPE* %reg449, i64 1, i32 0 ; <%IntList*> [#uses=1]
+ store %IntList %reg452, %IntList* %reg1202.idx1
+ br label %bb4
+
+bb113: ; preds = %bb111, %bb30, %bb13, %bb2
+ call void @yyerror( i8* getelementptr ([20 x i8]* @.LC1, i64 0, i64 0) )
+ br label %UnifiedExitNode
+
+UnifiedExitNode: ; preds = %bb113, %bb102, %bb34, %bb32
+ %UnifiedRetVal = phi i32 [ 1, %bb113 ], [ 1, %bb34 ], [ 1, %bb32 ], [ 0, %bb102 ] ; <i32> [#uses=1]
+ ret i32 %UnifiedRetVal
+}
+
+declare %List @newList(i8*, %List)
+
+declare %IntList @newIntList(i32, %IntList)
+
+declare void @doStart(i8*)
+
+declare void @yyerror(i8*)
+
+declare void @doSpec(%List, %List)
+
+declare %Arity @newArity(i32, %List)
+
+declare %Binding @newBinding(i8*, i32)
+
+declare %PatternAST @newPatternAST(i8*, %List)
+
+declare %RuleAST @newRuleAST(i8*, %PatternAST, i32, %IntList)
+
+declare void @yyfinished()
+
+declare i32 @yylex()
+
+declare void @doGram(%List)
+
+declare i32 @yygrowstack()
diff --git a/test/CodeGen/Generic/ConstantExprLowering.ll b/test/CodeGen/Generic/ConstantExprLowering.ll
new file mode 100644
index 0000000..428d712
--- /dev/null
+++ b/test/CodeGen/Generic/ConstantExprLowering.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s
+
[email protected]_1 = internal constant [16 x i8] c"%d %d %d %d %d\0A\00" ; <[16 x i8]*> [#uses=1]
+@XA = external global i32 ; <i32*> [#uses=1]
+@XB = external global i32 ; <i32*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define void @test(i32 %A, i32 %B, i32 %C, i32 %D) {
+entry:
+ %t1 = icmp slt i32 %A, 0 ; <i1> [#uses=1]
+ br i1 %t1, label %less, label %not_less
+
+less: ; preds = %entry
+ br label %not_less
+
+not_less: ; preds = %less, %entry
+ %t2 = phi i32 [ sub (i32 ptrtoint (i32* @XA to i32), i32 ptrtoint (i32* @XB to i32)), %less ], [ sub (i32 ptrtoint (i32* @XA to i32), i32 ptrtoint (i32* @XB to i32)), %entry ] ; <i32> [#uses=1]
+ %tmp.39 = call i32 (i8*, ...)* @printf( i8* getelementptr ([16 x i8]* @.str_1, i64 0, i64 0), i32 %t2 ) ; <i32> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/Generic/GC/alloc_loop.ll b/test/CodeGen/Generic/GC/alloc_loop.ll
new file mode 100644
index 0000000..fb78ba2
--- /dev/null
+++ b/test/CodeGen/Generic/GC/alloc_loop.ll
@@ -0,0 +1,53 @@
+; RUN: llc < %s
+
+
+declare i8* @llvm_gc_allocate(i32)
+declare void @llvm_gc_initialize(i32)
+
+declare void @llvm.gcroot(i8**, i8*)
+declare void @llvm.gcwrite(i8*, i8*, i8**)
+
+define i32 @main() gc "shadow-stack" {
+entry:
+ %A = alloca i8*
+ %B = alloca i8**
+
+ call void @llvm_gc_initialize(i32 1048576) ; Start with 1MB heap
+
+ ;; void *A;
+ call void @llvm.gcroot(i8** %A, i8* null)
+
+ ;; A = gcalloc(10);
+ %Aptr = call i8* @llvm_gc_allocate(i32 10)
+ store i8* %Aptr, i8** %A
+
+ ;; void **B;
+ %tmp.1 = bitcast i8*** %B to i8**
+ call void @llvm.gcroot(i8** %tmp.1, i8* null)
+
+ ;; B = gcalloc(4);
+ %B.upgrd.1 = call i8* @llvm_gc_allocate(i32 8)
+ %tmp.2 = bitcast i8* %B.upgrd.1 to i8**
+ store i8** %tmp.2, i8*** %B
+
+ ;; *B = A;
+ %B.1 = load i8*** %B
+ %A.1 = load i8** %A
+ call void @llvm.gcwrite(i8* %A.1, i8* %B.upgrd.1, i8** %B.1)
+
+ br label %AllocLoop
+
+AllocLoop:
+ %i = phi i32 [ 0, %entry ], [ %indvar.next, %AllocLoop ]
+ ;; Allocated mem: allocated memory is immediately dead.
+ call i8* @llvm_gc_allocate(i32 100)
+
+ %indvar.next = add i32 %i, 1
+ %exitcond = icmp eq i32 %indvar.next, 10000000
+ br i1 %exitcond, label %Exit, label %AllocLoop
+
+Exit:
+ ret i32 0
+}
+
+declare void @__main()
diff --git a/test/CodeGen/Generic/GC/argpromotion.ll b/test/CodeGen/Generic/GC/argpromotion.ll
new file mode 100644
index 0000000..dda376d
--- /dev/null
+++ b/test/CodeGen/Generic/GC/argpromotion.ll
@@ -0,0 +1,19 @@
+; RUN: opt < %s -anders-aa -argpromotion
+
+declare void @llvm.gcroot(i8**, i8*)
+
+define i32 @g() {
+entry:
+ %var = alloca i32
+ store i32 1, i32* %var
+ %x = call i32 @f(i32* %var)
+ ret i32 %x
+}
+
+define internal i32 @f(i32* %xp) gc "example" {
+entry:
+ %var = alloca i8*
+ call void @llvm.gcroot(i8** %var, i8* null)
+ %x = load i32* %xp
+ ret i32 %x
+}
diff --git a/test/CodeGen/Generic/GC/badreadproto.ll b/test/CodeGen/Generic/GC/badreadproto.ll
new file mode 100644
index 0000000..4fe90b9
--- /dev/null
+++ b/test/CodeGen/Generic/GC/badreadproto.ll
@@ -0,0 +1,13 @@
+; RUN: not llvm-as < %s >& /dev/null
+
+ %list = type { i32, %list* }
+
+; This usage is invalid now; instead, objects must be bitcast to i8* for input
+; to the gc intrinsics.
+declare %list* @llvm.gcread(%list*, %list**)
+
+define %list* @tl(%list* %l) gc "example" {
+ %hd.ptr = getelementptr %list* %l, i32 0, i32 0
+ %hd = call %list* @llvm.gcread(%list* %l, %list** %hd.ptr)
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Generic/GC/badrootproto.ll b/test/CodeGen/Generic/GC/badrootproto.ll
new file mode 100644
index 0000000..ff86d03
--- /dev/null
+++ b/test/CodeGen/Generic/GC/badrootproto.ll
@@ -0,0 +1,13 @@
+; RUN: not llvm-as < %s >& /dev/null
+
+ %list = type { i32, %list* }
+ %meta = type opaque
+
+; This usage is invalid now; instead, objects must be bitcast to i8* for input
+; to the gc intrinsics.
+declare void @llvm.gcroot(%list*, %meta*)
+
+define void @root() gc "example" {
+ %x.var = alloca i8*
+ call void @llvm.gcroot(i8** %x.var, %meta* null)
+}
diff --git a/test/CodeGen/Generic/GC/badwriteproto.ll b/test/CodeGen/Generic/GC/badwriteproto.ll
new file mode 100644
index 0000000..be81f84
--- /dev/null
+++ b/test/CodeGen/Generic/GC/badwriteproto.ll
@@ -0,0 +1,22 @@
+; RUN: not llvm-as < %s >& /dev/null
+
+ %list = type { i32, %list* }
+
+; This usage is invalid now; instead, objects must be bitcast to i8* for input
+; to the gc intrinsics.
+declare void @llvm.gcwrite(%list*, %list*, %list**)
+
+define %list* @cons(i32 %hd, %list* %tl) gc "example" {
+ %tmp = call i8* @gcalloc(i32 bitcast(%list* getelementptr(%list* null, i32 1) to i32))
+ %cell = bitcast i8* %tmp to %list*
+
+ %hd.ptr = getelementptr %list* %cell, i32 0, i32 0
+ store i32 %hd, i32* %hd.ptr
+
+ %tl.ptr = getelementptr %list* %cell, i32 0, i32 0
+ call void @llvm.gcwrite(%list* %tl, %list* %cell, %list** %tl.ptr)
+
+ ret %cell.2
+}
+
+declare i8* @gcalloc(i32)
diff --git a/test/CodeGen/Generic/GC/deadargelim.ll b/test/CodeGen/Generic/GC/deadargelim.ll
new file mode 100644
index 0000000..1760190
--- /dev/null
+++ b/test/CodeGen/Generic/GC/deadargelim.ll
@@ -0,0 +1,16 @@
+; RUN: opt < %s -deadargelim
+
+declare void @llvm.gcroot(i8**, i8*)
+
+define void @g() {
+entry:
+ call void @f(i32 0)
+ ret void
+}
+
+define internal void @f(i32 %unused) gc "example" {
+entry:
+ %var = alloca i8*
+ call void @llvm.gcroot(i8** %var, i8* null)
+ ret void
+}
diff --git a/test/CodeGen/Generic/GC/dg.exp b/test/CodeGen/Generic/GC/dg.exp
new file mode 100644
index 0000000..f200589
--- /dev/null
+++ b/test/CodeGen/Generic/GC/dg.exp
@@ -0,0 +1,3 @@
+load_lib llvm.exp
+
+RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
diff --git a/test/CodeGen/Generic/GC/fat.ll b/test/CodeGen/Generic/GC/fat.ll
new file mode 100644
index 0000000..d05ca3d
--- /dev/null
+++ b/test/CodeGen/Generic/GC/fat.ll
@@ -0,0 +1,10 @@
+; RUN: not llvm-as < %s >& /dev/null
+
+declare void @llvm.gcroot(i8**, i8*) nounwind
+
+define void @f() gc "x" {
+ %st = alloca { i8*, i1 } ; <{ i8*, i1 }*> [#uses=1]
+ %st_ptr = bitcast { i8*, i1 }* %st to i8** ; <i8**> [#uses=1]
+ call void @llvm.gcroot(i8** %st_ptr, i8* null)
+ ret void
+}
diff --git a/test/CodeGen/Generic/GC/inline.ll b/test/CodeGen/Generic/GC/inline.ll
new file mode 100644
index 0000000..9da33ae
--- /dev/null
+++ b/test/CodeGen/Generic/GC/inline.ll
@@ -0,0 +1,23 @@
+; RUN: opt < %s -inline -S | grep example
+
+ %IntArray = type { i32, [0 x i32*] }
+
+declare void @llvm.gcroot(i8**, i8*) nounwind
+
+define i32 @f() {
+ %x = call i32 @g( ) ; <i32> [#uses=1]
+ ret i32 %x
+}
+
+define internal i32 @g() gc "example" {
+ %root = alloca i8* ; <i8**> [#uses=2]
+ call void @llvm.gcroot( i8** %root, i8* null )
+ %obj = call %IntArray* @h( ) ; <%IntArray*> [#uses=2]
+ %obj.2 = bitcast %IntArray* %obj to i8* ; <i8*> [#uses=1]
+ store i8* %obj.2, i8** %root
+ %Length.ptr = getelementptr %IntArray* %obj, i32 0, i32 0 ; <i32*> [#uses=1]
+ %Length = load i32* %Length.ptr ; <i32> [#uses=1]
+ ret i32 %Length
+}
+
+declare %IntArray* @h()
diff --git a/test/CodeGen/Generic/GC/inline2.ll b/test/CodeGen/Generic/GC/inline2.ll
new file mode 100644
index 0000000..1594705
--- /dev/null
+++ b/test/CodeGen/Generic/GC/inline2.ll
@@ -0,0 +1,24 @@
+; RUN: opt < %s -inline -S | grep sample
+; RUN: opt < %s -inline -S | grep example
+
+ %IntArray = type { i32, [0 x i32*] }
+
+declare void @llvm.gcroot(i8**, i8*) nounwind
+
+define i32 @f() gc "sample" {
+ %x = call i32 @g( ) ; <i32> [#uses=1]
+ ret i32 %x
+}
+
+define internal i32 @g() gc "example" {
+ %root = alloca i8* ; <i8**> [#uses=2]
+ call void @llvm.gcroot( i8** %root, i8* null )
+ %obj = call %IntArray* @h( ) ; <%IntArray*> [#uses=2]
+ %obj.2 = bitcast %IntArray* %obj to i8* ; <i8*> [#uses=1]
+ store i8* %obj.2, i8** %root
+ %Length.ptr = getelementptr %IntArray* %obj, i32 0, i32 0 ; <i32*> [#uses=1]
+ %Length = load i32* %Length.ptr ; <i32> [#uses=1]
+ ret i32 %Length
+}
+
+declare %IntArray* @h()
diff --git a/test/CodeGen/Generic/GC/lower_gcroot.ll b/test/CodeGen/Generic/GC/lower_gcroot.ll
new file mode 100644
index 0000000..c2d418a
--- /dev/null
+++ b/test/CodeGen/Generic/GC/lower_gcroot.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+
+ %Env = type i8*
+
+define void @.main(%Env) gc "shadow-stack" {
+ %Root = alloca %Env
+ call void @llvm.gcroot( %Env* %Root, %Env null )
+ unreachable
+}
+
+declare void @llvm.gcroot(%Env*, %Env)
diff --git a/test/CodeGen/Generic/GC/outside.ll b/test/CodeGen/Generic/GC/outside.ll
new file mode 100644
index 0000000..2968c69
--- /dev/null
+++ b/test/CodeGen/Generic/GC/outside.ll
@@ -0,0 +1,10 @@
+; RUN: not llvm-as < %s >& /dev/null
+
+declare void @llvm.gcroot(i8**, i8*)
+
+define void @f(i8* %x) {
+ %root = alloca i8*
+ call void @llvm.gcroot(i8** %root, i8* null)
+ store i8* %x, i8** %root
+ ret void
+}
diff --git a/test/CodeGen/Generic/GC/redundant_init.ll b/test/CodeGen/Generic/GC/redundant_init.ll
new file mode 100644
index 0000000..10c70e7
--- /dev/null
+++ b/test/CodeGen/Generic/GC/redundant_init.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 | \
+; RUN: ignore grep {movl..0} | count 0
+
+%struct.obj = type { i8*, %struct.obj* }
+
+declare void @g() gc "shadow-stack"
+
+define void @f(i8* %o) gc "shadow-stack" {
+entry:
+ %root = alloca i8*
+ call void @llvm.gcroot(i8** %root, i8* null)
+ store i8* %o, i8** %root
+ call void @g()
+ ret void
+}
+
+declare void @llvm.gcroot(i8**, i8*)
diff --git a/test/CodeGen/Generic/GC/simple_ocaml.ll b/test/CodeGen/Generic/GC/simple_ocaml.ll
new file mode 100644
index 0000000..f765dc0
--- /dev/null
+++ b/test/CodeGen/Generic/GC/simple_ocaml.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s | grep caml.*__frametable
+; RUN: llc < %s -march=x86 | grep {movl .0}
+
+%struct.obj = type { i8*, %struct.obj* }
+
+define %struct.obj* @fun(%struct.obj* %head) gc "ocaml" {
+entry:
+ %gcroot.0 = alloca i8*
+ %gcroot.1 = alloca i8*
+
+ call void @llvm.gcroot(i8** %gcroot.0, i8* null)
+ call void @llvm.gcroot(i8** %gcroot.1, i8* null)
+
+ %local.0 = bitcast i8** %gcroot.0 to %struct.obj**
+ %local.1 = bitcast i8** %gcroot.1 to %struct.obj**
+
+ store %struct.obj* %head, %struct.obj** %local.0
+ br label %bb.loop
+bb.loop:
+ %t0 = load %struct.obj** %local.0
+ %t1 = getelementptr %struct.obj* %t0, i32 0, i32 1
+ %t2 = bitcast %struct.obj* %t0 to i8*
+ %t3 = bitcast %struct.obj** %t1 to i8**
+ %t4 = call i8* @llvm.gcread(i8* %t2, i8** %t3)
+ %t5 = bitcast i8* %t4 to %struct.obj*
+ %t6 = icmp eq %struct.obj* %t5, null
+ br i1 %t6, label %bb.loop, label %bb.end
+bb.end:
+ %t7 = malloc %struct.obj
+ store %struct.obj* %t7, %struct.obj** %local.1
+ %t8 = bitcast %struct.obj* %t7 to i8*
+ %t9 = load %struct.obj** %local.0
+ %t10 = getelementptr %struct.obj* %t9, i32 0, i32 1
+ %t11 = bitcast %struct.obj* %t9 to i8*
+ %t12 = bitcast %struct.obj** %t10 to i8**
+ call void @llvm.gcwrite(i8* %t8, i8* %t11, i8** %t12)
+ ret %struct.obj* %t7
+}
+
+declare void @llvm.gcroot(i8** %value, i8* %tag)
+declare void @llvm.gcwrite(i8* %value, i8* %obj, i8** %field)
+declare i8* @llvm.gcread(i8* %obj, i8** %field)
diff --git a/test/CodeGen/Generic/Makefile b/test/CodeGen/Generic/Makefile
new file mode 100644
index 0000000..26ebc31
--- /dev/null
+++ b/test/CodeGen/Generic/Makefile
@@ -0,0 +1,23 @@
+# Makefile for running ad-hoc custom LLVM tests
+#
+%.bc: %.ll
+ llvm-as $<
+
+%.llc.s: %.bc
+ llc $< -o $@
+
+%.gcc.s: %.c
+ gcc -O0 -S $< -o $@
+
+%.nat: %.s
+ gcc -O0 -lm $< -o $@
+
+%.cbe.out: %.cbe.nat
+ ./$< > $@
+
+%.out: %.nat
+ ./$< > $@
+
+%.clean:
+ rm -f $(patsubst %.clean,%.bc,$@) $(patsubst %.clean,%.*.s,$@) \
+ $(patsubst %.clean,%.*.nat,$@) $(patsubst %.clean,%.*.out,$@)
diff --git a/test/CodeGen/Generic/add-with-overflow-24.ll b/test/CodeGen/Generic/add-with-overflow-24.ll
new file mode 100644
index 0000000..63f5a22
--- /dev/null
+++ b/test/CodeGen/Generic/add-with-overflow-24.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s
+
+@ok = internal constant [4 x i8] c"%d\0A\00"
+@no = internal constant [4 x i8] c"no\0A\00"
+
+define i1 @func1(i24 signext %v1, i24 signext %v2) nounwind {
+entry:
+ %t = call {i24, i1} @llvm.sadd.with.overflow.i24(i24 %v1, i24 %v2)
+ %sum = extractvalue {i24, i1} %t, 0
+ %sum32 = sext i24 %sum to i32
+ %obit = extractvalue {i24, i1} %t, 1
+ br i1 %obit, label %overflow, label %normal
+
+normal:
+ %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum32 ) nounwind
+ ret i1 true
+
+overflow:
+ %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+ ret i1 false
+}
+
+define i1 @func2(i24 zeroext %v1, i24 zeroext %v2) nounwind {
+entry:
+ %t = call {i24, i1} @llvm.uadd.with.overflow.i24(i24 %v1, i24 %v2)
+ %sum = extractvalue {i24, i1} %t, 0
+ %sum32 = zext i24 %sum to i32
+ %obit = extractvalue {i24, i1} %t, 1
+ br i1 %obit, label %carry, label %normal
+
+normal:
+ %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum32 ) nounwind
+ ret i1 true
+
+carry:
+ %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+ ret i1 false
+}
+
+declare i32 @printf(i8*, ...) nounwind
+declare {i24, i1} @llvm.sadd.with.overflow.i24(i24, i24)
+declare {i24, i1} @llvm.uadd.with.overflow.i24(i24, i24)
diff --git a/test/CodeGen/Generic/add-with-overflow.ll b/test/CodeGen/Generic/add-with-overflow.ll
new file mode 100644
index 0000000..0c2c960
--- /dev/null
+++ b/test/CodeGen/Generic/add-with-overflow.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s
+; RUN: llc < %s -fast-isel
+
+@ok = internal constant [4 x i8] c"%d\0A\00"
+@no = internal constant [4 x i8] c"no\0A\00"
+
+define i1 @func1(i32 %v1, i32 %v2) nounwind {
+entry:
+ %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
+ %sum = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %overflow, label %normal
+
+normal:
+ %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+ ret i1 true
+
+overflow:
+ %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+ ret i1 false
+}
+
+define i1 @func2(i32 %v1, i32 %v2) nounwind {
+entry:
+ %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
+ %sum = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %overflow, label %normal
+
+normal:
+ %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+ ret i1 true
+
+overflow:
+ %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+ ret i1 false
+}
+
+declare i32 @printf(i8*, ...) nounwind
+declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32)
+declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32)
diff --git a/test/CodeGen/Generic/asm-large-immediate.ll b/test/CodeGen/Generic/asm-large-immediate.ll
new file mode 100644
index 0000000..605665b
--- /dev/null
+++ b/test/CodeGen/Generic/asm-large-immediate.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s | grep 68719476738
+
+define void @test() {
+entry:
+ tail call void asm sideeffect "/* result: ${0:c} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 )
+ ret void
+}
+
diff --git a/test/CodeGen/Generic/badCallArgLRLLVM.ll b/test/CodeGen/Generic/badCallArgLRLLVM.ll
new file mode 100644
index 0000000..4ed88df
--- /dev/null
+++ b/test/CodeGen/Generic/badCallArgLRLLVM.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s
+
+; This caused a problem because the argument of a call was defined by
+; the return value of another call that appears later in the code.
+; When processing the first call, the second call has not yet been processed
+; so no LiveRange has been created for its return value.
+;
+; llc dies in UltraSparcRegInfo::suggestRegs4CallArgs() with:
+; ERROR: In call instr, no LR for arg: 0x1009e0740
+;
+
+declare i32 @getInt(i32)
+
+define i32 @main(i32 %argc, i8** %argv) {
+bb0:
+ br label %bb2
+
+bb1: ; preds = %bb2
+ %reg222 = call i32 @getInt( i32 %reg218 ) ; <i32> [#uses=1]
+ %reg110 = add i32 %reg222, 1 ; <i32> [#uses=2]
+ %b = icmp sle i32 %reg110, 0 ; <i1> [#uses=1]
+ br i1 %b, label %bb2, label %bb3
+
+bb2: ; preds = %bb1, %bb0
+ %reg218 = call i32 @getInt( i32 %argc ) ; <i32> [#uses=1]
+ br label %bb1
+
+bb3: ; preds = %bb1
+ ret i32 %reg110
+}
+
diff --git a/test/CodeGen/Generic/badFoldGEP.ll b/test/CodeGen/Generic/badFoldGEP.ll
new file mode 100644
index 0000000..2d4474b
--- /dev/null
+++ b/test/CodeGen/Generic/badFoldGEP.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s
+
+;; GetMemInstArgs() folded the two getElementPtr instructions together,
+;; producing an illegal getElementPtr. That's because the type generated
+;; by the last index for the first one is a structure field, not an array
+;; element, and the second one indexes off that structure field.
+;; The code is legal but not type-safe and the two GEPs should not be folded.
+;;
+;; This code fragment is from Spec/CINT2000/197.parser/197.parser.bc,
+;; file post_process.c, function build_domain().
+;; (Modified to replace store with load and return load value.)
+;;
+ %Domain = type { i8*, i32, i32*, i32, i32, i32*, %Domain* }
+@domain_array = external global [497 x %Domain] ; <[497 x %Domain]*> [#uses=2]
+
+declare void @opaque([497 x %Domain]*)
+
+define i32 @main(i32 %argc, i8** %argv) {
+bb0:
+ call void @opaque( [497 x %Domain]* @domain_array )
+ %cann-indvar-idxcast = sext i32 %argc to i64 ; <i64> [#uses=1]
+ %reg841 = getelementptr [497 x %Domain]* @domain_array, i64 0, i64 %cann-indvar-idxcast, i32 3 ; <i32*> [#uses=1]
+ %reg846 = getelementptr i32* %reg841, i64 1 ; <i32*> [#uses=1]
+ %reg820 = load i32* %reg846 ; <i32> [#uses=1]
+ ret i32 %reg820
+}
+
diff --git a/test/CodeGen/Generic/badarg6.ll b/test/CodeGen/Generic/badarg6.ll
new file mode 100644
index 0000000..d6e5ac5
--- /dev/null
+++ b/test/CodeGen/Generic/badarg6.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s
+
+; On this code, llc did not pass the sixth argument (%reg321) to printf.
+; It passed the first five in %o0 - %o4, but never initialized %o5.
[email protected] = internal global [44 x i8] c"\09\09M = %g, I = %g, V = %g\0A\09\09O = %g, E = %g\0A\0A\00" ; <[44 x i8]*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+declare double @opaque(double)
+
+define i32 @main(i32 %argc, i8** %argv) {
+bb25:
+ %b = icmp sle i32 %argc, 2 ; <i1> [#uses=1]
+ br i1 %b, label %bb42, label %bb43
+
+bb42: ; preds = %bb25
+ %reg315 = call double @opaque( double 3.000000e+00 ) ; <double> [#uses=1]
+ %reg316 = call double @opaque( double 3.100000e+00 ) ; <double> [#uses=1]
+ %reg317 = call double @opaque( double 3.200000e+00 ) ; <double> [#uses=1]
+ %reg318 = call double @opaque( double 3.300000e+00 ) ; <double> [#uses=1]
+ %reg319 = call double @opaque( double 3.400000e+00 ) ; <double> [#uses=1]
+ br label %bb43
+
+bb43: ; preds = %bb42, %bb25
+ %reg321 = phi double [ 2.000000e-01, %bb25 ], [ %reg315, %bb42 ] ; <double> [#uses=1]
+ %reg322 = phi double [ 6.000000e+00, %bb25 ], [ %reg316, %bb42 ] ; <double> [#uses=1]
+ %reg323 = phi double [ -1.000000e+00, %bb25 ], [ %reg317, %bb42 ] ; <double> [#uses=1]
+ %reg324 = phi double [ -1.000000e+00, %bb25 ], [ %reg318, %bb42 ] ; <double> [#uses=1]
+ %reg325 = phi double [ 1.000000e+00, %bb25 ], [ %reg319, %bb42 ] ; <double> [#uses=1]
+ %reg609 = call i32 (i8*, ...)* @printf( i8* getelementptr ([44 x i8]* @.LC12, i64 0, i64 0), double %reg325, double %reg324, double %reg323, double %reg322, double %reg321 ) ; <i32> [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/Generic/badlive.ll b/test/CodeGen/Generic/badlive.ll
new file mode 100644
index 0000000..43b03e31
--- /dev/null
+++ b/test/CodeGen/Generic/badlive.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s
+
+define i32 @main() {
+bb0:
+ %reg109 = malloc i32, i32 100 ; <i32*> [#uses=2]
+ br label %bb2
+
+bb2: ; preds = %bb2, %bb0
+ %cann-indvar1 = phi i32 [ 0, %bb0 ], [ %add1-indvar1, %bb2 ] ; <i32> [#uses=2]
+ %reg127 = mul i32 %cann-indvar1, 2 ; <i32> [#uses=1]
+ %add1-indvar1 = add i32 %cann-indvar1, 1 ; <i32> [#uses=1]
+ store i32 999, i32* %reg109
+ %cond1015 = icmp sle i32 1, 99 ; <i1> [#uses=1]
+ %reg128 = add i32 %reg127, 2 ; <i32> [#uses=0]
+ br i1 %cond1015, label %bb2, label %bb4
+
+bb4: ; preds = %bb4, %bb2
+ %cann-indvar = phi i32 [ %add1-indvar, %bb4 ], [ 0, %bb2 ] ; <i32> [#uses=1]
+ %add1-indvar = add i32 %cann-indvar, 1 ; <i32> [#uses=2]
+ store i32 333, i32* %reg109
+ %reg131 = add i32 %add1-indvar, 3 ; <i32> [#uses=1]
+ %cond1017 = icmp ule i32 %reg131, 99 ; <i1> [#uses=1]
+ br i1 %cond1017, label %bb4, label %bb5
+
+bb5: ; preds = %bb4
+ ret i32 0
+}
+
diff --git a/test/CodeGen/Generic/bool-to-double.ll b/test/CodeGen/Generic/bool-to-double.ll
new file mode 100644
index 0000000..81350a4
--- /dev/null
+++ b/test/CodeGen/Generic/bool-to-double.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s
+define double @test(i1 %X) {
+ %Y = uitofp i1 %X to double ; <double> [#uses=1]
+ ret double %Y
+}
+
diff --git a/test/CodeGen/Generic/bool-vector.ll b/test/CodeGen/Generic/bool-vector.ll
new file mode 100644
index 0000000..4758697
--- /dev/null
+++ b/test/CodeGen/Generic/bool-vector.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+; PR1845
+
+define void @boolVectorSelect(<4 x i1>* %boolVectorPtr) {
+Body:
+ %castPtr = bitcast <4 x i1>* %boolVectorPtr to <4 x i1>*
+ %someBools = load <4 x i1>* %castPtr, align 1 ; <<4 x i1>>
+ %internal = alloca <4 x i1>, align 16 ; <<4 x i1>*> [#uses=1]
+ store <4 x i1> %someBools, <4 x i1>* %internal, align 1
+ ret void
+}
diff --git a/test/CodeGen/Generic/call-ret0.ll b/test/CodeGen/Generic/call-ret0.ll
new file mode 100644
index 0000000..a8e00cd5
--- /dev/null
+++ b/test/CodeGen/Generic/call-ret0.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s
+define i32 @foo(i32 %x) {
+ ret i32 %x
+}
+
+define i32 @main() {
+ %r = call i32 @foo( i32 0 ) ; <i32> [#uses=1]
+ ret i32 %r
+}
+
diff --git a/test/CodeGen/Generic/call-ret42.ll b/test/CodeGen/Generic/call-ret42.ll
new file mode 100644
index 0000000..95cc286
--- /dev/null
+++ b/test/CodeGen/Generic/call-ret42.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s
+
+define i32 @foo(i32 %x) {
+ ret i32 42
+}
+
+define i32 @main() {
+ %r = call i32 @foo( i32 15 ) ; <i32> [#uses=1]
+ ret i32 %r
+}
diff --git a/test/CodeGen/Generic/call-void.ll b/test/CodeGen/Generic/call-void.ll
new file mode 100644
index 0000000..9ed4179
--- /dev/null
+++ b/test/CodeGen/Generic/call-void.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+
+define void @foo() {
+ ret void
+}
+
+define i32 @main() {
+ call void @foo( )
+ ret i32 0
+}
+
diff --git a/test/CodeGen/Generic/call2-ret0.ll b/test/CodeGen/Generic/call2-ret0.ll
new file mode 100644
index 0000000..4e57ef8
--- /dev/null
+++ b/test/CodeGen/Generic/call2-ret0.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s
+
+define i32 @bar(i32 %x) {
+ ret i32 0
+}
+
+define i32 @foo(i32 %x) {
+ %q = call i32 @bar( i32 1 ) ; <i32> [#uses=1]
+ ret i32 %q
+}
+
+define i32 @main() {
+ %r = call i32 @foo( i32 2 ) ; <i32> [#uses=1]
+ ret i32 %r
+}
+
diff --git a/test/CodeGen/Generic/cast-fp.ll b/test/CodeGen/Generic/cast-fp.ll
new file mode 100644
index 0000000..590b7ce
--- /dev/null
+++ b/test/CodeGen/Generic/cast-fp.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s
+@a_fstr = internal constant [8 x i8] c"a = %f\0A\00" ; <[8 x i8]*> [#uses=1]
+@a_lstr = internal constant [10 x i8] c"a = %lld\0A\00" ; <[10 x i8]*> [#uses=1]
+@a_dstr = internal constant [8 x i8] c"a = %d\0A\00" ; <[8 x i8]*> [#uses=1]
+@b_dstr = internal constant [8 x i8] c"b = %d\0A\00" ; <[8 x i8]*> [#uses=1]
+@b_fstr = internal constant [8 x i8] c"b = %f\0A\00" ; <[8 x i8]*> [#uses=1]
+@A = global double 2.000000e+00 ; <double*> [#uses=1]
+@B = global i32 2 ; <i32*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+ %a = load double* @A ; <double> [#uses=4]
+ %a_fs = getelementptr [8 x i8]* @a_fstr, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %a_fs, double %a ) ; <i32>:1 [#uses=0]
+ %a_d2l = fptosi double %a to i64 ; <i64> [#uses=1]
+ %a_ls = getelementptr [10 x i8]* @a_lstr, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %a_ls, i64 %a_d2l ) ; <i32>:2 [#uses=0]
+ %a_d2i = fptosi double %a to i32 ; <i32> [#uses=2]
+ %a_ds = getelementptr [8 x i8]* @a_dstr, i64 0, i64 0 ; <i8*> [#uses=3]
+ call i32 (i8*, ...)* @printf( i8* %a_ds, i32 %a_d2i ) ; <i32>:3 [#uses=0]
+ %a_d2sb = fptosi double %a to i8 ; <i8> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %a_ds, i8 %a_d2sb ) ; <i32>:4 [#uses=0]
+ %a_d2i2sb = trunc i32 %a_d2i to i8 ; <i8> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %a_ds, i8 %a_d2i2sb ) ; <i32>:5 [#uses=0]
+ %b = load i32* @B ; <i32> [#uses=2]
+ %b_ds = getelementptr [8 x i8]* @b_dstr, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %b_ds, i32 %b ) ; <i32>:6 [#uses=0]
+ %b_i2d = sitofp i32 %b to double ; <double> [#uses=1]
+ %b_fs = getelementptr [8 x i8]* @b_fstr, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %b_fs, double %b_i2d ) ; <i32>:7 [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/Generic/constindices.ll b/test/CodeGen/Generic/constindices.ll
new file mode 100644
index 0000000..7deb30f
--- /dev/null
+++ b/test/CodeGen/Generic/constindices.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s
+
+; Test that a sequence of constant indices are folded correctly
+; into the equivalent offset at compile-time.
+
+ %MixedA = type { float, [15 x i32], i8, float }
+ %MixedB = type { float, %MixedA, float }
+@fmtArg = internal global [44 x i8] c"sqrt(2) = %g\0Aexp(1) = %g\0Api = %g\0Afive = %g\0A\00" ; <[44 x i8]*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+ %ScalarA = alloca %MixedA ; <%MixedA*> [#uses=1]
+ %ScalarB = alloca %MixedB ; <%MixedB*> [#uses=1]
+ %ArrayA = alloca %MixedA, i32 4 ; <%MixedA*> [#uses=3]
+ %ArrayB = alloca %MixedB, i32 3 ; <%MixedB*> [#uses=2]
+ %I1 = getelementptr %MixedA* %ScalarA, i64 0, i32 0 ; <float*> [#uses=2]
+ store float 0x3FF6A09020000000, float* %I1
+ %I2 = getelementptr %MixedB* %ScalarB, i64 0, i32 1, i32 0 ; <float*> [#uses=2]
+ store float 0x4005BF1420000000, float* %I2
+ %fptrA = getelementptr %MixedA* %ArrayA, i64 1, i32 0 ; <float*> [#uses=1]
+ %fptrB = getelementptr %MixedB* %ArrayB, i64 2, i32 1, i32 0 ; <float*> [#uses=1]
+ store float 0x400921CAC0000000, float* %fptrA
+ store float 5.000000e+00, float* %fptrB
+
+ ;; Test that a sequence of GEPs with constant indices are folded right
+ %fptrA1 = getelementptr %MixedA* %ArrayA, i64 3 ; <%MixedA*> [#uses=1]
+ %fptrA2 = getelementptr %MixedA* %fptrA1, i64 0, i32 1 ; <[15 x i32]*> [#uses=1]
+ %fptrA3 = getelementptr [15 x i32]* %fptrA2, i64 0, i64 8 ; <i32*> [#uses=1]
+ store i32 5, i32* %fptrA3
+ %sqrtTwo = load float* %I1 ; <float> [#uses=1]
+ %exp = load float* %I2 ; <float> [#uses=1]
+ %I3 = getelementptr %MixedA* %ArrayA, i64 1, i32 0 ; <float*> [#uses=1]
+ %pi = load float* %I3 ; <float> [#uses=1]
+ %I4 = getelementptr %MixedB* %ArrayB, i64 2, i32 1, i32 0 ; <float*> [#uses=1]
+ %five = load float* %I4 ; <float> [#uses=1]
+ %dsqrtTwo = fpext float %sqrtTwo to double ; <double> [#uses=1]
+ %dexp = fpext float %exp to double ; <double> [#uses=1]
+ %dpi = fpext float %pi to double ; <double> [#uses=1]
+ %dfive = fpext float %five to double ; <double> [#uses=1]
+ %castFmt = getelementptr [44 x i8]* @fmtArg, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %castFmt, double %dsqrtTwo, double %dexp, double %dpi, double %dfive ) ; <i32>:1 [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/Generic/debug-info.ll b/test/CodeGen/Generic/debug-info.ll
new file mode 100644
index 0000000..20d9f91
--- /dev/null
+++ b/test/CodeGen/Generic/debug-info.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s
+
+ %lldb.compile_unit = type { i32, i16, i16, i8*, i8*, i8*, { }* }
[email protected]_unit7 = external global %lldb.compile_unit ; <%lldb.compile_unit*> [#uses=1]
+
+declare void @llvm.dbg.stoppoint(i32, i32, %lldb.compile_unit*)
+
+define void @rb_raise(i32, ...) {
+entry:
+ br i1 false, label %strlen.exit, label %no_exit.i
+
+no_exit.i: ; preds = %entry
+ ret void
+
+strlen.exit: ; preds = %entry
+ call void @llvm.dbg.stoppoint( i32 4358, i32 0, %lldb.compile_unit* @d.compile_unit7 )
+ unreachable
+}
+
diff --git a/test/CodeGen/Generic/dg.exp b/test/CodeGen/Generic/dg.exp
new file mode 100644
index 0000000..f200589
--- /dev/null
+++ b/test/CodeGen/Generic/dg.exp
@@ -0,0 +1,3 @@
+load_lib llvm.exp
+
+RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
diff --git a/test/CodeGen/Generic/div-neg-power-2.ll b/test/CodeGen/Generic/div-neg-power-2.ll
new file mode 100644
index 0000000..246cd03
--- /dev/null
+++ b/test/CodeGen/Generic/div-neg-power-2.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s
+
+define i32 @test(i32 %X) {
+ %Y = sdiv i32 %X, -2 ; <i32> [#uses=1]
+ ret i32 %Y
+}
+
diff --git a/test/CodeGen/Generic/empty-load-store.ll b/test/CodeGen/Generic/empty-load-store.ll
new file mode 100644
index 0000000..bca7305
--- /dev/null
+++ b/test/CodeGen/Generic/empty-load-store.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s
+; PR2612
+
+@current_foo = internal global { } zeroinitializer
+
+define i32 @foo() {
+entry:
+ %retval = alloca i32
+ store i32 0, i32* %retval
+ %local_foo = alloca { }
+ load { }* @current_foo
+ store { } %0, { }* %local_foo
+ br label %return
+
+return:
+ load i32* %retval
+ ret i32 %1
+}
diff --git a/test/CodeGen/Generic/externally_available.ll b/test/CodeGen/Generic/externally_available.ll
new file mode 100644
index 0000000..7976cc9
--- /dev/null
+++ b/test/CodeGen/Generic/externally_available.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s | not grep test_
+
+; test_function should not be emitted to the .s file.
+define available_externally i32 @test_function() {
+ ret i32 4
+}
+
+; test_global should not be emitted to the .s file.
+@test_global = available_externally global i32 4
+
diff --git a/test/CodeGen/Generic/fastcall.ll b/test/CodeGen/Generic/fastcall.ll
new file mode 100644
index 0000000..35e04f1
--- /dev/null
+++ b/test/CodeGen/Generic/fastcall.ll
@@ -0,0 +1,14 @@
+; Test fastcc works. Test from bug 2770.
+; RUN: llc < %s -relocation-model=pic
+
+
+%struct.__gcov_var = type { i32 }
+@__gcov_var = external global %struct.__gcov_var
+
+define fastcc void @gcov_read_words(i32 %words) {
+entry:
+ store i32 %words, i32* getelementptr (%struct.__gcov_var*
+@__gcov_var,
+i32 0, i32 0)
+ ret void
+}
diff --git a/test/CodeGen/Generic/fneg-fabs.ll b/test/CodeGen/Generic/fneg-fabs.ll
new file mode 100644
index 0000000..2f2f597
--- /dev/null
+++ b/test/CodeGen/Generic/fneg-fabs.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s
+
+define double @fneg(double %X) {
+ %Y = fsub double -0.000000e+00, %X ; <double> [#uses=1]
+ ret double %Y
+}
+
+define float @fnegf(float %X) {
+ %Y = fsub float -0.000000e+00, %X ; <float> [#uses=1]
+ ret float %Y
+}
+
+declare double @fabs(double)
+
+declare float @fabsf(float)
+
+define double @fabstest(double %X) {
+ %Y = call double @fabs( double %X ) ; <double> [#uses=1]
+ ret double %Y
+}
+
+define float @fabsftest(float %X) {
+ %Y = call float @fabsf( float %X ) ; <float> [#uses=1]
+ ret float %Y
+}
+
diff --git a/test/CodeGen/Generic/fp-to-int-invalid.ll b/test/CodeGen/Generic/fp-to-int-invalid.ll
new file mode 100644
index 0000000..cdcc3a2
--- /dev/null
+++ b/test/CodeGen/Generic/fp-to-int-invalid.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s
+; PR4057
+define void @test_cast_float_to_char(i8* %result) nounwind {
+entry:
+ %result_addr = alloca i8* ; <i8**> [#uses=2]
+ %test = alloca float ; <float*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i8* %result, i8** %result_addr
+ store float 0x40B2AFA160000000, float* %test, align 4
+ %0 = load float* %test, align 4 ; <float> [#uses=1]
+ %1 = fptosi float %0 to i8 ; <i8> [#uses=1]
+ %2 = load i8** %result_addr, align 4 ; <i8*> [#uses=1]
+ store i8 %1, i8* %2, align 1
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/Generic/fp_to_int.ll b/test/CodeGen/Generic/fp_to_int.ll
new file mode 100644
index 0000000..ad94413
--- /dev/null
+++ b/test/CodeGen/Generic/fp_to_int.ll
@@ -0,0 +1,81 @@
+; RUN: llc < %s
+
+define i8 @test1(double %X) {
+ %tmp.1 = fptosi double %X to i8 ; <i8> [#uses=1]
+ ret i8 %tmp.1
+}
+
+define i16 @test2(double %X) {
+ %tmp.1 = fptosi double %X to i16 ; <i16> [#uses=1]
+ ret i16 %tmp.1
+}
+
+define i32 @test3(double %X) {
+ %tmp.1 = fptosi double %X to i32 ; <i32> [#uses=1]
+ ret i32 %tmp.1
+}
+
+define i64 @test4(double %X) {
+ %tmp.1 = fptosi double %X to i64 ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
+define i8 @test1u(double %X) {
+ %tmp.1 = fptoui double %X to i8 ; <i8> [#uses=1]
+ ret i8 %tmp.1
+}
+
+define i16 @test2u(double %X) {
+ %tmp.1 = fptoui double %X to i16 ; <i16> [#uses=1]
+ ret i16 %tmp.1
+}
+
+define i32 @test3u(double %X) {
+ %tmp.1 = fptoui double %X to i32 ; <i32> [#uses=1]
+ ret i32 %tmp.1
+}
+
+define i64 @test4u(double %X) {
+ %tmp.1 = fptoui double %X to i64 ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
+define i8 @test1f(float %X) {
+ %tmp.1 = fptosi float %X to i8 ; <i8> [#uses=1]
+ ret i8 %tmp.1
+}
+
+define i16 @test2f(float %X) {
+ %tmp.1 = fptosi float %X to i16 ; <i16> [#uses=1]
+ ret i16 %tmp.1
+}
+
+define i32 @test3f(float %X) {
+ %tmp.1 = fptosi float %X to i32 ; <i32> [#uses=1]
+ ret i32 %tmp.1
+}
+
+define i64 @test4f(float %X) {
+ %tmp.1 = fptosi float %X to i64 ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
+define i8 @test1uf(float %X) {
+ %tmp.1 = fptoui float %X to i8 ; <i8> [#uses=1]
+ ret i8 %tmp.1
+}
+
+define i16 @test2uf(float %X) {
+ %tmp.1 = fptoui float %X to i16 ; <i16> [#uses=1]
+ ret i16 %tmp.1
+}
+
+define i32 @test3uf(float %X) {
+ %tmp.1 = fptoui float %X to i32 ; <i32> [#uses=1]
+ ret i32 %tmp.1
+}
+
+define i64 @test4uf(float %X) {
+ %tmp.1 = fptoui float %X to i64 ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
diff --git a/test/CodeGen/Generic/fpowi-promote.ll b/test/CodeGen/Generic/fpowi-promote.ll
new file mode 100644
index 0000000..8dacebe
--- /dev/null
+++ b/test/CodeGen/Generic/fpowi-promote.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+
+; PR1239
+
+define float @test(float %tmp23302331, i32 %tmp23282329 ) {
+
+%tmp2339 = call float @llvm.powi.f32( float %tmp23302331, i32 %tmp23282329 )
+ ret float %tmp2339
+}
+
+declare float @llvm.powi.f32(float,i32)
diff --git a/test/CodeGen/Generic/fwdtwice.ll b/test/CodeGen/Generic/fwdtwice.ll
new file mode 100644
index 0000000..6b38f04
--- /dev/null
+++ b/test/CodeGen/Generic/fwdtwice.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s
+
+;;
+;; Test the sequence:
+;; cast -> setle 0, %cast -> br %cond
+;; This sequence should cause the cast value to be forwarded twice,
+;; i.e., cast is forwarded to the setle and the setle is forwarded
+;; to the branch.
+;; register argument of the "branch-on-register" instruction, i.e.,
+;;
+;; This produces the bogus output instruction:
+;; brlez <NULL VALUE>, .L_SumArray_bb3.
+;; This came from %bb1 of sumarrray.ll generated from sumarray.c.
+
+define i32 @SumArray(i32 %Num) {
+ %Num.upgrd.1 = alloca i32 ; <i32*> [#uses=2]
+ br label %Top
+
+Top: ; preds = %Top, %0
+ store i32 %Num, i32* %Num.upgrd.1
+ %reg108 = load i32* %Num.upgrd.1 ; <i32> [#uses=1]
+ %cast1006 = bitcast i32 %reg108 to i32 ; <i32> [#uses=1]
+ %cond1001 = icmp ule i32 %cast1006, 0 ; <i1> [#uses=1]
+ br i1 %cond1001, label %bb6, label %Top
+
+bb6: ; preds = %Top
+ ret i32 42
+}
+
diff --git a/test/CodeGen/Generic/getresult-undef.ll b/test/CodeGen/Generic/getresult-undef.ll
new file mode 100644
index 0000000..c675535
--- /dev/null
+++ b/test/CodeGen/Generic/getresult-undef.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s
+
+define double @foo() {
+ %t = getresult {double, double} undef, 1
+ ret double %t
+}
diff --git a/test/CodeGen/Generic/global-ret0.ll b/test/CodeGen/Generic/global-ret0.ll
new file mode 100644
index 0000000..74bff87
--- /dev/null
+++ b/test/CodeGen/Generic/global-ret0.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s
+
+@g = global i32 0 ; <i32*> [#uses=1]
+
+define i32 @main() {
+ %h = load i32* @g ; <i32> [#uses=1]
+ ret i32 %h
+}
diff --git a/test/CodeGen/Generic/hello.ll b/test/CodeGen/Generic/hello.ll
new file mode 100644
index 0000000..705945c
--- /dev/null
+++ b/test/CodeGen/Generic/hello.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+
[email protected]_1 = internal constant [7 x i8] c"hello\0A\00" ; <[7 x i8]*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+ %s = getelementptr [7 x i8]* @.str_1, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %s ) ; <i32>:1 [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/Generic/i128-addsub.ll b/test/CodeGen/Generic/i128-addsub.ll
new file mode 100644
index 0000000..e7cbf4a
--- /dev/null
+++ b/test/CodeGen/Generic/i128-addsub.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s
+
+define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
+entry:
+ %tmp1 = zext i64 %AL to i128 ; <i128> [#uses=1]
+ %tmp23 = zext i64 %AH to i128 ; <i128> [#uses=1]
+ %tmp4 = shl i128 %tmp23, 64 ; <i128> [#uses=1]
+ %tmp5 = or i128 %tmp4, %tmp1 ; <i128> [#uses=1]
+ %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1]
+ %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
+ %tmp11 = shl i128 %tmp89, 64 ; <i128> [#uses=1]
+ %tmp12 = or i128 %tmp11, %tmp67 ; <i128> [#uses=1]
+ %tmp15 = add i128 %tmp12, %tmp5 ; <i128> [#uses=2]
+ %tmp1617 = trunc i128 %tmp15 to i64 ; <i64> [#uses=1]
+ store i64 %tmp1617, i64* %RL
+ %tmp21 = lshr i128 %tmp15, 64 ; <i128> [#uses=1]
+ %tmp2122 = trunc i128 %tmp21 to i64 ; <i64> [#uses=1]
+ store i64 %tmp2122, i64* %RH
+ ret void
+}
+
+define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
+entry:
+ %tmp1 = zext i64 %AL to i128 ; <i128> [#uses=1]
+ %tmp23 = zext i64 %AH to i128 ; <i128> [#uses=1]
+ %tmp4 = shl i128 %tmp23, 64 ; <i128> [#uses=1]
+ %tmp5 = or i128 %tmp4, %tmp1 ; <i128> [#uses=1]
+ %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1]
+ %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
+ %tmp11 = shl i128 %tmp89, 64 ; <i128> [#uses=1]
+ %tmp12 = or i128 %tmp11, %tmp67 ; <i128> [#uses=1]
+ %tmp15 = sub i128 %tmp5, %tmp12 ; <i128> [#uses=2]
+ %tmp1617 = trunc i128 %tmp15 to i64 ; <i64> [#uses=1]
+ store i64 %tmp1617, i64* %RL
+ %tmp21 = lshr i128 %tmp15, 64 ; <i128> [#uses=1]
+ %tmp2122 = trunc i128 %tmp21 to i64 ; <i64> [#uses=1]
+ store i64 %tmp2122, i64* %RH
+ ret void
+}
diff --git a/test/CodeGen/Generic/i128-arith.ll b/test/CodeGen/Generic/i128-arith.ll
new file mode 100644
index 0000000..cf10463
--- /dev/null
+++ b/test/CodeGen/Generic/i128-arith.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+
+define i64 @foo(i64 %x, i64 %y, i32 %amt) {
+ %tmp0 = zext i64 %x to i128
+ %tmp1 = sext i64 %y to i128
+ %tmp2 = or i128 %tmp0, %tmp1
+ %tmp7 = zext i32 13 to i128
+ %tmp3 = lshr i128 %tmp2, %tmp7
+ %tmp4 = trunc i128 %tmp3 to i64
+ ret i64 %tmp4
+}
diff --git a/test/CodeGen/Generic/inline-asm-special-strings.ll b/test/CodeGen/Generic/inline-asm-special-strings.ll
new file mode 100644
index 0000000..d18221e
--- /dev/null
+++ b/test/CodeGen/Generic/inline-asm-special-strings.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s | grep "foo 0 0"
+
+define void @bar() nounwind {
+ tail call void asm sideeffect "foo ${:uid} ${:uid}", ""() nounwind
+ ret void
+}
diff --git a/test/CodeGen/Generic/intrinsics.ll b/test/CodeGen/Generic/intrinsics.ll
new file mode 100644
index 0000000..29bc499
--- /dev/null
+++ b/test/CodeGen/Generic/intrinsics.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s
+
+;; SQRT
+declare float @llvm.sqrt.f32(float)
+
+declare double @llvm.sqrt.f64(double)
+
+define double @test_sqrt(float %F) {
+ %G = call float @llvm.sqrt.f32( float %F ) ; <float> [#uses=1]
+ %H = fpext float %G to double ; <double> [#uses=1]
+ %I = call double @llvm.sqrt.f64( double %H ) ; <double> [#uses=1]
+ ret double %I
+}
+
+
+; SIN
+declare float @sinf(float) readonly
+
+declare double @sin(double) readonly
+
+define double @test_sin(float %F) {
+ %G = call float @sinf( float %F ) ; <float> [#uses=1]
+ %H = fpext float %G to double ; <double> [#uses=1]
+ %I = call double @sin( double %H ) ; <double> [#uses=1]
+ ret double %I
+}
+
+
+; COS
+declare float @cosf(float) readonly
+
+declare double @cos(double) readonly
+
+define double @test_cos(float %F) {
+ %G = call float @cosf( float %F ) ; <float> [#uses=1]
+ %H = fpext float %G to double ; <double> [#uses=1]
+ %I = call double @cos( double %H ) ; <double> [#uses=1]
+ ret double %I
+}
+
diff --git a/test/CodeGen/Generic/invalid-memcpy.ll b/test/CodeGen/Generic/invalid-memcpy.ll
new file mode 100644
index 0000000..8448565
--- /dev/null
+++ b/test/CodeGen/Generic/invalid-memcpy.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s
+
+; This testcase is invalid (the alignment specified for memcpy is
+; greater than the alignment guaranteed for Qux or C.0.1173), but it
+; should compile, not crash the code generator.
+
[email protected] = external constant [33 x i8] ; <[33 x i8]*> [#uses=1]
+
+define void @Bork() {
+entry:
+ %Qux = alloca [33 x i8] ; <[33 x i8]*> [#uses=1]
+ %Qux1 = bitcast [33 x i8]* %Qux to i8* ; <i8*> [#uses=1]
+ call void @llvm.memcpy.i64( i8* %Qux1, i8* getelementptr ([33 x i8]* @C.0.1173, i32 0, i32 0), i64 33, i32 8 )
+ ret void
+}
+
+declare void @llvm.memcpy.i64(i8*, i8*, i64, i32)
+
+
diff --git a/test/CodeGen/Generic/isunord.ll b/test/CodeGen/Generic/isunord.ll
new file mode 100644
index 0000000..ebbba01
--- /dev/null
+++ b/test/CodeGen/Generic/isunord.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s
+
+declare i1 @llvm.isunordered.f64(double, double)
+
+define i1 @test(double %X, double %Y) {
+ %tmp27 = fcmp uno double %X, %Y ; <i1> [#uses=1]
+ ret i1 %tmp27
+}
+
diff --git a/test/CodeGen/Generic/llvm-ct-intrinsics.ll b/test/CodeGen/Generic/llvm-ct-intrinsics.ll
new file mode 100644
index 0000000..1db7549
--- /dev/null
+++ b/test/CodeGen/Generic/llvm-ct-intrinsics.ll
@@ -0,0 +1,62 @@
+; Make sure this testcase is supported by all code generators
+; RUN: llc < %s
+
+declare i64 @llvm.ctpop.i64(i64)
+
+declare i32 @llvm.ctpop.i32(i32)
+
+declare i16 @llvm.ctpop.i16(i16)
+
+declare i8 @llvm.ctpop.i8(i8)
+
+define void @ctpoptest(i8 %A, i16 %B, i32 %C, i64 %D, i8* %AP, i16* %BP, i32* %CP, i64* %DP) {
+ %a = call i8 @llvm.ctpop.i8( i8 %A ) ; <i8> [#uses=1]
+ %b = call i16 @llvm.ctpop.i16( i16 %B ) ; <i16> [#uses=1]
+ %c = call i32 @llvm.ctpop.i32( i32 %C ) ; <i32> [#uses=1]
+ %d = call i64 @llvm.ctpop.i64( i64 %D ) ; <i64> [#uses=1]
+ store i8 %a, i8* %AP
+ store i16 %b, i16* %BP
+ store i32 %c, i32* %CP
+ store i64 %d, i64* %DP
+ ret void
+}
+
+declare i64 @llvm.ctlz.i64(i64)
+
+declare i32 @llvm.ctlz.i32(i32)
+
+declare i16 @llvm.ctlz.i16(i16)
+
+declare i8 @llvm.ctlz.i8(i8)
+
+define void @ctlztest(i8 %A, i16 %B, i32 %C, i64 %D, i8* %AP, i16* %BP, i32* %CP, i64* %DP) {
+ %a = call i8 @llvm.ctlz.i8( i8 %A ) ; <i8> [#uses=1]
+ %b = call i16 @llvm.ctlz.i16( i16 %B ) ; <i16> [#uses=1]
+ %c = call i32 @llvm.ctlz.i32( i32 %C ) ; <i32> [#uses=1]
+ %d = call i64 @llvm.ctlz.i64( i64 %D ) ; <i64> [#uses=1]
+ store i8 %a, i8* %AP
+ store i16 %b, i16* %BP
+ store i32 %c, i32* %CP
+ store i64 %d, i64* %DP
+ ret void
+}
+
+declare i64 @llvm.cttz.i64(i64)
+
+declare i32 @llvm.cttz.i32(i32)
+
+declare i16 @llvm.cttz.i16(i16)
+
+declare i8 @llvm.cttz.i8(i8)
+
+define void @cttztest(i8 %A, i16 %B, i32 %C, i64 %D, i8* %AP, i16* %BP, i32* %CP, i64* %DP) {
+ %a = call i8 @llvm.cttz.i8( i8 %A ) ; <i8> [#uses=1]
+ %b = call i16 @llvm.cttz.i16( i16 %B ) ; <i16> [#uses=1]
+ %c = call i32 @llvm.cttz.i32( i32 %C ) ; <i32> [#uses=1]
+ %d = call i64 @llvm.cttz.i64( i64 %D ) ; <i64> [#uses=1]
+ store i8 %a, i8* %AP
+ store i16 %b, i16* %BP
+ store i32 %c, i32* %CP
+ store i64 %d, i64* %DP
+ ret void
+}
diff --git a/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll b/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll
new file mode 100644
index 0000000..282e973
--- /dev/null
+++ b/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s
+
+declare { i64, double } @wild()
+
+define void @foo(i64* %p, double* %q) nounwind {
+ %t = invoke { i64, double } @wild() to label %normal unwind label %handler
+
+normal:
+ %mrv_gr = getresult { i64, double } %t, 0
+ store i64 %mrv_gr, i64* %p
+ %mrv_gr12681 = getresult { i64, double } %t, 1
+ store double %mrv_gr12681, double* %q
+ ret void
+
+handler:
+ ret void
+}
+
diff --git a/test/CodeGen/Generic/negintconst.ll b/test/CodeGen/Generic/negintconst.ll
new file mode 100644
index 0000000..67d775e
--- /dev/null
+++ b/test/CodeGen/Generic/negintconst.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s
+
+; Test that a negative constant smaller than 64 bits (e.g., int)
+; is correctly implemented with sign-extension.
+; In particular, the current code generated is:
+;
+; main:
+; .L_main_LL_0:
+; save %o6, -224, %o6
+; setx .G_fmtArg_1, %o1, %o0
+; setuw 1, %o1 ! i = 1
+; setuw 4294967295, %o3 ! THE BUG: 0x00000000ffffffff
+; setsw 0, %i0
+; add %i6, 1999, %o2 ! fval
+; add %o1, %g0, %o1
+; add %o0, 0, %o0
+; mulx %o1, %o3, %o1 ! ERROR: 0xffffffff; should be -1
+; add %o1, 3, %o1 ! ERROR: 0x100000002; should be 0x2
+; mulx %o1, 12, %o3 !
+; add %o2, %o3, %o3 ! produces bad address!
+; call printf
+; nop
+; jmpl %i7+8, %g0
+; restore %g0, 0, %g0
+;
+; llc produces:
+; ioff = 2 fval = 0xffffffff7fffec90 &fval[2] = 0xb7fffeca8
+; instead of:
+; ioff = 2 fval = 0xffffffff7fffec90 &fval[2] = 0xffffffff7fffeca8
+;
+ %Results = type { float, float, float }
+@fmtArg = internal global [39 x i8] c"ioff = %u\09fval = 0x%p\09&fval[2] = 0x%p\0A\00" ; <[39 x i8]*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+ %fval = alloca %Results, i32 4 ; <%Results*> [#uses=2]
+ %i = add i32 1, 0 ; <i32> [#uses=1]
+ %iscale = mul i32 %i, -1 ; <i32> [#uses=1]
+ %ioff = add i32 %iscale, 3 ; <i32> [#uses=2]
+ %ioff.upgrd.1 = zext i32 %ioff to i64 ; <i64> [#uses=1]
+ %fptr = getelementptr %Results* %fval, i64 %ioff.upgrd.1 ; <%Results*> [#uses=1]
+ %castFmt = getelementptr [39 x i8]* @fmtArg, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %castFmt, i32 %ioff, %Results* %fval, %Results* %fptr ) ; <i32>:1 [#uses=0]
+ ret i32 0
+}
+
diff --git a/test/CodeGen/Generic/nested-select.ll b/test/CodeGen/Generic/nested-select.ll
new file mode 100644
index 0000000..f81fed3
--- /dev/null
+++ b/test/CodeGen/Generic/nested-select.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -o /dev/null
+
+; Test that select of a select works
+
+%typedef.tree = type opaque
+
+define i32 @ic_test(double %p.0.2.0.val, double %p.0.2.1.val, double %p.0.2.2.val, %typedef.tree* %t) {
+ %result.1.0 = zext i1 false to i32 ; <i32> [#uses=1]
+ %tmp.55 = fcmp oge double 0.000000e+00, 1.000000e+00 ; <i1> [#uses=1]
+ %tmp.66 = fdiv double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ br label %N
+
+N: ; preds = %0
+ %result.1.1 = select i1 %tmp.55, i32 0, i32 %result.1.0 ; <i32> [#uses=1]
+ %tmp.75 = fcmp oge double %tmp.66, 1.000000e+00 ; <i1> [#uses=1]
+ %retval1 = select i1 %tmp.75, i32 0, i32 %result.1.1 ; <i32> [#uses=1]
+ ret i32 %retval1
+}
+
diff --git a/test/CodeGen/Generic/pr2625.ll b/test/CodeGen/Generic/pr2625.ll
new file mode 100644
index 0000000..3e3dc4b
--- /dev/null
+++ b/test/CodeGen/Generic/pr2625.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s
+; PR2625
+
+define i32 @main({ i32, { i32 } }*) {
+entry:
+ %state = alloca { i32, { i32 } }* ; <{ i32, { i32 } }**> [#uses=2]
+ store { i32, { i32 } }* %0, { i32, { i32 } }** %state
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ store i32 0, i32* %retval
+ load { i32, { i32 } }** %state ; <{ i32, { i32 } }*>:1 [#uses=1]
+ store { i32, { i32 } } zeroinitializer, { i32, { i32 } }* %1
+ br label %return
+
+return: ; preds = %entry
+ load i32* %retval ; <i32>:2 [#uses=1]
+ ret i32 %2
+}
diff --git a/test/CodeGen/Generic/pr3288.ll b/test/CodeGen/Generic/pr3288.ll
new file mode 100644
index 0000000..b62710f
--- /dev/null
+++ b/test/CodeGen/Generic/pr3288.ll
@@ -0,0 +1,67 @@
+; RUN: llc < %s
+; PR3288
+
+define void @a() {
+ %i = insertvalue [2 x [2 x i32]] undef, [2 x i32] undef, 1
+ ret void
+}
+define void @b() {
+ %i = insertvalue {{i32,float},{i16,double}} undef, {i16,double} undef, 1
+ ret void
+}
+define void @c() {
+ %i = insertvalue [2 x [2 x i32]] zeroinitializer, [2 x i32] zeroinitializer, 1
+ ret void
+}
+define void @d() {
+ %i = insertvalue {{i32,float},{i16,double}} zeroinitializer, {i16,double} zeroinitializer, 1
+ ret void
+}
+define void @e() {
+ %i = insertvalue [2 x [2 x i32]] undef, [2 x i32] undef, 0
+ ret void
+}
+define void @f() {
+ %i = insertvalue {{i32,float},{i16,double}} undef, {i32,float} undef, 0
+ ret void
+}
+define void @g() {
+ %i = insertvalue [2 x [2 x i32]] zeroinitializer, [2 x i32] zeroinitializer, 0
+ ret void
+}
+define void @h() {
+ %i = insertvalue {{i32,float},{i16,double}} zeroinitializer, {i32,float} zeroinitializer, 0
+ ret void
+}
+define void @ax() {
+ %i = insertvalue [2 x [2 x i32]] undef, i32 undef, 1, 1
+ ret void
+}
+define void @bx() {
+ %i = insertvalue {{i32,float},{i16,double}} undef, double undef, 1, 1
+ ret void
+}
+define void @cx() {
+ %i = insertvalue [2 x [2 x i32]] zeroinitializer, i32 zeroinitializer, 1, 1
+ ret void
+}
+define void @dx() {
+ %i = insertvalue {{i32,float},{i16,double}} zeroinitializer, double zeroinitializer, 1, 1
+ ret void
+}
+define void @ex() {
+ %i = insertvalue [2 x [2 x i32]] undef, i32 undef, 0, 1
+ ret void
+}
+define void @fx() {
+ %i = insertvalue {{i32,float},{i16,double}} undef, float undef, 0, 1
+ ret void
+}
+define void @gx() {
+ %i = insertvalue [2 x [2 x i32]] zeroinitializer, i32 zeroinitializer, 0, 1
+ ret void
+}
+define void @hx() {
+ %i = insertvalue {{i32,float},{i16,double}} zeroinitializer, float zeroinitializer, 0, 1
+ ret void
+}
diff --git a/test/CodeGen/Generic/print-add.ll b/test/CodeGen/Generic/print-add.ll
new file mode 100644
index 0000000..95608dc
--- /dev/null
+++ b/test/CodeGen/Generic/print-add.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s
+
[email protected]_1 = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+ %f = getelementptr [4 x i8]* @.str_1, i64 0, i64 0 ; <i8*> [#uses=3]
+ %d = add i32 1, 0 ; <i32> [#uses=3]
+ call i32 (i8*, ...)* @printf( i8* %f, i32 %d ) ; <i32>:1 [#uses=0]
+ %e = add i32 38, 2 ; <i32> [#uses=2]
+ call i32 (i8*, ...)* @printf( i8* %f, i32 %e ) ; <i32>:2 [#uses=0]
+ %g = add i32 %d, %d ; <i32> [#uses=1]
+ %h = add i32 %e, %g ; <i32> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %f, i32 %h ) ; <i32>:3 [#uses=0]
+ ret i32 0
+}
+
diff --git a/test/CodeGen/Generic/print-arith-fp.ll b/test/CodeGen/Generic/print-arith-fp.ll
new file mode 100644
index 0000000..d129ff8
--- /dev/null
+++ b/test/CodeGen/Generic/print-arith-fp.ll
@@ -0,0 +1,61 @@
+; RUN: llc < %s
+@a_str = internal constant [8 x i8] c"a = %f\0A\00" ; <[8 x i8]*> [#uses=1]
+@b_str = internal constant [8 x i8] c"b = %f\0A\00" ; <[8 x i8]*> [#uses=1]
+@add_str = internal constant [12 x i8] c"a + b = %f\0A\00" ; <[12 x i8]*> [#uses=1]
+@sub_str = internal constant [12 x i8] c"a - b = %f\0A\00" ; <[12 x i8]*> [#uses=1]
+@mul_str = internal constant [12 x i8] c"a * b = %f\0A\00" ; <[12 x i8]*> [#uses=1]
+@div_str = internal constant [12 x i8] c"b / a = %f\0A\00" ; <[12 x i8]*> [#uses=1]
+@rem_str = internal constant [13 x i8] c"b %% a = %f\0A\00" ; <[13 x i8]*> [#uses=1]
+@lt_str = internal constant [12 x i8] c"a < b = %d\0A\00" ; <[12 x i8]*> [#uses=1]
+@le_str = internal constant [13 x i8] c"a <= b = %d\0A\00" ; <[13 x i8]*> [#uses=1]
+@gt_str = internal constant [12 x i8] c"a > b = %d\0A\00" ; <[12 x i8]*> [#uses=1]
+@ge_str = internal constant [13 x i8] c"a >= b = %d\0A\00" ; <[13 x i8]*> [#uses=1]
+@eq_str = internal constant [13 x i8] c"a == b = %d\0A\00" ; <[13 x i8]*> [#uses=1]
+@ne_str = internal constant [13 x i8] c"a != b = %d\0A\00" ; <[13 x i8]*> [#uses=1]
+@A = global double 2.000000e+00 ; <double*> [#uses=1]
+@B = global double 5.000000e+00 ; <double*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+ %a = load double* @A ; <double> [#uses=12]
+ %b = load double* @B ; <double> [#uses=12]
+ %a_s = getelementptr [8 x i8]* @a_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %b_s = getelementptr [8 x i8]* @b_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %a_s, double %a ) ; <i32>:1 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %b_s, double %b ) ; <i32>:2 [#uses=0]
+ %add_r = fadd double %a, %b ; <double> [#uses=1]
+ %sub_r = fsub double %a, %b ; <double> [#uses=1]
+ %mul_r = fmul double %a, %b ; <double> [#uses=1]
+ %div_r = fdiv double %b, %a ; <double> [#uses=1]
+ %rem_r = frem double %b, %a ; <double> [#uses=1]
+ %add_s = getelementptr [12 x i8]* @add_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %sub_s = getelementptr [12 x i8]* @sub_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %mul_s = getelementptr [12 x i8]* @mul_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %div_s = getelementptr [12 x i8]* @div_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %rem_s = getelementptr [13 x i8]* @rem_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %add_s, double %add_r ) ; <i32>:3 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %sub_s, double %sub_r ) ; <i32>:4 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %mul_s, double %mul_r ) ; <i32>:5 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %div_s, double %div_r ) ; <i32>:6 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %rem_s, double %rem_r ) ; <i32>:7 [#uses=0]
+ %lt_r = fcmp olt double %a, %b ; <i1> [#uses=1]
+ %le_r = fcmp ole double %a, %b ; <i1> [#uses=1]
+ %gt_r = fcmp ogt double %a, %b ; <i1> [#uses=1]
+ %ge_r = fcmp oge double %a, %b ; <i1> [#uses=1]
+ %eq_r = fcmp oeq double %a, %b ; <i1> [#uses=1]
+ %ne_r = fcmp une double %a, %b ; <i1> [#uses=1]
+ %lt_s = getelementptr [12 x i8]* @lt_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %le_s = getelementptr [13 x i8]* @le_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %gt_s = getelementptr [12 x i8]* @gt_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %ge_s = getelementptr [13 x i8]* @ge_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %eq_s = getelementptr [13 x i8]* @eq_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %lt_s, i1 %lt_r ) ; <i32>:8 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %le_s, i1 %le_r ) ; <i32>:9 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %gt_s, i1 %gt_r ) ; <i32>:10 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %ge_s, i1 %ge_r ) ; <i32>:11 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %eq_s, i1 %eq_r ) ; <i32>:12 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %ne_s, i1 %ne_r ) ; <i32>:13 [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/Generic/print-arith-int.ll b/test/CodeGen/Generic/print-arith-int.ll
new file mode 100644
index 0000000..ce938cf
--- /dev/null
+++ b/test/CodeGen/Generic/print-arith-int.ll
@@ -0,0 +1,84 @@
+; RUN: llc < %s
+@a_str = internal constant [8 x i8] c"a = %d\0A\00" ; <[8 x i8]*> [#uses=1]
+@b_str = internal constant [8 x i8] c"b = %d\0A\00" ; <[8 x i8]*> [#uses=1]
+@add_str = internal constant [12 x i8] c"a + b = %d\0A\00" ; <[12 x i8]*> [#uses=1]
+@sub_str = internal constant [12 x i8] c"a - b = %d\0A\00" ; <[12 x i8]*> [#uses=1]
+@mul_str = internal constant [12 x i8] c"a * b = %d\0A\00" ; <[12 x i8]*> [#uses=1]
+@div_str = internal constant [12 x i8] c"b / a = %d\0A\00" ; <[12 x i8]*> [#uses=1]
+@rem_str = internal constant [13 x i8] c"b \5C% a = %d\0A\00" ; <[13 x i8]*> [#uses=1]
+@lt_str = internal constant [12 x i8] c"a < b = %d\0A\00" ; <[12 x i8]*> [#uses=1]
+@le_str = internal constant [13 x i8] c"a <= b = %d\0A\00" ; <[13 x i8]*> [#uses=1]
+@gt_str = internal constant [12 x i8] c"a > b = %d\0A\00" ; <[12 x i8]*> [#uses=1]
+@ge_str = internal constant [13 x i8] c"a >= b = %d\0A\00" ; <[13 x i8]*> [#uses=1]
+@eq_str = internal constant [13 x i8] c"a == b = %d\0A\00" ; <[13 x i8]*> [#uses=1]
+@ne_str = internal constant [13 x i8] c"a != b = %d\0A\00" ; <[13 x i8]*> [#uses=1]
+@and_str = internal constant [12 x i8] c"a & b = %d\0A\00" ; <[12 x i8]*> [#uses=1]
+@or_str = internal constant [12 x i8] c"a | b = %d\0A\00" ; <[12 x i8]*> [#uses=1]
+@xor_str = internal constant [12 x i8] c"a ^ b = %d\0A\00" ; <[12 x i8]*> [#uses=1]
+@shl_str = internal constant [13 x i8] c"b << a = %d\0A\00" ; <[13 x i8]*> [#uses=1]
+@shr_str = internal constant [13 x i8] c"b >> a = %d\0A\00" ; <[13 x i8]*> [#uses=1]
+@A = global i32 2 ; <i32*> [#uses=1]
+@B = global i32 5 ; <i32*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+ %a = load i32* @A ; <i32> [#uses=16]
+ %b = load i32* @B ; <i32> [#uses=17]
+ %a_s = getelementptr [8 x i8]* @a_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %b_s = getelementptr [8 x i8]* @b_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %a_s, i32 %a ) ; <i32>:1 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %b_s, i32 %b ) ; <i32>:2 [#uses=0]
+ %add_r = add i32 %a, %b ; <i32> [#uses=1]
+ %sub_r = sub i32 %a, %b ; <i32> [#uses=1]
+ %mul_r = mul i32 %a, %b ; <i32> [#uses=1]
+ %div_r = sdiv i32 %b, %a ; <i32> [#uses=1]
+ %rem_r = srem i32 %b, %a ; <i32> [#uses=1]
+ %add_s = getelementptr [12 x i8]* @add_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %sub_s = getelementptr [12 x i8]* @sub_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %mul_s = getelementptr [12 x i8]* @mul_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %div_s = getelementptr [12 x i8]* @div_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %rem_s = getelementptr [13 x i8]* @rem_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %add_s, i32 %add_r ) ; <i32>:3 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %sub_s, i32 %sub_r ) ; <i32>:4 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %mul_s, i32 %mul_r ) ; <i32>:5 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %div_s, i32 %div_r ) ; <i32>:6 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %rem_s, i32 %rem_r ) ; <i32>:7 [#uses=0]
+ %lt_r = icmp slt i32 %a, %b ; <i1> [#uses=1]
+ %le_r = icmp sle i32 %a, %b ; <i1> [#uses=1]
+ %gt_r = icmp sgt i32 %a, %b ; <i1> [#uses=1]
+ %ge_r = icmp sge i32 %a, %b ; <i1> [#uses=1]
+ %eq_r = icmp eq i32 %a, %b ; <i1> [#uses=1]
+ %ne_r = icmp ne i32 %a, %b ; <i1> [#uses=1]
+ %lt_s = getelementptr [12 x i8]* @lt_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %le_s = getelementptr [13 x i8]* @le_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %gt_s = getelementptr [12 x i8]* @gt_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %ge_s = getelementptr [13 x i8]* @ge_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %eq_s = getelementptr [13 x i8]* @eq_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %lt_s, i1 %lt_r ) ; <i32>:8 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %le_s, i1 %le_r ) ; <i32>:9 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %gt_s, i1 %gt_r ) ; <i32>:10 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %ge_s, i1 %ge_r ) ; <i32>:11 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %eq_s, i1 %eq_r ) ; <i32>:12 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %ne_s, i1 %ne_r ) ; <i32>:13 [#uses=0]
+ %and_r = and i32 %a, %b ; <i32> [#uses=1]
+ %or_r = or i32 %a, %b ; <i32> [#uses=1]
+ %xor_r = xor i32 %a, %b ; <i32> [#uses=1]
+ %u = trunc i32 %a to i8 ; <i8> [#uses=2]
+ %shift.upgrd.1 = zext i8 %u to i32 ; <i32> [#uses=1]
+ %shl_r = shl i32 %b, %shift.upgrd.1 ; <i32> [#uses=1]
+ %shift.upgrd.2 = zext i8 %u to i32 ; <i32> [#uses=1]
+ %shr_r = ashr i32 %b, %shift.upgrd.2 ; <i32> [#uses=1]
+ %and_s = getelementptr [12 x i8]* @and_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %or_s = getelementptr [12 x i8]* @or_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %xor_s = getelementptr [12 x i8]* @xor_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %shl_s = getelementptr [13 x i8]* @shl_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %shr_s = getelementptr [13 x i8]* @shr_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %and_s, i32 %and_r ) ; <i32>:14 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %or_s, i32 %or_r ) ; <i32>:15 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %xor_s, i32 %xor_r ) ; <i32>:16 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %shl_s, i32 %shl_r ) ; <i32>:17 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %shr_s, i32 %shr_r ) ; <i32>:18 [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/Generic/print-int.ll b/test/CodeGen/Generic/print-int.ll
new file mode 100644
index 0000000..7ca4b3d
--- /dev/null
+++ b/test/CodeGen/Generic/print-int.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s
+
[email protected]_1 = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+ %f = getelementptr [4 x i8]* @.str_1, i64 0, i64 0 ; <i8*> [#uses=1]
+ %d = add i32 0, 0 ; <i32> [#uses=1]
+ %tmp.0 = call i32 (i8*, ...)* @printf( i8* %f, i32 %d ) ; <i32> [#uses=0]
+ ret i32 0
+}
+
diff --git a/test/CodeGen/Generic/print-mul-exp.ll b/test/CodeGen/Generic/print-mul-exp.ll
new file mode 100644
index 0000000..90fc55b
--- /dev/null
+++ b/test/CodeGen/Generic/print-mul-exp.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s
+
+@a_str = internal constant [8 x i8] c"a = %d\0A\00" ; <[8 x i8]*> [#uses=1]
+@a_mul_str = internal constant [13 x i8] c"a * %d = %d\0A\00" ; <[13 x i8]*> [#uses=1]
+@A = global i32 2 ; <i32*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+ %a = load i32* @A ; <i32> [#uses=21]
+ %a_s = getelementptr [8 x i8]* @a_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %a_mul_s = getelementptr [13 x i8]* @a_mul_str, i64 0, i64 0 ; <i8*> [#uses=20]
+ call i32 (i8*, ...)* @printf( i8* %a_s, i32 %a ) ; <i32>:1 [#uses=0]
+ %r_0 = mul i32 %a, 0 ; <i32> [#uses=1]
+ %r_1 = mul i32 %a, 1 ; <i32> [#uses=1]
+ %r_2 = mul i32 %a, 2 ; <i32> [#uses=1]
+ %r_3 = mul i32 %a, 3 ; <i32> [#uses=1]
+ %r_4 = mul i32 %a, 4 ; <i32> [#uses=1]
+ %r_5 = mul i32 %a, 5 ; <i32> [#uses=1]
+ %r_6 = mul i32 %a, 6 ; <i32> [#uses=1]
+ %r_7 = mul i32 %a, 7 ; <i32> [#uses=1]
+ %r_8 = mul i32 %a, 8 ; <i32> [#uses=1]
+ %r_9 = mul i32 %a, 9 ; <i32> [#uses=1]
+ %r_10 = mul i32 %a, 10 ; <i32> [#uses=1]
+ %r_11 = mul i32 %a, 11 ; <i32> [#uses=1]
+ %r_12 = mul i32 %a, 12 ; <i32> [#uses=1]
+ %r_13 = mul i32 %a, 13 ; <i32> [#uses=1]
+ %r_14 = mul i32 %a, 14 ; <i32> [#uses=1]
+ %r_15 = mul i32 %a, 15 ; <i32> [#uses=1]
+ %r_16 = mul i32 %a, 16 ; <i32> [#uses=1]
+ %r_17 = mul i32 %a, 17 ; <i32> [#uses=1]
+ %r_18 = mul i32 %a, 18 ; <i32> [#uses=1]
+ %r_19 = mul i32 %a, 19 ; <i32> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 0, i32 %r_0 ) ; <i32>:2 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 1, i32 %r_1 ) ; <i32>:3 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 2, i32 %r_2 ) ; <i32>:4 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 3, i32 %r_3 ) ; <i32>:5 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 4, i32 %r_4 ) ; <i32>:6 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 5, i32 %r_5 ) ; <i32>:7 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 6, i32 %r_6 ) ; <i32>:8 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 7, i32 %r_7 ) ; <i32>:9 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 8, i32 %r_8 ) ; <i32>:10 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 9, i32 %r_9 ) ; <i32>:11 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 10, i32 %r_10 ) ; <i32>:12 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 11, i32 %r_11 ) ; <i32>:13 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 12, i32 %r_12 ) ; <i32>:14 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 13, i32 %r_13 ) ; <i32>:15 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 14, i32 %r_14 ) ; <i32>:16 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 15, i32 %r_15 ) ; <i32>:17 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 16, i32 %r_16 ) ; <i32>:18 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 17, i32 %r_17 ) ; <i32>:19 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 18, i32 %r_18 ) ; <i32>:20 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 19, i32 %r_19 ) ; <i32>:21 [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/Generic/print-mul.ll b/test/CodeGen/Generic/print-mul.ll
new file mode 100644
index 0000000..0707f3c
--- /dev/null
+++ b/test/CodeGen/Generic/print-mul.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s
+
+@a_str = internal constant [8 x i8] c"a = %d\0A\00" ; <[8 x i8]*> [#uses=1]
+@b_str = internal constant [8 x i8] c"b = %d\0A\00" ; <[8 x i8]*> [#uses=1]
+@a_mul_str = internal constant [13 x i8] c"a * %d = %d\0A\00" ; <[13 x i8]*> [#uses=1]
+@A = global i32 2 ; <i32*> [#uses=1]
+@B = global i32 5 ; <i32*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+entry:
+ %a = load i32* @A ; <i32> [#uses=2]
+ %b = load i32* @B ; <i32> [#uses=1]
+ %a_s = getelementptr [8 x i8]* @a_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %b_s = getelementptr [8 x i8]* @b_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %a_mul_s = getelementptr [13 x i8]* @a_mul_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %a_s, i32 %a ) ; <i32>:0 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %b_s, i32 %b ) ; <i32>:1 [#uses=0]
+ br label %shl_test
+
+shl_test: ; preds = %shl_test, %entry
+ %s = phi i32 [ 0, %entry ], [ %s_inc, %shl_test ] ; <i32> [#uses=4]
+ %result = mul i32 %a, %s ; <i32> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %a_mul_s, i32 %s, i32 %result ) ; <i32>:2 [#uses=0]
+ %s_inc = add i32 %s, 1 ; <i32> [#uses=1]
+ %done = icmp eq i32 %s, 256 ; <i1> [#uses=1]
+ br i1 %done, label %fini, label %shl_test
+
+fini: ; preds = %shl_test
+ ret i32 0
+}
diff --git a/test/CodeGen/Generic/print-shift.ll b/test/CodeGen/Generic/print-shift.ll
new file mode 100644
index 0000000..6c5d222
--- /dev/null
+++ b/test/CodeGen/Generic/print-shift.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s
+
+@a_str = internal constant [8 x i8] c"a = %d\0A\00" ; <[8 x i8]*> [#uses=1]
+@b_str = internal constant [8 x i8] c"b = %d\0A\00" ; <[8 x i8]*> [#uses=1]
+@a_shl_str = internal constant [14 x i8] c"a << %d = %d\0A\00" ; <[14 x i8]*> [#uses=1]
+@A = global i32 2 ; <i32*> [#uses=1]
+@B = global i32 5 ; <i32*> [#uses=1]
+
+declare i32 @printf(i8*, ...)
+
+define i32 @main() {
+entry:
+ %a = load i32* @A ; <i32> [#uses=2]
+ %b = load i32* @B ; <i32> [#uses=1]
+ %a_s = getelementptr [8 x i8]* @a_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %b_s = getelementptr [8 x i8]* @b_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ %a_shl_s = getelementptr [14 x i8]* @a_shl_str, i64 0, i64 0 ; <i8*> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %a_s, i32 %a ) ; <i32>:0 [#uses=0]
+ call i32 (i8*, ...)* @printf( i8* %b_s, i32 %b ) ; <i32>:1 [#uses=0]
+ br label %shl_test
+
+shl_test: ; preds = %shl_test, %entry
+ %s = phi i8 [ 0, %entry ], [ %s_inc, %shl_test ] ; <i8> [#uses=4]
+ %shift.upgrd.1 = zext i8 %s to i32 ; <i32> [#uses=1]
+ %result = shl i32 %a, %shift.upgrd.1 ; <i32> [#uses=1]
+ call i32 (i8*, ...)* @printf( i8* %a_shl_s, i8 %s, i32 %result ) ; <i32>:2 [#uses=0]
+ %s_inc = add i8 %s, 1 ; <i8> [#uses=1]
+ %done = icmp eq i8 %s, 32 ; <i1> [#uses=1]
+ br i1 %done, label %fini, label %shl_test
+
+fini: ; preds = %shl_test
+ ret i32 0
+}
+
diff --git a/test/CodeGen/Generic/ret0.ll b/test/CodeGen/Generic/ret0.ll
new file mode 100644
index 0000000..9e628a1
--- /dev/null
+++ b/test/CodeGen/Generic/ret0.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s
+
+define i32 @main() {
+ ret i32 0
+}
diff --git a/test/CodeGen/Generic/ret42.ll b/test/CodeGen/Generic/ret42.ll
new file mode 100644
index 0000000..f5cd33d
--- /dev/null
+++ b/test/CodeGen/Generic/ret42.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s
+
+define i32 @main() {
+ ret i32 42
+}
diff --git a/test/CodeGen/Generic/select-cc.ll b/test/CodeGen/Generic/select-cc.ll
new file mode 100644
index 0000000..b653e2a
--- /dev/null
+++ b/test/CodeGen/Generic/select-cc.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s
+; PR2504
+
+define <2 x double> @vector_select(<2 x double> %x, <2 x double> %y) nounwind {
+ %x.lo = extractelement <2 x double> %x, i32 0 ; <double> [#uses=1]
+ %x.lo.ge = fcmp oge double %x.lo, 0.000000e+00 ; <i1> [#uses=1]
+ %a.d = select i1 %x.lo.ge, <2 x double> %y, <2 x double> %x ; <<2 x double>> [#uses=1]
+ ret <2 x double> %a.d
+}
diff --git a/test/CodeGen/Generic/select.ll b/test/CodeGen/Generic/select.ll
new file mode 100644
index 0000000..63052c1
--- /dev/null
+++ b/test/CodeGen/Generic/select.ll
@@ -0,0 +1,187 @@
+; RUN: llc < %s
+
+%Domain = type { i8*, i32, i32*, i32, i32, i32*, %Domain* }
+@AConst = constant i32 123 ; <i32*> [#uses=1]
+
+; Test setting values of different constants in registers.
+;
+define void @testConsts(i32 %N, float %X) {
+ %a = add i32 %N, 1 ; <i32> [#uses=0]
+ %i = add i32 %N, 12345678 ; <i32> [#uses=0]
+ %b = add i16 4, 3 ; <i16> [#uses=0]
+ %c = fadd float %X, 0.000000e+00 ; <float> [#uses=0]
+ %d = fadd float %X, 0x400921CAC0000000 ; <float> [#uses=0]
+ %f = add i32 -1, 10 ; <i32> [#uses=0]
+ %g = add i16 20, -1 ; <i16> [#uses=0]
+ %j = add i16 -1, 30 ; <i16> [#uses=0]
+ %h = add i8 40, -1 ; <i8> [#uses=0]
+ %k = add i8 -1, 50 ; <i8> [#uses=0]
+ ret void
+}
+
+; A SetCC whose result is used should produce instructions to
+; compute the boolean value in a register. One whose result
+; is unused will only generate the condition code but not
+; the boolean result.
+;
+define void @unusedBool(i32* %x, i32* %y) {
+ icmp eq i32* %x, %y ; <i1>:1 [#uses=1]
+ xor i1 %1, true ; <i1>:2 [#uses=0]
+ icmp ne i32* %x, %y ; <i1>:3 [#uses=0]
+ ret void
+}
+
+; A constant argument to a Phi produces a Cast instruction in the
+; corresponding predecessor basic block. This checks a few things:
+; -- phi arguments coming from the bottom of the same basic block
+; (they should not be forward substituted in the machine code!)
+; -- code generation for casts of various types
+; -- use of immediate fields for integral constants of different sizes
+; -- branch on a constant condition
+;
+define void @mergeConstants(i32* %x, i32* %y) {
+; <label>:0
+ br label %Top
+
+Top: ; preds = %Next, %Top, %0
+ phi i32 [ 0, %0 ], [ 1, %Top ], [ 524288, %Next ] ; <i32>:1 [#uses=0]
+ phi float [ 0.000000e+00, %0 ], [ 1.000000e+00, %Top ], [ 2.000000e+00, %Next ] ; <float>:2 [#uses=0]
+ phi double [ 5.000000e-01, %0 ], [ 1.500000e+00, %Top ], [ 2.500000e+00, %Next ]
+ phi i1 [ true, %0 ], [ false, %Top ], [ true, %Next ] ; <i1>:4 [#uses=0]
+ br i1 true, label %Top, label %Next
+
+Next: ; preds = %Top
+ br label %Top
+}
+
+
+
+; A constant argument to a cast used only once should be forward substituted
+; and loaded where needed, which happens is:
+; -- User of cast has no immediate field
+; -- User of cast has immediate field but constant is too large to fit
+; or constant is not resolved until later (e.g., global address)
+; -- User of cast uses it as a call arg. or return value so it is an implicit
+; use but has to be loaded into a virtual register so that the reg.
+; allocator can allocate the appropriate phys. reg. for it
+;
+define i32* @castconst(float) {
+ %castbig = trunc i64 99999999 to i32 ; <i32> [#uses=1]
+ %castsmall = trunc i64 1 to i32 ; <i32> [#uses=1]
+ %usebig = add i32 %castbig, %castsmall ; <i32> [#uses=0]
+ %castglob = bitcast i32* @AConst to i64* ; <i64*> [#uses=1]
+ %dummyl = load i64* %castglob ; <i64> [#uses=0]
+ %castnull = inttoptr i64 0 to i32* ; <i32*> [#uses=1]
+ ret i32* %castnull
+}
+
+; Test branch-on-comparison-with-zero, in two ways:
+; 1. can be folded
+; 2. cannot be folded because result of comparison is used twice
+;
+define void @testbool(i32 %A, i32 %B) {
+ br label %Top
+
+Top: ; preds = %loop, %0
+ %D = add i32 %A, %B ; <i32> [#uses=2]
+ %E = sub i32 %D, -4 ; <i32> [#uses=1]
+ %C = icmp sle i32 %E, 0 ; <i1> [#uses=1]
+ br i1 %C, label %retlbl, label %loop
+
+loop: ; preds = %loop, %Top
+ %F = add i32 %A, %B ; <i32> [#uses=0]
+ %G = sub i32 %D, -4 ; <i32> [#uses=1]
+ %D.upgrd.1 = icmp sle i32 %G, 0 ; <i1> [#uses=1]
+ %E.upgrd.2 = xor i1 %D.upgrd.1, true ; <i1> [#uses=1]
+ br i1 %E.upgrd.2, label %loop, label %Top
+
+retlbl: ; preds = %Top
+ ret void
+}
+
+
+;; Test use of a boolean result in cast operations.
+;; Requires converting a condition code result into a 0/1 value in a reg.
+;;
+define i32 @castbool(i32 %A, i32 %B) {
+bb0:
+ %cond213 = icmp slt i32 %A, %B ; <i1> [#uses=1]
+ %cast110 = zext i1 %cond213 to i8 ; <i8> [#uses=1]
+ %cast109 = zext i8 %cast110 to i32 ; <i32> [#uses=1]
+ ret i32 %cast109
+}
+
+;; Test use of a boolean result in arithmetic and logical operations.
+;; Requires converting a condition code result into a 0/1 value in a reg.
+;;
+define i1 @boolexpr(i1 %b, i32 %N) {
+ %b2 = icmp sge i32 %N, 0 ; <i1> [#uses=1]
+ %b3 = and i1 %b, %b2 ; <i1> [#uses=1]
+ ret i1 %b3
+}
+
+; Test branch on floating point comparison
+;
+define void @testfloatbool(float %x, float %y) {
+ br label %Top
+
+Top: ; preds = %Top, %0
+ %p = fadd float %x, %y ; <float> [#uses=1]
+ %z = fsub float %x, %y ; <float> [#uses=1]
+ %b = fcmp ole float %p, %z ; <i1> [#uses=2]
+ %c = xor i1 %b, true ; <i1> [#uses=0]
+ br i1 %b, label %Top, label %goon
+
+goon: ; preds = %Top
+ ret void
+}
+
+
+; Test cases where an LLVM instruction requires no machine
+; instructions (e.g., cast int* to long). But there are 2 cases:
+; 1. If the result register has only a single use and the use is in the
+; same basic block, the operand will be copy-propagated during
+; instruction selection.
+; 2. If the result register has multiple uses or is in a different
+; basic block, it cannot (or will not) be copy propagated during
+; instruction selection. It will generate a
+; copy instruction (add-with-0), but this copy should get coalesced
+; away by the register allocator.
+;
+define i32 @checkForward(i32 %N, i32* %A) {
+bb2:
+ %reg114 = shl i32 %N, 2 ; <i32> [#uses=1]
+ %cast115 = sext i32 %reg114 to i64 ; <i64> [#uses=1]
+ %cast116 = ptrtoint i32* %A to i64 ; <i64> [#uses=1]
+ %reg116 = add i64 %cast116, %cast115 ; <i64> [#uses=1]
+ %castPtr = inttoptr i64 %reg116 to i32* ; <i32*> [#uses=1]
+ %reg118 = load i32* %castPtr ; <i32> [#uses=1]
+ %cast117 = sext i32 %reg118 to i64 ; <i64> [#uses=2]
+ %reg159 = add i64 1234567, %cast117 ; <i64> [#uses=0]
+ %reg160 = add i64 7654321, %cast117 ; <i64> [#uses=0]
+ ret i32 0
+}
+
+
+; Test case for unary NOT operation constructed from XOR.
+;
+define void @checkNot(i1 %b, i32 %i) {
+ %notB = xor i1 %b, true ; <i1> [#uses=1]
+ %notI = xor i32 %i, -1 ; <i32> [#uses=2]
+ %F = icmp sge i32 %notI, 100 ; <i1> [#uses=1]
+ %J = add i32 %i, %i ; <i32> [#uses=1]
+ %andNotB = and i1 %F, %notB ; <i1> [#uses=0]
+ %andNotI = and i32 %J, %notI ; <i32> [#uses=0]
+ %notB2 = xor i1 true, %b ; <i1> [#uses=0]
+ %notI2 = xor i32 -1, %i ; <i32> [#uses=0]
+ ret void
+}
+
+; Test case for folding getelementptr into a load/store
+;
+define i32 @checkFoldGEP(%Domain* %D, i64 %idx) {
+ %reg841 = getelementptr %Domain* %D, i64 0, i32 1 ; <i32*> [#uses=1]
+ %reg820 = load i32* %reg841 ; <i32> [#uses=1]
+ ret i32 %reg820
+}
+
diff --git a/test/CodeGen/Generic/shift-int64.ll b/test/CodeGen/Generic/shift-int64.ll
new file mode 100644
index 0000000..670ef20
--- /dev/null
+++ b/test/CodeGen/Generic/shift-int64.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s
+
+define i64 @test_imm(i64 %X) {
+ %Y = ashr i64 %X, 17 ; <i64> [#uses=1]
+ ret i64 %Y
+}
+
+define i64 @test_variable(i64 %X, i8 %Amt) {
+ %shift.upgrd.1 = zext i8 %Amt to i64 ; <i64> [#uses=1]
+ %Y = ashr i64 %X, %shift.upgrd.1 ; <i64> [#uses=1]
+ ret i64 %Y
+}
diff --git a/test/CodeGen/Generic/spillccr.ll b/test/CodeGen/Generic/spillccr.ll
new file mode 100644
index 0000000..0a774c6
--- /dev/null
+++ b/test/CodeGen/Generic/spillccr.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s
+
+; July 6, 2002 -- LLC Regression test
+; This test case checks if the integer CC register %xcc (or %ccr)
+; is correctly spilled. The code fragment came from function
+; MakeGraph in Olden-mst.
+; The original code made all comparisons with 0, so that the %xcc
+; register is not needed for the branch in the first basic block.
+; Replace 0 with 1 in the first comparson so that the
+; branch-on-register instruction cannot be used directly, i.e.,
+; the %xcc register is needed for the first branch.
+;
+
+ %Graph = type %struct.graph_st*
+ %Hash = type %struct.hash*
+ %HashEntry = type %struct.hash_entry*
+ %Vertex = type %struct.vert_st*
+ %struct.graph_st = type { [1 x %Vertex] }
+ %struct.hash = type { %HashEntry*, i32 (i32)*, i32 }
+ %struct.hash_entry = type { i32, i8*, %HashEntry }
+ %struct.vert_st = type { i32, %Vertex, %Hash }
+@HashRange = external global i32 ; <i32*> [#uses=0]
[email protected] = internal global [13 x i8] c"Make phase 2\00" ; <[13 x i8]*> [#uses=0]
[email protected] = internal global [13 x i8] c"Make phase 3\00" ; <[13 x i8]*> [#uses=0]
[email protected] = internal global [13 x i8] c"Make phase 4\00" ; <[13 x i8]*> [#uses=0]
[email protected] = internal global [15 x i8] c"Make returning\00" ; <[15 x i8]*> [#uses=0]
+
+define %Graph @MakeGraph(i32 %numvert, i32 %numproc) {
+bb1:
+ %reg111 = add i32 %numproc, -1 ; <i32> [#uses=2]
+ %cond275 = icmp slt i32 %reg111, 1 ; <i1> [#uses=1]
+ %cond276 = icmp sle i32 %reg111, 0 ; <i1> [#uses=1]
+ %cond277 = icmp sge i32 %numvert, 0 ; <i1> [#uses=1]
+ %reg162 = add i32 %numvert, 3 ; <i32> [#uses=0]
+ br i1 %cond275, label %bb7, label %bb4
+
+bb4: ; preds = %bb1
+ br i1 %cond276, label %bb7, label %bb5
+
+bb5: ; preds = %bb4
+ br i1 %cond277, label %bb7, label %bb6
+
+bb6: ; preds = %bb5
+ ret %Graph null
+
+bb7: ; preds = %bb5, %bb4, %bb1
+ ret %Graph null
+}
+
diff --git a/test/CodeGen/Generic/stack-protector.ll b/test/CodeGen/Generic/stack-protector.ll
new file mode 100644
index 0000000..a59c649
--- /dev/null
+++ b/test/CodeGen/Generic/stack-protector.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -o - | grep {__stack_chk_guard}
+; RUN: llc < %s -o - | grep {__stack_chk_fail}
+
+@"\01LC" = internal constant [11 x i8] c"buf == %s\0A\00" ; <[11 x i8]*> [#uses=1]
+
+define void @test(i8* %a) nounwind ssp {
+entry:
+ %a_addr = alloca i8* ; <i8**> [#uses=2]
+ %buf = alloca [8 x i8] ; <[8 x i8]*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i8* %a, i8** %a_addr
+ %buf1 = bitcast [8 x i8]* %buf to i8* ; <i8*> [#uses=1]
+ %0 = load i8** %a_addr, align 4 ; <i8*> [#uses=1]
+ %1 = call i8* @strcpy(i8* %buf1, i8* %0) nounwind ; <i8*> [#uses=0]
+ %buf2 = bitcast [8 x i8]* %buf to i8* ; <i8*> [#uses=1]
+ %2 = call i32 (i8*, ...)* @printf(i8* getelementptr ([11 x i8]* @"\01LC", i32 0, i32 0), i8* %buf2) nounwind ; <i32> [#uses=0]
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8* @strcpy(i8*, i8*) nounwind
+
+declare i32 @printf(i8*, ...) nounwind
diff --git a/test/CodeGen/Generic/stacksave-restore.ll b/test/CodeGen/Generic/stacksave-restore.ll
new file mode 100644
index 0000000..b124b5f
--- /dev/null
+++ b/test/CodeGen/Generic/stacksave-restore.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s
+
+declare i8* @llvm.stacksave()
+
+declare void @llvm.stackrestore(i8*)
+
+define i32* @test(i32 %N) {
+ %tmp = call i8* @llvm.stacksave( ) ; <i8*> [#uses=1]
+ %P = alloca i32, i32 %N ; <i32*> [#uses=1]
+ call void @llvm.stackrestore( i8* %tmp )
+ %Q = alloca i32, i32 %N ; <i32*> [#uses=0]
+ ret i32* %P
+}
+
diff --git a/test/CodeGen/Generic/storetrunc-fp.ll b/test/CodeGen/Generic/storetrunc-fp.ll
new file mode 100644
index 0000000..7f7c7f7
--- /dev/null
+++ b/test/CodeGen/Generic/storetrunc-fp.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s
+
+define void @foo(double %a, double %b, float* %fp) {
+ %c = fadd double %a, %b
+ %d = fptrunc double %c to float
+ store float %d, float* %fp
+ ret void
+}
diff --git a/test/CodeGen/Generic/switch-lower-feature.ll b/test/CodeGen/Generic/switch-lower-feature.ll
new file mode 100644
index 0000000..1e9dbee
--- /dev/null
+++ b/test/CodeGen/Generic/switch-lower-feature.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s
+
+define i32 @test(i32 %tmp158) {
+entry:
+ switch i32 %tmp158, label %bb336 [
+ i32 120, label %bb338
+ i32 121, label %bb338
+ i32 122, label %bb338
+ i32 123, label %bb338
+ i32 124, label %bb338
+ i32 125, label %bb338
+ i32 126, label %bb338
+ i32 1024, label %bb338
+ i32 0, label %bb338
+ i32 1, label %bb338
+ i32 2, label %bb338
+ i32 3, label %bb338
+ i32 4, label %bb338
+ i32 5, label %bb338
+ ]
+bb336:
+ ret i32 10
+bb338:
+ ret i32 11
+}
+
+define i32 @test2(i32 %tmp158) {
+entry:
+ switch i32 %tmp158, label %bb336 [
+ i32 -2147483648, label %bb338
+ i32 -2147483647, label %bb338
+ i32 -2147483646, label %bb338
+ i32 120, label %bb338
+ i32 121, label %bb339
+ i32 122, label %bb340
+ i32 123, label %bb341
+ i32 124, label %bb342
+ i32 125, label %bb343
+ i32 126, label %bb336
+ i32 1024, label %bb338
+ i32 0, label %bb338
+ i32 1, label %bb338
+ i32 2, label %bb338
+ i32 3, label %bb338
+ i32 4, label %bb338
+ i32 5, label %bb338
+ ]
+bb336:
+ ret i32 10
+bb338:
+ ret i32 11
+bb339:
+ ret i32 12
+bb340:
+ ret i32 13
+bb341:
+ ret i32 14
+bb342:
+ ret i32 15
+bb343:
+ ret i32 18
+
+}
diff --git a/test/CodeGen/Generic/switch-lower.ll b/test/CodeGen/Generic/switch-lower.ll
new file mode 100644
index 0000000..1cefe82
--- /dev/null
+++ b/test/CodeGen/Generic/switch-lower.ll
@@ -0,0 +1,348 @@
+; RUN: llc < %s
+
+
+; PR5421
+define void @test1() {
+entry:
+ switch i128 undef, label %exit [
+ i128 55340232221128654848, label %exit
+ i128 92233720368547758080, label %exit
+ i128 73786976294838206464, label %exit
+ i128 147573952589676412928, label %exit
+ ]
+exit:
+ unreachable
+}
+
+
+; PR1197
+define void @test2() {
+entry:
+ br i1 false, label %cond_next954, label %cond_true924
+
+cond_true924: ; preds = %entry
+ ret void
+
+cond_next954: ; preds = %entry
+ switch i8 0, label %cleanup7419 [
+ i8 1, label %bb956
+ i8 2, label %bb1069
+ i8 4, label %bb7328
+ i8 5, label %bb1267
+ i8 8, label %bb1348
+ i8 9, label %bb7328
+ i8 11, label %bb1439
+ i8 12, label %bb1484
+ i8 13, label %bb1706
+ i8 14, label %bb1783
+ i8 17, label %bb1925
+ i8 18, label %bb1929
+ i8 19, label %bb2240
+ i8 25, label %bb2447
+ i8 27, label %bb2480
+ i8 29, label %bb2590
+ i8 30, label %bb2594
+ i8 31, label %bb2621
+ i8 32, label %bb2664
+ i8 33, label %bb2697
+ i8 34, label %bb2735
+ i8 37, label %bb2786
+ i8 38, label %bb2849
+ i8 39, label %bb3269
+ i8 41, label %bb3303
+ i8 42, label %bb3346
+ i8 43, label %bb3391
+ i8 44, label %bb3395
+ i8 50, label %bb3673
+ i8 52, label %bb3677
+ i8 53, label %bb3693
+ i8 54, label %bb7328
+ i8 56, label %bb3758
+ i8 57, label %bb3787
+ i8 64, label %bb5019
+ i8 68, label %cond_true4235
+ i8 69, label %bb4325
+ i8 70, label %bb4526
+ i8 72, label %bb4618
+ i8 73, label %bb4991
+ i8 80, label %bb5012
+ i8 82, label %bb5019
+ i8 84, label %bb5518
+ i8 86, label %bb5752
+ i8 87, label %bb5953
+ i8 89, label %bb6040
+ i8 90, label %bb6132
+ i8 92, label %bb6186
+ i8 93, label %bb6151
+ i8 94, label %bb6155
+ i8 97, label %bb6355
+ i8 98, label %bb5019
+ i8 99, label %bb6401
+ i8 101, label %bb5019
+ i8 102, label %bb1484
+ i8 104, label %bb7064
+ i8 105, label %bb7068
+ i8 106, label %bb7072
+ i8 108, label %bb1065
+ i8 109, label %bb1702
+ i8 110, label %bb2200
+ i8 111, label %bb2731
+ i8 112, label %bb2782
+ i8 113, label %bb2845
+ i8 114, label %bb2875
+ i8 115, label %bb3669
+ i8 116, label %bb7316
+ i8 117, label %bb7316
+ i8 118, label %bb3875
+ i8 119, label %bb4359
+ i8 120, label %bb4987
+ i8 121, label %bb5008
+ i8 122, label %bb5786
+ i8 123, label %bb6147
+ i8 124, label %bb6916
+ i8 125, label %bb6920
+ i8 126, label %bb6955
+ i8 127, label %bb6990
+ i8 -128, label %bb7027
+ i8 -127, label %bb3879
+ i8 -126, label %bb4700
+ i8 -125, label %bb7076
+ i8 -124, label %bb2366
+ i8 -123, label %bb2366
+ i8 -122, label %bb5490
+ ]
+
+bb956: ; preds = %cond_next954
+ ret void
+
+bb1065: ; preds = %cond_next954
+ ret void
+
+bb1069: ; preds = %cond_next954
+ ret void
+
+bb1267: ; preds = %cond_next954
+ ret void
+
+bb1348: ; preds = %cond_next954
+ ret void
+
+bb1439: ; preds = %cond_next954
+ ret void
+
+bb1484: ; preds = %cond_next954, %cond_next954
+ ret void
+
+bb1702: ; preds = %cond_next954
+ ret void
+
+bb1706: ; preds = %cond_next954
+ ret void
+
+bb1783: ; preds = %cond_next954
+ ret void
+
+bb1925: ; preds = %cond_next954
+ ret void
+
+bb1929: ; preds = %cond_next954
+ ret void
+
+bb2200: ; preds = %cond_next954
+ ret void
+
+bb2240: ; preds = %cond_next954
+ ret void
+
+bb2366: ; preds = %cond_next954, %cond_next954
+ ret void
+
+bb2447: ; preds = %cond_next954
+ ret void
+
+bb2480: ; preds = %cond_next954
+ ret void
+
+bb2590: ; preds = %cond_next954
+ ret void
+
+bb2594: ; preds = %cond_next954
+ ret void
+
+bb2621: ; preds = %cond_next954
+ ret void
+
+bb2664: ; preds = %cond_next954
+ ret void
+
+bb2697: ; preds = %cond_next954
+ ret void
+
+bb2731: ; preds = %cond_next954
+ ret void
+
+bb2735: ; preds = %cond_next954
+ ret void
+
+bb2782: ; preds = %cond_next954
+ ret void
+
+bb2786: ; preds = %cond_next954
+ ret void
+
+bb2845: ; preds = %cond_next954
+ ret void
+
+bb2849: ; preds = %cond_next954
+ ret void
+
+bb2875: ; preds = %cond_next954
+ ret void
+
+bb3269: ; preds = %cond_next954
+ ret void
+
+bb3303: ; preds = %cond_next954
+ ret void
+
+bb3346: ; preds = %cond_next954
+ ret void
+
+bb3391: ; preds = %cond_next954
+ ret void
+
+bb3395: ; preds = %cond_next954
+ ret void
+
+bb3669: ; preds = %cond_next954
+ ret void
+
+bb3673: ; preds = %cond_next954
+ ret void
+
+bb3677: ; preds = %cond_next954
+ ret void
+
+bb3693: ; preds = %cond_next954
+ ret void
+
+bb3758: ; preds = %cond_next954
+ ret void
+
+bb3787: ; preds = %cond_next954
+ ret void
+
+bb3875: ; preds = %cond_next954
+ ret void
+
+bb3879: ; preds = %cond_next954
+ ret void
+
+cond_true4235: ; preds = %cond_next954
+ ret void
+
+bb4325: ; preds = %cond_next954
+ ret void
+
+bb4359: ; preds = %cond_next954
+ ret void
+
+bb4526: ; preds = %cond_next954
+ ret void
+
+bb4618: ; preds = %cond_next954
+ ret void
+
+bb4700: ; preds = %cond_next954
+ ret void
+
+bb4987: ; preds = %cond_next954
+ ret void
+
+bb4991: ; preds = %cond_next954
+ ret void
+
+bb5008: ; preds = %cond_next954
+ ret void
+
+bb5012: ; preds = %cond_next954
+ ret void
+
+bb5019: ; preds = %cond_next954, %cond_next954, %cond_next954, %cond_next954
+ ret void
+
+bb5490: ; preds = %cond_next954
+ ret void
+
+bb5518: ; preds = %cond_next954
+ ret void
+
+bb5752: ; preds = %cond_next954
+ ret void
+
+bb5786: ; preds = %cond_next954
+ ret void
+
+bb5953: ; preds = %cond_next954
+ ret void
+
+bb6040: ; preds = %cond_next954
+ ret void
+
+bb6132: ; preds = %cond_next954
+ ret void
+
+bb6147: ; preds = %cond_next954
+ ret void
+
+bb6151: ; preds = %cond_next954
+ ret void
+
+bb6155: ; preds = %cond_next954
+ ret void
+
+bb6186: ; preds = %cond_next954
+ ret void
+
+bb6355: ; preds = %cond_next954
+ ret void
+
+bb6401: ; preds = %cond_next954
+ ret void
+
+bb6916: ; preds = %cond_next954
+ ret void
+
+bb6920: ; preds = %cond_next954
+ ret void
+
+bb6955: ; preds = %cond_next954
+ ret void
+
+bb6990: ; preds = %cond_next954
+ ret void
+
+bb7027: ; preds = %cond_next954
+ ret void
+
+bb7064: ; preds = %cond_next954
+ ret void
+
+bb7068: ; preds = %cond_next954
+ ret void
+
+bb7072: ; preds = %cond_next954
+ ret void
+
+bb7076: ; preds = %cond_next954
+ ret void
+
+bb7316: ; preds = %cond_next954, %cond_next954
+ ret void
+
+bb7328: ; preds = %cond_next954, %cond_next954, %cond_next954
+ ret void
+
+cleanup7419: ; preds = %cond_next954
+ ret void
+}
diff --git a/test/CodeGen/Generic/trap.ll b/test/CodeGen/Generic/trap.ll
new file mode 100644
index 0000000..67d1a7a
--- /dev/null
+++ b/test/CodeGen/Generic/trap.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s
+define i32 @test() noreturn nounwind {
+entry:
+ tail call void @llvm.trap( )
+ unreachable
+}
+
+declare void @llvm.trap() nounwind
+
diff --git a/test/CodeGen/Generic/v-split.ll b/test/CodeGen/Generic/v-split.ll
new file mode 100644
index 0000000..634b562
--- /dev/null
+++ b/test/CodeGen/Generic/v-split.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+%f8 = type <8 x float>
+
+define void @test_f8(%f8 *%P, %f8* %Q, %f8 *%S) {
+ %p = load %f8* %P
+ %q = load %f8* %Q
+ %R = fadd %f8 %p, %q
+ store %f8 %R, %f8 *%S
+ ret void
+}
+
diff --git a/test/CodeGen/Generic/vector-casts.ll b/test/CodeGen/Generic/vector-casts.ll
new file mode 100644
index 0000000..a26918b
--- /dev/null
+++ b/test/CodeGen/Generic/vector-casts.ll
@@ -0,0 +1,45 @@
+; RUN: llc < %s
+; PR2671
+
+define void @a(<2 x double>* %p, <2 x i8>* %q) {
+ %t = load <2 x double>* %p
+ %r = fptosi <2 x double> %t to <2 x i8>
+ store <2 x i8> %r, <2 x i8>* %q
+ ret void
+}
+define void @b(<2 x double>* %p, <2 x i8>* %q) {
+ %t = load <2 x double>* %p
+ %r = fptoui <2 x double> %t to <2 x i8>
+ store <2 x i8> %r, <2 x i8>* %q
+ ret void
+}
+define void @c(<2 x i8>* %p, <2 x double>* %q) {
+ %t = load <2 x i8>* %p
+ %r = sitofp <2 x i8> %t to <2 x double>
+ store <2 x double> %r, <2 x double>* %q
+ ret void
+}
+define void @d(<2 x i8>* %p, <2 x double>* %q) {
+ %t = load <2 x i8>* %p
+ %r = uitofp <2 x i8> %t to <2 x double>
+ store <2 x double> %r, <2 x double>* %q
+ ret void
+}
+define void @e(<2 x i8>* %p, <2 x i16>* %q) {
+ %t = load <2 x i8>* %p
+ %r = sext <2 x i8> %t to <2 x i16>
+ store <2 x i16> %r, <2 x i16>* %q
+ ret void
+}
+define void @f(<2 x i8>* %p, <2 x i16>* %q) {
+ %t = load <2 x i8>* %p
+ %r = zext <2 x i8> %t to <2 x i16>
+ store <2 x i16> %r, <2 x i16>* %q
+ ret void
+}
+define void @g(<2 x i16>* %p, <2 x i8>* %q) {
+ %t = load <2 x i16>* %p
+ %r = trunc <2 x i16> %t to <2 x i8>
+ store <2 x i8> %r, <2 x i8>* %q
+ ret void
+}
diff --git a/test/CodeGen/Generic/vector-constantexpr.ll b/test/CodeGen/Generic/vector-constantexpr.ll
new file mode 100644
index 0000000..d8e0258
--- /dev/null
+++ b/test/CodeGen/Generic/vector-constantexpr.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s
+
+define void @""(float* %inregs, float* %outregs) {
+ %a_addr.i = alloca <4 x float> ; <<4 x float>*> [#uses=1]
+ store <4 x float> < float undef, float undef, float undef, float undef >, <4 x float>* %a_addr.i
+ ret void
+}
diff --git a/test/CodeGen/Generic/vector-identity-shuffle.ll b/test/CodeGen/Generic/vector-identity-shuffle.ll
new file mode 100644
index 0000000..332d6d8
--- /dev/null
+++ b/test/CodeGen/Generic/vector-identity-shuffle.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s
+
+
+define void @test(<4 x float>* %tmp2.i) {
+ %tmp2.i.upgrd.1 = load <4 x float>* %tmp2.i ; <<4 x float>> [#uses=4]
+ %xFloat0.48 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 0 ; <float> [#uses=1]
+ %inFloat0.49 = insertelement <4 x float> undef, float %xFloat0.48, i32 0 ; <<4 x float>> [#uses=1]
+ %xFloat1.50 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 1 ; <float> [#uses=1]
+ %inFloat1.52 = insertelement <4 x float> %inFloat0.49, float %xFloat1.50, i32 1 ; <<4 x float>> [#uses=1]
+ %xFloat2.53 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 2 ; <float> [#uses=1]
+ %inFloat2.55 = insertelement <4 x float> %inFloat1.52, float %xFloat2.53, i32 2 ; <<4 x float>> [#uses=1]
+ %xFloat3.56 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 3 ; <float> [#uses=1]
+ %inFloat3.58 = insertelement <4 x float> %inFloat2.55, float %xFloat3.56, i32 3 ; <<4 x float>> [#uses=1]
+ store <4 x float> %inFloat3.58, <4 x float>* %tmp2.i
+ ret void
+}
+
diff --git a/test/CodeGen/Generic/vector.ll b/test/CodeGen/Generic/vector.ll
new file mode 100644
index 0000000..a0f9a02
--- /dev/null
+++ b/test/CodeGen/Generic/vector.ll
@@ -0,0 +1,154 @@
+; Test that vectors are scalarized/lowered correctly.
+; RUN: llc < %s
+
+
+%d8 = type <8 x double>
+%f1 = type <1 x float>
+%f2 = type <2 x float>
+%f4 = type <4 x float>
+%f8 = type <8 x float>
+%i4 = type <4 x i32>
+
+;;; TEST HANDLING OF VARIOUS VECTOR SIZES
+
+define void @test_f1(%f1* %P, %f1* %Q, %f1* %S) {
+ %p = load %f1* %P ; <%f1> [#uses=1]
+ %q = load %f1* %Q ; <%f1> [#uses=1]
+ %R = fadd %f1 %p, %q ; <%f1> [#uses=1]
+ store %f1 %R, %f1* %S
+ ret void
+}
+
+define void @test_f2(%f2* %P, %f2* %Q, %f2* %S) {
+ %p = load %f2* %P ; <%f2> [#uses=1]
+ %q = load %f2* %Q ; <%f2> [#uses=1]
+ %R = fadd %f2 %p, %q ; <%f2> [#uses=1]
+ store %f2 %R, %f2* %S
+ ret void
+}
+
+define void @test_f4(%f4* %P, %f4* %Q, %f4* %S) {
+ %p = load %f4* %P ; <%f4> [#uses=1]
+ %q = load %f4* %Q ; <%f4> [#uses=1]
+ %R = fadd %f4 %p, %q ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_f8(%f8* %P, %f8* %Q, %f8* %S) {
+ %p = load %f8* %P ; <%f8> [#uses=1]
+ %q = load %f8* %Q ; <%f8> [#uses=1]
+ %R = fadd %f8 %p, %q ; <%f8> [#uses=1]
+ store %f8 %R, %f8* %S
+ ret void
+}
+
+define void @test_fmul(%f8* %P, %f8* %Q, %f8* %S) {
+ %p = load %f8* %P ; <%f8> [#uses=1]
+ %q = load %f8* %Q ; <%f8> [#uses=1]
+ %R = fmul %f8 %p, %q ; <%f8> [#uses=1]
+ store %f8 %R, %f8* %S
+ ret void
+}
+
+define void @test_div(%f8* %P, %f8* %Q, %f8* %S) {
+ %p = load %f8* %P ; <%f8> [#uses=1]
+ %q = load %f8* %Q ; <%f8> [#uses=1]
+ %R = fdiv %f8 %p, %q ; <%f8> [#uses=1]
+ store %f8 %R, %f8* %S
+ ret void
+}
+
+;;; TEST VECTOR CONSTRUCTS
+
+
+define void @test_cst(%f4* %P, %f4* %S) {
+ %p = load %f4* %P ; <%f4> [#uses=1]
+ %R = fadd %f4 %p, < float 0x3FB99999A0000000, float 1.000000e+00, float 2.000000e+00, float 4.500000e+00 > ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_zero(%f4* %P, %f4* %S) {
+ %p = load %f4* %P ; <%f4> [#uses=1]
+ %R = fadd %f4 %p, zeroinitializer ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_undef(%f4* %P, %f4* %S) {
+ %p = load %f4* %P ; <%f4> [#uses=1]
+ %R = fadd %f4 %p, undef ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_constant_insert(%f4* %S) {
+ %R = insertelement %f4 zeroinitializer, float 1.000000e+01, i32 0 ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_variable_buildvector(float %F, %f4* %S) {
+ %R = insertelement %f4 zeroinitializer, float %F, i32 0 ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_scalar_to_vector(float %F, %f4* %S) {
+ %R = insertelement %f4 undef, float %F, i32 0 ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define float @test_extract_elt(%f8* %P) {
+ %p = load %f8* %P ; <%f8> [#uses=1]
+ %R = extractelement %f8 %p, i32 3 ; <float> [#uses=1]
+ ret float %R
+}
+
+define double @test_extract_elt2(%d8* %P) {
+ %p = load %d8* %P ; <%d8> [#uses=1]
+ %R = extractelement %d8 %p, i32 3 ; <double> [#uses=1]
+ ret double %R
+}
+
+define void @test_cast_1(%f4* %b, %i4* %a) {
+ %tmp = load %f4* %b ; <%f4> [#uses=1]
+ %tmp2 = fadd %f4 %tmp, < float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00 > ; <%f4> [#uses=1]
+ %tmp3 = bitcast %f4 %tmp2 to %i4 ; <%i4> [#uses=1]
+ %tmp4 = add %i4 %tmp3, < i32 1, i32 2, i32 3, i32 4 > ; <%i4> [#uses=1]
+ store %i4 %tmp4, %i4* %a
+ ret void
+}
+
+define void @test_cast_2(%f8* %a, <8 x i32>* %b) {
+ %T = load %f8* %a ; <%f8> [#uses=1]
+ %T2 = bitcast %f8 %T to <8 x i32> ; <<8 x i32>> [#uses=1]
+ store <8 x i32> %T2, <8 x i32>* %b
+ ret void
+}
+
+;;; TEST IMPORTANT IDIOMS
+
+define void @splat(%f4* %P, %f4* %Q, float %X) {
+ %tmp = insertelement %f4 undef, float %X, i32 0 ; <%f4> [#uses=1]
+ %tmp2 = insertelement %f4 %tmp, float %X, i32 1 ; <%f4> [#uses=1]
+ %tmp4 = insertelement %f4 %tmp2, float %X, i32 2 ; <%f4> [#uses=1]
+ %tmp6 = insertelement %f4 %tmp4, float %X, i32 3 ; <%f4> [#uses=1]
+ %q = load %f4* %Q ; <%f4> [#uses=1]
+ %R = fadd %f4 %q, %tmp6 ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %P
+ ret void
+}
+
+define void @splat_i4(%i4* %P, %i4* %Q, i32 %X) {
+ %tmp = insertelement %i4 undef, i32 %X, i32 0 ; <%i4> [#uses=1]
+ %tmp2 = insertelement %i4 %tmp, i32 %X, i32 1 ; <%i4> [#uses=1]
+ %tmp4 = insertelement %i4 %tmp2, i32 %X, i32 2 ; <%i4> [#uses=1]
+ %tmp6 = insertelement %i4 %tmp4, i32 %X, i32 3 ; <%i4> [#uses=1]
+ %q = load %i4* %Q ; <%i4> [#uses=1]
+ %R = add %i4 %q, %tmp6 ; <%i4> [#uses=1]
+ store %i4 %R, %i4* %P
+ ret void
+}
diff --git a/test/CodeGen/MSP430/2009-05-10-CyclicDAG.ll b/test/CodeGen/MSP430/2009-05-10-CyclicDAG.ll
new file mode 100644
index 0000000..f339373
--- /dev/null
+++ b/test/CodeGen/MSP430/2009-05-10-CyclicDAG.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s
+; PR4136
+
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-unknown-linux-gnu"
+@uip_len = external global i16 ; <i16*> [#uses=2]
+
+define void @uip_arp_arpin() nounwind {
+entry:
+ %tmp = volatile load i16* @uip_len ; <i16> [#uses=1]
+ %cmp = icmp ult i16 %tmp, 42 ; <i1> [#uses=1]
+ volatile store i16 0, i16* @uip_len
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ ret void
+
+if.end: ; preds = %entry
+ switch i16 0, label %return [
+ i16 256, label %sw.bb
+ i16 512, label %sw.bb18
+ ]
+
+sw.bb: ; preds = %if.end
+ ret void
+
+sw.bb18: ; preds = %if.end
+ ret void
+
+return: ; preds = %if.end
+ ret void
+}
diff --git a/test/CodeGen/MSP430/2009-05-17-Rot.ll b/test/CodeGen/MSP430/2009-05-17-Rot.ll
new file mode 100644
index 0000000..2ae0052
--- /dev/null
+++ b/test/CodeGen/MSP430/2009-05-17-Rot.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=msp430
+
+define i16 @rol1u16(i16 %x.arg) nounwind {
+ %retval = alloca i16
+ %x = alloca i16
+ store i16 %x.arg, i16* %x
+ %1 = load i16* %x
+ %2 = shl i16 %1, 1
+ %3 = load i16* %x
+ %4 = lshr i16 %3, 15
+ %5 = or i16 %2, %4
+ store i16 %5, i16* %retval
+ br label %return
+return:
+ %6 = load i16* %retval
+ ret i16 %6
+}
\ No newline at end of file
diff --git a/test/CodeGen/MSP430/2009-05-17-Shift.ll b/test/CodeGen/MSP430/2009-05-17-Shift.ll
new file mode 100644
index 0000000..25aff60
--- /dev/null
+++ b/test/CodeGen/MSP430/2009-05-17-Shift.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=msp430 | grep rra | count 1
+
+define i16 @lsr2u16(i16 %x.arg) nounwind {
+ %retval = alloca i16
+ %x = alloca i16
+ store i16 %x.arg, i16* %x
+ %1 = load i16* %x
+ %2 = lshr i16 %1, 2
+ store i16 %2, i16* %retval
+ br label %return
+return:
+ %3 = load i16* %retval
+ ret i16 %3
+
+}
\ No newline at end of file
diff --git a/test/CodeGen/MSP430/2009-05-19-DoubleSplit.ll b/test/CodeGen/MSP430/2009-05-19-DoubleSplit.ll
new file mode 100644
index 0000000..54eb7ff
--- /dev/null
+++ b/test/CodeGen/MSP430/2009-05-19-DoubleSplit.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=msp430
+
+define i16 @test(double %d) nounwind {
+entry:
+ %add = fadd double %d, 1.000000e+00
+ %call = tail call i16 @funct(double %add) nounwind
+ ret i16 %call
+}
+
+declare i16 @funct(double)
+
diff --git a/test/CodeGen/MSP430/2009-08-25-DynamicStackAlloc.ll b/test/CodeGen/MSP430/2009-08-25-DynamicStackAlloc.ll
new file mode 100644
index 0000000..088d3e1
--- /dev/null
+++ b/test/CodeGen/MSP430/2009-08-25-DynamicStackAlloc.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s
+; PR4769
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+define i16 @foo() nounwind readnone {
+entry:
+ %result = alloca i16, align 1 ; <i16*> [#uses=2]
+ volatile store i16 0, i16* %result
+ %tmp = volatile load i16* %result ; <i16> [#uses=1]
+ ret i16 %tmp
+}
+
+define i16 @main() nounwind {
+entry:
+ br label %while.cond
+
+while.cond: ; preds = %while.cond, %entry
+ %call = call i16 @bar() nounwind ; <i16> [#uses=1]
+ %tobool = icmp eq i16 %call, 0 ; <i1> [#uses=1]
+ br i1 %tobool, label %while.end, label %while.cond
+
+while.end: ; preds = %while.cond
+ %result.i = alloca i16, align 1 ; <i16*> [#uses=2]
+ volatile store i16 0, i16* %result.i
+ %tmp.i = volatile load i16* %result.i ; <i16> [#uses=0]
+ ret i16 0
+}
+
+declare i16 @bar()
diff --git a/test/CodeGen/MSP430/2009-09-18-AbsoluteAddr.ll b/test/CodeGen/MSP430/2009-09-18-AbsoluteAddr.ll
new file mode 100644
index 0000000..4d7d9b9
--- /dev/null
+++ b/test/CodeGen/MSP430/2009-09-18-AbsoluteAddr.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s | grep 0x0021 | count 2
+; PR4776
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-unknown-unknown"
+
+@"\010x0021" = external global i8, align 1 ; <i8*> [#uses=2]
+
+define zeroext i8 @foo(i8 zeroext %x) nounwind {
+entry:
+ %retval = alloca i8 ; <i8*> [#uses=2]
+ %x.addr = alloca i8 ; <i8*> [#uses=2]
+ %tmp = alloca i8, align 1 ; <i8*> [#uses=2]
+ store i8 %x, i8* %x.addr
+ %tmp1 = volatile load i8* @"\010x0021" ; <i8> [#uses=1]
+ store i8 %tmp1, i8* %tmp
+ %tmp2 = load i8* %x.addr ; <i8> [#uses=1]
+ volatile store i8 %tmp2, i8* @"\010x0021"
+ %tmp3 = load i8* %tmp ; <i8> [#uses=1]
+ store i8 %tmp3, i8* %retval
+ %0 = load i8* %retval ; <i8> [#uses=1]
+ ret i8 %0
+}
diff --git a/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll b/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
new file mode 100644
index 0000000..856eb9d
--- /dev/null
+++ b/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
@@ -0,0 +1,14 @@
+; RUN: llc -march=msp430 < %s
+; PR4779
+define void @foo() nounwind {
+entry:
+ %r = alloca i8 ; <i8*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ volatile load i8* %r, align 1 ; <i8>:0 [#uses=1]
+ or i8 %0, 1 ; <i8>:1 [#uses=1]
+ volatile store i8 %1, i8* %r, align 1
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll b/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll
new file mode 100644
index 0000000..94fe5c7
--- /dev/null
+++ b/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-elf"
+
+@g_29 = common global i8 0, align 1 ; <i8*> [#uses=0]
+
+define signext i8 @foo(i8 signext %_si1, i8 signext %_si2) nounwind readnone {
+entry:
+; CHECK: foo:
+; CHECK: call #__mulqi3
+ %mul = mul i8 %_si2, %_si1 ; <i8> [#uses=1]
+ ret i8 %mul
+}
+
+define void @uint81(i16* nocapture %p_32) nounwind {
+entry:
+ %call = tail call i16 @bar(i8* bitcast (i8 (i8, i8)* @foo to i8*)) nounwind ; <i16> [#uses=0]
+ ret void
+}
+
+declare i16 @bar(i8*)
diff --git a/test/CodeGen/MSP430/2009-11-08-InvalidResNo.ll b/test/CodeGen/MSP430/2009-11-08-InvalidResNo.ll
new file mode 100644
index 0000000..d232aea
--- /dev/null
+++ b/test/CodeGen/MSP430/2009-11-08-InvalidResNo.ll
@@ -0,0 +1,64 @@
+; RUN: llc < %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-elf"
+
+%struct.httpd_fs_file = type { i8*, i16 }
+%struct.psock = type { %struct.pt, %struct.pt, i8*, i8*, i8*, i16, i16, %struct.httpd_fs_file, i16, i8, i8 }
+%struct.pt = type { i16 }
+
+@foo = external global i8*
+
+define signext i8 @psock_readto(%struct.psock* nocapture %psock, i8 zeroext %c) nounwind {
+entry:
+ switch i16 undef, label %sw.epilog [
+ i16 0, label %sw.bb
+ i16 283, label %if.else.i
+ ]
+
+sw.bb: ; preds = %entry
+ br label %do.body
+
+do.body: ; preds = %while.cond36.i, %while.end.i, %sw.bb
+ br label %while.cond.i
+
+if.else.i: ; preds = %entry
+ br i1 undef, label %psock_newdata.exit, label %if.else11.i
+
+if.else11.i: ; preds = %if.else.i
+ ret i8 0
+
+psock_newdata.exit: ; preds = %if.else.i
+ ret i8 0
+
+while.cond.i: ; preds = %while.body.i, %do.body
+ br i1 undef, label %while.end.i, label %while.body.i
+
+while.body.i: ; preds = %while.cond.i
+ br i1 undef, label %do.end41, label %while.cond.i
+
+while.end.i: ; preds = %while.cond.i
+ br i1 undef, label %do.body, label %while.cond36.i.preheader
+
+while.cond36.i.preheader: ; preds = %while.end.i
+ br label %while.cond36.i
+
+while.cond36.i: ; preds = %while.body41.i, %while.cond36.i.preheader
+ br i1 undef, label %do.body, label %while.body41.i
+
+while.body41.i: ; preds = %while.cond36.i
+ %tmp43.i = load i8** @foo ; <i8*> [#uses=2]
+ %tmp44.i = load i8* %tmp43.i ; <i8> [#uses=1]
+ %ptrincdec50.i = getelementptr inbounds i8* %tmp43.i, i16 1 ; <i8*> [#uses=1]
+ store i8* %ptrincdec50.i, i8** @foo
+ %cmp55.i = icmp eq i8 %tmp44.i, %c ; <i1> [#uses=1]
+ br i1 %cmp55.i, label %do.end41, label %while.cond36.i
+
+do.end41: ; preds = %while.body41.i, %while.body.i
+ br i1 undef, label %if.then46, label %sw.epilog
+
+if.then46: ; preds = %do.end41
+ ret i8 0
+
+sw.epilog: ; preds = %do.end41, %entry
+ ret i8 2
+}
diff --git a/test/CodeGen/MSP430/2009-11-20-NewNode.ll b/test/CodeGen/MSP430/2009-11-20-NewNode.ll
new file mode 100644
index 0000000..887c7d6
--- /dev/null
+++ b/test/CodeGen/MSP430/2009-11-20-NewNode.ll
@@ -0,0 +1,36 @@
+; RUN: llc -march=msp430 < %s
+; PR5558
+
+define i64 @_strtoll_r(i16 %base) nounwind {
+entry:
+ br i1 undef, label %if.then, label %if.end27
+
+if.then: ; preds = %do.end
+ br label %if.end27
+
+if.end27: ; preds = %if.then, %do.end
+ %cond66 = select i1 undef, i64 -9223372036854775808, i64 9223372036854775807 ; <i64> [#uses=3]
+ %conv69 = sext i16 %base to i64 ; <i64> [#uses=1]
+ %div = udiv i64 %cond66, %conv69 ; <i64> [#uses=1]
+ br label %for.cond
+
+for.cond: ; preds = %if.end116, %if.end27
+ br i1 undef, label %if.then152, label %if.then93
+
+if.then93: ; preds = %for.cond
+ br i1 undef, label %if.end116, label %if.then152
+
+if.end116: ; preds = %if.then93
+ %cmp123 = icmp ugt i64 undef, %div ; <i1> [#uses=1]
+ %or.cond = or i1 undef, %cmp123 ; <i1> [#uses=0]
+ br label %for.cond
+
+if.then152: ; preds = %if.then93, %for.cond
+ br i1 undef, label %if.end182, label %if.then172
+
+if.then172: ; preds = %if.then152
+ ret i64 %cond66
+
+if.end182: ; preds = %if.then152
+ ret i64 %cond66
+}
diff --git a/test/CodeGen/MSP430/2009-12-21-FrameAddr.ll b/test/CodeGen/MSP430/2009-12-21-FrameAddr.ll
new file mode 100644
index 0000000..b92477b
--- /dev/null
+++ b/test/CodeGen/MSP430/2009-12-21-FrameAddr.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s
+; PR5703
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-unknown-linux-gnu"
+
+define msp430_intrcc void @foo() nounwind {
+entry:
+ %fa = call i16* @llvm.frameaddress(i32 0)
+ store i16 0, i16* %fa
+ ret void
+}
+
+declare i16* @llvm.frameaddress(i32)
diff --git a/test/CodeGen/MSP430/2009-12-22-InlineAsm.ll b/test/CodeGen/MSP430/2009-12-22-InlineAsm.ll
new file mode 100644
index 0000000..a9df1a3e
--- /dev/null
+++ b/test/CodeGen/MSP430/2009-12-22-InlineAsm.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s
+; PR 5570
+; ModuleID = 'test.c'
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-n8:16"
+target triple = "msp430-unknown-unknown"
+
+@buf = common global [10 x i8] zeroinitializer, align 1 ; <[10 x i8]*> [#uses=2]
+
+define i16 @main() noreturn nounwind {
+entry:
+ %0 = tail call i8* asm "", "=r,0"(i8* getelementptr inbounds ([10 x i8]* @buf, i16 0, i16 0)) nounwind ; <i8*> [#uses=1]
+ %sub.ptr = getelementptr inbounds i8* %0, i16 1 ; <i8*> [#uses=1]
+ %sub.ptr.lhs.cast = ptrtoint i8* %sub.ptr to i16 ; <i16> [#uses=1]
+ %sub.ptr.sub = sub i16 %sub.ptr.lhs.cast, ptrtoint ([10 x i8]* @buf to i16) ; <i16> [#uses=1]
+ %cmp = icmp eq i16 %sub.ptr.sub, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %bar.exit, label %if.then.i
+
+if.then.i: ; preds = %entry
+ tail call void @abort() nounwind
+ br label %bar.exit
+
+bar.exit: ; preds = %entry, %if.then.i
+ tail call void @exit(i16 0) nounwind
+ unreachable
+}
+
+declare void @exit(i16) noreturn
+
+declare void @abort()
diff --git a/test/CodeGen/MSP430/AddrMode-bis-rx.ll b/test/CodeGen/MSP430/AddrMode-bis-rx.ll
new file mode 100644
index 0000000..3340494
--- /dev/null
+++ b/test/CodeGen/MSP430/AddrMode-bis-rx.ll
@@ -0,0 +1,74 @@
+; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
+target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
+target triple = "msp430-generic-generic"
+
+define i16 @am1(i16 %x, i16* %a) nounwind {
+ %1 = load i16* %a
+ %2 = or i16 %1,%x
+ ret i16 %2
+}
+; CHECK: am1:
+; CHECK: bis.w 0(r14), r15
+
+@foo = external global i16
+
+define i16 @am2(i16 %x) nounwind {
+ %1 = load i16* @foo
+ %2 = or i16 %1,%x
+ ret i16 %2
+}
+; CHECK: am2:
+; CHECK: bis.w &foo, r15
+
+@bar = internal constant [2 x i8] [ i8 32, i8 64 ]
+
+define i8 @am3(i8 %x, i16 %n) nounwind {
+ %1 = getelementptr [2 x i8]* @bar, i16 0, i16 %n
+ %2 = load i8* %1
+ %3 = or i8 %2,%x
+ ret i8 %3
+}
+; CHECK: am3:
+; CHECK: bis.b &bar(r14), r15
+
+define i16 @am4(i16 %x) nounwind {
+ %1 = volatile load i16* inttoptr(i16 32 to i16*)
+ %2 = or i16 %1,%x
+ ret i16 %2
+}
+; CHECK: am4:
+; CHECK: bis.w &32, r15
+
+define i16 @am5(i16 %x, i16* %a) nounwind {
+ %1 = getelementptr i16* %a, i16 2
+ %2 = load i16* %1
+ %3 = or i16 %2,%x
+ ret i16 %3
+}
+; CHECK: am5:
+; CHECK: bis.w 4(r14), r15
+
+%S = type { i16, i16 }
+@baz = common global %S zeroinitializer, align 1
+
+define i16 @am6(i16 %x) nounwind {
+ %1 = load i16* getelementptr (%S* @baz, i32 0, i32 1)
+ %2 = or i16 %1,%x
+ ret i16 %2
+}
+; CHECK: am6:
+; CHECK: bis.w &baz+2, r15
+
+%T = type { i16, [2 x i8] }
+@duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] }
+
+define i8 @am7(i8 %x, i16 %n) nounwind {
+ %1 = getelementptr %T* @duh, i32 0, i32 1
+ %2 = getelementptr [2 x i8]* %1, i16 0, i16 %n
+ %3= load i8* %2
+ %4 = or i8 %3,%x
+ ret i8 %4
+}
+; CHECK: am7:
+; CHECK: bis.b &duh+2(r14), r15
+
diff --git a/test/CodeGen/MSP430/AddrMode-bis-xr.ll b/test/CodeGen/MSP430/AddrMode-bis-xr.ll
new file mode 100644
index 0000000..ca79fb6
--- /dev/null
+++ b/test/CodeGen/MSP430/AddrMode-bis-xr.ll
@@ -0,0 +1,81 @@
+; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
+target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:16"
+target triple = "msp430-generic-generic"
+
+define void @am1(i16* %a, i16 %x) nounwind {
+ %1 = load i16* %a
+ %2 = or i16 %x, %1
+ store i16 %2, i16* %a
+ ret void
+}
+; CHECK: am1:
+; CHECK: bis.w r14, 0(r15)
+
+@foo = external global i16
+
+define void @am2(i16 %x) nounwind {
+ %1 = load i16* @foo
+ %2 = or i16 %x, %1
+ store i16 %2, i16* @foo
+ ret void
+}
+; CHECK: am2:
+; CHECK: bis.w r15, &foo
+
+@bar = external global [2 x i8]
+
+define void @am3(i16 %i, i8 %x) nounwind {
+ %1 = getelementptr [2 x i8]* @bar, i16 0, i16 %i
+ %2 = load i8* %1
+ %3 = or i8 %x, %2
+ store i8 %3, i8* %1
+ ret void
+}
+; CHECK: am3:
+; CHECK: bis.b r14, &bar(r15)
+
+define void @am4(i16 %x) nounwind {
+ %1 = volatile load i16* inttoptr(i16 32 to i16*)
+ %2 = or i16 %x, %1
+ volatile store i16 %2, i16* inttoptr(i16 32 to i16*)
+ ret void
+}
+; CHECK: am4:
+; CHECK: bis.w r15, &32
+
+define void @am5(i16* %a, i16 %x) readonly {
+ %1 = getelementptr inbounds i16* %a, i16 2
+ %2 = load i16* %1
+ %3 = or i16 %x, %2
+ store i16 %3, i16* %1
+ ret void
+}
+; CHECK: am5:
+; CHECK: bis.w r14, 4(r15)
+
+%S = type { i16, i16 }
+@baz = common global %S zeroinitializer
+
+define void @am6(i16 %x) nounwind {
+ %1 = load i16* getelementptr (%S* @baz, i32 0, i32 1)
+ %2 = or i16 %x, %1
+ store i16 %2, i16* getelementptr (%S* @baz, i32 0, i32 1)
+ ret void
+}
+; CHECK: am6:
+; CHECK: bis.w r15, &baz+2
+
+%T = type { i16, [2 x i8] }
+@duh = external global %T
+
+define void @am7(i16 %n, i8 %x) nounwind {
+ %1 = getelementptr %T* @duh, i32 0, i32 1
+ %2 = getelementptr [2 x i8]* %1, i16 0, i16 %n
+ %3 = load i8* %2
+ %4 = or i8 %x, %3
+ store i8 %4, i8* %2
+ ret void
+}
+; CHECK: am7:
+; CHECK: bis.b r14, &duh+2(r15)
+
diff --git a/test/CodeGen/MSP430/AddrMode-mov-rx.ll b/test/CodeGen/MSP430/AddrMode-mov-rx.ll
new file mode 100644
index 0000000..67cbb02
--- /dev/null
+++ b/test/CodeGen/MSP430/AddrMode-mov-rx.ll
@@ -0,0 +1,67 @@
+; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
+target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
+target triple = "msp430-generic-generic"
+
+define i16 @am1(i16* %a) nounwind {
+ %1 = load i16* %a
+ ret i16 %1
+}
+; CHECK: am1:
+; CHECK: mov.w 0(r15), r15
+
+@foo = external global i16
+
+define i16 @am2() nounwind {
+ %1 = load i16* @foo
+ ret i16 %1
+}
+; CHECK: am2:
+; CHECK: mov.w &foo, r15
+
+@bar = internal constant [2 x i8] [ i8 32, i8 64 ]
+
+define i8 @am3(i16 %n) nounwind {
+ %1 = getelementptr [2 x i8]* @bar, i16 0, i16 %n
+ %2 = load i8* %1
+ ret i8 %2
+}
+; CHECK: am3:
+; CHECK: mov.b &bar(r15), r15
+
+define i16 @am4() nounwind {
+ %1 = volatile load i16* inttoptr(i16 32 to i16*)
+ ret i16 %1
+}
+; CHECK: am4:
+; CHECK: mov.w &32, r15
+
+define i16 @am5(i16* %a) nounwind {
+ %1 = getelementptr i16* %a, i16 2
+ %2 = load i16* %1
+ ret i16 %2
+}
+; CHECK: am5:
+; CHECK: mov.w 4(r15), r15
+
+%S = type { i16, i16 }
+@baz = common global %S zeroinitializer, align 1
+
+define i16 @am6() nounwind {
+ %1 = load i16* getelementptr (%S* @baz, i32 0, i32 1)
+ ret i16 %1
+}
+; CHECK: am6:
+; CHECK: mov.w &baz+2, r15
+
+%T = type { i16, [2 x i8] }
+@duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] }
+
+define i8 @am7(i16 %n) nounwind {
+ %1 = getelementptr %T* @duh, i32 0, i32 1
+ %2 = getelementptr [2 x i8]* %1, i16 0, i16 %n
+ %3= load i8* %2
+ ret i8 %3
+}
+; CHECK: am7:
+; CHECK: mov.b &duh+2(r15), r15
+
diff --git a/test/CodeGen/MSP430/AddrMode-mov-xr.ll b/test/CodeGen/MSP430/AddrMode-mov-xr.ll
new file mode 100644
index 0000000..b8155d3
--- /dev/null
+++ b/test/CodeGen/MSP430/AddrMode-mov-xr.ll
@@ -0,0 +1,67 @@
+; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
+target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:16"
+target triple = "msp430-generic-generic"
+
+define void @am1(i16* %a, i16 %b) nounwind {
+ store i16 %b, i16* %a
+ ret void
+}
+; CHECK: am1:
+; CHECK: mov.w r14, 0(r15)
+
+@foo = external global i16
+
+define void @am2(i16 %a) nounwind {
+ store i16 %a, i16* @foo
+ ret void
+}
+; CHECK: am2:
+; CHECK: mov.w r15, &foo
+
+@bar = external global [2 x i8]
+
+define void @am3(i16 %i, i8 %a) nounwind {
+ %1 = getelementptr [2 x i8]* @bar, i16 0, i16 %i
+ store i8 %a, i8* %1
+ ret void
+}
+; CHECK: am3:
+; CHECK: mov.b r14, &bar(r15)
+
+define void @am4(i16 %a) nounwind {
+ volatile store i16 %a, i16* inttoptr(i16 32 to i16*)
+ ret void
+}
+; CHECK: am4:
+; CHECK: mov.w r15, &32
+
+define void @am5(i16* nocapture %p, i16 %a) nounwind readonly {
+ %1 = getelementptr inbounds i16* %p, i16 2
+ store i16 %a, i16* %1
+ ret void
+}
+; CHECK: am5:
+; CHECK: mov.w r14, 4(r15)
+
+%S = type { i16, i16 }
+@baz = common global %S zeroinitializer, align 1
+
+define void @am6(i16 %a) nounwind {
+ store i16 %a, i16* getelementptr (%S* @baz, i32 0, i32 1)
+ ret void
+}
+; CHECK: am6:
+; CHECK: mov.w r15, &baz+2
+
+%T = type { i16, [2 x i8] }
+@duh = external global %T
+
+define void @am7(i16 %n, i8 %a) nounwind {
+ %1 = getelementptr %T* @duh, i32 0, i32 1
+ %2 = getelementptr [2 x i8]* %1, i16 0, i16 %n
+ store i8 %a, i8* %2
+ ret void
+}
+; CHECK: am7:
+; CHECK: mov.b r14, &duh+2(r15)
+
diff --git a/test/CodeGen/MSP430/Inst16mi.ll b/test/CodeGen/MSP430/Inst16mi.ll
new file mode 100644
index 0000000..33d7aa4
--- /dev/null
+++ b/test/CodeGen/MSP430/Inst16mi.ll
@@ -0,0 +1,48 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+@foo = common global i16 0, align 2
+
+define void @mov() nounwind {
+; CHECK: mov:
+; CHECK: mov.w #2, &foo
+ store i16 2, i16 * @foo
+ ret void
+}
+
+define void @add() nounwind {
+; CHECK: add:
+; CHECK: add.w #2, &foo
+ %1 = load i16* @foo
+ %2 = add i16 %1, 2
+ store i16 %2, i16 * @foo
+ ret void
+}
+
+define void @and() nounwind {
+; CHECK: and:
+; CHECK: and.w #2, &foo
+ %1 = load i16* @foo
+ %2 = and i16 %1, 2
+ store i16 %2, i16 * @foo
+ ret void
+}
+
+define void @bis() nounwind {
+; CHECK: bis:
+; CHECK: bis.w #2, &foo
+ %1 = load i16* @foo
+ %2 = or i16 %1, 2
+ store i16 %2, i16 * @foo
+ ret void
+}
+
+define void @xor() nounwind {
+; CHECK: xor:
+; CHECK: xor.w #2, &foo
+ %1 = load i16* @foo
+ %2 = xor i16 %1, 2
+ store i16 %2, i16 * @foo
+ ret void
+}
diff --git a/test/CodeGen/MSP430/Inst16mm.ll b/test/CodeGen/MSP430/Inst16mm.ll
new file mode 100644
index 0000000..510afe3
--- /dev/null
+++ b/test/CodeGen/MSP430/Inst16mm.ll
@@ -0,0 +1,54 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+@foo = common global i16 0, align 2
+@bar = common global i16 0, align 2
+
+define void @mov() nounwind {
+; CHECK: mov:
+; CHECK: mov.w &bar, &foo
+ %1 = load i16* @bar
+ store i16 %1, i16* @foo
+ ret void
+}
+
+define void @add() nounwind {
+; CHECK: add:
+; CHECK: add.w &bar, &foo
+ %1 = load i16* @bar
+ %2 = load i16* @foo
+ %3 = add i16 %2, %1
+ store i16 %3, i16* @foo
+ ret void
+}
+
+define void @and() nounwind {
+; CHECK: and:
+; CHECK: and.w &bar, &foo
+ %1 = load i16* @bar
+ %2 = load i16* @foo
+ %3 = and i16 %2, %1
+ store i16 %3, i16* @foo
+ ret void
+}
+
+define void @bis() nounwind {
+; CHECK: bis:
+; CHECK: bis.w &bar, &foo
+ %1 = load i16* @bar
+ %2 = load i16* @foo
+ %3 = or i16 %2, %1
+ store i16 %3, i16* @foo
+ ret void
+}
+
+define void @xor() nounwind {
+; CHECK: xor:
+; CHECK: xor.w &bar, &foo
+ %1 = load i16* @bar
+ %2 = load i16* @foo
+ %3 = xor i16 %2, %1
+ store i16 %3, i16* @foo
+ ret void
+}
+
diff --git a/test/CodeGen/MSP430/Inst16mr.ll b/test/CodeGen/MSP430/Inst16mr.ll
new file mode 100644
index 0000000..2613f01
--- /dev/null
+++ b/test/CodeGen/MSP430/Inst16mr.ll
@@ -0,0 +1,58 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+@foo = common global i16 0, align 2
+
+define void @mov(i16 %a) nounwind {
+; CHECK: mov:
+; CHECK: mov.w r15, &foo
+ store i16 %a, i16* @foo
+ ret void
+}
+
+define void @add(i16 %a) nounwind {
+; CHECK: add:
+; CHECK: add.w r15, &foo
+ %1 = load i16* @foo
+ %2 = add i16 %a, %1
+ store i16 %2, i16* @foo
+ ret void
+}
+
+define void @and(i16 %a) nounwind {
+; CHECK: and:
+; CHECK: and.w r15, &foo
+ %1 = load i16* @foo
+ %2 = and i16 %a, %1
+ store i16 %2, i16* @foo
+ ret void
+}
+
+define void @bis(i16 %a) nounwind {
+; CHECK: bis:
+; CHECK: bis.w r15, &foo
+ %1 = load i16* @foo
+ %2 = or i16 %a, %1
+ store i16 %2, i16* @foo
+ ret void
+}
+
+define void @bic(i16 zeroext %m) nounwind {
+; CHECK: bic:
+; CHECK: bic.w r15, &foo
+ %1 = xor i16 %m, -1
+ %2 = load i16* @foo
+ %3 = and i16 %2, %1
+ store i16 %3, i16* @foo
+ ret void
+}
+
+define void @xor(i16 %a) nounwind {
+; CHECK: xor:
+; CHECK: xor.w r15, &foo
+ %1 = load i16* @foo
+ %2 = xor i16 %a, %1
+ store i16 %2, i16* @foo
+ ret void
+}
+
diff --git a/test/CodeGen/MSP430/Inst16ri.ll b/test/CodeGen/MSP430/Inst16ri.ll
new file mode 100644
index 0000000..5115a23
--- /dev/null
+++ b/test/CodeGen/MSP430/Inst16ri.ll
@@ -0,0 +1,37 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+define i16 @mov() nounwind {
+; CHECK: mov:
+; CHECK: mov.w #1, r15
+ ret i16 1
+}
+
+define i16 @add(i16 %a, i16 %b) nounwind {
+; CHECK: add:
+; CHECK: add.w #1, r15
+ %1 = add i16 %a, 1
+ ret i16 %1
+}
+
+define i16 @and(i16 %a, i16 %b) nounwind {
+; CHECK: and:
+; CHECK: and.w #1, r15
+ %1 = and i16 %a, 1
+ ret i16 %1
+}
+
+define i16 @bis(i16 %a, i16 %b) nounwind {
+; CHECK: bis:
+; CHECK: bis.w #1, r15
+ %1 = or i16 %a, 1
+ ret i16 %1
+}
+
+define i16 @xor(i16 %a, i16 %b) nounwind {
+; CHECK: xor:
+; CHECK: xor.w #1, r15
+ %1 = xor i16 %a, 1
+ ret i16 %1
+}
diff --git a/test/CodeGen/MSP430/Inst16rm.ll b/test/CodeGen/MSP430/Inst16rm.ll
new file mode 100644
index 0000000..02e89c7
--- /dev/null
+++ b/test/CodeGen/MSP430/Inst16rm.ll
@@ -0,0 +1,46 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+@foo = common global i16 0, align 2
+
+define i16 @add(i16 %a) nounwind {
+; CHECK: add:
+; CHECK: add.w &foo, r15
+ %1 = load i16* @foo
+ %2 = add i16 %a, %1
+ ret i16 %2
+}
+
+define i16 @and(i16 %a) nounwind {
+; CHECK: and:
+; CHECK: and.w &foo, r15
+ %1 = load i16* @foo
+ %2 = and i16 %a, %1
+ ret i16 %2
+}
+
+define i16 @bis(i16 %a) nounwind {
+; CHECK: bis:
+; CHECK: bis.w &foo, r15
+ %1 = load i16* @foo
+ %2 = or i16 %a, %1
+ ret i16 %2
+}
+
+define i16 @bic(i16 %a) nounwind {
+; CHECK: bic:
+; CHECK: bic.w &foo, r15
+ %1 = load i16* @foo
+ %2 = xor i16 %1, -1
+ %3 = and i16 %a, %2
+ ret i16 %3
+}
+
+define i16 @xor(i16 %a) nounwind {
+; CHECK: xor:
+; CHECK: xor.w &foo, r15
+ %1 = load i16* @foo
+ %2 = xor i16 %a, %1
+ ret i16 %2
+}
+
diff --git a/test/CodeGen/MSP430/Inst16rr.ll b/test/CodeGen/MSP430/Inst16rr.ll
new file mode 100644
index 0000000..2f1ba5b4
--- /dev/null
+++ b/test/CodeGen/MSP430/Inst16rr.ll
@@ -0,0 +1,45 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+define i16 @mov(i16 %a, i16 %b) nounwind {
+; CHECK: mov:
+; CHECK: mov.w r14, r15
+ ret i16 %b
+}
+
+define i16 @add(i16 %a, i16 %b) nounwind {
+; CHECK: add:
+; CHECK: add.w r14, r15
+ %1 = add i16 %a, %b
+ ret i16 %1
+}
+
+define i16 @and(i16 %a, i16 %b) nounwind {
+; CHECK: and:
+; CHECK: and.w r14, r15
+ %1 = and i16 %a, %b
+ ret i16 %1
+}
+
+define i16 @bis(i16 %a, i16 %b) nounwind {
+; CHECK: bis:
+; CHECK: bis.w r14, r15
+ %1 = or i16 %a, %b
+ ret i16 %1
+}
+
+define i16 @bic(i16 %a, i16 %b) nounwind {
+; CHECK: bic:
+; CHECK: bic.w r14, r15
+ %1 = xor i16 %b, -1
+ %2 = and i16 %a, %1
+ ret i16 %2
+}
+
+define i16 @xor(i16 %a, i16 %b) nounwind {
+; CHECK: xor:
+; CHECK: xor.w r14, r15
+ %1 = xor i16 %a, %b
+ ret i16 %1
+}
diff --git a/test/CodeGen/MSP430/Inst8mi.ll b/test/CodeGen/MSP430/Inst8mi.ll
new file mode 100644
index 0000000..ef318ce
--- /dev/null
+++ b/test/CodeGen/MSP430/Inst8mi.ll
@@ -0,0 +1,48 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i8:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+@foo = common global i8 0, align 1
+
+define void @mov() nounwind {
+; CHECK: mov:
+; CHECK: mov.b #2, &foo
+ store i8 2, i8 * @foo
+ ret void
+}
+
+define void @add() nounwind {
+; CHECK: add:
+; CHECK: add.b #2, &foo
+ %1 = load i8* @foo
+ %2 = add i8 %1, 2
+ store i8 %2, i8 * @foo
+ ret void
+}
+
+define void @and() nounwind {
+; CHECK: and:
+; CHECK: and.b #2, &foo
+ %1 = load i8* @foo
+ %2 = and i8 %1, 2
+ store i8 %2, i8 * @foo
+ ret void
+}
+
+define void @bis() nounwind {
+; CHECK: bis:
+; CHECK: bis.b #2, &foo
+ %1 = load i8* @foo
+ %2 = or i8 %1, 2
+ store i8 %2, i8 * @foo
+ ret void
+}
+
+define void @xor() nounwind {
+; CHECK: xor:
+; CHECK: xor.b #2, &foo
+ %1 = load i8* @foo
+ %2 = xor i8 %1, 2
+ store i8 %2, i8 * @foo
+ ret void
+}
+
diff --git a/test/CodeGen/MSP430/Inst8mm.ll b/test/CodeGen/MSP430/Inst8mm.ll
new file mode 100644
index 0000000..a2987ac
--- /dev/null
+++ b/test/CodeGen/MSP430/Inst8mm.ll
@@ -0,0 +1,55 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+@foo = common global i8 0, align 1
+@bar = common global i8 0, align 1
+
+define void @mov() nounwind {
+; CHECK: mov:
+; CHECK: mov.b &bar, &foo
+ %1 = load i8* @bar
+ store i8 %1, i8* @foo
+ ret void
+}
+
+define void @add() nounwind {
+; CHECK: add:
+; CHECK: add.b &bar, &foo
+ %1 = load i8* @bar
+ %2 = load i8* @foo
+ %3 = add i8 %2, %1
+ store i8 %3, i8* @foo
+ ret void
+}
+
+define void @and() nounwind {
+; CHECK: and:
+; CHECK: and.b &bar, &foo
+ %1 = load i8* @bar
+ %2 = load i8* @foo
+ %3 = and i8 %2, %1
+ store i8 %3, i8* @foo
+ ret void
+}
+
+define void @bis() nounwind {
+; CHECK: bis:
+; CHECK: bis.b &bar, &foo
+ %1 = load i8* @bar
+ %2 = load i8* @foo
+ %3 = or i8 %2, %1
+ store i8 %3, i8* @foo
+ ret void
+}
+
+define void @xor() nounwind {
+; CHECK: xor:
+; CHECK: xor.b &bar, &foo
+ %1 = load i8* @bar
+ %2 = load i8* @foo
+ %3 = xor i8 %2, %1
+ store i8 %3, i8* @foo
+ ret void
+}
+
diff --git a/test/CodeGen/MSP430/Inst8mr.ll b/test/CodeGen/MSP430/Inst8mr.ll
new file mode 100644
index 0000000..428d1fa
--- /dev/null
+++ b/test/CodeGen/MSP430/Inst8mr.ll
@@ -0,0 +1,58 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+@foo = common global i8 0, align 1
+
+define void @mov(i8 %a) nounwind {
+; CHECK: mov:
+; CHECK: mov.b r15, &foo
+ store i8 %a, i8* @foo
+ ret void
+}
+
+define void @and(i8 %a) nounwind {
+; CHECK: and:
+; CHECK: and.b r15, &foo
+ %1 = load i8* @foo
+ %2 = and i8 %a, %1
+ store i8 %2, i8* @foo
+ ret void
+}
+
+define void @add(i8 %a) nounwind {
+; CHECK: add:
+; CHECK: add.b r15, &foo
+ %1 = load i8* @foo
+ %2 = add i8 %a, %1
+ store i8 %2, i8* @foo
+ ret void
+}
+
+define void @bis(i8 %a) nounwind {
+; CHECK: bis:
+; CHECK: bis.b r15, &foo
+ %1 = load i8* @foo
+ %2 = or i8 %a, %1
+ store i8 %2, i8* @foo
+ ret void
+}
+
+define void @bic(i8 zeroext %m) nounwind {
+; CHECK: bic:
+; CHECK: bic.b r15, &foo
+ %1 = xor i8 %m, -1
+ %2 = load i8* @foo
+ %3 = and i8 %2, %1
+ store i8 %3, i8* @foo
+ ret void
+}
+
+define void @xor(i8 %a) nounwind {
+; CHECK: xor:
+; CHECK: xor.b r15, &foo
+ %1 = load i8* @foo
+ %2 = xor i8 %a, %1
+ store i8 %2, i8* @foo
+ ret void
+}
+
diff --git a/test/CodeGen/MSP430/Inst8ri.ll b/test/CodeGen/MSP430/Inst8ri.ll
new file mode 100644
index 0000000..ac3418a
--- /dev/null
+++ b/test/CodeGen/MSP430/Inst8ri.ll
@@ -0,0 +1,37 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+define i8 @mov() nounwind {
+; CHECK: mov:
+; CHECK: mov.b #1, r15
+ ret i8 1
+}
+
+define i8 @add(i8 %a, i8 %b) nounwind {
+; CHECK: add:
+; CHECK: add.b #1, r15
+ %1 = add i8 %a, 1
+ ret i8 %1
+}
+
+define i8 @and(i8 %a, i8 %b) nounwind {
+; CHECK: and:
+; CHECK: and.b #1, r15
+ %1 = and i8 %a, 1
+ ret i8 %1
+}
+
+define i8 @bis(i8 %a, i8 %b) nounwind {
+; CHECK: bis:
+; CHECK: bis.b #1, r15
+ %1 = or i8 %a, 1
+ ret i8 %1
+}
+
+define i8 @xor(i8 %a, i8 %b) nounwind {
+; CHECK: xor:
+; CHECK: xor.b #1, r15
+ %1 = xor i8 %a, 1
+ ret i8 %1
+}
diff --git a/test/CodeGen/MSP430/Inst8rm.ll b/test/CodeGen/MSP430/Inst8rm.ll
new file mode 100644
index 0000000..c062f04
--- /dev/null
+++ b/test/CodeGen/MSP430/Inst8rm.ll
@@ -0,0 +1,46 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i8:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+@foo = common global i8 0, align 1
+
+define i8 @add(i8 %a) nounwind {
+; CHECK: add:
+; CHECK: add.b &foo, r15
+ %1 = load i8* @foo
+ %2 = add i8 %a, %1
+ ret i8 %2
+}
+
+define i8 @and(i8 %a) nounwind {
+; CHECK: and:
+; CHECK: and.b &foo, r15
+ %1 = load i8* @foo
+ %2 = and i8 %a, %1
+ ret i8 %2
+}
+
+define i8 @bis(i8 %a) nounwind {
+; CHECK: bis:
+; CHECK: bis.b &foo, r15
+ %1 = load i8* @foo
+ %2 = or i8 %a, %1
+ ret i8 %2
+}
+
+define i8 @bic(i8 %a) nounwind {
+; CHECK: bic:
+; CHECK: bic.b &foo, r15
+ %1 = load i8* @foo
+ %2 = xor i8 %1, -1
+ %3 = and i8 %a, %2
+ ret i8 %3
+}
+
+define i8 @xor(i8 %a) nounwind {
+; CHECK: xor:
+; CHECK: xor.b &foo, r15
+ %1 = load i8* @foo
+ %2 = xor i8 %a, %1
+ ret i8 %2
+}
+
diff --git a/test/CodeGen/MSP430/Inst8rr.ll b/test/CodeGen/MSP430/Inst8rr.ll
new file mode 100644
index 0000000..74feaae
--- /dev/null
+++ b/test/CodeGen/MSP430/Inst8rr.ll
@@ -0,0 +1,46 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i8:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+define i8 @mov(i8 %a, i8 %b) nounwind {
+; CHECK: mov:
+; CHECK: mov.b r14, r15
+ ret i8 %b
+}
+
+define i8 @add(i8 %a, i8 %b) nounwind {
+; CHECK: add:
+; CHECK: add.b r14, r15
+ %1 = add i8 %a, %b
+ ret i8 %1
+}
+
+define i8 @and(i8 %a, i8 %b) nounwind {
+; CHECK: and:
+; CHECK: and.w r14, r15
+ %1 = and i8 %a, %b
+ ret i8 %1
+}
+
+define i8 @bis(i8 %a, i8 %b) nounwind {
+; CHECK: bis:
+; CHECK: bis.w r14, r15
+ %1 = or i8 %a, %b
+ ret i8 %1
+}
+
+define i8 @bic(i8 %a, i8 %b) nounwind {
+; CHECK: bic:
+; CHECK: bic.b r14, r15
+ %1 = xor i8 %b, -1
+ %2 = and i8 %a, %1
+ ret i8 %2
+}
+
+define i8 @xor(i8 %a, i8 %b) nounwind {
+; CHECK: xor:
+; CHECK: xor.w r14, r15
+ %1 = xor i8 %a, %b
+ ret i8 %1
+}
+
diff --git a/test/CodeGen/MSP430/bit.ll b/test/CodeGen/MSP430/bit.ll
new file mode 100644
index 0000000..cd664a1
--- /dev/null
+++ b/test/CodeGen/MSP430/bit.ll
@@ -0,0 +1,166 @@
+; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
+target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
+target triple = "msp430-generic-generic"
+
+@foo8 = external global i8
+@bar8 = external global i8
+
+define i8 @bitbrr(i8 %a, i8 %b) nounwind {
+ %t1 = and i8 %a, %b
+ %t2 = icmp ne i8 %t1, 0
+ %t3 = zext i1 %t2 to i8
+ ret i8 %t3
+}
+; CHECK: bitbrr:
+; CHECK: bit.b r14, r15
+
+define i8 @bitbri(i8 %a) nounwind {
+ %t1 = and i8 %a, 15
+ %t2 = icmp ne i8 %t1, 0
+ %t3 = zext i1 %t2 to i8
+ ret i8 %t3
+}
+; CHECK: bitbri:
+; CHECK: bit.b #15, r15
+
+define i8 @bitbir(i8 %a) nounwind {
+ %t1 = and i8 15, %a
+ %t2 = icmp ne i8 %t1, 0
+ %t3 = zext i1 %t2 to i8
+ ret i8 %t3
+}
+; CHECK: bitbir:
+; CHECK: bit.b #15, r15
+
+define i8 @bitbmi() nounwind {
+ %t1 = load i8* @foo8
+ %t2 = and i8 %t1, 15
+ %t3 = icmp ne i8 %t2, 0
+ %t4 = zext i1 %t3 to i8
+ ret i8 %t4
+}
+; CHECK: bitbmi:
+; CHECK: bit.b #15, &foo8
+
+define i8 @bitbim() nounwind {
+ %t1 = load i8* @foo8
+ %t2 = and i8 15, %t1
+ %t3 = icmp ne i8 %t2, 0
+ %t4 = zext i1 %t3 to i8
+ ret i8 %t4
+}
+; CHECK: bitbim:
+; CHECK: bit.b #15, &foo8
+
+define i8 @bitbrm(i8 %a) nounwind {
+ %t1 = load i8* @foo8
+ %t2 = and i8 %a, %t1
+ %t3 = icmp ne i8 %t2, 0
+ %t4 = zext i1 %t3 to i8
+ ret i8 %t4
+}
+; CHECK: bitbrm:
+; CHECK: bit.b &foo8, r15
+
+define i8 @bitbmr(i8 %a) nounwind {
+ %t1 = load i8* @foo8
+ %t2 = and i8 %t1, %a
+ %t3 = icmp ne i8 %t2, 0
+ %t4 = zext i1 %t3 to i8
+ ret i8 %t4
+}
+; CHECK: bitbmr:
+; CHECK: bit.b r15, &foo8
+
+define i8 @bitbmm() nounwind {
+ %t1 = load i8* @foo8
+ %t2 = load i8* @bar8
+ %t3 = and i8 %t1, %t2
+ %t4 = icmp ne i8 %t3, 0
+ %t5 = zext i1 %t4 to i8
+ ret i8 %t5
+}
+; CHECK: bitbmm:
+; CHECK: bit.b &bar8, &foo8
+
+@foo16 = external global i16
+@bar16 = external global i16
+
+define i16 @bitwrr(i16 %a, i16 %b) nounwind {
+ %t1 = and i16 %a, %b
+ %t2 = icmp ne i16 %t1, 0
+ %t3 = zext i1 %t2 to i16
+ ret i16 %t3
+}
+; CHECK: bitwrr:
+; CHECK: bit.w r14, r15
+
+define i16 @bitwri(i16 %a) nounwind {
+ %t1 = and i16 %a, 4080
+ %t2 = icmp ne i16 %t1, 0
+ %t3 = zext i1 %t2 to i16
+ ret i16 %t3
+}
+; CHECK: bitwri:
+; CHECK: bit.w #4080, r15
+
+define i16 @bitwir(i16 %a) nounwind {
+ %t1 = and i16 4080, %a
+ %t2 = icmp ne i16 %t1, 0
+ %t3 = zext i1 %t2 to i16
+ ret i16 %t3
+}
+; CHECK: bitwir:
+; CHECK: bit.w #4080, r15
+
+define i16 @bitwmi() nounwind {
+ %t1 = load i16* @foo16
+ %t2 = and i16 %t1, 4080
+ %t3 = icmp ne i16 %t2, 0
+ %t4 = zext i1 %t3 to i16
+ ret i16 %t4
+}
+; CHECK: bitwmi:
+; CHECK: bit.w #4080, &foo16
+
+define i16 @bitwim() nounwind {
+ %t1 = load i16* @foo16
+ %t2 = and i16 4080, %t1
+ %t3 = icmp ne i16 %t2, 0
+ %t4 = zext i1 %t3 to i16
+ ret i16 %t4
+}
+; CHECK: bitwim:
+; CHECK: bit.w #4080, &foo16
+
+define i16 @bitwrm(i16 %a) nounwind {
+ %t1 = load i16* @foo16
+ %t2 = and i16 %a, %t1
+ %t3 = icmp ne i16 %t2, 0
+ %t4 = zext i1 %t3 to i16
+ ret i16 %t4
+}
+; CHECK: bitwrm:
+; CHECK: bit.w &foo16, r15
+
+define i16 @bitwmr(i16 %a) nounwind {
+ %t1 = load i16* @foo16
+ %t2 = and i16 %t1, %a
+ %t3 = icmp ne i16 %t2, 0
+ %t4 = zext i1 %t3 to i16
+ ret i16 %t4
+}
+; CHECK: bitwmr:
+; CHECK: bit.w r15, &foo16
+
+define i16 @bitwmm() nounwind {
+ %t1 = load i16* @foo16
+ %t2 = load i16* @bar16
+ %t3 = and i16 %t1, %t2
+ %t4 = icmp ne i16 %t3, 0
+ %t5 = zext i1 %t4 to i16
+ ret i16 %t5
+}
+; CHECK: bitwmm:
+; CHECK: bit.w &bar16, &foo16
+
diff --git a/test/CodeGen/MSP430/dg.exp b/test/CodeGen/MSP430/dg.exp
new file mode 100644
index 0000000..e4ea13a
--- /dev/null
+++ b/test/CodeGen/MSP430/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target MSP430] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/MSP430/inline-asm.ll b/test/CodeGen/MSP430/inline-asm.ll
new file mode 100644
index 0000000..0e7886a
--- /dev/null
+++ b/test/CodeGen/MSP430/inline-asm.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430-generic-generic"
+
+define void @imm() nounwind {
+ call void asm sideeffect "bic\09$0,r2", "i"(i16 32) nounwind
+ ret void
+}
+
+define void @reg(i16 %a) nounwind {
+ call void asm sideeffect "bic\09$0,r2", "r"(i16 %a) nounwind
+ ret void
+}
+
+@foo = global i16 0, align 2
+
+define void @immmem() nounwind {
+ call void asm sideeffect "bic\09$0,r2", "i"(i16* getelementptr(i16* @foo, i32 1)) nounwind
+ ret void
+}
+
+define void @mem() nounwind {
+ %fooval = load i16* @foo
+ call void asm sideeffect "bic\09$0,r2", "m"(i16 %fooval) nounwind
+ ret void
+}
diff --git a/test/CodeGen/MSP430/postinc.ll b/test/CodeGen/MSP430/postinc.ll
new file mode 100644
index 0000000..8f01b83
--- /dev/null
+++ b/test/CodeGen/MSP430/postinc.ll
@@ -0,0 +1,114 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
+target triple = "msp430"
+
+define zeroext i16 @add(i16* nocapture %a, i16 zeroext %n) nounwind readonly {
+entry:
+ %cmp8 = icmp eq i16 %n, 0 ; <i1> [#uses=1]
+ br i1 %cmp8, label %for.end, label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
+ %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+ %arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
+; CHECK: add:
+; CHECK: add.w @r{{[0-9]+}}+, r{{[0-9]+}}
+ %tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
+ %add = add i16 %tmp4, %sum.09 ; <i16> [#uses=2]
+ %inc = add i16 %i.010, 1 ; <i16> [#uses=2]
+ %exitcond = icmp eq i16 %inc, %n ; <i1> [#uses=1]
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end: ; preds = %for.body, %entry
+ %sum.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+ ret i16 %sum.0.lcssa
+}
+
+define zeroext i16 @sub(i16* nocapture %a, i16 zeroext %n) nounwind readonly {
+entry:
+ %cmp8 = icmp eq i16 %n, 0 ; <i1> [#uses=1]
+ br i1 %cmp8, label %for.end, label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
+ %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+ %arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
+; CHECK: sub:
+; CHECK: sub.w @r{{[0-9]+}}+, r{{[0-9]+}}
+ %tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
+ %add = sub i16 %tmp4, %sum.09 ; <i16> [#uses=2]
+ %inc = add i16 %i.010, 1 ; <i16> [#uses=2]
+ %exitcond = icmp eq i16 %inc, %n ; <i1> [#uses=1]
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end: ; preds = %for.body, %entry
+ %sum.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+ ret i16 %sum.0.lcssa
+}
+
+define zeroext i16 @or(i16* nocapture %a, i16 zeroext %n) nounwind readonly {
+entry:
+ %cmp8 = icmp eq i16 %n, 0 ; <i1> [#uses=1]
+ br i1 %cmp8, label %for.end, label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
+ %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+ %arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
+; CHECK: or:
+; CHECK: bis.w @r{{[0-9]+}}+, r{{[0-9]+}}
+ %tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
+ %add = or i16 %tmp4, %sum.09 ; <i16> [#uses=2]
+ %inc = add i16 %i.010, 1 ; <i16> [#uses=2]
+ %exitcond = icmp eq i16 %inc, %n ; <i1> [#uses=1]
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end: ; preds = %for.body, %entry
+ %sum.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+ ret i16 %sum.0.lcssa
+}
+
+define zeroext i16 @xor(i16* nocapture %a, i16 zeroext %n) nounwind readonly {
+entry:
+ %cmp8 = icmp eq i16 %n, 0 ; <i1> [#uses=1]
+ br i1 %cmp8, label %for.end, label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
+ %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+ %arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
+; CHECK: xor:
+; CHECK: xor.w @r{{[0-9]+}}+, r{{[0-9]+}}
+ %tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
+ %add = xor i16 %tmp4, %sum.09 ; <i16> [#uses=2]
+ %inc = add i16 %i.010, 1 ; <i16> [#uses=2]
+ %exitcond = icmp eq i16 %inc, %n ; <i1> [#uses=1]
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end: ; preds = %for.body, %entry
+ %sum.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+ ret i16 %sum.0.lcssa
+}
+
+define zeroext i16 @and(i16* nocapture %a, i16 zeroext %n) nounwind readonly {
+entry:
+ %cmp8 = icmp eq i16 %n, 0 ; <i1> [#uses=1]
+ br i1 %cmp8, label %for.end, label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
+ %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+ %arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
+; CHECK: and:
+; CHECK: and.w @r{{[0-9]+}}+, r{{[0-9]+}}
+ %tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
+ %add = and i16 %tmp4, %sum.09 ; <i16> [#uses=2]
+ %inc = add i16 %i.010, 1 ; <i16> [#uses=2]
+ %exitcond = icmp eq i16 %inc, %n ; <i1> [#uses=1]
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end: ; preds = %for.body, %entry
+ %sum.0.lcssa = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
+ ret i16 %sum.0.lcssa
+}
+
diff --git a/test/CodeGen/MSP430/setcc.ll b/test/CodeGen/MSP430/setcc.ll
new file mode 100644
index 0000000..9db51cc
--- /dev/null
+++ b/test/CodeGen/MSP430/setcc.ll
@@ -0,0 +1,116 @@
+; RUN: llc -march=msp430 < %s | FileCheck %s
+target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
+target triple = "msp430-generic-generic"
+
+define i16 @sccweqand(i16 %a, i16 %b) nounwind {
+ %t1 = and i16 %a, %b
+ %t2 = icmp eq i16 %t1, 0
+ %t3 = zext i1 %t2 to i16
+ ret i16 %t3
+}
+; CHECK: sccweqand:
+; CHECK: bit.w r14, r15
+; CHECK-NEXT: mov.w r2, r15
+; CHECK-NEXT: and.w #1, r15
+; CHECK-NEXT: xor.w #1, r15
+
+define i16 @sccwneand(i16 %a, i16 %b) nounwind {
+ %t1 = and i16 %a, %b
+ %t2 = icmp ne i16 %t1, 0
+ %t3 = zext i1 %t2 to i16
+ ret i16 %t3
+}
+; CHECK: sccwneand:
+; CHECK: bit.w r14, r15
+; CHECK-NEXT: mov.w r2, r15
+; CHECK-NEXT: and.w #1, r15
+
+define i16 @sccwne(i16 %a, i16 %b) nounwind {
+ %t1 = icmp ne i16 %a, %b
+ %t2 = zext i1 %t1 to i16
+ ret i16 %t2
+}
+; CHECK:sccwne:
+; CHECK: cmp.w r14, r15
+; CHECK-NEXT: mov.w r2, r15
+; CHECK-NEXT: rra.w r15
+; CHECK-NEXT: and.w #1, r15
+
+define i16 @sccweq(i16 %a, i16 %b) nounwind {
+ %t1 = icmp eq i16 %a, %b
+ %t2 = zext i1 %t1 to i16
+ ret i16 %t2
+}
+; CHECK:sccweq:
+; CHECK: cmp.w r14, r15
+; CHECK-NEXT: mov.w r2, r15
+; CHECK-NEXT: rra.w r15
+; CHECK-NEXT: and.w #1, r15
+; CHECK-NEXT: xor.w #1, r15
+
+define i16 @sccwugt(i16 %a, i16 %b) nounwind {
+ %t1 = icmp ugt i16 %a, %b
+ %t2 = zext i1 %t1 to i16
+ ret i16 %t2
+}
+; CHECK:sccwugt:
+; CHECK: cmp.w r15, r14
+; CHECK-NEXT: mov.w r2, r15
+; CHECK-NEXT: and.w #1, r15
+; CHECK-NEXT: xor.w #1, r15
+
+define i16 @sccwuge(i16 %a, i16 %b) nounwind {
+ %t1 = icmp uge i16 %a, %b
+ %t2 = zext i1 %t1 to i16
+ ret i16 %t2
+}
+; CHECK:sccwuge:
+; CHECK: cmp.w r14, r15
+; CHECK-NEXT: mov.w r2, r15
+; CHECK-NEXT: and.w #1, r15
+
+define i16 @sccwult(i16 %a, i16 %b) nounwind {
+ %t1 = icmp ult i16 %a, %b
+ %t2 = zext i1 %t1 to i16
+ ret i16 %t2
+}
+; CHECK:sccwult:
+; CHECK: cmp.w r14, r15
+; CHECK-NEXT: mov.w r2, r15
+; CHECK-NEXT: and.w #1, r15
+; CHECK-NEXT: xor.w #1, r15
+
+define i16 @sccwule(i16 %a, i16 %b) nounwind {
+ %t1 = icmp ule i16 %a, %b
+ %t2 = zext i1 %t1 to i16
+ ret i16 %t2
+}
+; CHECK:sccwule:
+; CHECK: cmp.w r15, r14
+; CHECK-NEXT: mov.w r2, r15
+; CHECK-NEXT: and.w #1, r15
+
+define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
+ %t1 = icmp sgt i16 %a, %b
+ %t2 = zext i1 %t1 to i16
+ ret i16 %t2
+}
+
+define i16 @sccwsge(i16 %a, i16 %b) nounwind {
+ %t1 = icmp sge i16 %a, %b
+ %t2 = zext i1 %t1 to i16
+ ret i16 %t2
+}
+
+define i16 @sccwslt(i16 %a, i16 %b) nounwind {
+ %t1 = icmp slt i16 %a, %b
+ %t2 = zext i1 %t1 to i16
+ ret i16 %t2
+}
+
+define i16 @sccwsle(i16 %a, i16 %b) nounwind {
+ %t1 = icmp sle i16 %a, %b
+ %t2 = zext i1 %t1 to i16
+ ret i16 %t2
+}
+
diff --git a/test/CodeGen/MSP430/shifts.ll b/test/CodeGen/MSP430/shifts.ll
new file mode 100644
index 0000000..b5b3054
--- /dev/null
+++ b/test/CodeGen/MSP430/shifts.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-n8:16"
+target triple = "msp430-elf"
+
+define zeroext i8 @lshr8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK: lshr8:
+; CHECK: rrc.b
+ %shr = lshr i8 %a, %cnt
+ ret i8 %shr
+}
+
+define signext i8 @ashr8(i8 signext %a, i8 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK: ashr8:
+; CHECK: rra.b
+ %shr = ashr i8 %a, %cnt
+ ret i8 %shr
+}
+
+define zeroext i8 @shl8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK: shl8
+; CHECK: rla.b
+ %shl = shl i8 %a, %cnt
+ ret i8 %shl
+}
+
+define zeroext i16 @lshr16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK: lshr16:
+; CHECK: rrc.w
+ %shr = lshr i16 %a, %cnt
+ ret i16 %shr
+}
+
+define signext i16 @ashr16(i16 signext %a, i16 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK: ashr16:
+; CHECK: rra.w
+ %shr = ashr i16 %a, %cnt
+ ret i16 %shr
+}
+
+define zeroext i16 @shl16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
+entry:
+; CHECK: shl16:
+; CHECK: rla.w
+ %shl = shl i16 %a, %cnt
+ ret i16 %shl
+}
diff --git a/test/CodeGen/Mips/2008-06-05-Carry.ll b/test/CodeGen/Mips/2008-06-05-Carry.ll
new file mode 100644
index 0000000..8e7b70e
--- /dev/null
+++ b/test/CodeGen/Mips/2008-06-05-Carry.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=mips -o %t
+; RUN: grep subu %t | count 2
+; RUN: grep addu %t | count 4
+
+target datalayout =
+"e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define i64 @add64(i64 %u, i64 %v) nounwind {
+entry:
+ %tmp2 = add i64 %u, %v
+ ret i64 %tmp2
+}
+
+define i64 @sub64(i64 %u, i64 %v) nounwind {
+entry:
+ %tmp2 = sub i64 %u, %v
+ ret i64 %tmp2
+}
diff --git a/test/CodeGen/Mips/2008-07-03-SRet.ll b/test/CodeGen/Mips/2008-07-03-SRet.ll
new file mode 100644
index 0000000..b2aaa00
--- /dev/null
+++ b/test/CodeGen/Mips/2008-07-03-SRet.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=mips | grep {sw.*(\$4)} | count 3
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+ %struct.sret0 = type { i32, i32, i32 }
+
+define void @test0(%struct.sret0* noalias sret %agg.result, i32 %dummy) nounwind {
+entry:
+ getelementptr %struct.sret0* %agg.result, i32 0, i32 0 ; <i32*>:0 [#uses=1]
+ store i32 %dummy, i32* %0, align 4
+ getelementptr %struct.sret0* %agg.result, i32 0, i32 1 ; <i32*>:1 [#uses=1]
+ store i32 %dummy, i32* %1, align 4
+ getelementptr %struct.sret0* %agg.result, i32 0, i32 2 ; <i32*>:2 [#uses=1]
+ store i32 %dummy, i32* %2, align 4
+ ret void
+}
+
diff --git a/test/CodeGen/Mips/2008-07-05-ByVal.ll b/test/CodeGen/Mips/2008-07-05-ByVal.ll
new file mode 100644
index 0000000..6bb6bd8
--- /dev/null
+++ b/test/CodeGen/Mips/2008-07-05-ByVal.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=mips | grep {lw.*(\$4)} | count 2
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+ %struct.byval0 = type { i32, i32 }
+
+define i64 @test0(%struct.byval0* byval %b, i64 %sum) nounwind {
+entry:
+ getelementptr %struct.byval0* %b, i32 0, i32 0 ; <i32*>:0 [#uses=1]
+ load i32* %0, align 4 ; <i32>:1 [#uses=1]
+ getelementptr %struct.byval0* %b, i32 0, i32 1 ; <i32*>:2 [#uses=1]
+ load i32* %2, align 4 ; <i32>:3 [#uses=1]
+ add i32 %3, %1 ; <i32>:4 [#uses=1]
+ sext i32 %4 to i64 ; <i64>:5 [#uses=1]
+ add i64 %5, %sum ; <i64>:6 [#uses=1]
+ ret i64 %6
+}
+
diff --git a/test/CodeGen/Mips/2008-07-06-fadd64.ll b/test/CodeGen/Mips/2008-07-06-fadd64.ll
new file mode 100644
index 0000000..808ce16
--- /dev/null
+++ b/test/CodeGen/Mips/2008-07-06-fadd64.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=mips | grep __adddf3
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define double @dofloat(double %a, double %b) nounwind {
+entry:
+ fadd double %a, %b ; <double>:0 [#uses=1]
+ ret double %0
+}
diff --git a/test/CodeGen/Mips/2008-07-07-FPExtend.ll b/test/CodeGen/Mips/2008-07-07-FPExtend.ll
new file mode 100644
index 0000000..7ac0f5f
--- /dev/null
+++ b/test/CodeGen/Mips/2008-07-07-FPExtend.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=mips | grep __extendsfdf2
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define double @dofloat(float %a) nounwind {
+entry:
+ fpext float %a to double ; <double>:0 [#uses=1]
+ ret double %0
+}
diff --git a/test/CodeGen/Mips/2008-07-07-Float2Int.ll b/test/CodeGen/Mips/2008-07-07-Float2Int.ll
new file mode 100644
index 0000000..ca99636
--- /dev/null
+++ b/test/CodeGen/Mips/2008-07-07-Float2Int.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=mips | grep trunc.w.s | count 3
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define i32 @fptoint(float %a) nounwind {
+entry:
+ fptosi float %a to i32 ; <i32>:0 [#uses=1]
+ ret i32 %0
+}
+
+define i32 @fptouint(float %a) nounwind {
+entry:
+ fptoui float %a to i32 ; <i32>:0 [#uses=1]
+ ret i32 %0
+}
diff --git a/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll b/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll
new file mode 100644
index 0000000..20de18a
--- /dev/null
+++ b/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=mips -o %t
+; RUN: grep __floatsidf %t | count 1
+; RUN: grep __floatunsidf %t | count 1
+; RUN: grep __fixdfsi %t | count 1
+; RUN: grep __fixunsdfsi %t | count 1
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define double @int2fp(i32 %a) nounwind {
+entry:
+ sitofp i32 %a to double ; <double>:0 [#uses=1]
+ ret double %0
+}
+
+define double @uint2double(i32 %a) nounwind {
+entry:
+ uitofp i32 %a to double ; <double>:0 [#uses=1]
+ ret double %0
+}
+
+define i32 @double2int(double %a) nounwind {
+entry:
+ fptosi double %a to i32 ; <i32>:0 [#uses=1]
+ ret i32 %0
+}
+
+define i32 @double2uint(double %a) nounwind {
+entry:
+ fptoui double %a to i32 ; <i32>:0 [#uses=1]
+ ret i32 %0
+}
+
diff --git a/test/CodeGen/Mips/2008-07-15-InternalConstant.ll b/test/CodeGen/Mips/2008-07-15-InternalConstant.ll
new file mode 100644
index 0000000..f6b2045
--- /dev/null
+++ b/test/CodeGen/Mips/2008-07-15-InternalConstant.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=mips -o %t
+; RUN: grep {rodata.str1.4,"aMS",@progbits} %t | count 1
+; RUN: grep {r.data,} %t | count 1
+; RUN: grep {\%hi} %t | count 2
+; RUN: grep {\%lo} %t | count 2
+; RUN: not grep {gp_rel} %t
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
[email protected] = internal constant [10 x i8] c"AAAAAAAAA\00"
+@i0 = internal constant [5 x i32] [ i32 0, i32 1, i32 2, i32 3, i32 4 ]
+
+define i8* @foo() nounwind {
+entry:
+ ret i8* getelementptr ([10 x i8]* @.str, i32 0, i32 0)
+}
+
+define i32* @bar() nounwind {
+entry:
+ ret i32* getelementptr ([5 x i32]* @i0, i32 0, i32 0)
+}
+
diff --git a/test/CodeGen/Mips/2008-07-15-SmallSection.ll b/test/CodeGen/Mips/2008-07-15-SmallSection.ll
new file mode 100644
index 0000000..26eb4db
--- /dev/null
+++ b/test/CodeGen/Mips/2008-07-15-SmallSection.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -mips-ssection-threshold=8 -march=mips -o %t0
+; RUN: llc < %s -mips-ssection-threshold=0 -march=mips -o %t1
+; RUN: grep {sdata} %t0 | count 1
+; RUN: grep {sbss} %t0 | count 1
+; RUN: grep {gp_rel} %t0 | count 2
+; RUN: not grep {sdata} %t1
+; RUN: not grep {sbss} %t1
+; RUN: not grep {gp_rel} %t1
+; RUN: grep {\%hi} %t1 | count 2
+; RUN: grep {\%lo} %t1 | count 2
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+ %struct.anon = type { i32, i32 }
+@s0 = global [8 x i8] c"AAAAAAA\00", align 4
+@foo = global %struct.anon { i32 2, i32 3 }
+@bar = global %struct.anon zeroinitializer
+
+define i8* @A0() nounwind {
+entry:
+ ret i8* getelementptr ([8 x i8]* @s0, i32 0, i32 0)
+}
+
+define i32 @A1() nounwind {
+entry:
+ load i32* getelementptr (%struct.anon* @foo, i32 0, i32 0), align 8
+ load i32* getelementptr (%struct.anon* @foo, i32 0, i32 1), align 4
+ add i32 %1, %0
+ ret i32 %2
+}
+
diff --git a/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll b/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
new file mode 100644
index 0000000..59599b3
--- /dev/null
+++ b/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=mips -o %t
+; RUN: grep seh %t | count 1
+; RUN: grep seb %t | count 1
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define i8 @A(i8 %e.0, i8 signext %sum) signext nounwind {
+entry:
+ add i8 %sum, %e.0 ; <i8>:0 [#uses=1]
+ ret i8 %0
+}
+
+define i16 @B(i16 %e.0, i16 signext %sum) signext nounwind {
+entry:
+ add i16 %sum, %e.0 ; <i16>:0 [#uses=1]
+ ret i16 %0
+}
+
diff --git a/test/CodeGen/Mips/2008-07-22-Cstpool.ll b/test/CodeGen/Mips/2008-07-22-Cstpool.ll
new file mode 100644
index 0000000..21ff960
--- /dev/null
+++ b/test/CodeGen/Mips/2008-07-22-Cstpool.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=mips -o %t
+; RUN: grep {CPI\[01\]_\[01\]:} %t | count 2
+; RUN: grep {rodata.cst4,"aM",@progbits} %t | count 1
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define float @F(float %a) nounwind {
+entry:
+ fadd float %a, 0x4011333340000000 ; <float>:0 [#uses=1]
+ fadd float %0, 0x4010666660000000 ; <float>:1 [#uses=1]
+ ret float %1
+}
diff --git a/test/CodeGen/Mips/2008-07-23-fpcmp.ll b/test/CodeGen/Mips/2008-07-23-fpcmp.ll
new file mode 100644
index 0000000..80101fa
--- /dev/null
+++ b/test/CodeGen/Mips/2008-07-23-fpcmp.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=mips -o %t
+; RUN: grep {c\\..*\\.s} %t | count 3
+; RUN: grep {bc1\[tf\]} %t | count 3
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define float @A(float %a, float %b) nounwind {
+entry:
+ fcmp ogt float %a, 1.000000e+00 ; <i1>:0 [#uses=1]
+ br i1 %0, label %bb, label %bb2
+
+bb: ; preds = %entry
+ fadd float %a, 1.000000e+00 ; <float>:1 [#uses=1]
+ ret float %1
+
+bb2: ; preds = %entry
+ ret float %b
+}
+
+define float @B(float %a, float %b) nounwind {
+entry:
+ fcmp ogt float %a, 1.000000e+00 ; <i1>:0 [#uses=1]
+ %.0 = select i1 %0, float %a, float %b ; <float> [#uses=1]
+ ret float %.0
+}
+
+define i32 @C(i32 %a, i32 %b, float %j) nounwind {
+entry:
+ fcmp ogt float %j, 1.000000e+00 ; <i1>:0 [#uses=1]
+ %.0 = select i1 %0, i32 %a, i32 %b ; <i32> [#uses=1]
+ ret i32 %.0
+}
+
diff --git a/test/CodeGen/Mips/2008-07-29-icmp.ll b/test/CodeGen/Mips/2008-07-29-icmp.ll
new file mode 100644
index 0000000..042cad6
--- /dev/null
+++ b/test/CodeGen/Mips/2008-07-29-icmp.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=mips | grep {b\[ne\]\[eq\]} | count 1
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define float @A(float %a, float %b, i32 %j) nounwind {
+entry:
+ icmp sgt i32 %j, 1 ; <i1>:0 [#uses=1]
+ %.0 = select i1 %0, float %a, float %b ; <float> [#uses=1]
+ ret float %.0
+}
diff --git a/test/CodeGen/Mips/2008-07-31-fcopysign.ll b/test/CodeGen/Mips/2008-07-31-fcopysign.ll
new file mode 100644
index 0000000..77680bc
--- /dev/null
+++ b/test/CodeGen/Mips/2008-07-31-fcopysign.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=mips -o %t
+; RUN: grep abs.s %t | count 1
+; RUN: grep neg.s %t | count 1
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define float @A(float %i, float %j) nounwind {
+entry:
+ tail call float @copysignf( float %i, float %j ) nounwind readnone ; <float>:0 [#uses=1]
+ ret float %0
+}
+
+declare float @copysignf(float, float) nounwind readnone
diff --git a/test/CodeGen/Mips/2008-08-01-AsmInline.ll b/test/CodeGen/Mips/2008-08-01-AsmInline.ll
new file mode 100644
index 0000000..cd35cca
--- /dev/null
+++ b/test/CodeGen/Mips/2008-08-01-AsmInline.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=mips -o %t
+; RUN: grep mfhi %t | count 1
+; RUN: grep mflo %t | count 1
+; RUN: grep multu %t | count 1
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+ %struct.DWstruct = type { i32, i32 }
+
+define i32 @A0(i32 %u, i32 %v) nounwind {
+entry:
+ %asmtmp = tail call %struct.DWstruct asm "multu $2,$3", "={lo},={hi},d,d"( i32 %u, i32 %v ) nounwind
+ %asmresult = extractvalue %struct.DWstruct %asmtmp, 0
+ %asmresult1 = extractvalue %struct.DWstruct %asmtmp, 1 ; <i32> [#uses=1]
+ %res = add i32 %asmresult, %asmresult1
+ ret i32 %res
+}
diff --git a/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll b/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll
new file mode 100644
index 0000000..c41d521
--- /dev/null
+++ b/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll
@@ -0,0 +1,18 @@
+; Double return in abicall (default)
+; RUN: llc < %s -march=mips
+; PR2615
+
+define double @main(...) {
+entry:
+ %retval = alloca double ; <double*> [#uses=3]
+ store double 0.000000e+00, double* %retval
+ %r = alloca double ; <double*> [#uses=1]
+ load double* %r ; <double>:0 [#uses=1]
+ store double %0, double* %retval
+ br label %return
+
+return: ; preds = %entry
+ load double* %retval ; <double>:1 [#uses=1]
+ ret double %1
+}
+
diff --git a/test/CodeGen/Mips/2008-08-03-fabs64.ll b/test/CodeGen/Mips/2008-08-03-fabs64.ll
new file mode 100644
index 0000000..2f33e9b
--- /dev/null
+++ b/test/CodeGen/Mips/2008-08-03-fabs64.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=mips -o %t
+; RUN: grep {lui.*32767} %t | count 1
+; RUN: grep {ori.*65535} %t | count 1
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define double @A(double %c, double %d) nounwind readnone {
+entry:
+ tail call double @fabs( double %c ) nounwind readnone ; <double>:0 [#uses=1]
+ tail call double @fabs( double %d ) nounwind readnone ; <double>:0 [#uses=1]
+ fadd double %0, %1
+ ret double %2
+}
+
+declare double @fabs(double) nounwind readnone
diff --git a/test/CodeGen/Mips/2008-08-04-Bitconvert.ll b/test/CodeGen/Mips/2008-08-04-Bitconvert.ll
new file mode 100644
index 0000000..ca90b50
--- /dev/null
+++ b/test/CodeGen/Mips/2008-08-04-Bitconvert.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=mips -o %t
+; RUN: grep mtc1 %t | count 1
+; RUN: grep mfc1 %t | count 1
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define float @A(i32 %u) nounwind {
+entry:
+ bitcast i32 %u to float
+ ret float %0
+}
+
+define i32 @B(float %u) nounwind {
+entry:
+ bitcast float %u to i32
+ ret i32 %0
+}
diff --git a/test/CodeGen/Mips/2008-08-06-Alloca.ll b/test/CodeGen/Mips/2008-08-06-Alloca.ll
new file mode 100644
index 0000000..79e49a3
--- /dev/null
+++ b/test/CodeGen/Mips/2008-08-06-Alloca.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=mips | grep {subu.*sp} | count 2
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define i32 @twoalloca(i32 %size) nounwind {
+entry:
+ alloca i8, i32 %size ; <i8*>:0 [#uses=1]
+ alloca i8, i32 %size ; <i8*>:1 [#uses=1]
+ call i32 @foo( i8* %0 ) nounwind ; <i32>:2 [#uses=1]
+ call i32 @foo( i8* %1 ) nounwind ; <i32>:3 [#uses=1]
+ add i32 %3, %2 ; <i32>:4 [#uses=1]
+ ret i32 %4
+}
+
+declare i32 @foo(i8*)
diff --git a/test/CodeGen/Mips/2008-08-07-CC.ll b/test/CodeGen/Mips/2008-08-07-CC.ll
new file mode 100644
index 0000000..54d454c
--- /dev/null
+++ b/test/CodeGen/Mips/2008-08-07-CC.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=mips
+; Mips must ignore fastcc
+
+target datalayout =
+"e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define internal fastcc i32 @A(i32 %u) nounwind {
+entry:
+ ret i32 %u
+}
+
diff --git a/test/CodeGen/Mips/2008-08-07-FPRound.ll b/test/CodeGen/Mips/2008-08-07-FPRound.ll
new file mode 100644
index 0000000..f3bb965
--- /dev/null
+++ b/test/CodeGen/Mips/2008-08-07-FPRound.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=mips | grep __truncdfsf2 | count 1
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define float @round2float(double %a) nounwind {
+entry:
+ fptrunc double %a to float ; <float>:0 [#uses=1]
+ ret float %0
+}
diff --git a/test/CodeGen/Mips/2008-08-08-bswap.ll b/test/CodeGen/Mips/2008-08-08-bswap.ll
new file mode 100644
index 0000000..83289d9
--- /dev/null
+++ b/test/CodeGen/Mips/2008-08-08-bswap.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s | grep wsbw | count 1
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "psp"
+
+define i32 @__bswapsi2(i32 %u) nounwind {
+entry:
+ tail call i32 @llvm.bswap.i32( i32 %u ) ; <i32>:0 [#uses=1]
+ ret i32 %0
+}
+
+declare i32 @llvm.bswap.i32(i32) nounwind readnone
diff --git a/test/CodeGen/Mips/2008-08-08-ctlz.ll b/test/CodeGen/Mips/2008-08-08-ctlz.ll
new file mode 100644
index 0000000..1da1db2
--- /dev/null
+++ b/test/CodeGen/Mips/2008-08-08-ctlz.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=mips | grep clz | count 1
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "mipsallegrexel-psp-elf"
+
+define i32 @A0(i32 %u) nounwind {
+entry:
+ call i32 @llvm.ctlz.i32( i32 %u )
+ ret i32 %0
+}
+
+declare i32 @llvm.ctlz.i32(i32) nounwind readnone
diff --git a/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll b/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll
new file mode 100644
index 0000000..18f5b3d
--- /dev/null
+++ b/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=mips
+; PR2794
+
+define i32 @main(i8*) nounwind {
+entry:
+ br label %continue.outer
+
+continue.outer: ; preds = %case4, %entry
+ %p.0.ph.rec = phi i32 [ 0, %entry ], [ %indvar.next, %case4 ] ; <i32> [#uses=2]
+ %p.0.ph = getelementptr i8* %0, i32 %p.0.ph.rec ; <i8*> [#uses=1]
+ %1 = load i8* %p.0.ph ; <i8> [#uses=1]
+ switch i8 %1, label %infloop [
+ i8 0, label %return.split
+ i8 76, label %case4
+ i8 108, label %case4
+ i8 104, label %case4
+ i8 42, label %case4
+ ]
+
+case4: ; preds = %continue.outer, %continue.outer, %continue.outer, %continue.outer
+ %indvar.next = add i32 %p.0.ph.rec, 1 ; <i32> [#uses=1]
+ br label %continue.outer
+
+return.split: ; preds = %continue.outer
+ ret i32 0
+
+infloop: ; preds = %infloop, %continue.outer
+ br label %infloop
+}
diff --git a/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll b/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll
new file mode 100644
index 0000000..f518843
--- /dev/null
+++ b/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s
+; PR2667
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "psp"
+ %struct._Bigint = type { %struct._Bigint*, i32, i32, i32, i32, [1 x i32] }
+ %struct.__FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*, i8*, i32)*, i32 (i8*, i8*, i32)*, i32 (i8*, i32, i32)*, i32 (i8*)*, %struct.__sbuf, i8*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i32, %struct._reent*, i32 }
+ %struct.__sbuf = type { i8*, i32 }
+ %struct._atexit = type { %struct._atexit*, i32, [32 x void ()*], %struct._on_exit_args }
+ %struct._glue = type { %struct._glue*, i32, %struct.__FILE* }
+ %struct._on_exit_args = type { [32 x i8*], [32 x i8*], i32, i32 }
+ %struct._reent = type { i32, %struct.__FILE*, %struct.__FILE*, %struct.__FILE*, i32, [25 x i8], i32, i8*, i32, void (%struct._reent*)*, %struct._Bigint*, i32, %struct._Bigint*, %struct._Bigint**, i32, i8*, { { [30 x i8*], [30 x i32] } }, %struct._atexit*, %struct._atexit, void (i32)**, %struct._glue, [3 x %struct.__FILE] }
+@_impure_ptr = external global %struct._reent* ; <%struct._reent**> [#uses=1]
+
+define double @_erand48_r(%struct._reent* %r, i16* %xseed) nounwind {
+entry:
+ tail call void @__dorand48( %struct._reent* %r, i16* %xseed ) nounwind
+ load i16* %xseed, align 2 ; <i16>:0 [#uses=1]
+ uitofp i16 %0 to double ; <double>:1 [#uses=1]
+ tail call double @ldexp( double %1, i32 -48 ) nounwind ; <double>:2 [#uses=1]
+ getelementptr i16* %xseed, i32 1 ; <i16*>:3 [#uses=1]
+ load i16* %3, align 2 ; <i16>:4 [#uses=1]
+ uitofp i16 %4 to double ; <double>:5 [#uses=1]
+ tail call double @ldexp( double %5, i32 -32 ) nounwind ; <double>:6 [#uses=1]
+ fadd double %2, %6 ; <double>:7 [#uses=1]
+ getelementptr i16* %xseed, i32 2 ; <i16*>:8 [#uses=1]
+ load i16* %8, align 2 ; <i16>:9 [#uses=1]
+ uitofp i16 %9 to double ; <double>:10 [#uses=1]
+ tail call double @ldexp( double %10, i32 -16 ) nounwind ; <double>:11 [#uses=1]
+ fadd double %7, %11 ; <double>:12 [#uses=1]
+ ret double %12
+}
+
+declare void @__dorand48(%struct._reent*, i16*)
+
+declare double @ldexp(double, i32)
+
+define double @erand48(i16* %xseed) nounwind {
+entry:
+ load %struct._reent** @_impure_ptr, align 4 ; <%struct._reent*>:0 [#uses=1]
+ tail call void @__dorand48( %struct._reent* %0, i16* %xseed ) nounwind
+ load i16* %xseed, align 2 ; <i16>:1 [#uses=1]
+ uitofp i16 %1 to double ; <double>:2 [#uses=1]
+ tail call double @ldexp( double %2, i32 -48 ) nounwind ; <double>:3 [#uses=1]
+ getelementptr i16* %xseed, i32 1 ; <i16*>:4 [#uses=1]
+ load i16* %4, align 2 ; <i16>:5 [#uses=1]
+ uitofp i16 %5 to double ; <double>:6 [#uses=1]
+ tail call double @ldexp( double %6, i32 -32 ) nounwind ; <double>:7 [#uses=1]
+ fadd double %3, %7 ; <double>:8 [#uses=1]
+ getelementptr i16* %xseed, i32 2 ; <i16*>:9 [#uses=1]
+ load i16* %9, align 2 ; <i16>:10 [#uses=1]
+ uitofp i16 %10 to double ; <double>:11 [#uses=1]
+ tail call double @ldexp( double %11, i32 -16 ) nounwind ; <double>:12 [#uses=1]
+ fadd double %8, %12 ; <double>:13 [#uses=1]
+ ret double %13
+}
diff --git a/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll b/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll
new file mode 100644
index 0000000..636b318
--- /dev/null
+++ b/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-n32"
+target triple = "mips-unknown-linux"
+
+define float @h() nounwind readnone {
+entry:
+; CHECK: lw $2, %got($CPI1_0)($gp)
+; CHECK: lwc1 $f0, %lo($CPI1_0)($2)
+ ret float 0x400B333340000000
+}
diff --git a/test/CodeGen/Mips/dg.exp b/test/CodeGen/Mips/dg.exp
new file mode 100644
index 0000000..adb2cac
--- /dev/null
+++ b/test/CodeGen/Mips/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target Mips] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/Mips/private.ll b/test/CodeGen/Mips/private.ll
new file mode 100644
index 0000000..34b7547
--- /dev/null
+++ b/test/CodeGen/Mips/private.ll
@@ -0,0 +1,21 @@
+; Test to make sure that the 'private' is used correctly.
+;
+; RUN: llc < %s -march=mips > %t
+; RUN: grep \\\$foo: %t
+; RUN: grep call.*\\\$foo %t
+; RUN: grep \\\$baz: %t
+; RUN: grep lw.*\\\$baz %t
+
+declare void @foo()
+
+define private void @foo() {
+ ret void
+}
+
+@baz = private global i32 4
+
+define i32 @bar() {
+ call void @foo()
+ %1 = load i32* @baz, align 4
+ ret i32 %1
+}
diff --git a/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll b/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll
new file mode 100644
index 0000000..b508026
--- /dev/null
+++ b/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=pic16 | FileCheck %s
+
+target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-f32:32:32"
+target triple = "pic16-"
+@i = global i32 -10, align 1 ; <i32*> [#uses=1]
+@j = global i32 -20, align 1 ; <i32*> [#uses=1]
+@pc = global i8* inttoptr (i64 160 to i8*), align 1 ; <i8**> [#uses=3]
[email protected] = internal global i32 0 ; <i32*> [#uses=2]
+
+define void @main() nounwind {
+entry:
+ %tmp = load i32* @i ; <i32> [#uses=1]
+ %tmp1 = load i32* @j ; <i32> [#uses=1]
+ %add = add i32 %tmp, %tmp1 ; <i32> [#uses=1]
+ store i32 %add, i32* @main.auto.k
+ %tmp2 = load i32* @main.auto.k ; <i32> [#uses=1]
+ %add3 = add i32 %tmp2, 32 ; <i32> [#uses=1]
+ %conv = trunc i32 %add3 to i8 ; <i8> [#uses=1]
+ %tmp4 = load i8** @pc ; <i8*> [#uses=1]
+ store i8 %conv, i8* %tmp4
+ %tmp5 = load i8** @pc ; <i8*> [#uses=1]
+ %tmp6 = load i8* %tmp5 ; <i8> [#uses=1]
+ %conv7 = sext i8 %tmp6 to i16 ; <i16> [#uses=1]
+ %sub = sub i16 %conv7, 1 ; <i16> [#uses=1]
+ %conv8 = trunc i16 %sub to i8 ; <i8> [#uses=1]
+ %tmp9 = load i8** @pc ; <i8*> [#uses=1]
+ store i8 %conv8, i8* %tmp9
+ ret void
+}
+
+; CHECK: movf @i + 0, W
diff --git a/test/CodeGen/PIC16/2009-11-20-NewNode.ll b/test/CodeGen/PIC16/2009-11-20-NewNode.ll
new file mode 100644
index 0000000..d68f0f4
--- /dev/null
+++ b/test/CodeGen/PIC16/2009-11-20-NewNode.ll
@@ -0,0 +1,36 @@
+; RUN: llc -march=pic16 < %s
+; PR5558
+
+define i64 @_strtoll_r(i16 %base) nounwind {
+entry:
+ br i1 undef, label %if.then, label %if.end27
+
+if.then: ; preds = %do.end
+ br label %if.end27
+
+if.end27: ; preds = %if.then, %do.end
+ %cond66 = select i1 undef, i64 -9223372036854775808, i64 9223372036854775807 ; <i64> [#uses=3]
+ %conv69 = sext i16 %base to i64 ; <i64> [#uses=1]
+ %div = udiv i64 %cond66, %conv69 ; <i64> [#uses=1]
+ br label %for.cond
+
+for.cond: ; preds = %if.end116, %if.end27
+ br i1 undef, label %if.then152, label %if.then93
+
+if.then93: ; preds = %for.cond
+ br i1 undef, label %if.end116, label %if.then152
+
+if.end116: ; preds = %if.then93
+ %cmp123 = icmp ugt i64 undef, %div ; <i1> [#uses=1]
+ %or.cond = or i1 undef, %cmp123 ; <i1> [#uses=0]
+ br label %for.cond
+
+if.then152: ; preds = %if.then93, %for.cond
+ br i1 undef, label %if.end182, label %if.then172
+
+if.then172: ; preds = %if.then152
+ ret i64 %cond66
+
+if.end182: ; preds = %if.then152
+ ret i64 %cond66
+}
diff --git a/test/CodeGen/PIC16/C16-11.ll b/test/CodeGen/PIC16/C16-11.ll
new file mode 100644
index 0000000..e70092b
--- /dev/null
+++ b/test/CodeGen/PIC16/C16-11.ll
@@ -0,0 +1,37 @@
+;RUN: llc < %s -march=pic16
+
[email protected] = internal global i1 false ; <i1*> [#uses=2]
[email protected] = internal global i1 false ; <i1*> [#uses=2]
+
+define void @c612() nounwind {
+entry:
+ %tmp3.b = load i1* @c612.auto.a.b ; <i1> [#uses=1]
+ %tmp3 = zext i1 %tmp3.b to i16 ; <i16> [#uses=1]
+ %tmp4.b = load i1* @c612.auto.A.b ; <i1> [#uses=1]
+ %tmp4 = select i1 %tmp4.b, i16 2, i16 0 ; <i16> [#uses=1]
+ %cmp5 = icmp ne i16 %tmp3, %tmp4 ; <i1> [#uses=1]
+ %conv7 = zext i1 %cmp5 to i8 ; <i8> [#uses=1]
+ tail call void @expectWrap(i8 %conv7, i8 2)
+ ret void
+}
+
+define void @expectWrap(i8 %boolresult, i8 %errCode) nounwind {
+entry:
+ %tobool = icmp eq i8 %boolresult, 0 ; <i1> [#uses=1]
+ br i1 %tobool, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @exit(i16 1)
+ unreachable
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define i16 @main() nounwind {
+entry:
+ tail call void @c612()
+ ret i16 0
+}
+
+declare void @exit(i16) noreturn nounwind
diff --git a/test/CodeGen/PIC16/C16-15.ll b/test/CodeGen/PIC16/C16-15.ll
new file mode 100644
index 0000000..2e1dc0c
--- /dev/null
+++ b/test/CodeGen/PIC16/C16-15.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -march=pic16 | grep "extern @.lib.unordered.f32" | count 3
+
+@pc = global i8* inttoptr (i64 160 to i8*), align 1 ; <i8**> [#uses=2]
+@aa = common global i16 0, align 1 ; <i16*> [#uses=0]
[email protected] = internal global float 0.000000e+00, align 4 ; <float*> [#uses=1]
[email protected] = internal global float 0.000000e+00, align 4 ; <float*> [#uses=1]
+
+define float @dvalue(float %f) nounwind {
+entry:
+ ret float %f
+}
+
+define void @_assert(i16 %line, i16 %result) nounwind {
+entry:
+ %add = add i16 %line, %result ; <i16> [#uses=1]
+ %conv = trunc i16 %add to i8 ; <i8> [#uses=1]
+ %tmp2 = load i8** @pc ; <i8*> [#uses=1]
+ store i8 %conv, i8* %tmp2
+ ret void
+}
+
+define i16 @main() nounwind {
+entry:
+ %retval = alloca i16, align 1 ; <i16*> [#uses=2]
+ store i16 0, i16* %retval
+ call void @c6214()
+ %0 = load i16* %retval ; <i16> [#uses=1]
+ ret i16 %0
+}
+
+define internal void @c6214() nounwind {
+entry:
+ %call = call float @dvalue(float 0x3FF3C0CA40000000) ; <float> [#uses=3]
+ store float %call, float* @c6214.auto.d
+ store float %call, float* @c6214.auto.l
+ %cmp = fcmp ord float %call, 0.000000e+00 ; <i1> [#uses=1]
+ %conv = zext i1 %cmp to i16 ; <i16> [#uses=1]
+ call void @_assert(i16 10, i16 %conv)
+ %tmp3 = load i8** @pc ; <i8*> [#uses=2]
+ %tmp4 = load i8* %tmp3 ; <i8> [#uses=1]
+ %sub = add i8 %tmp4, -10 ; <i8> [#uses=1]
+ store i8 %sub, i8* %tmp3
+ ret void
+}
diff --git a/test/CodeGen/PIC16/C16-49.ll b/test/CodeGen/PIC16/C16-49.ll
new file mode 100644
index 0000000..e59800b
--- /dev/null
+++ b/test/CodeGen/PIC16/C16-49.ll
@@ -0,0 +1,15 @@
+;RUN: llvm-as < %s | llc -march=pic16
+
+@aa = global i16 55, align 1 ; <i16*> [#uses=1]
+@bb = global i16 44, align 1 ; <i16*> [#uses=1]
+@PORTD = external global i8 ; <i8*> [#uses=1]
+
+define void @foo() nounwind {
+entry:
+ %tmp = volatile load i16* @aa ; <i16> [#uses=1]
+ %tmp1 = volatile load i16* @bb ; <i16> [#uses=1]
+ %sub = sub i16 %tmp, %tmp1 ; <i16> [#uses=1]
+ %conv = trunc i16 %sub to i8 ; <i8> [#uses=1]
+ store i8 %conv, i8* @PORTD
+ ret void
+}
diff --git a/test/CodeGen/PIC16/check_inc_files.ll b/test/CodeGen/PIC16/check_inc_files.ll
new file mode 100644
index 0000000..436d416
--- /dev/null
+++ b/test/CodeGen/PIC16/check_inc_files.ll
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llc -march=pic16 | FileCheck %s
+
+;CHECK: #include p16f1xxx.inc
+;CHECK: #include stdmacros.inc
+
+define void @foo() nounwind {
+entry:
+ ret void
+}
diff --git a/test/CodeGen/PIC16/dg.exp b/test/CodeGen/PIC16/dg.exp
new file mode 100644
index 0000000..b08b985
--- /dev/null
+++ b/test/CodeGen/PIC16/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target PIC16] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/PIC16/global-in-user-section.ll b/test/CodeGen/PIC16/global-in-user-section.ll
new file mode 100644
index 0000000..74c9d9d
--- /dev/null
+++ b/test/CodeGen/PIC16/global-in-user-section.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=pic16 | FileCheck %s
+
+@G1 = common global i16 0, section "usersection", align 1
+; CHECK: usersection UDATA
+; CHECK: @G1 RES 2
diff --git a/test/CodeGen/PIC16/globals.ll b/test/CodeGen/PIC16/globals.ll
new file mode 100644
index 0000000..432c291
--- /dev/null
+++ b/test/CodeGen/PIC16/globals.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=pic16 | FileCheck %s
+
+@G1 = global i32 4712, section "Address=412"
+; CHECK: @G1.412..user_section.# IDATA 412
+; CHECK: @G1
+; CHECK: dl 4712
+
+@G2 = global i32 0, section "Address=412"
+; CHECK: @G2.412..user_section.# UDATA 412
+; CHECK: @G2 RES 4
+
+@G3 = addrspace(1) constant i32 4712, section "Address=412"
+; CHECK: @G3.412..user_section.# ROMDATA 412
+; CHECK: @G3
+; CHECK: rom_dl 4712
+
+
diff --git a/test/CodeGen/PIC16/result_direction.ll b/test/CodeGen/PIC16/result_direction.ll
new file mode 100644
index 0000000..8549e21
--- /dev/null
+++ b/test/CodeGen/PIC16/result_direction.ll
@@ -0,0 +1,13 @@
+; RUN: llvm-as < %s | llc -march=pic16 | FileCheck %s
+
+@a = common global i16 0, align 1 ; <i16*> [#uses=2]
+
+define void @foo() nounwind {
+entry:
+ %tmp = load i16* @a ; <i16> [#uses=1]
+ %add = add nsw i16 %tmp, 1 ; <i16> [#uses=1]
+ store i16 %add, i16* @a
+;CHECK: movlw 1
+;CHECK: addwf @a + 0, F
+ ret void
+}
diff --git a/test/CodeGen/PIC16/sext.ll b/test/CodeGen/PIC16/sext.ll
new file mode 100644
index 0000000..b49925f
--- /dev/null
+++ b/test/CodeGen/PIC16/sext.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=pic16
+
[email protected] = internal global i8 0 ; <i8*> [#uses=1]
+
+define i16 @main() nounwind {
+entry:
+ %tmp = load i8* @main.auto.c ; <i8> [#uses=1]
+ %conv = sext i8 %tmp to i16 ; <i16> [#uses=1]
+ ret i16 %conv
+}
diff --git a/test/CodeGen/PIC16/test_indf_name.ll b/test/CodeGen/PIC16/test_indf_name.ll
new file mode 100644
index 0000000..d52fc11
--- /dev/null
+++ b/test/CodeGen/PIC16/test_indf_name.ll
@@ -0,0 +1,12 @@
+; RUN: llvm-as < %s | llc -march=pic16 | FileCheck %s
+
+@pi = common global i16* null, align 1 ; <i16**> [#uses=1]
+
+define void @foo() nounwind {
+entry:
+ %tmp = load i16** @pi ; <i16*> [#uses=1]
+ store i16 1, i16* %tmp
+; CHECK: movwi {{[0-1]}}[INDF{{[0-1]}}]
+; CHECK: movwi {{[0-1]}}[INDF{{[0-1]}}]
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll b/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll
new file mode 100644
index 0000000..f95465c
--- /dev/null
+++ b/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=ppc32
+define void @test() {
+ %tr1 = lshr i32 1, 0 ; <i32> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll b/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll
new file mode 100644
index 0000000..c3bfa49
--- /dev/null
+++ b/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=ppc32
+
+define void @main() {
+ %tr4 = shl i64 1, 0 ; <i64> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll b/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll
new file mode 100644
index 0000000..dea654a
--- /dev/null
+++ b/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=ppc32
+
+define void @main() {
+ %shamt = add i8 0, 1 ; <i8> [#uses=1]
+ %shift.upgrd.1 = zext i8 %shamt to i64 ; <i64> [#uses=1]
+ %tr2 = ashr i64 1, %shift.upgrd.1 ; <i64> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll b/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll
new file mode 100644
index 0000000..fc190a48
--- /dev/null
+++ b/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll
@@ -0,0 +1,4 @@
+; RUN: llc < %s -march=ppc32 | not grep .comm.*X,0
+
+@X = linkonce global { } zeroinitializer ; <{ }*> [#uses=0]
+
diff --git a/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll b/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll
new file mode 100644
index 0000000..ad02ece
--- /dev/null
+++ b/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=ppc32
+
+define i32 @main() {
+ %setle = icmp sle i64 1, 0 ; <i1> [#uses=1]
+ %select = select i1 true, i1 %setle, i1 true ; <i1> [#uses=0]
+ ret i32 0
+}
+
diff --git a/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll b/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll
new file mode 100644
index 0000000..671bf80
--- /dev/null
+++ b/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=ppc32
+
+define i64 @test() {
+ ret i64 undef
+}
diff --git a/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll b/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll
new file mode 100644
index 0000000..95012c3
--- /dev/null
+++ b/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll
@@ -0,0 +1,13 @@
+; this should not crash the ppc backend
+
+; RUN: llc < %s -march=ppc32
+
+
+define i32 @test(i32 %j.0.0.i) {
+ %tmp.85.i = and i32 %j.0.0.i, 7 ; <i32> [#uses=1]
+ %tmp.161278.i = bitcast i32 %tmp.85.i to i32 ; <i32> [#uses=1]
+ %tmp.5.i77.i = lshr i32 %tmp.161278.i, 3 ; <i32> [#uses=1]
+ ret i32 %tmp.5.i77.i
+}
+
+
diff --git a/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll b/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll
new file mode 100644
index 0000000..5d1df46
--- /dev/null
+++ b/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll
@@ -0,0 +1,11 @@
+; This function should have exactly one call to fixdfdi, no more!
+
+; RUN: llc < %s -march=ppc32 -mattr=-64bit | \
+; RUN: grep {bl .*fixdfdi} | count 1
+
+define double @test2(double %tmp.7705) {
+ %mem_tmp.2.0.in = fptosi double %tmp.7705 to i64 ; <i64> [#uses=1]
+ %mem_tmp.2.0 = sitofp i64 %mem_tmp.2.0.in to double ; <double> [#uses=1]
+ ret double %mem_tmp.2.0
+}
+
diff --git a/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll b/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll
new file mode 100644
index 0000000..8a5d3b0
--- /dev/null
+++ b/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll
@@ -0,0 +1,11 @@
+; This was erroneously being turned into an rlwinm instruction.
+; The sign bit does matter in this case.
+
+; RUN: llc < %s -march=ppc32 | grep srawi
+
+define i32 @test(i32 %X) {
+ %Y = and i32 %X, -2 ; <i32> [#uses=1]
+ %Z = ashr i32 %Y, 11 ; <i32> [#uses=1]
+ ret i32 %Z
+}
+
diff --git a/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll b/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
new file mode 100644
index 0000000..047a12b
--- /dev/null
+++ b/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s
+
+target datalayout = "E-p:32:32"
+target triple = "powerpc-apple-darwin8.2.0"
+
+define void @bar(i32 %G, i32 %E, i32 %F, i32 %A, i32 %B, i32 %C, i32 %D, i8* %fmt, ...) {
+ %ap = alloca i8* ; <i8**> [#uses=2]
+ %va.upgrd.1 = bitcast i8** %ap to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_start( i8* %va.upgrd.1 )
+ %tmp.1 = load i8** %ap ; <i8*> [#uses=1]
+ %tmp.0 = call double @foo( i8* %tmp.1 ) ; <double> [#uses=0]
+ ret void
+}
+
+declare void @llvm.va_start(i8*)
+
+declare double @foo(i8*)
+
diff --git a/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll b/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll
new file mode 100644
index 0000000..97bb48e
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s | not grep {, f1}
+
+target datalayout = "E-p:32:32"
+target triple = "powerpc-apple-darwin8.2.0"
+
+; Dead argument should reserve an FP register.
+define double @bar(double %DEAD, double %X, double %Y) {
+ %tmp.2 = fadd double %X, %Y ; <double> [#uses=1]
+ ret double %tmp.2
+}
diff --git a/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll b/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
new file mode 100644
index 0000000..fbf2540
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s
+
+define void @iterative_hash_host_wide_int() {
+ %zero = alloca i32 ; <i32*> [#uses=2]
+ %b = alloca i32 ; <i32*> [#uses=1]
+ store i32 0, i32* %zero
+ %tmp = load i32* %zero ; <i32> [#uses=1]
+ %tmp5 = bitcast i32 %tmp to i32 ; <i32> [#uses=1]
+ %tmp6.u = add i32 %tmp5, 32 ; <i32> [#uses=1]
+ %tmp6 = bitcast i32 %tmp6.u to i32 ; <i32> [#uses=1]
+ %tmp7 = load i64* null ; <i64> [#uses=1]
+ %tmp6.upgrd.1 = trunc i32 %tmp6 to i8 ; <i8> [#uses=1]
+ %shift.upgrd.2 = zext i8 %tmp6.upgrd.1 to i64 ; <i64> [#uses=1]
+ %tmp8 = ashr i64 %tmp7, %shift.upgrd.2 ; <i64> [#uses=1]
+ %tmp8.upgrd.3 = trunc i64 %tmp8 to i32 ; <i32> [#uses=1]
+ store i32 %tmp8.upgrd.3, i32* %b
+ unreachable
+}
+
diff --git a/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll b/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll
new file mode 100644
index 0000000..172e348
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=ppc32
+
+
+define double @CalcSpeed(float %tmp127) {
+ %tmp145 = fpext float %tmp127 to double ; <double> [#uses=1]
+ %tmp150 = call double asm "frsqrte $0,$1", "=f,f"( double %tmp145 ) ; <double> [#uses=1]
+ ret double %tmp150
+}
+
diff --git a/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll b/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll
new file mode 100644
index 0000000..969772e
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
+; RUN: grep {vspltish v.*, 10}
+
+define void @test(<8 x i16>* %P) {
+ %tmp = load <8 x i16>* %P ; <<8 x i16>> [#uses=1]
+ %tmp1 = add <8 x i16> %tmp, < i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10 > ; <<8 x i16>> [#uses=1]
+ store <8 x i16> %tmp1, <8 x i16>* %P
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll b/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll
new file mode 100644
index 0000000..d225664
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll
@@ -0,0 +1,58 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5
+; END.
+
+define void @test(i8* %stack) {
+entry:
+ %tmp9 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ %tmp30 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp30, label %cond_next54, label %cond_true31
+cond_true860: ; preds = %bb855
+ %tmp879 = tail call <4 x float> @llvm.ppc.altivec.vmaddfp( <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x float> zeroinitializer ) ; <<4 x float>> [#uses=1]
+ %tmp880 = bitcast <4 x float> %tmp879 to <4 x i32> ; <<4 x i32>> [#uses=2]
+ %tmp883 = shufflevector <4 x i32> %tmp880, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x i32>> [#uses=1]
+ %tmp883.upgrd.1 = bitcast <4 x i32> %tmp883 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp885 = shufflevector <4 x i32> %tmp880, <4 x i32> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x i32>> [#uses=1]
+ %tmp885.upgrd.2 = bitcast <4 x i32> %tmp885 to <4 x float> ; <<4 x float>> [#uses=1]
+ br label %cond_next905
+cond_true31: ; preds = %entry
+ ret void
+cond_next54: ; preds = %entry
+ br i1 %tmp9, label %cond_false385, label %bb279
+bb279: ; preds = %cond_next54
+ ret void
+cond_false385: ; preds = %cond_next54
+ %tmp388 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp388, label %cond_next463, label %cond_true389
+cond_true389: ; preds = %cond_false385
+ ret void
+cond_next463: ; preds = %cond_false385
+ %tmp1208107 = icmp ugt i8* null, %stack ; <i1> [#uses=1]
+ br i1 %tmp1208107, label %cond_true1209.preheader, label %bb1212
+cond_true498: ; preds = %cond_true1209.preheader
+ ret void
+cond_true519: ; preds = %cond_true1209.preheader
+ %bothcond = or i1 false, false ; <i1> [#uses=1]
+ br i1 %bothcond, label %bb855, label %bb980
+cond_false548: ; preds = %cond_true1209.preheader
+ ret void
+bb855: ; preds = %cond_true519
+ %tmp859 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp859, label %cond_true860, label %cond_next905
+cond_next905: ; preds = %bb855, %cond_true860
+ %vfpw2.4 = phi <4 x float> [ %tmp885.upgrd.2, %cond_true860 ], [ undef, %bb855 ] ; <<4 x float>> [#uses=0]
+ %vfpw1.4 = phi <4 x float> [ %tmp883.upgrd.1, %cond_true860 ], [ undef, %bb855 ] ; <<4 x float>> [#uses=0]
+ %tmp930 = bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=0]
+ ret void
+bb980: ; preds = %cond_true519
+ ret void
+cond_true1209.preheader: ; preds = %cond_next463
+ %tmp496 = and i32 0, 12288 ; <i32> [#uses=1]
+ switch i32 %tmp496, label %cond_false548 [
+ i32 0, label %cond_true498
+ i32 4096, label %cond_true519
+ ]
+bb1212: ; preds = %cond_next463
+ ret void
+}
+
+declare <4 x float> @llvm.ppc.altivec.vmaddfp(<4 x float>, <4 x float>, <4 x float>)
diff --git a/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll b/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll
new file mode 100644
index 0000000..0205d10
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -march=ppc32
+; END.
+
+ %struct.attr_desc = type { i8*, %struct.attr_desc*, %struct.attr_value*, %struct.attr_value*, i32 }
+ %struct.attr_value = type { %struct.rtx_def*, %struct.attr_value*, %struct.insn_ent*, i32, i32 }
+ %struct.insn_def = type { %struct.insn_def*, %struct.rtx_def*, i32, i32, i32, i32, i32 }
+ %struct.insn_ent = type { %struct.insn_ent*, %struct.insn_def* }
+ %struct.rtx_def = type { i16, i8, i8, %struct.u }
+ %struct.u = type { [1 x i64] }
+
+define void @find_attr() {
+entry:
+ %tmp26 = icmp eq %struct.attr_desc* null, null ; <i1> [#uses=1]
+ br i1 %tmp26, label %bb30, label %cond_true27
+cond_true27: ; preds = %entry
+ ret void
+bb30: ; preds = %entry
+ %tmp67 = icmp eq %struct.attr_desc* null, null ; <i1> [#uses=1]
+ br i1 %tmp67, label %cond_next92, label %cond_true68
+cond_true68: ; preds = %bb30
+ ret void
+cond_next92: ; preds = %bb30
+ %tmp173 = getelementptr %struct.attr_desc* null, i32 0, i32 4 ; <i32*> [#uses=2]
+ %tmp174 = load i32* %tmp173 ; <i32> [#uses=1]
+ %tmp177 = and i32 %tmp174, -9 ; <i32> [#uses=1]
+ store i32 %tmp177, i32* %tmp173
+ %tmp180 = getelementptr %struct.attr_desc* null, i32 0, i32 4 ; <i32*> [#uses=1]
+ %tmp181 = load i32* %tmp180 ; <i32> [#uses=1]
+ %tmp185 = getelementptr %struct.attr_desc* null, i32 0, i32 4 ; <i32*> [#uses=2]
+ %tmp186 = load i32* %tmp185 ; <i32> [#uses=1]
+ %tmp183187 = shl i32 %tmp181, 1 ; <i32> [#uses=1]
+ %tmp188 = and i32 %tmp183187, 16 ; <i32> [#uses=1]
+ %tmp190 = and i32 %tmp186, -17 ; <i32> [#uses=1]
+ %tmp191 = or i32 %tmp190, %tmp188 ; <i32> [#uses=1]
+ store i32 %tmp191, i32* %tmp185
+ %tmp193 = getelementptr %struct.attr_desc* null, i32 0, i32 4 ; <i32*> [#uses=1]
+ %tmp194 = load i32* %tmp193 ; <i32> [#uses=1]
+ %tmp198 = getelementptr %struct.attr_desc* null, i32 0, i32 4 ; <i32*> [#uses=2]
+ %tmp199 = load i32* %tmp198 ; <i32> [#uses=1]
+ %tmp196200 = shl i32 %tmp194, 2 ; <i32> [#uses=1]
+ %tmp201 = and i32 %tmp196200, 64 ; <i32> [#uses=1]
+ %tmp203 = and i32 %tmp199, -65 ; <i32> [#uses=1]
+ %tmp204 = or i32 %tmp203, %tmp201 ; <i32> [#uses=1]
+ store i32 %tmp204, i32* %tmp198
+ %tmp206 = getelementptr %struct.attr_desc* null, i32 0, i32 4 ; <i32*> [#uses=1]
+ %tmp207 = load i32* %tmp206 ; <i32> [#uses=1]
+ %tmp211 = getelementptr %struct.attr_desc* null, i32 0, i32 4 ; <i32*> [#uses=2]
+ %tmp212 = load i32* %tmp211 ; <i32> [#uses=1]
+ %tmp209213 = shl i32 %tmp207, 1 ; <i32> [#uses=1]
+ %tmp214 = and i32 %tmp209213, 128 ; <i32> [#uses=1]
+ %tmp216 = and i32 %tmp212, -129 ; <i32> [#uses=1]
+ %tmp217 = or i32 %tmp216, %tmp214 ; <i32> [#uses=1]
+ store i32 %tmp217, i32* %tmp211
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
new file mode 100644
index 0000000..1b8b064
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mtriple=powerpc64-apple-darwin | grep extsw | count 2
+
+@lens = external global i8* ; <i8**> [#uses=1]
+@vals = external global i32* ; <i32**> [#uses=1]
+
+define i32 @test(i32 %i) {
+ %tmp = load i8** @lens ; <i8*> [#uses=1]
+ %tmp1 = getelementptr i8* %tmp, i32 %i ; <i8*> [#uses=1]
+ %tmp.upgrd.1 = load i8* %tmp1 ; <i8> [#uses=1]
+ %tmp2 = zext i8 %tmp.upgrd.1 to i32 ; <i32> [#uses=1]
+ %tmp3 = load i32** @vals ; <i32*> [#uses=1]
+ %tmp5 = sub i32 1, %tmp2 ; <i32> [#uses=1]
+ %tmp6 = getelementptr i32* %tmp3, i32 %tmp5 ; <i32*> [#uses=1]
+ %tmp7 = load i32* %tmp6 ; <i32> [#uses=1]
+ ret i32 %tmp7
+}
+
diff --git a/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll b/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll
new file mode 100644
index 0000000..65dd568
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=ppc32
+
+define void @img2buf(i32 %symbol_size_in_bytes, i16* %ui16) nounwind {
+ %tmp93 = load i16* null ; <i16> [#uses=1]
+ %tmp99 = call i16 @llvm.bswap.i16( i16 %tmp93 ) ; <i16> [#uses=1]
+ store i16 %tmp99, i16* %ui16
+ ret void
+}
+
+declare i16 @llvm.bswap.i16(i16)
+
diff --git a/test/CodeGen/PowerPC/2006-08-11-RetVector.ll b/test/CodeGen/PowerPC/2006-08-11-RetVector.ll
new file mode 100644
index 0000000..a947e5c
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-08-11-RetVector.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsldoi
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep vor
+
+define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) {
+ %tmp76 = shufflevector <4 x float> %fp0, <4 x float> %fp1, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp76
+}
+
diff --git a/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll b/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll
new file mode 100644
index 0000000..cb76b5c
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s
+
+ %struct..0anon = type { i32 }
+ %struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] }
+
+define fastcc void @immed_double_const(i32 %i0, i32 %i1) {
+entry:
+ %tmp1 = load i32* null ; <i32> [#uses=1]
+ switch i32 %tmp1, label %bb103 [
+ i32 1, label %bb
+ i32 3, label %bb
+ ]
+bb: ; preds = %entry, %entry
+ %tmp14 = icmp sgt i32 0, 31 ; <i1> [#uses=1]
+ br i1 %tmp14, label %cond_next77, label %cond_next17
+cond_next17: ; preds = %bb
+ ret void
+cond_next77: ; preds = %bb
+ %tmp79.not = icmp ne i32 %i1, 0 ; <i1> [#uses=1]
+ %tmp84 = icmp slt i32 %i0, 0 ; <i1> [#uses=2]
+ %bothcond1 = or i1 %tmp79.not, %tmp84 ; <i1> [#uses=1]
+ br i1 %bothcond1, label %bb88, label %bb99
+bb88: ; preds = %cond_next77
+ %bothcond2 = and i1 false, %tmp84 ; <i1> [#uses=0]
+ ret void
+bb99: ; preds = %cond_next77
+ ret void
+bb103: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2006-09-28-shift_64.ll b/test/CodeGen/PowerPC/2006-09-28-shift_64.ll
new file mode 100644
index 0000000..f748a8b
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-09-28-shift_64.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=ppc64
+
+target datalayout = "E-p:64:64"
+target triple = "powerpc64-apple-darwin8"
+
+define void @glArrayElement_CompExec() {
+entry:
+ %tmp3 = and i64 0, -8388609 ; <i64> [#uses=1]
+ br label %cond_true24
+cond_false: ; preds = %cond_true24
+ ret void
+cond_true24: ; preds = %cond_true24, %entry
+ %indvar.ph = phi i32 [ 0, %entry ], [ %indvar.next, %cond_true24 ] ; <i32> [#uses=1]
+ %indvar = add i32 0, %indvar.ph ; <i32> [#uses=2]
+ %code.0 = trunc i32 %indvar to i8 ; <i8> [#uses=1]
+ %tmp5 = add i8 %code.0, 16 ; <i8> [#uses=1]
+ %shift.upgrd.1 = zext i8 %tmp5 to i64 ; <i64> [#uses=1]
+ %tmp7 = lshr i64 %tmp3, %shift.upgrd.1 ; <i64> [#uses=1]
+ %tmp7.upgrd.2 = trunc i64 %tmp7 to i32 ; <i32> [#uses=1]
+ %tmp8 = and i32 %tmp7.upgrd.2, 1 ; <i32> [#uses=1]
+ %tmp8.upgrd.3 = icmp eq i32 %tmp8, 0 ; <i1> [#uses=1]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br i1 %tmp8.upgrd.3, label %cond_false, label %cond_true24
+}
+
diff --git a/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll b/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll
new file mode 100644
index 0000000..57ed250
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=ppc32 -combiner-alias-analysis | grep f5
+
+target datalayout = "E-p:32:32"
+target triple = "powerpc-apple-darwin8.2.0"
+ %struct.Point = type { double, double, double }
+
+define void @offset(%struct.Point* %pt, double %x, double %y, double %z) {
+entry:
+ %tmp = getelementptr %struct.Point* %pt, i32 0, i32 0 ; <double*> [#uses=2]
+ %tmp.upgrd.1 = load double* %tmp ; <double> [#uses=1]
+ %tmp2 = fadd double %tmp.upgrd.1, %x ; <double> [#uses=1]
+ store double %tmp2, double* %tmp
+ %tmp6 = getelementptr %struct.Point* %pt, i32 0, i32 1 ; <double*> [#uses=2]
+ %tmp7 = load double* %tmp6 ; <double> [#uses=1]
+ %tmp9 = fadd double %tmp7, %y ; <double> [#uses=1]
+ store double %tmp9, double* %tmp6
+ %tmp13 = getelementptr %struct.Point* %pt, i32 0, i32 2 ; <double*> [#uses=2]
+ %tmp14 = load double* %tmp13 ; <double> [#uses=1]
+ %tmp16 = fadd double %tmp14, %z ; <double> [#uses=1]
+ store double %tmp16, double* %tmp13
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll b/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll
new file mode 100644
index 0000000..002a064
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=ppc32 | not grep IMPLICIT_DEF
+
+define void @foo(i64 %X) {
+entry:
+ %tmp1 = and i64 %X, 3 ; <i64> [#uses=1]
+ %tmp = icmp sgt i64 %tmp1, 2 ; <i1> [#uses=1]
+ br i1 %tmp, label %UnifiedReturnBlock, label %cond_true
+cond_true: ; preds = %entry
+ %tmp.upgrd.1 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ ret void
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+declare i32 @bar(...)
+
diff --git a/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll b/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
new file mode 100644
index 0000000..3d462b4
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=ppc32 | grep xor
+
+target datalayout = "E-p:32:32"
+target triple = "powerpc-apple-darwin8.7.0"
+
+define void @foo(i32 %X) {
+entry:
+ %tmp1 = and i32 %X, 3 ; <i32> [#uses=1]
+ %tmp2 = xor i32 %tmp1, 1 ; <i32> [#uses=1]
+ %tmp = icmp eq i32 %tmp2, 0 ; <i1> [#uses=1]
+ br i1 %tmp, label %UnifiedReturnBlock, label %cond_true
+cond_true: ; preds = %entry
+ tail call i32 (...)* @bar( ) ; <i32>:0 [#uses=0]
+ ret void
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+declare i32 @bar(...)
+
diff --git a/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll b/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll
new file mode 100644
index 0000000..3284f0a
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=ppc64
+
+define i32* @foo(i32 %n) {
+ %A = alloca i32, i32 %n ; <i32*> [#uses=1]
+ ret i32* %A
+}
+
diff --git a/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll b/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll
new file mode 100644
index 0000000..49b3b9d
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=ppc32 | grep rlwimi
+
+define void @test(i16 %div.0.i.i.i.i, i32 %L_num.0.i.i.i.i, i32 %tmp1.i.i206.i.i, i16* %P) {
+ %X = shl i16 %div.0.i.i.i.i, 1 ; <i16> [#uses=1]
+ %tmp28.i.i.i.i = shl i32 %L_num.0.i.i.i.i, 1 ; <i32> [#uses=1]
+ %tmp31.i.i.i.i = icmp slt i32 %tmp28.i.i.i.i, %tmp1.i.i206.i.i ; <i1> [#uses=1]
+ %tmp31.i.i.i.i.upgrd.1 = zext i1 %tmp31.i.i.i.i to i16 ; <i16> [#uses=1]
+ %tmp371.i.i.i.i1 = or i16 %tmp31.i.i.i.i.upgrd.1, %X ; <i16> [#uses=1]
+ %div.0.be.i.i.i.i = xor i16 %tmp371.i.i.i.i1, 1 ; <i16> [#uses=1]
+ store i16 %div.0.be.i.i.i.i, i16* %P
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll b/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll
new file mode 100644
index 0000000..61b9967
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5
+
+define void @glgRunProcessor15() {
+ %tmp26355.i = shufflevector <4 x float> zeroinitializer, <4 x float> < float 0x379FFFE000000000, float 0x379FFFE000000000, float 0x379FFFE000000000, float 0x379FFFE000000000 >, <4 x i32> < i32 0, i32 1, i32 2, i32 7 >; <<4 x float>> [#uses=1]
+ %tmp3030030304.i = bitcast <4 x float> %tmp26355.i to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp30305.i = shufflevector <8 x i16> zeroinitializer, <8 x i16> %tmp3030030304.i, <8 x i32> < i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15 > ; <<8 x i16>> [#uses=1]
+ %tmp30305.i.upgrd.1 = bitcast <8 x i16> %tmp30305.i to <4 x i32> ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %tmp30305.i.upgrd.1, <4 x i32>* null
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll
new file mode 100644
index 0000000..ba86304
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=ppc64
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s
+
+define void @bitap() {
+entry:
+ %RMask.i = alloca [256 x i32], align 16 ; <[256 x i32]*> [#uses=1]
+ %buffer = alloca [147456 x i8], align 16 ; <[147456 x i8]*> [#uses=0]
+ br i1 false, label %bb19, label %bb.preheader
+bb.preheader: ; preds = %entry
+ ret void
+bb19: ; preds = %entry
+ br i1 false, label %bb12.i, label %cond_next39
+bb12.i: ; preds = %bb12.i, %bb19
+ %i.0.i = phi i32 [ %tmp11.i, %bb12.i ], [ 0, %bb19 ] ; <i32> [#uses=2]
+ %gep.upgrd.1 = zext i32 %i.0.i to i64 ; <i64> [#uses=1]
+ %tmp9.i = getelementptr [256 x i32]* %RMask.i, i32 0, i64 %gep.upgrd.1 ; <i32*> [#uses=1]
+ store i32 0, i32* %tmp9.i
+ %tmp11.i = add i32 %i.0.i, 1 ; <i32> [#uses=1]
+ br label %bb12.i
+cond_next39: ; preds = %bb19
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll b/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll
new file mode 100644
index 0000000..6d9a3fa
--- /dev/null
+++ b/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=ppc64
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s
+
[email protected] = external global i1 ; <i1*> [#uses=1]
+
+define fastcc void @qst() {
+entry:
+ br i1 true, label %cond_next71, label %cond_true
+cond_true: ; preds = %entry
+ ret void
+cond_next71: ; preds = %entry
+ %tmp73.b = load i1* @qsz.b ; <i1> [#uses=1]
+ %ii.4.ph = select i1 %tmp73.b, i64 4, i64 0 ; <i64> [#uses=1]
+ br label %bb139
+bb82: ; preds = %bb139
+ ret void
+bb139: ; preds = %bb139, %cond_next71
+ %exitcond89 = icmp eq i64 0, %ii.4.ph ; <i1> [#uses=1]
+ br i1 %exitcond89, label %bb82, label %bb139
+}
+
diff --git a/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll b/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll
new file mode 100644
index 0000000..805528c
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=ppc32 | grep extsb
+; RUN: llc < %s -march=ppc32 | grep extsh
+
+define i32 @p1(i8 %c, i16 %s) {
+entry:
+ %tmp = sext i8 %c to i32 ; <i32> [#uses=1]
+ %tmp1 = sext i16 %s to i32 ; <i32> [#uses=1]
+ %tmp2 = add i32 %tmp1, %tmp ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
diff --git a/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll b/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll
new file mode 100644
index 0000000..7b00ac6
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
+; RUN: grep cntlzw
+
+define i32 @foo() nounwind {
+entry:
+ %retval = alloca i32, align 4 ; <i32*> [#uses=2]
+ %temp = alloca i32, align 4 ; <i32*> [#uses=2]
+ %ctz_x = alloca i32, align 4 ; <i32*> [#uses=3]
+ %ctz_c = alloca i32, align 4 ; <i32*> [#uses=2]
+ "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 61440, i32* %ctz_x
+ %tmp = load i32* %ctz_x ; <i32> [#uses=1]
+ %tmp1 = sub i32 0, %tmp ; <i32> [#uses=1]
+ %tmp2 = load i32* %ctz_x ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp1, %tmp2 ; <i32> [#uses=1]
+ %tmp4 = call i32 asm "$(cntlz$|cntlzw$) $0,$1", "=r,r,~{dirflag},~{fpsr},~{flags}"( i32 %tmp3 ) ; <i32> [#uses=1]
+ store i32 %tmp4, i32* %ctz_c
+ %tmp5 = load i32* %ctz_c ; <i32> [#uses=1]
+ store i32 %tmp5, i32* %temp
+ %tmp6 = load i32* %temp ; <i32> [#uses=1]
+ store i32 %tmp6, i32* %retval
+ br label %return
+
+return: ; preds = %entry
+ %retval2 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval2
+}
diff --git a/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll b/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll
new file mode 100644
index 0000000..0c45472
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s -march=ppc64
+
+define i16 @test(i8* %d1, i16* %d2) {
+ %tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 ) ; <i16> [#uses=1]
+ ret i16 %tmp237
+}
diff --git a/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll b/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
new file mode 100644
index 0000000..fe5145d
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s -march=ppc64
+
+; Test two things: 1) that a frameidx can be rewritten in an inline asm
+; 2) that inline asms can handle reg+imm addr modes.
+
+ %struct.A = type { i32, i32 }
+
+
+define void @test1() {
+entry:
+ %Out = alloca %struct.A, align 4 ; <%struct.A*> [#uses=1]
+ %tmp2 = getelementptr %struct.A* %Out, i32 0, i32 1
+ %tmp5 = call i32 asm "lwbrx $0, $1", "=r,m"(i32* %tmp2 )
+ ret void
+}
+
+define void @test2() {
+entry:
+ %Out = alloca %struct.A, align 4 ; <%struct.A*> [#uses=1]
+ %tmp2 = getelementptr %struct.A* %Out, i32 0, i32 0 ; <i32*> [#uses=1]
+ %tmp5 = call i32 asm "lwbrx $0, $2, $1", "=r,r,bO,m"( i8* null, i32 0, i32* %tmp2 ) ; <i32> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll b/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll
new file mode 100644
index 0000000..621d43b
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll
@@ -0,0 +1,4 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | \
+; RUN: grep align.*3
+
+@X = global <{i32, i32}> <{ i32 1, i32 123 }>
diff --git a/test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll b/test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll
new file mode 100644
index 0000000..f48f365
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+
+target datalayout = "E-p:32:32"
+target triple = "powerpc-apple-darwin8.8.0"
+
+
+define void @blargh() {
+entry:
+ %tmp4 = call i32 asm "rlwimi $0,$2,$3,$4,$5", "=r,0,r,n,n,n"( i32 0, i32 0, i32 0, i32 24, i32 31 ) ; <i32> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll b/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll
new file mode 100644
index 0000000..0473857
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s | grep mflr | count 1
+
+target datalayout = "e-p:32:32"
+target triple = "powerpc-apple-darwin8"
+@str = internal constant [18 x i8] c"hello world!, %d\0A\00" ; <[18 x i8]*> [#uses=1]
+
+
+define i32 @main() {
+entry:
+ %tmp = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([18 x i8]* @str, i32 0, i32 0) ) ; <i32> [#uses=0]
+ ret i32 0
+}
+
+declare i32 @printf(i8*, ...)
diff --git a/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll b/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll
new file mode 100644
index 0000000..e93395a
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=ppc64 -mcpu=g5 | grep cntlzd
+
+define i32 @_ZNK4llvm5APInt17countLeadingZerosEv(i64 *%t) {
+ %tmp19 = load i64* %t
+ %tmp22 = tail call i64 @llvm.ctlz.i64( i64 %tmp19 ) ; <i64> [#uses=1]
+ %tmp23 = trunc i64 %tmp22 to i32
+ %tmp89 = add i32 %tmp23, -64 ; <i32> [#uses=1]
+ %tmp90 = add i32 %tmp89, 0 ; <i32> [#uses=1]
+ ret i32 %tmp90
+}
+
+declare i64 @llvm.ctlz.i64(i64)
diff --git a/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll b/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll
new file mode 100644
index 0000000..d43916d
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll
@@ -0,0 +1,1801 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5
+
+define void @test(<4 x float>*, { { i16, i16, i32 } }*) {
+xOperationInitMasks.exit:
+ %.sub7896 = getelementptr [4 x <4 x i32>]* null, i32 0, i32 0 ; <<4 x i32>*> [#uses=24]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 175, i32 3 ; <<4 x float>*>:2 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 174, i32 2 ; <<4 x float>*>:3 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 174, i32 3 ; <<4 x float>*>:4 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 1 ; <<4 x float>*>:5 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 2 ; <<4 x float>*>:6 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 3 ; <<4 x float>*>:7 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 1 ; <<4 x float>*>:8 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 2 ; <<4 x float>*>:9 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 3 ; <<4 x float>*>:10 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 171, i32 1 ; <<4 x float>*>:11 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 171, i32 2 ; <<4 x float>*>:12 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 171, i32 3 ; <<4 x float>*>:13 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 170, i32 1 ; <<4 x float>*>:14 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 170, i32 2 ; <<4 x float>*>:15 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 170, i32 3 ; <<4 x float>*>:16 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 169, i32 1 ; <<4 x float>*>:17 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 169, i32 2 ; <<4 x float>*>:18 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 169, i32 3 ; <<4 x float>*>:19 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 168, i32 1 ; <<4 x float>*>:20 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 168, i32 2 ; <<4 x float>*>:21 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 168, i32 3 ; <<4 x float>*>:22 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 167, i32 1 ; <<4 x float>*>:23 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 167, i32 2 ; <<4 x float>*>:24 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 167, i32 3 ; <<4 x float>*>:25 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 166, i32 1 ; <<4 x float>*>:26 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 166, i32 2 ; <<4 x float>*>:27 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 166, i32 3 ; <<4 x float>*>:28 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 165, i32 1 ; <<4 x float>*>:29 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 165, i32 2 ; <<4 x float>*>:30 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 165, i32 3 ; <<4 x float>*>:31 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 164, i32 1 ; <<4 x float>*>:32 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 164, i32 2 ; <<4 x float>*>:33 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 164, i32 3 ; <<4 x float>*>:34 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 163, i32 1 ; <<4 x float>*>:35 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 163, i32 2 ; <<4 x float>*>:36 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 163, i32 3 ; <<4 x float>*>:37 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 162, i32 1 ; <<4 x float>*>:38 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 162, i32 2 ; <<4 x float>*>:39 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 162, i32 3 ; <<4 x float>*>:40 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 161, i32 1 ; <<4 x float>*>:41 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 161, i32 2 ; <<4 x float>*>:42 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 161, i32 3 ; <<4 x float>*>:43 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 160, i32 1 ; <<4 x float>*>:44 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 160, i32 2 ; <<4 x float>*>:45 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 160, i32 3 ; <<4 x float>*>:46 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 159, i32 1 ; <<4 x float>*>:47 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 159, i32 2 ; <<4 x float>*>:48 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 159, i32 3 ; <<4 x float>*>:49 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 158, i32 1 ; <<4 x float>*>:50 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 158, i32 2 ; <<4 x float>*>:51 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 158, i32 3 ; <<4 x float>*>:52 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 157, i32 1 ; <<4 x float>*>:53 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 157, i32 2 ; <<4 x float>*>:54 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 157, i32 3 ; <<4 x float>*>:55 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 156, i32 1 ; <<4 x float>*>:56 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 156, i32 2 ; <<4 x float>*>:57 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 156, i32 3 ; <<4 x float>*>:58 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 155, i32 1 ; <<4 x float>*>:59 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 155, i32 2 ; <<4 x float>*>:60 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 155, i32 3 ; <<4 x float>*>:61 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 154, i32 1 ; <<4 x float>*>:62 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 154, i32 2 ; <<4 x float>*>:63 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 154, i32 3 ; <<4 x float>*>:64 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 153, i32 1 ; <<4 x float>*>:65 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 153, i32 2 ; <<4 x float>*>:66 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 153, i32 3 ; <<4 x float>*>:67 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 152, i32 1 ; <<4 x float>*>:68 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 152, i32 2 ; <<4 x float>*>:69 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 152, i32 3 ; <<4 x float>*>:70 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 151, i32 1 ; <<4 x float>*>:71 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 151, i32 2 ; <<4 x float>*>:72 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 151, i32 3 ; <<4 x float>*>:73 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 150, i32 1 ; <<4 x float>*>:74 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 150, i32 2 ; <<4 x float>*>:75 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 150, i32 3 ; <<4 x float>*>:76 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 149, i32 1 ; <<4 x float>*>:77 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 149, i32 2 ; <<4 x float>*>:78 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 149, i32 3 ; <<4 x float>*>:79 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 148, i32 1 ; <<4 x float>*>:80 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 148, i32 2 ; <<4 x float>*>:81 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 148, i32 3 ; <<4 x float>*>:82 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 147, i32 1 ; <<4 x float>*>:83 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 147, i32 2 ; <<4 x float>*>:84 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 147, i32 3 ; <<4 x float>*>:85 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 146, i32 1 ; <<4 x float>*>:86 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 146, i32 2 ; <<4 x float>*>:87 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 146, i32 3 ; <<4 x float>*>:88 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 145, i32 1 ; <<4 x float>*>:89 [#uses=0]
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+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 143, i32 1 ; <<4 x float>*>:95 [#uses=0]
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+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 132, i32 2 ; <<4 x float>*>:129 [#uses=0]
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+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 129, i32 1 ; <<4 x float>*>:137 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 129, i32 2 ; <<4 x float>*>:138 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 129, i32 3 ; <<4 x float>*>:139 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 128, i32 1 ; <<4 x float>*>:140 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 128, i32 2 ; <<4 x float>*>:141 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 128, i32 3 ; <<4 x float>*>:142 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 127, i32 1 ; <<4 x float>*>:143 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 127, i32 2 ; <<4 x float>*>:144 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 127, i32 3 ; <<4 x float>*>:145 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 126, i32 1 ; <<4 x float>*>:146 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 126, i32 2 ; <<4 x float>*>:147 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 126, i32 3 ; <<4 x float>*>:148 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 125, i32 1 ; <<4 x float>*>:149 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 125, i32 2 ; <<4 x float>*>:150 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 125, i32 3 ; <<4 x float>*>:151 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 124, i32 1 ; <<4 x float>*>:152 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 124, i32 2 ; <<4 x float>*>:153 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 124, i32 3 ; <<4 x float>*>:154 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 123, i32 1 ; <<4 x float>*>:155 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 123, i32 2 ; <<4 x float>*>:156 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 123, i32 3 ; <<4 x float>*>:157 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 122, i32 1 ; <<4 x float>*>:158 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 122, i32 2 ; <<4 x float>*>:159 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 122, i32 3 ; <<4 x float>*>:160 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 121, i32 1 ; <<4 x float>*>:161 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 121, i32 2 ; <<4 x float>*>:162 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 121, i32 3 ; <<4 x float>*>:163 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 120, i32 1 ; <<4 x float>*>:164 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 120, i32 2 ; <<4 x float>*>:165 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 120, i32 3 ; <<4 x float>*>:166 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 119, i32 1 ; <<4 x float>*>:167 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 119, i32 2 ; <<4 x float>*>:168 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 119, i32 3 ; <<4 x float>*>:169 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 118, i32 1 ; <<4 x float>*>:170 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 118, i32 2 ; <<4 x float>*>:171 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 118, i32 3 ; <<4 x float>*>:172 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 117, i32 1 ; <<4 x float>*>:173 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 117, i32 2 ; <<4 x float>*>:174 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 117, i32 3 ; <<4 x float>*>:175 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 116, i32 1 ; <<4 x float>*>:176 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 116, i32 2 ; <<4 x float>*>:177 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 116, i32 3 ; <<4 x float>*>:178 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 115, i32 1 ; <<4 x float>*>:179 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 115, i32 2 ; <<4 x float>*>:180 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 115, i32 3 ; <<4 x float>*>:181 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 114, i32 1 ; <<4 x float>*>:182 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 114, i32 2 ; <<4 x float>*>:183 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 114, i32 3 ; <<4 x float>*>:184 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 113, i32 1 ; <<4 x float>*>:185 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 113, i32 2 ; <<4 x float>*>:186 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 113, i32 3 ; <<4 x float>*>:187 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 112, i32 1 ; <<4 x float>*>:188 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 112, i32 2 ; <<4 x float>*>:189 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 112, i32 3 ; <<4 x float>*>:190 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 111, i32 1 ; <<4 x float>*>:191 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 111, i32 2 ; <<4 x float>*>:192 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 111, i32 3 ; <<4 x float>*>:193 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 110, i32 1 ; <<4 x float>*>:194 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 110, i32 2 ; <<4 x float>*>:195 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 110, i32 3 ; <<4 x float>*>:196 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 109, i32 1 ; <<4 x float>*>:197 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 109, i32 2 ; <<4 x float>*>:198 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 109, i32 3 ; <<4 x float>*>:199 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 108, i32 1 ; <<4 x float>*>:200 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 108, i32 2 ; <<4 x float>*>:201 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 108, i32 3 ; <<4 x float>*>:202 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 107, i32 1 ; <<4 x float>*>:203 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 107, i32 2 ; <<4 x float>*>:204 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 107, i32 3 ; <<4 x float>*>:205 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 106, i32 1 ; <<4 x float>*>:206 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 106, i32 2 ; <<4 x float>*>:207 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 106, i32 3 ; <<4 x float>*>:208 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 105, i32 1 ; <<4 x float>*>:209 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 105, i32 2 ; <<4 x float>*>:210 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 105, i32 3 ; <<4 x float>*>:211 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 104, i32 1 ; <<4 x float>*>:212 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 104, i32 2 ; <<4 x float>*>:213 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 104, i32 3 ; <<4 x float>*>:214 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 103, i32 1 ; <<4 x float>*>:215 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 103, i32 2 ; <<4 x float>*>:216 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 103, i32 3 ; <<4 x float>*>:217 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 102, i32 1 ; <<4 x float>*>:218 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 102, i32 2 ; <<4 x float>*>:219 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 102, i32 3 ; <<4 x float>*>:220 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 101, i32 1 ; <<4 x float>*>:221 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 101, i32 2 ; <<4 x float>*>:222 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 101, i32 3 ; <<4 x float>*>:223 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 100, i32 1 ; <<4 x float>*>:224 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 100, i32 2 ; <<4 x float>*>:225 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 100, i32 3 ; <<4 x float>*>:226 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 99, i32 1 ; <<4 x float>*>:227 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 99, i32 2 ; <<4 x float>*>:228 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 99, i32 3 ; <<4 x float>*>:229 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 98, i32 1 ; <<4 x float>*>:230 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 98, i32 2 ; <<4 x float>*>:231 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 98, i32 3 ; <<4 x float>*>:232 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 97, i32 1 ; <<4 x float>*>:233 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 97, i32 2 ; <<4 x float>*>:234 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 97, i32 3 ; <<4 x float>*>:235 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 96, i32 1 ; <<4 x float>*>:236 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 96, i32 2 ; <<4 x float>*>:237 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 96, i32 3 ; <<4 x float>*>:238 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 95, i32 1 ; <<4 x float>*>:239 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 95, i32 2 ; <<4 x float>*>:240 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 95, i32 3 ; <<4 x float>*>:241 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 94, i32 1 ; <<4 x float>*>:242 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 94, i32 2 ; <<4 x float>*>:243 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 94, i32 3 ; <<4 x float>*>:244 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 93, i32 1 ; <<4 x float>*>:245 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 93, i32 2 ; <<4 x float>*>:246 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 93, i32 3 ; <<4 x float>*>:247 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 92, i32 1 ; <<4 x float>*>:248 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 92, i32 2 ; <<4 x float>*>:249 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 92, i32 3 ; <<4 x float>*>:250 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 91, i32 1 ; <<4 x float>*>:251 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 91, i32 2 ; <<4 x float>*>:252 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 91, i32 3 ; <<4 x float>*>:253 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 90, i32 1 ; <<4 x float>*>:254 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 90, i32 2 ; <<4 x float>*>:255 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 90, i32 3 ; <<4 x float>*>:256 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 89, i32 1 ; <<4 x float>*>:257 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 89, i32 2 ; <<4 x float>*>:258 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 89, i32 3 ; <<4 x float>*>:259 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 88, i32 1 ; <<4 x float>*>:260 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 88, i32 2 ; <<4 x float>*>:261 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 88, i32 3 ; <<4 x float>*>:262 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 87, i32 1 ; <<4 x float>*>:263 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 87, i32 2 ; <<4 x float>*>:264 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 87, i32 3 ; <<4 x float>*>:265 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 86, i32 1 ; <<4 x float>*>:266 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 86, i32 2 ; <<4 x float>*>:267 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 86, i32 3 ; <<4 x float>*>:268 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 85, i32 1 ; <<4 x float>*>:269 [#uses=0]
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+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 63, i32 3 ; <<4 x float>*>:337 [#uses=0]
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+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 58, i32 3 ; <<4 x float>*>:352 [#uses=0]
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+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 56, i32 2 ; <<4 x float>*>:357 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 56, i32 3 ; <<4 x float>*>:358 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 55, i32 1 ; <<4 x float>*>:359 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 55, i32 2 ; <<4 x float>*>:360 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 55, i32 3 ; <<4 x float>*>:361 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 54, i32 1 ; <<4 x float>*>:362 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 54, i32 2 ; <<4 x float>*>:363 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 54, i32 3 ; <<4 x float>*>:364 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 53, i32 1 ; <<4 x float>*>:365 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 53, i32 2 ; <<4 x float>*>:366 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 53, i32 3 ; <<4 x float>*>:367 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 52, i32 1 ; <<4 x float>*>:368 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 52, i32 2 ; <<4 x float>*>:369 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 52, i32 3 ; <<4 x float>*>:370 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 51, i32 1 ; <<4 x float>*>:371 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 51, i32 2 ; <<4 x float>*>:372 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 51, i32 3 ; <<4 x float>*>:373 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 50, i32 1 ; <<4 x float>*>:374 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 50, i32 2 ; <<4 x float>*>:375 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 50, i32 3 ; <<4 x float>*>:376 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 49, i32 1 ; <<4 x float>*>:377 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 49, i32 2 ; <<4 x float>*>:378 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 49, i32 3 ; <<4 x float>*>:379 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 48, i32 1 ; <<4 x float>*>:380 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 48, i32 2 ; <<4 x float>*>:381 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 48, i32 3 ; <<4 x float>*>:382 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 47, i32 1 ; <<4 x float>*>:383 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 47, i32 2 ; <<4 x float>*>:384 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 47, i32 3 ; <<4 x float>*>:385 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 46, i32 1 ; <<4 x float>*>:386 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 46, i32 2 ; <<4 x float>*>:387 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 46, i32 3 ; <<4 x float>*>:388 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 45, i32 1 ; <<4 x float>*>:389 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 45, i32 2 ; <<4 x float>*>:390 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 45, i32 3 ; <<4 x float>*>:391 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 44, i32 1 ; <<4 x float>*>:392 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 44, i32 2 ; <<4 x float>*>:393 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 44, i32 3 ; <<4 x float>*>:394 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 43, i32 1 ; <<4 x float>*>:395 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 43, i32 2 ; <<4 x float>*>:396 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 43, i32 3 ; <<4 x float>*>:397 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 42, i32 1 ; <<4 x float>*>:398 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 42, i32 2 ; <<4 x float>*>:399 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 42, i32 3 ; <<4 x float>*>:400 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 41, i32 1 ; <<4 x float>*>:401 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 41, i32 2 ; <<4 x float>*>:402 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 41, i32 3 ; <<4 x float>*>:403 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 40, i32 1 ; <<4 x float>*>:404 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 40, i32 2 ; <<4 x float>*>:405 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 40, i32 3 ; <<4 x float>*>:406 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 39, i32 1 ; <<4 x float>*>:407 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 39, i32 2 ; <<4 x float>*>:408 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 39, i32 3 ; <<4 x float>*>:409 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 38, i32 1 ; <<4 x float>*>:410 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 38, i32 2 ; <<4 x float>*>:411 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 38, i32 3 ; <<4 x float>*>:412 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 37, i32 1 ; <<4 x float>*>:413 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 37, i32 2 ; <<4 x float>*>:414 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 37, i32 3 ; <<4 x float>*>:415 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 36, i32 1 ; <<4 x float>*>:416 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 36, i32 2 ; <<4 x float>*>:417 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 36, i32 3 ; <<4 x float>*>:418 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 35, i32 1 ; <<4 x float>*>:419 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 35, i32 2 ; <<4 x float>*>:420 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 35, i32 3 ; <<4 x float>*>:421 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 34, i32 1 ; <<4 x float>*>:422 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 34, i32 2 ; <<4 x float>*>:423 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 34, i32 3 ; <<4 x float>*>:424 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 33, i32 1 ; <<4 x float>*>:425 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 33, i32 2 ; <<4 x float>*>:426 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 33, i32 3 ; <<4 x float>*>:427 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 32, i32 1 ; <<4 x float>*>:428 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 32, i32 2 ; <<4 x float>*>:429 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 32, i32 3 ; <<4 x float>*>:430 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 31, i32 1 ; <<4 x float>*>:431 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 31, i32 2 ; <<4 x float>*>:432 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 31, i32 3 ; <<4 x float>*>:433 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 30, i32 1 ; <<4 x float>*>:434 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 30, i32 2 ; <<4 x float>*>:435 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 30, i32 3 ; <<4 x float>*>:436 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 29, i32 1 ; <<4 x float>*>:437 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 29, i32 2 ; <<4 x float>*>:438 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 29, i32 3 ; <<4 x float>*>:439 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 28, i32 1 ; <<4 x float>*>:440 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 28, i32 2 ; <<4 x float>*>:441 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 28, i32 3 ; <<4 x float>*>:442 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 27, i32 1 ; <<4 x float>*>:443 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 27, i32 2 ; <<4 x float>*>:444 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 27, i32 3 ; <<4 x float>*>:445 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 26, i32 1 ; <<4 x float>*>:446 [#uses=0]
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+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 26, i32 3 ; <<4 x float>*>:448 [#uses=0]
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+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 184, i32 3 ; <<4 x float>*>:505 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 185, i32 1 ; <<4 x float>*>:506 [#uses=0]
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+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 11, i32 3 ; <<4 x float>*>:520 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 12, i32 1 ; <<4 x float>*>:521 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 12, i32 2 ; <<4 x float>*>:522 [#uses=0]
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+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 13, i32 3 ; <<4 x float>*>:526 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 1 ; <<4 x float>*>:527 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2 ; <<4 x float>*>:528 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3 ; <<4 x float>*>:529 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1 ; <<4 x float>*>:530 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2 ; <<4 x float>*>:531 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3 ; <<4 x float>*>:532 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 1 ; <<4 x float>*>:533 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 2 ; <<4 x float>*>:534 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 3 ; <<4 x float>*>:535 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 6, i32 1 ; <<4 x float>*>:536 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 6, i32 2 ; <<4 x float>*>:537 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 6, i32 3 ; <<4 x float>*>:538 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 7, i32 1 ; <<4 x float>*>:539 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 7, i32 2 ; <<4 x float>*>:540 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 7, i32 3 ; <<4 x float>*>:541 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 1 ; <<4 x float>*>:542 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2 ; <<4 x float>*>:543 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3 ; <<4 x float>*>:544 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 187, i32 1 ; <<4 x float>*>:545 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 187, i32 2 ; <<4 x float>*>:546 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 187, i32 3 ; <<4 x float>*>:547 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 8, i32 1 ; <<4 x float>*>:548 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 8, i32 2 ; <<4 x float>*>:549 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 8, i32 3 ; <<4 x float>*>:550 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:551 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 1 ; <<4 x float>*>:552 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 2 ; <<4 x float>*>:553 [#uses=1]
+ load <4 x float>* %553 ; <<4 x float>>:554 [#uses=1]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 3 ; <<4 x float>*>:555 [#uses=0]
+ shufflevector <4 x float> %554, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:556 [#uses=1]
+ call <4 x i32> @llvm.ppc.altivec.vcmpgtfp( <4 x float> zeroinitializer, <4 x float> %556 ) ; <<4 x i32>>:557 [#uses=0]
+ bitcast <4 x i32> zeroinitializer to <4 x float> ; <<4 x float>>:558 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0 ; <<4 x float>*>:559 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 2 ; <<4 x float>*>:560 [#uses=1]
+ store <4 x float> zeroinitializer, <4 x float>* %560
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3 ; <<4 x float>*>:561 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1 ; <<4 x float>*>:562 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 2 ; <<4 x float>*>:563 [#uses=0]
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:564 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:565 [#uses=1]
+ store <4 x float> %565, <4 x float>* null
+ icmp eq i32 0, 0 ; <i1>:566 [#uses=1]
+ br i1 %566, label %.critedge, label %xPIF.exit
+
+.critedge: ; preds = %xOperationInitMasks.exit
+ getelementptr [4 x <4 x i32>]* null, i32 0, i32 3 ; <<4 x i32>*>:567 [#uses=0]
+ and <4 x i32> zeroinitializer, zeroinitializer ; <<4 x i32>>:568 [#uses=0]
+ or <4 x i32> zeroinitializer, zeroinitializer ; <<4 x i32>>:569 [#uses=0]
+ icmp eq i32 0, 0 ; <i1>:570 [#uses=1]
+ br i1 %570, label %.critedge7898, label %xPBRK.exit
+
+.critedge7898: ; preds = %.critedge
+ br label %xPIF.exit
+
+xPIF.exit: ; preds = %.critedge7898, %xOperationInitMasks.exit
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 1 ; <<4 x float>*>:571 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:572 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:573 [#uses=0]
+ icmp eq i32 0, 0 ; <i1>:574 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 1 ; <<4 x float>*>:575 [#uses=0]
+ load <4 x float>* %0 ; <<4 x float>>:576 [#uses=0]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:577 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 0 ; <<4 x float>*>:578 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 1 ; <<4 x float>*>:579 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 2 ; <<4 x float>*>:580 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 3 ; <<4 x float>*>:581 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3 ; <<4 x float>*>:582 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:583 [#uses=1]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1 ; <<4 x float>*>:584 [#uses=1]
+ load <4 x float>* %584 ; <<4 x float>>:585 [#uses=1]
+ load <4 x float>* null ; <<4 x float>>:586 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:587 [#uses=1]
+ load <4 x float>* %587 ; <<4 x float>>:588 [#uses=1]
+ shufflevector <4 x float> %583, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x float>>:589 [#uses=1]
+ shufflevector <4 x float> %585, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x float>>:590 [#uses=1]
+ shufflevector <4 x float> %588, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x float>>:591 [#uses=1]
+ fmul <4 x float> zeroinitializer, %589 ; <<4 x float>>:592 [#uses=0]
+ fmul <4 x float> zeroinitializer, %590 ; <<4 x float>>:593 [#uses=0]
+ fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:594 [#uses=1]
+ fmul <4 x float> zeroinitializer, %591 ; <<4 x float>>:595 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0 ; <<4 x float>*>:596 [#uses=2]
+ load <4 x float>* %596 ; <<4 x float>>:597 [#uses=0]
+ store <4 x float> zeroinitializer, <4 x float>* %596
+ load <4 x float>* null ; <<4 x float>>:598 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2 ; <<4 x float>*>:599 [#uses=0]
+ shufflevector <4 x float> %594, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:600 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3 ; <<4 x float>*>:601 [#uses=2]
+ load <4 x float>* %601 ; <<4 x float>>:602 [#uses=0]
+ store <4 x float> zeroinitializer, <4 x float>* %601
+ load <4 x float>* null ; <<4 x float>>:603 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:604 [#uses=1]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2 ; <<4 x float>*>:605 [#uses=1]
+ load <4 x float>* %605 ; <<4 x float>>:606 [#uses=1]
+ fsub <4 x float> zeroinitializer, %604 ; <<4 x float>>:607 [#uses=2]
+ fsub <4 x float> zeroinitializer, %606 ; <<4 x float>>:608 [#uses=2]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:609 [#uses=0]
+ br i1 false, label %617, label %610
+
+; <label>:610 ; preds = %xPIF.exit
+ load <4 x float>* null ; <<4 x float>>:611 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1 ; <<4 x float>*>:612 [#uses=2]
+ load <4 x float>* %612 ; <<4 x float>>:613 [#uses=1]
+ shufflevector <4 x float> %607, <4 x float> %613, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:614 [#uses=1]
+ store <4 x float> %614, <4 x float>* %612
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:615 [#uses=2]
+ load <4 x float>* %615 ; <<4 x float>>:616 [#uses=0]
+ store <4 x float> zeroinitializer, <4 x float>* %615
+ br label %xST.exit400
+
+; <label>:617 ; preds = %xPIF.exit
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:618 [#uses=0]
+ shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x i32>>:619 [#uses=1]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %619, <4 x i32> zeroinitializer ) ; <i32>:620 [#uses=1]
+ icmp eq i32 %620, 0 ; <i1>:621 [#uses=1]
+ br i1 %621, label %625, label %622
+
+; <label>:622 ; preds = %617
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1 ; <<4 x float>*>:623 [#uses=0]
+ shufflevector <4 x float> %607, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:624 [#uses=0]
+ br label %625
+
+; <label>:625 ; preds = %622, %617
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:626 [#uses=0]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:627 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:628 [#uses=1]
+ load <4 x float>* %628 ; <<4 x float>>:629 [#uses=0]
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:630 [#uses=0]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:631 [#uses=1]
+ icmp eq i32 %631, 0 ; <i1>:632 [#uses=1]
+ br i1 %632, label %xST.exit400, label %633
+
+; <label>:633 ; preds = %625
+ load <4 x float>* null ; <<4 x float>>:634 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %634, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:635 [#uses=1]
+ store <4 x float> %635, <4 x float>* null
+ br label %xST.exit400
+
+xST.exit400: ; preds = %633, %625, %610
+ %.17218 = phi <4 x float> [ zeroinitializer, %610 ], [ %608, %633 ], [ %608, %625 ] ; <<4 x float>> [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 0 ; <<4 x float>*>:636 [#uses=1]
+ load <4 x float>* %636 ; <<4 x float>>:637 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:638 [#uses=2]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:639 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:640 [#uses=2]
+ fmul <4 x float> %638, %638 ; <<4 x float>>:641 [#uses=1]
+ fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:642 [#uses=0]
+ fmul <4 x float> %640, %640 ; <<4 x float>>:643 [#uses=2]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x float>>:644 [#uses=0]
+ shufflevector <4 x float> %643, <4 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x float>>:645 [#uses=1]
+ fadd <4 x float> %645, %643 ; <<4 x float>>:646 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x float>>:647 [#uses=1]
+ shufflevector <4 x float> %641, <4 x float> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x float>>:648 [#uses=1]
+ fadd <4 x float> zeroinitializer, %647 ; <<4 x float>>:649 [#uses=2]
+ fadd <4 x float> zeroinitializer, %648 ; <<4 x float>>:650 [#uses=0]
+ fadd <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:651 [#uses=2]
+ call <4 x float> @llvm.ppc.altivec.vrsqrtefp( <4 x float> %649 ) ; <<4 x float>>:652 [#uses=1]
+ fmul <4 x float> %652, %649 ; <<4 x float>>:653 [#uses=1]
+ call <4 x float> @llvm.ppc.altivec.vrsqrtefp( <4 x float> %651 ) ; <<4 x float>>:654 [#uses=1]
+ fmul <4 x float> %654, %651 ; <<4 x float>>:655 [#uses=0]
+ icmp eq i32 0, 0 ; <i1>:656 [#uses=1]
+ br i1 %656, label %665, label %657
+
+; <label>:657 ; preds = %xST.exit400
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0 ; <<4 x float>*>:658 [#uses=0]
+ shufflevector <4 x float> %653, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:659 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1 ; <<4 x float>*>:660 [#uses=1]
+ load <4 x float>* %660 ; <<4 x float>>:661 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2 ; <<4 x float>*>:662 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3 ; <<4 x float>*>:663 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:664 [#uses=0]
+ br label %xST.exit402
+
+; <label>:665 ; preds = %xST.exit400
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:666 [#uses=0]
+ br i1 false, label %669, label %667
+
+; <label>:667 ; preds = %665
+ load <4 x float>* null ; <<4 x float>>:668 [#uses=0]
+ br label %669
+
+; <label>:669 ; preds = %667, %665
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:670 [#uses=0]
+ br label %xST.exit402
+
+xST.exit402: ; preds = %669, %657
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0 ; <<4 x float>*>:671 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:672 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2 ; <<4 x float>*>:673 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1 ; <<4 x float>*>:674 [#uses=1]
+ load <4 x float>* %674 ; <<4 x float>>:675 [#uses=1]
+ load <4 x float>* null ; <<4 x float>>:676 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:677 [#uses=1]
+ shufflevector <4 x float> %675, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:678 [#uses=1]
+ fmul <4 x float> zeroinitializer, %677 ; <<4 x float>>:679 [#uses=0]
+ fmul <4 x float> zeroinitializer, %678 ; <<4 x float>>:680 [#uses=0]
+ fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:681 [#uses=1]
+ icmp eq i32 0, 0 ; <i1>:682 [#uses=1]
+ br i1 %682, label %689, label %683
+
+; <label>:683 ; preds = %xST.exit402
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 1 ; <<4 x float>*>:684 [#uses=1]
+ load <4 x float>* %684 ; <<4 x float>>:685 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2 ; <<4 x float>*>:686 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3 ; <<4 x float>*>:687 [#uses=0]
+ shufflevector <4 x float> %681, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:688 [#uses=0]
+ br label %xST.exit405
+
+; <label>:689 ; preds = %xST.exit402
+ shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>>:690 [#uses=0]
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:691 [#uses=1]
+ shufflevector <4 x i32> %691, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>>:692 [#uses=1]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %692, <4 x i32> zeroinitializer ) ; <i32>:693 [#uses=1]
+ icmp eq i32 %693, 0 ; <i1>:694 [#uses=0]
+ br label %xST.exit405
+
+xST.exit405: ; preds = %689, %683
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3 ; <<4 x float>*>:695 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:696 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:697 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:698 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2 ; <<4 x float>*>:699 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:700 [#uses=1]
+ fadd <4 x float> zeroinitializer, %700 ; <<4 x float>>:701 [#uses=0]
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:702 [#uses=1]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %702, <4 x i32> zeroinitializer ) ; <i32>:703 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1 ; <<4 x float>*>:704 [#uses=2]
+ load <4 x float>* %704 ; <<4 x float>>:705 [#uses=0]
+ store <4 x float> zeroinitializer, <4 x float>* %704
+ load <4 x float>* null ; <<4 x float>>:706 [#uses=0]
+ store <4 x float> zeroinitializer, <4 x float>* null
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3 ; <<4 x float>*>:707 [#uses=2]
+ load <4 x float>* %707 ; <<4 x float>>:708 [#uses=0]
+ store <4 x float> zeroinitializer, <4 x float>* %707
+ load <4 x float>* null ; <<4 x float>>:709 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:710 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:711 [#uses=1]
+ shufflevector <4 x float> %711, <4 x float> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x float>>:712 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1 ; <<4 x float>*>:713 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2 ; <<4 x float>*>:714 [#uses=1]
+ load <4 x float>* %714 ; <<4 x float>>:715 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:716 [#uses=0]
+ fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:717 [#uses=1]
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:718 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 0 ; <<4 x float>*>:719 [#uses=1]
+ store <4 x float> zeroinitializer, <4 x float>* %719
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 1 ; <<4 x float>*>:720 [#uses=1]
+ shufflevector <4 x float> %717, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:721 [#uses=1]
+ store <4 x float> %721, <4 x float>* %720
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2 ; <<4 x float>*>:722 [#uses=1]
+ load <4 x float>* %722 ; <<4 x float>>:723 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %723, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:724 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3 ; <<4 x float>*>:725 [#uses=1]
+ store <4 x float> zeroinitializer, <4 x float>* %725
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2 ; <<4 x float>*>:726 [#uses=1]
+ load <4 x float>* %726 ; <<4 x float>>:727 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3 ; <<4 x float>*>:728 [#uses=1]
+ load <4 x float>* %728 ; <<4 x float>>:729 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0 ; <<4 x float>*>:730 [#uses=1]
+ load <4 x float>* %730 ; <<4 x float>>:731 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1 ; <<4 x float>*>:732 [#uses=1]
+ load <4 x float>* %732 ; <<4 x float>>:733 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3 ; <<4 x float>*>:734 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:735 [#uses=1]
+ fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:736 [#uses=1]
+ fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:737 [#uses=1]
+ fmul <4 x float> zeroinitializer, %735 ; <<4 x float>>:738 [#uses=1]
+ fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:739 [#uses=1]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:740 [#uses=1]
+ icmp eq i32 %740, 0 ; <i1>:741 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0 ; <<4 x float>*>:742 [#uses=2]
+ load <4 x float>* %742 ; <<4 x float>>:743 [#uses=1]
+ shufflevector <4 x float> %736, <4 x float> %743, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:744 [#uses=1]
+ store <4 x float> %744, <4 x float>* %742
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1 ; <<4 x float>*>:745 [#uses=1]
+ load <4 x float>* %745 ; <<4 x float>>:746 [#uses=1]
+ shufflevector <4 x float> %737, <4 x float> %746, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:747 [#uses=0]
+ shufflevector <4 x float> %738, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:748 [#uses=1]
+ store <4 x float> %748, <4 x float>* null
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3 ; <<4 x float>*>:749 [#uses=1]
+ load <4 x float>* %749 ; <<4 x float>>:750 [#uses=1]
+ shufflevector <4 x float> %739, <4 x float> %750, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:751 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0 ; <<4 x float>*>:752 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1 ; <<4 x float>*>:753 [#uses=1]
+ load <4 x float>* %753 ; <<4 x float>>:754 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2 ; <<4 x float>*>:755 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:756 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:757 [#uses=1]
+ shufflevector <4 x float> %756, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:758 [#uses=1]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2 ; <<4 x float>*>:759 [#uses=1]
+ load <4 x float>* %759 ; <<4 x float>>:760 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3 ; <<4 x float>*>:761 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:762 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:763 [#uses=1]
+ fadd <4 x float> %757, zeroinitializer ; <<4 x float>>:764 [#uses=0]
+ fadd <4 x float> %758, %763 ; <<4 x float>>:765 [#uses=0]
+ fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:766 [#uses=1]
+ br i1 false, label %773, label %767
+
+; <label>:767 ; preds = %xST.exit405
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1 ; <<4 x float>*>:768 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:769 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %769, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:770 [#uses=1]
+ store <4 x float> %770, <4 x float>* null
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:771 [#uses=1]
+ load <4 x float>* %771 ; <<4 x float>>:772 [#uses=0]
+ br label %xST.exit422
+
+; <label>:773 ; preds = %xST.exit405
+ br label %xST.exit422
+
+xST.exit422: ; preds = %773, %767
+ %.07267 = phi <4 x float> [ %766, %767 ], [ undef, %773 ] ; <<4 x float>> [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:774 [#uses=0]
+ fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:775 [#uses=0]
+ icmp eq i32 0, 0 ; <i1>:776 [#uses=1]
+ br i1 %776, label %780, label %777
+
+; <label>:777 ; preds = %xST.exit422
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:778 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:779 [#uses=0]
+ br label %xST.exit431
+
+; <label>:780 ; preds = %xST.exit422
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:781 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:782 [#uses=2]
+ load <4 x float>* %782 ; <<4 x float>>:783 [#uses=0]
+ store <4 x float> zeroinitializer, <4 x float>* %782
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:784 [#uses=1]
+ shufflevector <4 x i32> %784, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>>:785 [#uses=0]
+ icmp eq i32 0, 0 ; <i1>:786 [#uses=0]
+ br label %xST.exit431
+
+xST.exit431: ; preds = %780, %777
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:787 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:788 [#uses=0]
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:789 [#uses=2]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %789, <4 x i32> zeroinitializer ) ; <i32>:790 [#uses=1]
+ icmp eq i32 %790, 0 ; <i1>:791 [#uses=0]
+ shufflevector <4 x i32> %789, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>>:792 [#uses=1]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %792, <4 x i32> zeroinitializer ) ; <i32>:793 [#uses=1]
+ icmp eq i32 %793, 0 ; <i1>:794 [#uses=1]
+ br i1 %794, label %797, label %795
+
+; <label>:795 ; preds = %xST.exit431
+ load <4 x float>* null ; <<4 x float>>:796 [#uses=0]
+ store <4 x float> zeroinitializer, <4 x float>* null
+ br label %797
+
+; <label>:797 ; preds = %795, %xST.exit431
+ %.07332 = phi <4 x float> [ zeroinitializer, %795 ], [ undef, %xST.exit431 ] ; <<4 x float>> [#uses=0]
+ shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x i32>>:798 [#uses=0]
+ br i1 false, label %xST.exit434, label %799
+
+; <label>:799 ; preds = %797
+ load <4 x float>* null ; <<4 x float>>:800 [#uses=0]
+ store <4 x float> zeroinitializer, <4 x float>* null
+ br label %xST.exit434
+
+xST.exit434: ; preds = %799, %797
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:801 [#uses=1]
+ shufflevector <4 x i32> %801, <4 x i32> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x i32>>:802 [#uses=0]
+ shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>>:803 [#uses=0]
+ icmp eq i32 0, 0 ; <i1>:804 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 0 ; <<4 x float>*>:805 [#uses=1]
+ load <4 x float>* %805 ; <<4 x float>>:806 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1 ; <<4 x float>*>:807 [#uses=1]
+ load <4 x float>* %807 ; <<4 x float>>:808 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:809 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:810 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0 ; <<4 x float>*>:811 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2 ; <<4 x float>*>:812 [#uses=1]
+ load <4 x float>* %812 ; <<4 x float>>:813 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3 ; <<4 x float>*>:814 [#uses=1]
+ load <4 x float>* %814 ; <<4 x float>>:815 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:816 [#uses=0]
+ unreachable
+
+xPBRK.exit: ; preds = %.critedge
+ store <4 x i32> < i32 -1, i32 -1, i32 -1, i32 -1 >, <4 x i32>* %.sub7896
+ store <4 x i32> zeroinitializer, <4 x i32>* null
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 1 ; <<4 x float>*>:817 [#uses=1]
+ load <4 x float>* %817 ; <<4 x float>>:818 [#uses=1]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2 ; <<4 x float>*>:819 [#uses=1]
+ load <4 x float>* %819 ; <<4 x float>>:820 [#uses=1]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3 ; <<4 x float>*>:821 [#uses=1]
+ load <4 x float>* %821 ; <<4 x float>>:822 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:823 [#uses=1]
+ shufflevector <4 x float> %818, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:824 [#uses=1]
+ shufflevector <4 x float> %820, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:825 [#uses=1]
+ shufflevector <4 x float> %822, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:826 [#uses=1]
+ shufflevector <4 x float> %823, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:827 [#uses=0]
+ shufflevector <4 x float> %824, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:828 [#uses=1]
+ store <4 x float> %828, <4 x float>* null
+ load <4 x float>* null ; <<4 x float>>:829 [#uses=1]
+ shufflevector <4 x float> %825, <4 x float> %829, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:830 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3 ; <<4 x float>*>:831 [#uses=2]
+ load <4 x float>* %831 ; <<4 x float>>:832 [#uses=1]
+ shufflevector <4 x float> %826, <4 x float> %832, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:833 [#uses=1]
+ store <4 x float> %833, <4 x float>* %831
+ br label %xLS.exit449
+
+xLS.exit449: ; preds = %1215, %xPBRK.exit
+ %.27464 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.17463, %1215 ] ; <<4 x float>> [#uses=2]
+ %.27469 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.17468, %1215 ] ; <<4 x float>> [#uses=2]
+ %.27474 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=1]
+ %.17482 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0]
+ %.17486 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0]
+ %.17490 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07489, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17494 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0]
+ %.27504 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0]
+ %.17513 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0]
+ %.17517 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0]
+ %.17552 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07551, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17556 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07555, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17560 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0]
+ %.17583 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07582, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17591 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07590, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17599 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0]
+ %.17618 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07617, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17622 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07621, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17626 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0]
+ %.17653 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07652, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17657 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07656, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17661 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07660, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17665 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07664, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17723 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07722, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17727 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07726, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17731 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07730, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17735 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07734, %1215 ] ; <<4 x float>> [#uses=2]
+ %.17770 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07769, %1215 ] ; <<4 x float>> [#uses=2]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 0 ; <<4 x float>*>:834 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:835 [#uses=1]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2 ; <<4 x float>*>:836 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3 ; <<4 x float>*>:837 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:838 [#uses=0]
+ shufflevector <4 x float> %835, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:839 [#uses=1]
+ getelementptr <4 x float>* null, i32 878 ; <<4 x float>*>:840 [#uses=1]
+ load <4 x float>* %840 ; <<4 x float>>:841 [#uses=0]
+ call <4 x float> @llvm.ppc.altivec.vcfsx( <4 x i32> zeroinitializer, i32 0 ) ; <<4 x float>>:842 [#uses=1]
+ shufflevector <4 x float> %842, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:843 [#uses=2]
+ call <4 x i32> @llvm.ppc.altivec.vcmpgtfp( <4 x float> %843, <4 x float> %839 ) ; <<4 x i32>>:844 [#uses=1]
+ bitcast <4 x i32> %844 to <4 x float> ; <<4 x float>>:845 [#uses=1]
+ call <4 x i32> @llvm.ppc.altivec.vcmpgtfp( <4 x float> %843, <4 x float> zeroinitializer ) ; <<4 x i32>>:846 [#uses=0]
+ bitcast <4 x i32> zeroinitializer to <4 x float> ; <<4 x float>>:847 [#uses=1]
+ icmp eq i32 0, 0 ; <i1>:848 [#uses=1]
+ br i1 %848, label %854, label %849
+
+; <label>:849 ; preds = %xLS.exit449
+ shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:850 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1 ; <<4 x float>*>:851 [#uses=1]
+ store <4 x float> zeroinitializer, <4 x float>* %851
+ shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:852 [#uses=1]
+ store <4 x float> %852, <4 x float>* null
+ shufflevector <4 x float> %847, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:853 [#uses=0]
+ br label %xST.exit451
+
+; <label>:854 ; preds = %xLS.exit449
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:855 [#uses=0]
+ br i1 false, label %859, label %856
+
+; <label>:856 ; preds = %854
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0 ; <<4 x float>*>:857 [#uses=2]
+ load <4 x float>* %857 ; <<4 x float>>:858 [#uses=0]
+ store <4 x float> zeroinitializer, <4 x float>* %857
+ br label %859
+
+; <label>:859 ; preds = %856, %854
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:860 [#uses=0]
+ br i1 false, label %864, label %861
+
+; <label>:861 ; preds = %859
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1 ; <<4 x float>*>:862 [#uses=1]
+ shufflevector <4 x float> %845, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:863 [#uses=1]
+ store <4 x float> %863, <4 x float>* %862
+ br label %864
+
+; <label>:864 ; preds = %861, %859
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:865 [#uses=1]
+ shufflevector <4 x i32> %865, <4 x i32> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x i32>>:866 [#uses=0]
+ br i1 false, label %868, label %867
+
+; <label>:867 ; preds = %864
+ store <4 x float> zeroinitializer, <4 x float>* null
+ br label %868
+
+; <label>:868 ; preds = %867, %864
+ shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>>:869 [#uses=0]
+ br label %xST.exit451
+
+xST.exit451: ; preds = %868, %849
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0 ; <<4 x float>*>:870 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1 ; <<4 x float>*>:871 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:872 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:873 [#uses=1]
+ bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:874 [#uses=1]
+ xor <4 x i32> %874, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>>:875 [#uses=0]
+ bitcast <4 x float> %873 to <4 x i32> ; <<4 x i32>>:876 [#uses=1]
+ xor <4 x i32> %876, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>>:877 [#uses=0]
+ bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:878 [#uses=1]
+ xor <4 x i32> %878, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>>:879 [#uses=1]
+ bitcast <4 x i32> %879 to <4 x float> ; <<4 x float>>:880 [#uses=0]
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:881 [#uses=1]
+ icmp eq i32 0, 0 ; <i1>:882 [#uses=1]
+ br i1 %882, label %888, label %883
+
+; <label>:883 ; preds = %xST.exit451
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0 ; <<4 x float>*>:884 [#uses=1]
+ store <4 x float> zeroinitializer, <4 x float>* %884
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1 ; <<4 x float>*>:885 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:886 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3 ; <<4 x float>*>:887 [#uses=0]
+ br label %xST.exit453
+
+; <label>:888 ; preds = %xST.exit451
+ shufflevector <4 x i32> %881, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>>:889 [#uses=0]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:890 [#uses=0]
+ br i1 false, label %894, label %891
+
+; <label>:891 ; preds = %888
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1 ; <<4 x float>*>:892 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:893 [#uses=1]
+ store <4 x float> %893, <4 x float>* %892
+ br label %894
+
+; <label>:894 ; preds = %891, %888
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:895 [#uses=1]
+ icmp eq i32 %895, 0 ; <i1>:896 [#uses=1]
+ br i1 %896, label %898, label %897
+
+; <label>:897 ; preds = %894
+ br label %898
+
+; <label>:898 ; preds = %897, %894
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:899 [#uses=0]
+ br i1 false, label %xST.exit453, label %900
+
+; <label>:900 ; preds = %898
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3 ; <<4 x float>*>:901 [#uses=1]
+ load <4 x float>* %901 ; <<4 x float>>:902 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %902, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:903 [#uses=0]
+ br label %xST.exit453
+
+xST.exit453: ; preds = %900, %898, %883
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1 ; <<4 x float>*>:904 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:905 [#uses=1]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3 ; <<4 x float>*>:906 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:907 [#uses=1]
+ shufflevector <4 x float> %905, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:908 [#uses=1]
+ bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:909 [#uses=0]
+ bitcast <4 x float> %908 to <4 x i32> ; <<4 x i32>>:910 [#uses=0]
+ bitcast <4 x float> %907 to <4 x i32> ; <<4 x i32>>:911 [#uses=0]
+ bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:912 [#uses=0]
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:913 [#uses=0]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 2, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:914 [#uses=0]
+ br i1 false, label %915, label %xPIF.exit455
+
+; <label>:915 ; preds = %xST.exit453
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:916 [#uses=0]
+ getelementptr [4 x <4 x i32>]* null, i32 0, i32 3 ; <<4 x i32>*>:917 [#uses=1]
+ store <4 x i32> zeroinitializer, <4 x i32>* %917
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:918 [#uses=1]
+ and <4 x i32> %918, zeroinitializer ; <<4 x i32>>:919 [#uses=0]
+ br label %.critedge7899
+
+.critedge7899: ; preds = %.critedge7899, %915
+ or <4 x i32> zeroinitializer, zeroinitializer ; <<4 x i32>>:920 [#uses=1]
+ br i1 false, label %.critedge7899, label %xPBRK.exit456
+
+xPBRK.exit456: ; preds = %.critedge7899
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 2, <4 x i32> %920, <4 x i32> zeroinitializer ) ; <i32>:921 [#uses=0]
+ unreachable
+
+xPIF.exit455: ; preds = %xST.exit453
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 0 ; <<4 x float>*>:922 [#uses=1]
+ load <4 x float>* %922 ; <<4 x float>>:923 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 1 ; <<4 x float>*>:924 [#uses=1]
+ load <4 x float>* %924 ; <<4 x float>>:925 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2 ; <<4 x float>*>:926 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3 ; <<4 x float>*>:927 [#uses=0]
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:928 [#uses=0]
+ bitcast { { i16, i16, i32 } }* %1 to <4 x float>* ; <<4 x float>*>:929 [#uses=0]
+ bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:930 [#uses=0]
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:931 [#uses=0]
+ icmp eq i32 0, 0 ; <i1>:932 [#uses=1]
+ br i1 %932, label %934, label %933
+
+; <label>:933 ; preds = %xPIF.exit455
+ store <4 x float> zeroinitializer, <4 x float>* null
+ br label %934
+
+; <label>:934 ; preds = %933, %xPIF.exit455
+ shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x i32>>:935 [#uses=0]
+ icmp eq i32 0, 0 ; <i1>:936 [#uses=1]
+ br i1 %936, label %xST.exit459, label %937
+
+; <label>:937 ; preds = %934
+ br label %xST.exit459
+
+xST.exit459: ; preds = %937, %934
+ shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x i32>>:938 [#uses=1]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %938, <4 x i32> zeroinitializer ) ; <i32>:939 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 2 ; <<4 x float>*>:940 [#uses=1]
+ store <4 x float> zeroinitializer, <4 x float>* %940
+ load <4 x float>* null ; <<4 x float>>:941 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %941, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:942 [#uses=1]
+ store <4 x float> %942, <4 x float>* null
+ shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:943 [#uses=0]
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:944 [#uses=0]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:945 [#uses=0]
+ br i1 false, label %947, label %946
+
+; <label>:946 ; preds = %xST.exit459
+ br label %947
+
+; <label>:947 ; preds = %946, %xST.exit459
+ shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x i32>>:948 [#uses=0]
+ icmp eq i32 0, 0 ; <i1>:949 [#uses=1]
+ br i1 %949, label %952, label %950
+
+; <label>:950 ; preds = %947
+ shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>>:951 [#uses=1]
+ call void @llvm.ppc.altivec.stvewx( <4 x i32> %951, i8* null )
+ br label %952
+
+; <label>:952 ; preds = %950, %947
+ br i1 false, label %955, label %953
+
+; <label>:953 ; preds = %952
+ getelementptr [4 x <4 x i32>]* null, i32 0, i32 2 ; <<4 x i32>*>:954 [#uses=0]
+ br label %955
+
+; <label>:955 ; preds = %953, %952
+ shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>>:956 [#uses=0]
+ icmp eq i32 0, 0 ; <i1>:957 [#uses=1]
+ br i1 %957, label %xStoreDestAddressWithMask.exit461, label %958
+
+; <label>:958 ; preds = %955
+ shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>>:959 [#uses=1]
+ call void @llvm.ppc.altivec.stvewx( <4 x i32> %959, i8* null )
+ br label %xStoreDestAddressWithMask.exit461
+
+xStoreDestAddressWithMask.exit461: ; preds = %958, %955
+ load <4 x float>* %0 ; <<4 x float>>:960 [#uses=0]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:961 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 0 ; <<4 x float>*>:962 [#uses=0]
+ br i1 false, label %968, label %xST.exit463
+
+xST.exit463: ; preds = %xStoreDestAddressWithMask.exit461
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 1 ; <<4 x float>*>:963 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 2 ; <<4 x float>*>:964 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 3 ; <<4 x float>*>:965 [#uses=0]
+ load <4 x float>* %0 ; <<4 x float>>:966 [#uses=3]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:967 [#uses=0]
+ br i1 false, label %972, label %969
+
+; <label>:968 ; preds = %xStoreDestAddressWithMask.exit461
+ unreachable
+
+; <label>:969 ; preds = %xST.exit463
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 1 ; <<4 x float>*>:970 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 2 ; <<4 x float>*>:971 [#uses=1]
+ store <4 x float> %966, <4 x float>* %971
+ store <4 x float> %966, <4 x float>* null
+ br label %xST.exit465
+
+; <label>:972 ; preds = %xST.exit463
+ call <4 x i32> @llvm.ppc.altivec.vsel( <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <<4 x i32>>:973 [#uses=0]
+ store <4 x float> zeroinitializer, <4 x float>* null
+ store <4 x float> zeroinitializer, <4 x float>* null
+ load <4 x float>* null ; <<4 x float>>:974 [#uses=0]
+ bitcast <4 x float> %966 to <4 x i32> ; <<4 x i32>>:975 [#uses=1]
+ call <4 x i32> @llvm.ppc.altivec.vsel( <4 x i32> zeroinitializer, <4 x i32> %975, <4 x i32> zeroinitializer ) ; <<4 x i32>>:976 [#uses=1]
+ bitcast <4 x i32> %976 to <4 x float> ; <<4 x float>>:977 [#uses=1]
+ store <4 x float> %977, <4 x float>* null
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 3 ; <<4 x float>*>:978 [#uses=0]
+ bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:979 [#uses=1]
+ call <4 x i32> @llvm.ppc.altivec.vsel( <4 x i32> %979, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <<4 x i32>>:980 [#uses=1]
+ bitcast <4 x i32> %980 to <4 x float> ; <<4 x float>>:981 [#uses=0]
+ br label %xST.exit465
+
+xST.exit465: ; preds = %972, %969
+ load <4 x float>* %0 ; <<4 x float>>:982 [#uses=3]
+ icmp eq i32 0, 0 ; <i1>:983 [#uses=1]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0 ; <<4 x float>*>:984 [#uses=1]
+ br i1 %983, label %989, label %985
+
+; <label>:985 ; preds = %xST.exit465
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1 ; <<4 x float>*>:986 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2 ; <<4 x float>*>:987 [#uses=1]
+ store <4 x float> %982, <4 x float>* %987
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3 ; <<4 x float>*>:988 [#uses=0]
+ br label %xST.exit467
+
+; <label>:989 ; preds = %xST.exit465
+ bitcast <4 x float> %982 to <4 x i32> ; <<4 x i32>>:990 [#uses=0]
+ shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>>:991 [#uses=0]
+ store <4 x float> zeroinitializer, <4 x float>* %984
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1 ; <<4 x float>*>:992 [#uses=0]
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:993 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2 ; <<4 x float>*>:994 [#uses=0]
+ bitcast <4 x i32> zeroinitializer to <4 x float> ; <<4 x float>>:995 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3 ; <<4 x float>*>:996 [#uses=0]
+ bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:997 [#uses=1]
+ bitcast <4 x float> %982 to <4 x i32> ; <<4 x i32>>:998 [#uses=1]
+ shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>>:999 [#uses=1]
+ call <4 x i32> @llvm.ppc.altivec.vsel( <4 x i32> %997, <4 x i32> %998, <4 x i32> %999 ) ; <<4 x i32>>:1000 [#uses=1]
+ bitcast <4 x i32> %1000 to <4 x float> ; <<4 x float>>:1001 [#uses=0]
+ br label %xST.exit467
+
+xST.exit467: ; preds = %989, %985
+ load <4 x float>* %0 ; <<4 x float>>:1002 [#uses=5]
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:1003 [#uses=2]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %1003, <4 x i32> zeroinitializer ) ; <i32>:1004 [#uses=0]
+ br i1 false, label %1011, label %1005
+
+; <label>:1005 ; preds = %xST.exit467
+ load <4 x float>* null ; <<4 x float>>:1006 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1 ; <<4 x float>*>:1007 [#uses=1]
+ load <4 x float>* %1007 ; <<4 x float>>:1008 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:1009 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:1010 [#uses=0]
+ br label %xST.exit469
+
+; <label>:1011 ; preds = %xST.exit467
+ shufflevector <4 x i32> %1003, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>>:1012 [#uses=0]
+ icmp eq i32 0, 0 ; <i1>:1013 [#uses=1]
+ br i1 %1013, label %1015, label %1014
+
+; <label>:1014 ; preds = %1011
+ br label %1015
+
+; <label>:1015 ; preds = %1014, %1011
+ %.07472 = phi <4 x float> [ %1002, %1014 ], [ %.27474, %1011 ] ; <<4 x float>> [#uses=0]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:1016 [#uses=1]
+ icmp eq i32 %1016, 0 ; <i1>:1017 [#uses=1]
+ br i1 %1017, label %1021, label %1018
+
+; <label>:1018 ; preds = %1015
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1 ; <<4 x float>*>:1019 [#uses=0]
+ shufflevector <4 x float> %1002, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:1020 [#uses=0]
+ br label %1021
+
+; <label>:1021 ; preds = %1018, %1015
+ %.07467 = phi <4 x float> [ %1002, %1018 ], [ %.27469, %1015 ] ; <<4 x float>> [#uses=2]
+ icmp eq i32 0, 0 ; <i1>:1022 [#uses=1]
+ br i1 %1022, label %1025, label %1023
+
+; <label>:1023 ; preds = %1021
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:1024 [#uses=1]
+ store <4 x float> zeroinitializer, <4 x float>* %1024
+ br label %1025
+
+; <label>:1025 ; preds = %1023, %1021
+ %.07462 = phi <4 x float> [ %1002, %1023 ], [ %.27464, %1021 ] ; <<4 x float>> [#uses=2]
+ icmp eq i32 0, 0 ; <i1>:1026 [#uses=1]
+ br i1 %1026, label %xST.exit469, label %1027
+
+; <label>:1027 ; preds = %1025
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:1028 [#uses=0]
+ br label %xST.exit469
+
+xST.exit469: ; preds = %1027, %1025, %1005
+ %.17463 = phi <4 x float> [ %.27464, %1005 ], [ %.07462, %1027 ], [ %.07462, %1025 ] ; <<4 x float>> [#uses=1]
+ %.17468 = phi <4 x float> [ %.27469, %1005 ], [ %.07467, %1027 ], [ %.07467, %1025 ] ; <<4 x float>> [#uses=1]
+ %.07489 = phi <4 x float> [ %1002, %1005 ], [ %.17490, %1027 ], [ %.17490, %1025 ] ; <<4 x float>> [#uses=1]
+ load <4 x float>* null ; <<4 x float>>:1029 [#uses=0]
+ load <4 x float>* null ; <<4 x float>>:1030 [#uses=0]
+ fsub <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:1031 [#uses=1]
+ br i1 false, label %1037, label %1032
+
+; <label>:1032 ; preds = %xST.exit469
+ load <4 x float>* null ; <<4 x float>>:1033 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2 ; <<4 x float>*>:1034 [#uses=1]
+ load <4 x float>* %1034 ; <<4 x float>>:1035 [#uses=0]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3 ; <<4 x float>*>:1036 [#uses=0]
+ br label %xST.exit472
+
+; <label>:1037 ; preds = %xST.exit469
+ icmp eq i32 0, 0 ; <i1>:1038 [#uses=1]
+ br i1 %1038, label %1040, label %1039
+
+; <label>:1039 ; preds = %1037
+ br label %1040
+
+; <label>:1040 ; preds = %1039, %1037
+ %.07507 = phi <4 x float> [ zeroinitializer, %1039 ], [ zeroinitializer, %1037 ] ; <<4 x float>> [#uses=0]
+ icmp eq i32 0, 0 ; <i1>:1041 [#uses=1]
+ br i1 %1041, label %1045, label %1042
+
+; <label>:1042 ; preds = %1040
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1 ; <<4 x float>*>:1043 [#uses=1]
+ load <4 x float>* %1043 ; <<4 x float>>:1044 [#uses=0]
+ br label %1045
+
+; <label>:1045 ; preds = %1042, %1040
+ br i1 false, label %1048, label %1046
+
+; <label>:1046 ; preds = %1045
+ shufflevector <4 x float> %1031, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:1047 [#uses=0]
+ br label %1048
+
+; <label>:1048 ; preds = %1046, %1045
+ icmp eq i32 0, 0 ; <i1>:1049 [#uses=1]
+ br i1 %1049, label %xST.exit472, label %1050
+
+; <label>:1050 ; preds = %1048
+ br label %xST.exit472
+
+xST.exit472: ; preds = %1050, %1048, %1032
+ br i1 false, label %1052, label %1051
+
+; <label>:1051 ; preds = %xST.exit472
+ br label %xST.exit474
+
+; <label>:1052 ; preds = %xST.exit472
+ br i1 false, label %1054, label %1053
+
+; <label>:1053 ; preds = %1052
+ br label %1054
+
+; <label>:1054 ; preds = %1053, %1052
+ br i1 false, label %1056, label %1055
+
+; <label>:1055 ; preds = %1054
+ br label %1056
+
+; <label>:1056 ; preds = %1055, %1054
+ br i1 false, label %1058, label %1057
+
+; <label>:1057 ; preds = %1056
+ br label %1058
+
+; <label>:1058 ; preds = %1057, %1056
+ br i1 false, label %xST.exit474, label %1059
+
+; <label>:1059 ; preds = %1058
+ br label %xST.exit474
+
+xST.exit474: ; preds = %1059, %1058, %1051
+ load <4 x float>* null ; <<4 x float>>:1060 [#uses=1]
+ fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:1061 [#uses=1]
+ fmul <4 x float> %1060, zeroinitializer ; <<4 x float>>:1062 [#uses=2]
+ br i1 false, label %1065, label %1063
+
+; <label>:1063 ; preds = %xST.exit474
+ shufflevector <4 x float> %1062, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:1064 [#uses=1]
+ store <4 x float> %1064, <4 x float>* null
+ br label %xST.exit476
+
+; <label>:1065 ; preds = %xST.exit474
+ br i1 false, label %1067, label %1066
+
+; <label>:1066 ; preds = %1065
+ br label %1067
+
+; <label>:1067 ; preds = %1066, %1065
+ shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x i32>>:1068 [#uses=0]
+ br i1 false, label %1070, label %1069
+
+; <label>:1069 ; preds = %1067
+ br label %1070
+
+; <label>:1070 ; preds = %1069, %1067
+ br i1 false, label %1072, label %1071
+
+; <label>:1071 ; preds = %1070
+ br label %1072
+
+; <label>:1072 ; preds = %1071, %1070
+ br i1 false, label %xST.exit476, label %1073
+
+; <label>:1073 ; preds = %1072
+ br label %xST.exit476
+
+xST.exit476: ; preds = %1073, %1072, %1063
+ %.07551 = phi <4 x float> [ %1062, %1063 ], [ %.17552, %1073 ], [ %.17552, %1072 ] ; <<4 x float>> [#uses=1]
+ %.07555 = phi <4 x float> [ %1061, %1063 ], [ %.17556, %1073 ], [ %.17556, %1072 ] ; <<4 x float>> [#uses=1]
+ br i1 false, label %1075, label %1074
+
+; <label>:1074 ; preds = %xST.exit476
+ br label %xST.exit479
+
+; <label>:1075 ; preds = %xST.exit476
+ br i1 false, label %1077, label %1076
+
+; <label>:1076 ; preds = %1075
+ br label %1077
+
+; <label>:1077 ; preds = %1076, %1075
+ br i1 false, label %1079, label %1078
+
+; <label>:1078 ; preds = %1077
+ br label %1079
+
+; <label>:1079 ; preds = %1078, %1077
+ br i1 false, label %1081, label %1080
+
+; <label>:1080 ; preds = %1079
+ br label %1081
+
+; <label>:1081 ; preds = %1080, %1079
+ br i1 false, label %xST.exit479, label %1082
+
+; <label>:1082 ; preds = %1081
+ br label %xST.exit479
+
+xST.exit479: ; preds = %1082, %1081, %1074
+ br i1 false, label %1084, label %1083
+
+; <label>:1083 ; preds = %xST.exit479
+ br label %xST.exit482
+
+; <label>:1084 ; preds = %xST.exit479
+ br i1 false, label %1086, label %1085
+
+; <label>:1085 ; preds = %1084
+ br label %1086
+
+; <label>:1086 ; preds = %1085, %1084
+ br i1 false, label %1088, label %1087
+
+; <label>:1087 ; preds = %1086
+ br label %1088
+
+; <label>:1088 ; preds = %1087, %1086
+ br i1 false, label %1090, label %1089
+
+; <label>:1089 ; preds = %1088
+ br label %1090
+
+; <label>:1090 ; preds = %1089, %1088
+ br i1 false, label %xST.exit482, label %1091
+
+; <label>:1091 ; preds = %1090
+ br label %xST.exit482
+
+xST.exit482: ; preds = %1091, %1090, %1083
+ br i1 false, label %1093, label %1092
+
+; <label>:1092 ; preds = %xST.exit482
+ br label %xST.exit486
+
+; <label>:1093 ; preds = %xST.exit482
+ br i1 false, label %1095, label %1094
+
+; <label>:1094 ; preds = %1093
+ br label %1095
+
+; <label>:1095 ; preds = %1094, %1093
+ br i1 false, label %1097, label %1096
+
+; <label>:1096 ; preds = %1095
+ br label %1097
+
+; <label>:1097 ; preds = %1096, %1095
+ br i1 false, label %1099, label %1098
+
+; <label>:1098 ; preds = %1097
+ br label %1099
+
+; <label>:1099 ; preds = %1098, %1097
+ br i1 false, label %xST.exit486, label %1100
+
+; <label>:1100 ; preds = %1099
+ br label %xST.exit486
+
+xST.exit486: ; preds = %1100, %1099, %1092
+ br i1 false, label %1102, label %1101
+
+; <label>:1101 ; preds = %xST.exit486
+ br label %xST.exit489
+
+; <label>:1102 ; preds = %xST.exit486
+ br i1 false, label %1104, label %1103
+
+; <label>:1103 ; preds = %1102
+ br label %1104
+
+; <label>:1104 ; preds = %1103, %1102
+ br i1 false, label %1106, label %1105
+
+; <label>:1105 ; preds = %1104
+ br label %1106
+
+; <label>:1106 ; preds = %1105, %1104
+ br i1 false, label %1108, label %1107
+
+; <label>:1107 ; preds = %1106
+ br label %1108
+
+; <label>:1108 ; preds = %1107, %1106
+ br i1 false, label %xST.exit489, label %1109
+
+; <label>:1109 ; preds = %1108
+ br label %xST.exit489
+
+xST.exit489: ; preds = %1109, %1108, %1101
+ br i1 false, label %1111, label %1110
+
+; <label>:1110 ; preds = %xST.exit489
+ br label %xST.exit492
+
+; <label>:1111 ; preds = %xST.exit489
+ br i1 false, label %1113, label %1112
+
+; <label>:1112 ; preds = %1111
+ br label %1113
+
+; <label>:1113 ; preds = %1112, %1111
+ br i1 false, label %1115, label %1114
+
+; <label>:1114 ; preds = %1113
+ br label %1115
+
+; <label>:1115 ; preds = %1114, %1113
+ br i1 false, label %1117, label %1116
+
+; <label>:1116 ; preds = %1115
+ br label %1117
+
+; <label>:1117 ; preds = %1116, %1115
+ br i1 false, label %xST.exit492, label %1118
+
+; <label>:1118 ; preds = %1117
+ br label %xST.exit492
+
+xST.exit492: ; preds = %1118, %1117, %1110
+ load <4 x float>* null ; <<4 x float>>:1119 [#uses=1]
+ fmul <4 x float> %1119, zeroinitializer ; <<4 x float>>:1120 [#uses=1]
+ fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:1121 [#uses=1]
+ br i1 false, label %1123, label %1122
+
+; <label>:1122 ; preds = %xST.exit492
+ br label %xST.exit495
+
+; <label>:1123 ; preds = %xST.exit492
+ br i1 false, label %1125, label %1124
+
+; <label>:1124 ; preds = %1123
+ br label %1125
+
+; <label>:1125 ; preds = %1124, %1123
+ br i1 false, label %1127, label %1126
+
+; <label>:1126 ; preds = %1125
+ br label %1127
+
+; <label>:1127 ; preds = %1126, %1125
+ br i1 false, label %1129, label %1128
+
+; <label>:1128 ; preds = %1127
+ br label %1129
+
+; <label>:1129 ; preds = %1128, %1127
+ br i1 false, label %xST.exit495, label %1130
+
+; <label>:1130 ; preds = %1129
+ br label %xST.exit495
+
+xST.exit495: ; preds = %1130, %1129, %1122
+ %.07582 = phi <4 x float> [ %1121, %1122 ], [ %.17583, %1130 ], [ %.17583, %1129 ] ; <<4 x float>> [#uses=1]
+ %.07590 = phi <4 x float> [ %1120, %1122 ], [ %.17591, %1130 ], [ %.17591, %1129 ] ; <<4 x float>> [#uses=1]
+ load <4 x float>* null ; <<4 x float>>:1131 [#uses=1]
+ fadd <4 x float> %1131, zeroinitializer ; <<4 x float>>:1132 [#uses=1]
+ fadd <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:1133 [#uses=1]
+ br i1 false, label %1135, label %1134
+
+; <label>:1134 ; preds = %xST.exit495
+ br label %xST.exit498
+
+; <label>:1135 ; preds = %xST.exit495
+ br i1 false, label %1137, label %1136
+
+; <label>:1136 ; preds = %1135
+ br label %1137
+
+; <label>:1137 ; preds = %1136, %1135
+ br i1 false, label %1139, label %1138
+
+; <label>:1138 ; preds = %1137
+ br label %1139
+
+; <label>:1139 ; preds = %1138, %1137
+ br i1 false, label %1141, label %1140
+
+; <label>:1140 ; preds = %1139
+ br label %1141
+
+; <label>:1141 ; preds = %1140, %1139
+ br i1 false, label %xST.exit498, label %1142
+
+; <label>:1142 ; preds = %1141
+ br label %xST.exit498
+
+xST.exit498: ; preds = %1142, %1141, %1134
+ %.07617 = phi <4 x float> [ %1133, %1134 ], [ %.17618, %1142 ], [ %.17618, %1141 ] ; <<4 x float>> [#uses=1]
+ %.07621 = phi <4 x float> [ %1132, %1134 ], [ %.17622, %1142 ], [ %.17622, %1141 ] ; <<4 x float>> [#uses=1]
+ load <4 x float>* null ; <<4 x float>>:1143 [#uses=1]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:1144 [#uses=1]
+ load <4 x float>* %1144 ; <<4 x float>>:1145 [#uses=1]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:1146 [#uses=1]
+ load <4 x float>* %1146 ; <<4 x float>>:1147 [#uses=1]
+ shufflevector <4 x float> %1143, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:1148 [#uses=1]
+ shufflevector <4 x float> %1145, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:1149 [#uses=1]
+ shufflevector <4 x float> %1147, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:1150 [#uses=1]
+ fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:1151 [#uses=1]
+ fmul <4 x float> zeroinitializer, %1148 ; <<4 x float>>:1152 [#uses=1]
+ fmul <4 x float> zeroinitializer, %1149 ; <<4 x float>>:1153 [#uses=1]
+ fmul <4 x float> zeroinitializer, %1150 ; <<4 x float>>:1154 [#uses=1]
+ br i1 false, label %1156, label %1155
+
+; <label>:1155 ; preds = %xST.exit498
+ br label %xST.exit501
+
+; <label>:1156 ; preds = %xST.exit498
+ br i1 false, label %1158, label %1157
+
+; <label>:1157 ; preds = %1156
+ br label %1158
+
+; <label>:1158 ; preds = %1157, %1156
+ br i1 false, label %1160, label %1159
+
+; <label>:1159 ; preds = %1158
+ br label %1160
+
+; <label>:1160 ; preds = %1159, %1158
+ br i1 false, label %1162, label %1161
+
+; <label>:1161 ; preds = %1160
+ br label %1162
+
+; <label>:1162 ; preds = %1161, %1160
+ br i1 false, label %xST.exit501, label %1163
+
+; <label>:1163 ; preds = %1162
+ br label %xST.exit501
+
+xST.exit501: ; preds = %1163, %1162, %1155
+ %.07652 = phi <4 x float> [ %1154, %1155 ], [ %.17653, %1163 ], [ %.17653, %1162 ] ; <<4 x float>> [#uses=1]
+ %.07656 = phi <4 x float> [ %1153, %1155 ], [ %.17657, %1163 ], [ %.17657, %1162 ] ; <<4 x float>> [#uses=1]
+ %.07660 = phi <4 x float> [ %1152, %1155 ], [ %.17661, %1163 ], [ %.17661, %1162 ] ; <<4 x float>> [#uses=1]
+ %.07664 = phi <4 x float> [ %1151, %1155 ], [ %.17665, %1163 ], [ %.17665, %1162 ] ; <<4 x float>> [#uses=1]
+ load <4 x float>* null ; <<4 x float>>:1164 [#uses=1]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:1165 [#uses=1]
+ load <4 x float>* %1165 ; <<4 x float>>:1166 [#uses=1]
+ getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:1167 [#uses=1]
+ load <4 x float>* %1167 ; <<4 x float>>:1168 [#uses=1]
+ fadd <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:1169 [#uses=1]
+ fadd <4 x float> zeroinitializer, %1164 ; <<4 x float>>:1170 [#uses=1]
+ fadd <4 x float> zeroinitializer, %1166 ; <<4 x float>>:1171 [#uses=1]
+ fadd <4 x float> zeroinitializer, %1168 ; <<4 x float>>:1172 [#uses=1]
+ br i1 false, label %1174, label %1173
+
+; <label>:1173 ; preds = %xST.exit501
+ br label %xST.exit504
+
+; <label>:1174 ; preds = %xST.exit501
+ br i1 false, label %1176, label %1175
+
+; <label>:1175 ; preds = %1174
+ br label %1176
+
+; <label>:1176 ; preds = %1175, %1174
+ br i1 false, label %1178, label %1177
+
+; <label>:1177 ; preds = %1176
+ br label %1178
+
+; <label>:1178 ; preds = %1177, %1176
+ br i1 false, label %1180, label %1179
+
+; <label>:1179 ; preds = %1178
+ br label %1180
+
+; <label>:1180 ; preds = %1179, %1178
+ br i1 false, label %xST.exit504, label %1181
+
+; <label>:1181 ; preds = %1180
+ br label %xST.exit504
+
+xST.exit504: ; preds = %1181, %1180, %1173
+ %.07722 = phi <4 x float> [ %1172, %1173 ], [ %.17723, %1181 ], [ %.17723, %1180 ] ; <<4 x float>> [#uses=1]
+ %.07726 = phi <4 x float> [ %1171, %1173 ], [ %.17727, %1181 ], [ %.17727, %1180 ] ; <<4 x float>> [#uses=1]
+ %.07730 = phi <4 x float> [ %1170, %1173 ], [ %.17731, %1181 ], [ %.17731, %1180 ] ; <<4 x float>> [#uses=1]
+ %.07734 = phi <4 x float> [ %1169, %1173 ], [ %.17735, %1181 ], [ %.17735, %1180 ] ; <<4 x float>> [#uses=1]
+ fadd <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:1182 [#uses=1]
+ br i1 false, label %1184, label %1183
+
+; <label>:1183 ; preds = %xST.exit504
+ br label %xST.exit507
+
+; <label>:1184 ; preds = %xST.exit504
+ br i1 false, label %1186, label %1185
+
+; <label>:1185 ; preds = %1184
+ br label %1186
+
+; <label>:1186 ; preds = %1185, %1184
+ br i1 false, label %1188, label %1187
+
+; <label>:1187 ; preds = %1186
+ store <4 x float> zeroinitializer, <4 x float>* null
+ br label %1188
+
+; <label>:1188 ; preds = %1187, %1186
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:1189 [#uses=1]
+ shufflevector <4 x i32> %1189, <4 x i32> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x i32>>:1190 [#uses=1]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %1190, <4 x i32> zeroinitializer ) ; <i32>:1191 [#uses=1]
+ icmp eq i32 %1191, 0 ; <i1>:1192 [#uses=1]
+ br i1 %1192, label %1196, label %1193
+
+; <label>:1193 ; preds = %1188
+ load <4 x float>* null ; <<4 x float>>:1194 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %1194, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:1195 [#uses=1]
+ store <4 x float> %1195, <4 x float>* null
+ br label %1196
+
+; <label>:1196 ; preds = %1193, %1188
+ %.07742 = phi <4 x float> [ zeroinitializer, %1193 ], [ zeroinitializer, %1188 ] ; <<4 x float>> [#uses=0]
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:1197 [#uses=1]
+ shufflevector <4 x i32> %1197, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>>:1198 [#uses=1]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %1198, <4 x i32> zeroinitializer ) ; <i32>:1199 [#uses=1]
+ icmp eq i32 %1199, 0 ; <i1>:1200 [#uses=1]
+ br i1 %1200, label %xST.exit507, label %1201
+
+; <label>:1201 ; preds = %1196
+ store <4 x float> zeroinitializer, <4 x float>* null
+ br label %xST.exit507
+
+xST.exit507: ; preds = %1201, %1196, %1183
+ %.07769 = phi <4 x float> [ %1182, %1183 ], [ %.17770, %1201 ], [ %.17770, %1196 ] ; <<4 x float>> [#uses=1]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:1202 [#uses=1]
+ icmp eq i32 %1202, 0 ; <i1>:1203 [#uses=1]
+ br i1 %1203, label %1207, label %1204
+
+; <label>:1204 ; preds = %xST.exit507
+ load <4 x float>* null ; <<4 x float>>:1205 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %1205, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:1206 [#uses=1]
+ store <4 x float> %1206, <4 x float>* null
+ br label %1207
+
+; <label>:1207 ; preds = %1204, %xST.exit507
+ load <4 x i32>* %.sub7896 ; <<4 x i32>>:1208 [#uses=1]
+ shufflevector <4 x i32> %1208, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x i32>>:1209 [#uses=1]
+ call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %1209, <4 x i32> zeroinitializer ) ; <i32>:1210 [#uses=1]
+ icmp eq i32 %1210, 0 ; <i1>:1211 [#uses=1]
+ br i1 %1211, label %1215, label %1212
+
+; <label>:1212 ; preds = %1207
+ load <4 x float>* null ; <<4 x float>>:1213 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %1213, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:1214 [#uses=1]
+ store <4 x float> %1214, <4 x float>* null
+ br label %1215
+
+; <label>:1215 ; preds = %1212, %1207
+ store <4 x float> zeroinitializer, <4 x float>* null
+ br label %xLS.exit449
+}
+
+declare <4 x i32> @llvm.ppc.altivec.vsel(<4 x i32>, <4 x i32>, <4 x i32>)
+
+declare void @llvm.ppc.altivec.stvewx(<4 x i32>, i8*)
+
+declare <4 x float> @llvm.ppc.altivec.vrsqrtefp(<4 x float>)
+
+declare <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32>, i32)
+
+declare i32 @llvm.ppc.altivec.vcmpequw.p(i32, <4 x i32>, <4 x i32>)
+
+declare <4 x i32> @llvm.ppc.altivec.vcmpgtfp(<4 x float>, <4 x float>)
diff --git a/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll b/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll
new file mode 100644
index 0000000..86fd947
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep {foo r3, r4}
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep {bari r3, 47}
+
+; PR1351
+
+define i32 @test1(i32 %Y, i32 %X) nounwind {
+ %tmp1 = tail call i32 asm "foo${1:I} $0, $1", "=r,rI"( i32 %X )
+ ret i32 %tmp1
+}
+
+define i32 @test2(i32 %Y, i32 %X) nounwind {
+ %tmp1 = tail call i32 asm "bar${1:I} $0, $1", "=r,rI"( i32 47 )
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll b/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
new file mode 100644
index 0000000..d1d28ae
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s | grep {subfc r3,r5,r4}
+; RUN: llc < %s | grep {subfze r4,r2}
+; RUN: llc < %s -regalloc=local | grep {subfc r2,r5,r4}
+; RUN: llc < %s -regalloc=local | grep {subfze r3,r3}
+; The first argument of subfc must not be the same as any other register.
+
+; PR1357
+
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "powerpc-apple-darwin8.8.0"
+
+;long long test(int A, int B, int C) {
+; unsigned X, Y;
+; __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2"
+; : "=r" (X), "=&r" (Y)
+; : "r" (A), "rI" (B), "r" (C));
+; return ((long long)Y << 32) | X;
+;}
+
+define i64 @test(i32 %A, i32 %B, i32 %C) nounwind {
+entry:
+ %Y = alloca i32, align 4 ; <i32*> [#uses=2]
+ %tmp4 = call i32 asm "subf${3:I}c $1,$4,$3\0A\09subfze $0,$2", "=r,=*&r,r,rI,r"( i32* %Y, i32 %A, i32 %B, i32 %C ) ; <i32> [#uses=1]
+ %tmp5 = load i32* %Y ; <i32> [#uses=1]
+ %tmp56 = zext i32 %tmp5 to i64 ; <i64> [#uses=1]
+ %tmp7 = shl i64 %tmp56, 32 ; <i64> [#uses=1]
+ %tmp89 = zext i32 %tmp4 to i64 ; <i64> [#uses=1]
+ %tmp10 = or i64 %tmp7, %tmp89 ; <i64> [#uses=1]
+ ret i64 %tmp10
+}
diff --git a/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll b/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
new file mode 100644
index 0000000..1df5140
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s
+; PR1382
+
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "powerpc-apple-darwin8.8.0"
+@x = global [2 x i32] [ i32 1, i32 2 ] ; <[2 x i32]*> [#uses=1]
+
+define void @foo() {
+entry:
+ tail call void asm sideeffect "$0 $1", "s,i"( i8* bitcast (i32* getelementptr ([2 x i32]* @x, i32 0, i32 1) to i8*), i8* bitcast (i32* getelementptr ([2 x i32]* @x, i32 0, i32 1) to i8*) )
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll b/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll
new file mode 100644
index 0000000..e4e9314
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=ppc32
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "powerpc-apple-darwin8.8.0"
+ %struct..0anon = type { i32 }
+ %struct.A = type { %struct.anon }
+ %struct.anon = type <{ }>
+
+define void @bork(%struct.A* %In0P) {
+entry:
+ %tmp56 = bitcast %struct.A* %In0P to float* ; <float*> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %i.035.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
+ %tmp8 = getelementptr float* %tmp56, i32 %i.035.0 ; <float*> [#uses=2]
+ %tmp101112 = bitcast float* %tmp8 to i8* ; <i8*> [#uses=1]
+ %tmp1617 = bitcast float* %tmp8 to i32* ; <i32*> [#uses=1]
+ %tmp21 = tail call i32 asm "lwbrx $0, $2, $1", "=r,r,bO,*m"( i8* %tmp101112, i32 0, i32* %tmp1617 ) ; <i32> [#uses=0]
+ %indvar.next = add i32 %i.035.0, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, 4 ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
+
+return: ; preds = %bb
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll b/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll
new file mode 100644
index 0000000..42f2152
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll
@@ -0,0 +1,68 @@
+; RUN: llc < %s -march=ppc32 | grep bl.*baz | count 2
+; RUN: llc < %s -march=ppc32 | grep bl.*quux | count 2
+; RUN: llc < %s -march=ppc32 -enable-tail-merge | grep bl.*baz | count 1
+; RUN: llc < %s -march=ppc32 -enable-tail-merge=1 | grep bl.*quux | count 1
+; Check that tail merging is not the default on ppc, and that -enable-tail-merge works.
+
+; ModuleID = 'tail.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+
+define i32 @f(i32 %i, i32 %q) {
+entry:
+ %i_addr = alloca i32 ; <i32*> [#uses=2]
+ %q_addr = alloca i32 ; <i32*> [#uses=2]
+ %retval = alloca i32, align 4 ; <i32*> [#uses=1]
+ "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %i, i32* %i_addr
+ store i32 %q, i32* %q_addr
+ %tmp = load i32* %i_addr ; <i32> [#uses=1]
+ %tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
+ %tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1]
+ %toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1]
+ br i1 %toBool, label %cond_true, label %cond_false
+
+cond_true: ; preds = %entry
+ %tmp3 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
+ %tmp7 = load i32* %q_addr ; <i32> [#uses=1]
+ %tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1]
+ %tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1]
+ %toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1]
+ br i1 %toBool10, label %cond_true11, label %cond_false15
+
+cond_false: ; preds = %entry
+ %tmp5 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
+ %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
+ %tmp27 = load i32* %q_addr ; <i32> [#uses=1]
+ %tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1]
+ %tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1]
+ %toBool210 = icmp ne i8 %tmp289, 0 ; <i1> [#uses=1]
+ br i1 %toBool210, label %cond_true11, label %cond_false15
+
+cond_true11: ; preds = %cond_next
+ %tmp13 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
+ %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
+ br label %cond_next18
+
+cond_false15: ; preds = %cond_next
+ %tmp16 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
+ br label %cond_next18
+
+cond_next18: ; preds = %cond_false15, %cond_true11
+ %tmp19 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ br label %return
+
+return: ; preds = %cond_next18
+ %retval20 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval20
+}
+
+declare i32 @bar(...)
+
+declare i32 @baz(...)
+
+declare i32 @foo(...)
+
+declare i32 @quux(...)
diff --git a/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll b/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll
new file mode 100644
index 0000000..2938c70
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll
@@ -0,0 +1,14 @@
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "powerpc-apple-darwin8.8.0"
+
+; RUN: llc < %s -march=ppc32 | grep {rlwinm r3, r3, 23, 30, 30}
+; PR1473
+
+define i8 @foo(i16 zeroext %a) zeroext {
+ %tmp2 = lshr i16 %a, 10 ; <i16> [#uses=1]
+ %tmp23 = trunc i16 %tmp2 to i8 ; <i8> [#uses=1]
+ %tmp4 = shl i8 %tmp23, 1 ; <i8> [#uses=1]
+ %tmp5 = and i8 %tmp4, 2 ; <i8> [#uses=1]
+ ret i8 %tmp5
+}
+
diff --git a/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll b/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll
new file mode 100644
index 0000000..6de7a09
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll
@@ -0,0 +1,85 @@
+; RUN: llc < %s -march=ppc32 -mattr=+altivec
+
+ %struct.XATest = type { float, i16, i8, i8 }
+ %struct.XArrayRange = type { i8, i8, i8, i8 }
+ %struct.XBlendMode = type { i16, i16, i16, i16, %struct.GIC4, i16, i16, i8, i8, i8, i8 }
+ %struct.XClearC = type { double, %struct.GIC4, %struct.GIC4, float, i32 }
+ %struct.XClipPlane = type { i32, [6 x %struct.GIC4] }
+ %struct.XCBuffer = type { i16, i16, [8 x i16] }
+ %struct.XCMatrix = type { [16 x float]*, %struct.XICSS }
+ %struct.XConvolution = type { %struct.GIC4, %struct.XICSS, i16, i16, float*, i32, i32 }
+ %struct.XDepthTest = type { i16, i16, i8, i8, i8, i8, double, double }
+ %struct.XFixedFunctionProgram = type { %struct.PPSToken* }
+ %struct.XFogMode = type { %struct.GIC4, float, float, float, float, float, i16, i16, i16, i8, i8 }
+ %struct.XFramebufferAttachment = type { i32, i32, i32, i32 }
+ %struct.XHintMode = type { i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 }
+ %struct.XHistogram = type { %struct.XFramebufferAttachment*, i32, i16, i8, i8 }
+ %struct.XICSS = type { %struct.GTCoord2, %struct.GTCoord2, %struct.GTCoord2, %struct.GTCoord2 }
+ %struct.XISubset = type { %struct.XConvolution, %struct.XConvolution, %struct.XConvolution, %struct.XCMatrix, %struct.XMinmax, %struct.XHistogram, %struct.XICSS, %struct.XICSS, %struct.XICSS, %struct.XICSS, i32 }
+ %struct.XLight = type { %struct.GIC4, %struct.GIC4, %struct.GIC4, %struct.GIC4, %struct.XPointLineLimits, float, float, float, float, float, %struct.XPointLineLimits, float, float, float, float, float }
+ %struct.XLightModel = type { %struct.GIC4, [8 x %struct.XLight], [2 x %struct.XMaterial], i32, i16, i16, i16, i8, i8, i8, i8, i8, i8 }
+ %struct.XLightProduct = type { %struct.GIC4, %struct.GIC4, %struct.GIC4 }
+ %struct.XLineMode = type { float, i32, i16, i16, i8, i8, i8, i8 }
+ %struct.XLogicOp = type { i16, i8, i8 }
+ %struct.XMaskMode = type { i32, [3 x i32], i8, i8, i8, i8, i8, i8, i8, i8 }
+ %struct.XMaterial = type { %struct.GIC4, %struct.GIC4, %struct.GIC4, %struct.GIC4, float, float, float, float, [8 x %struct.XLightProduct], %struct.GIC4, [6 x i32], [2 x i32] }
+ %struct.XMinmax = type { %struct.XMinmaxTable*, i16, i8, i8 }
+ %struct.XMinmaxTable = type { %struct.GIC4, %struct.GIC4 }
+ %struct.XMipmaplevel = type { [4 x i32], [4 x i32], [4 x float], [4 x i32], i32, i32, float*, i8*, i16, i16, i16, i16, [2 x float] }
+ %struct.XMultisample = type { float, i8, i8, i8, i8, i8, i8, i8, i8 }
+ %struct.XPipelineProgramState = type { i8, i8, i8, i8, %struct.GIC4* }
+ %struct.XPMap = type { i32*, float*, float*, float*, float*, float*, float*, float*, float*, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.XPMode = type { float, float, %struct.XPStore, %struct.XPTransfer, %struct.XPMap, %struct.XISubset, i32, i32 }
+ %struct.XPPack = type { i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8 }
+ %struct.XPStore = type { %struct.XPPack, %struct.XPPack }
+ %struct.XPTransfer = type { float, float, float, float, float, float, float, float, float, float, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float }
+ %struct.XPointLineLimits = type { float, float, float }
+ %struct.XPointMode = type { float, float, float, float, %struct.XPointLineLimits, float, i8, i8, i8, i8, i16, i16, i32, i16, i16 }
+ %struct.XPGMode = type { [128 x i8], float, float, i16, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8 }
+ %struct.XRegisterCCs = type { i8, i8, i8, i8, i32, [2 x %struct.GIC4], [8 x %struct.XRegisterCCsPerStageState], %struct.XRegisterCCsFinalStageState }
+ %struct.XRegisterCCsFinalStageState = type { i8, i8, i8, i8, [7 x %struct.XRegisterCCsPerVariableState] }
+ %struct.XRegisterCCsPerPortionState = type { [4 x %struct.XRegisterCCsPerVariableState], i8, i8, i8, i8, i16, i16, i16, i16, i16, i16 }
+ %struct.XRegisterCCsPerStageState = type { [2 x %struct.XRegisterCCsPerPortionState], [2 x %struct.GIC4] }
+ %struct.XRegisterCCsPerVariableState = type { i16, i16, i16, i16 }
+ %struct.XScissorTest = type { %struct.XFramebufferAttachment, i8, i8, i8, i8 }
+ %struct.XState = type { i16, i16, i16, i16, i32, i32, [256 x %struct.GIC4], [128 x %struct.GIC4], %struct.XViewport, %struct.XXF, %struct.XLightModel, %struct.XATest, %struct.XBlendMode, %struct.XClearC, %struct.XCBuffer, %struct.XDepthTest, %struct.XArrayRange, %struct.XFogMode, %struct.XHintMode, %struct.XLineMode, %struct.XLogicOp, %struct.XMaskMode, %struct.XPMode, %struct.XPointMode, %struct.XPGMode, %struct.XScissorTest, i32, %struct.XStencilTest, [16 x %struct.XTMode], %struct.XArrayRange, [8 x %struct.XTCoordGen], %struct.XClipPlane, %struct.XMultisample, %struct.XRegisterCCs, %struct.XArrayRange, %struct.XArrayRange, [3 x %struct.XPipelineProgramState], %struct.XXFFeedback, i32*, %struct.XFixedFunctionProgram, [3 x i32] }
+ %struct.XStencilTest = type { [3 x { i32, i32, i16, i16, i16, i16 }], i32, [4 x i8] }
+ %struct.XTCoordGen = type { { i16, i16, %struct.GIC4, %struct.GIC4 }, { i16, i16, %struct.GIC4, %struct.GIC4 }, { i16, i16, %struct.GIC4, %struct.GIC4 }, { i16, i16, %struct.GIC4, %struct.GIC4 }, i8, i8, i8, i8 }
+ %struct.XTGeomState = type { i16, i16, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, [6 x i16], [6 x i16] }
+ %struct.XTLevel = type { i32, i32, i16, i16, i16, i8, i8, i16, i16, i16, i16, i8* }
+ %struct.XTMode = type { %struct.GIC4, i32, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, float, float, float, i16, i16, i16, i16, i16, i16, [4 x i16], i8, i8, i8, i8, [3 x float], [4 x float], float, float }
+ %struct.XTParamState = type { i16, i16, i16, i16, i16, i16, %struct.GIC4, float, float, float, float, i16, i16, i16, i16, float, i16, i8, i8, i32, i8* }
+ %struct.XTRec = type { %struct.XTState*, float, float, float, float, %struct.XMipmaplevel*, %struct.XMipmaplevel*, i32, i32, i32, i32, i32, i32, i32, [2 x %struct.PPSToken] }
+ %struct.XTState = type { i16, i8, i8, i16, i16, float, i32, %struct.GISWRSurface*, %struct.XTParamState, %struct.XTGeomState, %struct.XTLevel, [6 x [15 x %struct.XTLevel]] }
+ %struct.XXF = type { [24 x [16 x float]], [24 x [16 x float]], [16 x float], float, float, float, float, float, i8, i8, i8, i8, i32, i32, i32, i16, i16, i8, i8, i8, i8, i32 }
+ %struct.XXFFeedback = type { i8, i8, i8, i8, [16 x i32], [16 x i32] }
+ %struct.XViewport = type { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, double, double, i32, i32, i32, i32, float, float, float, float }
+ %struct.GIC4 = type { float, float, float, float }
+ %struct.GISWRSurface = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i8*, [4 x i8*], i32 }
+ %struct.GTCoord2 = type { float, float }
+ %struct.GVMFPContext = type { float, i32, i32, i32, float, [3 x float] }
+ %struct.GVMFPStack = type { [8 x i8*], i8*, i8*, i32, i32, { <4 x float> }, { <4 x float> }, <4 x i32> }
+ %struct.GVMFGAttrib = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, [8 x <4 x float>] }
+ %struct.GVMTs = type { [16 x %struct.XTRec*] }
+ %struct.PPSToken = type { { i16, i16, i32 } }
+ %struct._GVMConstants = type { <4 x i32>, <4 x i32>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, float, float, float, float, float, float, float, float, float, float, float, float, [256 x float], [528 x i8] }
+
+declare <4 x i32> @llvm.ppc.altivec.lvewx(i8*)
+
+declare i32 @llvm.ppc.altivec.vcmpequw.p(i32, <4 x i32>, <4 x i32>)
+
+define void @test(%struct.XState* %gldst, <4 x float>* %prgrm, <4 x float>** %buffs, %struct._GVMConstants* %cnstn, %struct.PPSToken* %pstrm, %struct.GVMFPContext* %vmctx, %struct.GVMTs* %txtrs, %struct.GVMFPStack* %fpstk, %struct.GVMFGAttrib* %start, %struct.GVMFGAttrib* %deriv, i32 %fragx, i32 %fragy) {
+bb58.i:
+ %tmp3405.i = getelementptr %struct.XTRec* null, i32 0, i32 1 ; <float*> [#uses=1]
+ %tmp34053406.i = bitcast float* %tmp3405.i to i8* ; <i8*> [#uses=1]
+ %tmp3407.i = call <4 x i32> @llvm.ppc.altivec.lvewx( i8* %tmp34053406.i ) ; <<4 x i32>> [#uses=0]
+ %tmp4146.i = call i32 @llvm.ppc.altivec.vcmpequw.p( i32 3, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32> [#uses=1]
+ %tmp4147.i = icmp eq i32 %tmp4146.i, 0 ; <i1> [#uses=1]
+ br i1 %tmp4147.i, label %bb8799.i, label %bb4150.i
+
+bb4150.i: ; preds = %bb58.i
+ br label %bb8799.i
+
+bb8799.i: ; preds = %bb4150.i, %bb58.i
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll b/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll
new file mode 100644
index 0000000..06f40d9
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=ppc64
+; PR1596
+
+ %struct._obstack_chunk = type { i8* }
+ %struct.obstack = type { i8*, %struct._obstack_chunk* (i8*, i64)*, i8*, i8 }
+
+define i32 @_obstack_newchunk(%struct.obstack* %h, i32 %length) {
+entry:
+ br i1 false, label %cond_false, label %cond_true
+
+cond_true: ; preds = %entry
+ br i1 false, label %cond_true28, label %cond_next30
+
+cond_false: ; preds = %entry
+ %tmp22 = tail call %struct._obstack_chunk* null( i64 undef ) ; <%struct._obstack_chunk*> [#uses=2]
+ br i1 false, label %cond_true28, label %cond_next30
+
+cond_true28: ; preds = %cond_false, %cond_true
+ %iftmp.0.043.0 = phi %struct._obstack_chunk* [ null, %cond_true ], [ %tmp22, %cond_false ] ; <%struct._obstack_chunk*> [#uses=1]
+ tail call void null( )
+ br label %cond_next30
+
+cond_next30: ; preds = %cond_true28, %cond_false, %cond_true
+ %iftmp.0.043.1 = phi %struct._obstack_chunk* [ %iftmp.0.043.0, %cond_true28 ], [ null, %cond_true ], [ %tmp22, %cond_false ] ; <%struct._obstack_chunk*> [#uses=1]
+ %tmp41 = getelementptr %struct._obstack_chunk* %iftmp.0.043.1, i32 0, i32 0 ; <i8**> [#uses=1]
+ store i8* null, i8** %tmp41, align 8
+ ret i32 undef
+}
diff --git a/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll b/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll
new file mode 100644
index 0000000..82ef2b8
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=ppc64 | grep dst | count 4
+
+define hidden void @_Z4borkPc(i8* %image) {
+entry:
+ tail call void @llvm.ppc.altivec.dst( i8* %image, i32 8, i32 0 )
+ tail call void @llvm.ppc.altivec.dstt( i8* %image, i32 8, i32 0 )
+ tail call void @llvm.ppc.altivec.dstst( i8* %image, i32 8, i32 0 )
+ tail call void @llvm.ppc.altivec.dststt( i8* %image, i32 8, i32 0 )
+ ret void
+}
+
+declare void @llvm.ppc.altivec.dst(i8*, i32, i32)
+declare void @llvm.ppc.altivec.dstt(i8*, i32, i32)
+declare void @llvm.ppc.altivec.dstst(i8*, i32, i32)
+declare void @llvm.ppc.altivec.dststt(i8*, i32, i32)
diff --git a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll
new file mode 100644
index 0000000..ea7de98
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=ppc64 | grep lwzx
+
+ %struct.__db_region = type { %struct.__mutex_t, [4 x i8], %struct.anon, i32, [1 x i32] }
+ %struct.__mutex_t = type { i32 }
+ %struct.anon = type { i64, i64 }
+
+define void @foo() {
+entry:
+ %ttype = alloca i32, align 4 ; <i32*> [#uses=1]
+ %regs = alloca [1024 x %struct.__db_region], align 16 ; <[1024 x %struct.__db_region]*> [#uses=0]
+ %tmp = load i32* %ttype, align 4 ; <i32> [#uses=1]
+ %tmp1 = call i32 (...)* @bork( i32 %tmp ) ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @bork(...)
diff --git a/test/CodeGen/PowerPC/2007-09-08-unaligned.ll b/test/CodeGen/PowerPC/2007-09-08-unaligned.ll
new file mode 100644
index 0000000..898c470
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-09-08-unaligned.ll
@@ -0,0 +1,53 @@
+; RUN: llc < %s | grep stfd | count 3
+; RUN: llc < %s | grep stfs | count 1
+; RUN: llc < %s | grep lfd | count 2
+; RUN: llc < %s | grep lfs | count 2
+; ModuleID = 'foo.c'
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin8"
+ %struct.anon = type <{ i8, float }>
+@s = global %struct.anon <{ i8 3, float 0x4014666660000000 }> ; <%struct.anon*> [#uses=1]
+@u = global <{ i8, double }> <{ i8 3, double 5.100000e+00 }> ; <<{ i8, double }>*> [#uses=1]
+@t = weak global %struct.anon zeroinitializer ; <%struct.anon*> [#uses=2]
+@v = weak global <{ i8, double }> zeroinitializer ; <<{ i8, double }>*> [#uses=2]
[email protected] = internal constant [8 x i8] c"%f %lf\0A\00" ; <[8 x i8]*> [#uses=1]
+
+define i32 @foo() {
+entry:
+ %retval = alloca i32, align 4 ; <i32*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %tmp = getelementptr %struct.anon* @s, i32 0, i32 1 ; <float*> [#uses=1]
+ %tmp1 = load float* %tmp, align 1 ; <float> [#uses=1]
+ %tmp2 = getelementptr %struct.anon* @t, i32 0, i32 1 ; <float*> [#uses=1]
+ store float %tmp1, float* %tmp2, align 1
+ %tmp3 = getelementptr <{ i8, double }>* @u, i32 0, i32 1 ; <double*> [#uses=1]
+ %tmp4 = load double* %tmp3, align 1 ; <double> [#uses=1]
+ %tmp5 = getelementptr <{ i8, double }>* @v, i32 0, i32 1 ; <double*> [#uses=1]
+ store double %tmp4, double* %tmp5, align 1
+ br label %return
+
+return: ; preds = %entry
+ %retval6 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval6
+}
+
+define i32 @main() {
+entry:
+ %retval = alloca i32, align 4 ; <i32*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %tmp = call i32 @foo( ) ; <i32> [#uses=0]
+ %tmp1 = getelementptr %struct.anon* @t, i32 0, i32 1 ; <float*> [#uses=1]
+ %tmp2 = load float* %tmp1, align 1 ; <float> [#uses=1]
+ %tmp23 = fpext float %tmp2 to double ; <double> [#uses=1]
+ %tmp4 = getelementptr <{ i8, double }>* @v, i32 0, i32 1 ; <double*> [#uses=1]
+ %tmp5 = load double* %tmp4, align 1 ; <double> [#uses=1]
+ %tmp6 = getelementptr [8 x i8]* @.str, i32 0, i32 0 ; <i8*> [#uses=1]
+ %tmp7 = call i32 (i8*, ...)* @printf( i8* %tmp6, double %tmp23, double %tmp5 ) ; <i32> [#uses=0]
+ br label %return
+
+return: ; preds = %entry
+ %retval8 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval8
+}
+
+declare i32 @printf(i8*, ...)
diff --git a/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll b/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll
new file mode 100644
index 0000000..d12698b
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=ppc64
+
+ %struct.TCMalloc_SpinLock = type { i32 }
+
+define void @_ZN17TCMalloc_SpinLock4LockEv(%struct.TCMalloc_SpinLock* %this) {
+entry:
+ %tmp3 = call i32 asm sideeffect "1: lwarx $0, 0, $1\0A\09stwcx. $2, 0, $1\0A\09bne- 1b\0A\09isync", "=&r,=*r,r,1,~{dirflag},~{fpsr},~{flags},~{memory}"( i32** null, i32 1, i32* null ) ; <i32> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll b/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll
new file mode 100644
index 0000000..5cfe54e
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=powerpc64-apple-darwin
+
+declare void @cxa_atexit_check_1(i8*)
+
+define i32 @check_cxa_atexit(i32 (void (i8*)*, i8*, i8*)* %cxa_atexit, void (i8*)* %cxa_finalize) {
+entry:
+ %tmp7 = call i32 null( void (i8*)* @cxa_atexit_check_1, i8* null, i8* null ) ; <i32> [#uses=0]
+ br i1 false, label %cond_true, label %cond_next
+
+cond_true: ; preds = %entry
+ ret i32 0
+
+cond_next: ; preds = %entry
+ ret i32 0
+}
diff --git a/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll b/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll
new file mode 100644
index 0000000..c4152b4
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=ppc32
+; rdar://5538377
+
+ %struct.disk_unsigned = type { i32 }
+ %struct._StorePageMax = type { %struct.disk_unsigned, %struct.disk_unsigned, [65536 x i8] }
+
+define i32 @test() {
+entry:
+ %data = alloca i32 ; <i32*> [#uses=1]
+ %compressedPage = alloca %struct._StorePageMax ; <%struct._StorePageMax*> [#uses=0]
+ %tmp107 = call i32 asm "lwbrx $0, $2, $1", "=r,r,bO,*m"( i8* null, i32 0, i32* %data ) ; <i32> [#uses=0]
+ unreachable
+}
+
diff --git a/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll b/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll
new file mode 100644
index 0000000..84fadd1
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=ppc64 -mattr=+altivec
+ %struct.inoutprops = type <{ i8, [3 x i8] }>
+
+define void @bork(float* %argA, float* %argB, float* %res, i8 %inoutspec.0) {
+entry:
+ %.mask = and i8 %inoutspec.0, -16 ; <i8> [#uses=1]
+ %tmp6 = icmp eq i8 %.mask, 16 ; <i1> [#uses=1]
+ br i1 %tmp6, label %cond_true, label %UnifiedReturnBlock
+
+cond_true: ; preds = %entry
+ %tmp89 = bitcast float* %res to <4 x i32>* ; <<4 x i32>*> [#uses=1]
+ %tmp1011 = bitcast float* %argA to <4 x i32>* ; <<4 x i32>*> [#uses=1]
+ %tmp14 = load <4 x i32>* %tmp1011, align 16 ; <<4 x i32>> [#uses=1]
+ %tmp1516 = bitcast float* %argB to <4 x i32>* ; <<4 x i32>*> [#uses=1]
+ %tmp18 = load <4 x i32>* %tmp1516, align 16 ; <<4 x i32>> [#uses=1]
+ %tmp19 = sdiv <4 x i32> %tmp14, %tmp18 ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %tmp19, <4 x i32>* %tmp89, align 16
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
new file mode 100644
index 0000000..ee61478
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic
+
+ %struct.NSError = type opaque
+ %struct.NSManagedObjectContext = type opaque
+ %struct.NSPersistentStoreCoordinator = type opaque
+ %struct.NSString = type opaque
+ %struct.NSURL = type opaque
+ %struct._message_ref_t = type { %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*, %struct.objc_selector* }
+ %struct.objc_object = type { }
+ %struct.objc_selector = type opaque
+@"\01L_OBJC_MESSAGE_REF_2" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=1]
+@"\01L_OBJC_MESSAGE_REF_6" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=1]
+@NSXMLStoreType = external constant %struct.NSString* ; <%struct.NSString**> [#uses=1]
+@"\01L_OBJC_MESSAGE_REF_5" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=2]
+@"\01L_OBJC_MESSAGE_REF_4" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=1]
+
+define %struct.NSManagedObjectContext* @"+[ListGenerator(Private) managedObjectContextWithModelURL:storeURL:]"(%struct.objc_object* %self, %struct._message_ref_t* %_cmd, %struct.NSURL* %modelURL, %struct.NSURL* %storeURL) {
+entry:
+ %storeCoordinator = alloca %struct.NSPersistentStoreCoordinator* ; <%struct.NSPersistentStoreCoordinator**> [#uses=0]
+ %tmp29 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2" ) ; <%struct.objc_object*> [#uses=0]
+ %tmp34 = load %struct.NSString** @NSXMLStoreType, align 8 ; <%struct.NSString*> [#uses=1]
+ %tmp37 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_5", i32 0, i32 0), align 8 ; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1]
+ %tmp42 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 1 ) ; <%struct.objc_object*> [#uses=1]
+ %tmp45 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp37( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_5", %struct.objc_object* %tmp42, %struct.NSString* null ) ; <%struct.objc_object*> [#uses=1]
+ %tmp48 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", %struct.NSString* %tmp34, i8* null, %struct.NSURL* null, %struct.objc_object* %tmp45, %struct.NSError** null ) ; <%struct.objc_object*> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
new file mode 100644
index 0000000..5a07a9b
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic
+
+ %struct.NSError = type opaque
+ %struct.NSManagedObjectContext = type opaque
+ %struct.NSString = type opaque
+ %struct.NSURL = type opaque
+ %struct._message_ref_t = type { %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*, %struct.objc_selector* }
+ %struct.objc_object = type { }
+ %struct.objc_selector = type opaque
+@"\01L_OBJC_MESSAGE_REF_2" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=2]
+@"\01L_OBJC_MESSAGE_REF_6" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=2]
+@NSXMLStoreType = external constant %struct.NSString* ; <%struct.NSString**> [#uses=1]
+@"\01L_OBJC_MESSAGE_REF_4" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=2]
+
+define %struct.NSManagedObjectContext* @"+[ListGenerator(Private) managedObjectContextWithModelURL:storeURL:]"(%struct.objc_object* %self, %struct._message_ref_t* %_cmd, %struct.NSURL* %modelURL, %struct.NSURL* %storeURL) {
+entry:
+ %tmp27 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2", i32 0, i32 0), align 8 ; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1]
+ %tmp29 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp27( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2" ) ; <%struct.objc_object*> [#uses=0]
+ %tmp33 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", i32 0, i32 0), align 8 ; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1]
+ %tmp34 = load %struct.NSString** @NSXMLStoreType, align 8 ; <%struct.NSString*> [#uses=1]
+ %tmp40 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 0, i32 0), align 8 ; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1]
+ %tmp42 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp40( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 1 ) ; <%struct.objc_object*> [#uses=0]
+ %tmp48 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp33( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", %struct.NSString* %tmp34, i8* null, %struct.NSURL* null, %struct.objc_object* null, %struct.NSError** null ) ; <%struct.objc_object*> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll b/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll
new file mode 100644
index 0000000..a9f242b
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll
@@ -0,0 +1,148 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
+
+ %struct.HDescriptor = type <{ i32, i32 }>
+
+declare void @bcopy(i8*, i8*, i32)
+
+define i32 @main(i32 %argc, i8** %argv) {
+entry:
+ br i1 false, label %bb31, label %bb
+
+bb: ; preds = %entry
+ ret i32 -6
+
+bb31: ; preds = %entry
+ switch i32 0, label %bb189 [
+ i32 73, label %cond_next209
+ i32 74, label %bb74
+ i32 77, label %bb57
+ i32 78, label %cond_next209
+ i32 85, label %cond_next209
+ i32 97, label %cond_next209
+ i32 100, label %cond_next209
+ i32 107, label %cond_next209
+ i32 109, label %bb57
+ i32 112, label %bb43
+ i32 115, label %cond_next209
+ i32 117, label %bb51
+ ]
+
+bb43: ; preds = %bb31
+ br i1 false, label %cond_true48, label %cond_true200.critedge2117
+
+cond_true48: ; preds = %bb43
+ br i1 false, label %cond_next372, label %AllDone
+
+bb51: ; preds = %bb31
+ ret i32 0
+
+bb57: ; preds = %bb31, %bb31
+ ret i32 0
+
+bb74: ; preds = %bb31
+ ret i32 0
+
+bb189: ; preds = %bb31
+ ret i32 0
+
+cond_true200.critedge2117: ; preds = %bb43
+ ret i32 0
+
+cond_next209: ; preds = %bb31, %bb31, %bb31, %bb31, %bb31, %bb31, %bb31
+ ret i32 0
+
+cond_next372: ; preds = %cond_true48
+ switch i32 0, label %bb1728 [
+ i32 73, label %bb1723
+ i32 74, label %cond_true1700
+ i32 78, label %bb1718
+ i32 85, label %bb1713
+ i32 97, label %bb1620
+ i32 107, label %AllDone
+ i32 112, label %cond_next423
+ i32 117, label %cond_next1453
+ ]
+
+cond_next423: ; preds = %cond_next372
+ switch i16 0, label %cond_next691 [
+ i16 18475, label %cond_next807
+ i16 18520, label %cond_next807
+ ]
+
+cond_next691: ; preds = %cond_next423
+ ret i32 0
+
+cond_next807: ; preds = %cond_next423, %cond_next423
+ switch i16 0, label %cond_true1192 [
+ i16 18475, label %cond_next21.i
+ i16 18520, label %cond_next21.i
+ ]
+
+cond_next21.i: ; preds = %cond_next807, %cond_next807
+ br i1 false, label %cond_next934, label %free.i
+
+free.i: ; preds = %cond_next21.i
+ ret i32 0
+
+cond_next934: ; preds = %bb1005, %cond_next21.i
+ %listsize.1 = phi i32 [ 0, %bb1005 ], [ 64, %cond_next21.i ] ; <i32> [#uses=1]
+ %catalogExtents.2 = phi %struct.HDescriptor* [ %catalogExtents.1.reg2mem.1, %bb1005 ], [ null, %cond_next21.i ] ; <%struct.HDescriptor*> [#uses=3]
+ br i1 false, label %cond_next942, label %Return1020
+
+cond_next942: ; preds = %cond_next934
+ br i1 false, label %bb1005, label %bb947
+
+bb947: ; preds = %cond_next971, %cond_next942
+ %indvar = phi i32 [ 0, %cond_next942 ], [ %indvar.next2140, %cond_next971 ] ; <i32> [#uses=2]
+ %catalogExtents.1.reg2mem.0 = phi %struct.HDescriptor* [ %catalogExtents.2, %cond_next942 ], [ %tmp977978, %cond_next971 ] ; <%struct.HDescriptor*> [#uses=1]
+ %extents.0.reg2mem.0 = phi %struct.HDescriptor* [ null, %cond_next942 ], [ %tmp977978, %cond_next971 ] ; <%struct.HDescriptor*> [#uses=1]
+ br i1 false, label %cond_next971, label %Return1020
+
+cond_next971: ; preds = %bb947
+ %tmp = shl i32 %indvar, 6 ; <i32> [#uses=1]
+ %listsize.0.reg2mem.0 = add i32 %tmp, %listsize.1 ; <i32> [#uses=1]
+ %tmp973 = add i32 %listsize.0.reg2mem.0, 64 ; <i32> [#uses=1]
+ %tmp974975 = bitcast %struct.HDescriptor* %extents.0.reg2mem.0 to i8* ; <i8*> [#uses=1]
+ %tmp977 = call i8* @realloc( i8* %tmp974975, i32 %tmp973 ) ; <i8*> [#uses=1]
+ %tmp977978 = bitcast i8* %tmp977 to %struct.HDescriptor* ; <%struct.HDescriptor*> [#uses=3]
+ call void @bcopy( i8* null, i8* null, i32 64 )
+ %indvar.next2140 = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br i1 false, label %bb1005, label %bb947
+
+bb1005: ; preds = %cond_next971, %cond_next942
+ %catalogExtents.1.reg2mem.1 = phi %struct.HDescriptor* [ %catalogExtents.2, %cond_next942 ], [ %tmp977978, %cond_next971 ] ; <%struct.HDescriptor*> [#uses=2]
+ br i1 false, label %Return1020, label %cond_next934
+
+Return1020: ; preds = %bb1005, %bb947, %cond_next934
+ %catalogExtents.3 = phi %struct.HDescriptor* [ %catalogExtents.1.reg2mem.0, %bb947 ], [ %catalogExtents.2, %cond_next934 ], [ %catalogExtents.1.reg2mem.1, %bb1005 ] ; <%struct.HDescriptor*> [#uses=0]
+ ret i32 0
+
+cond_true1192: ; preds = %cond_next807
+ ret i32 0
+
+cond_next1453: ; preds = %cond_next372
+ ret i32 0
+
+bb1620: ; preds = %cond_next372
+ ret i32 0
+
+cond_true1700: ; preds = %cond_next372
+ ret i32 0
+
+bb1713: ; preds = %cond_next372
+ ret i32 0
+
+bb1718: ; preds = %cond_next372
+ ret i32 0
+
+bb1723: ; preds = %cond_next372
+ ret i32 0
+
+bb1728: ; preds = %cond_next372
+ ret i32 -6
+
+AllDone: ; preds = %cond_next372, %cond_true48
+ ret i32 0
+}
+
+declare i8* @realloc(i8*, i32)
diff --git a/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll b/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll
new file mode 100644
index 0000000..439ef14
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll
@@ -0,0 +1,59 @@
+; RUN: llc < %s -enable-eh
+;; Formerly crashed, see PR 1508
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc64-apple-darwin8"
+ %struct.Range = type { i64, i64 }
+
+define void @Bork(i64 %range.0.0, i64 %range.0.1, i64 %size) {
+entry:
+ %effectiveRange = alloca %struct.Range, align 8 ; <%struct.Range*> [#uses=2]
+ %tmp4 = call i8* @llvm.stacksave() ; <i8*> [#uses=1]
+ %size1 = trunc i64 %size to i32 ; <i32> [#uses=1]
+ %tmp17 = alloca i8*, i32 %size1 ; <i8**> [#uses=1]
+ invoke void @Foo(i8** %tmp17)
+ to label %bb30.preheader unwind label %unwind
+
+bb30.preheader: ; preds = %entry
+ %tmp26 = getelementptr %struct.Range* %effectiveRange, i64 0, i32 1 ; <i64*> [#uses=1]
+ br label %bb30
+
+unwind: ; preds = %cond_true, %entry
+ %eh_ptr = call i8* @llvm.eh.exception() ; <i8*> [#uses=2]
+ %eh_select = call i64 (i8*, i8*, ...)* @llvm.eh.selector.i64(i8* %eh_ptr, i8* bitcast (void ()* @__gxx_personality_v0 to i8*), i8* null) ; <i64> [#uses=0]
+ call void @llvm.stackrestore(i8* %tmp4)
+ call void @_Unwind_Resume(i8* %eh_ptr)
+ unreachable
+
+invcont23: ; preds = %cond_true
+ %tmp27 = load i64* %tmp26, align 8 ; <i64> [#uses=1]
+ %tmp28 = sub i64 %range_addr.1.0, %tmp27 ; <i64> [#uses=1]
+ br label %bb30
+
+bb30: ; preds = %invcont23, %bb30.preheader
+ %range_addr.1.0 = phi i64 [ %tmp28, %invcont23 ], [ %range.0.1, %bb30.preheader ] ; <i64> [#uses=2]
+ %tmp33 = icmp eq i64 %range_addr.1.0, 0 ; <i1> [#uses=1]
+ br i1 %tmp33, label %cleanup, label %cond_true
+
+cond_true: ; preds = %bb30
+ invoke void @Bar(i64 %range.0.0, %struct.Range* %effectiveRange)
+ to label %invcont23 unwind label %unwind
+
+cleanup: ; preds = %bb30
+ ret void
+}
+
+declare i8* @llvm.stacksave() nounwind
+
+declare void @Foo(i8**)
+
+declare i8* @llvm.eh.exception() nounwind
+
+declare i64 @llvm.eh.selector.i64(i8*, i8*, ...) nounwind
+
+declare void @__gxx_personality_v0()
+
+declare void @_Unwind_Resume(i8*)
+
+declare void @Bar(i64, %struct.Range*)
+
+declare void @llvm.stackrestore(i8*) nounwind
diff --git a/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
new file mode 100644
index 0000000..d1f0285
--- /dev/null
+++ b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s
+; RUN: llc < %s -march=ppc32 -mcpu=g3
+; RUN: llc < %s -march=ppc32 -mcpu=g5
+; PR1811
+
+define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>*
+%CONST) {
+entry:
+ %input2 = load <4 x float>* null, align 16 ; <<4 x float>>
+ %shuffle7 = shufflevector <4 x float> %input2, <4 x float> < float 0.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00 >, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x float>> [#uses=1]
+
+ %mul1 = fmul <4 x float> %shuffle7, zeroinitializer ; <<4 x
+ %add2 = fadd <4 x float> %mul1, %input2 ; <<4 x float>>
+ store <4 x float> %add2, <4 x float>* null, align 16
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll b/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll
new file mode 100644
index 0000000..a05245d
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=ppc32 | grep .byte
+target triple = "powerpc-apple-darwin8"
+
+
+define void @bork() noreturn nounwind {
+entry:
+ unreachable
+}
diff --git a/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll b/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll
new file mode 100644
index 0000000..791e9e6
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll
@@ -0,0 +1,67 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
+
+ %struct.Handle = type { %struct.oopDesc** }
+ %struct.JNI_ArgumentPusher = type { %struct.SignatureIterator, %struct.JavaCallArguments* }
+ %struct.JNI_ArgumentPusherArray = type { %struct.JNI_ArgumentPusher, %struct.JvmtiEventEnabled* }
+ %struct.JavaCallArguments = type { [9 x i32], [9 x i32], i32*, i32*, i32, i32, i32 }
+ %struct.JvmtiEventEnabled = type { i64 }
+ %struct.KlassHandle = type { %struct.Handle }
+ %struct.SignatureIterator = type { i32 (...)**, %struct.KlassHandle, i32, i32, i32 }
+ %struct.instanceOopDesc = type { %struct.oopDesc }
+ %struct.oopDesc = type { %struct.instanceOopDesc*, %struct.instanceOopDesc* }
[email protected] = external constant [44 x i8] ; <[44 x i8]*> [#uses=1]
+
+define void @_ZN23JNI_ArgumentPusherArray7iterateEy(%struct.JNI_ArgumentPusherArray* %this, i64 %fingerprint) nounwind {
+entry:
+ br label %bb113
+
+bb22.preheader: ; preds = %bb113
+ ret void
+
+bb32.preheader: ; preds = %bb113
+ ret void
+
+bb42.preheader: ; preds = %bb113
+ ret void
+
+bb52: ; preds = %bb113
+ br label %bb113
+
+bb62.preheader: ; preds = %bb113
+ ret void
+
+bb72.preheader: ; preds = %bb113
+ ret void
+
+bb82: ; preds = %bb113
+ br label %bb113
+
+bb93: ; preds = %bb113
+ br label %bb113
+
+bb103.preheader: ; preds = %bb113
+ ret void
+
+bb113: ; preds = %bb113, %bb93, %bb82, %bb52, %entry
+ %fingerprint_addr.0.reg2mem.9 = phi i64 [ 0, %entry ], [ 0, %bb52 ], [ 0, %bb82 ], [ 0, %bb93 ], [ %tmp118, %bb113 ] ; <i64> [#uses=1]
+ tail call void @_Z28report_should_not_reach_herePKci( i8* getelementptr ([44 x i8]* @.str, i32 0, i32 0), i32 817 ) nounwind
+ %tmp118 = lshr i64 %fingerprint_addr.0.reg2mem.9, 4 ; <i64> [#uses=2]
+ %tmp21158 = and i64 %tmp118, 15 ; <i64> [#uses=1]
+ switch i64 %tmp21158, label %bb113 [
+ i64 1, label %bb22.preheader
+ i64 2, label %bb52
+ i64 3, label %bb32.preheader
+ i64 4, label %bb42.preheader
+ i64 5, label %bb62.preheader
+ i64 6, label %bb82
+ i64 7, label %bb93
+ i64 8, label %bb103.preheader
+ i64 9, label %bb72.preheader
+ i64 10, label %UnifiedReturnBlock
+ ]
+
+UnifiedReturnBlock: ; preds = %bb113
+ ret void
+}
+
+declare void @_Z28report_should_not_reach_herePKci(i8*, i32)
diff --git a/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll b/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll
new file mode 100644
index 0000000..cfa1b10
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin -regalloc=local
+
+define i32 @bork(i64 %foo, i64 %bar) {
+entry:
+ %tmp = load i64* null, align 8 ; <i64> [#uses=2]
+ %tmp2 = icmp ule i64 %tmp, 0 ; <i1> [#uses=1]
+ %min = select i1 %tmp2, i64 %tmp, i64 0 ; <i64> [#uses=1]
+ store i64 %min, i64* null, align 8
+ ret i32 0
+}
diff --git a/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll b/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
new file mode 100644
index 0000000..e50fac44
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin -enable-ppc32-regscavenger
+
+declare i8* @bar(i32)
+
+define void @foo(i8* %pp) nounwind {
+entry:
+ %tmp2 = tail call i8* @bar( i32 14 ) nounwind ; <i8*> [#uses=0]
+ %tmp28 = bitcast i8* %pp to void ()** ; <void ()**> [#uses=1]
+ %tmp38 = load void ()** %tmp28, align 4 ; <void ()*> [#uses=2]
+ br i1 false, label %bb34, label %bb25
+bb25: ; preds = %entry
+ %tmp30 = bitcast void ()* %tmp38 to void (i8*)* ; <void (i8*)*> [#uses=1]
+ tail call void %tmp30( i8* null ) nounwind
+ ret void
+bb34: ; preds = %entry
+ tail call void %tmp38( ) nounwind
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll b/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll
new file mode 100644
index 0000000..222dde4
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=ppc64 -enable-ppc64-regscavenger
[email protected] = external constant [3 x i8] ; <[3 x i8]*> [#uses=1]
+
+define fastcc void @ParseContent(i8* %buf, i32 %bufsize) {
+entry:
+ %items = alloca [10000 x i8*], align 16 ; <[10000 x i8*]*> [#uses=0]
+ %tmp86 = add i32 0, -1 ; <i32> [#uses=1]
+ br i1 false, label %cond_true94, label %cond_next99
+cond_true94: ; preds = %entry
+ %tmp98 = call i32 (i8*, ...)* @printf( i8* getelementptr ([3 x i8]* @.str242, i32 0, i32 0), i8* null ) ; <i32> [#uses=0]
+ %tmp20971 = icmp sgt i32 %tmp86, 0 ; <i1> [#uses=1]
+ br i1 %tmp20971, label %bb101, label %bb212
+cond_next99: ; preds = %entry
+ ret void
+bb101: ; preds = %cond_true94
+ ret void
+bb212: ; preds = %cond_true94
+ ret void
+}
+
+declare i32 @printf(i8*, ...)
diff --git a/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll b/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
new file mode 100644
index 0000000..9f35b83
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=ppc32 -enable-ppc32-regscavenger
+
+ %struct._cpp_strbuf = type { i8*, i32, i32 }
+ %struct.cpp_string = type { i32, i8* }
+
+declare fastcc void @emit_numeric_escape(i32, i32, %struct._cpp_strbuf*, i32) nounwind
+
+define i32 @cpp_interpret_string(i32 %pfile, %struct.cpp_string* %from, i32 %wide) nounwind {
+entry:
+ %tmp61 = load i32* null, align 4 ; <i32> [#uses=1]
+ %toBool = icmp eq i32 %wide, 0 ; <i1> [#uses=2]
+ %iftmp.87.0 = select i1 %toBool, i32 %tmp61, i32 0 ; <i32> [#uses=2]
+ %tmp69 = icmp ult i32 %iftmp.87.0, 33 ; <i1> [#uses=1]
+ %min = select i1 %tmp69, i32 %iftmp.87.0, i32 32 ; <i32> [#uses=1]
+ %tmp71 = icmp ugt i32 %min, 31 ; <i1> [#uses=1]
+ br i1 %tmp71, label %bb79, label %bb75
+bb75: ; preds = %entry
+ ret i32 0
+bb79: ; preds = %entry
+ br i1 %toBool, label %bb103, label %bb94
+bb94: ; preds = %bb79
+ br i1 false, label %bb729, label %bb130.preheader
+bb103: ; preds = %bb79
+ ret i32 0
+bb130.preheader: ; preds = %bb94
+ %tmp134 = getelementptr %struct.cpp_string* %from, i32 0, i32 1 ; <i8**> [#uses=0]
+ ret i32 0
+bb729: ; preds = %bb94
+ call fastcc void @emit_numeric_escape( i32 %pfile, i32 0, %struct._cpp_strbuf* null, i32 %wide ) nounwind
+ ret i32 1
+}
diff --git a/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll b/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll
new file mode 100644
index 0000000..dd425f5
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=ppc64 -enable-ppc64-regscavenger
+
+define i16 @test(i8* %d1, i16* %d2) {
+ %tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 )
+ ret i16 %tmp237
+}
diff --git a/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll b/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll
new file mode 100644
index 0000000..a8fef05
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=ppc64
+
+define fastcc i8* @page_rec_get_next(i8* %rec) nounwind {
+entry:
+ %tmp2627 = ptrtoint i8* %rec to i64 ; <i64> [#uses=2]
+ %tmp28 = and i64 %tmp2627, -16384 ; <i64> [#uses=2]
+ %tmp2829 = inttoptr i64 %tmp28 to i8* ; <i8*> [#uses=1]
+ %tmp37 = getelementptr i8* %tmp2829, i64 42 ; <i8*> [#uses=1]
+ %tmp40 = load i8* %tmp37, align 1 ; <i8> [#uses=1]
+ %tmp4041 = zext i8 %tmp40 to i64 ; <i64> [#uses=1]
+ %tmp42 = shl i64 %tmp4041, 8 ; <i64> [#uses=1]
+ %tmp47 = add i64 %tmp42, 0 ; <i64> [#uses=1]
+ %tmp52 = and i64 %tmp47, 32768 ; <i64> [#uses=1]
+ %tmp72 = icmp eq i64 %tmp52, 0 ; <i1> [#uses=1]
+ br i1 %tmp72, label %bb91, label %bb
+bb: ; preds = %entry
+ ret i8* null
+bb91: ; preds = %entry
+ br i1 false, label %bb100, label %bb185
+bb100: ; preds = %bb91
+ %tmp106 = sub i64 %tmp2627, %tmp28 ; <i64> [#uses=0]
+ ret i8* null
+bb185: ; preds = %bb91
+ ret i8* null
+}
diff --git a/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll
new file mode 100644
index 0000000..8776d9a
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=ppc32
+
+ %struct..0objc_object = type { %struct.objc_class* }
+ %struct.NSArray = type { %struct..0objc_object }
+ %struct.NSMutableArray = type { %struct.NSArray }
+ %struct.PFTPersistentSymbols = type { %struct..0objc_object, %struct.VMUSymbolicator*, %struct.NSMutableArray*, %struct.__CFDictionary*, %struct.__CFDictionary*, %struct.__CFDictionary*, %struct.__CFDictionary*, %struct.NSMutableArray*, i8, %struct.pthread_mutex_t, %struct.NSMutableArray*, %struct.pthread_rwlock_t }
+ %struct.VMUMachTaskContainer = type { %struct..0objc_object, i32, i32 }
+ %struct.VMUSymbolicator = type { %struct..0objc_object, %struct.NSMutableArray*, %struct.NSArray*, %struct.NSArray*, %struct.VMUMachTaskContainer*, i8 }
+ %struct.__CFDictionary = type opaque
+ %struct.__builtin_CFString = type { i32*, i32, i8*, i32 }
+ %struct.objc_class = type opaque
+ %struct.objc_selector = type opaque
+ %struct.pthread_mutex_t = type { i32, [40 x i8] }
+ %struct.pthread_rwlock_t = type { i32, [124 x i8] }
+external constant %struct.__builtin_CFString ; <%struct.__builtin_CFString*>:0 [#uses=1]
+
+define void @"-[PFTPersistentSymbols saveSymbolWithName:address:path:lineNumber:flags:owner:]"(%struct.PFTPersistentSymbols* %self, %struct.objc_selector* %_cmd, %struct.NSArray* %name, i64 %address, %struct.NSArray* %path, i32 %lineNumber, i64 %flags, %struct..0objc_object* %owner) nounwind {
+entry:
+ br i1 false, label %bb12, label %bb21
+bb12: ; preds = %entry
+ %tmp17 = tail call i8 inttoptr (i64 4294901504 to i8 (%struct..0objc_object*, %struct.objc_selector*, %struct.NSArray*)*)( %struct..0objc_object* null, %struct.objc_selector* null, %struct.NSArray* bitcast (%struct.__builtin_CFString* @0 to %struct.NSArray*) ) signext nounwind ; <i8> [#uses=0]
+ br i1 false, label %bb25, label %bb21
+bb21: ; preds = %bb12, %entry
+ %tmp24 = or i64 %flags, 4 ; <i64> [#uses=1]
+ br label %bb25
+bb25: ; preds = %bb21, %bb12
+ %flags_addr.0 = phi i64 [ %tmp24, %bb21 ], [ %flags, %bb12 ] ; <i64> [#uses=1]
+ %tmp3233 = trunc i64 %flags_addr.0 to i32 ; <i32> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll
new file mode 100644
index 0000000..8e5bf56
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
+
+define i32 @t(i64 %byteStart, i32 %activeIndex) nounwind {
+entry:
+ %tmp50 = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp5051 = zext i32 %tmp50 to i64 ; <i64> [#uses=3]
+ %tmp53 = udiv i64 %byteStart, %tmp5051 ; <i64> [#uses=1]
+ %tmp5354 = trunc i64 %tmp53 to i32 ; <i32> [#uses=1]
+ %tmp62 = urem i64 %byteStart, %tmp5051 ; <i64> [#uses=1]
+ %tmp94 = add i32 0, 1 ; <i32> [#uses=1]
+ %tmp100 = urem i32 %tmp94, 0 ; <i32> [#uses=2]
+ %tmp108 = add i32 0, %activeIndex ; <i32> [#uses=1]
+ %tmp110 = sub i32 %tmp108, 0 ; <i32> [#uses=1]
+ %tmp112 = urem i32 %tmp110, 0 ; <i32> [#uses=2]
+ %tmp122 = icmp ult i32 %tmp112, %tmp100 ; <i1> [#uses=1]
+ %iftmp.175.0 = select i1 %tmp122, i32 %tmp112, i32 %tmp100 ; <i32> [#uses=1]
+ %tmp119 = add i32 %tmp5354, 0 ; <i32> [#uses=1]
+ %tmp131 = add i32 %tmp119, %iftmp.175.0 ; <i32> [#uses=1]
+ %tmp131132 = zext i32 %tmp131 to i64 ; <i64> [#uses=1]
+ %tmp147 = mul i64 %tmp131132, %tmp5051 ; <i64> [#uses=1]
+ br i1 false, label %bb164, label %bb190
+bb164: ; preds = %entry
+ %tmp171172 = and i64 %tmp62, 4294967295 ; <i64> [#uses=1]
+ %tmp173 = add i64 %tmp171172, %tmp147 ; <i64> [#uses=0]
+ ret i32 0
+bb190: ; preds = %entry
+ ret i32 0
+}
diff --git a/test/CodeGen/PowerPC/2008-04-10-LiveIntervalCrash.ll b/test/CodeGen/PowerPC/2008-04-10-LiveIntervalCrash.ll
new file mode 100644
index 0000000..2706337
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-04-10-LiveIntervalCrash.ll
@@ -0,0 +1,100 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
+
+define fastcc i64 @nonzero_bits1() nounwind {
+entry:
+ switch i32 0, label %bb1385 [
+ i32 28, label %bb235
+ i32 35, label %bb153
+ i32 37, label %bb951
+ i32 40, label %bb289
+ i32 44, label %bb1344
+ i32 46, label %bb651
+ i32 47, label %bb651
+ i32 48, label %bb322
+ i32 49, label %bb651
+ i32 50, label %bb651
+ i32 51, label %bb651
+ i32 52, label %bb651
+ i32 53, label %bb651
+ i32 54, label %bb535
+ i32 55, label %bb565
+ i32 56, label %bb565
+ i32 58, label %bb1100
+ i32 59, label %bb1100
+ i32 60, label %bb1100
+ i32 61, label %bb1100
+ i32 63, label %bb565
+ i32 64, label %bb565
+ i32 65, label %bb565
+ i32 66, label %bb565
+ i32 73, label %bb302
+ i32 74, label %bb302
+ i32 75, label %bb302
+ i32 76, label %bb302
+ i32 77, label %bb302
+ i32 78, label %bb302
+ i32 79, label %bb302
+ i32 80, label %bb302
+ i32 81, label %bb302
+ i32 82, label %bb302
+ i32 83, label %bb302
+ i32 84, label %bb302
+ i32 85, label %bb302
+ i32 86, label %bb302
+ i32 87, label %bb302
+ i32 88, label %bb302
+ i32 89, label %bb302
+ i32 90, label %bb302
+ i32 91, label %bb507
+ i32 92, label %bb375
+ i32 93, label %bb355
+ i32 103, label %bb1277
+ i32 104, label %bb1310
+ i32 105, label %UnifiedReturnBlock
+ i32 106, label %bb1277
+ i32 107, label %bb1343
+ ]
+bb153: ; preds = %entry
+ ret i64 0
+bb235: ; preds = %entry
+ br i1 false, label %bb245, label %UnifiedReturnBlock
+bb245: ; preds = %bb235
+ ret i64 0
+bb289: ; preds = %entry
+ ret i64 0
+bb302: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry
+ ret i64 0
+bb322: ; preds = %entry
+ ret i64 0
+bb355: ; preds = %entry
+ ret i64 0
+bb375: ; preds = %entry
+ ret i64 0
+bb507: ; preds = %entry
+ ret i64 0
+bb535: ; preds = %entry
+ ret i64 0
+bb565: ; preds = %entry, %entry, %entry, %entry, %entry, %entry
+ ret i64 0
+bb651: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry
+ ret i64 0
+bb951: ; preds = %entry
+ ret i64 0
+bb1100: ; preds = %entry, %entry, %entry, %entry
+ ret i64 0
+bb1277: ; preds = %entry, %entry
+ br i1 false, label %UnifiedReturnBlock, label %bb1284
+bb1284: ; preds = %bb1277
+ ret i64 0
+bb1310: ; preds = %entry
+ ret i64 0
+bb1343: ; preds = %entry
+ ret i64 1
+bb1344: ; preds = %entry
+ ret i64 0
+bb1385: ; preds = %entry
+ ret i64 0
+UnifiedReturnBlock: ; preds = %bb1277, %bb235, %entry
+ %UnifiedRetVal = phi i64 [ 0, %bb235 ], [ undef, %bb1277 ], [ -1, %entry ] ; <i64> [#uses=1]
+ ret i64 %UnifiedRetVal
+}
diff --git a/test/CodeGen/PowerPC/2008-04-16-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-04-16-CoalescerBug.ll
new file mode 100644
index 0000000..839098e
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-04-16-CoalescerBug.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
+; Avoid reading memory that's already freed.
+
[email protected] = appending global [1 x i8*] [ i8* bitcast (i32 (i64)* @_Z13GetSectorSizey to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define i32 @_Z13GetSectorSizey(i64 %Base) nounwind {
+entry:
+ br i1 false, label %bb, label %UnifiedReturnBlock
+bb: ; preds = %entry
+ %tmp10 = and i64 0, %Base ; <i64> [#uses=0]
+ ret i32 0
+UnifiedReturnBlock: ; preds = %entry
+ ret i32 131072
+}
diff --git a/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll b/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll
new file mode 100644
index 0000000..7b6d491
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll
@@ -0,0 +1,89 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
+
+@_ZL10DeviceCode = internal global i16 0 ; <i16*> [#uses=1]
[email protected] = internal constant [64 x i8] c"unlock_then_erase_sector: failed to erase block (status= 0x%x)\0A\00" ; <[64 x i8]*> [#uses=1]
[email protected] = internal constant [68 x i8] c"ProgramByWords - Erasing sector 0x%llx to 0x%llx (size 0x%x bytes)\0A\00" ; <[68 x i8]*> [#uses=1]
[email protected] = internal constant [37 x i8] c"ProgramByWords - Done erasing flash\0A\00" ; <[37 x i8]*> [#uses=1]
[email protected] = internal constant [48 x i8] c"ProgramByWords - Starting to write to FLASH...\0A\00" ; <[48 x i8]*> [#uses=1]
+
+declare void @IOLog(i8*, ...)
+
+declare void @IODelay(i32)
+
+define i32 @_Z14ProgramByWordsPvyy(i8* %buffer, i64 %Offset, i64 %bufferSize) nounwind {
+entry:
+ volatile store i8 -1, i8* null, align 1
+ %tmp28 = icmp eq i8 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp28, label %bb107, label %bb
+
+bb: ; preds = %entry
+ %tmp9596430 = zext i32 0 to i64 ; <i64> [#uses=1]
+ %tmp98431 = add i64 %tmp9596430, %Offset ; <i64> [#uses=1]
+ %tmp100433 = icmp ugt i64 %tmp98431, %Offset ; <i1> [#uses=1]
+ br i1 %tmp100433, label %bb31, label %bb103
+
+bb31: ; preds = %_Z24unlock_then_erase_sectory.exit, %bb
+ %Pos.0.reg2mem.0 = phi i64 [ %tmp93, %_Z24unlock_then_erase_sectory.exit ], [ %Offset, %bb ] ; <i64> [#uses=3]
+ %tmp35 = load i16* @_ZL10DeviceCode, align 2 ; <i16> [#uses=1]
+ %tmp3536 = zext i16 %tmp35 to i32 ; <i32> [#uses=2]
+ %tmp37 = and i32 %tmp3536, 65520 ; <i32> [#uses=1]
+ %tmp38 = icmp eq i32 %tmp37, 35008 ; <i1> [#uses=1]
+ %tmp34 = sub i64 %Pos.0.reg2mem.0, %Offset ; <i64> [#uses=2]
+ br i1 %tmp38, label %bb41, label %bb68
+
+bb41: ; preds = %bb31
+ %tmp43 = add i32 0, -1 ; <i32> [#uses=1]
+ %tmp4344 = zext i32 %tmp43 to i64 ; <i64> [#uses=1]
+ %tmp46 = and i64 %tmp4344, %tmp34 ; <i64> [#uses=0]
+ %tmp49 = and i32 %tmp3536, 1 ; <i32> [#uses=0]
+ ret i32 0
+
+bb68: ; preds = %bb31
+ tail call void (i8*, ...)* @IOLog( i8* getelementptr ([68 x i8]* @.str34, i32 0, i32 0), i64 %tmp34, i64 0, i32 131072 ) nounwind
+ %tmp2021.i = trunc i64 %Pos.0.reg2mem.0 to i32 ; <i32> [#uses=1]
+ %tmp202122.i = inttoptr i32 %tmp2021.i to i8* ; <i8*> [#uses=1]
+ tail call void @IODelay( i32 500 ) nounwind
+ %tmp53.i = volatile load i16* null, align 2 ; <i16> [#uses=2]
+ %tmp5455.i = zext i16 %tmp53.i to i32 ; <i32> [#uses=1]
+ br i1 false, label %bb.i, label %bb65.i
+
+bb.i: ; preds = %bb68
+ ret i32 0
+
+bb65.i: ; preds = %bb68
+ %tmp67.i = icmp eq i16 %tmp53.i, 128 ; <i1> [#uses=1]
+ br i1 %tmp67.i, label %_Z24unlock_then_erase_sectory.exit, label %bb70.i
+
+bb70.i: ; preds = %bb65.i
+ tail call void (i8*, ...)* @IOLog( i8* getelementptr ([64 x i8]* @.str19, i32 0, i32 0), i32 %tmp5455.i ) nounwind
+ ret i32 0
+
+_Z24unlock_then_erase_sectory.exit: ; preds = %bb65.i
+ volatile store i8 -1, i8* %tmp202122.i, align 1
+ %tmp93 = add i64 0, %Pos.0.reg2mem.0 ; <i64> [#uses=2]
+ %tmp98 = add i64 0, %Offset ; <i64> [#uses=1]
+ %tmp100 = icmp ugt i64 %tmp98, %tmp93 ; <i1> [#uses=1]
+ br i1 %tmp100, label %bb31, label %bb103
+
+bb103: ; preds = %_Z24unlock_then_erase_sectory.exit, %bb
+ tail call void (i8*, ...)* @IOLog( i8* getelementptr ([37 x i8]* @.str35, i32 0, i32 0) ) nounwind
+ ret i32 0
+
+bb107: ; preds = %entry
+ tail call void (i8*, ...)* @IOLog( i8* getelementptr ([48 x i8]* @.str36, i32 0, i32 0) ) nounwind
+ %tmp114115 = bitcast i8* %buffer to i16* ; <i16*> [#uses=1]
+ %tmp256 = lshr i64 %bufferSize, 1 ; <i64> [#uses=1]
+ %tmp256257 = trunc i64 %tmp256 to i32 ; <i32> [#uses=1]
+ %tmp258 = getelementptr i16* %tmp114115, i32 %tmp256257 ; <i16*> [#uses=0]
+ ret i32 0
+}
+
+define i32 @_Z17program_64B_blockyPm(i64 %Base, i32* %pData) nounwind {
+entry:
+ unreachable
+}
+
+define i32 @_Z15ProgramByBlocksyy(i64 %Offset, i64 %bufferSize) nounwind {
+entry:
+ ret i32 0
+}
diff --git a/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll b/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll
new file mode 100644
index 0000000..d42c814
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=ppc32
+target triple = "powerpc-apple-darwin9.2.2"
+
+define i256 @func(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind readnone {
+entry:
+ br i1 false, label %bb36, label %bb484
+
+bb36: ; preds = %entry
+ %tmp124 = fcmp ord ppc_fp128 %b, 0xM00000000000000000000000000000000 ; <i1> [#uses=1]
+ %tmp140 = and i1 %tmp124, fcmp une (ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128 0xM00000000000000000000000000000000) ; <i1> [#uses=0]
+ unreachable
+
+bb484: ; preds = %entry
+ ret i256 0
+}
diff --git a/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll b/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll
new file mode 100644
index 0000000..6b40b24
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=ppc32
+
+define void @t() nounwind {
+ call void null( ppc_fp128 undef )
+ unreachable
+}
diff --git a/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll b/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll
new file mode 100644
index 0000000..862559b
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=ppc32
+
+@g = external global ppc_fp128
+@h = external global ppc_fp128
+
+define void @f() {
+ %tmp = load ppc_fp128* @g
+ store ppc_fp128 %tmp, ppc_fp128* @h
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll b/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll
new file mode 100644
index 0000000..83c5511
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=ppc32
+; <rdar://problem/6020042>
+
+define i32 @bork() nounwind {
+entry:
+ br i1 true, label %bb1, label %bb3
+
+bb1:
+ %tmp1 = load i8* null, align 1
+ %tmp2 = icmp eq i8 %tmp1, 0
+ br label %bb2
+
+bb2:
+ %val1 = phi i32 [ 0, %bb1 ], [ %val2, %bb2 ]
+ %val2 = select i1 %tmp2, i32 -1, i32 %val1
+ switch i32 %val2, label %bb2 [
+ i32 -1, label %bb3
+ i32 0, label %bb1
+ i32 1, label %bb3
+ i32 2, label %bb1
+ ]
+
+bb3:
+ ret i32 -1
+}
diff --git a/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll b/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll
new file mode 100644
index 0000000..8802b97
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vadduhm
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsubuhm
+
+define <4 x i32> @test() nounwind {
+ ret <4 x i32> < i32 4293066722, i32 4293066722, i32 4293066722, i32 4293066722>
+}
+
+define <4 x i32> @test2() nounwind {
+ ret <4 x i32> < i32 1114129, i32 1114129, i32 1114129, i32 1114129>
+}
diff --git a/test/CodeGen/PowerPC/2008-07-15-Bswap.ll b/test/CodeGen/PowerPC/2008-07-15-Bswap.ll
new file mode 100644
index 0000000..4a834f9
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-07-15-Bswap.ll
@@ -0,0 +1,386 @@
+; RUN: llc < %s
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin9"
+ %struct.BiPartSrcDescriptor = type <{ %"struct.BiPartSrcDescriptor::$_105" }>
+ %"struct.BiPartSrcDescriptor::$_105" = type { %struct.BiPartSrcDescriptor_NO_VECTOR_ALIGNMENT_size_is_16 }
+ %struct.BiPartSrcDescriptor_NO_VECTOR_ALIGNMENT_size_is_16 = type { [2 x %struct.MotionVectors], [2 x i8], %struct.Map4x4ToPartIdx, [2 x i8], i8, i8 }
+ %struct.Condv = type opaque
+ %struct.DHBFLayerId = type { i8 }
+ %struct.DecodeComplexityInfo = type { i32, i32, i32, i32, %"struct.DecodeComplexityInfo::IntraStats", %"struct.DecodeComplexityInfo::InterStats" }
+ %"struct.DecodeComplexityInfo::InterStats" = type { i32, i32, i32, i32, [5 x i32], [3 x i32], [4 x [4 x i32]], [4 x i32], i32, %struct.MotionVectors, %struct.MotionVectors }
+ %"struct.DecodeComplexityInfo::IntraStats" = type { i32, i32, i32, [5 x i32], [3 x i32], [4 x i32], [3 x i32] }
+ %struct.DecodeComplexityOptions = type { i8, i8, i32, double, i8, float, i8, float, i8, i8, i8, i8, i8 }
+ %struct.DescriptorAllocator = type { %struct.Mutex*, %struct.Mutex*, i8**, i32, i32, i8**, i32, i32, i8**, i32, i32 }
+ %struct.DetailsFromSliceType = type <{ i8 }>
+ %struct.FlatnessAnalysis = type { i16, i16, i32, i32*, i8*, [512 x i32], [256 x i32] }
+ %struct.Frame = type <{ i8, i8, i8, i8, i8, [3 x i8], i32, i32, %struct.Mutex*, %struct.Condv*, [8 x i8], %struct.FramePixels, %struct.FrameMotionVectorCache, %struct.FrameIndex, i32, i8*, i8*, i8*, i8*, i16*, %struct.FlatnessAnalysis, %struct.NoiseAnalysis, %struct.VisualActivity, %struct.FrameMotionInfo, %struct.FrameMotionAnalysis, %struct.FrameDataRateParameters, %struct.FrameEncoderTags, %struct.DecodeComplexityInfo, %struct.DecodeComplexityOptions, %struct.MotionInfoFor16x16_FasterSP*, [1 x i32] }>
+ %struct.FrameDataRateParameters = type { i32, float, i8, i8 }
+ %struct.FrameEncoderTags = type { i8, i8, i32, i8, i8, float }
+ %struct.FrameIndex = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i32, i32, %struct.Frame*, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, %struct.DHBFLayerId }
+ %struct.FrameMotionAnalysis = type { i32, i32, i32, %struct.MoEstMotion16x16*, %struct.MbAnalysis*, i32, i32, i16, i16, i32, i32, i32, i32, i8, i8 }
+ %struct.FrameMotionInfo = type { i32, i32, %struct.MoEstMbMotionInfo*, i32, i32, i32, i32, i32 }
+ %struct.FrameMotionVectorCache = type <{ %struct.ThreadAllocator**, i32, i32, i32, %struct.BiPartSrcDescriptor, %struct.BiPartSrcDescriptor, %struct.BiPartSrcDescriptor, [3 x %struct.BiPartSrcDescriptor*], %struct.BiPartSrcDescriptor** }>
+ %struct.FramePixels = type <{ i8, i8, i8, i8, i8, i8, i8, i8, i8*, i8*, i32, [4 x i8*], [4 x i8*], [2 x [4 x i32]], [2 x [4 x i32]], %struct.PixelData, %struct.InterpolationCache*, %struct.InterpolationCache*, %struct.InterpolationCache*, [16 x i16], [16 x i16], [12 x i8], %"struct.PortableSInt32Array<4>", %"struct.PortableSInt32Array<8>", %struct.ICOffsetArraysY, %struct.UVSrcOffsetEtcX_Struct*, i32*, i32*, [3 x i32] }>
+ %struct.ICOffsetArraysY = type { [21 x i32], [21 x i32], [4 x [21 x i32]] }
+ %struct.InterpolationCache = type opaque
+ %struct.LoopFilterInfo = type { %struct.BiPartSrcDescriptor**, i32, i32, i32, i32, i32*, i32, %"struct.LoopFilterInfo::SliceInfoStruct"*, i32, %struct.Mutex*, i16*, %struct.FramePixels*, i8*, i8*, i8*, i8*, i8*, %struct.PerMacroblockBoundaryStrengths*, %struct.Mutex*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8*, i8*, i8, void (i8*, i8*, i32, i32, i32, i32, i32, i8*, i32)*, void (i8*, i8*, i32, i32, i32, i32, i32, i8*, i32, i8*)*, i32 }
+ %"struct.LoopFilterInfo::SliceInfoStruct" = type { %"struct.LoopFilterInfo::SliceInfoStruct::LFDisableStats", i8, i8, i8, i8, [17 x %struct.Frame*], [17 x %struct.Frame*] }
+ %"struct.LoopFilterInfo::SliceInfoStruct::LFDisableStats" = type { i32, i32 }
+ %struct.LoopFilterParam = type { i32, %struct.LoopFilterInfo*, %struct.FramePixels*, %struct.FrameMotionVectorCache* }
+ %struct.Map4x4ToPartIdx = type { i16 }
+ %struct.MbAnalysis = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, %struct.RdCost, %struct.RdCost, i32 }
+ %struct.MoEstMbMotionInfo = type { i32, i32, i32, i32, [16 x %struct.MoEstPartMotionInfo] }
+ %struct.MoEstMotion16x16 = type { [2 x i8], [2 x %struct.MotionVectors], i8, [3 x %struct.MoEstPredCost] }
+ %struct.MoEstPartMotionInfo = type { i32, %struct.PartGeom, i32, i32, [2 x %struct.MotionVectors], [2 x i8], i16 }
+ %struct.MoEstPredCost = type { i32, i16, i16 }
+ %struct.MotionInfoFor16x16_FasterSP = type { [2 x %struct.MotionVectors], [2 x i8], i8, [2 x i32], i32, i32 }
+ %struct.MotionVectors = type { %"struct.MotionVectors::$_103" }
+ %"struct.MotionVectors::$_103" = type { i32 }
+ %struct.Mutex = type opaque
+ %struct.NoiseAnalysis = type { i16, i16, i32, i8*, i8*, i8*, [512 x i32] }
+ %struct.PartGeom = type { %struct.Map4x4ToPartIdx }
+ %struct.PerMacroblockBoundaryStrengths = type { [16 x i8], [16 x i8], [4 x i8], [4 x i8], [2 x i32] }
+ %struct.PixelData = type { i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8 }
+ %"struct.PortableSInt32Array<4>" = type { [4 x i32] }
+ %"struct.PortableSInt32Array<8>" = type { [8 x i32] }
+ %struct.RdCost = type { i32, i32, i32, double }
+ %struct.ThreadAllocator = type { %struct.DescriptorAllocator*, %struct.BiPartSrcDescriptor*, [256 x %struct.BiPartSrcDescriptor*], i32, i32, i32 }
+ %struct.ThreadedBatch = type opaque
+ %struct.UVSrcOffsetEtcX_Struct = type <{ i16 }>
+ %struct.VisualActivity = type { i16, i16, i32, i32, i32*, i32*, i32, i32, i32*, i32, i32, i32, i32, i32, i8*, i32, [2 x i32], i32, i32, i32, i16*, i16, i16, i16, i16, float, i8*, i32*, i32, i32, i8 }
+@_ZL33table_8_14_indexA_to_alpha_scalar = external constant [64 x i8] ; <[64 x i8]*> [#uses=0]
+@_ZL32table_8_14_indexB_to_beta_scalar = external constant [64 x i8] ; <[64 x i8]*> [#uses=0]
+@_ZL34table_8_15_indexA_bS_to_tc0_scalar = external constant [64 x [4 x i8]] ; <[64 x [4 x i8]]*> [#uses=0]
+@gkDummy = external global i32 ; <i32*> [#uses=0]
+@gkDetailsFromSliceTypeArray = external constant [10 x %struct.DetailsFromSliceType] ; <[10 x %struct.DetailsFromSliceType]*> [#uses=0]
+
+declare i32 @_Z20LoopFilter_ConstructP14LoopFilterInfojj(%struct.LoopFilterInfo*, i32, i32)
+
+declare i32 @_Z25LF_Threading2_assert_doneP14LoopFilterInfo(%struct.LoopFilterInfo*) nounwind
+
+declare i32 @_Z54S_CalcIfLargeMVDeltaForBMbBothPredictionsFromSameFramePK19BiPartSrcDescriptorS1_ijj(%struct.BiPartSrcDescriptor*, %struct.BiPartSrcDescriptor*, i32, i32, i32) nounwind
+
+declare void @_Z30LoopFilter_Internal_FilterLumaPhiiiiii(i8*, i32, i32, i32, i32, i32, i32) nounwind
+
+declare void @_Z33LoopFilter_Internal_FilterChromaVPhiiiiiiiiii(i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind
+
+declare void @_Z33LoopFilter_Internal_FilterChromaHPhiiiiii(i8*, i32, i32, i32, i32, i32, i32) nounwind
+
+declare void @_Z42LoopFilter_Internal_filter_macroblock_lumaPK14LoopFilterInfoPhS2_iiiPK30PerMacroblockBoundaryStrengthsjj(%struct.LoopFilterInfo*, i8*, i8*, i32, i32, i32, %struct.PerMacroblockBoundaryStrengths*, i32, i32) nounwind
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind
+
+declare i32 @_Z40LoopFilter_Internal_FilterLumaPlaneMBAFFPK14LoopFilterInfojjj(%struct.LoopFilterInfo*, i32, i32, i32) nounwind
+
+declare void @_Z18LoopFilter_DestroyP14LoopFilterInfo(%struct.LoopFilterInfo*)
+
+declare void @MutexDispose(%struct.Mutex*)
+
+declare void @_ZdaPv(i8*) nounwind
+
+declare void @jvtDisposePTRVectorAligned(i8*)
+
+declare void @jvtDisposePTR(i8*)
+
+declare void @jvtDisposePTRMemAligned(i8*)
+
+declare void @_Z31LoopFilter_Internal_ResetTablesP14LoopFilterInfo(%struct.LoopFilterInfo*) nounwind
+
+declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind
+
+define i32 @_Z60LoopFilter_Internal_CalculateBoundaryStrengths_MbaffFramePicPK14LoopFilterInfoP22FrameMotionVectorCachejj(%struct.LoopFilterInfo* %lfiPtr, %struct.FrameMotionVectorCache* %frameMotionVectorCachePtr, i32 %mbY_min, i32 %mbY_maxPlus1) nounwind {
+entry:
+ icmp ult i32 %mbY_min, %mbY_maxPlus1 ; <i1>:0 [#uses=1]
+ br i1 %0, label %bb16, label %bb642
+
+bb16: ; preds = %entry
+ bitcast %struct.PerMacroblockBoundaryStrengths* null to i32* ; <i32*>:1 [#uses=3]
+ getelementptr i32* %1, i32 1 ; <i32*>:2 [#uses=0]
+ getelementptr i32* %1, i32 2 ; <i32*>:3 [#uses=0]
+ getelementptr i32* %1, i32 3 ; <i32*>:4 [#uses=0]
+ bitcast [16 x i8]* null to i32* ; <i32*>:5 [#uses=3]
+ getelementptr i32* %5, i32 1 ; <i32*>:6 [#uses=0]
+ getelementptr i32* %5, i32 2 ; <i32*>:7 [#uses=0]
+ getelementptr i32* %5, i32 3 ; <i32*>:8 [#uses=0]
+ icmp eq i32 0, 0 ; <i1>:9 [#uses=0]
+ lshr i32 0, 30 ; <i32>:10 [#uses=0]
+ and i32 0, 268435455 ; <i32>:11 [#uses=0]
+ lshr i32 0, 28 ; <i32>:12 [#uses=1]
+ and i32 %12, 3 ; <i32>:13 [#uses=0]
+ and i32 0, 1 ; <i32>:14 [#uses=1]
+ icmp eq i32 %14, 0 ; <i1>:15 [#uses=0]
+ zext i8 0 to i32 ; <i32>:16 [#uses=1]
+ %.not656 = icmp ne i32 0, 0 ; <i1> [#uses=1]
+ icmp eq i8 0, 0 ; <i1>:17 [#uses=0]
+ trunc i32 0 to i8 ; <i8>:18 [#uses=2]
+ add i32 0, 1 ; <i32>:19 [#uses=1]
+ %.not658 = icmp ne i32 0, 0 ; <i1> [#uses=1]
+ and i32 0, 268369920 ; <i32>:20 [#uses=1]
+ icmp eq i32 %20, 268369920 ; <i1>:21 [#uses=2]
+ getelementptr %struct.PerMacroblockBoundaryStrengths* null, i32 0, i32 2 ; <[4 x i8]*>:22 [#uses=1]
+ getelementptr %struct.PerMacroblockBoundaryStrengths* null, i32 0, i32 2, i32 0 ; <i8*>:23 [#uses=0]
+ and i32 0, -2 ; <i32>:24 [#uses=1]
+ add i32 %24, -1 ; <i32>:25 [#uses=0]
+ bitcast [4 x i8]* %22 to i32* ; <i32*>:26 [#uses=3]
+ getelementptr i32* %26, i32 1 ; <i32*>:27 [#uses=0]
+ getelementptr i32* %26, i32 2 ; <i32*>:28 [#uses=0]
+ getelementptr i32* %26, i32 3 ; <i32*>:29 [#uses=0]
+ br label %bb144
+
+bb144: ; preds = %bb395, %bb16
+ %idxEachField11.0773 = phi i32 [ 0, %bb16 ], [ %162, %bb395 ] ; <i32> [#uses=3]
+ %mbYLeft.2776 = phi i32 [ 0, %bb16 ], [ %mbYLeft.2776, %bb395 ] ; <i32> [#uses=3]
+ %mbXYLeft.2775 = phi i32 [ 0, %bb16 ], [ %mbXYLeft.2775, %bb395 ] ; <i32> [#uses=1]
+ %mixedModeLeftEdgeOfMbFlag.2774 = phi i32 [ 0, %bb16 ], [ 0, %bb395 ] ; <i32> [#uses=0]
+ %mbIndexLeft.2772 = phi i32 [ 0, %bb16 ], [ %mbIndexLeft.2772, %bb395 ] ; <i32> [#uses=2]
+ %boundaryStrengthsV.1771 = phi i8* [ null, %bb16 ], [ %158, %bb395 ] ; <i8*> [#uses=2]
+ %numEdgesToTest.1770 = phi i32 [ 4, %bb16 ], [ %numEdgesToTest.2, %bb395 ] ; <i32> [#uses=1]
+ icmp eq i32 %idxEachField11.0773, 0 ; <i1>:30 [#uses=0]
+ getelementptr %struct.BiPartSrcDescriptor** null, i32 %mbIndexLeft.2772 ; <%struct.BiPartSrcDescriptor**>:31 [#uses=1]
+ load %struct.BiPartSrcDescriptor** %31, align 4 ; <%struct.BiPartSrcDescriptor*>:32 [#uses=0]
+ %fMacroblockHasNonZeroBS.4 = select i1 %21, i32 1, i32 0 ; <i32> [#uses=1]
+ %numEdgesToTest.2 = select i1 %21, i32 1, i32 %numEdgesToTest.1770 ; <i32> [#uses=2]
+ store i8 32, i8* %boundaryStrengthsV.1771, align 1
+ br label %labelContinueEdgesLoopV
+
+bb200: ; preds = %labelContinueEdgesLoopV
+ lshr i32 %159, 28 ; <i32>:33 [#uses=2]
+ and i32 %160, %16 ; <i32>:34 [#uses=1]
+ icmp eq i32 %34, 0 ; <i1>:35 [#uses=0]
+ icmp eq i32 %160, 0 ; <i1>:36 [#uses=3]
+ zext i1 %36 to i32 ; <i32>:37 [#uses=1]
+ or i32 %37, -1 ; <i32>:38 [#uses=1]
+ or i32 %38, %33 ; <i32>:39 [#uses=1]
+ icmp eq i32 %39, 0 ; <i1>:40 [#uses=1]
+ br i1 %40, label %bb205, label %bb206
+
+bb205: ; preds = %bb200
+ store i8 32, i8* %158, align 1
+ br label %labelContinueEdgesLoopV
+
+bb206: ; preds = %bb200
+ icmp eq i32 %33, 15 ; <i1>:41 [#uses=1]
+ br i1 %41, label %labelContinueEdgesLoopV, label %bb210.preheader
+
+bb210.preheader: ; preds = %bb206
+ add i32 %160, 0 ; <i32>:42 [#uses=2]
+ %bothcond657 = and i1 %36, %.not656 ; <i1> [#uses=0]
+ shl i32 %idxEachField11.0773, 1 ; <i32>:43 [#uses=1]
+ add i32 %43, 0 ; <i32>:44 [#uses=0]
+ shl i32 %mbYLeft.2776, 2 ; <i32>:45 [#uses=0]
+ add i32 %42, -1 ; <i32>:46 [#uses=1]
+ icmp eq i32 0, 0 ; <i1>:47 [#uses=1]
+ %brmerge689.not = and i1 %47, false ; <i1> [#uses=0]
+ %bothcond659 = and i1 %36, %.not658 ; <i1> [#uses=0]
+ shl i32 %mbYLeft.2776, 1 ; <i32>:48 [#uses=1]
+ or i32 %48, 0 ; <i32>:49 [#uses=1]
+ shl i32 %49, 1 ; <i32>:50 [#uses=0]
+ add i32 0, 0 ; <i32>:51 [#uses=2]
+ mul i32 %51, 0 ; <i32>:52 [#uses=1]
+ add i32 %52, %42 ; <i32>:53 [#uses=1]
+ mul i32 %51, 0 ; <i32>:54 [#uses=1]
+ add i32 %46, %54 ; <i32>:55 [#uses=1]
+ getelementptr %struct.BiPartSrcDescriptor** null, i32 %53 ; <%struct.BiPartSrcDescriptor**>:56 [#uses=1]
+ load %struct.BiPartSrcDescriptor** %56, align 4 ; <%struct.BiPartSrcDescriptor*>:57 [#uses=7]
+ getelementptr %struct.BiPartSrcDescriptor** null, i32 %55 ; <%struct.BiPartSrcDescriptor**>:58 [#uses=1]
+ load %struct.BiPartSrcDescriptor** %58, align 4 ; <%struct.BiPartSrcDescriptor*>:59 [#uses=5]
+ icmp slt i32 %159, 0 ; <i1>:60 [#uses=0]
+ icmp eq %struct.BiPartSrcDescriptor* %57, %59 ; <i1>:61 [#uses=0]
+ bitcast %struct.BiPartSrcDescriptor* %57 to i16* ; <i16*>:62 [#uses=5]
+ load i16* %62, align 2 ; <i16>:63 [#uses=2]
+ getelementptr i16* %62, i32 1 ; <i16*>:64 [#uses=1]
+ load i16* %64, align 2 ; <i16>:65 [#uses=2]
+ getelementptr i16* %62, i32 2 ; <i16*>:66 [#uses=1]
+ load i16* %66, align 2 ; <i16>:67 [#uses=2]
+ getelementptr i16* %62, i32 3 ; <i16*>:68 [#uses=1]
+ load i16* %68, align 2 ; <i16>:69 [#uses=2]
+ getelementptr i16* %62, i32 6 ; <i16*>:70 [#uses=1]
+ load i16* %70, align 2 ; <i16>:71 [#uses=2]
+ bitcast %struct.BiPartSrcDescriptor* %59 to i16* ; <i16*>:72 [#uses=5]
+ load i16* %72, align 2 ; <i16>:73 [#uses=2]
+ getelementptr i16* %72, i32 1 ; <i16*>:74 [#uses=1]
+ load i16* %74, align 2 ; <i16>:75 [#uses=2]
+ getelementptr i16* %72, i32 2 ; <i16*>:76 [#uses=1]
+ load i16* %76, align 2 ; <i16>:77 [#uses=2]
+ getelementptr i16* %72, i32 3 ; <i16*>:78 [#uses=1]
+ load i16* %78, align 2 ; <i16>:79 [#uses=2]
+ getelementptr i16* %72, i32 6 ; <i16*>:80 [#uses=1]
+ load i16* %80, align 2 ; <i16>:81 [#uses=2]
+ sub i16 %63, %73 ; <i16>:82 [#uses=3]
+ sub i16 %65, %75 ; <i16>:83 [#uses=3]
+ sub i16 %67, %77 ; <i16>:84 [#uses=3]
+ sub i16 %69, %79 ; <i16>:85 [#uses=3]
+ sub i16 %71, %81 ; <i16>:86 [#uses=3]
+ sub i16 0, %82 ; <i16>:87 [#uses=1]
+ icmp slt i16 %82, 0 ; <i1>:88 [#uses=1]
+ %. = select i1 %88, i16 %87, i16 %82 ; <i16> [#uses=1]
+ sub i16 0, %83 ; <i16>:89 [#uses=1]
+ icmp slt i16 %83, 0 ; <i1>:90 [#uses=1]
+ %.660 = select i1 %90, i16 %89, i16 %83 ; <i16> [#uses=1]
+ sub i16 0, %84 ; <i16>:91 [#uses=1]
+ icmp slt i16 %84, 0 ; <i1>:92 [#uses=1]
+ %.661 = select i1 %92, i16 %91, i16 %84 ; <i16> [#uses=1]
+ sub i16 0, %85 ; <i16>:93 [#uses=1]
+ icmp slt i16 %85, 0 ; <i1>:94 [#uses=1]
+ %.662 = select i1 %94, i16 %93, i16 %85 ; <i16> [#uses=1]
+ sub i16 0, %86 ; <i16>:95 [#uses=1]
+ icmp slt i16 %86, 0 ; <i1>:96 [#uses=1]
+ %.663 = select i1 %96, i16 %95, i16 %86 ; <i16> [#uses=1]
+ getelementptr %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 1, i32 0 ; <i8*>:97 [#uses=1]
+ load i8* %97, align 1 ; <i8>:98 [#uses=1]
+ zext i8 %98 to i32 ; <i32>:99 [#uses=1]
+ getelementptr %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 1, i32 1 ; <i8*>:100 [#uses=1]
+ load i8* %100, align 1 ; <i8>:101 [#uses=1]
+ zext i8 %101 to i32 ; <i32>:102 [#uses=1]
+ getelementptr %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 3, i32 0 ; <i8*>:103 [#uses=1]
+ load i8* %103, align 1 ; <i8>:104 [#uses=2]
+ zext i8 %104 to i32 ; <i32>:105 [#uses=1]
+ getelementptr %struct.BiPartSrcDescriptor* %59, i32 0, i32 0, i32 0, i32 3, i32 0 ; <i8*>:106 [#uses=1]
+ load i8* %106, align 1 ; <i8>:107 [#uses=2]
+ zext i8 %107 to i32 ; <i32>:108 [#uses=1]
+ getelementptr %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 3, i32 1 ; <i8*>:109 [#uses=1]
+ load i8* %109, align 1 ; <i8>:110 [#uses=1]
+ zext i8 %110 to i32 ; <i32>:111 [#uses=1]
+ getelementptr %struct.BiPartSrcDescriptor* %59, i32 0, i32 0, i32 0, i32 3, i32 1 ; <i8*>:112 [#uses=1]
+ load i8* %112, align 1 ; <i8>:113 [#uses=1]
+ zext i8 %113 to i32 ; <i32>:114 [#uses=1]
+ lshr i32 %99, 4 ; <i32>:115 [#uses=1]
+ and i32 %115, 2 ; <i32>:116 [#uses=1]
+ lshr i32 %102, 5 ; <i32>:117 [#uses=1]
+ or i32 %116, %117 ; <i32>:118 [#uses=3]
+ icmp eq i32 %118, 0 ; <i1>:119 [#uses=0]
+ icmp eq i32 %118, 1 ; <i1>:120 [#uses=1]
+ br i1 %120, label %bb297, label %bb298
+
+bb297: ; preds = %bb210.preheader
+ br label %bb298
+
+bb298: ; preds = %bb297, %bb210.preheader
+ %vu8Mask_0.1 = phi i8 [ -1, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=1]
+ %vu8Mask_1.1 = phi i8 [ -1, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=1]
+ %vu8Mask_2.1 = phi i8 [ -1, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=0]
+ %vu8Mask_3.1 = phi i8 [ -1, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=1]
+ %vu8Mask_4.1 = phi i8 [ 0, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=0]
+ %vu8Mask_5.1 = phi i8 [ 0, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=1]
+ %vu8Mask_6.1 = phi i8 [ 0, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=0]
+ %vu8Mask_7.1 = phi i8 [ 0, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=1]
+ %vu8Mask_12.1 = phi i8 [ -1, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=0]
+ %vu8Mask_13.1 = phi i8 [ -1, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=0]
+ icmp eq i32 %118, 2 ; <i1>:121 [#uses=0]
+ and i8 %vu8Mask_1.1, 3 ; <i8>:122 [#uses=0]
+ and i8 %vu8Mask_5.1, 3 ; <i8>:123 [#uses=0]
+ and i8 %vu8Mask_3.1, %18 ; <i8>:124 [#uses=0]
+ and i8 %vu8Mask_7.1, %18 ; <i8>:125 [#uses=0]
+ icmp eq i8 %104, %107 ; <i1>:126 [#uses=1]
+ br i1 %126, label %bb328, label %bb303
+
+bb303: ; preds = %bb298
+ call i16 @llvm.bswap.i16( i16 %81 ) ; <i16>:127 [#uses=1]
+ sub i16 %63, %77 ; <i16>:128 [#uses=3]
+ sub i16 %65, %79 ; <i16>:129 [#uses=3]
+ sub i16 %67, %73 ; <i16>:130 [#uses=3]
+ sub i16 %69, %75 ; <i16>:131 [#uses=3]
+ sub i16 %71, %127 ; <i16>:132 [#uses=3]
+ sub i16 0, %128 ; <i16>:133 [#uses=1]
+ icmp slt i16 %128, 0 ; <i1>:134 [#uses=1]
+ %.673 = select i1 %134, i16 %133, i16 %128 ; <i16> [#uses=1]
+ sub i16 0, %129 ; <i16>:135 [#uses=1]
+ icmp slt i16 %129, 0 ; <i1>:136 [#uses=1]
+ %.674 = select i1 %136, i16 %135, i16 %129 ; <i16> [#uses=1]
+ sub i16 0, %130 ; <i16>:137 [#uses=1]
+ icmp slt i16 %130, 0 ; <i1>:138 [#uses=1]
+ %.675 = select i1 %138, i16 %137, i16 %130 ; <i16> [#uses=1]
+ sub i16 0, %131 ; <i16>:139 [#uses=1]
+ icmp slt i16 %131, 0 ; <i1>:140 [#uses=1]
+ %.676 = select i1 %140, i16 %139, i16 %131 ; <i16> [#uses=1]
+ sub i16 0, %132 ; <i16>:141 [#uses=1]
+ icmp slt i16 %132, 0 ; <i1>:142 [#uses=1]
+ %.677 = select i1 %142, i16 %141, i16 %132 ; <i16> [#uses=1]
+ br label %bb328
+
+bb328: ; preds = %bb303, %bb298
+ %vu16Delta_0.0 = phi i16 [ %.673, %bb303 ], [ %., %bb298 ] ; <i16> [#uses=1]
+ %vu16Delta_1.0 = phi i16 [ %.674, %bb303 ], [ %.660, %bb298 ] ; <i16> [#uses=0]
+ %vu16Delta_2.0 = phi i16 [ %.675, %bb303 ], [ %.661, %bb298 ] ; <i16> [#uses=0]
+ %vu16Delta_3.0 = phi i16 [ %.676, %bb303 ], [ %.662, %bb298 ] ; <i16> [#uses=0]
+ %vu16Delta_6.0 = phi i16 [ %.677, %bb303 ], [ %.663, %bb298 ] ; <i16> [#uses=0]
+ lshr i16 %vu16Delta_0.0, 8 ; <i16>:143 [#uses=1]
+ trunc i16 %143 to i8 ; <i8>:144 [#uses=1]
+ and i8 %144, %vu8Mask_0.1 ; <i8>:145 [#uses=1]
+ icmp eq i8 %145, 0 ; <i1>:146 [#uses=0]
+ sub i32 %105, %114 ; <i32>:147 [#uses=1]
+ sub i32 %111, %108 ; <i32>:148 [#uses=1]
+ or i32 %147, %148 ; <i32>:149 [#uses=1]
+ icmp eq i32 %149, 0 ; <i1>:150 [#uses=0]
+ call i32 @_Z54S_CalcIfLargeMVDeltaForBMbBothPredictionsFromSameFramePK19BiPartSrcDescriptorS1_ijj( %struct.BiPartSrcDescriptor* %57, %struct.BiPartSrcDescriptor* %59, i32 %19, i32 0, i32 0 ) nounwind ; <i32>:151 [#uses=0]
+ unreachable
+
+labelContinueEdgesLoopV: ; preds = %bb206, %bb205, %bb144
+ %fEdgeHasNonZeroBS.0 = phi i32 [ 0, %bb205 ], [ 0, %bb144 ], [ 1, %bb206 ] ; <i32> [#uses=2]
+ %fMacroblockHasNonZeroBS.6 = phi i32 [ %152, %bb205 ], [ %fMacroblockHasNonZeroBS.4, %bb144 ], [ %152, %bb206 ] ; <i32> [#uses=1]
+ %ixEdge.1 = phi i32 [ %160, %bb205 ], [ 0, %bb144 ], [ %160, %bb206 ] ; <i32> [#uses=1]
+ %bfNZ12.2 = phi i32 [ %159, %bb205 ], [ 0, %bb144 ], [ %159, %bb206 ] ; <i32> [#uses=1]
+ %boundaryStrengthsV.3 = phi i8* [ %158, %bb205 ], [ %boundaryStrengthsV.1771, %bb144 ], [ %158, %bb206 ] ; <i8*> [#uses=3]
+ or i32 %fMacroblockHasNonZeroBS.6, %fEdgeHasNonZeroBS.0 ; <i32>:152 [#uses=2]
+ load i8* %boundaryStrengthsV.3, align 1 ; <i8>:153 [#uses=1]
+ trunc i32 %fEdgeHasNonZeroBS.0 to i8 ; <i8>:154 [#uses=1]
+ shl i8 %154, 5 ; <i8>:155 [#uses=1]
+ xor i8 %155, 32 ; <i8>:156 [#uses=1]
+ or i8 %153, %156 ; <i8>:157 [#uses=1]
+ store i8 %157, i8* %boundaryStrengthsV.3, align 1
+ getelementptr i8* %boundaryStrengthsV.3, i32 4 ; <i8*>:158 [#uses=4]
+ shl i32 %bfNZ12.2, 4 ; <i32>:159 [#uses=4]
+ add i32 %ixEdge.1, 1 ; <i32>:160 [#uses=6]
+ icmp ult i32 %160, %numEdgesToTest.2 ; <i1>:161 [#uses=1]
+ br i1 %161, label %bb200, label %bb395
+
+bb395: ; preds = %labelContinueEdgesLoopV
+ add i32 %idxEachField11.0773, 1 ; <i32>:162 [#uses=2]
+ icmp ugt i32 %162, 0 ; <i1>:163 [#uses=1]
+ br i1 %163, label %bb398, label %bb144
+
+bb398: ; preds = %bb395
+ call void asm sideeffect "dcbt $0, $1", "b%,r,~{memory}"( i32 19, i32* null ) nounwind
+ unreachable
+
+bb642: ; preds = %entry
+ ret i32 0
+}
+
+declare i16 @llvm.bswap.i16(i16) nounwind readnone
+
+declare i8* @jvtNewPtrVectorAligned(i32)
+
+declare i8* @jvtNewPtr(i32)
+
+declare i8* @jvtNewPtrMemAligned(i32)
+
+declare %struct.Mutex* @MutexNew()
+
+declare i8* @_Znam(i32)
+
+declare i32 @_Z24LoopFilter_FilterMbGroupP14LoopFilterInfoP11FramePixelsP22FrameMotionVectorCacheP19ThreadedBatchStructjjij(%struct.LoopFilterInfo*, %struct.FramePixels*, %struct.FrameMotionVectorCache*, %struct.ThreadedBatch*, i32, i32, i32, i32)
+
+declare void @MutexLock(%struct.Mutex*)
+
+declare void @MutexUnlock(%struct.Mutex*)
+
+declare i32 @_Z35LoopFilter_Internal_FilterLumaPlanePK14LoopFilterInfojjjjj(%struct.LoopFilterInfo*, i32, i32, i32, i32, i32)
+
+declare i32 @_Z37LoopFilter_Internal_FilterChromaPlanePK14LoopFilterInfojjjjj(%struct.LoopFilterInfo*, i32, i32, i32, i32, i32)
+
+declare void @_Z44LoopFilter_Internal_filter_macroblock_chromaPK14LoopFilterInfoPhS2_iiiPK30PerMacroblockBoundaryStrengthsjj(%struct.LoopFilterInfo*, i8*, i8*, i32, i32, i32, %struct.PerMacroblockBoundaryStrengths*, i32, i32) nounwind
+
+declare i32 @_Z42LoopFilter_Internal_FilterChromaPlaneMBAFFPK14LoopFilterInfojjj(%struct.LoopFilterInfo*, i32, i32, i32) nounwind
+
+declare i32 @_Z26LF_Threading2_ProcessTasksP14LoopFilterInfoP11FramePixelsP22FrameMotionVectorCacheij(%struct.LoopFilterInfo*, %struct.FramePixels*, %struct.FrameMotionVectorCache*, i32, i32)
+
+declare i32 @_Z46LoopFilter_Internal_CalculateBoundaryStrengthsPK14LoopFilterInfoP22FrameMotionVectorCachejj(%struct.LoopFilterInfo*, %struct.FrameMotionVectorCache*, i32, i32)
+
+declare i32 @_Z44LoopFilter_Internal_FilterLumaChromaPlane_PPP14LoopFilterInfojjjjj(%struct.LoopFilterInfo*, i32, i32, i32, i32, i32)
+
+declare i32 @_Z22LoopFilter_FilterFrameP14LoopFilterInfoP11FramePixelsP22FrameMotionVectorCacheP19ThreadedBatchStructij(%struct.LoopFilterInfo*, %struct.FramePixels*, %struct.FrameMotionVectorCache*, %struct.ThreadedBatch*, i32, i32)
+
+declare void @_Z34LF_Threading2_ProcessTasks_WrapperPv(i8*)
+
+declare void @llvm.memset.i64(i8*, i8, i64, i32) nounwind
diff --git a/test/CodeGen/PowerPC/2008-07-15-Fabs.ll b/test/CodeGen/PowerPC/2008-07-15-Fabs.ll
new file mode 100644
index 0000000..17737d9
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-07-15-Fabs.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin9"
+
+define hidden i256 @__divtc3(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind readnone {
+entry:
+ call ppc_fp128 @fabsl( ppc_fp128 %d ) nounwind readnone ; <ppc_fp128>:0 [#uses=1]
+ fcmp olt ppc_fp128 0xM00000000000000000000000000000000, %0 ; <i1>:1 [#uses=1]
+ %.pn106 = select i1 %1, ppc_fp128 %a, ppc_fp128 0xM00000000000000000000000000000000 ; <ppc_fp128> [#uses=1]
+ %.pn = fsub ppc_fp128 0xM00000000000000000000000000000000, %.pn106 ; <ppc_fp128> [#uses=1]
+ %y.0 = fdiv ppc_fp128 %.pn, 0xM00000000000000000000000000000000 ; <ppc_fp128> [#uses=1]
+ fmul ppc_fp128 %y.0, 0xM3FF00000000000000000000000000000 ; <ppc_fp128>:2 [#uses=1]
+ fadd ppc_fp128 %2, fmul (ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128 0xM00000000000000000000000000000000) ; <ppc_fp128>:3 [#uses=1]
+ %tmpi = fadd ppc_fp128 %3, 0xM00000000000000000000000000000000 ; <ppc_fp128> [#uses=1]
+ store ppc_fp128 %tmpi, ppc_fp128* null, align 16
+ ret i256 0
+}
+
+declare ppc_fp128 @fabsl(ppc_fp128) nounwind readnone
diff --git a/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
new file mode 100644
index 0000000..5cd8c34
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin9"
+
+define i16 @t(i16* %dct) signext nounwind {
+entry:
+ load i16* null, align 2 ; <i16>:0 [#uses=2]
+ lshr i16 %0, 11 ; <i16>:1 [#uses=0]
+ trunc i16 %0 to i8 ; <i8>:2 [#uses=1]
+ sext i8 %2 to i16 ; <i16>:3 [#uses=1]
+ add i16 0, %3 ; <i16>:4 [#uses=1]
+ sext i16 %4 to i32 ; <i32>:5 [#uses=1]
+ %dcval.0.in = shl i32 %5, 0 ; <i32> [#uses=1]
+ %dcval.0 = trunc i32 %dcval.0.in to i16 ; <i16> [#uses=1]
+ store i16 %dcval.0, i16* %dct, align 2
+ ret i16 0
+}
diff --git a/test/CodeGen/PowerPC/2008-07-17-Fneg.ll b/test/CodeGen/PowerPC/2008-07-17-Fneg.ll
new file mode 100644
index 0000000..dc1e936
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-07-17-Fneg.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin9"
+
+define hidden i64 @__fixunstfdi(ppc_fp128 %a) nounwind {
+entry:
+ br i1 false, label %bb3, label %bb4
+
+bb3: ; preds = %entry
+ fsub ppc_fp128 0xM80000000000000000000000000000000, 0xM00000000000000000000000000000000 ; <ppc_fp128>:0 [#uses=1]
+ fptoui ppc_fp128 %0 to i32 ; <i32>:1 [#uses=1]
+ zext i32 %1 to i64 ; <i64>:2 [#uses=1]
+ sub i64 0, %2 ; <i64>:3 [#uses=1]
+ ret i64 %3
+
+bb4: ; preds = %entry
+ ret i64 0
+}
diff --git a/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll b/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll
new file mode 100644
index 0000000..c9c05e1
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=powerpc64-apple-darwin | grep lwz | grep 228
+
+@"\01LC" = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1]
+
+define void @llvm_static_func(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, i32 %a10, i32 %a11, i32 %a12, i32 %a13, i32 %a14, i32 %a15) nounwind {
+entry:
+ tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i64 0), i32 %a8 ) nounwind ; <i32>:0 [#uses=0]
+ ret void
+}
+
+declare i32 @printf(i8*, ...) nounwind
diff --git a/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll
new file mode 100644
index 0000000..97844dd
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll
@@ -0,0 +1,254 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
+
+ %struct.CGLDI = type { %struct.cgli*, i32, i32, i32, i32, i32, i8*, i32, void (%struct.CGLSI*, i32, %struct.CGLDI*)*, i8*, %struct.vv_t }
+ %struct.cgli = type { i32, %struct.cgli*, void (%struct.cgli*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32)*, i32, i8*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i8*, i32*, %struct._cgro*, %struct._cgro*, float, float, float, float, i32, i8*, float, i8*, [16 x i32] }
+ %struct.CGLSI = type { %struct.cgli*, i32, i8*, i8*, i32, i32, i8*, void (%struct.cgli*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32)*, %struct.vv_t, %struct.vv_t, %struct.xx_t* }
+ %struct._cgro = type opaque
+ %struct.xx_t = type { [3 x %struct.vv_t], [2 x %struct.vv_t], [2 x [3 x i8*]] }
+ %struct.vv_t = type { <16 x i8> }
[email protected] = appending global [1 x i8*] [ i8* bitcast (void (%struct.CGLSI*, i32, %struct.CGLDI*)* @lb to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define void @lb(%struct.CGLSI* %src, i32 %n, %struct.CGLDI* %dst) nounwind {
+entry:
+ %0 = load i32* null, align 4 ; <i32> [#uses=1]
+ %1 = icmp sgt i32 %0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %bb.nph4945, label %return
+
+bb.nph4945: ; preds = %entry
+ %2 = bitcast [2 x %struct.vv_t]* null to i64* ; <i64*> [#uses=6]
+ %3 = getelementptr [2 x i64]* null, i32 0, i32 1 ; <i64*> [#uses=6]
+ %4 = bitcast %struct.vv_t* null to i64* ; <i64*> [#uses=5]
+ %5 = getelementptr [2 x i64]* null, i32 0, i32 1 ; <i64*> [#uses=3]
+ br label %bb2326
+
+bb2217: ; preds = %bb2326
+ %6 = or i64 0, 0 ; <i64> [#uses=2]
+ %7 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1]
+ %8 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1]
+ %9 = getelementptr float* null, i32 2 ; <float*> [#uses=1]
+ %10 = load float* %9, align 4 ; <float> [#uses=1]
+ %11 = getelementptr float* null, i32 3 ; <float*> [#uses=1]
+ %12 = load float* %11, align 4 ; <float> [#uses=1]
+ %13 = fmul float %10, 6.553500e+04 ; <float> [#uses=1]
+ %14 = fadd float %13, 5.000000e-01 ; <float> [#uses=1]
+ %15 = fmul float %12, 6.553500e+04 ; <float> [#uses=1]
+ %16 = fadd float %15, 5.000000e-01 ; <float> [#uses=3]
+ %17 = fcmp olt float %14, 0.000000e+00 ; <i1> [#uses=0]
+ %18 = fcmp olt float %16, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %18, label %bb2265, label %bb2262
+
+bb2262: ; preds = %bb2217
+ %19 = fcmp ogt float %16, 6.553500e+04 ; <i1> [#uses=1]
+ br i1 %19, label %bb2264, label %bb2265
+
+bb2264: ; preds = %bb2262
+ br label %bb2265
+
+bb2265: ; preds = %bb2264, %bb2262, %bb2217
+ %f3596.0 = phi float [ 6.553500e+04, %bb2264 ], [ 0.000000e+00, %bb2217 ], [ %16, %bb2262 ] ; <float> [#uses=1]
+ %20 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1]
+ %21 = fptosi float %f3596.0 to i32 ; <i32> [#uses=1]
+ %22 = zext i32 %7 to i64 ; <i64> [#uses=1]
+ %23 = shl i64 %22, 48 ; <i64> [#uses=1]
+ %24 = zext i32 %8 to i64 ; <i64> [#uses=1]
+ %25 = shl i64 %24, 32 ; <i64> [#uses=1]
+ %26 = sext i32 %20 to i64 ; <i64> [#uses=1]
+ %27 = shl i64 %26, 16 ; <i64> [#uses=1]
+ %28 = sext i32 %21 to i64 ; <i64> [#uses=1]
+ %29 = or i64 %25, %23 ; <i64> [#uses=1]
+ %30 = or i64 %29, %27 ; <i64> [#uses=1]
+ %31 = or i64 %30, %28 ; <i64> [#uses=2]
+ %32 = shl i64 %6, 48 ; <i64> [#uses=1]
+ %33 = shl i64 %31, 32 ; <i64> [#uses=1]
+ %34 = and i64 %33, 281470681743360 ; <i64> [#uses=1]
+ store i64 %6, i64* %2, align 16
+ store i64 %31, i64* %3, align 8
+ %35 = getelementptr i8* null, i32 0 ; <i8*> [#uses=1]
+ %36 = bitcast i8* %35 to float* ; <float*> [#uses=4]
+ %37 = load float* %36, align 4 ; <float> [#uses=1]
+ %38 = getelementptr float* %36, i32 1 ; <float*> [#uses=1]
+ %39 = load float* %38, align 4 ; <float> [#uses=1]
+ %40 = fmul float %37, 6.553500e+04 ; <float> [#uses=1]
+ %41 = fadd float %40, 5.000000e-01 ; <float> [#uses=1]
+ %42 = fmul float %39, 6.553500e+04 ; <float> [#uses=1]
+ %43 = fadd float %42, 5.000000e-01 ; <float> [#uses=3]
+ %44 = fcmp olt float %41, 0.000000e+00 ; <i1> [#uses=0]
+ %45 = fcmp olt float %43, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %45, label %bb2277, label %bb2274
+
+bb2274: ; preds = %bb2265
+ %46 = fcmp ogt float %43, 6.553500e+04 ; <i1> [#uses=0]
+ br label %bb2277
+
+bb2277: ; preds = %bb2274, %bb2265
+ %f1582.0 = phi float [ 0.000000e+00, %bb2265 ], [ %43, %bb2274 ] ; <float> [#uses=1]
+ %47 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1]
+ %48 = fptosi float %f1582.0 to i32 ; <i32> [#uses=1]
+ %49 = getelementptr float* %36, i32 2 ; <float*> [#uses=1]
+ %50 = load float* %49, align 4 ; <float> [#uses=1]
+ %51 = getelementptr float* %36, i32 3 ; <float*> [#uses=1]
+ %52 = load float* %51, align 4 ; <float> [#uses=1]
+ %53 = fmul float %50, 6.553500e+04 ; <float> [#uses=1]
+ %54 = fadd float %53, 5.000000e-01 ; <float> [#uses=1]
+ %55 = fmul float %52, 6.553500e+04 ; <float> [#uses=1]
+ %56 = fadd float %55, 5.000000e-01 ; <float> [#uses=1]
+ %57 = fcmp olt float %54, 0.000000e+00 ; <i1> [#uses=0]
+ %58 = fcmp olt float %56, 0.000000e+00 ; <i1> [#uses=0]
+ %59 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1]
+ %60 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1]
+ %61 = zext i32 %47 to i64 ; <i64> [#uses=1]
+ %62 = shl i64 %61, 48 ; <i64> [#uses=1]
+ %63 = zext i32 %48 to i64 ; <i64> [#uses=1]
+ %64 = shl i64 %63, 32 ; <i64> [#uses=1]
+ %65 = sext i32 %59 to i64 ; <i64> [#uses=1]
+ %66 = shl i64 %65, 16 ; <i64> [#uses=1]
+ %67 = sext i32 %60 to i64 ; <i64> [#uses=1]
+ %68 = or i64 %64, %62 ; <i64> [#uses=1]
+ %69 = or i64 %68, %66 ; <i64> [#uses=1]
+ %70 = or i64 %69, %67 ; <i64> [#uses=2]
+ %71 = getelementptr i8* null, i32 0 ; <i8*> [#uses=1]
+ %72 = bitcast i8* %71 to float* ; <float*> [#uses=4]
+ %73 = load float* %72, align 4 ; <float> [#uses=1]
+ %74 = getelementptr float* %72, i32 1 ; <float*> [#uses=1]
+ %75 = load float* %74, align 4 ; <float> [#uses=1]
+ %76 = fmul float %73, 6.553500e+04 ; <float> [#uses=1]
+ %77 = fadd float %76, 5.000000e-01 ; <float> [#uses=3]
+ %78 = fmul float %75, 6.553500e+04 ; <float> [#uses=1]
+ %79 = fadd float %78, 5.000000e-01 ; <float> [#uses=1]
+ %80 = fcmp olt float %77, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %80, label %bb2295, label %bb2292
+
+bb2292: ; preds = %bb2277
+ %81 = fcmp ogt float %77, 6.553500e+04 ; <i1> [#uses=1]
+ br i1 %81, label %bb2294, label %bb2295
+
+bb2294: ; preds = %bb2292
+ br label %bb2295
+
+bb2295: ; preds = %bb2294, %bb2292, %bb2277
+ %f0569.0 = phi float [ 6.553500e+04, %bb2294 ], [ 0.000000e+00, %bb2277 ], [ %77, %bb2292 ] ; <float> [#uses=1]
+ %82 = fcmp olt float %79, 0.000000e+00 ; <i1> [#uses=0]
+ %83 = fptosi float %f0569.0 to i32 ; <i32> [#uses=1]
+ %84 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1]
+ %85 = getelementptr float* %72, i32 2 ; <float*> [#uses=1]
+ %86 = load float* %85, align 4 ; <float> [#uses=1]
+ %87 = getelementptr float* %72, i32 3 ; <float*> [#uses=1]
+ %88 = load float* %87, align 4 ; <float> [#uses=1]
+ %89 = fmul float %86, 6.553500e+04 ; <float> [#uses=1]
+ %90 = fadd float %89, 5.000000e-01 ; <float> [#uses=1]
+ %91 = fmul float %88, 6.553500e+04 ; <float> [#uses=1]
+ %92 = fadd float %91, 5.000000e-01 ; <float> [#uses=1]
+ %93 = fcmp olt float %90, 0.000000e+00 ; <i1> [#uses=0]
+ %94 = fcmp olt float %92, 0.000000e+00 ; <i1> [#uses=0]
+ %95 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1]
+ %96 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1]
+ %97 = zext i32 %83 to i64 ; <i64> [#uses=1]
+ %98 = shl i64 %97, 48 ; <i64> [#uses=1]
+ %99 = zext i32 %84 to i64 ; <i64> [#uses=1]
+ %100 = shl i64 %99, 32 ; <i64> [#uses=1]
+ %101 = sext i32 %95 to i64 ; <i64> [#uses=1]
+ %102 = shl i64 %101, 16 ; <i64> [#uses=1]
+ %103 = sext i32 %96 to i64 ; <i64> [#uses=1]
+ %104 = or i64 %100, %98 ; <i64> [#uses=1]
+ %105 = or i64 %104, %102 ; <i64> [#uses=1]
+ %106 = or i64 %105, %103 ; <i64> [#uses=2]
+ %107 = shl i64 %70, 16 ; <i64> [#uses=1]
+ %108 = and i64 %107, 4294901760 ; <i64> [#uses=1]
+ %109 = and i64 %106, 65535 ; <i64> [#uses=1]
+ %110 = or i64 %34, %32 ; <i64> [#uses=1]
+ %111 = or i64 %110, %108 ; <i64> [#uses=1]
+ %112 = or i64 %111, %109 ; <i64> [#uses=1]
+ store i64 %70, i64* %4, align 16
+ store i64 %106, i64* %5, align 8
+ %113 = icmp eq i64 %112, 0 ; <i1> [#uses=1]
+ br i1 %113, label %bb2325, label %bb2315
+
+bb2315: ; preds = %bb2295
+ %114 = icmp eq %struct.xx_t* %159, null ; <i1> [#uses=1]
+ br i1 %114, label %bb2318, label %bb2317
+
+bb2317: ; preds = %bb2315
+ %115 = load i64* %2, align 16 ; <i64> [#uses=1]
+ %116 = call i32 (...)* @_u16a_cm( i64 %115, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=1]
+ %117 = sext i32 %116 to i64 ; <i64> [#uses=1]
+ store i64 %117, i64* %2, align 16
+ %118 = load i64* %3, align 8 ; <i64> [#uses=1]
+ %119 = call i32 (...)* @_u16a_cm( i64 %118, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=1]
+ %120 = sext i32 %119 to i64 ; <i64> [#uses=1]
+ store i64 %120, i64* %3, align 8
+ %121 = load i64* %4, align 16 ; <i64> [#uses=1]
+ %122 = call i32 (...)* @_u16a_cm( i64 %121, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=1]
+ %123 = sext i32 %122 to i64 ; <i64> [#uses=1]
+ store i64 %123, i64* %4, align 16
+ %124 = load i64* %5, align 8 ; <i64> [#uses=1]
+ %125 = call i32 (...)* @_u16a_cm( i64 %124, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=0]
+ unreachable
+
+bb2318: ; preds = %bb2315
+ %126 = getelementptr %struct.CGLSI* %src, i32 %indvar5021, i32 8 ; <%struct.vv_t*> [#uses=1]
+ %127 = bitcast %struct.vv_t* %126 to i64* ; <i64*> [#uses=1]
+ %128 = load i64* %127, align 8 ; <i64> [#uses=1]
+ %129 = trunc i64 %128 to i32 ; <i32> [#uses=4]
+ %130 = load i64* %2, align 16 ; <i64> [#uses=1]
+ %131 = call i32 (...)* @_u16_ff( i64 %130, i32 %129 ) nounwind ; <i32> [#uses=1]
+ %132 = sext i32 %131 to i64 ; <i64> [#uses=1]
+ store i64 %132, i64* %2, align 16
+ %133 = load i64* %3, align 8 ; <i64> [#uses=1]
+ %134 = call i32 (...)* @_u16_ff( i64 %133, i32 %129 ) nounwind ; <i32> [#uses=1]
+ %135 = sext i32 %134 to i64 ; <i64> [#uses=1]
+ store i64 %135, i64* %3, align 8
+ %136 = load i64* %4, align 16 ; <i64> [#uses=1]
+ %137 = call i32 (...)* @_u16_ff( i64 %136, i32 %129 ) nounwind ; <i32> [#uses=1]
+ %138 = sext i32 %137 to i64 ; <i64> [#uses=1]
+ store i64 %138, i64* %4, align 16
+ %139 = load i64* %5, align 8 ; <i64> [#uses=1]
+ %140 = call i32 (...)* @_u16_ff( i64 %139, i32 %129 ) nounwind ; <i32> [#uses=0]
+ unreachable
+
+bb2319: ; preds = %bb2326
+ %141 = getelementptr %struct.CGLSI* %src, i32 %indvar5021, i32 2 ; <i8**> [#uses=1]
+ %142 = load i8** %141, align 4 ; <i8*> [#uses=4]
+ %143 = getelementptr i8* %142, i32 0 ; <i8*> [#uses=1]
+ %144 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %143 ) nounwind ; <i32> [#uses=1]
+ %145 = sext i32 %144 to i64 ; <i64> [#uses=2]
+ %146 = getelementptr i8* %142, i32 0 ; <i8*> [#uses=1]
+ %147 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %146 ) nounwind ; <i32> [#uses=1]
+ %148 = sext i32 %147 to i64 ; <i64> [#uses=2]
+ %149 = shl i64 %145, 48 ; <i64> [#uses=0]
+ %150 = shl i64 %148, 32 ; <i64> [#uses=1]
+ %151 = and i64 %150, 281470681743360 ; <i64> [#uses=0]
+ store i64 %145, i64* %2, align 16
+ store i64 %148, i64* %3, align 8
+ %152 = getelementptr i8* %142, i32 0 ; <i8*> [#uses=1]
+ %153 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %152 ) nounwind ; <i32> [#uses=1]
+ %154 = sext i32 %153 to i64 ; <i64> [#uses=0]
+ %155 = getelementptr i8* %142, i32 0 ; <i8*> [#uses=1]
+ %156 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %155 ) nounwind ; <i32> [#uses=0]
+ unreachable
+
+bb2325: ; preds = %bb2326, %bb2295
+ %indvar.next5145 = add i32 %indvar5021, 1 ; <i32> [#uses=1]
+ br label %bb2326
+
+bb2326: ; preds = %bb2325, %bb.nph4945
+ %indvar5021 = phi i32 [ 0, %bb.nph4945 ], [ %indvar.next5145, %bb2325 ] ; <i32> [#uses=6]
+ %157 = icmp slt i32 %indvar5021, %n ; <i1> [#uses=0]
+ %158 = getelementptr %struct.CGLSI* %src, i32 %indvar5021, i32 10 ; <%struct.xx_t**> [#uses=1]
+ %159 = load %struct.xx_t** %158, align 4 ; <%struct.xx_t*> [#uses=5]
+ %160 = getelementptr %struct.CGLSI* %src, i32 %indvar5021, i32 1 ; <i32*> [#uses=1]
+ %161 = load i32* %160, align 4 ; <i32> [#uses=1]
+ %162 = and i32 %161, 255 ; <i32> [#uses=1]
+ switch i32 %162, label %bb2325 [
+ i32 59, label %bb2217
+ i32 60, label %bb2319
+ ]
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i32 @_u16_ff(...)
+
+declare i32 @_u16a_cm(...)
+
+declare i32 @_u16_sf32(...)
diff --git a/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll b/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll
new file mode 100644
index 0000000..91c36ef
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+; XFAIL: *
+; PR2356
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin9"
+
+define i32 @test(i64 %x, i32* %p) nounwind {
+ %asmtmp = call i32 asm "", "=r,0"(i64 0) nounwind ; <i32> [#uses=0]
+ %y = add i32 %asmtmp, 1
+ ret i32 %y
+}
diff --git a/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll b/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll
new file mode 100644
index 0000000..f474a6d
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=ppc64
+
+define void @__divtc3({ ppc_fp128, ppc_fp128 }* noalias sret %agg.result, ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind {
+entry:
+ %imag59 = load ppc_fp128* null, align 8 ; <ppc_fp128> [#uses=1]
+ %0 = fmul ppc_fp128 0xM00000000000000000000000000000000, %imag59 ; <ppc_fp128> [#uses=1]
+ %1 = fmul ppc_fp128 0xM00000000000000000000000000000000, 0xM00000000000000000000000000000000 ; <ppc_fp128> [#uses=1]
+ %2 = fadd ppc_fp128 %0, %1 ; <ppc_fp128> [#uses=1]
+ store ppc_fp128 %2, ppc_fp128* null, align 16
+ unreachable
+}
diff --git a/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll b/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
new file mode 100644
index 0000000..f4c06fb
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=ppc32 -o - | not grep fixunstfsi
+
+define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
+entry:
+ %0 = fcmp olt ppc_fp128 %a, 0xM00000000000000000000000000000000 ; <i1> [#uses=1]
+ br i1 %0, label %bb5, label %bb1
+
+bb1: ; preds = %entry
+ %1 = fmul ppc_fp128 %a, 0xM3DF00000000000000000000000000000 ; <ppc_fp128> [#uses=1]
+ %2 = fptoui ppc_fp128 %1 to i32 ; <i32> [#uses=1]
+ %3 = zext i32 %2 to i64 ; <i64> [#uses=1]
+ %4 = shl i64 %3, 32 ; <i64> [#uses=3]
+ %5 = uitofp i64 %4 to ppc_fp128 ; <ppc_fp128> [#uses=1]
+ %6 = fsub ppc_fp128 %a, %5 ; <ppc_fp128> [#uses=3]
+ %7 = fcmp olt ppc_fp128 %6, 0xM00000000000000000000000000000000 ; <i1> [#uses=1]
+ br i1 %7, label %bb2, label %bb3
+
+bb2: ; preds = %bb1
+ %8 = fsub ppc_fp128 0xM80000000000000000000000000000000, %6 ; <ppc_fp128> [#uses=1]
+ %9 = fptoui ppc_fp128 %8 to i32 ; <i32> [#uses=1]
+ %10 = zext i32 %9 to i64 ; <i64> [#uses=1]
+ %11 = sub i64 %4, %10 ; <i64> [#uses=1]
+ ret i64 %11
+
+bb3: ; preds = %bb1
+ %12 = fptoui ppc_fp128 %6 to i32 ; <i32> [#uses=1]
+ %13 = zext i32 %12 to i64 ; <i64> [#uses=1]
+ %14 = or i64 %13, %4 ; <i64> [#uses=1]
+ ret i64 %14
+
+bb5: ; preds = %entry
+ ret i64 0
+}
diff --git a/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll b/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll
new file mode 100644
index 0000000..83f3f6f
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=ppc32
+; PR2986
+@argc = external global i32 ; <i32*> [#uses=1]
+@buffer = external global [32 x i8], align 4 ; <[32 x i8]*> [#uses=1]
+
+define void @test1() nounwind noinline {
+entry:
+ %0 = load i32* @argc, align 4 ; <i32> [#uses=1]
+ %1 = trunc i32 %0 to i8 ; <i8> [#uses=1]
+ tail call void @llvm.memset.i32(i8* getelementptr ([32 x i8]* @buffer, i32 0, i32 0), i8 %1, i32 17, i32 4)
+ unreachable
+}
+
+declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind
diff --git a/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll b/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll
new file mode 100644
index 0000000..20683b9
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s
+; PR2988
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin10.0"
+@a = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 ; <ppc_fp128*> [#uses=2]
+@b = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 ; <ppc_fp128*> [#uses=2]
+@c = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 ; <ppc_fp128*> [#uses=3]
+@d = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 ; <ppc_fp128*> [#uses=2]
+
+define void @foo() nounwind {
+entry:
+ %0 = load ppc_fp128* @a, align 16 ; <ppc_fp128> [#uses=1]
+ %1 = call ppc_fp128 @llvm.sqrt.ppcf128(ppc_fp128 %0) ; <ppc_fp128> [#uses=1]
+ store ppc_fp128 %1, ppc_fp128* @a, align 16
+ %2 = load ppc_fp128* @b, align 16 ; <ppc_fp128> [#uses=1]
+ %3 = call ppc_fp128 @"\01_sinl$LDBL128"(ppc_fp128 %2) nounwind readonly ; <ppc_fp128> [#uses=1]
+ store ppc_fp128 %3, ppc_fp128* @b, align 16
+ %4 = load ppc_fp128* @c, align 16 ; <ppc_fp128> [#uses=1]
+ %5 = call ppc_fp128 @"\01_cosl$LDBL128"(ppc_fp128 %4) nounwind readonly ; <ppc_fp128> [#uses=1]
+ store ppc_fp128 %5, ppc_fp128* @c, align 16
+ %6 = load ppc_fp128* @d, align 16 ; <ppc_fp128> [#uses=1]
+ %7 = load ppc_fp128* @c, align 16 ; <ppc_fp128> [#uses=1]
+ %8 = call ppc_fp128 @llvm.pow.ppcf128(ppc_fp128 %6, ppc_fp128 %7) ; <ppc_fp128> [#uses=1]
+ store ppc_fp128 %8, ppc_fp128* @d, align 16
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare ppc_fp128 @llvm.sqrt.ppcf128(ppc_fp128) nounwind readonly
+
+declare ppc_fp128 @"\01_sinl$LDBL128"(ppc_fp128) nounwind readonly
+
+declare ppc_fp128 @"\01_cosl$LDBL128"(ppc_fp128) nounwind readonly
+
+declare ppc_fp128 @llvm.pow.ppcf128(ppc_fp128, ppc_fp128) nounwind readonly
diff --git a/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll b/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll
new file mode 100644
index 0000000..9ed7f6f
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -mtriple=powerpc64-apple-darwin9.5
+
+define void @__multc3({ ppc_fp128, ppc_fp128 }* noalias sret %agg.result, ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind {
+entry:
+ %.pre139 = and i1 false, false ; <i1> [#uses=1]
+ br i1 false, label %bb6, label %bb21
+
+bb6: ; preds = %entry
+ %0 = tail call ppc_fp128 @copysignl(ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128 %a) nounwind readnone ; <ppc_fp128> [#uses=0]
+ %iftmp.1.0 = select i1 %.pre139, ppc_fp128 0xM3FF00000000000000000000000000000, ppc_fp128 0xM00000000000000000000000000000000 ; <ppc_fp128> [#uses=1]
+ %1 = tail call ppc_fp128 @copysignl(ppc_fp128 %iftmp.1.0, ppc_fp128 %b) nounwind readnone ; <ppc_fp128> [#uses=0]
+ unreachable
+
+bb21: ; preds = %entry
+ unreachable
+}
+
+declare ppc_fp128 @copysignl(ppc_fp128, ppc_fp128) nounwind readnone
diff --git a/test/CodeGen/PowerPC/2008-12-12-EH.ll b/test/CodeGen/PowerPC/2008-12-12-EH.ll
new file mode 100644
index 0000000..2315e36
--- /dev/null
+++ b/test/CodeGen/PowerPC/2008-12-12-EH.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin9 | grep ^__Z1fv.eh
+
+define void @_Z1fv() {
+entry:
+ br label %return
+
+return:
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll b/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll
new file mode 100644
index 0000000..d49d58d
--- /dev/null
+++ b/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin9.5
+; rdar://6499616
+
+ %llvm.dbg.anchor.type = type { i32, i32 }
+ %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8* }
[email protected]_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 } ; <%llvm.dbg.anchor.type*> [#uses=1]
[email protected] = internal constant [11 x i8] c"testcase.c\00" ; <[11 x i8]*> [#uses=1]
[email protected] = internal constant [30 x i8] c"/Volumes/SandBox/NightlyTest/\00" ; <[30 x i8]*> [#uses=1]
[email protected] = internal constant [57 x i8] c"4.2.1 (Based on Apple Inc. build 5628) (LLVM build 9999)\00" ; <[57 x i8]*> [#uses=1]
[email protected]_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([11 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([30 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([57 x i8]* @.str2, i32 0, i32 0) } ; <%llvm.dbg.compile_unit.type*> [#uses=0]
+@"\01LC" = internal constant [13 x i8] c"conftest.val\00" ; <[13 x i8]*> [#uses=1]
+
+define i32 @main() nounwind {
+entry:
+ %0 = call i8* @fopen(i8* getelementptr ([13 x i8]* @"\01LC", i32 0, i32 0), i8* null) nounwind ; <i8*> [#uses=0]
+ unreachable
+}
+
+declare i8* @fopen(i8*, i8*)
diff --git a/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll b/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll
new file mode 100644
index 0000000..172531e
--- /dev/null
+++ b/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin10
+; rdar://6692215
+
+define fastcc void @_qsort(i8* %a, i32 %n, i32 %es, i32 (i8*, i8*)* %cmp, i32 %depth_limit) nounwind optsize ssp {
+entry:
+ br i1 false, label %bb21, label %bb20.loopexit
+
+bb20.loopexit: ; preds = %entry
+ ret void
+
+bb21: ; preds = %entry
+ %0 = getelementptr i8* %a, i32 0 ; <i8*> [#uses=2]
+ br label %bb35
+
+bb29: ; preds = %bb35
+ br i1 false, label %bb7.i252, label %bb34
+
+bb7.i252: ; preds = %bb7.i252, %bb29
+ %pj.0.rec.i247 = phi i32 [ %indvar.next488, %bb7.i252 ], [ 0, %bb29 ] ; <i32> [#uses=2]
+ %pi.0.i248 = getelementptr i8* %pa.1, i32 %pj.0.rec.i247 ; <i8*> [#uses=0]
+ %indvar.next488 = add i32 %pj.0.rec.i247, 1 ; <i32> [#uses=1]
+ br i1 false, label %bb34, label %bb7.i252
+
+bb34: ; preds = %bb7.i252, %bb29
+ %indvar.next505 = add i32 %indvar504, 1 ; <i32> [#uses=1]
+ br label %bb35
+
+bb35: ; preds = %bb34, %bb21
+ %indvar504 = phi i32 [ %indvar.next505, %bb34 ], [ 0, %bb21 ] ; <i32> [#uses=2]
+ %pa.1 = phi i8* [ null, %bb34 ], [ %0, %bb21 ] ; <i8*> [#uses=2]
+ %pb.0.rec = mul i32 %indvar504, %es ; <i32> [#uses=1]
+ br i1 false, label %bb43, label %bb29
+
+bb43: ; preds = %bb43, %bb35
+ br i1 false, label %bb50, label %bb43
+
+bb50: ; preds = %bb43
+ %1 = ptrtoint i8* %pa.1 to i32 ; <i32> [#uses=1]
+ %2 = sub i32 %1, 0 ; <i32> [#uses=2]
+ %3 = icmp sle i32 0, %2 ; <i1> [#uses=1]
+ %min = select i1 %3, i32 0, i32 %2 ; <i32> [#uses=1]
+ br label %bb7.i161
+
+bb7.i161: ; preds = %bb7.i161, %bb50
+ %pj.0.rec.i156 = phi i32 [ %indvar.next394, %bb7.i161 ], [ 0, %bb50 ] ; <i32> [#uses=2]
+ %.sum279 = sub i32 %pj.0.rec.i156, %min ; <i32> [#uses=1]
+ %pb.0.sum542 = add i32 %pb.0.rec, %.sum279 ; <i32> [#uses=1]
+ %pj.0.i158 = getelementptr i8* %0, i32 %pb.0.sum542 ; <i8*> [#uses=0]
+ %indvar.next394 = add i32 %pj.0.rec.i156, 1 ; <i32> [#uses=1]
+ br label %bb7.i161
+}
diff --git a/test/CodeGen/PowerPC/2009-05-28-LegalizeBRCC.ll b/test/CodeGen/PowerPC/2009-05-28-LegalizeBRCC.ll
new file mode 100644
index 0000000..29d115d
--- /dev/null
+++ b/test/CodeGen/PowerPC/2009-05-28-LegalizeBRCC.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin10
+; PR4280
+
+define i32 @__fixunssfsi(float %a) nounwind readnone {
+entry:
+ %0 = fcmp ult float %a, 0x41E0000000000000 ; <i1> [#uses=1]
+ br i1 %0, label %bb1, label %bb
+
+bb: ; preds = %entry
+ ret i32 1
+
+bb1: ; preds = %entry
+ ret i32 0
+}
+
diff --git a/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll b/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll
new file mode 100644
index 0000000..f64e3dc
--- /dev/null
+++ b/test/CodeGen/PowerPC/2009-07-16-InlineAsm-M-Operand.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=ppc32 -verify-machineinstrs
+
+; Machine code verifier will call isRegTiedToDefOperand() on /all/ register use
+; operands. We must make sure that the operand flag is found correctly.
+
+; This test case is actually not specific to PowerPC, but the (imm, reg) format
+; of PowerPC "m" operands trigger this bug.
+
+define void @memory_asm_operand(i32 %a) {
+ ; "m" operand will be represented as:
+ ; INLINEASM <es:fake $0>, 10, %R2, 20, -4, %R1
+ ; It is difficult to find the flag operand (20) when starting from %R1
+ call i32 asm "lbzx $0, $1", "=r,m" (i32 %a)
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll b/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
new file mode 100644
index 0000000..5d09696
--- /dev/null
+++ b/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=ppc32 | FileCheck %s
+; ModuleID = '<stdin>'
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin10.0"
+; It is wrong on powerpc to substitute reg+reg for $0; the stw opcode
+; would have to change.
+
+@x = external global [0 x i32] ; <[0 x i32]*> [#uses=1]
+
+define void @foo(i32 %y) nounwind ssp {
+entry:
+; CHECK: foo
+; CHECK: add r2
+; CHECK: 0(r2)
+ %y_addr = alloca i32 ; <i32*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %y, i32* %y_addr
+ %0 = load i32* %y_addr, align 4 ; <i32> [#uses=1]
+ %1 = getelementptr inbounds [0 x i32]* @x, i32 0, i32 %0 ; <i32*> [#uses=1]
+ call void asm sideeffect "isync\0A\09eieio\0A\09stw $1, $0", "=*o,r,~{memory}"(i32* %1, i32 0) nounwind
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll b/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll
new file mode 100644
index 0000000..12c4c99
--- /dev/null
+++ b/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=ppc32 -mtriple=ppc-apple-darwin | FileCheck %s
+
+; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm'
+
+@"\01l_objc_msgSend_fixup_alloc" = linker_private hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16 ; <i32*> [#uses=0]
+
+; CHECK: .globl l_objc_msgSend_fixup_alloc
+; CHECK: .weak_definition l_objc_msgSend_fixup_alloc
diff --git a/test/CodeGen/PowerPC/2009-09-18-carrybit.ll b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
new file mode 100644
index 0000000..6c23a61
--- /dev/null
+++ b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
@@ -0,0 +1,62 @@
+; RUN: llc -march=ppc32 < %s | FileCheck %s
+; ModuleID = '<stdin>'
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin9.6"
+
+define i64 @foo(i64 %r.0.ph, i64 %q.0.ph, i32 %sr1.1.ph) nounwind {
+entry:
+; CHECK: foo:
+; CHECK: subfc
+; CHECK: subfe
+; CHECK: subfc
+; CHECK: subfe
+ %tmp0 = add i64 %r.0.ph, -1 ; <i64> [#uses=1]
+ br label %bb40
+
+bb40: ; preds = %bb40, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb40 ] ; <i32> [#uses=1]
+ %carry.0274 = phi i32 [ 0, %entry ], [%tmp122, %bb40 ] ; <i32> [#uses=1]
+ %r.0273 = phi i64 [ %r.0.ph, %entry ], [ %tmp124, %bb40 ] ; <i64> [#uses=2]
+ %q.0272 = phi i64 [ %q.0.ph, %entry ], [ %ins169, %bb40 ] ; <i64> [#uses=3]
+ %tmp1 = lshr i64 %r.0273, 31 ; <i64> [#uses=1]
+ %tmp2 = trunc i64 %tmp1 to i32 ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp2, -2 ; <i32> [#uses=1]
+ %tmp213 = trunc i64 %r.0273 to i32 ; <i32> [#uses=2]
+ %tmp106 = lshr i32 %tmp213, 31 ; <i32> [#uses=1]
+ %tmp107 = or i32 %tmp3, %tmp106 ; <i32> [#uses=1]
+ %tmp215 = zext i32 %tmp107 to i64 ; <i64> [#uses=1]
+ %tmp216 = shl i64 %tmp215, 32 ; <i64> [#uses=1]
+ %tmp108 = shl i32 %tmp213, 1 ; <i32> [#uses=1]
+ %tmp109 = lshr i64 %q.0272, 63 ; <i64> [#uses=1]
+ %tmp110 = trunc i64 %tmp109 to i32 ; <i32> [#uses=1]
+ %tmp111 = or i32 %tmp108, %tmp110 ; <i32> [#uses=1]
+ %tmp222 = zext i32 %tmp111 to i64 ; <i64> [#uses=1]
+ %ins224 = or i64 %tmp216, %tmp222 ; <i64> [#uses=2]
+ %tmp112 = lshr i64 %q.0272, 31 ; <i64> [#uses=1]
+ %tmp113 = trunc i64 %tmp112 to i32 ; <i32> [#uses=1]
+ %tmp114 = and i32 %tmp113, -2 ; <i32> [#uses=1]
+ %tmp158 = trunc i64 %q.0272 to i32 ; <i32> [#uses=2]
+ %tmp115 = lshr i32 %tmp158, 31 ; <i32> [#uses=1]
+ %tmp116 = or i32 %tmp114, %tmp115 ; <i32> [#uses=1]
+ %tmp160 = zext i32 %tmp116 to i64 ; <i64> [#uses=1]
+ %tmp161 = shl i64 %tmp160, 32 ; <i64> [#uses=1]
+ %tmp117 = shl i32 %tmp158, 1 ; <i32> [#uses=1]
+ %tmp118 = or i32 %tmp117, %carry.0274 ; <i32> [#uses=1]
+ %tmp167 = zext i32 %tmp118 to i64 ; <i64> [#uses=1]
+ %ins169 = or i64 %tmp161, %tmp167 ; <i64> [#uses=2]
+ %tmp119 = sub i64 %tmp0, %ins224 ; <i64> [#uses=1]
+ %tmp120 = ashr i64 %tmp119, 63 ; <i64> [#uses=2]
+ %tmp121 = trunc i64 %tmp120 to i32 ; <i32> [#uses=1]
+ %tmp122 = and i32 %tmp121, 1 ; <i32> [#uses=2]
+ %tmp123 = and i64 %tmp120, %q.0.ph ; <i64> [#uses=1]
+ %tmp124 = sub i64 %ins224, %tmp123 ; <i64> [#uses=2]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %sr1.1.ph ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb41.bb42_crit_edge, label %bb40
+
+bb41.bb42_crit_edge: ; preds = %bb40
+ %phitmp278 = zext i32 %tmp122 to i64 ; <i64> [#uses=1]
+ %tmp125 = shl i64 %ins169, 1 ; <i64> [#uses=1]
+ %tmp126 = or i64 %phitmp278, %tmp125 ; <i64> [#uses=2]
+ ret i64 %tmp126
+}
diff --git a/test/CodeGen/PowerPC/2009-11-15-ProcImpDefsBug.ll b/test/CodeGen/PowerPC/2009-11-15-ProcImpDefsBug.ll
new file mode 100644
index 0000000..2d9d16a
--- /dev/null
+++ b/test/CodeGen/PowerPC/2009-11-15-ProcImpDefsBug.ll
@@ -0,0 +1,105 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin8
+
+define void @gcov_exit() nounwind {
+entry:
+ br i1 undef, label %return, label %bb.nph341
+
+bb.nph341: ; preds = %entry
+ br label %bb25
+
+bb25: ; preds = %read_fatal, %bb.nph341
+ br i1 undef, label %bb49.1, label %bb48
+
+bb48: ; preds = %bb25
+ br label %bb49.1
+
+bb51: ; preds = %bb48.4, %bb49.3
+ switch i32 undef, label %bb58 [
+ i32 0, label %rewrite
+ i32 1734567009, label %bb59
+ ]
+
+bb58: ; preds = %bb51
+ br label %read_fatal
+
+bb59: ; preds = %bb51
+ br i1 undef, label %bb60, label %bb3.i156
+
+bb3.i156: ; preds = %bb59
+ br label %read_fatal
+
+bb60: ; preds = %bb59
+ br i1 undef, label %bb78.preheader, label %rewrite
+
+bb78.preheader: ; preds = %bb60
+ br i1 undef, label %bb62, label %bb80
+
+bb62: ; preds = %bb78.preheader
+ br i1 undef, label %bb64, label %read_mismatch
+
+bb64: ; preds = %bb62
+ br i1 undef, label %bb65, label %read_mismatch
+
+bb65: ; preds = %bb64
+ br i1 undef, label %bb75, label %read_mismatch
+
+read_mismatch: ; preds = %bb98, %bb119.preheader, %bb72, %bb71, %bb65, %bb64, %bb62
+ br label %read_fatal
+
+bb71: ; preds = %bb75
+ br i1 undef, label %bb72, label %read_mismatch
+
+bb72: ; preds = %bb71
+ br i1 undef, label %bb73, label %read_mismatch
+
+bb73: ; preds = %bb72
+ unreachable
+
+bb74: ; preds = %bb75
+ br label %bb75
+
+bb75: ; preds = %bb74, %bb65
+ br i1 undef, label %bb74, label %bb71
+
+bb80: ; preds = %bb78.preheader
+ unreachable
+
+read_fatal: ; preds = %read_mismatch, %bb3.i156, %bb58
+ br i1 undef, label %return, label %bb25
+
+rewrite: ; preds = %bb60, %bb51
+ br i1 undef, label %bb94, label %bb119.preheader
+
+bb94: ; preds = %rewrite
+ unreachable
+
+bb119.preheader: ; preds = %rewrite
+ br i1 undef, label %read_mismatch, label %bb98
+
+bb98: ; preds = %bb119.preheader
+ br label %read_mismatch
+
+return: ; preds = %read_fatal, %entry
+ ret void
+
+bb49.1: ; preds = %bb48, %bb25
+ br i1 undef, label %bb49.2, label %bb48.2
+
+bb49.2: ; preds = %bb48.2, %bb49.1
+ br i1 undef, label %bb49.3, label %bb48.3
+
+bb48.2: ; preds = %bb49.1
+ br label %bb49.2
+
+bb49.3: ; preds = %bb48.3, %bb49.2
+ %c_ix.0.3 = phi i32 [ undef, %bb48.3 ], [ undef, %bb49.2 ] ; <i32> [#uses=1]
+ br i1 undef, label %bb51, label %bb48.4
+
+bb48.3: ; preds = %bb49.2
+ store i64* undef, i64** undef, align 4
+ br label %bb49.3
+
+bb48.4: ; preds = %bb49.3
+ %0 = getelementptr inbounds [5 x i64*]* undef, i32 0, i32 %c_ix.0.3 ; <i64**> [#uses=0]
+ br label %bb51
+}
diff --git a/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll b/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll
new file mode 100644
index 0000000..54f4b2e
--- /dev/null
+++ b/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll
@@ -0,0 +1,155 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin8
+
+%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+%struct.__gcov_var = type { %struct.FILE*, i32, i32, i32, i32, i32, i32, [1025 x i32] }
+%struct.__sFILEX = type opaque
+%struct.__sbuf = type { i8*, i32 }
+%struct.gcov_ctr_info = type { i32, i64*, void (i64*, i32)* }
+%struct.gcov_ctr_summary = type { i32, i32, i64, i64, i64 }
+%struct.gcov_fn_info = type { i32, i32, [0 x i32] }
+%struct.gcov_info = type { i32, %struct.gcov_info*, i32, i8*, i32, %struct.gcov_fn_info*, i32, [0 x %struct.gcov_ctr_info] }
+%struct.gcov_summary = type { i32, [1 x %struct.gcov_ctr_summary] }
+
+@__gcov_var = external global %struct.__gcov_var ; <%struct.__gcov_var*> [#uses=1]
+@__sF = external global [0 x %struct.FILE] ; <[0 x %struct.FILE]*> [#uses=1]
[email protected] = external constant [56 x i8], align 4 ; <[56 x i8]*> [#uses=1]
+@gcov_list = external global %struct.gcov_info* ; <%struct.gcov_info**> [#uses=1]
[email protected] = external constant [35 x i8], align 4 ; <[35 x i8]*> [#uses=1]
[email protected] = external constant [9 x i8], align 4 ; <[9 x i8]*> [#uses=1]
[email protected] = external constant [10 x i8], align 4 ; <[10 x i8]*> [#uses=1]
[email protected] = external constant [36 x i8], align 4 ; <[36 x i8]*> [#uses=1]
+
+declare i32 @"\01_fprintf$LDBL128"(%struct.FILE*, i8*, ...) nounwind
+
+define void @gcov_exit() nounwind {
+entry:
+ %gi_ptr.0357 = load %struct.gcov_info** @gcov_list, align 4 ; <%struct.gcov_info*> [#uses=1]
+ %0 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=3]
+ br i1 undef, label %return, label %bb.nph341
+
+bb.nph341: ; preds = %entry
+ %object27 = bitcast %struct.gcov_summary* undef to i8* ; <i8*> [#uses=1]
+ br label %bb25
+
+bb25: ; preds = %read_fatal, %bb.nph341
+ %gi_ptr.1329 = phi %struct.gcov_info* [ %gi_ptr.0357, %bb.nph341 ], [ undef, %read_fatal ] ; <%struct.gcov_info*> [#uses=1]
+ call void @llvm.memset.i32(i8* %object27, i8 0, i32 36, i32 8)
+ br i1 undef, label %bb49.1, label %bb48
+
+bb48: ; preds = %bb25
+ br label %bb49.1
+
+bb51: ; preds = %bb48.4, %bb49.3
+ switch i32 undef, label %bb58 [
+ i32 0, label %rewrite
+ i32 1734567009, label %bb59
+ ]
+
+bb58: ; preds = %bb51
+ %1 = call i32 (%struct.FILE*, i8*, ...)* @"\01_fprintf$LDBL128"(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE]* @__sF, i32 0, i32 2), i8* getelementptr inbounds ([35 x i8]* @.str7, i32 0, i32 0), i8* %0) nounwind ; <i32> [#uses=0]
+ br label %read_fatal
+
+bb59: ; preds = %bb51
+ br i1 undef, label %bb60, label %bb3.i156
+
+bb3.i156: ; preds = %bb59
+ store i8 52, i8* undef, align 1
+ store i8 42, i8* undef, align 1
+ %2 = call i32 (%struct.FILE*, i8*, ...)* @"\01_fprintf$LDBL128"(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE]* @__sF, i32 0, i32 2), i8* getelementptr inbounds ([56 x i8]* @.str, i32 0, i32 0), i8* %0, i8* undef, i8* undef) nounwind ; <i32> [#uses=0]
+ br label %read_fatal
+
+bb60: ; preds = %bb59
+ br i1 undef, label %bb78.preheader, label %rewrite
+
+bb78.preheader: ; preds = %bb60
+ br i1 undef, label %bb62, label %bb80
+
+bb62: ; preds = %bb78.preheader
+ br i1 undef, label %bb64, label %read_mismatch
+
+bb64: ; preds = %bb62
+ br i1 undef, label %bb65, label %read_mismatch
+
+bb65: ; preds = %bb64
+ br i1 undef, label %bb75, label %read_mismatch
+
+read_mismatch: ; preds = %bb98, %bb119.preheader, %bb72, %bb71, %bb65, %bb64, %bb62
+ %3 = icmp eq i32 undef, -1 ; <i1> [#uses=1]
+ %iftmp.11.0 = select i1 %3, i8* getelementptr inbounds ([10 x i8]* @.str9, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str8, i32 0, i32 0) ; <i8*> [#uses=1]
+ %4 = call i32 (%struct.FILE*, i8*, ...)* @"\01_fprintf$LDBL128"(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE]* @__sF, i32 0, i32 2), i8* getelementptr inbounds ([36 x i8]* @.str10, i32 0, i32 0), i8* %0, i8* %iftmp.11.0) nounwind ; <i32> [#uses=0]
+ br label %read_fatal
+
+bb71: ; preds = %bb75
+ %5 = load i32* undef, align 4 ; <i32> [#uses=1]
+ %6 = getelementptr inbounds %struct.gcov_info* %gi_ptr.1329, i32 0, i32 7, i32 undef, i32 2 ; <void (i64*, i32)**> [#uses=1]
+ %7 = load void (i64*, i32)** %6, align 4 ; <void (i64*, i32)*> [#uses=1]
+ %8 = call i32 @__gcov_read_unsigned() nounwind ; <i32> [#uses=1]
+ %9 = call i32 @__gcov_read_unsigned() nounwind ; <i32> [#uses=1]
+ %10 = icmp eq i32 %tmp386, %8 ; <i1> [#uses=1]
+ br i1 %10, label %bb72, label %read_mismatch
+
+bb72: ; preds = %bb71
+ %11 = icmp eq i32 undef, %9 ; <i1> [#uses=1]
+ br i1 %11, label %bb73, label %read_mismatch
+
+bb73: ; preds = %bb72
+ call void %7(i64* null, i32 %5) nounwind
+ unreachable
+
+bb74: ; preds = %bb75
+ %12 = add i32 %13, 1 ; <i32> [#uses=1]
+ br label %bb75
+
+bb75: ; preds = %bb74, %bb65
+ %13 = phi i32 [ %12, %bb74 ], [ 0, %bb65 ] ; <i32> [#uses=2]
+ %tmp386 = add i32 0, 27328512 ; <i32> [#uses=1]
+ %14 = shl i32 1, %13 ; <i32> [#uses=1]
+ %15 = load i32* undef, align 4 ; <i32> [#uses=1]
+ %16 = and i32 %15, %14 ; <i32> [#uses=1]
+ %17 = icmp eq i32 %16, 0 ; <i1> [#uses=1]
+ br i1 %17, label %bb74, label %bb71
+
+bb80: ; preds = %bb78.preheader
+ unreachable
+
+read_fatal: ; preds = %read_mismatch, %bb3.i156, %bb58
+ br i1 undef, label %return, label %bb25
+
+rewrite: ; preds = %bb60, %bb51
+ store i32 -1, i32* getelementptr inbounds (%struct.__gcov_var* @__gcov_var, i32 0, i32 6), align 4
+ br i1 undef, label %bb94, label %bb119.preheader
+
+bb94: ; preds = %rewrite
+ unreachable
+
+bb119.preheader: ; preds = %rewrite
+ br i1 undef, label %read_mismatch, label %bb98
+
+bb98: ; preds = %bb119.preheader
+ br label %read_mismatch
+
+return: ; preds = %read_fatal, %entry
+ ret void
+
+bb49.1: ; preds = %bb48, %bb25
+ br i1 undef, label %bb49.2, label %bb48.2
+
+bb49.2: ; preds = %bb48.2, %bb49.1
+ br i1 undef, label %bb49.3, label %bb48.3
+
+bb48.2: ; preds = %bb49.1
+ br label %bb49.2
+
+bb49.3: ; preds = %bb48.3, %bb49.2
+ br i1 undef, label %bb51, label %bb48.4
+
+bb48.3: ; preds = %bb49.2
+ br label %bb49.3
+
+bb48.4: ; preds = %bb49.3
+ br label %bb51
+}
+
+declare i32 @__gcov_read_unsigned() nounwind
+
+declare void @llvm.memset.i32(i8* nocapture, i8, i32, i32) nounwind
diff --git a/test/CodeGen/PowerPC/2009-11-25-ImpDefBug.ll b/test/CodeGen/PowerPC/2009-11-25-ImpDefBug.ll
new file mode 100644
index 0000000..9a22a6f
--- /dev/null
+++ b/test/CodeGen/PowerPC/2009-11-25-ImpDefBug.ll
@@ -0,0 +1,56 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin9.5 -mcpu=g5
+; rdar://7422268
+
+%struct..0EdgeT = type { i32, i32, float, float, i32, i32, i32, float, i32, i32 }
+
+define void @smooth_color_z_triangle(i32 %v0, i32 %v1, i32 %v2, i32 %pv) nounwind {
+entry:
+ br i1 undef, label %return, label %bb14
+
+bb14: ; preds = %entry
+ br i1 undef, label %bb15, label %return
+
+bb15: ; preds = %bb14
+ br i1 undef, label %bb16, label %bb17
+
+bb16: ; preds = %bb15
+ br label %bb17
+
+bb17: ; preds = %bb16, %bb15
+ %0 = fcmp olt float undef, 0.000000e+00 ; <i1> [#uses=2]
+ %eTop.eMaj = select i1 %0, %struct..0EdgeT* undef, %struct..0EdgeT* null ; <%struct..0EdgeT*> [#uses=1]
+ br label %bb69
+
+bb24: ; preds = %bb69
+ br i1 undef, label %bb25, label %bb28
+
+bb25: ; preds = %bb24
+ br label %bb33
+
+bb28: ; preds = %bb24
+ br i1 undef, label %return, label %bb32
+
+bb32: ; preds = %bb28
+ br i1 %0, label %bb38, label %bb33
+
+bb33: ; preds = %bb32, %bb25
+ br i1 undef, label %bb34, label %bb38
+
+bb34: ; preds = %bb33
+ br label %bb38
+
+bb38: ; preds = %bb34, %bb33, %bb32
+ %eRight.08 = phi %struct..0EdgeT* [ %eTop.eMaj, %bb32 ], [ undef, %bb34 ], [ undef, %bb33 ] ; <%struct..0EdgeT*> [#uses=0]
+ %fdgOuter.0 = phi i32 [ %fdgOuter.1, %bb32 ], [ undef, %bb34 ], [ %fdgOuter.1, %bb33 ] ; <i32> [#uses=1]
+ %fz.3 = phi i32 [ %fz.2, %bb32 ], [ 2147483647, %bb34 ], [ %fz.2, %bb33 ] ; <i32> [#uses=1]
+ %1 = add i32 undef, 1 ; <i32> [#uses=0]
+ br label %bb69
+
+bb69: ; preds = %bb38, %bb17
+ %fdgOuter.1 = phi i32 [ undef, %bb17 ], [ %fdgOuter.0, %bb38 ] ; <i32> [#uses=2]
+ %fz.2 = phi i32 [ undef, %bb17 ], [ %fz.3, %bb38 ] ; <i32> [#uses=2]
+ br i1 undef, label %bb24, label %return
+
+return: ; preds = %bb69, %bb28, %bb14, %entry
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll b/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll
new file mode 100644
index 0000000..32ddb34
--- /dev/null
+++ b/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin10 -relocation-model=pic -disable-fp-elim | FileCheck %s
+; <rdar://problem/7604010>
+
+%cmd.type = type { }
+
+@_cmd = constant %cmd.type zeroinitializer
+
+; CHECK: .globl __cmd
+; CHECK-NEXT: .align 3
+; CHECK-NEXT: __cmd:
+; CHECK-NEXT: .space 1
diff --git a/test/CodeGen/PowerPC/Atomics-32.ll b/test/CodeGen/PowerPC/Atomics-32.ll
new file mode 100644
index 0000000..03905a3
--- /dev/null
+++ b/test/CodeGen/PowerPC/Atomics-32.ll
@@ -0,0 +1,749 @@
+; RUN: llc < %s -march=ppc32
+; ModuleID = 'Atomics.c'
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin9"
+@sc = common global i8 0 ; <i8*> [#uses=52]
+@uc = common global i8 0 ; <i8*> [#uses=100]
+@ss = common global i16 0 ; <i16*> [#uses=15]
+@us = common global i16 0 ; <i16*> [#uses=15]
+@si = common global i32 0 ; <i32*> [#uses=15]
+@ui = common global i32 0 ; <i32*> [#uses=23]
+@sl = common global i32 0 ; <i32*> [#uses=15]
+@ul = common global i32 0 ; <i32*> [#uses=15]
+@sll = common global i64 0, align 8 ; <i64*> [#uses=1]
+@ull = common global i64 0, align 8 ; <i64*> [#uses=1]
+
+define void @test_op_ignore() nounwind {
+entry:
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:0 [#uses=0]
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:1 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 1 ) ; <i16>:3 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 1 ) ; <i16>:5 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 1 ) ; <i32>:7 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 1 ) ; <i32>:9 [#uses=0]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:10 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %10, i32 1 ) ; <i32>:11 [#uses=0]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:12 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %12, i32 1 ) ; <i32>:13 [#uses=0]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:14 [#uses=0]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:15 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:16 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 1 ) ; <i16>:17 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:18 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 1 ) ; <i16>:19 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:20 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 1 ) ; <i32>:21 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:22 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 1 ) ; <i32>:23 [#uses=0]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:24 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %24, i32 1 ) ; <i32>:25 [#uses=0]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:26 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %26, i32 1 ) ; <i32>:27 [#uses=0]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:28 [#uses=0]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:29 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:30 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 1 ) ; <i16>:31 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:32 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 1 ) ; <i16>:33 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:34 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 1 ) ; <i32>:35 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:36 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 1 ) ; <i32>:37 [#uses=0]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:38 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %38, i32 1 ) ; <i32>:39 [#uses=0]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:40 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %40, i32 1 ) ; <i32>:41 [#uses=0]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:42 [#uses=0]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:43 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:44 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 1 ) ; <i16>:45 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:46 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 1 ) ; <i16>:47 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:48 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 1 ) ; <i32>:49 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:50 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 1 ) ; <i32>:51 [#uses=0]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:52 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %52, i32 1 ) ; <i32>:53 [#uses=0]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:54 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %54, i32 1 ) ; <i32>:55 [#uses=0]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:56 [#uses=0]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:57 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:58 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 1 ) ; <i16>:59 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:60 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 1 ) ; <i16>:61 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:62 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 1 ) ; <i32>:63 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:64 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 1 ) ; <i32>:65 [#uses=0]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:66 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %66, i32 1 ) ; <i32>:67 [#uses=0]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:68 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %68, i32 1 ) ; <i32>:69 [#uses=0]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:70 [#uses=0]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:71 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:72 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 1 ) ; <i16>:73 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:74 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 1 ) ; <i16>:75 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:76 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 1 ) ; <i32>:77 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:78 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 1 ) ; <i32>:79 [#uses=0]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:80 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %80, i32 1 ) ; <i32>:81 [#uses=0]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:82 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %82, i32 1 ) ; <i32>:83 [#uses=0]
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.add.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind
+
+declare i8 @llvm.atomic.load.sub.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.sub.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind
+
+declare i8 @llvm.atomic.load.or.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.or.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind
+
+declare i8 @llvm.atomic.load.xor.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.xor.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind
+
+declare i8 @llvm.atomic.load.and.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.and.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind
+
+declare i8 @llvm.atomic.load.nand.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.nand.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.nand.i32.p0i32(i32*, i32) nounwind
+
+define void @test_fetch_and_op() nounwind {
+entry:
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:0 [#uses=1]
+ store i8 %0, i8* @sc, align 1
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:1 [#uses=1]
+ store i8 %1, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 11 ) ; <i16>:3 [#uses=1]
+ store i16 %3, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 11 ) ; <i16>:5 [#uses=1]
+ store i16 %5, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 11 ) ; <i32>:7 [#uses=1]
+ store i32 %7, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 11 ) ; <i32>:9 [#uses=1]
+ store i32 %9, i32* @ui, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:10 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %10, i32 11 ) ; <i32>:11 [#uses=1]
+ store i32 %11, i32* @sl, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:12 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %12, i32 11 ) ; <i32>:13 [#uses=1]
+ store i32 %13, i32* @ul, align 4
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:14 [#uses=1]
+ store i8 %14, i8* @sc, align 1
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:15 [#uses=1]
+ store i8 %15, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:16 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 11 ) ; <i16>:17 [#uses=1]
+ store i16 %17, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:18 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 11 ) ; <i16>:19 [#uses=1]
+ store i16 %19, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:20 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 11 ) ; <i32>:21 [#uses=1]
+ store i32 %21, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:22 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 11 ) ; <i32>:23 [#uses=1]
+ store i32 %23, i32* @ui, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:24 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %24, i32 11 ) ; <i32>:25 [#uses=1]
+ store i32 %25, i32* @sl, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:26 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %26, i32 11 ) ; <i32>:27 [#uses=1]
+ store i32 %27, i32* @ul, align 4
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:28 [#uses=1]
+ store i8 %28, i8* @sc, align 1
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:29 [#uses=1]
+ store i8 %29, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:30 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 11 ) ; <i16>:31 [#uses=1]
+ store i16 %31, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:32 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 11 ) ; <i16>:33 [#uses=1]
+ store i16 %33, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:34 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 11 ) ; <i32>:35 [#uses=1]
+ store i32 %35, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:36 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 11 ) ; <i32>:37 [#uses=1]
+ store i32 %37, i32* @ui, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:38 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %38, i32 11 ) ; <i32>:39 [#uses=1]
+ store i32 %39, i32* @sl, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:40 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %40, i32 11 ) ; <i32>:41 [#uses=1]
+ store i32 %41, i32* @ul, align 4
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:42 [#uses=1]
+ store i8 %42, i8* @sc, align 1
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:43 [#uses=1]
+ store i8 %43, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:44 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 11 ) ; <i16>:45 [#uses=1]
+ store i16 %45, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:46 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 11 ) ; <i16>:47 [#uses=1]
+ store i16 %47, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:48 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 11 ) ; <i32>:49 [#uses=1]
+ store i32 %49, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:50 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 11 ) ; <i32>:51 [#uses=1]
+ store i32 %51, i32* @ui, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:52 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %52, i32 11 ) ; <i32>:53 [#uses=1]
+ store i32 %53, i32* @sl, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:54 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %54, i32 11 ) ; <i32>:55 [#uses=1]
+ store i32 %55, i32* @ul, align 4
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:56 [#uses=1]
+ store i8 %56, i8* @sc, align 1
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:57 [#uses=1]
+ store i8 %57, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:58 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 11 ) ; <i16>:59 [#uses=1]
+ store i16 %59, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:60 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 11 ) ; <i16>:61 [#uses=1]
+ store i16 %61, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:62 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 11 ) ; <i32>:63 [#uses=1]
+ store i32 %63, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:64 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 11 ) ; <i32>:65 [#uses=1]
+ store i32 %65, i32* @ui, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:66 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %66, i32 11 ) ; <i32>:67 [#uses=1]
+ store i32 %67, i32* @sl, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:68 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %68, i32 11 ) ; <i32>:69 [#uses=1]
+ store i32 %69, i32* @ul, align 4
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:70 [#uses=1]
+ store i8 %70, i8* @sc, align 1
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:71 [#uses=1]
+ store i8 %71, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:72 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 11 ) ; <i16>:73 [#uses=1]
+ store i16 %73, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:74 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 11 ) ; <i16>:75 [#uses=1]
+ store i16 %75, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:76 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 11 ) ; <i32>:77 [#uses=1]
+ store i32 %77, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:78 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 11 ) ; <i32>:79 [#uses=1]
+ store i32 %79, i32* @ui, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:80 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %80, i32 11 ) ; <i32>:81 [#uses=1]
+ store i32 %81, i32* @sl, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:82 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %82, i32 11 ) ; <i32>:83 [#uses=1]
+ store i32 %83, i32* @ul, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define void @test_op_and_fetch() nounwind {
+entry:
+ load i8* @uc, align 1 ; <i8>:0 [#uses=2]
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 %0 ) ; <i8>:1 [#uses=1]
+ add i8 %1, %0 ; <i8>:2 [#uses=1]
+ store i8 %2, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:3 [#uses=2]
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 %3 ) ; <i8>:4 [#uses=1]
+ add i8 %4, %3 ; <i8>:5 [#uses=1]
+ store i8 %5, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:6 [#uses=1]
+ zext i8 %6 to i16 ; <i16>:7 [#uses=2]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:8 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %8, i16 %7 ) ; <i16>:9 [#uses=1]
+ add i16 %9, %7 ; <i16>:10 [#uses=1]
+ store i16 %10, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:11 [#uses=1]
+ zext i8 %11 to i16 ; <i16>:12 [#uses=2]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:13 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %13, i16 %12 ) ; <i16>:14 [#uses=1]
+ add i16 %14, %12 ; <i16>:15 [#uses=1]
+ store i16 %15, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:16 [#uses=1]
+ zext i8 %16 to i32 ; <i32>:17 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:18 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %18, i32 %17 ) ; <i32>:19 [#uses=1]
+ add i32 %19, %17 ; <i32>:20 [#uses=1]
+ store i32 %20, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:21 [#uses=1]
+ zext i8 %21 to i32 ; <i32>:22 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:23 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %23, i32 %22 ) ; <i32>:24 [#uses=1]
+ add i32 %24, %22 ; <i32>:25 [#uses=1]
+ store i32 %25, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:26 [#uses=1]
+ zext i8 %26 to i32 ; <i32>:27 [#uses=2]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:28 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %28, i32 %27 ) ; <i32>:29 [#uses=1]
+ add i32 %29, %27 ; <i32>:30 [#uses=1]
+ store i32 %30, i32* @sl, align 4
+ load i8* @uc, align 1 ; <i8>:31 [#uses=1]
+ zext i8 %31 to i32 ; <i32>:32 [#uses=2]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:33 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %33, i32 %32 ) ; <i32>:34 [#uses=1]
+ add i32 %34, %32 ; <i32>:35 [#uses=1]
+ store i32 %35, i32* @ul, align 4
+ load i8* @uc, align 1 ; <i8>:36 [#uses=2]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 %36 ) ; <i8>:37 [#uses=1]
+ sub i8 %37, %36 ; <i8>:38 [#uses=1]
+ store i8 %38, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:39 [#uses=2]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 %39 ) ; <i8>:40 [#uses=1]
+ sub i8 %40, %39 ; <i8>:41 [#uses=1]
+ store i8 %41, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:42 [#uses=1]
+ zext i8 %42 to i16 ; <i16>:43 [#uses=2]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:44 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %44, i16 %43 ) ; <i16>:45 [#uses=1]
+ sub i16 %45, %43 ; <i16>:46 [#uses=1]
+ store i16 %46, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:47 [#uses=1]
+ zext i8 %47 to i16 ; <i16>:48 [#uses=2]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:49 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %49, i16 %48 ) ; <i16>:50 [#uses=1]
+ sub i16 %50, %48 ; <i16>:51 [#uses=1]
+ store i16 %51, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:52 [#uses=1]
+ zext i8 %52 to i32 ; <i32>:53 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:54 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %54, i32 %53 ) ; <i32>:55 [#uses=1]
+ sub i32 %55, %53 ; <i32>:56 [#uses=1]
+ store i32 %56, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:57 [#uses=1]
+ zext i8 %57 to i32 ; <i32>:58 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:59 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %59, i32 %58 ) ; <i32>:60 [#uses=1]
+ sub i32 %60, %58 ; <i32>:61 [#uses=1]
+ store i32 %61, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:62 [#uses=1]
+ zext i8 %62 to i32 ; <i32>:63 [#uses=2]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:64 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %64, i32 %63 ) ; <i32>:65 [#uses=1]
+ sub i32 %65, %63 ; <i32>:66 [#uses=1]
+ store i32 %66, i32* @sl, align 4
+ load i8* @uc, align 1 ; <i8>:67 [#uses=1]
+ zext i8 %67 to i32 ; <i32>:68 [#uses=2]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:69 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %69, i32 %68 ) ; <i32>:70 [#uses=1]
+ sub i32 %70, %68 ; <i32>:71 [#uses=1]
+ store i32 %71, i32* @ul, align 4
+ load i8* @uc, align 1 ; <i8>:72 [#uses=2]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 %72 ) ; <i8>:73 [#uses=1]
+ or i8 %73, %72 ; <i8>:74 [#uses=1]
+ store i8 %74, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:75 [#uses=2]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 %75 ) ; <i8>:76 [#uses=1]
+ or i8 %76, %75 ; <i8>:77 [#uses=1]
+ store i8 %77, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:78 [#uses=1]
+ zext i8 %78 to i16 ; <i16>:79 [#uses=2]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:80 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %80, i16 %79 ) ; <i16>:81 [#uses=1]
+ or i16 %81, %79 ; <i16>:82 [#uses=1]
+ store i16 %82, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:83 [#uses=1]
+ zext i8 %83 to i16 ; <i16>:84 [#uses=2]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:85 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %85, i16 %84 ) ; <i16>:86 [#uses=1]
+ or i16 %86, %84 ; <i16>:87 [#uses=1]
+ store i16 %87, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:88 [#uses=1]
+ zext i8 %88 to i32 ; <i32>:89 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:90 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %90, i32 %89 ) ; <i32>:91 [#uses=1]
+ or i32 %91, %89 ; <i32>:92 [#uses=1]
+ store i32 %92, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:93 [#uses=1]
+ zext i8 %93 to i32 ; <i32>:94 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:95 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %95, i32 %94 ) ; <i32>:96 [#uses=1]
+ or i32 %96, %94 ; <i32>:97 [#uses=1]
+ store i32 %97, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:98 [#uses=1]
+ zext i8 %98 to i32 ; <i32>:99 [#uses=2]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:100 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %100, i32 %99 ) ; <i32>:101 [#uses=1]
+ or i32 %101, %99 ; <i32>:102 [#uses=1]
+ store i32 %102, i32* @sl, align 4
+ load i8* @uc, align 1 ; <i8>:103 [#uses=1]
+ zext i8 %103 to i32 ; <i32>:104 [#uses=2]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:105 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %105, i32 %104 ) ; <i32>:106 [#uses=1]
+ or i32 %106, %104 ; <i32>:107 [#uses=1]
+ store i32 %107, i32* @ul, align 4
+ load i8* @uc, align 1 ; <i8>:108 [#uses=2]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 %108 ) ; <i8>:109 [#uses=1]
+ xor i8 %109, %108 ; <i8>:110 [#uses=1]
+ store i8 %110, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:111 [#uses=2]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 %111 ) ; <i8>:112 [#uses=1]
+ xor i8 %112, %111 ; <i8>:113 [#uses=1]
+ store i8 %113, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:114 [#uses=1]
+ zext i8 %114 to i16 ; <i16>:115 [#uses=2]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:116 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %116, i16 %115 ) ; <i16>:117 [#uses=1]
+ xor i16 %117, %115 ; <i16>:118 [#uses=1]
+ store i16 %118, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:119 [#uses=1]
+ zext i8 %119 to i16 ; <i16>:120 [#uses=2]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:121 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %121, i16 %120 ) ; <i16>:122 [#uses=1]
+ xor i16 %122, %120 ; <i16>:123 [#uses=1]
+ store i16 %123, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:124 [#uses=1]
+ zext i8 %124 to i32 ; <i32>:125 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:126 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %126, i32 %125 ) ; <i32>:127 [#uses=1]
+ xor i32 %127, %125 ; <i32>:128 [#uses=1]
+ store i32 %128, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:129 [#uses=1]
+ zext i8 %129 to i32 ; <i32>:130 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:131 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %131, i32 %130 ) ; <i32>:132 [#uses=1]
+ xor i32 %132, %130 ; <i32>:133 [#uses=1]
+ store i32 %133, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:134 [#uses=1]
+ zext i8 %134 to i32 ; <i32>:135 [#uses=2]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:136 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %136, i32 %135 ) ; <i32>:137 [#uses=1]
+ xor i32 %137, %135 ; <i32>:138 [#uses=1]
+ store i32 %138, i32* @sl, align 4
+ load i8* @uc, align 1 ; <i8>:139 [#uses=1]
+ zext i8 %139 to i32 ; <i32>:140 [#uses=2]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:141 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %141, i32 %140 ) ; <i32>:142 [#uses=1]
+ xor i32 %142, %140 ; <i32>:143 [#uses=1]
+ store i32 %143, i32* @ul, align 4
+ load i8* @uc, align 1 ; <i8>:144 [#uses=2]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 %144 ) ; <i8>:145 [#uses=1]
+ and i8 %145, %144 ; <i8>:146 [#uses=1]
+ store i8 %146, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:147 [#uses=2]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 %147 ) ; <i8>:148 [#uses=1]
+ and i8 %148, %147 ; <i8>:149 [#uses=1]
+ store i8 %149, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:150 [#uses=1]
+ zext i8 %150 to i16 ; <i16>:151 [#uses=2]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:152 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %152, i16 %151 ) ; <i16>:153 [#uses=1]
+ and i16 %153, %151 ; <i16>:154 [#uses=1]
+ store i16 %154, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:155 [#uses=1]
+ zext i8 %155 to i16 ; <i16>:156 [#uses=2]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:157 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %157, i16 %156 ) ; <i16>:158 [#uses=1]
+ and i16 %158, %156 ; <i16>:159 [#uses=1]
+ store i16 %159, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:160 [#uses=1]
+ zext i8 %160 to i32 ; <i32>:161 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:162 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %162, i32 %161 ) ; <i32>:163 [#uses=1]
+ and i32 %163, %161 ; <i32>:164 [#uses=1]
+ store i32 %164, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:165 [#uses=1]
+ zext i8 %165 to i32 ; <i32>:166 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:167 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %167, i32 %166 ) ; <i32>:168 [#uses=1]
+ and i32 %168, %166 ; <i32>:169 [#uses=1]
+ store i32 %169, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:170 [#uses=1]
+ zext i8 %170 to i32 ; <i32>:171 [#uses=2]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:172 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %172, i32 %171 ) ; <i32>:173 [#uses=1]
+ and i32 %173, %171 ; <i32>:174 [#uses=1]
+ store i32 %174, i32* @sl, align 4
+ load i8* @uc, align 1 ; <i8>:175 [#uses=1]
+ zext i8 %175 to i32 ; <i32>:176 [#uses=2]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:177 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %177, i32 %176 ) ; <i32>:178 [#uses=1]
+ and i32 %178, %176 ; <i32>:179 [#uses=1]
+ store i32 %179, i32* @ul, align 4
+ load i8* @uc, align 1 ; <i8>:180 [#uses=2]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 %180 ) ; <i8>:181 [#uses=1]
+ xor i8 %181, -1 ; <i8>:182 [#uses=1]
+ and i8 %182, %180 ; <i8>:183 [#uses=1]
+ store i8 %183, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:184 [#uses=2]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 %184 ) ; <i8>:185 [#uses=1]
+ xor i8 %185, -1 ; <i8>:186 [#uses=1]
+ and i8 %186, %184 ; <i8>:187 [#uses=1]
+ store i8 %187, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:188 [#uses=1]
+ zext i8 %188 to i16 ; <i16>:189 [#uses=2]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:190 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %190, i16 %189 ) ; <i16>:191 [#uses=1]
+ xor i16 %191, -1 ; <i16>:192 [#uses=1]
+ and i16 %192, %189 ; <i16>:193 [#uses=1]
+ store i16 %193, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:194 [#uses=1]
+ zext i8 %194 to i16 ; <i16>:195 [#uses=2]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:196 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %196, i16 %195 ) ; <i16>:197 [#uses=1]
+ xor i16 %197, -1 ; <i16>:198 [#uses=1]
+ and i16 %198, %195 ; <i16>:199 [#uses=1]
+ store i16 %199, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:200 [#uses=1]
+ zext i8 %200 to i32 ; <i32>:201 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:202 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %202, i32 %201 ) ; <i32>:203 [#uses=1]
+ xor i32 %203, -1 ; <i32>:204 [#uses=1]
+ and i32 %204, %201 ; <i32>:205 [#uses=1]
+ store i32 %205, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:206 [#uses=1]
+ zext i8 %206 to i32 ; <i32>:207 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:208 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %208, i32 %207 ) ; <i32>:209 [#uses=1]
+ xor i32 %209, -1 ; <i32>:210 [#uses=1]
+ and i32 %210, %207 ; <i32>:211 [#uses=1]
+ store i32 %211, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:212 [#uses=1]
+ zext i8 %212 to i32 ; <i32>:213 [#uses=2]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:214 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %214, i32 %213 ) ; <i32>:215 [#uses=1]
+ xor i32 %215, -1 ; <i32>:216 [#uses=1]
+ and i32 %216, %213 ; <i32>:217 [#uses=1]
+ store i32 %217, i32* @sl, align 4
+ load i8* @uc, align 1 ; <i8>:218 [#uses=1]
+ zext i8 %218 to i32 ; <i32>:219 [#uses=2]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:220 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %220, i32 %219 ) ; <i32>:221 [#uses=1]
+ xor i32 %221, -1 ; <i32>:222 [#uses=1]
+ and i32 %222, %219 ; <i32>:223 [#uses=1]
+ store i32 %223, i32* @ul, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define void @test_compare_and_swap() nounwind {
+entry:
+ load i8* @uc, align 1 ; <i8>:0 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:1 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %0, i8 %1 ) ; <i8>:2 [#uses=1]
+ store i8 %2, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:3 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:4 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %3, i8 %4 ) ; <i8>:5 [#uses=1]
+ store i8 %5, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:6 [#uses=1]
+ zext i8 %6 to i16 ; <i16>:7 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:8 [#uses=1]
+ sext i8 %8 to i16 ; <i16>:9 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:10 [#uses=1]
+ call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %10, i16 %7, i16 %9 ) ; <i16>:11 [#uses=1]
+ store i16 %11, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:12 [#uses=1]
+ zext i8 %12 to i16 ; <i16>:13 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:14 [#uses=1]
+ sext i8 %14 to i16 ; <i16>:15 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:16 [#uses=1]
+ call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %16, i16 %13, i16 %15 ) ; <i16>:17 [#uses=1]
+ store i16 %17, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:18 [#uses=1]
+ zext i8 %18 to i32 ; <i32>:19 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:20 [#uses=1]
+ sext i8 %20 to i32 ; <i32>:21 [#uses=1]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:22 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %22, i32 %19, i32 %21 ) ; <i32>:23 [#uses=1]
+ store i32 %23, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:24 [#uses=1]
+ zext i8 %24 to i32 ; <i32>:25 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:26 [#uses=1]
+ sext i8 %26 to i32 ; <i32>:27 [#uses=1]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:28 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %28, i32 %25, i32 %27 ) ; <i32>:29 [#uses=1]
+ store i32 %29, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:30 [#uses=1]
+ zext i8 %30 to i32 ; <i32>:31 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:32 [#uses=1]
+ sext i8 %32 to i32 ; <i32>:33 [#uses=1]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:34 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %34, i32 %31, i32 %33 ) ; <i32>:35 [#uses=1]
+ store i32 %35, i32* @sl, align 4
+ load i8* @uc, align 1 ; <i8>:36 [#uses=1]
+ zext i8 %36 to i32 ; <i32>:37 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:38 [#uses=1]
+ sext i8 %38 to i32 ; <i32>:39 [#uses=1]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:40 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %40, i32 %37, i32 %39 ) ; <i32>:41 [#uses=1]
+ store i32 %41, i32* @ul, align 4
+ load i8* @uc, align 1 ; <i8>:42 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:43 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %42, i8 %43 ) ; <i8>:44 [#uses=1]
+ icmp eq i8 %44, %42 ; <i1>:45 [#uses=1]
+ zext i1 %45 to i32 ; <i32>:46 [#uses=1]
+ store i32 %46, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:47 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:48 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %47, i8 %48 ) ; <i8>:49 [#uses=1]
+ icmp eq i8 %49, %47 ; <i1>:50 [#uses=1]
+ zext i1 %50 to i32 ; <i32>:51 [#uses=1]
+ store i32 %51, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:52 [#uses=1]
+ zext i8 %52 to i16 ; <i16>:53 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:54 [#uses=1]
+ sext i8 %54 to i16 ; <i16>:55 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:56 [#uses=1]
+ call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %56, i16 %53, i16 %55 ) ; <i16>:57 [#uses=1]
+ icmp eq i16 %57, %53 ; <i1>:58 [#uses=1]
+ zext i1 %58 to i32 ; <i32>:59 [#uses=1]
+ store i32 %59, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:60 [#uses=1]
+ zext i8 %60 to i16 ; <i16>:61 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:62 [#uses=1]
+ sext i8 %62 to i16 ; <i16>:63 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:64 [#uses=1]
+ call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %64, i16 %61, i16 %63 ) ; <i16>:65 [#uses=1]
+ icmp eq i16 %65, %61 ; <i1>:66 [#uses=1]
+ zext i1 %66 to i32 ; <i32>:67 [#uses=1]
+ store i32 %67, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:68 [#uses=1]
+ zext i8 %68 to i32 ; <i32>:69 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:70 [#uses=1]
+ sext i8 %70 to i32 ; <i32>:71 [#uses=1]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:72 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %72, i32 %69, i32 %71 ) ; <i32>:73 [#uses=1]
+ icmp eq i32 %73, %69 ; <i1>:74 [#uses=1]
+ zext i1 %74 to i32 ; <i32>:75 [#uses=1]
+ store i32 %75, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:76 [#uses=1]
+ zext i8 %76 to i32 ; <i32>:77 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:78 [#uses=1]
+ sext i8 %78 to i32 ; <i32>:79 [#uses=1]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:80 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %80, i32 %77, i32 %79 ) ; <i32>:81 [#uses=1]
+ icmp eq i32 %81, %77 ; <i1>:82 [#uses=1]
+ zext i1 %82 to i32 ; <i32>:83 [#uses=1]
+ store i32 %83, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:84 [#uses=1]
+ zext i8 %84 to i32 ; <i32>:85 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:86 [#uses=1]
+ sext i8 %86 to i32 ; <i32>:87 [#uses=1]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:88 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %88, i32 %85, i32 %87 ) ; <i32>:89 [#uses=1]
+ icmp eq i32 %89, %85 ; <i1>:90 [#uses=1]
+ zext i1 %90 to i32 ; <i32>:91 [#uses=1]
+ store i32 %91, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:92 [#uses=1]
+ zext i8 %92 to i32 ; <i32>:93 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:94 [#uses=1]
+ sext i8 %94 to i32 ; <i32>:95 [#uses=1]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:96 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %96, i32 %93, i32 %95 ) ; <i32>:97 [#uses=1]
+ icmp eq i32 %97, %93 ; <i1>:98 [#uses=1]
+ zext i1 %98 to i32 ; <i32>:99 [#uses=1]
+ store i32 %99, i32* @ui, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8*, i8, i8) nounwind
+
+declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16*, i16, i16) nounwind
+
+declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind
+
+define void @test_lock() nounwind {
+entry:
+ call i8 @llvm.atomic.swap.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:0 [#uses=1]
+ store i8 %0, i8* @sc, align 1
+ call i8 @llvm.atomic.swap.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:1 [#uses=1]
+ store i8 %1, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1]
+ call i16 @llvm.atomic.swap.i16.p0i16( i16* %2, i16 1 ) ; <i16>:3 [#uses=1]
+ store i16 %3, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1]
+ call i16 @llvm.atomic.swap.i16.p0i16( i16* %4, i16 1 ) ; <i16>:5 [#uses=1]
+ store i16 %5, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1]
+ call i32 @llvm.atomic.swap.i32.p0i32( i32* %6, i32 1 ) ; <i32>:7 [#uses=1]
+ store i32 %7, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1]
+ call i32 @llvm.atomic.swap.i32.p0i32( i32* %8, i32 1 ) ; <i32>:9 [#uses=1]
+ store i32 %9, i32* @ui, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:10 [#uses=1]
+ call i32 @llvm.atomic.swap.i32.p0i32( i32* %10, i32 1 ) ; <i32>:11 [#uses=1]
+ store i32 %11, i32* @sl, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:12 [#uses=1]
+ call i32 @llvm.atomic.swap.i32.p0i32( i32* %12, i32 1 ) ; <i32>:13 [#uses=1]
+ store i32 %13, i32* @ul, align 4
+ call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true, i1 false )
+ volatile store i8 0, i8* @sc, align 1
+ volatile store i8 0, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:14 [#uses=1]
+ volatile store i16 0, i16* %14, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:15 [#uses=1]
+ volatile store i16 0, i16* %15, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:16 [#uses=1]
+ volatile store i32 0, i32* %16, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:17 [#uses=1]
+ volatile store i32 0, i32* %17, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:18 [#uses=1]
+ volatile store i32 0, i32* %18, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:19 [#uses=1]
+ volatile store i32 0, i32* %19, align 4
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:20 [#uses=1]
+ volatile store i64 0, i64* %20, align 8
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:21 [#uses=1]
+ volatile store i64 0, i64* %21, align 8
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.swap.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.swap.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind
+
+declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind
diff --git a/test/CodeGen/PowerPC/Atomics-64.ll b/test/CodeGen/PowerPC/Atomics-64.ll
new file mode 100644
index 0000000..1dc4310
--- /dev/null
+++ b/test/CodeGen/PowerPC/Atomics-64.ll
@@ -0,0 +1,773 @@
+; RUN: llc < %s -march=ppc64
+; ModuleID = 'Atomics.c'
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc64-apple-darwin9"
+@sc = common global i8 0 ; <i8*> [#uses=52]
+@uc = common global i8 0 ; <i8*> [#uses=100]
+@ss = common global i16 0 ; <i16*> [#uses=15]
+@us = common global i16 0 ; <i16*> [#uses=15]
+@si = common global i32 0 ; <i32*> [#uses=15]
+@ui = common global i32 0 ; <i32*> [#uses=23]
+@sl = common global i64 0, align 8 ; <i64*> [#uses=15]
+@ul = common global i64 0, align 8 ; <i64*> [#uses=15]
+@sll = common global i64 0, align 8 ; <i64*> [#uses=1]
+@ull = common global i64 0, align 8 ; <i64*> [#uses=1]
+
+define void @test_op_ignore() nounwind {
+entry:
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:0 [#uses=0]
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:1 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 1 ) ; <i16>:3 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 1 ) ; <i16>:5 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 1 ) ; <i32>:7 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 1 ) ; <i32>:9 [#uses=0]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:10 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %10, i64 1 ) ; <i64>:11 [#uses=0]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:12 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %12, i64 1 ) ; <i64>:13 [#uses=0]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:14 [#uses=0]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:15 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:16 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 1 ) ; <i16>:17 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:18 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 1 ) ; <i16>:19 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:20 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 1 ) ; <i32>:21 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:22 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 1 ) ; <i32>:23 [#uses=0]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:24 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %24, i64 1 ) ; <i64>:25 [#uses=0]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:26 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %26, i64 1 ) ; <i64>:27 [#uses=0]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:28 [#uses=0]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:29 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:30 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 1 ) ; <i16>:31 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:32 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 1 ) ; <i16>:33 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:34 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 1 ) ; <i32>:35 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:36 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 1 ) ; <i32>:37 [#uses=0]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:38 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %38, i64 1 ) ; <i64>:39 [#uses=0]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:40 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %40, i64 1 ) ; <i64>:41 [#uses=0]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:42 [#uses=0]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:43 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:44 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 1 ) ; <i16>:45 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:46 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 1 ) ; <i16>:47 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:48 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 1 ) ; <i32>:49 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:50 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 1 ) ; <i32>:51 [#uses=0]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:52 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %52, i64 1 ) ; <i64>:53 [#uses=0]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:54 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %54, i64 1 ) ; <i64>:55 [#uses=0]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:56 [#uses=0]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:57 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:58 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 1 ) ; <i16>:59 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:60 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 1 ) ; <i16>:61 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:62 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 1 ) ; <i32>:63 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:64 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 1 ) ; <i32>:65 [#uses=0]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:66 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %66, i64 1 ) ; <i64>:67 [#uses=0]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:68 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %68, i64 1 ) ; <i64>:69 [#uses=0]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:70 [#uses=0]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:71 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:72 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 1 ) ; <i16>:73 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:74 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 1 ) ; <i16>:75 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:76 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 1 ) ; <i32>:77 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:78 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 1 ) ; <i32>:79 [#uses=0]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:80 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %80, i64 1 ) ; <i64>:81 [#uses=0]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:82 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %82, i64 1 ) ; <i64>:83 [#uses=0]
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.add.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.add.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.sub.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.sub.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.sub.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.or.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.or.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.or.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.xor.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.xor.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.xor.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.and.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.and.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.and.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.nand.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.nand.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.nand.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.nand.i64.p0i64(i64*, i64) nounwind
+
+define void @test_fetch_and_op() nounwind {
+entry:
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:0 [#uses=1]
+ store i8 %0, i8* @sc, align 1
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:1 [#uses=1]
+ store i8 %1, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 11 ) ; <i16>:3 [#uses=1]
+ store i16 %3, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 11 ) ; <i16>:5 [#uses=1]
+ store i16 %5, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 11 ) ; <i32>:7 [#uses=1]
+ store i32 %7, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 11 ) ; <i32>:9 [#uses=1]
+ store i32 %9, i32* @ui, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:10 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %10, i64 11 ) ; <i64>:11 [#uses=1]
+ store i64 %11, i64* @sl, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:12 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %12, i64 11 ) ; <i64>:13 [#uses=1]
+ store i64 %13, i64* @ul, align 8
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:14 [#uses=1]
+ store i8 %14, i8* @sc, align 1
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:15 [#uses=1]
+ store i8 %15, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:16 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 11 ) ; <i16>:17 [#uses=1]
+ store i16 %17, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:18 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 11 ) ; <i16>:19 [#uses=1]
+ store i16 %19, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:20 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 11 ) ; <i32>:21 [#uses=1]
+ store i32 %21, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:22 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 11 ) ; <i32>:23 [#uses=1]
+ store i32 %23, i32* @ui, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:24 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %24, i64 11 ) ; <i64>:25 [#uses=1]
+ store i64 %25, i64* @sl, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:26 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %26, i64 11 ) ; <i64>:27 [#uses=1]
+ store i64 %27, i64* @ul, align 8
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:28 [#uses=1]
+ store i8 %28, i8* @sc, align 1
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:29 [#uses=1]
+ store i8 %29, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:30 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 11 ) ; <i16>:31 [#uses=1]
+ store i16 %31, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:32 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 11 ) ; <i16>:33 [#uses=1]
+ store i16 %33, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:34 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 11 ) ; <i32>:35 [#uses=1]
+ store i32 %35, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:36 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 11 ) ; <i32>:37 [#uses=1]
+ store i32 %37, i32* @ui, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:38 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %38, i64 11 ) ; <i64>:39 [#uses=1]
+ store i64 %39, i64* @sl, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:40 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %40, i64 11 ) ; <i64>:41 [#uses=1]
+ store i64 %41, i64* @ul, align 8
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:42 [#uses=1]
+ store i8 %42, i8* @sc, align 1
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:43 [#uses=1]
+ store i8 %43, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:44 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 11 ) ; <i16>:45 [#uses=1]
+ store i16 %45, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:46 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 11 ) ; <i16>:47 [#uses=1]
+ store i16 %47, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:48 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 11 ) ; <i32>:49 [#uses=1]
+ store i32 %49, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:50 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 11 ) ; <i32>:51 [#uses=1]
+ store i32 %51, i32* @ui, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:52 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %52, i64 11 ) ; <i64>:53 [#uses=1]
+ store i64 %53, i64* @sl, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:54 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %54, i64 11 ) ; <i64>:55 [#uses=1]
+ store i64 %55, i64* @ul, align 8
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:56 [#uses=1]
+ store i8 %56, i8* @sc, align 1
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:57 [#uses=1]
+ store i8 %57, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:58 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 11 ) ; <i16>:59 [#uses=1]
+ store i16 %59, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:60 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 11 ) ; <i16>:61 [#uses=1]
+ store i16 %61, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:62 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 11 ) ; <i32>:63 [#uses=1]
+ store i32 %63, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:64 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 11 ) ; <i32>:65 [#uses=1]
+ store i32 %65, i32* @ui, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:66 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %66, i64 11 ) ; <i64>:67 [#uses=1]
+ store i64 %67, i64* @sl, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:68 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %68, i64 11 ) ; <i64>:69 [#uses=1]
+ store i64 %69, i64* @ul, align 8
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:70 [#uses=1]
+ store i8 %70, i8* @sc, align 1
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:71 [#uses=1]
+ store i8 %71, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:72 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 11 ) ; <i16>:73 [#uses=1]
+ store i16 %73, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:74 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 11 ) ; <i16>:75 [#uses=1]
+ store i16 %75, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:76 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 11 ) ; <i32>:77 [#uses=1]
+ store i32 %77, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:78 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 11 ) ; <i32>:79 [#uses=1]
+ store i32 %79, i32* @ui, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:80 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %80, i64 11 ) ; <i64>:81 [#uses=1]
+ store i64 %81, i64* @sl, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:82 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %82, i64 11 ) ; <i64>:83 [#uses=1]
+ store i64 %83, i64* @ul, align 8
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define void @test_op_and_fetch() nounwind {
+entry:
+ load i8* @uc, align 1 ; <i8>:0 [#uses=2]
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 %0 ) ; <i8>:1 [#uses=1]
+ add i8 %1, %0 ; <i8>:2 [#uses=1]
+ store i8 %2, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:3 [#uses=2]
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 %3 ) ; <i8>:4 [#uses=1]
+ add i8 %4, %3 ; <i8>:5 [#uses=1]
+ store i8 %5, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:6 [#uses=1]
+ zext i8 %6 to i16 ; <i16>:7 [#uses=2]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:8 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %8, i16 %7 ) ; <i16>:9 [#uses=1]
+ add i16 %9, %7 ; <i16>:10 [#uses=1]
+ store i16 %10, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:11 [#uses=1]
+ zext i8 %11 to i16 ; <i16>:12 [#uses=2]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:13 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %13, i16 %12 ) ; <i16>:14 [#uses=1]
+ add i16 %14, %12 ; <i16>:15 [#uses=1]
+ store i16 %15, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:16 [#uses=1]
+ zext i8 %16 to i32 ; <i32>:17 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:18 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %18, i32 %17 ) ; <i32>:19 [#uses=1]
+ add i32 %19, %17 ; <i32>:20 [#uses=1]
+ store i32 %20, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:21 [#uses=1]
+ zext i8 %21 to i32 ; <i32>:22 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:23 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %23, i32 %22 ) ; <i32>:24 [#uses=1]
+ add i32 %24, %22 ; <i32>:25 [#uses=1]
+ store i32 %25, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:26 [#uses=1]
+ zext i8 %26 to i64 ; <i64>:27 [#uses=2]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:28 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %28, i64 %27 ) ; <i64>:29 [#uses=1]
+ add i64 %29, %27 ; <i64>:30 [#uses=1]
+ store i64 %30, i64* @sl, align 8
+ load i8* @uc, align 1 ; <i8>:31 [#uses=1]
+ zext i8 %31 to i64 ; <i64>:32 [#uses=2]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:33 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %33, i64 %32 ) ; <i64>:34 [#uses=1]
+ add i64 %34, %32 ; <i64>:35 [#uses=1]
+ store i64 %35, i64* @ul, align 8
+ load i8* @uc, align 1 ; <i8>:36 [#uses=2]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 %36 ) ; <i8>:37 [#uses=1]
+ sub i8 %37, %36 ; <i8>:38 [#uses=1]
+ store i8 %38, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:39 [#uses=2]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 %39 ) ; <i8>:40 [#uses=1]
+ sub i8 %40, %39 ; <i8>:41 [#uses=1]
+ store i8 %41, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:42 [#uses=1]
+ zext i8 %42 to i16 ; <i16>:43 [#uses=2]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:44 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %44, i16 %43 ) ; <i16>:45 [#uses=1]
+ sub i16 %45, %43 ; <i16>:46 [#uses=1]
+ store i16 %46, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:47 [#uses=1]
+ zext i8 %47 to i16 ; <i16>:48 [#uses=2]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:49 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %49, i16 %48 ) ; <i16>:50 [#uses=1]
+ sub i16 %50, %48 ; <i16>:51 [#uses=1]
+ store i16 %51, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:52 [#uses=1]
+ zext i8 %52 to i32 ; <i32>:53 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:54 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %54, i32 %53 ) ; <i32>:55 [#uses=1]
+ sub i32 %55, %53 ; <i32>:56 [#uses=1]
+ store i32 %56, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:57 [#uses=1]
+ zext i8 %57 to i32 ; <i32>:58 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:59 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %59, i32 %58 ) ; <i32>:60 [#uses=1]
+ sub i32 %60, %58 ; <i32>:61 [#uses=1]
+ store i32 %61, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:62 [#uses=1]
+ zext i8 %62 to i64 ; <i64>:63 [#uses=2]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:64 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %64, i64 %63 ) ; <i64>:65 [#uses=1]
+ sub i64 %65, %63 ; <i64>:66 [#uses=1]
+ store i64 %66, i64* @sl, align 8
+ load i8* @uc, align 1 ; <i8>:67 [#uses=1]
+ zext i8 %67 to i64 ; <i64>:68 [#uses=2]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:69 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %69, i64 %68 ) ; <i64>:70 [#uses=1]
+ sub i64 %70, %68 ; <i64>:71 [#uses=1]
+ store i64 %71, i64* @ul, align 8
+ load i8* @uc, align 1 ; <i8>:72 [#uses=2]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 %72 ) ; <i8>:73 [#uses=1]
+ or i8 %73, %72 ; <i8>:74 [#uses=1]
+ store i8 %74, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:75 [#uses=2]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 %75 ) ; <i8>:76 [#uses=1]
+ or i8 %76, %75 ; <i8>:77 [#uses=1]
+ store i8 %77, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:78 [#uses=1]
+ zext i8 %78 to i16 ; <i16>:79 [#uses=2]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:80 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %80, i16 %79 ) ; <i16>:81 [#uses=1]
+ or i16 %81, %79 ; <i16>:82 [#uses=1]
+ store i16 %82, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:83 [#uses=1]
+ zext i8 %83 to i16 ; <i16>:84 [#uses=2]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:85 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %85, i16 %84 ) ; <i16>:86 [#uses=1]
+ or i16 %86, %84 ; <i16>:87 [#uses=1]
+ store i16 %87, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:88 [#uses=1]
+ zext i8 %88 to i32 ; <i32>:89 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:90 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %90, i32 %89 ) ; <i32>:91 [#uses=1]
+ or i32 %91, %89 ; <i32>:92 [#uses=1]
+ store i32 %92, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:93 [#uses=1]
+ zext i8 %93 to i32 ; <i32>:94 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:95 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %95, i32 %94 ) ; <i32>:96 [#uses=1]
+ or i32 %96, %94 ; <i32>:97 [#uses=1]
+ store i32 %97, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:98 [#uses=1]
+ zext i8 %98 to i64 ; <i64>:99 [#uses=2]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:100 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %100, i64 %99 ) ; <i64>:101 [#uses=1]
+ or i64 %101, %99 ; <i64>:102 [#uses=1]
+ store i64 %102, i64* @sl, align 8
+ load i8* @uc, align 1 ; <i8>:103 [#uses=1]
+ zext i8 %103 to i64 ; <i64>:104 [#uses=2]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:105 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %105, i64 %104 ) ; <i64>:106 [#uses=1]
+ or i64 %106, %104 ; <i64>:107 [#uses=1]
+ store i64 %107, i64* @ul, align 8
+ load i8* @uc, align 1 ; <i8>:108 [#uses=2]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 %108 ) ; <i8>:109 [#uses=1]
+ xor i8 %109, %108 ; <i8>:110 [#uses=1]
+ store i8 %110, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:111 [#uses=2]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 %111 ) ; <i8>:112 [#uses=1]
+ xor i8 %112, %111 ; <i8>:113 [#uses=1]
+ store i8 %113, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:114 [#uses=1]
+ zext i8 %114 to i16 ; <i16>:115 [#uses=2]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:116 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %116, i16 %115 ) ; <i16>:117 [#uses=1]
+ xor i16 %117, %115 ; <i16>:118 [#uses=1]
+ store i16 %118, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:119 [#uses=1]
+ zext i8 %119 to i16 ; <i16>:120 [#uses=2]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:121 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %121, i16 %120 ) ; <i16>:122 [#uses=1]
+ xor i16 %122, %120 ; <i16>:123 [#uses=1]
+ store i16 %123, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:124 [#uses=1]
+ zext i8 %124 to i32 ; <i32>:125 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:126 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %126, i32 %125 ) ; <i32>:127 [#uses=1]
+ xor i32 %127, %125 ; <i32>:128 [#uses=1]
+ store i32 %128, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:129 [#uses=1]
+ zext i8 %129 to i32 ; <i32>:130 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:131 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %131, i32 %130 ) ; <i32>:132 [#uses=1]
+ xor i32 %132, %130 ; <i32>:133 [#uses=1]
+ store i32 %133, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:134 [#uses=1]
+ zext i8 %134 to i64 ; <i64>:135 [#uses=2]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:136 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %136, i64 %135 ) ; <i64>:137 [#uses=1]
+ xor i64 %137, %135 ; <i64>:138 [#uses=1]
+ store i64 %138, i64* @sl, align 8
+ load i8* @uc, align 1 ; <i8>:139 [#uses=1]
+ zext i8 %139 to i64 ; <i64>:140 [#uses=2]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:141 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %141, i64 %140 ) ; <i64>:142 [#uses=1]
+ xor i64 %142, %140 ; <i64>:143 [#uses=1]
+ store i64 %143, i64* @ul, align 8
+ load i8* @uc, align 1 ; <i8>:144 [#uses=2]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 %144 ) ; <i8>:145 [#uses=1]
+ and i8 %145, %144 ; <i8>:146 [#uses=1]
+ store i8 %146, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:147 [#uses=2]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 %147 ) ; <i8>:148 [#uses=1]
+ and i8 %148, %147 ; <i8>:149 [#uses=1]
+ store i8 %149, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:150 [#uses=1]
+ zext i8 %150 to i16 ; <i16>:151 [#uses=2]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:152 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %152, i16 %151 ) ; <i16>:153 [#uses=1]
+ and i16 %153, %151 ; <i16>:154 [#uses=1]
+ store i16 %154, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:155 [#uses=1]
+ zext i8 %155 to i16 ; <i16>:156 [#uses=2]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:157 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %157, i16 %156 ) ; <i16>:158 [#uses=1]
+ and i16 %158, %156 ; <i16>:159 [#uses=1]
+ store i16 %159, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:160 [#uses=1]
+ zext i8 %160 to i32 ; <i32>:161 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:162 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %162, i32 %161 ) ; <i32>:163 [#uses=1]
+ and i32 %163, %161 ; <i32>:164 [#uses=1]
+ store i32 %164, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:165 [#uses=1]
+ zext i8 %165 to i32 ; <i32>:166 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:167 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %167, i32 %166 ) ; <i32>:168 [#uses=1]
+ and i32 %168, %166 ; <i32>:169 [#uses=1]
+ store i32 %169, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:170 [#uses=1]
+ zext i8 %170 to i64 ; <i64>:171 [#uses=2]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:172 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %172, i64 %171 ) ; <i64>:173 [#uses=1]
+ and i64 %173, %171 ; <i64>:174 [#uses=1]
+ store i64 %174, i64* @sl, align 8
+ load i8* @uc, align 1 ; <i8>:175 [#uses=1]
+ zext i8 %175 to i64 ; <i64>:176 [#uses=2]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:177 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %177, i64 %176 ) ; <i64>:178 [#uses=1]
+ and i64 %178, %176 ; <i64>:179 [#uses=1]
+ store i64 %179, i64* @ul, align 8
+ load i8* @uc, align 1 ; <i8>:180 [#uses=2]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 %180 ) ; <i8>:181 [#uses=1]
+ xor i8 %181, -1 ; <i8>:182 [#uses=1]
+ and i8 %182, %180 ; <i8>:183 [#uses=1]
+ store i8 %183, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:184 [#uses=2]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 %184 ) ; <i8>:185 [#uses=1]
+ xor i8 %185, -1 ; <i8>:186 [#uses=1]
+ and i8 %186, %184 ; <i8>:187 [#uses=1]
+ store i8 %187, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:188 [#uses=1]
+ zext i8 %188 to i16 ; <i16>:189 [#uses=2]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:190 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %190, i16 %189 ) ; <i16>:191 [#uses=1]
+ xor i16 %191, -1 ; <i16>:192 [#uses=1]
+ and i16 %192, %189 ; <i16>:193 [#uses=1]
+ store i16 %193, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:194 [#uses=1]
+ zext i8 %194 to i16 ; <i16>:195 [#uses=2]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:196 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %196, i16 %195 ) ; <i16>:197 [#uses=1]
+ xor i16 %197, -1 ; <i16>:198 [#uses=1]
+ and i16 %198, %195 ; <i16>:199 [#uses=1]
+ store i16 %199, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:200 [#uses=1]
+ zext i8 %200 to i32 ; <i32>:201 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:202 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %202, i32 %201 ) ; <i32>:203 [#uses=1]
+ xor i32 %203, -1 ; <i32>:204 [#uses=1]
+ and i32 %204, %201 ; <i32>:205 [#uses=1]
+ store i32 %205, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:206 [#uses=1]
+ zext i8 %206 to i32 ; <i32>:207 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:208 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %208, i32 %207 ) ; <i32>:209 [#uses=1]
+ xor i32 %209, -1 ; <i32>:210 [#uses=1]
+ and i32 %210, %207 ; <i32>:211 [#uses=1]
+ store i32 %211, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:212 [#uses=1]
+ zext i8 %212 to i64 ; <i64>:213 [#uses=2]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:214 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %214, i64 %213 ) ; <i64>:215 [#uses=1]
+ xor i64 %215, -1 ; <i64>:216 [#uses=1]
+ and i64 %216, %213 ; <i64>:217 [#uses=1]
+ store i64 %217, i64* @sl, align 8
+ load i8* @uc, align 1 ; <i8>:218 [#uses=1]
+ zext i8 %218 to i64 ; <i64>:219 [#uses=2]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:220 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %220, i64 %219 ) ; <i64>:221 [#uses=1]
+ xor i64 %221, -1 ; <i64>:222 [#uses=1]
+ and i64 %222, %219 ; <i64>:223 [#uses=1]
+ store i64 %223, i64* @ul, align 8
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define void @test_compare_and_swap() nounwind {
+entry:
+ load i8* @uc, align 1 ; <i8>:0 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:1 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %0, i8 %1 ) ; <i8>:2 [#uses=1]
+ store i8 %2, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:3 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:4 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %3, i8 %4 ) ; <i8>:5 [#uses=1]
+ store i8 %5, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:6 [#uses=1]
+ zext i8 %6 to i16 ; <i16>:7 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:8 [#uses=1]
+ sext i8 %8 to i16 ; <i16>:9 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:10 [#uses=1]
+ call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %10, i16 %7, i16 %9 ) ; <i16>:11 [#uses=1]
+ store i16 %11, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:12 [#uses=1]
+ zext i8 %12 to i16 ; <i16>:13 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:14 [#uses=1]
+ sext i8 %14 to i16 ; <i16>:15 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:16 [#uses=1]
+ call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %16, i16 %13, i16 %15 ) ; <i16>:17 [#uses=1]
+ store i16 %17, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:18 [#uses=1]
+ zext i8 %18 to i32 ; <i32>:19 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:20 [#uses=1]
+ sext i8 %20 to i32 ; <i32>:21 [#uses=1]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:22 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %22, i32 %19, i32 %21 ) ; <i32>:23 [#uses=1]
+ store i32 %23, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:24 [#uses=1]
+ zext i8 %24 to i32 ; <i32>:25 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:26 [#uses=1]
+ sext i8 %26 to i32 ; <i32>:27 [#uses=1]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:28 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %28, i32 %25, i32 %27 ) ; <i32>:29 [#uses=1]
+ store i32 %29, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:30 [#uses=1]
+ zext i8 %30 to i64 ; <i64>:31 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:32 [#uses=1]
+ sext i8 %32 to i64 ; <i64>:33 [#uses=1]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:34 [#uses=1]
+ call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %34, i64 %31, i64 %33 ) ; <i64>:35 [#uses=1]
+ store i64 %35, i64* @sl, align 8
+ load i8* @uc, align 1 ; <i8>:36 [#uses=1]
+ zext i8 %36 to i64 ; <i64>:37 [#uses=1]
+ load i8* @sc, align 1 ; <i8>:38 [#uses=1]
+ sext i8 %38 to i64 ; <i64>:39 [#uses=1]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:40 [#uses=1]
+ call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %40, i64 %37, i64 %39 ) ; <i64>:41 [#uses=1]
+ store i64 %41, i64* @ul, align 8
+ load i8* @uc, align 1 ; <i8>:42 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:43 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %42, i8 %43 ) ; <i8>:44 [#uses=1]
+ icmp eq i8 %44, %42 ; <i1>:45 [#uses=1]
+ zext i1 %45 to i8 ; <i8>:46 [#uses=1]
+ zext i8 %46 to i32 ; <i32>:47 [#uses=1]
+ store i32 %47, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:48 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:49 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %48, i8 %49 ) ; <i8>:50 [#uses=1]
+ icmp eq i8 %50, %48 ; <i1>:51 [#uses=1]
+ zext i1 %51 to i8 ; <i8>:52 [#uses=1]
+ zext i8 %52 to i32 ; <i32>:53 [#uses=1]
+ store i32 %53, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:54 [#uses=1]
+ zext i8 %54 to i16 ; <i16>:55 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:56 [#uses=1]
+ sext i8 %56 to i16 ; <i16>:57 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:58 [#uses=1]
+ call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %58, i16 %55, i16 %57 ) ; <i16>:59 [#uses=1]
+ icmp eq i16 %59, %55 ; <i1>:60 [#uses=1]
+ zext i1 %60 to i8 ; <i8>:61 [#uses=1]
+ zext i8 %61 to i32 ; <i32>:62 [#uses=1]
+ store i32 %62, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:63 [#uses=1]
+ zext i8 %63 to i16 ; <i16>:64 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:65 [#uses=1]
+ sext i8 %65 to i16 ; <i16>:66 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:67 [#uses=1]
+ call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %67, i16 %64, i16 %66 ) ; <i16>:68 [#uses=1]
+ icmp eq i16 %68, %64 ; <i1>:69 [#uses=1]
+ zext i1 %69 to i8 ; <i8>:70 [#uses=1]
+ zext i8 %70 to i32 ; <i32>:71 [#uses=1]
+ store i32 %71, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:72 [#uses=1]
+ zext i8 %72 to i32 ; <i32>:73 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:74 [#uses=1]
+ sext i8 %74 to i32 ; <i32>:75 [#uses=1]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:76 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %76, i32 %73, i32 %75 ) ; <i32>:77 [#uses=1]
+ icmp eq i32 %77, %73 ; <i1>:78 [#uses=1]
+ zext i1 %78 to i8 ; <i8>:79 [#uses=1]
+ zext i8 %79 to i32 ; <i32>:80 [#uses=1]
+ store i32 %80, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:81 [#uses=1]
+ zext i8 %81 to i32 ; <i32>:82 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:83 [#uses=1]
+ sext i8 %83 to i32 ; <i32>:84 [#uses=1]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:85 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %85, i32 %82, i32 %84 ) ; <i32>:86 [#uses=1]
+ icmp eq i32 %86, %82 ; <i1>:87 [#uses=1]
+ zext i1 %87 to i8 ; <i8>:88 [#uses=1]
+ zext i8 %88 to i32 ; <i32>:89 [#uses=1]
+ store i32 %89, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:90 [#uses=1]
+ zext i8 %90 to i64 ; <i64>:91 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:92 [#uses=1]
+ sext i8 %92 to i64 ; <i64>:93 [#uses=1]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:94 [#uses=1]
+ call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %94, i64 %91, i64 %93 ) ; <i64>:95 [#uses=1]
+ icmp eq i64 %95, %91 ; <i1>:96 [#uses=1]
+ zext i1 %96 to i8 ; <i8>:97 [#uses=1]
+ zext i8 %97 to i32 ; <i32>:98 [#uses=1]
+ store i32 %98, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:99 [#uses=1]
+ zext i8 %99 to i64 ; <i64>:100 [#uses=2]
+ load i8* @sc, align 1 ; <i8>:101 [#uses=1]
+ sext i8 %101 to i64 ; <i64>:102 [#uses=1]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:103 [#uses=1]
+ call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %103, i64 %100, i64 %102 ) ; <i64>:104 [#uses=1]
+ icmp eq i64 %104, %100 ; <i1>:105 [#uses=1]
+ zext i1 %105 to i8 ; <i8>:106 [#uses=1]
+ zext i8 %106 to i32 ; <i32>:107 [#uses=1]
+ store i32 %107, i32* @ui, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8*, i8, i8) nounwind
+
+declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16*, i16, i16) nounwind
+
+declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind
+
+declare i64 @llvm.atomic.cmp.swap.i64.p0i64(i64*, i64, i64) nounwind
+
+define void @test_lock() nounwind {
+entry:
+ call i8 @llvm.atomic.swap.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:0 [#uses=1]
+ store i8 %0, i8* @sc, align 1
+ call i8 @llvm.atomic.swap.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:1 [#uses=1]
+ store i8 %1, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1]
+ call i16 @llvm.atomic.swap.i16.p0i16( i16* %2, i16 1 ) ; <i16>:3 [#uses=1]
+ store i16 %3, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1]
+ call i16 @llvm.atomic.swap.i16.p0i16( i16* %4, i16 1 ) ; <i16>:5 [#uses=1]
+ store i16 %5, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1]
+ call i32 @llvm.atomic.swap.i32.p0i32( i32* %6, i32 1 ) ; <i32>:7 [#uses=1]
+ store i32 %7, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1]
+ call i32 @llvm.atomic.swap.i32.p0i32( i32* %8, i32 1 ) ; <i32>:9 [#uses=1]
+ store i32 %9, i32* @ui, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:10 [#uses=1]
+ call i64 @llvm.atomic.swap.i64.p0i64( i64* %10, i64 1 ) ; <i64>:11 [#uses=1]
+ store i64 %11, i64* @sl, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:12 [#uses=1]
+ call i64 @llvm.atomic.swap.i64.p0i64( i64* %12, i64 1 ) ; <i64>:13 [#uses=1]
+ store i64 %13, i64* @ul, align 8
+ call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true, i1 false )
+ volatile store i8 0, i8* @sc, align 1
+ volatile store i8 0, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:14 [#uses=1]
+ volatile store i16 0, i16* %14, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:15 [#uses=1]
+ volatile store i16 0, i16* %15, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:16 [#uses=1]
+ volatile store i32 0, i32* %16, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:17 [#uses=1]
+ volatile store i32 0, i32* %17, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:18 [#uses=1]
+ volatile store i64 0, i64* %18, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:19 [#uses=1]
+ volatile store i64 0, i64* %19, align 8
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:20 [#uses=1]
+ volatile store i64 0, i64* %20, align 8
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:21 [#uses=1]
+ volatile store i64 0, i64* %21, align 8
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.swap.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.swap.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.swap.i64.p0i64(i64*, i64) nounwind
+
+declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind
diff --git a/test/CodeGen/PowerPC/Frames-alloca.ll b/test/CodeGen/PowerPC/Frames-alloca.ll
new file mode 100644
index 0000000..aed4fdb
--- /dev/null
+++ b/test/CodeGen/PowerPC/Frames-alloca.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32
+; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC64
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-NOFP
+; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-NOFP
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS-NOFP
+
+; CHECK-PPC32: stw r31, -4(r1)
+; CHECK-PPC32: lwz r1, 0(r1)
+; CHECK-PPC32: lwz r31, -4(r1)
+; CHECK-PPC32-NOFP: stw r31, -4(r1)
+; CHECK-PPC32-NOFP: lwz r1, 0(r1)
+; CHECK-PPC32-NOFP: lwz r31, -4(r1)
+; CHECK-PPC32-RS: stwu r1, -80(r1)
+; CHECK-PPC32-RS-NOFP: stwu r1, -80(r1)
+
+; CHECK-PPC64: std r31, -8(r1)
+; CHECK-PPC64: stdu r1, -128(r1)
+; CHECK-PPC64: ld r1, 0(r1)
+; CHECK-PPC64: ld r31, -8(r1)
+; CHECK-PPC64-NOFP: std r31, -8(r1)
+; CHECK-PPC64-NOFP: stdu r1, -128(r1)
+; CHECK-PPC64-NOFP: ld r1, 0(r1)
+; CHECK-PPC64-NOFP: ld r31, -8(r1)
+
+define i32* @f1(i32 %n) {
+ %tmp = alloca i32, i32 %n ; <i32*> [#uses=1]
+ ret i32* %tmp
+}
diff --git a/test/CodeGen/PowerPC/Frames-large.ll b/test/CodeGen/PowerPC/Frames-large.ll
new file mode 100644
index 0000000..302d3df
--- /dev/null
+++ b/test/CodeGen/PowerPC/Frames-large.ll
@@ -0,0 +1,52 @@
+; RUN: llvm-as < %s > %t.bc
+; RUN: llc < %t.bc -march=ppc32 | FileCheck %s -check-prefix=PPC32-NOFP
+; RUN: llc < %t.bc -march=ppc32 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-FP
+
+; RUN: llc < %t.bc -march=ppc64 | FileCheck %s -check-prefix=PPC64-NOFP
+; RUN: llc < %t.bc -march=ppc64 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-FP
+
+
+target triple = "powerpc-apple-darwin8"
+
+define i32* @f1() nounwind {
+ %tmp = alloca i32, i32 8191 ; <i32*> [#uses=1]
+ ret i32* %tmp
+}
+
+; PPC32-NOFP: _f1:
+; PPC32-NOFP: lis r0, -1
+; PPC32-NOFP: ori r0, r0, 32704
+; PPC32-NOFP: stwux r1, r1, r0
+; PPC32-NOFP: addi r3, r1, 68
+; PPC32-NOFP: lwz r1, 0(r1)
+; PPC32-NOFP: blr
+
+; PPC32-FP: _f1:
+; PPC32-FP: stw r31, -4(r1)
+; PPC32-FP: lis r0, -1
+; PPC32-FP: ori r0, r0, 32704
+; PPC32-FP: stwux r1, r1, r0
+; ...
+; PPC32-FP: lwz r1, 0(r1)
+; PPC32-FP: lwz r31, -4(r1)
+; PPC32-FP: blr
+
+
+; PPC64-NOFP: _f1:
+; PPC64-NOFP: lis r0, -1
+; PPC64-NOFP: ori r0, r0, 32656
+; PPC64-NOFP: stdux r1, r1, r0
+; PPC64-NOFP: addi r3, r1, 116
+; PPC64-NOFP: ld r1, 0(r1)
+; PPC64-NOFP: blr
+
+
+; PPC64-FP: _f1:
+; PPC64-FP: std r31, -8(r1)
+; PPC64-FP: lis r0, -1
+; PPC64-FP: ori r0, r0, 32640
+; PPC64-FP: stdux r1, r1, r0
+; ...
+; PPC64-FP: ld r1, 0(r1)
+; PPC64-FP: ld r31, -8(r1)
+; PPC64-FP: blr
diff --git a/test/CodeGen/PowerPC/Frames-leaf.ll b/test/CodeGen/PowerPC/Frames-leaf.ll
new file mode 100644
index 0000000..c2e1d6b
--- /dev/null
+++ b/test/CodeGen/PowerPC/Frames-leaf.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=ppc32 | \
+; RUN: not grep {stw r31, 20(r1)}
+; RUN: llc < %s -march=ppc32 | \
+; RUN: not grep {stwu r1, -.*(r1)}
+; RUN: llc < %s -march=ppc32 | \
+; RUN: not grep {addi r1, r1, }
+; RUN: llc < %s -march=ppc32 | \
+; RUN: not grep {lwz r31, 20(r1)}
+; RUN: llc < %s -march=ppc32 -disable-fp-elim | \
+; RUN: not grep {stw r31, 20(r1)}
+; RUN: llc < %s -march=ppc32 -disable-fp-elim | \
+; RUN: not grep {stwu r1, -.*(r1)}
+; RUN: llc < %s -march=ppc32 -disable-fp-elim | \
+; RUN: not grep {addi r1, r1, }
+; RUN: llc < %s -march=ppc32 -disable-fp-elim | \
+; RUN: not grep {lwz r31, 20(r1)}
+; RUN: llc < %s -march=ppc64 | \
+; RUN: not grep {std r31, 40(r1)}
+; RUN: llc < %s -march=ppc64 | \
+; RUN: not grep {stdu r1, -.*(r1)}
+; RUN: llc < %s -march=ppc64 | \
+; RUN: not grep {addi r1, r1, }
+; RUN: llc < %s -march=ppc64 | \
+; RUN: not grep {ld r31, 40(r1)}
+; RUN: llc < %s -march=ppc64 -disable-fp-elim | \
+; RUN: not grep {stw r31, 40(r1)}
+; RUN: llc < %s -march=ppc64 -disable-fp-elim | \
+; RUN: not grep {stdu r1, -.*(r1)}
+; RUN: llc < %s -march=ppc64 -disable-fp-elim | \
+; RUN: not grep {addi r1, r1, }
+; RUN: llc < %s -march=ppc64 -disable-fp-elim | \
+; RUN: not grep {ld r31, 40(r1)}
+
+define i32* @f1() {
+ %tmp = alloca i32, i32 2 ; <i32*> [#uses=1]
+ ret i32* %tmp
+}
diff --git a/test/CodeGen/PowerPC/Frames-small.ll b/test/CodeGen/PowerPC/Frames-small.ll
new file mode 100644
index 0000000..404fdd0
--- /dev/null
+++ b/test/CodeGen/PowerPC/Frames-small.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -o %t1
+; RUN not grep {stw r31, -4(r1)} %t1
+; RUN: grep {stwu r1, -16448(r1)} %t1
+; RUN: grep {addi r1, r1, 16448} %t1
+; RUN: llc < %s -march=ppc32 | \
+; RUN: not grep {lwz r31, -4(r1)}
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \
+; RUN: -o %t2
+; RUN: grep {stw r31, -4(r1)} %t2
+; RUN: grep {stwu r1, -16448(r1)} %t2
+; RUN: grep {addi r1, r1, 16448} %t2
+; RUN: grep {lwz r31, -4(r1)} %t2
+; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -o %t3
+; RUN: not grep {std r31, -8(r1)} %t3
+; RUN: grep {stdu r1, -16496(r1)} %t3
+; RUN: grep {addi r1, r1, 16496} %t3
+; RUN: not grep {ld r31, -8(r1)} %t3
+; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \
+; RUN: -o %t4
+; RUN: grep {std r31, -8(r1)} %t4
+; RUN: grep {stdu r1, -16512(r1)} %t4
+; RUN: grep {addi r1, r1, 16512} %t4
+; RUN: grep {ld r31, -8(r1)} %t4
+
+define i32* @f1() {
+ %tmp = alloca i32, i32 4095 ; <i32*> [#uses=1]
+ ret i32* %tmp
+}
+
diff --git a/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll b/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
new file mode 100644
index 0000000..0f7acac
--- /dev/null
+++ b/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | \
+; RUN: grep {stw r3, 32751}
+; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
+; RUN: grep {stw r3, 32751}
+; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
+; RUN: grep {std r2, 9024}
+
+define void @test() {
+ store i32 0, i32* inttoptr (i64 48725999 to i32*)
+ ret void
+}
+
+define void @test2() {
+ store i64 0, i64* inttoptr (i64 74560 to i64*)
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/addc.ll b/test/CodeGen/PowerPC/addc.ll
new file mode 100644
index 0000000..09a7fbd
--- /dev/null
+++ b/test/CodeGen/PowerPC/addc.ll
@@ -0,0 +1,26 @@
+; All of these should be codegen'd without loading immediates
+; RUN: llc < %s -march=ppc32 -o %t
+; RUN: grep addc %t | count 1
+; RUN: grep adde %t | count 1
+; RUN: grep addze %t | count 1
+; RUN: grep addme %t | count 1
+; RUN: grep addic %t | count 2
+
+define i64 @add_ll(i64 %a, i64 %b) {
+entry:
+ %tmp.2 = add i64 %b, %a ; <i64> [#uses=1]
+ ret i64 %tmp.2
+}
+
+define i64 @add_l_5(i64 %a) {
+entry:
+ %tmp.1 = add i64 %a, 5 ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
+define i64 @add_l_m5(i64 %a) {
+entry:
+ %tmp.1 = add i64 %a, -5 ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
diff --git a/test/CodeGen/PowerPC/addi-reassoc.ll b/test/CodeGen/PowerPC/addi-reassoc.ll
new file mode 100644
index 0000000..2b71ce6
--- /dev/null
+++ b/test/CodeGen/PowerPC/addi-reassoc.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=ppc32 | not grep addi
+
+ %struct.X = type { [5 x i8] }
+
+define i32 @test1([4 x i32]* %P, i32 %i) {
+ %tmp.2 = add i32 %i, 2 ; <i32> [#uses=1]
+ %tmp.4 = getelementptr [4 x i32]* %P, i32 %tmp.2, i32 1 ; <i32*> [#uses=1]
+ %tmp.5 = load i32* %tmp.4 ; <i32> [#uses=1]
+ ret i32 %tmp.5
+}
+
+define i32 @test2(%struct.X* %P, i32 %i) {
+ %tmp.2 = add i32 %i, 2 ; <i32> [#uses=1]
+ %tmp.5 = getelementptr %struct.X* %P, i32 %tmp.2, i32 0, i32 1 ; <i8*> [#uses=1]
+ %tmp.6 = load i8* %tmp.5 ; <i8> [#uses=1]
+ %tmp.7 = sext i8 %tmp.6 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp.7
+}
+
diff --git a/test/CodeGen/PowerPC/align.ll b/test/CodeGen/PowerPC/align.ll
new file mode 100644
index 0000000..109a837
--- /dev/null
+++ b/test/CodeGen/PowerPC/align.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -mtriple=powerpc-linux-gnu | FileCheck %s -check-prefix=ELF
+; RUN: llc < %s -mtriple=powerpc-apple-darwin9 | FileCheck %s -check-prefix=DARWIN
+
+@a = global i1 true
+; no alignment
+
+@b = global i8 1
+; no alignment
+
+@c = global i16 2
+;ELF: .align 1
+;ELF: c:
+;DARWIN: .align 1
+;DARWIN: _c:
+
+@d = global i32 3
+;ELF: .align 2
+;ELF: d:
+;DARWIN: .align 2
+;DARWIN: _d:
+
+@e = global i64 4
+;ELF: .align 3
+;ELF: e
+;DARWIN: .align 3
+;DARWIN: _e:
+
+@f = global float 5.0
+;ELF: .align 2
+;ELF: f:
+;DARWIN: .align 2
+;DARWIN: _f:
+
+@g = global double 6.0
+;ELF: .align 3
+;ELF: g:
+;DARWIN: .align 3
+;DARWIN: _g:
+
+@bar = common global [75 x i8] zeroinitializer, align 128
+;ELF: .comm bar,75,128
+;DARWIN: .comm _bar,75,7
diff --git a/test/CodeGen/PowerPC/and-branch.ll b/test/CodeGen/PowerPC/and-branch.ll
new file mode 100644
index 0000000..0484f88
--- /dev/null
+++ b/test/CodeGen/PowerPC/and-branch.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=ppc32 | not grep mfcr
+
+define void @foo(i32 %X, i32 %Y, i32 %Z) {
+entry:
+ %tmp = icmp eq i32 %X, 0 ; <i1> [#uses=1]
+ %tmp3 = icmp slt i32 %Y, 5 ; <i1> [#uses=1]
+ %tmp4 = and i1 %tmp3, %tmp ; <i1> [#uses=1]
+ br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
+cond_true: ; preds = %entry
+ %tmp5 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ ret void
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+declare i32 @bar(...)
+
diff --git a/test/CodeGen/PowerPC/and-elim.ll b/test/CodeGen/PowerPC/and-elim.ll
new file mode 100644
index 0000000..3685361
--- /dev/null
+++ b/test/CodeGen/PowerPC/and-elim.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=ppc32 | not grep rlwin
+
+define void @test(i8* %P) {
+ %W = load i8* %P
+ %X = shl i8 %W, 1
+ %Y = add i8 %X, 2
+ %Z = and i8 %Y, 254 ; dead and
+ store i8 %Z, i8* %P
+ ret void
+}
+
+define i16 @test2(i16 zeroext %crc) zeroext {
+ ; No and's should be needed for the i16s here.
+ %tmp.1 = lshr i16 %crc, 1
+ %tmp.7 = xor i16 %tmp.1, 40961
+ ret i16 %tmp.7
+}
+
diff --git a/test/CodeGen/PowerPC/and-imm.ll b/test/CodeGen/PowerPC/and-imm.ll
new file mode 100644
index 0000000..64a45e5
--- /dev/null
+++ b/test/CodeGen/PowerPC/and-imm.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=ppc32 | not grep {ori\\|lis}
+
+; andi. r3, r3, 32769
+define i32 @test(i32 %X) {
+ %Y = and i32 %X, 32769 ; <i32> [#uses=1]
+ ret i32 %Y
+}
+
+; andis. r3, r3, 32769
+define i32 @test2(i32 %X) {
+ %Y = and i32 %X, -2147418112 ; <i32> [#uses=1]
+ ret i32 %Y
+}
+
diff --git a/test/CodeGen/PowerPC/and_add.ll b/test/CodeGen/PowerPC/and_add.ll
new file mode 100644
index 0000000..517e775
--- /dev/null
+++ b/test/CodeGen/PowerPC/and_add.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=ppc32 -o %t
+; RUN: grep slwi %t
+; RUN: not grep addi %t
+; RUN: not grep rlwinm %t
+
+define i32 @test(i32 %A) {
+ ;; shift
+ %B = mul i32 %A, 8 ; <i32> [#uses=1]
+ ;; dead, no demanded bits.
+ %C = add i32 %B, 7 ; <i32> [#uses=1]
+ ;; dead once add is gone.
+ %D = and i32 %C, -8 ; <i32> [#uses=1]
+ ret i32 %D
+}
+
diff --git a/test/CodeGen/PowerPC/and_sext.ll b/test/CodeGen/PowerPC/and_sext.ll
new file mode 100644
index 0000000..c6d234ea
--- /dev/null
+++ b/test/CodeGen/PowerPC/and_sext.ll
@@ -0,0 +1,28 @@
+; These tests should not contain a sign extend.
+; RUN: llc < %s -march=ppc32 | not grep extsh
+; RUN: llc < %s -march=ppc32 | not grep extsb
+
+define i32 @test1(i32 %mode.0.i.0) {
+ %tmp.79 = trunc i32 %mode.0.i.0 to i16
+ %tmp.80 = sext i16 %tmp.79 to i32
+ %tmp.81 = and i32 %tmp.80, 24
+ ret i32 %tmp.81
+}
+
+define i16 @test2(i16 signext %X, i16 signext %x) signext {
+ %tmp = sext i16 %X to i32
+ %tmp1 = sext i16 %x to i32
+ %tmp2 = add i32 %tmp, %tmp1
+ %tmp4 = ashr i32 %tmp2, 1
+ %tmp5 = trunc i32 %tmp4 to i16
+ %tmp45 = sext i16 %tmp5 to i32
+ %retval = trunc i32 %tmp45 to i16
+ ret i16 %retval
+}
+
+define i16 @test3(i32 zeroext %X) signext {
+ %tmp1 = lshr i32 %X, 16
+ %tmp2 = trunc i32 %tmp1 to i16
+ ret i16 %tmp2
+}
+
diff --git a/test/CodeGen/PowerPC/and_sra.ll b/test/CodeGen/PowerPC/and_sra.ll
new file mode 100644
index 0000000..e6c02d8
--- /dev/null
+++ b/test/CodeGen/PowerPC/and_sra.ll
@@ -0,0 +1,27 @@
+; Neither of these functions should contain algebraic right shifts
+; RUN: llc < %s -march=ppc32 | not grep srawi
+
+define i32 @test1(i32 %mode.0.i.0) {
+ %tmp.79 = bitcast i32 %mode.0.i.0 to i32 ; <i32> [#uses=1]
+ %tmp.80 = ashr i32 %tmp.79, 15 ; <i32> [#uses=1]
+ %tmp.81 = and i32 %tmp.80, 24 ; <i32> [#uses=1]
+ ret i32 %tmp.81
+}
+
+define i32 @test2(i32 %mode.0.i.0) {
+ %tmp.79 = bitcast i32 %mode.0.i.0 to i32 ; <i32> [#uses=1]
+ %tmp.80 = ashr i32 %tmp.79, 15 ; <i32> [#uses=1]
+ %tmp.81 = lshr i32 %mode.0.i.0, 16 ; <i32> [#uses=1]
+ %tmp.82 = bitcast i32 %tmp.81 to i32 ; <i32> [#uses=1]
+ %tmp.83 = and i32 %tmp.80, %tmp.82 ; <i32> [#uses=1]
+ ret i32 %tmp.83
+}
+
+define i32 @test3(i32 %specbits.6.1) {
+ %tmp.2540 = ashr i32 %specbits.6.1, 11 ; <i32> [#uses=1]
+ %tmp.2541 = bitcast i32 %tmp.2540 to i32 ; <i32> [#uses=1]
+ %tmp.2542 = shl i32 %tmp.2541, 13 ; <i32> [#uses=1]
+ %tmp.2543 = and i32 %tmp.2542, 8192 ; <i32> [#uses=1]
+ ret i32 %tmp.2543
+}
+
diff --git a/test/CodeGen/PowerPC/atomic-1.ll b/test/CodeGen/PowerPC/atomic-1.ll
new file mode 100644
index 0000000..ec4e42d
--- /dev/null
+++ b/test/CodeGen/PowerPC/atomic-1.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=ppc32 | grep lwarx | count 3
+; RUN: llc < %s -march=ppc32 | grep stwcx. | count 4
+
+define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind {
+ %tmp = call i32 @llvm.atomic.load.add.i32( i32* %mem, i32 %val )
+ ret i32 %tmp
+}
+
+define i32 @exchange_and_cmp(i32* %mem) nounwind {
+ %tmp = call i32 @llvm.atomic.cmp.swap.i32( i32* %mem, i32 0, i32 1 )
+ ret i32 %tmp
+}
+
+define i32 @exchange(i32* %mem, i32 %val) nounwind {
+ %tmp = call i32 @llvm.atomic.swap.i32( i32* %mem, i32 1 )
+ ret i32 %tmp
+}
+
+declare i32 @llvm.atomic.load.add.i32(i32*, i32) nounwind
+declare i32 @llvm.atomic.cmp.swap.i32(i32*, i32, i32) nounwind
+declare i32 @llvm.atomic.swap.i32(i32*, i32) nounwind
diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll
new file mode 100644
index 0000000..6d9daef
--- /dev/null
+++ b/test/CodeGen/PowerPC/atomic-2.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=ppc64 | grep ldarx | count 3
+; RUN: llc < %s -march=ppc64 | grep stdcx. | count 4
+
+define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
+ %tmp = call i64 @llvm.atomic.load.add.i64( i64* %mem, i64 %val )
+ ret i64 %tmp
+}
+
+define i64 @exchange_and_cmp(i64* %mem) nounwind {
+ %tmp = call i64 @llvm.atomic.cmp.swap.i64( i64* %mem, i64 0, i64 1 )
+ ret i64 %tmp
+}
+
+define i64 @exchange(i64* %mem, i64 %val) nounwind {
+ %tmp = call i64 @llvm.atomic.swap.i64( i64* %mem, i64 1 )
+ ret i64 %tmp
+}
+
+declare i64 @llvm.atomic.load.add.i64(i64*, i64) nounwind
+declare i64 @llvm.atomic.cmp.swap.i64(i64*, i64, i64) nounwind
+declare i64 @llvm.atomic.swap.i64(i64*, i64) nounwind
diff --git a/test/CodeGen/PowerPC/available-externally.ll b/test/CodeGen/PowerPC/available-externally.ll
new file mode 100644
index 0000000..fdead7d
--- /dev/null
+++ b/test/CodeGen/PowerPC/available-externally.ll
@@ -0,0 +1,71 @@
+; RUN: llc < %s -relocation-model=static | FileCheck %s -check-prefix=STATIC
+; RUN: llc < %s -relocation-model=pic | FileCheck %s -check-prefix=PIC
+; RUN: llc < %s -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DYNAMIC
+; PR4482
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "powerpc-apple-darwin8"
+
+define i32 @foo(i64 %x) nounwind {
+entry:
+; STATIC: _foo:
+; STATIC: bl _exact_log2
+; STATIC: blr
+; STATIC: .subsections_via_symbols
+
+; PIC: _foo:
+; PIC: bl L_exact_log2$stub
+; PIC: blr
+
+; DYNAMIC: _foo:
+; DYNAMIC: bl L_exact_log2$stub
+; DYNAMIC: blr
+
+ %A = call i32 @exact_log2(i64 %x) nounwind
+ ret i32 %A
+}
+
+define available_externally i32 @exact_log2(i64 %x) nounwind {
+entry:
+ ret i32 42
+}
+
+
+; PIC: .section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
+; PIC: L_exact_log2$stub:
+; PIC: .indirect_symbol _exact_log2
+; PIC: mflr r0
+; PIC: bcl 20,31,L_exact_log2$stub$tmp
+
+; PIC: L_exact_log2$stub$tmp:
+; PIC: mflr r11
+; PIC: addis r11,r11,ha16(L_exact_log2$lazy_ptr-L_exact_log2$stub$tmp)
+; PIC: mtlr r0
+; PIC: lwzu r12,lo16(L_exact_log2$lazy_ptr-L_exact_log2$stub$tmp)(r11)
+; PIC: mtctr r12
+; PIC: bctr
+
+; PIC: .section __DATA,__la_symbol_ptr,lazy_symbol_pointers
+; PIC: L_exact_log2$lazy_ptr:
+; PIC: .indirect_symbol _exact_log2
+; PIC: .long dyld_stub_binding_helper
+
+; PIC: .subsections_via_symbols
+
+
+; DYNAMIC: .section __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16
+; DYNAMIC: L_exact_log2$stub:
+; DYNAMIC: .indirect_symbol _exact_log2
+; DYNAMIC: lis r11,ha16(L_exact_log2$lazy_ptr)
+; DYNAMIC: lwzu r12,lo16(L_exact_log2$lazy_ptr)(r11)
+; DYNAMIC: mtctr r12
+; DYNAMIC: bctr
+
+; DYNAMIC: .section __DATA,__la_symbol_ptr,lazy_symbol_pointers
+; DYNAMIC: L_exact_log2$lazy_ptr:
+; DYNAMIC: .indirect_symbol _exact_log2
+; DYNAMIC: .long dyld_stub_binding_helper
+
+
+
+
+
diff --git a/test/CodeGen/PowerPC/big-endian-actual-args.ll b/test/CodeGen/PowerPC/big-endian-actual-args.ll
new file mode 100644
index 0000000..009f468
--- /dev/null
+++ b/test/CodeGen/PowerPC/big-endian-actual-args.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: grep {addc 4, 4, 6}
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: grep {adde 3, 3, 5}
+
+define i64 @foo(i64 %x, i64 %y) {
+ %z = add i64 %x, %y
+ ret i64 %z
+}
diff --git a/test/CodeGen/PowerPC/big-endian-call-result.ll b/test/CodeGen/PowerPC/big-endian-call-result.ll
new file mode 100644
index 0000000..fe85404
--- /dev/null
+++ b/test/CodeGen/PowerPC/big-endian-call-result.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: grep {addic 4, 4, 1}
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: grep {addze 3, 3}
+
+declare i64 @foo()
+
+define i64 @bar()
+{
+ %t = call i64 @foo()
+ %s = add i64 %t, 1
+ ret i64 %s
+}
diff --git a/test/CodeGen/PowerPC/big-endian-formal-args.ll b/test/CodeGen/PowerPC/big-endian-formal-args.ll
new file mode 100644
index 0000000..e46e1ec
--- /dev/null
+++ b/test/CodeGen/PowerPC/big-endian-formal-args.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: grep {li 6, 3}
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: grep {li 4, 2}
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: grep {li 3, 0}
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
+; RUN: grep {mr 5, 3}
+
+declare void @bar(i64 %x, i64 %y)
+
+define void @foo() {
+ call void @bar(i64 2, i64 3)
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/branch-opt.ll b/test/CodeGen/PowerPC/branch-opt.ll
new file mode 100644
index 0000000..cc02e40
--- /dev/null
+++ b/test/CodeGen/PowerPC/branch-opt.ll
@@ -0,0 +1,71 @@
+; RUN: llc < %s -march=ppc32 | \
+; RUN: grep {b LBB.*} | count 4
+
+target datalayout = "E-p:32:32"
+target triple = "powerpc-apple-darwin8.7.0"
+
+define void @foo(i32 %W, i32 %X, i32 %Y, i32 %Z) {
+entry:
+ %tmp1 = and i32 %W, 1 ; <i32> [#uses=1]
+ %tmp1.upgrd.1 = icmp eq i32 %tmp1, 0 ; <i1> [#uses=1]
+ br i1 %tmp1.upgrd.1, label %cond_false, label %bb5
+bb: ; preds = %bb5, %bb
+ %indvar77 = phi i32 [ %indvar.next78, %bb ], [ 0, %bb5 ] ; <i32> [#uses=1]
+ %tmp2 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ %indvar.next78 = add i32 %indvar77, 1 ; <i32> [#uses=2]
+ %exitcond79 = icmp eq i32 %indvar.next78, %X ; <i1> [#uses=1]
+ br i1 %exitcond79, label %cond_next48, label %bb
+bb5: ; preds = %entry
+ %tmp = icmp eq i32 %X, 0 ; <i1> [#uses=1]
+ br i1 %tmp, label %cond_next48, label %bb
+cond_false: ; preds = %entry
+ %tmp10 = and i32 %W, 2 ; <i32> [#uses=1]
+ %tmp10.upgrd.2 = icmp eq i32 %tmp10, 0 ; <i1> [#uses=1]
+ br i1 %tmp10.upgrd.2, label %cond_false20, label %bb16
+bb12: ; preds = %bb16, %bb12
+ %indvar72 = phi i32 [ %indvar.next73, %bb12 ], [ 0, %bb16 ] ; <i32> [#uses=1]
+ %tmp13 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ %indvar.next73 = add i32 %indvar72, 1 ; <i32> [#uses=2]
+ %exitcond74 = icmp eq i32 %indvar.next73, %Y ; <i1> [#uses=1]
+ br i1 %exitcond74, label %cond_next48, label %bb12
+bb16: ; preds = %cond_false
+ %tmp18 = icmp eq i32 %Y, 0 ; <i1> [#uses=1]
+ br i1 %tmp18, label %cond_next48, label %bb12
+cond_false20: ; preds = %cond_false
+ %tmp23 = and i32 %W, 4 ; <i32> [#uses=1]
+ %tmp23.upgrd.3 = icmp eq i32 %tmp23, 0 ; <i1> [#uses=1]
+ br i1 %tmp23.upgrd.3, label %cond_false33, label %bb29
+bb25: ; preds = %bb29, %bb25
+ %indvar67 = phi i32 [ %indvar.next68, %bb25 ], [ 0, %bb29 ] ; <i32> [#uses=1]
+ %tmp26 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ %indvar.next68 = add i32 %indvar67, 1 ; <i32> [#uses=2]
+ %exitcond69 = icmp eq i32 %indvar.next68, %Z ; <i1> [#uses=1]
+ br i1 %exitcond69, label %cond_next48, label %bb25
+bb29: ; preds = %cond_false20
+ %tmp31 = icmp eq i32 %Z, 0 ; <i1> [#uses=1]
+ br i1 %tmp31, label %cond_next48, label %bb25
+cond_false33: ; preds = %cond_false20
+ %tmp36 = and i32 %W, 8 ; <i32> [#uses=1]
+ %tmp36.upgrd.4 = icmp eq i32 %tmp36, 0 ; <i1> [#uses=1]
+ br i1 %tmp36.upgrd.4, label %cond_next48, label %bb42
+bb38: ; preds = %bb42
+ %tmp39 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br label %bb42
+bb42: ; preds = %bb38, %cond_false33
+ %indvar = phi i32 [ %indvar.next, %bb38 ], [ 0, %cond_false33 ] ; <i32> [#uses=4]
+ %W_addr.0 = sub i32 %W, %indvar ; <i32> [#uses=1]
+ %exitcond = icmp eq i32 %indvar, %W ; <i1> [#uses=1]
+ br i1 %exitcond, label %cond_next48, label %bb38
+cond_next48: ; preds = %bb42, %cond_false33, %bb29, %bb25, %bb16, %bb12, %bb5, %bb
+ %W_addr.1 = phi i32 [ %W, %bb5 ], [ %W, %bb16 ], [ %W, %bb29 ], [ %W, %cond_false33 ], [ %W_addr.0, %bb42 ], [ %W, %bb25 ], [ %W, %bb12 ], [ %W, %bb ] ; <i32> [#uses=1]
+ %tmp50 = icmp eq i32 %W_addr.1, 0 ; <i1> [#uses=1]
+ br i1 %tmp50, label %UnifiedReturnBlock, label %cond_true51
+cond_true51: ; preds = %cond_next48
+ %tmp52 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ ret void
+UnifiedReturnBlock: ; preds = %cond_next48
+ ret void
+}
+
+declare i32 @bar(...)
diff --git a/test/CodeGen/PowerPC/bswap-load-store.ll b/test/CodeGen/PowerPC/bswap-load-store.ll
new file mode 100644
index 0000000..4f6bfc7
--- /dev/null
+++ b/test/CodeGen/PowerPC/bswap-load-store.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -march=ppc32 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -march=ppc64 | FileCheck %s -check-prefix=X64
+
+
+define void @STWBRX(i32 %i, i8* %ptr, i32 %off) {
+ %tmp1 = getelementptr i8* %ptr, i32 %off ; <i8*> [#uses=1]
+ %tmp1.upgrd.1 = bitcast i8* %tmp1 to i32* ; <i32*> [#uses=1]
+ %tmp13 = tail call i32 @llvm.bswap.i32( i32 %i ) ; <i32> [#uses=1]
+ store i32 %tmp13, i32* %tmp1.upgrd.1
+ ret void
+}
+
+define i32 @LWBRX(i8* %ptr, i32 %off) {
+ %tmp1 = getelementptr i8* %ptr, i32 %off ; <i8*> [#uses=1]
+ %tmp1.upgrd.2 = bitcast i8* %tmp1 to i32* ; <i32*> [#uses=1]
+ %tmp = load i32* %tmp1.upgrd.2 ; <i32> [#uses=1]
+ %tmp14 = tail call i32 @llvm.bswap.i32( i32 %tmp ) ; <i32> [#uses=1]
+ ret i32 %tmp14
+}
+
+define void @STHBRX(i16 %s, i8* %ptr, i32 %off) {
+ %tmp1 = getelementptr i8* %ptr, i32 %off ; <i8*> [#uses=1]
+ %tmp1.upgrd.3 = bitcast i8* %tmp1 to i16* ; <i16*> [#uses=1]
+ %tmp5 = call i16 @llvm.bswap.i16( i16 %s ) ; <i16> [#uses=1]
+ store i16 %tmp5, i16* %tmp1.upgrd.3
+ ret void
+}
+
+define i16 @LHBRX(i8* %ptr, i32 %off) {
+ %tmp1 = getelementptr i8* %ptr, i32 %off ; <i8*> [#uses=1]
+ %tmp1.upgrd.4 = bitcast i8* %tmp1 to i16* ; <i16*> [#uses=1]
+ %tmp = load i16* %tmp1.upgrd.4 ; <i16> [#uses=1]
+ %tmp6 = call i16 @llvm.bswap.i16( i16 %tmp ) ; <i16> [#uses=1]
+ ret i16 %tmp6
+}
+
+declare i32 @llvm.bswap.i32(i32)
+
+declare i16 @llvm.bswap.i16(i16)
+
+
+; X32: stwbrx
+; X32: lwbrx
+; X32: sthbrx
+; X32: lhbrx
+
+; X64: stwbrx
+; X64: lwbrx
+; X64: sthbrx
+; X64: lhbrx
+
diff --git a/test/CodeGen/PowerPC/buildvec_canonicalize.ll b/test/CodeGen/PowerPC/buildvec_canonicalize.ll
new file mode 100644
index 0000000..0454c58
--- /dev/null
+++ b/test/CodeGen/PowerPC/buildvec_canonicalize.ll
@@ -0,0 +1,24 @@
+; There should be exactly one vxor here.
+; RUN: llc < %s -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \
+; RUN: grep vxor | count 1
+
+; There should be exactly one vsplti here.
+; RUN: llc < %s -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \
+; RUN: grep vsplti | count 1
+
+define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
+ %tmp = load <4 x float>* %P3 ; <<4 x float>> [#uses=1]
+ %tmp3 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1]
+ %tmp4 = fmul <4 x float> %tmp, %tmp3 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp4, <4 x float>* %P3
+ store <4 x float> zeroinitializer, <4 x float>* %P1
+ store <4 x i32> zeroinitializer, <4 x i32>* %P2
+ ret void
+}
+
+define void @VSPLTI(<4 x i32>* %P2, <8 x i16>* %P3) {
+ store <4 x i32> bitcast (<16 x i8> < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > to <4 x i32>), <4 x i32>* %P2
+ store <8 x i16> < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >, <8 x i16>* %P3
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/calls.ll b/test/CodeGen/PowerPC/calls.ll
new file mode 100644
index 0000000..0db184f
--- /dev/null
+++ b/test/CodeGen/PowerPC/calls.ll
@@ -0,0 +1,32 @@
+; Test various forms of calls.
+
+; RUN: llc < %s -march=ppc32 | \
+; RUN: grep {bl } | count 2
+; RUN: llc < %s -march=ppc32 | \
+; RUN: grep {bctrl} | count 1
+; RUN: llc < %s -march=ppc32 | \
+; RUN: grep {bla } | count 1
+
+declare void @foo()
+
+define void @test_direct() {
+ call void @foo( )
+ ret void
+}
+
+define void @test_extsym(i8* %P) {
+ free i8* %P
+ ret void
+}
+
+define void @test_indirect(void ()* %fp) {
+ call void %fp( )
+ ret void
+}
+
+define void @test_abs() {
+ %fp = inttoptr i32 400 to void ()* ; <void ()*> [#uses=1]
+ call void %fp( )
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/cmp-cmp.ll b/test/CodeGen/PowerPC/cmp-cmp.ll
new file mode 100644
index 0000000..35a5e42
--- /dev/null
+++ b/test/CodeGen/PowerPC/cmp-cmp.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=ppc32 | not grep mfcr
+
+define void @test(i64 %X) {
+ %tmp1 = and i64 %X, 3 ; <i64> [#uses=1]
+ %tmp = icmp sgt i64 %tmp1, 2 ; <i1> [#uses=1]
+ br i1 %tmp, label %UnifiedReturnBlock, label %cond_true
+cond_true: ; preds = %0
+ tail call void @test( i64 0 )
+ ret void
+UnifiedReturnBlock: ; preds = %0
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/compare-duplicate.ll b/test/CodeGen/PowerPC/compare-duplicate.ll
new file mode 100644
index 0000000..f5108c3
--- /dev/null
+++ b/test/CodeGen/PowerPC/compare-duplicate.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin8 | not grep slwi
+
+define i32 @test(i32 %A, i32 %B) {
+ %C = sub i32 %B, %A
+ %D = icmp eq i32 %C, %A
+ br i1 %D, label %T, label %F
+T:
+ ret i32 19123
+F:
+ ret i32 %C
+}
diff --git a/test/CodeGen/PowerPC/compare-simm.ll b/test/CodeGen/PowerPC/compare-simm.ll
new file mode 100644
index 0000000..5ba0500
--- /dev/null
+++ b/test/CodeGen/PowerPC/compare-simm.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
+; RUN: grep {cmpwi cr0, r3, -1}
+
+define i32 @test(i32 %x) {
+ %c = icmp eq i32 %x, -1
+ br i1 %c, label %T, label %F
+T:
+ %A = call i32 @test(i32 123)
+ %B = add i32 %A, 43
+ ret i32 %B
+F:
+ %G = add i32 %x, 1234
+ ret i32 %G
+}
diff --git a/test/CodeGen/PowerPC/constants.ll b/test/CodeGen/PowerPC/constants.ll
new file mode 100644
index 0000000..8901e02
--- /dev/null
+++ b/test/CodeGen/PowerPC/constants.ll
@@ -0,0 +1,52 @@
+; All of these routines should be perform optimal load of constants.
+; RUN: llc < %s -march=ppc32 | \
+; RUN: grep lis | count 5
+; RUN: llc < %s -march=ppc32 | \
+; RUN: grep ori | count 3
+; RUN: llc < %s -march=ppc32 | \
+; RUN: grep {li } | count 4
+
+define i32 @f1() {
+entry:
+ ret i32 1
+}
+
+define i32 @f2() {
+entry:
+ ret i32 -1
+}
+
+define i32 @f3() {
+entry:
+ ret i32 0
+}
+
+define i32 @f4() {
+entry:
+ ret i32 32767
+}
+
+define i32 @f5() {
+entry:
+ ret i32 65535
+}
+
+define i32 @f6() {
+entry:
+ ret i32 65536
+}
+
+define i32 @f7() {
+entry:
+ ret i32 131071
+}
+
+define i32 @f8() {
+entry:
+ ret i32 2147483647
+}
+
+define i32 @f9() {
+entry:
+ ret i32 -2147483648
+}
diff --git a/test/CodeGen/PowerPC/cr_spilling.ll b/test/CodeGen/PowerPC/cr_spilling.ll
new file mode 100644
index 0000000..b215868
--- /dev/null
+++ b/test/CodeGen/PowerPC/cr_spilling.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o -
+; PR1638
+
[email protected] = external constant [3 x i8] ; <[3 x i8]*> [#uses=1]
+
+define fastcc void @ParseContent(i8* %buf, i32 %bufsize) {
+entry:
+ %items = alloca [10000 x i8*], align 16 ; <[10000 x i8*]*> [#uses=0]
+ %tmp86 = add i32 0, -1 ; <i32> [#uses=1]
+ br i1 false, label %cond_true94, label %cond_next99
+
+cond_true94: ; preds = %entry
+ %tmp98 = call i32 (i8*, ...)* @printf(i8* getelementptr ([3 x i8]* @.str242, i32 0, i32 0), i8* null) ; <i32> [#uses=0]
+ %tmp20971 = icmp sgt i32 %tmp86, 0 ; <i1> [#uses=1]
+ br i1 %tmp20971, label %bb101, label %bb212
+
+cond_next99: ; preds = %entry
+ ret void
+
+bb101: ; preds = %cond_true94
+ ret void
+
+bb212: ; preds = %cond_true94
+ ret void
+}
+
+declare i32 @printf(i8*, ...)
diff --git a/test/CodeGen/PowerPC/cttz.ll b/test/CodeGen/PowerPC/cttz.ll
new file mode 100644
index 0000000..ab493a0
--- /dev/null
+++ b/test/CodeGen/PowerPC/cttz.ll
@@ -0,0 +1,11 @@
+; Make sure this testcase does not use ctpop
+; RUN: llc < %s -march=ppc32 | grep -i cntlzw
+
+declare i32 @llvm.cttz.i32(i32)
+
+define i32 @bar(i32 %x) {
+entry:
+ %tmp.1 = call i32 @llvm.cttz.i32( i32 %x ) ; <i32> [#uses=1]
+ ret i32 %tmp.1
+}
+
diff --git a/test/CodeGen/PowerPC/darwin-labels.ll b/test/CodeGen/PowerPC/darwin-labels.ll
new file mode 100644
index 0000000..af23369
--- /dev/null
+++ b/test/CodeGen/PowerPC/darwin-labels.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s | grep {foo bar":}
+
+target datalayout = "E-p:32:32"
+target triple = "powerpc-apple-darwin8.2.0"
+@"foo bar" = global i32 4 ; <i32*> [#uses=0]
+
diff --git a/test/CodeGen/PowerPC/delete-node.ll b/test/CodeGen/PowerPC/delete-node.ll
new file mode 100644
index 0000000..a26c211
--- /dev/null
+++ b/test/CodeGen/PowerPC/delete-node.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=ppc32
+
+; The DAGCombiner leaves behind a dead node in this testcase. Currently
+; ISel is ignoring dead nodes, though it would be preferable for
+; DAGCombiner to be able to eliminate the dead node.
+
+define void @GrayATo32ARGBTabB(i8* %baseAddr, i16** %cmp, i32 %rowBytes) nounwind {
+entry:
+ br label %bb1
+
+bb1: ; preds = %bb1, %entry
+ %0 = load i16* null, align 2 ; <i16> [#uses=1]
+ %1 = ashr i16 %0, 4 ; <i16> [#uses=1]
+ %2 = sext i16 %1 to i32 ; <i32> [#uses=1]
+ %3 = getelementptr i8* null, i32 %2 ; <i8*> [#uses=1]
+ %4 = load i8* %3, align 1 ; <i8> [#uses=1]
+ %5 = zext i8 %4 to i32 ; <i32> [#uses=1]
+ %6 = shl i32 %5, 24 ; <i32> [#uses=1]
+ %7 = or i32 0, %6 ; <i32> [#uses=1]
+ store i32 %7, i32* null, align 4
+ br label %bb1
+}
diff --git a/test/CodeGen/PowerPC/dg.exp b/test/CodeGen/PowerPC/dg.exp
new file mode 100644
index 0000000..9e50b55
--- /dev/null
+++ b/test/CodeGen/PowerPC/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target PowerPC] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/PowerPC/div-2.ll b/test/CodeGen/PowerPC/div-2.ll
new file mode 100644
index 0000000..2fc916f
--- /dev/null
+++ b/test/CodeGen/PowerPC/div-2.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=ppc32 | not grep srawi
+; RUN: llc < %s -march=ppc32 | grep blr
+
+define i32 @test1(i32 %X) {
+ %Y = and i32 %X, 15 ; <i32> [#uses=1]
+ %Z = sdiv i32 %Y, 4 ; <i32> [#uses=1]
+ ret i32 %Z
+}
+
+define i32 @test2(i32 %W) {
+ %X = and i32 %W, 15 ; <i32> [#uses=1]
+ %Y = sub i32 16, %X ; <i32> [#uses=1]
+ %Z = sdiv i32 %Y, 4 ; <i32> [#uses=1]
+ ret i32 %Z
+}
+
+define i32 @test3(i32 %W) {
+ %X = and i32 %W, 15 ; <i32> [#uses=1]
+ %Y = sub i32 15, %X ; <i32> [#uses=1]
+ %Z = sdiv i32 %Y, 4 ; <i32> [#uses=1]
+ ret i32 %Z
+}
+
+define i32 @test4(i32 %W) {
+ %X = and i32 %W, 2 ; <i32> [#uses=1]
+ %Y = sub i32 5, %X ; <i32> [#uses=1]
+ %Z = sdiv i32 %Y, 2 ; <i32> [#uses=1]
+ ret i32 %Z
+}
+
diff --git a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
new file mode 100644
index 0000000..558fd1b
--- /dev/null
+++ b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
@@ -0,0 +1,93 @@
+; RUN: llc < %s -march=ppc32 | \
+; RUN: grep eqv | count 3
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
+; RUN: grep andc | count 3
+; RUN: llc < %s -march=ppc32 | \
+; RUN: grep orc | count 2
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
+; RUN: grep nor | count 3
+; RUN: llc < %s -march=ppc32 | \
+; RUN: grep nand | count 1
+
+define i32 @EQV1(i32 %X, i32 %Y) {
+ %A = xor i32 %X, %Y ; <i32> [#uses=1]
+ %B = xor i32 %A, -1 ; <i32> [#uses=1]
+ ret i32 %B
+}
+
+define i32 @EQV2(i32 %X, i32 %Y) {
+ %A = xor i32 %X, -1 ; <i32> [#uses=1]
+ %B = xor i32 %A, %Y ; <i32> [#uses=1]
+ ret i32 %B
+}
+
+define i32 @EQV3(i32 %X, i32 %Y) {
+ %A = xor i32 %X, -1 ; <i32> [#uses=1]
+ %B = xor i32 %Y, %A ; <i32> [#uses=1]
+ ret i32 %B
+}
+
+define i32 @ANDC1(i32 %X, i32 %Y) {
+ %A = xor i32 %Y, -1 ; <i32> [#uses=1]
+ %B = and i32 %X, %A ; <i32> [#uses=1]
+ ret i32 %B
+}
+
+define i32 @ANDC2(i32 %X, i32 %Y) {
+ %A = xor i32 %X, -1 ; <i32> [#uses=1]
+ %B = and i32 %A, %Y ; <i32> [#uses=1]
+ ret i32 %B
+}
+
+define i32 @ORC1(i32 %X, i32 %Y) {
+ %A = xor i32 %Y, -1 ; <i32> [#uses=1]
+ %B = or i32 %X, %A ; <i32> [#uses=1]
+ ret i32 %B
+}
+
+define i32 @ORC2(i32 %X, i32 %Y) {
+ %A = xor i32 %X, -1 ; <i32> [#uses=1]
+ %B = or i32 %A, %Y ; <i32> [#uses=1]
+ ret i32 %B
+}
+
+define i32 @NOR1(i32 %X) {
+ %Y = xor i32 %X, -1 ; <i32> [#uses=1]
+ ret i32 %Y
+}
+
+define i32 @NOR2(i32 %X, i32 %Y) {
+ %Z = or i32 %X, %Y ; <i32> [#uses=1]
+ %R = xor i32 %Z, -1 ; <i32> [#uses=1]
+ ret i32 %R
+}
+
+define i32 @NAND1(i32 %X, i32 %Y) {
+ %Z = and i32 %X, %Y ; <i32> [#uses=1]
+ %W = xor i32 %Z, -1 ; <i32> [#uses=1]
+ ret i32 %W
+}
+
+define void @VNOR(<4 x float>* %P, <4 x float>* %Q) {
+ %tmp = load <4 x float>* %P ; <<4 x float>> [#uses=1]
+ %tmp.upgrd.1 = bitcast <4 x float> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp2 = load <4 x float>* %Q ; <<4 x float>> [#uses=1]
+ %tmp2.upgrd.2 = bitcast <4 x float> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp3 = or <4 x i32> %tmp.upgrd.1, %tmp2.upgrd.2 ; <<4 x i32>> [#uses=1]
+ %tmp4 = xor <4 x i32> %tmp3, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %tmp4.upgrd.3 = bitcast <4 x i32> %tmp4 to <4 x float> ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp4.upgrd.3, <4 x float>* %P
+ ret void
+}
+
+define void @VANDC(<4 x float>* %P, <4 x float>* %Q) {
+ %tmp = load <4 x float>* %P ; <<4 x float>> [#uses=1]
+ %tmp.upgrd.4 = bitcast <4 x float> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp2 = load <4 x float>* %Q ; <<4 x float>> [#uses=1]
+ %tmp2.upgrd.5 = bitcast <4 x float> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp4 = xor <4 x i32> %tmp2.upgrd.5, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %tmp3 = and <4 x i32> %tmp.upgrd.4, %tmp4 ; <<4 x i32>> [#uses=1]
+ %tmp4.upgrd.6 = bitcast <4 x i32> %tmp3 to <4 x float> ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp4.upgrd.6, <4 x float>* %P
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/extsh.ll b/test/CodeGen/PowerPC/extsh.ll
new file mode 100644
index 0000000..506ff86
--- /dev/null
+++ b/test/CodeGen/PowerPC/extsh.ll
@@ -0,0 +1,8 @@
+; This should turn into a single extsh
+; RUN: llc < %s -march=ppc32 | grep extsh | count 1
+define i32 @test(i32 %X) {
+ %tmp.81 = shl i32 %X, 16 ; <i32> [#uses=1]
+ %tmp.82 = ashr i32 %tmp.81, 16 ; <i32> [#uses=1]
+ ret i32 %tmp.82
+}
+
diff --git a/test/CodeGen/PowerPC/fabs.ll b/test/CodeGen/PowerPC/fabs.ll
new file mode 100644
index 0000000..6ef740f
--- /dev/null
+++ b/test/CodeGen/PowerPC/fabs.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | grep {fabs f1, f1}
+
+define double @fabs(double %f) {
+entry:
+ %tmp2 = tail call double @fabs( double %f ) ; <double> [#uses=1]
+ ret double %tmp2
+}
diff --git a/test/CodeGen/PowerPC/fma.ll b/test/CodeGen/PowerPC/fma.ll
new file mode 100644
index 0000000..815c72c
--- /dev/null
+++ b/test/CodeGen/PowerPC/fma.ll
@@ -0,0 +1,54 @@
+; RUN: llc < %s -march=ppc32 | \
+; RUN: egrep {fn?madd|fn?msub} | count 8
+
+define double @test_FMADD1(double %A, double %B, double %C) {
+ %D = fmul double %A, %B ; <double> [#uses=1]
+ %E = fadd double %D, %C ; <double> [#uses=1]
+ ret double %E
+}
+
+define double @test_FMADD2(double %A, double %B, double %C) {
+ %D = fmul double %A, %B ; <double> [#uses=1]
+ %E = fadd double %D, %C ; <double> [#uses=1]
+ ret double %E
+}
+
+define double @test_FMSUB(double %A, double %B, double %C) {
+ %D = fmul double %A, %B ; <double> [#uses=1]
+ %E = fsub double %D, %C ; <double> [#uses=1]
+ ret double %E
+}
+
+define double @test_FNMADD1(double %A, double %B, double %C) {
+ %D = fmul double %A, %B ; <double> [#uses=1]
+ %E = fadd double %D, %C ; <double> [#uses=1]
+ %F = fsub double -0.000000e+00, %E ; <double> [#uses=1]
+ ret double %F
+}
+
+define double @test_FNMADD2(double %A, double %B, double %C) {
+ %D = fmul double %A, %B ; <double> [#uses=1]
+ %E = fadd double %C, %D ; <double> [#uses=1]
+ %F = fsub double -0.000000e+00, %E ; <double> [#uses=1]
+ ret double %F
+}
+
+define double @test_FNMSUB1(double %A, double %B, double %C) {
+ %D = fmul double %A, %B ; <double> [#uses=1]
+ %E = fsub double %C, %D ; <double> [#uses=1]
+ ret double %E
+}
+
+define double @test_FNMSUB2(double %A, double %B, double %C) {
+ %D = fmul double %A, %B ; <double> [#uses=1]
+ %E = fsub double %D, %C ; <double> [#uses=1]
+ %F = fsub double -0.000000e+00, %E ; <double> [#uses=1]
+ ret double %F
+}
+
+define float @test_FNMSUBS(float %A, float %B, float %C) {
+ %D = fmul float %A, %B ; <float> [#uses=1]
+ %E = fsub float %D, %C ; <float> [#uses=1]
+ %F = fsub float -0.000000e+00, %E ; <float> [#uses=1]
+ ret float %F
+}
diff --git a/test/CodeGen/PowerPC/fnabs.ll b/test/CodeGen/PowerPC/fnabs.ll
new file mode 100644
index 0000000..bbd5c71
--- /dev/null
+++ b/test/CodeGen/PowerPC/fnabs.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=ppc32 | grep fnabs
+
+declare double @fabs(double)
+
+define double @test(double %X) {
+ %Y = call double @fabs( double %X ) ; <double> [#uses=1]
+ %Z = fsub double -0.000000e+00, %Y ; <double> [#uses=1]
+ ret double %Z
+}
+
diff --git a/test/CodeGen/PowerPC/fneg.ll b/test/CodeGen/PowerPC/fneg.ll
new file mode 100644
index 0000000..0bd31bb
--- /dev/null
+++ b/test/CodeGen/PowerPC/fneg.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=ppc32 | not grep fneg
+
+define double @test1(double %a, double %b, double %c, double %d) {
+entry:
+ %tmp2 = fsub double -0.000000e+00, %c ; <double> [#uses=1]
+ %tmp4 = fmul double %tmp2, %d ; <double> [#uses=1]
+ %tmp7 = fmul double %a, %b ; <double> [#uses=1]
+ %tmp9 = fsub double %tmp7, %tmp4 ; <double> [#uses=1]
+ ret double %tmp9
+}
+
+
diff --git a/test/CodeGen/PowerPC/fold-li.ll b/test/CodeGen/PowerPC/fold-li.ll
new file mode 100644
index 0000000..92d8da5
--- /dev/null
+++ b/test/CodeGen/PowerPC/fold-li.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=ppc32 | \
+; RUN: grep -v align | not grep li
+
+;; Test that immediates are folded into these instructions correctly.
+
+define i32 @ADD(i32 %X) nounwind {
+ %Y = add i32 %X, 65537 ; <i32> [#uses=1]
+ ret i32 %Y
+}
+
+define i32 @SUB(i32 %X) nounwind {
+ %Y = sub i32 %X, 65537 ; <i32> [#uses=1]
+ ret i32 %Y
+}
+
diff --git a/test/CodeGen/PowerPC/fp-branch.ll b/test/CodeGen/PowerPC/fp-branch.ll
new file mode 100644
index 0000000..673da02
--- /dev/null
+++ b/test/CodeGen/PowerPC/fp-branch.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=ppc32 | grep fcmp | count 1
+
+declare i1 @llvm.isunordered.f64(double, double)
+
+define i1 @intcoord_cond_next55(double %tmp48.reload) {
+newFuncRoot:
+ br label %cond_next55
+
+bb72.exitStub: ; preds = %cond_next55
+ ret i1 true
+
+cond_next62.exitStub: ; preds = %cond_next55
+ ret i1 false
+
+cond_next55: ; preds = %newFuncRoot
+ %tmp57 = fcmp oge double %tmp48.reload, 1.000000e+00 ; <i1> [#uses=1]
+ %tmp58 = fcmp uno double %tmp48.reload, 1.000000e+00 ; <i1> [#uses=1]
+ %tmp59 = or i1 %tmp57, %tmp58 ; <i1> [#uses=1]
+ br i1 %tmp59, label %bb72.exitStub, label %cond_next62.exitStub
+}
+
diff --git a/test/CodeGen/PowerPC/fp-int-fp.ll b/test/CodeGen/PowerPC/fp-int-fp.ll
new file mode 100644
index 0000000..18f7f83
--- /dev/null
+++ b/test/CodeGen/PowerPC/fp-int-fp.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep r1
+
+define double @test1(double %X) {
+ %Y = fptosi double %X to i64 ; <i64> [#uses=1]
+ %Z = sitofp i64 %Y to double ; <double> [#uses=1]
+ ret double %Z
+}
+
+define float @test2(double %X) {
+ %Y = fptosi double %X to i64 ; <i64> [#uses=1]
+ %Z = sitofp i64 %Y to float ; <float> [#uses=1]
+ ret float %Z
+}
+
+define double @test3(float %X) {
+ %Y = fptosi float %X to i64 ; <i64> [#uses=1]
+ %Z = sitofp i64 %Y to double ; <double> [#uses=1]
+ ret double %Z
+}
+
+define float @test4(float %X) {
+ %Y = fptosi float %X to i64 ; <i64> [#uses=1]
+ %Z = sitofp i64 %Y to float ; <float> [#uses=1]
+ ret float %Z
+}
+
+
diff --git a/test/CodeGen/PowerPC/fp_to_uint.ll b/test/CodeGen/PowerPC/fp_to_uint.ll
new file mode 100644
index 0000000..1360b62
--- /dev/null
+++ b/test/CodeGen/PowerPC/fp_to_uint.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=ppc32 | grep fctiwz | count 1
+
+define i16 @foo(float %a) {
+entry:
+ %tmp.1 = fptoui float %a to i16 ; <i16> [#uses=1]
+ ret i16 %tmp.1
+}
+
diff --git a/test/CodeGen/PowerPC/fpcopy.ll b/test/CodeGen/PowerPC/fpcopy.ll
new file mode 100644
index 0000000..7b9446b
--- /dev/null
+++ b/test/CodeGen/PowerPC/fpcopy.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=ppc32 | not grep fmr
+
+define double @test(float %F) {
+ %F.upgrd.1 = fpext float %F to double ; <double> [#uses=1]
+ ret double %F.upgrd.1
+}
+
diff --git a/test/CodeGen/PowerPC/frounds.ll b/test/CodeGen/PowerPC/frounds.ll
new file mode 100644
index 0000000..8eeadc3
--- /dev/null
+++ b/test/CodeGen/PowerPC/frounds.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=ppc32
+
+define i32 @foo() {
+entry:
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ %tmp = alloca i32 ; <i32*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %tmp1 = call i32 @llvm.flt.rounds( ) ; <i32> [#uses=1]
+ store i32 %tmp1, i32* %tmp, align 4
+ %tmp2 = load i32* %tmp, align 4 ; <i32> [#uses=1]
+ store i32 %tmp2, i32* %retval, align 4
+ br label %return
+
+return: ; preds = %entry
+ %retval3 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval3
+}
+
+declare i32 @llvm.flt.rounds() nounwind
diff --git a/test/CodeGen/PowerPC/fsqrt.ll b/test/CodeGen/PowerPC/fsqrt.ll
new file mode 100644
index 0000000..74a8725
--- /dev/null
+++ b/test/CodeGen/PowerPC/fsqrt.ll
@@ -0,0 +1,19 @@
+; fsqrt should be generated when the fsqrt feature is enabled, but not
+; otherwise.
+
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \
+; RUN: grep {fsqrt f1, f1}
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
+; RUN: grep {fsqrt f1, f1}
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \
+; RUN: not grep {fsqrt f1, f1}
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \
+; RUN: not grep {fsqrt f1, f1}
+
+declare double @llvm.sqrt.f64(double)
+
+define double @X(double %Y) {
+ %Z = call double @llvm.sqrt.f64( double %Y ) ; <double> [#uses=1]
+ ret double %Z
+}
+
diff --git a/test/CodeGen/PowerPC/hello.ll b/test/CodeGen/PowerPC/hello.ll
new file mode 100644
index 0000000..ea27e92
--- /dev/null
+++ b/test/CodeGen/PowerPC/hello.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s -march=ppc64
+; PR1399
+
[email protected] = internal constant [13 x i8] c"Hello World!\00"
+
+define i32 @main() {
+ %tmp2 = tail call i32 @puts( i8* getelementptr ([13 x i8]* @.str, i32 0, i64 0) )
+ ret i32 0
+}
+
+declare i32 @puts(i8*)
diff --git a/test/CodeGen/PowerPC/hidden-vis-2.ll b/test/CodeGen/PowerPC/hidden-vis-2.ll
new file mode 100644
index 0000000..e9e2c0a
--- /dev/null
+++ b/test/CodeGen/PowerPC/hidden-vis-2.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin9 | grep non_lazy_ptr | count 6
+
+@x = external hidden global i32 ; <i32*> [#uses=1]
+@y = extern_weak hidden global i32 ; <i32*> [#uses=1]
+
+define i32 @t() nounwind readonly {
+entry:
+ %0 = load i32* @x, align 4 ; <i32> [#uses=1]
+ %1 = load i32* @y, align 4 ; <i32> [#uses=1]
+ %2 = add i32 %1, %0 ; <i32> [#uses=1]
+ ret i32 %2
+}
diff --git a/test/CodeGen/PowerPC/hidden-vis.ll b/test/CodeGen/PowerPC/hidden-vis.ll
new file mode 100644
index 0000000..b2cc143
--- /dev/null
+++ b/test/CodeGen/PowerPC/hidden-vis.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin9 | not grep non_lazy_ptr
+
+@x = weak hidden global i32 0 ; <i32*> [#uses=1]
+
+define i32 @t() nounwind readonly {
+entry:
+ %0 = load i32* @x, align 4 ; <i32> [#uses=1]
+ ret i32 %0
+}
diff --git a/test/CodeGen/PowerPC/i128-and-beyond.ll b/test/CodeGen/PowerPC/i128-and-beyond.ll
new file mode 100644
index 0000000..51bcab2
--- /dev/null
+++ b/test/CodeGen/PowerPC/i128-and-beyond.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=ppc32 | grep 4294967295 | count 28
+
+; These static initializers are too big to hand off to assemblers
+; as monolithic blobs.
+
+@x = global i128 -1
+@y = global i256 -1
+@z = global i512 -1
diff --git a/test/CodeGen/PowerPC/i64_fp.ll b/test/CodeGen/PowerPC/i64_fp.ll
new file mode 100644
index 0000000..d53c948
--- /dev/null
+++ b/test/CodeGen/PowerPC/i64_fp.ll
@@ -0,0 +1,26 @@
+; fcfid and fctid should be generated when the 64bit feature is enabled, but not
+; otherwise.
+
+; RUN: llc < %s -march=ppc32 -mattr=+64bit | \
+; RUN: grep fcfid
+; RUN: llc < %s -march=ppc32 -mattr=+64bit | \
+; RUN: grep fctidz
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
+; RUN: grep fcfid
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
+; RUN: grep fctidz
+; RUN: llc < %s -march=ppc32 -mattr=-64bit | \
+; RUN: not grep fcfid
+; RUN: llc < %s -march=ppc32 -mattr=-64bit | \
+; RUN: not grep fctidz
+; RUN: llc < %s -march=ppc32 -mcpu=g4 | \
+; RUN: not grep fcfid
+; RUN: llc < %s -march=ppc32 -mcpu=g4 | \
+; RUN: not grep fctidz
+
+define double @X(double %Y) {
+ %A = fptosi double %Y to i64 ; <i64> [#uses=1]
+ %B = sitofp i64 %A to double ; <double> [#uses=1]
+ ret double %B
+}
+
diff --git a/test/CodeGen/PowerPC/iabs.ll b/test/CodeGen/PowerPC/iabs.ll
new file mode 100644
index 0000000..a43f09c
--- /dev/null
+++ b/test/CodeGen/PowerPC/iabs.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=ppc32 -stats |& \
+; RUN: grep {4 .*Number of machine instrs printed}
+
+;; Integer absolute value, should produce something as good as:
+;; srawi r2, r3, 31
+;; add r3, r3, r2
+;; xor r3, r3, r2
+;; blr
+define i32 @test(i32 %a) {
+ %tmp1neg = sub i32 0, %a
+ %b = icmp sgt i32 %a, -1
+ %abs = select i1 %b, i32 %a, i32 %tmp1neg
+ ret i32 %abs
+}
+
diff --git a/test/CodeGen/PowerPC/illegal-element-type.ll b/test/CodeGen/PowerPC/illegal-element-type.ll
new file mode 100644
index 0000000..58bd055
--- /dev/null
+++ b/test/CodeGen/PowerPC/illegal-element-type.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g3
+
+define void @foo() {
+entry:
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ br i1 false, label %bb26, label %bb
+
+bb19: ; preds = %bb26
+ ret void
+
+bb26: ; preds = %bb
+ br i1 false, label %bb30, label %bb19
+
+bb30: ; preds = %bb26
+ br label %bb45
+
+bb45: ; preds = %bb45, %bb30
+ %V.0 = phi <8 x i16> [ %tmp42, %bb45 ], [ zeroinitializer, %bb30 ] ; <<8 x i16>> [#uses=1]
+ %tmp42 = mul <8 x i16> zeroinitializer, %V.0 ; <<8 x i16>> [#uses=1]
+ br label %bb45
+}
diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll
new file mode 100644
index 0000000..fbc7bd2
--- /dev/null
+++ b/test/CodeGen/PowerPC/indirectbr.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -relocation-model=pic -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s -check-prefix=PIC
+; RUN: llc < %s -relocation-model=static -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s -check-prefix=STATIC
+
+@nextaddr = global i8* null ; <i8**> [#uses=2]
[email protected] = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
+
+define internal i32 @foo(i32 %i) nounwind {
+; PIC: foo:
+; STATIC: foo:
+entry:
+ %0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2]
+ %1 = icmp eq i8* %0, null ; <i1> [#uses=1]
+ br i1 %1, label %bb3, label %bb2
+
+bb2: ; preds = %entry, %bb3
+ %gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1]
+; PIC: mtctr
+; PIC-NEXT: bctr
+; STATIC: mtctr
+; STATIC-NEXT: bctr
+ indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
+
+bb3: ; preds = %entry
+ %2 = getelementptr inbounds [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1]
+ %gotovar.4.0.pre = load i8** %2, align 4 ; <i8*> [#uses=1]
+ br label %bb2
+
+L5: ; preds = %bb2
+ br label %L4
+
+L4: ; preds = %L5, %bb2
+ %res.0 = phi i32 [ 385, %L5 ], [ 35, %bb2 ] ; <i32> [#uses=1]
+ br label %L3
+
+L3: ; preds = %L4, %bb2
+ %res.1 = phi i32 [ %res.0, %L4 ], [ 5, %bb2 ] ; <i32> [#uses=1]
+ br label %L2
+
+L2: ; preds = %L3, %bb2
+ %res.2 = phi i32 [ %res.1, %L3 ], [ 1, %bb2 ] ; <i32> [#uses=1]
+ %phitmp = mul i32 %res.2, 6 ; <i32> [#uses=1]
+ br label %L1
+
+L1: ; preds = %L2, %bb2
+ %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1]
+; PIC: addis r4, r2, ha16(L_BA4__foo_L5-"L1$pb")
+; PIC: li r5, lo16(L_BA4__foo_L5-"L1$pb")
+; PIC: add r4, r4, r5
+; PIC: stw r4
+; STATIC: li r2, lo16(L_BA4__foo_L5)
+; STATIC: addis r2, r2, ha16(L_BA4__foo_L5)
+; STATIC: stw r2
+ store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
+ ret i32 %res.3
+}
diff --git a/test/CodeGen/PowerPC/inlineasm-copy.ll b/test/CodeGen/PowerPC/inlineasm-copy.ll
new file mode 100644
index 0000000..e1ff82d
--- /dev/null
+++ b/test/CodeGen/PowerPC/inlineasm-copy.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=ppc32 | not grep mr
+
+define i32 @test(i32 %Y, i32 %X) {
+entry:
+ %tmp = tail call i32 asm "foo $0", "=r"( ) ; <i32> [#uses=1]
+ ret i32 %tmp
+}
+
+define i32 @test2(i32 %Y, i32 %X) {
+entry:
+ %tmp1 = tail call i32 asm "foo $0, $1", "=r,r"( i32 %X ) ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
diff --git a/test/CodeGen/PowerPC/int-fp-conv-0.ll b/test/CodeGen/PowerPC/int-fp-conv-0.ll
new file mode 100644
index 0000000..983d2b8
--- /dev/null
+++ b/test/CodeGen/PowerPC/int-fp-conv-0.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=ppc64 > %t
+; RUN: grep __floattitf %t
+; RUN: grep __fixunstfti %t
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc64-apple-darwin9.2.0"
+
+define ppc_fp128 @foo(i128 %a) nounwind {
+entry:
+ %tmp2829 = uitofp i128 %a to ppc_fp128 ; <i64> [#uses=1]
+ ret ppc_fp128 %tmp2829
+}
+define i128 @boo(ppc_fp128 %a) nounwind {
+entry:
+ %tmp2829 = fptoui ppc_fp128 %a to i128 ; <i64> [#uses=1]
+ ret i128 %tmp2829
+}
diff --git a/test/CodeGen/PowerPC/int-fp-conv-1.ll b/test/CodeGen/PowerPC/int-fp-conv-1.ll
new file mode 100644
index 0000000..6c82723
--- /dev/null
+++ b/test/CodeGen/PowerPC/int-fp-conv-1.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=ppc64 | grep __floatditf
+
+define i64 @__fixunstfdi(ppc_fp128 %a) nounwind {
+entry:
+ %tmp1213 = uitofp i64 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
+ %tmp15 = fsub ppc_fp128 %a, %tmp1213 ; <ppc_fp128> [#uses=1]
+ %tmp2829 = fptoui ppc_fp128 %tmp15 to i32 ; <i32> [#uses=1]
+ %tmp282930 = zext i32 %tmp2829 to i64 ; <i64> [#uses=1]
+ %tmp32 = add i64 %tmp282930, 0 ; <i64> [#uses=1]
+ ret i64 %tmp32
+}
diff --git a/test/CodeGen/PowerPC/invalid-memcpy.ll b/test/CodeGen/PowerPC/invalid-memcpy.ll
new file mode 100644
index 0000000..3b1f306
--- /dev/null
+++ b/test/CodeGen/PowerPC/invalid-memcpy.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s -march=ppc64
+
+; This testcase is invalid (the alignment specified for memcpy is
+; greater than the alignment guaranteed for Qux or C.0.1173, but it
+; should compile, not crash the code generator.
+
[email protected] = external constant [33 x i8] ; <[33 x i8]*> [#uses=1]
+
+define void @Bork() {
+entry:
+ %Qux = alloca [33 x i8] ; <[33 x i8]*> [#uses=1]
+ %Qux1 = bitcast [33 x i8]* %Qux to i8* ; <i8*> [#uses=1]
+ call void @llvm.memcpy.i64( i8* %Qux1, i8* getelementptr ([33 x i8]* @C.0.1173, i32 0, i32 0), i64 33, i32 8 )
+ ret void
+}
+
+declare void @llvm.memcpy.i64(i8*, i8*, i64, i32)
+
+
diff --git a/test/CodeGen/PowerPC/inverted-bool-compares.ll b/test/CodeGen/PowerPC/inverted-bool-compares.ll
new file mode 100644
index 0000000..aa7e4d6
--- /dev/null
+++ b/test/CodeGen/PowerPC/inverted-bool-compares.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=ppc32 | not grep xori
+
+define i32 @test(i1 %B, i32* %P) {
+ br i1 %B, label %T, label %F
+
+T: ; preds = %0
+ store i32 123, i32* %P
+ ret i32 0
+
+F: ; preds = %0
+ ret i32 17
+}
+
diff --git a/test/CodeGen/PowerPC/ispositive.ll b/test/CodeGen/PowerPC/ispositive.ll
new file mode 100644
index 0000000..4161e34
--- /dev/null
+++ b/test/CodeGen/PowerPC/ispositive.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
+; RUN: grep {srwi r3, r3, 31}
+
+define i32 @test1(i32 %X) {
+entry:
+ icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]
+ zext i1 %0 to i32 ; <i32>:1 [#uses=1]
+ ret i32 %1
+}
+
diff --git a/test/CodeGen/PowerPC/itofp128.ll b/test/CodeGen/PowerPC/itofp128.ll
new file mode 100644
index 0000000..6d9ef95
--- /dev/null
+++ b/test/CodeGen/PowerPC/itofp128.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=ppc64
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc64-apple-darwin9.2.0"
+
+define i128 @__fixunstfti(ppc_fp128 %a) nounwind {
+entry:
+ %tmp1213 = uitofp i128 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
+ %tmp15 = fsub ppc_fp128 %a, %tmp1213 ; <ppc_fp128> [#uses=1]
+ %tmp2829 = fptoui ppc_fp128 %tmp15 to i64 ; <i64> [#uses=1]
+ %tmp282930 = zext i64 %tmp2829 to i128 ; <i128> [#uses=1]
+ %tmp32 = add i128 %tmp282930, 0 ; <i128> [#uses=1]
+ ret i128 %tmp32
+}
diff --git a/test/CodeGen/PowerPC/lha.ll b/test/CodeGen/PowerPC/lha.ll
new file mode 100644
index 0000000..3a100c1
--- /dev/null
+++ b/test/CodeGen/PowerPC/lha.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=ppc32 | grep lha
+
+define i32 @test(i16* %a) {
+ %tmp.1 = load i16* %a ; <i16> [#uses=1]
+ %tmp.2 = sext i16 %tmp.1 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp.2
+}
+
diff --git a/test/CodeGen/PowerPC/load-constant-addr.ll b/test/CodeGen/PowerPC/load-constant-addr.ll
new file mode 100644
index 0000000..f1d061c
--- /dev/null
+++ b/test/CodeGen/PowerPC/load-constant-addr.ll
@@ -0,0 +1,9 @@
+; Should fold the ori into the lfs.
+; RUN: llc < %s -march=ppc32 | grep lfs
+; RUN: llc < %s -march=ppc32 | not grep ori
+
+define float @test() {
+ %tmp.i = load float* inttoptr (i32 186018016 to float*) ; <float> [#uses=1]
+ ret float %tmp.i
+}
+
diff --git a/test/CodeGen/PowerPC/long-compare.ll b/test/CodeGen/PowerPC/long-compare.ll
new file mode 100644
index 0000000..94c2526
--- /dev/null
+++ b/test/CodeGen/PowerPC/long-compare.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=ppc32 | grep cntlzw
+; RUN: llc < %s -march=ppc32 | not grep xori
+; RUN: llc < %s -march=ppc32 | not grep {li }
+; RUN: llc < %s -march=ppc32 | not grep {mr }
+
+define i1 @test(i64 %x) {
+ %tmp = icmp ult i64 %x, 4294967296
+ ret i1 %tmp
+}
diff --git a/test/CodeGen/PowerPC/longdbl-truncate.ll b/test/CodeGen/PowerPC/longdbl-truncate.ll
new file mode 100644
index 0000000..e5f63c6
--- /dev/null
+++ b/test/CodeGen/PowerPC/longdbl-truncate.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin8"
+
+define double @SolveCubic(ppc_fp128 %X) {
+entry:
+ %Y = fptrunc ppc_fp128 %X to double
+ ret double %Y
+}
diff --git a/test/CodeGen/PowerPC/mask64.ll b/test/CodeGen/PowerPC/mask64.ll
new file mode 100644
index 0000000..139621a
--- /dev/null
+++ b/test/CodeGen/PowerPC/mask64.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc64-apple-darwin9.2.0"
+ %struct.re_pattern_buffer = type <{ i8*, i64, i8, [7 x i8] }>
+
+define i32 @xre_search_2(%struct.re_pattern_buffer* %bufp, i32 %range) nounwind {
+entry:
+ br i1 false, label %bb16, label %bb49
+
+bb16: ; preds = %entry
+ %tmp19 = load i8** null, align 1 ; <i8*> [#uses=1]
+ %tmp21 = load i8* %tmp19, align 1 ; <i8> [#uses=1]
+ switch i8 %tmp21, label %bb49 [
+ i8 0, label %bb45
+ i8 1, label %bb34
+ ]
+
+bb34: ; preds = %bb16
+ ret i32 0
+
+bb45: ; preds = %bb16
+ ret i32 -1
+
+bb49: ; preds = %bb16, %entry
+ ret i32 0
+}
diff --git a/test/CodeGen/PowerPC/mem-rr-addr-mode.ll b/test/CodeGen/PowerPC/mem-rr-addr-mode.ll
new file mode 100644
index 0000000..5661ef9
--- /dev/null
+++ b/test/CodeGen/PowerPC/mem-rr-addr-mode.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep li.*16
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep addi
+
+; Codegen lvx (R+16) as t = li 16, lvx t,R
+; This shares the 16 between the two loads.
+
+define void @func(<4 x float>* %a, <4 x float>* %b) {
+ %tmp1 = getelementptr <4 x float>* %b, i32 1 ; <<4 x float>*> [#uses=1]
+ %tmp = load <4 x float>* %tmp1 ; <<4 x float>> [#uses=1]
+ %tmp3 = getelementptr <4 x float>* %a, i32 1 ; <<4 x float>*> [#uses=1]
+ %tmp4 = load <4 x float>* %tmp3 ; <<4 x float>> [#uses=1]
+ %tmp5 = fmul <4 x float> %tmp, %tmp4 ; <<4 x float>> [#uses=1]
+ %tmp8 = load <4 x float>* %b ; <<4 x float>> [#uses=1]
+ %tmp9 = fadd <4 x float> %tmp5, %tmp8 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp9, <4 x float>* %a
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/mem_update.ll b/test/CodeGen/PowerPC/mem_update.ll
new file mode 100644
index 0000000..b267719
--- /dev/null
+++ b/test/CodeGen/PowerPC/mem_update.ll
@@ -0,0 +1,68 @@
+; RUN: llc < %s -march=ppc32 -enable-ppc-preinc | \
+; RUN: not grep addi
+; RUN: llc < %s -march=ppc64 -enable-ppc-preinc | \
+; RUN: not grep addi
+
+@Glob = global i64 4 ; <i64*> [#uses=2]
+
+define i32* @test0(i32* %X, i32* %dest) {
+ %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2]
+ %A = load i32* %Y ; <i32> [#uses=1]
+ store i32 %A, i32* %dest
+ ret i32* %Y
+}
+
+define i32* @test1(i32* %X, i32* %dest) {
+ %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2]
+ %A = load i32* %Y ; <i32> [#uses=1]
+ store i32 %A, i32* %dest
+ ret i32* %Y
+}
+
+define i16* @test2(i16* %X, i32* %dest) {
+ %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2]
+ %A = load i16* %Y ; <i16> [#uses=1]
+ %B = sext i16 %A to i32 ; <i32> [#uses=1]
+ store i32 %B, i32* %dest
+ ret i16* %Y
+}
+
+define i16* @test3(i16* %X, i32* %dest) {
+ %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2]
+ %A = load i16* %Y ; <i16> [#uses=1]
+ %B = zext i16 %A to i32 ; <i32> [#uses=1]
+ store i32 %B, i32* %dest
+ ret i16* %Y
+}
+
+define i16* @test3a(i16* %X, i64* %dest) {
+ %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2]
+ %A = load i16* %Y ; <i16> [#uses=1]
+ %B = sext i16 %A to i64 ; <i64> [#uses=1]
+ store i64 %B, i64* %dest
+ ret i16* %Y
+}
+
+define i64* @test4(i64* %X, i64* %dest) {
+ %Y = getelementptr i64* %X, i32 4 ; <i64*> [#uses=2]
+ %A = load i64* %Y ; <i64> [#uses=1]
+ store i64 %A, i64* %dest
+ ret i64* %Y
+}
+
+define i16* @test5(i16* %X) {
+ %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2]
+ store i16 7, i16* %Y
+ ret i16* %Y
+}
+
+define i64* @test6(i64* %X, i64 %A) {
+ %Y = getelementptr i64* %X, i32 4 ; <i64*> [#uses=2]
+ store i64 %A, i64* %Y
+ ret i64* %Y
+}
+
+define i64* @test7(i64* %X, i64 %A) {
+ store i64 %A, i64* @Glob
+ ret i64* @Glob
+}
diff --git a/test/CodeGen/PowerPC/mul-neg-power-2.ll b/test/CodeGen/PowerPC/mul-neg-power-2.ll
new file mode 100644
index 0000000..9688d6e
--- /dev/null
+++ b/test/CodeGen/PowerPC/mul-neg-power-2.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=ppc32 | not grep mul
+
+define i32 @test1(i32 %a) {
+ %tmp.1 = mul i32 %a, -2 ; <i32> [#uses=1]
+ %tmp.2 = add i32 %tmp.1, 63 ; <i32> [#uses=1]
+ ret i32 %tmp.2
+}
+
diff --git a/test/CodeGen/PowerPC/mul-with-overflow.ll b/test/CodeGen/PowerPC/mul-with-overflow.ll
new file mode 100644
index 0000000..f03e3cb
--- /dev/null
+++ b/test/CodeGen/PowerPC/mul-with-overflow.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=ppc32
+
+declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b)
+define i1 @a(i32 %x) zeroext nounwind {
+ %res = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %x, i32 3)
+ %obil = extractvalue {i32, i1} %res, 1
+ ret i1 %obil
+}
+
+declare {i32, i1} @llvm.smul.with.overflow.i32(i32 %a, i32 %b)
+define i1 @b(i32 %x) zeroext nounwind {
+ %res = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %x, i32 3)
+ %obil = extractvalue {i32, i1} %res, 1
+ ret i1 %obil
+}
diff --git a/test/CodeGen/PowerPC/mulhs.ll b/test/CodeGen/PowerPC/mulhs.ll
new file mode 100644
index 0000000..9ab8d99
--- /dev/null
+++ b/test/CodeGen/PowerPC/mulhs.ll
@@ -0,0 +1,17 @@
+; All of these ands and shifts should be folded into rlwimi's
+; RUN: llc < %s -march=ppc32 -o %t
+; RUN: not grep mulhwu %t
+; RUN: not grep srawi %t
+; RUN: not grep add %t
+; RUN: grep mulhw %t | count 1
+
+define i32 @mulhs(i32 %a, i32 %b) {
+entry:
+ %tmp.1 = sext i32 %a to i64 ; <i64> [#uses=1]
+ %tmp.3 = sext i32 %b to i64 ; <i64> [#uses=1]
+ %tmp.4 = mul i64 %tmp.3, %tmp.1 ; <i64> [#uses=1]
+ %tmp.6 = lshr i64 %tmp.4, 32 ; <i64> [#uses=1]
+ %tmp.7 = trunc i64 %tmp.6 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp.7
+}
+
diff --git a/test/CodeGen/PowerPC/multiple-return-values.ll b/test/CodeGen/PowerPC/multiple-return-values.ll
new file mode 100644
index 0000000..b9317f9
--- /dev/null
+++ b/test/CodeGen/PowerPC/multiple-return-values.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=ppc32
+; RUN: llc < %s -march=ppc64
+
+define {i64, float} @bar(i64 %a, float %b) {
+ %y = add i64 %a, 7
+ %z = fadd float %b, 7.0
+ ret i64 %y, float %z
+}
+
+define i64 @foo() {
+ %M = call {i64, float} @bar(i64 21, float 21.0)
+ %N = getresult {i64, float} %M, 0
+ %O = getresult {i64, float} %M, 1
+ %P = fptosi float %O to i64
+ %Q = add i64 %P, %N
+ ret i64 %Q
+}
diff --git a/test/CodeGen/PowerPC/neg.ll b/test/CodeGen/PowerPC/neg.ll
new file mode 100644
index 0000000..c673912
--- /dev/null
+++ b/test/CodeGen/PowerPC/neg.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=ppc32 | grep neg
+
+define i32 @test(i32 %X) {
+ %Y = sub i32 0, %X ; <i32> [#uses=1]
+ ret i32 %Y
+}
+
diff --git a/test/CodeGen/PowerPC/no-dead-strip.ll b/test/CodeGen/PowerPC/no-dead-strip.ll
new file mode 100644
index 0000000..3459413
--- /dev/null
+++ b/test/CodeGen/PowerPC/no-dead-strip.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s | grep {no_dead_strip.*_X}
+
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "powerpc-apple-darwin8.8.0"
+@X = weak global i32 0 ; <i32*> [#uses=1]
[email protected] = internal constant [4 x i8] c"t.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1]
[email protected] = appending global [1 x i8*] [ i8* bitcast (i32* @X to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
diff --git a/test/CodeGen/PowerPC/or-addressing-mode.ll b/test/CodeGen/PowerPC/or-addressing-mode.ll
new file mode 100644
index 0000000..e50374e
--- /dev/null
+++ b/test/CodeGen/PowerPC/or-addressing-mode.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin8 | not grep ori
+; RUN: llc < %s -mtriple=powerpc-apple-darwin8 | not grep rlwimi
+
+define i32 @test1(i8* %P) {
+ %tmp.2.i = ptrtoint i8* %P to i32 ; <i32> [#uses=2]
+ %tmp.4.i = and i32 %tmp.2.i, -65536 ; <i32> [#uses=1]
+ %tmp.10.i = lshr i32 %tmp.2.i, 5 ; <i32> [#uses=1]
+ %tmp.11.i = and i32 %tmp.10.i, 2040 ; <i32> [#uses=1]
+ %tmp.13.i = or i32 %tmp.11.i, %tmp.4.i ; <i32> [#uses=1]
+ %tmp.14.i = inttoptr i32 %tmp.13.i to i32* ; <i32*> [#uses=1]
+ %tmp.3 = load i32* %tmp.14.i ; <i32> [#uses=1]
+ ret i32 %tmp.3
+}
+
+define i32 @test2(i32 %P) {
+ %tmp.2 = shl i32 %P, 4 ; <i32> [#uses=1]
+ %tmp.3 = or i32 %tmp.2, 2 ; <i32> [#uses=1]
+ %tmp.4 = inttoptr i32 %tmp.3 to i32* ; <i32*> [#uses=1]
+ %tmp.5 = load i32* %tmp.4 ; <i32> [#uses=1]
+ ret i32 %tmp.5
+}
+
diff --git a/test/CodeGen/PowerPC/ppc-prologue.ll b/test/CodeGen/PowerPC/ppc-prologue.ll
new file mode 100644
index 0000000..e49dcb8
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc-prologue.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s
+
+define i32 @_Z4funci(i32 %a) ssp {
+; CHECK: mflr r0
+; CHECK-NEXT: stw r31, -4(r1)
+; CHECK-NEXT: stw r0, 8(r1)
+; CHECK-NEXT: stwu r1, -80(r1)
+; CHECK-NEXT: Llabel1:
+; CHECK-NEXT: mr r31, r1
+; CHECK-NEXT: Llabel2:
+entry:
+ %a_addr = alloca i32 ; <i32*> [#uses=2]
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ %0 = alloca i32 ; <i32*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %a, i32* %a_addr
+ %1 = call i32 @_Z3barPi(i32* %a_addr) ; <i32> [#uses=1]
+ store i32 %1, i32* %0, align 4
+ %2 = load i32* %0, align 4 ; <i32> [#uses=1]
+ store i32 %2, i32* %retval, align 4
+ br label %return
+
+return: ; preds = %entry
+ %retval1 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval1
+}
+
+declare i32 @_Z3barPi(i32*)
diff --git a/test/CodeGen/PowerPC/ppcf128-1-opt.ll b/test/CodeGen/PowerPC/ppcf128-1-opt.ll
new file mode 100644
index 0000000..2fc1720
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppcf128-1-opt.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s > %t
+; ModuleID = '<stdin>'
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin8"
+
+define ppc_fp128 @plus(ppc_fp128 %x, ppc_fp128 %y) {
+entry:
+ %tmp3 = fadd ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1]
+ ret ppc_fp128 %tmp3
+}
+
+define ppc_fp128 @minus(ppc_fp128 %x, ppc_fp128 %y) {
+entry:
+ %tmp3 = fsub ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1]
+ ret ppc_fp128 %tmp3
+}
+
+define ppc_fp128 @times(ppc_fp128 %x, ppc_fp128 %y) {
+entry:
+ %tmp3 = fmul ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1]
+ ret ppc_fp128 %tmp3
+}
+
+define ppc_fp128 @divide(ppc_fp128 %x, ppc_fp128 %y) {
+entry:
+ %tmp3 = fdiv ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1]
+ ret ppc_fp128 %tmp3
+}
+
diff --git a/test/CodeGen/PowerPC/ppcf128-1.ll b/test/CodeGen/PowerPC/ppcf128-1.ll
new file mode 100644
index 0000000..1047fe5
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppcf128-1.ll
@@ -0,0 +1,92 @@
+; RUN: opt < %s -std-compile-opts | llc > %t
+; ModuleID = 'ld3.c'
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin8"
+
+define ppc_fp128 @plus(ppc_fp128 %x, ppc_fp128 %y) {
+entry:
+ %x_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
+ %y_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
+ %retval = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
+ %tmp = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store ppc_fp128 %x, ppc_fp128* %x_addr
+ store ppc_fp128 %y, ppc_fp128* %y_addr
+ %tmp1 = load ppc_fp128* %x_addr, align 16 ; <ppc_fp128> [#uses=1]
+ %tmp2 = load ppc_fp128* %y_addr, align 16 ; <ppc_fp128> [#uses=1]
+ %tmp3 = fadd ppc_fp128 %tmp1, %tmp2 ; <ppc_fp128> [#uses=1]
+ store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16
+ %tmp4 = load ppc_fp128* %tmp, align 16 ; <ppc_fp128> [#uses=1]
+ store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16
+ br label %return
+
+return: ; preds = %entry
+ %retval5 = load ppc_fp128* %retval ; <ppc_fp128> [#uses=1]
+ ret ppc_fp128 %retval5
+}
+
+define ppc_fp128 @minus(ppc_fp128 %x, ppc_fp128 %y) {
+entry:
+ %x_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
+ %y_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
+ %retval = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
+ %tmp = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store ppc_fp128 %x, ppc_fp128* %x_addr
+ store ppc_fp128 %y, ppc_fp128* %y_addr
+ %tmp1 = load ppc_fp128* %x_addr, align 16 ; <ppc_fp128> [#uses=1]
+ %tmp2 = load ppc_fp128* %y_addr, align 16 ; <ppc_fp128> [#uses=1]
+ %tmp3 = fsub ppc_fp128 %tmp1, %tmp2 ; <ppc_fp128> [#uses=1]
+ store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16
+ %tmp4 = load ppc_fp128* %tmp, align 16 ; <ppc_fp128> [#uses=1]
+ store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16
+ br label %return
+
+return: ; preds = %entry
+ %retval5 = load ppc_fp128* %retval ; <ppc_fp128> [#uses=1]
+ ret ppc_fp128 %retval5
+}
+
+define ppc_fp128 @times(ppc_fp128 %x, ppc_fp128 %y) {
+entry:
+ %x_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
+ %y_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
+ %retval = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
+ %tmp = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store ppc_fp128 %x, ppc_fp128* %x_addr
+ store ppc_fp128 %y, ppc_fp128* %y_addr
+ %tmp1 = load ppc_fp128* %x_addr, align 16 ; <ppc_fp128> [#uses=1]
+ %tmp2 = load ppc_fp128* %y_addr, align 16 ; <ppc_fp128> [#uses=1]
+ %tmp3 = fmul ppc_fp128 %tmp1, %tmp2 ; <ppc_fp128> [#uses=1]
+ store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16
+ %tmp4 = load ppc_fp128* %tmp, align 16 ; <ppc_fp128> [#uses=1]
+ store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16
+ br label %return
+
+return: ; preds = %entry
+ %retval5 = load ppc_fp128* %retval ; <ppc_fp128> [#uses=1]
+ ret ppc_fp128 %retval5
+}
+
+define ppc_fp128 @divide(ppc_fp128 %x, ppc_fp128 %y) {
+entry:
+ %x_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
+ %y_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2]
+ %retval = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
+ %tmp = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store ppc_fp128 %x, ppc_fp128* %x_addr
+ store ppc_fp128 %y, ppc_fp128* %y_addr
+ %tmp1 = load ppc_fp128* %x_addr, align 16 ; <ppc_fp128> [#uses=1]
+ %tmp2 = load ppc_fp128* %y_addr, align 16 ; <ppc_fp128> [#uses=1]
+ %tmp3 = fdiv ppc_fp128 %tmp1, %tmp2 ; <ppc_fp128> [#uses=1]
+ store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16
+ %tmp4 = load ppc_fp128* %tmp, align 16 ; <ppc_fp128> [#uses=1]
+ store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16
+ br label %return
+
+return: ; preds = %entry
+ %retval5 = load ppc_fp128* %retval ; <ppc_fp128> [#uses=1]
+ ret ppc_fp128 %retval5
+}
diff --git a/test/CodeGen/PowerPC/ppcf128-2.ll b/test/CodeGen/PowerPC/ppcf128-2.ll
new file mode 100644
index 0000000..7eee354
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppcf128-2.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=ppc64
+
+define i64 @__fixtfdi(ppc_fp128 %a) nounwind {
+entry:
+ br i1 false, label %bb, label %bb8
+bb: ; preds = %entry
+ %tmp5 = fsub ppc_fp128 0xM80000000000000000000000000000000, %a ; <ppc_fp128> [#uses=1]
+ %tmp6 = tail call i64 @__fixunstfdi( ppc_fp128 %tmp5 ) nounwind ; <i64> [#uses=0]
+ ret i64 0
+bb8: ; preds = %entry
+ ret i64 0
+}
+
+declare i64 @__fixunstfdi(ppc_fp128)
diff --git a/test/CodeGen/PowerPC/ppcf128-3.ll b/test/CodeGen/PowerPC/ppcf128-3.ll
new file mode 100644
index 0000000..5043b62
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppcf128-3.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=ppc32
+ %struct.stp_sequence = type { double, double }
+
+define i32 @stp_sequence_set_short_data(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
+entry:
+ %tmp1112 = sitofp i16 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
+ %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
+
+define i32 @stp_sequence_set_short_data2(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
+entry:
+ %tmp1112 = sitofp i8 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
+ %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
+
+define i32 @stp_sequence_set_short_data3(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
+entry:
+ %tmp1112 = uitofp i16 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
+ %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
+
+define i32 @stp_sequence_set_short_data4(%struct.stp_sequence* %sequence, i32 %count, i16* %data) {
+entry:
+ %tmp1112 = uitofp i8 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
+ %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
+
+declare i32 @__inline_isfinite(...)
diff --git a/test/CodeGen/PowerPC/ppcf128-4.ll b/test/CodeGen/PowerPC/ppcf128-4.ll
new file mode 100644
index 0000000..104a25e
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppcf128-4.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=ppc32
+
+define ppc_fp128 @__floatditf(i64 %u) nounwind {
+entry:
+ %tmp6 = fmul ppc_fp128 0xM00000000000000000000000000000000, 0xM41F00000000000000000000000000000
+ %tmp78 = trunc i64 %u to i32
+ %tmp789 = uitofp i32 %tmp78 to ppc_fp128
+ %tmp11 = fadd ppc_fp128 %tmp789, %tmp6
+ ret ppc_fp128 %tmp11
+}
diff --git a/test/CodeGen/PowerPC/pr3711_widen_bit.ll b/test/CodeGen/PowerPC/pr3711_widen_bit.ll
new file mode 100644
index 0000000..7abdeda
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr3711_widen_bit.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5
+
+; Test that causes a abort in expanding a bit convert due to a missing support
+; for widening.
+
+define i32 @main() nounwind {
+entry:
+ br i1 icmp ne (i32 trunc (i64 bitcast (<2 x i32> <i32 2, i32 2> to i64) to i32), i32 2), label %bb, label %bb1
+
+bb: ; preds = %entry
+ tail call void @abort() noreturn nounwind
+ unreachable
+
+bb1: ; preds = %entry
+ ret i32 0
+}
+
+declare void @abort() noreturn nounwind
diff --git a/test/CodeGen/PowerPC/private.ll b/test/CodeGen/PowerPC/private.ll
new file mode 100644
index 0000000..f9405f6
--- /dev/null
+++ b/test/CodeGen/PowerPC/private.ll
@@ -0,0 +1,24 @@
+; Test to make sure that the 'private' is used correctly.
+;
+; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu > %t
+; RUN: grep .Lfoo: %t
+; RUN: grep bl.*\.Lfoo %t
+; RUN: grep .Lbaz: %t
+; RUN: grep lis.*\.Lbaz %t
+; RUN: llc < %s -mtriple=powerpc-apple-darwin > %t
+; RUN: grep L_foo: %t
+; RUN: grep bl.*\L_foo %t
+; RUN: grep L_baz: %t
+; RUN: grep lis.*\L_baz %t
+
+define private void @foo() nounwind {
+ ret void
+}
+
+@baz = private global i32 4
+
+define i32 @bar() nounwind {
+ call void @foo()
+ %1 = load i32* @baz, align 4
+ ret i32 %1
+}
diff --git a/test/CodeGen/PowerPC/reg-coalesce-simple.ll b/test/CodeGen/PowerPC/reg-coalesce-simple.ll
new file mode 100644
index 0000000..e0ddb42
--- /dev/null
+++ b/test/CodeGen/PowerPC/reg-coalesce-simple.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=ppc32 | not grep or
+
+%struct.foo = type { i32, i32, [0 x i8] }
+
+define i32 @test(%struct.foo* %X) nounwind {
+ %tmp1 = getelementptr %struct.foo* %X, i32 0, i32 2, i32 100 ; <i8*> [#uses=1]
+ %tmp = load i8* %tmp1 ; <i8> [#uses=1]
+ %tmp2 = zext i8 %tmp to i32 ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
+
+
diff --git a/test/CodeGen/PowerPC/retaddr.ll b/test/CodeGen/PowerPC/retaddr.ll
new file mode 100644
index 0000000..9f8647d
--- /dev/null
+++ b/test/CodeGen/PowerPC/retaddr.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=ppc32 | grep mflr
+; RUN: llc < %s -march=ppc32 | grep lwz
+; RUN: llc < %s -march=ppc64 | grep {ld r., 16(r1)}
+
+target triple = "powerpc-apple-darwin8"
+
+define void @foo(i8** %X) {
+entry:
+ %tmp = tail call i8* @llvm.returnaddress( i32 0 ) ; <i8*> [#uses=1]
+ store i8* %tmp, i8** %X, align 4
+ ret void
+}
+
+declare i8* @llvm.returnaddress(i32)
+
diff --git a/test/CodeGen/PowerPC/return-val-i128.ll b/test/CodeGen/PowerPC/return-val-i128.ll
new file mode 100644
index 0000000..e14a438
--- /dev/null
+++ b/test/CodeGen/PowerPC/return-val-i128.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -march=ppc64
+
+define i128 @__fixsfdi(float %a) {
+entry:
+ %a_addr = alloca float ; <float*> [#uses=4]
+ %retval = alloca i128, align 16 ; <i128*> [#uses=2]
+ %tmp = alloca i128, align 16 ; <i128*> [#uses=3]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store float %a, float* %a_addr
+ %tmp1 = load float* %a_addr, align 4 ; <float> [#uses=1]
+ %tmp2 = fcmp olt float %tmp1, 0.000000e+00 ; <i1> [#uses=1]
+ %tmp23 = zext i1 %tmp2 to i8 ; <i8> [#uses=1]
+ %toBool = icmp ne i8 %tmp23, 0 ; <i1> [#uses=1]
+ br i1 %toBool, label %bb, label %bb8
+bb: ; preds = %entry
+ %tmp4 = load float* %a_addr, align 4 ; <float> [#uses=1]
+ %tmp5 = fsub float -0.000000e+00, %tmp4 ; <float> [#uses=1]
+ %tmp6 = call i128 @__fixunssfDI( float %tmp5 ) nounwind ; <i128> [#uses=1]
+ %tmp7 = sub i128 0, %tmp6 ; <i128> [#uses=1]
+ store i128 %tmp7, i128* %tmp, align 16
+ br label %bb11
+bb8: ; preds = %entry
+ %tmp9 = load float* %a_addr, align 4 ; <float> [#uses=1]
+ %tmp10 = call i128 @__fixunssfDI( float %tmp9 ) nounwind ; <i128> [#uses=1]
+ store i128 %tmp10, i128* %tmp, align 16
+ br label %bb11
+bb11: ; preds = %bb8, %bb
+ %tmp12 = load i128* %tmp, align 16 ; <i128> [#uses=1]
+ store i128 %tmp12, i128* %retval, align 16
+ br label %return
+return: ; preds = %bb11
+ %retval13 = load i128* %retval ; <i128> [#uses=1]
+ ret i128 %retval13
+}
+
+declare i128 @__fixunssfDI(float)
diff --git a/test/CodeGen/PowerPC/rlwimi-commute.ll b/test/CodeGen/PowerPC/rlwimi-commute.ll
new file mode 100644
index 0000000..6410c63
--- /dev/null
+++ b/test/CodeGen/PowerPC/rlwimi-commute.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=ppc32 | grep rlwimi
+; RUN: llc < %s -march=ppc32 | not grep {or }
+
+; Make sure there is no register-register copies here.
+
+define void @test1(i32* %A, i32* %B, i32* %D, i32* %E) {
+ %A.upgrd.1 = load i32* %A ; <i32> [#uses=2]
+ %B.upgrd.2 = load i32* %B ; <i32> [#uses=1]
+ %X = and i32 %A.upgrd.1, 15 ; <i32> [#uses=1]
+ %Y = and i32 %B.upgrd.2, -16 ; <i32> [#uses=1]
+ %Z = or i32 %X, %Y ; <i32> [#uses=1]
+ store i32 %Z, i32* %D
+ store i32 %A.upgrd.1, i32* %E
+ ret void
+}
+
+define void @test2(i32* %A, i32* %B, i32* %D, i32* %E) {
+ %A.upgrd.3 = load i32* %A ; <i32> [#uses=1]
+ %B.upgrd.4 = load i32* %B ; <i32> [#uses=2]
+ %X = and i32 %A.upgrd.3, 15 ; <i32> [#uses=1]
+ %Y = and i32 %B.upgrd.4, -16 ; <i32> [#uses=1]
+ %Z = or i32 %X, %Y ; <i32> [#uses=1]
+ store i32 %Z, i32* %D
+ store i32 %B.upgrd.4, i32* %E
+ ret void
+}
+
+define i32 @test3(i32 %a, i32 %b) {
+ %tmp.1 = and i32 %a, 15 ; <i32> [#uses=1]
+ %tmp.3 = and i32 %b, 240 ; <i32> [#uses=1]
+ %tmp.4 = or i32 %tmp.3, %tmp.1 ; <i32> [#uses=1]
+ ret i32 %tmp.4
+}
+
diff --git a/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll b/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll
new file mode 100644
index 0000000..7bce01c
--- /dev/null
+++ b/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s
+; Formerly dropped the RHS of %tmp6 when constructing rlwimi.
+; 7346117
+
+@foo = external global i32
+
+define void @xxx(i32 %a, i32 %b, i32 %c, i32 %d) nounwind optsize {
+; CHECK: _xxx:
+; CHECK: or
+; CHECK: and
+; CHECK: rlwimi
+entry:
+ %tmp0 = ashr i32 %d, 31
+ %tmp1 = and i32 %tmp0, 255
+ %tmp2 = xor i32 %tmp1, 255
+ %tmp3 = ashr i32 %b, 31
+ %tmp4 = ashr i32 %a, 4
+ %tmp5 = or i32 %tmp3, %tmp4
+ %tmp6 = and i32 %tmp2, %tmp5
+ %tmp7 = shl i32 %c, 8
+ %tmp8 = or i32 %tmp6, %tmp7
+ store i32 %tmp8, i32* @foo, align 4
+ br label %return
+
+return:
+ ret void
+; CHECK: blr
+}
\ No newline at end of file
diff --git a/test/CodeGen/PowerPC/rlwimi.ll b/test/CodeGen/PowerPC/rlwimi.ll
new file mode 100644
index 0000000..556ca3d
--- /dev/null
+++ b/test/CodeGen/PowerPC/rlwimi.ll
@@ -0,0 +1,70 @@
+; All of these ands and shifts should be folded into rlwimi's
+; RUN: llc < %s -march=ppc32 | not grep and
+; RUN: llc < %s -march=ppc32 | grep rlwimi | count 8
+
+define i32 @test1(i32 %x, i32 %y) {
+entry:
+ %tmp.3 = shl i32 %x, 16 ; <i32> [#uses=1]
+ %tmp.7 = and i32 %y, 65535 ; <i32> [#uses=1]
+ %tmp.9 = or i32 %tmp.7, %tmp.3 ; <i32> [#uses=1]
+ ret i32 %tmp.9
+}
+
+define i32 @test2(i32 %x, i32 %y) {
+entry:
+ %tmp.7 = and i32 %x, 65535 ; <i32> [#uses=1]
+ %tmp.3 = shl i32 %y, 16 ; <i32> [#uses=1]
+ %tmp.9 = or i32 %tmp.7, %tmp.3 ; <i32> [#uses=1]
+ ret i32 %tmp.9
+}
+
+define i32 @test3(i32 %x, i32 %y) {
+entry:
+ %tmp.3 = lshr i32 %x, 16 ; <i32> [#uses=1]
+ %tmp.6 = and i32 %y, -65536 ; <i32> [#uses=1]
+ %tmp.7 = or i32 %tmp.6, %tmp.3 ; <i32> [#uses=1]
+ ret i32 %tmp.7
+}
+
+define i32 @test4(i32 %x, i32 %y) {
+entry:
+ %tmp.6 = and i32 %x, -65536 ; <i32> [#uses=1]
+ %tmp.3 = lshr i32 %y, 16 ; <i32> [#uses=1]
+ %tmp.7 = or i32 %tmp.6, %tmp.3 ; <i32> [#uses=1]
+ ret i32 %tmp.7
+}
+
+define i32 @test5(i32 %x, i32 %y) {
+entry:
+ %tmp.3 = shl i32 %x, 1 ; <i32> [#uses=1]
+ %tmp.4 = and i32 %tmp.3, -65536 ; <i32> [#uses=1]
+ %tmp.7 = and i32 %y, 65535 ; <i32> [#uses=1]
+ %tmp.9 = or i32 %tmp.4, %tmp.7 ; <i32> [#uses=1]
+ ret i32 %tmp.9
+}
+
+define i32 @test6(i32 %x, i32 %y) {
+entry:
+ %tmp.7 = and i32 %x, 65535 ; <i32> [#uses=1]
+ %tmp.3 = shl i32 %y, 1 ; <i32> [#uses=1]
+ %tmp.4 = and i32 %tmp.3, -65536 ; <i32> [#uses=1]
+ %tmp.9 = or i32 %tmp.4, %tmp.7 ; <i32> [#uses=1]
+ ret i32 %tmp.9
+}
+
+define i32 @test7(i32 %x, i32 %y) {
+entry:
+ %tmp.2 = and i32 %x, -65536 ; <i32> [#uses=1]
+ %tmp.5 = and i32 %y, 65535 ; <i32> [#uses=1]
+ %tmp.7 = or i32 %tmp.5, %tmp.2 ; <i32> [#uses=1]
+ ret i32 %tmp.7
+}
+
+define i32 @test8(i32 %bar) {
+entry:
+ %tmp.3 = shl i32 %bar, 1 ; <i32> [#uses=1]
+ %tmp.4 = and i32 %tmp.3, 2 ; <i32> [#uses=1]
+ %tmp.6 = and i32 %bar, -3 ; <i32> [#uses=1]
+ %tmp.7 = or i32 %tmp.4, %tmp.6 ; <i32> [#uses=1]
+ ret i32 %tmp.7
+}
diff --git a/test/CodeGen/PowerPC/rlwimi2.ll b/test/CodeGen/PowerPC/rlwimi2.ll
new file mode 100644
index 0000000..59a3655
--- /dev/null
+++ b/test/CodeGen/PowerPC/rlwimi2.ll
@@ -0,0 +1,29 @@
+; All of these ands and shifts should be folded into rlwimi's
+; RUN: llc < %s -march=ppc32 -o %t
+; RUN: grep rlwimi %t | count 3
+; RUN: grep srwi %t | count 1
+; RUN: not grep slwi %t
+
+define i16 @test1(i32 %srcA, i32 %srcB, i32 %alpha) {
+entry:
+ %tmp.1 = shl i32 %srcA, 15 ; <i32> [#uses=1]
+ %tmp.4 = and i32 %tmp.1, 32505856 ; <i32> [#uses=1]
+ %tmp.6 = and i32 %srcA, 31775 ; <i32> [#uses=1]
+ %tmp.7 = or i32 %tmp.4, %tmp.6 ; <i32> [#uses=1]
+ %tmp.9 = shl i32 %srcB, 15 ; <i32> [#uses=1]
+ %tmp.12 = and i32 %tmp.9, 32505856 ; <i32> [#uses=1]
+ %tmp.14 = and i32 %srcB, 31775 ; <i32> [#uses=1]
+ %tmp.15 = or i32 %tmp.12, %tmp.14 ; <i32> [#uses=1]
+ %tmp.18 = mul i32 %tmp.7, %alpha ; <i32> [#uses=1]
+ %tmp.20 = sub i32 32, %alpha ; <i32> [#uses=1]
+ %tmp.22 = mul i32 %tmp.15, %tmp.20 ; <i32> [#uses=1]
+ %tmp.23 = add i32 %tmp.22, %tmp.18 ; <i32> [#uses=2]
+ %tmp.27 = lshr i32 %tmp.23, 5 ; <i32> [#uses=1]
+ %tmp.28 = trunc i32 %tmp.27 to i16 ; <i16> [#uses=1]
+ %tmp.29 = and i16 %tmp.28, 31775 ; <i16> [#uses=1]
+ %tmp.33 = lshr i32 %tmp.23, 20 ; <i32> [#uses=1]
+ %tmp.34 = trunc i32 %tmp.33 to i16 ; <i16> [#uses=1]
+ %tmp.35 = and i16 %tmp.34, 992 ; <i16> [#uses=1]
+ %tmp.36 = or i16 %tmp.29, %tmp.35 ; <i16> [#uses=1]
+ ret i16 %tmp.36
+}
diff --git a/test/CodeGen/PowerPC/rlwimi3.ll b/test/CodeGen/PowerPC/rlwimi3.ll
new file mode 100644
index 0000000..05d37bf
--- /dev/null
+++ b/test/CodeGen/PowerPC/rlwimi3.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=ppc32 -stats |& \
+; RUN: grep {Number of machine instrs printed} | grep 12
+
+define i16 @Trans16Bit(i32 %srcA, i32 %srcB, i32 %alpha) {
+ %tmp1 = shl i32 %srcA, 15 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 32505856 ; <i32> [#uses=1]
+ %tmp4 = and i32 %srcA, 31775 ; <i32> [#uses=1]
+ %tmp5 = or i32 %tmp2, %tmp4 ; <i32> [#uses=1]
+ %tmp7 = shl i32 %srcB, 15 ; <i32> [#uses=1]
+ %tmp8 = and i32 %tmp7, 32505856 ; <i32> [#uses=1]
+ %tmp10 = and i32 %srcB, 31775 ; <i32> [#uses=1]
+ %tmp11 = or i32 %tmp8, %tmp10 ; <i32> [#uses=1]
+ %tmp14 = mul i32 %tmp5, %alpha ; <i32> [#uses=1]
+ %tmp16 = sub i32 32, %alpha ; <i32> [#uses=1]
+ %tmp18 = mul i32 %tmp11, %tmp16 ; <i32> [#uses=1]
+ %tmp19 = add i32 %tmp18, %tmp14 ; <i32> [#uses=2]
+ %tmp21 = lshr i32 %tmp19, 5 ; <i32> [#uses=1]
+ %tmp21.upgrd.1 = trunc i32 %tmp21 to i16 ; <i16> [#uses=1]
+ %tmp = and i16 %tmp21.upgrd.1, 31775 ; <i16> [#uses=1]
+ %tmp23 = lshr i32 %tmp19, 20 ; <i32> [#uses=1]
+ %tmp23.upgrd.2 = trunc i32 %tmp23 to i16 ; <i16> [#uses=1]
+ %tmp24 = and i16 %tmp23.upgrd.2, 992 ; <i16> [#uses=1]
+ %tmp25 = or i16 %tmp, %tmp24 ; <i16> [#uses=1]
+ ret i16 %tmp25
+}
diff --git a/test/CodeGen/PowerPC/rlwinm.ll b/test/CodeGen/PowerPC/rlwinm.ll
new file mode 100644
index 0000000..699f6e7
--- /dev/null
+++ b/test/CodeGen/PowerPC/rlwinm.ll
@@ -0,0 +1,61 @@
+; All of these ands and shifts should be folded into rlwimi's
+; RUN: llc < %s -march=ppc32 -o %t
+; RUN: not grep and %t
+; RUN: not grep srawi %t
+; RUN: not grep srwi %t
+; RUN: not grep slwi %t
+; RUN: grep rlwinm %t | count 8
+
+define i32 @test1(i32 %a) {
+entry:
+ %tmp.1 = and i32 %a, 268431360 ; <i32> [#uses=1]
+ ret i32 %tmp.1
+}
+
+define i32 @test2(i32 %a) {
+entry:
+ %tmp.1 = and i32 %a, -268435441 ; <i32> [#uses=1]
+ ret i32 %tmp.1
+}
+
+define i32 @test3(i32 %a) {
+entry:
+ %tmp.2 = ashr i32 %a, 8 ; <i32> [#uses=1]
+ %tmp.3 = and i32 %tmp.2, 255 ; <i32> [#uses=1]
+ ret i32 %tmp.3
+}
+
+define i32 @test4(i32 %a) {
+entry:
+ %tmp.3 = lshr i32 %a, 8 ; <i32> [#uses=1]
+ %tmp.4 = and i32 %tmp.3, 255 ; <i32> [#uses=1]
+ ret i32 %tmp.4
+}
+
+define i32 @test5(i32 %a) {
+entry:
+ %tmp.2 = shl i32 %a, 8 ; <i32> [#uses=1]
+ %tmp.3 = and i32 %tmp.2, -8388608 ; <i32> [#uses=1]
+ ret i32 %tmp.3
+}
+
+define i32 @test6(i32 %a) {
+entry:
+ %tmp.1 = and i32 %a, 65280 ; <i32> [#uses=1]
+ %tmp.2 = ashr i32 %tmp.1, 8 ; <i32> [#uses=1]
+ ret i32 %tmp.2
+}
+
+define i32 @test7(i32 %a) {
+entry:
+ %tmp.1 = and i32 %a, 65280 ; <i32> [#uses=1]
+ %tmp.2 = lshr i32 %tmp.1, 8 ; <i32> [#uses=1]
+ ret i32 %tmp.2
+}
+
+define i32 @test8(i32 %a) {
+entry:
+ %tmp.1 = and i32 %a, 16711680 ; <i32> [#uses=1]
+ %tmp.2 = shl i32 %tmp.1, 8 ; <i32> [#uses=1]
+ ret i32 %tmp.2
+}
diff --git a/test/CodeGen/PowerPC/rlwinm2.ll b/test/CodeGen/PowerPC/rlwinm2.ll
new file mode 100644
index 0000000..46542d8
--- /dev/null
+++ b/test/CodeGen/PowerPC/rlwinm2.ll
@@ -0,0 +1,28 @@
+; All of these ands and shifts should be folded into rlw[i]nm instructions
+; RUN: llc < %s -march=ppc32 -o %t
+; RUN: not grep and %t
+; RUN: not grep srawi %t
+; RUN: not grep srwi %t
+; RUN: not grep slwi %t
+; RUN: grep rlwnm %t | count 1
+; RUN: grep rlwinm %t | count 1
+
+define i32 @test1(i32 %X, i32 %Y) {
+entry:
+ %tmp = trunc i32 %Y to i8 ; <i8> [#uses=2]
+ %tmp1 = shl i32 %X, %Y ; <i32> [#uses=1]
+ %tmp2 = sub i32 32, %Y ; <i8> [#uses=1]
+ %tmp3 = lshr i32 %X, %tmp2 ; <i32> [#uses=1]
+ %tmp4 = or i32 %tmp1, %tmp3 ; <i32> [#uses=1]
+ %tmp6 = and i32 %tmp4, 127 ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+define i32 @test2(i32 %X) {
+entry:
+ %tmp1 = lshr i32 %X, 27 ; <i32> [#uses=1]
+ %tmp2 = shl i32 %X, 5 ; <i32> [#uses=1]
+ %tmp2.masked = and i32 %tmp2, 96 ; <i32> [#uses=1]
+ %tmp5 = or i32 %tmp1, %tmp2.masked ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
diff --git a/test/CodeGen/PowerPC/rotl-2.ll b/test/CodeGen/PowerPC/rotl-2.ll
new file mode 100644
index 0000000..d32ef59
--- /dev/null
+++ b/test/CodeGen/PowerPC/rotl-2.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -march=ppc32 | grep rlwinm | count 4
+; RUN: llc < %s -march=ppc32 | grep rlwnm | count 2
+; RUN: llc < %s -march=ppc32 | not grep or
+
+define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
+ %shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
+ %B = shl i32 %A, %shift.upgrd.1 ; <i32> [#uses=1]
+ %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
+ %shift.upgrd.2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
+ %C = lshr i32 %A, %shift.upgrd.2 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+define i32 @rotr32(i32 %A, i8 %Amt) nounwind {
+ %shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
+ %B = lshr i32 %A, %shift.upgrd.3 ; <i32> [#uses=1]
+ %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
+ %shift.upgrd.4 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
+ %C = shl i32 %A, %shift.upgrd.4 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+define i32 @rotli32(i32 %A) nounwind {
+ %B = shl i32 %A, 5 ; <i32> [#uses=1]
+ %C = lshr i32 %A, 27 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+define i32 @rotri32(i32 %A) nounwind {
+ %B = lshr i32 %A, 5 ; <i32> [#uses=1]
+ %C = shl i32 %A, 27 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
diff --git a/test/CodeGen/PowerPC/rotl-64.ll b/test/CodeGen/PowerPC/rotl-64.ll
new file mode 100644
index 0000000..674c9e4
--- /dev/null
+++ b/test/CodeGen/PowerPC/rotl-64.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=ppc64 | grep rldicl
+; RUN: llc < %s -march=ppc64 | grep rldcl
+; PR1613
+
+define i64 @t1(i64 %A) {
+ %tmp1 = lshr i64 %A, 57
+ %tmp2 = shl i64 %A, 7
+ %tmp3 = or i64 %tmp1, %tmp2
+ ret i64 %tmp3
+}
+
+define i64 @t2(i64 %A, i8 zeroext %Amt) {
+ %Amt1 = zext i8 %Amt to i64
+ %tmp1 = lshr i64 %A, %Amt1
+ %Amt2 = sub i8 64, %Amt
+ %Amt3 = zext i8 %Amt2 to i64
+ %tmp2 = shl i64 %A, %Amt3
+ %tmp3 = or i64 %tmp1, %tmp2
+ ret i64 %tmp3
+}
diff --git a/test/CodeGen/PowerPC/rotl.ll b/test/CodeGen/PowerPC/rotl.ll
new file mode 100644
index 0000000..56fc4a8
--- /dev/null
+++ b/test/CodeGen/PowerPC/rotl.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=ppc32 | grep rlwnm | count 2
+; RUN: llc < %s -march=ppc32 | grep rlwinm | count 2
+
+define i32 @rotlw(i32 %x, i32 %sh) {
+entry:
+ %tmp.7 = sub i32 32, %sh ; <i32> [#uses=1]
+ %tmp.10 = lshr i32 %x, %tmp.7 ; <i32> [#uses=2]
+ %tmp.4 = shl i32 %x, %sh ; <i32> [#uses=1]
+ %tmp.12 = or i32 %tmp.10, %tmp.4 ; <i32> [#uses=1]
+ ret i32 %tmp.12
+}
+
+define i32 @rotrw(i32 %x, i32 %sh) {
+entry:
+ %tmp.3 = trunc i32 %sh to i8 ; <i8> [#uses=1]
+ %tmp.4 = lshr i32 %x, %sh ; <i32> [#uses=2]
+ %tmp.7 = sub i32 32, %sh ; <i32> [#uses=1]
+ %tmp.10 = shl i32 %x, %tmp.7 ; <i32> [#uses=1]
+ %tmp.12 = or i32 %tmp.4, %tmp.10 ; <i32> [#uses=1]
+ ret i32 %tmp.12
+}
+
+define i32 @rotlwi(i32 %x) {
+entry:
+ %tmp.7 = lshr i32 %x, 27 ; <i32> [#uses=2]
+ %tmp.3 = shl i32 %x, 5 ; <i32> [#uses=1]
+ %tmp.9 = or i32 %tmp.3, %tmp.7 ; <i32> [#uses=1]
+ ret i32 %tmp.9
+}
+
+define i32 @rotrwi(i32 %x) {
+entry:
+ %tmp.3 = lshr i32 %x, 5 ; <i32> [#uses=2]
+ %tmp.7 = shl i32 %x, 27 ; <i32> [#uses=1]
+ %tmp.9 = or i32 %tmp.3, %tmp.7 ; <i32> [#uses=1]
+ ret i32 %tmp.9
+}
diff --git a/test/CodeGen/PowerPC/sections.ll b/test/CodeGen/PowerPC/sections.ll
new file mode 100644
index 0000000..0ff4a89
--- /dev/null
+++ b/test/CodeGen/PowerPC/sections.ll
@@ -0,0 +1,8 @@
+; Test to make sure that bss sections are printed with '.section' directive.
+; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
+
+@A = global i32 0
+
+; CHECK: .section .bss,"aw",@nobits
+; CHECK: .globl A
+
diff --git a/test/CodeGen/PowerPC/select-cc.ll b/test/CodeGen/PowerPC/select-cc.ll
new file mode 100644
index 0000000..ccc6489
--- /dev/null
+++ b/test/CodeGen/PowerPC/select-cc.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=ppc32
+; PR3011
+
+define <2 x double> @vector_select(<2 x double> %x, <2 x double> %y) nounwind {
+ %x.lo = extractelement <2 x double> %x, i32 0 ; <double> [#uses=1]
+ %x.lo.ge = fcmp oge double %x.lo, 0.000000e+00 ; <i1> [#uses=1]
+ %a.d = select i1 %x.lo.ge, <2 x double> %y, <2 x double> %x ; <<2 x double>> [#uses=1]
+ ret <2 x double> %a.d
+}
diff --git a/test/CodeGen/PowerPC/select_lt0.ll b/test/CodeGen/PowerPC/select_lt0.ll
new file mode 100644
index 0000000..95ba84a
--- /dev/null
+++ b/test/CodeGen/PowerPC/select_lt0.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -march=ppc32 | not grep cmp
+
+define i32 @seli32_1(i32 %a) {
+entry:
+ %tmp.1 = icmp slt i32 %a, 0 ; <i1> [#uses=1]
+ %retval = select i1 %tmp.1, i32 5, i32 0 ; <i32> [#uses=1]
+ ret i32 %retval
+}
+
+define i32 @seli32_2(i32 %a, i32 %b) {
+entry:
+ %tmp.1 = icmp slt i32 %a, 0 ; <i1> [#uses=1]
+ %retval = select i1 %tmp.1, i32 %b, i32 0 ; <i32> [#uses=1]
+ ret i32 %retval
+}
+
+define i32 @seli32_3(i32 %a, i16 %b) {
+entry:
+ %tmp.2 = sext i16 %b to i32 ; <i32> [#uses=1]
+ %tmp.1 = icmp slt i32 %a, 0 ; <i1> [#uses=1]
+ %retval = select i1 %tmp.1, i32 %tmp.2, i32 0 ; <i32> [#uses=1]
+ ret i32 %retval
+}
+
+define i32 @seli32_4(i32 %a, i16 %b) {
+entry:
+ %tmp.2 = zext i16 %b to i32 ; <i32> [#uses=1]
+ %tmp.1 = icmp slt i32 %a, 0 ; <i1> [#uses=1]
+ %retval = select i1 %tmp.1, i32 %tmp.2, i32 0 ; <i32> [#uses=1]
+ ret i32 %retval
+}
+
+define i16 @seli16_1(i16 %a) {
+entry:
+ %tmp.1 = icmp slt i16 %a, 0 ; <i1> [#uses=1]
+ %retval = select i1 %tmp.1, i16 7, i16 0 ; <i16> [#uses=1]
+ ret i16 %retval
+}
+
+define i16 @seli16_2(i32 %a, i16 %b) {
+ %tmp.1 = icmp slt i32 %a, 0 ; <i1> [#uses=1]
+ %retval = select i1 %tmp.1, i16 %b, i16 0 ; <i16> [#uses=1]
+ ret i16 %retval
+}
+
+define i32 @seli32_a_a(i32 %a) {
+ %tmp = icmp slt i32 %a, 1 ; <i1> [#uses=1]
+ %min = select i1 %tmp, i32 %a, i32 0 ; <i32> [#uses=1]
+ ret i32 %min
+}
diff --git a/test/CodeGen/PowerPC/setcc_no_zext.ll b/test/CodeGen/PowerPC/setcc_no_zext.ll
new file mode 100644
index 0000000..9b2036e
--- /dev/null
+++ b/test/CodeGen/PowerPC/setcc_no_zext.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=ppc32 | not grep rlwinm
+
+define i32 @setcc_one_or_zero(i32* %a) {
+entry:
+ %tmp.1 = icmp ne i32* %a, null ; <i1> [#uses=1]
+ %inc.1 = zext i1 %tmp.1 to i32 ; <i32> [#uses=1]
+ ret i32 %inc.1
+}
+
diff --git a/test/CodeGen/PowerPC/seteq-0.ll b/test/CodeGen/PowerPC/seteq-0.ll
new file mode 100644
index 0000000..688b29a
--- /dev/null
+++ b/test/CodeGen/PowerPC/seteq-0.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
+; RUN: grep {srwi r., r., 5}
+
+define i32 @eq0(i32 %a) {
+ %tmp.1 = icmp eq i32 %a, 0 ; <i1> [#uses=1]
+ %tmp.2 = zext i1 %tmp.1 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp.2
+}
+
diff --git a/test/CodeGen/PowerPC/shift128.ll b/test/CodeGen/PowerPC/shift128.ll
new file mode 100644
index 0000000..8e518c1
--- /dev/null
+++ b/test/CodeGen/PowerPC/shift128.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=ppc64 | grep sld | count 5
+
+define i128 @foo_lshr(i128 %x, i128 %y) {
+ %r = lshr i128 %x, %y
+ ret i128 %r
+}
+define i128 @foo_ashr(i128 %x, i128 %y) {
+ %r = ashr i128 %x, %y
+ ret i128 %r
+}
+define i128 @foo_shl(i128 %x, i128 %y) {
+ %r = shl i128 %x, %y
+ ret i128 %r
+}
diff --git a/test/CodeGen/PowerPC/shl_elim.ll b/test/CodeGen/PowerPC/shl_elim.ll
new file mode 100644
index 0000000..f177c4a
--- /dev/null
+++ b/test/CodeGen/PowerPC/shl_elim.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=ppc32 | not grep slwi
+
+define i32 @test1(i64 %a) {
+ %tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1]
+ %tmp23 = trunc i64 %tmp29 to i32 ; <i32> [#uses=1]
+ %tmp410 = lshr i32 %tmp23, 9 ; <i32> [#uses=1]
+ %tmp45 = trunc i32 %tmp410 to i16 ; <i16> [#uses=1]
+ %tmp456 = sext i16 %tmp45 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp456
+}
+
diff --git a/test/CodeGen/PowerPC/shl_sext.ll b/test/CodeGen/PowerPC/shl_sext.ll
new file mode 100644
index 0000000..1f35eb4
--- /dev/null
+++ b/test/CodeGen/PowerPC/shl_sext.ll
@@ -0,0 +1,18 @@
+; This test should not contain a sign extend
+; RUN: llc < %s -march=ppc32 | not grep extsb
+
+define i32 @test(i32 %mode.0.i.0) {
+ %tmp.79 = trunc i32 %mode.0.i.0 to i8 ; <i8> [#uses=1]
+ %tmp.80 = sext i8 %tmp.79 to i32 ; <i32> [#uses=1]
+ %tmp.81 = shl i32 %tmp.80, 24 ; <i32> [#uses=1]
+ ret i32 %tmp.81
+}
+
+define i32 @test2(i32 %mode.0.i.0) {
+ %tmp.79 = trunc i32 %mode.0.i.0 to i8 ; <i8> [#uses=1]
+ %tmp.80 = sext i8 %tmp.79 to i32 ; <i32> [#uses=1]
+ %tmp.81 = shl i32 %tmp.80, 16 ; <i32> [#uses=1]
+ %tmp.82 = and i32 %tmp.81, 16711680 ; <i32> [#uses=1]
+ ret i32 %tmp.82
+}
+
diff --git a/test/CodeGen/PowerPC/sign_ext_inreg1.ll b/test/CodeGen/PowerPC/sign_ext_inreg1.ll
new file mode 100644
index 0000000..2679c8e
--- /dev/null
+++ b/test/CodeGen/PowerPC/sign_ext_inreg1.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=ppc32 | grep srwi
+; RUN: llc < %s -march=ppc32 | not grep rlwimi
+
+define i32 @baz(i64 %a) {
+ %tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1]
+ %tmp23 = trunc i64 %tmp29 to i32 ; <i32> [#uses=1]
+ %tmp410 = lshr i32 %tmp23, 9 ; <i32> [#uses=1]
+ %tmp45 = trunc i32 %tmp410 to i16 ; <i16> [#uses=1]
+ %tmp456 = sext i16 %tmp45 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp456
+}
+
diff --git a/test/CodeGen/PowerPC/small-arguments.ll b/test/CodeGen/PowerPC/small-arguments.ll
new file mode 100644
index 0000000..31bcee6
--- /dev/null
+++ b/test/CodeGen/PowerPC/small-arguments.ll
@@ -0,0 +1,52 @@
+; RUN: llc < %s -march=ppc32 | not grep {extsh\\|rlwinm}
+
+declare i16 @foo() signext
+
+define i32 @test1(i16 signext %X) {
+ %Y = sext i16 %X to i32 ;; dead
+ ret i32 %Y
+}
+
+define i32 @test2(i16 zeroext %X) {
+ %Y = sext i16 %X to i32
+ %Z = and i32 %Y, 65535 ;; dead
+ ret i32 %Z
+}
+
+define void @test3() {
+ %tmp.0 = call i16 @foo() signext ;; no extsh!
+ %tmp.1 = icmp slt i16 %tmp.0, 1234
+ br i1 %tmp.1, label %then, label %UnifiedReturnBlock
+
+then:
+ call i32 @test1(i16 0 signext)
+ ret void
+UnifiedReturnBlock:
+ ret void
+}
+
+define i32 @test4(i16* %P) {
+ %tmp.1 = load i16* %P
+ %tmp.2 = zext i16 %tmp.1 to i32
+ %tmp.3 = and i32 %tmp.2, 255
+ ret i32 %tmp.3
+}
+
+define i32 @test5(i16* %P) {
+ %tmp.1 = load i16* %P
+ %tmp.2 = bitcast i16 %tmp.1 to i16
+ %tmp.3 = zext i16 %tmp.2 to i32
+ %tmp.4 = and i32 %tmp.3, 255
+ ret i32 %tmp.4
+}
+
+define i32 @test6(i32* %P) {
+ %tmp.1 = load i32* %P
+ %tmp.2 = and i32 %tmp.1, 255
+ ret i32 %tmp.2
+}
+
+define i16 @test7(float %a) zeroext {
+ %tmp.1 = fptoui float %a to i16
+ ret i16 %tmp.1
+}
diff --git a/test/CodeGen/PowerPC/stfiwx-2.ll b/test/CodeGen/PowerPC/stfiwx-2.ll
new file mode 100644
index 0000000..c49b25c
--- /dev/null
+++ b/test/CodeGen/PowerPC/stfiwx-2.ll
@@ -0,0 +1,11 @@
+; This cannot be a stfiwx
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep stb
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep stfiwx
+
+define void @test(float %F, i8* %P) {
+ %I = fptosi float %F to i32
+ %X = trunc i32 %I to i8
+ store i8 %X, i8* %P
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/stfiwx.ll b/test/CodeGen/PowerPC/stfiwx.ll
new file mode 100644
index 0000000..d1c3f52
--- /dev/null
+++ b/test/CodeGen/PowerPC/stfiwx.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=stfiwx -o %t1
+; RUN: grep stfiwx %t1
+; RUN: not grep r1 %t1
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-stfiwx \
+; RUN: -o %t2
+; RUN: not grep stfiwx %t2
+; RUN: grep r1 %t2
+
+define void @test(float %a, i32* %b) {
+ %tmp.2 = fptosi float %a to i32 ; <i32> [#uses=1]
+ store i32 %tmp.2, i32* %b
+ ret void
+}
+
+define void @test2(float %a, i32* %b, i32 %i) {
+ %tmp.2 = getelementptr i32* %b, i32 1 ; <i32*> [#uses=1]
+ %tmp.5 = getelementptr i32* %b, i32 %i ; <i32*> [#uses=1]
+ %tmp.7 = fptosi float %a to i32 ; <i32> [#uses=3]
+ store i32 %tmp.7, i32* %tmp.5
+ store i32 %tmp.7, i32* %tmp.2
+ store i32 %tmp.7, i32* %b
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/store-load-fwd.ll b/test/CodeGen/PowerPC/store-load-fwd.ll
new file mode 100644
index 0000000..25663c1
--- /dev/null
+++ b/test/CodeGen/PowerPC/store-load-fwd.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=ppc32 | not grep lwz
+
+define i32 @test(i32* %P) {
+ store i32 1, i32* %P
+ %V = load i32* %P ; <i32> [#uses=1]
+ ret i32 %V
+}
+
diff --git a/test/CodeGen/PowerPC/stubs.ll b/test/CodeGen/PowerPC/stubs.ll
new file mode 100644
index 0000000..4889263
--- /dev/null
+++ b/test/CodeGen/PowerPC/stubs.ll
@@ -0,0 +1,22 @@
+; RUN: llc %s -o - -mtriple=powerpc-apple-darwin8 | FileCheck %s
+define ppc_fp128 @test1(i64 %X) nounwind readnone {
+entry:
+ %0 = sitofp i64 %X to ppc_fp128
+ ret ppc_fp128 %0
+}
+
+; CHECK: _test1:
+; CHECK: bl ___floatditf$stub
+; CHECK: .section __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16
+; CHECK: ___floatditf$stub:
+; CHECK: .indirect_symbol ___floatditf
+; CHECK: lis r11,ha16(___floatditf$lazy_ptr)
+; CHECK: lwzu r12,lo16(___floatditf$lazy_ptr)(r11)
+; CHECK: mtctr r12
+; CHECK: bctr
+; CHECK: .section __DATA,__la_symbol_ptr,lazy_symbol_pointers
+; CHECK: ___floatditf$lazy_ptr:
+; CHECK: .indirect_symbol ___floatditf
+; CHECK: .long dyld_stub_binding_helper
+
+
diff --git a/test/CodeGen/PowerPC/subc.ll b/test/CodeGen/PowerPC/subc.ll
new file mode 100644
index 0000000..5914dca
--- /dev/null
+++ b/test/CodeGen/PowerPC/subc.ll
@@ -0,0 +1,25 @@
+; All of these should be codegen'd without loading immediates
+; RUN: llc < %s -march=ppc32 -o %t
+; RUN: grep subfc %t | count 1
+; RUN: grep subfe %t | count 1
+; RUN: grep subfze %t | count 1
+; RUN: grep subfme %t | count 1
+; RUN: grep subfic %t | count 2
+
+define i64 @sub_ll(i64 %a, i64 %b) {
+entry:
+ %tmp.2 = sub i64 %a, %b ; <i64> [#uses=1]
+ ret i64 %tmp.2
+}
+
+define i64 @sub_l_5(i64 %a) {
+entry:
+ %tmp.1 = sub i64 5, %a ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
+define i64 @sub_l_m5(i64 %a) {
+entry:
+ %tmp.1 = sub i64 -5, %a ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
diff --git a/test/CodeGen/PowerPC/tailcall1-64.ll b/test/CodeGen/PowerPC/tailcall1-64.ll
new file mode 100644
index 0000000..e9c83a5
--- /dev/null
+++ b/test/CodeGen/PowerPC/tailcall1-64.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=ppc64 -tailcallopt | grep TC_RETURNd8
+define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
+entry:
+ ret i32 %a3
+}
+
+define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
+entry:
+ %tmp11 = tail call fastcc i32 @tailcallee( i32 %in1, i32 %in2, i32 %in1, i32 %in2 ) ; <i32> [#uses=1]
+ ret i32 %tmp11
+}
diff --git a/test/CodeGen/PowerPC/tailcall1.ll b/test/CodeGen/PowerPC/tailcall1.ll
new file mode 100644
index 0000000..08f3392
--- /dev/null
+++ b/test/CodeGen/PowerPC/tailcall1.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=ppc32 -tailcallopt | grep TC_RETURN
+define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
+entry:
+ ret i32 %a3
+}
+
+define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
+entry:
+ %tmp11 = tail call fastcc i32 @tailcallee( i32 %in1, i32 %in2, i32 %in1, i32 %in2 ) ; <i32> [#uses=1]
+ ret i32 %tmp11
+}
diff --git a/test/CodeGen/PowerPC/tailcallpic1.ll b/test/CodeGen/PowerPC/tailcallpic1.ll
new file mode 100644
index 0000000..f3f5028
--- /dev/null
+++ b/test/CodeGen/PowerPC/tailcallpic1.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -tailcallopt -mtriple=powerpc-apple-darwin -relocation-model=pic | grep TC_RETURN
+
+
+
+define protected fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
+entry:
+ ret i32 %a3
+}
+
+define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
+entry:
+ %tmp11 = tail call fastcc i32 @tailcallee( i32 %in1, i32 %in2, i32 %in1, i32 %in2 ) ; <i32> [#uses=1]
+ ret i32 %tmp11
+}
diff --git a/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll b/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll
new file mode 100644
index 0000000..8a1288a
--- /dev/null
+++ b/test/CodeGen/PowerPC/tango.net.ftp.FtpClient.ll
@@ -0,0 +1,583 @@
+; RUN: llc < %s
+; PR4534
+
+; ModuleID = 'tango.net.ftp.FtpClient.bc'
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin9.6.0"
+ %"byte[]" = type { i32, i8* }
[email protected] = external constant [11 x i8] ; <[11 x i8]*> [#uses=1]
[email protected] = external constant [11 x i8] ; <[11 x i8]*> [#uses=2]
[email protected] = external constant [5 x i8] ; <[5 x i8]*> [#uses=1]
[email protected] = appending global [1 x i8*] [i8* bitcast (void (%"byte[]")* @foo to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define fastcc void @foo(%"byte[]" %line_arg) {
+entry:
+ %line_arg830 = extractvalue %"byte[]" %line_arg, 0 ; <i32> [#uses=12]
+ %line_arg831 = extractvalue %"byte[]" %line_arg, 1 ; <i8*> [#uses=17]
+ %t5 = load i8* %line_arg831 ; <i8> [#uses=1]
+ br label %forcondi
+
+forcondi: ; preds = %forbodyi, %entry
+ %l.0i = phi i32 [ 10, %entry ], [ %t4i, %forbodyi ] ; <i32> [#uses=2]
+ %p.0i = phi i8* [ getelementptr ([11 x i8]* @.str167, i32 0, i32 -1), %entry ], [ %t7i, %forbodyi ] ; <i8*> [#uses=1]
+ %t4i = add i32 %l.0i, -1 ; <i32> [#uses=1]
+ %t5i = icmp eq i32 %l.0i, 0 ; <i1> [#uses=1]
+ br i1 %t5i, label %forcond.i, label %forbodyi
+
+forbodyi: ; preds = %forcondi
+ %t7i = getelementptr i8* %p.0i, i32 1 ; <i8*> [#uses=2]
+ %t8i = load i8* %t7i ; <i8> [#uses=1]
+ %t12i = icmp eq i8 %t8i, %t5 ; <i1> [#uses=1]
+ br i1 %t12i, label %forcond.i, label %forcondi
+
+forcond.i: ; preds = %forbody.i, %forbodyi, %forcondi
+ %storemerge.i = phi i32 [ %t106.i, %forbody.i ], [ 1, %forcondi ], [ 1, %forbodyi ] ; <i32> [#uses=1]
+ %t77.i286 = phi i1 [ %phit3, %forbody.i ], [ false, %forcondi ], [ false, %forbodyi ] ; <i1> [#uses=1]
+ br i1 %t77.i286, label %forcond.i295, label %forbody.i
+
+forbody.i: ; preds = %forcond.i
+ %t106.i = add i32 %storemerge.i, 1 ; <i32> [#uses=2]
+ %phit3 = icmp ugt i32 %t106.i, 3 ; <i1> [#uses=1]
+ br label %forcond.i
+
+forcond.i295: ; preds = %forbody.i301, %forcond.i
+ %storemerge.i292 = phi i32 [ %t106.i325, %forbody.i301 ], [ 4, %forcond.i ] ; <i32> [#uses=1]
+ %t77.i293 = phi i1 [ %phit2, %forbody.i301 ], [ false, %forcond.i ] ; <i1> [#uses=1]
+ br i1 %t77.i293, label %forcond.i332, label %forbody.i301
+
+forbody.i301: ; preds = %forcond.i295
+ %t106.i325 = add i32 %storemerge.i292, 1 ; <i32> [#uses=2]
+ %phit2 = icmp ugt i32 %t106.i325, 6 ; <i1> [#uses=1]
+ br label %forcond.i295
+
+forcond.i332: ; preds = %forbody.i338, %forcond.i295
+ %storemerge.i329 = phi i32 [ %t106.i362, %forbody.i338 ], [ 7, %forcond.i295 ] ; <i32> [#uses=3]
+ %t77.i330 = phi i1 [ %phit1, %forbody.i338 ], [ false, %forcond.i295 ] ; <i1> [#uses=1]
+ br i1 %t77.i330, label %wcond.i370, label %forbody.i338
+
+forbody.i338: ; preds = %forcond.i332
+ %t106.i362 = add i32 %storemerge.i329, 1 ; <i32> [#uses=2]
+ %phit1 = icmp ugt i32 %t106.i362, 9 ; <i1> [#uses=1]
+ br label %forcond.i332
+
+wcond.i370: ; preds = %wbody.i372, %forcond.i332
+ %.frame.0.11 = phi i32 [ %t18.i371.c, %wbody.i372 ], [ %storemerge.i329, %forcond.i332 ] ; <i32> [#uses=2]
+ %t3.i368 = phi i32 [ %t18.i371.c, %wbody.i372 ], [ %storemerge.i329, %forcond.i332 ] ; <i32> [#uses=5]
+ %t4.i369 = icmp ult i32 %t3.i368, %line_arg830 ; <i1> [#uses=1]
+ br i1 %t4.i369, label %andand.i378, label %wcond22.i383
+
+wbody.i372: ; preds = %andand.i378
+ %t18.i371.c = add i32 %t3.i368, 1 ; <i32> [#uses=2]
+ br label %wcond.i370
+
+andand.i378: ; preds = %wcond.i370
+ %t11.i375 = getelementptr i8* %line_arg831, i32 %t3.i368 ; <i8*> [#uses=1]
+ %t12.i376 = load i8* %t11.i375 ; <i8> [#uses=1]
+ %t14.i377 = icmp eq i8 %t12.i376, 32 ; <i1> [#uses=1]
+ br i1 %t14.i377, label %wbody.i372, label %wcond22.i383
+
+wcond22.i383: ; preds = %wbody23.i385, %andand.i378, %wcond.i370
+ %.frame.0.10 = phi i32 [ %t50.i384, %wbody23.i385 ], [ %.frame.0.11, %wcond.i370 ], [ %.frame.0.11, %andand.i378 ] ; <i32> [#uses=2]
+ %t49.i381 = phi i32 [ %t50.i384, %wbody23.i385 ], [ %t3.i368, %wcond.i370 ], [ %t3.i368, %andand.i378 ] ; <i32> [#uses=5]
+ %t32.i382 = icmp ult i32 %t49.i381, %line_arg830 ; <i1> [#uses=1]
+ br i1 %t32.i382, label %andand33.i391, label %wcond54.i396
+
+wbody23.i385: ; preds = %andand33.i391
+ %t50.i384 = add i32 %t49.i381, 1 ; <i32> [#uses=2]
+ br label %wcond22.i383
+
+andand33.i391: ; preds = %wcond22.i383
+ %t42.i388 = getelementptr i8* %line_arg831, i32 %t49.i381 ; <i8*> [#uses=1]
+ %t43.i389 = load i8* %t42.i388 ; <i8> [#uses=1]
+ %t45.i390 = icmp eq i8 %t43.i389, 32 ; <i1> [#uses=1]
+ br i1 %t45.i390, label %wcond54.i396, label %wbody23.i385
+
+wcond54.i396: ; preds = %wbody55.i401, %andand33.i391, %wcond22.i383
+ %.frame.0.9 = phi i32 [ %t82.i400, %wbody55.i401 ], [ %.frame.0.10, %wcond22.i383 ], [ %.frame.0.10, %andand33.i391 ] ; <i32> [#uses=2]
+ %t81.i394 = phi i32 [ %t82.i400, %wbody55.i401 ], [ %t49.i381, %wcond22.i383 ], [ %t49.i381, %andand33.i391 ] ; <i32> [#uses=3]
+ %t64.i395 = icmp ult i32 %t81.i394, %line_arg830 ; <i1> [#uses=1]
+ br i1 %t64.i395, label %andand65.i407, label %wcond.i716
+
+wbody55.i401: ; preds = %andand65.i407
+ %t82.i400 = add i32 %t81.i394, 1 ; <i32> [#uses=2]
+ br label %wcond54.i396
+
+andand65.i407: ; preds = %wcond54.i396
+ %t74.i404 = getelementptr i8* %line_arg831, i32 %t81.i394 ; <i8*> [#uses=1]
+ %t75.i405 = load i8* %t74.i404 ; <i8> [#uses=1]
+ %t77.i406 = icmp eq i8 %t75.i405, 32 ; <i1> [#uses=1]
+ br i1 %t77.i406, label %wbody55.i401, label %wcond.i716
+
+wcond.i716: ; preds = %wbody.i717, %andand65.i407, %wcond54.i396
+ %.frame.0.0 = phi i32 [ %t18.i.c829, %wbody.i717 ], [ %.frame.0.9, %wcond54.i396 ], [ %.frame.0.9, %andand65.i407 ] ; <i32> [#uses=7]
+ %t4.i715 = icmp ult i32 %.frame.0.0, %line_arg830 ; <i1> [#uses=1]
+ br i1 %t4.i715, label %andand.i721, label %wcond22.i724
+
+wbody.i717: ; preds = %andand.i721
+ %t18.i.c829 = add i32 %.frame.0.0, 1 ; <i32> [#uses=1]
+ br label %wcond.i716
+
+andand.i721: ; preds = %wcond.i716
+ %t11.i718 = getelementptr i8* %line_arg831, i32 %.frame.0.0 ; <i8*> [#uses=1]
+ %t12.i719 = load i8* %t11.i718 ; <i8> [#uses=1]
+ %t14.i720 = icmp eq i8 %t12.i719, 32 ; <i1> [#uses=1]
+ br i1 %t14.i720, label %wbody.i717, label %wcond22.i724
+
+wcond22.i724: ; preds = %wbody23.i726, %andand.i721, %wcond.i716
+ %.frame.0.1 = phi i32 [ %t50.i725, %wbody23.i726 ], [ %.frame.0.0, %wcond.i716 ], [ %.frame.0.0, %andand.i721 ] ; <i32> [#uses=2]
+ %t49.i722 = phi i32 [ %t50.i725, %wbody23.i726 ], [ %.frame.0.0, %wcond.i716 ], [ %.frame.0.0, %andand.i721 ] ; <i32> [#uses=5]
+ %t32.i723 = icmp ult i32 %t49.i722, %line_arg830 ; <i1> [#uses=1]
+ br i1 %t32.i723, label %andand33.i731, label %wcond54.i734
+
+wbody23.i726: ; preds = %andand33.i731
+ %t50.i725 = add i32 %t49.i722, 1 ; <i32> [#uses=2]
+ br label %wcond22.i724
+
+andand33.i731: ; preds = %wcond22.i724
+ %t42.i728 = getelementptr i8* %line_arg831, i32 %t49.i722 ; <i8*> [#uses=1]
+ %t43.i729 = load i8* %t42.i728 ; <i8> [#uses=1]
+ %t45.i730 = icmp eq i8 %t43.i729, 32 ; <i1> [#uses=1]
+ br i1 %t45.i730, label %wcond54.i734, label %wbody23.i726
+
+wcond54.i734: ; preds = %wbody55.i736, %andand33.i731, %wcond22.i724
+ %.frame.0.2 = phi i32 [ %t82.i735, %wbody55.i736 ], [ %.frame.0.1, %wcond22.i724 ], [ %.frame.0.1, %andand33.i731 ] ; <i32> [#uses=2]
+ %t81.i732 = phi i32 [ %t82.i735, %wbody55.i736 ], [ %t49.i722, %wcond22.i724 ], [ %t49.i722, %andand33.i731 ] ; <i32> [#uses=3]
+ %t64.i733 = icmp ult i32 %t81.i732, %line_arg830 ; <i1> [#uses=1]
+ br i1 %t64.i733, label %andand65.i740, label %wcond.i750
+
+wbody55.i736: ; preds = %andand65.i740
+ %t82.i735 = add i32 %t81.i732, 1 ; <i32> [#uses=2]
+ br label %wcond54.i734
+
+andand65.i740: ; preds = %wcond54.i734
+ %t74.i737 = getelementptr i8* %line_arg831, i32 %t81.i732 ; <i8*> [#uses=1]
+ %t75.i738 = load i8* %t74.i737 ; <i8> [#uses=1]
+ %t77.i739 = icmp eq i8 %t75.i738, 32 ; <i1> [#uses=1]
+ br i1 %t77.i739, label %wbody55.i736, label %wcond.i750
+
+wcond.i750: ; preds = %wbody.i752, %andand65.i740, %wcond54.i734
+ %.frame.0.3 = phi i32 [ %t18.i751.c, %wbody.i752 ], [ %.frame.0.2, %wcond54.i734 ], [ %.frame.0.2, %andand65.i740 ] ; <i32> [#uses=11]
+ %t4.i749 = icmp ult i32 %.frame.0.3, %line_arg830 ; <i1> [#uses=1]
+ br i1 %t4.i749, label %andand.i758, label %wcond22.i761
+
+wbody.i752: ; preds = %andand.i758
+ %t18.i751.c = add i32 %.frame.0.3, 1 ; <i32> [#uses=1]
+ br label %wcond.i750
+
+andand.i758: ; preds = %wcond.i750
+ %t11.i755 = getelementptr i8* %line_arg831, i32 %.frame.0.3 ; <i8*> [#uses=1]
+ %t12.i756 = load i8* %t11.i755 ; <i8> [#uses=1]
+ %t14.i757 = icmp eq i8 %t12.i756, 32 ; <i1> [#uses=1]
+ br i1 %t14.i757, label %wbody.i752, label %wcond22.i761
+
+wcond22.i761: ; preds = %wbody23.i763, %andand.i758, %wcond.i750
+ %.frame.0.4 = phi i32 [ %t50.i762, %wbody23.i763 ], [ %.frame.0.3, %wcond.i750 ], [ %.frame.0.3, %andand.i758 ] ; <i32> [#uses=2]
+ %t49.i759 = phi i32 [ %t50.i762, %wbody23.i763 ], [ %.frame.0.3, %wcond.i750 ], [ %.frame.0.3, %andand.i758 ] ; <i32> [#uses=7]
+ %t32.i760 = icmp ult i32 %t49.i759, %line_arg830 ; <i1> [#uses=1]
+ br i1 %t32.i760, label %andand33.i769, label %wcond54.i773
+
+wbody23.i763: ; preds = %andand33.i769
+ %t50.i762 = add i32 %t49.i759, 1 ; <i32> [#uses=2]
+ br label %wcond22.i761
+
+andand33.i769: ; preds = %wcond22.i761
+ %t42.i766 = getelementptr i8* %line_arg831, i32 %t49.i759 ; <i8*> [#uses=1]
+ %t43.i767 = load i8* %t42.i766 ; <i8> [#uses=1]
+ %t45.i768 = icmp eq i8 %t43.i767, 32 ; <i1> [#uses=1]
+ br i1 %t45.i768, label %wcond54.i773, label %wbody23.i763
+
+wcond54.i773: ; preds = %wbody55.i775, %andand33.i769, %wcond22.i761
+ %.frame.0.5 = phi i32 [ %t82.i774, %wbody55.i775 ], [ %.frame.0.4, %wcond22.i761 ], [ %.frame.0.4, %andand33.i769 ] ; <i32> [#uses=1]
+ %t81.i770 = phi i32 [ %t82.i774, %wbody55.i775 ], [ %t49.i759, %wcond22.i761 ], [ %t49.i759, %andand33.i769 ] ; <i32> [#uses=3]
+ %t64.i771 = icmp ult i32 %t81.i770, %line_arg830 ; <i1> [#uses=1]
+ br i1 %t64.i771, label %andand65.i780, label %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786
+
+wbody55.i775: ; preds = %andand65.i780
+ %t82.i774 = add i32 %t81.i770, 1 ; <i32> [#uses=2]
+ br label %wcond54.i773
+
+andand65.i780: ; preds = %wcond54.i773
+ %t74.i777 = getelementptr i8* %line_arg831, i32 %t81.i770 ; <i8*> [#uses=1]
+ %t75.i778 = load i8* %t74.i777 ; <i8> [#uses=1]
+ %t77.i779 = icmp eq i8 %t75.i778, 32 ; <i1> [#uses=1]
+ br i1 %t77.i779, label %wbody55.i775, label %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786
+
+Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786: ; preds = %andand65.i780, %wcond54.i773
+ %t89.i782 = getelementptr i8* %line_arg831, i32 %.frame.0.3 ; <i8*> [#uses=4]
+ %t90.i783 = sub i32 %t49.i759, %.frame.0.3 ; <i32> [#uses=2]
+ br label %wcond.i792
+
+wcond.i792: ; preds = %wbody.i794, %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786
+ %.frame.0.6 = phi i32 [ %.frame.0.5, %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit786 ], [ %t18.i793.c, %wbody.i794 ] ; <i32> [#uses=9]
+ %t4.i791 = icmp ult i32 %.frame.0.6, %line_arg830 ; <i1> [#uses=1]
+ br i1 %t4.i791, label %andand.i800, label %wcond22.i803
+
+wbody.i794: ; preds = %andand.i800
+ %t18.i793.c = add i32 %.frame.0.6, 1 ; <i32> [#uses=1]
+ br label %wcond.i792
+
+andand.i800: ; preds = %wcond.i792
+ %t11.i797 = getelementptr i8* %line_arg831, i32 %.frame.0.6 ; <i8*> [#uses=1]
+ %t12.i798 = load i8* %t11.i797 ; <i8> [#uses=1]
+ %t14.i799 = icmp eq i8 %t12.i798, 32 ; <i1> [#uses=1]
+ br i1 %t14.i799, label %wbody.i794, label %wcond22.i803
+
+wcond22.i803: ; preds = %wbody23.i805, %andand.i800, %wcond.i792
+ %t49.i801 = phi i32 [ %t50.i804, %wbody23.i805 ], [ %.frame.0.6, %wcond.i792 ], [ %.frame.0.6, %andand.i800 ] ; <i32> [#uses=7]
+ %t32.i802 = icmp ult i32 %t49.i801, %line_arg830 ; <i1> [#uses=1]
+ br i1 %t32.i802, label %andand33.i811, label %wcond54.i815
+
+wbody23.i805: ; preds = %andand33.i811
+ %t50.i804 = add i32 %t49.i801, 1 ; <i32> [#uses=1]
+ br label %wcond22.i803
+
+andand33.i811: ; preds = %wcond22.i803
+ %t42.i808 = getelementptr i8* %line_arg831, i32 %t49.i801 ; <i8*> [#uses=1]
+ %t43.i809 = load i8* %t42.i808 ; <i8> [#uses=1]
+ %t45.i810 = icmp eq i8 %t43.i809, 32 ; <i1> [#uses=1]
+ br i1 %t45.i810, label %wcond54.i815, label %wbody23.i805
+
+wcond54.i815: ; preds = %wbody55.i817, %andand33.i811, %wcond22.i803
+ %t81.i812 = phi i32 [ %t82.i816, %wbody55.i817 ], [ %t49.i801, %wcond22.i803 ], [ %t49.i801, %andand33.i811 ] ; <i32> [#uses=3]
+ %t64.i813 = icmp ult i32 %t81.i812, %line_arg830 ; <i1> [#uses=1]
+ br i1 %t64.i813, label %andand65.i822, label %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828
+
+wbody55.i817: ; preds = %andand65.i822
+ %t82.i816 = add i32 %t81.i812, 1 ; <i32> [#uses=1]
+ br label %wcond54.i815
+
+andand65.i822: ; preds = %wcond54.i815
+ %t74.i819 = getelementptr i8* %line_arg831, i32 %t81.i812 ; <i8*> [#uses=1]
+ %t75.i820 = load i8* %t74.i819 ; <i8> [#uses=1]
+ %t77.i821 = icmp eq i8 %t75.i820, 32 ; <i1> [#uses=1]
+ br i1 %t77.i821, label %wbody55.i817, label %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828
+
+Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828: ; preds = %andand65.i822, %wcond54.i815
+ %t89.i824 = getelementptr i8* %line_arg831, i32 %.frame.0.6 ; <i8*> [#uses=4]
+ %t90.i825 = sub i32 %t49.i801, %.frame.0.6 ; <i32> [#uses=2]
+ %t63 = load i8* %t89.i824 ; <i8> [#uses=2]
+ br label %forcondi622
+
+forcondi622: ; preds = %forbodyi626, %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828
+ %l.0i618 = phi i32 [ 10, %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828 ], [ %t4i620, %forbodyi626 ] ; <i32> [#uses=2]
+ %p.0i619 = phi i8* [ getelementptr ([11 x i8]* @.str170, i32 0, i32 -1), %Dt3net3ftp9FClient13FConnection13pListLineMFAaZS5t3net3ftp9FClient11FFileInfo10p_wordMFZAa.exit828 ], [ %t7i623, %forbodyi626 ] ; <i8*> [#uses=1]
+ %t4i620 = add i32 %l.0i618, -1 ; <i32> [#uses=1]
+ %t5i621 = icmp eq i32 %l.0i618, 0 ; <i1> [#uses=1]
+ br i1 %t5i621, label %if65, label %forbodyi626
+
+forbodyi626: ; preds = %forcondi622
+ %t7i623 = getelementptr i8* %p.0i619, i32 1 ; <i8*> [#uses=3]
+ %t8i624 = load i8* %t7i623 ; <i8> [#uses=1]
+ %t12i625 = icmp eq i8 %t8i624, %t63 ; <i1> [#uses=1]
+ br i1 %t12i625, label %ifi630, label %forcondi622
+
+ifi630: ; preds = %forbodyi626
+ %t15i627 = ptrtoint i8* %t7i623 to i32 ; <i32> [#uses=1]
+ %t17i629 = sub i32 %t15i627, ptrtoint ([11 x i8]* @.str170 to i32) ; <i32> [#uses=1]
+ %phit636 = icmp eq i32 %t17i629, 10 ; <i1> [#uses=1]
+ br i1 %phit636, label %if65, label %e67
+
+if65: ; preds = %ifi630, %forcondi622
+ %t4i532 = icmp eq i32 %t49.i759, %.frame.0.3 ; <i1> [#uses=1]
+ br i1 %t4i532, label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576, label %forcondi539
+
+forcondi539: ; preds = %zi546, %if65
+ %sign.1.i533 = phi i1 [ %sign.0.i543, %zi546 ], [ false, %if65 ] ; <i1> [#uses=2]
+ %l.0i534 = phi i32 [ %t33i545, %zi546 ], [ %t90.i783, %if65 ] ; <i32> [#uses=3]
+ %p.0i535 = phi i8* [ %t30i544, %zi546 ], [ %t89.i782, %if65 ] ; <i8*> [#uses=6]
+ %c.0.ini536 = phi i8* [ %t30i544, %zi546 ], [ %t89.i782, %if65 ] ; <i8*> [#uses=1]
+ %c.0i537 = load i8* %c.0.ini536 ; <i8> [#uses=2]
+ %t8i538 = icmp eq i32 %l.0i534, 0 ; <i1> [#uses=1]
+ br i1 %t8i538, label %endfori550, label %forbodyi540
+
+forbodyi540: ; preds = %forcondi539
+ switch i8 %c.0i537, label %endfori550 [
+ i8 32, label %zi546
+ i8 9, label %zi546
+ i8 45, label %if20i541
+ i8 43, label %if26i542
+ ]
+
+if20i541: ; preds = %forbodyi540
+ br label %zi546
+
+if26i542: ; preds = %forbodyi540
+ br label %zi546
+
+zi546: ; preds = %if26i542, %if20i541, %forbodyi540, %forbodyi540
+ %sign.0.i543 = phi i1 [ false, %if26i542 ], [ true, %if20i541 ], [ %sign.1.i533, %forbodyi540 ], [ %sign.1.i533, %forbodyi540 ] ; <i1> [#uses=1]
+ %t30i544 = getelementptr i8* %p.0i535, i32 1 ; <i8*> [#uses=2]
+ %t33i545 = add i32 %l.0i534, -1 ; <i32> [#uses=1]
+ br label %forcondi539
+
+endfori550: ; preds = %forbodyi540, %forcondi539
+ %t37i547 = icmp eq i8 %c.0i537, 48 ; <i1> [#uses=1]
+ %t39i548 = icmp sgt i32 %l.0i534, 1 ; <i1> [#uses=1]
+ %or.condi549 = and i1 %t37i547, %t39i548 ; <i1> [#uses=1]
+ br i1 %or.condi549, label %if40i554, label %endif41i564
+
+if40i554: ; preds = %endfori550
+ %t43i551 = getelementptr i8* %p.0i535, i32 1 ; <i8*> [#uses=2]
+ %t44i552 = load i8* %t43i551 ; <i8> [#uses=1]
+ %t45i553 = zext i8 %t44i552 to i32 ; <i32> [#uses=1]
+ switch i32 %t45i553, label %endif41i564 [
+ i32 120, label %case46i556
+ i32 88, label %case46i556
+ i32 98, label %case51i558
+ i32 66, label %case51i558
+ i32 111, label %case56i560
+ i32 79, label %case56i560
+ ]
+
+case46i556: ; preds = %if40i554, %if40i554
+ %t48i555 = getelementptr i8* %p.0i535, i32 2 ; <i8*> [#uses=1]
+ br label %endif41i564
+
+case51i558: ; preds = %if40i554, %if40i554
+ %t53i557 = getelementptr i8* %p.0i535, i32 2 ; <i8*> [#uses=1]
+ br label %endif41i564
+
+case56i560: ; preds = %if40i554, %if40i554
+ %t58i559 = getelementptr i8* %p.0i535, i32 2 ; <i8*> [#uses=1]
+ br label %endif41i564
+
+endif41i564: ; preds = %case56i560, %case51i558, %case46i556, %if40i554, %endfori550
+ %r.0i561 = phi i32 [ 0, %if40i554 ], [ 8, %case56i560 ], [ 2, %case51i558 ], [ 16, %case46i556 ], [ 0, %endfori550 ] ; <i32> [#uses=2]
+ %p.2i562 = phi i8* [ %t43i551, %if40i554 ], [ %t58i559, %case56i560 ], [ %t53i557, %case51i558 ], [ %t48i555, %case46i556 ], [ %p.0i535, %endfori550 ] ; <i8*> [#uses=2]
+ %t63i563 = icmp eq i32 %r.0i561, 0 ; <i1> [#uses=1]
+ br i1 %t63i563, label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576, label %if70i568
+
+if70i568: ; preds = %endif41i564
+ br label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576
+
+Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576: ; preds = %if70i568, %endif41i564, %if65
+ %radix.0.i570 = phi i32 [ 0, %if65 ], [ %r.0i561, %if70i568 ], [ 10, %endif41i564 ] ; <i32> [#uses=2]
+ %p.1i571 = phi i8* [ %p.2i562, %if70i568 ], [ %t89.i782, %if65 ], [ %p.2i562, %endif41i564 ] ; <i8*> [#uses=1]
+ %t84i572 = ptrtoint i8* %p.1i571 to i32 ; <i32> [#uses=1]
+ %t85i573 = ptrtoint i8* %t89.i782 to i32 ; <i32> [#uses=1]
+ %t86i574 = sub i32 %t84i572, %t85i573 ; <i32> [#uses=2]
+ %t6.i575 = sub i32 %t90.i783, %t86i574 ; <i32> [#uses=1]
+ %t59i604 = zext i32 %radix.0.i570 to i64 ; <i64> [#uses=1]
+ br label %fcondi581
+
+fcondi581: ; preds = %if55i610, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576
+ %value.0i577 = phi i64 [ 0, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576 ], [ %t65i607, %if55i610 ] ; <i64> [#uses=1]
+ %fkey.0i579 = phi i32 [ 0, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i576 ], [ %t70i609, %if55i610 ] ; <i32> [#uses=3]
+ %t3i580 = icmp ult i32 %fkey.0i579, %t6.i575 ; <i1> [#uses=1]
+ br i1 %t3i580, label %fbodyi587, label %wcond.i422
+
+fbodyi587: ; preds = %fcondi581
+ %t5.s.i582 = add i32 %t86i574, %fkey.0i579 ; <i32> [#uses=1]
+ %t89.i782.s = add i32 %.frame.0.3, %t5.s.i582 ; <i32> [#uses=1]
+ %t5i583 = getelementptr i8* %line_arg831, i32 %t89.i782.s ; <i8*> [#uses=1]
+ %t6i584 = load i8* %t5i583 ; <i8> [#uses=6]
+ %t6.off84i585 = add i8 %t6i584, -48 ; <i8> [#uses=1]
+ %or.cond.i28.i586 = icmp ugt i8 %t6.off84i585, 9 ; <i1> [#uses=1]
+ br i1 %or.cond.i28.i586, label %ei590, label %endifi603
+
+ei590: ; preds = %fbodyi587
+ %t6.off83i588 = add i8 %t6i584, -97 ; <i8> [#uses=1]
+ %or.cond81i589 = icmp ugt i8 %t6.off83i588, 25 ; <i1> [#uses=1]
+ br i1 %or.cond81i589, label %e24i595, label %if22i592
+
+if22i592: ; preds = %ei590
+ %t27i591 = add i8 %t6i584, -39 ; <i8> [#uses=1]
+ br label %endifi603
+
+e24i595: ; preds = %ei590
+ %t6.offi593 = add i8 %t6i584, -65 ; <i8> [#uses=1]
+ %or.cond82i594 = icmp ugt i8 %t6.offi593, 25 ; <i1> [#uses=1]
+ br i1 %or.cond82i594, label %wcond.i422, label %if39i597
+
+if39i597: ; preds = %e24i595
+ %t44.i29.i596 = add i8 %t6i584, -7 ; <i8> [#uses=1]
+ br label %endifi603
+
+endifi603: ; preds = %if39i597, %if22i592, %fbodyi587
+ %c.0.i30.i598 = phi i8 [ %t27i591, %if22i592 ], [ %t44.i29.i596, %if39i597 ], [ %t6i584, %fbodyi587 ] ; <i8> [#uses=1]
+ %t48.i31.i599 = zext i8 %c.0.i30.i598 to i32 ; <i32> [#uses=1]
+ %t49i600 = add i32 %t48.i31.i599, 208 ; <i32> [#uses=1]
+ %t52i601 = and i32 %t49i600, 255 ; <i32> [#uses=2]
+ %t54i602 = icmp ult i32 %t52i601, %radix.0.i570 ; <i1> [#uses=1]
+ br i1 %t54i602, label %if55i610, label %wcond.i422
+
+if55i610: ; preds = %endifi603
+ %t61i605 = mul i64 %value.0i577, %t59i604 ; <i64> [#uses=1]
+ %t64i606 = zext i32 %t52i601 to i64 ; <i64> [#uses=1]
+ %t65i607 = add i64 %t61i605, %t64i606 ; <i64> [#uses=1]
+ %t70i609 = add i32 %fkey.0i579, 1 ; <i32> [#uses=1]
+ br label %fcondi581
+
+e67: ; preds = %ifi630
+ %t4i447 = icmp eq i32 %t49.i801, %.frame.0.6 ; <i1> [#uses=1]
+ br i1 %t4i447, label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491, label %forcondi454
+
+forcondi454: ; preds = %zi461, %e67
+ %c.0i452 = phi i8 [ %c.0i452.pre, %zi461 ], [ %t63, %e67 ] ; <i8> [#uses=2]
+ %sign.1.i448 = phi i1 [ %sign.0.i458, %zi461 ], [ false, %e67 ] ; <i1> [#uses=2]
+ %l.0i449 = phi i32 [ %t33i460, %zi461 ], [ %t90.i825, %e67 ] ; <i32> [#uses=3]
+ %p.0i450 = phi i8* [ %t30i459, %zi461 ], [ %t89.i824, %e67 ] ; <i8*> [#uses=5]
+ %t8i453 = icmp eq i32 %l.0i449, 0 ; <i1> [#uses=1]
+ br i1 %t8i453, label %endfori465, label %forbodyi455
+
+forbodyi455: ; preds = %forcondi454
+ switch i8 %c.0i452, label %endfori465 [
+ i8 32, label %zi461
+ i8 9, label %zi461
+ i8 45, label %if20i456
+ i8 43, label %if26i457
+ ]
+
+if20i456: ; preds = %forbodyi455
+ br label %zi461
+
+if26i457: ; preds = %forbodyi455
+ br label %zi461
+
+zi461: ; preds = %if26i457, %if20i456, %forbodyi455, %forbodyi455
+ %sign.0.i458 = phi i1 [ false, %if26i457 ], [ true, %if20i456 ], [ %sign.1.i448, %forbodyi455 ], [ %sign.1.i448, %forbodyi455 ] ; <i1> [#uses=1]
+ %t30i459 = getelementptr i8* %p.0i450, i32 1 ; <i8*> [#uses=2]
+ %t33i460 = add i32 %l.0i449, -1 ; <i32> [#uses=1]
+ %c.0i452.pre = load i8* %t30i459 ; <i8> [#uses=1]
+ br label %forcondi454
+
+endfori465: ; preds = %forbodyi455, %forcondi454
+ %t37i462 = icmp eq i8 %c.0i452, 48 ; <i1> [#uses=1]
+ %t39i463 = icmp sgt i32 %l.0i449, 1 ; <i1> [#uses=1]
+ %or.condi464 = and i1 %t37i462, %t39i463 ; <i1> [#uses=1]
+ br i1 %or.condi464, label %if40i469, label %endif41i479
+
+if40i469: ; preds = %endfori465
+ %t43i466 = getelementptr i8* %p.0i450, i32 1 ; <i8*> [#uses=2]
+ %t44i467 = load i8* %t43i466 ; <i8> [#uses=1]
+ %t45i468 = zext i8 %t44i467 to i32 ; <i32> [#uses=1]
+ switch i32 %t45i468, label %endif41i479 [
+ i32 120, label %case46i471
+ i32 111, label %case56i475
+ ]
+
+case46i471: ; preds = %if40i469
+ %t48i470 = getelementptr i8* %p.0i450, i32 2 ; <i8*> [#uses=1]
+ br label %endif41i479
+
+case56i475: ; preds = %if40i469
+ %t58i474 = getelementptr i8* %p.0i450, i32 2 ; <i8*> [#uses=1]
+ br label %endif41i479
+
+endif41i479: ; preds = %case56i475, %case46i471, %if40i469, %endfori465
+ %r.0i476 = phi i32 [ 0, %if40i469 ], [ 8, %case56i475 ], [ 16, %case46i471 ], [ 0, %endfori465 ] ; <i32> [#uses=2]
+ %p.2i477 = phi i8* [ %t43i466, %if40i469 ], [ %t58i474, %case56i475 ], [ %t48i470, %case46i471 ], [ %p.0i450, %endfori465 ] ; <i8*> [#uses=2]
+ %t63i478 = icmp eq i32 %r.0i476, 0 ; <i1> [#uses=1]
+ br i1 %t63i478, label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491, label %if70i483
+
+if70i483: ; preds = %endif41i479
+ br label %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491
+
+Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491: ; preds = %if70i483, %endif41i479, %e67
+ %radix.0.i485 = phi i32 [ 0, %e67 ], [ %r.0i476, %if70i483 ], [ 10, %endif41i479 ] ; <i32> [#uses=2]
+ %p.1i486 = phi i8* [ %p.2i477, %if70i483 ], [ %t89.i824, %e67 ], [ %p.2i477, %endif41i479 ] ; <i8*> [#uses=1]
+ %t84i487 = ptrtoint i8* %p.1i486 to i32 ; <i32> [#uses=1]
+ %t85i488 = ptrtoint i8* %t89.i824 to i32 ; <i32> [#uses=1]
+ %t86i489 = sub i32 %t84i487, %t85i488 ; <i32> [#uses=2]
+ %ttt = sub i32 %t90.i825, %t86i489 ; <i32> [#uses=1]
+ %t59i519 = zext i32 %radix.0.i485 to i64 ; <i64> [#uses=1]
+ br label %fcondi496
+
+fcondi496: ; preds = %if55i525, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491
+ %value.0i492 = phi i64 [ 0, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491 ], [ %t65i522, %if55i525 ] ; <i64> [#uses=1]
+ %fkey.0i494 = phi i32 [ 0, %Dt4x7c7I11V4tTaZ4tFAaKbKkZk.exit.i491 ], [ %t70i524, %if55i525 ] ; <i32> [#uses=3]
+ %t3i495 = icmp ult i32 %fkey.0i494, %ttt ; <i1> [#uses=1]
+ br i1 %t3i495, label %fbodyi502, label %wcond.i422
+
+fbodyi502: ; preds = %fcondi496
+ %t5.s.i497 = add i32 %t86i489, %fkey.0i494 ; <i32> [#uses=1]
+ %t89.i824.s = add i32 %.frame.0.6, %t5.s.i497 ; <i32> [#uses=1]
+ %t5i498 = getelementptr i8* %line_arg831, i32 %t89.i824.s ; <i8*> [#uses=1]
+ %t6i499 = load i8* %t5i498 ; <i8> [#uses=6]
+ %t6.off84i500 = add i8 %t6i499, -48 ; <i8> [#uses=1]
+ %or.cond.i28.i501 = icmp ugt i8 %t6.off84i500, 9 ; <i1> [#uses=1]
+ br i1 %or.cond.i28.i501, label %ei505, label %endifi518
+
+ei505: ; preds = %fbodyi502
+ %t6.off83i503 = add i8 %t6i499, -97 ; <i8> [#uses=1]
+ %or.cond81i504 = icmp ugt i8 %t6.off83i503, 25 ; <i1> [#uses=1]
+ br i1 %or.cond81i504, label %e24i510, label %if22i507
+
+if22i507: ; preds = %ei505
+ %t27i506 = add i8 %t6i499, -39 ; <i8> [#uses=1]
+ br label %endifi518
+
+e24i510: ; preds = %ei505
+ %t6.offi508 = add i8 %t6i499, -65 ; <i8> [#uses=1]
+ %or.cond82i509 = icmp ugt i8 %t6.offi508, 25 ; <i1> [#uses=1]
+ br i1 %or.cond82i509, label %wcond.i422, label %if39i512
+
+if39i512: ; preds = %e24i510
+ %t44.i29.i511 = add i8 %t6i499, -7 ; <i8> [#uses=1]
+ br label %endifi518
+
+endifi518: ; preds = %if39i512, %if22i507, %fbodyi502
+ %c.0.i30.i513 = phi i8 [ %t27i506, %if22i507 ], [ %t44.i29.i511, %if39i512 ], [ %t6i499, %fbodyi502 ] ; <i8> [#uses=1]
+ %t48.i31.i514 = zext i8 %c.0.i30.i513 to i32 ; <i32> [#uses=1]
+ %t49i515 = add i32 %t48.i31.i514, 208 ; <i32> [#uses=1]
+ %t52i516 = and i32 %t49i515, 255 ; <i32> [#uses=2]
+ %t54i517 = icmp ult i32 %t52i516, %radix.0.i485 ; <i1> [#uses=1]
+ br i1 %t54i517, label %if55i525, label %wcond.i422
+
+if55i525: ; preds = %endifi518
+ %t61i520 = mul i64 %value.0i492, %t59i519 ; <i64> [#uses=1]
+ %t64i521 = zext i32 %t52i516 to i64 ; <i64> [#uses=1]
+ %t65i522 = add i64 %t61i520, %t64i521 ; <i64> [#uses=1]
+ %t70i524 = add i32 %fkey.0i494, 1 ; <i32> [#uses=1]
+ br label %fcondi496
+
+wcond.i422: ; preds = %e40.i, %endifi518, %e24i510, %fcondi496, %endifi603, %e24i595, %fcondi581
+ %sarg60.pn.i = phi i8* [ %p.0.i, %e40.i ], [ undef, %fcondi496 ], [ undef, %e24i510 ], [ undef, %endifi518 ], [ undef, %endifi603 ], [ undef, %e24i595 ], [ undef, %fcondi581 ] ; <i8*> [#uses=3]
+ %start_arg.pn.i = phi i32 [ %t49.i443, %e40.i ], [ 0, %fcondi496 ], [ 0, %e24i510 ], [ 0, %endifi518 ], [ 0, %endifi603 ], [ 0, %e24i595 ], [ 0, %fcondi581 ] ; <i32> [#uses=3]
+ %extent.0.i = phi i32 [ %t51.i, %e40.i ], [ undef, %fcondi496 ], [ undef, %e24i510 ], [ undef, %endifi518 ], [ undef, %endifi603 ], [ undef, %e24i595 ], [ undef, %fcondi581 ] ; <i32> [#uses=3]
+ %p.0.i = getelementptr i8* %sarg60.pn.i, i32 %start_arg.pn.i ; <i8*> [#uses=2]
+ %p.0.s63.i = add i32 %start_arg.pn.i, -1 ; <i32> [#uses=1]
+ %t2i424 = getelementptr i8* %sarg60.pn.i, i32 %p.0.s63.i ; <i8*> [#uses=1]
+ br label %forcondi430
+
+forcondi430: ; preds = %forbodyi434, %wcond.i422
+ %l.0i426 = phi i32 [ %extent.0.i, %wcond.i422 ], [ %t4i428, %forbodyi434 ] ; <i32> [#uses=2]
+ %p.0i427 = phi i8* [ %t2i424, %wcond.i422 ], [ %t7i431, %forbodyi434 ] ; <i8*> [#uses=1]
+ %t4i428 = add i32 %l.0i426, -1 ; <i32> [#uses=1]
+ %t5i429 = icmp eq i32 %l.0i426, 0 ; <i1> [#uses=1]
+ br i1 %t5i429, label %e.i441, label %forbodyi434
+
+forbodyi434: ; preds = %forcondi430
+ %t7i431 = getelementptr i8* %p.0i427, i32 1 ; <i8*> [#uses=3]
+ %t8i432 = load i8* %t7i431 ; <i8> [#uses=1]
+ %t12i433 = icmp eq i8 %t8i432, 32 ; <i1> [#uses=1]
+ br i1 %t12i433, label %ifi438, label %forcondi430
+
+ifi438: ; preds = %forbodyi434
+ %t15i435 = ptrtoint i8* %t7i431 to i32 ; <i32> [#uses=1]
+ %t16i436 = ptrtoint i8* %p.0.i to i32 ; <i32> [#uses=1]
+ %t17i437 = sub i32 %t15i435, %t16i436 ; <i32> [#uses=1]
+ br label %e.i441
+
+e.i441: ; preds = %ifi438, %forcondi430
+ %t2561.i = phi i32 [ %t17i437, %ifi438 ], [ %extent.0.i, %forcondi430 ] ; <i32> [#uses=2]
+ %p.0.s.i = add i32 %start_arg.pn.i, %t2561.i ; <i32> [#uses=1]
+ %t32.s.i = add i32 %p.0.s.i, -1 ; <i32> [#uses=1]
+ %t2i.i = getelementptr i8* %sarg60.pn.i, i32 %t32.s.i ; <i8*> [#uses=1]
+ br label %forbodyi.i
+
+forbodyi.i: ; preds = %forbodyi.i, %e.i441
+ %p.0i.i = phi i8* [ %t2i.i, %e.i441 ], [ %t7i.i, %forbodyi.i ] ; <i8*> [#uses=1]
+ %s2.0i.i = phi i8* [ getelementptr ([5 x i8]* @.str171, i32 0, i32 0), %e.i441 ], [ %t11i.i, %forbodyi.i ] ; <i8*> [#uses=2]
+ %t7i.i = getelementptr i8* %p.0i.i, i32 1 ; <i8*> [#uses=2]
+ %t8i.i = load i8* %t7i.i ; <i8> [#uses=1]
+ %t11i.i = getelementptr i8* %s2.0i.i, i32 1 ; <i8*> [#uses=1]
+ %t12i.i = load i8* %s2.0i.i ; <i8> [#uses=1]
+ %t14i.i = icmp eq i8 %t8i.i, %t12i.i ; <i1> [#uses=1]
+ br i1 %t14i.i, label %forbodyi.i, label %e40.i
+
+e40.i: ; preds = %forbodyi.i
+ %t49.i443 = add i32 %t2561.i, 1 ; <i32> [#uses=2]
+ %t51.i = sub i32 %extent.0.i, %t49.i443 ; <i32> [#uses=1]
+ br label %wcond.i422
+}
diff --git a/test/CodeGen/PowerPC/trampoline.ll b/test/CodeGen/PowerPC/trampoline.ll
new file mode 100644
index 0000000..bc05bb1
--- /dev/null
+++ b/test/CodeGen/PowerPC/trampoline.ll
@@ -0,0 +1,166 @@
+; RUN: llc < %s -march=ppc32 | grep {__trampoline_setup}
+
+module asm "\09.lazy_reference .objc_class_name_NSImageRep"
+module asm "\09.objc_class_name_NSBitmapImageRep=0"
+module asm "\09.globl .objc_class_name_NSBitmapImageRep"
+ %struct.CGImage = type opaque
+ %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]" = type { %struct.NSBitmapImageRep*, void (%struct.__block_1*, %struct.CGImage*)* }
+ %struct.NSBitmapImageRep = type { %struct.NSImageRep }
+ %struct.NSImageRep = type { }
+ %struct.NSZone = type opaque
+ %struct.__block_1 = type { %struct.__invoke_impl, %struct.NSZone*, %struct.NSBitmapImageRep** }
+ %struct.__builtin_trampoline = type { [40 x i8] }
+ %struct.__invoke_impl = type { i8*, i32, i32, i8* }
+ %struct._objc__method_prototype_list = type opaque
+ %struct._objc_class = type { %struct._objc_class*, %struct._objc_class*, i8*, i32, i32, i32, %struct._objc_ivar_list*, %struct._objc_method_list*, %struct.objc_cache*, %struct._objc_protocol**, i8*, %struct._objc_class_ext* }
+ %struct._objc_class_ext = type opaque
+ %struct._objc_ivar_list = type opaque
+ %struct._objc_method = type { %struct.objc_selector*, i8*, i8* }
+ %struct._objc_method_list = type opaque
+ %struct._objc_module = type { i32, i32, i8*, %struct._objc_symtab* }
+ %struct._objc_protocol = type { %struct._objc_protocol_extension*, i8*, %struct._objc_protocol**, %struct._objc__method_prototype_list*, %struct._objc__method_prototype_list* }
+ %struct._objc_protocol_extension = type opaque
+ %struct._objc_super = type { %struct.objc_object*, %struct._objc_class* }
+ %struct._objc_symtab = type { i32, %struct.objc_selector**, i16, i16, [1 x i8*] }
+ %struct.anon = type { %struct._objc__method_prototype_list*, i32, [1 x %struct._objc_method] }
+ %struct.objc_cache = type opaque
+ %struct.objc_object = type opaque
+ %struct.objc_selector = type opaque
+ %struct.objc_super = type opaque
+@_NSConcreteStackBlock = external global i8* ; <i8**> [#uses=1]
+@"\01L_OBJC_SELECTOR_REFERENCES_1" = internal global %struct.objc_selector* bitcast ([34 x i8]* @"\01L_OBJC_METH_VAR_NAME_1" to %struct.objc_selector*), section "__OBJC,__message_refs,literal_pointers,no_dead_strip" ; <%struct.objc_selector**> [#uses=2]
+@"\01L_OBJC_CLASS_NSBitmapImageRep" = internal global %struct._objc_class { %struct._objc_class* @"\01L_OBJC_METACLASS_NSBitmapImageRep", %struct._objc_class* bitcast ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), i8* getelementptr ([17 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i32 0, i32 1, i32 0, %struct._objc_ivar_list* null, %struct._objc_method_list* bitcast ({ i8*, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_INSTANCE_METHODS_NSBitmapImageRep" to %struct._objc_method_list*), %struct.objc_cache* null, %struct._objc_protocol** null, i8* null, %struct._objc_class_ext* null }, section "__OBJC,__class,regular,no_dead_strip" ; <%struct._objc_class*> [#uses=3]
+@"\01L_OBJC_SELECTOR_REFERENCES_0" = internal global %struct.objc_selector* bitcast ([14 x i8]* @"\01L_OBJC_METH_VAR_NAME_0" to %struct.objc_selector*), section "__OBJC,__message_refs,literal_pointers,no_dead_strip" ; <%struct.objc_selector**> [#uses=2]
+@"\01L_OBJC_SYMBOLS" = internal global { i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] } { i32 0, %struct.objc_selector** null, i16 1, i16 0, [1 x %struct._objc_class*] [ %struct._objc_class* @"\01L_OBJC_CLASS_NSBitmapImageRep" ] }, section "__OBJC,__symbols,regular,no_dead_strip" ; <{ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }*> [#uses=2]
+@"\01L_OBJC_METH_VAR_NAME_0" = internal global [14 x i8] c"copyWithZone:\00", section "__TEXT,__cstring,cstring_literals", align 4 ; <[14 x i8]*> [#uses=2]
+@"\01L_OBJC_METH_VAR_TYPE_0" = internal global [20 x i8] c"@12@0:4^{_NSZone=}8\00", section "__TEXT,__cstring,cstring_literals", align 4 ; <[20 x i8]*> [#uses=1]
+@"\01L_OBJC_INSTANCE_METHODS_NSBitmapImageRep" = internal global { i8*, i32, [1 x %struct._objc_method] } { i8* null, i32 1, [1 x %struct._objc_method] [ %struct._objc_method { %struct.objc_selector* bitcast ([14 x i8]* @"\01L_OBJC_METH_VAR_NAME_0" to %struct.objc_selector*), i8* getelementptr ([20 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0), i8* bitcast (%struct.objc_object* (%struct.NSBitmapImageRep*, %struct.objc_selector*, %struct.NSZone*)* @"-[NSBitmapImageRep copyWithZone:]" to i8*) } ] }, section "__OBJC,__inst_meth,regular,no_dead_strip" ; <{ i8*, i32, [1 x %struct._objc_method] }*> [#uses=2]
+@"\01L_OBJC_CLASS_NAME_0" = internal global [17 x i8] c"NSBitmapImageRep\00", section "__TEXT,__cstring,cstring_literals", align 4 ; <[17 x i8]*> [#uses=1]
+@"\01L_OBJC_CLASS_NAME_1" = internal global [11 x i8] c"NSImageRep\00", section "__TEXT,__cstring,cstring_literals", align 4 ; <[11 x i8]*> [#uses=2]
+@"\01L_OBJC_METACLASS_NSBitmapImageRep" = internal global %struct._objc_class { %struct._objc_class* bitcast ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), %struct._objc_class* bitcast ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), i8* getelementptr ([17 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i32 0, i32 2, i32 48, %struct._objc_ivar_list* null, %struct._objc_method_list* null, %struct.objc_cache* null, %struct._objc_protocol** null, i8* null, %struct._objc_class_ext* null }, section "__OBJC,__meta_class,regular,no_dead_strip" ; <%struct._objc_class*> [#uses=2]
+@"\01L_OBJC_METH_VAR_NAME_1" = internal global [34 x i8] c"_performBlockUsingBackingCGImage:\00", section "__TEXT,__cstring,cstring_literals", align 4 ; <[34 x i8]*> [#uses=2]
+@"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] zeroinitializer, section "__OBJC, __image_info,regular" ; <[2 x i32]*> [#uses=1]
+@"\01L_OBJC_CLASS_NAME_2" = internal global [1 x i8] zeroinitializer, section "__TEXT,__cstring,cstring_literals", align 4 ; <[1 x i8]*> [#uses=1]
+@"\01L_OBJC_MODULES" = internal global %struct._objc_module { i32 7, i32 16, i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0), %struct._objc_symtab* bitcast ({ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }* @"\01L_OBJC_SYMBOLS" to %struct._objc_symtab*) }, section "__OBJC,__module_info,regular,no_dead_strip" ; <%struct._objc_module*> [#uses=1]
[email protected] = appending global [14 x i8*] [ i8* bitcast (%struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_1" to i8*), i8* bitcast (%struct._objc_class* @"\01L_OBJC_CLASS_NSBitmapImageRep" to i8*), i8* bitcast (%struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0" to i8*), i8* bitcast ({ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }* @"\01L_OBJC_SYMBOLS" to i8*), i8* getelementptr ([14 x i8]* @"\01L_OBJC_METH_VAR_NAME_0", i32 0, i32 0), i8* getelementptr ([20 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0), i8* bitcast ({ i8*, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_INSTANCE_METHODS_NSBitmapImageRep" to i8*), i8* getelementptr ([17 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i8* getelementptr ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1", i32 0, i32 0), i8* bitcast (%struct._objc_class* @"\01L_OBJC_METACLASS_NSBitmapImageRep" to i8*), i8* getelementptr ([34 x i8]* @"\01L_OBJC_METH_VAR_NAME_1", i32 0, i32 0), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*), i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0), i8* bitcast (%struct._objc_module* @"\01L_OBJC_MODULES" to i8*) ], section "llvm.metadata" ; <[14 x i8*]*> [#uses=0]
+
+define internal %struct.objc_object* @"-[NSBitmapImageRep copyWithZone:]"(%struct.NSBitmapImageRep* %self, %struct.objc_selector* %_cmd, %struct.NSZone* %zone) nounwind {
+entry:
+ %self_addr = alloca %struct.NSBitmapImageRep* ; <%struct.NSBitmapImageRep**> [#uses=2]
+ %_cmd_addr = alloca %struct.objc_selector* ; <%struct.objc_selector**> [#uses=1]
+ %zone_addr = alloca %struct.NSZone* ; <%struct.NSZone**> [#uses=2]
+ %retval = alloca %struct.objc_object* ; <%struct.objc_object**> [#uses=1]
+ %__block_holder_tmp_1.0 = alloca %struct.__block_1 ; <%struct.__block_1*> [#uses=7]
+ %new = alloca %struct.NSBitmapImageRep* ; <%struct.NSBitmapImageRep**> [#uses=2]
+ %self.1 = alloca %struct.objc_object* ; <%struct.objc_object**> [#uses=2]
+ %0 = alloca i8* ; <i8**> [#uses=2]
+ %TRAMP.9 = alloca %struct.__builtin_trampoline, align 4 ; <%struct.__builtin_trampoline*> [#uses=1]
+ %1 = alloca void (%struct.__block_1*, %struct.CGImage*)* ; <void (%struct.__block_1*, %struct.CGImage*)**> [#uses=2]
+ %2 = alloca %struct.NSBitmapImageRep* ; <%struct.NSBitmapImageRep**> [#uses=2]
+ %FRAME.7 = alloca %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]" ; <%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"*> [#uses=5]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store %struct.NSBitmapImageRep* %self, %struct.NSBitmapImageRep** %self_addr
+ store %struct.objc_selector* %_cmd, %struct.objc_selector** %_cmd_addr
+ store %struct.NSZone* %zone, %struct.NSZone** %zone_addr
+ %3 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 0 ; <%struct.NSBitmapImageRep**> [#uses=1]
+ %4 = load %struct.NSBitmapImageRep** %self_addr, align 4 ; <%struct.NSBitmapImageRep*> [#uses=1]
+ store %struct.NSBitmapImageRep* %4, %struct.NSBitmapImageRep** %3, align 4
+ %TRAMP.91 = bitcast %struct.__builtin_trampoline* %TRAMP.9 to i8* ; <i8*> [#uses=1]
+ %FRAME.72 = bitcast %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7 to i8* ; <i8*> [#uses=1]
+ %tramp = call i8* @llvm.init.trampoline(i8* %TRAMP.91, i8* bitcast (void (%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"*, %struct.__block_1*, %struct.CGImage*)* @__helper_1.1632 to i8*), i8* %FRAME.72) ; <i8*> [#uses=1]
+ store i8* %tramp, i8** %0, align 4
+ %5 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 1 ; <void (%struct.__block_1*, %struct.CGImage*)**> [#uses=1]
+ %6 = load i8** %0, align 4 ; <i8*> [#uses=1]
+ %7 = bitcast i8* %6 to void (%struct.__block_1*, %struct.CGImage*)* ; <void (%struct.__block_1*, %struct.CGImage*)*> [#uses=1]
+ store void (%struct.__block_1*, %struct.CGImage*)* %7, void (%struct.__block_1*, %struct.CGImage*)** %5, align 4
+ store %struct.NSBitmapImageRep* null, %struct.NSBitmapImageRep** %new, align 4
+ %8 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0 ; <%struct.__invoke_impl*> [#uses=1]
+ %9 = getelementptr %struct.__invoke_impl* %8, i32 0, i32 0 ; <i8**> [#uses=1]
+ store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** %9, align 4
+ %10 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0 ; <%struct.__invoke_impl*> [#uses=1]
+ %11 = getelementptr %struct.__invoke_impl* %10, i32 0, i32 1 ; <i32*> [#uses=1]
+ store i32 67108864, i32* %11, align 4
+ %12 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0 ; <%struct.__invoke_impl*> [#uses=1]
+ %13 = getelementptr %struct.__invoke_impl* %12, i32 0, i32 2 ; <i32*> [#uses=1]
+ store i32 24, i32* %13, align 4
+ %14 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 1 ; <void (%struct.__block_1*, %struct.CGImage*)**> [#uses=1]
+ %15 = load void (%struct.__block_1*, %struct.CGImage*)** %14, align 4 ; <void (%struct.__block_1*, %struct.CGImage*)*> [#uses=1]
+ store void (%struct.__block_1*, %struct.CGImage*)* %15, void (%struct.__block_1*, %struct.CGImage*)** %1, align 4
+ %16 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0 ; <%struct.__invoke_impl*> [#uses=1]
+ %17 = getelementptr %struct.__invoke_impl* %16, i32 0, i32 3 ; <i8**> [#uses=1]
+ %18 = load void (%struct.__block_1*, %struct.CGImage*)** %1, align 4 ; <void (%struct.__block_1*, %struct.CGImage*)*> [#uses=1]
+ %19 = bitcast void (%struct.__block_1*, %struct.CGImage*)* %18 to i8* ; <i8*> [#uses=1]
+ store i8* %19, i8** %17, align 4
+ %20 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 1 ; <%struct.NSZone**> [#uses=1]
+ %21 = load %struct.NSZone** %zone_addr, align 4 ; <%struct.NSZone*> [#uses=1]
+ store %struct.NSZone* %21, %struct.NSZone** %20, align 4
+ %22 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 2 ; <%struct.NSBitmapImageRep***> [#uses=1]
+ store %struct.NSBitmapImageRep** %new, %struct.NSBitmapImageRep*** %22, align 4
+ %23 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 0 ; <%struct.NSBitmapImageRep**> [#uses=1]
+ %24 = load %struct.NSBitmapImageRep** %23, align 4 ; <%struct.NSBitmapImageRep*> [#uses=1]
+ store %struct.NSBitmapImageRep* %24, %struct.NSBitmapImageRep** %2, align 4
+ %25 = load %struct.NSBitmapImageRep** %2, align 4 ; <%struct.NSBitmapImageRep*> [#uses=1]
+ %26 = bitcast %struct.NSBitmapImageRep* %25 to %struct.objc_object* ; <%struct.objc_object*> [#uses=1]
+ store %struct.objc_object* %26, %struct.objc_object** %self.1, align 4
+ %27 = load %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_1", align 4 ; <%struct.objc_selector*> [#uses=1]
+ %__block_holder_tmp_1.03 = bitcast %struct.__block_1* %__block_holder_tmp_1.0 to void (%struct.CGImage*)* ; <void (%struct.CGImage*)*> [#uses=1]
+ %28 = load %struct.objc_object** %self.1, align 4 ; <%struct.objc_object*> [#uses=1]
+ %29 = call %struct.objc_object* (%struct.objc_object*, %struct.objc_selector*, ...)* inttoptr (i64 4294901504 to %struct.objc_object* (%struct.objc_object*, %struct.objc_selector*, ...)*)(%struct.objc_object* %28, %struct.objc_selector* %27, void (%struct.CGImage*)* %__block_holder_tmp_1.03) nounwind ; <%struct.objc_object*> [#uses=0]
+ br label %return
+
+return: ; preds = %entry
+ %retval5 = load %struct.objc_object** %retval ; <%struct.objc_object*> [#uses=1]
+ ret %struct.objc_object* %retval5
+}
+
+declare i8* @llvm.init.trampoline(i8*, i8*, i8*) nounwind
+
+define internal void @__helper_1.1632(%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* nest %CHAIN.8, %struct.__block_1* %_self, %struct.CGImage* %cgImage) nounwind {
+entry:
+ %CHAIN.8_addr = alloca %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* ; <%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"**> [#uses=2]
+ %_self_addr = alloca %struct.__block_1* ; <%struct.__block_1**> [#uses=3]
+ %cgImage_addr = alloca %struct.CGImage* ; <%struct.CGImage**> [#uses=1]
+ %zone = alloca %struct.NSZone* ; <%struct.NSZone**> [#uses=2]
+ %objc_super = alloca %struct._objc_super ; <%struct._objc_super*> [#uses=3]
+ %new = alloca %struct.NSBitmapImageRep** ; <%struct.NSBitmapImageRep***> [#uses=2]
+ %objc_super.5 = alloca %struct.objc_super* ; <%struct.objc_super**> [#uses=2]
+ %0 = alloca %struct.NSBitmapImageRep* ; <%struct.NSBitmapImageRep**> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %CHAIN.8, %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"** %CHAIN.8_addr
+ store %struct.__block_1* %_self, %struct.__block_1** %_self_addr
+ store %struct.CGImage* %cgImage, %struct.CGImage** %cgImage_addr
+ %1 = load %struct.__block_1** %_self_addr, align 4 ; <%struct.__block_1*> [#uses=1]
+ %2 = getelementptr %struct.__block_1* %1, i32 0, i32 2 ; <%struct.NSBitmapImageRep***> [#uses=1]
+ %3 = load %struct.NSBitmapImageRep*** %2, align 4 ; <%struct.NSBitmapImageRep**> [#uses=1]
+ store %struct.NSBitmapImageRep** %3, %struct.NSBitmapImageRep*** %new, align 4
+ %4 = load %struct.__block_1** %_self_addr, align 4 ; <%struct.__block_1*> [#uses=1]
+ %5 = getelementptr %struct.__block_1* %4, i32 0, i32 1 ; <%struct.NSZone**> [#uses=1]
+ %6 = load %struct.NSZone** %5, align 4 ; <%struct.NSZone*> [#uses=1]
+ store %struct.NSZone* %6, %struct.NSZone** %zone, align 4
+ %7 = load %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"** %CHAIN.8_addr, align 4 ; <%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"*> [#uses=1]
+ %8 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %7, i32 0, i32 0 ; <%struct.NSBitmapImageRep**> [#uses=1]
+ %9 = load %struct.NSBitmapImageRep** %8, align 4 ; <%struct.NSBitmapImageRep*> [#uses=1]
+ store %struct.NSBitmapImageRep* %9, %struct.NSBitmapImageRep** %0, align 4
+ %10 = load %struct.NSBitmapImageRep** %0, align 4 ; <%struct.NSBitmapImageRep*> [#uses=1]
+ %11 = bitcast %struct.NSBitmapImageRep* %10 to %struct.objc_object* ; <%struct.objc_object*> [#uses=1]
+ %12 = getelementptr %struct._objc_super* %objc_super, i32 0, i32 0 ; <%struct.objc_object**> [#uses=1]
+ store %struct.objc_object* %11, %struct.objc_object** %12, align 4
+ %13 = load %struct._objc_class** getelementptr (%struct._objc_class* @"\01L_OBJC_CLASS_NSBitmapImageRep", i32 0, i32 1), align 4 ; <%struct._objc_class*> [#uses=1]
+ %14 = getelementptr %struct._objc_super* %objc_super, i32 0, i32 1 ; <%struct._objc_class**> [#uses=1]
+ store %struct._objc_class* %13, %struct._objc_class** %14, align 4
+ %objc_super1 = bitcast %struct._objc_super* %objc_super to %struct.objc_super* ; <%struct.objc_super*> [#uses=1]
+ store %struct.objc_super* %objc_super1, %struct.objc_super** %objc_super.5, align 4
+ %15 = load %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0", align 4 ; <%struct.objc_selector*> [#uses=1]
+ %16 = load %struct.objc_super** %objc_super.5, align 4 ; <%struct.objc_super*> [#uses=1]
+ %17 = load %struct.NSZone** %zone, align 4 ; <%struct.NSZone*> [#uses=1]
+ %18 = call %struct.objc_object* (%struct.objc_super*, %struct.objc_selector*, ...)* @objc_msgSendSuper(%struct.objc_super* %16, %struct.objc_selector* %15, %struct.NSZone* %17) nounwind ; <%struct.objc_object*> [#uses=1]
+ %19 = bitcast %struct.objc_object* %18 to %struct.NSBitmapImageRep* ; <%struct.NSBitmapImageRep*> [#uses=1]
+ %20 = load %struct.NSBitmapImageRep*** %new, align 4 ; <%struct.NSBitmapImageRep**> [#uses=1]
+ store %struct.NSBitmapImageRep* %19, %struct.NSBitmapImageRep** %20, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare %struct.objc_object* @objc_msgSendSuper(%struct.objc_super*, %struct.objc_selector*, ...)
diff --git a/test/CodeGen/PowerPC/unsafe-math.ll b/test/CodeGen/PowerPC/unsafe-math.ll
new file mode 100644
index 0000000..ef97912
--- /dev/null
+++ b/test/CodeGen/PowerPC/unsafe-math.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=ppc32 | grep fmul | count 2
+; RUN: llc < %s -march=ppc32 -enable-unsafe-fp-math | \
+; RUN: grep fmul | count 1
+
+define double @foo(double %X) {
+ %tmp1 = fmul double %X, 1.23
+ %tmp2 = fmul double %tmp1, 4.124
+ ret double %tmp2
+}
+
diff --git a/test/CodeGen/PowerPC/vcmp-fold.ll b/test/CodeGen/PowerPC/vcmp-fold.ll
new file mode 100644
index 0000000..7a42c27
--- /dev/null
+++ b/test/CodeGen/PowerPC/vcmp-fold.ll
@@ -0,0 +1,22 @@
+; This should fold the "vcmpbfp." and "vcmpbfp" instructions into a single
+; "vcmpbfp.".
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vcmpbfp | count 1
+
+
+define void @test(<4 x float>* %x, <4 x float>* %y, i32* %P) {
+entry:
+ %tmp = load <4 x float>* %x ; <<4 x float>> [#uses=1]
+ %tmp2 = load <4 x float>* %y ; <<4 x float>> [#uses=1]
+ %tmp.upgrd.1 = call i32 @llvm.ppc.altivec.vcmpbfp.p( i32 1, <4 x float> %tmp, <4 x float> %tmp2 ) ; <i32> [#uses=1]
+ %tmp4 = load <4 x float>* %x ; <<4 x float>> [#uses=1]
+ %tmp6 = load <4 x float>* %y ; <<4 x float>> [#uses=1]
+ %tmp.upgrd.2 = call <4 x i32> @llvm.ppc.altivec.vcmpbfp( <4 x float> %tmp4, <4 x float> %tmp6 ) ; <<4 x i32>> [#uses=1]
+ %tmp7 = bitcast <4 x i32> %tmp.upgrd.2 to <4 x float> ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp7, <4 x float>* %x
+ store i32 %tmp.upgrd.1, i32* %P
+ ret void
+}
+
+declare i32 @llvm.ppc.altivec.vcmpbfp.p(i32, <4 x float>, <4 x float>)
+
+declare <4 x i32> @llvm.ppc.altivec.vcmpbfp(<4 x float>, <4 x float>)
diff --git a/test/CodeGen/PowerPC/vec_auto_constant.ll b/test/CodeGen/PowerPC/vec_auto_constant.ll
new file mode 100644
index 0000000..973f089
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_auto_constant.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s
+; Formerly produced .long, 7320806 (partial)
+; CHECK: .byte 22
+; CHECK: .byte 21
+; CHECK: .byte 20
+; CHECK: .byte 3
+; CHECK: .byte 25
+; CHECK: .byte 24
+; CHECK: .byte 23
+; CHECK: .byte 3
+; CHECK: .byte 28
+; CHECK: .byte 27
+; CHECK: .byte 26
+; CHECK: .byte 3
+; CHECK: .byte 31
+; CHECK: .byte 30
+; CHECK: .byte 29
+; CHECK: .byte 3
+@baz = common global <16 x i8> zeroinitializer ; <<16 x i8>*> [#uses=1]
+
+define void @foo(<16 x i8> %x) nounwind ssp {
+entry:
+ %x_addr = alloca <16 x i8> ; <<16 x i8>*> [#uses=2]
+ %temp = alloca <16 x i8> ; <<16 x i8>*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store <16 x i8> %x, <16 x i8>* %x_addr
+ store <16 x i8> <i8 22, i8 21, i8 20, i8 3, i8 25, i8 24, i8 23, i8 3, i8 28, i8 27, i8 26, i8 3, i8 31, i8 30, i8 29, i8 3>, <16 x i8>* %temp, align 16
+ %0 = load <16 x i8>* %x_addr, align 16 ; <<16 x i8>> [#uses=1]
+ %1 = load <16 x i8>* %temp, align 16 ; <<16 x i8>> [#uses=1]
+ %tmp = add <16 x i8> %0, %1 ; <<16 x i8>> [#uses=1]
+ store <16 x i8> %tmp, <16 x i8>* @baz, align 16
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/vec_br_cmp.ll b/test/CodeGen/PowerPC/vec_br_cmp.ll
new file mode 100644
index 0000000..c34d850
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_br_cmp.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5 -o %t
+; RUN: grep vcmpeqfp. %t
+; RUN: not grep mfcr %t
+
+; A predicate compare used immediately by a branch should not generate an mfcr.
+
+define void @test(<4 x float>* %A, <4 x float>* %B) {
+ %tmp = load <4 x float>* %A ; <<4 x float>> [#uses=1]
+ %tmp3 = load <4 x float>* %B ; <<4 x float>> [#uses=1]
+ %tmp.upgrd.1 = tail call i32 @llvm.ppc.altivec.vcmpeqfp.p( i32 1, <4 x float> %tmp, <4 x float> %tmp3 ) ; <i32> [#uses=1]
+ %tmp.upgrd.2 = icmp eq i32 %tmp.upgrd.1, 0 ; <i1> [#uses=1]
+ br i1 %tmp.upgrd.2, label %cond_true, label %UnifiedReturnBlock
+
+cond_true: ; preds = %0
+ store <4 x float> zeroinitializer, <4 x float>* %B
+ ret void
+
+UnifiedReturnBlock: ; preds = %0
+ ret void
+}
+
+declare i32 @llvm.ppc.altivec.vcmpeqfp.p(i32, <4 x float>, <4 x float>)
diff --git a/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll b/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll
new file mode 100644
index 0000000..015c086
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mattr=+altivec | FileCheck %s
+; Formerly this did byte loads and word stores.
+@a = external global <16 x i8>
+@b = external global <16 x i8>
+@c = external global <16 x i8>
+
+define void @foo() nounwind ssp {
+; CHECK: _foo:
+; CHECK-NOT: stw
+entry:
+ %tmp0 = load <16 x i8>* @a, align 16
+ %tmp180.i = extractelement <16 x i8> %tmp0, i32 0 ; <i8> [#uses=1]
+ %tmp181.i = insertelement <16 x i8> <i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp180.i, i32 2 ; <<16 x i8>> [#uses=1]
+ %tmp182.i = extractelement <16 x i8> %tmp0, i32 1 ; <i8> [#uses=1]
+ %tmp183.i = insertelement <16 x i8> %tmp181.i, i8 %tmp182.i, i32 3 ; <<16 x i8>> [#uses=1]
+ %tmp184.i = insertelement <16 x i8> %tmp183.i, i8 0, i32 4 ; <<16 x i8>> [#uses=1]
+ %tmp185.i = insertelement <16 x i8> %tmp184.i, i8 0, i32 5 ; <<16 x i8>> [#uses=1]
+ %tmp186.i = extractelement <16 x i8> %tmp0, i32 4 ; <i8> [#uses=1]
+ %tmp187.i = insertelement <16 x i8> %tmp185.i, i8 %tmp186.i, i32 6 ; <<16 x i8>> [#uses=1]
+ %tmp188.i = extractelement <16 x i8> %tmp0, i32 5 ; <i8> [#uses=1]
+ %tmp189.i = insertelement <16 x i8> %tmp187.i, i8 %tmp188.i, i32 7 ; <<16 x i8>> [#uses=1]
+ %tmp190.i = insertelement <16 x i8> %tmp189.i, i8 0, i32 8 ; <<16 x i8>> [#uses=1]
+ %tmp191.i = insertelement <16 x i8> %tmp190.i, i8 0, i32 9 ; <<16 x i8>> [#uses=1]
+ %tmp192.i = extractelement <16 x i8> %tmp0, i32 8 ; <i8> [#uses=1]
+ %tmp193.i = insertelement <16 x i8> %tmp191.i, i8 %tmp192.i, i32 10 ; <<16 x i8>> [#uses=1]
+ %tmp194.i = extractelement <16 x i8> %tmp0, i32 9 ; <i8> [#uses=1]
+ %tmp195.i = insertelement <16 x i8> %tmp193.i, i8 %tmp194.i, i32 11 ; <<16 x i8>> [#uses=1]
+ %tmp196.i = insertelement <16 x i8> %tmp195.i, i8 0, i32 12 ; <<16 x i8>> [#uses=1]
+ %tmp197.i = insertelement <16 x i8> %tmp196.i, i8 0, i32 13 ; <<16 x i8>> [#uses=1]
+%tmp201 = shufflevector <16 x i8> %tmp197.i, <16 x i8> %tmp0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 28, i32 29>; ModuleID = 'try.c'
+ store <16 x i8> %tmp201, <16 x i8>* @c, align 16
+ br label %return
+
+return: ; preds = %bb2
+ ret void
+; CHECK: blr
+}
diff --git a/test/CodeGen/PowerPC/vec_call.ll b/test/CodeGen/PowerPC/vec_call.ll
new file mode 100644
index 0000000..4511315
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_call.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5
+
+define <4 x i32> @test_arg(<4 x i32> %A, <4 x i32> %B) {
+ %C = add <4 x i32> %A, %B ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %C
+}
+
+define <4 x i32> @foo() {
+ %X = call <4 x i32> @test_arg( <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %X
+}
diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll
new file mode 100644
index 0000000..32c6f48
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_constants.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep CPI
+
+define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
+ %tmp = load <4 x i32>* %P1 ; <<4 x i32>> [#uses=1]
+ %tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %tmp4, <4 x i32>* %P1
+ %tmp7 = load <4 x i32>* %P2 ; <<4 x i32>> [#uses=1]
+ %tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %tmp9, <4 x i32>* %P2
+ %tmp.upgrd.1 = load <4 x float>* %P3 ; <<4 x float>> [#uses=1]
+ %tmp11 = bitcast <4 x float> %tmp.upgrd.1 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp12 = and <4 x i32> %tmp11, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1]
+ %tmp13 = bitcast <4 x i32> %tmp12 to <4 x float> ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp13, <4 x float>* %P3
+ ret void
+}
+
+define <4 x i32> @test_30() {
+ ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
+}
+
+define <4 x i32> @test_29() {
+ ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
+}
+
+define <8 x i16> @test_n30() {
+ ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
+}
+
+define <16 x i8> @test_n104() {
+ ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
+}
+
+define <4 x i32> @test_vsldoi() {
+ ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
+}
+
+define <4 x i32> @test_rol() {
+ ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
+}
diff --git a/test/CodeGen/PowerPC/vec_fneg.ll b/test/CodeGen/PowerPC/vec_fneg.ll
new file mode 100644
index 0000000..e01e659
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_fneg.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsubfp
+
+define void @t(<4 x float>* %A) {
+ %tmp2 = load <4 x float>* %A
+ %tmp3 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp2
+ store <4 x float> %tmp3, <4 x float>* %A
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/vec_insert.ll b/test/CodeGen/PowerPC/vec_insert.ll
new file mode 100644
index 0000000..185454c
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_insert.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep sth
+
+define <8 x i16> @insert(<8 x i16> %foo, i16 %a) nounwind {
+entry:
+ %vecext = insertelement <8 x i16> %foo, i16 %a, i32 7 ; <i8> [#uses=1]
+ ret <8 x i16> %vecext
+}
+
diff --git a/test/CodeGen/PowerPC/vec_misaligned.ll b/test/CodeGen/PowerPC/vec_misaligned.ll
new file mode 100644
index 0000000..d7ed64a
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_misaligned.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5
+
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
+target triple = "powerpc-apple-darwin8"
+ %struct.S2203 = type { %struct.u16qi }
+ %struct.u16qi = type { <16 x i8> }
+@s = weak global %struct.S2203 zeroinitializer ; <%struct.S2203*> [#uses=1]
+
+define void @foo(i32 %x, ...) {
+entry:
+ %x_addr = alloca i32 ; <i32*> [#uses=1]
+ %ap = alloca i8* ; <i8**> [#uses=3]
+ %ap.0 = alloca i8* ; <i8**> [#uses=3]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %x, i32* %x_addr
+ %ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_start( i8* %ap1 )
+ %tmp = load i8** %ap, align 4 ; <i8*> [#uses=1]
+ store i8* %tmp, i8** %ap.0, align 4
+ %tmp2 = load i8** %ap.0, align 4 ; <i8*> [#uses=1]
+ %tmp3 = getelementptr i8* %tmp2, i64 16 ; <i8*> [#uses=1]
+ store i8* %tmp3, i8** %ap, align 4
+ %tmp4 = load i8** %ap.0, align 4 ; <i8*> [#uses=1]
+ %tmp45 = bitcast i8* %tmp4 to %struct.S2203* ; <%struct.S2203*> [#uses=1]
+ %tmp6 = getelementptr %struct.S2203* @s, i32 0, i32 0 ; <%struct.u16qi*> [#uses=1]
+ %tmp7 = getelementptr %struct.S2203* %tmp45, i32 0, i32 0 ; <%struct.u16qi*> [#uses=1]
+ %tmp8 = getelementptr %struct.u16qi* %tmp6, i32 0, i32 0 ; <<16 x i8>*> [#uses=1]
+ %tmp9 = getelementptr %struct.u16qi* %tmp7, i32 0, i32 0 ; <<16 x i8>*> [#uses=1]
+ %tmp10 = load <16 x i8>* %tmp9, align 4 ; <<16 x i8>> [#uses=1]
+ store <16 x i8> %tmp10, <16 x i8>* %tmp8, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare void @llvm.va_start(i8*) nounwind
diff --git a/test/CodeGen/PowerPC/vec_mul.ll b/test/CodeGen/PowerPC/vec_mul.ll
new file mode 100644
index 0000000..80f4de4
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_mul.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep mullw
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vmsumuhm
+
+define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
+ %tmp = load <4 x i32>* %X ; <<4 x i32>> [#uses=1]
+ %tmp2 = load <4 x i32>* %Y ; <<4 x i32>> [#uses=1]
+ %tmp3 = mul <4 x i32> %tmp, %tmp2 ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %tmp3
+}
+
+define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
+ %tmp = load <8 x i16>* %X ; <<8 x i16>> [#uses=1]
+ %tmp2 = load <8 x i16>* %Y ; <<8 x i16>> [#uses=1]
+ %tmp3 = mul <8 x i16> %tmp, %tmp2 ; <<8 x i16>> [#uses=1]
+ ret <8 x i16> %tmp3
+}
+
+define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
+ %tmp = load <16 x i8>* %X ; <<16 x i8>> [#uses=1]
+ %tmp2 = load <16 x i8>* %Y ; <<16 x i8>> [#uses=1]
+ %tmp3 = mul <16 x i8> %tmp, %tmp2 ; <<16 x i8>> [#uses=1]
+ ret <16 x i8> %tmp3
+}
diff --git a/test/CodeGen/PowerPC/vec_perf_shuffle.ll b/test/CodeGen/PowerPC/vec_perf_shuffle.ll
new file mode 100644
index 0000000..2c3594d
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_perf_shuffle.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep vperm
+
+define <4 x float> @test_uu72(<4 x float>* %P1, <4 x float>* %P2) {
+ %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1]
+ %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1]
+ %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 undef, i32 undef, i32 7, i32 2 > ; <<4 x float>> [#uses=1]
+ ret <4 x float> %V3
+}
+
+define <4 x float> @test_30u5(<4 x float>* %P1, <4 x float>* %P2) {
+ %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1]
+ %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1]
+ %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 0, i32 undef, i32 5 > ; <<4 x float>> [#uses=1]
+ ret <4 x float> %V3
+}
+
+define <4 x float> @test_3u73(<4 x float>* %P1, <4 x float>* %P2) {
+ %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1]
+ %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1]
+ %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 undef, i32 7, i32 3 > ; <<4 x float>> [#uses=1]
+ ret <4 x float> %V3
+}
+
+define <4 x float> @test_3774(<4 x float>* %P1, <4 x float>* %P2) {
+ %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1]
+ %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1]
+ %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 7, i32 7, i32 4 > ; <<4 x float>> [#uses=1]
+ ret <4 x float> %V3
+}
+
+define <4 x float> @test_4450(<4 x float>* %P1, <4 x float>* %P2) {
+ %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1]
+ %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1]
+ %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 4, i32 4, i32 5, i32 0 > ; <<4 x float>> [#uses=1]
+ ret <4 x float> %V3
+}
diff --git a/test/CodeGen/PowerPC/vec_shift.ll b/test/CodeGen/PowerPC/vec_shift.ll
new file mode 100644
index 0000000..646fb5f
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_shift.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5
+; PR3628
+
+define void @update(<4 x i32> %val, <4 x i32>* %dst) nounwind {
+entry:
+ %shl = shl <4 x i32> %val, < i32 4, i32 3, i32 2, i32 1 >
+ %shr = ashr <4 x i32> %shl, < i32 1, i32 2, i32 3, i32 4 >
+ store <4 x i32> %shr, <4 x i32>* %dst
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/vec_shuffle.ll b/test/CodeGen/PowerPC/vec_shuffle.ll
new file mode 100644
index 0000000..8270632
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_shuffle.ll
@@ -0,0 +1,504 @@
+; RUN: opt < %s -instcombine | \
+; RUN: llc -march=ppc32 -mcpu=g5 | not grep vperm
+; RUN: llc < %s -march=ppc32 -mcpu=g5 > %t
+; RUN: grep vsldoi %t | count 2
+; RUN: grep vmrgh %t | count 7
+; RUN: grep vmrgl %t | count 6
+; RUN: grep vpkuhum %t | count 1
+; RUN: grep vpkuwum %t | count 1
+
+define void @VSLDOI_xy(<8 x i16>* %A, <8 x i16>* %B) {
+entry:
+ %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=1]
+ %tmp2 = load <8 x i16>* %B ; <<8 x i16>> [#uses=1]
+ %tmp.upgrd.1 = bitcast <8 x i16> %tmp to <16 x i8> ; <<16 x i8>> [#uses=11]
+ %tmp2.upgrd.2 = bitcast <8 x i16> %tmp2 to <16 x i8> ; <<16 x i8>> [#uses=5]
+ %tmp.upgrd.3 = extractelement <16 x i8> %tmp.upgrd.1, i32 5 ; <i8> [#uses=1]
+ %tmp3 = extractelement <16 x i8> %tmp.upgrd.1, i32 6 ; <i8> [#uses=1]
+ %tmp4 = extractelement <16 x i8> %tmp.upgrd.1, i32 7 ; <i8> [#uses=1]
+ %tmp5 = extractelement <16 x i8> %tmp.upgrd.1, i32 8 ; <i8> [#uses=1]
+ %tmp6 = extractelement <16 x i8> %tmp.upgrd.1, i32 9 ; <i8> [#uses=1]
+ %tmp7 = extractelement <16 x i8> %tmp.upgrd.1, i32 10 ; <i8> [#uses=1]
+ %tmp8 = extractelement <16 x i8> %tmp.upgrd.1, i32 11 ; <i8> [#uses=1]
+ %tmp9 = extractelement <16 x i8> %tmp.upgrd.1, i32 12 ; <i8> [#uses=1]
+ %tmp10 = extractelement <16 x i8> %tmp.upgrd.1, i32 13 ; <i8> [#uses=1]
+ %tmp11 = extractelement <16 x i8> %tmp.upgrd.1, i32 14 ; <i8> [#uses=1]
+ %tmp12 = extractelement <16 x i8> %tmp.upgrd.1, i32 15 ; <i8> [#uses=1]
+ %tmp13 = extractelement <16 x i8> %tmp2.upgrd.2, i32 0 ; <i8> [#uses=1]
+ %tmp14 = extractelement <16 x i8> %tmp2.upgrd.2, i32 1 ; <i8> [#uses=1]
+ %tmp15 = extractelement <16 x i8> %tmp2.upgrd.2, i32 2 ; <i8> [#uses=1]
+ %tmp16 = extractelement <16 x i8> %tmp2.upgrd.2, i32 3 ; <i8> [#uses=1]
+ %tmp17 = extractelement <16 x i8> %tmp2.upgrd.2, i32 4 ; <i8> [#uses=1]
+ %tmp18 = insertelement <16 x i8> undef, i8 %tmp.upgrd.3, i32 0 ; <<16 x i8>> [#uses=1]
+ %tmp19 = insertelement <16 x i8> %tmp18, i8 %tmp3, i32 1 ; <<16 x i8>> [#uses=1]
+ %tmp20 = insertelement <16 x i8> %tmp19, i8 %tmp4, i32 2 ; <<16 x i8>> [#uses=1]
+ %tmp21 = insertelement <16 x i8> %tmp20, i8 %tmp5, i32 3 ; <<16 x i8>> [#uses=1]
+ %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1]
+ %tmp23 = insertelement <16 x i8> %tmp22, i8 %tmp7, i32 5 ; <<16 x i8>> [#uses=1]
+ %tmp24 = insertelement <16 x i8> %tmp23, i8 %tmp8, i32 6 ; <<16 x i8>> [#uses=1]
+ %tmp25 = insertelement <16 x i8> %tmp24, i8 %tmp9, i32 7 ; <<16 x i8>> [#uses=1]
+ %tmp26 = insertelement <16 x i8> %tmp25, i8 %tmp10, i32 8 ; <<16 x i8>> [#uses=1]
+ %tmp27 = insertelement <16 x i8> %tmp26, i8 %tmp11, i32 9 ; <<16 x i8>> [#uses=1]
+ %tmp28 = insertelement <16 x i8> %tmp27, i8 %tmp12, i32 10 ; <<16 x i8>> [#uses=1]
+ %tmp29 = insertelement <16 x i8> %tmp28, i8 %tmp13, i32 11 ; <<16 x i8>> [#uses=1]
+ %tmp30 = insertelement <16 x i8> %tmp29, i8 %tmp14, i32 12 ; <<16 x i8>> [#uses=1]
+ %tmp31 = insertelement <16 x i8> %tmp30, i8 %tmp15, i32 13 ; <<16 x i8>> [#uses=1]
+ %tmp32 = insertelement <16 x i8> %tmp31, i8 %tmp16, i32 14 ; <<16 x i8>> [#uses=1]
+ %tmp33 = insertelement <16 x i8> %tmp32, i8 %tmp17, i32 15 ; <<16 x i8>> [#uses=1]
+ %tmp33.upgrd.4 = bitcast <16 x i8> %tmp33 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ store <8 x i16> %tmp33.upgrd.4, <8 x i16>* %A
+ ret void
+}
+
+define void @VSLDOI_xx(<8 x i16>* %A, <8 x i16>* %B) {
+ %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=1]
+ %tmp2 = load <8 x i16>* %A ; <<8 x i16>> [#uses=1]
+ %tmp.upgrd.5 = bitcast <8 x i16> %tmp to <16 x i8> ; <<16 x i8>> [#uses=11]
+ %tmp2.upgrd.6 = bitcast <8 x i16> %tmp2 to <16 x i8> ; <<16 x i8>> [#uses=5]
+ %tmp.upgrd.7 = extractelement <16 x i8> %tmp.upgrd.5, i32 5 ; <i8> [#uses=1]
+ %tmp3 = extractelement <16 x i8> %tmp.upgrd.5, i32 6 ; <i8> [#uses=1]
+ %tmp4 = extractelement <16 x i8> %tmp.upgrd.5, i32 7 ; <i8> [#uses=1]
+ %tmp5 = extractelement <16 x i8> %tmp.upgrd.5, i32 8 ; <i8> [#uses=1]
+ %tmp6 = extractelement <16 x i8> %tmp.upgrd.5, i32 9 ; <i8> [#uses=1]
+ %tmp7 = extractelement <16 x i8> %tmp.upgrd.5, i32 10 ; <i8> [#uses=1]
+ %tmp8 = extractelement <16 x i8> %tmp.upgrd.5, i32 11 ; <i8> [#uses=1]
+ %tmp9 = extractelement <16 x i8> %tmp.upgrd.5, i32 12 ; <i8> [#uses=1]
+ %tmp10 = extractelement <16 x i8> %tmp.upgrd.5, i32 13 ; <i8> [#uses=1]
+ %tmp11 = extractelement <16 x i8> %tmp.upgrd.5, i32 14 ; <i8> [#uses=1]
+ %tmp12 = extractelement <16 x i8> %tmp.upgrd.5, i32 15 ; <i8> [#uses=1]
+ %tmp13 = extractelement <16 x i8> %tmp2.upgrd.6, i32 0 ; <i8> [#uses=1]
+ %tmp14 = extractelement <16 x i8> %tmp2.upgrd.6, i32 1 ; <i8> [#uses=1]
+ %tmp15 = extractelement <16 x i8> %tmp2.upgrd.6, i32 2 ; <i8> [#uses=1]
+ %tmp16 = extractelement <16 x i8> %tmp2.upgrd.6, i32 3 ; <i8> [#uses=1]
+ %tmp17 = extractelement <16 x i8> %tmp2.upgrd.6, i32 4 ; <i8> [#uses=1]
+ %tmp18 = insertelement <16 x i8> undef, i8 %tmp.upgrd.7, i32 0 ; <<16 x i8>> [#uses=1]
+ %tmp19 = insertelement <16 x i8> %tmp18, i8 %tmp3, i32 1 ; <<16 x i8>> [#uses=1]
+ %tmp20 = insertelement <16 x i8> %tmp19, i8 %tmp4, i32 2 ; <<16 x i8>> [#uses=1]
+ %tmp21 = insertelement <16 x i8> %tmp20, i8 %tmp5, i32 3 ; <<16 x i8>> [#uses=1]
+ %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1]
+ %tmp23 = insertelement <16 x i8> %tmp22, i8 %tmp7, i32 5 ; <<16 x i8>> [#uses=1]
+ %tmp24 = insertelement <16 x i8> %tmp23, i8 %tmp8, i32 6 ; <<16 x i8>> [#uses=1]
+ %tmp25 = insertelement <16 x i8> %tmp24, i8 %tmp9, i32 7 ; <<16 x i8>> [#uses=1]
+ %tmp26 = insertelement <16 x i8> %tmp25, i8 %tmp10, i32 8 ; <<16 x i8>> [#uses=1]
+ %tmp27 = insertelement <16 x i8> %tmp26, i8 %tmp11, i32 9 ; <<16 x i8>> [#uses=1]
+ %tmp28 = insertelement <16 x i8> %tmp27, i8 %tmp12, i32 10 ; <<16 x i8>> [#uses=1]
+ %tmp29 = insertelement <16 x i8> %tmp28, i8 %tmp13, i32 11 ; <<16 x i8>> [#uses=1]
+ %tmp30 = insertelement <16 x i8> %tmp29, i8 %tmp14, i32 12 ; <<16 x i8>> [#uses=1]
+ %tmp31 = insertelement <16 x i8> %tmp30, i8 %tmp15, i32 13 ; <<16 x i8>> [#uses=1]
+ %tmp32 = insertelement <16 x i8> %tmp31, i8 %tmp16, i32 14 ; <<16 x i8>> [#uses=1]
+ %tmp33 = insertelement <16 x i8> %tmp32, i8 %tmp17, i32 15 ; <<16 x i8>> [#uses=1]
+ %tmp33.upgrd.8 = bitcast <16 x i8> %tmp33 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ store <8 x i16> %tmp33.upgrd.8, <8 x i16>* %A
+ ret void
+}
+
+define void @VPERM_promote(<8 x i16>* %A, <8 x i16>* %B) {
+entry:
+ %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=1]
+ %tmp.upgrd.9 = bitcast <8 x i16> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp2 = load <8 x i16>* %B ; <<8 x i16>> [#uses=1]
+ %tmp2.upgrd.10 = bitcast <8 x i16> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp3 = call <4 x i32> @llvm.ppc.altivec.vperm( <4 x i32> %tmp.upgrd.9, <4 x i32> %tmp2.upgrd.10, <16 x i8> < i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14 > ) ; <<4 x i32>> [#uses=1]
+ %tmp3.upgrd.11 = bitcast <4 x i32> %tmp3 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ store <8 x i16> %tmp3.upgrd.11, <8 x i16>* %A
+ ret void
+}
+
+declare <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32>, <4 x i32>, <16 x i8>)
+
+define void @tb_l(<16 x i8>* %A, <16 x i8>* %B) {
+entry:
+ %tmp = load <16 x i8>* %A ; <<16 x i8>> [#uses=8]
+ %tmp2 = load <16 x i8>* %B ; <<16 x i8>> [#uses=8]
+ %tmp.upgrd.12 = extractelement <16 x i8> %tmp, i32 8 ; <i8> [#uses=1]
+ %tmp3 = extractelement <16 x i8> %tmp2, i32 8 ; <i8> [#uses=1]
+ %tmp4 = extractelement <16 x i8> %tmp, i32 9 ; <i8> [#uses=1]
+ %tmp5 = extractelement <16 x i8> %tmp2, i32 9 ; <i8> [#uses=1]
+ %tmp6 = extractelement <16 x i8> %tmp, i32 10 ; <i8> [#uses=1]
+ %tmp7 = extractelement <16 x i8> %tmp2, i32 10 ; <i8> [#uses=1]
+ %tmp8 = extractelement <16 x i8> %tmp, i32 11 ; <i8> [#uses=1]
+ %tmp9 = extractelement <16 x i8> %tmp2, i32 11 ; <i8> [#uses=1]
+ %tmp10 = extractelement <16 x i8> %tmp, i32 12 ; <i8> [#uses=1]
+ %tmp11 = extractelement <16 x i8> %tmp2, i32 12 ; <i8> [#uses=1]
+ %tmp12 = extractelement <16 x i8> %tmp, i32 13 ; <i8> [#uses=1]
+ %tmp13 = extractelement <16 x i8> %tmp2, i32 13 ; <i8> [#uses=1]
+ %tmp14 = extractelement <16 x i8> %tmp, i32 14 ; <i8> [#uses=1]
+ %tmp15 = extractelement <16 x i8> %tmp2, i32 14 ; <i8> [#uses=1]
+ %tmp16 = extractelement <16 x i8> %tmp, i32 15 ; <i8> [#uses=1]
+ %tmp17 = extractelement <16 x i8> %tmp2, i32 15 ; <i8> [#uses=1]
+ %tmp18 = insertelement <16 x i8> undef, i8 %tmp.upgrd.12, i32 0 ; <<16 x i8>> [#uses=1]
+ %tmp19 = insertelement <16 x i8> %tmp18, i8 %tmp3, i32 1 ; <<16 x i8>> [#uses=1]
+ %tmp20 = insertelement <16 x i8> %tmp19, i8 %tmp4, i32 2 ; <<16 x i8>> [#uses=1]
+ %tmp21 = insertelement <16 x i8> %tmp20, i8 %tmp5, i32 3 ; <<16 x i8>> [#uses=1]
+ %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1]
+ %tmp23 = insertelement <16 x i8> %tmp22, i8 %tmp7, i32 5 ; <<16 x i8>> [#uses=1]
+ %tmp24 = insertelement <16 x i8> %tmp23, i8 %tmp8, i32 6 ; <<16 x i8>> [#uses=1]
+ %tmp25 = insertelement <16 x i8> %tmp24, i8 %tmp9, i32 7 ; <<16 x i8>> [#uses=1]
+ %tmp26 = insertelement <16 x i8> %tmp25, i8 %tmp10, i32 8 ; <<16 x i8>> [#uses=1]
+ %tmp27 = insertelement <16 x i8> %tmp26, i8 %tmp11, i32 9 ; <<16 x i8>> [#uses=1]
+ %tmp28 = insertelement <16 x i8> %tmp27, i8 %tmp12, i32 10 ; <<16 x i8>> [#uses=1]
+ %tmp29 = insertelement <16 x i8> %tmp28, i8 %tmp13, i32 11 ; <<16 x i8>> [#uses=1]
+ %tmp30 = insertelement <16 x i8> %tmp29, i8 %tmp14, i32 12 ; <<16 x i8>> [#uses=1]
+ %tmp31 = insertelement <16 x i8> %tmp30, i8 %tmp15, i32 13 ; <<16 x i8>> [#uses=1]
+ %tmp32 = insertelement <16 x i8> %tmp31, i8 %tmp16, i32 14 ; <<16 x i8>> [#uses=1]
+ %tmp33 = insertelement <16 x i8> %tmp32, i8 %tmp17, i32 15 ; <<16 x i8>> [#uses=1]
+ store <16 x i8> %tmp33, <16 x i8>* %A
+ ret void
+}
+
+define void @th_l(<8 x i16>* %A, <8 x i16>* %B) {
+entry:
+ %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=4]
+ %tmp2 = load <8 x i16>* %B ; <<8 x i16>> [#uses=4]
+ %tmp.upgrd.13 = extractelement <8 x i16> %tmp, i32 4 ; <i16> [#uses=1]
+ %tmp3 = extractelement <8 x i16> %tmp2, i32 4 ; <i16> [#uses=1]
+ %tmp4 = extractelement <8 x i16> %tmp, i32 5 ; <i16> [#uses=1]
+ %tmp5 = extractelement <8 x i16> %tmp2, i32 5 ; <i16> [#uses=1]
+ %tmp6 = extractelement <8 x i16> %tmp, i32 6 ; <i16> [#uses=1]
+ %tmp7 = extractelement <8 x i16> %tmp2, i32 6 ; <i16> [#uses=1]
+ %tmp8 = extractelement <8 x i16> %tmp, i32 7 ; <i16> [#uses=1]
+ %tmp9 = extractelement <8 x i16> %tmp2, i32 7 ; <i16> [#uses=1]
+ %tmp10 = insertelement <8 x i16> undef, i16 %tmp.upgrd.13, i32 0 ; <<8 x i16>> [#uses=1]
+ %tmp11 = insertelement <8 x i16> %tmp10, i16 %tmp3, i32 1 ; <<8 x i16>> [#uses=1]
+ %tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp4, i32 2 ; <<8 x i16>> [#uses=1]
+ %tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 3 ; <<8 x i16>> [#uses=1]
+ %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp6, i32 4 ; <<8 x i16>> [#uses=1]
+ %tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 5 ; <<8 x i16>> [#uses=1]
+ %tmp16 = insertelement <8 x i16> %tmp15, i16 %tmp8, i32 6 ; <<8 x i16>> [#uses=1]
+ %tmp17 = insertelement <8 x i16> %tmp16, i16 %tmp9, i32 7 ; <<8 x i16>> [#uses=1]
+ store <8 x i16> %tmp17, <8 x i16>* %A
+ ret void
+}
+
+define void @tw_l(<4 x i32>* %A, <4 x i32>* %B) {
+entry:
+ %tmp = load <4 x i32>* %A ; <<4 x i32>> [#uses=2]
+ %tmp2 = load <4 x i32>* %B ; <<4 x i32>> [#uses=2]
+ %tmp.upgrd.14 = extractelement <4 x i32> %tmp, i32 2 ; <i32> [#uses=1]
+ %tmp3 = extractelement <4 x i32> %tmp2, i32 2 ; <i32> [#uses=1]
+ %tmp4 = extractelement <4 x i32> %tmp, i32 3 ; <i32> [#uses=1]
+ %tmp5 = extractelement <4 x i32> %tmp2, i32 3 ; <i32> [#uses=1]
+ %tmp6 = insertelement <4 x i32> undef, i32 %tmp.upgrd.14, i32 0 ; <<4 x i32>> [#uses=1]
+ %tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 1 ; <<4 x i32>> [#uses=1]
+ %tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 2 ; <<4 x i32>> [#uses=1]
+ %tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp5, i32 3 ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %tmp9, <4 x i32>* %A
+ ret void
+}
+
+define void @tb_h(<16 x i8>* %A, <16 x i8>* %B) {
+entry:
+ %tmp = load <16 x i8>* %A ; <<16 x i8>> [#uses=8]
+ %tmp2 = load <16 x i8>* %B ; <<16 x i8>> [#uses=8]
+ %tmp.upgrd.15 = extractelement <16 x i8> %tmp, i32 0 ; <i8> [#uses=1]
+ %tmp3 = extractelement <16 x i8> %tmp2, i32 0 ; <i8> [#uses=1]
+ %tmp4 = extractelement <16 x i8> %tmp, i32 1 ; <i8> [#uses=1]
+ %tmp5 = extractelement <16 x i8> %tmp2, i32 1 ; <i8> [#uses=1]
+ %tmp6 = extractelement <16 x i8> %tmp, i32 2 ; <i8> [#uses=1]
+ %tmp7 = extractelement <16 x i8> %tmp2, i32 2 ; <i8> [#uses=1]
+ %tmp8 = extractelement <16 x i8> %tmp, i32 3 ; <i8> [#uses=1]
+ %tmp9 = extractelement <16 x i8> %tmp2, i32 3 ; <i8> [#uses=1]
+ %tmp10 = extractelement <16 x i8> %tmp, i32 4 ; <i8> [#uses=1]
+ %tmp11 = extractelement <16 x i8> %tmp2, i32 4 ; <i8> [#uses=1]
+ %tmp12 = extractelement <16 x i8> %tmp, i32 5 ; <i8> [#uses=1]
+ %tmp13 = extractelement <16 x i8> %tmp2, i32 5 ; <i8> [#uses=1]
+ %tmp14 = extractelement <16 x i8> %tmp, i32 6 ; <i8> [#uses=1]
+ %tmp15 = extractelement <16 x i8> %tmp2, i32 6 ; <i8> [#uses=1]
+ %tmp16 = extractelement <16 x i8> %tmp, i32 7 ; <i8> [#uses=1]
+ %tmp17 = extractelement <16 x i8> %tmp2, i32 7 ; <i8> [#uses=1]
+ %tmp18 = insertelement <16 x i8> undef, i8 %tmp.upgrd.15, i32 0 ; <<16 x i8>> [#uses=1]
+ %tmp19 = insertelement <16 x i8> %tmp18, i8 %tmp3, i32 1 ; <<16 x i8>> [#uses=1]
+ %tmp20 = insertelement <16 x i8> %tmp19, i8 %tmp4, i32 2 ; <<16 x i8>> [#uses=1]
+ %tmp21 = insertelement <16 x i8> %tmp20, i8 %tmp5, i32 3 ; <<16 x i8>> [#uses=1]
+ %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1]
+ %tmp23 = insertelement <16 x i8> %tmp22, i8 %tmp7, i32 5 ; <<16 x i8>> [#uses=1]
+ %tmp24 = insertelement <16 x i8> %tmp23, i8 %tmp8, i32 6 ; <<16 x i8>> [#uses=1]
+ %tmp25 = insertelement <16 x i8> %tmp24, i8 %tmp9, i32 7 ; <<16 x i8>> [#uses=1]
+ %tmp26 = insertelement <16 x i8> %tmp25, i8 %tmp10, i32 8 ; <<16 x i8>> [#uses=1]
+ %tmp27 = insertelement <16 x i8> %tmp26, i8 %tmp11, i32 9 ; <<16 x i8>> [#uses=1]
+ %tmp28 = insertelement <16 x i8> %tmp27, i8 %tmp12, i32 10 ; <<16 x i8>> [#uses=1]
+ %tmp29 = insertelement <16 x i8> %tmp28, i8 %tmp13, i32 11 ; <<16 x i8>> [#uses=1]
+ %tmp30 = insertelement <16 x i8> %tmp29, i8 %tmp14, i32 12 ; <<16 x i8>> [#uses=1]
+ %tmp31 = insertelement <16 x i8> %tmp30, i8 %tmp15, i32 13 ; <<16 x i8>> [#uses=1]
+ %tmp32 = insertelement <16 x i8> %tmp31, i8 %tmp16, i32 14 ; <<16 x i8>> [#uses=1]
+ %tmp33 = insertelement <16 x i8> %tmp32, i8 %tmp17, i32 15 ; <<16 x i8>> [#uses=1]
+ store <16 x i8> %tmp33, <16 x i8>* %A
+ ret void
+}
+
+define void @th_h(<8 x i16>* %A, <8 x i16>* %B) {
+entry:
+ %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=4]
+ %tmp2 = load <8 x i16>* %B ; <<8 x i16>> [#uses=4]
+ %tmp.upgrd.16 = extractelement <8 x i16> %tmp, i32 0 ; <i16> [#uses=1]
+ %tmp3 = extractelement <8 x i16> %tmp2, i32 0 ; <i16> [#uses=1]
+ %tmp4 = extractelement <8 x i16> %tmp, i32 1 ; <i16> [#uses=1]
+ %tmp5 = extractelement <8 x i16> %tmp2, i32 1 ; <i16> [#uses=1]
+ %tmp6 = extractelement <8 x i16> %tmp, i32 2 ; <i16> [#uses=1]
+ %tmp7 = extractelement <8 x i16> %tmp2, i32 2 ; <i16> [#uses=1]
+ %tmp8 = extractelement <8 x i16> %tmp, i32 3 ; <i16> [#uses=1]
+ %tmp9 = extractelement <8 x i16> %tmp2, i32 3 ; <i16> [#uses=1]
+ %tmp10 = insertelement <8 x i16> undef, i16 %tmp.upgrd.16, i32 0 ; <<8 x i16>> [#uses=1]
+ %tmp11 = insertelement <8 x i16> %tmp10, i16 %tmp3, i32 1 ; <<8 x i16>> [#uses=1]
+ %tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp4, i32 2 ; <<8 x i16>> [#uses=1]
+ %tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 3 ; <<8 x i16>> [#uses=1]
+ %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp6, i32 4 ; <<8 x i16>> [#uses=1]
+ %tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 5 ; <<8 x i16>> [#uses=1]
+ %tmp16 = insertelement <8 x i16> %tmp15, i16 %tmp8, i32 6 ; <<8 x i16>> [#uses=1]
+ %tmp17 = insertelement <8 x i16> %tmp16, i16 %tmp9, i32 7 ; <<8 x i16>> [#uses=1]
+ store <8 x i16> %tmp17, <8 x i16>* %A
+ ret void
+}
+
+define void @tw_h(<4 x i32>* %A, <4 x i32>* %B) {
+entry:
+ %tmp = load <4 x i32>* %A ; <<4 x i32>> [#uses=2]
+ %tmp2 = load <4 x i32>* %B ; <<4 x i32>> [#uses=2]
+ %tmp.upgrd.17 = extractelement <4 x i32> %tmp2, i32 0 ; <i32> [#uses=1]
+ %tmp3 = extractelement <4 x i32> %tmp, i32 0 ; <i32> [#uses=1]
+ %tmp4 = extractelement <4 x i32> %tmp2, i32 1 ; <i32> [#uses=1]
+ %tmp5 = extractelement <4 x i32> %tmp, i32 1 ; <i32> [#uses=1]
+ %tmp6 = insertelement <4 x i32> undef, i32 %tmp.upgrd.17, i32 0 ; <<4 x i32>> [#uses=1]
+ %tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 1 ; <<4 x i32>> [#uses=1]
+ %tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 2 ; <<4 x i32>> [#uses=1]
+ %tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp5, i32 3 ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %tmp9, <4 x i32>* %A
+ ret void
+}
+
+define void @tw_h_flop(<4 x i32>* %A, <4 x i32>* %B) {
+ %tmp = load <4 x i32>* %A ; <<4 x i32>> [#uses=2]
+ %tmp2 = load <4 x i32>* %B ; <<4 x i32>> [#uses=2]
+ %tmp.upgrd.18 = extractelement <4 x i32> %tmp, i32 0 ; <i32> [#uses=1]
+ %tmp3 = extractelement <4 x i32> %tmp2, i32 0 ; <i32> [#uses=1]
+ %tmp4 = extractelement <4 x i32> %tmp, i32 1 ; <i32> [#uses=1]
+ %tmp5 = extractelement <4 x i32> %tmp2, i32 1 ; <i32> [#uses=1]
+ %tmp6 = insertelement <4 x i32> undef, i32 %tmp.upgrd.18, i32 0 ; <<4 x i32>> [#uses=1]
+ %tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 1 ; <<4 x i32>> [#uses=1]
+ %tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 2 ; <<4 x i32>> [#uses=1]
+ %tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp5, i32 3 ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %tmp9, <4 x i32>* %A
+ ret void
+}
+
+define void @VMRG_UNARY_tb_l(<16 x i8>* %A, <16 x i8>* %B) {
+entry:
+ %tmp = load <16 x i8>* %A ; <<16 x i8>> [#uses=16]
+ %tmp.upgrd.19 = extractelement <16 x i8> %tmp, i32 8 ; <i8> [#uses=1]
+ %tmp3 = extractelement <16 x i8> %tmp, i32 8 ; <i8> [#uses=1]
+ %tmp4 = extractelement <16 x i8> %tmp, i32 9 ; <i8> [#uses=1]
+ %tmp5 = extractelement <16 x i8> %tmp, i32 9 ; <i8> [#uses=1]
+ %tmp6 = extractelement <16 x i8> %tmp, i32 10 ; <i8> [#uses=1]
+ %tmp7 = extractelement <16 x i8> %tmp, i32 10 ; <i8> [#uses=1]
+ %tmp8 = extractelement <16 x i8> %tmp, i32 11 ; <i8> [#uses=1]
+ %tmp9 = extractelement <16 x i8> %tmp, i32 11 ; <i8> [#uses=1]
+ %tmp10 = extractelement <16 x i8> %tmp, i32 12 ; <i8> [#uses=1]
+ %tmp11 = extractelement <16 x i8> %tmp, i32 12 ; <i8> [#uses=1]
+ %tmp12 = extractelement <16 x i8> %tmp, i32 13 ; <i8> [#uses=1]
+ %tmp13 = extractelement <16 x i8> %tmp, i32 13 ; <i8> [#uses=1]
+ %tmp14 = extractelement <16 x i8> %tmp, i32 14 ; <i8> [#uses=1]
+ %tmp15 = extractelement <16 x i8> %tmp, i32 14 ; <i8> [#uses=1]
+ %tmp16 = extractelement <16 x i8> %tmp, i32 15 ; <i8> [#uses=1]
+ %tmp17 = extractelement <16 x i8> %tmp, i32 15 ; <i8> [#uses=1]
+ %tmp18 = insertelement <16 x i8> undef, i8 %tmp.upgrd.19, i32 0 ; <<16 x i8>> [#uses=1]
+ %tmp19 = insertelement <16 x i8> %tmp18, i8 %tmp3, i32 1 ; <<16 x i8>> [#uses=1]
+ %tmp20 = insertelement <16 x i8> %tmp19, i8 %tmp4, i32 2 ; <<16 x i8>> [#uses=1]
+ %tmp21 = insertelement <16 x i8> %tmp20, i8 %tmp5, i32 3 ; <<16 x i8>> [#uses=1]
+ %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1]
+ %tmp23 = insertelement <16 x i8> %tmp22, i8 %tmp7, i32 5 ; <<16 x i8>> [#uses=1]
+ %tmp24 = insertelement <16 x i8> %tmp23, i8 %tmp8, i32 6 ; <<16 x i8>> [#uses=1]
+ %tmp25 = insertelement <16 x i8> %tmp24, i8 %tmp9, i32 7 ; <<16 x i8>> [#uses=1]
+ %tmp26 = insertelement <16 x i8> %tmp25, i8 %tmp10, i32 8 ; <<16 x i8>> [#uses=1]
+ %tmp27 = insertelement <16 x i8> %tmp26, i8 %tmp11, i32 9 ; <<16 x i8>> [#uses=1]
+ %tmp28 = insertelement <16 x i8> %tmp27, i8 %tmp12, i32 10 ; <<16 x i8>> [#uses=1]
+ %tmp29 = insertelement <16 x i8> %tmp28, i8 %tmp13, i32 11 ; <<16 x i8>> [#uses=1]
+ %tmp30 = insertelement <16 x i8> %tmp29, i8 %tmp14, i32 12 ; <<16 x i8>> [#uses=1]
+ %tmp31 = insertelement <16 x i8> %tmp30, i8 %tmp15, i32 13 ; <<16 x i8>> [#uses=1]
+ %tmp32 = insertelement <16 x i8> %tmp31, i8 %tmp16, i32 14 ; <<16 x i8>> [#uses=1]
+ %tmp33 = insertelement <16 x i8> %tmp32, i8 %tmp17, i32 15 ; <<16 x i8>> [#uses=1]
+ store <16 x i8> %tmp33, <16 x i8>* %A
+ ret void
+}
+
+define void @VMRG_UNARY_th_l(<8 x i16>* %A, <8 x i16>* %B) {
+entry:
+ %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=8]
+ %tmp.upgrd.20 = extractelement <8 x i16> %tmp, i32 4 ; <i16> [#uses=1]
+ %tmp3 = extractelement <8 x i16> %tmp, i32 4 ; <i16> [#uses=1]
+ %tmp4 = extractelement <8 x i16> %tmp, i32 5 ; <i16> [#uses=1]
+ %tmp5 = extractelement <8 x i16> %tmp, i32 5 ; <i16> [#uses=1]
+ %tmp6 = extractelement <8 x i16> %tmp, i32 6 ; <i16> [#uses=1]
+ %tmp7 = extractelement <8 x i16> %tmp, i32 6 ; <i16> [#uses=1]
+ %tmp8 = extractelement <8 x i16> %tmp, i32 7 ; <i16> [#uses=1]
+ %tmp9 = extractelement <8 x i16> %tmp, i32 7 ; <i16> [#uses=1]
+ %tmp10 = insertelement <8 x i16> undef, i16 %tmp.upgrd.20, i32 0 ; <<8 x i16>> [#uses=1]
+ %tmp11 = insertelement <8 x i16> %tmp10, i16 %tmp3, i32 1 ; <<8 x i16>> [#uses=1]
+ %tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp4, i32 2 ; <<8 x i16>> [#uses=1]
+ %tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 3 ; <<8 x i16>> [#uses=1]
+ %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp6, i32 4 ; <<8 x i16>> [#uses=1]
+ %tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 5 ; <<8 x i16>> [#uses=1]
+ %tmp16 = insertelement <8 x i16> %tmp15, i16 %tmp8, i32 6 ; <<8 x i16>> [#uses=1]
+ %tmp17 = insertelement <8 x i16> %tmp16, i16 %tmp9, i32 7 ; <<8 x i16>> [#uses=1]
+ store <8 x i16> %tmp17, <8 x i16>* %A
+ ret void
+}
+
+define void @VMRG_UNARY_tw_l(<4 x i32>* %A, <4 x i32>* %B) {
+entry:
+ %tmp = load <4 x i32>* %A ; <<4 x i32>> [#uses=4]
+ %tmp.upgrd.21 = extractelement <4 x i32> %tmp, i32 2 ; <i32> [#uses=1]
+ %tmp3 = extractelement <4 x i32> %tmp, i32 2 ; <i32> [#uses=1]
+ %tmp4 = extractelement <4 x i32> %tmp, i32 3 ; <i32> [#uses=1]
+ %tmp5 = extractelement <4 x i32> %tmp, i32 3 ; <i32> [#uses=1]
+ %tmp6 = insertelement <4 x i32> undef, i32 %tmp.upgrd.21, i32 0 ; <<4 x i32>> [#uses=1]
+ %tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 1 ; <<4 x i32>> [#uses=1]
+ %tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 2 ; <<4 x i32>> [#uses=1]
+ %tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp5, i32 3 ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %tmp9, <4 x i32>* %A
+ ret void
+}
+
+define void @VMRG_UNARY_tb_h(<16 x i8>* %A, <16 x i8>* %B) {
+entry:
+ %tmp = load <16 x i8>* %A ; <<16 x i8>> [#uses=16]
+ %tmp.upgrd.22 = extractelement <16 x i8> %tmp, i32 0 ; <i8> [#uses=1]
+ %tmp3 = extractelement <16 x i8> %tmp, i32 0 ; <i8> [#uses=1]
+ %tmp4 = extractelement <16 x i8> %tmp, i32 1 ; <i8> [#uses=1]
+ %tmp5 = extractelement <16 x i8> %tmp, i32 1 ; <i8> [#uses=1]
+ %tmp6 = extractelement <16 x i8> %tmp, i32 2 ; <i8> [#uses=1]
+ %tmp7 = extractelement <16 x i8> %tmp, i32 2 ; <i8> [#uses=1]
+ %tmp8 = extractelement <16 x i8> %tmp, i32 3 ; <i8> [#uses=1]
+ %tmp9 = extractelement <16 x i8> %tmp, i32 3 ; <i8> [#uses=1]
+ %tmp10 = extractelement <16 x i8> %tmp, i32 4 ; <i8> [#uses=1]
+ %tmp11 = extractelement <16 x i8> %tmp, i32 4 ; <i8> [#uses=1]
+ %tmp12 = extractelement <16 x i8> %tmp, i32 5 ; <i8> [#uses=1]
+ %tmp13 = extractelement <16 x i8> %tmp, i32 5 ; <i8> [#uses=1]
+ %tmp14 = extractelement <16 x i8> %tmp, i32 6 ; <i8> [#uses=1]
+ %tmp15 = extractelement <16 x i8> %tmp, i32 6 ; <i8> [#uses=1]
+ %tmp16 = extractelement <16 x i8> %tmp, i32 7 ; <i8> [#uses=1]
+ %tmp17 = extractelement <16 x i8> %tmp, i32 7 ; <i8> [#uses=1]
+ %tmp18 = insertelement <16 x i8> undef, i8 %tmp.upgrd.22, i32 0 ; <<16 x i8>> [#uses=1]
+ %tmp19 = insertelement <16 x i8> %tmp18, i8 %tmp3, i32 1 ; <<16 x i8>> [#uses=1]
+ %tmp20 = insertelement <16 x i8> %tmp19, i8 %tmp4, i32 2 ; <<16 x i8>> [#uses=1]
+ %tmp21 = insertelement <16 x i8> %tmp20, i8 %tmp5, i32 3 ; <<16 x i8>> [#uses=1]
+ %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1]
+ %tmp23 = insertelement <16 x i8> %tmp22, i8 %tmp7, i32 5 ; <<16 x i8>> [#uses=1]
+ %tmp24 = insertelement <16 x i8> %tmp23, i8 %tmp8, i32 6 ; <<16 x i8>> [#uses=1]
+ %tmp25 = insertelement <16 x i8> %tmp24, i8 %tmp9, i32 7 ; <<16 x i8>> [#uses=1]
+ %tmp26 = insertelement <16 x i8> %tmp25, i8 %tmp10, i32 8 ; <<16 x i8>> [#uses=1]
+ %tmp27 = insertelement <16 x i8> %tmp26, i8 %tmp11, i32 9 ; <<16 x i8>> [#uses=1]
+ %tmp28 = insertelement <16 x i8> %tmp27, i8 %tmp12, i32 10 ; <<16 x i8>> [#uses=1]
+ %tmp29 = insertelement <16 x i8> %tmp28, i8 %tmp13, i32 11 ; <<16 x i8>> [#uses=1]
+ %tmp30 = insertelement <16 x i8> %tmp29, i8 %tmp14, i32 12 ; <<16 x i8>> [#uses=1]
+ %tmp31 = insertelement <16 x i8> %tmp30, i8 %tmp15, i32 13 ; <<16 x i8>> [#uses=1]
+ %tmp32 = insertelement <16 x i8> %tmp31, i8 %tmp16, i32 14 ; <<16 x i8>> [#uses=1]
+ %tmp33 = insertelement <16 x i8> %tmp32, i8 %tmp17, i32 15 ; <<16 x i8>> [#uses=1]
+ store <16 x i8> %tmp33, <16 x i8>* %A
+ ret void
+}
+
+define void @VMRG_UNARY_th_h(<8 x i16>* %A, <8 x i16>* %B) {
+entry:
+ %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=8]
+ %tmp.upgrd.23 = extractelement <8 x i16> %tmp, i32 0 ; <i16> [#uses=1]
+ %tmp3 = extractelement <8 x i16> %tmp, i32 0 ; <i16> [#uses=1]
+ %tmp4 = extractelement <8 x i16> %tmp, i32 1 ; <i16> [#uses=1]
+ %tmp5 = extractelement <8 x i16> %tmp, i32 1 ; <i16> [#uses=1]
+ %tmp6 = extractelement <8 x i16> %tmp, i32 2 ; <i16> [#uses=1]
+ %tmp7 = extractelement <8 x i16> %tmp, i32 2 ; <i16> [#uses=1]
+ %tmp8 = extractelement <8 x i16> %tmp, i32 3 ; <i16> [#uses=1]
+ %tmp9 = extractelement <8 x i16> %tmp, i32 3 ; <i16> [#uses=1]
+ %tmp10 = insertelement <8 x i16> undef, i16 %tmp.upgrd.23, i32 0 ; <<8 x i16>> [#uses=1]
+ %tmp11 = insertelement <8 x i16> %tmp10, i16 %tmp3, i32 1 ; <<8 x i16>> [#uses=1]
+ %tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp4, i32 2 ; <<8 x i16>> [#uses=1]
+ %tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 3 ; <<8 x i16>> [#uses=1]
+ %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp6, i32 4 ; <<8 x i16>> [#uses=1]
+ %tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 5 ; <<8 x i16>> [#uses=1]
+ %tmp16 = insertelement <8 x i16> %tmp15, i16 %tmp8, i32 6 ; <<8 x i16>> [#uses=1]
+ %tmp17 = insertelement <8 x i16> %tmp16, i16 %tmp9, i32 7 ; <<8 x i16>> [#uses=1]
+ store <8 x i16> %tmp17, <8 x i16>* %A
+ ret void
+}
+
+define void @VMRG_UNARY_tw_h(<4 x i32>* %A, <4 x i32>* %B) {
+entry:
+ %tmp = load <4 x i32>* %A ; <<4 x i32>> [#uses=4]
+ %tmp.upgrd.24 = extractelement <4 x i32> %tmp, i32 0 ; <i32> [#uses=1]
+ %tmp3 = extractelement <4 x i32> %tmp, i32 0 ; <i32> [#uses=1]
+ %tmp4 = extractelement <4 x i32> %tmp, i32 1 ; <i32> [#uses=1]
+ %tmp5 = extractelement <4 x i32> %tmp, i32 1 ; <i32> [#uses=1]
+ %tmp6 = insertelement <4 x i32> undef, i32 %tmp.upgrd.24, i32 0 ; <<4 x i32>> [#uses=1]
+ %tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 1 ; <<4 x i32>> [#uses=1]
+ %tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 2 ; <<4 x i32>> [#uses=1]
+ %tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp5, i32 3 ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %tmp9, <4 x i32>* %A
+ ret void
+}
+
+define void @VPCKUHUM_unary(<8 x i16>* %A, <8 x i16>* %B) {
+entry:
+ %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=2]
+ %tmp.upgrd.25 = bitcast <8 x i16> %tmp to <16 x i8> ; <<16 x i8>> [#uses=8]
+ %tmp3 = bitcast <8 x i16> %tmp to <16 x i8> ; <<16 x i8>> [#uses=8]
+ %tmp.upgrd.26 = extractelement <16 x i8> %tmp.upgrd.25, i32 1 ; <i8> [#uses=1]
+ %tmp4 = extractelement <16 x i8> %tmp.upgrd.25, i32 3 ; <i8> [#uses=1]
+ %tmp5 = extractelement <16 x i8> %tmp.upgrd.25, i32 5 ; <i8> [#uses=1]
+ %tmp6 = extractelement <16 x i8> %tmp.upgrd.25, i32 7 ; <i8> [#uses=1]
+ %tmp7 = extractelement <16 x i8> %tmp.upgrd.25, i32 9 ; <i8> [#uses=1]
+ %tmp8 = extractelement <16 x i8> %tmp.upgrd.25, i32 11 ; <i8> [#uses=1]
+ %tmp9 = extractelement <16 x i8> %tmp.upgrd.25, i32 13 ; <i8> [#uses=1]
+ %tmp10 = extractelement <16 x i8> %tmp.upgrd.25, i32 15 ; <i8> [#uses=1]
+ %tmp11 = extractelement <16 x i8> %tmp3, i32 1 ; <i8> [#uses=1]
+ %tmp12 = extractelement <16 x i8> %tmp3, i32 3 ; <i8> [#uses=1]
+ %tmp13 = extractelement <16 x i8> %tmp3, i32 5 ; <i8> [#uses=1]
+ %tmp14 = extractelement <16 x i8> %tmp3, i32 7 ; <i8> [#uses=1]
+ %tmp15 = extractelement <16 x i8> %tmp3, i32 9 ; <i8> [#uses=1]
+ %tmp16 = extractelement <16 x i8> %tmp3, i32 11 ; <i8> [#uses=1]
+ %tmp17 = extractelement <16 x i8> %tmp3, i32 13 ; <i8> [#uses=1]
+ %tmp18 = extractelement <16 x i8> %tmp3, i32 15 ; <i8> [#uses=1]
+ %tmp19 = insertelement <16 x i8> undef, i8 %tmp.upgrd.26, i32 0 ; <<16 x i8>> [#uses=1]
+ %tmp20 = insertelement <16 x i8> %tmp19, i8 %tmp4, i32 1 ; <<16 x i8>> [#uses=1]
+ %tmp21 = insertelement <16 x i8> %tmp20, i8 %tmp5, i32 2 ; <<16 x i8>> [#uses=1]
+ %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 3 ; <<16 x i8>> [#uses=1]
+ %tmp23 = insertelement <16 x i8> %tmp22, i8 %tmp7, i32 4 ; <<16 x i8>> [#uses=1]
+ %tmp24 = insertelement <16 x i8> %tmp23, i8 %tmp8, i32 5 ; <<16 x i8>> [#uses=1]
+ %tmp25 = insertelement <16 x i8> %tmp24, i8 %tmp9, i32 6 ; <<16 x i8>> [#uses=1]
+ %tmp26 = insertelement <16 x i8> %tmp25, i8 %tmp10, i32 7 ; <<16 x i8>> [#uses=1]
+ %tmp27 = insertelement <16 x i8> %tmp26, i8 %tmp11, i32 8 ; <<16 x i8>> [#uses=1]
+ %tmp28 = insertelement <16 x i8> %tmp27, i8 %tmp12, i32 9 ; <<16 x i8>> [#uses=1]
+ %tmp29 = insertelement <16 x i8> %tmp28, i8 %tmp13, i32 10 ; <<16 x i8>> [#uses=1]
+ %tmp30 = insertelement <16 x i8> %tmp29, i8 %tmp14, i32 11 ; <<16 x i8>> [#uses=1]
+ %tmp31 = insertelement <16 x i8> %tmp30, i8 %tmp15, i32 12 ; <<16 x i8>> [#uses=1]
+ %tmp32 = insertelement <16 x i8> %tmp31, i8 %tmp16, i32 13 ; <<16 x i8>> [#uses=1]
+ %tmp33 = insertelement <16 x i8> %tmp32, i8 %tmp17, i32 14 ; <<16 x i8>> [#uses=1]
+ %tmp34 = insertelement <16 x i8> %tmp33, i8 %tmp18, i32 15 ; <<16 x i8>> [#uses=1]
+ %tmp34.upgrd.27 = bitcast <16 x i8> %tmp34 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ store <8 x i16> %tmp34.upgrd.27, <8 x i16>* %A
+ ret void
+}
+
+define void @VPCKUWUM_unary(<4 x i32>* %A, <4 x i32>* %B) {
+entry:
+ %tmp = load <4 x i32>* %A ; <<4 x i32>> [#uses=2]
+ %tmp.upgrd.28 = bitcast <4 x i32> %tmp to <8 x i16> ; <<8 x i16>> [#uses=4]
+ %tmp3 = bitcast <4 x i32> %tmp to <8 x i16> ; <<8 x i16>> [#uses=4]
+ %tmp.upgrd.29 = extractelement <8 x i16> %tmp.upgrd.28, i32 1 ; <i16> [#uses=1]
+ %tmp4 = extractelement <8 x i16> %tmp.upgrd.28, i32 3 ; <i16> [#uses=1]
+ %tmp5 = extractelement <8 x i16> %tmp.upgrd.28, i32 5 ; <i16> [#uses=1]
+ %tmp6 = extractelement <8 x i16> %tmp.upgrd.28, i32 7 ; <i16> [#uses=1]
+ %tmp7 = extractelement <8 x i16> %tmp3, i32 1 ; <i16> [#uses=1]
+ %tmp8 = extractelement <8 x i16> %tmp3, i32 3 ; <i16> [#uses=1]
+ %tmp9 = extractelement <8 x i16> %tmp3, i32 5 ; <i16> [#uses=1]
+ %tmp10 = extractelement <8 x i16> %tmp3, i32 7 ; <i16> [#uses=1]
+ %tmp11 = insertelement <8 x i16> undef, i16 %tmp.upgrd.29, i32 0 ; <<8 x i16>> [#uses=1]
+ %tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp4, i32 1 ; <<8 x i16>> [#uses=1]
+ %tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 2 ; <<8 x i16>> [#uses=1]
+ %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp6, i32 3 ; <<8 x i16>> [#uses=1]
+ %tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 4 ; <<8 x i16>> [#uses=1]
+ %tmp16 = insertelement <8 x i16> %tmp15, i16 %tmp8, i32 5 ; <<8 x i16>> [#uses=1]
+ %tmp17 = insertelement <8 x i16> %tmp16, i16 %tmp9, i32 6 ; <<8 x i16>> [#uses=1]
+ %tmp18 = insertelement <8 x i16> %tmp17, i16 %tmp10, i32 7 ; <<8 x i16>> [#uses=1]
+ %tmp18.upgrd.30 = bitcast <8 x i16> %tmp18 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %tmp18.upgrd.30, <4 x i32>* %A
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/vec_splat.ll b/test/CodeGen/PowerPC/vec_splat.ll
new file mode 100644
index 0000000..6123728
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_splat.ll
@@ -0,0 +1,71 @@
+; Test that vectors are scalarized/lowered correctly.
+; RUN: llc < %s -march=ppc32 -mcpu=g3 | \
+; RUN: grep stfs | count 4
+; RUN: llc < %s -march=ppc32 -mcpu=g5 -o %t
+; RUN: grep vspltw %t | count 2
+; RUN: grep vsplti %t | count 3
+; RUN: grep vsplth %t | count 1
+
+ %f4 = type <4 x float>
+ %i4 = type <4 x i32>
+
+define void @splat(%f4* %P, %f4* %Q, float %X) nounwind {
+ %tmp = insertelement %f4 undef, float %X, i32 0 ; <%f4> [#uses=1]
+ %tmp2 = insertelement %f4 %tmp, float %X, i32 1 ; <%f4> [#uses=1]
+ %tmp4 = insertelement %f4 %tmp2, float %X, i32 2 ; <%f4> [#uses=1]
+ %tmp6 = insertelement %f4 %tmp4, float %X, i32 3 ; <%f4> [#uses=1]
+ %q = load %f4* %Q ; <%f4> [#uses=1]
+ %R = fadd %f4 %q, %tmp6 ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %P
+ ret void
+}
+
+define void @splat_i4(%i4* %P, %i4* %Q, i32 %X) nounwind {
+ %tmp = insertelement %i4 undef, i32 %X, i32 0 ; <%i4> [#uses=1]
+ %tmp2 = insertelement %i4 %tmp, i32 %X, i32 1 ; <%i4> [#uses=1]
+ %tmp4 = insertelement %i4 %tmp2, i32 %X, i32 2 ; <%i4> [#uses=1]
+ %tmp6 = insertelement %i4 %tmp4, i32 %X, i32 3 ; <%i4> [#uses=1]
+ %q = load %i4* %Q ; <%i4> [#uses=1]
+ %R = add %i4 %q, %tmp6 ; <%i4> [#uses=1]
+ store %i4 %R, %i4* %P
+ ret void
+}
+
+define void @splat_imm_i32(%i4* %P, %i4* %Q, i32 %X) nounwind {
+ %q = load %i4* %Q ; <%i4> [#uses=1]
+ %R = add %i4 %q, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <%i4> [#uses=1]
+ store %i4 %R, %i4* %P
+ ret void
+}
+
+define void @splat_imm_i16(%i4* %P, %i4* %Q, i32 %X) nounwind {
+ %q = load %i4* %Q ; <%i4> [#uses=1]
+ %R = add %i4 %q, < i32 65537, i32 65537, i32 65537, i32 65537 > ; <%i4> [#uses=1]
+ store %i4 %R, %i4* %P
+ ret void
+}
+
+define void @splat_h(i16 %tmp, <16 x i8>* %dst) nounwind {
+ %tmp.upgrd.1 = insertelement <8 x i16> undef, i16 %tmp, i32 0
+ %tmp72 = insertelement <8 x i16> %tmp.upgrd.1, i16 %tmp, i32 1
+ %tmp73 = insertelement <8 x i16> %tmp72, i16 %tmp, i32 2
+ %tmp74 = insertelement <8 x i16> %tmp73, i16 %tmp, i32 3
+ %tmp75 = insertelement <8 x i16> %tmp74, i16 %tmp, i32 4
+ %tmp76 = insertelement <8 x i16> %tmp75, i16 %tmp, i32 5
+ %tmp77 = insertelement <8 x i16> %tmp76, i16 %tmp, i32 6
+ %tmp78 = insertelement <8 x i16> %tmp77, i16 %tmp, i32 7
+ %tmp78.upgrd.2 = bitcast <8 x i16> %tmp78 to <16 x i8>
+ store <16 x i8> %tmp78.upgrd.2, <16 x i8>* %dst
+ ret void
+}
+
+define void @spltish(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+ %tmp = load <16 x i8>* %B ; <<16 x i8>> [#uses=1]
+ %tmp.s = bitcast <16 x i8> %tmp to <16 x i8> ; <<16 x i8>> [#uses=1]
+ %tmp4 = sub <16 x i8> %tmp.s, bitcast (<8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16
+ 15, i16 15, i16 15 > to <16 x i8>) ; <<16 x i8>> [#uses=1]
+ %tmp4.u = bitcast <16 x i8> %tmp4 to <16 x i8> ; <<16 x i8>> [#uses=1]
+ store <16 x i8> %tmp4.u, <16 x i8>* %A
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/vec_splat_constant.ll b/test/CodeGen/PowerPC/vec_splat_constant.ll
new file mode 100644
index 0000000..b227794
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_splat_constant.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s
+; Formerly incorrectly inserted vsldoi (endian confusion)
+
+@baz = common global <16 x i8> zeroinitializer ; <<16 x i8>*> [#uses=1]
+
+define void @foo(<16 x i8> %x) nounwind ssp {
+entry:
+; CHECK: _foo:
+; CHECK-NOT: vsldoi
+ %x_addr = alloca <16 x i8> ; <<16 x i8>*> [#uses=2]
+ %temp = alloca <16 x i8> ; <<16 x i8>*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store <16 x i8> %x, <16 x i8>* %x_addr
+ store <16 x i8> <i8 0, i8 0, i8 0, i8 14, i8 0, i8 0, i8 0, i8 14, i8 0, i8 0, i8 0, i8 14, i8 0, i8 0, i8 0, i8 14>, <16 x i8>* %temp, align 16
+ %0 = load <16 x i8>* %x_addr, align 16 ; <<16 x i8>> [#uses=1]
+ %1 = load <16 x i8>* %temp, align 16 ; <<16 x i8>> [#uses=1]
+ %tmp = add <16 x i8> %0, %1 ; <<16 x i8>> [#uses=1]
+ store <16 x i8> %tmp, <16 x i8>* @baz, align 16
+ br label %return
+
+return: ; preds = %entry
+ ret void
+; CHECK: blr
+}
diff --git a/test/CodeGen/PowerPC/vec_vrsave.ll b/test/CodeGen/PowerPC/vec_vrsave.ll
new file mode 100644
index 0000000..2a03d58
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_vrsave.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5 -o %t
+; RUN: grep vrlw %t
+; RUN: not grep spr %t
+; RUN: not grep vrsave %t
+
+define <4 x i32> @test_rol() {
+ ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
+}
+
+define <4 x i32> @test_arg(<4 x i32> %A, <4 x i32> %B) {
+ %C = add <4 x i32> %A, %B ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %C
+}
+
diff --git a/test/CodeGen/PowerPC/vec_zero.ll b/test/CodeGen/PowerPC/vec_zero.ll
new file mode 100644
index 0000000..f862b2c
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_zero.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vxor
+
+define void @foo(<4 x float>* %P) {
+ %T = load <4 x float>* %P ; <<4 x float>> [#uses=1]
+ %S = fadd <4 x float> zeroinitializer, %T ; <<4 x float>> [#uses=1]
+ store <4 x float> %S, <4 x float>* %P
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/vector-identity-shuffle.ll b/test/CodeGen/PowerPC/vector-identity-shuffle.ll
new file mode 100644
index 0000000..dfa2e35
--- /dev/null
+++ b/test/CodeGen/PowerPC/vector-identity-shuffle.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep test:
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep vperm
+
+define void @test(<4 x float>* %tmp2.i) {
+ %tmp2.i.upgrd.1 = load <4 x float>* %tmp2.i ; <<4 x float>> [#uses=4]
+ %xFloat0.48 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 0 ; <float> [#uses=1]
+ %inFloat0.49 = insertelement <4 x float> undef, float %xFloat0.48, i32 0 ; <<4 x float>> [#uses=1]
+ %xFloat1.50 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 1 ; <float> [#uses=1]
+ %inFloat1.52 = insertelement <4 x float> %inFloat0.49, float %xFloat1.50, i32 1 ; <<4 x float>> [#uses=1]
+ %xFloat2.53 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 2 ; <float> [#uses=1]
+ %inFloat2.55 = insertelement <4 x float> %inFloat1.52, float %xFloat2.53, i32 2 ; <<4 x float>> [#uses=1]
+ %xFloat3.56 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 3 ; <float> [#uses=1]
+ %inFloat3.58 = insertelement <4 x float> %inFloat2.55, float %xFloat3.56, i32 3 ; <<4 x float>> [#uses=1]
+ store <4 x float> %inFloat3.58, <4 x float>* %tmp2.i
+ ret void
+}
+
diff --git a/test/CodeGen/PowerPC/vector.ll b/test/CodeGen/PowerPC/vector.ll
new file mode 100644
index 0000000..ee4da31
--- /dev/null
+++ b/test/CodeGen/PowerPC/vector.ll
@@ -0,0 +1,158 @@
+; Test that vectors are scalarized/lowered correctly.
+; RUN: llc < %s -march=ppc32 -mcpu=g5 > %t
+; RUN: llc < %s -march=ppc32 -mcpu=g3 > %t
+
+%d8 = type <8 x double>
+%f1 = type <1 x float>
+%f2 = type <2 x float>
+%f4 = type <4 x float>
+%f8 = type <8 x float>
+%i4 = type <4 x i32>
+
+;;; TEST HANDLING OF VARIOUS VECTOR SIZES
+
+define void @test_f1(%f1* %P, %f1* %Q, %f1* %S) {
+ %p = load %f1* %P ; <%f1> [#uses=1]
+ %q = load %f1* %Q ; <%f1> [#uses=1]
+ %R = fadd %f1 %p, %q ; <%f1> [#uses=1]
+ store %f1 %R, %f1* %S
+ ret void
+}
+
+define void @test_f2(%f2* %P, %f2* %Q, %f2* %S) {
+ %p = load %f2* %P ; <%f2> [#uses=1]
+ %q = load %f2* %Q ; <%f2> [#uses=1]
+ %R = fadd %f2 %p, %q ; <%f2> [#uses=1]
+ store %f2 %R, %f2* %S
+ ret void
+}
+
+define void @test_f4(%f4* %P, %f4* %Q, %f4* %S) {
+ %p = load %f4* %P ; <%f4> [#uses=1]
+ %q = load %f4* %Q ; <%f4> [#uses=1]
+ %R = fadd %f4 %p, %q ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_f8(%f8* %P, %f8* %Q, %f8* %S) {
+ %p = load %f8* %P ; <%f8> [#uses=1]
+ %q = load %f8* %Q ; <%f8> [#uses=1]
+ %R = fadd %f8 %p, %q ; <%f8> [#uses=1]
+ store %f8 %R, %f8* %S
+ ret void
+}
+
+define void @test_fmul(%f8* %P, %f8* %Q, %f8* %S) {
+ %p = load %f8* %P ; <%f8> [#uses=1]
+ %q = load %f8* %Q ; <%f8> [#uses=1]
+ %R = fmul %f8 %p, %q ; <%f8> [#uses=1]
+ store %f8 %R, %f8* %S
+ ret void
+}
+
+define void @test_div(%f8* %P, %f8* %Q, %f8* %S) {
+ %p = load %f8* %P ; <%f8> [#uses=1]
+ %q = load %f8* %Q ; <%f8> [#uses=1]
+ %R = fdiv %f8 %p, %q ; <%f8> [#uses=1]
+ store %f8 %R, %f8* %S
+ ret void
+}
+
+;;; TEST VECTOR CONSTRUCTS
+
+define void @test_cst(%f4* %P, %f4* %S) {
+ %p = load %f4* %P ; <%f4> [#uses=1]
+ %R = fadd %f4 %p, < float 0x3FB99999A0000000, float 1.000000e+00, float
+ 2.000000e+00, float 4.500000e+00 > ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_zero(%f4* %P, %f4* %S) {
+ %p = load %f4* %P ; <%f4> [#uses=1]
+ %R = fadd %f4 %p, zeroinitializer ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_undef(%f4* %P, %f4* %S) {
+ %p = load %f4* %P ; <%f4> [#uses=1]
+ %R = fadd %f4 %p, undef ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_constant_insert(%f4* %S) {
+ %R = insertelement %f4 zeroinitializer, float 1.000000e+01, i32 0
+ ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_variable_buildvector(float %F, %f4* %S) {
+ %R = insertelement %f4 zeroinitializer, float %F, i32 0
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_scalar_to_vector(float %F, %f4* %S) {
+ %R = insertelement %f4 undef, float %F, i32 0
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define float @test_extract_elt(%f8* %P) {
+ %p = load %f8* %P ; <%f8> [#uses=1]
+ %R = extractelement %f8 %p, i32 3 ; <float> [#uses=1]
+ ret float %R
+}
+
+define double @test_extract_elt2(%d8* %P) {
+ %p = load %d8* %P ; <%d8> [#uses=1]
+ %R = extractelement %d8 %p, i32 3 ; <double> [#uses=1]
+ ret double %R
+}
+
+define void @test_cast_1(%f4* %b, %i4* %a) {
+ %tmp = load %f4* %b ; <%f4> [#uses=1]
+ %tmp2 = fadd %f4 %tmp, < float 1.000000e+00, float 2.000000e+00, float
+3.000000e+00, float 4.000000e+00 > ; <%f4> [#uses=1]
+ %tmp3 = bitcast %f4 %tmp2 to %i4 ; <%i4> [#uses=1]
+ %tmp4 = add %i4 %tmp3, < i32 1, i32 2, i32 3, i32 4 >
+ store %i4 %tmp4, %i4* %a
+ ret void
+}
+
+define void @test_cast_2(%f8* %a, <8 x i32>* %b) {
+ %T = load %f8* %a ; <%f8> [#uses=1]
+ %T2 = bitcast %f8 %T to <8 x i32>
+ store <8 x i32> %T2, <8 x i32>* %b
+ ret void
+}
+
+
+;;; TEST IMPORTANT IDIOMS
+
+define void @splat(%f4* %P, %f4* %Q, float %X) {
+ %tmp = insertelement %f4 undef, float %X, i32 0
+ %tmp2 = insertelement %f4 %tmp, float %X, i32 1
+ %tmp4 = insertelement %f4 %tmp2, float %X, i32 2
+ %tmp6 = insertelement %f4 %tmp4, float %X, i32 3
+ %q = load %f4* %Q ; <%f4> [#uses=1]
+ %R = fadd %f4 %q, %tmp6 ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %P
+ ret void
+}
+
+define void @splat_i4(%i4* %P, %i4* %Q, i32 %X) {
+ %tmp = insertelement %i4 undef, i32 %X, i32 0
+ %tmp2 = insertelement %i4 %tmp, i32 %X, i32 1
+ %tmp4 = insertelement %i4 %tmp2, i32 %X, i32 2
+ %tmp6 = insertelement %i4 %tmp4, i32 %X, i32 3
+ %q = load %i4* %Q ; <%i4> [#uses=1]
+ %R = add %i4 %q, %tmp6 ; <%i4> [#uses=1]
+ store %i4 %R, %i4* %P
+ ret void
+}
+
diff --git a/test/CodeGen/SPARC/2006-01-22-BitConvertLegalize.ll b/test/CodeGen/SPARC/2006-01-22-BitConvertLegalize.ll
new file mode 100644
index 0000000..082f9f4
--- /dev/null
+++ b/test/CodeGen/SPARC/2006-01-22-BitConvertLegalize.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=sparc
+
+define void @execute_list() {
+ %tmp.33.i = fdiv float 0.000000e+00, 0.000000e+00 ; <float> [#uses=1]
+ %tmp.37.i = fmul float 0.000000e+00, %tmp.33.i ; <float> [#uses=1]
+ %tmp.42.i = fadd float %tmp.37.i, 0.000000e+00 ; <float> [#uses=1]
+ call void @gl_EvalCoord1f( float %tmp.42.i )
+ ret void
+}
+
+declare void @gl_EvalCoord1f(float)
+
diff --git a/test/CodeGen/SPARC/2007-05-09-JumpTables.ll b/test/CodeGen/SPARC/2007-05-09-JumpTables.ll
new file mode 100644
index 0000000..41ad3b2
--- /dev/null
+++ b/test/CodeGen/SPARC/2007-05-09-JumpTables.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=sparc
+
+; We cannot emit jump tables on Sparc, but we should correctly handle this case.
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+
+define i32 @foo(i32 %f) {
+entry:
+ switch i32 %f, label %bb14 [
+ i32 0, label %UnifiedReturnBlock
+ i32 1, label %bb4
+ i32 2, label %bb7
+ i32 3, label %bb10
+ ]
+
+bb4: ; preds = %entry
+ ret i32 2
+
+bb7: ; preds = %entry
+ ret i32 5
+
+bb10: ; preds = %entry
+ ret i32 9
+
+bb14: ; preds = %entry
+ ret i32 0
+
+UnifiedReturnBlock: ; preds = %entry
+ ret i32 1
+}
diff --git a/test/CodeGen/SPARC/2007-07-05-LiveIntervalAssert.ll b/test/CodeGen/SPARC/2007-07-05-LiveIntervalAssert.ll
new file mode 100644
index 0000000..77c2002
--- /dev/null
+++ b/test/CodeGen/SPARC/2007-07-05-LiveIntervalAssert.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=sparc
+; PR1540
+
+declare float @sinf(float)
+declare double @sin(double)
+define double @test_sin(float %F) {
+ %G = call float @sinf( float %F ) ; <float> [#uses=1]
+ %H = fpext float %G to double ; <double> [#uses=1]
+ %I = call double @sin( double %H ) ; <double> [#uses=1]
+ ret double %I
+}
diff --git a/test/CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll b/test/CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll
new file mode 100644
index 0000000..e8315f1
--- /dev/null
+++ b/test/CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=sparc
+; PR 1557
+
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128"
[email protected]_ctors = appending global [1 x { i32, void ()* }] [ { i32, void ()* } { i32 65535, void ()* @set_fast_math } ] ; <[1 x { i32, void ()* }]*> [#uses=0]
+
+define internal void @set_fast_math() nounwind {
+entry:
+ %fsr = alloca i32 ; <i32*> [#uses=4]
+ call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
+ %0 = load i32* %fsr, align 4 ; <i32> [#uses=1]
+ %1 = or i32 %0, 4194304 ; <i32> [#uses=1]
+ store i32 %1, i32* %fsr, align 4
+ call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
+ ret void
+}
diff --git a/test/CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll b/test/CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll
new file mode 100644
index 0000000..c12e9c1
--- /dev/null
+++ b/test/CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=sparc
+; PR 1557
+
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f128:128:128"
+module asm "\09.section\09\22.ctors\22,#alloc,#write"
+module asm "\09.section\09\22.dtors\22,#alloc,#write"
+
+define void @frame_dummy() nounwind {
+entry:
+ %asmtmp = tail call void (i8*)* (void (i8*)*)* asm "", "=r,0"(void (i8*)* @_Jv_RegisterClasses) nounwind ; <void (i8*)*> [#uses=0]
+ unreachable
+}
+
+declare void @_Jv_RegisterClasses(i8*)
diff --git a/test/CodeGen/SPARC/2009-08-28-PIC.ll b/test/CodeGen/SPARC/2009-08-28-PIC.ll
new file mode 100644
index 0000000..a2ba0d0
--- /dev/null
+++ b/test/CodeGen/SPARC/2009-08-28-PIC.ll
@@ -0,0 +1,9 @@
+; RUN: llc -march=sparc --relocation-model=pic < %s | grep _GLOBAL_OFFSET_TABLE_
+
+@foo = global i32 0 ; <i32*> [#uses=1]
+
+define i32 @func() nounwind readonly {
+entry:
+ %0 = load i32* @foo, align 4 ; <i32> [#uses=1]
+ ret i32 %0
+}
diff --git a/test/CodeGen/SPARC/2009-08-28-WeakLinkage.ll b/test/CodeGen/SPARC/2009-08-28-WeakLinkage.ll
new file mode 100644
index 0000000..0167d32
--- /dev/null
+++ b/test/CodeGen/SPARC/2009-08-28-WeakLinkage.ll
@@ -0,0 +1,6 @@
+; RUN: llc -march=sparc < %s | grep weak
+
+define weak i32 @func() nounwind {
+entry:
+ ret i32 0
+}
diff --git a/test/CodeGen/SPARC/basictest.ll b/test/CodeGen/SPARC/basictest.ll
new file mode 100644
index 0000000..9c2c16a
--- /dev/null
+++ b/test/CodeGen/SPARC/basictest.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=sparc
+
+define i32 @test(i32 %X) {
+ %tmp.1 = add i32 %X, 1
+ ret i32 %tmp.1
+}
diff --git a/test/CodeGen/SPARC/ctpop.ll b/test/CodeGen/SPARC/ctpop.ll
new file mode 100644
index 0000000..e56f494
--- /dev/null
+++ b/test/CodeGen/SPARC/ctpop.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=sparc -mattr=-v9 | not grep popc
+; RUN: llc < %s -march=sparcv9 -mattr=v9 | grep popc
+
+declare i32 @llvm.ctpop.i32(i32)
+
+define i32 @test(i32 %X) {
+ %Y = call i32 @llvm.ctpop.i32( i32 %X ) ; <i32> [#uses=1]
+ ret i32 %Y
+}
+
diff --git a/test/CodeGen/SPARC/dg.exp b/test/CodeGen/SPARC/dg.exp
new file mode 100644
index 0000000..6c0a997
--- /dev/null
+++ b/test/CodeGen/SPARC/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target Sparc] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/SPARC/private.ll b/test/CodeGen/SPARC/private.ll
new file mode 100644
index 0000000..f091aa6
--- /dev/null
+++ b/test/CodeGen/SPARC/private.ll
@@ -0,0 +1,21 @@
+; Test to make sure that the 'private' is used correctly.
+;
+; RUN: llc < %s -march=sparc > %t
+; RUN: grep .foo: %t
+; RUN: grep call.*\.foo %t
+; RUN: grep .baz: %t
+; RUN: grep ld.*\.baz %t
+
+declare void @foo()
+
+define private void @foo() {
+ ret void
+}
+
+@baz = private global i32 4
+
+define i32 @bar() {
+ call void @foo()
+ %1 = load i32* @baz, align 4
+ ret i32 %1
+}
diff --git a/test/CodeGen/SPARC/xnor.ll b/test/CodeGen/SPARC/xnor.ll
new file mode 100644
index 0000000..6ff66bd
--- /dev/null
+++ b/test/CodeGen/SPARC/xnor.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=sparc | \
+; RUN: grep xnor | count 2
+
+define i32 @test1(i32 %X, i32 %Y) {
+ %A = xor i32 %X, %Y ; <i32> [#uses=1]
+ %B = xor i32 %A, -1 ; <i32> [#uses=1]
+ ret i32 %B
+}
+
+define i32 @test2(i32 %X, i32 %Y) {
+ %A = xor i32 %X, -1 ; <i32> [#uses=1]
+ %B = xor i32 %A, %Y ; <i32> [#uses=1]
+ ret i32 %B
+}
+
diff --git a/test/CodeGen/SystemZ/00-RetVoid.ll b/test/CodeGen/SystemZ/00-RetVoid.ll
new file mode 100644
index 0000000..de23795
--- /dev/null
+++ b/test/CodeGen/SystemZ/00-RetVoid.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=systemz
+
+define void @foo() {
+entry:
+ ret void
+}
\ No newline at end of file
diff --git a/test/CodeGen/SystemZ/01-RetArg.ll b/test/CodeGen/SystemZ/01-RetArg.ll
new file mode 100644
index 0000000..9ab2097
--- /dev/null
+++ b/test/CodeGen/SystemZ/01-RetArg.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=systemz
+
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+ ret i64 %b
+}
\ No newline at end of file
diff --git a/test/CodeGen/SystemZ/01-RetImm.ll b/test/CodeGen/SystemZ/01-RetImm.ll
new file mode 100644
index 0000000..8b99e68
--- /dev/null
+++ b/test/CodeGen/SystemZ/01-RetImm.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=systemz | grep lghi | count 1
+; RUN: llc < %s -march=systemz | grep llill | count 1
+; RUN: llc < %s -march=systemz | grep llilh | count 1
+; RUN: llc < %s -march=systemz | grep llihl | count 1
+; RUN: llc < %s -march=systemz | grep llihh | count 1
+; RUN: llc < %s -march=systemz | grep lgfi | count 1
+; RUN: llc < %s -march=systemz | grep llilf | count 1
+; RUN: llc < %s -march=systemz | grep llihf | count 1
+
+
+define i64 @foo1() {
+entry:
+ ret i64 1
+}
+
+define i64 @foo2() {
+entry:
+ ret i64 65535
+}
+
+define i64 @foo3() {
+entry:
+ ret i64 131072
+}
+
+define i64 @foo4() {
+entry:
+ ret i64 8589934592
+}
+
+define i64 @foo5() {
+entry:
+ ret i64 562949953421312
+}
+
+define i64 @foo6() {
+entry:
+ ret i64 65537
+}
+
+define i64 @foo7() {
+entry:
+ ret i64 4294967295
+}
+
+define i64 @foo8() {
+entry:
+ ret i64 281483566645248
+}
diff --git a/test/CodeGen/SystemZ/02-MemArith.ll b/test/CodeGen/SystemZ/02-MemArith.ll
new file mode 100644
index 0000000..04022a0
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-MemArith.ll
@@ -0,0 +1,133 @@
+; RUN: llc < %s -march=systemz | FileCheck %s
+
+define i32 @foo1(i32 %a, i32 *%b, i64 %idx) signext {
+; CHECK: foo1:
+; CHECK: a %r2, 4(%r1,%r3)
+entry:
+ %idx2 = add i64 %idx, 1 ; <i64> [#uses=1]
+ %ptr = getelementptr i32* %b, i64 %idx2 ; <i32*> [#uses=1]
+ %c = load i32* %ptr
+ %d = add i32 %a, %c
+ ret i32 %d
+}
+
+define i32 @foo2(i32 %a, i32 *%b, i64 %idx) signext {
+; CHECK: foo2:
+; CHECK: ay %r2, -4(%r1,%r3)
+entry:
+ %idx2 = add i64 %idx, -1 ; <i64> [#uses=1]
+ %ptr = getelementptr i32* %b, i64 %idx2 ; <i32*> [#uses=1]
+ %c = load i32* %ptr
+ %d = add i32 %a, %c
+ ret i32 %d
+}
+
+define i64 @foo3(i64 %a, i64 *%b, i64 %idx) signext {
+; CHECK: foo3:
+; CHECK: ag %r2, 8(%r1,%r3)
+entry:
+ %idx2 = add i64 %idx, 1 ; <i64> [#uses=1]
+ %ptr = getelementptr i64* %b, i64 %idx2 ; <i64*> [#uses=1]
+ %c = load i64* %ptr
+ %d = add i64 %a, %c
+ ret i64 %d
+}
+
+define i32 @foo4(i32 %a, i32 *%b, i64 %idx) signext {
+; CHECK: foo4:
+; CHECK: n %r2, 4(%r1,%r3)
+entry:
+ %idx2 = add i64 %idx, 1 ; <i64> [#uses=1]
+ %ptr = getelementptr i32* %b, i64 %idx2 ; <i32*> [#uses=1]
+ %c = load i32* %ptr
+ %d = and i32 %a, %c
+ ret i32 %d
+}
+
+define i32 @foo5(i32 %a, i32 *%b, i64 %idx) signext {
+; CHECK: foo5:
+; CHECK: ny %r2, -4(%r1,%r3)
+entry:
+ %idx2 = add i64 %idx, -1 ; <i64> [#uses=1]
+ %ptr = getelementptr i32* %b, i64 %idx2 ; <i32*> [#uses=1]
+ %c = load i32* %ptr
+ %d = and i32 %a, %c
+ ret i32 %d
+}
+
+define i64 @foo6(i64 %a, i64 *%b, i64 %idx) signext {
+; CHECK: foo6:
+; CHECK: ng %r2, 8(%r1,%r3)
+entry:
+ %idx2 = add i64 %idx, 1 ; <i64> [#uses=1]
+ %ptr = getelementptr i64* %b, i64 %idx2 ; <i64*> [#uses=1]
+ %c = load i64* %ptr
+ %d = and i64 %a, %c
+ ret i64 %d
+}
+
+define i32 @foo7(i32 %a, i32 *%b, i64 %idx) signext {
+; CHECK: foo7:
+; CHECK: o %r2, 4(%r1,%r3)
+entry:
+ %idx2 = add i64 %idx, 1 ; <i64> [#uses=1]
+ %ptr = getelementptr i32* %b, i64 %idx2 ; <i32*> [#uses=1]
+ %c = load i32* %ptr
+ %d = or i32 %a, %c
+ ret i32 %d
+}
+
+define i32 @foo8(i32 %a, i32 *%b, i64 %idx) signext {
+; CHECK: foo8:
+; CHECK: oy %r2, -4(%r1,%r3)
+entry:
+ %idx2 = add i64 %idx, -1 ; <i64> [#uses=1]
+ %ptr = getelementptr i32* %b, i64 %idx2 ; <i32*> [#uses=1]
+ %c = load i32* %ptr
+ %d = or i32 %a, %c
+ ret i32 %d
+}
+
+define i64 @foo9(i64 %a, i64 *%b, i64 %idx) signext {
+; CHECK: foo9:
+; CHECK: og %r2, 8(%r1,%r3)
+entry:
+ %idx2 = add i64 %idx, 1 ; <i64> [#uses=1]
+ %ptr = getelementptr i64* %b, i64 %idx2 ; <i64*> [#uses=1]
+ %c = load i64* %ptr
+ %d = or i64 %a, %c
+ ret i64 %d
+}
+
+define i32 @foo10(i32 %a, i32 *%b, i64 %idx) signext {
+; CHECK: foo10:
+; CHECK: x %r2, 4(%r1,%r3)
+entry:
+ %idx2 = add i64 %idx, 1 ; <i64> [#uses=1]
+ %ptr = getelementptr i32* %b, i64 %idx2 ; <i32*> [#uses=1]
+ %c = load i32* %ptr
+ %d = xor i32 %a, %c
+ ret i32 %d
+}
+
+define i32 @foo11(i32 %a, i32 *%b, i64 %idx) signext {
+; CHECK: foo11:
+; CHECK: xy %r2, -4(%r1,%r3)
+entry:
+ %idx2 = add i64 %idx, -1 ; <i64> [#uses=1]
+ %ptr = getelementptr i32* %b, i64 %idx2 ; <i32*> [#uses=1]
+ %c = load i32* %ptr
+ %d = xor i32 %a, %c
+ ret i32 %d
+}
+
+define i64 @foo12(i64 %a, i64 *%b, i64 %idx) signext {
+; CHECK: foo12:
+; CHECK: xg %r2, 8(%r1,%r3)
+entry:
+ %idx2 = add i64 %idx, 1 ; <i64> [#uses=1]
+ %ptr = getelementptr i64* %b, i64 %idx2 ; <i64*> [#uses=1]
+ %c = load i64* %ptr
+ %d = xor i64 %a, %c
+ ret i64 %d
+}
diff --git a/test/CodeGen/SystemZ/02-RetAdd.ll b/test/CodeGen/SystemZ/02-RetAdd.ll
new file mode 100644
index 0000000..9ff9b6a
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetAdd.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=systemz
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+ %c = add i64 %a, %b
+ ret i64 %c
+}
\ No newline at end of file
diff --git a/test/CodeGen/SystemZ/02-RetAddImm.ll b/test/CodeGen/SystemZ/02-RetAddImm.ll
new file mode 100644
index 0000000..6d73e4d
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetAddImm.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=systemz
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+ %c = add i64 %a, 1
+ ret i64 %c
+}
\ No newline at end of file
diff --git a/test/CodeGen/SystemZ/02-RetAnd.ll b/test/CodeGen/SystemZ/02-RetAnd.ll
new file mode 100644
index 0000000..1492f9d
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetAnd.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=systemz
+
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+ %c = and i64 %a, %b
+ ret i64 %c
+}
\ No newline at end of file
diff --git a/test/CodeGen/SystemZ/02-RetAndImm.ll b/test/CodeGen/SystemZ/02-RetAndImm.ll
new file mode 100644
index 0000000..53c5e54
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetAndImm.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=systemz | grep ngr | count 4
+; RUN: llc < %s -march=systemz | grep llilh | count 1
+; RUN: llc < %s -march=systemz | grep llihl | count 1
+; RUN: llc < %s -march=systemz | grep llihh | count 1
+
+define i64 @foo1(i64 %a, i64 %b) {
+entry:
+ %c = and i64 %a, 1
+ ret i64 %c
+}
+
+define i64 @foo2(i64 %a, i64 %b) {
+entry:
+ %c = and i64 %a, 131072
+ ret i64 %c
+}
+
+define i64 @foo3(i64 %a, i64 %b) {
+entry:
+ %c = and i64 %a, 8589934592
+ ret i64 %c
+}
+
+define i64 @foo4(i64 %a, i64 %b) {
+entry:
+ %c = and i64 %a, 562949953421312
+ ret i64 %c
+}
diff --git a/test/CodeGen/SystemZ/02-RetNeg.ll b/test/CodeGen/SystemZ/02-RetNeg.ll
new file mode 100644
index 0000000..7f3380d
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetNeg.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=systemz | grep lcgr | count 1
+
+define i64 @foo(i64 %a) {
+entry:
+ %c = sub i64 0, %a
+ ret i64 %c
+}
\ No newline at end of file
diff --git a/test/CodeGen/SystemZ/02-RetOr.ll b/test/CodeGen/SystemZ/02-RetOr.ll
new file mode 100644
index 0000000..1e8134d
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetOr.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=systemz
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+ %c = or i64 %a, %b
+ ret i64 %c
+}
\ No newline at end of file
diff --git a/test/CodeGen/SystemZ/02-RetOrImm.ll b/test/CodeGen/SystemZ/02-RetOrImm.ll
new file mode 100644
index 0000000..68cd24d
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetOrImm.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=systemz | grep oill | count 1
+; RUN: llc < %s -march=systemz | grep oilh | count 1
+; RUN: llc < %s -march=systemz | grep oihl | count 1
+; RUN: llc < %s -march=systemz | grep oihh | count 1
+
+define i64 @foo1(i64 %a, i64 %b) {
+entry:
+ %c = or i64 %a, 1
+ ret i64 %c
+}
+
+define i64 @foo2(i64 %a, i64 %b) {
+entry:
+ %c = or i64 %a, 131072
+ ret i64 %c
+}
+
+define i64 @foo3(i64 %a, i64 %b) {
+entry:
+ %c = or i64 %a, 8589934592
+ ret i64 %c
+}
+
+define i64 @foo4(i64 %a, i64 %b) {
+entry:
+ %c = or i64 %a, 562949953421312
+ ret i64 %c
+}
diff --git a/test/CodeGen/SystemZ/02-RetSub.ll b/test/CodeGen/SystemZ/02-RetSub.ll
new file mode 100644
index 0000000..1c4514f
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetSub.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=systemz
+
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+ %c = sub i64 %a, %b
+ ret i64 %c
+}
\ No newline at end of file
diff --git a/test/CodeGen/SystemZ/02-RetSubImm.ll b/test/CodeGen/SystemZ/02-RetSubImm.ll
new file mode 100644
index 0000000..4f91cb0
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetSubImm.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=systemz
+
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+ %c = sub i64 %a, 1
+ ret i64 %c
+}
\ No newline at end of file
diff --git a/test/CodeGen/SystemZ/02-RetXor.ll b/test/CodeGen/SystemZ/02-RetXor.ll
new file mode 100644
index 0000000..a9439bf
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetXor.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=systemz
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+ %c = xor i64 %a, %b
+ ret i64 %c
+}
\ No newline at end of file
diff --git a/test/CodeGen/SystemZ/02-RetXorImm.ll b/test/CodeGen/SystemZ/02-RetXorImm.ll
new file mode 100644
index 0000000..ea4b829
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetXorImm.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=systemz
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+ %c = xor i64 %a, 1
+ ret i64 %c
+}
\ No newline at end of file
diff --git a/test/CodeGen/SystemZ/03-RetAddImmSubreg.ll b/test/CodeGen/SystemZ/03-RetAddImmSubreg.ll
new file mode 100644
index 0000000..0a81271
--- /dev/null
+++ b/test/CodeGen/SystemZ/03-RetAddImmSubreg.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=systemz | grep ahi | count 3
+; RUN: llc < %s -march=systemz | grep afi | count 3
+; RUN: llc < %s -march=systemz | grep lgfr | count 4
+; RUN: llc < %s -march=systemz | grep llgfr | count 2
+
+
+define i32 @foo1(i32 %a, i32 %b) {
+entry:
+ %c = add i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo2(i32 %a, i32 %b) {
+entry:
+ %c = add i32 %a, 131072
+ ret i32 %c
+}
+
+define i32 @foo3(i32 %a, i32 %b) zeroext {
+entry:
+ %c = add i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo4(i32 %a, i32 %b) zeroext {
+entry:
+ %c = add i32 %a, 131072
+ ret i32 %c
+}
+
+define i32 @foo5(i32 %a, i32 %b) signext {
+entry:
+ %c = add i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo6(i32 %a, i32 %b) signext {
+entry:
+ %c = add i32 %a, 131072
+ ret i32 %c
+}
+
diff --git a/test/CodeGen/SystemZ/03-RetAddSubreg.ll b/test/CodeGen/SystemZ/03-RetAddSubreg.ll
new file mode 100644
index 0000000..2787083
--- /dev/null
+++ b/test/CodeGen/SystemZ/03-RetAddSubreg.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=systemz | grep ar | count 3
+; RUN: llc < %s -march=systemz | grep lgfr | count 2
+; RUN: llc < %s -march=systemz | grep llgfr | count 1
+
+define i32 @foo(i32 %a, i32 %b) {
+entry:
+ %c = add i32 %a, %b
+ ret i32 %c
+}
+
+define i32 @foo1(i32 %a, i32 %b) zeroext {
+entry:
+ %c = add i32 %a, %b
+ ret i32 %c
+}
+
+define i32 @foo2(i32 %a, i32 %b) signext {
+entry:
+ %c = add i32 %a, %b
+ ret i32 %c
+}
+
diff --git a/test/CodeGen/SystemZ/03-RetAndImmSubreg.ll b/test/CodeGen/SystemZ/03-RetAndImmSubreg.ll
new file mode 100644
index 0000000..32673dd
--- /dev/null
+++ b/test/CodeGen/SystemZ/03-RetAndImmSubreg.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -march=systemz | grep ngr | count 6
+
+define i32 @foo1(i32 %a, i32 %b) {
+entry:
+ %c = and i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo2(i32 %a, i32 %b) {
+entry:
+ %c = and i32 %a, 131072
+ ret i32 %c
+}
+
+define i32 @foo3(i32 %a, i32 %b) zeroext {
+entry:
+ %c = and i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo4(i32 %a, i32 %b) signext {
+entry:
+ %c = and i32 %a, 131072
+ ret i32 %c
+}
+
+define i32 @foo5(i32 %a, i32 %b) zeroext {
+entry:
+ %c = and i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo6(i32 %a, i32 %b) signext {
+entry:
+ %c = and i32 %a, 131072
+ ret i32 %c
+}
+
diff --git a/test/CodeGen/SystemZ/03-RetAndSubreg.ll b/test/CodeGen/SystemZ/03-RetAndSubreg.ll
new file mode 100644
index 0000000..ed5e526
--- /dev/null
+++ b/test/CodeGen/SystemZ/03-RetAndSubreg.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=systemz | grep ngr | count 3
+; RUN: llc < %s -march=systemz | grep nihf | count 1
+
+define i32 @foo(i32 %a, i32 %b) {
+entry:
+ %c = and i32 %a, %b
+ ret i32 %c
+}
+
+define i32 @foo1(i32 %a, i32 %b) zeroext {
+entry:
+ %c = and i32 %a, %b
+ ret i32 %c
+}
+
+define i32 @foo2(i32 %a, i32 %b) signext {
+entry:
+ %c = and i32 %a, %b
+ ret i32 %c
+}
+
diff --git a/test/CodeGen/SystemZ/03-RetArgSubreg.ll b/test/CodeGen/SystemZ/03-RetArgSubreg.ll
new file mode 100644
index 0000000..0c9bb14
--- /dev/null
+++ b/test/CodeGen/SystemZ/03-RetArgSubreg.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=systemz | grep lgr | count 2
+; RUN: llc < %s -march=systemz | grep nihf | count 1
+; RUN: llc < %s -march=systemz | grep lgfr | count 1
+
+
+define i32 @foo(i32 %a, i32 %b) {
+entry:
+ ret i32 %b
+}
+
+define i32 @foo1(i32 %a, i32 %b) zeroext {
+entry:
+ ret i32 %b
+}
+
+define i32 @foo2(i32 %a, i32 %b) signext {
+entry:
+ ret i32 %b
+}
diff --git a/test/CodeGen/SystemZ/03-RetImmSubreg.ll b/test/CodeGen/SystemZ/03-RetImmSubreg.ll
new file mode 100644
index 0000000..343e30b
--- /dev/null
+++ b/test/CodeGen/SystemZ/03-RetImmSubreg.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=systemz | grep lghi | count 2
+; RUN: llc < %s -march=systemz | grep llill | count 1
+; RUN: llc < %s -march=systemz | grep llilh | count 1
+; RUN: llc < %s -march=systemz | grep lgfi | count 1
+; RUN: llc < %s -march=systemz | grep llilf | count 2
+
+
+define i32 @foo1() {
+entry:
+ ret i32 1
+}
+
+define i32 @foo2() {
+entry:
+ ret i32 65535
+}
+
+define i32 @foo3() {
+entry:
+ ret i32 131072
+}
+
+define i32 @foo4() {
+entry:
+ ret i32 65537
+}
+
+define i32 @foo5() {
+entry:
+ ret i32 4294967295
+}
+
+define i32 @foo6() zeroext {
+entry:
+ ret i32 4294967295
+}
+
+define i32 @foo7() signext {
+entry:
+ ret i32 4294967295
+}
+
diff --git a/test/CodeGen/SystemZ/03-RetNegImmSubreg.ll b/test/CodeGen/SystemZ/03-RetNegImmSubreg.ll
new file mode 100644
index 0000000..87ebcc1
--- /dev/null
+++ b/test/CodeGen/SystemZ/03-RetNegImmSubreg.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=systemz | grep lcr | count 1
+
+define i32 @foo(i32 %a) {
+entry:
+ %c = sub i32 0, %a
+ ret i32 %c
+}
+
diff --git a/test/CodeGen/SystemZ/03-RetOrImmSubreg.ll b/test/CodeGen/SystemZ/03-RetOrImmSubreg.ll
new file mode 100644
index 0000000..6d118b5
--- /dev/null
+++ b/test/CodeGen/SystemZ/03-RetOrImmSubreg.ll
@@ -0,0 +1,60 @@
+; RUN: llc < %s -march=systemz | grep oill | count 3
+; RUN: llc < %s -march=systemz | grep oilh | count 3
+; RUN: llc < %s -march=systemz | grep oilf | count 3
+; RUN: llc < %s -march=systemz | grep llgfr | count 3
+; RUN: llc < %s -march=systemz | grep lgfr | count 6
+
+define i32 @foo1(i32 %a, i32 %b) {
+entry:
+ %c = or i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo2(i32 %a, i32 %b) {
+entry:
+ %c = or i32 %a, 131072
+ ret i32 %c
+}
+
+define i32 @foo7(i32 %a, i32 %b) {
+entry:
+ %c = or i32 %a, 123456
+ ret i32 %c
+}
+
+define i32 @foo3(i32 %a, i32 %b) zeroext {
+entry:
+ %c = or i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo8(i32 %a, i32 %b) zeroext {
+entry:
+ %c = or i32 %a, 123456
+ ret i32 %c
+}
+
+define i32 @foo4(i32 %a, i32 %b) signext {
+entry:
+ %c = or i32 %a, 131072
+ ret i32 %c
+}
+
+define i32 @foo5(i32 %a, i32 %b) zeroext {
+entry:
+ %c = or i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo6(i32 %a, i32 %b) signext {
+entry:
+ %c = or i32 %a, 131072
+ ret i32 %c
+}
+
+define i32 @foo9(i32 %a, i32 %b) signext {
+entry:
+ %c = or i32 %a, 123456
+ ret i32 %c
+}
+
diff --git a/test/CodeGen/SystemZ/03-RetOrSubreg.ll b/test/CodeGen/SystemZ/03-RetOrSubreg.ll
new file mode 100644
index 0000000..4d7661a
--- /dev/null
+++ b/test/CodeGen/SystemZ/03-RetOrSubreg.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=systemz | grep ogr | count 3
+; RUN: llc < %s -march=systemz | grep nihf | count 1
+; RUN: llc < %s -march=systemz | grep lgfr | count 1
+
+
+define i32 @foo(i32 %a, i32 %b) {
+entry:
+ %c = or i32 %a, %b
+ ret i32 %c
+}
+
+define i32 @foo1(i32 %a, i32 %b) zeroext {
+entry:
+ %c = or i32 %a, %b
+ ret i32 %c
+}
+
+define i32 @foo2(i32 %a, i32 %b) signext {
+entry:
+ %c = or i32 %a, %b
+ ret i32 %c
+}
+
diff --git a/test/CodeGen/SystemZ/03-RetSubImmSubreg.ll b/test/CodeGen/SystemZ/03-RetSubImmSubreg.ll
new file mode 100644
index 0000000..11ca796
--- /dev/null
+++ b/test/CodeGen/SystemZ/03-RetSubImmSubreg.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=systemz | grep ahi | count 3
+; RUN: llc < %s -march=systemz | grep afi | count 3
+; RUN: llc < %s -march=systemz | grep lgfr | count 4
+; RUN: llc < %s -march=systemz | grep llgfr | count 2
+
+
+define i32 @foo1(i32 %a, i32 %b) {
+entry:
+ %c = sub i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo2(i32 %a, i32 %b) {
+entry:
+ %c = sub i32 %a, 131072
+ ret i32 %c
+}
+
+define i32 @foo3(i32 %a, i32 %b) zeroext {
+entry:
+ %c = sub i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo4(i32 %a, i32 %b) signext {
+entry:
+ %c = sub i32 %a, 131072
+ ret i32 %c
+}
+
+define i32 @foo5(i32 %a, i32 %b) zeroext {
+entry:
+ %c = sub i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo6(i32 %a, i32 %b) signext {
+entry:
+ %c = sub i32 %a, 131072
+ ret i32 %c
+}
+
diff --git a/test/CodeGen/SystemZ/03-RetSubSubreg.ll b/test/CodeGen/SystemZ/03-RetSubSubreg.ll
new file mode 100644
index 0000000..b3e1ac2
--- /dev/null
+++ b/test/CodeGen/SystemZ/03-RetSubSubreg.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=systemz | grep sr | count 3
+; RUN: llc < %s -march=systemz | grep llgfr | count 1
+; RUN: llc < %s -march=systemz | grep lgfr | count 2
+
+define i32 @foo(i32 %a, i32 %b) {
+entry:
+ %c = sub i32 %a, %b
+ ret i32 %c
+}
+
+define i32 @foo1(i32 %a, i32 %b) zeroext {
+entry:
+ %c = sub i32 %a, %b
+ ret i32 %c
+}
+
+define i32 @foo2(i32 %a, i32 %b) signext {
+entry:
+ %c = sub i32 %a, %b
+ ret i32 %c
+}
+
diff --git a/test/CodeGen/SystemZ/03-RetXorImmSubreg.ll b/test/CodeGen/SystemZ/03-RetXorImmSubreg.ll
new file mode 100644
index 0000000..0033126
--- /dev/null
+++ b/test/CodeGen/SystemZ/03-RetXorImmSubreg.ll
@@ -0,0 +1,58 @@
+; RUN: llc < %s -march=systemz | grep xilf | count 9
+; RUN: llc < %s -march=systemz | grep llgfr | count 3
+; RUN: llc < %s -march=systemz | grep lgfr | count 6
+
+define i32 @foo1(i32 %a, i32 %b) {
+entry:
+ %c = xor i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo2(i32 %a, i32 %b) {
+entry:
+ %c = xor i32 %a, 131072
+ ret i32 %c
+}
+
+define i32 @foo7(i32 %a, i32 %b) {
+entry:
+ %c = xor i32 %a, 123456
+ ret i32 %c
+}
+
+define i32 @foo3(i32 %a, i32 %b) zeroext {
+entry:
+ %c = xor i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo8(i32 %a, i32 %b) zeroext {
+entry:
+ %c = xor i32 %a, 123456
+ ret i32 %c
+}
+
+define i32 @foo4(i32 %a, i32 %b) signext {
+entry:
+ %c = xor i32 %a, 131072
+ ret i32 %c
+}
+
+define i32 @foo5(i32 %a, i32 %b) zeroext {
+entry:
+ %c = xor i32 %a, 1
+ ret i32 %c
+}
+
+define i32 @foo6(i32 %a, i32 %b) signext {
+entry:
+ %c = xor i32 %a, 131072
+ ret i32 %c
+}
+
+define i32 @foo9(i32 %a, i32 %b) signext {
+entry:
+ %c = xor i32 %a, 123456
+ ret i32 %c
+}
+
diff --git a/test/CodeGen/SystemZ/03-RetXorSubreg.ll b/test/CodeGen/SystemZ/03-RetXorSubreg.ll
new file mode 100644
index 0000000..a9af231
--- /dev/null
+++ b/test/CodeGen/SystemZ/03-RetXorSubreg.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=systemz | grep xgr | count 3
+; RUN: llc < %s -march=systemz | grep nihf | count 1
+; RUN: llc < %s -march=systemz | grep lgfr | count 1
+
+
+define i32 @foo(i32 %a, i32 %b) {
+entry:
+ %c = xor i32 %a, %b
+ ret i32 %c
+}
+
+define i32 @foo1(i32 %a, i32 %b) zeroext {
+entry:
+ %c = xor i32 %a, %b
+ ret i32 %c
+}
+
+define i32 @foo2(i32 %a, i32 %b) signext {
+entry:
+ %c = xor i32 %a, %b
+ ret i32 %c
+}
+
diff --git a/test/CodeGen/SystemZ/04-RetShifts.ll b/test/CodeGen/SystemZ/04-RetShifts.ll
new file mode 100644
index 0000000..cccdc47
--- /dev/null
+++ b/test/CodeGen/SystemZ/04-RetShifts.ll
@@ -0,0 +1,121 @@
+; RUN: llc < %s -march=systemz | grep sra | count 6
+; RUN: llc < %s -march=systemz | grep srag | count 3
+; RUN: llc < %s -march=systemz | grep srl | count 6
+; RUN: llc < %s -march=systemz | grep srlg | count 3
+; RUN: llc < %s -march=systemz | grep sll | count 6
+; RUN: llc < %s -march=systemz | grep sllg | count 3
+
+define signext i32 @foo1(i32 %a, i32 %idx) nounwind readnone {
+entry:
+ %add = add i32 %idx, 1 ; <i32> [#uses=1]
+ %shr = ashr i32 %a, %add ; <i32> [#uses=1]
+ ret i32 %shr
+}
+
+define signext i32 @foo2(i32 %a, i32 %idx) nounwind readnone {
+entry:
+ %add = add i32 %idx, 1 ; <i32> [#uses=1]
+ %shr = shl i32 %a, %add ; <i32> [#uses=1]
+ ret i32 %shr
+}
+
+define signext i32 @foo3(i32 %a, i32 %idx) nounwind readnone {
+entry:
+ %add = add i32 %idx, 1 ; <i32> [#uses=1]
+ %shr = lshr i32 %a, %add ; <i32> [#uses=1]
+ ret i32 %shr
+}
+
+define signext i64 @foo4(i64 %a, i64 %idx) nounwind readnone {
+entry:
+ %add = add i64 %idx, 1 ; <i64> [#uses=1]
+ %shr = ashr i64 %a, %add ; <i64> [#uses=1]
+ ret i64 %shr
+}
+
+define signext i64 @foo5(i64 %a, i64 %idx) nounwind readnone {
+entry:
+ %add = add i64 %idx, 1 ; <i64> [#uses=1]
+ %shr = shl i64 %a, %add ; <i64> [#uses=1]
+ ret i64 %shr
+}
+
+define signext i64 @foo6(i64 %a, i64 %idx) nounwind readnone {
+entry:
+ %add = add i64 %idx, 1 ; <i64> [#uses=1]
+ %shr = lshr i64 %a, %add ; <i64> [#uses=1]
+ ret i64 %shr
+}
+
+define signext i32 @foo7(i32 %a, i32 %idx) nounwind readnone {
+entry:
+ %shr = ashr i32 %a, 1
+ ret i32 %shr
+}
+
+define signext i32 @foo8(i32 %a, i32 %idx) nounwind readnone {
+entry:
+ %shr = shl i32 %a, 1
+ ret i32 %shr
+}
+
+define signext i32 @foo9(i32 %a, i32 %idx) nounwind readnone {
+entry:
+ %shr = lshr i32 %a, 1
+ ret i32 %shr
+}
+
+define signext i32 @foo10(i32 %a, i32 %idx) nounwind readnone {
+entry:
+ %shr = ashr i32 %a, %idx
+ ret i32 %shr
+}
+
+define signext i32 @foo11(i32 %a, i32 %idx) nounwind readnone {
+entry:
+ %shr = shl i32 %a, %idx
+ ret i32 %shr
+}
+
+define signext i32 @foo12(i32 %a, i32 %idx) nounwind readnone {
+entry:
+ %shr = lshr i32 %a, %idx
+ ret i32 %shr
+}
+
+define signext i64 @foo13(i64 %a, i64 %idx) nounwind readnone {
+entry:
+ %shr = ashr i64 %a, 1
+ ret i64 %shr
+}
+
+define signext i64 @foo14(i64 %a, i64 %idx) nounwind readnone {
+entry:
+ %shr = shl i64 %a, 1
+ ret i64 %shr
+}
+
+define signext i64 @foo15(i64 %a, i64 %idx) nounwind readnone {
+entry:
+ %shr = lshr i64 %a, 1
+ ret i64 %shr
+}
+
+define signext i64 @foo16(i64 %a, i64 %idx) nounwind readnone {
+entry:
+ %shr = ashr i64 %a, %idx
+ ret i64 %shr
+}
+
+define signext i64 @foo17(i64 %a, i64 %idx) nounwind readnone {
+entry:
+ %shr = shl i64 %a, %idx
+ ret i64 %shr
+}
+
+define signext i64 @foo18(i64 %a, i64 %idx) nounwind readnone {
+entry:
+ %shr = lshr i64 %a, %idx
+ ret i64 %shr
+}
+
diff --git a/test/CodeGen/SystemZ/05-LoadAddr.ll b/test/CodeGen/SystemZ/05-LoadAddr.ll
new file mode 100644
index 0000000..cf02642
--- /dev/null
+++ b/test/CodeGen/SystemZ/05-LoadAddr.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s | grep lay | count 1
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define i64* @foo(i64* %a, i64 %idx) nounwind readnone {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i64* %a, i64 %add.ptr.sum ; <i64*> [#uses=1]
+ ret i64* %add.ptr2
+}
diff --git a/test/CodeGen/SystemZ/05-MemImmStores.ll b/test/CodeGen/SystemZ/05-MemImmStores.ll
new file mode 100644
index 0000000..3cf21cc
--- /dev/null
+++ b/test/CodeGen/SystemZ/05-MemImmStores.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -mattr=+z10 | grep mvghi | count 1
+; RUN: llc < %s -mattr=+z10 | grep mvhi | count 1
+; RUN: llc < %s -mattr=+z10 | grep mvhhi | count 1
+; RUN: llc < %s | grep mvi | count 2
+; RUN: llc < %s | grep mviy | count 1
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define void @foo1(i64* nocapture %a, i64 %idx) nounwind {
+entry:
+ %add.ptr = getelementptr i64* %a, i64 1 ; <i64*> [#uses=1]
+ store i64 1, i64* %add.ptr
+ ret void
+}
+
+define void @foo2(i32* nocapture %a, i64 %idx) nounwind {
+entry:
+ %add.ptr = getelementptr i32* %a, i64 1 ; <i32*> [#uses=1]
+ store i32 2, i32* %add.ptr
+ ret void
+}
+
+define void @foo3(i16* nocapture %a, i64 %idx) nounwind {
+entry:
+ %add.ptr = getelementptr i16* %a, i64 1 ; <i16*> [#uses=1]
+ store i16 3, i16* %add.ptr
+ ret void
+}
+
+define void @foo4(i8* nocapture %a, i64 %idx) nounwind {
+entry:
+ %add.ptr = getelementptr i8* %a, i64 1 ; <i8*> [#uses=1]
+ store i8 4, i8* %add.ptr
+ ret void
+}
+
+define void @foo5(i8* nocapture %a, i64 %idx) nounwind {
+entry:
+ %add.ptr = getelementptr i8* %a, i64 -1 ; <i8*> [#uses=1]
+ store i8 4, i8* %add.ptr
+ ret void
+}
+
+define void @foo6(i16* nocapture %a, i64 %idx) nounwind {
+entry:
+ %add.ptr = getelementptr i16* %a, i64 -1 ; <i16*> [#uses=1]
+ store i16 3, i16* %add.ptr
+ ret void
+}
diff --git a/test/CodeGen/SystemZ/05-MemLoadsStores.ll b/test/CodeGen/SystemZ/05-MemLoadsStores.ll
new file mode 100644
index 0000000..cf12063
--- /dev/null
+++ b/test/CodeGen/SystemZ/05-MemLoadsStores.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s | grep ly | count 2
+; RUN: llc < %s | grep sty | count 2
+; RUN: llc < %s | grep {l %} | count 2
+; RUN: llc < %s | grep {st %} | count 2
+
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
+target triple = "s390x-linux"
+
+define void @foo1(i32* nocapture %foo, i32* nocapture %bar) nounwind {
+entry:
+ %tmp1 = load i32* %foo ; <i32> [#uses=1]
+ store i32 %tmp1, i32* %bar
+ ret void
+}
+
+define void @foo2(i32* nocapture %foo, i32* nocapture %bar, i64 %idx) nounwind {
+entry:
+ %add.ptr = getelementptr i32* %foo, i64 1 ; <i32*> [#uses=1]
+ %tmp1 = load i32* %add.ptr ; <i32> [#uses=1]
+ %add.ptr3.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr5 = getelementptr i32* %bar, i64 %add.ptr3.sum ; <i32*> [#uses=1]
+ store i32 %tmp1, i32* %add.ptr5
+ ret void
+}
+
+define void @foo3(i32* nocapture %foo, i32* nocapture %bar, i64 %idx) nounwind {
+entry:
+ %sub.ptr = getelementptr i32* %foo, i64 -1 ; <i32*> [#uses=1]
+ %tmp1 = load i32* %sub.ptr ; <i32> [#uses=1]
+ %sub.ptr3.sum = add i64 %idx, -1 ; <i64> [#uses=1]
+ %add.ptr = getelementptr i32* %bar, i64 %sub.ptr3.sum ; <i32*> [#uses=1]
+ store i32 %tmp1, i32* %add.ptr
+ ret void
+}
+
+define void @foo4(i32* nocapture %foo, i32* nocapture %bar, i64 %idx) nounwind {
+entry:
+ %add.ptr = getelementptr i32* %foo, i64 8192 ; <i32*> [#uses=1]
+ %tmp1 = load i32* %add.ptr ; <i32> [#uses=1]
+ %add.ptr3.sum = add i64 %idx, 8192 ; <i64> [#uses=1]
+ %add.ptr5 = getelementptr i32* %bar, i64 %add.ptr3.sum ; <i32*> [#uses=1]
+ store i32 %tmp1, i32* %add.ptr5
+ ret void
+}
diff --git a/test/CodeGen/SystemZ/05-MemLoadsStores16.ll b/test/CodeGen/SystemZ/05-MemLoadsStores16.ll
new file mode 100644
index 0000000..1e6232a
--- /dev/null
+++ b/test/CodeGen/SystemZ/05-MemLoadsStores16.ll
@@ -0,0 +1,85 @@
+; RUN: llc < %s | grep {sthy.%} | count 2
+; RUN: llc < %s | grep {lhy.%} | count 2
+; RUN: llc < %s | grep {lh.%} | count 6
+; RUN: llc < %s | grep {sth.%} | count 2
+
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
+target triple = "s390x-linux"
+
+define void @foo1(i16* nocapture %foo, i16* nocapture %bar) nounwind {
+entry:
+ %tmp1 = load i16* %foo ; <i16> [#uses=1]
+ store i16 %tmp1, i16* %bar
+ ret void
+}
+
+define void @foo2(i16* nocapture %foo, i16* nocapture %bar, i64 %idx) nounwind {
+entry:
+ %add.ptr = getelementptr i16* %foo, i64 1 ; <i16*> [#uses=1]
+ %tmp1 = load i16* %add.ptr ; <i16> [#uses=1]
+ %add.ptr3.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr5 = getelementptr i16* %bar, i64 %add.ptr3.sum ; <i16*> [#uses=1]
+ store i16 %tmp1, i16* %add.ptr5
+ ret void
+}
+
+define void @foo3(i16* nocapture %foo, i16* nocapture %bar, i64 %idx) nounwind {
+entry:
+ %sub.ptr = getelementptr i16* %foo, i64 -1 ; <i16*> [#uses=1]
+ %tmp1 = load i16* %sub.ptr ; <i16> [#uses=1]
+ %sub.ptr3.sum = add i64 %idx, -1 ; <i64> [#uses=1]
+ %add.ptr = getelementptr i16* %bar, i64 %sub.ptr3.sum ; <i16*> [#uses=1]
+ store i16 %tmp1, i16* %add.ptr
+ ret void
+}
+
+define void @foo4(i16* nocapture %foo, i16* nocapture %bar, i64 %idx) nounwind {
+entry:
+ %add.ptr = getelementptr i16* %foo, i64 8192 ; <i16*> [#uses=1]
+ %tmp1 = load i16* %add.ptr ; <i16> [#uses=1]
+ %add.ptr3.sum = add i64 %idx, 8192 ; <i64> [#uses=1]
+ %add.ptr5 = getelementptr i16* %bar, i64 %add.ptr3.sum ; <i16*> [#uses=1]
+ store i16 %tmp1, i16* %add.ptr5
+ ret void
+}
+
+define void @foo5(i16* nocapture %foo, i32* nocapture %bar) nounwind {
+entry:
+ %tmp1 = load i16* %foo ; <i16> [#uses=1]
+ %conv = sext i16 %tmp1 to i32 ; <i32> [#uses=1]
+ store i32 %conv, i32* %bar
+ ret void
+}
+
+define void @foo6(i16* nocapture %foo, i32* nocapture %bar, i64 %idx) nounwind {
+entry:
+ %add.ptr = getelementptr i16* %foo, i64 1 ; <i16*> [#uses=1]
+ %tmp1 = load i16* %add.ptr ; <i16> [#uses=1]
+ %conv = sext i16 %tmp1 to i32 ; <i32> [#uses=1]
+ %add.ptr3.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr5 = getelementptr i32* %bar, i64 %add.ptr3.sum ; <i32*> [#uses=1]
+ store i32 %conv, i32* %add.ptr5
+ ret void
+}
+
+define void @foo7(i16* nocapture %foo, i32* nocapture %bar, i64 %idx) nounwind {
+entry:
+ %sub.ptr = getelementptr i16* %foo, i64 -1 ; <i16*> [#uses=1]
+ %tmp1 = load i16* %sub.ptr ; <i16> [#uses=1]
+ %conv = sext i16 %tmp1 to i32 ; <i32> [#uses=1]
+ %sub.ptr3.sum = add i64 %idx, -1 ; <i64> [#uses=1]
+ %add.ptr = getelementptr i32* %bar, i64 %sub.ptr3.sum ; <i32*> [#uses=1]
+ store i32 %conv, i32* %add.ptr
+ ret void
+}
+
+define void @foo8(i16* nocapture %foo, i32* nocapture %bar, i64 %idx) nounwind {
+entry:
+ %add.ptr = getelementptr i16* %foo, i64 8192 ; <i16*> [#uses=1]
+ %tmp1 = load i16* %add.ptr ; <i16> [#uses=1]
+ %conv = sext i16 %tmp1 to i32 ; <i32> [#uses=1]
+ %add.ptr3.sum = add i64 %idx, 8192 ; <i64> [#uses=1]
+ %add.ptr5 = getelementptr i32* %bar, i64 %add.ptr3.sum ; <i32*> [#uses=1]
+ store i32 %conv, i32* %add.ptr5
+ ret void
+}
diff --git a/test/CodeGen/SystemZ/05-MemRegLoads.ll b/test/CodeGen/SystemZ/05-MemRegLoads.ll
new file mode 100644
index 0000000..f690a48
--- /dev/null
+++ b/test/CodeGen/SystemZ/05-MemRegLoads.ll
@@ -0,0 +1,75 @@
+; RUN: llc < %s -march=systemz | not grep aghi
+; RUN: llc < %s -march=systemz | grep llgf | count 1
+; RUN: llc < %s -march=systemz | grep llgh | count 1
+; RUN: llc < %s -march=systemz | grep llgc | count 1
+; RUN: llc < %s -march=systemz | grep lgf | count 2
+; RUN: llc < %s -march=systemz | grep lgh | count 2
+; RUN: llc < %s -march=systemz | grep lgb | count 1
+
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define zeroext i64 @foo1(i64* nocapture %a, i64 %idx) nounwind readonly {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i64* %a, i64 %add.ptr.sum ; <i64*> [#uses=1]
+ %tmp3 = load i64* %add.ptr2 ; <i64> [#uses=1]
+ ret i64 %tmp3
+}
+
+define zeroext i32 @foo2(i32* nocapture %a, i64 %idx) nounwind readonly {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i32* %a, i64 %add.ptr.sum ; <i32*> [#uses=1]
+ %tmp3 = load i32* %add.ptr2 ; <i32> [#uses=1]
+ ret i32 %tmp3
+}
+
+define zeroext i16 @foo3(i16* nocapture %a, i64 %idx) nounwind readonly {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i16* %a, i64 %add.ptr.sum ; <i16*> [#uses=1]
+ %tmp3 = load i16* %add.ptr2 ; <i16> [#uses=1]
+ ret i16 %tmp3
+}
+
+define zeroext i8 @foo4(i8* nocapture %a, i64 %idx) nounwind readonly {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i8* %a, i64 %add.ptr.sum ; <i8*> [#uses=1]
+ %tmp3 = load i8* %add.ptr2 ; <i8> [#uses=1]
+ ret i8 %tmp3
+}
+
+define signext i64 @foo5(i64* nocapture %a, i64 %idx) nounwind readonly {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i64* %a, i64 %add.ptr.sum ; <i64*> [#uses=1]
+ %tmp3 = load i64* %add.ptr2 ; <i64> [#uses=1]
+ ret i64 %tmp3
+}
+
+define signext i32 @foo6(i32* nocapture %a, i64 %idx) nounwind readonly {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i32* %a, i64 %add.ptr.sum ; <i32*> [#uses=1]
+ %tmp3 = load i32* %add.ptr2 ; <i32> [#uses=1]
+ ret i32 %tmp3
+}
+
+define signext i16 @foo7(i16* nocapture %a, i64 %idx) nounwind readonly {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i16* %a, i64 %add.ptr.sum ; <i16*> [#uses=1]
+ %tmp3 = load i16* %add.ptr2 ; <i16> [#uses=1]
+ ret i16 %tmp3
+}
+
+define signext i8 @foo8(i8* nocapture %a, i64 %idx) nounwind readonly {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i8* %a, i64 %add.ptr.sum ; <i8*> [#uses=1]
+ %tmp3 = load i8* %add.ptr2 ; <i8> [#uses=1]
+ ret i8 %tmp3
+}
diff --git a/test/CodeGen/SystemZ/05-MemRegStores.ll b/test/CodeGen/SystemZ/05-MemRegStores.ll
new file mode 100644
index 0000000..b851c3f
--- /dev/null
+++ b/test/CodeGen/SystemZ/05-MemRegStores.ll
@@ -0,0 +1,79 @@
+; RUN: llc < %s | not grep aghi
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define void @foo1(i64* nocapture %a, i64 %idx, i64 %val) nounwind {
+entry:
+
+; CHECK: foo1:
+; CHECK: stg %r4, 8(%r1,%r2)
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i64* %a, i64 %add.ptr.sum ; <i64*> [#uses=1]
+ store i64 %val, i64* %add.ptr2
+ ret void
+}
+
+define void @foo2(i32* nocapture %a, i64 %idx, i32 %val) nounwind {
+entry:
+; CHECK: foo2:
+; CHECK: st %r4, 4(%r1,%r2)
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i32* %a, i64 %add.ptr.sum ; <i32*> [#uses=1]
+ store i32 %val, i32* %add.ptr2
+ ret void
+}
+
+define void @foo3(i16* nocapture %a, i64 %idx, i16 zeroext %val) nounwind {
+entry:
+; CHECK: foo3:
+; CHECK: sth %r4, 2(%r1,%r2)
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i16* %a, i64 %add.ptr.sum ; <i16*> [#uses=1]
+ store i16 %val, i16* %add.ptr2
+ ret void
+}
+
+define void @foo4(i8* nocapture %a, i64 %idx, i8 zeroext %val) nounwind {
+entry:
+; CHECK: foo4:
+; CHECK: stc %r4, 1(%r3,%r2)
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i8* %a, i64 %add.ptr.sum ; <i8*> [#uses=1]
+ store i8 %val, i8* %add.ptr2
+ ret void
+}
+
+define void @foo5(i8* nocapture %a, i64 %idx, i64 %val) nounwind {
+entry:
+; CHECK: foo5:
+; CHECK: stc %r4, 1(%r3,%r2)
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i8* %a, i64 %add.ptr.sum ; <i8*> [#uses=1]
+ %conv = trunc i64 %val to i8 ; <i8> [#uses=1]
+ store i8 %conv, i8* %add.ptr2
+ ret void
+}
+
+define void @foo6(i16* nocapture %a, i64 %idx, i64 %val) nounwind {
+entry:
+; CHECK: foo6:
+; CHECK: sth %r4, 2(%r1,%r2)
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i16* %a, i64 %add.ptr.sum ; <i16*> [#uses=1]
+ %conv = trunc i64 %val to i16 ; <i16> [#uses=1]
+ store i16 %conv, i16* %add.ptr2
+ ret void
+}
+
+define void @foo7(i32* nocapture %a, i64 %idx, i64 %val) nounwind {
+entry:
+; CHECK: foo7:
+; CHECK: st %r4, 4(%r1,%r2)
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i32* %a, i64 %add.ptr.sum ; <i32*> [#uses=1]
+ %conv = trunc i64 %val to i32 ; <i32> [#uses=1]
+ store i32 %conv, i32* %add.ptr2
+ ret void
+}
diff --git a/test/CodeGen/SystemZ/06-CallViaStack.ll b/test/CodeGen/SystemZ/06-CallViaStack.ll
new file mode 100644
index 0000000..e904f49
--- /dev/null
+++ b/test/CodeGen/SystemZ/06-CallViaStack.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s | grep 168 | count 1
+; RUN: llc < %s | grep 160 | count 3
+; RUN: llc < %s | grep 328 | count 1
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define i64 @foo(i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g) nounwind {
+entry:
+ %a = alloca i64, align 8 ; <i64*> [#uses=3]
+ store i64 %g, i64* %a
+ call void @bar(i64* %a) nounwind
+ %tmp1 = load i64* %a ; <i64> [#uses=1]
+ ret i64 %tmp1
+}
+
+declare void @bar(i64*)
diff --git a/test/CodeGen/SystemZ/06-FrameIdxLoad.ll b/test/CodeGen/SystemZ/06-FrameIdxLoad.ll
new file mode 100644
index 0000000..c71da9b
--- /dev/null
+++ b/test/CodeGen/SystemZ/06-FrameIdxLoad.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s | grep 160 | count 1
+; RUN: llc < %s | grep 168 | count 1
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define i64 @foo(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64* %g) nounwind readnone {
+entry:
+ ret i64 %f
+}
+
+define i64 @bar(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64* %g) nounwind readnone {
+entry:
+ %conv = ptrtoint i64* %g to i64 ; <i64> [#uses=1]
+ ret i64 %conv
+}
diff --git a/test/CodeGen/SystemZ/06-LocalFrame.ll b/test/CodeGen/SystemZ/06-LocalFrame.ll
new file mode 100644
index 0000000..d89b0df
--- /dev/null
+++ b/test/CodeGen/SystemZ/06-LocalFrame.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s | grep 160 | count 1
+; RUN: llc < %s | grep 328 | count 1
+; RUN: llc < %s | grep 168 | count 1
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define noalias i64* @foo(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f) nounwind readnone {
+entry:
+ %g = alloca i64, align 8 ; <i64*> [#uses=1]
+ %add.ptr = getelementptr i64* %g, i64 %f ; <i64*> [#uses=1]
+ ret i64* %add.ptr
+}
diff --git a/test/CodeGen/SystemZ/06-SimpleCall.ll b/test/CodeGen/SystemZ/06-SimpleCall.ll
new file mode 100644
index 0000000..fd4b502
--- /dev/null
+++ b/test/CodeGen/SystemZ/06-SimpleCall.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define void @foo() nounwind {
+entry:
+ tail call void @bar() nounwind
+ ret void
+}
+
+declare void @bar()
diff --git a/test/CodeGen/SystemZ/07-BrCond.ll b/test/CodeGen/SystemZ/07-BrCond.ll
new file mode 100644
index 0000000..8599717
--- /dev/null
+++ b/test/CodeGen/SystemZ/07-BrCond.ll
@@ -0,0 +1,141 @@
+; RUN: llc < %s | grep je | count 1
+; RUN: llc < %s | grep jne | count 1
+; RUN: llc < %s | grep jhe | count 2
+; RUN: llc < %s | grep jle | count 2
+; RUN: llc < %s | grep jh | count 4
+; RUN: llc < %s | grep jl | count 4
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define void @foo(i64 %a, i64 %b) nounwind {
+entry:
+ %cmp = icmp ult i64 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+declare void @bar()
+
+define void @foo1(i64 %a, i64 %b) nounwind {
+entry:
+ %cmp = icmp ugt i64 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo2(i64 %a, i64 %b) nounwind {
+entry:
+ %cmp = icmp ugt i64 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo3(i64 %a, i64 %b) nounwind {
+entry:
+ %cmp = icmp ult i64 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo4(i64 %a, i64 %b) nounwind {
+entry:
+ %cmp = icmp eq i64 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo5(i64 %a, i64 %b) nounwind {
+entry:
+ %cmp = icmp eq i64 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo6(i64 %a, i64 %b) nounwind {
+entry:
+ %cmp = icmp slt i64 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo7(i64 %a, i64 %b) nounwind {
+entry:
+ %cmp = icmp sgt i64 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo8(i64 %a, i64 %b) nounwind {
+entry:
+ %cmp = icmp sgt i64 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo9(i64 %a, i64 %b) nounwind {
+entry:
+ %cmp = icmp slt i64 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/SystemZ/07-BrCond32.ll b/test/CodeGen/SystemZ/07-BrCond32.ll
new file mode 100644
index 0000000..8ece5ac
--- /dev/null
+++ b/test/CodeGen/SystemZ/07-BrCond32.ll
@@ -0,0 +1,142 @@
+; RUN: llc < %s | grep je | count 1
+; RUN: llc < %s | grep jne | count 1
+; RUN: llc < %s | grep jhe | count 2
+; RUN: llc < %s | grep jle | count 2
+; RUN: llc < %s | grep jh | count 4
+; RUN: llc < %s | grep jl | count 4
+
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define void @foo(i32 %a, i32 %b) nounwind {
+entry:
+ %cmp = icmp ult i32 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+declare void @bar()
+
+define void @foo1(i32 %a, i32 %b) nounwind {
+entry:
+ %cmp = icmp ugt i32 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo2(i32 %a, i32 %b) nounwind {
+entry:
+ %cmp = icmp ugt i32 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo3(i32 %a, i32 %b) nounwind {
+entry:
+ %cmp = icmp ult i32 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo4(i32 %a, i32 %b) nounwind {
+entry:
+ %cmp = icmp eq i32 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo5(i32 %a, i32 %b) nounwind {
+entry:
+ %cmp = icmp eq i32 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo6(i32 %a, i32 %b) nounwind {
+entry:
+ %cmp = icmp slt i32 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo7(i32 %a, i32 %b) nounwind {
+entry:
+ %cmp = icmp sgt i32 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo8(i32 %a, i32 %b) nounwind {
+entry:
+ %cmp = icmp sgt i32 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo9(i32 %a, i32 %b) nounwind {
+entry:
+ %cmp = icmp slt i32 %a, %b ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/SystemZ/07-BrUnCond.ll b/test/CodeGen/SystemZ/07-BrUnCond.ll
new file mode 100644
index 0000000..e0bc302c
--- /dev/null
+++ b/test/CodeGen/SystemZ/07-BrUnCond.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-linux"
+
+define void @foo() noreturn nounwind {
+entry:
+ tail call void @baz() nounwind
+ br label %l1
+
+l1: ; preds = %entry, %l1
+ tail call void @bar() nounwind
+ br label %l1
+}
+
+declare void @bar()
+
+declare void @baz()
diff --git a/test/CodeGen/SystemZ/07-CmpImm.ll b/test/CodeGen/SystemZ/07-CmpImm.ll
new file mode 100644
index 0000000..4d0ebda
--- /dev/null
+++ b/test/CodeGen/SystemZ/07-CmpImm.ll
@@ -0,0 +1,137 @@
+; RUN: llc < %s | grep cgfi | count 8
+; RUN: llc < %s | grep clgfi | count 2
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define void @foo(i64 %a, i64 %b) nounwind {
+entry:
+ %cmp = icmp eq i64 %a, 0 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+declare void @bar()
+
+define void @foo1(i64 %a, i64 %b) nounwind {
+entry:
+ %cmp = icmp ugt i64 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo2(i64 %a, i64 %b) nounwind {
+entry:
+ %cmp = icmp ugt i64 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo3(i64 %a) nounwind {
+entry:
+ %cmp = icmp eq i64 %a, 0 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo4(i64 %a) nounwind {
+entry:
+ %cmp = icmp eq i64 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo5(i64 %a) nounwind {
+entry:
+ %cmp = icmp eq i64 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo6(i64 %a) nounwind {
+entry:
+ %cmp = icmp slt i64 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo7(i64 %a) nounwind {
+entry:
+ %cmp = icmp sgt i64 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo8(i64 %a) nounwind {
+entry:
+ %cmp = icmp sgt i64 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo9(i64 %a) nounwind {
+entry:
+ %cmp = icmp slt i64 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/SystemZ/07-CmpImm32.ll b/test/CodeGen/SystemZ/07-CmpImm32.ll
new file mode 100644
index 0000000..add34fa
--- /dev/null
+++ b/test/CodeGen/SystemZ/07-CmpImm32.ll
@@ -0,0 +1,139 @@
+; RUN: llc < %s | grep jl | count 3
+; RUN: llc < %s | grep jh | count 3
+; RUN: llc < %s | grep je | count 2
+; RUN: llc < %s | grep jne | count 2
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define void @foo(i32 %a, i32 %b) nounwind {
+entry:
+ %cmp = icmp eq i32 %a, 0 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+declare void @bar()
+
+define void @foo1(i32 %a, i32 %b) nounwind {
+entry:
+ %cmp = icmp ugt i32 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo2(i32 %a, i32 %b) nounwind {
+entry:
+ %cmp = icmp ugt i32 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo3(i32 %a) nounwind {
+entry:
+ %cmp = icmp eq i32 %a, 0 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo4(i32 %a) nounwind {
+entry:
+ %cmp = icmp eq i32 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo5(i32 %a) nounwind {
+entry:
+ %cmp = icmp eq i32 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo6(i32 %a) nounwind {
+entry:
+ %cmp = icmp slt i32 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo7(i32 %a) nounwind {
+entry:
+ %cmp = icmp sgt i32 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo8(i32 %a) nounwind {
+entry:
+ %cmp = icmp sgt i32 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
+
+define void @foo9(i32 %a) nounwind {
+entry:
+ %cmp = icmp slt i32 %a, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ ret void
+
+if.end: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/SystemZ/07-SelectCC.ll b/test/CodeGen/SystemZ/07-SelectCC.ll
new file mode 100644
index 0000000..aa4b36e
--- /dev/null
+++ b/test/CodeGen/SystemZ/07-SelectCC.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s | grep clgr
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define i64 @foo(i64 %a, i64 %b) nounwind readnone {
+entry:
+ %cmp = icmp ult i64 %a, %b ; <i1> [#uses=1]
+ %cond = select i1 %cmp, i64 %a, i64 %b ; <i64> [#uses=1]
+ ret i64 %cond
+}
diff --git a/test/CodeGen/SystemZ/08-DivRem.ll b/test/CodeGen/SystemZ/08-DivRem.ll
new file mode 100644
index 0000000..ff1e441
--- /dev/null
+++ b/test/CodeGen/SystemZ/08-DivRem.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s | grep dsgr | count 2
+; RUN: llc < %s | grep dsgfr | count 2
+; RUN: llc < %s | grep dlr | count 2
+; RUN: llc < %s | grep dlgr | count 2
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define i64 @div(i64 %a, i64 %b) nounwind readnone {
+entry:
+ %div = sdiv i64 %a, %b ; <i64> [#uses=1]
+ ret i64 %div
+}
+
+define i32 @div1(i32 %a, i32 %b) nounwind readnone {
+entry:
+ %div = sdiv i32 %a, %b ; <i32> [#uses=1]
+ ret i32 %div
+}
+
+define i64 @div2(i64 %a, i64 %b) nounwind readnone {
+entry:
+ %div = udiv i64 %a, %b ; <i64> [#uses=1]
+ ret i64 %div
+}
+
+define i32 @div3(i32 %a, i32 %b) nounwind readnone {
+entry:
+ %div = udiv i32 %a, %b ; <i32> [#uses=1]
+ ret i32 %div
+}
+
+define i64 @rem(i64 %a, i64 %b) nounwind readnone {
+entry:
+ %rem = srem i64 %a, %b ; <i64> [#uses=1]
+ ret i64 %rem
+}
+
+define i32 @rem1(i32 %a, i32 %b) nounwind readnone {
+entry:
+ %rem = srem i32 %a, %b ; <i32> [#uses=1]
+ ret i32 %rem
+}
+
+define i64 @rem2(i64 %a, i64 %b) nounwind readnone {
+entry:
+ %rem = urem i64 %a, %b ; <i64> [#uses=1]
+ ret i64 %rem
+}
+
+define i32 @rem3(i32 %a, i32 %b) nounwind readnone {
+entry:
+ %rem = urem i32 %a, %b ; <i32> [#uses=1]
+ ret i32 %rem
+}
diff --git a/test/CodeGen/SystemZ/08-DivRemMemOp.ll b/test/CodeGen/SystemZ/08-DivRemMemOp.ll
new file mode 100644
index 0000000..d6ec0e74
--- /dev/null
+++ b/test/CodeGen/SystemZ/08-DivRemMemOp.ll
@@ -0,0 +1,64 @@
+; RUN: llc < %s | grep {dsgf.%} | count 2
+; RUN: llc < %s | grep {dsg.%} | count 2
+; RUN: llc < %s | grep {dl.%} | count 2
+; RUN: llc < %s | grep dlg | count 2
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define i64 @div(i64 %a, i64* %b) nounwind readnone {
+entry:
+ %b1 = load i64* %b
+ %div = sdiv i64 %a, %b1
+ ret i64 %div
+}
+
+define i64 @div1(i64 %a, i64* %b) nounwind readnone {
+entry:
+ %b1 = load i64* %b
+ %div = udiv i64 %a, %b1
+ ret i64 %div
+}
+
+define i64 @rem(i64 %a, i64* %b) nounwind readnone {
+entry:
+ %b1 = load i64* %b
+ %div = srem i64 %a, %b1
+ ret i64 %div
+}
+
+define i64 @rem1(i64 %a, i64* %b) nounwind readnone {
+entry:
+ %b1 = load i64* %b
+ %div = urem i64 %a, %b1
+ ret i64 %div
+}
+
+define i32 @div2(i32 %a, i32* %b) nounwind readnone {
+entry:
+ %b1 = load i32* %b
+ %div = sdiv i32 %a, %b1
+ ret i32 %div
+}
+
+define i32 @div3(i32 %a, i32* %b) nounwind readnone {
+entry:
+ %b1 = load i32* %b
+ %div = udiv i32 %a, %b1
+ ret i32 %div
+}
+
+define i32 @rem2(i32 %a, i32* %b) nounwind readnone {
+entry:
+ %b1 = load i32* %b
+ %div = srem i32 %a, %b1
+ ret i32 %div
+}
+
+define i32 @rem3(i32 %a, i32* %b) nounwind readnone {
+entry:
+ %b1 = load i32* %b
+ %div = urem i32 %a, %b1
+ ret i32 %div
+}
+
diff --git a/test/CodeGen/SystemZ/08-SimpleMuls.ll b/test/CodeGen/SystemZ/08-SimpleMuls.ll
new file mode 100644
index 0000000..1ab88d6
--- /dev/null
+++ b/test/CodeGen/SystemZ/08-SimpleMuls.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s | grep msgr | count 2
+; RUN: llc < %s | grep msr | count 2
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define i64 @foo(i64 %a, i64 %b) nounwind readnone {
+entry:
+ %mul = mul i64 %b, %a ; <i64> [#uses=1]
+ ret i64 %mul
+}
+
+define i64 @foo2(i64 %a, i64 %b) nounwind readnone {
+entry:
+ %mul = mul i64 %b, %a ; <i64> [#uses=1]
+ ret i64 %mul
+}
+
+define i32 @foo3(i32 %a, i32 %b) nounwind readnone {
+entry:
+ %mul = mul i32 %b, %a ; <i32> [#uses=1]
+ ret i32 %mul
+}
+
+define i32 @foo4(i32 %a, i32 %b) nounwind readnone {
+entry:
+ %mul = mul i32 %b, %a ; <i32> [#uses=1]
+ ret i32 %mul
+}
diff --git a/test/CodeGen/SystemZ/09-DynamicAlloca.ll b/test/CodeGen/SystemZ/09-DynamicAlloca.ll
new file mode 100644
index 0000000..27189ab
--- /dev/null
+++ b/test/CodeGen/SystemZ/09-DynamicAlloca.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s
+
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
+target triple = "s390x-linux"
+
+define void @foo(i64 %N) nounwind {
+entry:
+ %N3 = trunc i64 %N to i32 ; <i32> [#uses=1]
+ %vla = alloca i8, i32 %N3, align 2 ; <i8*> [#uses=1]
+ call void @bar(i8* %vla) nounwind
+ ret void
+}
+
+declare void @bar(i8*)
diff --git a/test/CodeGen/SystemZ/09-Globals.ll b/test/CodeGen/SystemZ/09-Globals.ll
new file mode 100644
index 0000000..6e0c1ab
--- /dev/null
+++ b/test/CodeGen/SystemZ/09-Globals.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s | grep larl | count 3
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-linux"
+@bar = common global i64 0, align 8 ; <i64*> [#uses=3]
+
+define i64 @foo() nounwind readonly {
+entry:
+ %tmp = load i64* @bar ; <i64> [#uses=1]
+ ret i64 %tmp
+}
+
+define i64* @foo2() nounwind readnone {
+entry:
+ ret i64* @bar
+}
+
+define i64* @foo3(i64 %idx) nounwind readnone {
+entry:
+ %add.ptr.sum = add i64 %idx, 1 ; <i64> [#uses=1]
+ %add.ptr2 = getelementptr i64* @bar, i64 %add.ptr.sum ; <i64*> [#uses=1]
+ ret i64* %add.ptr2
+}
diff --git a/test/CodeGen/SystemZ/09-Switches.ll b/test/CodeGen/SystemZ/09-Switches.ll
new file mode 100644
index 0000000..32aaa62
--- /dev/null
+++ b/test/CodeGen/SystemZ/09-Switches.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s -march=systemz | grep larl
+
+define i32 @main(i32 %tmp158) {
+entry:
+ switch i32 %tmp158, label %bb336 [
+ i32 -2147483648, label %bb338
+ i32 -2147483647, label %bb338
+ i32 -2147483646, label %bb338
+ i32 120, label %bb338
+ i32 121, label %bb339
+ i32 122, label %bb340
+ i32 123, label %bb341
+ i32 124, label %bb342
+ i32 125, label %bb343
+ i32 126, label %bb336
+ i32 1024, label %bb338
+ i32 0, label %bb338
+ i32 1, label %bb338
+ i32 2, label %bb338
+ i32 3, label %bb338
+ i32 4, label %bb338
+ i32 5, label %bb338
+ ]
+bb336:
+ ret i32 10
+bb338:
+ ret i32 11
+bb339:
+ ret i32 12
+bb340:
+ ret i32 13
+bb341:
+ ret i32 14
+bb342:
+ ret i32 15
+bb343:
+ ret i32 18
+
+}
diff --git a/test/CodeGen/SystemZ/10-FuncsPic.ll b/test/CodeGen/SystemZ/10-FuncsPic.ll
new file mode 100644
index 0000000..cc32538
--- /dev/null
+++ b/test/CodeGen/SystemZ/10-FuncsPic.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -relocation-model=pic | grep GOTENT | count 3
+; RUN: llc < %s -relocation-model=pic | grep PLT | count 1
+
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
+target triple = "s390x-linux"
+@ptr = external global void (...)* ; <void (...)**> [#uses=2]
+
+define void @foo1() nounwind {
+entry:
+ store void (...)* @func, void (...)** @ptr
+ ret void
+}
+
+declare void @func(...)
+
+define void @foo2() nounwind {
+entry:
+ tail call void (...)* @func() nounwind
+ ret void
+}
+
+define void @foo3() nounwind {
+entry:
+ %tmp = load void (...)** @ptr ; <void (...)*> [#uses=1]
+ tail call void (...)* %tmp() nounwind
+ ret void
+}
diff --git a/test/CodeGen/SystemZ/10-GlobalsPic.ll b/test/CodeGen/SystemZ/10-GlobalsPic.ll
new file mode 100644
index 0000000..a77671e
--- /dev/null
+++ b/test/CodeGen/SystemZ/10-GlobalsPic.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -relocation-model=pic | grep GOTENT | count 6
+
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
+target triple = "s390x-linux"
+@src = external global i32 ; <i32*> [#uses=2]
+@dst = external global i32 ; <i32*> [#uses=2]
+@ptr = external global i32* ; <i32**> [#uses=2]
+
+define void @foo1() nounwind {
+entry:
+ %tmp = load i32* @src ; <i32> [#uses=1]
+ store i32 %tmp, i32* @dst
+ ret void
+}
+
+define void @foo2() nounwind {
+entry:
+ store i32* @dst, i32** @ptr
+ ret void
+}
+
+define void @foo3() nounwind {
+entry:
+ %tmp = load i32* @src ; <i32> [#uses=1]
+ %tmp1 = load i32** @ptr ; <i32*> [#uses=1]
+ %arrayidx = getelementptr i32* %tmp1, i64 1 ; <i32*> [#uses=1]
+ store i32 %tmp, i32* %arrayidx
+ ret void
+}
diff --git a/test/CodeGen/SystemZ/11-BSwap.ll b/test/CodeGen/SystemZ/11-BSwap.ll
new file mode 100644
index 0000000..609d9dc
--- /dev/null
+++ b/test/CodeGen/SystemZ/11-BSwap.ll
@@ -0,0 +1,74 @@
+; RUN: llc < %s | FileCheck %s
+
+
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
+target triple = "s390x-linux"
+
+
+define i16 @foo(i16 zeroext %a) zeroext {
+ %res = tail call i16 @llvm.bswap.i16(i16 %a)
+ ret i16 %res
+}
+
+define i32 @foo2(i32 zeroext %a) zeroext {
+; CHECK: foo2:
+; CHECK: lrvr %r1, %r2
+ %res = tail call i32 @llvm.bswap.i32(i32 %a)
+ ret i32 %res
+}
+
+define i64 @foo3(i64 %a) zeroext {
+; CHECK: foo3:
+; CHECK: lrvgr %r2, %r2
+ %res = tail call i64 @llvm.bswap.i64(i64 %a)
+ ret i64 %res
+}
+
+define i16 @foo4(i16* %b) zeroext {
+ %a = load i16* %b
+ %res = tail call i16 @llvm.bswap.i16(i16 %a)
+ ret i16 %res
+}
+
+define i32 @foo5(i32* %b) zeroext {
+; CHECK: foo5:
+; CHECK: lrv %r1, 0(%r2)
+ %a = load i32* %b
+ %res = tail call i32 @llvm.bswap.i32(i32 %a)
+ ret i32 %res
+}
+
+define i64 @foo6(i64* %b) {
+; CHECK: foo6:
+; CHECK: lrvg %r2, 0(%r2)
+ %a = load i64* %b
+ %res = tail call i64 @llvm.bswap.i64(i64 %a)
+ ret i64 %res
+}
+
+define void @foo7(i16 %a, i16* %b) {
+ %res = tail call i16 @llvm.bswap.i16(i16 %a)
+ store i16 %res, i16* %b
+ ret void
+}
+
+define void @foo8(i32 %a, i32* %b) {
+; CHECK: foo8:
+; CHECK: strv %r2, 0(%r3)
+ %res = tail call i32 @llvm.bswap.i32(i32 %a)
+ store i32 %res, i32* %b
+ ret void
+}
+
+define void @foo9(i64 %a, i64* %b) {
+; CHECK: foo9:
+; CHECK: strvg %r2, 0(%r3)
+ %res = tail call i64 @llvm.bswap.i64(i64 %a)
+ store i64 %res, i64* %b
+ ret void
+}
+
+declare i16 @llvm.bswap.i16(i16) nounwind readnone
+declare i32 @llvm.bswap.i32(i32) nounwind readnone
+declare i64 @llvm.bswap.i64(i64) nounwind readnone
+
diff --git a/test/CodeGen/SystemZ/2009-05-29-InvalidRetResult.ll b/test/CodeGen/SystemZ/2009-05-29-InvalidRetResult.ll
new file mode 100644
index 0000000..65f8e14
--- /dev/null
+++ b/test/CodeGen/SystemZ/2009-05-29-InvalidRetResult.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-unknown-linux-gnu"
+
+define i32 @main() nounwind {
+entry:
+ %call = call i32 (...)* @random() nounwind ; <i32> [#uses=0]
+ unreachable
+}
+
+declare i32 @random(...)
diff --git a/test/CodeGen/SystemZ/2009-06-02-And32Imm.ll b/test/CodeGen/SystemZ/2009-06-02-And32Imm.ll
new file mode 100644
index 0000000..3cfa97d
--- /dev/null
+++ b/test/CodeGen/SystemZ/2009-06-02-And32Imm.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=systemz | grep nilf | count 1
+; RUN: llc < %s -march=systemz | grep nill | count 1
+
+define i32 @gnu_dev_major(i64 %__dev) nounwind readnone {
+entry:
+ %shr = lshr i64 %__dev, 8 ; <i64> [#uses=1]
+ %shr8 = trunc i64 %shr to i32 ; <i32> [#uses=1]
+ %shr2 = lshr i64 %__dev, 32 ; <i64> [#uses=1]
+ %conv = trunc i64 %shr2 to i32 ; <i32> [#uses=1]
+ %and3 = and i32 %conv, -4096 ; <i32> [#uses=1]
+ %and6 = and i32 %shr8, 4095 ; <i32> [#uses=1]
+ %conv5 = or i32 %and6, %and3 ; <i32> [#uses=1]
+ ret i32 %conv5
+}
diff --git a/test/CodeGen/SystemZ/2009-06-02-Rotate.ll b/test/CodeGen/SystemZ/2009-06-02-Rotate.ll
new file mode 100644
index 0000000..07a164d
--- /dev/null
+++ b/test/CodeGen/SystemZ/2009-06-02-Rotate.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=systemz | grep rll
+
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
+target triple = "s390x-linux"
+
+define i32 @rotl(i32 %x, i32 %y, i32 %z) nounwind readnone {
+entry:
+ %shl = shl i32 %x, 1 ; <i32> [#uses=1]
+ %sub = sub i32 32, 1 ; <i32> [#uses=1]
+ %shr = lshr i32 %x, %sub ; <i32> [#uses=1]
+ %or = or i32 %shr, %shl ; <i32> [#uses=1]
+ ret i32 %or
+}
diff --git a/test/CodeGen/SystemZ/2009-06-05-InvalidArgLoad.ll b/test/CodeGen/SystemZ/2009-06-05-InvalidArgLoad.ll
new file mode 100644
index 0000000..5f6ec50
--- /dev/null
+++ b/test/CodeGen/SystemZ/2009-06-05-InvalidArgLoad.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
+target triple = "s390x-ibm-linux"
+ %struct.re_pattern_buffer = type <{ i8*, i64, i64, i64, i8*, i8*, i64, i8, i8, i8, i8, i8, i8, i8, i8 }>
+ %struct.re_registers = type <{ i32, i8, i8, i8, i8, i32*, i32* }>
+
+define i32 @xre_search_2(%struct.re_pattern_buffer* nocapture %bufp, i8* %string1, i32 %size1, i8* %string2, i32 %size2, i32 %startpos, i32 %range, %struct.re_registers* %regs, i32 %stop) nounwind {
+entry:
+ %cmp17.i = icmp slt i32 undef, %startpos ; <i1> [#uses=1]
+ %or.cond.i = or i1 undef, %cmp17.i ; <i1> [#uses=1]
+ br i1 %or.cond.i, label %byte_re_search_2.exit, label %if.then20.i
+
+if.then20.i: ; preds = %entry
+ ret i32 -2
+
+byte_re_search_2.exit: ; preds = %entry
+ ret i32 -1
+}
diff --git a/test/CodeGen/SystemZ/2009-07-04-Shl32.ll b/test/CodeGen/SystemZ/2009-07-04-Shl32.ll
new file mode 100644
index 0000000..99d0ee7
--- /dev/null
+++ b/test/CodeGen/SystemZ/2009-07-04-Shl32.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s
+
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
+target triple = "s390x-linux"
+
+define void @compdecomp(i8* nocapture %data, i64 %data_len) nounwind {
+entry:
+ br label %for.body38
+
+for.body38: ; preds = %for.body38, %entry
+ br i1 undef, label %for.cond220, label %for.body38
+
+for.cond220: ; preds = %for.cond220, %for.body38
+ br i1 false, label %for.cond220, label %for.end297
+
+for.end297: ; preds = %for.cond220
+ %tmp334 = load i8* undef ; <i8> [#uses=1]
+ %conv343 = zext i8 %tmp334 to i32 ; <i32> [#uses=1]
+ %sub344 = add i32 %conv343, -1 ; <i32> [#uses=1]
+ %shl345 = shl i32 1, %sub344 ; <i32> [#uses=1]
+ %conv346 = sext i32 %shl345 to i64 ; <i64> [#uses=1]
+ br label %for.body356
+
+for.body356: ; preds = %for.body356, %for.end297
+ %mask.1633 = phi i64 [ %conv346, %for.end297 ], [ undef, %for.body356 ] ; <i64> [#uses=0]
+ br label %for.body356
+}
diff --git a/test/CodeGen/SystemZ/2009-07-05-Shifts.ll b/test/CodeGen/SystemZ/2009-07-05-Shifts.ll
new file mode 100644
index 0000000..a35167f
--- /dev/null
+++ b/test/CodeGen/SystemZ/2009-07-05-Shifts.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s
+
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
+target triple = "s390x-linux"
+
+define signext i32 @bit_place_piece(i32 signext %col, i32 signext %player, i64* nocapture %b1, i64* nocapture %b2) nounwind {
+entry:
+ br i1 undef, label %for.body, label %return
+
+for.body: ; preds = %entry
+ %add = add i32 0, %col ; <i32> [#uses=1]
+ %sh_prom = zext i32 %add to i64 ; <i64> [#uses=1]
+ %shl = shl i64 1, %sh_prom ; <i64> [#uses=1]
+ br i1 undef, label %if.then13, label %if.else
+
+if.then13: ; preds = %for.body
+ ret i32 0
+
+if.else: ; preds = %for.body
+ %or34 = or i64 undef, %shl ; <i64> [#uses=0]
+ ret i32 0
+
+return: ; preds = %entry
+ ret i32 1
+}
diff --git a/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll b/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll
new file mode 100644
index 0000000..6a76a8e
--- /dev/null
+++ b/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s | grep 168
+
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
+target triple = "s390x-linux"
+
+declare void @rdft(i32 signext, i32 signext, double*, i32* nocapture, double*) nounwind
+
+declare double @mp_mul_d2i_test(i32 signext, i32 signext, double* nocapture) nounwind
+
+define void @mp_mul_radix_test_bb3(i32 %radix, i32 %nfft, double* %tmpfft, i32* %ip, double* %w, double* %arrayidx44.reload, double* %call.out) nounwind {
+newFuncRoot:
+ br label %bb3
+
+bb4.exitStub: ; preds = %bb3
+ store double %call, double* %call.out
+ ret void
+
+bb3: ; preds = %newFuncRoot
+ tail call void @rdft(i32 signext %nfft, i32 signext -1, double* %arrayidx44.reload, i32* %ip, double* %w) nounwind
+ %call = tail call double @mp_mul_d2i_test(i32 signext %radix, i32 signext %nfft, double* %tmpfft) ; <double> [#uses=1]
+ br label %bb4.exitStub
+}
diff --git a/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll b/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll
new file mode 100644
index 0000000..564d343
--- /dev/null
+++ b/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s
+
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
+target triple = "s390x-linux"
+
+define float @foo(i32 signext %a) {
+entry:
+ %b = bitcast i32 %a to float
+ ret float %b
+}
+
+define i32 @bar(float %a) {
+entry:
+ %b = bitcast float %a to i32
+ ret i32 %b
+}
\ No newline at end of file
diff --git a/test/CodeGen/SystemZ/2009-07-11-InvalidRIISel.ll b/test/CodeGen/SystemZ/2009-07-11-InvalidRIISel.ll
new file mode 100644
index 0000000..a91e29e
--- /dev/null
+++ b/test/CodeGen/SystemZ/2009-07-11-InvalidRIISel.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s
+
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
+target triple = "s390x-linux"
+
+define signext i32 @dfg_parse() nounwind {
+entry:
+ br i1 undef, label %if.then2208, label %if.else2360
+
+if.then2208: ; preds = %entry
+ br i1 undef, label %bb.nph3189, label %for.end2270
+
+bb.nph3189: ; preds = %if.then2208
+ unreachable
+
+for.end2270: ; preds = %if.then2208
+ %call2279 = call i64 @strlen(i8* undef) nounwind ; <i64> [#uses=1]
+ %add2281 = add i64 0, %call2279 ; <i64> [#uses=1]
+ %tmp2283 = trunc i64 %add2281 to i32 ; <i32> [#uses=1]
+ %tmp2284 = alloca i8, i32 %tmp2283, align 2 ; <i8*> [#uses=1]
+ %yyd.0.i2561.13 = getelementptr i8* %tmp2284, i64 13 ; <i8*> [#uses=1]
+ store i8 117, i8* %yyd.0.i2561.13
+ br label %while.cond.i2558
+
+while.cond.i2558: ; preds = %while.cond.i2558, %for.end2270
+ br label %while.cond.i2558
+
+if.else2360: ; preds = %entry
+ unreachable
+}
+
+declare i64 @strlen(i8* nocapture) nounwind readonly
diff --git a/test/CodeGen/SystemZ/2009-08-21-InlineAsmRConstraint.ll b/test/CodeGen/SystemZ/2009-08-21-InlineAsmRConstraint.ll
new file mode 100644
index 0000000..f7686f1
--- /dev/null
+++ b/test/CodeGen/SystemZ/2009-08-21-InlineAsmRConstraint.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:16:16-f128:128:128"
+target triple = "s390x-ibm-linux-gnu"
+
+@__JCR_LIST__ = internal global [0 x i8*] zeroinitializer, section ".jcr", align 8 ; <[0 x i8*]*> [#uses=1]
+
+define internal void @frame_dummy() nounwind {
+entry:
+ %asmtmp = tail call void (i8*)* (void (i8*)*)* asm "", "=r,0"(void (i8*)* @_Jv_RegisterClasses) nounwind ; <void (i8*)*> [#uses=2]
+ %0 = icmp eq void (i8*)* %asmtmp, null ; <i1> [#uses=1]
+ br i1 %0, label %return, label %bb3
+
+bb3: ; preds = %entry
+ tail call void %asmtmp(i8* bitcast ([0 x i8*]* @__JCR_LIST__ to i8*)) nounwind
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
+
+declare extern_weak void @_Jv_RegisterClasses(i8*)
diff --git a/test/CodeGen/SystemZ/2009-08-22-FCopySign.ll b/test/CodeGen/SystemZ/2009-08-22-FCopySign.ll
new file mode 100644
index 0000000..fde7d9d
--- /dev/null
+++ b/test/CodeGen/SystemZ/2009-08-22-FCopySign.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:16:16-f128:128:128"
+target triple = "s390x-ibm-linux-gnu"
+
+define double @foo(double %a, double %b) nounwind {
+entry:
+; CHECK: cpsdr %f0, %f2, %f0
+ %0 = tail call double @copysign(double %a, double %b) nounwind readnone
+ ret double %0
+}
+
+define float @bar(float %a, float %b) nounwind {
+entry:
+; CHECK: cpsdr %f0, %f2, %f0
+ %0 = tail call float @copysignf(float %a, float %b) nounwind readnone
+ ret float %0
+}
+
+
+declare double @copysign(double, double) nounwind readnone
+declare float @copysignf(float, float) nounwind readnone
diff --git a/test/CodeGen/SystemZ/2010-01-04-DivMem.ll b/test/CodeGen/SystemZ/2010-01-04-DivMem.ll
new file mode 100644
index 0000000..d730bec
--- /dev/null
+++ b/test/CodeGen/SystemZ/2010-01-04-DivMem.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16-n32:64"
+target triple = "s390x-elf"
+
+@REGISTER = external global [10 x i32] ; <[10 x i32]*> [#uses=2]
+
+define void @DIVR_P(i32 signext %PRINT_EFFECT) nounwind {
+entry:
+ %REG1 = alloca i32, align 4 ; <i32*> [#uses=2]
+ %REG2 = alloca i32, align 4 ; <i32*> [#uses=2]
+ %call = call signext i32 (...)* @FORMAT2(i32* %REG1, i32* %REG2) nounwind ; <i32> [#uses=0]
+ %tmp = load i32* %REG1 ; <i32> [#uses=1]
+ %idxprom = sext i32 %tmp to i64 ; <i64> [#uses=1]
+ %arrayidx = getelementptr inbounds [10 x i32]* @REGISTER, i64 0, i64 %idxprom ; <i32*> [#uses=2]
+ %tmp1 = load i32* %arrayidx ; <i32> [#uses=2]
+ %tmp2 = load i32* %REG2 ; <i32> [#uses=1]
+ %idxprom3 = sext i32 %tmp2 to i64 ; <i64> [#uses=1]
+ %arrayidx4 = getelementptr inbounds [10 x i32]* @REGISTER, i64 0, i64 %idxprom3 ; <i32*> [#uses=3]
+ %tmp5 = load i32* %arrayidx4 ; <i32> [#uses=3]
+ %cmp6 = icmp sgt i32 %tmp5, 8388607 ; <i1> [#uses=1]
+ %REG2_SIGN.0 = select i1 %cmp6, i32 -1, i32 1 ; <i32> [#uses=2]
+ %cmp10 = icmp eq i32 %REG2_SIGN.0, 1 ; <i1> [#uses=1]
+ %not.cmp = icmp slt i32 %tmp1, 8388608 ; <i1> [#uses=2]
+ %or.cond = and i1 %cmp10, %not.cmp ; <i1> [#uses=1]
+ br i1 %or.cond, label %if.then13, label %if.end25
+
+if.then13: ; preds = %entry
+ %div = sdiv i32 %tmp5, %tmp1 ; <i32> [#uses=2]
+ store i32 %div, i32* %arrayidx4
+ br label %if.end25
+
+if.end25: ; preds = %if.then13, %entry
+ %tmp35 = phi i32 [ %div, %if.then13 ], [ %tmp5, %entry ] ; <i32> [#uses=1]
+ %cmp27 = icmp eq i32 %REG2_SIGN.0, -1 ; <i1> [#uses=1]
+ %or.cond46 = and i1 %cmp27, %not.cmp ; <i1> [#uses=1]
+ br i1 %or.cond46, label %if.then31, label %if.end45
+
+if.then31: ; preds = %if.end25
+ %sub = sub i32 16777216, %tmp35 ; <i32> [#uses=1]
+ %tmp39 = load i32* %arrayidx ; <i32> [#uses=1]
+ %div40 = udiv i32 %sub, %tmp39 ; <i32> [#uses=1]
+ %sub41 = sub i32 16777216, %div40 ; <i32> [#uses=1]
+ store i32 %sub41, i32* %arrayidx4
+ ret void
+
+if.end45: ; preds = %if.end25
+ ret void
+}
+
+declare signext i32 @FORMAT2(...)
diff --git a/test/CodeGen/SystemZ/dg.exp b/test/CodeGen/SystemZ/dg.exp
new file mode 100644
index 0000000..e9624ba
--- /dev/null
+++ b/test/CodeGen/SystemZ/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target SystemZ] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/Thumb/2007-01-31-RegInfoAssert.ll b/test/CodeGen/Thumb/2007-01-31-RegInfoAssert.ll
new file mode 100644
index 0000000..1e61b23
--- /dev/null
+++ b/test/CodeGen/Thumb/2007-01-31-RegInfoAssert.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=thumb-apple-darwin
+
+%struct.rtx_def = type { i8 }
+@str = external global [7 x i8]
+
+define void @f1() {
+ %D = alloca %struct.rtx_def, align 1
+ %tmp1 = bitcast %struct.rtx_def* %D to i32*
+ %tmp7 = load i32* %tmp1
+ %tmp14 = lshr i32 %tmp7, 1
+ %tmp1415 = and i32 %tmp14, 1
+ call void (i32, ...)* @printf( i32 undef, i32 0, i32 %tmp1415 )
+ ret void
+}
+
+declare void @printf(i32, ...)
diff --git a/test/CodeGen/Thumb/2007-02-02-JoinIntervalsCrash.ll b/test/CodeGen/Thumb/2007-02-02-JoinIntervalsCrash.ll
new file mode 100644
index 0000000..be2b839
--- /dev/null
+++ b/test/CodeGen/Thumb/2007-02-02-JoinIntervalsCrash.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -mtriple=thumb-apple-darwin
+
+ %struct.color_sample = type { i32 }
+ %struct.ref = type { %struct.color_sample, i16, i16 }
+
+define void @zcvrs() {
+ br i1 false, label %bb22, label %UnifiedReturnBlock
+
+bb22:
+ br i1 false, label %bb64, label %UnifiedReturnBlock
+
+bb64:
+ %tmp67 = urem i32 0, 0
+ %tmp69 = icmp slt i32 %tmp67, 10
+ %iftmp.13.0 = select i1 %tmp69, i8 48, i8 55
+ %tmp75 = add i8 %iftmp.13.0, 0
+ store i8 %tmp75, i8* null
+ %tmp81 = udiv i32 0, 0
+ %tmp83 = icmp eq i32 %tmp81, 0
+ br i1 %tmp83, label %bb85, label %bb64
+
+bb85:
+ ret void
+
+UnifiedReturnBlock:
+ ret void
+}
diff --git a/test/CodeGen/Thumb/2007-03-06-AddR7.ll b/test/CodeGen/Thumb/2007-03-06-AddR7.ll
new file mode 100644
index 0000000..8d139e9
--- /dev/null
+++ b/test/CodeGen/Thumb/2007-03-06-AddR7.ll
@@ -0,0 +1,117 @@
+; RUN: llc < %s -march=thumb
+; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=pic \
+; RUN: -mattr=+v6,+vfp2 | not grep {add r., r7, #2 \\* 4}
+
+ %struct.__fooAllocator = type opaque
+ %struct.__fooY = type { %struct.fooXBase, %struct.__fooString*, %struct.__fooU*, %struct.__fooV*, i8** }
+ %struct.__fooZ = type opaque
+ %struct.__fooU = type opaque
+ %struct.__fooString = type opaque
+ %struct.__fooV = type opaque
+ %struct.fooXBase = type { i32, [4 x i8] }
+ %struct.fooXClass = type { i32, i8*, void (i8*)*, i8* (%struct.__fooAllocator*, i8*)*, void (i8*)*, i8 (i8*, i8*) zeroext *, i32 (i8*)*, %struct.__fooString* (i8*, %struct.__fooZ*)*, %struct.__fooString* (i8*)* }
+ %struct.aa_cache = type { i32, i32, [1 x %struct.aa_method*] }
+ %struct.aa_class = type { %struct.aa_class*, %struct.aa_class*, i8*, i32, i32, i32, %struct.aa_ivar_list*, %struct.aa_method_list**, %struct.aa_cache*, %struct.aa_protocol_list* }
+ %struct.aa_ivar = type { i8*, i8*, i32 }
+ %struct.aa_ivar_list = type { i32, [1 x %struct.aa_ivar] }
+ %struct.aa_method = type { %struct.aa_ss*, i8*, %struct.aa_object* (%struct.aa_object*, %struct.aa_ss*, ...)* }
+ %struct.aa_method_list = type { %struct.aa_method_list*, i32, [1 x %struct.aa_method] }
+ %struct.aa_object = type { %struct.aa_class* }
+ %struct.aa_protocol_list = type { %struct.aa_protocol_list*, i32, [1 x %struct.aa_object*] }
+ %struct.aa_ss = type opaque
+@__kfooYTypeID = external global i32 ; <i32*> [#uses=3]
+@__fooYClass = external constant %struct.fooXClass ; <%struct.fooXClass*> [#uses=1]
+@__fooXClassTableSize = external global i32 ; <i32*> [#uses=1]
+@__fooXAaClassTable = external global i32* ; <i32**> [#uses=1]
[email protected] = external global %struct.aa_ss* ; <%struct.aa_ss**> [#uses=2]
+@str15 = external constant [24 x i8] ; <[24 x i8]*> [#uses=1]
+
+
+define i8 @test(%struct.__fooY* %calendar, double* %atp, i8* %componentDesc, ...) zeroext {
+entry:
+ %args = alloca i8*, align 4 ; <i8**> [#uses=5]
+ %args4 = bitcast i8** %args to i8* ; <i8*> [#uses=2]
+ call void @llvm.va_start( i8* %args4 )
+ %tmp6 = load i32* @__kfooYTypeID ; <i32> [#uses=1]
+ icmp eq i32 %tmp6, 0 ; <i1>:0 [#uses=1]
+ br i1 %0, label %cond_true, label %cond_next
+
+cond_true: ; preds = %entry
+ %tmp7 = call i32 @_fooXRegisterClass( %struct.fooXClass* @__fooYClass ) ; <i32> [#uses=1]
+ store i32 %tmp7, i32* @__kfooYTypeID
+ br label %cond_next
+
+cond_next: ; preds = %cond_true, %entry
+ %tmp8 = load i32* @__kfooYTypeID ; <i32> [#uses=2]
+ %tmp15 = load i32* @__fooXClassTableSize ; <i32> [#uses=1]
+ icmp ugt i32 %tmp15, %tmp8 ; <i1>:1 [#uses=1]
+ br i1 %1, label %cond_next18, label %cond_true58
+
+cond_next18: ; preds = %cond_next
+ %tmp21 = getelementptr %struct.__fooY* %calendar, i32 0, i32 0, i32 0 ; <i32*> [#uses=1]
+ %tmp22 = load i32* %tmp21 ; <i32> [#uses=2]
+ %tmp29 = load i32** @__fooXAaClassTable ; <i32*> [#uses=1]
+ %tmp31 = getelementptr i32* %tmp29, i32 %tmp8 ; <i32*> [#uses=1]
+ %tmp32 = load i32* %tmp31 ; <i32> [#uses=1]
+ icmp eq i32 %tmp22, %tmp32 ; <i1>:2 [#uses=1]
+ %.not = xor i1 %2, true ; <i1> [#uses=1]
+ icmp ugt i32 %tmp22, 4095 ; <i1>:3 [#uses=1]
+ %bothcond = and i1 %.not, %3 ; <i1> [#uses=1]
+ br i1 %bothcond, label %cond_true58, label %bb48
+
+bb48: ; preds = %cond_next18
+ %tmp78 = call i32 @strlen( i8* %componentDesc ) ; <i32> [#uses=4]
+ %tmp92 = alloca i32, i32 %tmp78 ; <i32*> [#uses=2]
+ icmp sgt i32 %tmp78, 0 ; <i1>:4 [#uses=1]
+ br i1 %4, label %cond_true111, label %bb114
+
+cond_true58: ; preds = %cond_next18, %cond_next
+ %tmp59 = load %struct.aa_ss** @s.10319 ; <%struct.aa_ss*> [#uses=2]
+ icmp eq %struct.aa_ss* %tmp59, null ; <i1>:5 [#uses=1]
+ %tmp6869 = bitcast %struct.__fooY* %calendar to i8* ; <i8*> [#uses=2]
+ br i1 %5, label %cond_true60, label %cond_next64
+
+cond_true60: ; preds = %cond_true58
+ %tmp63 = call %struct.aa_ss* @sel_registerName( i8* getelementptr ([24 x i8]* @str15, i32 0, i32 0) ) ; <%struct.aa_ss*> [#uses=2]
+ store %struct.aa_ss* %tmp63, %struct.aa_ss** @s.10319
+ %tmp66137 = volatile load i8** %args ; <i8*> [#uses=1]
+ %tmp73138 = call i8 (i8*, %struct.aa_ss*, ...) zeroext * bitcast (%struct.aa_object* (%struct.aa_object*, %struct.aa_ss*, ...)* @aa_mm to i8 (i8*, %struct.aa_ss*, ...) zeroext *)( i8* %tmp6869, %struct.aa_ss* %tmp63, double* %atp, i8* %componentDesc, i8* %tmp66137) zeroext ; <i8> [#uses=1]
+ ret i8 %tmp73138
+
+cond_next64: ; preds = %cond_true58
+ %tmp66 = volatile load i8** %args ; <i8*> [#uses=1]
+ %tmp73 = call i8 (i8*, %struct.aa_ss*, ...) zeroext * bitcast (%struct.aa_object* (%struct.aa_object*, %struct.aa_ss*, ...)* @aa_mm to i8 (i8*, %struct.aa_ss*, ...) zeroext *)( i8* %tmp6869, %struct.aa_ss* %tmp59, double* %atp, i8* %componentDesc, i8* %tmp66 ) zeroext ; <i8> [#uses=1]
+ ret i8 %tmp73
+
+cond_true111: ; preds = %cond_true111, %bb48
+ %idx.2132.0 = phi i32 [ 0, %bb48 ], [ %indvar.next, %cond_true111 ] ; <i32> [#uses=2]
+ %tmp95 = volatile load i8** %args ; <i8*> [#uses=2]
+ %tmp97 = getelementptr i8* %tmp95, i32 4 ; <i8*> [#uses=1]
+ volatile store i8* %tmp97, i8** %args
+ %tmp9899 = bitcast i8* %tmp95 to i32* ; <i32*> [#uses=1]
+ %tmp100 = load i32* %tmp9899 ; <i32> [#uses=1]
+ %tmp104 = getelementptr i32* %tmp92, i32 %idx.2132.0 ; <i32*> [#uses=1]
+ store i32 %tmp100, i32* %tmp104
+ %indvar.next = add i32 %idx.2132.0, 1 ; <i32> [#uses=2]
+ icmp eq i32 %indvar.next, %tmp78 ; <i1>:6 [#uses=1]
+ br i1 %6, label %bb114, label %cond_true111
+
+bb114: ; preds = %cond_true111, %bb48
+ call void @llvm.va_end( i8* %args4 )
+ %tmp122 = call i8 @_fooYCCV( %struct.__fooY* %calendar, double* %atp, i8* %componentDesc, i32* %tmp92, i32 %tmp78 ) zeroext ; <i8> [#uses=1]
+ ret i8 %tmp122
+}
+
+declare i32 @_fooXRegisterClass(%struct.fooXClass*)
+
+declare i8 @_fooYCCV(%struct.__fooY*, double*, i8*, i32*, i32) zeroext
+
+declare %struct.aa_object* @aa_mm(%struct.aa_object*, %struct.aa_ss*, ...)
+
+declare %struct.aa_ss* @sel_registerName(i8*)
+
+declare void @llvm.va_start(i8*)
+
+declare i32 @strlen(i8*)
+
+declare void @llvm.va_end(i8*)
diff --git a/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll b/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll
new file mode 100644
index 0000000..2074bfd
--- /dev/null
+++ b/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s | not grep r11
+
+target triple = "thumb-linux-gnueabi"
+ %struct.__sched_param = type { i32 }
+ %struct.pthread_attr_t = type { i32, i32, %struct.__sched_param, i32, i32, i32, i32, i8*, i32 }
[email protected] = internal global i32 1 ; <i32*> [#uses=2]
[email protected] = internal constant [14 x i8] c"Thread 1: %d\0A\00" ; <[14 x i8]*> [#uses=1]
[email protected] = internal constant [14 x i8] c"Thread 2: %d\0A\00" ; <[14 x i8]*> [#uses=1]
+
+define i8* @f(i8* %a) {
+entry:
+ %tmp1 = load i32* @i.1882 ; <i32> [#uses=1]
+ %tmp2 = add i32 %tmp1, 1 ; <i32> [#uses=2]
+ store i32 %tmp2, i32* @i.1882
+ %tmp34 = inttoptr i32 %tmp2 to i8* ; <i8*> [#uses=1]
+ ret i8* %tmp34
+}
+
+define i32 @main() {
+entry:
+ %t = alloca i32, align 4 ; <i32*> [#uses=4]
+ %ret = alloca i32, align 4 ; <i32*> [#uses=3]
+ %tmp1 = call i32 @pthread_create( i32* %t, %struct.pthread_attr_t* null, i8* (i8*)* @f, i8* null ) ; <i32> [#uses=0]
+ %tmp2 = load i32* %t ; <i32> [#uses=1]
+ %ret3 = bitcast i32* %ret to i8** ; <i8**> [#uses=2]
+ %tmp4 = call i32 @pthread_join( i32 %tmp2, i8** %ret3 ) ; <i32> [#uses=0]
+ %tmp5 = load i32* %ret ; <i32> [#uses=1]
+ %tmp7 = call i32 (i8*, ...)* @printf( i8* getelementptr ([14 x i8]* @.str, i32 0, i32 0), i32 %tmp5 ) ; <i32> [#uses=0]
+ %tmp8 = call i32 @pthread_create( i32* %t, %struct.pthread_attr_t* null, i8* (i8*)* @f, i8* null ) ; <i32> [#uses=0]
+ %tmp9 = load i32* %t ; <i32> [#uses=1]
+ %tmp11 = call i32 @pthread_join( i32 %tmp9, i8** %ret3 ) ; <i32> [#uses=0]
+ %tmp12 = load i32* %ret ; <i32> [#uses=1]
+ %tmp14 = call i32 (i8*, ...)* @printf( i8* getelementptr ([14 x i8]* @.str1, i32 0, i32 0), i32 %tmp12 ) ; <i32> [#uses=0]
+ ret i32 0
+}
+
+declare i32 @pthread_create(i32*, %struct.pthread_attr_t*, i8* (i8*)*, i8*)
+
+declare i32 @pthread_join(i32, i8**)
+
+declare i32 @printf(i8*, ...)
diff --git a/test/CodeGen/Thumb/2009-06-18-ThumbCommuteMul.ll b/test/CodeGen/Thumb/2009-06-18-ThumbCommuteMul.ll
new file mode 100644
index 0000000..5c883b3
--- /dev/null
+++ b/test/CodeGen/Thumb/2009-06-18-ThumbCommuteMul.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=thumb | grep r0 | count 1
+
+define i32 @a(i32 %x, i32 %y) nounwind readnone {
+entry:
+ %mul = mul i32 %y, %x ; <i32> [#uses=1]
+ ret i32 %mul
+}
+
diff --git a/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll b/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll
new file mode 100644
index 0000000..471a82f
--- /dev/null
+++ b/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -mtriple=thumbv6-elf | not grep "subs sp"
+; PR4567
+
+define arm_apcscc i8* @__gets_chk(i8* %s, i32 %slen) nounwind {
+entry:
+ br i1 undef, label %bb, label %bb1
+
+bb: ; preds = %entry
+ ret i8* undef
+
+bb1: ; preds = %entry
+ br i1 undef, label %bb3, label %bb2
+
+bb2: ; preds = %bb1
+ %0 = alloca i8, i32 undef, align 4 ; <i8*> [#uses=0]
+ br label %bb4
+
+bb3: ; preds = %bb1
+ %1 = malloc i8, i32 undef ; <i8*> [#uses=0]
+ br label %bb4
+
+bb4: ; preds = %bb3, %bb2
+ br i1 undef, label %bb5, label %bb6
+
+bb5: ; preds = %bb4
+ %2 = call arm_apcscc i8* @gets(i8* %s) nounwind ; <i8*> [#uses=1]
+ ret i8* %2
+
+bb6: ; preds = %bb4
+ unreachable
+}
+
+declare arm_apcscc i8* @gets(i8*) nounwind
diff --git a/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll b/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll
new file mode 100644
index 0000000..6e035d0
--- /dev/null
+++ b/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin10
+
[email protected] = external global i64 ; <i64*> [#uses=2]
+
+define arm_apcscc i64 @millisecs() nounwind {
+entry:
+ %0 = load i64* @Time.2535, align 4 ; <i64> [#uses=2]
+ %1 = add i64 %0, 1 ; <i64> [#uses=1]
+ store i64 %1, i64* @Time.2535, align 4
+ ret i64 %0
+}
diff --git a/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll b/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll
new file mode 100644
index 0000000..f195348
--- /dev/null
+++ b/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin -relocation-model=pic -disable-fp-elim
+
+ %struct.LinkList = type { i32, %struct.LinkList* }
+ %struct.List = type { i32, i32* }
[email protected] = appending global [1 x i8*] [i8* bitcast (i32 ()* @main to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define arm_apcscc i32 @main() nounwind {
+entry:
+ %ll = alloca %struct.LinkList*, align 4 ; <%struct.LinkList**> [#uses=1]
+ %0 = call arm_apcscc i32 @ReadList(%struct.LinkList** %ll, %struct.List** null) nounwind ; <i32> [#uses=1]
+ switch i32 %0, label %bb5 [
+ i32 7, label %bb4
+ i32 42, label %bb3
+ ]
+
+bb3: ; preds = %entry
+ ret i32 1
+
+bb4: ; preds = %entry
+ ret i32 0
+
+bb5: ; preds = %entry
+ ret i32 1
+}
+
+declare arm_apcscc i32 @ReadList(%struct.LinkList** nocapture, %struct.List** nocapture) nounwind
diff --git a/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll b/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll
new file mode 100644
index 0000000..ef4b5ce
--- /dev/null
+++ b/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll
@@ -0,0 +1,737 @@
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin
+
+ %struct.BF_KEY = type { [18 x i32], [1024 x i32] }
+
+define arm_apcscc void @BF_encrypt(i32* nocapture %data, %struct.BF_KEY* nocapture %key, i32 %encrypt) nounwind {
+entry:
+ %0 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 0; <i32*> [#uses=2]
+ %1 = load i32* %data, align 4 ; <i32> [#uses=2]
+ %2 = load i32* undef, align 4 ; <i32> [#uses=2]
+ br i1 undef, label %bb1, label %bb
+
+bb: ; preds = %entry
+ %3 = load i32* %0, align 4 ; <i32> [#uses=1]
+ %4 = xor i32 %3, %1 ; <i32> [#uses=4]
+ %5 = load i32* null, align 4 ; <i32> [#uses=1]
+ %6 = lshr i32 %4, 24 ; <i32> [#uses=1]
+ %7 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %6; <i32*> [#uses=1]
+ %8 = load i32* %7, align 4 ; <i32> [#uses=1]
+ %9 = lshr i32 %4, 16 ; <i32> [#uses=1]
+ %10 = or i32 %9, 256 ; <i32> [#uses=1]
+ %11 = and i32 %10, 511 ; <i32> [#uses=1]
+ %12 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %11; <i32*> [#uses=1]
+ %13 = load i32* %12, align 4 ; <i32> [#uses=1]
+ %14 = add i32 %13, %8 ; <i32> [#uses=1]
+ %15 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 undef; <i32*> [#uses=1]
+ %16 = load i32* %15, align 4 ; <i32> [#uses=1]
+ %17 = xor i32 %14, %16 ; <i32> [#uses=1]
+ %18 = or i32 %4, 768 ; <i32> [#uses=1]
+ %19 = and i32 %18, 1023 ; <i32> [#uses=1]
+ %20 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %19; <i32*> [#uses=1]
+ %21 = load i32* %20, align 4 ; <i32> [#uses=1]
+ %22 = add i32 %17, %21 ; <i32> [#uses=1]
+ %23 = xor i32 %5, %2 ; <i32> [#uses=1]
+ %24 = xor i32 %23, %22 ; <i32> [#uses=5]
+ %25 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 2; <i32*> [#uses=1]
+ %26 = load i32* %25, align 4 ; <i32> [#uses=1]
+ %27 = lshr i32 %24, 24 ; <i32> [#uses=1]
+ %28 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %27; <i32*> [#uses=1]
+ %29 = load i32* %28, align 4 ; <i32> [#uses=1]
+ %30 = lshr i32 %24, 16 ; <i32> [#uses=1]
+ %31 = or i32 %30, 256 ; <i32> [#uses=1]
+ %32 = and i32 %31, 511 ; <i32> [#uses=1]
+ %33 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %32; <i32*> [#uses=1]
+ %34 = load i32* %33, align 4 ; <i32> [#uses=1]
+ %35 = add i32 %34, %29 ; <i32> [#uses=1]
+ %36 = lshr i32 %24, 8 ; <i32> [#uses=1]
+ %37 = or i32 %36, 512 ; <i32> [#uses=1]
+ %38 = and i32 %37, 767 ; <i32> [#uses=1]
+ %39 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %38; <i32*> [#uses=1]
+ %40 = load i32* %39, align 4 ; <i32> [#uses=1]
+ %41 = xor i32 %35, %40 ; <i32> [#uses=1]
+ %42 = or i32 %24, 768 ; <i32> [#uses=1]
+ %43 = and i32 %42, 1023 ; <i32> [#uses=1]
+ %44 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %43; <i32*> [#uses=1]
+ %45 = load i32* %44, align 4 ; <i32> [#uses=1]
+ %46 = add i32 %41, %45 ; <i32> [#uses=1]
+ %47 = xor i32 %26, %4 ; <i32> [#uses=1]
+ %48 = xor i32 %47, %46 ; <i32> [#uses=5]
+ %49 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 3; <i32*> [#uses=1]
+ %50 = load i32* %49, align 4 ; <i32> [#uses=1]
+ %51 = lshr i32 %48, 24 ; <i32> [#uses=1]
+ %52 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %51; <i32*> [#uses=1]
+ %53 = load i32* %52, align 4 ; <i32> [#uses=1]
+ %54 = lshr i32 %48, 16 ; <i32> [#uses=1]
+ %55 = or i32 %54, 256 ; <i32> [#uses=1]
+ %56 = and i32 %55, 511 ; <i32> [#uses=1]
+ %57 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %56; <i32*> [#uses=1]
+ %58 = load i32* %57, align 4 ; <i32> [#uses=1]
+ %59 = add i32 %58, %53 ; <i32> [#uses=1]
+ %60 = lshr i32 %48, 8 ; <i32> [#uses=1]
+ %61 = or i32 %60, 512 ; <i32> [#uses=1]
+ %62 = and i32 %61, 767 ; <i32> [#uses=1]
+ %63 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %62; <i32*> [#uses=1]
+ %64 = load i32* %63, align 4 ; <i32> [#uses=1]
+ %65 = xor i32 %59, %64 ; <i32> [#uses=1]
+ %66 = or i32 %48, 768 ; <i32> [#uses=1]
+ %67 = and i32 %66, 1023 ; <i32> [#uses=1]
+ %68 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %67; <i32*> [#uses=1]
+ %69 = load i32* %68, align 4 ; <i32> [#uses=1]
+ %70 = add i32 %65, %69 ; <i32> [#uses=1]
+ %71 = xor i32 %50, %24 ; <i32> [#uses=1]
+ %72 = xor i32 %71, %70 ; <i32> [#uses=5]
+ %73 = load i32* null, align 4 ; <i32> [#uses=1]
+ %74 = lshr i32 %72, 24 ; <i32> [#uses=1]
+ %75 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %74; <i32*> [#uses=1]
+ %76 = load i32* %75, align 4 ; <i32> [#uses=1]
+ %77 = lshr i32 %72, 16 ; <i32> [#uses=1]
+ %78 = or i32 %77, 256 ; <i32> [#uses=1]
+ %79 = and i32 %78, 511 ; <i32> [#uses=1]
+ %80 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %79; <i32*> [#uses=1]
+ %81 = load i32* %80, align 4 ; <i32> [#uses=1]
+ %82 = add i32 %81, %76 ; <i32> [#uses=1]
+ %83 = lshr i32 %72, 8 ; <i32> [#uses=1]
+ %84 = or i32 %83, 512 ; <i32> [#uses=1]
+ %85 = and i32 %84, 767 ; <i32> [#uses=1]
+ %86 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %85; <i32*> [#uses=1]
+ %87 = load i32* %86, align 4 ; <i32> [#uses=1]
+ %88 = xor i32 %82, %87 ; <i32> [#uses=1]
+ %89 = or i32 %72, 768 ; <i32> [#uses=1]
+ %90 = and i32 %89, 1023 ; <i32> [#uses=1]
+ %91 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %90; <i32*> [#uses=1]
+ %92 = load i32* %91, align 4 ; <i32> [#uses=1]
+ %93 = add i32 %88, %92 ; <i32> [#uses=1]
+ %94 = xor i32 %73, %48 ; <i32> [#uses=1]
+ %95 = xor i32 %94, %93 ; <i32> [#uses=5]
+ %96 = load i32* undef, align 4 ; <i32> [#uses=1]
+ %97 = lshr i32 %95, 24 ; <i32> [#uses=1]
+ %98 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %97; <i32*> [#uses=1]
+ %99 = load i32* %98, align 4 ; <i32> [#uses=1]
+ %100 = lshr i32 %95, 16 ; <i32> [#uses=1]
+ %101 = or i32 %100, 256 ; <i32> [#uses=1]
+ %102 = and i32 %101, 511 ; <i32> [#uses=1]
+ %103 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %102; <i32*> [#uses=1]
+ %104 = load i32* %103, align 4 ; <i32> [#uses=1]
+ %105 = add i32 %104, %99 ; <i32> [#uses=1]
+ %106 = lshr i32 %95, 8 ; <i32> [#uses=1]
+ %107 = or i32 %106, 512 ; <i32> [#uses=1]
+ %108 = and i32 %107, 767 ; <i32> [#uses=1]
+ %109 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %108; <i32*> [#uses=1]
+ %110 = load i32* %109, align 4 ; <i32> [#uses=1]
+ %111 = xor i32 %105, %110 ; <i32> [#uses=1]
+ %112 = or i32 %95, 768 ; <i32> [#uses=1]
+ %113 = and i32 %112, 1023 ; <i32> [#uses=1]
+ %114 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %113; <i32*> [#uses=1]
+ %115 = load i32* %114, align 4 ; <i32> [#uses=1]
+ %116 = add i32 %111, %115 ; <i32> [#uses=1]
+ %117 = xor i32 %96, %72 ; <i32> [#uses=1]
+ %118 = xor i32 %117, %116 ; <i32> [#uses=5]
+ %119 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 6; <i32*> [#uses=1]
+ %120 = load i32* %119, align 4 ; <i32> [#uses=1]
+ %121 = lshr i32 %118, 24 ; <i32> [#uses=1]
+ %122 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %121; <i32*> [#uses=1]
+ %123 = load i32* %122, align 4 ; <i32> [#uses=1]
+ %124 = lshr i32 %118, 16 ; <i32> [#uses=1]
+ %125 = or i32 %124, 256 ; <i32> [#uses=1]
+ %126 = and i32 %125, 511 ; <i32> [#uses=1]
+ %127 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %126; <i32*> [#uses=1]
+ %128 = load i32* %127, align 4 ; <i32> [#uses=1]
+ %129 = add i32 %128, %123 ; <i32> [#uses=1]
+ %130 = lshr i32 %118, 8 ; <i32> [#uses=1]
+ %131 = or i32 %130, 512 ; <i32> [#uses=1]
+ %132 = and i32 %131, 767 ; <i32> [#uses=1]
+ %133 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %132; <i32*> [#uses=1]
+ %134 = load i32* %133, align 4 ; <i32> [#uses=1]
+ %135 = xor i32 %129, %134 ; <i32> [#uses=1]
+ %136 = or i32 %118, 768 ; <i32> [#uses=1]
+ %137 = and i32 %136, 1023 ; <i32> [#uses=1]
+ %138 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %137; <i32*> [#uses=1]
+ %139 = load i32* %138, align 4 ; <i32> [#uses=1]
+ %140 = add i32 %135, %139 ; <i32> [#uses=1]
+ %141 = xor i32 %120, %95 ; <i32> [#uses=1]
+ %142 = xor i32 %141, %140 ; <i32> [#uses=5]
+ %143 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 7; <i32*> [#uses=1]
+ %144 = load i32* %143, align 4 ; <i32> [#uses=1]
+ %145 = lshr i32 %142, 24 ; <i32> [#uses=1]
+ %146 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %145; <i32*> [#uses=1]
+ %147 = load i32* %146, align 4 ; <i32> [#uses=1]
+ %148 = lshr i32 %142, 16 ; <i32> [#uses=1]
+ %149 = or i32 %148, 256 ; <i32> [#uses=1]
+ %150 = and i32 %149, 511 ; <i32> [#uses=1]
+ %151 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %150; <i32*> [#uses=1]
+ %152 = load i32* %151, align 4 ; <i32> [#uses=1]
+ %153 = add i32 %152, %147 ; <i32> [#uses=1]
+ %154 = lshr i32 %142, 8 ; <i32> [#uses=1]
+ %155 = or i32 %154, 512 ; <i32> [#uses=1]
+ %156 = and i32 %155, 767 ; <i32> [#uses=1]
+ %157 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %156; <i32*> [#uses=1]
+ %158 = load i32* %157, align 4 ; <i32> [#uses=1]
+ %159 = xor i32 %153, %158 ; <i32> [#uses=1]
+ %160 = or i32 %142, 768 ; <i32> [#uses=1]
+ %161 = and i32 %160, 1023 ; <i32> [#uses=1]
+ %162 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %161; <i32*> [#uses=1]
+ %163 = load i32* %162, align 4 ; <i32> [#uses=1]
+ %164 = add i32 %159, %163 ; <i32> [#uses=1]
+ %165 = xor i32 %144, %118 ; <i32> [#uses=1]
+ %166 = xor i32 %165, %164 ; <i32> [#uses=5]
+ %167 = load i32* undef, align 4 ; <i32> [#uses=1]
+ %168 = lshr i32 %166, 24 ; <i32> [#uses=1]
+ %169 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %168; <i32*> [#uses=1]
+ %170 = load i32* %169, align 4 ; <i32> [#uses=1]
+ %171 = lshr i32 %166, 16 ; <i32> [#uses=1]
+ %172 = or i32 %171, 256 ; <i32> [#uses=1]
+ %173 = and i32 %172, 511 ; <i32> [#uses=1]
+ %174 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %173; <i32*> [#uses=1]
+ %175 = load i32* %174, align 4 ; <i32> [#uses=1]
+ %176 = add i32 %175, %170 ; <i32> [#uses=1]
+ %177 = lshr i32 %166, 8 ; <i32> [#uses=1]
+ %178 = or i32 %177, 512 ; <i32> [#uses=1]
+ %179 = and i32 %178, 767 ; <i32> [#uses=1]
+ %180 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %179; <i32*> [#uses=1]
+ %181 = load i32* %180, align 4 ; <i32> [#uses=1]
+ %182 = xor i32 %176, %181 ; <i32> [#uses=1]
+ %183 = or i32 %166, 768 ; <i32> [#uses=1]
+ %184 = and i32 %183, 1023 ; <i32> [#uses=1]
+ %185 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %184; <i32*> [#uses=1]
+ %186 = load i32* %185, align 4 ; <i32> [#uses=1]
+ %187 = add i32 %182, %186 ; <i32> [#uses=1]
+ %188 = xor i32 %167, %142 ; <i32> [#uses=1]
+ %189 = xor i32 %188, %187 ; <i32> [#uses=5]
+ %190 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 9; <i32*> [#uses=1]
+ %191 = load i32* %190, align 4 ; <i32> [#uses=1]
+ %192 = lshr i32 %189, 24 ; <i32> [#uses=1]
+ %193 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %192; <i32*> [#uses=1]
+ %194 = load i32* %193, align 4 ; <i32> [#uses=1]
+ %195 = lshr i32 %189, 16 ; <i32> [#uses=1]
+ %196 = or i32 %195, 256 ; <i32> [#uses=1]
+ %197 = and i32 %196, 511 ; <i32> [#uses=1]
+ %198 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %197; <i32*> [#uses=1]
+ %199 = load i32* %198, align 4 ; <i32> [#uses=1]
+ %200 = add i32 %199, %194 ; <i32> [#uses=1]
+ %201 = lshr i32 %189, 8 ; <i32> [#uses=1]
+ %202 = or i32 %201, 512 ; <i32> [#uses=1]
+ %203 = and i32 %202, 767 ; <i32> [#uses=1]
+ %204 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %203; <i32*> [#uses=1]
+ %205 = load i32* %204, align 4 ; <i32> [#uses=1]
+ %206 = xor i32 %200, %205 ; <i32> [#uses=1]
+ %207 = or i32 %189, 768 ; <i32> [#uses=1]
+ %208 = and i32 %207, 1023 ; <i32> [#uses=1]
+ %209 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %208; <i32*> [#uses=1]
+ %210 = load i32* %209, align 4 ; <i32> [#uses=1]
+ %211 = add i32 %206, %210 ; <i32> [#uses=1]
+ %212 = xor i32 %191, %166 ; <i32> [#uses=1]
+ %213 = xor i32 %212, %211 ; <i32> [#uses=5]
+ %214 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 10; <i32*> [#uses=1]
+ %215 = load i32* %214, align 4 ; <i32> [#uses=1]
+ %216 = lshr i32 %213, 24 ; <i32> [#uses=1]
+ %217 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %216; <i32*> [#uses=1]
+ %218 = load i32* %217, align 4 ; <i32> [#uses=1]
+ %219 = lshr i32 %213, 16 ; <i32> [#uses=1]
+ %220 = or i32 %219, 256 ; <i32> [#uses=1]
+ %221 = and i32 %220, 511 ; <i32> [#uses=1]
+ %222 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %221; <i32*> [#uses=1]
+ %223 = load i32* %222, align 4 ; <i32> [#uses=1]
+ %224 = add i32 %223, %218 ; <i32> [#uses=1]
+ %225 = lshr i32 %213, 8 ; <i32> [#uses=1]
+ %226 = or i32 %225, 512 ; <i32> [#uses=1]
+ %227 = and i32 %226, 767 ; <i32> [#uses=1]
+ %228 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %227; <i32*> [#uses=1]
+ %229 = load i32* %228, align 4 ; <i32> [#uses=1]
+ %230 = xor i32 %224, %229 ; <i32> [#uses=1]
+ %231 = or i32 %213, 768 ; <i32> [#uses=1]
+ %232 = and i32 %231, 1023 ; <i32> [#uses=1]
+ %233 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %232; <i32*> [#uses=1]
+ %234 = load i32* %233, align 4 ; <i32> [#uses=1]
+ %235 = add i32 %230, %234 ; <i32> [#uses=1]
+ %236 = xor i32 %215, %189 ; <i32> [#uses=1]
+ %237 = xor i32 %236, %235 ; <i32> [#uses=5]
+ %238 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 11; <i32*> [#uses=1]
+ %239 = load i32* %238, align 4 ; <i32> [#uses=1]
+ %240 = lshr i32 %237, 24 ; <i32> [#uses=1]
+ %241 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %240; <i32*> [#uses=1]
+ %242 = load i32* %241, align 4 ; <i32> [#uses=1]
+ %243 = lshr i32 %237, 16 ; <i32> [#uses=1]
+ %244 = or i32 %243, 256 ; <i32> [#uses=1]
+ %245 = and i32 %244, 511 ; <i32> [#uses=1]
+ %246 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %245; <i32*> [#uses=1]
+ %247 = load i32* %246, align 4 ; <i32> [#uses=1]
+ %248 = add i32 %247, %242 ; <i32> [#uses=1]
+ %249 = lshr i32 %237, 8 ; <i32> [#uses=1]
+ %250 = or i32 %249, 512 ; <i32> [#uses=1]
+ %251 = and i32 %250, 767 ; <i32> [#uses=1]
+ %252 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %251; <i32*> [#uses=1]
+ %253 = load i32* %252, align 4 ; <i32> [#uses=1]
+ %254 = xor i32 %248, %253 ; <i32> [#uses=1]
+ %255 = or i32 %237, 768 ; <i32> [#uses=1]
+ %256 = and i32 %255, 1023 ; <i32> [#uses=1]
+ %257 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %256; <i32*> [#uses=1]
+ %258 = load i32* %257, align 4 ; <i32> [#uses=1]
+ %259 = add i32 %254, %258 ; <i32> [#uses=1]
+ %260 = xor i32 %239, %213 ; <i32> [#uses=1]
+ %261 = xor i32 %260, %259 ; <i32> [#uses=5]
+ %262 = load i32* undef, align 4 ; <i32> [#uses=1]
+ %263 = lshr i32 %261, 24 ; <i32> [#uses=1]
+ %264 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %263; <i32*> [#uses=1]
+ %265 = load i32* %264, align 4 ; <i32> [#uses=1]
+ %266 = lshr i32 %261, 16 ; <i32> [#uses=1]
+ %267 = or i32 %266, 256 ; <i32> [#uses=1]
+ %268 = and i32 %267, 511 ; <i32> [#uses=1]
+ %269 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %268; <i32*> [#uses=1]
+ %270 = load i32* %269, align 4 ; <i32> [#uses=1]
+ %271 = add i32 %270, %265 ; <i32> [#uses=1]
+ %272 = lshr i32 %261, 8 ; <i32> [#uses=1]
+ %273 = or i32 %272, 512 ; <i32> [#uses=1]
+ %274 = and i32 %273, 767 ; <i32> [#uses=1]
+ %275 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %274; <i32*> [#uses=1]
+ %276 = load i32* %275, align 4 ; <i32> [#uses=1]
+ %277 = xor i32 %271, %276 ; <i32> [#uses=1]
+ %278 = or i32 %261, 768 ; <i32> [#uses=1]
+ %279 = and i32 %278, 1023 ; <i32> [#uses=1]
+ %280 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %279; <i32*> [#uses=1]
+ %281 = load i32* %280, align 4 ; <i32> [#uses=1]
+ %282 = add i32 %277, %281 ; <i32> [#uses=1]
+ %283 = xor i32 %262, %237 ; <i32> [#uses=1]
+ %284 = xor i32 %283, %282 ; <i32> [#uses=4]
+ %285 = load i32* null, align 4 ; <i32> [#uses=1]
+ %286 = lshr i32 %284, 24 ; <i32> [#uses=1]
+ %287 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %286; <i32*> [#uses=1]
+ %288 = load i32* %287, align 4 ; <i32> [#uses=1]
+ %289 = lshr i32 %284, 16 ; <i32> [#uses=1]
+ %290 = or i32 %289, 256 ; <i32> [#uses=1]
+ %291 = and i32 %290, 511 ; <i32> [#uses=1]
+ %292 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %291; <i32*> [#uses=1]
+ %293 = load i32* %292, align 4 ; <i32> [#uses=1]
+ %294 = add i32 %293, %288 ; <i32> [#uses=1]
+ %295 = lshr i32 %284, 8 ; <i32> [#uses=1]
+ %296 = or i32 %295, 512 ; <i32> [#uses=1]
+ %297 = and i32 %296, 767 ; <i32> [#uses=1]
+ %298 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %297; <i32*> [#uses=1]
+ %299 = load i32* %298, align 4 ; <i32> [#uses=1]
+ %300 = xor i32 %294, %299 ; <i32> [#uses=1]
+ %301 = or i32 %284, 768 ; <i32> [#uses=1]
+ %302 = and i32 %301, 1023 ; <i32> [#uses=1]
+ %303 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %302; <i32*> [#uses=1]
+ %304 = load i32* %303, align 4 ; <i32> [#uses=1]
+ %305 = add i32 %300, %304 ; <i32> [#uses=1]
+ %306 = xor i32 %285, %261 ; <i32> [#uses=1]
+ %307 = xor i32 %306, %305 ; <i32> [#uses=1]
+ %308 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 15; <i32*> [#uses=1]
+ %309 = load i32* %308, align 4 ; <i32> [#uses=1]
+ %310 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 0; <i32*> [#uses=1]
+ %311 = load i32* %310, align 4 ; <i32> [#uses=1]
+ %312 = or i32 0, 256 ; <i32> [#uses=1]
+ %313 = and i32 %312, 511 ; <i32> [#uses=1]
+ %314 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %313; <i32*> [#uses=1]
+ %315 = load i32* %314, align 4 ; <i32> [#uses=1]
+ %316 = add i32 %315, %311 ; <i32> [#uses=1]
+ %317 = or i32 0, 512 ; <i32> [#uses=1]
+ %318 = and i32 %317, 767 ; <i32> [#uses=1]
+ %319 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %318; <i32*> [#uses=1]
+ %320 = load i32* %319, align 4 ; <i32> [#uses=1]
+ %321 = xor i32 %316, %320 ; <i32> [#uses=1]
+ %322 = or i32 0, 768 ; <i32> [#uses=1]
+ %323 = and i32 %322, 1023 ; <i32> [#uses=1]
+ %324 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %323; <i32*> [#uses=1]
+ %325 = load i32* %324, align 4 ; <i32> [#uses=1]
+ %326 = add i32 %321, %325 ; <i32> [#uses=1]
+ %327 = xor i32 %309, %307 ; <i32> [#uses=1]
+ %328 = xor i32 %327, %326 ; <i32> [#uses=5]
+ %329 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 17; <i32*> [#uses=1]
+ br label %bb2
+
+bb1: ; preds = %entry
+ %330 = load i32* null, align 4 ; <i32> [#uses=1]
+ %331 = xor i32 %330, %1 ; <i32> [#uses=4]
+ %332 = load i32* null, align 4 ; <i32> [#uses=1]
+ %333 = lshr i32 %331, 24 ; <i32> [#uses=1]
+ %334 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %333; <i32*> [#uses=1]
+ %335 = load i32* %334, align 4 ; <i32> [#uses=1]
+ %336 = load i32* null, align 4 ; <i32> [#uses=1]
+ %337 = add i32 %336, %335 ; <i32> [#uses=1]
+ %338 = lshr i32 %331, 8 ; <i32> [#uses=1]
+ %339 = or i32 %338, 512 ; <i32> [#uses=1]
+ %340 = and i32 %339, 767 ; <i32> [#uses=1]
+ %341 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %340; <i32*> [#uses=1]
+ %342 = load i32* %341, align 4 ; <i32> [#uses=1]
+ %343 = xor i32 %337, %342 ; <i32> [#uses=1]
+ %344 = or i32 %331, 768 ; <i32> [#uses=1]
+ %345 = and i32 %344, 1023 ; <i32> [#uses=1]
+ %346 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %345; <i32*> [#uses=1]
+ %347 = load i32* %346, align 4 ; <i32> [#uses=1]
+ %348 = add i32 %343, %347 ; <i32> [#uses=1]
+ %349 = xor i32 %332, %2 ; <i32> [#uses=1]
+ %350 = xor i32 %349, %348 ; <i32> [#uses=5]
+ %351 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 15; <i32*> [#uses=1]
+ %352 = load i32* %351, align 4 ; <i32> [#uses=1]
+ %353 = lshr i32 %350, 24 ; <i32> [#uses=1]
+ %354 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %353; <i32*> [#uses=1]
+ %355 = load i32* %354, align 4 ; <i32> [#uses=1]
+ %356 = lshr i32 %350, 16 ; <i32> [#uses=1]
+ %357 = or i32 %356, 256 ; <i32> [#uses=1]
+ %358 = and i32 %357, 511 ; <i32> [#uses=1]
+ %359 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %358; <i32*> [#uses=1]
+ %360 = load i32* %359, align 4 ; <i32> [#uses=1]
+ %361 = add i32 %360, %355 ; <i32> [#uses=1]
+ %362 = lshr i32 %350, 8 ; <i32> [#uses=1]
+ %363 = or i32 %362, 512 ; <i32> [#uses=1]
+ %364 = and i32 %363, 767 ; <i32> [#uses=1]
+ %365 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %364; <i32*> [#uses=1]
+ %366 = load i32* %365, align 4 ; <i32> [#uses=1]
+ %367 = xor i32 %361, %366 ; <i32> [#uses=1]
+ %368 = or i32 %350, 768 ; <i32> [#uses=1]
+ %369 = and i32 %368, 1023 ; <i32> [#uses=1]
+ %370 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %369; <i32*> [#uses=1]
+ %371 = load i32* %370, align 4 ; <i32> [#uses=1]
+ %372 = add i32 %367, %371 ; <i32> [#uses=1]
+ %373 = xor i32 %352, %331 ; <i32> [#uses=1]
+ %374 = xor i32 %373, %372 ; <i32> [#uses=5]
+ %375 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 14; <i32*> [#uses=1]
+ %376 = load i32* %375, align 4 ; <i32> [#uses=1]
+ %377 = lshr i32 %374, 24 ; <i32> [#uses=1]
+ %378 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %377; <i32*> [#uses=1]
+ %379 = load i32* %378, align 4 ; <i32> [#uses=1]
+ %380 = lshr i32 %374, 16 ; <i32> [#uses=1]
+ %381 = or i32 %380, 256 ; <i32> [#uses=1]
+ %382 = and i32 %381, 511 ; <i32> [#uses=1]
+ %383 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %382; <i32*> [#uses=1]
+ %384 = load i32* %383, align 4 ; <i32> [#uses=1]
+ %385 = add i32 %384, %379 ; <i32> [#uses=1]
+ %386 = lshr i32 %374, 8 ; <i32> [#uses=1]
+ %387 = or i32 %386, 512 ; <i32> [#uses=1]
+ %388 = and i32 %387, 767 ; <i32> [#uses=1]
+ %389 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %388; <i32*> [#uses=1]
+ %390 = load i32* %389, align 4 ; <i32> [#uses=1]
+ %391 = xor i32 %385, %390 ; <i32> [#uses=1]
+ %392 = or i32 %374, 768 ; <i32> [#uses=1]
+ %393 = and i32 %392, 1023 ; <i32> [#uses=1]
+ %394 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %393; <i32*> [#uses=1]
+ %395 = load i32* %394, align 4 ; <i32> [#uses=1]
+ %396 = add i32 %391, %395 ; <i32> [#uses=1]
+ %397 = xor i32 %376, %350 ; <i32> [#uses=1]
+ %398 = xor i32 %397, %396 ; <i32> [#uses=5]
+ %399 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 13; <i32*> [#uses=1]
+ %400 = load i32* %399, align 4 ; <i32> [#uses=1]
+ %401 = lshr i32 %398, 24 ; <i32> [#uses=1]
+ %402 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %401; <i32*> [#uses=1]
+ %403 = load i32* %402, align 4 ; <i32> [#uses=1]
+ %404 = lshr i32 %398, 16 ; <i32> [#uses=1]
+ %405 = or i32 %404, 256 ; <i32> [#uses=1]
+ %406 = and i32 %405, 511 ; <i32> [#uses=1]
+ %407 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %406; <i32*> [#uses=1]
+ %408 = load i32* %407, align 4 ; <i32> [#uses=1]
+ %409 = add i32 %408, %403 ; <i32> [#uses=1]
+ %410 = lshr i32 %398, 8 ; <i32> [#uses=1]
+ %411 = or i32 %410, 512 ; <i32> [#uses=1]
+ %412 = and i32 %411, 767 ; <i32> [#uses=1]
+ %413 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %412; <i32*> [#uses=1]
+ %414 = load i32* %413, align 4 ; <i32> [#uses=1]
+ %415 = xor i32 %409, %414 ; <i32> [#uses=1]
+ %416 = or i32 %398, 768 ; <i32> [#uses=1]
+ %417 = and i32 %416, 1023 ; <i32> [#uses=1]
+ %418 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %417; <i32*> [#uses=1]
+ %419 = load i32* %418, align 4 ; <i32> [#uses=1]
+ %420 = add i32 %415, %419 ; <i32> [#uses=1]
+ %421 = xor i32 %400, %374 ; <i32> [#uses=1]
+ %422 = xor i32 %421, %420 ; <i32> [#uses=5]
+ %423 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 12; <i32*> [#uses=1]
+ %424 = load i32* %423, align 4 ; <i32> [#uses=1]
+ %425 = lshr i32 %422, 24 ; <i32> [#uses=1]
+ %426 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %425; <i32*> [#uses=1]
+ %427 = load i32* %426, align 4 ; <i32> [#uses=1]
+ %428 = lshr i32 %422, 16 ; <i32> [#uses=1]
+ %429 = or i32 %428, 256 ; <i32> [#uses=1]
+ %430 = and i32 %429, 511 ; <i32> [#uses=1]
+ %431 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %430; <i32*> [#uses=1]
+ %432 = load i32* %431, align 4 ; <i32> [#uses=1]
+ %433 = add i32 %432, %427 ; <i32> [#uses=1]
+ %434 = lshr i32 %422, 8 ; <i32> [#uses=1]
+ %435 = or i32 %434, 512 ; <i32> [#uses=1]
+ %436 = and i32 %435, 767 ; <i32> [#uses=1]
+ %437 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %436; <i32*> [#uses=1]
+ %438 = load i32* %437, align 4 ; <i32> [#uses=1]
+ %439 = xor i32 %433, %438 ; <i32> [#uses=1]
+ %440 = or i32 %422, 768 ; <i32> [#uses=1]
+ %441 = and i32 %440, 1023 ; <i32> [#uses=1]
+ %442 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %441; <i32*> [#uses=1]
+ %443 = load i32* %442, align 4 ; <i32> [#uses=1]
+ %444 = add i32 %439, %443 ; <i32> [#uses=1]
+ %445 = xor i32 %424, %398 ; <i32> [#uses=1]
+ %446 = xor i32 %445, %444 ; <i32> [#uses=5]
+ %447 = load i32* undef, align 4 ; <i32> [#uses=1]
+ %448 = lshr i32 %446, 24 ; <i32> [#uses=1]
+ %449 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %448; <i32*> [#uses=1]
+ %450 = load i32* %449, align 4 ; <i32> [#uses=1]
+ %451 = lshr i32 %446, 16 ; <i32> [#uses=1]
+ %452 = or i32 %451, 256 ; <i32> [#uses=1]
+ %453 = and i32 %452, 511 ; <i32> [#uses=1]
+ %454 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %453; <i32*> [#uses=1]
+ %455 = load i32* %454, align 4 ; <i32> [#uses=1]
+ %456 = add i32 %455, %450 ; <i32> [#uses=1]
+ %457 = lshr i32 %446, 8 ; <i32> [#uses=1]
+ %458 = or i32 %457, 512 ; <i32> [#uses=1]
+ %459 = and i32 %458, 767 ; <i32> [#uses=1]
+ %460 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %459; <i32*> [#uses=1]
+ %461 = load i32* %460, align 4 ; <i32> [#uses=1]
+ %462 = xor i32 %456, %461 ; <i32> [#uses=1]
+ %463 = or i32 %446, 768 ; <i32> [#uses=1]
+ %464 = and i32 %463, 1023 ; <i32> [#uses=1]
+ %465 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %464; <i32*> [#uses=1]
+ %466 = load i32* %465, align 4 ; <i32> [#uses=1]
+ %467 = add i32 %462, %466 ; <i32> [#uses=1]
+ %468 = xor i32 %447, %422 ; <i32> [#uses=1]
+ %469 = xor i32 %468, %467 ; <i32> [#uses=5]
+ %470 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 10; <i32*> [#uses=1]
+ %471 = load i32* %470, align 4 ; <i32> [#uses=1]
+ %472 = lshr i32 %469, 24 ; <i32> [#uses=1]
+ %473 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %472; <i32*> [#uses=1]
+ %474 = load i32* %473, align 4 ; <i32> [#uses=1]
+ %475 = lshr i32 %469, 16 ; <i32> [#uses=1]
+ %476 = or i32 %475, 256 ; <i32> [#uses=1]
+ %477 = and i32 %476, 511 ; <i32> [#uses=1]
+ %478 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %477; <i32*> [#uses=1]
+ %479 = load i32* %478, align 4 ; <i32> [#uses=1]
+ %480 = add i32 %479, %474 ; <i32> [#uses=1]
+ %481 = lshr i32 %469, 8 ; <i32> [#uses=1]
+ %482 = or i32 %481, 512 ; <i32> [#uses=1]
+ %483 = and i32 %482, 767 ; <i32> [#uses=1]
+ %484 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %483; <i32*> [#uses=1]
+ %485 = load i32* %484, align 4 ; <i32> [#uses=1]
+ %486 = xor i32 %480, %485 ; <i32> [#uses=1]
+ %487 = or i32 %469, 768 ; <i32> [#uses=1]
+ %488 = and i32 %487, 1023 ; <i32> [#uses=1]
+ %489 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %488; <i32*> [#uses=1]
+ %490 = load i32* %489, align 4 ; <i32> [#uses=1]
+ %491 = add i32 %486, %490 ; <i32> [#uses=1]
+ %492 = xor i32 %471, %446 ; <i32> [#uses=1]
+ %493 = xor i32 %492, %491 ; <i32> [#uses=5]
+ %494 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 9; <i32*> [#uses=1]
+ %495 = load i32* %494, align 4 ; <i32> [#uses=1]
+ %496 = lshr i32 %493, 24 ; <i32> [#uses=1]
+ %497 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %496; <i32*> [#uses=1]
+ %498 = load i32* %497, align 4 ; <i32> [#uses=1]
+ %499 = lshr i32 %493, 16 ; <i32> [#uses=1]
+ %500 = or i32 %499, 256 ; <i32> [#uses=1]
+ %501 = and i32 %500, 511 ; <i32> [#uses=1]
+ %502 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %501; <i32*> [#uses=1]
+ %503 = load i32* %502, align 4 ; <i32> [#uses=1]
+ %504 = add i32 %503, %498 ; <i32> [#uses=1]
+ %505 = lshr i32 %493, 8 ; <i32> [#uses=1]
+ %506 = or i32 %505, 512 ; <i32> [#uses=1]
+ %507 = and i32 %506, 767 ; <i32> [#uses=1]
+ %508 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %507; <i32*> [#uses=1]
+ %509 = load i32* %508, align 4 ; <i32> [#uses=1]
+ %510 = xor i32 %504, %509 ; <i32> [#uses=1]
+ %511 = or i32 %493, 768 ; <i32> [#uses=1]
+ %512 = and i32 %511, 1023 ; <i32> [#uses=1]
+ %513 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %512; <i32*> [#uses=1]
+ %514 = load i32* %513, align 4 ; <i32> [#uses=1]
+ %515 = add i32 %510, %514 ; <i32> [#uses=1]
+ %516 = xor i32 %495, %469 ; <i32> [#uses=1]
+ %517 = xor i32 %516, %515 ; <i32> [#uses=5]
+ %518 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 8; <i32*> [#uses=1]
+ %519 = load i32* %518, align 4 ; <i32> [#uses=1]
+ %520 = lshr i32 %517, 24 ; <i32> [#uses=1]
+ %521 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %520; <i32*> [#uses=1]
+ %522 = load i32* %521, align 4 ; <i32> [#uses=1]
+ %523 = lshr i32 %517, 16 ; <i32> [#uses=1]
+ %524 = or i32 %523, 256 ; <i32> [#uses=1]
+ %525 = and i32 %524, 511 ; <i32> [#uses=1]
+ %526 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %525; <i32*> [#uses=1]
+ %527 = load i32* %526, align 4 ; <i32> [#uses=1]
+ %528 = add i32 %527, %522 ; <i32> [#uses=1]
+ %529 = lshr i32 %517, 8 ; <i32> [#uses=1]
+ %530 = or i32 %529, 512 ; <i32> [#uses=1]
+ %531 = and i32 %530, 767 ; <i32> [#uses=1]
+ %532 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %531; <i32*> [#uses=1]
+ %533 = load i32* %532, align 4 ; <i32> [#uses=1]
+ %534 = xor i32 %528, %533 ; <i32> [#uses=1]
+ %535 = or i32 %517, 768 ; <i32> [#uses=1]
+ %536 = and i32 %535, 1023 ; <i32> [#uses=1]
+ %537 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %536; <i32*> [#uses=1]
+ %538 = load i32* %537, align 4 ; <i32> [#uses=1]
+ %539 = add i32 %534, %538 ; <i32> [#uses=1]
+ %540 = xor i32 %519, %493 ; <i32> [#uses=1]
+ %541 = xor i32 %540, %539 ; <i32> [#uses=5]
+ %542 = load i32* undef, align 4 ; <i32> [#uses=1]
+ %543 = lshr i32 %541, 24 ; <i32> [#uses=1]
+ %544 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %543; <i32*> [#uses=1]
+ %545 = load i32* %544, align 4 ; <i32> [#uses=1]
+ %546 = lshr i32 %541, 16 ; <i32> [#uses=1]
+ %547 = or i32 %546, 256 ; <i32> [#uses=1]
+ %548 = and i32 %547, 511 ; <i32> [#uses=1]
+ %549 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %548; <i32*> [#uses=1]
+ %550 = load i32* %549, align 4 ; <i32> [#uses=1]
+ %551 = add i32 %550, %545 ; <i32> [#uses=1]
+ %552 = lshr i32 %541, 8 ; <i32> [#uses=1]
+ %553 = or i32 %552, 512 ; <i32> [#uses=1]
+ %554 = and i32 %553, 767 ; <i32> [#uses=1]
+ %555 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %554; <i32*> [#uses=1]
+ %556 = load i32* %555, align 4 ; <i32> [#uses=1]
+ %557 = xor i32 %551, %556 ; <i32> [#uses=1]
+ %558 = or i32 %541, 768 ; <i32> [#uses=1]
+ %559 = and i32 %558, 1023 ; <i32> [#uses=1]
+ %560 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %559; <i32*> [#uses=1]
+ %561 = load i32* %560, align 4 ; <i32> [#uses=1]
+ %562 = add i32 %557, %561 ; <i32> [#uses=1]
+ %563 = xor i32 %542, %517 ; <i32> [#uses=1]
+ %564 = xor i32 %563, %562 ; <i32> [#uses=5]
+ %565 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 6; <i32*> [#uses=1]
+ %566 = load i32* %565, align 4 ; <i32> [#uses=1]
+ %567 = lshr i32 %564, 24 ; <i32> [#uses=1]
+ %568 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %567; <i32*> [#uses=1]
+ %569 = load i32* %568, align 4 ; <i32> [#uses=1]
+ %570 = lshr i32 %564, 16 ; <i32> [#uses=1]
+ %571 = or i32 %570, 256 ; <i32> [#uses=1]
+ %572 = and i32 %571, 511 ; <i32> [#uses=1]
+ %573 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %572; <i32*> [#uses=1]
+ %574 = load i32* %573, align 4 ; <i32> [#uses=1]
+ %575 = add i32 %574, %569 ; <i32> [#uses=1]
+ %576 = lshr i32 %564, 8 ; <i32> [#uses=1]
+ %577 = or i32 %576, 512 ; <i32> [#uses=1]
+ %578 = and i32 %577, 767 ; <i32> [#uses=1]
+ %579 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %578; <i32*> [#uses=1]
+ %580 = load i32* %579, align 4 ; <i32> [#uses=1]
+ %581 = xor i32 %575, %580 ; <i32> [#uses=1]
+ %582 = or i32 %564, 768 ; <i32> [#uses=1]
+ %583 = and i32 %582, 1023 ; <i32> [#uses=1]
+ %584 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %583; <i32*> [#uses=1]
+ %585 = load i32* %584, align 4 ; <i32> [#uses=1]
+ %586 = add i32 %581, %585 ; <i32> [#uses=1]
+ %587 = xor i32 %566, %541 ; <i32> [#uses=1]
+ %588 = xor i32 %587, %586 ; <i32> [#uses=5]
+ %589 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 5; <i32*> [#uses=1]
+ %590 = load i32* %589, align 4 ; <i32> [#uses=1]
+ %591 = lshr i32 %588, 24 ; <i32> [#uses=1]
+ %592 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %591; <i32*> [#uses=1]
+ %593 = load i32* %592, align 4 ; <i32> [#uses=1]
+ %594 = lshr i32 %588, 16 ; <i32> [#uses=1]
+ %595 = or i32 %594, 256 ; <i32> [#uses=1]
+ %596 = and i32 %595, 511 ; <i32> [#uses=1]
+ %597 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %596; <i32*> [#uses=1]
+ %598 = load i32* %597, align 4 ; <i32> [#uses=1]
+ %599 = add i32 %598, %593 ; <i32> [#uses=1]
+ %600 = lshr i32 %588, 8 ; <i32> [#uses=1]
+ %601 = or i32 %600, 512 ; <i32> [#uses=1]
+ %602 = and i32 %601, 767 ; <i32> [#uses=1]
+ %603 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %602; <i32*> [#uses=1]
+ %604 = load i32* %603, align 4 ; <i32> [#uses=1]
+ %605 = xor i32 %599, %604 ; <i32> [#uses=1]
+ %606 = or i32 %588, 768 ; <i32> [#uses=1]
+ %607 = and i32 %606, 1023 ; <i32> [#uses=1]
+ %608 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %607; <i32*> [#uses=1]
+ %609 = load i32* %608, align 4 ; <i32> [#uses=1]
+ %610 = add i32 %605, %609 ; <i32> [#uses=1]
+ %611 = xor i32 %590, %564 ; <i32> [#uses=1]
+ %612 = xor i32 %611, %610 ; <i32> [#uses=5]
+ %613 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 4; <i32*> [#uses=1]
+ %614 = load i32* %613, align 4 ; <i32> [#uses=1]
+ %615 = lshr i32 %612, 24 ; <i32> [#uses=1]
+ %616 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %615; <i32*> [#uses=1]
+ %617 = load i32* %616, align 4 ; <i32> [#uses=1]
+ %618 = lshr i32 %612, 16 ; <i32> [#uses=1]
+ %619 = or i32 %618, 256 ; <i32> [#uses=1]
+ %620 = and i32 %619, 511 ; <i32> [#uses=1]
+ %621 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %620; <i32*> [#uses=1]
+ %622 = load i32* %621, align 4 ; <i32> [#uses=1]
+ %623 = add i32 %622, %617 ; <i32> [#uses=1]
+ %624 = lshr i32 %612, 8 ; <i32> [#uses=1]
+ %625 = or i32 %624, 512 ; <i32> [#uses=1]
+ %626 = and i32 %625, 767 ; <i32> [#uses=1]
+ %627 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %626; <i32*> [#uses=1]
+ %628 = load i32* %627, align 4 ; <i32> [#uses=1]
+ %629 = xor i32 %623, %628 ; <i32> [#uses=1]
+ %630 = or i32 %612, 768 ; <i32> [#uses=1]
+ %631 = and i32 %630, 1023 ; <i32> [#uses=1]
+ %632 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %631; <i32*> [#uses=1]
+ %633 = load i32* %632, align 4 ; <i32> [#uses=1]
+ %634 = add i32 %629, %633 ; <i32> [#uses=1]
+ %635 = xor i32 %614, %588 ; <i32> [#uses=1]
+ %636 = xor i32 %635, %634 ; <i32> [#uses=5]
+ %637 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 3; <i32*> [#uses=1]
+ %638 = load i32* %637, align 4 ; <i32> [#uses=1]
+ %639 = lshr i32 %636, 24 ; <i32> [#uses=1]
+ %640 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %639; <i32*> [#uses=1]
+ %641 = load i32* %640, align 4 ; <i32> [#uses=1]
+ %642 = lshr i32 %636, 16 ; <i32> [#uses=1]
+ %643 = or i32 %642, 256 ; <i32> [#uses=1]
+ %644 = and i32 %643, 511 ; <i32> [#uses=1]
+ %645 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %644; <i32*> [#uses=1]
+ %646 = load i32* %645, align 4 ; <i32> [#uses=1]
+ %647 = add i32 %646, %641 ; <i32> [#uses=1]
+ %648 = lshr i32 %636, 8 ; <i32> [#uses=1]
+ %649 = or i32 %648, 512 ; <i32> [#uses=1]
+ %650 = and i32 %649, 767 ; <i32> [#uses=1]
+ %651 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %650; <i32*> [#uses=1]
+ %652 = load i32* %651, align 4 ; <i32> [#uses=1]
+ %653 = xor i32 %647, %652 ; <i32> [#uses=1]
+ %654 = or i32 %636, 768 ; <i32> [#uses=1]
+ %655 = and i32 %654, 1023 ; <i32> [#uses=1]
+ %656 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %655; <i32*> [#uses=1]
+ %657 = load i32* %656, align 4 ; <i32> [#uses=1]
+ %658 = add i32 %653, %657 ; <i32> [#uses=1]
+ %659 = xor i32 %638, %612 ; <i32> [#uses=1]
+ %660 = xor i32 %659, %658 ; <i32> [#uses=5]
+ %661 = load i32* undef, align 4 ; <i32> [#uses=1]
+ %662 = lshr i32 %660, 24 ; <i32> [#uses=1]
+ %663 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %662; <i32*> [#uses=1]
+ %664 = load i32* %663, align 4 ; <i32> [#uses=1]
+ %665 = lshr i32 %660, 16 ; <i32> [#uses=1]
+ %666 = or i32 %665, 256 ; <i32> [#uses=1]
+ %667 = and i32 %666, 511 ; <i32> [#uses=1]
+ %668 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %667; <i32*> [#uses=1]
+ %669 = load i32* %668, align 4 ; <i32> [#uses=1]
+ %670 = add i32 %669, %664 ; <i32> [#uses=1]
+ %671 = lshr i32 %660, 8 ; <i32> [#uses=1]
+ %672 = or i32 %671, 512 ; <i32> [#uses=1]
+ %673 = and i32 %672, 767 ; <i32> [#uses=1]
+ %674 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %673; <i32*> [#uses=1]
+ %675 = load i32* %674, align 4 ; <i32> [#uses=1]
+ %676 = xor i32 %670, %675 ; <i32> [#uses=1]
+ %677 = or i32 %660, 768 ; <i32> [#uses=1]
+ %678 = and i32 %677, 1023 ; <i32> [#uses=1]
+ %679 = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %678; <i32*> [#uses=1]
+ %680 = load i32* %679, align 4 ; <i32> [#uses=1]
+ %681 = add i32 %676, %680 ; <i32> [#uses=1]
+ %682 = xor i32 %661, %636 ; <i32> [#uses=1]
+ %683 = xor i32 %682, %681 ; <i32> [#uses=5]
+ %684 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 1; <i32*> [#uses=1]
+ br label %bb2
+
+bb2: ; preds = %bb1, %bb
+ %.pn2.in = phi i32* [ %329, %bb ], [ %0, %bb1 ]; <i32*> [#uses=1]
+ %.pn3 = phi i32 [ %328, %bb ], [ %683, %bb1 ]; <i32> [#uses=1]
+ %.pn15.in = phi i32 [ %328, %bb ], [ %683, %bb1 ]; <i32> [#uses=1]
+ %.pn14.in.in.in = phi i32 [ %328, %bb ], [ %683, %bb1 ]; <i32> [#uses=1]
+ %.pn13.in.in.in = phi i32 [ %328, %bb ], [ %683, %bb1 ]; <i32> [#uses=1]
+ %.pn10.in.in = phi i32 [ %328, %bb ], [ %683, %bb1 ]; <i32> [#uses=1]
+ %.pn4.in = phi i32* [ null, %bb ], [ %684, %bb1 ]; <i32*> [#uses=1]
+ %.pn5 = phi i32 [ 0, %bb ], [ %660, %bb1 ]; <i32> [#uses=1]
+ %.pn14.in.in = lshr i32 %.pn14.in.in.in, 16; <i32> [#uses=1]
+ %.pn14.in = or i32 %.pn14.in.in, 256 ; <i32> [#uses=1]
+ %.pn13.in.in = lshr i32 %.pn13.in.in.in, 8; <i32> [#uses=1]
+ %.pn15 = lshr i32 %.pn15.in, 24 ; <i32> [#uses=1]
+ %.pn14 = and i32 %.pn14.in, 511 ; <i32> [#uses=1]
+ %.pn13.in = or i32 %.pn13.in.in, 512 ; <i32> [#uses=1]
+ %.pn11.in = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %.pn15; <i32*> [#uses=1]
+ %.pn12.in = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %.pn14; <i32*> [#uses=1]
+ %.pn13 = and i32 %.pn13.in, 767 ; <i32> [#uses=1]
+ %.pn10.in = or i32 %.pn10.in.in, 768 ; <i32> [#uses=1]
+ %.pn11 = load i32* %.pn11.in ; <i32> [#uses=1]
+ %.pn12 = load i32* %.pn12.in ; <i32> [#uses=1]
+ %.pn9.in = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %.pn13; <i32*> [#uses=1]
+ %.pn10 = and i32 %.pn10.in, 1023 ; <i32> [#uses=1]
+ %.pn8 = add i32 %.pn12, %.pn11 ; <i32> [#uses=1]
+ %.pn9 = load i32* %.pn9.in ; <i32> [#uses=1]
+ %.pn7.in = getelementptr %struct.BF_KEY* %key, i32 0, i32 1, i32 %.pn10; <i32*> [#uses=1]
+ %.pn6 = xor i32 %.pn8, %.pn9 ; <i32> [#uses=1]
+ %.pn7 = load i32* %.pn7.in ; <i32> [#uses=1]
+ %.pn4 = load i32* %.pn4.in ; <i32> [#uses=1]
+ %.pn2 = load i32* %.pn2.in ; <i32> [#uses=1]
+ %.pn = add i32 %.pn6, %.pn7 ; <i32> [#uses=1]
+ %r.0 = xor i32 %.pn2, %.pn3 ; <i32> [#uses=1]
+ %.pn1 = xor i32 %.pn, %.pn5 ; <i32> [#uses=1]
+ %l.0 = xor i32 %.pn1, %.pn4 ; <i32> [#uses=1]
+ store i32 %l.0, i32* undef, align 4
+ store i32 %r.0, i32* %data, align 4
+ ret void
+}
diff --git a/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll b/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll
new file mode 100644
index 0000000..b6e67b1
--- /dev/null
+++ b/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin
+
+ %struct.vorbis_comment = type { i8**, i32*, i32, i8* }
[email protected] = external constant [2 x i8], align 1 ; <[2 x i8]*> [#uses=1]
+
+declare arm_apcscc i8* @__strcpy_chk(i8*, i8*, i32) nounwind
+
+declare arm_apcscc i8* @__strcat_chk(i8*, i8*, i32) nounwind
+
+define arm_apcscc i8* @vorbis_comment_query(%struct.vorbis_comment* nocapture %vc, i8* %tag, i32 %count) nounwind {
+entry:
+ %0 = alloca i8, i32 undef, align 4 ; <i8*> [#uses=2]
+ %1 = call arm_apcscc i8* @__strcpy_chk(i8* %0, i8* %tag, i32 -1) nounwind; <i8*> [#uses=0]
+ %2 = call arm_apcscc i8* @__strcat_chk(i8* %0, i8* getelementptr ([2 x i8]* @.str16, i32 0, i32 0), i32 -1) nounwind; <i8*> [#uses=0]
+ %3 = getelementptr %struct.vorbis_comment* %vc, i32 0, i32 0; <i8***> [#uses=1]
+ br label %bb11
+
+bb6: ; preds = %bb11
+ %4 = load i8*** %3, align 4 ; <i8**> [#uses=1]
+ %scevgep = getelementptr i8** %4, i32 %8 ; <i8**> [#uses=1]
+ %5 = load i8** %scevgep, align 4 ; <i8*> [#uses=1]
+ br label %bb3.i
+
+bb3.i: ; preds = %bb3.i, %bb6
+ %scevgep7.i = getelementptr i8* %5, i32 0 ; <i8*> [#uses=1]
+ %6 = load i8* %scevgep7.i, align 1 ; <i8> [#uses=0]
+ br i1 undef, label %bb3.i, label %bb10
+
+bb10: ; preds = %bb3.i
+ %7 = add i32 %8, 1 ; <i32> [#uses=1]
+ br label %bb11
+
+bb11: ; preds = %bb10, %entry
+ %8 = phi i32 [ %7, %bb10 ], [ 0, %entry ] ; <i32> [#uses=3]
+ %9 = icmp sgt i32 undef, %8 ; <i1> [#uses=1]
+ br i1 %9, label %bb6, label %bb13
+
+bb13: ; preds = %bb11
+ ret i8* null
+}
diff --git a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
new file mode 100644
index 0000000..c31b65b
--- /dev/null
+++ b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
@@ -0,0 +1,66 @@
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin -relocation-model=pic -disable-fp-elim -mattr=+v6 | FileCheck %s
+; rdar://7157006
+
+%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+%struct.__sFILEX = type opaque
+%struct.__sbuf = type { i8*, i32 }
+%struct.asl_file_t = type { i32, i32, i32, %struct.file_string_t*, i64, i64, i64, i64, i64, i64, i32, %struct.FILE*, i8*, i8* }
+%struct.file_string_t = type { i64, i32, %struct.file_string_t*, [0 x i8] }
+
[email protected] = appending global [1 x i8*] [i8* bitcast (i32 (%struct.asl_file_t*, i64, i64*)* @t to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define arm_apcscc i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize {
+; CHECK: t:
+; CHECK: adds r3, #8
+entry:
+ %val = alloca i64, align 4 ; <i64*> [#uses=3]
+ %0 = icmp eq %struct.asl_file_t* %s, null ; <i1> [#uses=1]
+ br i1 %0, label %bb13, label %bb1
+
+bb1: ; preds = %entry
+ %1 = getelementptr inbounds %struct.asl_file_t* %s, i32 0, i32 11 ; <%struct.FILE**> [#uses=2]
+ %2 = load %struct.FILE** %1, align 4 ; <%struct.FILE*> [#uses=2]
+ %3 = icmp eq %struct.FILE* %2, null ; <i1> [#uses=1]
+ br i1 %3, label %bb13, label %bb3
+
+bb3: ; preds = %bb1
+ %4 = add nsw i64 %off, 8 ; <i64> [#uses=1]
+ %5 = getelementptr inbounds %struct.asl_file_t* %s, i32 0, i32 10 ; <i32*> [#uses=1]
+ %6 = load i32* %5, align 4 ; <i32> [#uses=1]
+ %7 = zext i32 %6 to i64 ; <i64> [#uses=1]
+ %8 = icmp sgt i64 %4, %7 ; <i1> [#uses=1]
+ br i1 %8, label %bb13, label %bb5
+
+bb5: ; preds = %bb3
+ %9 = call arm_apcscc i32 @fseeko(%struct.FILE* %2, i64 %off, i32 0) nounwind ; <i32> [#uses=1]
+ %10 = icmp eq i32 %9, 0 ; <i1> [#uses=1]
+ br i1 %10, label %bb7, label %bb13
+
+bb7: ; preds = %bb5
+ store i64 0, i64* %val, align 4
+ %11 = load %struct.FILE** %1, align 4 ; <%struct.FILE*> [#uses=1]
+ %val8 = bitcast i64* %val to i8* ; <i8*> [#uses=1]
+ %12 = call arm_apcscc i32 @fread(i8* noalias %val8, i32 8, i32 1, %struct.FILE* noalias %11) nounwind ; <i32> [#uses=1]
+ %13 = icmp eq i32 %12, 1 ; <i1> [#uses=1]
+ br i1 %13, label %bb10, label %bb13
+
+bb10: ; preds = %bb7
+ %14 = icmp eq i64* %out, null ; <i1> [#uses=1]
+ br i1 %14, label %bb13, label %bb11
+
+bb11: ; preds = %bb10
+ %15 = load i64* %val, align 4 ; <i64> [#uses=1]
+ %16 = call arm_apcscc i64 @asl_core_ntohq(i64 %15) nounwind ; <i64> [#uses=1]
+ store i64 %16, i64* %out, align 4
+ ret i32 0
+
+bb13: ; preds = %bb10, %bb7, %bb5, %bb3, %bb1, %entry
+ %.0 = phi i32 [ 2, %entry ], [ 2, %bb1 ], [ 7, %bb3 ], [ 7, %bb5 ], [ 7, %bb7 ], [ 0, %bb10 ] ; <i32> [#uses=1]
+ ret i32 %.0
+}
+
+declare arm_apcscc i32 @fseeko(%struct.FILE* nocapture, i64, i32) nounwind
+
+declare arm_apcscc i32 @fread(i8* noalias nocapture, i32, i32, %struct.FILE* noalias nocapture) nounwind
+
+declare arm_apcscc i64 @asl_core_ntohq(i64)
diff --git a/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll b/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll
new file mode 100644
index 0000000..2a5d9d6
--- /dev/null
+++ b/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll
@@ -0,0 +1,66 @@
+; RUN: llc -O3 < %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
+target triple = "thumbv7-apple-darwin10"
+
+; This test should not produce any spills, even when tail duplication creates lots of phi nodes.
+; CHECK-NOT: push
+; CHECK-NOT: pop
+; CHECK: bx lr
+
[email protected] = internal constant [5 x i8*] [i8* blockaddress(@interpret_threaded, %RETURN), i8* blockaddress(@interpret_threaded, %INCREMENT), i8* blockaddress(@interpret_threaded, %DECREMENT), i8* blockaddress(@interpret_threaded, %DOUBLE), i8* blockaddress(@interpret_threaded, %SWAPWORD)] ; <[5 x i8*]*> [#uses=5]
[email protected] = appending global [1 x i8*] [i8* bitcast (i32 (i8*)* @interpret_threaded to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define arm_apcscc i32 @interpret_threaded(i8* nocapture %opcodes) nounwind readonly optsize {
+entry:
+ %0 = load i8* %opcodes, align 1 ; <i8> [#uses=1]
+ %1 = zext i8 %0 to i32 ; <i32> [#uses=1]
+ %2 = getelementptr inbounds [5 x i8*]* @codetable.2928, i32 0, i32 %1 ; <i8**> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb.backedge, %entry
+ %indvar = phi i32 [ %phitmp, %bb.backedge ], [ 1, %entry ] ; <i32> [#uses=2]
+ %gotovar.22.0.in = phi i8** [ %gotovar.22.0.in.be, %bb.backedge ], [ %2, %entry ] ; <i8**> [#uses=1]
+ %result.0 = phi i32 [ %result.0.be, %bb.backedge ], [ 0, %entry ] ; <i32> [#uses=6]
+ %opcodes_addr.0 = getelementptr i8* %opcodes, i32 %indvar ; <i8*> [#uses=4]
+ %gotovar.22.0 = load i8** %gotovar.22.0.in, align 4 ; <i8*> [#uses=1]
+ indirectbr i8* %gotovar.22.0, [label %RETURN, label %INCREMENT, label %DECREMENT, label %DOUBLE, label %SWAPWORD]
+
+RETURN: ; preds = %bb
+ ret i32 %result.0
+
+INCREMENT: ; preds = %bb
+ %3 = add nsw i32 %result.0, 1 ; <i32> [#uses=1]
+ %4 = load i8* %opcodes_addr.0, align 1 ; <i8> [#uses=1]
+ %5 = zext i8 %4 to i32 ; <i32> [#uses=1]
+ %6 = getelementptr inbounds [5 x i8*]* @codetable.2928, i32 0, i32 %5 ; <i8**> [#uses=1]
+ br label %bb.backedge
+
+bb.backedge: ; preds = %SWAPWORD, %DOUBLE, %DECREMENT, %INCREMENT
+ %gotovar.22.0.in.be = phi i8** [ %20, %SWAPWORD ], [ %14, %DOUBLE ], [ %10, %DECREMENT ], [ %6, %INCREMENT ] ; <i8**> [#uses=1]
+ %result.0.be = phi i32 [ %17, %SWAPWORD ], [ %11, %DOUBLE ], [ %7, %DECREMENT ], [ %3, %INCREMENT ] ; <i32> [#uses=1]
+ %phitmp = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br label %bb
+
+DECREMENT: ; preds = %bb
+ %7 = add i32 %result.0, -1 ; <i32> [#uses=1]
+ %8 = load i8* %opcodes_addr.0, align 1 ; <i8> [#uses=1]
+ %9 = zext i8 %8 to i32 ; <i32> [#uses=1]
+ %10 = getelementptr inbounds [5 x i8*]* @codetable.2928, i32 0, i32 %9 ; <i8**> [#uses=1]
+ br label %bb.backedge
+
+DOUBLE: ; preds = %bb
+ %11 = shl i32 %result.0, 1 ; <i32> [#uses=1]
+ %12 = load i8* %opcodes_addr.0, align 1 ; <i8> [#uses=1]
+ %13 = zext i8 %12 to i32 ; <i32> [#uses=1]
+ %14 = getelementptr inbounds [5 x i8*]* @codetable.2928, i32 0, i32 %13 ; <i8**> [#uses=1]
+ br label %bb.backedge
+
+SWAPWORD: ; preds = %bb
+ %15 = shl i32 %result.0, 16 ; <i32> [#uses=1]
+ %16 = ashr i32 %result.0, 16 ; <i32> [#uses=1]
+ %17 = or i32 %15, %16 ; <i32> [#uses=1]
+ %18 = load i8* %opcodes_addr.0, align 1 ; <i8> [#uses=1]
+ %19 = zext i8 %18 to i32 ; <i32> [#uses=1]
+ %20 = getelementptr inbounds [5 x i8*]* @codetable.2928, i32 0, i32 %19 ; <i8**> [#uses=1]
+ br label %bb.backedge
+}
diff --git a/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll b/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll
new file mode 100644
index 0000000..d676369
--- /dev/null
+++ b/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -regalloc=local -relocation-model=pic | FileCheck %s
+
+target triple = "thumbv6-apple-darwin10"
+
+@fred = internal global i32 0 ; <i32*> [#uses=1]
+
+define arm_apcscc void @foo() nounwind {
+entry:
+; CHECK: str r0, [sp]
+ %0 = call arm_apcscc i32 (...)* @bar() nounwind ; <i32> [#uses=1]
+; CHECK: blx _bar
+; CHECK: ldr r1, [sp]
+ store i32 %0, i32* @fred, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare arm_apcscc i32 @bar(...)
diff --git a/test/CodeGen/Thumb/asmprinter-bug.ll b/test/CodeGen/Thumb/asmprinter-bug.ll
new file mode 100644
index 0000000..1e3c070
--- /dev/null
+++ b/test/CodeGen/Thumb/asmprinter-bug.ll
@@ -0,0 +1,288 @@
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin10 | grep rsbs | grep {#0}
+
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+ %struct.adpcm_state = type { i16, i8 }
+@stepsizeTable = internal constant [89 x i32] [i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 16, i32 17, i32 19, i32 21, i32 23, i32 25, i32 28, i32 31, i32 34, i32 37, i32 41, i32 45, i32 50, i32 55, i32 60, i32 66, i32 73, i32 80, i32 88, i32 97, i32 107, i32 118, i32 130, i32 143, i32 157, i32 173, i32 190, i32 209, i32 230, i32 253, i32 279, i32 307, i32 337, i32 371, i32 408, i32 449, i32 494, i32 544, i32 598, i32 658, i32 724, i32 796, i32 876, i32 963, i32 1060, i32 1166, i32 1282, i32 1411, i32 1552, i32 1707, i32 1878, i32 2066, i32 2272, i32 2499, i32 2749, i32 3024, i32 3327, i32 3660, i32 4026, i32 4428, i32 4871, i32 5358, i32 5894, i32 6484, i32 7132, i32 7845, i32 8630, i32 9493, i32 10442, i32 11487, i32 12635, i32 13899, i32 15289, i32 16818, i32 18500, i32 20350, i32 22385, i32 24623, i32 27086, i32 29794, i32 32767] ; <[89 x i32]*> [#uses=4]
+@indexTable = internal constant [16 x i32] [i32 -1, i32 -1, i32 -1, i32 -1, i32 2, i32 4, i32 6, i32 8, i32 -1, i32 -1, i32 -1, i32 -1, i32 2, i32 4, i32 6, i32 8] ; <[16 x i32]*> [#uses=2]
+@abuf = common global [500 x i8] zeroinitializer ; <[500 x i8]*> [#uses=1]
[email protected] = private constant [11 x i8] c"input file\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[11 x i8]*> [#uses=1]
+@sbuf = common global [1000 x i16] zeroinitializer ; <[1000 x i16]*> [#uses=1]
+@state = common global %struct.adpcm_state zeroinitializer ; <%struct.adpcm_state*> [#uses=3]
+@__stderrp = external global %struct.FILE* ; <%struct.FILE**> [#uses=1]
[email protected] = private constant [28 x i8] c"Final valprev=%d, index=%d\0A\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[28 x i8]*> [#uses=1]
+
+define arm_apcscc void @adpcm_coder(i16* nocapture %indata, i8* nocapture %outdata, i32 %len, %struct.adpcm_state* nocapture %state) nounwind {
+entry:
+ %0 = getelementptr %struct.adpcm_state* %state, i32 0, i32 0 ; <i16*> [#uses=2]
+ %1 = load i16* %0, align 2 ; <i16> [#uses=1]
+ %2 = sext i16 %1 to i32 ; <i32> [#uses=2]
+ %3 = getelementptr %struct.adpcm_state* %state, i32 0, i32 1 ; <i8*> [#uses=2]
+ %4 = load i8* %3, align 2 ; <i8> [#uses=1]
+ %5 = sext i8 %4 to i32 ; <i32> [#uses=3]
+ %6 = getelementptr [89 x i32]* @stepsizeTable, i32 0, i32 %5 ; <i32*> [#uses=1]
+ %7 = load i32* %6, align 4 ; <i32> [#uses=1]
+ %8 = icmp sgt i32 %len, 0 ; <i1> [#uses=1]
+ br i1 %8, label %bb, label %bb27
+
+bb: ; preds = %bb25, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb25 ] ; <i32> [#uses=2]
+ %outp.136 = phi i8* [ %outdata, %entry ], [ %outp.0, %bb25 ] ; <i8*> [#uses=3]
+ %bufferstep.035 = phi i32 [ 1, %entry ], [ %tmp, %bb25 ] ; <i32> [#uses=3]
+ %outputbuffer.134 = phi i32 [ undef, %entry ], [ %outputbuffer.0, %bb25 ] ; <i32> [#uses=2]
+ %index.033 = phi i32 [ %5, %entry ], [ %index.2, %bb25 ] ; <i32> [#uses=1]
+ %valpred.132 = phi i32 [ %2, %entry ], [ %valpred.2, %bb25 ] ; <i32> [#uses=2]
+ %step.031 = phi i32 [ %7, %entry ], [ %36, %bb25 ] ; <i32> [#uses=5]
+ %inp.038 = getelementptr i16* %indata, i32 %indvar ; <i16*> [#uses=1]
+ %9 = load i16* %inp.038, align 2 ; <i16> [#uses=1]
+ %10 = sext i16 %9 to i32 ; <i32> [#uses=1]
+ %11 = sub i32 %10, %valpred.132 ; <i32> [#uses=3]
+ %12 = icmp slt i32 %11, 0 ; <i1> [#uses=1]
+ %iftmp.1.0 = select i1 %12, i32 8, i32 0 ; <i32> [#uses=2]
+ %13 = sub i32 0, %11 ; <i32> [#uses=1]
+ %14 = icmp eq i32 %iftmp.1.0, 0 ; <i1> [#uses=2]
+ %. = select i1 %14, i32 %11, i32 %13 ; <i32> [#uses=2]
+ %15 = ashr i32 %step.031, 3 ; <i32> [#uses=1]
+ %16 = icmp slt i32 %., %step.031 ; <i1> [#uses=2]
+ %delta.0 = select i1 %16, i32 0, i32 4 ; <i32> [#uses=2]
+ %17 = select i1 %16, i32 0, i32 %step.031 ; <i32> [#uses=2]
+ %diff.1 = sub i32 %., %17 ; <i32> [#uses=2]
+ %18 = ashr i32 %step.031, 1 ; <i32> [#uses=2]
+ %19 = icmp slt i32 %diff.1, %18 ; <i1> [#uses=2]
+ %20 = or i32 %delta.0, 2 ; <i32> [#uses=1]
+ %21 = select i1 %19, i32 %delta.0, i32 %20 ; <i32> [#uses=1]
+ %22 = select i1 %19, i32 0, i32 %18 ; <i32> [#uses=2]
+ %diff.2 = sub i32 %diff.1, %22 ; <i32> [#uses=1]
+ %23 = ashr i32 %step.031, 2 ; <i32> [#uses=2]
+ %24 = icmp slt i32 %diff.2, %23 ; <i1> [#uses=2]
+ %25 = zext i1 %24 to i32 ; <i32> [#uses=1]
+ %26 = select i1 %24, i32 0, i32 %23 ; <i32> [#uses=1]
+ %vpdiff.0 = add i32 %17, %15 ; <i32> [#uses=1]
+ %vpdiff.1 = add i32 %vpdiff.0, %22 ; <i32> [#uses=1]
+ %vpdiff.2 = add i32 %vpdiff.1, %26 ; <i32> [#uses=2]
+ %tmp30 = sub i32 0, %vpdiff.2 ; <i32> [#uses=1]
+ %valpred.0.p = select i1 %14, i32 %vpdiff.2, i32 %tmp30 ; <i32> [#uses=1]
+ %valpred.0 = add i32 %valpred.0.p, %valpred.132 ; <i32> [#uses=3]
+ %27 = icmp sgt i32 %valpred.0, 32767 ; <i1> [#uses=1]
+ br i1 %27, label %bb18, label %bb16
+
+bb16: ; preds = %bb
+ %28 = icmp slt i32 %valpred.0, -32768 ; <i1> [#uses=1]
+ br i1 %28, label %bb17, label %bb18
+
+bb17: ; preds = %bb16
+ br label %bb18
+
+bb18: ; preds = %bb17, %bb16, %bb
+ %valpred.2 = phi i32 [ -32768, %bb17 ], [ 32767, %bb ], [ %valpred.0, %bb16 ] ; <i32> [#uses=2]
+ %delta.1 = or i32 %21, %iftmp.1.0 ; <i32> [#uses=1]
+ %delta.2 = or i32 %delta.1, %25 ; <i32> [#uses=1]
+ %29 = xor i32 %delta.2, 1 ; <i32> [#uses=3]
+ %30 = getelementptr [16 x i32]* @indexTable, i32 0, i32 %29 ; <i32*> [#uses=1]
+ %31 = load i32* %30, align 4 ; <i32> [#uses=1]
+ %32 = add i32 %31, %index.033 ; <i32> [#uses=2]
+ %33 = icmp slt i32 %32, 0 ; <i1> [#uses=1]
+ %index.1 = select i1 %33, i32 0, i32 %32 ; <i32> [#uses=2]
+ %34 = icmp sgt i32 %index.1, 88 ; <i1> [#uses=1]
+ %index.2 = select i1 %34, i32 88, i32 %index.1 ; <i32> [#uses=3]
+ %35 = getelementptr [89 x i32]* @stepsizeTable, i32 0, i32 %index.2 ; <i32*> [#uses=1]
+ %36 = load i32* %35, align 4 ; <i32> [#uses=1]
+ %37 = icmp eq i32 %bufferstep.035, 0 ; <i1> [#uses=1]
+ br i1 %37, label %bb24, label %bb23
+
+bb23: ; preds = %bb18
+ %38 = shl i32 %29, 4 ; <i32> [#uses=1]
+ %39 = and i32 %38, 240 ; <i32> [#uses=1]
+ br label %bb25
+
+bb24: ; preds = %bb18
+ %40 = trunc i32 %29 to i8 ; <i8> [#uses=1]
+ %41 = and i8 %40, 15 ; <i8> [#uses=1]
+ %42 = trunc i32 %outputbuffer.134 to i8 ; <i8> [#uses=1]
+ %43 = or i8 %41, %42 ; <i8> [#uses=1]
+ store i8 %43, i8* %outp.136, align 1
+ %44 = getelementptr i8* %outp.136, i32 1 ; <i8*> [#uses=1]
+ br label %bb25
+
+bb25: ; preds = %bb24, %bb23
+ %outputbuffer.0 = phi i32 [ %39, %bb23 ], [ %outputbuffer.134, %bb24 ] ; <i32> [#uses=2]
+ %outp.0 = phi i8* [ %outp.136, %bb23 ], [ %44, %bb24 ] ; <i8*> [#uses=2]
+ %tmp = xor i32 %bufferstep.035, 1 ; <i32> [#uses=1]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %len ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb26.bb27_crit_edge, label %bb
+
+bb26.bb27_crit_edge: ; preds = %bb25
+ %phitmp44 = icmp eq i32 %bufferstep.035, 1 ; <i1> [#uses=1]
+ br label %bb27
+
+bb27: ; preds = %bb26.bb27_crit_edge, %entry
+ %outp.1.lcssa = phi i8* [ %outp.0, %bb26.bb27_crit_edge ], [ %outdata, %entry ] ; <i8*> [#uses=1]
+ %bufferstep.0.lcssa = phi i1 [ %phitmp44, %bb26.bb27_crit_edge ], [ false, %entry ] ; <i1> [#uses=1]
+ %outputbuffer.1.lcssa = phi i32 [ %outputbuffer.0, %bb26.bb27_crit_edge ], [ undef, %entry ] ; <i32> [#uses=1]
+ %index.0.lcssa = phi i32 [ %index.2, %bb26.bb27_crit_edge ], [ %5, %entry ] ; <i32> [#uses=1]
+ %valpred.1.lcssa = phi i32 [ %valpred.2, %bb26.bb27_crit_edge ], [ %2, %entry ] ; <i32> [#uses=1]
+ br i1 %bufferstep.0.lcssa, label %bb28, label %bb29
+
+bb28: ; preds = %bb27
+ %45 = trunc i32 %outputbuffer.1.lcssa to i8 ; <i8> [#uses=1]
+ store i8 %45, i8* %outp.1.lcssa, align 1
+ br label %bb29
+
+bb29: ; preds = %bb28, %bb27
+ %46 = trunc i32 %valpred.1.lcssa to i16 ; <i16> [#uses=1]
+ store i16 %46, i16* %0, align 2
+ %47 = trunc i32 %index.0.lcssa to i8 ; <i8> [#uses=1]
+ store i8 %47, i8* %3, align 2
+ ret void
+}
+
+define arm_apcscc void @adpcm_decoder(i8* nocapture %indata, i16* nocapture %outdata, i32 %len, %struct.adpcm_state* nocapture %state) nounwind {
+entry:
+ %0 = getelementptr %struct.adpcm_state* %state, i32 0, i32 0 ; <i16*> [#uses=2]
+ %1 = load i16* %0, align 2 ; <i16> [#uses=1]
+ %2 = sext i16 %1 to i32 ; <i32> [#uses=2]
+ %3 = getelementptr %struct.adpcm_state* %state, i32 0, i32 1 ; <i8*> [#uses=2]
+ %4 = load i8* %3, align 2 ; <i8> [#uses=1]
+ %5 = sext i8 %4 to i32 ; <i32> [#uses=3]
+ %6 = getelementptr [89 x i32]* @stepsizeTable, i32 0, i32 %5 ; <i32*> [#uses=1]
+ %7 = load i32* %6, align 4 ; <i32> [#uses=1]
+ %8 = icmp sgt i32 %len, 0 ; <i1> [#uses=1]
+ br i1 %8, label %bb, label %bb22
+
+bb: ; preds = %bb20, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb20 ] ; <i32> [#uses=2]
+ %inp.131 = phi i8* [ %indata, %entry ], [ %inp.0, %bb20 ] ; <i8*> [#uses=3]
+ %bufferstep.028 = phi i32 [ 0, %entry ], [ %tmp, %bb20 ] ; <i32> [#uses=2]
+ %inputbuffer.127 = phi i32 [ undef, %entry ], [ %inputbuffer.0, %bb20 ] ; <i32> [#uses=2]
+ %index.026 = phi i32 [ %5, %entry ], [ %index.2, %bb20 ] ; <i32> [#uses=1]
+ %valpred.125 = phi i32 [ %2, %entry ], [ %valpred.2, %bb20 ] ; <i32> [#uses=1]
+ %step.024 = phi i32 [ %7, %entry ], [ %35, %bb20 ] ; <i32> [#uses=4]
+ %outp.030 = getelementptr i16* %outdata, i32 %indvar ; <i16*> [#uses=1]
+ %9 = icmp eq i32 %bufferstep.028, 0 ; <i1> [#uses=1]
+ br i1 %9, label %bb2, label %bb3
+
+bb2: ; preds = %bb
+ %10 = load i8* %inp.131, align 1 ; <i8> [#uses=1]
+ %11 = sext i8 %10 to i32 ; <i32> [#uses=2]
+ %12 = getelementptr i8* %inp.131, i32 1 ; <i8*> [#uses=1]
+ %13 = ashr i32 %11, 4 ; <i32> [#uses=1]
+ br label %bb3
+
+bb3: ; preds = %bb2, %bb
+ %inputbuffer.0 = phi i32 [ %11, %bb2 ], [ %inputbuffer.127, %bb ] ; <i32> [#uses=1]
+ %delta.0.in = phi i32 [ %13, %bb2 ], [ %inputbuffer.127, %bb ] ; <i32> [#uses=5]
+ %inp.0 = phi i8* [ %12, %bb2 ], [ %inp.131, %bb ] ; <i8*> [#uses=1]
+ %delta.0 = and i32 %delta.0.in, 15 ; <i32> [#uses=1]
+ %tmp = xor i32 %bufferstep.028, 1 ; <i32> [#uses=1]
+ %14 = getelementptr [16 x i32]* @indexTable, i32 0, i32 %delta.0 ; <i32*> [#uses=1]
+ %15 = load i32* %14, align 4 ; <i32> [#uses=1]
+ %16 = add i32 %15, %index.026 ; <i32> [#uses=2]
+ %17 = icmp slt i32 %16, 0 ; <i1> [#uses=1]
+ %index.1 = select i1 %17, i32 0, i32 %16 ; <i32> [#uses=2]
+ %18 = icmp sgt i32 %index.1, 88 ; <i1> [#uses=1]
+ %index.2 = select i1 %18, i32 88, i32 %index.1 ; <i32> [#uses=3]
+ %19 = and i32 %delta.0.in, 8 ; <i32> [#uses=1]
+ %20 = ashr i32 %step.024, 3 ; <i32> [#uses=1]
+ %21 = and i32 %delta.0.in, 4 ; <i32> [#uses=1]
+ %22 = icmp eq i32 %21, 0 ; <i1> [#uses=1]
+ %23 = select i1 %22, i32 0, i32 %step.024 ; <i32> [#uses=1]
+ %vpdiff.0 = add i32 %23, %20 ; <i32> [#uses=2]
+ %24 = and i32 %delta.0.in, 2 ; <i32> [#uses=1]
+ %25 = icmp eq i32 %24, 0 ; <i1> [#uses=1]
+ br i1 %25, label %bb11, label %bb10
+
+bb10: ; preds = %bb3
+ %26 = ashr i32 %step.024, 1 ; <i32> [#uses=1]
+ %27 = add i32 %vpdiff.0, %26 ; <i32> [#uses=1]
+ br label %bb11
+
+bb11: ; preds = %bb10, %bb3
+ %vpdiff.1 = phi i32 [ %27, %bb10 ], [ %vpdiff.0, %bb3 ] ; <i32> [#uses=2]
+ %28 = and i32 %delta.0.in, 1 ; <i32> [#uses=1]
+ %toBool = icmp eq i32 %28, 0 ; <i1> [#uses=1]
+ br i1 %toBool, label %bb13, label %bb12
+
+bb12: ; preds = %bb11
+ %29 = ashr i32 %step.024, 2 ; <i32> [#uses=1]
+ %30 = add i32 %vpdiff.1, %29 ; <i32> [#uses=1]
+ br label %bb13
+
+bb13: ; preds = %bb12, %bb11
+ %vpdiff.2 = phi i32 [ %30, %bb12 ], [ %vpdiff.1, %bb11 ] ; <i32> [#uses=2]
+ %31 = icmp eq i32 %19, 0 ; <i1> [#uses=1]
+ %tmp23 = sub i32 0, %vpdiff.2 ; <i32> [#uses=1]
+ %valpred.0.p = select i1 %31, i32 %vpdiff.2, i32 %tmp23 ; <i32> [#uses=1]
+ %valpred.0 = add i32 %valpred.0.p, %valpred.125 ; <i32> [#uses=3]
+ %32 = icmp sgt i32 %valpred.0, 32767 ; <i1> [#uses=1]
+ br i1 %32, label %bb20, label %bb18
+
+bb18: ; preds = %bb13
+ %33 = icmp slt i32 %valpred.0, -32768 ; <i1> [#uses=1]
+ br i1 %33, label %bb19, label %bb20
+
+bb19: ; preds = %bb18
+ br label %bb20
+
+bb20: ; preds = %bb19, %bb18, %bb13
+ %valpred.2 = phi i32 [ -32768, %bb19 ], [ 32767, %bb13 ], [ %valpred.0, %bb18 ] ; <i32> [#uses=3]
+ %34 = getelementptr [89 x i32]* @stepsizeTable, i32 0, i32 %index.2 ; <i32*> [#uses=1]
+ %35 = load i32* %34, align 4 ; <i32> [#uses=1]
+ %36 = trunc i32 %valpred.2 to i16 ; <i16> [#uses=1]
+ store i16 %36, i16* %outp.030, align 2
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %len ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb22, label %bb
+
+bb22: ; preds = %bb20, %entry
+ %index.0.lcssa = phi i32 [ %5, %entry ], [ %index.2, %bb20 ] ; <i32> [#uses=1]
+ %valpred.1.lcssa = phi i32 [ %2, %entry ], [ %valpred.2, %bb20 ] ; <i32> [#uses=1]
+ %37 = trunc i32 %valpred.1.lcssa to i16 ; <i16> [#uses=1]
+ store i16 %37, i16* %0, align 2
+ %38 = trunc i32 %index.0.lcssa to i8 ; <i8> [#uses=1]
+ store i8 %38, i8* %3, align 2
+ ret void
+}
+
+define arm_apcscc i32 @main() nounwind {
+entry:
+ br label %bb
+
+bb: ; preds = %bb3, %entry
+ %0 = tail call arm_apcscc i32 (...)* @read(i32 0, i8* getelementptr ([500 x i8]* @abuf, i32 0, i32 0), i32 500) nounwind ; <i32> [#uses=4]
+ %1 = icmp slt i32 %0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %bb1, label %bb2
+
+bb1: ; preds = %bb
+ tail call arm_apcscc void @perror(i8* getelementptr ([11 x i8]* @.str, i32 0, i32 0)) nounwind
+ ret i32 1
+
+bb2: ; preds = %bb
+ %2 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
+ br i1 %2, label %bb4, label %bb3
+
+bb3: ; preds = %bb2
+ %3 = shl i32 %0, 1 ; <i32> [#uses=1]
+ tail call arm_apcscc void @adpcm_decoder(i8* getelementptr ([500 x i8]* @abuf, i32 0, i32 0), i16* getelementptr ([1000 x i16]* @sbuf, i32 0, i32 0), i32 %3, %struct.adpcm_state* @state) nounwind
+ %4 = shl i32 %0, 2 ; <i32> [#uses=1]
+ %5 = tail call arm_apcscc i32 (...)* @write(i32 1, i16* getelementptr ([1000 x i16]* @sbuf, i32 0, i32 0), i32 %4) nounwind ; <i32> [#uses=0]
+ br label %bb
+
+bb4: ; preds = %bb2
+ %6 = load %struct.FILE** @__stderrp, align 4 ; <%struct.FILE*> [#uses=1]
+ %7 = load i16* getelementptr (%struct.adpcm_state* @state, i32 0, i32 0), align 4 ; <i16> [#uses=1]
+ %8 = sext i16 %7 to i32 ; <i32> [#uses=1]
+ %9 = load i8* getelementptr (%struct.adpcm_state* @state, i32 0, i32 1), align 2 ; <i8> [#uses=1]
+ %10 = sext i8 %9 to i32 ; <i32> [#uses=1]
+ %11 = tail call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %6, i8* getelementptr ([28 x i8]* @.str1, i32 0, i32 0), i32 %8, i32 %10) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
+
+declare arm_apcscc i32 @read(...)
+
+declare arm_apcscc void @perror(i8* nocapture) nounwind
+
+declare arm_apcscc i32 @write(...)
+
+declare arm_apcscc i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind
diff --git a/test/CodeGen/Thumb/dg.exp b/test/CodeGen/Thumb/dg.exp
new file mode 100644
index 0000000..3ff359a
--- /dev/null
+++ b/test/CodeGen/Thumb/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target ARM] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/Thumb/dyn-stackalloc.ll b/test/CodeGen/Thumb/dyn-stackalloc.ll
new file mode 100644
index 0000000..acfdc91
--- /dev/null
+++ b/test/CodeGen/Thumb/dyn-stackalloc.ll
@@ -0,0 +1,59 @@
+; RUN: llc < %s -march=thumb | not grep {ldr sp}
+; RUN: llc < %s -mtriple=thumb-apple-darwin | \
+; RUN: not grep {sub.*r7}
+; RUN: llc < %s -march=thumb | grep 4294967280
+
+ %struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
+ %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
+
+define void @t1(%struct.state* %v) {
+ %tmp6 = load i32* null
+ %tmp8 = alloca float, i32 %tmp6
+ store i32 1, i32* null
+ br i1 false, label %bb123.preheader, label %return
+
+bb123.preheader:
+ br i1 false, label %bb43, label %return
+
+bb43:
+ call fastcc void @f1( float* %tmp8, float* null, i32 0 )
+ %tmp70 = load i32* null
+ %tmp85 = getelementptr float* %tmp8, i32 0
+ call fastcc void @f2( float* null, float* null, float* %tmp85, i32 %tmp70 )
+ ret void
+
+return:
+ ret void
+}
+
+declare fastcc void @f1(float*, float*, i32)
+
+declare fastcc void @f2(float*, float*, float*, i32)
+
+ %struct.comment = type { i8**, i32*, i32, i8* }
+@str215 = external global [2 x i8]
+
+define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) {
+ %tmp1 = call i32 @strlen( i8* %tag )
+ %tmp3 = call i32 @strlen( i8* %contents )
+ %tmp4 = add i32 %tmp1, 2
+ %tmp5 = add i32 %tmp4, %tmp3
+ %tmp6 = alloca i8, i32 %tmp5
+ %tmp9 = call i8* @strcpy( i8* %tmp6, i8* %tag )
+ %tmp6.len = call i32 @strlen( i8* %tmp6 )
+ %tmp6.indexed = getelementptr i8* %tmp6, i32 %tmp6.len
+ call void @llvm.memcpy.i32( i8* %tmp6.indexed, i8* getelementptr ([2 x i8]* @str215, i32 0, i32 0), i32 2, i32 1 )
+ %tmp15 = call i8* @strcat( i8* %tmp6, i8* %contents )
+ call fastcc void @comment_add( %struct.comment* %vc, i8* %tmp6 )
+ ret void
+}
+
+declare i32 @strlen(i8*)
+
+declare i8* @strcat(i8*, i8*)
+
+declare fastcc void @comment_add(%struct.comment*, i8*)
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32)
+
+declare i8* @strcpy(i8*, i8*)
diff --git a/test/CodeGen/Thumb/fpconv.ll b/test/CodeGen/Thumb/fpconv.ll
new file mode 100644
index 0000000..7da36ddf
--- /dev/null
+++ b/test/CodeGen/Thumb/fpconv.ll
@@ -0,0 +1,61 @@
+; RUN: llc < %s -march=thumb
+
+define float @f1(double %x) {
+entry:
+ %tmp1 = fptrunc double %x to float ; <float> [#uses=1]
+ ret float %tmp1
+}
+
+define double @f2(float %x) {
+entry:
+ %tmp1 = fpext float %x to double ; <double> [#uses=1]
+ ret double %tmp1
+}
+
+define i32 @f3(float %x) {
+entry:
+ %tmp = fptosi float %x to i32 ; <i32> [#uses=1]
+ ret i32 %tmp
+}
+
+define i32 @f4(float %x) {
+entry:
+ %tmp = fptoui float %x to i32 ; <i32> [#uses=1]
+ ret i32 %tmp
+}
+
+define i32 @f5(double %x) {
+entry:
+ %tmp = fptosi double %x to i32 ; <i32> [#uses=1]
+ ret i32 %tmp
+}
+
+define i32 @f6(double %x) {
+entry:
+ %tmp = fptoui double %x to i32 ; <i32> [#uses=1]
+ ret i32 %tmp
+}
+
+define float @f7(i32 %a) {
+entry:
+ %tmp = sitofp i32 %a to float ; <float> [#uses=1]
+ ret float %tmp
+}
+
+define double @f8(i32 %a) {
+entry:
+ %tmp = sitofp i32 %a to double ; <double> [#uses=1]
+ ret double %tmp
+}
+
+define float @f9(i32 %a) {
+entry:
+ %tmp = uitofp i32 %a to float ; <float> [#uses=1]
+ ret float %tmp
+}
+
+define double @f10(i32 %a) {
+entry:
+ %tmp = uitofp i32 %a to double ; <double> [#uses=1]
+ ret double %tmp
+}
diff --git a/test/CodeGen/Thumb/fpow.ll b/test/CodeGen/Thumb/fpow.ll
new file mode 100644
index 0000000..be3dc0b
--- /dev/null
+++ b/test/CodeGen/Thumb/fpow.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=thumb
+
+define double @t(double %x, double %y) nounwind optsize {
+entry:
+ %0 = tail call double @llvm.pow.f64( double %x, double %y ) ; <double> [#uses=1]
+ ret double %0
+}
+
+declare double @llvm.pow.f64(double, double) nounwind readonly
diff --git a/test/CodeGen/Thumb/frame_thumb.ll b/test/CodeGen/Thumb/frame_thumb.ll
new file mode 100644
index 0000000..0cac755
--- /dev/null
+++ b/test/CodeGen/Thumb/frame_thumb.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=thumb-apple-darwin \
+; RUN: -disable-fp-elim | not grep {r11}
+; RUN: llc < %s -mtriple=thumb-linux-gnueabi \
+; RUN: -disable-fp-elim | not grep {r11}
+
+define i32 @f() {
+entry:
+ ret i32 10
+}
diff --git a/test/CodeGen/Thumb/iabs.ll b/test/CodeGen/Thumb/iabs.ll
new file mode 100644
index 0000000..d7cdcd8
--- /dev/null
+++ b/test/CodeGen/Thumb/iabs.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=thumb -stats |& \
+; RUN: grep {4 .*Number of machine instrs printed}
+
+;; Integer absolute value, should produce something as good as:
+;; Thumb:
+;; asr r2, r0, #31
+;; add r0, r0, r2
+;; eor r0, r2
+;; bx lr
+
+define i32 @test(i32 %a) {
+ %tmp1neg = sub i32 0, %a
+ %b = icmp sgt i32 %a, -1
+ %abs = select i1 %b, i32 %a, i32 %tmp1neg
+ ret i32 %abs
+}
+
diff --git a/test/CodeGen/Thumb/inlineasm-imm-thumb.ll b/test/CodeGen/Thumb/inlineasm-imm-thumb.ll
new file mode 100644
index 0000000..5c8a52a
--- /dev/null
+++ b/test/CodeGen/Thumb/inlineasm-imm-thumb.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -march=thumb
+
+; Test Thumb-mode "I" constraint, for ADD immediate.
+define i32 @testI(i32 %x) {
+ %y = call i32 asm "add $0, $1, $2", "=r,r,I"( i32 %x, i32 255 ) nounwind
+ ret i32 %y
+}
+
+; Test Thumb-mode "J" constraint, for negated ADD immediates.
+define void @testJ() {
+ tail call void asm sideeffect ".word $0", "J"( i32 -255 ) nounwind
+ ret void
+}
+
+; Test Thumb-mode "K" constraint, for compatibility with GCC's internal use.
+define void @testK() {
+ tail call void asm sideeffect ".word $0", "K"( i32 65280 ) nounwind
+ ret void
+}
+
+; Test Thumb-mode "L" constraint, for 3-operand ADD immediates.
+define i32 @testL(i32 %x) {
+ %y = call i32 asm "add $0, $1, $2", "=r,r,L"( i32 %x, i32 -7 ) nounwind
+ ret i32 %y
+}
+
+; Test Thumb-mode "M" constraint, for "ADD r = sp + imm".
+define i32 @testM() {
+ %y = call i32 asm "add $0, sp, $1", "=r,M"( i32 1020 ) nounwind
+ ret i32 %y
+}
+
+; Test Thumb-mode "N" constraint, for values between 0 and 31.
+define i32 @testN(i32 %x) {
+ %y = call i32 asm "lsl $0, $1, $2", "=r,r,N"( i32 %x, i32 31 ) nounwind
+ ret i32 %y
+}
+
+; Test Thumb-mode "O" constraint, for "ADD sp = sp + imm".
+define void @testO() {
+ tail call void asm sideeffect "add sp, sp, $0; add sp, sp, $1", "O,O"( i32 -508, i32 508 ) nounwind
+ ret void
+}
diff --git a/test/CodeGen/Thumb/ispositive.ll b/test/CodeGen/Thumb/ispositive.ll
new file mode 100644
index 0000000..eac3ef2
--- /dev/null
+++ b/test/CodeGen/Thumb/ispositive.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=thumb | FileCheck %s
+
+define i32 @test1(i32 %X) {
+entry:
+; CHECK: test1:
+; CHECK: lsrs r0, r0, #31
+ icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]
+ zext i1 %0 to i32 ; <i32>:1 [#uses=1]
+ ret i32 %1
+}
+
diff --git a/test/CodeGen/Thumb/large-stack.ll b/test/CodeGen/Thumb/large-stack.ll
new file mode 100644
index 0000000..02de36a
--- /dev/null
+++ b/test/CodeGen/Thumb/large-stack.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=thumb | grep {ldr.*LCP} | count 5
+
+define void @test1() {
+ %tmp = alloca [ 64 x i32 ] , align 4
+ ret void
+}
+
+define void @test2() {
+ %tmp = alloca [ 4168 x i8 ] , align 4
+ ret void
+}
+
+define i32 @test3() {
+ %retval = alloca i32, align 4
+ %tmp = alloca i32, align 4
+ %a = alloca [805306369 x i8], align 16
+ store i32 0, i32* %tmp
+ %tmp1 = load i32* %tmp
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/Thumb/ldr_ext.ll b/test/CodeGen/Thumb/ldr_ext.ll
new file mode 100644
index 0000000..9a28124
--- /dev/null
+++ b/test/CodeGen/Thumb/ldr_ext.ll
@@ -0,0 +1,57 @@
+; RUN: llc < %s -march=thumb | FileCheck %s -check-prefix=V5
+; RUN: llc < %s -march=thumb -mattr=+v6 | FileCheck %s -check-prefix=V6
+
+; rdar://7176514
+
+define i32 @test1(i8* %t1) nounwind {
+; V5: ldrb
+
+; V6: ldrb
+ %tmp.u = load i8* %t1
+ %tmp1.s = zext i8 %tmp.u to i32
+ ret i32 %tmp1.s
+}
+
+define i32 @test2(i16* %t1) nounwind {
+; V5: ldrh
+
+; V6: ldrh
+ %tmp.u = load i16* %t1
+ %tmp1.s = zext i16 %tmp.u to i32
+ ret i32 %tmp1.s
+}
+
+define i32 @test3(i8* %t0) nounwind {
+; V5: ldrb
+; V5: lsls
+; V5: asrs
+
+; V6: ldrb
+; V6: sxtb
+ %tmp.s = load i8* %t0
+ %tmp1.s = sext i8 %tmp.s to i32
+ ret i32 %tmp1.s
+}
+
+define i32 @test4(i16* %t0) nounwind {
+; V5: ldrh
+; V5: lsls
+; V5: asrs
+
+; V6: ldrh
+; V6: sxth
+ %tmp.s = load i16* %t0
+ %tmp1.s = sext i16 %tmp.s to i32
+ ret i32 %tmp1.s
+}
+
+define i32 @test5() nounwind {
+; V5: movs r0, #0
+; V5: ldrsh
+
+; V6: movs r0, #0
+; V6: ldrsh
+ %tmp.s = load i16* null
+ %tmp1.s = sext i16 %tmp.s to i32
+ ret i32 %tmp1.s
+}
diff --git a/test/CodeGen/Thumb/ldr_frame.ll b/test/CodeGen/Thumb/ldr_frame.ll
new file mode 100644
index 0000000..81782cd
--- /dev/null
+++ b/test/CodeGen/Thumb/ldr_frame.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -march=thumb | FileCheck %s
+
+define i32 @f1() {
+; CHECK: f1:
+; CHECK: ldr r0
+ %buf = alloca [32 x i32], align 4
+ %tmp = getelementptr [32 x i32]* %buf, i32 0, i32 0
+ %tmp1 = load i32* %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f2() {
+; CHECK: f2:
+; CHECK: mov r0
+; CHECK: ldrb
+ %buf = alloca [32 x i8], align 4
+ %tmp = getelementptr [32 x i8]* %buf, i32 0, i32 0
+ %tmp1 = load i8* %tmp
+ %tmp2 = zext i8 %tmp1 to i32
+ ret i32 %tmp2
+}
+
+define i32 @f3() {
+; CHECK: f3:
+; CHECK: ldr r0
+ %buf = alloca [32 x i32], align 4
+ %tmp = getelementptr [32 x i32]* %buf, i32 0, i32 32
+ %tmp1 = load i32* %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f4() {
+; CHECK: f4:
+; CHECK: mov r0
+; CHECK: ldrb
+ %buf = alloca [32 x i8], align 4
+ %tmp = getelementptr [32 x i8]* %buf, i32 0, i32 2
+ %tmp1 = load i8* %tmp
+ %tmp2 = zext i8 %tmp1 to i32
+ ret i32 %tmp2
+}
diff --git a/test/CodeGen/Thumb/long-setcc.ll b/test/CodeGen/Thumb/long-setcc.ll
new file mode 100644
index 0000000..8f2d98f
--- /dev/null
+++ b/test/CodeGen/Thumb/long-setcc.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=thumb | grep cmp | count 1
+
+
+define i1 @t1(i64 %x) {
+ %B = icmp slt i64 %x, 0
+ ret i1 %B
+}
+
+define i1 @t2(i64 %x) {
+ %tmp = icmp ult i64 %x, 4294967296
+ ret i1 %tmp
+}
+
+define i1 @t3(i32 %x) {
+ %tmp = icmp ugt i32 %x, -1
+ ret i1 %tmp
+}
diff --git a/test/CodeGen/Thumb/long.ll b/test/CodeGen/Thumb/long.ll
new file mode 100644
index 0000000..e3ef44a
--- /dev/null
+++ b/test/CodeGen/Thumb/long.ll
@@ -0,0 +1,76 @@
+; RUN: llc < %s -march=thumb | \
+; RUN: grep mvn | count 1
+; RUN: llc < %s -march=thumb | \
+; RUN: grep adc | count 1
+; RUN: llc < %s -march=thumb | \
+; RUN: grep sbc | count 1
+; RUN: llc < %s -march=thumb | grep __muldi3
+
+define i64 @f1() {
+entry:
+ ret i64 0
+}
+
+define i64 @f2() {
+entry:
+ ret i64 1
+}
+
+define i64 @f3() {
+entry:
+ ret i64 2147483647
+}
+
+define i64 @f4() {
+entry:
+ ret i64 2147483648
+}
+
+define i64 @f5() {
+entry:
+ ret i64 9223372036854775807
+}
+
+define i64 @f6(i64 %x, i64 %y) {
+entry:
+ %tmp1 = add i64 %y, 1 ; <i64> [#uses=1]
+ ret i64 %tmp1
+}
+
+define void @f7() {
+entry:
+ %tmp = call i64 @f8( ) ; <i64> [#uses=0]
+ ret void
+}
+
+declare i64 @f8()
+
+define i64 @f9(i64 %a, i64 %b) {
+entry:
+ %tmp = sub i64 %a, %b ; <i64> [#uses=1]
+ ret i64 %tmp
+}
+
+define i64 @f(i32 %a, i32 %b) {
+entry:
+ %tmp = sext i32 %a to i64 ; <i64> [#uses=1]
+ %tmp1 = sext i32 %b to i64 ; <i64> [#uses=1]
+ %tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
+ ret i64 %tmp2
+}
+
+define i64 @g(i32 %a, i32 %b) {
+entry:
+ %tmp = zext i32 %a to i64 ; <i64> [#uses=1]
+ %tmp1 = zext i32 %b to i64 ; <i64> [#uses=1]
+ %tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
+ ret i64 %tmp2
+}
+
+define i64 @f10() {
+entry:
+ %a = alloca i64, align 8 ; <i64*> [#uses=1]
+ %retval = load i64* %a ; <i64> [#uses=1]
+ ret i64 %retval
+}
+
diff --git a/test/CodeGen/Thumb/long_shift.ll b/test/CodeGen/Thumb/long_shift.ll
new file mode 100644
index 0000000..2431714
--- /dev/null
+++ b/test/CodeGen/Thumb/long_shift.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=thumb
+
+define i64 @f0(i64 %A, i64 %B) {
+ %tmp = bitcast i64 %A to i64
+ %tmp2 = lshr i64 %B, 1
+ %tmp3 = sub i64 %tmp, %tmp2
+ ret i64 %tmp3
+}
+
+define i32 @f1(i64 %x, i64 %y) {
+ %a = shl i64 %x, %y
+ %b = trunc i64 %a to i32
+ ret i32 %b
+}
+
+define i32 @f2(i64 %x, i64 %y) {
+ %a = ashr i64 %x, %y
+ %b = trunc i64 %a to i32
+ ret i32 %b
+}
+
+define i32 @f3(i64 %x, i64 %y) {
+ %a = lshr i64 %x, %y
+ %b = trunc i64 %a to i32
+ ret i32 %b
+}
diff --git a/test/CodeGen/Thumb/machine-licm.ll b/test/CodeGen/Thumb/machine-licm.ll
new file mode 100644
index 0000000..dae1412
--- /dev/null
+++ b/test/CodeGen/Thumb/machine-licm.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s
+; rdar://7353541
+; rdar://7354376
+
+; The generated code is no where near ideal. It's not recognizing the two
+; constantpool entries being loaded can be merged into one.
+
+@GV = external global i32 ; <i32*> [#uses=2]
+
+define arm_apcscc void @t(i32* nocapture %vals, i32 %c) nounwind {
+entry:
+; CHECK: t:
+ %0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
+ br i1 %0, label %return, label %bb.nph
+
+bb.nph: ; preds = %entry
+; CHECK: BB#1
+; CHECK: ldr.n r2, LCPI1_0
+; CHECK: add r2, pc
+; CHECK: ldr r{{[0-9]+}}, [r2]
+; CHECK: LBB1_2
+; CHECK: LCPI1_0:
+; CHECK-NOT: LCPI1_1:
+; CHECK: .section
+ %.pre = load i32* @GV, align 4 ; <i32> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %bb.nph
+ %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; <i32> [#uses=1]
+ %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; <i32> [#uses=2]
+ %scevgep = getelementptr i32* %vals, i32 %i.03 ; <i32*> [#uses=1]
+ %2 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
+ %3 = add nsw i32 %1, %2 ; <i32> [#uses=2]
+ store i32 %3, i32* @GV, align 4
+ %4 = add i32 %i.03, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %4, %c ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ ret void
+}
diff --git a/test/CodeGen/Thumb/mul.ll b/test/CodeGen/Thumb/mul.ll
new file mode 100644
index 0000000..c1a2fb2
--- /dev/null
+++ b/test/CodeGen/Thumb/mul.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=thumb | grep mul | count 3
+; RUN: llc < %s -march=thumb | grep lsl | count 1
+
+define i32 @f1(i32 %u) {
+ %tmp = mul i32 %u, %u
+ ret i32 %tmp
+}
+
+define i32 @f2(i32 %u, i32 %v) {
+ %tmp = mul i32 %u, %v
+ ret i32 %tmp
+}
+
+define i32 @f3(i32 %u) {
+ %tmp = mul i32 %u, 5
+ ret i32 %tmp
+}
+
+define i32 @f4(i32 %u) {
+ %tmp = mul i32 %u, 4
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb/pop.ll b/test/CodeGen/Thumb/pop.ll
new file mode 100644
index 0000000..0e1b2e5
--- /dev/null
+++ b/test/CodeGen/Thumb/pop.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
+; rdar://7268481
+
+define arm_apcscc void @t(i8* %a, ...) nounwind {
+; CHECK: t:
+; CHECK: pop {r3}
+; CHECK-NEXT: add sp, #12
+; CHECK-NEXT: bx r3
+entry:
+ %a.addr = alloca i8*
+ store i8* %a, i8** %a.addr
+ ret void
+}
diff --git a/test/CodeGen/Thumb/push.ll b/test/CodeGen/Thumb/push.ll
new file mode 100644
index 0000000..63773c4
--- /dev/null
+++ b/test/CodeGen/Thumb/push.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-fp-elim | FileCheck %s
+; rdar://7268481
+
+define arm_apcscc void @t() nounwind {
+; CHECK: t:
+; CHECK-NEXT : push {r7}
+entry:
+ call void asm sideeffect ".long 0xe7ffdefe", ""() nounwind
+ ret void
+}
diff --git a/test/CodeGen/Thumb/select.ll b/test/CodeGen/Thumb/select.ll
new file mode 100644
index 0000000..7a183b0
--- /dev/null
+++ b/test/CodeGen/Thumb/select.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -march=thumb | grep beq | count 1
+; RUN: llc < %s -march=thumb | grep bgt | count 1
+; RUN: llc < %s -march=thumb | grep blt | count 3
+; RUN: llc < %s -march=thumb | grep ble | count 1
+; RUN: llc < %s -march=thumb | grep bls | count 1
+; RUN: llc < %s -march=thumb | grep bhi | count 1
+; RUN: llc < %s -march=thumb | grep __ltdf2
+
+define i32 @f1(i32 %a.s) {
+entry:
+ %tmp = icmp eq i32 %a.s, 4
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f2(i32 %a.s) {
+entry:
+ %tmp = icmp sgt i32 %a.s, 4
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f3(i32 %a.s, i32 %b.s) {
+entry:
+ %tmp = icmp slt i32 %a.s, %b.s
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f4(i32 %a.s, i32 %b.s) {
+entry:
+ %tmp = icmp sle i32 %a.s, %b.s
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f5(i32 %a.u, i32 %b.u) {
+entry:
+ %tmp = icmp ule i32 %a.u, %b.u
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f6(i32 %a.u, i32 %b.u) {
+entry:
+ %tmp = icmp ugt i32 %a.u, %b.u
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define double @f7(double %a, double %b) {
+ %tmp = fcmp olt double %a, 1.234e+00
+ %tmp1 = select i1 %tmp, double -1.000e+00, double %b
+ ret double %tmp1
+}
diff --git a/test/CodeGen/Thumb/stack-frame.ll b/test/CodeGen/Thumb/stack-frame.ll
new file mode 100644
index 0000000..b103b33
--- /dev/null
+++ b/test/CodeGen/Thumb/stack-frame.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=thumb
+; RUN: llc < %s -march=thumb | grep add | count 1
+
+define void @f1() {
+ %c = alloca i8, align 1
+ ret void
+}
+
+define i32 @f2() {
+ ret i32 1
+}
+
+
diff --git a/test/CodeGen/Thumb/thumb-imm.ll b/test/CodeGen/Thumb/thumb-imm.ll
new file mode 100644
index 0000000..74a57ff
--- /dev/null
+++ b/test/CodeGen/Thumb/thumb-imm.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=thumb | not grep CPI
+
+
+define i32 @test1() {
+ ret i32 1000
+}
+
+define i32 @test2() {
+ ret i32 -256
+}
diff --git a/test/CodeGen/Thumb/tst_teq.ll b/test/CodeGen/Thumb/tst_teq.ll
new file mode 100644
index 0000000..21ada3e
--- /dev/null
+++ b/test/CodeGen/Thumb/tst_teq.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=thumb | grep tst
+
+define i32 @f(i32 %a) {
+entry:
+ %tmp2 = and i32 %a, 255 ; <i32> [#uses=1]
+ icmp eq i32 %tmp2, 0 ; <i1>:0 [#uses=1]
+ %retval = select i1 %0, i32 20, i32 10 ; <i32> [#uses=1]
+ ret i32 %retval
+}
+
+define i32 @g(i32 %a) {
+entry:
+ %tmp2 = xor i32 %a, 255
+ icmp eq i32 %tmp2, 0 ; <i1>:0 [#uses=1]
+ %retval = select i1 %0, i32 20, i32 10 ; <i32> [#uses=1]
+ ret i32 %retval
+}
diff --git a/test/CodeGen/Thumb/unord.ll b/test/CodeGen/Thumb/unord.ll
new file mode 100644
index 0000000..39458ae
--- /dev/null
+++ b/test/CodeGen/Thumb/unord.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=thumb | grep bne | count 1
+; RUN: llc < %s -march=thumb | grep beq | count 1
+
+define i32 @f1(float %X, float %Y) {
+ %tmp = fcmp uno float %X, %Y
+ %retval = select i1 %tmp, i32 1, i32 -1
+ ret i32 %retval
+}
+
+define i32 @f2(float %X, float %Y) {
+ %tmp = fcmp ord float %X, %Y
+ %retval = select i1 %tmp, i32 1, i32 -1
+ ret i32 %retval
+}
diff --git a/test/CodeGen/Thumb/vargs.ll b/test/CodeGen/Thumb/vargs.ll
new file mode 100644
index 0000000..16a9c44
--- /dev/null
+++ b/test/CodeGen/Thumb/vargs.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -march=thumb
+; RUN: llc < %s -mtriple=thumb-linux | grep pop | count 1
+; RUN: llc < %s -mtriple=thumb-darwin | grep pop | count 2
+
+@str = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1]
+
+define void @f(i32 %a, ...) {
+entry:
+ %va = alloca i8*, align 4 ; <i8**> [#uses=4]
+ %va.upgrd.1 = bitcast i8** %va to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_start( i8* %va.upgrd.1 )
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %a_addr.0 = phi i32 [ %a, %entry ], [ %tmp5, %bb ] ; <i32> [#uses=2]
+ %tmp = volatile load i8** %va ; <i8*> [#uses=2]
+ %tmp2 = getelementptr i8* %tmp, i32 4 ; <i8*> [#uses=1]
+ volatile store i8* %tmp2, i8** %va
+ %tmp5 = add i32 %a_addr.0, -1 ; <i32> [#uses=1]
+ %tmp.upgrd.2 = icmp eq i32 %a_addr.0, 1 ; <i1> [#uses=1]
+ br i1 %tmp.upgrd.2, label %bb7, label %bb
+
+bb7: ; preds = %bb
+ %tmp3 = bitcast i8* %tmp to i32* ; <i32*> [#uses=1]
+ %tmp.upgrd.3 = load i32* %tmp3 ; <i32> [#uses=1]
+ %tmp10 = call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @str, i32 0, i64 0), i32 %tmp.upgrd.3 ) ; <i32> [#uses=0]
+ %va.upgrd.4 = bitcast i8** %va to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_end( i8* %va.upgrd.4 )
+ ret void
+}
+
+declare void @llvm.va_start(i8*)
+
+declare i32 @printf(i8*, ...)
+
+declare void @llvm.va_end(i8*)
diff --git a/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll b/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll
new file mode 100644
index 0000000..8f2283f
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s
+
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
+target triple = "thumbv6t2-elf"
+ %struct.dwarf_cie = type <{ i32, i32, i8, [0 x i8], [3 x i8] }>
+
+declare arm_apcscc i8* @read_sleb128(i8*, i32* nocapture) nounwind
+
+define arm_apcscc i32 @get_cie_encoding(%struct.dwarf_cie* %cie) nounwind {
+entry:
+ br i1 undef, label %bb1, label %bb13
+
+bb1: ; preds = %entry
+ %tmp38 = add i32 undef, 10 ; <i32> [#uses=1]
+ br label %bb.i
+
+bb.i: ; preds = %bb.i, %bb1
+ %indvar.i = phi i32 [ 0, %bb1 ], [ %2, %bb.i ] ; <i32> [#uses=3]
+ %tmp39 = add i32 %indvar.i, %tmp38 ; <i32> [#uses=1]
+ %p_addr.0.i = getelementptr i8* undef, i32 %tmp39 ; <i8*> [#uses=1]
+ %0 = load i8* %p_addr.0.i, align 1 ; <i8> [#uses=1]
+ %1 = icmp slt i8 %0, 0 ; <i1> [#uses=1]
+ %2 = add i32 %indvar.i, 1 ; <i32> [#uses=1]
+ br i1 %1, label %bb.i, label %read_uleb128.exit
+
+read_uleb128.exit: ; preds = %bb.i
+ %.sum40 = add i32 %indvar.i, undef ; <i32> [#uses=1]
+ %.sum31 = add i32 %.sum40, 2 ; <i32> [#uses=1]
+ %scevgep.i = getelementptr %struct.dwarf_cie* %cie, i32 0, i32 3, i32 %.sum31 ; <i8*> [#uses=1]
+ %3 = call arm_apcscc i8* @read_sleb128(i8* %scevgep.i, i32* undef) ; <i8*> [#uses=0]
+ unreachable
+
+bb13: ; preds = %entry
+ ret i32 0
+}
diff --git a/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll b/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
new file mode 100644
index 0000000..ef076a4
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+vfp2,+thumb2 | FileCheck %s
+; rdar://7076238
+
+@"\01LC" = external constant [36 x i8], align 1 ; <[36 x i8]*> [#uses=1]
+
+define arm_apcscc i32 @t(i32, ...) nounwind {
+entry:
+; CHECK: t:
+; CHECK: add r7, sp, #12
+ %1 = load i8** undef, align 4 ; <i8*> [#uses=3]
+ %2 = getelementptr i8* %1, i32 4 ; <i8*> [#uses=1]
+ %3 = getelementptr i8* %1, i32 8 ; <i8*> [#uses=1]
+ %4 = bitcast i8* %2 to i32* ; <i32*> [#uses=1]
+ %5 = load i32* %4, align 4 ; <i32> [#uses=1]
+ %6 = trunc i32 %5 to i8 ; <i8> [#uses=1]
+ %7 = getelementptr i8* %1, i32 12 ; <i8*> [#uses=1]
+ %8 = bitcast i8* %3 to i32* ; <i32*> [#uses=1]
+ %9 = load i32* %8, align 4 ; <i32> [#uses=1]
+ %10 = trunc i32 %9 to i16 ; <i16> [#uses=1]
+ %11 = bitcast i8* %7 to i32* ; <i32*> [#uses=1]
+ %12 = load i32* %11, align 4 ; <i32> [#uses=1]
+ %13 = trunc i32 %12 to i16 ; <i16> [#uses=1]
+ %14 = load i32* undef, align 4 ; <i32> [#uses=2]
+ %15 = sext i8 %6 to i32 ; <i32> [#uses=2]
+ %16 = sext i16 %10 to i32 ; <i32> [#uses=2]
+ %17 = sext i16 %13 to i32 ; <i32> [#uses=2]
+ %18 = call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([36 x i8]* @"\01LC", i32 0, i32 0), i32 -128, i32 0, i32 %15, i32 %16, i32 %17, i32 0, i32 %14) nounwind ; <i32> [#uses=0]
+ %19 = add i32 0, %15 ; <i32> [#uses=1]
+ %20 = add i32 %19, %16 ; <i32> [#uses=1]
+ %21 = add i32 %20, %14 ; <i32> [#uses=1]
+ %22 = add i32 %21, %17 ; <i32> [#uses=1]
+ %23 = add i32 %22, 0 ; <i32> [#uses=1]
+ ret i32 %23
+}
+
+declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind
diff --git a/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll b/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll
new file mode 100644
index 0000000..4d21f9b
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+vfp2,+thumb2
+; rdar://7083961
+
+define arm_apcscc i32 @value(i64 %b1, i64 %b2) nounwind readonly {
+entry:
+ %0 = icmp eq i32 undef, 0 ; <i1> [#uses=1]
+ %mod.0.ph.ph = select i1 %0, float -1.000000e+00, float 1.000000e+00 ; <float> [#uses=1]
+ br label %bb7
+
+bb7: ; preds = %bb7, %entry
+ br i1 undef, label %bb86.preheader, label %bb7
+
+bb86.preheader: ; preds = %bb7
+ %1 = fmul float %mod.0.ph.ph, 5.000000e+00 ; <float> [#uses=0]
+ br label %bb79
+
+bb79: ; preds = %bb79, %bb86.preheader
+ br i1 undef, label %bb119, label %bb79
+
+bb119: ; preds = %bb79
+ ret i32 undef
+}
diff --git a/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll b/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll
new file mode 100644
index 0000000..f74d12e
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll
@@ -0,0 +1,193 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim
+
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.JHUFF_TBL = type { [17 x i8], [256 x i8], i32 }
+ %struct.JQUANT_TBL = type { [64 x i16], i32 }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+ %struct.anon = type { [8 x i32], [48 x i8] }
+ %struct.backing_store_info = type { void (%struct.jpeg_common_struct*, %struct.backing_store_info*, i8*, i32, i32)*, void (%struct.jpeg_common_struct*, %struct.backing_store_info*, i8*, i32, i32)*, void (%struct.jpeg_common_struct*, %struct.backing_store_info*)*, %struct.FILE*, [64 x i8] }
+ %struct.jpeg_color_deconverter = type { void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*, i8***, i32, i8**, i32)* }
+ %struct.jpeg_color_quantizer = type { void (%struct.jpeg_decompress_struct*, i32)*, void (%struct.jpeg_decompress_struct*, i8**, i8**, i32)*, void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)* }
+ %struct.jpeg_common_struct = type { %struct.jpeg_error_mgr*, %struct.jpeg_memory_mgr*, %struct.jpeg_progress_mgr*, i32, i32 }
+ %struct.jpeg_component_info = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.JQUANT_TBL*, i8* }
+ %struct.jpeg_d_coef_controller = type { void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*, i8***)*, %struct.jvirt_barray_control** }
+ %struct.jpeg_d_main_controller = type { void (%struct.jpeg_decompress_struct*, i32)*, void (%struct.jpeg_decompress_struct*, i8**, i32*, i32)* }
+ %struct.jpeg_d_post_controller = type { void (%struct.jpeg_decompress_struct*, i32)*, void (%struct.jpeg_decompress_struct*, i8***, i32*, i32, i8**, i32*, i32)* }
+ %struct.jpeg_decomp_master = type { void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, i32 }
+ %struct.jpeg_decompress_struct = type { %struct.jpeg_error_mgr*, %struct.jpeg_memory_mgr*, %struct.jpeg_progress_mgr*, i32, i32, %struct.jpeg_source_mgr*, i32, i32, i32, i32, i32, i32, i32, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8**, i32, i32, i32, i32, i32, [64 x i32]*, [4 x %struct.JQUANT_TBL*], [4 x %struct.JHUFF_TBL*], [4 x %struct.JHUFF_TBL*], i32, %struct.jpeg_component_info*, i32, i32, [16 x i8], [16 x i8], [16 x i8], i32, i32, i8, i16, i16, i32, i8, i32, i32, i32, i32, i32, i8*, i32, [4 x %struct.jpeg_component_info*], i32, i32, i32, [10 x i32], i32, i32, i32, i32, i32, %struct.jpeg_decomp_master*, %struct.jpeg_d_main_controller*, %struct.jpeg_d_coef_controller*, %struct.jpeg_d_post_controller*, %struct.jpeg_input_controller*, %struct.jpeg_marker_reader*, %struct.jpeg_entropy_decoder*, %struct.jpeg_inverse_dct*, %struct.jpeg_upsampler*, %struct.jpeg_color_deconverter*, %struct.jpeg_color_quantizer* }
+ %struct.jpeg_entropy_decoder = type { void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*, [64 x i16]**)* }
+ %struct.jpeg_error_mgr = type { void (%struct.jpeg_common_struct*)*, void (%struct.jpeg_common_struct*, i32)*, void (%struct.jpeg_common_struct*)*, void (%struct.jpeg_common_struct*, i8*)*, void (%struct.jpeg_common_struct*)*, i32, %struct.anon, i32, i32, i8**, i32, i8**, i32, i32 }
+ %struct.jpeg_input_controller = type { i32 (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, i32, i32 }
+ %struct.jpeg_inverse_dct = type { void (%struct.jpeg_decompress_struct*)*, [10 x void (%struct.jpeg_decompress_struct*, %struct.jpeg_component_info*, i16*, i8**, i32)*] }
+ %struct.jpeg_marker_reader = type { void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, [16 x i32 (%struct.jpeg_decompress_struct*)*], i32, i32, i32, i32 }
+ %struct.jpeg_memory_mgr = type { i8* (%struct.jpeg_common_struct*, i32, i32)*, i8* (%struct.jpeg_common_struct*, i32, i32)*, i8** (%struct.jpeg_common_struct*, i32, i32, i32)*, [64 x i16]** (%struct.jpeg_common_struct*, i32, i32, i32)*, %struct.jvirt_sarray_control* (%struct.jpeg_common_struct*, i32, i32, i32, i32, i32)*, %struct.jvirt_barray_control* (%struct.jpeg_common_struct*, i32, i32, i32, i32, i32)*, void (%struct.jpeg_common_struct*)*, i8** (%struct.jpeg_common_struct*, %struct.jvirt_sarray_control*, i32, i32, i32)*, [64 x i16]** (%struct.jpeg_common_struct*, %struct.jvirt_barray_control*, i32, i32, i32)*, void (%struct.jpeg_common_struct*, i32)*, void (%struct.jpeg_common_struct*)*, i32 }
+ %struct.jpeg_progress_mgr = type { void (%struct.jpeg_common_struct*)*, i32, i32, i32, i32 }
+ %struct.jpeg_source_mgr = type { i8*, i32, void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*, i32)*, i32 (%struct.jpeg_decompress_struct*, i32)*, void (%struct.jpeg_decompress_struct*)* }
+ %struct.jpeg_upsampler = type { void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*, i8***, i32*, i32, i8**, i32*, i32)*, i32 }
+ %struct.jvirt_barray_control = type { [64 x i16]**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_barray_control*, %struct.backing_store_info }
+ %struct.jvirt_sarray_control = type { i8**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_sarray_control*, %struct.backing_store_info }
+
+define arm_apcscc void @jpeg_idct_float(%struct.jpeg_decompress_struct* nocapture %cinfo, %struct.jpeg_component_info* nocapture %compptr, i16* nocapture %coef_block, i8** nocapture %output_buf, i32 %output_col) nounwind {
+entry:
+ %workspace = alloca [64 x float], align 4 ; <[64 x float]*> [#uses=11]
+ %0 = load i8** undef, align 4 ; <i8*> [#uses=5]
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=11]
+ %tmp39 = add i32 %indvar, 8 ; <i32> [#uses=0]
+ %tmp41 = add i32 %indvar, 16 ; <i32> [#uses=2]
+ %scevgep42 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp41 ; <float*> [#uses=1]
+ %tmp43 = add i32 %indvar, 24 ; <i32> [#uses=1]
+ %scevgep44 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp43 ; <float*> [#uses=1]
+ %tmp45 = add i32 %indvar, 32 ; <i32> [#uses=1]
+ %scevgep46 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp45 ; <float*> [#uses=1]
+ %tmp47 = add i32 %indvar, 40 ; <i32> [#uses=1]
+ %scevgep48 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp47 ; <float*> [#uses=1]
+ %tmp49 = add i32 %indvar, 48 ; <i32> [#uses=1]
+ %scevgep50 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp49 ; <float*> [#uses=1]
+ %tmp51 = add i32 %indvar, 56 ; <i32> [#uses=1]
+ %scevgep52 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp51 ; <float*> [#uses=1]
+ %wsptr.119 = getelementptr [64 x float]* %workspace, i32 0, i32 %indvar ; <float*> [#uses=1]
+ %tmp54 = shl i32 %indvar, 2 ; <i32> [#uses=1]
+ %scevgep76 = getelementptr i8* undef, i32 %tmp54 ; <i8*> [#uses=1]
+ %quantptr.118 = bitcast i8* %scevgep76 to float* ; <float*> [#uses=1]
+ %scevgep79 = getelementptr i16* %coef_block, i32 %tmp41 ; <i16*> [#uses=0]
+ %inptr.117 = getelementptr i16* %coef_block, i32 %indvar ; <i16*> [#uses=1]
+ %1 = load i16* null, align 2 ; <i16> [#uses=1]
+ %2 = load i16* undef, align 2 ; <i16> [#uses=1]
+ %3 = load i16* %inptr.117, align 2 ; <i16> [#uses=1]
+ %4 = sitofp i16 %3 to float ; <float> [#uses=1]
+ %5 = load float* %quantptr.118, align 4 ; <float> [#uses=1]
+ %6 = fmul float %4, %5 ; <float> [#uses=1]
+ %7 = fsub float %6, undef ; <float> [#uses=2]
+ %8 = fmul float undef, 0x3FF6A09E60000000 ; <float> [#uses=1]
+ %9 = fsub float %8, 0.000000e+00 ; <float> [#uses=2]
+ %10 = fadd float undef, 0.000000e+00 ; <float> [#uses=2]
+ %11 = fadd float %7, %9 ; <float> [#uses=2]
+ %12 = fsub float %7, %9 ; <float> [#uses=2]
+ %13 = sitofp i16 %1 to float ; <float> [#uses=1]
+ %14 = fmul float %13, undef ; <float> [#uses=2]
+ %15 = sitofp i16 %2 to float ; <float> [#uses=1]
+ %16 = load float* undef, align 4 ; <float> [#uses=1]
+ %17 = fmul float %15, %16 ; <float> [#uses=1]
+ %18 = fadd float %14, undef ; <float> [#uses=2]
+ %19 = fsub float %14, undef ; <float> [#uses=2]
+ %20 = fadd float undef, %17 ; <float> [#uses=2]
+ %21 = fadd float %20, %18 ; <float> [#uses=3]
+ %22 = fsub float %20, %18 ; <float> [#uses=1]
+ %23 = fmul float %22, 0x3FF6A09E60000000 ; <float> [#uses=1]
+ %24 = fadd float %19, undef ; <float> [#uses=1]
+ %25 = fmul float %24, 0x3FFD906BC0000000 ; <float> [#uses=2]
+ %26 = fmul float undef, 0x3FF1517A80000000 ; <float> [#uses=1]
+ %27 = fsub float %26, %25 ; <float> [#uses=1]
+ %28 = fmul float %19, 0xC004E7AEA0000000 ; <float> [#uses=1]
+ %29 = fadd float %28, %25 ; <float> [#uses=1]
+ %30 = fsub float %29, %21 ; <float> [#uses=3]
+ %31 = fsub float %23, %30 ; <float> [#uses=3]
+ %32 = fadd float %27, %31 ; <float> [#uses=1]
+ %33 = fadd float %10, %21 ; <float> [#uses=1]
+ store float %33, float* %wsptr.119, align 4
+ %34 = fsub float %10, %21 ; <float> [#uses=1]
+ store float %34, float* %scevgep52, align 4
+ %35 = fadd float %11, %30 ; <float> [#uses=1]
+ store float %35, float* null, align 4
+ %36 = fsub float %11, %30 ; <float> [#uses=1]
+ store float %36, float* %scevgep50, align 4
+ %37 = fadd float %12, %31 ; <float> [#uses=1]
+ store float %37, float* %scevgep42, align 4
+ %38 = fsub float %12, %31 ; <float> [#uses=1]
+ store float %38, float* %scevgep48, align 4
+ %39 = fadd float undef, %32 ; <float> [#uses=1]
+ store float %39, float* %scevgep46, align 4
+ store float undef, float* %scevgep44, align 4
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br i1 undef, label %bb6, label %bb
+
+bb6: ; preds = %bb
+ %.sum10 = add i32 %output_col, 1 ; <i32> [#uses=1]
+ %.sum8 = add i32 %output_col, 6 ; <i32> [#uses=1]
+ %.sum6 = add i32 %output_col, 2 ; <i32> [#uses=1]
+ %.sum = add i32 %output_col, 3 ; <i32> [#uses=1]
+ br label %bb8
+
+bb8: ; preds = %bb8, %bb6
+ %ctr.116 = phi i32 [ 0, %bb6 ], [ %88, %bb8 ] ; <i32> [#uses=3]
+ %scevgep = getelementptr i8** %output_buf, i32 %ctr.116 ; <i8**> [#uses=1]
+ %tmp = shl i32 %ctr.116, 3 ; <i32> [#uses=5]
+ %tmp2392 = or i32 %tmp, 4 ; <i32> [#uses=1]
+ %scevgep24 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp2392 ; <float*> [#uses=1]
+ %tmp2591 = or i32 %tmp, 2 ; <i32> [#uses=1]
+ %scevgep26 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp2591 ; <float*> [#uses=1]
+ %tmp2790 = or i32 %tmp, 6 ; <i32> [#uses=1]
+ %scevgep28 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp2790 ; <float*> [#uses=1]
+ %tmp3586 = or i32 %tmp, 7 ; <i32> [#uses=0]
+ %wsptr.215 = getelementptr [64 x float]* %workspace, i32 0, i32 %tmp ; <float*> [#uses=1]
+ %40 = load i8** %scevgep, align 4 ; <i8*> [#uses=4]
+ %41 = load float* %wsptr.215, align 4 ; <float> [#uses=1]
+ %42 = load float* %scevgep24, align 4 ; <float> [#uses=1]
+ %43 = fadd float %41, %42 ; <float> [#uses=1]
+ %44 = load float* %scevgep26, align 4 ; <float> [#uses=1]
+ %45 = load float* %scevgep28, align 4 ; <float> [#uses=1]
+ %46 = fadd float %44, %45 ; <float> [#uses=1]
+ %47 = fsub float %43, %46 ; <float> [#uses=2]
+ %48 = fsub float undef, 0.000000e+00 ; <float> [#uses=1]
+ %49 = fadd float 0.000000e+00, undef ; <float> [#uses=1]
+ %50 = fptosi float %49 to i32 ; <i32> [#uses=1]
+ %51 = add i32 %50, 4 ; <i32> [#uses=1]
+ %52 = lshr i32 %51, 3 ; <i32> [#uses=1]
+ %53 = and i32 %52, 1023 ; <i32> [#uses=1]
+ %.sum14 = add i32 %53, 128 ; <i32> [#uses=1]
+ %54 = getelementptr i8* %0, i32 %.sum14 ; <i8*> [#uses=1]
+ %55 = load i8* %54, align 1 ; <i8> [#uses=1]
+ store i8 %55, i8* null, align 1
+ %56 = getelementptr i8* %40, i32 %.sum10 ; <i8*> [#uses=1]
+ store i8 0, i8* %56, align 1
+ %57 = load i8* null, align 1 ; <i8> [#uses=1]
+ %58 = getelementptr i8* %40, i32 %.sum8 ; <i8*> [#uses=1]
+ store i8 %57, i8* %58, align 1
+ %59 = fadd float undef, %48 ; <float> [#uses=1]
+ %60 = fptosi float %59 to i32 ; <i32> [#uses=1]
+ %61 = add i32 %60, 4 ; <i32> [#uses=1]
+ %62 = lshr i32 %61, 3 ; <i32> [#uses=1]
+ %63 = and i32 %62, 1023 ; <i32> [#uses=1]
+ %.sum7 = add i32 %63, 128 ; <i32> [#uses=1]
+ %64 = getelementptr i8* %0, i32 %.sum7 ; <i8*> [#uses=1]
+ %65 = load i8* %64, align 1 ; <i8> [#uses=1]
+ %66 = getelementptr i8* %40, i32 %.sum6 ; <i8*> [#uses=1]
+ store i8 %65, i8* %66, align 1
+ %67 = fptosi float undef to i32 ; <i32> [#uses=1]
+ %68 = add i32 %67, 4 ; <i32> [#uses=1]
+ %69 = lshr i32 %68, 3 ; <i32> [#uses=1]
+ %70 = and i32 %69, 1023 ; <i32> [#uses=1]
+ %.sum5 = add i32 %70, 128 ; <i32> [#uses=1]
+ %71 = getelementptr i8* %0, i32 %.sum5 ; <i8*> [#uses=1]
+ %72 = load i8* %71, align 1 ; <i8> [#uses=1]
+ store i8 %72, i8* undef, align 1
+ %73 = fadd float %47, undef ; <float> [#uses=1]
+ %74 = fptosi float %73 to i32 ; <i32> [#uses=1]
+ %75 = add i32 %74, 4 ; <i32> [#uses=1]
+ %76 = lshr i32 %75, 3 ; <i32> [#uses=1]
+ %77 = and i32 %76, 1023 ; <i32> [#uses=1]
+ %.sum3 = add i32 %77, 128 ; <i32> [#uses=1]
+ %78 = getelementptr i8* %0, i32 %.sum3 ; <i8*> [#uses=1]
+ %79 = load i8* %78, align 1 ; <i8> [#uses=1]
+ store i8 %79, i8* undef, align 1
+ %80 = fsub float %47, undef ; <float> [#uses=1]
+ %81 = fptosi float %80 to i32 ; <i32> [#uses=1]
+ %82 = add i32 %81, 4 ; <i32> [#uses=1]
+ %83 = lshr i32 %82, 3 ; <i32> [#uses=1]
+ %84 = and i32 %83, 1023 ; <i32> [#uses=1]
+ %.sum1 = add i32 %84, 128 ; <i32> [#uses=1]
+ %85 = getelementptr i8* %0, i32 %.sum1 ; <i8*> [#uses=1]
+ %86 = load i8* %85, align 1 ; <i8> [#uses=1]
+ %87 = getelementptr i8* %40, i32 %.sum ; <i8*> [#uses=1]
+ store i8 %86, i8* %87, align 1
+ %88 = add i32 %ctr.116, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %88, 8 ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb8
+
+return: ; preds = %bb8
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll b/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
new file mode 100644
index 0000000..a8e86d5
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
@@ -0,0 +1,85 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s
+
+@csize = external global [100 x [20 x [4 x i8]]] ; <[100 x [20 x [4 x i8]]]*> [#uses=1]
+@vsize = external global [100 x [20 x [4 x i8]]] ; <[100 x [20 x [4 x i8]]]*> [#uses=1]
+@cll = external global [20 x [10 x i8]] ; <[20 x [10 x i8]]*> [#uses=1]
+@lefline = external global [100 x [20 x i32]] ; <[100 x [20 x i32]]*> [#uses=1]
+@sep = external global [20 x i32] ; <[20 x i32]*> [#uses=1]
+
+define arm_apcscc void @main(i32 %argc, i8** %argv) noreturn nounwind {
+; CHECK: main:
+; CHECK: ldrb
+entry:
+ %nb.i.i.i = alloca [25 x i8], align 1 ; <[25 x i8]*> [#uses=0]
+ %line.i.i.i = alloca [200 x i8], align 1 ; <[200 x i8]*> [#uses=1]
+ %line.i = alloca [1024 x i8], align 1 ; <[1024 x i8]*> [#uses=0]
+ br i1 undef, label %bb.i.i, label %bb4.preheader.i
+
+bb.i.i: ; preds = %entry
+ unreachable
+
+bb4.preheader.i: ; preds = %entry
+ br i1 undef, label %tbl.exit, label %bb.i.preheader
+
+bb.i.preheader: ; preds = %bb4.preheader.i
+ %line3.i.i.i = getelementptr [200 x i8]* %line.i.i.i, i32 0, i32 0 ; <i8*> [#uses=1]
+ br label %bb.i
+
+bb.i: ; preds = %bb4.backedge.i, %bb.i.preheader
+ br i1 undef, label %bb3.i, label %bb4.backedge.i
+
+bb3.i: ; preds = %bb.i
+ br i1 undef, label %bb2.i184.i.i, label %bb.i183.i.i
+
+bb.i183.i.i: ; preds = %bb.i183.i.i, %bb3.i
+ br i1 undef, label %bb2.i184.i.i, label %bb.i183.i.i
+
+bb2.i184.i.i: ; preds = %bb.i183.i.i, %bb3.i
+ br i1 undef, label %bb5.i185.i.i, label %bb35.preheader.i.i.i
+
+bb35.preheader.i.i.i: ; preds = %bb2.i184.i.i
+ %0 = load i8* %line3.i.i.i, align 1 ; <i8> [#uses=1]
+ %1 = icmp eq i8 %0, 59 ; <i1> [#uses=1]
+ br i1 %1, label %bb36.i.i.i, label %bb9.i186.i.i
+
+bb5.i185.i.i: ; preds = %bb2.i184.i.i
+ br label %bb.i171.i.i
+
+bb9.i186.i.i: ; preds = %bb35.preheader.i.i.i
+ unreachable
+
+bb36.i.i.i: ; preds = %bb35.preheader.i.i.i
+ br label %bb.i171.i.i
+
+bb.i171.i.i: ; preds = %bb3.i176.i.i, %bb36.i.i.i, %bb5.i185.i.i
+ %2 = phi i32 [ %4, %bb3.i176.i.i ], [ 0, %bb36.i.i.i ], [ 0, %bb5.i185.i.i ] ; <i32> [#uses=6]
+ %scevgep16.i.i.i = getelementptr [20 x i32]* @sep, i32 0, i32 %2 ; <i32*> [#uses=1]
+ %scevgep18.i.i.i = getelementptr [20 x [10 x i8]]* @cll, i32 0, i32 %2, i32 0 ; <i8*> [#uses=0]
+ store i32 -1, i32* %scevgep16.i.i.i, align 4
+ br label %bb1.i175.i.i
+
+bb1.i175.i.i: ; preds = %bb1.i175.i.i, %bb.i171.i.i
+ %i.03.i172.i.i = phi i32 [ 0, %bb.i171.i.i ], [ %3, %bb1.i175.i.i ] ; <i32> [#uses=4]
+ %scevgep11.i.i.i = getelementptr [100 x [20 x i32]]* @lefline, i32 0, i32 %i.03.i172.i.i, i32 %2 ; <i32*> [#uses=1]
+ %scevgep12.i.i.i = getelementptr [100 x [20 x [4 x i8]]]* @vsize, i32 0, i32 %i.03.i172.i.i, i32 %2, i32 0 ; <i8*> [#uses=1]
+ %scevgep13.i.i.i = getelementptr [100 x [20 x [4 x i8]]]* @csize, i32 0, i32 %i.03.i172.i.i, i32 %2, i32 0 ; <i8*> [#uses=0]
+ store i8 0, i8* %scevgep12.i.i.i, align 1
+ store i32 0, i32* %scevgep11.i.i.i, align 4
+ store i32 108, i32* undef, align 4
+ %3 = add i32 %i.03.i172.i.i, 1 ; <i32> [#uses=2]
+ %exitcond.i174.i.i = icmp eq i32 %3, 100 ; <i1> [#uses=1]
+ br i1 %exitcond.i174.i.i, label %bb3.i176.i.i, label %bb1.i175.i.i
+
+bb3.i176.i.i: ; preds = %bb1.i175.i.i
+ %4 = add i32 %2, 1 ; <i32> [#uses=1]
+ br i1 undef, label %bb5.i177.i.i, label %bb.i171.i.i
+
+bb5.i177.i.i: ; preds = %bb3.i176.i.i
+ unreachable
+
+bb4.backedge.i: ; preds = %bb.i
+ br i1 undef, label %tbl.exit, label %bb.i
+
+tbl.exit: ; preds = %bb4.backedge.i, %bb4.preheader.i
+ unreachable
+}
diff --git a/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll b/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll
new file mode 100644
index 0000000..6cbfd0d
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim
+
+ type { void (%"struct.xalanc_1_8::FormatterToXML"*, i16)*, i32 } ; type %0
+ type { void (%"struct.xalanc_1_8::FormatterToXML"*, i16*)*, i32 } ; type %1
+ type { void (%"struct.xalanc_1_8::FormatterToXML"*, %"struct.xalanc_1_8::XalanDOMString"*)*, i32 } ; type %2
+ type { void (%"struct.xalanc_1_8::FormatterToXML"*, i16*, i32, i32)*, i32 } ; type %3
+ type { void (%"struct.xalanc_1_8::FormatterToXML"*)*, i32 } ; type %4
+ %"struct.std::CharVectorType" = type { %"struct.std::_Vector_base<char,std::allocator<char> >" }
+ %"struct.std::_Bit_const_iterator" = type { %"struct.std::_Bit_iterator_base" }
+ %"struct.std::_Bit_iterator_base" = type { i32*, i32 }
+ %"struct.std::_Bvector_base<std::allocator<bool> >" = type { %"struct.std::_Bvector_base<std::allocator<bool> >::_Bvector_impl" }
+ %"struct.std::_Bvector_base<std::allocator<bool> >::_Bvector_impl" = type { %"struct.std::_Bit_const_iterator", %"struct.std::_Bit_const_iterator", i32* }
+ %"struct.std::_Vector_base<char,std::allocator<char> >" = type { %"struct.std::_Vector_base<char,std::allocator<char> >::_Vector_impl" }
+ %"struct.std::_Vector_base<char,std::allocator<char> >::_Vector_impl" = type { i8*, i8*, i8* }
+ %"struct.std::_Vector_base<short unsigned int,std::allocator<short unsigned int> >" = type { %"struct.std::_Vector_base<short unsigned int,std::allocator<short unsigned int> >::_Vector_impl" }
+ %"struct.std::_Vector_base<short unsigned int,std::allocator<short unsigned int> >::_Vector_impl" = type { i16*, i16*, i16* }
+ %"struct.std::basic_ostream<char,std::char_traits<char> >.base" = type { i32 (...)** }
+ %"struct.std::vector<bool,std::allocator<bool> >" = type { %"struct.std::_Bvector_base<std::allocator<bool> >" }
+ %"struct.std::vector<short unsigned int,std::allocator<short unsigned int> >" = type { %"struct.std::_Vector_base<short unsigned int,std::allocator<short unsigned int> >" }
+ %"struct.xalanc_1_8::FormatterListener" = type { %"struct.std::basic_ostream<char,std::char_traits<char> >.base", %"struct.std::basic_ostream<char,std::char_traits<char> >.base"*, i32 }
+ %"struct.xalanc_1_8::FormatterToXML" = type { %"struct.xalanc_1_8::FormatterListener", %"struct.std::basic_ostream<char,std::char_traits<char> >.base"*, %"struct.xalanc_1_8::XalanOutputStream"*, i16, [256 x i16], [256 x i16], i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, %"struct.xalanc_1_8::XalanDOMString", %"struct.xalanc_1_8::XalanDOMString", %"struct.xalanc_1_8::XalanDOMString", i32, i32, %"struct.std::vector<bool,std::allocator<bool> >", %"struct.xalanc_1_8::XalanDOMString", i8, i8, i8, i8, i8, %"struct.xalanc_1_8::XalanDOMString", %"struct.xalanc_1_8::XalanDOMString", %"struct.xalanc_1_8::XalanDOMString", %"struct.xalanc_1_8::XalanDOMString", %"struct.std::vector<short unsigned int,std::allocator<short unsigned int> >", i32, %"struct.std::CharVectorType", %"struct.std::vector<bool,std::allocator<bool> >", %0, %1, %2, %3, %0, %1, %2, %3, %4, i16*, i32 }
+ %"struct.xalanc_1_8::XalanDOMString" = type { %"struct.std::vector<short unsigned int,std::allocator<short unsigned int> >", i32 }
+ %"struct.xalanc_1_8::XalanOutputStream" = type { i32 (...)**, i32, %"struct.std::basic_ostream<char,std::char_traits<char> >.base"*, i32, %"struct.std::vector<short unsigned int,std::allocator<short unsigned int> >", %"struct.xalanc_1_8::XalanDOMString", i8, i8, %"struct.std::CharVectorType" }
+
+declare arm_apcscc void @_ZN10xalanc_1_814FormatterToXML17writeParentTagEndEv(%"struct.xalanc_1_8::FormatterToXML"*)
+
+define arm_apcscc void @_ZN10xalanc_1_814FormatterToXML5cdataEPKtj(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 %length) {
+entry:
+ %0 = getelementptr %"struct.xalanc_1_8::FormatterToXML"* %this, i32 0, i32 13 ; <i8*> [#uses=1]
+ br i1 undef, label %bb4, label %bb
+
+bb: ; preds = %entry
+ store i8 0, i8* %0, align 1
+ %1 = getelementptr %"struct.xalanc_1_8::FormatterToXML"* %this, i32 0, i32 0, i32 0, i32 0 ; <i32 (...)***> [#uses=1]
+ %2 = load i32 (...)*** %1, align 4 ; <i32 (...)**> [#uses=1]
+ %3 = getelementptr i32 (...)** %2, i32 11 ; <i32 (...)**> [#uses=1]
+ %4 = load i32 (...)** %3, align 4 ; <i32 (...)*> [#uses=1]
+ %5 = bitcast i32 (...)* %4 to void (%"struct.xalanc_1_8::FormatterToXML"*, i16*, i32)* ; <void (%"struct.xalanc_1_8::FormatterToXML"*, i16*, i32)*> [#uses=1]
+ tail call arm_apcscc void %5(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 %length)
+ ret void
+
+bb4: ; preds = %entry
+ tail call arm_apcscc void @_ZN10xalanc_1_814FormatterToXML17writeParentTagEndEv(%"struct.xalanc_1_8::FormatterToXML"* %this)
+ tail call arm_apcscc void undef(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 0, i32 %length, i8 zeroext undef)
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll b/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll
new file mode 100644
index 0000000..ebe9d46
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi
+; PR4681
+
+ %struct.FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct.FILE*, i32, i32, i32, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i32, i32, [40 x i8] }
+ %struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 }
[email protected] = external constant [30 x i8], align 1 ; <[30 x i8]*> [#uses=1]
+
+define arm_aapcscc i32 @__mf_heuristic_check(i32 %ptr, i32 %ptr_high) nounwind {
+entry:
+ br i1 undef, label %bb1, label %bb
+
+bb: ; preds = %entry
+ unreachable
+
+bb1: ; preds = %entry
+ br i1 undef, label %bb9, label %bb2
+
+bb2: ; preds = %bb1
+ %0 = call i8* @llvm.frameaddress(i32 0) ; <i8*> [#uses=1]
+ %1 = call arm_aapcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* noalias undef, i8* noalias getelementptr ([30 x i8]* @.str2, i32 0, i32 0), i8* %0, i8* null) nounwind ; <i32> [#uses=0]
+ unreachable
+
+bb9: ; preds = %bb1
+ ret i32 undef
+}
+
+declare i8* @llvm.frameaddress(i32) nounwind readnone
+
+declare arm_aapcscc i32 @fprintf(%struct.FILE* noalias nocapture, i8* noalias nocapture, ...) nounwind
diff --git a/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll b/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll
new file mode 100644
index 0000000..319d29b7
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll
@@ -0,0 +1,153 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+neon -arm-use-neon-fp -relocation-model=pic -disable-fp-elim
+
+ type { %struct.GAP } ; type %0
+ type { i16, i8, i8 } ; type %1
+ type { [2 x i32], [2 x i32] } ; type %2
+ type { %struct.rec* } ; type %3
+ type { i8, i8, i16, i8, i8, i8, i8 } ; type %4
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.FILE_POS = type { i8, i8, i16, i32 }
+ %struct.FIRST_UNION = type { %struct.FILE_POS }
+ %struct.FOURTH_UNION = type { %struct.STYLE }
+ %struct.GAP = type { i8, i8, i16 }
+ %struct.LIST = type { %struct.rec*, %struct.rec* }
+ %struct.SECOND_UNION = type { %1 }
+ %struct.STYLE = type { %0, %0, i16, i16, i32 }
+ %struct.THIRD_UNION = type { %2 }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+ %struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, %struct.rec*, %3, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i32 }
+ %struct.rec = type { %struct.head_type }
[email protected] = external constant [20 x i8], align 1 ; <[20 x i8]*> [#uses=1]
+@no_file_pos = external global %4 ; <%4*> [#uses=1]
+@zz_tmp = external global %struct.rec* ; <%struct.rec**> [#uses=1]
[email protected] = external constant [10 x i8], align 1 ; <[10 x i8]*> [#uses=1]
+@out_fp = external global %struct.FILE* ; <%struct.FILE**> [#uses=2]
+@cpexists = external global i32 ; <i32*> [#uses=2]
[email protected] = external constant [17 x i8], align 1 ; <[17 x i8]*> [#uses=1]
[email protected] = external constant [8 x i8], align 1 ; <[8 x i8]*> [#uses=1]
[email protected] = external constant [11 x i8], align 1 ; <[11 x i8]*> [#uses=1]
+
+declare arm_apcscc i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind
+
+declare arm_apcscc i32 @"\01_fwrite"(i8*, i32, i32, i8*)
+
+declare arm_apcscc %struct.FILE* @OpenIncGraphicFile(i8*, i8 zeroext, %struct.rec** nocapture, %struct.FILE_POS*, i32* nocapture) nounwind
+
+declare arm_apcscc void @Error(i32, i32, i8*, i32, %struct.FILE_POS*, ...) nounwind
+
+declare arm_apcscc i8* @fgets(i8*, i32, %struct.FILE* nocapture) nounwind
+
+define arm_apcscc void @PS_PrintGraphicInclude(%struct.rec* %x, i32 %colmark, i32 %rowmark) nounwind {
+entry:
+ br label %bb5
+
+bb5: ; preds = %bb5, %entry
+ %.pn = phi %struct.rec* [ %y.0, %bb5 ], [ undef, %entry ] ; <%struct.rec*> [#uses=1]
+ %y.0.in = getelementptr %struct.rec* %.pn, i32 0, i32 0, i32 0, i32 1, i32 0 ; <%struct.rec**> [#uses=1]
+ %y.0 = load %struct.rec** %y.0.in ; <%struct.rec*> [#uses=2]
+ br i1 undef, label %bb5, label %bb6
+
+bb6: ; preds = %bb5
+ %0 = call arm_apcscc %struct.FILE* @OpenIncGraphicFile(i8* undef, i8 zeroext 0, %struct.rec** undef, %struct.FILE_POS* null, i32* undef) nounwind ; <%struct.FILE*> [#uses=1]
+ br i1 false, label %bb.i, label %FontHalfXHeight.exit
+
+bb.i: ; preds = %bb6
+ br label %FontHalfXHeight.exit
+
+FontHalfXHeight.exit: ; preds = %bb.i, %bb6
+ br i1 undef, label %bb.i1, label %FontSize.exit
+
+bb.i1: ; preds = %FontHalfXHeight.exit
+ br label %FontSize.exit
+
+FontSize.exit: ; preds = %bb.i1, %FontHalfXHeight.exit
+ %1 = load i32* undef, align 4 ; <i32> [#uses=1]
+ %2 = icmp ult i32 0, undef ; <i1> [#uses=1]
+ br i1 %2, label %bb.i5, label %FontName.exit
+
+bb.i5: ; preds = %FontSize.exit
+ call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([10 x i8]* @.str81872, i32 0, i32 0)) nounwind
+ br label %FontName.exit
+
+FontName.exit: ; preds = %bb.i5, %FontSize.exit
+ %3 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([8 x i8]* @.str1822946, i32 0, i32 0), i32 %1, i8* undef) nounwind ; <i32> [#uses=0]
+ %4 = call arm_apcscc i32 @"\01_fwrite"(i8* getelementptr ([11 x i8]* @.str1842948, i32 0, i32 0), i32 1, i32 10, i8* undef) nounwind ; <i32> [#uses=0]
+ %5 = sub i32 %colmark, undef ; <i32> [#uses=1]
+ %6 = sub i32 %rowmark, undef ; <i32> [#uses=1]
+ %7 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1]
+ %8 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %7, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 %5, i32 %6) nounwind ; <i32> [#uses=0]
+ store i32 0, i32* @cpexists, align 4
+ %9 = getelementptr %struct.rec* %y.0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 1 ; <i32*> [#uses=1]
+ %10 = load i32* %9, align 4 ; <i32> [#uses=1]
+ %11 = sub i32 0, %10 ; <i32> [#uses=1]
+ %12 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1]
+ %13 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %12, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 undef, i32 %11) nounwind ; <i32> [#uses=0]
+ store i32 0, i32* @cpexists, align 4
+ br label %bb100.outer.outer
+
+bb100.outer.outer: ; preds = %bb79.critedge, %bb1.i3, %FontName.exit
+ %x_addr.0.ph.ph = phi %struct.rec* [ %x, %FontName.exit ], [ null, %bb79.critedge ], [ null, %bb1.i3 ] ; <%struct.rec*> [#uses=1]
+ %14 = getelementptr %struct.rec* %x_addr.0.ph.ph, i32 0, i32 0, i32 1, i32 0 ; <%struct.FILE_POS*> [#uses=0]
+ br label %bb100.outer
+
+bb.i80: ; preds = %bb3.i85
+ br i1 undef, label %bb2.i84, label %bb2.i51
+
+bb2.i84: ; preds = %bb100.outer, %bb.i80
+ br i1 undef, label %bb3.i77, label %bb3.i85
+
+bb3.i85: ; preds = %bb2.i84
+ br i1 false, label %StringBeginsWith.exit88, label %bb.i80
+
+StringBeginsWith.exit88: ; preds = %bb3.i85
+ br i1 undef, label %bb3.i77, label %bb2.i51
+
+bb2.i.i68: ; preds = %bb3.i77
+ br label %bb3.i77
+
+bb3.i77: ; preds = %bb2.i.i68, %StringBeginsWith.exit88, %bb2.i84
+ br i1 false, label %bb1.i58, label %bb2.i.i68
+
+bb1.i58: ; preds = %bb3.i77
+ unreachable
+
+bb.i47: ; preds = %bb3.i52
+ br i1 undef, label %bb2.i51, label %bb2.i.i15.critedge
+
+bb2.i51: ; preds = %bb.i47, %StringBeginsWith.exit88, %bb.i80
+ %15 = load i8* undef, align 1 ; <i8> [#uses=0]
+ br i1 false, label %StringBeginsWith.exit55thread-split, label %bb3.i52
+
+bb3.i52: ; preds = %bb2.i51
+ br i1 false, label %StringBeginsWith.exit55, label %bb.i47
+
+StringBeginsWith.exit55thread-split: ; preds = %bb2.i51
+ br label %StringBeginsWith.exit55
+
+StringBeginsWith.exit55: ; preds = %StringBeginsWith.exit55thread-split, %bb3.i52
+ br label %bb2.i41
+
+bb2.i41: ; preds = %bb2.i41, %StringBeginsWith.exit55
+ br label %bb2.i41
+
+bb2.i.i15.critedge: ; preds = %bb.i47
+ %16 = call arm_apcscc i8* @fgets(i8* undef, i32 512, %struct.FILE* %0) nounwind ; <i8*> [#uses=0]
+ %iftmp.560.0 = select i1 undef, i32 2, i32 0 ; <i32> [#uses=1]
+ br label %bb100.outer
+
+bb2.i8: ; preds = %bb100.outer
+ br i1 undef, label %bb1.i3, label %bb79.critedge
+
+bb1.i3: ; preds = %bb2.i8
+ br label %bb100.outer.outer
+
+bb79.critedge: ; preds = %bb2.i8
+ store %struct.rec* null, %struct.rec** @zz_tmp, align 4
+ br label %bb100.outer.outer
+
+bb100.outer: ; preds = %bb2.i.i15.critedge, %bb100.outer.outer
+ %state.0.ph = phi i32 [ 0, %bb100.outer.outer ], [ %iftmp.560.0, %bb2.i.i15.critedge ] ; <i32> [#uses=1]
+ %cond = icmp eq i32 %state.0.ph, 1 ; <i1> [#uses=1]
+ br i1 %cond, label %bb2.i8, label %bb2.i84
+}
diff --git a/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll b/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll
new file mode 100644
index 0000000..a62b612
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll
@@ -0,0 +1,508 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+neon -arm-use-neon-fp -relocation-model=pic -disable-fp-elim -O3
+
+ type { i16, i8, i8 } ; type %0
+ type { [2 x i32], [2 x i32] } ; type %1
+ type { %struct.GAP } ; type %2
+ type { %struct.rec* } ; type %3
+ type { i8, i8, i16, i8, i8, i8, i8 } ; type %4
+ type { i8, i8, i8, i8 } ; type %5
+ %struct.COMPOSITE = type { i8, i16, i16 }
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.FILE_POS = type { i8, i8, i16, i32 }
+ %struct.FIRST_UNION = type { %struct.FILE_POS }
+ %struct.FONT_INFO = type { %struct.metrics*, i8*, i16*, %struct.COMPOSITE*, i32, %struct.rec*, %struct.rec*, i16, i16, i16*, i8*, i8*, i16* }
+ %struct.FOURTH_UNION = type { %struct.STYLE }
+ %struct.GAP = type { i8, i8, i16 }
+ %struct.LIST = type { %struct.rec*, %struct.rec* }
+ %struct.SECOND_UNION = type { %0 }
+ %struct.STYLE = type { %2, %2, i16, i16, i32 }
+ %struct.THIRD_UNION = type { %1 }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+ %struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, %struct.rec*, %3, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i32 }
+ %struct.metrics = type { i16, i16, i16, i16, i16 }
+ %struct.rec = type { %struct.head_type }
[email protected] = external constant [20 x i8], align 1 ; <[20 x i8]*> [#uses=1]
+@no_file_pos = external global %4 ; <%4*> [#uses=1]
[email protected] = external constant [9 x i8], align 1 ; <[9 x i8]*> [#uses=1]
+@zz_lengths = external global [150 x i8] ; <[150 x i8]*> [#uses=1]
+@next_free.4772 = external global i8** ; <i8***> [#uses=3]
+@top_free.4773 = external global i8** ; <i8***> [#uses=2]
[email protected] = external constant [32 x i8], align 1 ; <[32 x i8]*> [#uses=1]
+@zz_free = external global [524 x %struct.rec*] ; <[524 x %struct.rec*]*> [#uses=2]
+@zz_hold = external global %struct.rec* ; <%struct.rec**> [#uses=5]
+@zz_tmp = external global %struct.rec* ; <%struct.rec**> [#uses=2]
+@zz_res = external global %struct.rec* ; <%struct.rec**> [#uses=2]
+@xx_link = external global %struct.rec* ; <%struct.rec**> [#uses=2]
+@font_count = external global i32 ; <i32*> [#uses=1]
[email protected] = external constant [10 x i8], align 1 ; <[10 x i8]*> [#uses=1]
[email protected] = external constant [30 x i8], align 1 ; <[30 x i8]*> [#uses=1]
[email protected] = external constant [17 x i8], align 1 ; <[17 x i8]*> [#uses=1]
[email protected] = external constant [27 x i8], align 1 ; <[27 x i8]*> [#uses=1]
+@out_fp = external global %struct.FILE* ; <%struct.FILE**> [#uses=3]
[email protected] = external constant [17 x i8], align 1 ; <[17 x i8]*> [#uses=1]
+@cpexists = external global i32 ; <i32*> [#uses=2]
[email protected] = external constant [17 x i8], align 1 ; <[17 x i8]*> [#uses=1]
+@currentfont = external global i32 ; <i32*> [#uses=3]
+@wordcount = external global i32 ; <i32*> [#uses=1]
+@needs = external global %struct.rec* ; <%struct.rec**> [#uses=1]
[email protected] = external constant [6 x i8], align 1 ; <[6 x i8]*> [#uses=1]
[email protected] = external constant [10 x i8], align 1 ; <[10 x i8]*> [#uses=1]
[email protected] = external constant [40 x i8], align 1 ; <[40 x i8]*> [#uses=1]
[email protected] = external constant [8 x i8], align 1 ; <[8 x i8]*> [#uses=1]
[email protected] = external constant [11 x i8], align 1 ; <[11 x i8]*> [#uses=1]
[email protected] = external constant [23 x i8], align 1 ; <[23 x i8]*> [#uses=1]
[email protected] = external constant [17 x i8], align 1 ; <[17 x i8]*> [#uses=1]
[email protected] = external constant [26 x i8], align 1 ; <[26 x i8]*> [#uses=1]
+
+declare arm_apcscc i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind
+
+declare arm_apcscc i32 @"\01_fwrite"(i8*, i32, i32, i8*)
+
+declare arm_apcscc i32 @remove(i8* nocapture) nounwind
+
+declare arm_apcscc %struct.FILE* @OpenIncGraphicFile(i8*, i8 zeroext, %struct.rec** nocapture, %struct.FILE_POS*, i32* nocapture) nounwind
+
+declare arm_apcscc %struct.rec* @MakeWord(i32, i8* nocapture, %struct.FILE_POS*) nounwind
+
+declare arm_apcscc void @Error(i32, i32, i8*, i32, %struct.FILE_POS*, ...) nounwind
+
+declare arm_apcscc i32 @"\01_fputs"(i8*, %struct.FILE*)
+
+declare arm_apcscc noalias i8* @calloc(i32, i32) nounwind
+
+declare arm_apcscc i8* @fgets(i8*, i32, %struct.FILE* nocapture) nounwind
+
+define arm_apcscc void @PS_PrintGraphicInclude(%struct.rec* %x, i32 %colmark, i32 %rowmark) nounwind {
+entry:
+ %buff = alloca [512 x i8], align 4 ; <[512 x i8]*> [#uses=5]
+ %0 = getelementptr %struct.rec* %x, i32 0, i32 0, i32 1, i32 0, i32 0 ; <i8*> [#uses=2]
+ %1 = load i8* %0, align 4 ; <i8> [#uses=1]
+ %2 = add i8 %1, -94 ; <i8> [#uses=1]
+ %3 = icmp ugt i8 %2, 1 ; <i1> [#uses=1]
+ br i1 %3, label %bb, label %bb1
+
+bb: ; preds = %entry
+ br label %bb1
+
+bb1: ; preds = %bb, %entry
+ %4 = getelementptr %struct.rec* %x, i32 0, i32 0, i32 2 ; <%struct.SECOND_UNION*> [#uses=1]
+ %5 = bitcast %struct.SECOND_UNION* %4 to %5* ; <%5*> [#uses=1]
+ %6 = getelementptr %5* %5, i32 0, i32 1 ; <i8*> [#uses=1]
+ %7 = load i8* %6, align 1 ; <i8> [#uses=1]
+ %8 = icmp eq i8 %7, 0 ; <i1> [#uses=1]
+ br i1 %8, label %bb2, label %bb3
+
+bb2: ; preds = %bb1
+ call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([40 x i8]* @.str1802944, i32 0, i32 0)) nounwind
+ br label %bb3
+
+bb3: ; preds = %bb2, %bb1
+ %9 = load %struct.rec** undef, align 4 ; <%struct.rec*> [#uses=0]
+ br label %bb5
+
+bb5: ; preds = %bb5, %bb3
+ %y.0 = load %struct.rec** null ; <%struct.rec*> [#uses=2]
+ br i1 false, label %bb5, label %bb6
+
+bb6: ; preds = %bb5
+ %10 = load i8* %0, align 4 ; <i8> [#uses=1]
+ %11 = getelementptr %struct.rec* %y.0, i32 0, i32 0, i32 1, i32 0 ; <%struct.FILE_POS*> [#uses=1]
+ %12 = call arm_apcscc %struct.FILE* @OpenIncGraphicFile(i8* undef, i8 zeroext %10, %struct.rec** null, %struct.FILE_POS* %11, i32* undef) nounwind ; <%struct.FILE*> [#uses=4]
+ br i1 false, label %bb7, label %bb8
+
+bb7: ; preds = %bb6
+ unreachable
+
+bb8: ; preds = %bb6
+ %13 = and i32 undef, 4095 ; <i32> [#uses=2]
+ %14 = load i32* @currentfont, align 4 ; <i32> [#uses=0]
+ br i1 false, label %bb10, label %bb9
+
+bb9: ; preds = %bb8
+ %15 = icmp ult i32 0, %13 ; <i1> [#uses=1]
+ br i1 %15, label %bb.i, label %FontHalfXHeight.exit
+
+bb.i: ; preds = %bb9
+ call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([17 x i8]* @.str111875, i32 0, i32 0)) nounwind
+ %.pre186 = load i32* @currentfont, align 4 ; <i32> [#uses=1]
+ br label %FontHalfXHeight.exit
+
+FontHalfXHeight.exit: ; preds = %bb.i, %bb9
+ %16 = phi i32 [ %.pre186, %bb.i ], [ %13, %bb9 ] ; <i32> [#uses=1]
+ br i1 false, label %bb.i1, label %bb1.i
+
+bb.i1: ; preds = %FontHalfXHeight.exit
+ br label %bb1.i
+
+bb1.i: ; preds = %bb.i1, %FontHalfXHeight.exit
+ br i1 undef, label %bb2.i, label %FontSize.exit
+
+bb2.i: ; preds = %bb1.i
+ call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 37, i32 61, i8* getelementptr ([30 x i8]* @.str101874, i32 0, i32 0), i32 1, %struct.FILE_POS* null) nounwind
+ unreachable
+
+FontSize.exit: ; preds = %bb1.i
+ %17 = getelementptr %struct.FONT_INFO* undef, i32 %16, i32 5 ; <%struct.rec**> [#uses=0]
+ %18 = load i32* undef, align 4 ; <i32> [#uses=1]
+ %19 = load i32* @currentfont, align 4 ; <i32> [#uses=2]
+ %20 = load i32* @font_count, align 4 ; <i32> [#uses=1]
+ %21 = icmp ult i32 %20, %19 ; <i1> [#uses=1]
+ br i1 %21, label %bb.i5, label %FontName.exit
+
+bb.i5: ; preds = %FontSize.exit
+ call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([10 x i8]* @.str81872, i32 0, i32 0)) nounwind
+ br label %FontName.exit
+
+FontName.exit: ; preds = %bb.i5, %FontSize.exit
+ %22 = phi %struct.FONT_INFO* [ undef, %bb.i5 ], [ undef, %FontSize.exit ] ; <%struct.FONT_INFO*> [#uses=1]
+ %23 = getelementptr %struct.FONT_INFO* %22, i32 %19, i32 5 ; <%struct.rec**> [#uses=0]
+ %24 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([8 x i8]* @.str1822946, i32 0, i32 0), i32 %18, i8* null) nounwind ; <i32> [#uses=0]
+ br label %bb10
+
+bb10: ; preds = %FontName.exit, %bb8
+ %25 = call arm_apcscc i32 @"\01_fwrite"(i8* getelementptr ([11 x i8]* @.str1842948, i32 0, i32 0), i32 1, i32 10, i8* undef) nounwind ; <i32> [#uses=0]
+ %26 = sub i32 %rowmark, undef ; <i32> [#uses=1]
+ %27 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1]
+ %28 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %27, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 undef, i32 %26) nounwind ; <i32> [#uses=0]
+ store i32 0, i32* @cpexists, align 4
+ %29 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([17 x i8]* @.str192782, i32 0, i32 0), double 2.000000e+01, double 2.000000e+01) nounwind ; <i32> [#uses=0]
+ %30 = getelementptr %struct.rec* %y.0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 0 ; <i32*> [#uses=1]
+ %31 = load i32* %30, align 4 ; <i32> [#uses=1]
+ %32 = sub i32 0, %31 ; <i32> [#uses=1]
+ %33 = load i32* undef, align 4 ; <i32> [#uses=1]
+ %34 = sub i32 0, %33 ; <i32> [#uses=1]
+ %35 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1]
+ %36 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %35, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 %32, i32 %34) nounwind ; <i32> [#uses=0]
+ store i32 0, i32* @cpexists, align 4
+ %37 = load %struct.rec** null, align 4 ; <%struct.rec*> [#uses=1]
+ %38 = getelementptr %struct.rec* %37, i32 0, i32 0, i32 4 ; <%struct.FOURTH_UNION*> [#uses=1]
+ %39 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([23 x i8]* @.str1852949, i32 0, i32 0), %struct.FOURTH_UNION* %38) nounwind ; <i32> [#uses=0]
+ %buff14 = getelementptr [512 x i8]* %buff, i32 0, i32 0 ; <i8*> [#uses=5]
+ %40 = call arm_apcscc i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; <i8*> [#uses=0]
+ %iftmp.506.0 = select i1 undef, i32 2, i32 0 ; <i32> [#uses=1]
+ %41 = getelementptr [512 x i8]* %buff, i32 0, i32 26 ; <i8*> [#uses=1]
+ br label %bb100.outer.outer
+
+bb100.outer.outer: ; preds = %bb83, %bb10
+ %state.0.ph.ph = phi i32 [ %iftmp.506.0, %bb10 ], [ undef, %bb83 ] ; <i32> [#uses=1]
+ %x_addr.0.ph.ph = phi %struct.rec* [ %x, %bb10 ], [ %71, %bb83 ] ; <%struct.rec*> [#uses=1]
+ %42 = getelementptr %struct.rec* %x_addr.0.ph.ph, i32 0, i32 0, i32 1, i32 0 ; <%struct.FILE_POS*> [#uses=0]
+ br label %bb100.outer
+
+bb.i80: ; preds = %bb3.i85
+ %43 = icmp eq i8 %44, %46 ; <i1> [#uses=1]
+ %indvar.next.i79 = add i32 %indvar.i81, 1 ; <i32> [#uses=1]
+ br i1 %43, label %bb2.i84, label %bb2.i51
+
+bb2.i84: ; preds = %bb100.outer, %bb.i80
+ %indvar.i81 = phi i32 [ %indvar.next.i79, %bb.i80 ], [ 0, %bb100.outer ] ; <i32> [#uses=3]
+ %pp.0.i82 = getelementptr [27 x i8]* @.str141878, i32 0, i32 %indvar.i81 ; <i8*> [#uses=2]
+ %sp.0.i83 = getelementptr [512 x i8]* %buff, i32 0, i32 %indvar.i81 ; <i8*> [#uses=1]
+ %44 = load i8* %sp.0.i83, align 1 ; <i8> [#uses=2]
+ %45 = icmp eq i8 %44, 0 ; <i1> [#uses=1]
+ br i1 %45, label %StringBeginsWith.exit88thread-split, label %bb3.i85
+
+bb3.i85: ; preds = %bb2.i84
+ %46 = load i8* %pp.0.i82, align 1 ; <i8> [#uses=3]
+ %47 = icmp eq i8 %46, 0 ; <i1> [#uses=1]
+ br i1 %47, label %StringBeginsWith.exit88, label %bb.i80
+
+StringBeginsWith.exit88thread-split: ; preds = %bb2.i84
+ %.pr = load i8* %pp.0.i82 ; <i8> [#uses=1]
+ br label %StringBeginsWith.exit88
+
+StringBeginsWith.exit88: ; preds = %StringBeginsWith.exit88thread-split, %bb3.i85
+ %48 = phi i8 [ %.pr, %StringBeginsWith.exit88thread-split ], [ %46, %bb3.i85 ] ; <i8> [#uses=1]
+ %phitmp91 = icmp eq i8 %48, 0 ; <i1> [#uses=1]
+ br i1 %phitmp91, label %bb3.i77, label %bb2.i51
+
+bb2.i.i68: ; preds = %bb3.i77
+ br i1 false, label %bb2.i51, label %bb2.i75
+
+bb2.i75: ; preds = %bb2.i.i68
+ br label %bb3.i77
+
+bb3.i77: ; preds = %bb2.i75, %StringBeginsWith.exit88
+ %sp.0.i76 = getelementptr [512 x i8]* %buff, i32 0, i32 undef ; <i8*> [#uses=1]
+ %49 = load i8* %sp.0.i76, align 1 ; <i8> [#uses=1]
+ %50 = icmp eq i8 %49, 0 ; <i1> [#uses=1]
+ br i1 %50, label %bb24, label %bb2.i.i68
+
+bb24: ; preds = %bb3.i77
+ %51 = call arm_apcscc %struct.rec* @MakeWord(i32 11, i8* %41, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind ; <%struct.rec*> [#uses=0]
+ %52 = load i8* getelementptr ([150 x i8]* @zz_lengths, i32 0, i32 0), align 4 ; <i8> [#uses=1]
+ %53 = zext i8 %52 to i32 ; <i32> [#uses=2]
+ %54 = getelementptr [524 x %struct.rec*]* @zz_free, i32 0, i32 %53 ; <%struct.rec**> [#uses=2]
+ %55 = load %struct.rec** %54, align 4 ; <%struct.rec*> [#uses=3]
+ %56 = icmp eq %struct.rec* %55, null ; <i1> [#uses=1]
+ br i1 %56, label %bb27, label %bb28
+
+bb27: ; preds = %bb24
+ br i1 undef, label %bb.i56, label %GetMemory.exit62
+
+bb.i56: ; preds = %bb27
+ br i1 undef, label %bb1.i58, label %bb2.i60
+
+bb1.i58: ; preds = %bb.i56
+ call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 31, i32 1, i8* getelementptr ([32 x i8]* @.str1575, i32 0, i32 0), i32 1, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind
+ br label %bb2.i60
+
+bb2.i60: ; preds = %bb1.i58, %bb.i56
+ %.pre1.i59 = phi i8** [ undef, %bb1.i58 ], [ undef, %bb.i56 ] ; <i8**> [#uses=1]
+ store i8** undef, i8*** @top_free.4773, align 4
+ br label %GetMemory.exit62
+
+GetMemory.exit62: ; preds = %bb2.i60, %bb27
+ %57 = phi i8** [ %.pre1.i59, %bb2.i60 ], [ undef, %bb27 ] ; <i8**> [#uses=1]
+ %58 = getelementptr i8** %57, i32 %53 ; <i8**> [#uses=1]
+ store i8** %58, i8*** @next_free.4772, align 4
+ store %struct.rec* undef, %struct.rec** @zz_hold, align 4
+ br label %bb29
+
+bb28: ; preds = %bb24
+ store %struct.rec* %55, %struct.rec** @zz_hold, align 4
+ %59 = load %struct.rec** null, align 4 ; <%struct.rec*> [#uses=1]
+ store %struct.rec* %59, %struct.rec** %54, align 4
+ br label %bb29
+
+bb29: ; preds = %bb28, %GetMemory.exit62
+ %.pre184 = phi %struct.rec* [ %55, %bb28 ], [ undef, %GetMemory.exit62 ] ; <%struct.rec*> [#uses=3]
+ store i8 0, i8* undef
+ store %struct.rec* %.pre184, %struct.rec** @xx_link, align 4
+ br i1 undef, label %bb35, label %bb31
+
+bb31: ; preds = %bb29
+ store %struct.rec* %.pre184, %struct.rec** undef
+ br label %bb35
+
+bb35: ; preds = %bb31, %bb29
+ br i1 undef, label %bb41, label %bb37
+
+bb37: ; preds = %bb35
+ %60 = load %struct.rec** null, align 4 ; <%struct.rec*> [#uses=1]
+ store %struct.rec* %60, %struct.rec** undef
+ store %struct.rec* undef, %struct.rec** null
+ store %struct.rec* %.pre184, %struct.rec** null, align 4
+ br label %bb41
+
+bb41: ; preds = %bb37, %bb35
+ %61 = call arm_apcscc i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; <i8*> [#uses=1]
+ %62 = icmp eq i8* %61, null ; <i1> [#uses=1]
+ %iftmp.554.0 = select i1 %62, i32 2, i32 1 ; <i32> [#uses=1]
+ br label %bb100.outer
+
+bb.i47: ; preds = %bb3.i52
+ %63 = icmp eq i8 %64, %65 ; <i1> [#uses=1]
+ br i1 %63, label %bb2.i51, label %bb2.i41
+
+bb2.i51: ; preds = %bb.i47, %bb2.i.i68, %StringBeginsWith.exit88, %bb.i80
+ %pp.0.i49 = getelementptr [17 x i8]* @.str1872951, i32 0, i32 0 ; <i8*> [#uses=1]
+ %64 = load i8* null, align 1 ; <i8> [#uses=1]
+ br i1 false, label %StringBeginsWith.exit55thread-split, label %bb3.i52
+
+bb3.i52: ; preds = %bb2.i51
+ %65 = load i8* %pp.0.i49, align 1 ; <i8> [#uses=1]
+ br i1 false, label %StringBeginsWith.exit55, label %bb.i47
+
+StringBeginsWith.exit55thread-split: ; preds = %bb2.i51
+ br label %StringBeginsWith.exit55
+
+StringBeginsWith.exit55: ; preds = %StringBeginsWith.exit55thread-split, %bb3.i52
+ br i1 false, label %bb49, label %bb2.i41
+
+bb49: ; preds = %StringBeginsWith.exit55
+ br label %bb2.i41
+
+bb2.i41: ; preds = %bb2.i41, %bb49, %StringBeginsWith.exit55, %bb.i47
+ br i1 false, label %bb2.i41, label %bb2.i.i15
+
+bb2.i.i15: ; preds = %bb2.i41
+ %pp.0.i.i13 = getelementptr [6 x i8]* @.str742838, i32 0, i32 0 ; <i8*> [#uses=1]
+ br i1 false, label %StringBeginsWith.exitthread-split.i18, label %bb3.i.i16
+
+bb3.i.i16: ; preds = %bb2.i.i15
+ %66 = load i8* %pp.0.i.i13, align 1 ; <i8> [#uses=1]
+ br label %StringBeginsWith.exit.i20
+
+StringBeginsWith.exitthread-split.i18: ; preds = %bb2.i.i15
+ br label %StringBeginsWith.exit.i20
+
+StringBeginsWith.exit.i20: ; preds = %StringBeginsWith.exitthread-split.i18, %bb3.i.i16
+ %67 = phi i8 [ undef, %StringBeginsWith.exitthread-split.i18 ], [ %66, %bb3.i.i16 ] ; <i8> [#uses=1]
+ %phitmp.i19 = icmp eq i8 %67, 0 ; <i1> [#uses=1]
+ br i1 %phitmp.i19, label %bb58, label %bb2.i6.i26
+
+bb2.i6.i26: ; preds = %bb2.i6.i26, %StringBeginsWith.exit.i20
+ %indvar.i3.i23 = phi i32 [ %indvar.next.i1.i21, %bb2.i6.i26 ], [ 0, %StringBeginsWith.exit.i20 ] ; <i32> [#uses=3]
+ %sp.0.i5.i25 = getelementptr [512 x i8]* %buff, i32 0, i32 %indvar.i3.i23 ; <i8*> [#uses=0]
+ %pp.0.i4.i24 = getelementptr [10 x i8]* @.str752839, i32 0, i32 %indvar.i3.i23 ; <i8*> [#uses=1]
+ %68 = load i8* %pp.0.i4.i24, align 1 ; <i8> [#uses=0]
+ %indvar.next.i1.i21 = add i32 %indvar.i3.i23, 1 ; <i32> [#uses=1]
+ br i1 undef, label %bb2.i6.i26, label %bb55
+
+bb55: ; preds = %bb2.i6.i26
+ %69 = call arm_apcscc i32 @"\01_fputs"(i8* %buff14, %struct.FILE* undef) nounwind ; <i32> [#uses=0]
+ unreachable
+
+bb58: ; preds = %StringBeginsWith.exit.i20
+ %70 = call arm_apcscc i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; <i8*> [#uses=0]
+ %iftmp.560.0 = select i1 undef, i32 2, i32 0 ; <i32> [#uses=1]
+ br label %bb100.outer
+
+bb.i7: ; preds = %bb3.i
+ br i1 false, label %bb2.i8, label %bb2.i.i
+
+bb2.i8: ; preds = %bb100.outer, %bb.i7
+ br i1 undef, label %StringBeginsWith.exitthread-split, label %bb3.i
+
+bb3.i: ; preds = %bb2.i8
+ br i1 undef, label %StringBeginsWith.exit, label %bb.i7
+
+StringBeginsWith.exitthread-split: ; preds = %bb2.i8
+ br label %StringBeginsWith.exit
+
+StringBeginsWith.exit: ; preds = %StringBeginsWith.exitthread-split, %bb3.i
+ %phitmp93 = icmp eq i8 undef, 0 ; <i1> [#uses=1]
+ br i1 %phitmp93, label %bb66, label %bb2.i.i
+
+bb66: ; preds = %StringBeginsWith.exit
+ %71 = call arm_apcscc %struct.rec* @MakeWord(i32 11, i8* undef, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind ; <%struct.rec*> [#uses=4]
+ %72 = load i8* getelementptr ([150 x i8]* @zz_lengths, i32 0, i32 0), align 4 ; <i8> [#uses=1]
+ %73 = zext i8 %72 to i32 ; <i32> [#uses=2]
+ %74 = getelementptr [524 x %struct.rec*]* @zz_free, i32 0, i32 %73 ; <%struct.rec**> [#uses=2]
+ %75 = load %struct.rec** %74, align 4 ; <%struct.rec*> [#uses=3]
+ %76 = icmp eq %struct.rec* %75, null ; <i1> [#uses=1]
+ br i1 %76, label %bb69, label %bb70
+
+bb69: ; preds = %bb66
+ br i1 undef, label %bb.i2, label %GetMemory.exit
+
+bb.i2: ; preds = %bb69
+ %77 = call arm_apcscc noalias i8* @calloc(i32 1020, i32 4) nounwind ; <i8*> [#uses=1]
+ %78 = bitcast i8* %77 to i8** ; <i8**> [#uses=3]
+ store i8** %78, i8*** @next_free.4772, align 4
+ br i1 undef, label %bb1.i3, label %bb2.i4
+
+bb1.i3: ; preds = %bb.i2
+ call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 31, i32 1, i8* getelementptr ([32 x i8]* @.str1575, i32 0, i32 0), i32 1, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind
+ br label %bb2.i4
+
+bb2.i4: ; preds = %bb1.i3, %bb.i2
+ %.pre1.i = phi i8** [ undef, %bb1.i3 ], [ %78, %bb.i2 ] ; <i8**> [#uses=1]
+ %79 = phi i8** [ undef, %bb1.i3 ], [ %78, %bb.i2 ] ; <i8**> [#uses=1]
+ %80 = getelementptr i8** %79, i32 1020 ; <i8**> [#uses=1]
+ store i8** %80, i8*** @top_free.4773, align 4
+ br label %GetMemory.exit
+
+GetMemory.exit: ; preds = %bb2.i4, %bb69
+ %81 = phi i8** [ %.pre1.i, %bb2.i4 ], [ undef, %bb69 ] ; <i8**> [#uses=2]
+ %82 = bitcast i8** %81 to %struct.rec* ; <%struct.rec*> [#uses=3]
+ %83 = getelementptr i8** %81, i32 %73 ; <i8**> [#uses=1]
+ store i8** %83, i8*** @next_free.4772, align 4
+ store %struct.rec* %82, %struct.rec** @zz_hold, align 4
+ br label %bb71
+
+bb70: ; preds = %bb66
+ %84 = load %struct.rec** null, align 4 ; <%struct.rec*> [#uses=1]
+ store %struct.rec* %84, %struct.rec** %74, align 4
+ br label %bb71
+
+bb71: ; preds = %bb70, %GetMemory.exit
+ %.pre185 = phi %struct.rec* [ %75, %bb70 ], [ %82, %GetMemory.exit ] ; <%struct.rec*> [#uses=8]
+ %85 = phi %struct.rec* [ %75, %bb70 ], [ %82, %GetMemory.exit ] ; <%struct.rec*> [#uses=1]
+ %86 = getelementptr %struct.rec* %85, i32 0, i32 0, i32 1, i32 0, i32 0 ; <i8*> [#uses=0]
+ %87 = getelementptr %struct.rec* %.pre185, i32 0, i32 0, i32 0, i32 1, i32 1 ; <%struct.rec**> [#uses=0]
+ %88 = getelementptr %struct.rec* %.pre185, i32 0, i32 0, i32 0, i32 1, i32 0 ; <%struct.rec**> [#uses=1]
+ store %struct.rec* %.pre185, %struct.rec** @xx_link, align 4
+ store %struct.rec* %.pre185, %struct.rec** @zz_res, align 4
+ %89 = load %struct.rec** @needs, align 4 ; <%struct.rec*> [#uses=2]
+ store %struct.rec* %89, %struct.rec** @zz_hold, align 4
+ br i1 false, label %bb77, label %bb73
+
+bb73: ; preds = %bb71
+ %90 = getelementptr %struct.rec* %89, i32 0, i32 0, i32 0, i32 0, i32 0 ; <%struct.rec**> [#uses=1]
+ store %struct.rec* null, %struct.rec** @zz_tmp, align 4
+ store %struct.rec* %.pre185, %struct.rec** %90
+ store %struct.rec* %.pre185, %struct.rec** undef, align 4
+ br label %bb77
+
+bb77: ; preds = %bb73, %bb71
+ store %struct.rec* %.pre185, %struct.rec** @zz_res, align 4
+ store %struct.rec* %71, %struct.rec** @zz_hold, align 4
+ br i1 undef, label %bb83, label %bb79
+
+bb79: ; preds = %bb77
+ %91 = getelementptr %struct.rec* %71, i32 0, i32 0, i32 0, i32 1, i32 0 ; <%struct.rec**> [#uses=1]
+ store %struct.rec* null, %struct.rec** @zz_tmp, align 4
+ %92 = load %struct.rec** %88, align 4 ; <%struct.rec*> [#uses=1]
+ store %struct.rec* %92, %struct.rec** %91
+ %93 = getelementptr %struct.rec* undef, i32 0, i32 0, i32 0, i32 1, i32 1 ; <%struct.rec**> [#uses=1]
+ store %struct.rec* %71, %struct.rec** %93, align 4
+ store %struct.rec* %.pre185, %struct.rec** undef, align 4
+ br label %bb83
+
+bb83: ; preds = %bb79, %bb77
+ br label %bb100.outer.outer
+
+bb.i.i: ; preds = %bb3.i.i
+ br i1 undef, label %bb2.i.i, label %bb2.i6.i
+
+bb2.i.i: ; preds = %bb.i.i, %StringBeginsWith.exit, %bb.i7
+ br i1 undef, label %StringBeginsWith.exitthread-split.i, label %bb3.i.i
+
+bb3.i.i: ; preds = %bb2.i.i
+ br i1 undef, label %StringBeginsWith.exit.i, label %bb.i.i
+
+StringBeginsWith.exitthread-split.i: ; preds = %bb2.i.i
+ br label %StringBeginsWith.exit.i
+
+StringBeginsWith.exit.i: ; preds = %StringBeginsWith.exitthread-split.i, %bb3.i.i
+ br i1 false, label %bb94, label %bb2.i6.i
+
+bb.i2.i: ; preds = %bb3.i7.i
+ br i1 false, label %bb2.i6.i, label %bb91
+
+bb2.i6.i: ; preds = %bb.i2.i, %StringBeginsWith.exit.i, %bb.i.i
+ br i1 undef, label %strip_out.exitthread-split, label %bb3.i7.i
+
+bb3.i7.i: ; preds = %bb2.i6.i
+ %94 = load i8* undef, align 1 ; <i8> [#uses=1]
+ br i1 undef, label %strip_out.exit, label %bb.i2.i
+
+strip_out.exitthread-split: ; preds = %bb2.i6.i
+ %.pr100 = load i8* undef ; <i8> [#uses=1]
+ br label %strip_out.exit
+
+strip_out.exit: ; preds = %strip_out.exitthread-split, %bb3.i7.i
+ %95 = phi i8 [ %.pr100, %strip_out.exitthread-split ], [ %94, %bb3.i7.i ] ; <i8> [#uses=0]
+ br i1 undef, label %bb94, label %bb91
+
+bb91: ; preds = %strip_out.exit, %bb.i2.i
+ unreachable
+
+bb94: ; preds = %strip_out.exit, %StringBeginsWith.exit.i
+ %96 = call arm_apcscc i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; <i8*> [#uses=0]
+ unreachable
+
+bb100.outer: ; preds = %bb58, %bb41, %bb100.outer.outer
+ %state.0.ph = phi i32 [ %state.0.ph.ph, %bb100.outer.outer ], [ %iftmp.560.0, %bb58 ], [ %iftmp.554.0, %bb41 ] ; <i32> [#uses=1]
+ switch i32 %state.0.ph, label %bb2.i84 [
+ i32 2, label %bb101.split
+ i32 1, label %bb2.i8
+ ]
+
+bb101.split: ; preds = %bb100.outer
+ %97 = icmp eq i32 undef, 0 ; <i1> [#uses=1]
+ br i1 %97, label %bb103, label %bb102
+
+bb102: ; preds = %bb101.split
+ %98 = call arm_apcscc i32 @remove(i8* getelementptr ([9 x i8]* @.str19294, i32 0, i32 0)) nounwind ; <i32> [#uses=0]
+ unreachable
+
+bb103: ; preds = %bb101.split
+ %99 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1]
+ %100 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %99, i8* getelementptr ([26 x i8]* @.str1932957, i32 0, i32 0)) nounwind ; <i32> [#uses=0]
+ store i32 0, i32* @wordcount, align 4
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll
new file mode 100644
index 0000000..7647474
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp | not grep fcpys
+; rdar://7117307
+
+ %struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }
+ %struct.List = type { %struct.List*, %struct.Patient*, %struct.List* }
+ %struct.Patient = type { i32, i32, i32, %struct.Village* }
+ %struct.Results = type { float, float, float }
+ %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 }
+
+define arm_apcscc void @get_results(%struct.Results* noalias nocapture sret %agg.result, %struct.Village* %village) nounwind {
+entry:
+ br i1 undef, label %bb, label %bb6.preheader
+
+bb6.preheader: ; preds = %entry
+ call void @llvm.memcpy.i32(i8* undef, i8* undef, i32 12, i32 4)
+ br i1 undef, label %bb15, label %bb13
+
+bb: ; preds = %entry
+ ret void
+
+bb13: ; preds = %bb13, %bb6.preheader
+ %0 = fadd float undef, undef ; <float> [#uses=1]
+ %1 = fadd float undef, 1.000000e+00 ; <float> [#uses=1]
+ br i1 undef, label %bb15, label %bb13
+
+bb15: ; preds = %bb13, %bb6.preheader
+ %r1.0.0.lcssa = phi float [ 0.000000e+00, %bb6.preheader ], [ %1, %bb13 ] ; <float> [#uses=1]
+ %r1.1.0.lcssa = phi float [ undef, %bb6.preheader ], [ %0, %bb13 ] ; <float> [#uses=0]
+ store float %r1.0.0.lcssa, float* undef, align 4
+ ret void
+}
+
+declare void @llvm.memcpy.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind
diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll
new file mode 100644
index 0000000..acf562c
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp
+; rdar://7117307
+
+ %struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }
+ %struct.List = type { %struct.List*, %struct.Patient*, %struct.List* }
+ %struct.Patient = type { i32, i32, i32, %struct.Village* }
+ %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 }
+
+define arm_apcscc %struct.List* @sim(%struct.Village* %village) nounwind {
+entry:
+ br i1 undef, label %bb14, label %bb3.preheader
+
+bb3.preheader: ; preds = %entry
+ br label %bb5
+
+bb5: ; preds = %bb5, %bb3.preheader
+ br i1 undef, label %bb11, label %bb5
+
+bb11: ; preds = %bb5
+ %0 = fmul float undef, 0x41E0000000000000 ; <float> [#uses=1]
+ %1 = fptosi float %0 to i32 ; <i32> [#uses=1]
+ store i32 %1, i32* undef, align 4
+ br i1 undef, label %generate_patient.exit, label %generate_patient.exit.thread
+
+generate_patient.exit.thread: ; preds = %bb11
+ ret %struct.List* null
+
+generate_patient.exit: ; preds = %bb11
+ br i1 undef, label %bb14, label %bb12
+
+bb12: ; preds = %generate_patient.exit
+ br i1 undef, label %bb.i, label %bb1.i
+
+bb.i: ; preds = %bb12
+ ret %struct.List* null
+
+bb1.i: ; preds = %bb12
+ ret %struct.List* null
+
+bb14: ; preds = %generate_patient.exit, %entry
+ ret %struct.List* undef
+}
diff --git a/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll
new file mode 100644
index 0000000..3ada026
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll
@@ -0,0 +1,54 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp
+; rdar://7117307
+
+ %struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }
+ %struct.List = type { %struct.List*, %struct.Patient*, %struct.List* }
+ %struct.Patient = type { i32, i32, i32, %struct.Village* }
+ %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 }
+
+define arm_apcscc %struct.List* @sim(%struct.Village* %village) nounwind {
+entry:
+ br i1 undef, label %bb14, label %bb3.preheader
+
+bb3.preheader: ; preds = %entry
+ br label %bb5
+
+bb5: ; preds = %bb5, %bb3.preheader
+ br i1 undef, label %bb11, label %bb5
+
+bb11: ; preds = %bb5
+ %0 = load i32* undef, align 4 ; <i32> [#uses=1]
+ %1 = xor i32 %0, 123459876 ; <i32> [#uses=1]
+ %2 = sdiv i32 %1, 127773 ; <i32> [#uses=1]
+ %3 = mul i32 %2, 2836 ; <i32> [#uses=1]
+ %4 = sub i32 0, %3 ; <i32> [#uses=1]
+ %5 = xor i32 %4, 123459876 ; <i32> [#uses=1]
+ %idum_addr.0.i.i = select i1 undef, i32 undef, i32 %5 ; <i32> [#uses=1]
+ %6 = sitofp i32 %idum_addr.0.i.i to double ; <double> [#uses=1]
+ %7 = fmul double %6, 0x3E00000000200000 ; <double> [#uses=1]
+ %8 = fptrunc double %7 to float ; <float> [#uses=2]
+ %9 = fmul float %8, 0x41E0000000000000 ; <float> [#uses=1]
+ %10 = fptosi float %9 to i32 ; <i32> [#uses=1]
+ store i32 %10, i32* undef, align 4
+ %11 = fpext float %8 to double ; <double> [#uses=1]
+ %12 = fcmp ogt double %11, 6.660000e-01 ; <i1> [#uses=1]
+ br i1 %12, label %generate_patient.exit, label %generate_patient.exit.thread
+
+generate_patient.exit.thread: ; preds = %bb11
+ ret %struct.List* null
+
+generate_patient.exit: ; preds = %bb11
+ br i1 undef, label %bb14, label %bb12
+
+bb12: ; preds = %generate_patient.exit
+ br i1 undef, label %bb.i, label %bb1.i
+
+bb.i: ; preds = %bb12
+ ret %struct.List* null
+
+bb1.i: ; preds = %bb12
+ ret %struct.List* null
+
+bb14: ; preds = %generate_patient.exit, %entry
+ ret %struct.List* undef
+}
diff --git a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
new file mode 100644
index 0000000..4077535
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s
+; PR4659
+; PR4682
+
+define hidden arm_aapcscc i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind {
+entry:
+; CHECK: __gcov_execlp:
+; CHECK: mov sp, r7
+; CHECK: sub sp, #4
+ call arm_aapcscc void @__gcov_flush() nounwind
+ br i1 undef, label %bb5, label %bb
+
+bb: ; preds = %bb, %entry
+ br i1 undef, label %bb5, label %bb
+
+bb5: ; preds = %bb, %entry
+ %0 = alloca i8*, i32 undef, align 4 ; <i8**> [#uses=1]
+ %1 = call arm_aapcscc i32 @execvp(i8* %path, i8** %0) nounwind ; <i32> [#uses=1]
+ ret i32 %1
+}
+
+declare hidden arm_aapcscc void @__gcov_flush()
+
+declare arm_aapcscc i32 @execvp(i8*, i8**) nounwind
diff --git a/test/CodeGen/Thumb2/2009-08-07-CoalescerBug.ll b/test/CodeGen/Thumb2/2009-08-07-CoalescerBug.ll
new file mode 100644
index 0000000..93f5a0f
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-08-07-CoalescerBug.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=armv7-eabi -mattr=+vfp2
+; PR4686
+
+ %a = type { i32 (...)** }
+ %b = type { %a }
+ %c = type { float, float, float, float }
+
+declare arm_aapcs_vfpcc float @bar(%c*)
+
+define arm_aapcs_vfpcc void @foo(%b* %x, %c* %y) {
+entry:
+ %0 = call arm_aapcs_vfpcc float @bar(%c* %y) ; <float> [#uses=0]
+ %1 = fadd float undef, undef ; <float> [#uses=1]
+ store float %1, float* undef, align 8
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll b/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll
new file mode 100644
index 0000000..090ed2d
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll
@@ -0,0 +1,80 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 -arm-use-neon-fp
+
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.JHUFF_TBL = type { [17 x i8], [256 x i8], i32 }
+ %struct.JQUANT_TBL = type { [64 x i16], i32 }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+ %struct.anon = type { [8 x i32], [48 x i8] }
+ %struct.backing_store_info = type { void (%struct.jpeg_common_struct*, %struct.backing_store_info*, i8*, i32, i32)*, void (%struct.jpeg_common_struct*, %struct.backing_store_info*, i8*, i32, i32)*, void (%struct.jpeg_common_struct*, %struct.backing_store_info*)*, %struct.FILE*, [64 x i8] }
+ %struct.jpeg_color_deconverter = type { void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*, i8***, i32, i8**, i32)* }
+ %struct.jpeg_color_quantizer = type { void (%struct.jpeg_decompress_struct*, i32)*, void (%struct.jpeg_decompress_struct*, i8**, i8**, i32)*, void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)* }
+ %struct.jpeg_common_struct = type { %struct.jpeg_error_mgr*, %struct.jpeg_memory_mgr*, %struct.jpeg_progress_mgr*, i32, i32 }
+ %struct.jpeg_component_info = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.JQUANT_TBL*, i8* }
+ %struct.jpeg_d_coef_controller = type { void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*, i8***)*, %struct.jvirt_barray_control** }
+ %struct.jpeg_d_main_controller = type { void (%struct.jpeg_decompress_struct*, i32)*, void (%struct.jpeg_decompress_struct*, i8**, i32*, i32)* }
+ %struct.jpeg_d_post_controller = type { void (%struct.jpeg_decompress_struct*, i32)*, void (%struct.jpeg_decompress_struct*, i8***, i32*, i32, i8**, i32*, i32)* }
+ %struct.jpeg_decomp_master = type { void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, i32 }
+ %struct.jpeg_decompress_struct = type { %struct.jpeg_error_mgr*, %struct.jpeg_memory_mgr*, %struct.jpeg_progress_mgr*, i32, i32, %struct.jpeg_source_mgr*, i32, i32, i32, i32, i32, i32, i32, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8**, i32, i32, i32, i32, i32, [64 x i32]*, [4 x %struct.JQUANT_TBL*], [4 x %struct.JHUFF_TBL*], [4 x %struct.JHUFF_TBL*], i32, %struct.jpeg_component_info*, i32, i32, [16 x i8], [16 x i8], [16 x i8], i32, i32, i8, i16, i16, i32, i8, i32, i32, i32, i32, i32, i8*, i32, [4 x %struct.jpeg_component_info*], i32, i32, i32, [10 x i32], i32, i32, i32, i32, i32, %struct.jpeg_decomp_master*, %struct.jpeg_d_main_controller*, %struct.jpeg_d_coef_controller*, %struct.jpeg_d_post_controller*, %struct.jpeg_input_controller*, %struct.jpeg_marker_reader*, %struct.jpeg_entropy_decoder*, %struct.jpeg_inverse_dct*, %struct.jpeg_upsampler*, %struct.jpeg_color_deconverter*, %struct.jpeg_color_quantizer* }
+ %struct.jpeg_entropy_decoder = type { void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*, [64 x i16]**)* }
+ %struct.jpeg_error_mgr = type { void (%struct.jpeg_common_struct*)*, void (%struct.jpeg_common_struct*, i32)*, void (%struct.jpeg_common_struct*)*, void (%struct.jpeg_common_struct*, i8*)*, void (%struct.jpeg_common_struct*)*, i32, %struct.anon, i32, i32, i8**, i32, i8**, i32, i32 }
+ %struct.jpeg_input_controller = type { i32 (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*)*, i32, i32 }
+ %struct.jpeg_inverse_dct = type { void (%struct.jpeg_decompress_struct*)*, [10 x void (%struct.jpeg_decompress_struct*, %struct.jpeg_component_info*, i16*, i8**, i32)*] }
+ %struct.jpeg_marker_reader = type { void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, [16 x i32 (%struct.jpeg_decompress_struct*)*], i32, i32, i32, i32 }
+ %struct.jpeg_memory_mgr = type { i8* (%struct.jpeg_common_struct*, i32, i32)*, i8* (%struct.jpeg_common_struct*, i32, i32)*, i8** (%struct.jpeg_common_struct*, i32, i32, i32)*, [64 x i16]** (%struct.jpeg_common_struct*, i32, i32, i32)*, %struct.jvirt_sarray_control* (%struct.jpeg_common_struct*, i32, i32, i32, i32, i32)*, %struct.jvirt_barray_control* (%struct.jpeg_common_struct*, i32, i32, i32, i32, i32)*, void (%struct.jpeg_common_struct*)*, i8** (%struct.jpeg_common_struct*, %struct.jvirt_sarray_control*, i32, i32, i32)*, [64 x i16]** (%struct.jpeg_common_struct*, %struct.jvirt_barray_control*, i32, i32, i32)*, void (%struct.jpeg_common_struct*, i32)*, void (%struct.jpeg_common_struct*)*, i32 }
+ %struct.jpeg_progress_mgr = type { void (%struct.jpeg_common_struct*)*, i32, i32, i32, i32 }
+ %struct.jpeg_source_mgr = type { i8*, i32, void (%struct.jpeg_decompress_struct*)*, i32 (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*, i32)*, i32 (%struct.jpeg_decompress_struct*, i32)*, void (%struct.jpeg_decompress_struct*)* }
+ %struct.jpeg_upsampler = type { void (%struct.jpeg_decompress_struct*)*, void (%struct.jpeg_decompress_struct*, i8***, i32*, i32, i8**, i32*, i32)*, i32 }
+ %struct.jvirt_barray_control = type { [64 x i16]**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_barray_control*, %struct.backing_store_info }
+ %struct.jvirt_sarray_control = type { i8**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_sarray_control*, %struct.backing_store_info }
+
+define arm_apcscc void @jpeg_idct_float(%struct.jpeg_decompress_struct* nocapture %cinfo, %struct.jpeg_component_info* nocapture %compptr, i16* nocapture %coef_block, i8** nocapture %output_buf, i32 %output_col) nounwind {
+entry:
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %0 = load float* undef, align 4 ; <float> [#uses=1]
+ %1 = fmul float undef, %0 ; <float> [#uses=2]
+ %tmp73 = add i32 0, 224 ; <i32> [#uses=1]
+ %scevgep74 = getelementptr i8* null, i32 %tmp73 ; <i8*> [#uses=1]
+ %scevgep7475 = bitcast i8* %scevgep74 to float* ; <float*> [#uses=1]
+ %2 = load float* null, align 4 ; <float> [#uses=1]
+ %3 = fmul float 0.000000e+00, %2 ; <float> [#uses=2]
+ %4 = fadd float %1, %3 ; <float> [#uses=1]
+ %5 = fsub float %1, %3 ; <float> [#uses=2]
+ %6 = fadd float undef, 0.000000e+00 ; <float> [#uses=2]
+ %7 = fmul float undef, 0x3FF6A09E60000000 ; <float> [#uses=1]
+ %8 = fsub float %7, %6 ; <float> [#uses=2]
+ %9 = fsub float %4, %6 ; <float> [#uses=1]
+ %10 = fadd float %5, %8 ; <float> [#uses=2]
+ %11 = fsub float %5, %8 ; <float> [#uses=1]
+ %12 = sitofp i16 undef to float ; <float> [#uses=1]
+ %13 = fmul float %12, 0.000000e+00 ; <float> [#uses=2]
+ %14 = sitofp i16 undef to float ; <float> [#uses=1]
+ %15 = load float* %scevgep7475, align 4 ; <float> [#uses=1]
+ %16 = fmul float %14, %15 ; <float> [#uses=2]
+ %17 = fadd float undef, undef ; <float> [#uses=2]
+ %18 = fadd float %13, %16 ; <float> [#uses=2]
+ %19 = fsub float %13, %16 ; <float> [#uses=1]
+ %20 = fadd float %18, %17 ; <float> [#uses=2]
+ %21 = fsub float %18, %17 ; <float> [#uses=1]
+ %22 = fmul float %21, 0x3FF6A09E60000000 ; <float> [#uses=1]
+ %23 = fmul float undef, 0x3FFD906BC0000000 ; <float> [#uses=2]
+ %24 = fmul float %19, 0x3FF1517A80000000 ; <float> [#uses=1]
+ %25 = fsub float %24, %23 ; <float> [#uses=1]
+ %26 = fadd float undef, %23 ; <float> [#uses=1]
+ %27 = fsub float %26, %20 ; <float> [#uses=3]
+ %28 = fsub float %22, %27 ; <float> [#uses=2]
+ %29 = fadd float %25, %28 ; <float> [#uses=1]
+ %30 = fadd float undef, %20 ; <float> [#uses=1]
+ store float %30, float* undef, align 4
+ %31 = fadd float %10, %27 ; <float> [#uses=1]
+ store float %31, float* undef, align 4
+ %32 = fsub float %10, %27 ; <float> [#uses=1]
+ store float %32, float* undef, align 4
+ %33 = fadd float %11, %28 ; <float> [#uses=1]
+ store float %33, float* undef, align 4
+ %34 = fsub float %9, %29 ; <float> [#uses=1]
+ store float %34, float* undef, align 4
+ br label %bb
+}
diff --git a/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll b/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll
new file mode 100644
index 0000000..a0f9918
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -mtriple=armv7-eabi -mattr=+vfp2
+; PR4686
+
+@g_d = external global double ; <double*> [#uses=1]
+
+define arm_aapcscc void @foo(float %yIncr) {
+entry:
+ br i1 undef, label %bb, label %bb4
+
+bb: ; preds = %entry
+ %0 = call arm_aapcs_vfpcc float @bar() ; <float> [#uses=1]
+ %1 = fpext float %0 to double ; <double> [#uses=1]
+ store double %1, double* @g_d, align 8
+ br label %bb4
+
+bb4: ; preds = %bb, %entry
+ unreachable
+}
+
+declare arm_aapcs_vfpcc float @bar()
diff --git a/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll b/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll
new file mode 100644
index 0000000..cbe250b
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+vfp2
+
+define arm_apcscc float @t1(i32 %v0) nounwind {
+entry:
+ store i32 undef, i32* undef, align 4
+ %0 = load [4 x i8]** undef, align 4 ; <[4 x i8]*> [#uses=1]
+ %1 = load i8* undef, align 1 ; <i8> [#uses=1]
+ %2 = zext i8 %1 to i32 ; <i32> [#uses=1]
+ %3 = getelementptr [4 x i8]* %0, i32 %v0, i32 0 ; <i8*> [#uses=1]
+ %4 = load i8* %3, align 1 ; <i8> [#uses=1]
+ %5 = zext i8 %4 to i32 ; <i32> [#uses=1]
+ %6 = sub i32 %5, %2 ; <i32> [#uses=1]
+ %7 = sitofp i32 %6 to float ; <float> [#uses=1]
+ ret float %7
+}
diff --git a/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll b/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
new file mode 100644
index 0000000..8d03b52
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
@@ -0,0 +1,152 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
+
+%struct.pix_pos = type { i32, i32, i32, i32, i32, i32 }
+
+@getNeighbour = external global void (i32, i32, i32, i32, %struct.pix_pos*)*, align 4 ; <void (i32, i32, i32, i32, %struct.pix_pos*)**> [#uses=2]
+
+define arm_apcscc void @t() nounwind {
+; CHECK: t:
+; CHECK: it eq
+; CHECK-NEXT: cmpeq
+entry:
+ %pix_a.i294 = alloca [4 x %struct.pix_pos], align 4 ; <[4 x %struct.pix_pos]*> [#uses=2]
+ br i1 undef, label %land.rhs, label %lor.end
+
+land.rhs: ; preds = %entry
+ br label %lor.end
+
+lor.end: ; preds = %land.rhs, %entry
+ switch i32 0, label %if.end371 [
+ i32 10, label %if.then366
+ i32 14, label %if.then366
+ ]
+
+if.then366: ; preds = %lor.end, %lor.end
+ unreachable
+
+if.end371: ; preds = %lor.end
+ %arrayidx56.2.i = getelementptr [4 x %struct.pix_pos]* %pix_a.i294, i32 0, i32 2 ; <%struct.pix_pos*> [#uses=1]
+ %arrayidx56.3.i = getelementptr [4 x %struct.pix_pos]* %pix_a.i294, i32 0, i32 3 ; <%struct.pix_pos*> [#uses=1]
+ br i1 undef, label %for.body1857, label %for.end4557
+
+for.body1857: ; preds = %if.end371
+ br i1 undef, label %if.then1867, label %for.cond1933
+
+if.then1867: ; preds = %for.body1857
+ unreachable
+
+for.cond1933: ; preds = %for.body1857
+ br i1 undef, label %for.body1940, label %if.then4493
+
+for.body1940: ; preds = %for.cond1933
+ %shl = shl i32 undef, 2 ; <i32> [#uses=1]
+ %shl1959 = shl i32 undef, 2 ; <i32> [#uses=4]
+ br i1 undef, label %if.then1992, label %if.else2003
+
+if.then1992: ; preds = %for.body1940
+ %tmp14.i302 = load i32* undef ; <i32> [#uses=4]
+ %add.i307452 = or i32 %shl1959, 1 ; <i32> [#uses=1]
+ %sub.i308 = add i32 %shl, -1 ; <i32> [#uses=4]
+ call arm_apcscc void undef(i32 %tmp14.i302, i32 %sub.i308, i32 %shl1959, i32 0, %struct.pix_pos* undef) nounwind
+ %tmp49.i309 = load void (i32, i32, i32, i32, %struct.pix_pos*)** @getNeighbour ; <void (i32, i32, i32, i32, %struct.pix_pos*)*> [#uses=1]
+ call arm_apcscc void %tmp49.i309(i32 %tmp14.i302, i32 %sub.i308, i32 %add.i307452, i32 0, %struct.pix_pos* null) nounwind
+ %tmp49.1.i = load void (i32, i32, i32, i32, %struct.pix_pos*)** @getNeighbour ; <void (i32, i32, i32, i32, %struct.pix_pos*)*> [#uses=1]
+ call arm_apcscc void %tmp49.1.i(i32 %tmp14.i302, i32 %sub.i308, i32 undef, i32 0, %struct.pix_pos* %arrayidx56.2.i) nounwind
+ call arm_apcscc void undef(i32 %tmp14.i302, i32 %sub.i308, i32 undef, i32 0, %struct.pix_pos* %arrayidx56.3.i) nounwind
+ unreachable
+
+if.else2003: ; preds = %for.body1940
+ switch i32 undef, label %if.then2015 [
+ i32 10, label %if.then4382
+ i32 14, label %if.then4382
+ ]
+
+if.then2015: ; preds = %if.else2003
+ br i1 undef, label %if.else2298, label %if.then2019
+
+if.then2019: ; preds = %if.then2015
+ br i1 undef, label %if.then2065, label %if.else2081
+
+if.then2065: ; preds = %if.then2019
+ br label %if.end2128
+
+if.else2081: ; preds = %if.then2019
+ br label %if.end2128
+
+if.end2128: ; preds = %if.else2081, %if.then2065
+ unreachable
+
+if.else2298: ; preds = %if.then2015
+ br i1 undef, label %land.lhs.true2813, label %cond.end2841
+
+land.lhs.true2813: ; preds = %if.else2298
+ br i1 undef, label %cond.end2841, label %cond.true2824
+
+cond.true2824: ; preds = %land.lhs.true2813
+ br label %cond.end2841
+
+cond.end2841: ; preds = %cond.true2824, %land.lhs.true2813, %if.else2298
+ br i1 undef, label %for.cond2882.preheader, label %for.cond2940.preheader
+
+for.cond2882.preheader: ; preds = %cond.end2841
+ %mul3693 = shl i32 undef, 1 ; <i32> [#uses=2]
+ br i1 undef, label %if.then3689, label %if.else3728
+
+for.cond2940.preheader: ; preds = %cond.end2841
+ br label %for.inc3040
+
+for.inc3040: ; preds = %for.inc3040, %for.cond2940.preheader
+ br label %for.inc3040
+
+if.then3689: ; preds = %for.cond2882.preheader
+ %add3695 = add nsw i32 %mul3693, %shl1959 ; <i32> [#uses=1]
+ %mul3697 = shl i32 %add3695, 2 ; <i32> [#uses=2]
+ %arrayidx3705 = getelementptr inbounds i16* undef, i32 1 ; <i16*> [#uses=1]
+ %tmp3706 = load i16* %arrayidx3705 ; <i16> [#uses=1]
+ %conv3707 = sext i16 %tmp3706 to i32 ; <i32> [#uses=1]
+ %add3708 = add nsw i32 %conv3707, %mul3697 ; <i32> [#uses=1]
+ %arrayidx3724 = getelementptr inbounds i16* null, i32 1 ; <i16*> [#uses=1]
+ %tmp3725 = load i16* %arrayidx3724 ; <i16> [#uses=1]
+ %conv3726 = sext i16 %tmp3725 to i32 ; <i32> [#uses=1]
+ %add3727 = add nsw i32 %conv3726, %mul3697 ; <i32> [#uses=1]
+ br label %if.end3770
+
+if.else3728: ; preds = %for.cond2882.preheader
+ %mul3733 = add i32 %shl1959, 1073741816 ; <i32> [#uses=1]
+ %add3735 = add nsw i32 %mul3733, %mul3693 ; <i32> [#uses=1]
+ %mul3737 = shl i32 %add3735, 2 ; <i32> [#uses=2]
+ %tmp3746 = load i16* undef ; <i16> [#uses=1]
+ %conv3747 = sext i16 %tmp3746 to i32 ; <i32> [#uses=1]
+ %add3748 = add nsw i32 %conv3747, %mul3737 ; <i32> [#uses=1]
+ %arrayidx3765 = getelementptr inbounds i16* null, i32 1 ; <i16*> [#uses=1]
+ %tmp3766 = load i16* %arrayidx3765 ; <i16> [#uses=1]
+ %conv3767 = sext i16 %tmp3766 to i32 ; <i32> [#uses=1]
+ %add3768 = add nsw i32 %conv3767, %mul3737 ; <i32> [#uses=1]
+ br label %if.end3770
+
+if.end3770: ; preds = %if.else3728, %if.then3689
+ %vec2_y.1 = phi i32 [ %add3727, %if.then3689 ], [ %add3768, %if.else3728 ] ; <i32> [#uses=0]
+ %vec1_y.2 = phi i32 [ %add3708, %if.then3689 ], [ %add3748, %if.else3728 ] ; <i32> [#uses=0]
+ unreachable
+
+if.then4382: ; preds = %if.else2003, %if.else2003
+ switch i32 undef, label %if.then4394 [
+ i32 10, label %if.else4400
+ i32 14, label %if.else4400
+ ]
+
+if.then4394: ; preds = %if.then4382
+ unreachable
+
+if.else4400: ; preds = %if.then4382, %if.then4382
+ br label %for.cond4451.preheader
+
+for.cond4451.preheader: ; preds = %for.cond4451.preheader, %if.else4400
+ br label %for.cond4451.preheader
+
+if.then4493: ; preds = %for.cond1933
+ unreachable
+
+for.end4557: ; preds = %if.end371
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
new file mode 100644
index 0000000..b4b6ed9
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -mtriple=thumbv7-eabi -mcpu=cortex-a8 -float-abi=hard | FileCheck %s
+
+; A fix for PR5204 will require this check to be changed.
+
+%"struct.__gnu_cxx::__normal_iterator<char*,std::basic_string<char, std::char_traits<char>, std::allocator<char> > >" = type { i8* }
+%"struct.__gnu_cxx::new_allocator<char>" = type <{ i8 }>
+%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >" = type { %"struct.__gnu_cxx::__normal_iterator<char*,std::basic_string<char, std::char_traits<char>, std::allocator<char> > >" }
+%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Rep" = type { %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Rep_base" }
+%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Rep_base" = type { i32, i32, i32 }
+
+
+define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) {
+; CHECK: _ZNKSs7compareERKSs:
+; CHECK: it ne
+; CHECK-NEXT: ldmfdne.w
+; CHECK-NEXT: itt eq
+; CHECK-NEXT: subeq.w
+; CHECK-NEXT: ldmfdeq.w
+entry:
+ %0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3]
+ %1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3]
+ %2 = icmp ult i32 %1, %0 ; <i1> [#uses=1]
+ %3 = select i1 %2, i32 %1, i32 %0 ; <i32> [#uses=1]
+ %4 = tail call arm_aapcs_vfpcc i8* @_ZNKSs7_M_dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i8*> [#uses=1]
+ %5 = tail call arm_aapcs_vfpcc i8* @_ZNKSs4dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i8*> [#uses=1]
+ %6 = tail call arm_aapcs_vfpcc i32 @memcmp(i8* %4, i8* %5, i32 %3) nounwind readonly ; <i32> [#uses=2]
+ %7 = icmp eq i32 %6, 0 ; <i1> [#uses=1]
+ br i1 %7, label %bb, label %bb1
+
+bb: ; preds = %entry
+ %8 = sub i32 %0, %1 ; <i32> [#uses=1]
+ ret i32 %8
+
+bb1: ; preds = %entry
+ ret i32 %6
+}
+
+declare arm_aapcs_vfpcc i32 @memcmp(i8* nocapture, i8* nocapture, i32) nounwind readonly
+
+declare arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this)
+
+declare arm_aapcs_vfpcc i8* @_ZNKSs7_M_dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this)
+
+declare arm_aapcs_vfpcc i8* @_ZNKSs4dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this)
diff --git a/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll b/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll
new file mode 100644
index 0000000..216f3e3
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8
+
+define arm_apcscc void @get_initial_mb16x16_cost() nounwind {
+entry:
+ br i1 undef, label %bb4, label %bb1
+
+bb1: ; preds = %entry
+ br label %bb7
+
+bb4: ; preds = %entry
+ br i1 undef, label %bb7.thread, label %bb5
+
+bb5: ; preds = %bb4
+ br label %bb7
+
+bb7.thread: ; preds = %bb4
+ br label %bb8
+
+bb7: ; preds = %bb5, %bb1
+ br i1 undef, label %bb8, label %bb10
+
+bb8: ; preds = %bb7, %bb7.thread
+ %0 = phi double [ 5.120000e+02, %bb7.thread ], [ undef, %bb7 ] ; <double> [#uses=1]
+ %1 = fdiv double %0, undef ; <double> [#uses=0]
+ unreachable
+
+bb10: ; preds = %bb7
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll b/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll
new file mode 100644
index 0000000..9f2e399
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll
@@ -0,0 +1,85 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10
+
+%struct.OP = type { %struct.OP*, %struct.OP*, %struct.OP* ()*, i32, i16, i16, i8, i8 }
+%struct.SV = type { i8*, i32, i32 }
+
+declare arm_apcscc void @Perl_mg_set(%struct.SV*) nounwind
+
+define arm_apcscc %struct.OP* @Perl_pp_complement() nounwind {
+entry:
+ %0 = load %struct.SV** null, align 4 ; <%struct.SV*> [#uses=2]
+ br i1 undef, label %bb21, label %bb5
+
+bb5: ; preds = %entry
+ br i1 undef, label %bb13, label %bb6
+
+bb6: ; preds = %bb5
+ br i1 undef, label %bb8, label %bb7
+
+bb7: ; preds = %bb6
+ %1 = getelementptr inbounds %struct.SV* %0, i32 0, i32 0 ; <i8**> [#uses=1]
+ %2 = load i8** %1, align 4 ; <i8*> [#uses=1]
+ %3 = getelementptr inbounds i8* %2, i32 12 ; <i8*> [#uses=1]
+ %4 = bitcast i8* %3 to i32* ; <i32*> [#uses=1]
+ %5 = load i32* %4, align 4 ; <i32> [#uses=1]
+ %storemerge5 = xor i32 %5, -1 ; <i32> [#uses=1]
+ call arm_apcscc void @Perl_sv_setiv(%struct.SV* undef, i32 %storemerge5) nounwind
+ %6 = getelementptr inbounds %struct.SV* undef, i32 0, i32 2 ; <i32*> [#uses=1]
+ %7 = load i32* %6, align 4 ; <i32> [#uses=1]
+ %8 = and i32 %7, 16384 ; <i32> [#uses=1]
+ %9 = icmp eq i32 %8, 0 ; <i1> [#uses=1]
+ br i1 %9, label %bb12, label %bb11
+
+bb8: ; preds = %bb6
+ unreachable
+
+bb11: ; preds = %bb7
+ call arm_apcscc void @Perl_mg_set(%struct.SV* undef) nounwind
+ br label %bb12
+
+bb12: ; preds = %bb11, %bb7
+ store %struct.SV* undef, %struct.SV** null, align 4
+ br label %bb44
+
+bb13: ; preds = %bb5
+ %10 = call arm_apcscc i32 @Perl_sv_2uv(%struct.SV* %0) nounwind ; <i32> [#uses=0]
+ br i1 undef, label %bb.i, label %bb1.i
+
+bb.i: ; preds = %bb13
+ call arm_apcscc void @Perl_sv_setiv(%struct.SV* undef, i32 undef) nounwind
+ br label %Perl_sv_setuv.exit
+
+bb1.i: ; preds = %bb13
+ br label %Perl_sv_setuv.exit
+
+Perl_sv_setuv.exit: ; preds = %bb1.i, %bb.i
+ %11 = getelementptr inbounds %struct.SV* undef, i32 0, i32 2 ; <i32*> [#uses=1]
+ %12 = load i32* %11, align 4 ; <i32> [#uses=1]
+ %13 = and i32 %12, 16384 ; <i32> [#uses=1]
+ %14 = icmp eq i32 %13, 0 ; <i1> [#uses=1]
+ br i1 %14, label %bb20, label %bb19
+
+bb19: ; preds = %Perl_sv_setuv.exit
+ call arm_apcscc void @Perl_mg_set(%struct.SV* undef) nounwind
+ br label %bb20
+
+bb20: ; preds = %bb19, %Perl_sv_setuv.exit
+ store %struct.SV* undef, %struct.SV** null, align 4
+ br label %bb44
+
+bb21: ; preds = %entry
+ br i1 undef, label %bb23, label %bb22
+
+bb22: ; preds = %bb21
+ unreachable
+
+bb23: ; preds = %bb21
+ unreachable
+
+bb44: ; preds = %bb20, %bb12
+ ret %struct.OP* undef
+}
+
+declare arm_apcscc void @Perl_sv_setiv(%struct.SV*, i32) nounwind
+
+declare arm_apcscc i32 @Perl_sv_2uv(%struct.SV*) nounwind
diff --git a/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll b/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll
new file mode 100644
index 0000000..8a67bb1
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10
+; rdar://7394794
+
+define arm_apcscc void @lshift_double(i64 %l1, i64 %h1, i64 %count, i32 %prec, i64* nocapture %lv, i64* nocapture %hv, i32 %arith) nounwind {
+entry:
+ %..i = select i1 false, i64 0, i64 0 ; <i64> [#uses=1]
+ br i1 undef, label %bb11.i, label %bb6.i
+
+bb6.i: ; preds = %entry
+ %0 = lshr i64 %h1, 0 ; <i64> [#uses=1]
+ store i64 %0, i64* %hv, align 4
+ %1 = lshr i64 %l1, 0 ; <i64> [#uses=1]
+ %2 = or i64 0, %1 ; <i64> [#uses=1]
+ store i64 %2, i64* %lv, align 4
+ br label %bb11.i
+
+bb11.i: ; preds = %bb6.i, %entry
+ store i64 %..i, i64* %lv, align 4
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll b/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll
new file mode 100644
index 0000000..79ad0a9
--- /dev/null
+++ b/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll
@@ -0,0 +1,128 @@
+; RUN: opt < %s -std-compile-opts | \
+; RUN: llc -mtriple=thumbv7-apple-darwin10 -mattr=+neon | FileCheck %s
+
+define arm_apcscc void @fred(i32 %three_by_three, i8* %in, double %dt1, i32 %x_size, i32 %y_size, i8* %bp) nounwind {
+entry:
+; -- The loop following the load should only use a single add-literation
+; instruction.
+; CHECK: ldr.64
+; CHECK: adds r{{[0-9]+}}, #1
+; CHECK-NOT: adds r{{[0-9]+}}, #1
+; CHECK: subsections_via_symbols
+
+
+ %three_by_three_addr = alloca i32 ; <i32*> [#uses=2]
+ %in_addr = alloca i8* ; <i8**> [#uses=2]
+ %dt_addr = alloca float ; <float*> [#uses=4]
+ %x_size_addr = alloca i32 ; <i32*> [#uses=2]
+ %y_size_addr = alloca i32 ; <i32*> [#uses=1]
+ %bp_addr = alloca i8* ; <i8**> [#uses=1]
+ %tmp_image = alloca i8* ; <i8**> [#uses=0]
+ %out = alloca i8* ; <i8**> [#uses=1]
+ %cp = alloca i8* ; <i8**> [#uses=0]
+ %dpt = alloca i8* ; <i8**> [#uses=4]
+ %dp = alloca i8* ; <i8**> [#uses=2]
+ %ip = alloca i8* ; <i8**> [#uses=0]
+ %centre = alloca i32 ; <i32*> [#uses=0]
+ %tmp = alloca i32 ; <i32*> [#uses=0]
+ %brightness = alloca i32 ; <i32*> [#uses=0]
+ %area = alloca i32 ; <i32*> [#uses=0]
+ %y = alloca i32 ; <i32*> [#uses=0]
+ %x = alloca i32 ; <i32*> [#uses=2]
+ %j = alloca i32 ; <i32*> [#uses=6]
+ %i = alloca i32 ; <i32*> [#uses=1]
+ %mask_size = alloca i32 ; <i32*> [#uses=5]
+ %increment = alloca i32 ; <i32*> [#uses=1]
+ %n_max = alloca i32 ; <i32*> [#uses=4]
+ %temp = alloca float ; <float*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %three_by_three, i32* %three_by_three_addr
+ store i8* %in, i8** %in_addr
+ %dt = fptrunc double %dt1 to float ; <float> [#uses=1]
+ store float %dt, float* %dt_addr
+ store i32 %x_size, i32* %x_size_addr
+ store i32 %y_size, i32* %y_size_addr
+ store i8* %bp, i8** %bp_addr
+ %0 = load i8** %in_addr, align 4 ; <i8*> [#uses=1]
+ store i8* %0, i8** %out, align 4
+ %1 = call arm_apcscc i32 (...)* @foo() nounwind ; <i32> [#uses=1]
+ store i32 %1, i32* %i, align 4
+ %2 = load i32* %three_by_three_addr, align 4 ; <i32> [#uses=1]
+ %3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
+ br i1 %3, label %bb, label %bb2
+
+bb: ; preds = %entry
+ %4 = load float* %dt_addr, align 4 ; <float> [#uses=1]
+ %5 = fpext float %4 to double ; <double> [#uses=1]
+ %6 = fmul double %5, 1.500000e+00 ; <double> [#uses=1]
+ %7 = fptosi double %6 to i32 ; <i32> [#uses=1]
+ %8 = add nsw i32 %7, 1 ; <i32> [#uses=1]
+ store i32 %8, i32* %mask_size, align 4
+ br label %bb3
+
+bb2: ; preds = %entry
+ store i32 1, i32* %mask_size, align 4
+ br label %bb3
+
+bb3: ; preds = %bb2, %bb
+ %9 = load i32* %mask_size, align 4 ; <i32> [#uses=1]
+ %10 = mul i32 %9, 2 ; <i32> [#uses=1]
+ %11 = add nsw i32 %10, 1 ; <i32> [#uses=1]
+ store i32 %11, i32* %n_max, align 4
+ %12 = load i32* %x_size_addr, align 4 ; <i32> [#uses=1]
+ %13 = load i32* %n_max, align 4 ; <i32> [#uses=1]
+ %14 = sub i32 %12, %13 ; <i32> [#uses=1]
+ store i32 %14, i32* %increment, align 4
+ %15 = load i32* %n_max, align 4 ; <i32> [#uses=1]
+ %16 = load i32* %n_max, align 4 ; <i32> [#uses=1]
+ %17 = mul i32 %15, %16 ; <i32> [#uses=1]
+ %18 = call arm_apcscc noalias i8* @malloc(i32 %17) nounwind ; <i8*> [#uses=1]
+ store i8* %18, i8** %dp, align 4
+ %19 = load i8** %dp, align 4 ; <i8*> [#uses=1]
+ store i8* %19, i8** %dpt, align 4
+ %20 = load float* %dt_addr, align 4 ; <float> [#uses=1]
+ %21 = load float* %dt_addr, align 4 ; <float> [#uses=1]
+ %22 = fmul float %20, %21 ; <float> [#uses=1]
+ %23 = fsub float -0.000000e+00, %22 ; <float> [#uses=1]
+ store float %23, float* %temp, align 4
+ %24 = load i32* %mask_size, align 4 ; <i32> [#uses=1]
+ %25 = sub i32 0, %24 ; <i32> [#uses=1]
+ store i32 %25, i32* %j, align 4
+ br label %bb5
+
+bb4: ; preds = %bb5
+ %26 = load i32* %j, align 4 ; <i32> [#uses=1]
+ %27 = load i32* %j, align 4 ; <i32> [#uses=1]
+ %28 = mul i32 %26, %27 ; <i32> [#uses=1]
+ %29 = sitofp i32 %28 to double ; <double> [#uses=1]
+ %30 = fmul double %29, 1.234000e+00 ; <double> [#uses=1]
+ %31 = fptosi double %30 to i32 ; <i32> [#uses=1]
+ store i32 %31, i32* %x, align 4
+ %32 = load i32* %x, align 4 ; <i32> [#uses=1]
+ %33 = trunc i32 %32 to i8 ; <i8> [#uses=1]
+ %34 = load i8** %dpt, align 4 ; <i8*> [#uses=1]
+ store i8 %33, i8* %34, align 1
+ %35 = load i8** %dpt, align 4 ; <i8*> [#uses=1]
+ %36 = getelementptr inbounds i8* %35, i64 1 ; <i8*> [#uses=1]
+ store i8* %36, i8** %dpt, align 4
+ %37 = load i32* %j, align 4 ; <i32> [#uses=1]
+ %38 = add nsw i32 %37, 1 ; <i32> [#uses=1]
+ store i32 %38, i32* %j, align 4
+ br label %bb5
+
+bb5: ; preds = %bb4, %bb3
+ %39 = load i32* %j, align 4 ; <i32> [#uses=1]
+ %40 = load i32* %mask_size, align 4 ; <i32> [#uses=1]
+ %41 = icmp sle i32 %39, %40 ; <i1> [#uses=1]
+ br i1 %41, label %bb4, label %bb6
+
+bb6: ; preds = %bb5
+ br label %return
+
+return: ; preds = %bb6
+ ret void
+}
+
+declare arm_apcscc i32 @foo(...)
+
+declare arm_apcscc noalias i8* @malloc(i32) nounwind
diff --git a/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll b/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll
new file mode 100644
index 0000000..07a3527
--- /dev/null
+++ b/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll
@@ -0,0 +1,89 @@
+; RUN: llc -relocation-model=pic < %s | grep {:$} | sort | uniq -d | count 0
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
+target triple = "thumbv7-apple-darwin10"
+
+; This function produces a duplicate LPC label unless special care is taken when duplicating a t2LDRpci_pic instruction.
+
+%struct.PlatformMutex = type { i32, [40 x i8] }
+%struct.SpinLock = type { %struct.PlatformMutex }
+%"struct.WTF::TCMalloc_ThreadCache" = type { i32, %struct._opaque_pthread_t*, i8, [68 x %"struct.WTF::TCMalloc_ThreadCache_FreeList"], i32, i32, %"struct.WTF::TCMalloc_ThreadCache"*, %"struct.WTF::TCMalloc_ThreadCache"* }
+%"struct.WTF::TCMalloc_ThreadCache_FreeList" = type { i8*, i16, i16 }
+%struct.__darwin_pthread_handler_rec = type { void (i8*)*, i8*, %struct.__darwin_pthread_handler_rec* }
+%struct._opaque_pthread_t = type { i32, %struct.__darwin_pthread_handler_rec*, [596 x i8] }
+
+@_ZN3WTFL8heap_keyE = internal global i32 0 ; <i32*> [#uses=1]
+@_ZN3WTFL10tsd_initedE.b = internal global i1 false ; <i1*> [#uses=2]
+@_ZN3WTFL13pageheap_lockE = internal global %struct.SpinLock { %struct.PlatformMutex { i32 850045863, [40 x i8] zeroinitializer } } ; <%struct.SpinLock*> [#uses=1]
+@_ZN3WTFL12thread_heapsE = internal global %"struct.WTF::TCMalloc_ThreadCache"* null ; <%"struct.WTF::TCMalloc_ThreadCache"**> [#uses=1]
[email protected] = appending global [1 x i8*] [i8* bitcast (%"struct.WTF::TCMalloc_ThreadCache"* ()* @_ZN3WTF20TCMalloc_ThreadCache22CreateCacheIfNecessaryEv to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define arm_apcscc %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache22CreateCacheIfNecessaryEv() nounwind {
+entry:
+ %0 = tail call arm_apcscc i32 @pthread_mutex_lock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind
+ %.b24 = load i1* @_ZN3WTFL10tsd_initedE.b, align 4 ; <i1> [#uses=1]
+ br i1 %.b24, label %bb5, label %bb6
+
+bb5: ; preds = %entry
+ %1 = tail call arm_apcscc %struct._opaque_pthread_t* @pthread_self() nounwind
+ br label %bb6
+
+bb6: ; preds = %bb5, %entry
+ %me.0 = phi %struct._opaque_pthread_t* [ %1, %bb5 ], [ null, %entry ] ; <%struct._opaque_pthread_t*> [#uses=2]
+ br label %bb11
+
+bb7: ; preds = %bb11
+ %2 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache"* %h.0, i32 0, i32 1
+ %3 = load %struct._opaque_pthread_t** %2, align 4
+ %4 = tail call arm_apcscc i32 @pthread_equal(%struct._opaque_pthread_t* %3, %struct._opaque_pthread_t* %me.0) nounwind
+ %5 = icmp eq i32 %4, 0
+ br i1 %5, label %bb10, label %bb14
+
+bb10: ; preds = %bb7
+ %6 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache"* %h.0, i32 0, i32 6
+ br label %bb11
+
+bb11: ; preds = %bb10, %bb6
+ %h.0.in = phi %"struct.WTF::TCMalloc_ThreadCache"** [ @_ZN3WTFL12thread_heapsE, %bb6 ], [ %6, %bb10 ] ; <%"struct.WTF::TCMalloc_ThreadCache"**> [#uses=1]
+ %h.0 = load %"struct.WTF::TCMalloc_ThreadCache"** %h.0.in, align 4 ; <%"struct.WTF::TCMalloc_ThreadCache"*> [#uses=4]
+ %7 = icmp eq %"struct.WTF::TCMalloc_ThreadCache"* %h.0, null
+ br i1 %7, label %bb13, label %bb7
+
+bb13: ; preds = %bb11
+ %8 = tail call arm_apcscc %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache7NewHeapEP17_opaque_pthread_t(%struct._opaque_pthread_t* %me.0) nounwind
+ br label %bb14
+
+bb14: ; preds = %bb13, %bb7
+ %heap.1 = phi %"struct.WTF::TCMalloc_ThreadCache"* [ %8, %bb13 ], [ %h.0, %bb7 ] ; <%"struct.WTF::TCMalloc_ThreadCache"*> [#uses=4]
+ %9 = tail call arm_apcscc i32 @pthread_mutex_unlock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind
+ %10 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache"* %heap.1, i32 0, i32 2
+ %11 = load i8* %10, align 4
+ %toBool15not = icmp eq i8 %11, 0 ; <i1> [#uses=1]
+ br i1 %toBool15not, label %bb19, label %bb22
+
+bb19: ; preds = %bb14
+ %.b = load i1* @_ZN3WTFL10tsd_initedE.b, align 4 ; <i1> [#uses=1]
+ br i1 %.b, label %bb21, label %bb22
+
+bb21: ; preds = %bb19
+ store i8 1, i8* %10, align 4
+ %12 = load i32* @_ZN3WTFL8heap_keyE, align 4
+ %13 = bitcast %"struct.WTF::TCMalloc_ThreadCache"* %heap.1 to i8*
+ %14 = tail call arm_apcscc i32 @pthread_setspecific(i32 %12, i8* %13) nounwind
+ ret %"struct.WTF::TCMalloc_ThreadCache"* %heap.1
+
+bb22: ; preds = %bb19, %bb14
+ ret %"struct.WTF::TCMalloc_ThreadCache"* %heap.1
+}
+
+declare arm_apcscc i32 @pthread_mutex_lock(%struct.PlatformMutex*)
+
+declare arm_apcscc i32 @pthread_mutex_unlock(%struct.PlatformMutex*)
+
+declare hidden arm_apcscc %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache7NewHeapEP17_opaque_pthread_t(%struct._opaque_pthread_t*) nounwind
+
+declare arm_apcscc i32 @pthread_setspecific(i32, i8*)
+
+declare arm_apcscc %struct._opaque_pthread_t* @pthread_self()
+
+declare arm_apcscc i32 @pthread_equal(%struct._opaque_pthread_t*, %struct._opaque_pthread_t*)
+
diff --git a/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll b/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll
new file mode 100644
index 0000000..41682c1
--- /dev/null
+++ b/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll
@@ -0,0 +1,53 @@
+; RUN: llc -O3 -relocation-model=pic -mcpu=cortex-a8 -mattr=+thumb2 < %s
+;
+; This test creates a predicated t2ADDri instruction that is then turned into a t2MOVgpr2gpr instr.
+; Test that that the predicate operands are removed properly.
+;
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
+target triple = "thumbv7-apple-darwin10"
+
+declare arm_apcscc void @etoe53(i16* nocapture, i16* nocapture) nounwind
+
+define arm_apcscc void @earith(double* nocapture %value, i32 %icode, double* nocapture %r1, double* nocapture %r2) nounwind {
+entry:
+ %v = alloca [6 x i16], align 4 ; <[6 x i16]*> [#uses=1]
+ br i1 undef, label %bb2.i, label %bb5
+
+bb2.i: ; preds = %entry
+ %0 = bitcast double* %value to i16* ; <i16*> [#uses=1]
+ call arm_apcscc void @etoe53(i16* null, i16* %0) nounwind
+ ret void
+
+bb5: ; preds = %entry
+ switch i32 %icode, label %bb10 [
+ i32 57, label %bb14
+ i32 58, label %bb18
+ i32 67, label %bb22
+ i32 76, label %bb26
+ i32 77, label %bb35
+ ]
+
+bb10: ; preds = %bb5
+ br label %bb46
+
+bb14: ; preds = %bb5
+ unreachable
+
+bb18: ; preds = %bb5
+ unreachable
+
+bb22: ; preds = %bb5
+ unreachable
+
+bb26: ; preds = %bb5
+ br label %bb46
+
+bb35: ; preds = %bb5
+ unreachable
+
+bb46: ; preds = %bb26, %bb10
+ %1 = bitcast double* %value to i16* ; <i16*> [#uses=1]
+ %v47 = getelementptr inbounds [6 x i16]* %v, i32 0, i32 0 ; <i16*> [#uses=1]
+ call arm_apcscc void @etoe53(i16* %v47, i16* %1) nounwind
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/carry.ll b/test/CodeGen/Thumb2/carry.ll
new file mode 100644
index 0000000..de6f6e2
--- /dev/null
+++ b/test/CodeGen/Thumb2/carry.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i64 @f1(i64 %a, i64 %b) {
+entry:
+; CHECK: f1:
+; CHECK: subs r0, r0, r2
+; CHECK: sbcs r1, r3
+ %tmp = sub i64 %a, %b
+ ret i64 %tmp
+}
+
+define i64 @f2(i64 %a, i64 %b) {
+entry:
+; CHECK: f2:
+; CHECK: adds r0, r0, r0
+; CHECK: adcs r1, r1
+; CHECK: subs r0, r0, r2
+; CHECK: sbcs r1, r3
+ %tmp1 = shl i64 %a, 1
+ %tmp2 = sub i64 %tmp1, %b
+ ret i64 %tmp2
+}
diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll
new file mode 100644
index 0000000..572f1e8
--- /dev/null
+++ b/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll
@@ -0,0 +1,52 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8
+
+%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+%struct.__sFILEX = type opaque
+%struct.__sbuf = type { i8*, i32 }
+
+declare arm_apcscc i32 @fgetc(%struct.FILE* nocapture) nounwind
+
+define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
+entry:
+ br i1 undef, label %bb, label %bb1
+
+bb: ; preds = %entry
+ unreachable
+
+bb1: ; preds = %entry
+ br i1 undef, label %bb.i1, label %bb1.i2
+
+bb.i1: ; preds = %bb1
+ unreachable
+
+bb1.i2: ; preds = %bb1
+ %0 = call arm_apcscc i32 @fgetc(%struct.FILE* undef) nounwind ; <i32> [#uses=0]
+ br i1 undef, label %bb2.i3, label %bb3.i4
+
+bb2.i3: ; preds = %bb1.i2
+ br i1 undef, label %bb4.i, label %bb3.i4
+
+bb3.i4: ; preds = %bb2.i3, %bb1.i2
+ unreachable
+
+bb4.i: ; preds = %bb2.i3
+ br i1 undef, label %bb5.i, label %get_image.exit
+
+bb5.i: ; preds = %bb4.i
+ unreachable
+
+get_image.exit: ; preds = %bb4.i
+ br i1 undef, label %bb28, label %bb27
+
+bb27: ; preds = %get_image.exit
+ br label %bb.i
+
+bb.i: ; preds = %bb.i, %bb27
+ %1 = fptrunc double undef to float ; <float> [#uses=1]
+ %2 = fptoui float %1 to i8 ; <i8> [#uses=1]
+ store i8 %2, i8* undef, align 1
+ br label %bb.i
+
+bb28: ; preds = %get_image.exit
+ unreachable
+}
diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
new file mode 100644
index 0000000..8f6449e
--- /dev/null
+++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
@@ -0,0 +1,67 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 7
+
+define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind {
+entry:
+ br label %bb5
+
+bb5: ; preds = %bb5, %entry
+ br i1 undef, label %bb5, label %bb.nph
+
+bb.nph: ; preds = %bb5
+ br label %bb7
+
+bb7: ; preds = %bb9, %bb.nph
+ %s1.02 = phi float [ undef, %bb.nph ], [ %35, %bb9 ] ; <float> [#uses=3]
+ %tmp79 = add i32 undef, undef ; <i32> [#uses=1]
+ %tmp53 = sub i32 undef, undef ; <i32> [#uses=1]
+ %0 = fadd float 0.000000e+00, 1.000000e+00 ; <float> [#uses=2]
+ %1 = fmul float 0.000000e+00, 0.000000e+00 ; <float> [#uses=2]
+ br label %bb8
+
+bb8: ; preds = %bb8, %bb7
+ %tmp54 = add i32 0, %tmp53 ; <i32> [#uses=0]
+ %fi.1 = getelementptr float* %fz, i32 undef ; <float*> [#uses=2]
+ %tmp80 = add i32 0, %tmp79 ; <i32> [#uses=1]
+ %scevgep81 = getelementptr float* %fz, i32 %tmp80 ; <float*> [#uses=1]
+ %2 = load float* undef, align 4 ; <float> [#uses=1]
+ %3 = fmul float %2, %1 ; <float> [#uses=1]
+ %4 = load float* null, align 4 ; <float> [#uses=2]
+ %5 = fmul float %4, %0 ; <float> [#uses=1]
+ %6 = fsub float %3, %5 ; <float> [#uses=1]
+ %7 = fmul float %4, %1 ; <float> [#uses=1]
+ %8 = fadd float undef, %7 ; <float> [#uses=2]
+ %9 = load float* %fi.1, align 4 ; <float> [#uses=2]
+ %10 = fsub float %9, %8 ; <float> [#uses=1]
+ %11 = fadd float %9, %8 ; <float> [#uses=1]
+ %12 = fsub float 0.000000e+00, %6 ; <float> [#uses=1]
+ %13 = fsub float 0.000000e+00, undef ; <float> [#uses=2]
+ %14 = fmul float undef, %0 ; <float> [#uses=1]
+ %15 = fadd float %14, undef ; <float> [#uses=2]
+ %16 = load float* %scevgep81, align 4 ; <float> [#uses=2]
+ %17 = fsub float %16, %15 ; <float> [#uses=1]
+ %18 = fadd float %16, %15 ; <float> [#uses=2]
+ %19 = load float* undef, align 4 ; <float> [#uses=2]
+ %20 = fsub float %19, %13 ; <float> [#uses=2]
+ %21 = fadd float %19, %13 ; <float> [#uses=1]
+ %22 = fmul float %s1.02, %18 ; <float> [#uses=1]
+ %23 = fmul float 0.000000e+00, %20 ; <float> [#uses=1]
+ %24 = fsub float %22, %23 ; <float> [#uses=1]
+ %25 = fmul float 0.000000e+00, %18 ; <float> [#uses=1]
+ %26 = fmul float %s1.02, %20 ; <float> [#uses=1]
+ %27 = fadd float %25, %26 ; <float> [#uses=1]
+ %28 = fadd float %11, %27 ; <float> [#uses=1]
+ store float %28, float* %fi.1, align 4
+ %29 = fadd float %12, %24 ; <float> [#uses=1]
+ store float %29, float* null, align 4
+ %30 = fmul float 0.000000e+00, %21 ; <float> [#uses=1]
+ %31 = fmul float %s1.02, %17 ; <float> [#uses=1]
+ %32 = fsub float %30, %31 ; <float> [#uses=1]
+ %33 = fsub float %10, %32 ; <float> [#uses=1]
+ store float %33, float* undef, align 4
+ %34 = icmp slt i32 undef, undef ; <i1> [#uses=1]
+ br i1 %34, label %bb8, label %bb9
+
+bb9: ; preds = %bb8
+ %35 = fadd float 0.000000e+00, undef ; <float> [#uses=1]
+ br label %bb7
+}
diff --git a/test/CodeGen/Thumb2/dg.exp b/test/CodeGen/Thumb2/dg.exp
new file mode 100644
index 0000000..3ff359a
--- /dev/null
+++ b/test/CodeGen/Thumb2/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target ARM] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/Thumb2/frameless.ll b/test/CodeGen/Thumb2/frameless.ll
new file mode 100644
index 0000000..c3c8cf1
--- /dev/null
+++ b/test/CodeGen/Thumb2/frameless.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-fp-elim | not grep mov
+; RUN: llc < %s -mtriple=thumbv7-linux -disable-fp-elim | not grep mov
+
+define arm_apcscc void @t() nounwind readnone {
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/frameless2.ll b/test/CodeGen/Thumb2/frameless2.ll
new file mode 100644
index 0000000..7cc7b19
--- /dev/null
+++ b/test/CodeGen/Thumb2/frameless2.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-fp-elim | not grep r7
+
+%struct.noise3 = type { [3 x [17 x i32]] }
+%struct.noiseguard = type { i32, i32, i32 }
+
+define arm_apcscc void @vorbis_encode_noisebias_setup(i8* nocapture %vi.0.7.val, double %s, i32 %block, i32* nocapture %suppress, %struct.noise3* nocapture %in, %struct.noiseguard* nocapture %guard, double %userbias) nounwind {
+entry:
+ %0 = getelementptr %struct.noiseguard* %guard, i32 %block, i32 2; <i32*> [#uses=1]
+ %1 = load i32* %0, align 4 ; <i32> [#uses=1]
+ store i32 %1, i32* undef, align 4
+ unreachable
+}
diff --git a/test/CodeGen/Thumb2/ifcvt-neon.ll b/test/CodeGen/Thumb2/ifcvt-neon.ll
new file mode 100644
index 0000000..c667909
--- /dev/null
+++ b/test/CodeGen/Thumb2/ifcvt-neon.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s
+; rdar://7368193
+
+@a = common global float 0.000000e+00 ; <float*> [#uses=2]
+@b = common global float 0.000000e+00 ; <float*> [#uses=1]
+
+define arm_apcscc float @t(i32 %c) nounwind {
+entry:
+ %0 = icmp sgt i32 %c, 1 ; <i1> [#uses=1]
+ %1 = load float* @a, align 4 ; <float> [#uses=2]
+ %2 = load float* @b, align 4 ; <float> [#uses=2]
+ br i1 %0, label %bb, label %bb1
+
+bb: ; preds = %entry
+; CHECK: ite lt
+; CHECK: vsublt.f32
+; CHECK-NEXT: vaddge.f32
+ %3 = fadd float %1, %2 ; <float> [#uses=1]
+ br label %bb2
+
+bb1: ; preds = %entry
+ %4 = fsub float %1, %2 ; <float> [#uses=1]
+ br label %bb2
+
+bb2: ; preds = %bb1, %bb
+ %storemerge = phi float [ %4, %bb1 ], [ %3, %bb ] ; <float> [#uses=2]
+ store float %storemerge, float* @a
+ ret float %storemerge
+}
diff --git a/test/CodeGen/Thumb2/large-stack.ll b/test/CodeGen/Thumb2/large-stack.ll
new file mode 100644
index 0000000..fe0e506
--- /dev/null
+++ b/test/CodeGen/Thumb2/large-stack.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
+; RUN: llc < %s -march=thumb -mattr=+thumb2 -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=LINUX
+
+define void @test1() {
+; DARWIN: test1:
+; DARWIN: sub sp, #256
+; LINUX: test1:
+; LINUX: sub sp, #256
+ %tmp = alloca [ 64 x i32 ] , align 4
+ ret void
+}
+
+define void @test2() {
+; DARWIN: test2:
+; DARWIN: sub.w sp, sp, #4160
+; DARWIN: sub sp, #8
+; LINUX: test2:
+; LINUX: sub.w sp, sp, #4160
+; LINUX: sub sp, #8
+ %tmp = alloca [ 4168 x i8 ] , align 4
+ ret void
+}
+
+define i32 @test3() {
+; DARWIN: test3:
+; DARWIN: push {r4, r7, lr}
+; DARWIN: sub.w sp, sp, #805306368
+; DARWIN: sub sp, #20
+; LINUX: test3:
+; LINUX: stmfd sp!, {r4, r7, r11, lr}
+; LINUX: sub.w sp, sp, #805306368
+; LINUX: sub sp, #16
+ %retval = alloca i32, align 4
+ %tmp = alloca i32, align 4
+ %a = alloca [805306369 x i8], align 16
+ store i32 0, i32* %tmp
+ %tmp1 = load i32* %tmp
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/Thumb2/ldr-str-imm12.ll b/test/CodeGen/Thumb2/ldr-str-imm12.ll
new file mode 100644
index 0000000..47d85b1
--- /dev/null
+++ b/test/CodeGen/Thumb2/ldr-str-imm12.ll
@@ -0,0 +1,79 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s
+; rdar://7352504
+; Make sure we use "str r9, [sp, #+28]" instead of "sub.w r4, r7, #256" followed by "str r9, [r4, #-32]".
+
+%0 = type { i16, i8, i8 }
+%1 = type { [2 x i32], [2 x i32] }
+%2 = type { %union.rec* }
+%struct.FILE_POS = type { i8, i8, i16, i32 }
+%struct.GAP = type { i8, i8, i16 }
+%struct.LIST = type { %union.rec*, %union.rec* }
+%struct.STYLE = type { %union.anon, %union.anon, i16, i16, i32 }
+%struct.head_type = type { [2 x %struct.LIST], %union.FIRST_UNION, %union.SECOND_UNION, %union.THIRD_UNION, %union.FOURTH_UNION, %union.rec*, %2, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, i32 }
+%union.FIRST_UNION = type { %struct.FILE_POS }
+%union.FOURTH_UNION = type { %struct.STYLE }
+%union.SECOND_UNION = type { %0 }
+%union.THIRD_UNION = type { %1 }
+%union.anon = type { %struct.GAP }
+%union.rec = type { %struct.head_type }
+
+@zz_hold = external global %union.rec* ; <%union.rec**> [#uses=2]
+@zz_res = external global %union.rec* ; <%union.rec**> [#uses=1]
+
+define arm_apcscc %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind {
+entry:
+; CHECK: ldr.w r9, [r7, #+28]
+ %xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0]
+ %ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0]
+ br i1 false, label %bb, label %bb20
+
+bb: ; preds = %entry
+ unreachable
+
+bb20: ; preds = %entry
+ switch i32 undef, label %bb1287 [
+ i32 11, label %bb119
+ i32 12, label %bb119
+ i32 21, label %bb420
+ i32 23, label %bb420
+ i32 45, label %bb438
+ i32 46, label %bb438
+ i32 55, label %bb533
+ i32 56, label %bb569
+ i32 64, label %bb745
+ i32 78, label %bb1098
+ ]
+
+bb119: ; preds = %bb20, %bb20
+ unreachable
+
+bb420: ; preds = %bb20, %bb20
+; CHECK: bb420
+; CHECK: str r{{[0-7]}}, [sp]
+; CHECK: str r{{[0-7]}}, [sp, #+4]
+; CHECK: str r{{[0-7]}}, [sp, #+8]
+; CHECK: str r{{[0-7]}}, [sp, #+24]
+ store %union.rec* null, %union.rec** @zz_hold, align 4
+ store %union.rec* null, %union.rec** @zz_res, align 4
+ store %union.rec* %x, %union.rec** @zz_hold, align 4
+ %0 = call arm_apcscc %union.rec* @Manifest(%union.rec* undef, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind ; <%union.rec*> [#uses=0]
+ unreachable
+
+bb438: ; preds = %bb20, %bb20
+ unreachable
+
+bb533: ; preds = %bb20
+ ret %union.rec* %x
+
+bb569: ; preds = %bb20
+ unreachable
+
+bb745: ; preds = %bb20
+ unreachable
+
+bb1098: ; preds = %bb20
+ unreachable
+
+bb1287: ; preds = %bb20
+ unreachable
+}
diff --git a/test/CodeGen/Thumb2/load-global.ll b/test/CodeGen/Thumb2/load-global.ll
new file mode 100644
index 0000000..9286670
--- /dev/null
+++ b/test/CodeGen/Thumb2/load-global.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=STATIC
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DYNAMIC
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=PIC
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LINUX
+
+@G = external global i32
+
+define i32 @test1() {
+; STATIC: _test1:
+; STATIC: .long _G
+
+; DYNAMIC: _test1:
+; DYNAMIC: .long L_G$non_lazy_ptr
+
+; PIC: _test1
+; PIC: add r0, pc
+; PIC: .long L_G$non_lazy_ptr-(LPC1_0+4)
+
+; LINUX: test1
+; LINUX: .long G(GOT)
+ %tmp = load i32* @G
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/lsr-deficiency.ll b/test/CodeGen/Thumb2/lsr-deficiency.ll
new file mode 100644
index 0000000..7b1b57a
--- /dev/null
+++ b/test/CodeGen/Thumb2/lsr-deficiency.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic | FileCheck %s
+; rdar://7387640
+
+; FIXME: We still need to rewrite array reference iv of stride -4 with loop
+; count iv of stride -1.
+
+@G = external global i32 ; <i32*> [#uses=2]
+@array = external global i32* ; <i32**> [#uses=1]
+
+define arm_apcscc void @t() nounwind optsize {
+; CHECK: t:
+; CHECK: mov.w r2, #4000
+; CHECK: movw r3, #1001
+entry:
+ %.pre = load i32* @G, align 4 ; <i32> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %entry
+; CHECK: LBB1_1:
+; CHECK: subs r3, #1
+; CHECK: cmp r3, #0
+; CHECK: sub.w r2, r2, #4
+ %0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; <i32> [#uses=1]
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
+ %tmp5 = sub i32 1000, %indvar ; <i32> [#uses=1]
+ %1 = load i32** @array, align 4 ; <i32*> [#uses=1]
+ %scevgep = getelementptr i32* %1, i32 %tmp5 ; <i32*> [#uses=1]
+ %2 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
+ %3 = add nsw i32 %2, %0 ; <i32> [#uses=2]
+ store i32 %3, i32* @G, align 4
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, 1001 ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
+
+return: ; preds = %bb
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll
new file mode 100644
index 0000000..9ab19e9
--- /dev/null
+++ b/test/CodeGen/Thumb2/machine-licm.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-fp-elim | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC
+; rdar://7353541
+; rdar://7354376
+
+; The generated code is no where near ideal. It's not recognizing the two
+; constantpool entries being loaded can be merged into one.
+
+@GV = external global i32 ; <i32*> [#uses=2]
+
+define arm_apcscc void @t(i32* nocapture %vals, i32 %c) nounwind {
+entry:
+; CHECK: t:
+; CHECK: cbz
+ %0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
+ br i1 %0, label %return, label %bb.nph
+
+bb.nph: ; preds = %entry
+; CHECK: BB#1
+; CHECK: ldr.n r2, LCPI1_0
+; CHECK: ldr r3, [r2]
+; CHECK: ldr r3, [r3]
+; CHECK: ldr r2, [r2]
+; CHECK: LBB1_2
+; CHECK: LCPI1_0:
+; CHECK-NOT: LCPI1_1:
+; CHECK: .section
+
+; PIC: BB#1
+; PIC: ldr.n r2, LCPI1_0
+; PIC: add r2, pc
+; PIC: ldr r3, [r2]
+; PIC: ldr r3, [r3]
+; PIC: ldr r2, [r2]
+; PIC: LBB1_2
+; PIC: LCPI1_0:
+; PIC-NOT: LCPI1_1:
+; PIC: .section
+ %.pre = load i32* @GV, align 4 ; <i32> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %bb.nph
+ %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; <i32> [#uses=1]
+ %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; <i32> [#uses=2]
+ %scevgep = getelementptr i32* %vals, i32 %i.03 ; <i32*> [#uses=1]
+ %2 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
+ %3 = add nsw i32 %1, %2 ; <i32> [#uses=2]
+ store i32 %3, i32* @GV, align 4
+ %4 = add i32 %i.03, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %4, %c ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/mul_const.ll b/test/CodeGen/Thumb2/mul_const.ll
new file mode 100644
index 0000000..9a2ec93
--- /dev/null
+++ b/test/CodeGen/Thumb2/mul_const.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+; rdar://7069502
+
+define i32 @t1(i32 %v) nounwind readnone {
+entry:
+; CHECK: t1:
+; CHECK: add.w r0, r0, r0, lsl #3
+ %0 = mul i32 %v, 9
+ ret i32 %0
+}
+
+define i32 @t2(i32 %v) nounwind readnone {
+entry:
+; CHECK: t2:
+; CHECK: rsb r0, r0, r0, lsl #3
+ %0 = mul i32 %v, 7
+ ret i32 %0
+}
diff --git a/test/CodeGen/Thumb2/pic-load.ll b/test/CodeGen/Thumb2/pic-load.ll
new file mode 100644
index 0000000..1f8aea9
--- /dev/null
+++ b/test/CodeGen/Thumb2/pic-load.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -relocation-model=pic | FileCheck %s
+
+ %struct.anon = type { void ()* }
+ %struct.one_atexit_routine = type { %struct.anon, i32, i8* }
+@__dso_handle = external global { } ; <{ }*> [#uses=1]
[email protected] = appending global [1 x i8*] [i8* bitcast (i32 (void ()*)* @atexit to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define hidden arm_apcscc i32 @atexit(void ()* %func) nounwind {
+entry:
+; CHECK: atexit:
+; CHECK: add r0, pc
+ %r = alloca %struct.one_atexit_routine, align 4 ; <%struct.one_atexit_routine*> [#uses=3]
+ %0 = getelementptr %struct.one_atexit_routine* %r, i32 0, i32 0, i32 0 ; <void ()**> [#uses=1]
+ store void ()* %func, void ()** %0, align 4
+ %1 = getelementptr %struct.one_atexit_routine* %r, i32 0, i32 1 ; <i32*> [#uses=1]
+ store i32 0, i32* %1, align 4
+ %2 = call arm_apcscc i32 @atexit_common(%struct.one_atexit_routine* %r, i8* bitcast ({ }* @__dso_handle to i8*)) nounwind ; <i32> [#uses=1]
+ ret i32 %2
+}
+
+declare arm_apcscc i32 @atexit_common(%struct.one_atexit_routine*, i8*) nounwind
diff --git a/test/CodeGen/Thumb2/thumb2-adc.ll b/test/CodeGen/Thumb2/thumb2-adc.ll
new file mode 100644
index 0000000..702df91
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-adc.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+; 734439407618 = 0x000000ab00000002
+define i64 @f1(i64 %a) {
+; CHECK: f1:
+; CHECK: adds r0, #2
+ %tmp = add i64 %a, 734439407618
+ ret i64 %tmp
+}
+
+; 5066626890203138 = 0x0012001200000002
+define i64 @f2(i64 %a) {
+; CHECK: f2:
+; CHECK: adds r0, #2
+ %tmp = add i64 %a, 5066626890203138
+ ret i64 %tmp
+}
+
+; 3747052064576897026 = 0x3400340000000002
+define i64 @f3(i64 %a) {
+; CHECK: f3:
+; CHECK: adds r0, #2
+ %tmp = add i64 %a, 3747052064576897026
+ ret i64 %tmp
+}
+
+; 6221254862626095106 = 0x5656565600000002
+define i64 @f4(i64 %a) {
+; CHECK: f4:
+; CHECK: adds r0, #2
+ %tmp = add i64 %a, 6221254862626095106
+ ret i64 %tmp
+}
+
+; 287104476244869122 = 0x03fc000000000002
+define i64 @f5(i64 %a) {
+; CHECK: f5:
+; CHECK: adds r0, #2
+ %tmp = add i64 %a, 287104476244869122
+ ret i64 %tmp
+}
+
+define i64 @f6(i64 %a, i64 %b) {
+; CHECK: f6:
+; CHECK: adds r0, r0, r2
+ %tmp = add i64 %a, %b
+ ret i64 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-add.ll b/test/CodeGen/Thumb2/thumb2-add.ll
new file mode 100644
index 0000000..5e25cf6
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-add.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #255
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #256
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #257
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #4094
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #4095
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #4096
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep lsl | grep #8
+
+define i32 @t2ADDrc_255(i32 %lhs) {
+ %Rd = add i32 %lhs, 255
+ ret i32 %Rd
+}
+
+define i32 @t2ADDrc_256(i32 %lhs) {
+ %Rd = add i32 %lhs, 256
+ ret i32 %Rd
+}
+
+define i32 @t2ADDrc_257(i32 %lhs) {
+ %Rd = add i32 %lhs, 257
+ ret i32 %Rd
+}
+
+define i32 @t2ADDrc_4094(i32 %lhs) {
+ %Rd = add i32 %lhs, 4094
+ ret i32 %Rd
+}
+
+define i32 @t2ADDrc_4095(i32 %lhs) {
+ %Rd = add i32 %lhs, 4095
+ ret i32 %Rd
+}
+
+define i32 @t2ADDrc_4096(i32 %lhs) {
+ %Rd = add i32 %lhs, 4096
+ ret i32 %Rd
+}
+
+define i32 @t2ADDrr(i32 %lhs, i32 %rhs) {
+ %Rd = add i32 %lhs, %rhs
+ ret i32 %Rd
+}
+
+define i32 @t2ADDrs(i32 %lhs, i32 %rhs) {
+ %tmp = shl i32 %rhs, 8
+ %Rd = add i32 %lhs, %tmp
+ ret i32 %Rd
+}
+
diff --git a/test/CodeGen/Thumb2/thumb2-add2.ll b/test/CodeGen/Thumb2/thumb2-add2.ll
new file mode 100644
index 0000000..e496654
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-add2.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+; 171 = 0x000000ab
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: adds r0, #171
+ %tmp = add i32 %a, 171
+ ret i32 %tmp
+}
+
+; 1179666 = 0x00120012
+define i32 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: add.w r0, r0, #1179666
+ %tmp = add i32 %a, 1179666
+ ret i32 %tmp
+}
+
+; 872428544 = 0x34003400
+define i32 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: add.w r0, r0, #872428544
+ %tmp = add i32 %a, 872428544
+ ret i32 %tmp
+}
+
+; 1448498774 = 0x56565656
+define i32 @f4(i32 %a) {
+; CHECK: f4:
+; CHECK: add.w r0, r0, #1448498774
+ %tmp = add i32 %a, 1448498774
+ ret i32 %tmp
+}
+
+; 510 = 0x000001fe
+define i32 @f5(i32 %a) {
+; CHECK: f5:
+; CHECK: add.w r0, r0, #510
+ %tmp = add i32 %a, 510
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-add3.ll b/test/CodeGen/Thumb2/thumb2-add3.ll
new file mode 100644
index 0000000..58fc333
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-add3.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a) {
+ %tmp = add i32 %a, 4095
+ ret i32 %tmp
+}
+
+; CHECK: f1:
+; CHECK: addw r0, r0, #4095
diff --git a/test/CodeGen/Thumb2/thumb2-add4.ll b/test/CodeGen/Thumb2/thumb2-add4.ll
new file mode 100644
index 0000000..b94e84d
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-add4.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+; 171 = 0x000000ab
+define i64 @f1(i64 %a) {
+; CHECK: f1:
+; CHECK: adds r0, #171
+; CHECK: adc r1, r1, #0
+ %tmp = add i64 %a, 171
+ ret i64 %tmp
+}
+
+; 1179666 = 0x00120012
+define i64 @f2(i64 %a) {
+; CHECK: f2:
+; CHECK: adds.w r0, r0, #1179666
+; CHECK: adc r1, r1, #0
+ %tmp = add i64 %a, 1179666
+ ret i64 %tmp
+}
+
+; 872428544 = 0x34003400
+define i64 @f3(i64 %a) {
+; CHECK: f3:
+; CHECK: adds.w r0, r0, #872428544
+; CHECK: adc r1, r1, #0
+ %tmp = add i64 %a, 872428544
+ ret i64 %tmp
+}
+
+; 1448498774 = 0x56565656
+define i64 @f4(i64 %a) {
+; CHECK: f4:
+; CHECK: adds.w r0, r0, #1448498774
+; CHECK: adc r1, r1, #0
+ %tmp = add i64 %a, 1448498774
+ ret i64 %tmp
+}
+
+; 66846720 = 0x03fc0000
+define i64 @f5(i64 %a) {
+; CHECK: f5:
+; CHECK: adds.w r0, r0, #66846720
+; CHECK: adc r1, r1, #0
+ %tmp = add i64 %a, 66846720
+ ret i64 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-add5.ll b/test/CodeGen/Thumb2/thumb2-add5.ll
new file mode 100644
index 0000000..8b3a4f6
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-add5.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK: f1:
+; CHECK: add r0, r1
+ %tmp = add i32 %a, %b
+ ret i32 %tmp
+}
+
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK: f2:
+; CHECK: add.w r0, r0, r1, lsl #5
+ %tmp = shl i32 %b, 5
+ %tmp1 = add i32 %a, %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f3(i32 %a, i32 %b) {
+; CHECK: f3:
+; CHECK: add.w r0, r0, r1, lsr #6
+ %tmp = lshr i32 %b, 6
+ %tmp1 = add i32 %a, %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f4(i32 %a, i32 %b) {
+; CHECK: f4:
+; CHECK: add.w r0, r0, r1, asr #7
+ %tmp = ashr i32 %b, 7
+ %tmp1 = add i32 %a, %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f5(i32 %a, i32 %b) {
+; CHECK: f5:
+; CHECK: add.w r0, r0, r0, ror #8
+ %l8 = shl i32 %a, 24
+ %r8 = lshr i32 %a, 8
+ %tmp = or i32 %l8, %r8
+ %tmp1 = add i32 %a, %tmp
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/Thumb2/thumb2-add6.ll b/test/CodeGen/Thumb2/thumb2-add6.ll
new file mode 100644
index 0000000..0ecaa79
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-add6.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i64 @f1(i64 %a, i64 %b) {
+; CHECK: f1:
+; CHECK: adds r0, r0, r2
+; CHECK: adcs r1, r3
+ %tmp = add i64 %a, %b
+ ret i64 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-and.ll b/test/CodeGen/Thumb2/thumb2-and.ll
new file mode 100644
index 0000000..8e2245a
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-and.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK: f1:
+; CHECK: ands r0, r1
+ %tmp = and i32 %a, %b
+ ret i32 %tmp
+}
+
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK: f2:
+; CHECK: and.w r0, r0, r1, lsl #5
+ %tmp = shl i32 %b, 5
+ %tmp1 = and i32 %a, %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f3(i32 %a, i32 %b) {
+; CHECK: f3:
+; CHECK: and.w r0, r0, r1, lsr #6
+ %tmp = lshr i32 %b, 6
+ %tmp1 = and i32 %a, %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f4(i32 %a, i32 %b) {
+; CHECK: f4:
+; CHECK: and.w r0, r0, r1, asr #7
+ %tmp = ashr i32 %b, 7
+ %tmp1 = and i32 %a, %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f5(i32 %a, i32 %b) {
+; CHECK: f5:
+; CHECK: and.w r0, r0, r0, ror #8
+ %l8 = shl i32 %a, 24
+ %r8 = lshr i32 %a, 8
+ %tmp = or i32 %l8, %r8
+ %tmp1 = and i32 %a, %tmp
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/Thumb2/thumb2-and2.ll b/test/CodeGen/Thumb2/thumb2-and2.ll
new file mode 100644
index 0000000..76c56d0
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-and2.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+; 171 = 0x000000ab
+define i32 @f1(i32 %a) {
+ %tmp = and i32 %a, 171
+ ret i32 %tmp
+}
+; CHECK: f1:
+; CHECK: and r0, r0, #171
+
+; 1179666 = 0x00120012
+define i32 @f2(i32 %a) {
+ %tmp = and i32 %a, 1179666
+ ret i32 %tmp
+}
+; CHECK: f2:
+; CHECK: and r0, r0, #1179666
+
+; 872428544 = 0x34003400
+define i32 @f3(i32 %a) {
+ %tmp = and i32 %a, 872428544
+ ret i32 %tmp
+}
+; CHECK: f3:
+; CHECK: and r0, r0, #872428544
+
+; 1448498774 = 0x56565656
+define i32 @f4(i32 %a) {
+ %tmp = and i32 %a, 1448498774
+ ret i32 %tmp
+}
+; CHECK: f4:
+; CHECK: and r0, r0, #1448498774
+
+; 66846720 = 0x03fc0000
+define i32 @f5(i32 %a) {
+ %tmp = and i32 %a, 66846720
+ ret i32 %tmp
+}
+; CHECK: f5:
+; CHECK: and r0, r0, #66846720
diff --git a/test/CodeGen/Thumb2/thumb2-asr.ll b/test/CodeGen/Thumb2/thumb2-asr.ll
new file mode 100644
index 0000000..a0a60e6
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-asr.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK: f1:
+; CHECK: asrs r0, r1
+ %tmp = ashr i32 %a, %b
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-asr2.ll b/test/CodeGen/Thumb2/thumb2-asr2.ll
new file mode 100644
index 0000000..9c8634f
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-asr2.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: asrs r0, r0, #17
+ %tmp = ashr i32 %a, 17
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-bcc.ll b/test/CodeGen/Thumb2/thumb2-bcc.ll
new file mode 100644
index 0000000..aae9f5c
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-bcc.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep it
+
+define i32 @t1(i32 %a, i32 %b, i32 %c) {
+; CHECK: t1:
+; CHECK: cbz
+ %tmp2 = icmp eq i32 %a, 0
+ br i1 %tmp2, label %cond_false, label %cond_true
+
+cond_true:
+ %tmp5 = add i32 %b, 1
+ %tmp6 = and i32 %tmp5, %c
+ ret i32 %tmp6
+
+cond_false:
+ %tmp7 = add i32 %b, -1
+ %tmp8 = xor i32 %tmp7, %c
+ ret i32 %tmp8
+}
diff --git a/test/CodeGen/Thumb2/thumb2-bfc.ll b/test/CodeGen/Thumb2/thumb2-bfc.ll
new file mode 100644
index 0000000..b486045
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-bfc.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+; 4278190095 = 0xff00000f
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: bfc r
+ %tmp = and i32 %a, 4278190095
+ ret i32 %tmp
+}
+
+; 4286578688 = 0xff800000
+define i32 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: bfc r
+ %tmp = and i32 %a, 4286578688
+ ret i32 %tmp
+}
+
+; 4095 = 0x00000fff
+define i32 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: bfc r
+ %tmp = and i32 %a, 4095
+ ret i32 %tmp
+}
+
+; 2147483646 = 0x7ffffffe not implementable w/ BFC
+define i32 @f4(i32 %a) {
+; CHECK: f4:
+ %tmp = and i32 %a, 2147483646
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-bic.ll b/test/CodeGen/Thumb2/thumb2-bic.ll
new file mode 100644
index 0000000..4e35383
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-bic.ll
@@ -0,0 +1,105 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK: f1:
+; CHECK: bics r0, r1
+ %tmp = xor i32 %b, 4294967295
+ %tmp1 = and i32 %a, %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK: f2:
+; CHECK: bics r0, r1
+ %tmp = xor i32 %b, 4294967295
+ %tmp1 = and i32 %tmp, %a
+ ret i32 %tmp1
+}
+
+define i32 @f3(i32 %a, i32 %b) {
+; CHECK: f3:
+; CHECK: bics r0, r1
+ %tmp = xor i32 4294967295, %b
+ %tmp1 = and i32 %a, %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f4(i32 %a, i32 %b) {
+; CHECK: f4:
+; CHECK: bics r0, r1
+ %tmp = xor i32 4294967295, %b
+ %tmp1 = and i32 %tmp, %a
+ ret i32 %tmp1
+}
+
+define i32 @f5(i32 %a, i32 %b) {
+; CHECK: f5:
+; CHECK: bic.w r0, r0, r1, lsl #5
+ %tmp = shl i32 %b, 5
+ %tmp1 = xor i32 4294967295, %tmp
+ %tmp2 = and i32 %a, %tmp1
+ ret i32 %tmp2
+}
+
+define i32 @f6(i32 %a, i32 %b) {
+; CHECK: f6:
+; CHECK: bic.w r0, r0, r1, lsr #6
+ %tmp = lshr i32 %b, 6
+ %tmp1 = xor i32 %tmp, 4294967295
+ %tmp2 = and i32 %tmp1, %a
+ ret i32 %tmp2
+}
+
+define i32 @f7(i32 %a, i32 %b) {
+; CHECK: f7:
+; CHECK: bic.w r0, r0, r1, asr #7
+ %tmp = ashr i32 %b, 7
+ %tmp1 = xor i32 %tmp, 4294967295
+ %tmp2 = and i32 %a, %tmp1
+ ret i32 %tmp2
+}
+
+define i32 @f8(i32 %a, i32 %b) {
+; CHECK: f8:
+; CHECK: bic.w r0, r0, r0, ror #8
+ %l8 = shl i32 %a, 24
+ %r8 = lshr i32 %a, 8
+ %tmp = or i32 %l8, %r8
+ %tmp1 = xor i32 4294967295, %tmp
+ %tmp2 = and i32 %tmp1, %a
+ ret i32 %tmp2
+}
+
+; ~0x000000bb = 4294967108
+define i32 @f9(i32 %a) {
+ %tmp = and i32 %a, 4294967108
+ ret i32 %tmp
+
+; CHECK: f9:
+; CHECK: bic r0, r0, #187
+}
+
+; ~0x00aa00aa = 4283826005
+define i32 @f10(i32 %a) {
+ %tmp = and i32 %a, 4283826005
+ ret i32 %tmp
+
+; CHECK: f10:
+; CHECK: bic r0, r0, #11141290
+}
+
+; ~0xcc00cc00 = 872363007
+define i32 @f11(i32 %a) {
+ %tmp = and i32 %a, 872363007
+ ret i32 %tmp
+; CHECK: f11:
+; CHECK: bic r0, r0, #-872363008
+}
+
+; ~0x00110000 = 4293853183
+define i32 @f12(i32 %a) {
+ %tmp = and i32 %a, 4293853183
+ ret i32 %tmp
+; CHECK: f12:
+; CHECK: bic r0, r0, #1114112
+}
diff --git a/test/CodeGen/Thumb2/thumb2-branch.ll b/test/CodeGen/Thumb2/thumb2-branch.ll
new file mode 100644
index 0000000..1298384
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-branch.ll
@@ -0,0 +1,61 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
+
+define void @f1(i32 %a, i32 %b, i32* %v) {
+entry:
+; CHECK: f1:
+; CHECK: bne LBB
+ %tmp = icmp eq i32 %a, %b ; <i1> [#uses=1]
+ br i1 %tmp, label %cond_true, label %return
+
+cond_true: ; preds = %entry
+ store i32 0, i32* %v
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
+
+define void @f2(i32 %a, i32 %b, i32* %v) {
+entry:
+; CHECK: f2:
+; CHECK: bge LBB
+ %tmp = icmp slt i32 %a, %b ; <i1> [#uses=1]
+ br i1 %tmp, label %cond_true, label %return
+
+cond_true: ; preds = %entry
+ store i32 0, i32* %v
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
+
+define void @f3(i32 %a, i32 %b, i32* %v) {
+entry:
+; CHECK: f3:
+; CHECK: bhs LBB
+ %tmp = icmp ult i32 %a, %b ; <i1> [#uses=1]
+ br i1 %tmp, label %cond_true, label %return
+
+cond_true: ; preds = %entry
+ store i32 0, i32* %v
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
+
+define void @f4(i32 %a, i32 %b, i32* %v) {
+entry:
+; CHECK: f4:
+; CHECK: blo LBB
+ %tmp = icmp ult i32 %a, %b ; <i1> [#uses=1]
+ br i1 %tmp, label %return, label %cond_true
+
+cond_true: ; preds = %entry
+ store i32 0, i32* %v
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/thumb2-call.ll b/test/CodeGen/Thumb2/thumb2-call.ll
new file mode 100644
index 0000000..7dc6b26
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-call.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s -check-prefix=DARWIN
+; RUN: llc < %s -mtriple=thumbv7-linux -mattr=+thumb2 | FileCheck %s -check-prefix=LINUX
+
+@t = weak global i32 ()* null ; <i32 ()**> [#uses=1]
+
+declare void @g(i32, i32, i32, i32)
+
+define void @f() {
+; DARWIN: f:
+; DARWIN: blx _g
+
+; LINUX: f:
+; LINUX: bl g
+ call void @g( i32 1, i32 2, i32 3, i32 4 )
+ ret void
+}
+
+define void @h() {
+; DARWIN: h:
+; DARWIN: blx r0
+
+; LINUX: h:
+; LINUX: blx r0
+ %tmp = load i32 ()** @t ; <i32 ()*> [#uses=1]
+ %tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/thumb2-cbnz.ll b/test/CodeGen/Thumb2/thumb2-cbnz.ll
new file mode 100644
index 0000000..0fc6899
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-cbnz.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
+; rdar://7354379
+
+declare arm_apcscc double @floor(double) nounwind readnone
+
+define void @t(i1 %a, double %b) {
+entry:
+ br i1 %a, label %bb3, label %bb1
+
+bb1: ; preds = %entry
+ unreachable
+
+bb3: ; preds = %entry
+ br i1 %a, label %bb7, label %bb5
+
+bb5: ; preds = %bb3
+ unreachable
+
+bb7: ; preds = %bb3
+ br i1 %a, label %bb11, label %bb9
+
+bb9: ; preds = %bb7
+; CHECK: cmp r0, #0
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: cbnz
+ %0 = tail call arm_apcscc double @floor(double %b) nounwind readnone ; <double> [#uses=0]
+ br label %bb11
+
+bb11: ; preds = %bb9, %bb7
+ %1 = getelementptr i32* undef, i32 0
+ store i32 0, i32* %1
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/thumb2-clz.ll b/test/CodeGen/Thumb2/thumb2-clz.ll
new file mode 100644
index 0000000..74728bf
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-clz.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | FileCheck %s
+
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: clz r
+ %tmp = tail call i32 @llvm.ctlz.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.ctlz.i32(i32) nounwind readnone
diff --git a/test/CodeGen/Thumb2/thumb2-cmn.ll b/test/CodeGen/Thumb2/thumb2-cmn.ll
new file mode 100644
index 0000000..eeaaa7f
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-cmn.ll
@@ -0,0 +1,72 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i1 @f1(i32 %a, i32 %b) {
+ %nb = sub i32 0, %b
+ %tmp = icmp ne i32 %a, %nb
+ ret i1 %tmp
+}
+; CHECK: f1:
+; CHECK: cmn.w r0, r1
+
+define i1 @f2(i32 %a, i32 %b) {
+ %nb = sub i32 0, %b
+ %tmp = icmp ne i32 %nb, %a
+ ret i1 %tmp
+}
+; CHECK: f2:
+; CHECK: cmn.w r0, r1
+
+define i1 @f3(i32 %a, i32 %b) {
+ %nb = sub i32 0, %b
+ %tmp = icmp eq i32 %a, %nb
+ ret i1 %tmp
+}
+; CHECK: f3:
+; CHECK: cmn.w r0, r1
+
+define i1 @f4(i32 %a, i32 %b) {
+ %nb = sub i32 0, %b
+ %tmp = icmp eq i32 %nb, %a
+ ret i1 %tmp
+}
+; CHECK: f4:
+; CHECK: cmn.w r0, r1
+
+define i1 @f5(i32 %a, i32 %b) {
+ %tmp = shl i32 %b, 5
+ %nb = sub i32 0, %tmp
+ %tmp1 = icmp eq i32 %nb, %a
+ ret i1 %tmp1
+}
+; CHECK: f5:
+; CHECK: cmn.w r0, r1, lsl #5
+
+define i1 @f6(i32 %a, i32 %b) {
+ %tmp = lshr i32 %b, 6
+ %nb = sub i32 0, %tmp
+ %tmp1 = icmp ne i32 %nb, %a
+ ret i1 %tmp1
+}
+; CHECK: f6:
+; CHECK: cmn.w r0, r1, lsr #6
+
+define i1 @f7(i32 %a, i32 %b) {
+ %tmp = ashr i32 %b, 7
+ %nb = sub i32 0, %tmp
+ %tmp1 = icmp eq i32 %a, %nb
+ ret i1 %tmp1
+}
+; CHECK: f7:
+; CHECK: cmn.w r0, r1, asr #7
+
+define i1 @f8(i32 %a, i32 %b) {
+ %l8 = shl i32 %a, 24
+ %r8 = lshr i32 %a, 8
+ %tmp = or i32 %l8, %r8
+ %nb = sub i32 0, %tmp
+ %tmp1 = icmp ne i32 %a, %nb
+ ret i1 %tmp1
+}
+; CHECK: f8:
+; CHECK: cmn.w r0, r0, ror #8
+
diff --git a/test/CodeGen/Thumb2/thumb2-cmn2.ll b/test/CodeGen/Thumb2/thumb2-cmn2.ll
new file mode 100644
index 0000000..c0e19f6
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-cmn2.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+; -0x000000bb = 4294967109
+define i1 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: cmn.w {{r.*}}, #187
+ %tmp = icmp ne i32 %a, 4294967109
+ ret i1 %tmp
+}
+
+; -0x00aa00aa = 4283826006
+define i1 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: cmn.w {{r.*}}, #11141290
+ %tmp = icmp eq i32 %a, 4283826006
+ ret i1 %tmp
+}
+
+; -0xcc00cc00 = 872363008
+define i1 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: cmn.w {{r.*}}, #-872363008
+ %tmp = icmp ne i32 %a, 872363008
+ ret i1 %tmp
+}
+
+; -0x00110000 = 4293853184
+define i1 @f4(i32 %a) {
+; CHECK: f4:
+; CHECK: cmn.w {{r.*}}, #1114112
+ %tmp = icmp eq i32 %a, 4293853184
+ ret i1 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-cmp.ll b/test/CodeGen/Thumb2/thumb2-cmp.ll
new file mode 100644
index 0000000..d4773bb
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-cmp.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+; 0x000000bb = 187
+define i1 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: cmp r0, #187
+ %tmp = icmp ne i32 %a, 187
+ ret i1 %tmp
+}
+
+; 0x00aa00aa = 11141290
+define i1 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: cmp.w r0, #11141290
+ %tmp = icmp eq i32 %a, 11141290
+ ret i1 %tmp
+}
+
+; 0xcc00cc00 = 3422604288
+define i1 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: cmp.w r0, #-872363008
+ %tmp = icmp ne i32 %a, 3422604288
+ ret i1 %tmp
+}
+
+; 0xdddddddd = 3722304989
+define i1 @f4(i32 %a) {
+; CHECK: f4:
+; CHECK: cmp.w r0, #-572662307
+ %tmp = icmp ne i32 %a, 3722304989
+ ret i1 %tmp
+}
+
+; 0x00110000 = 1114112
+define i1 @f5(i32 %a) {
+; CHECK: f5:
+; CHECK: cmp.w r0, #1114112
+ %tmp = icmp eq i32 %a, 1114112
+ ret i1 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-cmp2.ll b/test/CodeGen/Thumb2/thumb2-cmp2.ll
new file mode 100644
index 0000000..55c321d
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-cmp2.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i1 @f1(i32 %a, i32 %b) {
+; CHECK: f1:
+; CHECK: cmp r0, r1
+ %tmp = icmp ne i32 %a, %b
+ ret i1 %tmp
+}
+
+define i1 @f2(i32 %a, i32 %b) {
+; CHECK: f2:
+; CHECK: cmp r0, r1
+ %tmp = icmp eq i32 %a, %b
+ ret i1 %tmp
+}
+
+define i1 @f6(i32 %a, i32 %b) {
+; CHECK: f6:
+; CHECK: cmp.w r0, r1, lsl #5
+ %tmp = shl i32 %b, 5
+ %tmp1 = icmp eq i32 %tmp, %a
+ ret i1 %tmp1
+}
+
+define i1 @f7(i32 %a, i32 %b) {
+; CHECK: f7:
+; CHECK: cmp.w r0, r1, lsr #6
+ %tmp = lshr i32 %b, 6
+ %tmp1 = icmp ne i32 %tmp, %a
+ ret i1 %tmp1
+}
+
+define i1 @f8(i32 %a, i32 %b) {
+; CHECK: f8:
+; CHECK: cmp.w r0, r1, asr #7
+ %tmp = ashr i32 %b, 7
+ %tmp1 = icmp eq i32 %a, %tmp
+ ret i1 %tmp1
+}
+
+define i1 @f9(i32 %a, i32 %b) {
+; CHECK: f9:
+; CHECK: cmp.w r0, r0, ror #8
+ %l8 = shl i32 %a, 24
+ %r8 = lshr i32 %a, 8
+ %tmp = or i32 %l8, %r8
+ %tmp1 = icmp ne i32 %a, %tmp
+ ret i1 %tmp1
+}
diff --git a/test/CodeGen/Thumb2/thumb2-eor.ll b/test/CodeGen/Thumb2/thumb2-eor.ll
new file mode 100644
index 0000000..b7e2766
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-eor.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK: f1:
+; CHECK: eors r0, r1
+ %tmp = xor i32 %a, %b
+ ret i32 %tmp
+}
+
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK: f2:
+; CHECK: eor.w r0, r1, r0
+ %tmp = xor i32 %b, %a
+ ret i32 %tmp
+}
+
+define i32 @f3(i32 %a, i32 %b) {
+; CHECK: f3:
+; CHECK: eor.w r0, r0, r1, lsl #5
+ %tmp = shl i32 %b, 5
+ %tmp1 = xor i32 %a, %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f4(i32 %a, i32 %b) {
+; CHECK: f4:
+; CHECK: eor.w r0, r0, r1, lsr #6
+ %tmp = lshr i32 %b, 6
+ %tmp1 = xor i32 %tmp, %a
+ ret i32 %tmp1
+}
+
+define i32 @f5(i32 %a, i32 %b) {
+; CHECK: f5:
+; CHECK: eor.w r0, r0, r1, asr #7
+ %tmp = ashr i32 %b, 7
+ %tmp1 = xor i32 %a, %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f6(i32 %a, i32 %b) {
+; CHECK: f6:
+; CHECK: eor.w r0, r0, r0, ror #8
+ %l8 = shl i32 %a, 24
+ %r8 = lshr i32 %a, 8
+ %tmp = or i32 %l8, %r8
+ %tmp1 = xor i32 %tmp, %a
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/Thumb2/thumb2-eor2.ll b/test/CodeGen/Thumb2/thumb2-eor2.ll
new file mode 100644
index 0000000..6b2e9dc
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-eor2.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+; 0x000000bb = 187
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: eor {{.*}}#187
+ %tmp = xor i32 %a, 187
+ ret i32 %tmp
+}
+
+; 0x00aa00aa = 11141290
+define i32 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: eor {{.*}}#11141290
+ %tmp = xor i32 %a, 11141290
+ ret i32 %tmp
+}
+
+; 0xcc00cc00 = 3422604288
+define i32 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: eor {{.*}}#-872363008
+ %tmp = xor i32 %a, 3422604288
+ ret i32 %tmp
+}
+
+; 0xdddddddd = 3722304989
+define i32 @f4(i32 %a) {
+; CHECK: f4:
+; CHECK: eor {{.*}}#-572662307
+ %tmp = xor i32 %a, 3722304989
+ ret i32 %tmp
+}
+
+; 0x00110000 = 1114112
+define i32 @f5(i32 %a) {
+; CHECK: f5:
+; CHECK: eor {{.*}}#1114112
+ %tmp = xor i32 %a, 1114112
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
new file mode 100644
index 0000000..71199ab
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
@@ -0,0 +1,84 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
+
+define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
+; CHECK: t1:
+; CHECK: it ne
+; CHECK: cmpne
+ switch i32 %c, label %cond_next [
+ i32 1, label %cond_true
+ i32 7, label %cond_true
+ ]
+
+cond_true:
+ %tmp12 = add i32 %a, 1
+ %tmp1518 = add i32 %tmp12, %b
+ ret i32 %tmp1518
+
+cond_next:
+ %tmp15 = add i32 %b, %a
+ ret i32 %tmp15
+}
+
+; FIXME: Check for # of unconditional branch after adding branch folding post ifcvt.
+define i32 @t2(i32 %a, i32 %b) {
+entry:
+; CHECK: t2:
+; CHECK: ite le
+; CHECK: suble
+; CHECK: subgt
+ %tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1]
+ br i1 %tmp1434, label %bb17, label %bb.outer
+
+bb.outer: ; preds = %cond_false, %entry
+ %b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ] ; <i32> [#uses=5]
+ %a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1]
+ br label %bb
+
+bb: ; preds = %cond_true, %bb.outer
+ %indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ] ; <i32> [#uses=2]
+ %tmp. = sub i32 0, %b_addr.021.0.ph ; <i32> [#uses=1]
+ %tmp.40 = mul i32 %indvar, %tmp. ; <i32> [#uses=1]
+ %a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph ; <i32> [#uses=6]
+ %tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph ; <i1> [#uses=1]
+ br i1 %tmp3, label %cond_true, label %cond_false
+
+cond_true: ; preds = %bb
+ %tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph ; <i32> [#uses=2]
+ %tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph ; <i1> [#uses=1]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br i1 %tmp1437, label %bb17, label %bb
+
+cond_false: ; preds = %bb
+ %tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0 ; <i32> [#uses=2]
+ %tmp14 = icmp eq i32 %a_addr.026.0, %tmp10 ; <i1> [#uses=1]
+ br i1 %tmp14, label %bb17, label %bb.outer
+
+bb17: ; preds = %cond_false, %cond_true, %entry
+ %a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1]
+ ret i32 %a_addr.026.1
+}
+
+@x = external global i32* ; <i32**> [#uses=1]
+
+define void @foo(i32 %a) {
+entry:
+ %tmp = load i32** @x ; <i32*> [#uses=1]
+ store i32 %a, i32* %tmp
+ ret void
+}
+
+define void @t3(i32 %a, i32 %b) {
+entry:
+; CHECK: t3:
+; CHECK: it lt
+; CHECK: poplt {r7, pc}
+ %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
+ br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
+
+cond_true: ; preds = %entry
+ tail call void @foo( i32 %b )
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
new file mode 100644
index 0000000..d917ffe
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
@@ -0,0 +1,93 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
+
+define void @foo(i32 %X, i32 %Y) {
+entry:
+; CHECK: foo:
+; CHECK: it ne
+; CHECK: cmpne
+; CHECK: it hi
+; CHECK: pophi {r7, pc}
+ %tmp1 = icmp ult i32 %X, 4 ; <i1> [#uses=1]
+ %tmp4 = icmp eq i32 %Y, 0 ; <i1> [#uses=1]
+ %tmp7 = or i1 %tmp4, %tmp1 ; <i1> [#uses=1]
+ br i1 %tmp7, label %cond_true, label %UnifiedReturnBlock
+
+cond_true: ; preds = %entry
+ %tmp10 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+declare i32 @bar(...)
+
+; FIXME: Need post-ifcvt branch folding to get rid of the extra br at end of BB1.
+
+ %struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }
+
+define fastcc i32 @CountTree(%struct.quad_struct* %tree) {
+entry:
+; CHECK: CountTree:
+; CHECK: it eq
+; CHECK: cmpeq
+; CHECK: bne
+; CHECK: itt eq
+; CHECK: moveq
+; CHECK: popeq
+ br label %tailrecurse
+
+tailrecurse: ; preds = %bb, %entry
+ %tmp6 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1]
+ %tmp9 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=2]
+ %tmp12 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1]
+ %tmp14 = icmp eq %struct.quad_struct* null, null ; <i1> [#uses=1]
+ %tmp17 = icmp eq %struct.quad_struct* %tmp6, null ; <i1> [#uses=1]
+ %tmp23 = icmp eq %struct.quad_struct* %tmp9, null ; <i1> [#uses=1]
+ %tmp29 = icmp eq %struct.quad_struct* %tmp12, null ; <i1> [#uses=1]
+ %bothcond = and i1 %tmp17, %tmp14 ; <i1> [#uses=1]
+ %bothcond1 = and i1 %bothcond, %tmp23 ; <i1> [#uses=1]
+ %bothcond2 = and i1 %bothcond1, %tmp29 ; <i1> [#uses=1]
+ br i1 %bothcond2, label %return, label %bb
+
+bb: ; preds = %tailrecurse
+ %tmp41 = tail call fastcc i32 @CountTree( %struct.quad_struct* %tmp9 ) ; <i32> [#uses=0]
+ br label %tailrecurse
+
+return: ; preds = %tailrecurse
+ ret i32 0
+}
+
+ %struct.SString = type { i8*, i32, i32 }
+
+declare void @abort()
+
+define fastcc void @t1(%struct.SString* %word, i8 signext %c) {
+entry:
+; CHECK: t1:
+; CHECK: it ne
+; CHECK: popne {r7, pc}
+ %tmp1 = icmp eq %struct.SString* %word, null ; <i1> [#uses=1]
+ br i1 %tmp1, label %cond_true, label %cond_false
+
+cond_true: ; preds = %entry
+ tail call void @abort( )
+ unreachable
+
+cond_false: ; preds = %entry
+ ret void
+}
+
+define fastcc void @t2() nounwind {
+entry:
+; CHECK: t2:
+; CHECK: cmp r0, #0
+; CHECK: beq
+ br i1 undef, label %bb.i.i3, label %growMapping.exit
+
+bb.i.i3: ; preds = %entry
+ unreachable
+
+growMapping.exit: ; preds = %entry
+ unreachable
+}
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll
new file mode 100644
index 0000000..496158c
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
+
+; There shouldn't be a unconditional branch at end of bb52.
+; rdar://7184787
+
+@posed = external global i64 ; <i64*> [#uses=1]
+
+define i1 @ab_bb52(i64 %.reload78, i64* %.out, i64* %.out1) nounwind {
+newFuncRoot:
+ br label %bb52
+
+bb52.bb55_crit_edge.exitStub: ; preds = %bb52
+ store i64 %0, i64* %.out
+ store i64 %2, i64* %.out1
+ ret i1 true
+
+bb52.bb53_crit_edge.exitStub: ; preds = %bb52
+ store i64 %0, i64* %.out
+ store i64 %2, i64* %.out1
+ ret i1 false
+
+bb52: ; preds = %newFuncRoot
+; CHECK: movne
+; CHECK: moveq
+; CHECK: pop
+; CHECK-NEXT: LBB1_1:
+ %0 = load i64* @posed, align 4 ; <i64> [#uses=3]
+ %1 = sub i64 %0, %.reload78 ; <i64> [#uses=1]
+ %2 = ashr i64 %1, 1 ; <i64> [#uses=3]
+ %3 = icmp eq i64 %2, 0 ; <i1> [#uses=1]
+ br i1 %3, label %bb52.bb55_crit_edge.exitStub, label %bb52.bb53_crit_edge.exitStub
+}
diff --git a/test/CodeGen/Thumb2/thumb2-jtb.ll b/test/CodeGen/Thumb2/thumb2-jtb.ll
new file mode 100644
index 0000000..f5a56e5
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-jtb.ll
@@ -0,0 +1,120 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 -arm-adjust-jump-tables=0 | not grep tbb
+
+; Do not use tbb / tbh if any destination is before the jumptable.
+; rdar://7102917
+
+define i16 @main__getopt_internal_2E_exit_2E_ce(i32) nounwind {
+newFuncRoot:
+ br label %_getopt_internal.exit.ce
+
+codeRepl127.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 0
+
+parse_options.exit.loopexit.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 1
+
+bb1.i.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 2
+
+bb90.i.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 3
+
+codeRepl104.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 4
+
+codeRepl113.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 5
+
+codeRepl51.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 6
+
+codeRepl70.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 7
+
+codeRepl119.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 8
+
+codeRepl93.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 9
+
+codeRepl101.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 10
+
+codeRepl120.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 11
+
+codeRepl89.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 12
+
+codeRepl45.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 13
+
+codeRepl58.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 14
+
+codeRepl46.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 15
+
+codeRepl50.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 16
+
+codeRepl52.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 17
+
+codeRepl53.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 18
+
+codeRepl61.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 19
+
+codeRepl85.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 20
+
+codeRepl97.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 21
+
+codeRepl79.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 22
+
+codeRepl102.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 23
+
+codeRepl54.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 24
+
+codeRepl57.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 25
+
+codeRepl103.exitStub: ; preds = %_getopt_internal.exit.ce
+ ret i16 26
+
+_getopt_internal.exit.ce: ; preds = %newFuncRoot
+ switch i32 %0, label %codeRepl127.exitStub [
+ i32 -1, label %parse_options.exit.loopexit.exitStub
+ i32 0, label %bb1.i.exitStub
+ i32 63, label %bb90.i.exitStub
+ i32 66, label %codeRepl104.exitStub
+ i32 67, label %codeRepl113.exitStub
+ i32 71, label %codeRepl51.exitStub
+ i32 77, label %codeRepl70.exitStub
+ i32 78, label %codeRepl119.exitStub
+ i32 80, label %codeRepl93.exitStub
+ i32 81, label %codeRepl101.exitStub
+ i32 82, label %codeRepl120.exitStub
+ i32 88, label %codeRepl89.exitStub
+ i32 97, label %codeRepl45.exitStub
+ i32 98, label %codeRepl58.exitStub
+ i32 99, label %codeRepl46.exitStub
+ i32 100, label %codeRepl50.exitStub
+ i32 104, label %codeRepl52.exitStub
+ i32 108, label %codeRepl53.exitStub
+ i32 109, label %codeRepl61.exitStub
+ i32 110, label %codeRepl85.exitStub
+ i32 111, label %codeRepl97.exitStub
+ i32 113, label %codeRepl79.exitStub
+ i32 114, label %codeRepl102.exitStub
+ i32 115, label %codeRepl54.exitStub
+ i32 116, label %codeRepl57.exitStub
+ i32 118, label %codeRepl103.exitStub
+ ]
+}
diff --git a/test/CodeGen/Thumb2/thumb2-ldm.ll b/test/CodeGen/Thumb2/thumb2-ldm.ll
new file mode 100644
index 0000000..da2874d
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-ldm.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
+
+@X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
+
+define i32 @t1() {
+; CHECK: t1:
+; CHECK: push {r7, lr}
+; CHECK: pop {r7, pc}
+ %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1]
+ %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
+ %tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; <i32> [#uses=1]
+ ret i32 %tmp4
+}
+
+define i32 @t2() {
+; CHECK: t2:
+; CHECK: push {r7, lr}
+; CHECK: ldmia
+; CHECK: pop {r7, pc}
+ %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
+ %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
+ %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4) ; <i32> [#uses=1]
+ %tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+define i32 @t3() {
+; CHECK: t3:
+; CHECK: push {r7, lr}
+; CHECK: pop {r7, pc}
+ %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
+ %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
+ %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
+ %tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+declare i32 @f1(i32, i32)
+
+declare i32 @f2(i32, i32, i32)
diff --git a/test/CodeGen/Thumb2/thumb2-ldr.ll b/test/CodeGen/Thumb2/thumb2-ldr.ll
new file mode 100644
index 0000000..94888fd
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-ldr.ll
@@ -0,0 +1,72 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32* %v) {
+entry:
+; CHECK: f1:
+; CHECK: ldr r0, [r0]
+ %tmp = load i32* %v
+ ret i32 %tmp
+}
+
+define i32 @f2(i32* %v) {
+entry:
+; CHECK: f2:
+; CHECK: ldr.w r0, [r0, #+4092]
+ %tmp2 = getelementptr i32* %v, i32 1023
+ %tmp = load i32* %tmp2
+ ret i32 %tmp
+}
+
+define i32 @f3(i32* %v) {
+entry:
+; CHECK: f3:
+; CHECK: mov.w r1, #4096
+; CHECK: ldr r0, [r0, r1]
+ %tmp2 = getelementptr i32* %v, i32 1024
+ %tmp = load i32* %tmp2
+ ret i32 %tmp
+}
+
+define i32 @f4(i32 %base) {
+entry:
+; CHECK: f4:
+; CHECK: ldr r0, [r0, #-128]
+ %tmp1 = sub i32 %base, 128
+ %tmp2 = inttoptr i32 %tmp1 to i32*
+ %tmp3 = load i32* %tmp2
+ ret i32 %tmp3
+}
+
+define i32 @f5(i32 %base, i32 %offset) {
+entry:
+; CHECK: f5:
+; CHECK: ldr r0, [r0, r1]
+ %tmp1 = add i32 %base, %offset
+ %tmp2 = inttoptr i32 %tmp1 to i32*
+ %tmp3 = load i32* %tmp2
+ ret i32 %tmp3
+}
+
+define i32 @f6(i32 %base, i32 %offset) {
+entry:
+; CHECK: f6:
+; CHECK: ldr.w r0, [r0, r1, lsl #2]
+ %tmp1 = shl i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i32*
+ %tmp4 = load i32* %tmp3
+ ret i32 %tmp4
+}
+
+define i32 @f7(i32 %base, i32 %offset) {
+entry:
+; CHECK: f7:
+; CHECK: lsrs r1, r1, #2
+; CHECK: ldr r0, [r0, r1]
+
+ %tmp1 = lshr i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i32*
+ %tmp4 = load i32* %tmp3
+ ret i32 %tmp4
+}
diff --git a/test/CodeGen/Thumb2/thumb2-ldr_ext.ll b/test/CodeGen/Thumb2/thumb2-ldr_ext.ll
new file mode 100644
index 0000000..9e6aef4
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-ldr_ext.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep ldrb | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep ldrh | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep ldrsb | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep ldrsh | count 1
+
+define i32 @test1(i8* %v.pntr.s0.u1) {
+ %tmp.u = load i8* %v.pntr.s0.u1
+ %tmp1.s = zext i8 %tmp.u to i32
+ ret i32 %tmp1.s
+}
+
+define i32 @test2(i16* %v.pntr.s0.u1) {
+ %tmp.u = load i16* %v.pntr.s0.u1
+ %tmp1.s = zext i16 %tmp.u to i32
+ ret i32 %tmp1.s
+}
+
+define i32 @test3(i8* %v.pntr.s1.u0) {
+ %tmp.s = load i8* %v.pntr.s1.u0
+ %tmp1.s = sext i8 %tmp.s to i32
+ ret i32 %tmp1.s
+}
+
+define i32 @test4() {
+ %tmp.s = load i16* null
+ %tmp1.s = sext i16 %tmp.s to i32
+ ret i32 %tmp1.s
+}
diff --git a/test/CodeGen/Thumb2/thumb2-ldr_post.ll b/test/CodeGen/Thumb2/thumb2-ldr_post.ll
new file mode 100644
index 0000000..d1af4ba
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-ldr_post.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
+; RUN: grep {ldr.*\\\[.*\],} | count 1
+
+define i32 @test(i32 %a, i32 %b, i32 %c) {
+ %tmp1 = mul i32 %a, %b ; <i32> [#uses=2]
+ %tmp2 = inttoptr i32 %tmp1 to i32* ; <i32*> [#uses=1]
+ %tmp3 = load i32* %tmp2 ; <i32> [#uses=1]
+ %tmp4 = sub i32 %tmp1, 8 ; <i32> [#uses=1]
+ %tmp5 = mul i32 %tmp4, %tmp3 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
diff --git a/test/CodeGen/Thumb2/thumb2-ldr_pre.ll b/test/CodeGen/Thumb2/thumb2-ldr_pre.ll
new file mode 100644
index 0000000..9cc3f4a
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-ldr_pre.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
+; RUN: grep {ldr.*\\!} | count 3
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
+; RUN: grep {ldrsb.*\\!} | count 1
+
+define i32* @test1(i32* %X, i32* %dest) {
+ %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2]
+ %A = load i32* %Y ; <i32> [#uses=1]
+ store i32 %A, i32* %dest
+ ret i32* %Y
+}
+
+define i32 @test2(i32 %a, i32 %b) {
+ %tmp1 = sub i32 %a, 64 ; <i32> [#uses=2]
+ %tmp2 = inttoptr i32 %tmp1 to i32* ; <i32*> [#uses=1]
+ %tmp3 = load i32* %tmp2 ; <i32> [#uses=1]
+ %tmp4 = sub i32 %tmp1, %b ; <i32> [#uses=1]
+ %tmp5 = add i32 %tmp4, %tmp3 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
+define i8* @test3(i8* %X, i32* %dest) {
+ %tmp1 = getelementptr i8* %X, i32 4
+ %tmp2 = load i8* %tmp1
+ %tmp3 = sext i8 %tmp2 to i32
+ store i32 %tmp3, i32* %dest
+ ret i8* %tmp1
+}
diff --git a/test/CodeGen/Thumb2/thumb2-ldrb.ll b/test/CodeGen/Thumb2/thumb2-ldrb.ll
new file mode 100644
index 0000000..bf10097
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-ldrb.ll
@@ -0,0 +1,72 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i8 @f1(i8* %v) {
+entry:
+; CHECK: f1:
+; CHECK: ldrb r0, [r0]
+ %tmp = load i8* %v
+ ret i8 %tmp
+}
+
+define i8 @f2(i8* %v) {
+entry:
+; CHECK: f2:
+; CHECK: ldrb r0, [r0, #-1]
+ %tmp2 = getelementptr i8* %v, i8 1023
+ %tmp = load i8* %tmp2
+ ret i8 %tmp
+}
+
+define i8 @f3(i32 %base) {
+entry:
+; CHECK: f3:
+; CHECK: mov.w r1, #4096
+; CHECK: ldrb r0, [r0, r1]
+ %tmp1 = add i32 %base, 4096
+ %tmp2 = inttoptr i32 %tmp1 to i8*
+ %tmp3 = load i8* %tmp2
+ ret i8 %tmp3
+}
+
+define i8 @f4(i32 %base) {
+entry:
+; CHECK: f4:
+; CHECK: ldrb r0, [r0, #-128]
+ %tmp1 = sub i32 %base, 128
+ %tmp2 = inttoptr i32 %tmp1 to i8*
+ %tmp3 = load i8* %tmp2
+ ret i8 %tmp3
+}
+
+define i8 @f5(i32 %base, i32 %offset) {
+entry:
+; CHECK: f5:
+; CHECK: ldrb r0, [r0, r1]
+ %tmp1 = add i32 %base, %offset
+ %tmp2 = inttoptr i32 %tmp1 to i8*
+ %tmp3 = load i8* %tmp2
+ ret i8 %tmp3
+}
+
+define i8 @f6(i32 %base, i32 %offset) {
+entry:
+; CHECK: f6:
+; CHECK: ldrb.w r0, [r0, r1, lsl #2]
+ %tmp1 = shl i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i8*
+ %tmp4 = load i8* %tmp3
+ ret i8 %tmp4
+}
+
+define i8 @f7(i32 %base, i32 %offset) {
+entry:
+; CHECK: f7:
+; CHECK: lsrs r1, r1, #2
+; CHECK: ldrb r0, [r0, r1]
+ %tmp1 = lshr i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i8*
+ %tmp4 = load i8* %tmp3
+ ret i8 %tmp4
+}
diff --git a/test/CodeGen/Thumb2/thumb2-ldrd.ll b/test/CodeGen/Thumb2/thumb2-ldrd.ll
new file mode 100644
index 0000000..22d4e88
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-ldrd.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
+
+@b = external global i64*
+
+define i64 @t(i64 %a) nounwind readonly {
+entry:
+;CHECK: ldrd r2, [r2]
+ %0 = load i64** @b, align 4
+ %1 = load i64* %0, align 4
+ %2 = mul i64 %1, %a
+ ret i64 %2
+}
diff --git a/test/CodeGen/Thumb2/thumb2-ldrh.ll b/test/CodeGen/Thumb2/thumb2-ldrh.ll
new file mode 100644
index 0000000..f1fb79c
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-ldrh.ll
@@ -0,0 +1,71 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i16 @f1(i16* %v) {
+entry:
+; CHECK: f1:
+; CHECK: ldrh r0, [r0]
+ %tmp = load i16* %v
+ ret i16 %tmp
+}
+
+define i16 @f2(i16* %v) {
+entry:
+; CHECK: f2:
+; CHECK: ldrh.w r0, [r0, #+2046]
+ %tmp2 = getelementptr i16* %v, i16 1023
+ %tmp = load i16* %tmp2
+ ret i16 %tmp
+}
+
+define i16 @f3(i16* %v) {
+entry:
+; CHECK: f3:
+; CHECK: mov.w r1, #4096
+; CHECK: ldrh r0, [r0, r1]
+ %tmp2 = getelementptr i16* %v, i16 2048
+ %tmp = load i16* %tmp2
+ ret i16 %tmp
+}
+
+define i16 @f4(i32 %base) {
+entry:
+; CHECK: f4:
+; CHECK: ldrh r0, [r0, #-128]
+ %tmp1 = sub i32 %base, 128
+ %tmp2 = inttoptr i32 %tmp1 to i16*
+ %tmp3 = load i16* %tmp2
+ ret i16 %tmp3
+}
+
+define i16 @f5(i32 %base, i32 %offset) {
+entry:
+; CHECK: f5:
+; CHECK: ldrh r0, [r0, r1]
+ %tmp1 = add i32 %base, %offset
+ %tmp2 = inttoptr i32 %tmp1 to i16*
+ %tmp3 = load i16* %tmp2
+ ret i16 %tmp3
+}
+
+define i16 @f6(i32 %base, i32 %offset) {
+entry:
+; CHECK: f6:
+; CHECK: ldrh.w r0, [r0, r1, lsl #2]
+ %tmp1 = shl i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i16*
+ %tmp4 = load i16* %tmp3
+ ret i16 %tmp4
+}
+
+define i16 @f7(i32 %base, i32 %offset) {
+entry:
+; CHECK: f7:
+; CHECK: lsrs r1, r1, #2
+; CHECK: ldrh r0, [r0, r1]
+ %tmp1 = lshr i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i16*
+ %tmp4 = load i16* %tmp3
+ ret i16 %tmp4
+}
diff --git a/test/CodeGen/Thumb2/thumb2-lsl.ll b/test/CodeGen/Thumb2/thumb2-lsl.ll
new file mode 100644
index 0000000..6b0818a
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-lsl.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: lsls r0, r0, #5
+ %tmp = shl i32 %a, 5
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-lsl2.ll b/test/CodeGen/Thumb2/thumb2-lsl2.ll
new file mode 100644
index 0000000..f283eef
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-lsl2.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK: f1:
+; CHECK: lsls r0, r1
+ %tmp = shl i32 %a, %b
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-lsr.ll b/test/CodeGen/Thumb2/thumb2-lsr.ll
new file mode 100644
index 0000000..7cbee54
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-lsr.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: lsrs r0, r0, #13
+ %tmp = lshr i32 %a, 13
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-lsr2.ll b/test/CodeGen/Thumb2/thumb2-lsr2.ll
new file mode 100644
index 0000000..87800f9
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-lsr2.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK: f1:
+; CHECK: lsrs r0, r1
+ %tmp = lshr i32 %a, %b
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-lsr3.ll b/test/CodeGen/Thumb2/thumb2-lsr3.ll
new file mode 100644
index 0000000..5cfd3f5
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-lsr3.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2
+
+define i1 @test1(i64 %poscnt, i32 %work) {
+entry:
+; CHECK: rrx r0, r0
+; CHECK: lsrs.w r1, r1, #1
+ %0 = lshr i64 %poscnt, 1
+ %1 = icmp eq i64 %0, 0
+ ret i1 %1
+}
+
+define i1 @test2(i64 %poscnt, i32 %work) {
+entry:
+; CHECK: rrx r0, r0
+; CHECK: asrs.w r1, r1, #1
+ %0 = ashr i64 %poscnt, 1
+ %1 = icmp eq i64 %0, 0
+ ret i1 %1
+}
diff --git a/test/CodeGen/Thumb2/thumb2-mla.ll b/test/CodeGen/Thumb2/thumb2-mla.ll
new file mode 100644
index 0000000..c4cc749
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-mla.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+ %tmp1 = mul i32 %a, %b
+ %tmp2 = add i32 %c, %tmp1
+ ret i32 %tmp2
+}
+; CHECK: f1:
+; CHECK: mla r0, r0, r1, r2
+
+define i32 @f2(i32 %a, i32 %b, i32 %c) {
+ %tmp1 = mul i32 %a, %b
+ %tmp2 = add i32 %tmp1, %c
+ ret i32 %tmp2
+}
+; CHECK: f2:
+; CHECK: mla r0, r0, r1, r2
diff --git a/test/CodeGen/Thumb2/thumb2-mls.ll b/test/CodeGen/Thumb2/thumb2-mls.ll
new file mode 100644
index 0000000..fc9e6ba
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-mls.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+ %tmp1 = mul i32 %a, %b
+ %tmp2 = sub i32 %c, %tmp1
+ ret i32 %tmp2
+}
+; CHECK: f1:
+; CHECK: mls r0, r0, r1, r2
+
+; sub doesn't commute, so no mls for this one
+define i32 @f2(i32 %a, i32 %b, i32 %c) {
+ %tmp1 = mul i32 %a, %b
+ %tmp2 = sub i32 %tmp1, %c
+ ret i32 %tmp2
+}
+; CHECK: f2:
+; CHECK: muls r0, r1
+
diff --git a/test/CodeGen/Thumb2/thumb2-mov.ll b/test/CodeGen/Thumb2/thumb2-mov.ll
new file mode 100644
index 0000000..1dc3614
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-mov.ll
@@ -0,0 +1,266 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+; Test #<const>
+
+; var 2.1 - 0x00ab00ab
+define i32 @t2_const_var2_1_ok_1(i32 %lhs) {
+;CHECK: t2_const_var2_1_ok_1:
+;CHECK: add.w r0, r0, #11206827
+ %ret = add i32 %lhs, 11206827 ; 0x00ab00ab
+ ret i32 %ret
+}
+
+define i32 @t2_const_var2_1_ok_2(i32 %lhs) {
+;CHECK: t2_const_var2_1_ok_2:
+;CHECK: add.w r0, r0, #11206656
+;CHECK: adds r0, #187
+ %ret = add i32 %lhs, 11206843 ; 0x00ab00bb
+ ret i32 %ret
+}
+
+define i32 @t2_const_var2_1_ok_3(i32 %lhs) {
+;CHECK: t2_const_var2_1_ok_3:
+;CHECK: add.w r0, r0, #11206827
+;CHECK: add.w r0, r0, #16777216
+ %ret = add i32 %lhs, 27984043 ; 0x01ab00ab
+ ret i32 %ret
+}
+
+define i32 @t2_const_var2_1_ok_4(i32 %lhs) {
+;CHECK: t2_const_var2_1_ok_4:
+;CHECK: add.w r0, r0, #16777472
+;CHECK: add.w r0, r0, #11206827
+ %ret = add i32 %lhs, 27984299 ; 0x01ab01ab
+ ret i32 %ret
+}
+
+define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
+;CHECK: t2_const_var2_1_fail_1:
+;CHECK: movw r1, #43777
+;CHECK: movt r1, #427
+;CHECK: add r0, r1
+ %ret = add i32 %lhs, 28027649 ; 0x01abab01
+ ret i32 %ret
+}
+
+; var 2.2 - 0xab00ab00
+define i32 @t2_const_var2_2_ok_1(i32 %lhs) {
+;CHECK: t2_const_var2_2_ok_1:
+;CHECK: add.w r0, r0, #-1426019584
+ %ret = add i32 %lhs, 2868947712 ; 0xab00ab00
+ ret i32 %ret
+}
+
+define i32 @t2_const_var2_2_ok_2(i32 %lhs) {
+;CHECK: t2_const_var2_2_ok_2:
+;CHECK: add.w r0, r0, #-1426063360
+;CHECK: add.w r0, r0, #47616
+ %ret = add i32 %lhs, 2868951552 ; 0xab00ba00
+ ret i32 %ret
+}
+
+define i32 @t2_const_var2_2_ok_3(i32 %lhs) {
+;CHECK: t2_const_var2_2_ok_3:
+;CHECK: add.w r0, r0, #-1426019584
+;CHECK: adds r0, #16
+ %ret = add i32 %lhs, 2868947728 ; 0xab00ab10
+ ret i32 %ret
+}
+
+define i32 @t2_const_var2_2_ok_4(i32 %lhs) {
+;CHECK: t2_const_var2_2_ok_4:
+;CHECK: add.w r0, r0, #-1426019584
+;CHECK: add.w r0, r0, #1048592
+ %ret = add i32 %lhs, 2869996304 ; 0xab10ab10
+ ret i32 %ret
+}
+
+define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
+;CHECK: t2_const_var2_2_fail_1:
+;CHECK: movw r1, #43792
+;CHECK: movt r1, #4267
+;CHECK: add r0, r1
+ %ret = add i32 %lhs, 279685904 ; 0x10abab10
+ ret i32 %ret
+}
+
+; var 2.3 - 0xabababab
+define i32 @t2_const_var2_3_ok_1(i32 %lhs) {
+;CHECK: t2_const_var2_3_ok_1:
+;CHECK: add.w r0, r0, #-1414812757
+ %ret = add i32 %lhs, 2880154539 ; 0xabababab
+ ret i32 %ret
+}
+
+define i32 @t2_const_var2_3_fail_1(i32 %lhs) {
+;CHECK: t2_const_var2_3_fail_1:
+;CHECK: movw r1, #43962
+;CHECK: movt r1, #43947
+;CHECK: add r0, r1
+ %ret = add i32 %lhs, 2880154554 ; 0xabababba
+ ret i32 %ret
+}
+
+define i32 @t2_const_var2_3_fail_2(i32 %lhs) {
+;CHECK: t2_const_var2_3_fail_2:
+;CHECK: movw r1, #47787
+;CHECK: movt r1, #43947
+;CHECK: add r0, r1
+ %ret = add i32 %lhs, 2880158379 ; 0xababbaab
+ ret i32 %ret
+}
+
+define i32 @t2_const_var2_3_fail_3(i32 %lhs) {
+;CHECK: t2_const_var2_3_fail_3:
+;CHECK: movw r1, #43947
+;CHECK: movt r1, #43962
+;CHECK: add r0, r1
+ %ret = add i32 %lhs, 2881137579 ; 0xabbaabab
+ ret i32 %ret
+}
+
+define i32 @t2_const_var2_3_fail_4(i32 %lhs) {
+;CHECK: t2_const_var2_3_fail_4:
+;CHECK: movw r1, #43947
+;CHECK: movt r1, #47787
+;CHECK: add r0, r1
+ %ret = add i32 %lhs, 3131812779 ; 0xbaababab
+ ret i32 %ret
+}
+
+; var 3 - 0x0F000000
+define i32 @t2_const_var3_1_ok_1(i32 %lhs) {
+;CHECK: t2_const_var3_1_ok_1:
+;CHECK: add.w r0, r0, #251658240
+ %ret = add i32 %lhs, 251658240 ; 0x0F000000
+ ret i32 %ret
+}
+
+define i32 @t2_const_var3_2_ok_1(i32 %lhs) {
+;CHECK: t2_const_var3_2_ok_1:
+;CHECK: add.w r0, r0, #3948544
+ %ret = add i32 %lhs, 3948544 ; 0b00000000001111000100000000000000
+ ret i32 %ret
+}
+
+define i32 @t2_const_var3_2_ok_2(i32 %lhs) {
+;CHECK: t2_const_var3_2_ok_2:
+;CHECK: add.w r0, r0, #2097152
+;CHECK: add.w r0, r0, #1843200
+ %ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000
+ ret i32 %ret
+}
+
+define i32 @t2_const_var3_3_ok_1(i32 %lhs) {
+;CHECK: t2_const_var3_3_ok_1:
+;CHECK: add.w r0, r0, #258
+ %ret = add i32 %lhs, 258 ; 0b00000000000000000000000100000010
+ ret i32 %ret
+}
+
+define i32 @t2_const_var3_4_ok_1(i32 %lhs) {
+;CHECK: t2_const_var3_4_ok_1:
+;CHECK: add.w r0, r0, #-268435456
+ %ret = add i32 %lhs, 4026531840 ; 0xF0000000
+ ret i32 %ret
+}
+
+define i32 @t2MOVTi16_ok_1(i32 %a) {
+; CHECK: t2MOVTi16_ok_1:
+; CHECK: movt r0, #1234
+ %1 = and i32 %a, 65535
+ %2 = shl i32 1234, 16
+ %3 = or i32 %1, %2
+
+ ret i32 %3
+}
+
+define i32 @t2MOVTi16_test_1(i32 %a) {
+; CHECK: t2MOVTi16_test_1:
+; CHECK: movt r0, #1234
+ %1 = shl i32 255, 8
+ %2 = shl i32 1234, 8
+ %3 = or i32 %1, 255 ; This gives us 0xFFFF in %3
+ %4 = shl i32 %2, 8 ; This gives us (1234 << 16) in %4
+ %5 = and i32 %a, %3
+ %6 = or i32 %4, %5
+
+ ret i32 %6
+}
+
+define i32 @t2MOVTi16_test_2(i32 %a) {
+; CHECK: t2MOVTi16_test_2:
+; CHECK: movt r0, #1234
+ %1 = shl i32 255, 8
+ %2 = shl i32 1234, 8
+ %3 = or i32 %1, 255 ; This gives us 0xFFFF in %3
+ %4 = shl i32 %2, 6
+ %5 = and i32 %a, %3
+ %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
+ %7 = or i32 %5, %6
+
+ ret i32 %7
+}
+
+define i32 @t2MOVTi16_test_3(i32 %a) {
+; CHECK: t2MOVTi16_test_3:
+; CHECK: movt r0, #1234
+ %1 = shl i32 255, 8
+ %2 = shl i32 1234, 8
+ %3 = or i32 %1, 255 ; This gives us 0xFFFF in %3
+ %4 = shl i32 %2, 6
+ %5 = and i32 %a, %3
+ %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
+ %7 = lshr i32 %6, 6
+ %8 = shl i32 %7, 6
+ %9 = or i32 %5, %8
+
+ ret i32 %8
+}
+
+; 171 = 0x000000ab
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: movs r0, #171
+ %tmp = add i32 0, 171
+ ret i32 %tmp
+}
+
+; 1179666 = 0x00120012
+define i32 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: mov.w r0, #1179666
+ %tmp = add i32 0, 1179666
+ ret i32 %tmp
+}
+
+; 872428544 = 0x34003400
+define i32 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: mov.w r0, #872428544
+ %tmp = add i32 0, 872428544
+ ret i32 %tmp
+}
+
+; 1448498774 = 0x56565656
+define i32 @f4(i32 %a) {
+; CHECK: f4:
+; CHECK: mov.w r0, #1448498774
+ %tmp = add i32 0, 1448498774
+ ret i32 %tmp
+}
+
+; 66846720 = 0x03fc0000
+define i32 @f5(i32 %a) {
+; CHECK: f5:
+; CHECK: mov.w r0, #66846720
+ %tmp = add i32 0, 66846720
+ ret i32 %tmp
+}
+
+define i32 @f6(i32 %a) {
+;CHECK: f6
+;CHECK: movw r0, #65535
+ %tmp = add i32 0, 65535
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-mul.ll b/test/CodeGen/Thumb2/thumb2-mul.ll
new file mode 100644
index 0000000..b1515b5
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-mul.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK: f1:
+; CHECK: muls r0, r1
+ %tmp = mul i32 %a, %b
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-mulhi.ll b/test/CodeGen/Thumb2/thumb2-mulhi.ll
new file mode 100644
index 0000000..5d47770
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-mulhi.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep smmul | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep umull | count 1
+
+define i32 @smulhi(i32 %x, i32 %y) {
+ %tmp = sext i32 %x to i64 ; <i64> [#uses=1]
+ %tmp1 = sext i32 %y to i64 ; <i64> [#uses=1]
+ %tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
+ %tmp3 = lshr i64 %tmp2, 32 ; <i64> [#uses=1]
+ %tmp3.upgrd.1 = trunc i64 %tmp3 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp3.upgrd.1
+}
+
+define i32 @umulhi(i32 %x, i32 %y) {
+ %tmp = zext i32 %x to i64 ; <i64> [#uses=1]
+ %tmp1 = zext i32 %y to i64 ; <i64> [#uses=1]
+ %tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
+ %tmp3 = lshr i64 %tmp2, 32 ; <i64> [#uses=1]
+ %tmp3.upgrd.2 = trunc i64 %tmp3 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp3.upgrd.2
+}
diff --git a/test/CodeGen/Thumb2/thumb2-mvn.ll b/test/CodeGen/Thumb2/thumb2-mvn.ll
new file mode 100644
index 0000000..a8c8f83
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-mvn.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
+
+; 0x000000bb = 187
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: mvn r0, #187
+ %tmp = xor i32 4294967295, 187
+ ret i32 %tmp
+}
+
+; 0x00aa00aa = 11141290
+define i32 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: mvn r0, #11141290
+ %tmp = xor i32 4294967295, 11141290
+ ret i32 %tmp
+}
+
+; 0xcc00cc00 = 3422604288
+define i32 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: mvn r0, #-872363008
+ %tmp = xor i32 4294967295, 3422604288
+ ret i32 %tmp
+}
+
+; 0x00110000 = 1114112
+define i32 @f5(i32 %a) {
+; CHECK: f5:
+; CHECK: mvn r0, #1114112
+ %tmp = xor i32 4294967295, 1114112
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-mvn2.ll b/test/CodeGen/Thumb2/thumb2-mvn2.ll
new file mode 100644
index 0000000..375d0aa
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-mvn2.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: mvns r0, r0
+ %tmp = xor i32 4294967295, %a
+ ret i32 %tmp
+}
+
+define i32 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: mvns r0, r0
+ %tmp = xor i32 %a, 4294967295
+ ret i32 %tmp
+}
+
+define i32 @f5(i32 %a) {
+; CHECK: f5:
+; CHECK: mvn.w r0, r0, lsl #5
+ %tmp = shl i32 %a, 5
+ %tmp1 = xor i32 %tmp, 4294967295
+ ret i32 %tmp1
+}
+
+define i32 @f6(i32 %a) {
+; CHECK: f6:
+; CHECK: mvn.w r0, r0, lsr #6
+ %tmp = lshr i32 %a, 6
+ %tmp1 = xor i32 %tmp, 4294967295
+ ret i32 %tmp1
+}
+
+define i32 @f7(i32 %a) {
+; CHECK: f7:
+; CHECK: mvn.w r0, r0, asr #7
+ %tmp = ashr i32 %a, 7
+ %tmp1 = xor i32 %tmp, 4294967295
+ ret i32 %tmp1
+}
+
+define i32 @f8(i32 %a) {
+; CHECK: f8:
+; CHECK: mvn.w r0, r0, ror #8
+ %l8 = shl i32 %a, 24
+ %r8 = lshr i32 %a, 8
+ %tmp = or i32 %l8, %r8
+ %tmp1 = xor i32 %tmp, 4294967295
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/Thumb2/thumb2-neg.ll b/test/CodeGen/Thumb2/thumb2-neg.ll
new file mode 100644
index 0000000..6bf11ec
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-neg.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: rsbs r0, r0, #0
+ %tmp = sub i32 0, %a
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-orn.ll b/test/CodeGen/Thumb2/thumb2-orn.ll
new file mode 100644
index 0000000..97a3fd7
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-orn.ll
@@ -0,0 +1,72 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+
+define i32 @f1(i32 %a, i32 %b) {
+ %tmp = xor i32 %b, 4294967295
+ %tmp1 = or i32 %a, %tmp
+ ret i32 %tmp1
+}
+; CHECK: f1:
+; CHECK: orn r0, r0, r1
+
+define i32 @f2(i32 %a, i32 %b) {
+ %tmp = xor i32 %b, 4294967295
+ %tmp1 = or i32 %tmp, %a
+ ret i32 %tmp1
+}
+; CHECK: f2:
+; CHECK: orn r0, r0, r1
+
+define i32 @f3(i32 %a, i32 %b) {
+ %tmp = xor i32 4294967295, %b
+ %tmp1 = or i32 %a, %tmp
+ ret i32 %tmp1
+}
+; CHECK: f3:
+; CHECK: orn r0, r0, r1
+
+define i32 @f4(i32 %a, i32 %b) {
+ %tmp = xor i32 4294967295, %b
+ %tmp1 = or i32 %tmp, %a
+ ret i32 %tmp1
+}
+; CHECK: f4:
+; CHECK: orn r0, r0, r1
+
+define i32 @f5(i32 %a, i32 %b) {
+ %tmp = shl i32 %b, 5
+ %tmp1 = xor i32 4294967295, %tmp
+ %tmp2 = or i32 %a, %tmp1
+ ret i32 %tmp2
+}
+; CHECK: f5:
+; CHECK: orn r0, r0, r1, lsl #5
+
+define i32 @f6(i32 %a, i32 %b) {
+ %tmp = lshr i32 %b, 6
+ %tmp1 = xor i32 4294967295, %tmp
+ %tmp2 = or i32 %a, %tmp1
+ ret i32 %tmp2
+}
+; CHECK: f6:
+; CHECK: orn r0, r0, r1, lsr #6
+
+define i32 @f7(i32 %a, i32 %b) {
+ %tmp = ashr i32 %b, 7
+ %tmp1 = xor i32 4294967295, %tmp
+ %tmp2 = or i32 %a, %tmp1
+ ret i32 %tmp2
+}
+; CHECK: f7:
+; CHECK: orn r0, r0, r1, asr #7
+
+define i32 @f8(i32 %a, i32 %b) {
+ %l8 = shl i32 %a, 24
+ %r8 = lshr i32 %a, 8
+ %tmp = or i32 %l8, %r8
+ %tmp1 = xor i32 4294967295, %tmp
+ %tmp2 = or i32 %a, %tmp1
+ ret i32 %tmp2
+}
+; CHECK: f8:
+; CHECK: orn r0, r0, r0, ror #8
diff --git a/test/CodeGen/Thumb2/thumb2-orn2.ll b/test/CodeGen/Thumb2/thumb2-orn2.ll
new file mode 100644
index 0000000..34ab3a5
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-orn2.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+
+; 0x000000bb = 187
+define i32 @f1(i32 %a) {
+ %tmp1 = xor i32 4294967295, 187
+ %tmp2 = or i32 %a, %tmp1
+ ret i32 %tmp2
+}
+; CHECK: f1:
+; CHECK: orn r0, r0, #187
+
+; 0x00aa00aa = 11141290
+define i32 @f2(i32 %a) {
+ %tmp1 = xor i32 4294967295, 11141290
+ %tmp2 = or i32 %a, %tmp1
+ ret i32 %tmp2
+}
+; CHECK: f2:
+; CHECK: orn r0, r0, #11141290
+
+; 0xcc00cc00 = 3422604288
+define i32 @f3(i32 %a) {
+ %tmp1 = xor i32 4294967295, 3422604288
+ %tmp2 = or i32 %a, %tmp1
+ ret i32 %tmp2
+}
+; CHECK: f3:
+; CHECK: orn r0, r0, #-872363008
+
+; 0x00110000 = 1114112
+define i32 @f5(i32 %a) {
+ %tmp1 = xor i32 4294967295, 1114112
+ %tmp2 = or i32 %a, %tmp1
+ ret i32 %tmp2
+}
+; CHECK: f5:
+; CHECK: orn r0, r0, #1114112
diff --git a/test/CodeGen/Thumb2/thumb2-orr.ll b/test/CodeGen/Thumb2/thumb2-orr.ll
new file mode 100644
index 0000000..89ab7b1
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-orr.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK: f1:
+; CHECK: orrs r0, r1
+ %tmp2 = or i32 %a, %b
+ ret i32 %tmp2
+}
+
+define i32 @f5(i32 %a, i32 %b) {
+; CHECK: f5:
+; CHECK: orr.w r0, r0, r1, lsl #5
+ %tmp = shl i32 %b, 5
+ %tmp2 = or i32 %a, %tmp
+ ret i32 %tmp2
+}
+
+define i32 @f6(i32 %a, i32 %b) {
+; CHECK: f6:
+; CHECK: orr.w r0, r0, r1, lsr #6
+ %tmp = lshr i32 %b, 6
+ %tmp2 = or i32 %a, %tmp
+ ret i32 %tmp2
+}
+
+define i32 @f7(i32 %a, i32 %b) {
+; CHECK: f7:
+; CHECK: orr.w r0, r0, r1, asr #7
+ %tmp = ashr i32 %b, 7
+ %tmp2 = or i32 %a, %tmp
+ ret i32 %tmp2
+}
+
+define i32 @f8(i32 %a, i32 %b) {
+; CHECK: f8:
+; CHECK: orr.w r0, r0, r0, ror #8
+ %l8 = shl i32 %a, 24
+ %r8 = lshr i32 %a, 8
+ %tmp = or i32 %l8, %r8
+ %tmp2 = or i32 %a, %tmp
+ ret i32 %tmp2
+}
diff --git a/test/CodeGen/Thumb2/thumb2-orr2.ll b/test/CodeGen/Thumb2/thumb2-orr2.ll
new file mode 100644
index 0000000..8f7a3c2
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-orr2.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+
+; 0x000000bb = 187
+define i32 @f1(i32 %a) {
+ %tmp2 = or i32 %a, 187
+ ret i32 %tmp2
+}
+; CHECK: f1:
+; CHECK: orr r0, r0, #187
+
+; 0x00aa00aa = 11141290
+define i32 @f2(i32 %a) {
+ %tmp2 = or i32 %a, 11141290
+ ret i32 %tmp2
+}
+; CHECK: f2:
+; CHECK: orr r0, r0, #11141290
+
+; 0xcc00cc00 = 3422604288
+define i32 @f3(i32 %a) {
+ %tmp2 = or i32 %a, 3422604288
+ ret i32 %tmp2
+}
+; CHECK: f3:
+; CHECK: orr r0, r0, #-872363008
+
+; 0x44444444 = 1145324612
+define i32 @f4(i32 %a) {
+ %tmp2 = or i32 %a, 1145324612
+ ret i32 %tmp2
+}
+; CHECK: f4:
+; CHECK: orr r0, r0, #1145324612
+
+; 0x00110000 = 1114112
+define i32 @f5(i32 %a) {
+ %tmp2 = or i32 %a, 1114112
+ ret i32 %tmp2
+}
+; CHECK: f5:
+; CHECK: orr r0, r0, #1114112
diff --git a/test/CodeGen/Thumb2/thumb2-pack.ll b/test/CodeGen/Thumb2/thumb2-pack.ll
new file mode 100644
index 0000000..a982249
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-pack.ll
@@ -0,0 +1,73 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
+; RUN: grep pkhbt | count 5
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | \
+; RUN: grep pkhtb | count 4
+
+define i32 @test1(i32 %X, i32 %Y) {
+ %tmp1 = and i32 %X, 65535 ; <i32> [#uses=1]
+ %tmp4 = shl i32 %Y, 16 ; <i32> [#uses=1]
+ %tmp5 = or i32 %tmp4, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
+define i32 @test1a(i32 %X, i32 %Y) {
+ %tmp19 = and i32 %X, 65535 ; <i32> [#uses=1]
+ %tmp37 = shl i32 %Y, 16 ; <i32> [#uses=1]
+ %tmp5 = or i32 %tmp37, %tmp19 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
+define i32 @test2(i32 %X, i32 %Y) {
+ %tmp1 = and i32 %X, 65535 ; <i32> [#uses=1]
+ %tmp3 = shl i32 %Y, 12 ; <i32> [#uses=1]
+ %tmp4 = and i32 %tmp3, -65536 ; <i32> [#uses=1]
+ %tmp57 = or i32 %tmp4, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp57
+}
+
+define i32 @test3(i32 %X, i32 %Y) {
+ %tmp19 = and i32 %X, 65535 ; <i32> [#uses=1]
+ %tmp37 = shl i32 %Y, 18 ; <i32> [#uses=1]
+ %tmp5 = or i32 %tmp37, %tmp19 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
+define i32 @test4(i32 %X, i32 %Y) {
+ %tmp1 = and i32 %X, 65535 ; <i32> [#uses=1]
+ %tmp3 = and i32 %Y, -65536 ; <i32> [#uses=1]
+ %tmp46 = or i32 %tmp3, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp46
+}
+
+define i32 @test5(i32 %X, i32 %Y) {
+ %tmp17 = and i32 %X, -65536 ; <i32> [#uses=1]
+ %tmp2 = bitcast i32 %Y to i32 ; <i32> [#uses=1]
+ %tmp4 = lshr i32 %tmp2, 16 ; <i32> [#uses=2]
+ %tmp5 = or i32 %tmp4, %tmp17 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
+define i32 @test5a(i32 %X, i32 %Y) {
+ %tmp110 = and i32 %X, -65536 ; <i32> [#uses=1]
+ %tmp37 = lshr i32 %Y, 16 ; <i32> [#uses=1]
+ %tmp39 = bitcast i32 %tmp37 to i32 ; <i32> [#uses=1]
+ %tmp5 = or i32 %tmp39, %tmp110 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
+define i32 @test6(i32 %X, i32 %Y) {
+ %tmp1 = and i32 %X, -65536 ; <i32> [#uses=1]
+ %tmp37 = lshr i32 %Y, 12 ; <i32> [#uses=1]
+ %tmp38 = bitcast i32 %tmp37 to i32 ; <i32> [#uses=1]
+ %tmp4 = and i32 %tmp38, 65535 ; <i32> [#uses=1]
+ %tmp59 = or i32 %tmp4, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp59
+}
+
+define i32 @test7(i32 %X, i32 %Y) {
+ %tmp1 = and i32 %X, -65536 ; <i32> [#uses=1]
+ %tmp3 = ashr i32 %Y, 18 ; <i32> [#uses=1]
+ %tmp4 = and i32 %tmp3, 65535 ; <i32> [#uses=1]
+ %tmp57 = or i32 %tmp4, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp57
+}
diff --git a/test/CodeGen/Thumb2/thumb2-rev.ll b/test/CodeGen/Thumb2/thumb2-rev.ll
new file mode 100644
index 0000000..27b1672
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-rev.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | FileCheck %s
+
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: rev r0, r0
+ %tmp = tail call i32 @llvm.bswap.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.bswap.i32(i32) nounwind readnone
+
+define i32 @f2(i32 %X) {
+; CHECK: f2:
+; CHECK: revsh r0, r0
+ %tmp1 = lshr i32 %X, 8
+ %tmp1.upgrd.1 = trunc i32 %tmp1 to i16
+ %tmp3 = trunc i32 %X to i16
+ %tmp2 = and i16 %tmp1.upgrd.1, 255
+ %tmp4 = shl i16 %tmp3, 8
+ %tmp5 = or i16 %tmp2, %tmp4
+ %tmp5.upgrd.2 = sext i16 %tmp5 to i32
+ ret i32 %tmp5.upgrd.2
+}
diff --git a/test/CodeGen/Thumb2/thumb2-rev16.ll b/test/CodeGen/Thumb2/thumb2-rev16.ll
new file mode 100644
index 0000000..39b6ac3
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-rev16.ll
@@ -0,0 +1,32 @@
+; XFAIL: *
+; fixme rev16 pattern is not matching
+
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rev16\\W*r\[0-9\]*,\\W*r\[0-9\]*} | count 1
+
+; 0xff00ff00 = 4278255360
+; 0x00ff00ff = 16711935
+define i32 @f1(i32 %a) {
+ %l8 = shl i32 %a, 8
+ %r8 = lshr i32 %a, 8
+ %mask_l8 = and i32 %l8, 4278255360
+ %mask_r8 = and i32 %r8, 16711935
+ %tmp = or i32 %mask_l8, %mask_r8
+ ret i32 %tmp
+}
+
+; 0xff000000 = 4278190080
+; 0x00ff0000 = 16711680
+; 0x0000ff00 = 65280
+; 0x000000ff = 255
+define i32 @f2(i32 %a) {
+ %l8 = shl i32 %a, 8
+ %r8 = lshr i32 %a, 8
+ %masklo_l8 = and i32 %l8, 65280
+ %maskhi_l8 = and i32 %l8, 4278190080
+ %masklo_r8 = and i32 %r8, 255
+ %maskhi_r8 = and i32 %r8, 16711680
+ %tmp1 = or i32 %masklo_l8, %masklo_r8
+ %tmp2 = or i32 %maskhi_l8, %maskhi_r8
+ %tmp = or i32 %tmp1, %tmp2
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-ror.ll b/test/CodeGen/Thumb2/thumb2-ror.ll
new file mode 100644
index 0000000..0200116
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-ror.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+
+define i32 @f1(i32 %a) {
+ %l8 = shl i32 %a, 10
+ %r8 = lshr i32 %a, 22
+ %tmp = or i32 %l8, %r8
+ ret i32 %tmp
+}
+; CHECK: f1:
+; CHECK: ror.w r0, r0, #22
diff --git a/test/CodeGen/Thumb2/thumb2-ror2.ll b/test/CodeGen/Thumb2/thumb2-ror2.ll
new file mode 100644
index 0000000..ffd1dd7
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-ror2.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK: f1:
+; CHECK: rors r0, r1
+ %db = sub i32 32, %b
+ %l8 = shl i32 %a, %b
+ %r8 = lshr i32 %a, %db
+ %tmp = or i32 %l8, %r8
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-rsb.ll b/test/CodeGen/Thumb2/thumb2-rsb.ll
new file mode 100644
index 0000000..15185be
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-rsb.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b) {
+ %tmp = shl i32 %b, 5
+ %tmp1 = sub i32 %tmp, %a
+ ret i32 %tmp1
+}
+; CHECK: f1:
+; CHECK: rsb r0, r0, r1, lsl #5
+
+define i32 @f2(i32 %a, i32 %b) {
+ %tmp = lshr i32 %b, 6
+ %tmp1 = sub i32 %tmp, %a
+ ret i32 %tmp1
+}
+; CHECK: f2:
+; CHECK: rsb r0, r0, r1, lsr #6
+
+define i32 @f3(i32 %a, i32 %b) {
+ %tmp = ashr i32 %b, 7
+ %tmp1 = sub i32 %tmp, %a
+ ret i32 %tmp1
+}
+; CHECK: f3:
+; CHECK: rsb r0, r0, r1, asr #7
+
+define i32 @f4(i32 %a, i32 %b) {
+ %l8 = shl i32 %a, 24
+ %r8 = lshr i32 %a, 8
+ %tmp = or i32 %l8, %r8
+ %tmp1 = sub i32 %tmp, %a
+ ret i32 %tmp1
+}
+; CHECK: f4:
+; CHECK: rsb r0, r0, r0, ror #8
diff --git a/test/CodeGen/Thumb2/thumb2-rsb2.ll b/test/CodeGen/Thumb2/thumb2-rsb2.ll
new file mode 100644
index 0000000..61fb619
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-rsb2.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+; 171 = 0x000000ab
+define i32 @f1(i32 %a) {
+ %tmp = sub i32 171, %a
+ ret i32 %tmp
+}
+; CHECK: f1:
+; CHECK: rsb.w r0, r0, #171
+
+; 1179666 = 0x00120012
+define i32 @f2(i32 %a) {
+ %tmp = sub i32 1179666, %a
+ ret i32 %tmp
+}
+; CHECK: f2:
+; CHECK: rsb.w r0, r0, #1179666
+
+; 872428544 = 0x34003400
+define i32 @f3(i32 %a) {
+ %tmp = sub i32 872428544, %a
+ ret i32 %tmp
+}
+; CHECK: f3:
+; CHECK: rsb.w r0, r0, #872428544
+
+; 1448498774 = 0x56565656
+define i32 @f4(i32 %a) {
+ %tmp = sub i32 1448498774, %a
+ ret i32 %tmp
+}
+; CHECK: f4:
+; CHECK: rsb.w r0, r0, #1448498774
+
+; 66846720 = 0x03fc0000
+define i32 @f5(i32 %a) {
+ %tmp = sub i32 66846720, %a
+ ret i32 %tmp
+}
+; CHECK: f5:
+; CHECK: rsb.w r0, r0, #66846720
diff --git a/test/CodeGen/Thumb2/thumb2-sbc.ll b/test/CodeGen/Thumb2/thumb2-sbc.ll
new file mode 100644
index 0000000..ad96291
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-sbc.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i64 @f1(i64 %a, i64 %b) {
+; CHECK: f1:
+; CHECK: subs r0, r0, r2
+ %tmp = sub i64 %a, %b
+ ret i64 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-select.ll b/test/CodeGen/Thumb2/thumb2-select.ll
new file mode 100644
index 0000000..2dcf8aa
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-select.ll
@@ -0,0 +1,98 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a.s) {
+entry:
+; CHECK: f1:
+; CHECK: it eq
+; CHECK: moveq
+
+ %tmp = icmp eq i32 %a.s, 4
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f2(i32 %a.s) {
+entry:
+; CHECK: f2:
+; CHECK: it gt
+; CHECK: movgt
+ %tmp = icmp sgt i32 %a.s, 4
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f3(i32 %a.s, i32 %b.s) {
+entry:
+; CHECK: f3:
+; CHECK: it lt
+; CHECK: movlt
+ %tmp = icmp slt i32 %a.s, %b.s
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f4(i32 %a.s, i32 %b.s) {
+entry:
+; CHECK: f4:
+; CHECK: it le
+; CHECK: movle
+
+ %tmp = icmp sle i32 %a.s, %b.s
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f5(i32 %a.u, i32 %b.u) {
+entry:
+; CHECK: f5:
+; CHECK: it ls
+; CHECK: movls
+ %tmp = icmp ule i32 %a.u, %b.u
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f6(i32 %a.u, i32 %b.u) {
+entry:
+; CHECK: f6:
+; CHECK: it hi
+; CHECK: movhi
+ %tmp = icmp ugt i32 %a.u, %b.u
+ %tmp1.s = select i1 %tmp, i32 2, i32 3
+ ret i32 %tmp1.s
+}
+
+define i32 @f7(i32 %a, i32 %b, i32 %c) {
+entry:
+; CHECK: f7:
+; CHECK: it hi
+; CHECK: lsrhi.w
+ %tmp1 = icmp ugt i32 %a, %b
+ %tmp2 = udiv i32 %c, 3
+ %tmp3 = select i1 %tmp1, i32 %tmp2, i32 3
+ ret i32 %tmp3
+}
+
+define i32 @f8(i32 %a, i32 %b, i32 %c) {
+entry:
+; CHECK: f8:
+; CHECK: it lo
+; CHECK: lsllo.w
+ %tmp1 = icmp ult i32 %a, %b
+ %tmp2 = mul i32 %c, 4
+ %tmp3 = select i1 %tmp1, i32 %tmp2, i32 3
+ ret i32 %tmp3
+}
+
+define i32 @f9(i32 %a, i32 %b, i32 %c) {
+entry:
+; CHECK: f9:
+; CHECK: it ge
+; CHECK: rorge.w
+ %tmp1 = icmp sge i32 %a, %b
+ %tmp2 = shl i32 %c, 10
+ %tmp3 = lshr i32 %c, 22
+ %tmp4 = or i32 %tmp2, %tmp3
+ %tmp5 = select i1 %tmp1, i32 %tmp4, i32 3
+ ret i32 %tmp5
+}
diff --git a/test/CodeGen/Thumb2/thumb2-select_xform.ll b/test/CodeGen/Thumb2/thumb2-select_xform.ll
new file mode 100644
index 0000000..7fc2e2a
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-select_xform.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
+; CHECK: t1
+; CHECK: sub.w r0, r1, #-2147483648
+; CHECK: cmp r2, #10
+; CHECK: sub.w r0, r0, #1
+; CHECK: it gt
+; CHECK: movgt r0, r1
+ %tmp1 = icmp sgt i32 %c, 10
+ %tmp2 = select i1 %tmp1, i32 0, i32 2147483647
+ %tmp3 = add i32 %tmp2, %b
+ ret i32 %tmp3
+}
+
+define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind {
+; CHECK: t2
+; CHECK: add.w r0, r1, #-2147483648
+; CHECK: cmp r2, #10
+; CHECK: it gt
+; CHECK: movgt r0, r1
+
+ %tmp1 = icmp sgt i32 %c, 10
+ %tmp2 = select i1 %tmp1, i32 0, i32 2147483648
+ %tmp3 = add i32 %tmp2, %b
+ ret i32 %tmp3
+}
+
+define i32 @t3(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
+; CHECK: t3
+; CHECK: sub.w r0, r1, #10
+; CHECK: cmp r2, #10
+; CHECK: it gt
+; CHECK: movgt r0, r1
+ %tmp1 = icmp sgt i32 %c, 10
+ %tmp2 = select i1 %tmp1, i32 0, i32 10
+ %tmp3 = sub i32 %b, %tmp2
+ ret i32 %tmp3
+}
diff --git a/test/CodeGen/Thumb2/thumb2-shifter.ll b/test/CodeGen/Thumb2/thumb2-shifter.ll
new file mode 100644
index 0000000..b106ced
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-shifter.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @t2ADDrs_lsl(i32 %X, i32 %Y) {
+; CHECK: t2ADDrs_lsl
+; CHECK: add.w r0, r0, r1, lsl #16
+ %A = shl i32 %Y, 16
+ %B = add i32 %X, %A
+ ret i32 %B
+}
+
+define i32 @t2ADDrs_lsr(i32 %X, i32 %Y) {
+; CHECK: t2ADDrs_lsr
+; CHECK: add.w r0, r0, r1, lsr #16
+ %A = lshr i32 %Y, 16
+ %B = add i32 %X, %A
+ ret i32 %B
+}
+
+define i32 @t2ADDrs_asr(i32 %X, i32 %Y) {
+; CHECK: t2ADDrs_asr
+; CHECK: add.w r0, r0, r1, asr #16
+ %A = ashr i32 %Y, 16
+ %B = add i32 %X, %A
+ ret i32 %B
+}
+
+; i32 ror(n) = (x >> n) | (x << (32 - n))
+define i32 @t2ADDrs_ror(i32 %X, i32 %Y) {
+; CHECK: t2ADDrs_ror
+; CHECK: add.w r0, r0, r1, ror #16
+ %A = lshr i32 %Y, 16
+ %B = shl i32 %Y, 16
+ %C = or i32 %B, %A
+ %R = add i32 %X, %C
+ ret i32 %R
+}
+
+define i32 @t2ADDrs_noRegShift(i32 %X, i32 %Y, i8 %sh) {
+; CHECK: t2ADDrs_noRegShift
+; CHECK: uxtb r2, r2
+; CHECK: lsls r1, r2
+; CHECK: add r0, r1
+ %shift.upgrd.1 = zext i8 %sh to i32
+ %A = shl i32 %Y, %shift.upgrd.1
+ %B = add i32 %X, %A
+ ret i32 %B
+}
+
diff --git a/test/CodeGen/Thumb2/thumb2-smla.ll b/test/CodeGen/Thumb2/thumb2-smla.ll
new file mode 100644
index 0000000..092ec27
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-smla.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f3(i32 %a, i16 %x, i32 %y) {
+; CHECK: f3
+; CHECK: smlabt r0, r1, r2, r0
+ %tmp = sext i16 %x to i32 ; <i32> [#uses=1]
+ %tmp2 = ashr i32 %y, 16 ; <i32> [#uses=1]
+ %tmp3 = mul i32 %tmp2, %tmp ; <i32> [#uses=1]
+ %tmp5 = add i32 %tmp3, %a ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
diff --git a/test/CodeGen/Thumb2/thumb2-smul.ll b/test/CodeGen/Thumb2/thumb2-smul.ll
new file mode 100644
index 0000000..16ea85d
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-smul.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+@x = weak global i16 0 ; <i16*> [#uses=1]
+@y = weak global i16 0 ; <i16*> [#uses=0]
+
+define i32 @f1(i32 %y) {
+; CHECK: f1
+; CHECK: smulbt r0, r1, r0
+ %tmp = load i16* @x ; <i16> [#uses=1]
+ %tmp1 = add i16 %tmp, 2 ; <i16> [#uses=1]
+ %tmp2 = sext i16 %tmp1 to i32 ; <i32> [#uses=1]
+ %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1]
+ %tmp4 = mul i32 %tmp2, %tmp3 ; <i32> [#uses=1]
+ ret i32 %tmp4
+}
+
+define i32 @f2(i32 %x, i32 %y) {
+; CHECK: f2
+; CHECK: smultt r0, r1, r0
+ %tmp1 = ashr i32 %x, 16 ; <i32> [#uses=1]
+ %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1]
+ %tmp4 = mul i32 %tmp3, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp4
+}
diff --git a/test/CodeGen/Thumb2/thumb2-spill-q.ll b/test/CodeGen/Thumb2/thumb2-spill-q.ll
new file mode 100644
index 0000000..7935163
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-spill-q.ll
@@ -0,0 +1,58 @@
+; RUN: llc < %s -mtriple=thumbv7-elf -mattr=+neon | FileCheck %s
+; PR4789
+
+%bar = type { float, float, float }
+%baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 }
+%foo = type { <4 x float> }
+%quux = type { i32 (...)**, %baz*, i32 }
+%quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo }
+
+declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly
+
+define arm_apcscc void @aaa(%quuz* %this, i8* %block) {
+; CHECK: aaa:
+; CHECK: bic r4, r4, #15
+; CHECK: vst1.64 {{.*}}[r{{.*}}, :128]
+; CHECK: vld1.64 {{.*}}[r{{.*}}, :128]
+entry:
+ %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1]
+ store float 6.300000e+01, float* undef, align 4
+ %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1]
+ store float 0.000000e+00, float* undef, align 4
+ %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef) nounwind ; <<4 x float>> [#uses=1]
+ %val173 = load <4 x float>* undef ; <<4 x float>> [#uses=1]
+ br label %bb4
+
+bb4: ; preds = %bb193, %entry
+ %besterror.0.2264 = phi <4 x float> [ undef, %entry ], [ %besterror.0.0, %bb193 ] ; <<4 x float>> [#uses=2]
+ %part0.0.0261 = phi <4 x float> [ zeroinitializer, %entry ], [ %23, %bb193 ] ; <<4 x float>> [#uses=2]
+ %3 = fmul <4 x float> zeroinitializer, %0 ; <<4 x float>> [#uses=2]
+ %4 = fadd <4 x float> %3, %part0.0.0261 ; <<4 x float>> [#uses=1]
+ %5 = shufflevector <4 x float> %3, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
+ %6 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>> [#uses=1]
+ %7 = fmul <4 x float> %1, undef ; <<4 x float>> [#uses=1]
+ %8 = fadd <4 x float> %7, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01> ; <<4 x float>> [#uses=1]
+ %9 = fptosi <4 x float> %8 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %10 = sitofp <4 x i32> %9 to <4 x float> ; <<4 x float>> [#uses=1]
+ %11 = fmul <4 x float> %10, %2 ; <<4 x float>> [#uses=1]
+ %12 = fmul <4 x float> undef, %6 ; <<4 x float>> [#uses=1]
+ %13 = fmul <4 x float> %11, %4 ; <<4 x float>> [#uses=1]
+ %14 = fsub <4 x float> %12, %13 ; <<4 x float>> [#uses=1]
+ %15 = fsub <4 x float> %14, undef ; <<4 x float>> [#uses=1]
+ %16 = fmul <4 x float> %15, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00> ; <<4 x float>> [#uses=1]
+ %17 = fadd <4 x float> %16, undef ; <<4 x float>> [#uses=1]
+ %18 = fmul <4 x float> %17, %val173 ; <<4 x float>> [#uses=1]
+ %19 = shufflevector <4 x float> %18, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
+ %20 = shufflevector <2 x float> %19, <2 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %21 = fadd <4 x float> zeroinitializer, %20 ; <<4 x float>> [#uses=2]
+ %22 = fcmp ogt <4 x float> %besterror.0.2264, %21 ; <<4 x i1>> [#uses=0]
+ br i1 undef, label %bb193, label %bb186
+
+bb186: ; preds = %bb4
+ br label %bb193
+
+bb193: ; preds = %bb186, %bb4
+ %besterror.0.0 = phi <4 x float> [ %21, %bb186 ], [ %besterror.0.2264, %bb4 ] ; <<4 x float>> [#uses=1]
+ %23 = fadd <4 x float> %part0.0.0261, zeroinitializer ; <<4 x float>> [#uses=1]
+ br label %bb4
+}
diff --git a/test/CodeGen/Thumb2/thumb2-str.ll b/test/CodeGen/Thumb2/thumb2-str.ll
new file mode 100644
index 0000000..3eeec8c
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-str.ll
@@ -0,0 +1,76 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32* %v) {
+; CHECK: f1:
+; CHECK: str r0, [r1]
+ store i32 %a, i32* %v
+ ret i32 %a
+}
+
+define i32 @f2(i32 %a, i32* %v) {
+; CHECK: f2:
+; CHECK: str.w r0, [r1, #+4092]
+ %tmp2 = getelementptr i32* %v, i32 1023
+ store i32 %a, i32* %tmp2
+ ret i32 %a
+}
+
+define i32 @f2a(i32 %a, i32* %v) {
+; CHECK: f2a:
+; CHECK: str r0, [r1, #-128]
+ %tmp2 = getelementptr i32* %v, i32 -32
+ store i32 %a, i32* %tmp2
+ ret i32 %a
+}
+
+define i32 @f3(i32 %a, i32* %v) {
+; CHECK: f3:
+; CHECK: mov.w r2, #4096
+; CHECK: str r0, [r1, r2]
+ %tmp2 = getelementptr i32* %v, i32 1024
+ store i32 %a, i32* %tmp2
+ ret i32 %a
+}
+
+define i32 @f4(i32 %a, i32 %base) {
+entry:
+; CHECK: f4:
+; CHECK: str r0, [r1, #-128]
+ %tmp1 = sub i32 %base, 128
+ %tmp2 = inttoptr i32 %tmp1 to i32*
+ store i32 %a, i32* %tmp2
+ ret i32 %a
+}
+
+define i32 @f5(i32 %a, i32 %base, i32 %offset) {
+entry:
+; CHECK: f5:
+; CHECK: str r0, [r1, r2]
+ %tmp1 = add i32 %base, %offset
+ %tmp2 = inttoptr i32 %tmp1 to i32*
+ store i32 %a, i32* %tmp2
+ ret i32 %a
+}
+
+define i32 @f6(i32 %a, i32 %base, i32 %offset) {
+entry:
+; CHECK: f6:
+; CHECK: str.w r0, [r1, r2, lsl #2]
+ %tmp1 = shl i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i32*
+ store i32 %a, i32* %tmp3
+ ret i32 %a
+}
+
+define i32 @f7(i32 %a, i32 %base, i32 %offset) {
+entry:
+; CHECK: f7:
+; CHECK: lsrs r2, r2, #2
+; CHECK: str r0, [r1, r2]
+ %tmp1 = lshr i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i32*
+ store i32 %a, i32* %tmp3
+ ret i32 %a
+}
diff --git a/test/CodeGen/Thumb2/thumb2-str_post.ll b/test/CodeGen/Thumb2/thumb2-str_post.ll
new file mode 100644
index 0000000..bbfb447
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-str_post.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i16 @test1(i32* %X, i16* %A) {
+; CHECK: test1:
+; CHECK: strh {{.*}}[{{.*}}], #-4
+ %Y = load i32* %X ; <i32> [#uses=1]
+ %tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1]
+ store i16 %tmp1, i16* %A
+ %tmp2 = ptrtoint i16* %A to i16 ; <i16> [#uses=1]
+ %tmp3 = sub i16 %tmp2, 4 ; <i16> [#uses=1]
+ ret i16 %tmp3
+}
+
+define i32 @test2(i32* %X, i32* %A) {
+; CHECK: test2:
+; CHECK: str {{.*}}[{{.*}}],
+ %Y = load i32* %X ; <i32> [#uses=1]
+ store i32 %Y, i32* %A
+ %tmp1 = ptrtoint i32* %A to i32 ; <i32> [#uses=1]
+ %tmp2 = sub i32 %tmp1, 4 ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
diff --git a/test/CodeGen/Thumb2/thumb2-str_pre.ll b/test/CodeGen/Thumb2/thumb2-str_pre.ll
new file mode 100644
index 0000000..9af960b
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-str_pre.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define void @test1(i32* %X, i32* %A, i32** %dest) {
+; CHECK: test1
+; CHECK: str r1, [r0, #+16]!
+ %B = load i32* %A ; <i32> [#uses=1]
+ %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2]
+ store i32 %B, i32* %Y
+ store i32* %Y, i32** %dest
+ ret void
+}
+
+define i16* @test2(i16* %X, i32* %A) {
+; CHECK: test2
+; CHECK: strh r1, [r0, #+8]!
+ %B = load i32* %A ; <i32> [#uses=1]
+ %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2]
+ %tmp = trunc i32 %B to i16 ; <i16> [#uses=1]
+ store i16 %tmp, i16* %Y
+ ret i16* %Y
+}
diff --git a/test/CodeGen/Thumb2/thumb2-strb.ll b/test/CodeGen/Thumb2/thumb2-strb.ll
new file mode 100644
index 0000000..1ebb938
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-strb.ll
@@ -0,0 +1,76 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i8 @f1(i8 %a, i8* %v) {
+; CHECK: f1:
+; CHECK: strb r0, [r1]
+ store i8 %a, i8* %v
+ ret i8 %a
+}
+
+define i8 @f2(i8 %a, i8* %v) {
+; CHECK: f2:
+; CHECK: strb.w r0, [r1, #+4092]
+ %tmp2 = getelementptr i8* %v, i32 4092
+ store i8 %a, i8* %tmp2
+ ret i8 %a
+}
+
+define i8 @f2a(i8 %a, i8* %v) {
+; CHECK: f2a:
+; CHECK: strb r0, [r1, #-128]
+ %tmp2 = getelementptr i8* %v, i32 -128
+ store i8 %a, i8* %tmp2
+ ret i8 %a
+}
+
+define i8 @f3(i8 %a, i8* %v) {
+; CHECK: f3:
+; CHECK: mov.w r2, #4096
+; CHECK: strb r0, [r1, r2]
+ %tmp2 = getelementptr i8* %v, i32 4096
+ store i8 %a, i8* %tmp2
+ ret i8 %a
+}
+
+define i8 @f4(i8 %a, i32 %base) {
+entry:
+; CHECK: f4:
+; CHECK: strb r0, [r1, #-128]
+ %tmp1 = sub i32 %base, 128
+ %tmp2 = inttoptr i32 %tmp1 to i8*
+ store i8 %a, i8* %tmp2
+ ret i8 %a
+}
+
+define i8 @f5(i8 %a, i32 %base, i32 %offset) {
+entry:
+; CHECK: f5:
+; CHECK: strb r0, [r1, r2]
+ %tmp1 = add i32 %base, %offset
+ %tmp2 = inttoptr i32 %tmp1 to i8*
+ store i8 %a, i8* %tmp2
+ ret i8 %a
+}
+
+define i8 @f6(i8 %a, i32 %base, i32 %offset) {
+entry:
+; CHECK: f6:
+; CHECK: strb.w r0, [r1, r2, lsl #2]
+ %tmp1 = shl i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i8*
+ store i8 %a, i8* %tmp3
+ ret i8 %a
+}
+
+define i8 @f7(i8 %a, i32 %base, i32 %offset) {
+entry:
+; CHECK: f7:
+; CHECK: lsrs r2, r2, #2
+; CHECK: strb r0, [r1, r2]
+ %tmp1 = lshr i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i8*
+ store i8 %a, i8* %tmp3
+ ret i8 %a
+}
diff --git a/test/CodeGen/Thumb2/thumb2-strh.ll b/test/CodeGen/Thumb2/thumb2-strh.ll
new file mode 100644
index 0000000..b0eb8c1
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-strh.ll
@@ -0,0 +1,76 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i16 @f1(i16 %a, i16* %v) {
+; CHECK: f1:
+; CHECK: strh r0, [r1]
+ store i16 %a, i16* %v
+ ret i16 %a
+}
+
+define i16 @f2(i16 %a, i16* %v) {
+; CHECK: f2:
+; CHECK: strh.w r0, [r1, #+4092]
+ %tmp2 = getelementptr i16* %v, i32 2046
+ store i16 %a, i16* %tmp2
+ ret i16 %a
+}
+
+define i16 @f2a(i16 %a, i16* %v) {
+; CHECK: f2a:
+; CHECK: strh r0, [r1, #-128]
+ %tmp2 = getelementptr i16* %v, i32 -64
+ store i16 %a, i16* %tmp2
+ ret i16 %a
+}
+
+define i16 @f3(i16 %a, i16* %v) {
+; CHECK: f3:
+; CHECK: mov.w r2, #4096
+; CHECK: strh r0, [r1, r2]
+ %tmp2 = getelementptr i16* %v, i32 2048
+ store i16 %a, i16* %tmp2
+ ret i16 %a
+}
+
+define i16 @f4(i16 %a, i32 %base) {
+entry:
+; CHECK: f4:
+; CHECK: strh r0, [r1, #-128]
+ %tmp1 = sub i32 %base, 128
+ %tmp2 = inttoptr i32 %tmp1 to i16*
+ store i16 %a, i16* %tmp2
+ ret i16 %a
+}
+
+define i16 @f5(i16 %a, i32 %base, i32 %offset) {
+entry:
+; CHECK: f5:
+; CHECK: strh r0, [r1, r2]
+ %tmp1 = add i32 %base, %offset
+ %tmp2 = inttoptr i32 %tmp1 to i16*
+ store i16 %a, i16* %tmp2
+ ret i16 %a
+}
+
+define i16 @f6(i16 %a, i32 %base, i32 %offset) {
+entry:
+; CHECK: f6:
+; CHECK: strh.w r0, [r1, r2, lsl #2]
+ %tmp1 = shl i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i16*
+ store i16 %a, i16* %tmp3
+ ret i16 %a
+}
+
+define i16 @f7(i16 %a, i32 %base, i32 %offset) {
+entry:
+; CHECK: f7:
+; CHECK: lsrs r2, r2, #2
+; CHECK: strh r0, [r1, r2]
+ %tmp1 = lshr i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i16*
+ store i16 %a, i16* %tmp3
+ ret i16 %a
+}
diff --git a/test/CodeGen/Thumb2/thumb2-sub.ll b/test/CodeGen/Thumb2/thumb2-sub.ll
new file mode 100644
index 0000000..95335a2
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-sub.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+; 171 = 0x000000ab
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: subs r0, #171
+ %tmp = sub i32 %a, 171
+ ret i32 %tmp
+}
+
+; 1179666 = 0x00120012
+define i32 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: sub.w r0, r0, #1179666
+ %tmp = sub i32 %a, 1179666
+ ret i32 %tmp
+}
+
+; 872428544 = 0x34003400
+define i32 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: sub.w r0, r0, #872428544
+ %tmp = sub i32 %a, 872428544
+ ret i32 %tmp
+}
+
+; 1448498774 = 0x56565656
+define i32 @f4(i32 %a) {
+; CHECK: f4:
+; CHECK: sub.w r0, r0, #1448498774
+ %tmp = sub i32 %a, 1448498774
+ ret i32 %tmp
+}
+
+; 510 = 0x000001fe
+define i32 @f5(i32 %a) {
+; CHECK: f5:
+; CHECK: sub.w r0, r0, #510
+ %tmp = sub i32 %a, 510
+ ret i32 %tmp
+}
+
+; Don't change this to an add.
+define i32 @f6(i32 %a) {
+; CHECK: f6:
+; CHECK: subs r0, #1
+ %tmp = sub i32 %a, 1
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-sub2.ll b/test/CodeGen/Thumb2/thumb2-sub2.ll
new file mode 100644
index 0000000..bb99cbd
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-sub2.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a) {
+ %tmp = sub i32 %a, 4095
+ ret i32 %tmp
+}
+; CHECK: f1:
+; CHECK: subw r0, r0, #4095
diff --git a/test/CodeGen/Thumb2/thumb2-sub4.ll b/test/CodeGen/Thumb2/thumb2-sub4.ll
new file mode 100644
index 0000000..a040d17
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-sub4.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK: f1:
+; CHECK: subs r0, r0, r1
+ %tmp = sub i32 %a, %b
+ ret i32 %tmp
+}
+
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK: f2:
+; CHECK: sub.w r0, r0, r1, lsl #5
+ %tmp = shl i32 %b, 5
+ %tmp1 = sub i32 %a, %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f3(i32 %a, i32 %b) {
+; CHECK: f3:
+; CHECK: sub.w r0, r0, r1, lsr #6
+ %tmp = lshr i32 %b, 6
+ %tmp1 = sub i32 %a, %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f4(i32 %a, i32 %b) {
+; CHECK: f4:
+; CHECK: sub.w r0, r0, r1, asr #7
+ %tmp = ashr i32 %b, 7
+ %tmp1 = sub i32 %a, %tmp
+ ret i32 %tmp1
+}
+
+define i32 @f5(i32 %a, i32 %b) {
+; CHECK: f5:
+; CHECK: sub.w r0, r0, r0, ror #8
+ %l8 = shl i32 %a, 24
+ %r8 = lshr i32 %a, 8
+ %tmp = or i32 %l8, %r8
+ %tmp1 = sub i32 %a, %tmp
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/Thumb2/thumb2-sub5.ll b/test/CodeGen/Thumb2/thumb2-sub5.ll
new file mode 100644
index 0000000..c3b56bc
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-sub5.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i64 @f1(i64 %a, i64 %b) {
+; CHECK: f1:
+; CHECK: subs r0, r0, r2
+; CHECK: sbcs r1, r3
+ %tmp = sub i64 %a, %b
+ ret i64 %tmp
+}
diff --git a/test/CodeGen/Thumb2/thumb2-sxt_rot.ll b/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
new file mode 100644
index 0000000..054d5df
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @test0(i8 %A) {
+; CHECK: test0
+; CHECK: sxtb r0, r0
+ %B = sext i8 %A to i32
+ ret i32 %B
+}
+
+define i8 @test1(i32 %A) signext {
+; CHECK: test1
+; CHECK: sxtb.w r0, r0, ror #8
+ %B = lshr i32 %A, 8
+ %C = shl i32 %A, 24
+ %D = or i32 %B, %C
+ %E = trunc i32 %D to i8
+ ret i8 %E
+}
+
+define i32 @test2(i32 %A, i32 %X) signext {
+; CHECK: test2
+; CHECK: lsrs r0, r0, #8
+; CHECK: sxtab r0, r1, r0
+ %B = lshr i32 %A, 8
+ %C = shl i32 %A, 24
+ %D = or i32 %B, %C
+ %E = trunc i32 %D to i8
+ %F = sext i8 %E to i32
+ %G = add i32 %F, %X
+ ret i32 %G
+}
diff --git a/test/CodeGen/Thumb2/thumb2-tbb.ll b/test/CodeGen/Thumb2/thumb2-tbb.ll
new file mode 100644
index 0000000..5dc3cc3
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-tbb.ll
@@ -0,0 +1,57 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s
+
+define void @bar(i32 %n.u) {
+entry:
+; CHECK: bar:
+; CHECK: tbb
+; CHECK: .align 1
+
+ switch i32 %n.u, label %bb12 [i32 1, label %bb i32 2, label %bb6 i32 4, label %bb7 i32 5, label %bb8 i32 6, label %bb10 i32 7, label %bb1 i32 8, label %bb3 i32 9, label %bb4 i32 10, label %bb9 i32 11, label %bb2 i32 12, label %bb5 i32 13, label %bb11 ]
+bb:
+ tail call void(...)* @foo1()
+ ret void
+bb1:
+ tail call void(...)* @foo2()
+ ret void
+bb2:
+ tail call void(...)* @foo6()
+ ret void
+bb3:
+ tail call void(...)* @foo3()
+ ret void
+bb4:
+ tail call void(...)* @foo4()
+ ret void
+bb5:
+ tail call void(...)* @foo5()
+ ret void
+bb6:
+ tail call void(...)* @foo1()
+ ret void
+bb7:
+ tail call void(...)* @foo2()
+ ret void
+bb8:
+ tail call void(...)* @foo6()
+ ret void
+bb9:
+ tail call void(...)* @foo3()
+ ret void
+bb10:
+ tail call void(...)* @foo4()
+ ret void
+bb11:
+ tail call void(...)* @foo5()
+ ret void
+bb12:
+ tail call void(...)* @foo6()
+ ret void
+}
+
+declare void @foo1(...)
+declare void @foo2(...)
+declare void @foo6(...)
+declare void @foo3(...)
+declare void @foo4(...)
+declare void @foo5(...)
diff --git a/test/CodeGen/Thumb2/thumb2-tbh.ll b/test/CodeGen/Thumb2/thumb2-tbh.ll
new file mode 100644
index 0000000..2cf1d6a
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-tbh.ll
@@ -0,0 +1,84 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s
+
+; Thumb2 target should reorder the bb's in order to use tbb / tbh.
+
+ %struct.R_flstr = type { i32, i32, i8* }
+ %struct._T_tstr = type { i32, %struct.R_flstr*, %struct._T_tstr* }
+@_C_nextcmd = external global i32 ; <i32*> [#uses=3]
[email protected] = external constant [28 x i8], align 1 ; <[28 x i8]*> [#uses=1]
+@_T_gtol = external global %struct._T_tstr* ; <%struct._T_tstr**> [#uses=2]
+
+declare arm_apcscc i32 @strlen(i8* nocapture) nounwind readonly
+
+declare arm_apcscc void @Z_fatal(i8*) noreturn nounwind
+
+declare arm_apcscc noalias i8* @calloc(i32, i32) nounwind
+
+define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
+; CHECK: main:
+; CHECK: tbb
+entry:
+ br label %bb42.i
+
+bb1.i2: ; preds = %bb42.i
+ br label %bb40.i
+
+bb5.i: ; preds = %bb42.i
+ %0 = or i32 %argc, 32 ; <i32> [#uses=1]
+ br label %bb40.i
+
+bb7.i: ; preds = %bb42.i
+ call arm_apcscc void @_T_addtol(%struct._T_tstr** @_T_gtol, i32 0, i8* null) nounwind
+ unreachable
+
+bb15.i: ; preds = %bb42.i
+ call arm_apcscc void @_T_addtol(%struct._T_tstr** @_T_gtol, i32 2, i8* null) nounwind
+ unreachable
+
+bb23.i: ; preds = %bb42.i
+ %1 = call arm_apcscc i32 @strlen(i8* null) nounwind readonly ; <i32> [#uses=0]
+ unreachable
+
+bb33.i: ; preds = %bb42.i
+ store i32 0, i32* @_C_nextcmd, align 4
+ %2 = call arm_apcscc noalias i8* @calloc(i32 21, i32 1) nounwind ; <i8*> [#uses=0]
+ unreachable
+
+bb34.i: ; preds = %bb42.i
+ %3 = load i32* @_C_nextcmd, align 4 ; <i32> [#uses=1]
+ %4 = add i32 %3, 1 ; <i32> [#uses=1]
+ store i32 %4, i32* @_C_nextcmd, align 4
+ %5 = call arm_apcscc noalias i8* @calloc(i32 22, i32 1) nounwind ; <i8*> [#uses=0]
+ unreachable
+
+bb35.i: ; preds = %bb42.i
+ %6 = call arm_apcscc noalias i8* @calloc(i32 20, i32 1) nounwind ; <i8*> [#uses=0]
+ unreachable
+
+bb37.i: ; preds = %bb42.i
+ %7 = call arm_apcscc noalias i8* @calloc(i32 14, i32 1) nounwind ; <i8*> [#uses=0]
+ unreachable
+
+bb39.i: ; preds = %bb42.i
+ call arm_apcscc void @Z_fatal(i8* getelementptr ([28 x i8]* @.str31, i32 0, i32 0)) nounwind
+ unreachable
+
+bb40.i: ; preds = %bb42.i, %bb5.i, %bb1.i2
+ br label %bb42.i
+
+bb42.i: ; preds = %bb40.i, %entry
+ switch i32 %argc, label %bb39.i [
+ i32 67, label %bb33.i
+ i32 70, label %bb35.i
+ i32 77, label %bb37.i
+ i32 83, label %bb34.i
+ i32 97, label %bb7.i
+ i32 100, label %bb5.i
+ i32 101, label %bb40.i
+ i32 102, label %bb23.i
+ i32 105, label %bb15.i
+ i32 116, label %bb1.i2
+ ]
+}
+
+declare arm_apcscc void @_T_addtol(%struct._T_tstr** nocapture, i32, i8*) nounwind
diff --git a/test/CodeGen/Thumb2/thumb2-teq.ll b/test/CodeGen/Thumb2/thumb2-teq.ll
new file mode 100644
index 0000000..69f0383
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-teq.ll
@@ -0,0 +1,93 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+
+; 0x000000bb = 187
+define i1 @f1(i32 %a) {
+ %tmp = xor i32 %a, 187
+ %tmp1 = icmp ne i32 %tmp, 0
+ ret i1 %tmp1
+}
+; CHECK: f1:
+; CHECK: teq.w r0, #187
+
+; 0x000000bb = 187
+define i1 @f2(i32 %a) {
+ %tmp = xor i32 %a, 187
+ %tmp1 = icmp eq i32 0, %tmp
+ ret i1 %tmp1
+}
+; CHECK: f2:
+; CHECK: teq.w r0, #187
+
+; 0x00aa00aa = 11141290
+define i1 @f3(i32 %a) {
+ %tmp = xor i32 %a, 11141290
+ %tmp1 = icmp eq i32 %tmp, 0
+ ret i1 %tmp1
+}
+; CHECK: f3:
+; CHECK: teq.w r0, #11141290
+
+; 0x00aa00aa = 11141290
+define i1 @f4(i32 %a) {
+ %tmp = xor i32 %a, 11141290
+ %tmp1 = icmp ne i32 0, %tmp
+ ret i1 %tmp1
+}
+; CHECK: f4:
+; CHECK: teq.w r0, #11141290
+
+; 0xcc00cc00 = 3422604288
+define i1 @f5(i32 %a) {
+ %tmp = xor i32 %a, 3422604288
+ %tmp1 = icmp ne i32 %tmp, 0
+ ret i1 %tmp1
+}
+; CHECK: f5:
+; CHECK: teq.w r0, #-872363008
+
+; 0xcc00cc00 = 3422604288
+define i1 @f6(i32 %a) {
+ %tmp = xor i32 %a, 3422604288
+ %tmp1 = icmp eq i32 0, %tmp
+ ret i1 %tmp1
+}
+; CHECK: f6:
+; CHECK: teq.w r0, #-872363008
+
+; 0xdddddddd = 3722304989
+define i1 @f7(i32 %a) {
+ %tmp = xor i32 %a, 3722304989
+ %tmp1 = icmp eq i32 %tmp, 0
+ ret i1 %tmp1
+}
+; CHECK: f7:
+; CHECK: teq.w r0, #-572662307
+
+; 0xdddddddd = 3722304989
+define i1 @f8(i32 %a) {
+ %tmp = xor i32 %a, 3722304989
+ %tmp1 = icmp ne i32 0, %tmp
+ ret i1 %tmp1
+}
+; CHECK: f8:
+; CHECK: teq.w r0, #-572662307
+
+; 0x00110000 = 1114112
+define i1 @f9(i32 %a) {
+ %tmp = xor i32 %a, 1114112
+ %tmp1 = icmp ne i32 %tmp, 0
+ ret i1 %tmp1
+}
+; CHECK: f9:
+; CHECK: teq.w r0, #1114112
+
+; 0x00110000 = 1114112
+define i1 @f10(i32 %a) {
+ %tmp = xor i32 %a, 1114112
+ %tmp1 = icmp eq i32 0, %tmp
+ ret i1 %tmp1
+}
+; CHECK: f10:
+; CHECK: teq.w r0, #1114112
+
diff --git a/test/CodeGen/Thumb2/thumb2-teq2.ll b/test/CodeGen/Thumb2/thumb2-teq2.ll
new file mode 100644
index 0000000..0f122f2
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-teq2.ll
@@ -0,0 +1,71 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i1 @f1(i32 %a, i32 %b) {
+; CHECK: f1
+; CHECK: teq.w r0, r1
+ %tmp = xor i32 %a, %b
+ %tmp1 = icmp ne i32 %tmp, 0
+ ret i1 %tmp1
+}
+
+define i1 @f2(i32 %a, i32 %b) {
+; CHECK: f2
+; CHECK: teq.w r0, r1
+ %tmp = xor i32 %a, %b
+ %tmp1 = icmp eq i32 %tmp, 0
+ ret i1 %tmp1
+}
+
+define i1 @f3(i32 %a, i32 %b) {
+; CHECK: f3
+; CHECK: teq.w r0, r1
+ %tmp = xor i32 %a, %b
+ %tmp1 = icmp ne i32 0, %tmp
+ ret i1 %tmp1
+}
+
+define i1 @f4(i32 %a, i32 %b) {
+; CHECK: f4
+; CHECK: teq.w r0, r1
+ %tmp = xor i32 %a, %b
+ %tmp1 = icmp eq i32 0, %tmp
+ ret i1 %tmp1
+}
+
+define i1 @f6(i32 %a, i32 %b) {
+; CHECK: f6
+; CHECK: teq.w r0, r1, lsl #5
+ %tmp = shl i32 %b, 5
+ %tmp1 = xor i32 %a, %tmp
+ %tmp2 = icmp eq i32 %tmp1, 0
+ ret i1 %tmp2
+}
+
+define i1 @f7(i32 %a, i32 %b) {
+; CHECK: f7
+; CHECK: teq.w r0, r1, lsr #6
+ %tmp = lshr i32 %b, 6
+ %tmp1 = xor i32 %a, %tmp
+ %tmp2 = icmp eq i32 %tmp1, 0
+ ret i1 %tmp2
+}
+
+define i1 @f8(i32 %a, i32 %b) {
+; CHECK: f8
+; CHECK: teq.w r0, r1, asr #7
+ %tmp = ashr i32 %b, 7
+ %tmp1 = xor i32 %a, %tmp
+ %tmp2 = icmp eq i32 %tmp1, 0
+ ret i1 %tmp2
+}
+
+define i1 @f9(i32 %a, i32 %b) {
+; CHECK: f9
+; CHECK: teq.w r0, r0, ror #8
+ %l8 = shl i32 %a, 24
+ %r8 = lshr i32 %a, 8
+ %tmp = or i32 %l8, %r8
+ %tmp1 = xor i32 %a, %tmp
+ %tmp2 = icmp eq i32 %tmp1, 0
+ ret i1 %tmp2
+}
diff --git a/test/CodeGen/Thumb2/thumb2-tst.ll b/test/CodeGen/Thumb2/thumb2-tst.ll
new file mode 100644
index 0000000..d905217
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-tst.ll
@@ -0,0 +1,92 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+
+; 0x000000bb = 187
+define i1 @f1(i32 %a) {
+ %tmp = and i32 %a, 187
+ %tmp1 = icmp ne i32 %tmp, 0
+ ret i1 %tmp1
+}
+; CHECK: f1:
+; CHECK: tst.w r0, #187
+
+; 0x000000bb = 187
+define i1 @f2(i32 %a) {
+ %tmp = and i32 %a, 187
+ %tmp1 = icmp eq i32 0, %tmp
+ ret i1 %tmp1
+}
+; CHECK: f2:
+; CHECK: tst.w r0, #187
+
+; 0x00aa00aa = 11141290
+define i1 @f3(i32 %a) {
+ %tmp = and i32 %a, 11141290
+ %tmp1 = icmp eq i32 %tmp, 0
+ ret i1 %tmp1
+}
+; CHECK: f3:
+; CHECK: tst.w r0, #11141290
+
+; 0x00aa00aa = 11141290
+define i1 @f4(i32 %a) {
+ %tmp = and i32 %a, 11141290
+ %tmp1 = icmp ne i32 0, %tmp
+ ret i1 %tmp1
+}
+; CHECK: f4:
+; CHECK: tst.w r0, #11141290
+
+; 0xcc00cc00 = 3422604288
+define i1 @f5(i32 %a) {
+ %tmp = and i32 %a, 3422604288
+ %tmp1 = icmp ne i32 %tmp, 0
+ ret i1 %tmp1
+}
+; CHECK: f5:
+; CHECK: tst.w r0, #-872363008
+
+; 0xcc00cc00 = 3422604288
+define i1 @f6(i32 %a) {
+ %tmp = and i32 %a, 3422604288
+ %tmp1 = icmp eq i32 0, %tmp
+ ret i1 %tmp1
+}
+; CHECK: f6:
+; CHECK: tst.w r0, #-872363008
+
+; 0xdddddddd = 3722304989
+define i1 @f7(i32 %a) {
+ %tmp = and i32 %a, 3722304989
+ %tmp1 = icmp eq i32 %tmp, 0
+ ret i1 %tmp1
+}
+; CHECK: f7:
+; CHECK: tst.w r0, #-572662307
+
+; 0xdddddddd = 3722304989
+define i1 @f8(i32 %a) {
+ %tmp = and i32 %a, 3722304989
+ %tmp1 = icmp ne i32 0, %tmp
+ ret i1 %tmp1
+}
+; CHECK: f8:
+; CHECK: tst.w r0, #-572662307
+
+; 0x00110000 = 1114112
+define i1 @f9(i32 %a) {
+ %tmp = and i32 %a, 1114112
+ %tmp1 = icmp ne i32 %tmp, 0
+ ret i1 %tmp1
+}
+; CHECK: f9:
+; CHECK: tst.w r0, #1114112
+
+; 0x00110000 = 1114112
+define i1 @f10(i32 %a) {
+ %tmp = and i32 %a, 1114112
+ %tmp1 = icmp eq i32 0, %tmp
+ ret i1 %tmp1
+}
+; CHECK: f10:
+; CHECK: tst.w r0, #1114112
diff --git a/test/CodeGen/Thumb2/thumb2-tst2.ll b/test/CodeGen/Thumb2/thumb2-tst2.ll
new file mode 100644
index 0000000..db202dd
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-tst2.ll
@@ -0,0 +1,71 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i1 @f1(i32 %a, i32 %b) {
+; CHECK: f1:
+; CHECK: tst r0, r1
+ %tmp = and i32 %a, %b
+ %tmp1 = icmp ne i32 %tmp, 0
+ ret i1 %tmp1
+}
+
+define i1 @f2(i32 %a, i32 %b) {
+; CHECK: f2:
+; CHECK: tst r0, r1
+ %tmp = and i32 %a, %b
+ %tmp1 = icmp eq i32 %tmp, 0
+ ret i1 %tmp1
+}
+
+define i1 @f3(i32 %a, i32 %b) {
+; CHECK: f3:
+; CHECK: tst r0, r1
+ %tmp = and i32 %a, %b
+ %tmp1 = icmp ne i32 0, %tmp
+ ret i1 %tmp1
+}
+
+define i1 @f4(i32 %a, i32 %b) {
+; CHECK: f4:
+; CHECK: tst r0, r1
+ %tmp = and i32 %a, %b
+ %tmp1 = icmp eq i32 0, %tmp
+ ret i1 %tmp1
+}
+
+define i1 @f6(i32 %a, i32 %b) {
+; CHECK: f6:
+; CHECK: tst.w r0, r1, lsl #5
+ %tmp = shl i32 %b, 5
+ %tmp1 = and i32 %a, %tmp
+ %tmp2 = icmp eq i32 %tmp1, 0
+ ret i1 %tmp2
+}
+
+define i1 @f7(i32 %a, i32 %b) {
+; CHECK: f7:
+; CHECK: tst.w r0, r1, lsr #6
+ %tmp = lshr i32 %b, 6
+ %tmp1 = and i32 %a, %tmp
+ %tmp2 = icmp eq i32 %tmp1, 0
+ ret i1 %tmp2
+}
+
+define i1 @f8(i32 %a, i32 %b) {
+; CHECK: f8:
+; CHECK: tst.w r0, r1, asr #7
+ %tmp = ashr i32 %b, 7
+ %tmp1 = and i32 %a, %tmp
+ %tmp2 = icmp eq i32 %tmp1, 0
+ ret i1 %tmp2
+}
+
+define i1 @f9(i32 %a, i32 %b) {
+; CHECK: f9:
+; CHECK: tst.w r0, r0, ror #8
+ %l8 = shl i32 %a, 24
+ %r8 = lshr i32 %a, 8
+ %tmp = or i32 %l8, %r8
+ %tmp1 = and i32 %a, %tmp
+ %tmp2 = icmp eq i32 %tmp1, 0
+ ret i1 %tmp2
+}
diff --git a/test/CodeGen/Thumb2/thumb2-uxt_rot.ll b/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
new file mode 100644
index 0000000..75e1d70
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i8 @test1(i32 %A.u) zeroext {
+; CHECK: test1
+; CHECK: uxtb r0, r0
+ %B.u = trunc i32 %A.u to i8
+ ret i8 %B.u
+}
+
+define i32 @test2(i32 %A.u, i32 %B.u) zeroext {
+; CHECK: test2
+; CHECK: uxtab r0, r0, r1
+ %C.u = trunc i32 %B.u to i8
+ %D.u = zext i8 %C.u to i32
+ %E.u = add i32 %A.u, %D.u
+ ret i32 %E.u
+}
+
+define i32 @test3(i32 %A.u) zeroext {
+; CHECK: test3
+; CHECK: uxth.w r0, r0, ror #8
+ %B.u = lshr i32 %A.u, 8
+ %C.u = shl i32 %A.u, 24
+ %D.u = or i32 %B.u, %C.u
+ %E.u = trunc i32 %D.u to i16
+ %F.u = zext i16 %E.u to i32
+ ret i32 %F.u
+}
diff --git a/test/CodeGen/Thumb2/thumb2-uxtb.ll b/test/CodeGen/Thumb2/thumb2-uxtb.ll
new file mode 100644
index 0000000..4e23f53
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-uxtb.ll
@@ -0,0 +1,98 @@
+; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
+
+define i32 @test1(i32 %x) {
+; CHECK: test1
+; CHECK: uxtb16.w r0, r0
+ %tmp1 = and i32 %x, 16711935 ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32 @test2(i32 %x) {
+; CHECK: test2
+; CHECK: uxtb16.w r0, r0, ror #8
+ %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
+
+define i32 @test3(i32 %x) {
+; CHECK: test3
+; CHECK: uxtb16.w r0, r0, ror #8
+ %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
+
+define i32 @test4(i32 %x) {
+; CHECK: test4
+; CHECK: uxtb16.w r0, r0, ror #8
+ %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
+ %tmp6 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+define i32 @test5(i32 %x) {
+; CHECK: test5
+; CHECK: uxtb16.w r0, r0, ror #8
+ %tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
+
+define i32 @test6(i32 %x) {
+; CHECK: test6
+; CHECK: uxtb16.w r0, r0, ror #16
+ %tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1]
+ %tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
+ %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
+ %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+define i32 @test7(i32 %x) {
+; CHECK: test7
+; CHECK: uxtb16.w r0, r0, ror #16
+ %tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1]
+ %tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
+ %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
+ %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+define i32 @test8(i32 %x) {
+; CHECK: test8
+; CHECK: uxtb16.w r0, r0, ror #24
+ %tmp1 = shl i32 %x, 8 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 16711680 ; <i32> [#uses=1]
+ %tmp5 = lshr i32 %x, 24 ; <i32> [#uses=1]
+ %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+define i32 @test9(i32 %x) {
+; CHECK: test9
+; CHECK: uxtb16.w r0, r0, ror #24
+ %tmp1 = lshr i32 %x, 24 ; <i32> [#uses=1]
+ %tmp4 = shl i32 %x, 8 ; <i32> [#uses=1]
+ %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
+ %tmp6 = or i32 %tmp5, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
+define i32 @test10(i32 %p0) {
+; CHECK: test10
+; CHECK: mov.w r1, #16253176
+; CHECK: and.w r0, r1, r0, lsr #7
+; CHECK: lsrs r1, r0, #5
+; CHECK: uxtb16.w r1, r1
+; CHECK: orr.w r0, r1, r0
+
+ %tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2]
+ %tmp4 = lshr i32 %tmp2, 5 ; <i32> [#uses=1]
+ %tmp5 = and i32 %tmp4, 458759 ; <i32> [#uses=1]
+ %tmp7 = or i32 %tmp5, %tmp2 ; <i32> [#uses=1]
+ ret i32 %tmp7
+}
diff --git a/test/CodeGen/Thumb2/tls1.ll b/test/CodeGen/Thumb2/tls1.ll
new file mode 100644
index 0000000..1e55557
--- /dev/null
+++ b/test/CodeGen/Thumb2/tls1.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi | \
+; RUN: grep {i(tpoff)}
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi | \
+; RUN: grep {__aeabi_read_tp}
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi \
+; RUN: -relocation-model=pic | grep {__tls_get_addr}
+
+
+@i = thread_local global i32 15 ; <i32*> [#uses=2]
+
+define i32 @f() {
+entry:
+ %tmp1 = load i32* @i ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32* @g() {
+entry:
+ ret i32* @i
+}
diff --git a/test/CodeGen/Thumb2/tls2.ll b/test/CodeGen/Thumb2/tls2.ll
new file mode 100644
index 0000000..b8a0657
--- /dev/null
+++ b/test/CodeGen/Thumb2/tls2.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi | FileCheck %s -check-prefix=CHECK-NOT-PIC
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC
+
+@i = external thread_local global i32 ; <i32*> [#uses=2]
+
+define i32 @f() {
+entry:
+; CHECK-NOT-PIC: f:
+; CHECK-NOT-PIC: add r0, pc
+; CHECK-NOT-PIC: ldr r1, [r0]
+; CHECK-NOT-PIC: i(gottpoff)
+
+; CHECK-PIC: f:
+; CHECK-PIC: bl __tls_get_addr(PLT)
+ %tmp1 = load i32* @i ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32* @g() {
+entry:
+; CHECK-NOT-PIC: g:
+; CHECK-NOT-PIC: add r0, pc
+; CHECK-NOT-PIC: ldr r1, [r0]
+; CHECK-NOT-PIC: i(gottpoff)
+
+; CHECK-PIC: g:
+; CHECK-PIC: bl __tls_get_addr(PLT)
+ ret i32* @i
+}
diff --git a/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll b/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll
new file mode 100644
index 0000000..2484860
--- /dev/null
+++ b/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll
@@ -0,0 +1,18 @@
+; The old instruction selector used to load all arguments to a call up in
+; registers, then start pushing them all onto the stack. This is bad news as
+; it makes a ton of annoying overlapping live ranges. This code should not
+; cause spills!
+;
+; RUN: llc < %s -march=x86 -stats |& not grep spilled
+
+target datalayout = "e-p:32:32"
+
+define i32 @test(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) {
+ ret i32 0
+}
+
+define i32 @main() {
+ %X = call i32 @test( i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10 ) ; <i32> [#uses=1]
+ ret i32 %X
+}
+
diff --git a/test/CodeGen/X86/2003-08-23-DeadBlockTest.ll b/test/CodeGen/X86/2003-08-23-DeadBlockTest.ll
new file mode 100644
index 0000000..5c40eeaa
--- /dev/null
+++ b/test/CodeGen/X86/2003-08-23-DeadBlockTest.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86
+
+define i32 @test() {
+entry:
+ ret i32 7
+Test: ; No predecessors!
+ %A = call i32 @test( ) ; <i32> [#uses=1]
+ %B = call i32 @test( ) ; <i32> [#uses=1]
+ %C = add i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %C
+}
+
diff --git a/test/CodeGen/X86/2003-11-03-GlobalBool.ll b/test/CodeGen/X86/2003-11-03-GlobalBool.ll
new file mode 100644
index 0000000..8b0a185
--- /dev/null
+++ b/test/CodeGen/X86/2003-11-03-GlobalBool.ll
@@ -0,0 +1,4 @@
+; RUN: llc < %s -march=x86 | \
+; RUN: not grep {.byte\[\[:space:\]\]*true}
+
+@X = global i1 true ; <i1*> [#uses=0]
diff --git a/test/CodeGen/X86/2004-02-12-Memcpy.ll b/test/CodeGen/X86/2004-02-12-Memcpy.ll
new file mode 100644
index 0000000..f15a1b4
--- /dev/null
+++ b/test/CodeGen/X86/2004-02-12-Memcpy.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep movs | count 1
+
+@A = global [32 x i32] zeroinitializer
+@B = global [32 x i32] zeroinitializer
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32)
+
+define void @main() nounwind {
+ ; dword copy
+ call void @llvm.memcpy.i32(i8* bitcast ([32 x i32]* @A to i8*),
+ i8* bitcast ([32 x i32]* @B to i8*),
+ i32 128, i32 4 )
+
+ ; word copy
+ call void @llvm.memcpy.i32( i8* bitcast ([32 x i32]* @A to i8*),
+ i8* bitcast ([32 x i32]* @B to i8*),
+ i32 128, i32 2 )
+
+ ; byte copy
+ call void @llvm.memcpy.i32( i8* bitcast ([32 x i32]* @A to i8*),
+ i8* bitcast ([32 x i32]* @B to i8*),
+ i32 128, i32 1 )
+
+ ret void
+}
diff --git a/test/CodeGen/X86/2004-02-13-FrameReturnAddress.ll b/test/CodeGen/X86/2004-02-13-FrameReturnAddress.ll
new file mode 100644
index 0000000..fea2b54
--- /dev/null
+++ b/test/CodeGen/X86/2004-02-13-FrameReturnAddress.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 | grep {(%esp}
+; RUN: llc < %s -march=x86 | grep {pushl %ebp} | count 1
+; RUN: llc < %s -march=x86 | grep {popl %ebp} | count 1
+
+declare i8* @llvm.returnaddress(i32)
+
+declare i8* @llvm.frameaddress(i32)
+
+define i8* @test1() {
+ %X = call i8* @llvm.returnaddress( i32 0 ) ; <i8*> [#uses=1]
+ ret i8* %X
+}
+
+define i8* @test2() {
+ %X = call i8* @llvm.frameaddress( i32 0 ) ; <i8*> [#uses=1]
+ ret i8* %X
+}
+
diff --git a/test/CodeGen/X86/2004-02-14-InefficientStackPointer.ll b/test/CodeGen/X86/2004-02-14-InefficientStackPointer.ll
new file mode 100644
index 0000000..f986ebd
--- /dev/null
+++ b/test/CodeGen/X86/2004-02-14-InefficientStackPointer.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=x86 | grep -i ESP | not grep sub
+
+define i32 @test(i32 %X) {
+ ret i32 %X
+}
diff --git a/test/CodeGen/X86/2004-02-22-Casts.ll b/test/CodeGen/X86/2004-02-22-Casts.ll
new file mode 100644
index 0000000..dabf7d3
--- /dev/null
+++ b/test/CodeGen/X86/2004-02-22-Casts.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86
+define i1 @test1(double %X) {
+ %V = fcmp one double %X, 0.000000e+00 ; <i1> [#uses=1]
+ ret i1 %V
+}
+
+define double @test2(i64 %X) {
+ %V = uitofp i64 %X to double ; <double> [#uses=1]
+ ret double %V
+}
+
+
diff --git a/test/CodeGen/X86/2004-03-30-Select-Max.ll b/test/CodeGen/X86/2004-03-30-Select-Max.ll
new file mode 100644
index 0000000..b6631b6
--- /dev/null
+++ b/test/CodeGen/X86/2004-03-30-Select-Max.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 | not grep {j\[lgbe\]}
+
+define i32 @max(i32 %A, i32 %B) {
+ %gt = icmp sgt i32 %A, %B ; <i1> [#uses=1]
+ %R = select i1 %gt, i32 %A, i32 %B ; <i32> [#uses=1]
+ ret i32 %R
+}
+
diff --git a/test/CodeGen/X86/2004-04-09-SameValueCoalescing.ll b/test/CodeGen/X86/2004-04-09-SameValueCoalescing.ll
new file mode 100644
index 0000000..c62fee1b
--- /dev/null
+++ b/test/CodeGen/X86/2004-04-09-SameValueCoalescing.ll
@@ -0,0 +1,13 @@
+; Linear scan does not currently coalesce any two variables that have
+; overlapping live intervals. When two overlapping intervals have the same
+; value, they can be joined though.
+;
+; RUN: llc < %s -march=x86 -regalloc=linearscan | \
+; RUN: not grep {mov %\[A-Z\]\\\{2,3\\\}, %\[A-Z\]\\\{2,3\\\}}
+
+define i64 @test(i64 %x) {
+entry:
+ %tmp.1 = mul i64 %x, 4294967297 ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
+
diff --git a/test/CodeGen/X86/2004-04-13-FPCMOV-Crash.ll b/test/CodeGen/X86/2004-04-13-FPCMOV-Crash.ll
new file mode 100644
index 0000000..f8ed016
--- /dev/null
+++ b/test/CodeGen/X86/2004-04-13-FPCMOV-Crash.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86
+
+define double @test(double %d) {
+ %X = select i1 false, double %d, double %d ; <double> [#uses=1]
+ ret double %X
+}
+
diff --git a/test/CodeGen/X86/2004-06-10-StackifierCrash.ll b/test/CodeGen/X86/2004-06-10-StackifierCrash.ll
new file mode 100644
index 0000000..036aa6a
--- /dev/null
+++ b/test/CodeGen/X86/2004-06-10-StackifierCrash.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86
+
+define i1 @T(double %X) {
+ %V = fcmp oeq double %X, %X ; <i1> [#uses=1]
+ ret i1 %V
+}
diff --git a/test/CodeGen/X86/2004-10-08-SelectSetCCFold.ll b/test/CodeGen/X86/2004-10-08-SelectSetCCFold.ll
new file mode 100644
index 0000000..db3af01
--- /dev/null
+++ b/test/CodeGen/X86/2004-10-08-SelectSetCCFold.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86
+
+define i1 @test(i1 %C, i1 %D, i32 %X, i32 %Y) {
+ %E = icmp slt i32 %X, %Y ; <i1> [#uses=1]
+ %F = select i1 %C, i1 %D, i1 %E ; <i1> [#uses=1]
+ ret i1 %F
+}
+
diff --git a/test/CodeGen/X86/2005-01-17-CycleInDAG.ll b/test/CodeGen/X86/2005-01-17-CycleInDAG.ll
new file mode 100644
index 0000000..32fafc6
--- /dev/null
+++ b/test/CodeGen/X86/2005-01-17-CycleInDAG.ll
@@ -0,0 +1,17 @@
+; This testcase was distilled from 132.ijpeg. Bsaically we cannot fold the
+; load into the sub instruction here as it induces a cycle in the dag, which
+; is invalid code (there is no correct way to order the instruction). Check
+; that we do not fold the load into the sub.
+
+; RUN: llc < %s -march=x86 | not grep sub.*GLOBAL
+
+@GLOBAL = external global i32 ; <i32*> [#uses=1]
+
+define i32 @test(i32* %P1, i32* %P2, i32* %P3) {
+ %L = load i32* @GLOBAL ; <i32> [#uses=1]
+ store i32 12, i32* %P2
+ %Y = load i32* %P3 ; <i32> [#uses=1]
+ %Z = sub i32 %Y, %L ; <i32> [#uses=1]
+ ret i32 %Z
+}
+
diff --git a/test/CodeGen/X86/2005-02-14-IllegalAssembler.ll b/test/CodeGen/X86/2005-02-14-IllegalAssembler.ll
new file mode 100644
index 0000000..30a6ac6
--- /dev/null
+++ b/test/CodeGen/X86/2005-02-14-IllegalAssembler.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=x86 | not grep 18446744073709551612
+
+@A = external global i32 ; <i32*> [#uses=1]
+@Y = global i32* getelementptr (i32* @A, i32 -1) ; <i32**> [#uses=0]
+
diff --git a/test/CodeGen/X86/2005-05-08-FPStackifierPHI.ll b/test/CodeGen/X86/2005-05-08-FPStackifierPHI.ll
new file mode 100644
index 0000000..5266009
--- /dev/null
+++ b/test/CodeGen/X86/2005-05-08-FPStackifierPHI.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -march=x86 -mcpu=generic
+; Make sure LLC doesn't crash in the stackifier due to FP PHI nodes.
+
+define void @radfg_() {
+entry:
+ br i1 false, label %no_exit.16.preheader, label %loopentry.0
+loopentry.0: ; preds = %entry
+ ret void
+no_exit.16.preheader: ; preds = %entry
+ br label %no_exit.16
+no_exit.16: ; preds = %no_exit.16, %no_exit.16.preheader
+ br i1 false, label %loopexit.16.loopexit, label %no_exit.16
+loopexit.16.loopexit: ; preds = %no_exit.16
+ br label %no_exit.18
+no_exit.18: ; preds = %loopexit.20, %loopexit.16.loopexit
+ %tmp.882 = fadd float 0.000000e+00, 0.000000e+00 ; <float> [#uses=2]
+ br i1 false, label %loopexit.19, label %no_exit.19.preheader
+no_exit.19.preheader: ; preds = %no_exit.18
+ ret void
+loopexit.19: ; preds = %no_exit.18
+ br i1 false, label %loopexit.20, label %no_exit.20
+no_exit.20: ; preds = %loopexit.21, %loopexit.19
+ %ai2.1122.tmp.3 = phi float [ %tmp.958, %loopexit.21 ], [ %tmp.882, %loopexit.19 ] ; <float> [#uses=1]
+ %tmp.950 = fmul float %tmp.882, %ai2.1122.tmp.3 ; <float> [#uses=1]
+ %tmp.951 = fsub float 0.000000e+00, %tmp.950 ; <float> [#uses=1]
+ %tmp.958 = fadd float 0.000000e+00, 0.000000e+00 ; <float> [#uses=1]
+ br i1 false, label %loopexit.21, label %no_exit.21.preheader
+no_exit.21.preheader: ; preds = %no_exit.20
+ ret void
+loopexit.21: ; preds = %no_exit.20
+ br i1 false, label %loopexit.20, label %no_exit.20
+loopexit.20: ; preds = %loopexit.21, %loopexit.19
+ %ar2.1124.tmp.2 = phi float [ 0.000000e+00, %loopexit.19 ], [ %tmp.951, %loopexit.21 ] ; <float> [#uses=0]
+ br i1 false, label %loopexit.18.loopexit, label %no_exit.18
+loopexit.18.loopexit: ; preds = %loopexit.20
+ ret void
+}
+
diff --git a/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll b/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll
new file mode 100644
index 0000000..d906da4
--- /dev/null
+++ b/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86 | \
+; RUN: grep shld | count 1
+;
+; Check that the isel does not fold the shld, which already folds a load
+; and has two uses, into a store.
+
+@A = external global i32 ; <i32*> [#uses=2]
+
+define i32 @test5(i32 %B, i8 %C) {
+ %tmp.1 = load i32* @A ; <i32> [#uses=1]
+ %shift.upgrd.1 = zext i8 %C to i32 ; <i32> [#uses=1]
+ %tmp.2 = shl i32 %tmp.1, %shift.upgrd.1 ; <i32> [#uses=1]
+ %tmp.3 = sub i8 32, %C ; <i8> [#uses=1]
+ %shift.upgrd.2 = zext i8 %tmp.3 to i32 ; <i32> [#uses=1]
+ %tmp.4 = lshr i32 %B, %shift.upgrd.2 ; <i32> [#uses=1]
+ %tmp.5 = or i32 %tmp.4, %tmp.2 ; <i32> [#uses=2]
+ store i32 %tmp.5, i32* @A
+ ret i32 %tmp.5
+}
+
diff --git a/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll b/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll
new file mode 100644
index 0000000..dc69ef8
--- /dev/null
+++ b/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 | not grep {subl.*%esp}
+
+define i32 @f(i32 %a, i32 %b) {
+ %tmp.2 = mul i32 %a, %a ; <i32> [#uses=1]
+ %tmp.5 = shl i32 %a, 1 ; <i32> [#uses=1]
+ %tmp.6 = mul i32 %tmp.5, %b ; <i32> [#uses=1]
+ %tmp.10 = mul i32 %b, %b ; <i32> [#uses=1]
+ %tmp.7 = add i32 %tmp.10, %tmp.2 ; <i32> [#uses=1]
+ %tmp.11 = add i32 %tmp.7, %tmp.6 ; <i32> [#uses=1]
+ ret i32 %tmp.11
+}
+
diff --git a/test/CodeGen/X86/2006-03-02-InstrSchedBug.ll b/test/CodeGen/X86/2006-03-02-InstrSchedBug.ll
new file mode 100644
index 0000000..0421896
--- /dev/null
+++ b/test/CodeGen/X86/2006-03-02-InstrSchedBug.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -stats |& \
+; RUN: grep asm-printer | grep 7
+
+define i32 @g(i32 %a, i32 %b) nounwind {
+ %tmp.1 = shl i32 %b, 1 ; <i32> [#uses=1]
+ %tmp.3 = add i32 %tmp.1, %a ; <i32> [#uses=1]
+ %tmp.5 = mul i32 %tmp.3, %a ; <i32> [#uses=1]
+ %tmp.8 = mul i32 %b, %b ; <i32> [#uses=1]
+ %tmp.9 = add i32 %tmp.5, %tmp.8 ; <i32> [#uses=1]
+ ret i32 %tmp.9
+}
+
diff --git a/test/CodeGen/X86/2006-04-04-CrossBlockCrash.ll b/test/CodeGen/X86/2006-04-04-CrossBlockCrash.ll
new file mode 100644
index 0000000..3f67097
--- /dev/null
+++ b/test/CodeGen/X86/2006-04-04-CrossBlockCrash.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah
+; END.
+
+target datalayout = "e-p:32:32"
+target triple = "i686-apple-darwin8.6.1"
+ %struct.GLTColor4 = type { float, float, float, float }
+ %struct.GLTCoord3 = type { float, float, float }
+ %struct.__GLIContextRec = type { { %struct.anon, { [24 x [16 x float]], [24 x [16 x float]] }, %struct.GLTColor4, { float, float, float, float, %struct.GLTCoord3, float } }, { float, float, float, float, float, float, float, float, [4 x i32], [4 x i32], [4 x i32] } }
+ %struct.__GLvertex = type { %struct.GLTColor4, %struct.GLTColor4, %struct.GLTColor4, %struct.GLTColor4, %struct.GLTColor4, %struct.GLTCoord3, float, %struct.GLTColor4, float, float, float, i8, i8, i8, i8, [4 x float], [2 x i8*], i32, i32, [16 x %struct.GLTColor4] }
+ %struct.anon = type { float, float, float, float, float, float, float, float }
+
+declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8)
+
+declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>)
+
+declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>)
+
+define void @gleLLVMVecInterpolateClip() {
+entry:
+ br i1 false, label %cond_false, label %cond_false183
+cond_false: ; preds = %entry
+ br i1 false, label %cond_false183, label %cond_true69
+cond_true69: ; preds = %cond_false
+ ret void
+cond_false183: ; preds = %cond_false, %entry
+ %vuizmsk.0.1 = phi <4 x i32> [ < i32 -1, i32 -1, i32 -1, i32 0 >, %entry ], [ < i32 -1, i32 0, i32 0, i32 0 >, %cond_false ] ; <<4 x i32>> [#uses=2]
+ %tmp192 = extractelement <4 x i32> %vuizmsk.0.1, i32 2 ; <i32> [#uses=1]
+ %tmp193 = extractelement <4 x i32> %vuizmsk.0.1, i32 3 ; <i32> [#uses=2]
+ %tmp195 = insertelement <4 x i32> zeroinitializer, i32 %tmp192, i32 1 ; <<4 x i32>> [#uses=1]
+ %tmp196 = insertelement <4 x i32> %tmp195, i32 %tmp193, i32 2 ; <<4 x i32>> [#uses=1]
+ %tmp197 = insertelement <4 x i32> %tmp196, i32 %tmp193, i32 3 ; <<4 x i32>> [#uses=1]
+ %tmp336 = and <4 x i32> zeroinitializer, %tmp197 ; <<4 x i32>> [#uses=1]
+ %tmp337 = bitcast <4 x i32> %tmp336 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp378 = tail call <4 x float> @llvm.x86.sse.cmp.ps( <4 x float> %tmp337, <4 x float> zeroinitializer, i8 1 ) ; <<4 x float>> [#uses=1]
+ %tmp379 = bitcast <4 x float> %tmp378 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp388 = tail call <8 x i16> @llvm.x86.sse2.packssdw.128( <4 x i32> zeroinitializer, <4 x i32> %tmp379 ) ; <<4 x i32>> [#uses=1]
+ %tmp392 = bitcast <8 x i16> %tmp388 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp399 = extractelement <8 x i16> %tmp392, i32 7 ; <i16> [#uses=1]
+ %tmp423 = insertelement <8 x i16> zeroinitializer, i16 %tmp399, i32 7 ; <<8 x i16>> [#uses=1]
+ %tmp427 = bitcast <8 x i16> %tmp423 to <16 x i8> ; <<16 x i8>> [#uses=1]
+ %tmp428 = tail call i32 @llvm.x86.sse2.pmovmskb.128( <16 x i8> %tmp427 ) ; <i32> [#uses=1]
+ %tmp432 = trunc i32 %tmp428 to i8 ; <i8> [#uses=1]
+ %tmp = and i8 %tmp432, 42 ; <i8> [#uses=1]
+ %tmp436 = bitcast i8 %tmp to i8 ; <i8> [#uses=1]
+ %tmp446 = zext i8 %tmp436 to i32 ; <i32> [#uses=1]
+ %tmp447 = shl i32 %tmp446, 24 ; <i32> [#uses=1]
+ %tmp449 = or i32 0, %tmp447 ; <i32> [#uses=1]
+ store i32 %tmp449, i32* null
+ ret void
+}
diff --git a/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll b/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
new file mode 100644
index 0000000..8783a11
--- /dev/null
+++ b/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin8 -relocation-model=static > %t
+; RUN: grep {movl _last} %t | count 1
+; RUN: grep {cmpl.*_last} %t | count 1
+
+@block = external global i8* ; <i8**> [#uses=1]
+@last = external global i32 ; <i32*> [#uses=3]
+
+define i1 @loadAndRLEsource_no_exit_2E_1_label_2E_0(i32 %tmp.21.reload, i32 %tmp.8) {
+newFuncRoot:
+ br label %label.0
+label.0.no_exit.1_crit_edge.exitStub: ; preds = %label.0
+ ret i1 true
+codeRepl5.exitStub: ; preds = %label.0
+ ret i1 false
+label.0: ; preds = %newFuncRoot
+ %tmp.35 = load i32* @last ; <i32> [#uses=1]
+ %inc.1 = add i32 %tmp.35, 1 ; <i32> [#uses=2]
+ store i32 %inc.1, i32* @last
+ %tmp.36 = load i8** @block ; <i8*> [#uses=1]
+ %tmp.38 = getelementptr i8* %tmp.36, i32 %inc.1 ; <i8*> [#uses=1]
+ %tmp.40 = trunc i32 %tmp.21.reload to i8 ; <i8> [#uses=1]
+ store i8 %tmp.40, i8* %tmp.38
+ %tmp.910 = load i32* @last ; <i32> [#uses=1]
+ %tmp.1111 = icmp slt i32 %tmp.910, %tmp.8 ; <i1> [#uses=1]
+ %tmp.1412 = icmp ne i32 %tmp.21.reload, 257 ; <i1> [#uses=1]
+ %tmp.1613 = and i1 %tmp.1111, %tmp.1412 ; <i1> [#uses=1]
+ br i1 %tmp.1613, label %label.0.no_exit.1_crit_edge.exitStub, label %codeRepl5.exitStub
+}
+
diff --git a/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll b/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll
new file mode 100644
index 0000000..b045329
--- /dev/null
+++ b/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll
@@ -0,0 +1,76 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah -stats |& \
+; RUN: not grep {Number of register spills}
+; END.
+
+
+define i32 @foo(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
+ %tmp44 = load <4 x float>* %a ; <<4 x float>> [#uses=9]
+ %tmp46 = load <4 x float>* %b ; <<4 x float>> [#uses=1]
+ %tmp48 = load <4 x float>* %c ; <<4 x float>> [#uses=1]
+ %tmp50 = load <4 x float>* %d ; <<4 x float>> [#uses=1]
+ %tmp51 = bitcast <4 x float> %tmp44 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp = shufflevector <4 x i32> %tmp51, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>> [#uses=2]
+ %tmp52 = bitcast <4 x i32> %tmp to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp60 = xor <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1]
+ %tmp61 = bitcast <4 x i32> %tmp60 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp74 = tail call <4 x float> @llvm.x86.sse.cmp.ps( <4 x float> %tmp52, <4 x float> %tmp44, i8 1 ) ; <<4 x float>> [#uses=1]
+ %tmp75 = bitcast <4 x float> %tmp74 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp88 = tail call <4 x float> @llvm.x86.sse.cmp.ps( <4 x float> %tmp44, <4 x float> %tmp61, i8 1 ) ; <<4 x float>> [#uses=1]
+ %tmp89 = bitcast <4 x float> %tmp88 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp98 = tail call <8 x i16> @llvm.x86.sse2.packssdw.128( <4 x i32> %tmp75, <4 x i32> %tmp89 ) ; <<4 x i32>> [#uses=1]
+ %tmp102 = bitcast <8 x i16> %tmp98 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp.upgrd.1 = shufflevector <8 x i16> %tmp102, <8 x i16> undef, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 6, i32 5, i32 4, i32 7 > ; <<8 x i16>> [#uses=1]
+ %tmp105 = shufflevector <8 x i16> %tmp.upgrd.1, <8 x i16> undef, <8 x i32> < i32 2, i32 1, i32 0, i32 3, i32 4, i32 5, i32 6, i32 7 > ; <<8 x i16>> [#uses=1]
+ %tmp105.upgrd.2 = bitcast <8 x i16> %tmp105 to <4 x float> ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp105.upgrd.2, <4 x float>* %a
+ %tmp108 = bitcast <4 x float> %tmp46 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp109 = shufflevector <4 x i32> %tmp108, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>> [#uses=2]
+ %tmp109.upgrd.3 = bitcast <4 x i32> %tmp109 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp119 = xor <4 x i32> %tmp109, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1]
+ %tmp120 = bitcast <4 x i32> %tmp119 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp133 = tail call <4 x float> @llvm.x86.sse.cmp.ps( <4 x float> %tmp109.upgrd.3, <4 x float> %tmp44, i8 1 ) ; <<4 x float>> [#uses=1]
+ %tmp134 = bitcast <4 x float> %tmp133 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp147 = tail call <4 x float> @llvm.x86.sse.cmp.ps( <4 x float> %tmp44, <4 x float> %tmp120, i8 1 ) ; <<4 x float>> [#uses=1]
+ %tmp148 = bitcast <4 x float> %tmp147 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp159 = tail call <8 x i16> @llvm.x86.sse2.packssdw.128( <4 x i32> %tmp134, <4 x i32> %tmp148 ) ; <<4 x i32>> [#uses=1]
+ %tmp163 = bitcast <8 x i16> %tmp159 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp164 = shufflevector <8 x i16> %tmp163, <8 x i16> undef, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 6, i32 5, i32 4, i32 7 > ; <<8 x i16>> [#uses=1]
+ %tmp166 = shufflevector <8 x i16> %tmp164, <8 x i16> undef, <8 x i32> < i32 2, i32 1, i32 0, i32 3, i32 4, i32 5, i32 6, i32 7 > ; <<8 x i16>> [#uses=1]
+ %tmp166.upgrd.4 = bitcast <8 x i16> %tmp166 to <4 x float> ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp166.upgrd.4, <4 x float>* %b
+ %tmp169 = bitcast <4 x float> %tmp48 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp170 = shufflevector <4 x i32> %tmp169, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>> [#uses=2]
+ %tmp170.upgrd.5 = bitcast <4 x i32> %tmp170 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp180 = xor <4 x i32> %tmp170, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1]
+ %tmp181 = bitcast <4 x i32> %tmp180 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp194 = tail call <4 x float> @llvm.x86.sse.cmp.ps( <4 x float> %tmp170.upgrd.5, <4 x float> %tmp44, i8 1 ) ; <<4 x float>> [#uses=1]
+ %tmp195 = bitcast <4 x float> %tmp194 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp208 = tail call <4 x float> @llvm.x86.sse.cmp.ps( <4 x float> %tmp44, <4 x float> %tmp181, i8 1 ) ; <<4 x float>> [#uses=1]
+ %tmp209 = bitcast <4 x float> %tmp208 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp220 = tail call <8 x i16> @llvm.x86.sse2.packssdw.128( <4 x i32> %tmp195, <4 x i32> %tmp209 ) ; <<4 x i32>> [#uses=1]
+ %tmp224 = bitcast <8 x i16> %tmp220 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp225 = shufflevector <8 x i16> %tmp224, <8 x i16> undef, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 6, i32 5, i32 4, i32 7 > ; <<8 x i16>> [#uses=1]
+ %tmp227 = shufflevector <8 x i16> %tmp225, <8 x i16> undef, <8 x i32> < i32 2, i32 1, i32 0, i32 3, i32 4, i32 5, i32 6, i32 7 > ; <<8 x i16>> [#uses=1]
+ %tmp227.upgrd.6 = bitcast <8 x i16> %tmp227 to <4 x float> ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp227.upgrd.6, <4 x float>* %c
+ %tmp230 = bitcast <4 x float> %tmp50 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp231 = shufflevector <4 x i32> %tmp230, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>> [#uses=2]
+ %tmp231.upgrd.7 = bitcast <4 x i32> %tmp231 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp241 = xor <4 x i32> %tmp231, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1]
+ %tmp242 = bitcast <4 x i32> %tmp241 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp255 = tail call <4 x float> @llvm.x86.sse.cmp.ps( <4 x float> %tmp231.upgrd.7, <4 x float> %tmp44, i8 1 ) ; <<4 x float>> [#uses=1]
+ %tmp256 = bitcast <4 x float> %tmp255 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp269 = tail call <4 x float> @llvm.x86.sse.cmp.ps( <4 x float> %tmp44, <4 x float> %tmp242, i8 1 ) ; <<4 x float>> [#uses=1]
+ %tmp270 = bitcast <4 x float> %tmp269 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp281 = tail call <8 x i16> @llvm.x86.sse2.packssdw.128( <4 x i32> %tmp256, <4 x i32> %tmp270 ) ; <<4 x i32>> [#uses=1]
+ %tmp285 = bitcast <8 x i16> %tmp281 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp286 = shufflevector <8 x i16> %tmp285, <8 x i16> undef, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 6, i32 5, i32 4, i32 7 > ; <<8 x i16>> [#uses=1]
+ %tmp288 = shufflevector <8 x i16> %tmp286, <8 x i16> undef, <8 x i32> < i32 2, i32 1, i32 0, i32 3, i32 4, i32 5, i32 6, i32 7 > ; <<8 x i16>> [#uses=1]
+ %tmp288.upgrd.8 = bitcast <8 x i16> %tmp288 to <4 x float> ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp288.upgrd.8, <4 x float>* %d
+ ret i32 0
+}
+
+declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8)
+
+declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>)
diff --git a/test/CodeGen/X86/2006-05-02-InstrSched1.ll b/test/CodeGen/X86/2006-05-02-InstrSched1.ll
new file mode 100644
index 0000000..7d0a6ab
--- /dev/null
+++ b/test/CodeGen/X86/2006-05-02-InstrSched1.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86 -relocation-model=static -stats |& \
+; RUN: grep asm-printer | grep 14
+;
+@size20 = external global i32 ; <i32*> [#uses=1]
+@in5 = external global i8* ; <i8**> [#uses=1]
+
+define i32 @compare(i8* %a, i8* %b) nounwind {
+ %tmp = bitcast i8* %a to i32* ; <i32*> [#uses=1]
+ %tmp1 = bitcast i8* %b to i32* ; <i32*> [#uses=1]
+ %tmp.upgrd.1 = load i32* @size20 ; <i32> [#uses=1]
+ %tmp.upgrd.2 = load i8** @in5 ; <i8*> [#uses=2]
+ %tmp3 = load i32* %tmp1 ; <i32> [#uses=1]
+ %gep.upgrd.3 = zext i32 %tmp3 to i64 ; <i64> [#uses=1]
+ %tmp4 = getelementptr i8* %tmp.upgrd.2, i64 %gep.upgrd.3 ; <i8*> [#uses=2]
+ %tmp7 = load i32* %tmp ; <i32> [#uses=1]
+ %gep.upgrd.4 = zext i32 %tmp7 to i64 ; <i64> [#uses=1]
+ %tmp8 = getelementptr i8* %tmp.upgrd.2, i64 %gep.upgrd.4 ; <i8*> [#uses=2]
+ %tmp.upgrd.5 = tail call i32 @memcmp( i8* %tmp8, i8* %tmp4, i32 %tmp.upgrd.1 ) ; <i32> [#uses=1]
+ ret i32 %tmp.upgrd.5
+}
+
+declare i32 @memcmp(i8*, i8*, i32)
+
diff --git a/test/CodeGen/X86/2006-05-02-InstrSched2.ll b/test/CodeGen/X86/2006-05-02-InstrSched2.ll
new file mode 100644
index 0000000..23954d7
--- /dev/null
+++ b/test/CodeGen/X86/2006-05-02-InstrSched2.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 -stats |& \
+; RUN: grep asm-printer | grep 13
+
+define void @_ZN9__gnu_cxx9hashtableISt4pairIKPKciES3_NS_4hashIS3_EESt10_Select1stIS5_E5eqstrSaIiEE14find_or_insertERKS5__cond_true456.i(i8* %tmp435.i, i32* %tmp449.i.out) nounwind {
+newFuncRoot:
+ br label %cond_true456.i
+bb459.i.exitStub: ; preds = %cond_true456.i
+ store i32 %tmp449.i, i32* %tmp449.i.out
+ ret void
+cond_true456.i: ; preds = %cond_true456.i, %newFuncRoot
+ %__s441.2.4.i = phi i8* [ %tmp451.i.upgrd.1, %cond_true456.i ], [ %tmp435.i, %newFuncRoot ] ; <i8*> [#uses=2]
+ %__h.2.4.i = phi i32 [ %tmp449.i, %cond_true456.i ], [ 0, %newFuncRoot ] ; <i32> [#uses=1]
+ %tmp446.i = mul i32 %__h.2.4.i, 5 ; <i32> [#uses=1]
+ %tmp.i = load i8* %__s441.2.4.i ; <i8> [#uses=1]
+ %tmp448.i = sext i8 %tmp.i to i32 ; <i32> [#uses=1]
+ %tmp449.i = add i32 %tmp448.i, %tmp446.i ; <i32> [#uses=2]
+ %tmp450.i = ptrtoint i8* %__s441.2.4.i to i32 ; <i32> [#uses=1]
+ %tmp451.i = add i32 %tmp450.i, 1 ; <i32> [#uses=1]
+ %tmp451.i.upgrd.1 = inttoptr i32 %tmp451.i to i8* ; <i8*> [#uses=2]
+ %tmp45435.i = load i8* %tmp451.i.upgrd.1 ; <i8> [#uses=1]
+ %tmp45536.i = icmp eq i8 %tmp45435.i, 0 ; <i1> [#uses=1]
+ br i1 %tmp45536.i, label %bb459.i.exitStub, label %cond_true456.i
+}
+
diff --git a/test/CodeGen/X86/2006-05-08-CoalesceSubRegClass.ll b/test/CodeGen/X86/2006-05-08-CoalesceSubRegClass.ll
new file mode 100644
index 0000000..8421483
--- /dev/null
+++ b/test/CodeGen/X86/2006-05-08-CoalesceSubRegClass.ll
@@ -0,0 +1,25 @@
+; Coalescing from R32 to a subset R32_. Once another register coalescer bug is
+; fixed, the movb should go away as well.
+
+; RUN: llc < %s -march=x86 -relocation-model=static | \
+; RUN: grep movl
+
+@B = external global i32 ; <i32*> [#uses=2]
+@C = external global i16* ; <i16**> [#uses=2]
+
+define void @test(i32 %A) {
+ %A.upgrd.1 = trunc i32 %A to i8 ; <i8> [#uses=1]
+ %tmp2 = load i32* @B ; <i32> [#uses=1]
+ %tmp3 = and i8 %A.upgrd.1, 16 ; <i8> [#uses=1]
+ %shift.upgrd.2 = zext i8 %tmp3 to i32 ; <i32> [#uses=1]
+ %tmp4 = shl i32 %tmp2, %shift.upgrd.2 ; <i32> [#uses=1]
+ store i32 %tmp4, i32* @B
+ %tmp6 = lshr i32 %A, 3 ; <i32> [#uses=1]
+ %tmp = load i16** @C ; <i16*> [#uses=1]
+ %tmp8 = ptrtoint i16* %tmp to i32 ; <i32> [#uses=1]
+ %tmp9 = add i32 %tmp8, %tmp6 ; <i32> [#uses=1]
+ %tmp9.upgrd.3 = inttoptr i32 %tmp9 to i16* ; <i16*> [#uses=1]
+ store i16* %tmp9.upgrd.3, i16** @C
+ ret void
+}
+
diff --git a/test/CodeGen/X86/2006-05-08-InstrSched.ll b/test/CodeGen/X86/2006-05-08-InstrSched.ll
new file mode 100644
index 0000000..d58d638
--- /dev/null
+++ b/test/CodeGen/X86/2006-05-08-InstrSched.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86 -relocation-model=static | not grep {subl.*%esp}
+
+@A = external global i16* ; <i16**> [#uses=1]
+@B = external global i32 ; <i32*> [#uses=1]
+@C = external global i32 ; <i32*> [#uses=2]
+
+define void @test() {
+ %tmp = load i16** @A ; <i16*> [#uses=1]
+ %tmp1 = getelementptr i16* %tmp, i32 1 ; <i16*> [#uses=1]
+ %tmp.upgrd.1 = load i16* %tmp1 ; <i16> [#uses=1]
+ %tmp3 = zext i16 %tmp.upgrd.1 to i32 ; <i32> [#uses=1]
+ %tmp.upgrd.2 = load i32* @B ; <i32> [#uses=1]
+ %tmp4 = and i32 %tmp.upgrd.2, 16 ; <i32> [#uses=1]
+ %tmp5 = load i32* @C ; <i32> [#uses=1]
+ %tmp6 = trunc i32 %tmp4 to i8 ; <i8> [#uses=2]
+ %shift.upgrd.3 = zext i8 %tmp6 to i32 ; <i32> [#uses=1]
+ %tmp7 = shl i32 %tmp5, %shift.upgrd.3 ; <i32> [#uses=1]
+ %tmp9 = xor i8 %tmp6, 16 ; <i8> [#uses=1]
+ %shift.upgrd.4 = zext i8 %tmp9 to i32 ; <i32> [#uses=1]
+ %tmp11 = lshr i32 %tmp3, %shift.upgrd.4 ; <i32> [#uses=1]
+ %tmp12 = or i32 %tmp11, %tmp7 ; <i32> [#uses=1]
+ store i32 %tmp12, i32* @C
+ ret void
+}
+
diff --git a/test/CodeGen/X86/2006-05-11-InstrSched.ll b/test/CodeGen/X86/2006-05-11-InstrSched.ll
new file mode 100644
index 0000000..bdbe713
--- /dev/null
+++ b/test/CodeGen/X86/2006-05-11-InstrSched.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -stats -realign-stack=0 |&\
+; RUN: grep {asm-printer} | grep 31
+
+target datalayout = "e-p:32:32"
+define void @foo(i32* %mc, i32* %bp, i32* %ms, i32* %xmb, i32* %mpp, i32* %tpmm, i32* %ip, i32* %tpim, i32* %dpp, i32* %tpdm, i32* %bpi, i32 %M) nounwind {
+entry:
+ %tmp9 = icmp slt i32 %M, 5 ; <i1> [#uses=1]
+ br i1 %tmp9, label %return, label %cond_true
+
+cond_true: ; preds = %cond_true, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %cond_true ] ; <i32> [#uses=2]
+ %tmp. = shl i32 %indvar, 2 ; <i32> [#uses=1]
+ %tmp.10 = add nsw i32 %tmp., 1 ; <i32> [#uses=2]
+ %tmp31 = add nsw i32 %tmp.10, -1 ; <i32> [#uses=4]
+ %tmp32 = getelementptr i32* %mpp, i32 %tmp31 ; <i32*> [#uses=1]
+ %tmp34 = bitcast i32* %tmp32 to <16 x i8>* ; <i8*> [#uses=1]
+ %tmp = load <16 x i8>* %tmp34, align 1
+ %tmp42 = getelementptr i32* %tpmm, i32 %tmp31 ; <i32*> [#uses=1]
+ %tmp42.upgrd.1 = bitcast i32* %tmp42 to <4 x i32>* ; <<4 x i32>*> [#uses=1]
+ %tmp46 = load <4 x i32>* %tmp42.upgrd.1 ; <<4 x i32>> [#uses=1]
+ %tmp54 = bitcast <16 x i8> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp55 = add <4 x i32> %tmp54, %tmp46 ; <<4 x i32>> [#uses=2]
+ %tmp55.upgrd.2 = bitcast <4 x i32> %tmp55 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp62 = getelementptr i32* %ip, i32 %tmp31 ; <i32*> [#uses=1]
+ %tmp65 = bitcast i32* %tmp62 to <16 x i8>* ; <i8*> [#uses=1]
+ %tmp66 = load <16 x i8>* %tmp65, align 1
+ %tmp73 = getelementptr i32* %tpim, i32 %tmp31 ; <i32*> [#uses=1]
+ %tmp73.upgrd.3 = bitcast i32* %tmp73 to <4 x i32>* ; <<4 x i32>*> [#uses=1]
+ %tmp77 = load <4 x i32>* %tmp73.upgrd.3 ; <<4 x i32>> [#uses=1]
+ %tmp87 = bitcast <16 x i8> %tmp66 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp88 = add <4 x i32> %tmp87, %tmp77 ; <<4 x i32>> [#uses=2]
+ %tmp88.upgrd.4 = bitcast <4 x i32> %tmp88 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp99 = tail call <4 x i32> @llvm.x86.sse2.pcmpgt.d( <4 x i32> %tmp88, <4 x i32> %tmp55 ) ; <<4 x i32>> [#uses=1]
+ %tmp99.upgrd.5 = bitcast <4 x i32> %tmp99 to <2 x i64> ; <<2 x i64>> [#uses=2]
+ %tmp110 = xor <2 x i64> %tmp99.upgrd.5, < i64 -1, i64 -1 > ; <<2 x i64>> [#uses=1]
+ %tmp111 = and <2 x i64> %tmp110, %tmp55.upgrd.2 ; <<2 x i64>> [#uses=1]
+ %tmp121 = and <2 x i64> %tmp99.upgrd.5, %tmp88.upgrd.4 ; <<2 x i64>> [#uses=1]
+ %tmp131 = or <2 x i64> %tmp121, %tmp111 ; <<2 x i64>> [#uses=1]
+ %tmp137 = getelementptr i32* %mc, i32 %tmp.10 ; <i32*> [#uses=1]
+ %tmp137.upgrd.7 = bitcast i32* %tmp137 to <2 x i64>* ; <<2 x i64>*> [#uses=1]
+ store <2 x i64> %tmp131, <2 x i64>* %tmp137.upgrd.7
+ %tmp147 = add nsw i32 %tmp.10, 8 ; <i32> [#uses=1]
+ %tmp.upgrd.8 = icmp slt i32 %tmp147, %M ; <i1> [#uses=1]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br i1 %tmp.upgrd.8, label %cond_true, label %return
+
+return: ; preds = %cond_true, %entry
+ ret void
+}
+
+declare <4 x i32> @llvm.x86.sse2.pcmpgt.d(<4 x i32>, <4 x i32>)
diff --git a/test/CodeGen/X86/2006-05-17-VectorArg.ll b/test/CodeGen/X86/2006-05-17-VectorArg.ll
new file mode 100644
index 0000000..b36d61e
--- /dev/null
+++ b/test/CodeGen/X86/2006-05-17-VectorArg.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+
+define <4 x float> @opRSQ(<4 x float> %a) nounwind {
+entry:
+ %tmp2 = extractelement <4 x float> %a, i32 3 ; <float> [#uses=2]
+ %abscond = fcmp oge float %tmp2, -0.000000e+00 ; <i1> [#uses=1]
+ %abs = select i1 %abscond, float %tmp2, float 0.000000e+00 ; <float> [#uses=1]
+ %tmp3 = tail call float @llvm.sqrt.f32( float %abs ) ; <float> [#uses=1]
+ %tmp4 = fdiv float 1.000000e+00, %tmp3 ; <float> [#uses=1]
+ %tmp11 = insertelement <4 x float> zeroinitializer, float %tmp4, i32 3 ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp11
+}
+
+declare float @llvm.sqrt.f32(float)
+
diff --git a/test/CodeGen/X86/2006-05-22-FPSetEQ.ll b/test/CodeGen/X86/2006-05-22-FPSetEQ.ll
new file mode 100644
index 0000000..083d068
--- /dev/null
+++ b/test/CodeGen/X86/2006-05-22-FPSetEQ.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 | grep setnp
+; RUN: llc < %s -march=x86 -enable-unsafe-fp-math | \
+; RUN: not grep setnp
+
+define i32 @test(float %f) {
+ %tmp = fcmp oeq float %f, 0.000000e+00 ; <i1> [#uses=1]
+ %tmp.upgrd.1 = zext i1 %tmp to i32 ; <i32> [#uses=1]
+ ret i32 %tmp.upgrd.1
+}
+
diff --git a/test/CodeGen/X86/2006-05-25-CycleInDAG.ll b/test/CodeGen/X86/2006-05-25-CycleInDAG.ll
new file mode 100644
index 0000000..0288278
--- /dev/null
+++ b/test/CodeGen/X86/2006-05-25-CycleInDAG.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86
+
+define i32 @test() {
+ br i1 false, label %cond_next33, label %cond_true12
+cond_true12: ; preds = %0
+ ret i32 0
+cond_next33: ; preds = %0
+ %tmp44.i = call double @foo( double 0.000000e+00, i32 32 ) ; <double> [#uses=1]
+ %tmp61.i = load i8* null ; <i8> [#uses=1]
+ %tmp61.i.upgrd.1 = zext i8 %tmp61.i to i32 ; <i32> [#uses=1]
+ %tmp58.i = or i32 0, %tmp61.i.upgrd.1 ; <i32> [#uses=1]
+ %tmp62.i = or i32 %tmp58.i, 0 ; <i32> [#uses=1]
+ %tmp62.i.upgrd.2 = sitofp i32 %tmp62.i to double ; <double> [#uses=1]
+ %tmp64.i = fadd double %tmp62.i.upgrd.2, %tmp44.i ; <double> [#uses=1]
+ %tmp68.i = call double @foo( double %tmp64.i, i32 0 ) ; <double> [#uses=0]
+ ret i32 0
+}
+
+declare double @foo(double, i32)
+
diff --git a/test/CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll b/test/CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
new file mode 100644
index 0000000..4ea364d
--- /dev/null
+++ b/test/CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86
+; PR825
+
+define i64 @test() {
+ %tmp.i5 = call i64 asm sideeffect "rdtsc", "=A,~{dirflag},~{fpsr},~{flags}"( ) ; <i64> [#uses=1]
+ ret i64 %tmp.i5
+}
+
diff --git a/test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll b/test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll
new file mode 100644
index 0000000..568fbbc
--- /dev/null
+++ b/test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86
+; PR828
+
+target datalayout = "e-p:32:32"
+target triple = "i686-pc-linux-gnu"
+
+define void @_ZN5() {
+cond_true9:
+ %tmp3.i.i = call i32 asm sideeffect "lock; cmpxchg $1,$2", "={ax},q,m,0,~{dirflag},~{fpsr},~{flags},~{memory}"( i32 0, i32* null, i32 0 ) ; <i32> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/X86/2006-07-19-ATTAsm.ll b/test/CodeGen/X86/2006-07-19-ATTAsm.ll
new file mode 100644
index 0000000..c8fd10f
--- /dev/null
+++ b/test/CodeGen/X86/2006-07-19-ATTAsm.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=att
+; PR834
+; END.
+
+target datalayout = "e-p:32:32"
+target triple = "i386-unknown-freebsd6.1"
+ %llvm.dbg.anchor.type = type { i32, i32 }
+ %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 }
+ %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8* }
+ %llvm.dbg.global_variable.type = type { i32, { }*, { }*, i8*, i8 *, i8*, { }*, i32, { }*, i1, i1, { }* }
+@x = global i32 0 ; <i32*> [#uses=1]
[email protected]_variable = internal constant %llvm.dbg.global_variable.type {
+ i32 327732,
+ { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.global_variables to { }*),
+ { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*),
+ i8* getelementptr ([2 x i8]* @str, i64 0, i64 0),
+ i8* getelementptr ([2 x i8]* @str, i64 0, i64 0),
+ i8* null,
+ { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*),
+ i32 1,
+ { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*),
+ i1 false,
+ i1 true,
+ { }* bitcast (i32* @x to { }*) }, section "llvm.metadata" ; <%llvm.dbg.global_variable.type*> [#uses=0]
[email protected]_variables = linkonce constant %llvm.dbg.anchor.type { i32 327680, i32 52 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1]
[email protected]_unit = internal constant %llvm.dbg.compile_unit.type {
+ i32 327697,
+ { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*),
+ i32 4,
+ i8* getelementptr ([10 x i8]* @str1, i64 0, i64 0),
+ i8* getelementptr ([32 x i8]* @str2, i64 0, i64 0),
+ i8* getelementptr ([45 x i8]* @str3, i64 0, i64 0) }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1]
[email protected]_units = linkonce constant %llvm.dbg.anchor.type { i32 327680, i32 17 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1]
+@str1 = internal constant [10 x i8] c"testb.cpp\00", section "llvm.metadata" ; <[10 x i8]*> [#uses=1]
+@str2 = internal constant [32 x i8] c"/Sources/Projects/DwarfTesting/\00", section "llvm.metadata" ; <[32 x i8]*> [#uses=1]
+@str3 = internal constant [45 x i8] c"4.0.1 LLVM (Apple Computer, Inc. build 5400)\00", section "llvm.metadata" ; <[45 x i8]*> [#uses=1]
+@str = internal constant [2 x i8] c"x\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1]
[email protected] = internal constant %llvm.dbg.basictype.type {
+ i32 327716,
+ { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*),
+ i8* getelementptr ([4 x i8]* @str4, i64 0, i64 0),
+ { }* null,
+ i32 0,
+ i64 32,
+ i64 32,
+ i64 0,
+ i32 0,
+ i32 5 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1]
+@str4 = internal constant [4 x i8] c"int\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1]
diff --git a/test/CodeGen/X86/2006-07-20-InlineAsm.ll b/test/CodeGen/X86/2006-07-20-InlineAsm.ll
new file mode 100644
index 0000000..cac47cd
--- /dev/null
+++ b/test/CodeGen/X86/2006-07-20-InlineAsm.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86
+; PR833
+
+@G = weak global i32 0 ; <i32*> [#uses=3]
+
+define i32 @foo(i32 %X) {
+entry:
+ %X_addr = alloca i32 ; <i32*> [#uses=3]
+ store i32 %X, i32* %X_addr
+ call void asm sideeffect "xchg{l} {$0,$1|$1,$0}", "=*m,=*r,m,1,~{dirflag},~{fpsr},~{flags}"( i32* @G, i32* %X_addr, i32* @G, i32 %X )
+ %tmp1 = load i32* %X_addr ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32 @foo2(i32 %X) {
+entry:
+ %X_addr = alloca i32 ; <i32*> [#uses=3]
+ store i32 %X, i32* %X_addr
+ call void asm sideeffect "xchg{l} {$0,$1|$1,$0}", "=*m,=*r,1,~{dirflag},~{fpsr},~{flags}"( i32* @G, i32* %X_addr, i32 %X )
+ %tmp1 = load i32* %X_addr ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
diff --git a/test/CodeGen/X86/2006-07-28-AsmPrint-Long-As-Pointer.ll b/test/CodeGen/X86/2006-07-28-AsmPrint-Long-As-Pointer.ll
new file mode 100644
index 0000000..deae086
--- /dev/null
+++ b/test/CodeGen/X86/2006-07-28-AsmPrint-Long-As-Pointer.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=x86 | grep -- 4294967240
+; PR853
+
+@X = global i32* inttoptr (i64 -56 to i32*) ; <i32**> [#uses=0]
+
diff --git a/test/CodeGen/X86/2006-07-31-SingleRegClass.ll b/test/CodeGen/X86/2006-07-31-SingleRegClass.ll
new file mode 100644
index 0000000..3159cec
--- /dev/null
+++ b/test/CodeGen/X86/2006-07-31-SingleRegClass.ll
@@ -0,0 +1,10 @@
+; PR850
+; RUN: llc < %s -march=x86 -x86-asm-syntax=att > %t
+; RUN: grep {movl 4(%eax),%ebp} %t
+; RUN: grep {movl 0(%eax), %ebx} %t
+
+define i32 @foo(i32 %__s.i.i, i32 %tmp5.i.i, i32 %tmp6.i.i, i32 %tmp7.i.i, i32 %tmp8.i.i) {
+ %tmp9.i.i = call i32 asm sideeffect "push %ebp\0Apush %ebx\0Amovl 4($2),%ebp\0Amovl 0($2), %ebx\0Amovl $1,%eax\0Aint $$0x80\0Apop %ebx\0Apop %ebp", "={ax},i,0,{cx},{dx},{si},{di}"( i32 192, i32 %__s.i.i, i32 %tmp5.i.i, i32 %tmp6.i.i, i32 %tmp7.i.i, i32 %tmp8.i.i ) ; <i32> [#uses=1]
+ ret i32 %tmp9.i.i
+}
+
diff --git a/test/CodeGen/X86/2006-08-07-CycleInDAG.ll b/test/CodeGen/X86/2006-08-07-CycleInDAG.ll
new file mode 100644
index 0000000..aea707e
--- /dev/null
+++ b/test/CodeGen/X86/2006-08-07-CycleInDAG.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+ %struct.foo = type opaque
+
+define fastcc i32 @test(%struct.foo* %v, %struct.foo* %vi) {
+ br i1 false, label %ilog2.exit, label %cond_true.i
+
+cond_true.i: ; preds = %0
+ ret i32 0
+
+ilog2.exit: ; preds = %0
+ %tmp24.i = load i32* null ; <i32> [#uses=1]
+ %tmp13.i12.i = tail call double @ldexp( double 0.000000e+00, i32 0 ) ; <double> [#uses=1]
+ %tmp13.i13.i = fptrunc double %tmp13.i12.i to float ; <float> [#uses=1]
+ %tmp11.s = load i32* null ; <i32> [#uses=1]
+ %tmp11.i = bitcast i32 %tmp11.s to i32 ; <i32> [#uses=1]
+ %n.i = bitcast i32 %tmp24.i to i32 ; <i32> [#uses=1]
+ %tmp13.i7 = mul i32 %tmp11.i, %n.i ; <i32> [#uses=1]
+ %tmp.i8 = tail call i8* @calloc( i32 %tmp13.i7, i32 4 ) ; <i8*> [#uses=0]
+ br i1 false, label %bb224.preheader.i, label %bb.i
+
+bb.i: ; preds = %ilog2.exit
+ ret i32 0
+
+bb224.preheader.i: ; preds = %ilog2.exit
+ %tmp165.i = fpext float %tmp13.i13.i to double ; <double> [#uses=0]
+ ret i32 0
+}
+
+declare i8* @calloc(i32, i32)
+
+declare double @ldexp(double, i32)
diff --git a/test/CodeGen/X86/2006-08-16-CycleInDAG.ll b/test/CodeGen/X86/2006-08-16-CycleInDAG.ll
new file mode 100644
index 0000000..5fee326
--- /dev/null
+++ b/test/CodeGen/X86/2006-08-16-CycleInDAG.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86
+ %struct.expr = type { %struct.rtx_def*, i32, %struct.expr*, %struct.occr*, %struct.occr*, %struct.rtx_def* }
+ %struct.hash_table = type { %struct.expr**, i32, i32, i32 }
+ %struct.occr = type { %struct.occr*, %struct.rtx_def*, i8, i8 }
+ %struct.rtx_def = type { i16, i8, i8, %struct.u }
+ %struct.u = type { [1 x i64] }
+
+define void @test() {
+ %tmp = load i32* null ; <i32> [#uses=1]
+ %tmp8 = call i32 @hash_rtx( ) ; <i32> [#uses=1]
+ %tmp11 = urem i32 %tmp8, %tmp ; <i32> [#uses=1]
+ br i1 false, label %cond_next, label %return
+
+cond_next: ; preds = %0
+ %gep.upgrd.1 = zext i32 %tmp11 to i64 ; <i64> [#uses=1]
+ %tmp17 = getelementptr %struct.expr** null, i64 %gep.upgrd.1 ; <%struct.expr**> [#uses=0]
+ ret void
+
+return: ; preds = %0
+ ret void
+}
+
+declare i32 @hash_rtx()
diff --git a/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll b/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll
new file mode 100644
index 0000000..a19d8f7
--- /dev/null
+++ b/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 -mcpu=i386 | \
+; RUN: not grep {movl %eax, %edx}
+
+define i32 @foo(i32 %t, i32 %C) {
+entry:
+ br label %cond_true
+
+cond_true: ; preds = %cond_true, %entry
+ %t_addr.0.0 = phi i32 [ %t, %entry ], [ %tmp7, %cond_true ] ; <i32> [#uses=2]
+ %tmp7 = add i32 %t_addr.0.0, 1 ; <i32> [#uses=1]
+ %tmp = icmp sgt i32 %C, 39 ; <i1> [#uses=1]
+ br i1 %tmp, label %bb12, label %cond_true
+
+bb12: ; preds = %cond_true
+ ret i32 %t_addr.0.0
+}
+
diff --git a/test/CodeGen/X86/2006-09-01-CycleInDAG.ll b/test/CodeGen/X86/2006-09-01-CycleInDAG.ll
new file mode 100644
index 0000000..1e890bb
--- /dev/null
+++ b/test/CodeGen/X86/2006-09-01-CycleInDAG.ll
@@ -0,0 +1,131 @@
+; RUN: llc < %s -march=x86
+target datalayout = "e-p:32:32"
+target triple = "i686-apple-darwin8"
+ %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.VEC_edge = type { i32, i32, [1 x %struct.edge_def*] }
+ %struct.VEC_tree = type { i32, i32, [1 x %struct.tree_node*] }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+ %struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
+ %struct._var_map = type { %struct.partition_def*, i32*, i32*, %struct.tree_node**, i32, i32, i32* }
+ %struct.basic_block_def = type { %struct.rtx_def*, %struct.rtx_def*, %struct.tree_node*, %struct.VEC_edge*, %struct.VEC_edge*, %struct.bitmap_head_def*, %struct.bitmap_head_def*, i8*, %struct.loop*, [2 x %struct.et_node*], %struct.basic_block_def*, %struct.basic_block_def*, %struct.reorder_block_def*, %struct.bb_ann_d*, i64, i32, i32, i32, i32 }
+ %struct.bb_ann_d = type { %struct.tree_node*, i8, %struct.edge_prediction* }
+ %struct.bitmap_element_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, [4 x i32] }
+ %struct.bitmap_head_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, %struct.bitmap_obstack* }
+ %struct.bitmap_iterator = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, i32 }
+ %struct.bitmap_obstack = type { %struct.bitmap_element_def*, %struct.bitmap_head_def*, %struct.obstack }
+ %struct.block_stmt_iterator = type { %struct.tree_stmt_iterator, %struct.basic_block_def* }
+ %struct.coalesce_list_d = type { %struct._var_map*, %struct.partition_pair_d**, i1 }
+ %struct.conflict_graph_def = type opaque
+ %struct.dataflow_d = type { %struct.varray_head_tag*, [2 x %struct.tree_node*] }
+ %struct.def_operand_ptr = type { %struct.tree_node** }
+ %struct.def_optype_d = type { i32, [1 x %struct.def_operand_ptr] }
+ %struct.die_struct = type opaque
+ %struct.edge_def = type { %struct.basic_block_def*, %struct.basic_block_def*, %struct.edge_def_insns, i8*, %struct.__sbuf*, i32, i32, i64, i32 }
+ %struct.edge_def_insns = type { %struct.rtx_def* }
+ %struct.edge_iterator = type { i32, %struct.VEC_edge** }
+ %struct.edge_prediction = type { %struct.edge_prediction*, %struct.edge_def*, i32, i32 }
+ %struct.eh_status = type opaque
+ %struct.elt_list = type opaque
+ %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.__sbuf, i32, i8*, %struct.rtx_def** }
+ %struct.et_node = type opaque
+ %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+ %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i1, i1, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.__sbuf, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 }
+ %struct.ht_identifier = type { i8*, i32, i32 }
+ %struct.initial_value_struct = type opaque
+ %struct.lang_decl = type opaque
+ %struct.lang_type = type opaque
+ %struct.language_function = type opaque
+ %struct.location_t = type { i8*, i32 }
+ %struct.loop = type opaque
+ %struct.machine_function = type { i32, i32, i8*, i32, i32 }
+ %struct.obstack = type { i32, %struct._obstack_chunk*, i8*, i8*, i8*, i32, i32, %struct._obstack_chunk* (i8*, i32)*, void (i8*, %struct._obstack_chunk*)*, i8*, i8 }
+ %struct.partition_def = type { i32, [1 x %struct.partition_elem] }
+ %struct.partition_elem = type { i32, %struct.partition_elem*, i32 }
+ %struct.partition_pair_d = type { i32, i32, i32, %struct.partition_pair_d* }
+ %struct.phi_arg_d = type { %struct.tree_node*, i1 }
+ %struct.pointer_set_t = type opaque
+ %struct.ptr_info_def = type { i8, %struct.bitmap_head_def*, %struct.tree_node* }
+ %struct.real_value = type opaque
+ %struct.reg_info_def = type opaque
+ %struct.reorder_block_def = type { %struct.rtx_def*, %struct.rtx_def*, %struct.basic_block_def*, %struct.basic_block_def*, %struct.basic_block_def*, i32, i32, i32 }
+ %struct.rtvec_def = type opaque
+ %struct.rtx_def = type opaque
+ %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
+ %struct.simple_bitmap_def = type { i32, i32, i32, [1 x i64] }
+ %struct.ssa_op_iter = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.stmt_operands_d*, i1 }
+ %struct.stmt_ann_d = type { %struct.tree_ann_common_d, i8, %struct.basic_block_def*, %struct.stmt_operands_d, %struct.dataflow_d*, %struct.bitmap_head_def*, i32 }
+ %struct.stmt_operands_d = type { %struct.def_optype_d*, %struct.def_optype_d*, %struct.v_may_def_optype_d*, %struct.vuse_optype_d*, %struct.v_may_def_optype_d* }
+ %struct.temp_slot = type opaque
+ %struct.tree_ann_common_d = type { i32, i8*, %struct.tree_node* }
+ %struct.tree_ann_d = type { %struct.stmt_ann_d }
+ %struct.tree_binfo = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.VEC_tree*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.VEC_tree }
+ %struct.tree_block = type { %struct.tree_common, i8, [3 x i8], %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node* }
+ %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_ann_d*, i8, i8, i8, i8, i8 }
+ %struct.tree_complex = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node* }
+ %struct.tree_decl = type { %struct.tree_common, %struct.__sbuf, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_decl_u1 = type { i64 }
+ %struct.tree_decl_u1_a = type { i32 }
+ %struct.tree_decl_u2 = type { %struct.function* }
+ %struct.tree_exp = type { %struct.tree_common, %struct.__sbuf*, i32, %struct.tree_node*, [1 x %struct.tree_node*] }
+ %struct.tree_identifier = type { %struct.tree_common, %struct.ht_identifier }
+ %struct.tree_int_cst = type { %struct.tree_common, %struct.tree_int_cst_lowhi }
+ %struct.tree_int_cst_lowhi = type { i64, i64 }
+ %struct.tree_list = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node* }
+ %struct.tree_live_info_d = type { %struct._var_map*, %struct.bitmap_head_def*, %struct.bitmap_head_def**, i32, %struct.bitmap_head_def** }
+ %struct.tree_node = type { %struct.tree_decl }
+ %struct.tree_partition_associator_d = type { %struct.varray_head_tag*, %struct.varray_head_tag*, i32*, i32*, i32, i32, %struct._var_map* }
+ %struct.tree_phi_node = type { %struct.tree_common, %struct.tree_node*, i32, i32, i32, %struct.basic_block_def*, %struct.dataflow_d*, [1 x %struct.phi_arg_d] }
+ %struct.tree_real_cst = type { %struct.tree_common, %struct.real_value* }
+ %struct.tree_ssa_name = type { %struct.tree_common, %struct.tree_node*, i32, %struct.ptr_info_def*, %struct.tree_node*, i8* }
+ %struct.tree_statement_list = type { %struct.tree_common, %struct.tree_statement_list_node*, %struct.tree_statement_list_node* }
+ %struct.tree_statement_list_node = type { %struct.tree_statement_list_node*, %struct.tree_statement_list_node*, %struct.tree_node* }
+ %struct.tree_stmt_iterator = type { %struct.tree_statement_list_node*, %struct.tree_node* }
+ %struct.tree_string = type { %struct.tree_common, i32, [1 x i8] }
+ %struct.tree_type = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i32, i16, i8, i8, i32, %struct.tree_node*, %struct.tree_node*, %struct.tree_decl_u1_a, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_type* }
+ %struct.tree_type_symtab = type { i32 }
+ %struct.tree_value_handle = type { %struct.tree_common, %struct.value_set*, i32 }
+ %struct.tree_vec = type { %struct.tree_common, i32, [1 x %struct.tree_node*] }
+ %struct.tree_vector = type { %struct.tree_common, %struct.tree_node* }
+ %struct.use_operand_ptr = type { %struct.tree_node** }
+ %struct.use_optype_d = type { i32, [1 x %struct.def_operand_ptr] }
+ %struct.v_def_use_operand_type_t = type { %struct.tree_node*, %struct.tree_node* }
+ %struct.v_may_def_optype_d = type { i32, [1 x %struct.v_def_use_operand_type_t] }
+ %struct.v_must_def_optype_d = type { i32, [1 x %struct.v_def_use_operand_type_t] }
+ %struct.value_set = type opaque
+ %struct.var_ann_d = type { %struct.tree_ann_common_d, i8, i8, %struct.tree_node*, %struct.varray_head_tag*, i32, i32, i32, %struct.tree_node*, %struct.tree_node* }
+ %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+ %struct.varasm_status = type opaque
+ %struct.varray_data = type { [1 x i64] }
+ %struct.varray_head_tag = type { i32, i32, i32, i8*, %struct.varray_data }
+ %struct.vuse_optype_d = type { i32, [1 x %struct.tree_node*] }
+@basic_block_info = external global %struct.varray_head_tag* ; <%struct.varray_head_tag**> [#uses=1]
+
+define void @calculate_live_on_entry_cond_true3632(%struct.varray_head_tag* %stack3023.6, i32* %tmp3629, %struct.VEC_edge*** %tmp3397.out) {
+newFuncRoot:
+ br label %cond_true3632
+
+bb3502.exitStub: ; preds = %cond_true3632
+ store %struct.VEC_edge** %tmp3397, %struct.VEC_edge*** %tmp3397.out
+ ret void
+
+cond_true3632: ; preds = %newFuncRoot
+ %tmp3378 = load i32* %tmp3629 ; <i32> [#uses=1]
+ %tmp3379 = add i32 %tmp3378, -1 ; <i32> [#uses=1]
+ %tmp3381 = getelementptr %struct.varray_head_tag* %stack3023.6, i32 0, i32 4 ; <%struct.varray_data*> [#uses=1]
+ %tmp3382 = bitcast %struct.varray_data* %tmp3381 to [1 x i32]* ; <[1 x i32]*> [#uses=1]
+ %gep.upgrd.1 = zext i32 %tmp3379 to i64 ; <i64> [#uses=1]
+ %tmp3383 = getelementptr [1 x i32]* %tmp3382, i32 0, i64 %gep.upgrd.1 ; <i32*> [#uses=1]
+ %tmp3384 = load i32* %tmp3383 ; <i32> [#uses=1]
+ %tmp3387 = load i32* %tmp3629 ; <i32> [#uses=1]
+ %tmp3388 = add i32 %tmp3387, -1 ; <i32> [#uses=1]
+ store i32 %tmp3388, i32* %tmp3629
+ %tmp3391 = load %struct.varray_head_tag** @basic_block_info ; <%struct.varray_head_tag*> [#uses=1]
+ %tmp3393 = getelementptr %struct.varray_head_tag* %tmp3391, i32 0, i32 4 ; <%struct.varray_data*> [#uses=1]
+ %tmp3394 = bitcast %struct.varray_data* %tmp3393 to [1 x %struct.basic_block_def*]* ; <[1 x %struct.basic_block_def*]*> [#uses=1]
+ %tmp3395 = getelementptr [1 x %struct.basic_block_def*]* %tmp3394, i32 0, i32 %tmp3384 ; <%struct.basic_block_def**> [#uses=1]
+ %tmp3396 = load %struct.basic_block_def** %tmp3395 ; <%struct.basic_block_def*> [#uses=1]
+ %tmp3397 = getelementptr %struct.basic_block_def* %tmp3396, i32 0, i32 3 ; <%struct.VEC_edge**> [#uses=1]
+ br label %bb3502.exitStub
+}
diff --git a/test/CodeGen/X86/2006-10-02-BoolRetCrash.ll b/test/CodeGen/X86/2006-10-02-BoolRetCrash.ll
new file mode 100644
index 0000000..795d464
--- /dev/null
+++ b/test/CodeGen/X86/2006-10-02-BoolRetCrash.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s
+; PR933
+
+define fastcc i1 @test() {
+ ret i1 true
+}
+
diff --git a/test/CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll b/test/CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll
new file mode 100644
index 0000000..bf9fa57
--- /dev/null
+++ b/test/CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mattr=sse | grep movaps
+; Test that the load is NOT folded into the intrinsic, which would zero the top
+; elts of the loaded vector.
+
+target datalayout = "e-p:32:32"
+target triple = "i686-apple-darwin8.7.2"
+
+define <4 x float> @test(<4 x float> %A, <4 x float>* %B) {
+ %BV = load <4 x float>* %B ; <<4 x float>> [#uses=1]
+ %tmp28 = tail call <4 x float> @llvm.x86.sse.sub.ss( <4 x float> %A, <4 x float> %BV ) ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp28
+}
+
+declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>)
+
diff --git a/test/CodeGen/X86/2006-10-09-CycleInDAG.ll b/test/CodeGen/X86/2006-10-09-CycleInDAG.ll
new file mode 100644
index 0000000..fbb14ee
--- /dev/null
+++ b/test/CodeGen/X86/2006-10-09-CycleInDAG.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86
+
+define void @_ZN13QFSFileEngine4readEPcx() {
+ %tmp201 = load i32* null ; <i32> [#uses=1]
+ %tmp201.upgrd.1 = sext i32 %tmp201 to i64 ; <i64> [#uses=1]
+ %tmp202 = load i64* null ; <i64> [#uses=1]
+ %tmp203 = add i64 %tmp201.upgrd.1, %tmp202 ; <i64> [#uses=1]
+ store i64 %tmp203, i64* null
+ ret void
+}
+
diff --git a/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.ll b/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.ll
new file mode 100644
index 0000000..b1f0451
--- /dev/null
+++ b/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=x86 | grep shrl
+; Bug in FindModifiedNodeSlot cause tmp14 load to become a zextload and shr 31
+; is then optimized away.
+@tree_code_type = external global [0 x i32] ; <[0 x i32]*> [#uses=1]
+
+define void @copy_if_shared_r() {
+ %tmp = load i32* null ; <i32> [#uses=1]
+ %tmp56 = and i32 %tmp, 255 ; <i32> [#uses=1]
+ %gep.upgrd.1 = zext i32 %tmp56 to i64 ; <i64> [#uses=1]
+ %tmp8 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %gep.upgrd.1 ; <i32*> [#uses=1]
+ %tmp9 = load i32* %tmp8 ; <i32> [#uses=1]
+ %tmp10 = add i32 %tmp9, -1 ; <i32> [#uses=1]
+ %tmp.upgrd.2 = icmp ugt i32 %tmp10, 2 ; <i1> [#uses=1]
+ %tmp14 = load i32* null ; <i32> [#uses=1]
+ %tmp15 = lshr i32 %tmp14, 31 ; <i32> [#uses=1]
+ %tmp15.upgrd.3 = trunc i32 %tmp15 to i8 ; <i8> [#uses=1]
+ %tmp16 = icmp ne i8 %tmp15.upgrd.3, 0 ; <i1> [#uses=1]
+ br i1 %tmp.upgrd.2, label %cond_false25, label %cond_true
+cond_true: ; preds = %0
+ br i1 %tmp16, label %cond_true17, label %cond_false
+cond_true17: ; preds = %cond_true
+ ret void
+cond_false: ; preds = %cond_true
+ ret void
+cond_false25: ; preds = %0
+ ret void
+}
+
diff --git a/test/CodeGen/X86/2006-10-12-CycleInDAG.ll b/test/CodeGen/X86/2006-10-12-CycleInDAG.ll
new file mode 100644
index 0000000..3b987ac
--- /dev/null
+++ b/test/CodeGen/X86/2006-10-12-CycleInDAG.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -march=x86
+ %struct.function = type opaque
+ %struct.lang_decl = type opaque
+ %struct.location_t = type { i8*, i32 }
+ %struct.rtx_def = type opaque
+ %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 }
+ %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_decl_u1 = type { i64 }
+ %struct.tree_decl_u2 = type { %struct.function* }
+ %struct.tree_node = type { %struct.tree_decl }
+ %union.tree_ann_d = type opaque
+
+define void @check_format_arg() {
+ br i1 false, label %cond_next196, label %bb12.preheader
+
+bb12.preheader: ; preds = %0
+ ret void
+
+cond_next196: ; preds = %0
+ br i1 false, label %cond_next330, label %cond_true304
+
+cond_true304: ; preds = %cond_next196
+ ret void
+
+cond_next330: ; preds = %cond_next196
+ br i1 false, label %cond_next472, label %bb441
+
+bb441: ; preds = %cond_next330
+ ret void
+
+cond_next472: ; preds = %cond_next330
+ %tmp490 = load %struct.tree_node** null ; <%struct.tree_node*> [#uses=1]
+ %tmp492 = getelementptr %struct.tree_node* %tmp490, i32 0, i32 0, i32 0, i32 3 ; <i8*> [#uses=1]
+ %tmp492.upgrd.1 = bitcast i8* %tmp492 to i32* ; <i32*> [#uses=1]
+ %tmp493 = load i32* %tmp492.upgrd.1 ; <i32> [#uses=1]
+ %tmp495 = trunc i32 %tmp493 to i8 ; <i8> [#uses=1]
+ %tmp496 = icmp eq i8 %tmp495, 11 ; <i1> [#uses=1]
+ %tmp496.upgrd.2 = zext i1 %tmp496 to i8 ; <i8> [#uses=1]
+ store i8 %tmp496.upgrd.2, i8* null
+ ret void
+}
diff --git a/test/CodeGen/X86/2006-10-13-CycleInDAG.ll b/test/CodeGen/X86/2006-10-13-CycleInDAG.ll
new file mode 100644
index 0000000..6ed2e7b
--- /dev/null
+++ b/test/CodeGen/X86/2006-10-13-CycleInDAG.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86
+@str = external global [18 x i8] ; <[18 x i8]*> [#uses=1]
+
+define void @test() {
+bb.i:
+ %tmp.i660 = load <4 x float>* null ; <<4 x float>> [#uses=1]
+ call void (i32, ...)* @printf( i32 0, i8* getelementptr ([18 x i8]* @str, i32 0, i64 0), double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00 )
+ %tmp152.i = load <4 x i32>* null ; <<4 x i32>> [#uses=1]
+ %tmp156.i = bitcast <4 x i32> %tmp152.i to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp175.i = bitcast <4 x float> %tmp.i660 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp176.i = xor <4 x i32> %tmp156.i, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %tmp177.i = and <4 x i32> %tmp176.i, %tmp175.i ; <<4 x i32>> [#uses=1]
+ %tmp190.i = or <4 x i32> %tmp177.i, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %tmp191.i = bitcast <4 x i32> %tmp190.i to <4 x float> ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp191.i, <4 x float>* null
+ ret void
+}
+
+declare void @printf(i32, ...)
diff --git a/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll b/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
new file mode 100644
index 0000000..88e8b4a
--- /dev/null
+++ b/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=x86 -asm-verbose | FileCheck %s
+
+@str = internal constant [14 x i8] c"Hello world!\0A\00" ; <[14 x i8]*> [#uses=1]
[email protected] = internal constant [13 x i8] c"Blah world!\0A\00" ; <[13 x i8]*> [#uses=1]
+
+define i32 @test(i32 %argc, i8** %argv) nounwind {
+entry:
+; CHECK: cmpl $2
+; CHECK-NEXT: je
+; CHECK-NEXT: %entry
+
+ switch i32 %argc, label %UnifiedReturnBlock [
+ i32 1, label %bb
+ i32 2, label %bb2
+ ]
+
+bb: ; preds = %entry
+ %tmp1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([14 x i8]* @str, i32 0, i64 0) ) ; <i32> [#uses=0]
+ ret i32 0
+
+bb2: ; preds = %entry
+ %tmp4 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([13 x i8]* @str.upgrd.1, i32 0, i64 0) ) ; <i32> [#uses=0]
+ ret i32 0
+
+UnifiedReturnBlock: ; preds = %entry
+ ret i32 0
+}
+
+declare i32 @printf(i8*, ...)
diff --git a/test/CodeGen/X86/2006-11-12-CSRetCC.ll b/test/CodeGen/X86/2006-11-12-CSRetCC.ll
new file mode 100644
index 0000000..91210ea
--- /dev/null
+++ b/test/CodeGen/X86/2006-11-12-CSRetCC.ll
@@ -0,0 +1,59 @@
+; RUN: llc < %s -march=x86 | grep {subl \$4, %esp}
+
+target triple = "i686-pc-linux-gnu"
+@str = internal constant [9 x i8] c"%f+%f*i\0A\00" ; <[9 x i8]*> [#uses=1]
+
+define i32 @main() {
+entry:
+ %retval = alloca i32, align 4 ; <i32*> [#uses=1]
+ %tmp = alloca { double, double }, align 16 ; <{ double, double }*> [#uses=4]
+ %tmp1 = alloca { double, double }, align 16 ; <{ double, double }*> [#uses=4]
+ %tmp2 = alloca { double, double }, align 16 ; <{ double, double }*> [#uses=3]
+ %pi = alloca double, align 8 ; <double*> [#uses=2]
+ %z = alloca { double, double }, align 16 ; <{ double, double }*> [#uses=4]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store double 0x400921FB54442D18, double* %pi
+ %tmp.upgrd.1 = load double* %pi ; <double> [#uses=1]
+ %real = getelementptr { double, double }* %tmp1, i64 0, i32 0 ; <double*> [#uses=1]
+ store double 0.000000e+00, double* %real
+ %real3 = getelementptr { double, double }* %tmp1, i64 0, i32 1 ; <double*> [#uses=1]
+ store double %tmp.upgrd.1, double* %real3
+ %tmp.upgrd.2 = getelementptr { double, double }* %tmp, i64 0, i32 0 ; <double*> [#uses=1]
+ %tmp4 = getelementptr { double, double }* %tmp1, i64 0, i32 0 ; <double*> [#uses=1]
+ %tmp5 = load double* %tmp4 ; <double> [#uses=1]
+ store double %tmp5, double* %tmp.upgrd.2
+ %tmp6 = getelementptr { double, double }* %tmp, i64 0, i32 1 ; <double*> [#uses=1]
+ %tmp7 = getelementptr { double, double }* %tmp1, i64 0, i32 1 ; <double*> [#uses=1]
+ %tmp8 = load double* %tmp7 ; <double> [#uses=1]
+ store double %tmp8, double* %tmp6
+ %tmp.upgrd.3 = bitcast { double, double }* %tmp to { i64, i64 }* ; <{ i64, i64 }*> [#uses=1]
+ %tmp.upgrd.4 = getelementptr { i64, i64 }* %tmp.upgrd.3, i64 0, i32 0 ; <i64*> [#uses=1]
+ %tmp.upgrd.5 = load i64* %tmp.upgrd.4 ; <i64> [#uses=1]
+ %tmp9 = bitcast { double, double }* %tmp to { i64, i64 }* ; <{ i64, i64 }*> [#uses=1]
+ %tmp10 = getelementptr { i64, i64 }* %tmp9, i64 0, i32 1 ; <i64*> [#uses=1]
+ %tmp11 = load i64* %tmp10 ; <i64> [#uses=1]
+ call void @cexp( { double, double }* sret %tmp2, i64 %tmp.upgrd.5, i64 %tmp11 )
+ %tmp12 = getelementptr { double, double }* %z, i64 0, i32 0 ; <double*> [#uses=1]
+ %tmp13 = getelementptr { double, double }* %tmp2, i64 0, i32 0 ; <double*> [#uses=1]
+ %tmp14 = load double* %tmp13 ; <double> [#uses=1]
+ store double %tmp14, double* %tmp12
+ %tmp15 = getelementptr { double, double }* %z, i64 0, i32 1 ; <double*> [#uses=1]
+ %tmp16 = getelementptr { double, double }* %tmp2, i64 0, i32 1 ; <double*> [#uses=1]
+ %tmp17 = load double* %tmp16 ; <double> [#uses=1]
+ store double %tmp17, double* %tmp15
+ %tmp18 = getelementptr { double, double }* %z, i64 0, i32 1 ; <double*> [#uses=1]
+ %tmp19 = load double* %tmp18 ; <double> [#uses=1]
+ %tmp20 = getelementptr { double, double }* %z, i64 0, i32 0 ; <double*> [#uses=1]
+ %tmp21 = load double* %tmp20 ; <double> [#uses=1]
+ %tmp.upgrd.6 = getelementptr [9 x i8]* @str, i32 0, i64 0 ; <i8*> [#uses=1]
+ %tmp.upgrd.7 = call i32 (i8*, ...)* @printf( i8* %tmp.upgrd.6, double %tmp21, double %tmp19 ) ; <i32> [#uses=0]
+ br label %return
+return: ; preds = %entry
+ %retval.upgrd.8 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval.upgrd.8
+}
+
+declare void @cexp({ double, double }* sret , i64, i64)
+
+declare i32 @printf(i8*, ...)
+
diff --git a/test/CodeGen/X86/2006-11-17-IllegalMove.ll b/test/CodeGen/X86/2006-11-17-IllegalMove.ll
new file mode 100644
index 0000000..e839d72
--- /dev/null
+++ b/test/CodeGen/X86/2006-11-17-IllegalMove.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: grep movb %t | count 2
+; RUN: grep {movzb\[wl\]} %t
+
+
+define void @handle_vector_size_attribute() nounwind {
+entry:
+ %tmp69 = load i32* null ; <i32> [#uses=1]
+ switch i32 %tmp69, label %bb84 [
+ i32 2, label %bb77
+ i32 1, label %bb77
+ ]
+
+bb77: ; preds = %entry, %entry
+ %tmp99 = udiv i64 0, 0 ; <i64> [#uses=1]
+ %tmp = load i8* null ; <i8> [#uses=1]
+ %tmp114 = icmp eq i64 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp114, label %cond_true115, label %cond_next136
+
+bb84: ; preds = %entry
+ ret void
+
+cond_true115: ; preds = %bb77
+ %tmp118 = load i8* null ; <i8> [#uses=1]
+ br i1 false, label %cond_next129, label %cond_true120
+
+cond_true120: ; preds = %cond_true115
+ %tmp127 = udiv i8 %tmp, %tmp118 ; <i8> [#uses=1]
+ %tmp127.upgrd.1 = zext i8 %tmp127 to i64 ; <i64> [#uses=1]
+ br label %cond_next129
+
+cond_next129: ; preds = %cond_true120, %cond_true115
+ %iftmp.30.0 = phi i64 [ %tmp127.upgrd.1, %cond_true120 ], [ 0, %cond_true115 ] ; <i64> [#uses=1]
+ %tmp132 = icmp eq i64 %iftmp.30.0, %tmp99 ; <i1> [#uses=1]
+ br i1 %tmp132, label %cond_false148, label %cond_next136
+
+cond_next136: ; preds = %cond_next129, %bb77
+ ret void
+
+cond_false148: ; preds = %cond_next129
+ ret void
+}
diff --git a/test/CodeGen/X86/2006-11-27-SelectLegalize.ll b/test/CodeGen/X86/2006-11-27-SelectLegalize.ll
new file mode 100644
index 0000000..ea2e6db
--- /dev/null
+++ b/test/CodeGen/X86/2006-11-27-SelectLegalize.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 | grep test.*1
+; PR1016
+
+define i32 @test(i32 %A, i32 %B, i32 %C) {
+ %a = trunc i32 %A to i1 ; <i1> [#uses=1]
+ %D = select i1 %a, i32 %B, i32 %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
diff --git a/test/CodeGen/X86/2006-11-28-Memcpy.ll b/test/CodeGen/X86/2006-11-28-Memcpy.ll
new file mode 100644
index 0000000..8c1573f
--- /dev/null
+++ b/test/CodeGen/X86/2006-11-28-Memcpy.ll
@@ -0,0 +1,34 @@
+; PR1022, PR1023
+; RUN: llc < %s -march=x86 | grep -- -573785174 | count 2
+; RUN: llc < %s -march=x86 | grep -E {movl _?bytes2} | count 1
+
+@fmt = constant [4 x i8] c"%x\0A\00" ; <[4 x i8]*> [#uses=2]
+@bytes = constant [4 x i8] c"\AA\BB\CC\DD" ; <[4 x i8]*> [#uses=1]
+@bytes2 = global [4 x i8] c"\AA\BB\CC\DD" ; <[4 x i8]*> [#uses=1]
+
+define i32 @test1() nounwind {
+ %y = alloca i32 ; <i32*> [#uses=2]
+ %c = bitcast i32* %y to i8* ; <i8*> [#uses=1]
+ %z = getelementptr [4 x i8]* @bytes, i32 0, i32 0 ; <i8*> [#uses=1]
+ call void @llvm.memcpy.i32( i8* %c, i8* %z, i32 4, i32 1 )
+ %r = load i32* %y ; <i32> [#uses=1]
+ %t = bitcast [4 x i8]* @fmt to i8* ; <i8*> [#uses=1]
+ %tmp = call i32 (i8*, ...)* @printf( i8* %t, i32 %r ) ; <i32> [#uses=0]
+ ret i32 0
+}
+
+define void @test2() nounwind {
+ %y = alloca i32 ; <i32*> [#uses=2]
+ %c = bitcast i32* %y to i8* ; <i8*> [#uses=1]
+ %z = getelementptr [4 x i8]* @bytes2, i32 0, i32 0 ; <i8*> [#uses=1]
+ call void @llvm.memcpy.i32( i8* %c, i8* %z, i32 4, i32 1 )
+ %r = load i32* %y ; <i32> [#uses=1]
+ %t = bitcast [4 x i8]* @fmt to i8* ; <i8*> [#uses=1]
+ %tmp = call i32 (i8*, ...)* @printf( i8* %t, i32 %r ) ; <i32> [#uses=0]
+ ret void
+}
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32)
+
+declare i32 @printf(i8*, ...)
+
diff --git a/test/CodeGen/X86/2006-12-16-InlineAsmCrash.ll b/test/CodeGen/X86/2006-12-16-InlineAsmCrash.ll
new file mode 100644
index 0000000..50a244b
--- /dev/null
+++ b/test/CodeGen/X86/2006-12-16-InlineAsmCrash.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=x86
+; PR1049
+target datalayout = "e-p:32:32"
+target triple = "i686-pc-linux-gnu"
+ %struct.QBasicAtomic = type { i32 }
+ %struct.QByteArray = type { %"struct.QByteArray::Data"* }
+ %"struct.QByteArray::Data" = type { %struct.QBasicAtomic, i32, i32, i8*, [1 x i8] }
+ %struct.QFactoryLoader = type { %struct.QObject }
+ %struct.QImageIOHandler = type { i32 (...)**, %struct.QImageIOHandlerPrivate* }
+ %struct.QImageIOHandlerPrivate = type opaque
+ %struct.QImageWriter = type { %struct.QImageWriterPrivate* }
+ %struct.QImageWriterPrivate = type { %struct.QByteArray, %struct.QFactoryLoader*, i1, %struct.QImageIOHandler*, i32, float, %struct.QString, %struct.QString, i32, %struct.QString, %struct.QImageWriter* }
+ %"struct.QList<QByteArray>" = type { %"struct.QList<QByteArray>::._20" }
+ %"struct.QList<QByteArray>::._20" = type { %struct.QListData }
+ %struct.QListData = type { %"struct.QListData::Data"* }
+ %"struct.QListData::Data" = type { %struct.QBasicAtomic, i32, i32, i32, i8, [1 x i8*] }
+ %struct.QObject = type { i32 (...)**, %struct.QObjectData* }
+ %struct.QObjectData = type { i32 (...)**, %struct.QObject*, %struct.QObject*, %"struct.QList<QByteArray>", i8, [3 x i8], i32, i32 }
+ %struct.QString = type { %"struct.QString::Data"* }
+ %"struct.QString::Data" = type { %struct.QBasicAtomic, i32, i32, i16*, i8, i8, [1 x i16] }
+
+define i1 @_ZNK12QImageWriter8canWriteEv() {
+ %tmp62 = load %struct.QImageWriterPrivate** null ; <%struct.QImageWriterPrivate*> [#uses=1]
+ %tmp = getelementptr %struct.QImageWriterPrivate* %tmp62, i32 0, i32 9 ; <%struct.QString*> [#uses=1]
+ %tmp75 = call %struct.QString* @_ZN7QStringaSERKS_( %struct.QString* %tmp, %struct.QString* null ) ; <%struct.QString*> [#uses=0]
+ call void asm sideeffect "lock\0Adecl $0\0Asetne 1", "=*m"( i32* null )
+ ret i1 false
+}
+
+declare %struct.QString* @_ZN7QStringaSERKS_(%struct.QString*, %struct.QString*)
diff --git a/test/CodeGen/X86/2006-12-19-IntelSyntax.ll b/test/CodeGen/X86/2006-12-19-IntelSyntax.ll
new file mode 100644
index 0000000..f81b303
--- /dev/null
+++ b/test/CodeGen/X86/2006-12-19-IntelSyntax.ll
@@ -0,0 +1,86 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel
+; PR1061
+target datalayout = "e-p:32:32"
+target triple = "i686-pc-linux-gnu"
+
+define void @bar(i32 %n) {
+entry:
+ switch i32 %n, label %bb12 [
+ i32 1, label %bb
+ i32 2, label %bb6
+ i32 4, label %bb7
+ i32 5, label %bb8
+ i32 6, label %bb10
+ i32 7, label %bb1
+ i32 8, label %bb3
+ i32 9, label %bb4
+ i32 10, label %bb9
+ i32 11, label %bb2
+ i32 12, label %bb5
+ i32 13, label %bb11
+ ]
+
+bb: ; preds = %entry
+ call void (...)* @foo1( )
+ ret void
+
+bb1: ; preds = %entry
+ call void (...)* @foo2( )
+ ret void
+
+bb2: ; preds = %entry
+ call void (...)* @foo6( )
+ ret void
+
+bb3: ; preds = %entry
+ call void (...)* @foo3( )
+ ret void
+
+bb4: ; preds = %entry
+ call void (...)* @foo4( )
+ ret void
+
+bb5: ; preds = %entry
+ call void (...)* @foo5( )
+ ret void
+
+bb6: ; preds = %entry
+ call void (...)* @foo1( )
+ ret void
+
+bb7: ; preds = %entry
+ call void (...)* @foo2( )
+ ret void
+
+bb8: ; preds = %entry
+ call void (...)* @foo6( )
+ ret void
+
+bb9: ; preds = %entry
+ call void (...)* @foo3( )
+ ret void
+
+bb10: ; preds = %entry
+ call void (...)* @foo4( )
+ ret void
+
+bb11: ; preds = %entry
+ call void (...)* @foo5( )
+ ret void
+
+bb12: ; preds = %entry
+ call void (...)* @foo6( )
+ ret void
+}
+
+declare void @foo1(...)
+
+declare void @foo2(...)
+
+declare void @foo6(...)
+
+declare void @foo3(...)
+
+declare void @foo4(...)
+
+declare void @foo5(...)
diff --git a/test/CodeGen/X86/2007-01-08-InstrSched.ll b/test/CodeGen/X86/2007-01-08-InstrSched.ll
new file mode 100644
index 0000000..317ed0a
--- /dev/null
+++ b/test/CodeGen/X86/2007-01-08-InstrSched.ll
@@ -0,0 +1,22 @@
+; PR1075
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -O3 | FileCheck %s
+
+define float @foo(float %x) nounwind {
+ %tmp1 = fmul float %x, 3.000000e+00
+ %tmp3 = fmul float %x, 5.000000e+00
+ %tmp5 = fmul float %x, 7.000000e+00
+ %tmp7 = fmul float %x, 1.100000e+01
+ %tmp10 = fadd float %tmp1, %tmp3
+ %tmp12 = fadd float %tmp10, %tmp5
+ %tmp14 = fadd float %tmp12, %tmp7
+ ret float %tmp14
+
+; CHECK: mulss LCPI1_3(%rip)
+; CHECK-NEXT: mulss LCPI1_0(%rip)
+; CHECK-NEXT: mulss LCPI1_1(%rip)
+; CHECK-NEXT: mulss LCPI1_2(%rip)
+; CHECK-NEXT: addss
+; CHECK-NEXT: addss
+; CHECK-NEXT: addss
+; CHECK-NEXT: ret
+}
diff --git a/test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll b/test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll
new file mode 100644
index 0000000..de226a1
--- /dev/null
+++ b/test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll
@@ -0,0 +1,19 @@
+; RUN: llc %s -o - -march=x86-64 | grep {(%rdi,%rax,8)}
+; RUN: llc %s -o - -march=x86-64 | not grep {addq.*8}
+
+define void @foo(double* %y) nounwind {
+entry:
+ br label %bb
+
+bb:
+ %i = phi i64 [ 0, %entry ], [ %k, %bb ]
+ %j = getelementptr double* %y, i64 %i
+ store double 0.000000e+00, double* %j
+ %k = add i64 %i, 1
+ %n = icmp eq i64 %k, 0
+ br i1 %n, label %return, label %bb
+
+return:
+ ret void
+}
+
diff --git a/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll b/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
new file mode 100644
index 0000000..5e7c0a7
--- /dev/null
+++ b/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
@@ -0,0 +1,462 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: grep leaq %t
+; RUN: not grep {,%rsp)} %t
+; PR1103
+
+target datalayout = "e-p:64:64"
+@i6000 = global [128 x i64] zeroinitializer, align 16
+
+
+define void @foo(i32* %a0, i32* %a1, i32* %a2, i32* %a3, i32* %a4, i32* %a5) {
+b:
+ %r = load i32* %a0
+ %r2 = load i32* %a1
+ %r4 = load i32* %a2
+ %r6 = load i32* %a3
+ %r8 = load i32* %a4
+ %r14 = load i32* %a5
+ %rx = sext i32 %r2 to i64
+ %r9 = sext i32 %r to i64
+ %r11 = add i64 %rx, 0
+ %ras = icmp slt i64 %r11, 0
+ %r12 = select i1 %ras, i64 0, i64 %r11
+ %r16 = sext i32 %r14 to i64
+ %r17 = sext i32 %r8 to i64
+ %r18 = sub i64 %r16, 0
+ %r19 = add i64 %r18, 0
+ %r20 = icmp slt i64 %r19, 0
+ %r19h = add i64 %r18, 0
+ %r22 = select i1 %r20, i64 1, i64 %r19h
+ %r23 = mul i64 %r22, 0
+ %r23a = trunc i64 %r23 to i32
+ %r24 = shl i32 %r23a, 0
+ %r25 = add i32 %r24, 0
+ %ras2 = alloca i8, i32 %r25, align 16
+ %r28 = getelementptr i8* %ras2, i32 0
+ %r38 = shl i64 %r12, 0
+ %s2013 = add i64 %r38, 0
+ %c22012 = getelementptr i8* %ras2, i64 %s2013
+ %r42 = shl i64 %r12, 0
+ %s2011 = add i64 %r42, 16
+ %c22010 = getelementptr i8* %ras2, i64 %s2011
+ %r50 = add i64 %r16, 0
+ %r51 = icmp slt i64 %r50, 0
+ %r50sh = shl i64 %r50, 0
+ %r50j = add i64 %r50sh, 0
+ %r54 = select i1 %r51, i64 0, i64 %r50j
+ %r56 = mul i64 %r54, %r12
+ %r28s = add i64 %r56, 16
+ %c2 = getelementptr i8* %ras2, i64 %r28s
+ %r60 = sub i32 %r2, %r
+ %r61 = icmp slt i32 %r60, 0
+ br i1 %r61, label %a29b, label %b63
+a29b:
+ %r155 = sub i32 %r6, %r4
+ %r156 = icmp slt i32 %r155, 0
+ br i1 %r156, label %a109b, label %b158
+b63:
+ %r66 = sext i32 %r60 to i64
+ %r67 = add i64 %r66, 0
+ %r76 = mul i64 %r17, 0
+ %r82 = add i64 %r76, 0
+ %r84 = icmp slt i64 %r67, 0
+ br i1 %r84, label %b85, label %a25b
+b85:
+ %e641 = phi i64 [ 0, %b63 ], [ %r129, %a25b ]
+ %r137 = icmp slt i64 %e641, 0
+ br i1 %r137, label %a25b140q, label %a29b
+a25b140q:
+ br label %a25b140
+a25b:
+ %w1989 = phi i64 [ 0, %b63 ], [ %v1990, %a25b ]
+ %e642 = shl i64 %w1989, 0
+ %r129 = add i64 %e642, 0
+ %r132 = add i64 %e642, 0
+ %r134 = icmp slt i64 %r132, 0
+ %v1990 = add i64 %w1989, 0
+ br i1 %r134, label %b85, label %a25b
+a25b140:
+ %w1982 = phi i64 [ 0, %a25b140q ], [ %v1983, %a25b140 ]
+ %r145 = add i64 %r82, 0
+ %v1983 = add i64 %w1982, 0
+ %u1987 = icmp slt i64 %v1983, 0
+ br i1 %u1987, label %a29b, label %a25b140
+b158:
+ %r161 = sext i32 %r to i64
+ %r163 = sext i32 %r4 to i64
+ br label %a29b173
+a29b173:
+ %w1964 = phi i64 [ 0, %b158 ], [ %v1973, %b1606 ]
+ %b1974 = mul i64 %r163, 0
+ %b1975 = add i64 %r161, 0
+ %b1976 = mul i64 %w1964, 0
+ %b1977 = add i64 %b1976, 0
+ %s761 = bitcast i64 %b1977 to i64
+ %b1980 = mul i64 %w1964, 0
+ %s661 = add i64 %b1980, 0
+ br i1 %r61, label %a33b, label %b179
+a33b:
+ %r328 = icmp slt i32 %r14, 0
+ %r335 = or i1 %r328, %r61
+ br i1 %r335, label %a50b, label %b341
+b179:
+ %r182 = sext i32 %r60 to i64
+ %r183 = add i64 %r182, 0
+ %r187 = icmp slt i64 %r183, 0
+ br i1 %r187, label %b188, label %a30b
+b188:
+ %e653 = phi i64 [ 0, %b179 ], [ %r283, %a30b ]
+ %r291 = icmp slt i64 %e653, 0
+ br i1 %r291, label %a30b294q, label %a33b
+a30b294q:
+ br label %a30b294
+a30b:
+ %w = phi i64 [ 0, %b179 ], [ %v, %a30b ]
+ %b2 = shl i64 %w, 0
+ %r283 = add i64 %b2, 0
+ %r286 = add i64 %b2, 0
+ %r288 = icmp slt i64 %r286, 0
+ %v = add i64 %w, 0
+ br i1 %r288, label %b188, label %a30b
+a30b294:
+ %w1847 = phi i64 [ 0, %a30b294q ], [ %v1848, %a30b294 ]
+ %v1848 = add i64 %w1847, 0
+ %u = icmp slt i64 %v1848, 0
+ br i1 %u, label %a33b, label %a30b294
+a50b:
+ %r814 = add i32 %r14, 0
+ %r815 = icmp slt i32 %r814, 0
+ %r817 = or i1 %r61, %r815
+ br i1 %r817, label %a57b, label %b820
+b341:
+ %w1874 = phi i64 [ 0, %a33b ], [ %v1880, %b463 ]
+ %d753 = bitcast i64 %w1874 to i64
+ %r343 = add i64 %s661, 0
+ %r346 = add i64 %r343, 0
+ %r347 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r346
+ %r348 = load float* %r347
+ %r352 = add i64 %r343, 0
+ %r353 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r352
+ %r354 = load float* %r353
+ %r362 = load float* bitcast ([128 x i64]* @i6000 to float*)
+ %r363 = fadd float 0.000000e+00, %r362
+ %r370 = load float* bitcast ([128 x i64]* @i6000 to float*)
+ %r376 = icmp slt i64 %r16, 0
+ br i1 %r376, label %b377, label %a35b
+b377:
+ %d753p = phi i64 [ %d753, %b341 ], [ %r411, %a35b ]
+ %s761p = phi i64 [ %s761, %b341 ], [ 322, %a35b ]
+ %e784 = phi i64 [ 0, %b341 ], [ %r454, %a35b ]
+ %s794 = add i64 %d753p, 0
+ %r462 = icmp slt i64 %e784, 0
+ br i1 %r462, label %a35b465, label %b463
+a35b:
+ %w1865 = phi i64 [ 0, %b341 ], [ %v1866, %a35b ]
+ %e785 = shl i64 %w1865, 0
+ %b1877 = mul i64 %w1865, 0
+ %s795 = add i64 %b1877, 0
+ %r399 = fadd float %r354, 0.000000e+00
+ %r402 = fadd float %r370, 0.000000e+00
+ %r403 = fadd float %r348, 0.000000e+00
+ %r411 = add i64 %s795, 0
+ %r431 = fadd float %r362, 0.000000e+00
+ %r454 = add i64 %e785, 0
+ %r457 = add i64 %e785, 0
+ %r459 = icmp slt i64 %r457, 0
+ %v1866 = add i64 %w1865, 0
+ br i1 %r459, label %b377, label %a35b
+b463:
+ %r506 = add i64 %d753, 0
+ %r511 = sext i32 %r60 to i64
+ %r512 = add i64 %r511, 0
+ %r513 = icmp slt i64 %r506, 0
+ %v1880 = add i64 %w1874, 0
+ br i1 %r513, label %b341, label %b514
+a35b465:
+ %r469 = add i64 %s794, 0
+ br label %b463
+b514:
+ %r525 = mul i64 %r17, 0
+ %r533 = add i64 %r525, 0
+ br label %b535
+b535:
+ %w1855 = phi i64 [ 0, %b514 ], [ %v1856, %b712 ]
+ %s923 = phi i64 [ 0, %b514 ], [ %r799, %b712 ]
+ %s933 = phi i64 [ %r533, %b514 ], [ %r795, %b712 ]
+ %r538 = add i64 %w1855, 0
+ %r539 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r538
+ %r540 = load float* %r539
+ %r551 = load float* bitcast ([128 x i64]* @i6000 to float*)
+ %r562 = sub i64 %s933, 0
+ %r564 = icmp slt i64 %r512, 0
+ br i1 %r564, label %b565, label %a45b
+b565:
+ %e944 = phi i64 [ 0, %b535 ], [ %r703, %a45b ]
+ %r711 = icmp slt i64 %e944, 0
+ br i1 %r711, label %a45b714, label %b712
+a45b:
+ %w1852 = phi i64 [ 0, %b535 ], [ %v1853, %a45b ]
+ %e945 = shl i64 %w1852, 0
+ %r609 = add i64 %r562, 0
+ %r703 = add i64 %e945, 0
+ %r706 = add i64 %e945, 0
+ %r708 = icmp slt i64 %r706, 0
+ %v1853 = add i64 %w1852, 0
+ br i1 %r708, label %b565, label %a45b
+b712:
+ %r795 = add i64 %rx, 0
+ %r799 = add i64 %s923, 0
+ %r802 = add i64 %w1855, 0
+ %r807 = icmp slt i64 %r802, 0
+ %v1856 = add i64 %w1855, 0
+ br i1 %r807, label %b535, label %a50b
+a45b714:
+ %r717 = add i64 %e944, 0
+ %r720 = add i64 %r717, 0
+ %r721 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r720
+ %r722 = load float* %r721
+ %r726 = add i64 %r717, 0
+ %r727 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r726
+ %r728 = load float* %r727
+ %r732 = add i64 %r717, 0
+ %r733 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r732
+ %r734 = load float* %r733
+ %r738 = add i64 %r717, 0
+ %r739 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r738
+ %r740 = load float* %r739
+ %r744 = add i64 %r717, 0
+ %r745 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r744
+ %r746 = load float* %r745
+ %r750 = add i64 %r717, 0
+ %r751 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r750
+ %r752 = load float* %r751
+ %r753 = fadd float %r752, %r746
+ %r754 = fadd float %r728, %r722
+ %r755 = fadd float %r734, %r754
+ %r756 = fadd float %r755, %r740
+ %r757 = fadd float %r753, %r756
+ %r759 = fadd float %r757, %r540
+ %r770 = add i64 %r717, 0
+ %r771 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r770
+ %r772 = load float* %r771
+ %r776 = add i64 %r717, 0
+ %r777 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r776
+ %r778 = load float* %r777
+ %r781 = fadd float %r363, %r772
+ %r782 = fadd float %r781, %r778
+ %r783 = fadd float %r551, %r782
+ br label %b712
+a57b:
+ br i1 %r335, label %a66b, label %b1086
+b820:
+ %r823 = sext i32 %r2 to i64
+ %r834 = sext i32 %r8 to i64
+ %r844 = add i64 %r16, 0
+ %r846 = sext i32 %r60 to i64
+ %r847 = add i64 %r846, 0
+ %r851 = load float* bitcast ([128 x i64]* @i6000 to float*)
+ %r856 = sub i64 %rx, 0
+ br label %b858
+b858:
+ %w1891 = phi i64 [ 0, %b820 ], [ %v1892, %b1016 ]
+ %s1193 = phi i64 [ 0, %b820 ], [ %r1068, %b1016 ]
+ %b1894 = mul i64 %r834, 0
+ %b1896 = shl i64 %r823, 0
+ %b1902 = mul i64 %w1891, 0
+ %s1173 = add i64 %b1902, 0
+ %r859 = add i64 %r856, 0
+ %r862 = add i64 %w1891, 0
+ %r863 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r862
+ %r864 = load float* %r863
+ %r868 = add i64 %w1891, 0
+ %r869 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r868
+ %r870 = load float* %r869
+ %r873 = sub i64 %r859, 0
+ %r876 = sub i64 %s1173, 0
+ %r878 = icmp slt i64 %r847, 0
+ br i1 %r878, label %b879, label %a53b
+b879:
+ %e1204 = phi i64 [ 0, %b858 ], [ %r1007, %a53b ]
+ %r1015 = icmp slt i64 %e1204, 0
+ br i1 %r1015, label %a53b1019q, label %b1016
+a53b1019q:
+ %b1888 = sub i64 %r846, 0
+ %b1889 = add i64 %b1888, 0
+ br label %a53b1019
+a53b:
+ %w1881 = phi i64 [ 0, %b858 ], [ %v1882, %a53b ]
+ %e1205 = shl i64 %w1881, 0
+ %r1007 = add i64 %e1205, 0
+ %r1010 = add i64 %e1205, 0
+ %r1012 = icmp slt i64 %r1010, 0
+ %v1882 = add i64 %w1881, 0
+ br i1 %r1012, label %b879, label %a53b
+b1016:
+ %r1068 = add i64 %s1193, 0
+ %r1071 = add i64 %w1891, 0
+ %r1073 = icmp slt i64 %r1071, %r844
+ %v1892 = add i64 %w1891, 0
+ br i1 %r1073, label %b858, label %a57b
+a53b1019:
+ %w1885 = phi i64 [ 0, %a53b1019q ], [ %v1886, %a53b1019 ]
+ %r1022 = add i64 %r876, 0
+ %r1024 = bitcast i8* %c2 to float*
+ %r1025 = add i64 %r1022, 0
+ %r1026 = getelementptr float* %r1024, i64 %r1025
+ %r1027 = load float* %r1026
+ %r1032 = add i64 %r873, 0
+ %r1033 = add i64 %r1032, 0
+ %r1034 = getelementptr float* %r1024, i64 %r1033
+ %r1035 = load float* %r1034
+ %r1037 = bitcast i8* %c22010 to float*
+ %r1040 = getelementptr float* %r1037, i64 %r1025
+ %r1044 = fadd float %r864, %r1035
+ %r1046 = fadd float %r870, %r1027
+ %r1047 = fadd float %r1044, %r1046
+ %r1048 = fadd float %r851, %r1047
+ %v1886 = add i64 %w1885, 0
+ %u1890 = icmp slt i64 %v1886, %b1889
+ br i1 %u1890, label %b1016, label %a53b1019
+a66b:
+ br i1 %r817, label %a93b, label %b1321
+b1086:
+ %r1089 = sext i32 %r2 to i64
+ %r1090 = add i64 %rx, 0
+ %r1096 = mul i64 %r9, 0
+ %r1101 = sext i32 %r8 to i64
+ %r1104 = add i64 %r1096, 0
+ %r1108 = sub i64 %r1104, 0
+ %r1110 = sext i32 %r60 to i64
+ %r1111 = add i64 %r1110, 0
+ %r1113 = sext i32 %r14 to i64
+ %r1114 = add i64 %r16, 0
+ br label %b1117
+b1117:
+ %w1915 = phi i64 [ 0, %b1086 ], [ %v1957, %b1263 ]
+ %d1353 = bitcast i64 %w1915 to i64
+ %r1120 = add i64 %s661, 0
+ %r1121 = add i64 %r1120, 0
+ %r1122 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r1121
+ %r1123 = load float* %r1122
+ %r1132 = bitcast i8* %c22012 to float*
+ %r1134 = getelementptr float* %r1132, i64 %w1915
+ %r1135 = load float* %r1134
+ %r1136 = fadd float %r1123, %r1135
+ %r1138 = icmp slt i64 %r1114, 0
+ br i1 %r1138, label %b1139, label %a63b
+b1139:
+ %e1364 = phi i64 [ 0, %b1117 ], [ %r1254, %a63b ]
+ %p1998 = phi i64 [ %s761, %b1117 ], [ %r1216, %a63b ]
+ %r1108p = phi i64 [ %r1108, %b1117 ], [ %r1219, %a63b ]
+ %p2004 = phi i64 [ %d1353, %b1117 ], [ %r1090, %a63b ]
+ %s1374 = phi i64 [ 0, %b1117 ], [ %r1251, %a63b ]
+ %s1384 = add i64 %r1108p, 0
+ %s1394 = add i64 %p1998, 0
+ %r1262 = icmp slt i64 %e1364, %r1114
+ br i1 %r1262, label %a63b1266q, label %b1263
+a63b1266q:
+ %b1947 = sub i64 %r1113, 0
+ %b1948 = add i64 %b1947, 0
+ br label %a63b1266
+a63b:
+ %w1904 = phi i64 [ 0, %b1117 ], [ %v1905, %a63b ]
+ %s1375 = phi i64 [ 0, %b1117 ], [ %r1251, %a63b ]
+ %b1906 = add i64 %r1089, 0
+ %b1907 = mul i64 %r1101, 0
+ %b1929 = mul i64 %w1904, 0
+ %s1395 = add i64 %b1929, 0
+ %e1365 = shl i64 %w1904, 0
+ %r1163 = add i64 %r1090, 0
+ %r1167 = add i64 %s1375, 0
+ %r1191 = add i64 %r1163, 0
+ %r1195 = add i64 %r1167, 0
+ %r1216 = add i64 %s1395, 0
+ %r1219 = add i64 %r1191, 0
+ %r1223 = add i64 %r1195, 0
+ %r1251 = add i64 %r1223, 0
+ %r1254 = add i64 %e1365, 0
+ %r1257 = add i64 %e1365, 0
+ %r1259 = icmp slt i64 %r1257, %r1114
+ %v1905 = add i64 %w1904, 0
+ br i1 %r1259, label %b1139, label %a63b
+b1263:
+ %r1306 = add i64 %d1353, 0
+ %r1308 = icmp slt i64 %r1306, %r1111
+ %v1957 = add i64 %w1915, 0
+ br i1 %r1308, label %b1117, label %a66b
+a63b1266:
+ %w1944 = phi i64 [ 0, %a63b1266q ], [ %v1945, %a63b1266 ]
+ %s1377 = phi i64 [ %s1374, %a63b1266q ], [ %r1297, %a63b1266 ]
+ %r1282 = fadd float %r1136, 0.000000e+00
+ %r1297 = add i64 %s1377, 0
+ %v1945 = add i64 %w1944, 0
+ %u1949 = icmp slt i64 %v1945, %b1948
+ br i1 %u1949, label %b1263, label %a63b1266
+a93b:
+ br i1 %r61, label %b1606, label %a97b
+b1321:
+ %r1331 = mul i64 %r17, 0
+ %r1339 = add i64 %r1331, 0
+ br label %b1342
+b1342:
+ %w1960 = phi i64 [ 0, %b1321 ], [ %v1961, %b1582 ]
+ %s1523 = phi i64 [ %r1339, %b1321 ], [ %r1587, %b1582 ]
+ %s1563 = phi i64 [ 0, %b1321 ], [ %r1591, %b1582 ]
+ %d1533 = bitcast i64 %w1960 to i64
+ %b1968 = mul i64 %w1960, 0
+ %s1543 = add i64 %b1968, 0
+ %r1345 = add i64 %s1523, 0
+ %r1348 = sub i64 %r1345, 0
+ %r1352 = add i64 %s1523, 0
+ %r1355 = sub i64 %r1352, 0
+ %r1370 = add i64 %d1533, 0
+ %r1371 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r1370
+ %r1372 = load float* %r1371
+ br label %a74b
+a74b:
+ %w1958 = phi i64 [ 0, %b1342 ], [ %v1959, %a74b ]
+ %r1379 = add i64 %s1543, 0
+ %r1403 = add i64 %r1355, 0
+ %r1422 = add i64 %r1348, 0
+ %r1526 = fadd float %r1372, 0.000000e+00
+ %r1573 = add i64 %w1958, 0
+ %r1581 = icmp slt i64 %r1573, 0
+ %v1959 = add i64 %w1958, 0
+ br i1 %r1581, label %a74b, label %b1582
+b1582:
+ %r1587 = add i64 %rx, 0
+ %r1591 = add i64 %s1563, 0
+ %r1596 = add i64 %d1533, 0
+ %r1601 = icmp slt i64 %r1596, 0
+ %v1961 = add i64 %w1960, 0
+ br i1 %r1601, label %b1342, label %a93b
+b1606:
+ %r1833 = add i64 %w1964, 0
+ %r1840 = icmp slt i64 %r1833, 0
+ %v1973 = add i64 %w1964, 0
+ br i1 %r1840, label %a29b173, label %a109b
+a97b:
+ %w1970 = phi i64 [ 0, %a93b ], [ %v1971, %a97b ]
+ %r1613 = add i64 %w1964, 0
+ %r1614 = mul i64 %r1613, 0
+ %r1622 = add i64 %r1614, 0
+ %r1754 = bitcast i8* %r28 to float*
+ %r1756 = getelementptr float* %r1754, i64 %w1970
+ %r1757 = load float* %r1756
+ %r1761 = add i64 %r1622, 0
+ %r1762 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r1761
+ %r1763 = load float* %r1762
+ %r1767 = add i64 %r1622, 0
+ %r1768 = getelementptr float* bitcast ([128 x i64]* @i6000 to float*), i64 %r1767
+ %r1772 = fadd float %r1763, 0.000000e+00
+ %r1773 = fadd float %r1772, 0.000000e+00
+ %r1809 = fadd float %r1757, 0.000000e+00
+ %r1810 = fadd float %r1773, %r1809
+ store float %r1810, float* %r1768
+ %r1818 = add i64 %w1970, 0
+ %r1826 = icmp slt i64 %r1818, 0
+ %v1971 = add i64 %w1970, 0
+ br i1 %r1826, label %a97b, label %b1606
+a109b:
+ ret void
+}
diff --git a/test/CodeGen/X86/2007-01-29-InlineAsm-ir.ll b/test/CodeGen/X86/2007-01-29-InlineAsm-ir.ll
new file mode 100644
index 0000000..e83e2e5
--- /dev/null
+++ b/test/CodeGen/X86/2007-01-29-InlineAsm-ir.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86
+; Test 'ri' constraint.
+
+define void @run_init_process() {
+ %tmp = call i32 asm sideeffect "push %ebx ; movl $2,%ebx ; int $$0x80 ; pop %ebx", "={ax},0,ri,{cx},{dx},~{dirflag},~{fpsr},~{flags},~{memory}"( i32 11, i32 0, i32 0, i32 0 )
+ unreachable
+ }
diff --git a/test/CodeGen/X86/2007-02-04-OrAddrMode.ll b/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
new file mode 100644
index 0000000..10bbe74
--- /dev/null
+++ b/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=x86 | grep {orl \$1, %eax}
+; RUN: llc < %s -march=x86 | grep {leal 3(,%eax,8)}
+
+;; This example can't fold the or into an LEA.
+define i32 @test(float ** %tmp2, i32 %tmp12) nounwind {
+ %tmp3 = load float** %tmp2
+ %tmp132 = shl i32 %tmp12, 2 ; <i32> [#uses=1]
+ %tmp4 = bitcast float* %tmp3 to i8* ; <i8*> [#uses=1]
+ %ctg2 = getelementptr i8* %tmp4, i32 %tmp132 ; <i8*> [#uses=1]
+ %tmp6 = ptrtoint i8* %ctg2 to i32 ; <i32> [#uses=1]
+ %tmp14 = or i32 %tmp6, 1 ; <i32> [#uses=1]
+ ret i32 %tmp14
+}
+
+
+;; This can!
+define i32 @test2(i32 %a, i32 %b) nounwind {
+ %c = shl i32 %a, 3
+ %d = or i32 %c, 3
+ ret i32 %d
+}
diff --git a/test/CodeGen/X86/2007-02-19-LiveIntervalAssert.ll b/test/CodeGen/X86/2007-02-19-LiveIntervalAssert.ll
new file mode 100644
index 0000000..954c95d
--- /dev/null
+++ b/test/CodeGen/X86/2007-02-19-LiveIntervalAssert.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu -relocation-model=pic
+; PR1027
+
+ %struct._IO_FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct._IO_FILE*, i32, i32, i32, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i32, i32, [40 x i8] }
+ %struct._IO_marker = type { %struct._IO_marker*, %struct._IO_FILE*, i32 }
+@stderr = external global %struct._IO_FILE*
+
+define void @__eprintf(i8* %string, i8* %expression, i32 %line, i8* %filename) {
+ %tmp = load %struct._IO_FILE** @stderr
+ %tmp5 = tail call i32 (%struct._IO_FILE*, i8*, ...)* @fprintf( %struct._IO_FILE* %tmp, i8* %string, i8* %expression, i32 %line, i8* %filename )
+ %tmp6 = load %struct._IO_FILE** @stderr
+ %tmp7 = tail call i32 @fflush( %struct._IO_FILE* %tmp6 )
+ tail call void @abort( )
+ unreachable
+}
+
+declare i32 @fprintf(%struct._IO_FILE*, i8*, ...)
+
+declare i32 @fflush(%struct._IO_FILE*)
+
+declare void @abort()
diff --git a/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll b/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll
new file mode 100644
index 0000000..a8f0e57
--- /dev/null
+++ b/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll
@@ -0,0 +1,13 @@
+; PR1219
+; RUN: llc < %s -march=x86 | grep {movl \$1, %eax}
+
+define i32 @test(i1 %X) {
+old_entry1:
+ %hvar2 = zext i1 %X to i32
+ %C = icmp sgt i32 %hvar2, -1
+ br i1 %C, label %cond_true15, label %cond_true
+cond_true15:
+ ret i32 1
+cond_true:
+ ret i32 2
+}
diff --git a/test/CodeGen/X86/2007-02-25-FastCCStack.ll b/test/CodeGen/X86/2007-02-25-FastCCStack.ll
new file mode 100644
index 0000000..2e2b56d
--- /dev/null
+++ b/test/CodeGen/X86/2007-02-25-FastCCStack.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=x86 -mcpu=pentium3
+
+define internal fastcc double @ggc_rlimit_bound(double %limit) {
+ ret double %limit
+}
diff --git a/test/CodeGen/X86/2007-03-01-SpillerCrash.ll b/test/CodeGen/X86/2007-03-01-SpillerCrash.ll
new file mode 100644
index 0000000..112d1ab
--- /dev/null
+++ b/test/CodeGen/X86/2007-03-01-SpillerCrash.ll
@@ -0,0 +1,86 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin8 -mattr=+sse2
+; RUN: llc < %s -mtriple=x86_64-apple-darwin8 -mattr=+sse2 | not grep movhlps
+
+define void @test() nounwind {
+test.exit:
+ fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:0 [#uses=4]
+ load <4 x float>* null ; <<4 x float>>:1 [#uses=1]
+ shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x float>>:2 [#uses=1]
+ fmul <4 x float> %0, %2 ; <<4 x float>>:3 [#uses=1]
+ fsub <4 x float> zeroinitializer, %3 ; <<4 x float>>:4 [#uses=1]
+ fmul <4 x float> %4, zeroinitializer ; <<4 x float>>:5 [#uses=2]
+ bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:6 [#uses=1]
+ and <4 x i32> %6, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>>:7 [#uses=1]
+ bitcast <4 x i32> %7 to <4 x float> ; <<4 x float>>:8 [#uses=2]
+ extractelement <4 x float> %8, i32 0 ; <float>:9 [#uses=1]
+ extractelement <4 x float> %8, i32 1 ; <float>:10 [#uses=2]
+ br i1 false, label %11, label %19
+
+; <label>:11 ; preds = %test.exit
+ br i1 false, label %17, label %12
+
+; <label>:12 ; preds = %11
+ br i1 false, label %19, label %13
+
+; <label>:13 ; preds = %12
+ fsub float -0.000000e+00, 0.000000e+00 ; <float>:14 [#uses=1]
+ %tmp207 = extractelement <4 x float> zeroinitializer, i32 0 ; <float> [#uses=1]
+ %tmp208 = extractelement <4 x float> zeroinitializer, i32 2 ; <float> [#uses=1]
+ fsub float -0.000000e+00, %tmp208 ; <float>:15 [#uses=1]
+ %tmp155 = extractelement <4 x float> zeroinitializer, i32 0 ; <float> [#uses=1]
+ %tmp156 = extractelement <4 x float> zeroinitializer, i32 2 ; <float> [#uses=1]
+ fsub float -0.000000e+00, %tmp156 ; <float>:16 [#uses=1]
+ br label %19
+
+; <label>:17 ; preds = %11
+ br i1 false, label %19, label %18
+
+; <label>:18 ; preds = %17
+ br label %19
+
+; <label>:19 ; preds = %18, %17, %13, %12, %test.exit
+ phi i32 [ 5, %18 ], [ 3, %13 ], [ 1, %test.exit ], [ 2, %12 ], [ 4, %17 ] ; <i32>:20 [#uses=0]
+ phi float [ 0.000000e+00, %18 ], [ %16, %13 ], [ 0.000000e+00, %test.exit ], [ 0.000000e+00, %12 ], [ 0.000000e+00, %17 ] ; <float>:21 [#uses=1]
+ phi float [ 0.000000e+00, %18 ], [ %tmp155, %13 ], [ 0.000000e+00, %test.exit ], [ 0.000000e+00, %12 ], [ 0.000000e+00, %17 ] ; <float>:22 [#uses=1]
+ phi float [ 0.000000e+00, %18 ], [ %15, %13 ], [ 0.000000e+00, %test.exit ], [ 0.000000e+00, %12 ], [ 0.000000e+00, %17 ] ; <float>:23 [#uses=1]
+ phi float [ 0.000000e+00, %18 ], [ %tmp207, %13 ], [ 0.000000e+00, %test.exit ], [ 0.000000e+00, %12 ], [ 0.000000e+00, %17 ] ; <float>:24 [#uses=1]
+ phi float [ 0.000000e+00, %18 ], [ %10, %13 ], [ %9, %test.exit ], [ %10, %12 ], [ 0.000000e+00, %17 ] ; <float>:25 [#uses=2]
+ phi float [ 0.000000e+00, %18 ], [ %14, %13 ], [ 0.000000e+00, %test.exit ], [ 0.000000e+00, %12 ], [ 0.000000e+00, %17 ] ; <float>:26 [#uses=1]
+ phi float [ 0.000000e+00, %18 ], [ 0.000000e+00, %13 ], [ 0.000000e+00, %test.exit ], [ 0.000000e+00, %12 ], [ 0.000000e+00, %17 ] ; <float>:27 [#uses=1]
+ insertelement <4 x float> undef, float %27, i32 0 ; <<4 x float>>:28 [#uses=1]
+ insertelement <4 x float> %28, float %26, i32 1 ; <<4 x float>>:29 [#uses=0]
+ insertelement <4 x float> undef, float %24, i32 0 ; <<4 x float>>:30 [#uses=1]
+ insertelement <4 x float> %30, float %23, i32 1 ; <<4 x float>>:31 [#uses=1]
+ insertelement <4 x float> %31, float %25, i32 2 ; <<4 x float>>:32 [#uses=1]
+ insertelement <4 x float> %32, float %25, i32 3 ; <<4 x float>>:33 [#uses=1]
+ fdiv <4 x float> %33, zeroinitializer ; <<4 x float>>:34 [#uses=1]
+ fmul <4 x float> %34, < float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01 > ; <<4 x float>>:35 [#uses=1]
+ insertelement <4 x float> undef, float %22, i32 0 ; <<4 x float>>:36 [#uses=1]
+ insertelement <4 x float> %36, float %21, i32 1 ; <<4 x float>>:37 [#uses=0]
+ br i1 false, label %foo.exit, label %38
+
+; <label>:38 ; preds = %19
+ extractelement <4 x float> %0, i32 0 ; <float>:39 [#uses=1]
+ fcmp ogt float %39, 0.000000e+00 ; <i1>:40 [#uses=1]
+ extractelement <4 x float> %0, i32 2 ; <float>:41 [#uses=1]
+ extractelement <4 x float> %0, i32 1 ; <float>:42 [#uses=1]
+ fsub float -0.000000e+00, %42 ; <float>:43 [#uses=2]
+ %tmp189 = extractelement <4 x float> %5, i32 2 ; <float> [#uses=1]
+ br i1 %40, label %44, label %46
+
+; <label>:44 ; preds = %38
+ fsub float -0.000000e+00, %tmp189 ; <float>:45 [#uses=0]
+ br label %foo.exit
+
+; <label>:46 ; preds = %38
+ %tmp192 = extractelement <4 x float> %5, i32 1 ; <float> [#uses=1]
+ fsub float -0.000000e+00, %tmp192 ; <float>:47 [#uses=1]
+ br label %foo.exit
+
+foo.exit: ; preds = %46, %44, %19
+ phi float [ 0.000000e+00, %44 ], [ %47, %46 ], [ 0.000000e+00, %19 ] ; <float>:48 [#uses=0]
+ phi float [ %43, %44 ], [ %43, %46 ], [ 0.000000e+00, %19 ] ; <float>:49 [#uses=0]
+ phi float [ 0.000000e+00, %44 ], [ %41, %46 ], [ 0.000000e+00, %19 ] ; <float>:50 [#uses=0]
+ shufflevector <4 x float> %35, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x float>>:51 [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll b/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll
new file mode 100644
index 0000000..4cac9b4
--- /dev/null
+++ b/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll
@@ -0,0 +1,73 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-darwin | \
+; RUN: grep push | count 3
+
+define void @foo(i8** %buf, i32 %size, i32 %col, i8* %p) {
+entry:
+ icmp sgt i32 %size, 0 ; <i1>:0 [#uses=1]
+ br i1 %0, label %bb.preheader, label %return
+
+bb.preheader: ; preds = %entry
+ %tmp5.sum72 = add i32 %col, 7 ; <i32> [#uses=1]
+ %tmp5.sum71 = add i32 %col, 5 ; <i32> [#uses=1]
+ %tmp5.sum70 = add i32 %col, 3 ; <i32> [#uses=1]
+ %tmp5.sum69 = add i32 %col, 2 ; <i32> [#uses=1]
+ %tmp5.sum68 = add i32 %col, 1 ; <i32> [#uses=1]
+ %tmp5.sum66 = add i32 %col, 4 ; <i32> [#uses=1]
+ %tmp5.sum = add i32 %col, 6 ; <i32> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %bb.preheader
+ %i.073.0 = phi i32 [ 0, %bb.preheader ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
+ %p_addr.076.0.rec = mul i32 %i.073.0, 9 ; <i32> [#uses=9]
+ %p_addr.076.0 = getelementptr i8* %p, i32 %p_addr.076.0.rec ; <i8*> [#uses=1]
+ %tmp2 = getelementptr i8** %buf, i32 %i.073.0 ; <i8**> [#uses=1]
+ %tmp3 = load i8** %tmp2 ; <i8*> [#uses=8]
+ %tmp5 = getelementptr i8* %tmp3, i32 %col ; <i8*> [#uses=1]
+ %tmp7 = load i8* %p_addr.076.0 ; <i8> [#uses=1]
+ store i8 %tmp7, i8* %tmp5
+ %p_addr.076.0.sum93 = add i32 %p_addr.076.0.rec, 1 ; <i32> [#uses=1]
+ %tmp11 = getelementptr i8* %p, i32 %p_addr.076.0.sum93 ; <i8*> [#uses=1]
+ %tmp13 = load i8* %tmp11 ; <i8> [#uses=1]
+ %tmp15 = getelementptr i8* %tmp3, i32 %tmp5.sum72 ; <i8*> [#uses=1]
+ store i8 %tmp13, i8* %tmp15
+ %p_addr.076.0.sum92 = add i32 %p_addr.076.0.rec, 2 ; <i32> [#uses=1]
+ %tmp17 = getelementptr i8* %p, i32 %p_addr.076.0.sum92 ; <i8*> [#uses=1]
+ %tmp19 = load i8* %tmp17 ; <i8> [#uses=1]
+ %tmp21 = getelementptr i8* %tmp3, i32 %tmp5.sum71 ; <i8*> [#uses=1]
+ store i8 %tmp19, i8* %tmp21
+ %p_addr.076.0.sum91 = add i32 %p_addr.076.0.rec, 3 ; <i32> [#uses=1]
+ %tmp23 = getelementptr i8* %p, i32 %p_addr.076.0.sum91 ; <i8*> [#uses=1]
+ %tmp25 = load i8* %tmp23 ; <i8> [#uses=1]
+ %tmp27 = getelementptr i8* %tmp3, i32 %tmp5.sum70 ; <i8*> [#uses=1]
+ store i8 %tmp25, i8* %tmp27
+ %p_addr.076.0.sum90 = add i32 %p_addr.076.0.rec, 4 ; <i32> [#uses=1]
+ %tmp29 = getelementptr i8* %p, i32 %p_addr.076.0.sum90 ; <i8*> [#uses=1]
+ %tmp31 = load i8* %tmp29 ; <i8> [#uses=1]
+ %tmp33 = getelementptr i8* %tmp3, i32 %tmp5.sum69 ; <i8*> [#uses=2]
+ store i8 %tmp31, i8* %tmp33
+ %p_addr.076.0.sum89 = add i32 %p_addr.076.0.rec, 5 ; <i32> [#uses=1]
+ %tmp35 = getelementptr i8* %p, i32 %p_addr.076.0.sum89 ; <i8*> [#uses=1]
+ %tmp37 = load i8* %tmp35 ; <i8> [#uses=1]
+ %tmp39 = getelementptr i8* %tmp3, i32 %tmp5.sum68 ; <i8*> [#uses=1]
+ store i8 %tmp37, i8* %tmp39
+ %p_addr.076.0.sum88 = add i32 %p_addr.076.0.rec, 6 ; <i32> [#uses=1]
+ %tmp41 = getelementptr i8* %p, i32 %p_addr.076.0.sum88 ; <i8*> [#uses=1]
+ %tmp43 = load i8* %tmp41 ; <i8> [#uses=1]
+ store i8 %tmp43, i8* %tmp33
+ %p_addr.076.0.sum87 = add i32 %p_addr.076.0.rec, 7 ; <i32> [#uses=1]
+ %tmp47 = getelementptr i8* %p, i32 %p_addr.076.0.sum87 ; <i8*> [#uses=1]
+ %tmp49 = load i8* %tmp47 ; <i8> [#uses=1]
+ %tmp51 = getelementptr i8* %tmp3, i32 %tmp5.sum66 ; <i8*> [#uses=1]
+ store i8 %tmp49, i8* %tmp51
+ %p_addr.076.0.sum = add i32 %p_addr.076.0.rec, 8 ; <i32> [#uses=1]
+ %tmp53 = getelementptr i8* %p, i32 %p_addr.076.0.sum ; <i8*> [#uses=1]
+ %tmp55 = load i8* %tmp53 ; <i8> [#uses=1]
+ %tmp57 = getelementptr i8* %tmp3, i32 %tmp5.sum ; <i8*> [#uses=1]
+ store i8 %tmp55, i8* %tmp57
+ %indvar.next = add i32 %i.073.0, 1 ; <i32> [#uses=2]
+ icmp eq i32 %indvar.next, %size ; <i1>:1 [#uses=1]
+ br i1 %1, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2007-03-16-InlineAsm.ll b/test/CodeGen/X86/2007-03-16-InlineAsm.ll
new file mode 100644
index 0000000..9580726
--- /dev/null
+++ b/test/CodeGen/X86/2007-03-16-InlineAsm.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=x86
+
+; ModuleID = 'a.bc'
+
+define i32 @foo(i32 %A, i32 %B) {
+entry:
+ %A_addr = alloca i32 ; <i32*> [#uses=2]
+ %B_addr = alloca i32 ; <i32*> [#uses=1]
+ %retval = alloca i32, align 4 ; <i32*> [#uses=2]
+ %tmp = alloca i32, align 4 ; <i32*> [#uses=2]
+ %ret = alloca i32, align 4 ; <i32*> [#uses=2]
+ "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %A, i32* %A_addr
+ store i32 %B, i32* %B_addr
+ %tmp1 = load i32* %A_addr ; <i32> [#uses=1]
+ %tmp2 = call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"( i32 7, i32 %tmp1 ) ; <i32> [#uses=1]
+ store i32 %tmp2, i32* %ret
+ %tmp3 = load i32* %ret ; <i32> [#uses=1]
+ store i32 %tmp3, i32* %tmp
+ %tmp4 = load i32* %tmp ; <i32> [#uses=1]
+ store i32 %tmp4, i32* %retval
+ br label %return
+
+return: ; preds = %entry
+ %retval5 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval5
+}
diff --git a/test/CodeGen/X86/2007-03-18-LiveIntervalAssert.ll b/test/CodeGen/X86/2007-03-18-LiveIntervalAssert.ll
new file mode 100644
index 0000000..70936fb
--- /dev/null
+++ b/test/CodeGen/X86/2007-03-18-LiveIntervalAssert.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86
+; PR1259
+
+define void @test() {
+ %tmp2 = call i32 asm "...", "=r,~{dirflag},~{fpsr},~{flags},~{dx},~{cx},~{ax}"( )
+ unreachable
+}
diff --git a/test/CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll b/test/CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
new file mode 100644
index 0000000..44d68dd
--- /dev/null
+++ b/test/CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86
+
+define i32 @test(i16 %tmp40414244) {
+ %tmp48 = call i32 asm sideeffect "inl ${1:w}, $0", "={ax},N{dx},~{dirflag},~{fpsr},~{flags}"( i16 %tmp40414244 )
+ ret i32 %tmp48
+}
+
+define i32 @test2(i16 %tmp40414244) {
+ %tmp48 = call i32 asm sideeffect "inl ${1:w}, $0", "={ax},N{dx},~{dirflag},~{fpsr},~{flags}"( i16 14 )
+ ret i32 %tmp48
+}
diff --git a/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll b/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
new file mode 100644
index 0000000..3312e01
--- /dev/null
+++ b/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 | grep {mov %gs:72, %eax}
+target datalayout = "e-p:32:32"
+target triple = "i686-apple-darwin9"
+
+define void @test() {
+ %tmp1 = tail call i32* asm sideeffect "mov %gs:${1:P}, $0", "=r,i,~{dirflag},~{fpsr},~{flags}"( i32 72 ) ; <%struct._pthread*> [#uses=1]
+ ret void
+}
+
+
diff --git a/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll b/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
new file mode 100644
index 0000000..c1b1ad1
--- /dev/null
+++ b/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mcpu=yonah -march=x86 | \
+; RUN: grep {cmpltsd %xmm0, %xmm0}
+target datalayout = "e-p:32:32"
+target triple = "i686-apple-darwin9"
+
+
+define void @acoshf() {
+ %tmp19 = tail call <2 x double> asm sideeffect "pcmpeqd $0, $0 \0A\09 cmpltsd $0, $0", "=x,0,~{dirflag},~{fpsr},~{flags}"( <2 x double> zeroinitializer ) ; <<2 x double>> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll b/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
new file mode 100644
index 0000000..30453d5
--- /dev/null
+++ b/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 | grep {psrlw \$8, %xmm0}
+target datalayout = "e-p:32:32"
+target triple = "i686-apple-darwin9"
+
+define void @test() {
+ tail call void asm sideeffect "psrlw $0, %xmm0", "X,~{dirflag},~{fpsr},~{flags}"( i32 8 )
+ ret void
+}
+
diff --git a/test/CodeGen/X86/2007-03-26-CoalescerBug.ll b/test/CodeGen/X86/2007-03-26-CoalescerBug.ll
new file mode 100644
index 0000000..9676f14
--- /dev/null
+++ b/test/CodeGen/X86/2007-03-26-CoalescerBug.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=x86
+
+@data = external global [339 x i64]
+
+define void @foo(...) {
+bb1:
+ %t43 = load i64* getelementptr ([339 x i64]* @data, i32 0, i64 212), align 4
+ br i1 false, label %bb80, label %bb6
+bb6:
+ br i1 false, label %bb38, label %bb265
+bb265:
+ ret void
+bb38:
+ br i1 false, label %bb80, label %bb49
+bb80:
+ br i1 false, label %bb146, label %bb268
+bb49:
+ ret void
+bb113:
+ ret void
+bb268:
+ %t1062 = shl i64 %t43, 3
+ %t1066 = shl i64 0, 3
+ br label %bb85
+bb85:
+ %t1025 = phi i64 [ 0, %bb268 ], [ %t102.0, %bb234 ]
+ %t1028 = phi i64 [ 0, %bb268 ], [ %t1066, %bb234 ]
+ %t1031 = phi i64 [ 0, %bb268 ], [ %t103.0, %bb234 ]
+ %t1034 = phi i64 [ 0, %bb268 ], [ %t1066, %bb234 ]
+ %t102.0 = add i64 %t1028, %t1025
+ %t103.0 = add i64 %t1034, %t1031
+ br label %bb86
+bb86:
+ %t108.0 = phi i64 [ %t102.0, %bb85 ], [ %t1139, %bb248 ]
+ %t110.0 = phi i64 [ %t103.0, %bb85 ], [ %t1142, %bb248 ]
+ br label %bb193
+bb193:
+ %t1081 = add i64 %t110.0, -8
+ %t1087 = add i64 %t108.0, -8
+ br i1 false, label %bb193, label %bb248
+bb248:
+ %t1139 = add i64 %t108.0, %t1062
+ %t1142 = add i64 %t110.0, %t1062
+ br i1 false, label %bb86, label %bb234
+bb234:
+ br i1 false, label %bb85, label %bb113
+bb146:
+ ret void
+}
diff --git a/test/CodeGen/X86/2007-04-08-InlineAsmCrash.ll b/test/CodeGen/X86/2007-04-08-InlineAsmCrash.ll
new file mode 100644
index 0000000..9f09e88
--- /dev/null
+++ b/test/CodeGen/X86/2007-04-08-InlineAsmCrash.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s
+; PR1314
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "x86_64-unknown-linux-gnu"
+ %struct.CycleCount = type { i64, i64 }
+ %struct.bc_struct = type { i32, i32, i32, i32, %struct.bc_struct*, i8*, i8* }
+@_programStartTime = external global %struct.CycleCount ; <%struct.CycleCount*> [#uses=1]
+
+define fastcc i32 @bc_divide(%struct.bc_struct* %n1, %struct.bc_struct* %n2, %struct.bc_struct** %quot, i32 %scale) nounwind {
+entry:
+ %tmp7.i46 = tail call i64 asm sideeffect ".byte 0x0f,0x31", "={dx},=*{ax},~{dirflag},~{fpsr},~{flags}"( i64* getelementptr (%struct.CycleCount* @_programStartTime, i32 0, i32 1) ) ; <i64> [#uses=0]
+ %tmp221 = sdiv i32 10, 0 ; <i32> [#uses=1]
+ tail call fastcc void @_one_mult( i8* null, i32 0, i32 %tmp221, i8* null )
+ ret i32 0
+}
+
+declare fastcc void @_one_mult(i8*, i32, i32, i8*)
diff --git a/test/CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll b/test/CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll
new file mode 100644
index 0000000..f48c132
--- /dev/null
+++ b/test/CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+
+define void @test(<4 x float> %tmp42i) {
+ %tmp42 = call <4 x float> asm "movss $1, $0", "=x,m,~{dirflag},~{fpsr},~{flags}"( float* null ) ; <<4 x float>> [#uses=1]
+ %tmp49 = shufflevector <4 x float> %tmp42, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %cond_true10
+ %tmp52 = bitcast <4 x float> %tmp49 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp53 = call <4 x i32> @llvm.x86.sse2.psll.d( <4 x i32> %tmp52, <4 x i32> < i32 8, i32 undef, i32 undef, i32 undef > ) ; <<4 x i32>> [#uses=1]
+ %tmp105 = bitcast <4 x i32> %tmp53 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp108 = fsub <4 x float> zeroinitializer, %tmp105 ; <<4 x float>> [#uses=0]
+ br label %bb
+
+return: ; preds = %entry
+ ret void
+}
+
+declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>)
diff --git a/test/CodeGen/X86/2007-04-17-LiveIntervalAssert.ll b/test/CodeGen/X86/2007-04-17-LiveIntervalAssert.ll
new file mode 100644
index 0000000..4604f46
--- /dev/null
+++ b/test/CodeGen/X86/2007-04-17-LiveIntervalAssert.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin -relocation-model=pic --disable-fp-elim
+
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+ %struct.partition_def = type { i32, [1 x %struct.partition_elem] }
+ %struct.partition_elem = type { i32, %struct.partition_elem*, i32 }
+
+define void @partition_print(%struct.partition_def* %part) {
+entry:
+ br i1 false, label %bb.preheader, label %bb99
+
+bb.preheader: ; preds = %entry
+ br i1 false, label %cond_true, label %cond_next90
+
+cond_true: ; preds = %bb.preheader
+ br i1 false, label %bb32, label %bb87.critedge
+
+bb32: ; preds = %bb32, %cond_true
+ %i.2115.0 = phi i32 [ 0, %cond_true ], [ %indvar.next127, %bb32 ] ; <i32> [#uses=1]
+ %c.2112.0 = phi i32 [ 0, %cond_true ], [ %tmp49, %bb32 ] ; <i32> [#uses=1]
+ %tmp43 = getelementptr %struct.partition_def* %part, i32 0, i32 1, i32 %c.2112.0, i32 1 ; <%struct.partition_elem**> [#uses=1]
+ %tmp44 = load %struct.partition_elem** %tmp43 ; <%struct.partition_elem*> [#uses=1]
+ %tmp4445 = ptrtoint %struct.partition_elem* %tmp44 to i32 ; <i32> [#uses=1]
+ %tmp48 = sub i32 %tmp4445, 0 ; <i32> [#uses=1]
+ %tmp49 = sdiv i32 %tmp48, 12 ; <i32> [#uses=1]
+ %indvar.next127 = add i32 %i.2115.0, 1 ; <i32> [#uses=2]
+ %exitcond128 = icmp eq i32 %indvar.next127, 0 ; <i1> [#uses=1]
+ br i1 %exitcond128, label %bb58, label %bb32
+
+bb58: ; preds = %bb32
+ ret void
+
+bb87.critedge: ; preds = %cond_true
+ ret void
+
+cond_next90: ; preds = %bb.preheader
+ ret void
+
+bb99: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2007-04-24-Huge-Stack.ll b/test/CodeGen/X86/2007-04-24-Huge-Stack.ll
new file mode 100644
index 0000000..7528129
--- /dev/null
+++ b/test/CodeGen/X86/2007-04-24-Huge-Stack.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86-64 | not grep 4294967112
+; PR1348
+
+ %struct.md5_ctx = type { i32, i32, i32, i32, [2 x i32], i32, [128 x i8], [4294967288 x i8] }
+
+define i8* @md5_buffer(i8* %buffer, i64 %len, i8* %resblock) {
+entry:
+ %ctx = alloca %struct.md5_ctx, align 16 ; <%struct.md5_ctx*> [#uses=3]
+ call void @md5_init_ctx( %struct.md5_ctx* %ctx )
+ call void @md5_process_bytes( i8* %buffer, i64 %len, %struct.md5_ctx* %ctx )
+ %tmp4 = call i8* @md5_finish_ctx( %struct.md5_ctx* %ctx, i8* %resblock ) ; <i8*> [#uses=1]
+ ret i8* %tmp4
+}
+
+declare void @md5_init_ctx(%struct.md5_ctx*)
+
+declare i8* @md5_finish_ctx(%struct.md5_ctx*, i8*)
+
+declare void @md5_process_bytes(i8*, i64, %struct.md5_ctx*)
diff --git a/test/CodeGen/X86/2007-04-24-VectorCrash.ll b/test/CodeGen/X86/2007-04-24-VectorCrash.ll
new file mode 100644
index 0000000..e38992d
--- /dev/null
+++ b/test/CodeGen/X86/2007-04-24-VectorCrash.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s -mcpu=yonah
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+
+declare <4 x float> @llvm.x86.sse.add.ss(<4 x float>, <4 x float>)
+
+define void @test(float* %P) {
+entry:
+ or <4 x i32> zeroinitializer, and (<4 x i32> bitcast (<4 x float> shufflevector (<4 x float> undef, <4 x float> undef, <4 x i32> zeroinitializer) to <4 x i32>), <4 x i32> < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 >) ; <<4 x i32>>:0 [#uses=1]
+ bitcast <4 x i32> %0 to <4 x float> ; <<4 x float>>:1 [#uses=1]
+ fsub <4 x float> %1, zeroinitializer ; <<4 x float>>:2 [#uses=1]
+ fsub <4 x float> shufflevector (<4 x float> undef, <4 x float> undef, <4 x i32> zeroinitializer), %2 ; <<4 x float>>:3 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %3, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:4 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %4, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:5 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %5, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:6 [#uses=1]
+ shufflevector <4 x float> %6, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:7 [#uses=1]
+ shufflevector <4 x float> %7, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:8 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %8, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:9 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %9, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:10 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %10, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:11 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %11, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:12 [#uses=1]
+ shufflevector <4 x float> %12, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:13 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %13, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:14 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %14, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:15 [#uses=1]
+ shufflevector <4 x float> %15, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:16 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %16, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:17 [#uses=1]
+ shufflevector <4 x float> %17, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:18 [#uses=1]
+ shufflevector <4 x float> %18, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:19 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %19, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:20 [#uses=1]
+ shufflevector <4 x float> %20, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:21 [#uses=1]
+ shufflevector <4 x float> %21, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:22 [#uses=1]
+ fmul <4 x float> %22, zeroinitializer ; <<4 x float>>:23 [#uses=1]
+ shufflevector <4 x float> %23, <4 x float> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x float>>:24 [#uses=1]
+ call <4 x float> @llvm.x86.sse.add.ss( <4 x float> zeroinitializer, <4 x float> %24 ) ; <<4 x float>>:25 [#uses=1]
+ shufflevector <4 x float> %25, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:26 [#uses=1]
+ shufflevector <4 x float> %26, <4 x float> zeroinitializer, <4 x i32> zeroinitializer ; <<4 x float>>:27 [#uses=1]
+ shufflevector <4 x float> %27, <4 x float> zeroinitializer, <4 x i32> < i32 4, i32 1, i32 6, i32 7 > ; <<4 x float>>:28 [#uses=1]
+ fmul <4 x float> zeroinitializer, %28 ; <<4 x float>>:29 [#uses=1]
+ fadd <4 x float> %29, zeroinitializer ; <<4 x float>>:30 [#uses=1]
+ fmul <4 x float> zeroinitializer, %30 ; <<4 x float>>:31 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %31, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:32 [#uses=1]
+ fmul <4 x float> zeroinitializer, %32 ; <<4 x float>>:33 [#uses=1]
+ shufflevector <4 x float> %33, <4 x float> zeroinitializer, <4 x i32> zeroinitializer ; <<4 x float>>:34 [#uses=1]
+ fmul <4 x float> zeroinitializer, %34 ; <<4 x float>>:35 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %35, <4 x i32> < i32 0, i32 1, i32 6, i32 7 > ; <<4 x float>>:36 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %36, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:37 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %37, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:38 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %38, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:39 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %39, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:40 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %40, <4 x i32> < i32 4, i32 1, i32 6, i32 7 > ; <<4 x float>>:41 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %41, <4 x i32> < i32 4, i32 1, i32 6, i32 7 > ; <<4 x float>>:42 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %42, <4 x i32> < i32 4, i32 1, i32 6, i32 7 > ; <<4 x float>>:43 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %43, <4 x i32> < i32 4, i32 1, i32 6, i32 7 > ; <<4 x float>>:44 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %44, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:45 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %45, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:46 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %46, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:47 [#uses=1]
+ shufflevector <4 x float> zeroinitializer, <4 x float> %47, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:48 [#uses=1]
+ shufflevector <4 x float> %48, <4 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x float>>:49 [#uses=1]
+ fadd <4 x float> %49, zeroinitializer ; <<4 x float>>:50 [#uses=1]
+ %tmp5845 = extractelement <4 x float> %50, i32 2 ; <float> [#uses=1]
+ store float %tmp5845, float* %P
+ ret void
+}
diff --git a/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll b/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll
new file mode 100644
index 0000000..113d0eb
--- /dev/null
+++ b/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -o - -march=x86 -mattr=+mmx | grep paddq | count 2
+; RUN: llc < %s -o - -march=x86 -mattr=+mmx | grep movq | count 2
+
+define <1 x i64> @unsigned_add3(<1 x i64>* %a, <1 x i64>* %b, i32 %count) {
+entry:
+ %tmp2942 = icmp eq i32 %count, 0 ; <i1> [#uses=1]
+ br i1 %tmp2942, label %bb31, label %bb26
+
+bb26: ; preds = %bb26, %entry
+ %i.037.0 = phi i32 [ 0, %entry ], [ %tmp25, %bb26 ] ; <i32> [#uses=3]
+ %sum.035.0 = phi <1 x i64> [ zeroinitializer, %entry ], [ %tmp22, %bb26 ] ; <<1 x i64>> [#uses=1]
+ %tmp13 = getelementptr <1 x i64>* %b, i32 %i.037.0 ; <<1 x i64>*> [#uses=1]
+ %tmp14 = load <1 x i64>* %tmp13 ; <<1 x i64>> [#uses=1]
+ %tmp18 = getelementptr <1 x i64>* %a, i32 %i.037.0 ; <<1 x i64>*> [#uses=1]
+ %tmp19 = load <1 x i64>* %tmp18 ; <<1 x i64>> [#uses=1]
+ %tmp21 = add <1 x i64> %tmp19, %tmp14 ; <<1 x i64>> [#uses=1]
+ %tmp22 = add <1 x i64> %tmp21, %sum.035.0 ; <<1 x i64>> [#uses=2]
+ %tmp25 = add i32 %i.037.0, 1 ; <i32> [#uses=2]
+ %tmp29 = icmp ult i32 %tmp25, %count ; <i1> [#uses=1]
+ br i1 %tmp29, label %bb26, label %bb31
+
+bb31: ; preds = %bb26, %entry
+ %sum.035.1 = phi <1 x i64> [ zeroinitializer, %entry ], [ %tmp22, %bb26 ] ; <<1 x i64>> [#uses=1]
+ ret <1 x i64> %sum.035.1
+}
diff --git a/test/CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll b/test/CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
new file mode 100644
index 0000000..85a2ecc
--- /dev/null
+++ b/test/CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s | not grep {bsrl.*10}
+; PR1356
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+
+define i32 @main() {
+entry:
+ %tmp4 = tail call i32 asm "bsrl $1, $0", "=r,ro,~{dirflag},~{fpsr},~{flags},~{cc}"( i32 10 ) ; <i32> [#uses=1]
+ ret i32 %tmp4
+}
+
diff --git a/test/CodeGen/X86/2007-05-05-VecCastExpand.ll b/test/CodeGen/X86/2007-05-05-VecCastExpand.ll
new file mode 100644
index 0000000..e58b193
--- /dev/null
+++ b/test/CodeGen/X86/2007-05-05-VecCastExpand.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=x86 -mcpu=i386 -mattr=+sse
+; PR1371
+
+@str = external global [18 x i8] ; <[18 x i8]*> [#uses=1]
+
+define void @test() {
+bb.i:
+ %tmp.i660 = load <4 x float>* null ; <<4 x float>> [#uses=1]
+ call void (i32, ...)* @printf( i32 0, i8* getelementptr ([18 x i8]* @str, i32 0, i64 0), double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00 )
+ %tmp152.i = load <4 x i32>* null ; <<4 x i32>> [#uses=1]
+ %tmp156.i = bitcast <4 x i32> %tmp152.i to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp175.i = bitcast <4 x float> %tmp.i660 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp176.i = xor <4 x i32> %tmp156.i, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %tmp177.i = and <4 x i32> %tmp176.i, %tmp175.i ; <<4 x i32>> [#uses=1]
+ %tmp190.i = or <4 x i32> %tmp177.i, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %tmp191.i = bitcast <4 x i32> %tmp190.i to <4 x float> ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp191.i, <4 x float>* null
+ ret void
+}
+
+declare void @printf(i32, ...)
diff --git a/test/CodeGen/X86/2007-05-07-InvokeSRet.ll b/test/CodeGen/X86/2007-05-07-InvokeSRet.ll
new file mode 100644
index 0000000..a3ff2f6
--- /dev/null
+++ b/test/CodeGen/X86/2007-05-07-InvokeSRet.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu -enable-eh -disable-fp-elim | not grep {addl .12, %esp}
+; PR1398
+
+ %struct.S = type { i32, i32 }
+
+declare void @invokee(%struct.S* sret )
+
+define void @invoker(%struct.S* %name.0.0) {
+entry:
+ invoke void @invokee( %struct.S* %name.0.0 sret )
+ to label %return unwind label %return
+
+return: ; preds = %entry, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll b/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll
new file mode 100644
index 0000000..8ef2538
--- /dev/null
+++ b/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=x86-64
+
+ %struct.XDesc = type <{ i32, %struct.OpaqueXDataStorageType** }>
+ %struct.OpaqueXDataStorageType = type opaque
+
+declare i16 @GetParamDesc(%struct.XDesc*, i32, i32, %struct.XDesc*) signext
+
+declare void @r_raise(i64, i8*, ...)
+
+define i64 @app_send_event(i64 %self, i64 %event_class, i64 %event_id, i64 %params, i64 %need_retval) {
+entry:
+ br i1 false, label %cond_true109, label %bb83.preheader
+
+bb83.preheader: ; preds = %entry
+ ret i64 0
+
+cond_true109: ; preds = %entry
+ br i1 false, label %cond_next164, label %cond_true239
+
+cond_next164: ; preds = %cond_true109
+ %tmp176 = call i16 @GetParamDesc( %struct.XDesc* null, i32 1701999219, i32 1413830740, %struct.XDesc* null ) signext ; <i16> [#uses=0]
+ call void (i64, i8*, ...)* @r_raise( i64 0, i8* null )
+ unreachable
+
+cond_true239: ; preds = %cond_true109
+ ret i64 0
+}
diff --git a/test/CodeGen/X86/2007-05-15-maskmovq.ll b/test/CodeGen/X86/2007-05-15-maskmovq.ll
new file mode 100644
index 0000000..2093b8f
--- /dev/null
+++ b/test/CodeGen/X86/2007-05-15-maskmovq.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mcpu=yonah
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+
+define void @test(<1 x i64> %c64, <1 x i64> %mask1, i8* %P) {
+entry:
+ %tmp4 = bitcast <1 x i64> %mask1 to <8 x i8> ; <<8 x i8>> [#uses=1]
+ %tmp6 = bitcast <1 x i64> %c64 to <8 x i8> ; <<8 x i8>> [#uses=1]
+ tail call void @llvm.x86.mmx.maskmovq( <8 x i8> %tmp6, <8 x i8> %tmp4, i8* %P )
+ ret void
+}
+
+declare void @llvm.x86.mmx.maskmovq(<8 x i8>, <8 x i8>, i8*)
diff --git a/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll b/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll
new file mode 100644
index 0000000..b27ef83
--- /dev/null
+++ b/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep punpckhwd
+
+declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>)
+
+declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>)
+
+define fastcc void @test(i32* %src, i32 %sbpr, i32* %dst, i32 %dbpr, i32 %w, i32 %h, i32 %dstalpha, i32 %mask) {
+ %tmp633 = shufflevector <8 x i16> zeroinitializer, <8 x i16> undef, <8 x i32> < i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7 >
+ %tmp715 = mul <8 x i16> zeroinitializer, %tmp633
+ %tmp776 = bitcast <8 x i16> %tmp715 to <4 x i32>
+ %tmp777 = add <4 x i32> %tmp776, shufflevector (<4 x i32> < i32 65537, i32 0, i32 0, i32 0 >, <4 x i32> < i32 65537, i32 0, i32 0, i32 0 >, <4 x i32> zeroinitializer)
+ %tmp805 = add <4 x i32> %tmp777, zeroinitializer
+ %tmp832 = bitcast <4 x i32> %tmp805 to <8 x i16>
+ %tmp838 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp832, <8 x i16> < i16 8, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef > )
+ %tmp1020 = tail call <16 x i8> @llvm.x86.sse2.packuswb.128( <8 x i16> zeroinitializer, <8 x i16> %tmp838 )
+ %tmp1030 = bitcast <16 x i8> %tmp1020 to <4 x i32>
+ %tmp1033 = add <4 x i32> zeroinitializer, %tmp1030
+ %tmp1048 = bitcast <4 x i32> %tmp1033 to <2 x i64>
+ %tmp1049 = or <2 x i64> %tmp1048, zeroinitializer
+ store <2 x i64> %tmp1049, <2 x i64>* null
+ ret void
+}
diff --git a/test/CodeGen/X86/2007-06-04-X86-64-CtorAsmBugs.ll b/test/CodeGen/X86/2007-06-04-X86-64-CtorAsmBugs.ll
new file mode 100644
index 0000000..321e116
--- /dev/null
+++ b/test/CodeGen/X86/2007-06-04-X86-64-CtorAsmBugs.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep GOTPCREL
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep ".align.*3"
+
+ %struct.A = type { [1024 x i8] }
+@_ZN1A1aE = global %struct.A zeroinitializer, align 32 ; <%struct.A*> [#uses=1]
[email protected]_ctors = appending global [1 x { i32, void ()* }] [ { i32, void ()* } { i32 65535, void ()* @_GLOBAL__I__ZN1A1aE } ] ; <[1 x { i32, void ()* }]*> [#uses=0]
+
+define internal void @_GLOBAL__I__ZN1A1aE() section "__TEXT,__StaticInit,regular,pure_instructions" {
+entry:
+ br label %bb.i
+
+bb.i: ; preds = %bb.i, %entry
+ %i.1.i1.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb.i ] ; <i32> [#uses=2]
+ %tmp1012.i = sext i32 %i.1.i1.0 to i64 ; <i64> [#uses=1]
+ %tmp13.i = getelementptr %struct.A* @_ZN1A1aE, i32 0, i32 0, i64 %tmp1012.i ; <i8*> [#uses=1]
+ store i8 0, i8* %tmp13.i
+ %indvar.next = add i32 %i.1.i1.0, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, 1024 ; <i1> [#uses=1]
+ br i1 %exitcond, label %_Z41__static_initialization_and_destruction_0ii.exit, label %bb.i
+
+_Z41__static_initialization_and_destruction_0ii.exit: ; preds = %bb.i
+ ret void
+}
+
+define i32 @main(i32 %argc, i8** %argv) {
+entry:
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2007-06-04-tailmerge4.ll b/test/CodeGen/X86/2007-06-04-tailmerge4.ll
new file mode 100644
index 0000000..baf2377
--- /dev/null
+++ b/test/CodeGen/X86/2007-06-04-tailmerge4.ll
@@ -0,0 +1,454 @@
+; RUN: llc < %s -enable-eh -asm-verbose | grep invcont131
+; PR 1496: tail merge was incorrectly removing this block
+
+; ModuleID = 'report.1.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-pc-linux-gnu"
+ %struct.ALLOC = type { %struct.string___XUB, [2 x i8] }
+ %struct.RETURN = type { i32, i32, i32, i64 }
+ %struct.ada__streams__root_stream_type = type { %struct.ada__tags__dispatch_table* }
+ %struct.ada__tags__dispatch_table = type { [1 x i8*] }
+ %struct.ada__text_io__text_afcb = type { %struct.system__file_control_block__afcb, i32, i32, i32, i32, i32, %struct.ada__text_io__text_afcb*, i8, i8 }
+ %struct.string___XUB = type { i32, i32 }
+ %struct.string___XUP = type { i8*, %struct.string___XUB* }
+ %struct.system__file_control_block__afcb = type { %struct.ada__streams__root_stream_type, i32, %struct.string___XUP, i32, %struct.string___XUP, i8, i8, i8, i8, i8, i8, i8, %struct.system__file_control_block__afcb*, %struct.system__file_control_block__afcb* }
+ %struct.system__secondary_stack__mark_id = type { i8*, i32 }
+ %struct.wide_string___XUP = type { i16*, %struct.string___XUB* }
+@report_E = global i8 0 ; <i8*> [#uses=0]
+@report__test_status = internal global i8 1 ; <i8*> [#uses=8]
+@report__test_name = internal global [15 x i8] zeroinitializer ; <[15 x i8]*> [#uses=10]
+@report__test_name_len = internal global i32 0 ; <i32*> [#uses=15]
[email protected] = internal constant [12 x i8] c"report.adb\00\00" ; <[12 x i8]*> [#uses=1]
[email protected] = internal constant %struct.string___XUB { i32 1, i32 1 } ; <%struct.string___XUB*> [#uses=1]
[email protected] = internal constant [1 x i8] c":" ; <[1 x i8]*> [#uses=1]
[email protected] = internal constant [1 x i8] c" " ; <[1 x i8]*> [#uses=1]
[email protected] = internal constant [1 x i8] c"-" ; <[1 x i8]*> [#uses=1]
[email protected] = internal constant [10 x i8] c"0123456789" ; <[10 x i8]*> [#uses=12]
[email protected] = internal constant %struct.string___XUB { i32 1, i32 0 } ; <%struct.string___XUB*> [#uses=1]
[email protected] = internal constant %struct.string___XUB { i32 1, i32 3 } ; <%struct.string___XUB*> [#uses=1]
[email protected] = internal constant %struct.string___XUB { i32 1, i32 6 } ; <%struct.string___XUB*> [#uses=1]
[email protected] = internal constant %struct.string___XUB { i32 1, i32 5 } ; <%struct.string___XUB*> [#uses=1]
[email protected] = internal constant [0 x i8] zeroinitializer ; <[0 x i8]*> [#uses=1]
[email protected] = internal constant [3 x i8] c"2.5" ; <[3 x i8]*> [#uses=1]
[email protected] = internal constant [6 x i8] c"ACATS " ; <[6 x i8]*> [#uses=1]
[email protected] = internal constant [5 x i8] c",.,. " ; <[5 x i8]*> [#uses=1]
[email protected] = internal constant [1 x i8] c"." ; <[1 x i8]*> [#uses=1]
[email protected] = internal constant [5 x i8] c"---- " ; <[5 x i8]*> [#uses=1]
[email protected] = internal constant [5 x i8] c" - " ; <[5 x i8]*> [#uses=1]
[email protected] = internal constant [5 x i8] c" * " ; <[5 x i8]*> [#uses=1]
[email protected] = internal constant [5 x i8] c" + " ; <[5 x i8]*> [#uses=1]
[email protected] = internal constant [5 x i8] c" ! " ; <[5 x i8]*> [#uses=1]
[email protected] = internal constant %struct.string___XUB { i32 1, i32 37 } ; <%struct.string___XUB*> [#uses=1]
[email protected] = internal constant [37 x i8] c" PASSED ============================." ; <[37 x i8]*> [#uses=1]
[email protected] = internal constant [5 x i8] c"==== " ; <[5 x i8]*> [#uses=1]
[email protected] = internal constant [37 x i8] c" NOT-APPLICABLE ++++++++++++++++++++." ; <[37 x i8]*> [#uses=1]
[email protected] = internal constant [5 x i8] c"++++ " ; <[5 x i8]*> [#uses=1]
[email protected] = internal constant [37 x i8] c" TENTATIVELY PASSED !!!!!!!!!!!!!!!!." ; <[37 x i8]*> [#uses=1]
[email protected] = internal constant [5 x i8] c"!!!! " ; <[5 x i8]*> [#uses=1]
[email protected] = internal constant [37 x i8] c" SEE '!' COMMENTS FOR SPECIAL NOTES!!" ; <[37 x i8]*> [#uses=1]
[email protected] = internal constant [37 x i8] c" FAILED ****************************." ; <[37 x i8]*> [#uses=1]
[email protected] = internal constant [5 x i8] c"**** " ; <[5 x i8]*> [#uses=1]
+@__gnat_others_value = external constant i32 ; <i32*> [#uses=2]
+@system__soft_links__abort_undefer = external global void ()* ; <void ()**> [#uses=1]
[email protected] = internal constant %struct.string___XUB { i32 2, i32 6 } ; <%struct.string___XUB*> [#uses=1]
+
+declare void @report__put_msg(i64 %msg.0.0)
+
+declare void @__gnat_rcheck_05(i8*, i32)
+
+declare void @__gnat_rcheck_12(i8*, i32)
+
+declare %struct.ada__text_io__text_afcb* @ada__text_io__standard_output()
+
+declare void @ada__text_io__set_col(%struct.ada__text_io__text_afcb*, i32)
+
+declare void @ada__text_io__put_line(%struct.ada__text_io__text_afcb*, i64)
+
+declare void @report__time_stamp(%struct.string___XUP* sret %agg.result)
+
+declare i64 @ada__calendar__clock()
+
+declare void @ada__calendar__split(%struct.RETURN* sret , i64)
+
+declare void @system__string_ops_concat_5__str_concat_5(%struct.string___XUP* sret , i64, i64, i64, i64, i64)
+
+declare void @system__string_ops_concat_3__str_concat_3(%struct.string___XUP* sret , i64, i64, i64)
+
+declare i8* @system__secondary_stack__ss_allocate(i32)
+
+declare void @report__test(i64 %name.0.0, i64 %descr.0.0)
+
+declare void @system__secondary_stack__ss_mark(%struct.system__secondary_stack__mark_id* sret )
+
+declare i8* @llvm.eh.exception()
+
+declare i32 @llvm.eh.selector(i8*, i8*, ...)
+
+declare i32 @llvm.eh.typeid.for(i8*)
+
+declare i32 @__gnat_eh_personality(...)
+
+declare i32 @_Unwind_Resume(...)
+
+declare void @__gnat_rcheck_07(i8*, i32)
+
+declare void @system__secondary_stack__ss_release(i64)
+
+declare void @report__comment(i64 %descr.0.0)
+
+declare void @report__failed(i64 %descr.0.0)
+
+declare void @report__not_applicable(i64 %descr.0.0)
+
+declare void @report__special_action(i64 %descr.0.0)
+
+define void @report__result() {
+entry:
+ %tmp = alloca %struct.system__secondary_stack__mark_id, align 8 ; <%struct.system__secondary_stack__mark_id*> [#uses=3]
+ %A.210 = alloca %struct.string___XUB, align 8 ; <%struct.string___XUB*> [#uses=3]
+ %tmp5 = alloca %struct.string___XUP, align 8 ; <%struct.string___XUP*> [#uses=3]
+ %A.229 = alloca %struct.string___XUB, align 8 ; <%struct.string___XUB*> [#uses=3]
+ %tmp10 = alloca %struct.string___XUP, align 8 ; <%struct.string___XUP*> [#uses=3]
+ %A.248 = alloca %struct.string___XUB, align 8 ; <%struct.string___XUB*> [#uses=3]
+ %tmp15 = alloca %struct.string___XUP, align 8 ; <%struct.string___XUP*> [#uses=3]
+ %A.270 = alloca %struct.string___XUB, align 8 ; <%struct.string___XUB*> [#uses=3]
+ %tmp20 = alloca %struct.string___XUP, align 8 ; <%struct.string___XUP*> [#uses=3]
+ %A.284 = alloca %struct.string___XUB, align 8 ; <%struct.string___XUB*> [#uses=3]
+ %tmp25 = alloca %struct.string___XUP, align 8 ; <%struct.string___XUP*> [#uses=3]
+ call void @system__secondary_stack__ss_mark( %struct.system__secondary_stack__mark_id* %tmp sret )
+ %tmp28 = getelementptr %struct.system__secondary_stack__mark_id* %tmp, i32 0, i32 0 ; <i8**> [#uses=1]
+ %tmp29 = load i8** %tmp28 ; <i8*> [#uses=2]
+ %tmp31 = getelementptr %struct.system__secondary_stack__mark_id* %tmp, i32 0, i32 1 ; <i32*> [#uses=1]
+ %tmp32 = load i32* %tmp31 ; <i32> [#uses=2]
+ %tmp33 = load i8* @report__test_status ; <i8> [#uses=1]
+ switch i8 %tmp33, label %bb483 [
+ i8 0, label %bb
+ i8 2, label %bb143
+ i8 3, label %bb261
+ ]
+
+bb: ; preds = %entry
+ %tmp34 = load i32* @report__test_name_len ; <i32> [#uses=4]
+ %tmp35 = icmp sgt i32 %tmp34, 0 ; <i1> [#uses=2]
+ %tmp40 = icmp sgt i32 %tmp34, 15 ; <i1> [#uses=1]
+ %bothcond139 = and i1 %tmp35, %tmp40 ; <i1> [#uses=1]
+ br i1 %bothcond139, label %cond_true43, label %cond_next44
+
+cond_true43: ; preds = %bb
+ invoke void @__gnat_rcheck_12( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 212 )
+ to label %UnifiedUnreachableBlock unwind label %unwind
+
+unwind: ; preds = %invcont589, %cond_next567, %bb555, %cond_true497, %invcont249, %cond_next227, %bb215, %cond_true157, %invcont131, %cond_next109, %bb97, %cond_true43
+ %eh_ptr = call i8* @llvm.eh.exception( ) ; <i8*> [#uses=1]
+ br label %cleanup717
+
+cond_next44: ; preds = %bb
+ %tmp72 = getelementptr %struct.string___XUB* %A.210, i32 0, i32 0 ; <i32*> [#uses=1]
+ store i32 1, i32* %tmp72
+ %tmp73 = getelementptr %struct.string___XUB* %A.210, i32 0, i32 1 ; <i32*> [#uses=1]
+ store i32 %tmp34, i32* %tmp73
+ br i1 %tmp35, label %cond_true80, label %cond_next109
+
+cond_true80: ; preds = %cond_next44
+ %tmp45.off = add i32 %tmp34, -1 ; <i32> [#uses=1]
+ %bothcond = icmp ugt i32 %tmp45.off, 14 ; <i1> [#uses=1]
+ br i1 %bothcond, label %bb97, label %cond_next109
+
+bb97: ; preds = %cond_true80
+ invoke void @__gnat_rcheck_05( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 212 )
+ to label %UnifiedUnreachableBlock unwind label %unwind
+
+cond_next109: ; preds = %cond_true80, %cond_next44
+ %A.210128 = ptrtoint %struct.string___XUB* %A.210 to i32 ; <i32> [#uses=1]
+ %A.210128129 = zext i32 %A.210128 to i64 ; <i64> [#uses=1]
+ %A.210128129130 = shl i64 %A.210128129, 32 ; <i64> [#uses=1]
+ %A.210128129130.ins = or i64 %A.210128129130, zext (i32 ptrtoint ([15 x i8]* @report__test_name to i32) to i64) ; <i64> [#uses=1]
+ invoke void @system__string_ops_concat_3__str_concat_3( %struct.string___XUP* %tmp5 sret , i64 or (i64 zext (i32 ptrtoint ([5 x i8]* @.str17 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.81.900 to i32) to i64), i64 32)), i64 %A.210128129130.ins, i64 or (i64 zext (i32 ptrtoint ([37 x i8]* @.str16 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.209.1380 to i32) to i64), i64 32)) )
+ to label %invcont131 unwind label %unwind
+
+invcont131: ; preds = %cond_next109
+ %tmp133 = getelementptr %struct.string___XUP* %tmp5, i32 0, i32 0 ; <i8**> [#uses=1]
+ %tmp134 = load i8** %tmp133 ; <i8*> [#uses=1]
+ %tmp134120 = ptrtoint i8* %tmp134 to i32 ; <i32> [#uses=1]
+ %tmp134120121 = zext i32 %tmp134120 to i64 ; <i64> [#uses=1]
+ %tmp136 = getelementptr %struct.string___XUP* %tmp5, i32 0, i32 1 ; <%struct.string___XUB**> [#uses=1]
+ %tmp137 = load %struct.string___XUB** %tmp136 ; <%struct.string___XUB*> [#uses=1]
+ %tmp137116 = ptrtoint %struct.string___XUB* %tmp137 to i32 ; <i32> [#uses=1]
+ %tmp137116117 = zext i32 %tmp137116 to i64 ; <i64> [#uses=1]
+ %tmp137116117118 = shl i64 %tmp137116117, 32 ; <i64> [#uses=1]
+ %tmp137116117118.ins = or i64 %tmp137116117118, %tmp134120121 ; <i64> [#uses=1]
+ invoke fastcc void @report__put_msg( i64 %tmp137116117118.ins )
+ to label %cond_next618 unwind label %unwind
+
+bb143: ; preds = %entry
+ %tmp144 = load i32* @report__test_name_len ; <i32> [#uses=4]
+ %tmp147 = icmp sgt i32 %tmp144, 0 ; <i1> [#uses=2]
+ %tmp154 = icmp sgt i32 %tmp144, 15 ; <i1> [#uses=1]
+ %bothcond140 = and i1 %tmp147, %tmp154 ; <i1> [#uses=1]
+ br i1 %bothcond140, label %cond_true157, label %cond_next160
+
+cond_true157: ; preds = %bb143
+ invoke void @__gnat_rcheck_12( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 215 )
+ to label %UnifiedUnreachableBlock unwind label %unwind
+
+cond_next160: ; preds = %bb143
+ %tmp189 = getelementptr %struct.string___XUB* %A.229, i32 0, i32 0 ; <i32*> [#uses=1]
+ store i32 1, i32* %tmp189
+ %tmp190 = getelementptr %struct.string___XUB* %A.229, i32 0, i32 1 ; <i32*> [#uses=1]
+ store i32 %tmp144, i32* %tmp190
+ br i1 %tmp147, label %cond_true197, label %cond_next227
+
+cond_true197: ; preds = %cond_next160
+ %tmp161.off = add i32 %tmp144, -1 ; <i32> [#uses=1]
+ %bothcond1 = icmp ugt i32 %tmp161.off, 14 ; <i1> [#uses=1]
+ br i1 %bothcond1, label %bb215, label %cond_next227
+
+bb215: ; preds = %cond_true197
+ invoke void @__gnat_rcheck_05( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 215 )
+ to label %UnifiedUnreachableBlock unwind label %unwind
+
+cond_next227: ; preds = %cond_true197, %cond_next160
+ %A.229105 = ptrtoint %struct.string___XUB* %A.229 to i32 ; <i32> [#uses=1]
+ %A.229105106 = zext i32 %A.229105 to i64 ; <i64> [#uses=1]
+ %A.229105106107 = shl i64 %A.229105106, 32 ; <i64> [#uses=1]
+ %A.229105106107.ins = or i64 %A.229105106107, zext (i32 ptrtoint ([15 x i8]* @report__test_name to i32) to i64) ; <i64> [#uses=1]
+ invoke void @system__string_ops_concat_3__str_concat_3( %struct.string___XUP* %tmp10 sret , i64 or (i64 zext (i32 ptrtoint ([5 x i8]* @.str19 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.81.900 to i32) to i64), i64 32)), i64 %A.229105106107.ins, i64 or (i64 zext (i32 ptrtoint ([37 x i8]* @.str18 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.209.1380 to i32) to i64), i64 32)) )
+ to label %invcont249 unwind label %unwind
+
+invcont249: ; preds = %cond_next227
+ %tmp251 = getelementptr %struct.string___XUP* %tmp10, i32 0, i32 0 ; <i8**> [#uses=1]
+ %tmp252 = load i8** %tmp251 ; <i8*> [#uses=1]
+ %tmp25297 = ptrtoint i8* %tmp252 to i32 ; <i32> [#uses=1]
+ %tmp2529798 = zext i32 %tmp25297 to i64 ; <i64> [#uses=1]
+ %tmp254 = getelementptr %struct.string___XUP* %tmp10, i32 0, i32 1 ; <%struct.string___XUB**> [#uses=1]
+ %tmp255 = load %struct.string___XUB** %tmp254 ; <%struct.string___XUB*> [#uses=1]
+ %tmp25593 = ptrtoint %struct.string___XUB* %tmp255 to i32 ; <i32> [#uses=1]
+ %tmp2559394 = zext i32 %tmp25593 to i64 ; <i64> [#uses=1]
+ %tmp255939495 = shl i64 %tmp2559394, 32 ; <i64> [#uses=1]
+ %tmp255939495.ins = or i64 %tmp255939495, %tmp2529798 ; <i64> [#uses=1]
+ invoke fastcc void @report__put_msg( i64 %tmp255939495.ins )
+ to label %cond_next618 unwind label %unwind
+
+bb261: ; preds = %entry
+ %tmp262 = call i8* @llvm.stacksave( ) ; <i8*> [#uses=2]
+ %tmp263 = load i32* @report__test_name_len ; <i32> [#uses=4]
+ %tmp266 = icmp sgt i32 %tmp263, 0 ; <i1> [#uses=2]
+ %tmp273 = icmp sgt i32 %tmp263, 15 ; <i1> [#uses=1]
+ %bothcond141 = and i1 %tmp266, %tmp273 ; <i1> [#uses=1]
+ br i1 %bothcond141, label %cond_true276, label %cond_next281
+
+cond_true276: ; preds = %bb261
+ invoke void @__gnat_rcheck_12( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 218 )
+ to label %UnifiedUnreachableBlock unwind label %unwind277
+
+unwind277: ; preds = %invcont467, %cond_next442, %invcont370, %cond_next348, %bb336, %cond_true276
+ %eh_ptr278 = call i8* @llvm.eh.exception( ) ; <i8*> [#uses=1]
+ call void @llvm.stackrestore( i8* %tmp262 )
+ br label %cleanup717
+
+cond_next281: ; preds = %bb261
+ %tmp310 = getelementptr %struct.string___XUB* %A.248, i32 0, i32 0 ; <i32*> [#uses=1]
+ store i32 1, i32* %tmp310
+ %tmp311 = getelementptr %struct.string___XUB* %A.248, i32 0, i32 1 ; <i32*> [#uses=1]
+ store i32 %tmp263, i32* %tmp311
+ br i1 %tmp266, label %cond_true318, label %cond_next348
+
+cond_true318: ; preds = %cond_next281
+ %tmp282.off = add i32 %tmp263, -1 ; <i32> [#uses=1]
+ %bothcond2 = icmp ugt i32 %tmp282.off, 14 ; <i1> [#uses=1]
+ br i1 %bothcond2, label %bb336, label %cond_next348
+
+bb336: ; preds = %cond_true318
+ invoke void @__gnat_rcheck_05( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 218 )
+ to label %UnifiedUnreachableBlock unwind label %unwind277
+
+cond_next348: ; preds = %cond_true318, %cond_next281
+ %A.24882 = ptrtoint %struct.string___XUB* %A.248 to i32 ; <i32> [#uses=1]
+ %A.2488283 = zext i32 %A.24882 to i64 ; <i64> [#uses=1]
+ %A.248828384 = shl i64 %A.2488283, 32 ; <i64> [#uses=1]
+ %A.248828384.ins = or i64 %A.248828384, zext (i32 ptrtoint ([15 x i8]* @report__test_name to i32) to i64) ; <i64> [#uses=1]
+ invoke void @system__string_ops_concat_3__str_concat_3( %struct.string___XUP* %tmp15 sret , i64 or (i64 zext (i32 ptrtoint ([5 x i8]* @.str21 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.81.900 to i32) to i64), i64 32)), i64 %A.248828384.ins, i64 or (i64 zext (i32 ptrtoint ([37 x i8]* @.str20 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.209.1380 to i32) to i64), i64 32)) )
+ to label %invcont370 unwind label %unwind277
+
+invcont370: ; preds = %cond_next348
+ %tmp372 = getelementptr %struct.string___XUP* %tmp15, i32 0, i32 0 ; <i8**> [#uses=1]
+ %tmp373 = load i8** %tmp372 ; <i8*> [#uses=1]
+ %tmp37374 = ptrtoint i8* %tmp373 to i32 ; <i32> [#uses=1]
+ %tmp3737475 = zext i32 %tmp37374 to i64 ; <i64> [#uses=1]
+ %tmp375 = getelementptr %struct.string___XUP* %tmp15, i32 0, i32 1 ; <%struct.string___XUB**> [#uses=1]
+ %tmp376 = load %struct.string___XUB** %tmp375 ; <%struct.string___XUB*> [#uses=1]
+ %tmp37670 = ptrtoint %struct.string___XUB* %tmp376 to i32 ; <i32> [#uses=1]
+ %tmp3767071 = zext i32 %tmp37670 to i64 ; <i64> [#uses=1]
+ %tmp376707172 = shl i64 %tmp3767071, 32 ; <i64> [#uses=1]
+ %tmp376707172.ins = or i64 %tmp376707172, %tmp3737475 ; <i64> [#uses=1]
+ invoke fastcc void @report__put_msg( i64 %tmp376707172.ins )
+ to label %invcont381 unwind label %unwind277
+
+invcont381: ; preds = %invcont370
+ %tmp382 = load i32* @report__test_name_len ; <i32> [#uses=6]
+ %tmp415 = icmp sgt i32 %tmp382, -1 ; <i1> [#uses=1]
+ %max416 = select i1 %tmp415, i32 %tmp382, i32 0 ; <i32> [#uses=1]
+ %tmp417 = alloca i8, i32 %max416 ; <i8*> [#uses=3]
+ %tmp423 = icmp sgt i32 %tmp382, 0 ; <i1> [#uses=1]
+ br i1 %tmp423, label %bb427, label %cond_next442
+
+bb427: ; preds = %invcont381
+ store i8 32, i8* %tmp417
+ %tmp434 = icmp eq i32 %tmp382, 1 ; <i1> [#uses=1]
+ br i1 %tmp434, label %cond_next442, label %cond_next438.preheader
+
+cond_next438.preheader: ; preds = %bb427
+ %tmp. = add i32 %tmp382, -1 ; <i32> [#uses=1]
+ br label %cond_next438
+
+cond_next438: ; preds = %cond_next438, %cond_next438.preheader
+ %indvar = phi i32 [ 0, %cond_next438.preheader ], [ %J130b.513.5, %cond_next438 ] ; <i32> [#uses=1]
+ %J130b.513.5 = add i32 %indvar, 1 ; <i32> [#uses=3]
+ %tmp43118 = getelementptr i8* %tmp417, i32 %J130b.513.5 ; <i8*> [#uses=1]
+ store i8 32, i8* %tmp43118
+ %exitcond = icmp eq i32 %J130b.513.5, %tmp. ; <i1> [#uses=1]
+ br i1 %exitcond, label %cond_next442, label %cond_next438
+
+cond_next442: ; preds = %cond_next438, %bb427, %invcont381
+ %tmp448 = getelementptr %struct.string___XUB* %A.270, i32 0, i32 0 ; <i32*> [#uses=1]
+ store i32 1, i32* %tmp448
+ %tmp449 = getelementptr %struct.string___XUB* %A.270, i32 0, i32 1 ; <i32*> [#uses=1]
+ store i32 %tmp382, i32* %tmp449
+ %tmp41762 = ptrtoint i8* %tmp417 to i32 ; <i32> [#uses=1]
+ %tmp4176263 = zext i32 %tmp41762 to i64 ; <i64> [#uses=1]
+ %A.27058 = ptrtoint %struct.string___XUB* %A.270 to i32 ; <i32> [#uses=1]
+ %A.2705859 = zext i32 %A.27058 to i64 ; <i64> [#uses=1]
+ %A.270585960 = shl i64 %A.2705859, 32 ; <i64> [#uses=1]
+ %A.270585960.ins = or i64 %tmp4176263, %A.270585960 ; <i64> [#uses=1]
+ invoke void @system__string_ops_concat_3__str_concat_3( %struct.string___XUP* %tmp20 sret , i64 or (i64 zext (i32 ptrtoint ([5 x i8]* @.str21 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.81.900 to i32) to i64), i64 32)), i64 %A.270585960.ins, i64 or (i64 zext (i32 ptrtoint ([37 x i8]* @.str22 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.209.1380 to i32) to i64), i64 32)) )
+ to label %invcont467 unwind label %unwind277
+
+invcont467: ; preds = %cond_next442
+ %tmp469 = getelementptr %struct.string___XUP* %tmp20, i32 0, i32 0 ; <i8**> [#uses=1]
+ %tmp470 = load i8** %tmp469 ; <i8*> [#uses=1]
+ %tmp47050 = ptrtoint i8* %tmp470 to i32 ; <i32> [#uses=1]
+ %tmp4705051 = zext i32 %tmp47050 to i64 ; <i64> [#uses=1]
+ %tmp472 = getelementptr %struct.string___XUP* %tmp20, i32 0, i32 1 ; <%struct.string___XUB**> [#uses=1]
+ %tmp473 = load %struct.string___XUB** %tmp472 ; <%struct.string___XUB*> [#uses=1]
+ %tmp47346 = ptrtoint %struct.string___XUB* %tmp473 to i32 ; <i32> [#uses=1]
+ %tmp4734647 = zext i32 %tmp47346 to i64 ; <i64> [#uses=1]
+ %tmp473464748 = shl i64 %tmp4734647, 32 ; <i64> [#uses=1]
+ %tmp473464748.ins = or i64 %tmp473464748, %tmp4705051 ; <i64> [#uses=1]
+ invoke fastcc void @report__put_msg( i64 %tmp473464748.ins )
+ to label %cleanup unwind label %unwind277
+
+cleanup: ; preds = %invcont467
+ call void @llvm.stackrestore( i8* %tmp262 )
+ br label %cond_next618
+
+bb483: ; preds = %entry
+ %tmp484 = load i32* @report__test_name_len ; <i32> [#uses=4]
+ %tmp487 = icmp sgt i32 %tmp484, 0 ; <i1> [#uses=2]
+ %tmp494 = icmp sgt i32 %tmp484, 15 ; <i1> [#uses=1]
+ %bothcond142 = and i1 %tmp487, %tmp494 ; <i1> [#uses=1]
+ br i1 %bothcond142, label %cond_true497, label %cond_next500
+
+cond_true497: ; preds = %bb483
+ invoke void @__gnat_rcheck_12( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 223 )
+ to label %UnifiedUnreachableBlock unwind label %unwind
+
+cond_next500: ; preds = %bb483
+ %tmp529 = getelementptr %struct.string___XUB* %A.284, i32 0, i32 0 ; <i32*> [#uses=1]
+ store i32 1, i32* %tmp529
+ %tmp530 = getelementptr %struct.string___XUB* %A.284, i32 0, i32 1 ; <i32*> [#uses=1]
+ store i32 %tmp484, i32* %tmp530
+ br i1 %tmp487, label %cond_true537, label %cond_next567
+
+cond_true537: ; preds = %cond_next500
+ %tmp501.off = add i32 %tmp484, -1 ; <i32> [#uses=1]
+ %bothcond3 = icmp ugt i32 %tmp501.off, 14 ; <i1> [#uses=1]
+ br i1 %bothcond3, label %bb555, label %cond_next567
+
+bb555: ; preds = %cond_true537
+ invoke void @__gnat_rcheck_05( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 223 )
+ to label %UnifiedUnreachableBlock unwind label %unwind
+
+cond_next567: ; preds = %cond_true537, %cond_next500
+ %A.28435 = ptrtoint %struct.string___XUB* %A.284 to i32 ; <i32> [#uses=1]
+ %A.2843536 = zext i32 %A.28435 to i64 ; <i64> [#uses=1]
+ %A.284353637 = shl i64 %A.2843536, 32 ; <i64> [#uses=1]
+ %A.284353637.ins = or i64 %A.284353637, zext (i32 ptrtoint ([15 x i8]* @report__test_name to i32) to i64) ; <i64> [#uses=1]
+ invoke void @system__string_ops_concat_3__str_concat_3( %struct.string___XUP* %tmp25 sret , i64 or (i64 zext (i32 ptrtoint ([5 x i8]* @.str24 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.81.900 to i32) to i64), i64 32)), i64 %A.284353637.ins, i64 or (i64 zext (i32 ptrtoint ([37 x i8]* @.str23 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.209.1380 to i32) to i64), i64 32)) )
+ to label %invcont589 unwind label %unwind
+
+invcont589: ; preds = %cond_next567
+ %tmp591 = getelementptr %struct.string___XUP* %tmp25, i32 0, i32 0 ; <i8**> [#uses=1]
+ %tmp592 = load i8** %tmp591 ; <i8*> [#uses=1]
+ %tmp59228 = ptrtoint i8* %tmp592 to i32 ; <i32> [#uses=1]
+ %tmp5922829 = zext i32 %tmp59228 to i64 ; <i64> [#uses=1]
+ %tmp594 = getelementptr %struct.string___XUP* %tmp25, i32 0, i32 1 ; <%struct.string___XUB**> [#uses=1]
+ %tmp595 = load %struct.string___XUB** %tmp594 ; <%struct.string___XUB*> [#uses=1]
+ %tmp59524 = ptrtoint %struct.string___XUB* %tmp595 to i32 ; <i32> [#uses=1]
+ %tmp5952425 = zext i32 %tmp59524 to i64 ; <i64> [#uses=1]
+ %tmp595242526 = shl i64 %tmp5952425, 32 ; <i64> [#uses=1]
+ %tmp595242526.ins = or i64 %tmp595242526, %tmp5922829 ; <i64> [#uses=1]
+ invoke fastcc void @report__put_msg( i64 %tmp595242526.ins )
+ to label %cond_next618 unwind label %unwind
+
+cond_next618: ; preds = %invcont589, %cleanup, %invcont249, %invcont131
+ store i8 1, i8* @report__test_status
+ store i32 7, i32* @report__test_name_len
+ store i8 78, i8* getelementptr ([15 x i8]* @report__test_name, i32 0, i32 0)
+ store i8 79, i8* getelementptr ([15 x i8]* @report__test_name, i32 0, i32 1)
+ store i8 95, i8* getelementptr ([15 x i8]* @report__test_name, i32 0, i32 2)
+ store i8 78, i8* getelementptr ([15 x i8]* @report__test_name, i32 0, i32 3)
+ store i8 65, i8* getelementptr ([15 x i8]* @report__test_name, i32 0, i32 4)
+ store i8 77, i8* getelementptr ([15 x i8]* @report__test_name, i32 0, i32 5)
+ store i8 69, i8* getelementptr ([15 x i8]* @report__test_name, i32 0, i32 6)
+ %CHAIN.310.0.0.0.val5.i = ptrtoint i8* %tmp29 to i32 ; <i32> [#uses=1]
+ %CHAIN.310.0.0.0.val56.i = zext i32 %CHAIN.310.0.0.0.val5.i to i64 ; <i64> [#uses=1]
+ %CHAIN.310.0.0.1.val2.i = zext i32 %tmp32 to i64 ; <i64> [#uses=1]
+ %CHAIN.310.0.0.1.val23.i = shl i64 %CHAIN.310.0.0.1.val2.i, 32 ; <i64> [#uses=1]
+ %CHAIN.310.0.0.1.val23.ins.i = or i64 %CHAIN.310.0.0.1.val23.i, %CHAIN.310.0.0.0.val56.i ; <i64> [#uses=1]
+ call void @system__secondary_stack__ss_release( i64 %CHAIN.310.0.0.1.val23.ins.i )
+ ret void
+
+cleanup717: ; preds = %unwind277, %unwind
+ %eh_exception.0 = phi i8* [ %eh_ptr278, %unwind277 ], [ %eh_ptr, %unwind ] ; <i8*> [#uses=1]
+ %CHAIN.310.0.0.0.val5.i8 = ptrtoint i8* %tmp29 to i32 ; <i32> [#uses=1]
+ %CHAIN.310.0.0.0.val56.i9 = zext i32 %CHAIN.310.0.0.0.val5.i8 to i64 ; <i64> [#uses=1]
+ %CHAIN.310.0.0.1.val2.i10 = zext i32 %tmp32 to i64 ; <i64> [#uses=1]
+ %CHAIN.310.0.0.1.val23.i11 = shl i64 %CHAIN.310.0.0.1.val2.i10, 32 ; <i64> [#uses=1]
+ %CHAIN.310.0.0.1.val23.ins.i12 = or i64 %CHAIN.310.0.0.1.val23.i11, %CHAIN.310.0.0.0.val56.i9 ; <i64> [#uses=1]
+ call void @system__secondary_stack__ss_release( i64 %CHAIN.310.0.0.1.val23.ins.i12 )
+ call i32 (...)* @_Unwind_Resume( i8* %eh_exception.0 ) ; <i32>:0 [#uses=0]
+ unreachable
+
+UnifiedUnreachableBlock: ; preds = %bb555, %cond_true497, %bb336, %cond_true276, %bb215, %cond_true157, %bb97, %cond_true43
+ unreachable
+}
+
+declare i8* @llvm.stacksave()
+
+declare void @llvm.stackrestore(i8*)
+
+declare i32 @report__ident_int(i32 %x)
+
+declare i8 @report__equal(i32 %x, i32 %y)
+
+declare i8 @report__ident_char(i8 zeroext %x)
+
+declare i16 @report__ident_wide_char(i16 zeroext %x)
+
+declare i8 @report__ident_bool(i8 %x)
+
+declare void @report__ident_str(%struct.string___XUP* sret %agg.result, i64 %x.0.0)
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32)
+
+declare void @report__ident_wide_str(%struct.wide_string___XUP* sret %agg.result, i64 %x.0.0)
+
+declare void @__gnat_begin_handler(i8*)
+
+declare void @__gnat_end_handler(i8*)
+
+declare void @report__legal_file_name(%struct.string___XUP* sret %agg.result, i32 %x, i64 %nam.0.0)
+
+declare void @__gnat_rcheck_06(i8*, i32)
+
+declare void @system__string_ops__str_concat_cs(%struct.string___XUP* sret , i8 zeroext , i64)
diff --git a/test/CodeGen/X86/2007-06-05-LSR-Dominator.ll b/test/CodeGen/X86/2007-06-05-LSR-Dominator.ll
new file mode 100644
index 0000000..36a97ef
--- /dev/null
+++ b/test/CodeGen/X86/2007-06-05-LSR-Dominator.ll
@@ -0,0 +1,129 @@
+; PR1495
+; RUN: llc < %s -march=x86
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-pc-linux-gnu"
+ %struct.AVRational = type { i32, i32 }
+ %struct.FFTComplex = type { float, float }
+ %struct.FFTContext = type { i32, i32, i16*, %struct.FFTComplex*, %struct.FFTComplex*, void (%struct.FFTContext*, %struct.FFTComplex*)*, void (%struct.MDCTContext*, float*, float*, float*)* }
+ %struct.MDCTContext = type { i32, i32, float*, float*, %struct.FFTContext }
+ %struct.Minima = type { i32, i32, i32, i32 }
+ %struct.codebook_t = type { i32, i8*, i32*, i32, float, float, i32, i32, i32*, float*, float* }
+ %struct.floor_class_t = type { i32, i32, i32, i32* }
+ %struct.floor_t = type { i32, i32*, i32, %struct.floor_class_t*, i32, i32, i32, %struct.Minima* }
+ %struct.mapping_t = type { i32, i32*, i32*, i32*, i32, i32*, i32* }
+ %struct.residue_t = type { i32, i32, i32, i32, i32, i32, [8 x i8]*, [2 x float]* }
+ %struct.venc_context_t = type { i32, i32, [2 x i32], [2 x %struct.MDCTContext], [2 x float*], i32, float*, float*, float*, float*, float, i32, %struct.codebook_t*, i32, %struct.floor_t*, i32, %struct.residue_t*, i32, %struct.mapping_t*, i32, %struct.AVRational* }
+
+define fastcc i32 @put_main_header(%struct.venc_context_t* %venc, i8** %out) {
+entry:
+ br i1 false, label %bb1820, label %bb288.bb148_crit_edge
+
+bb288.bb148_crit_edge: ; preds = %entry
+ ret i32 0
+
+cond_next1712: ; preds = %bb1820.bb1680_crit_edge
+ ret i32 0
+
+bb1817: ; preds = %bb1820.bb1680_crit_edge
+ br label %bb1820
+
+bb1820: ; preds = %bb1817, %entry
+ %pb.1.50 = phi i32 [ %tmp1693, %bb1817 ], [ 8, %entry ] ; <i32> [#uses=3]
+ br i1 false, label %bb2093, label %bb1820.bb1680_crit_edge
+
+bb1820.bb1680_crit_edge: ; preds = %bb1820
+ %tmp1693 = add i32 %pb.1.50, 8 ; <i32> [#uses=2]
+ %tmp1702 = icmp slt i32 %tmp1693, 0 ; <i1> [#uses=1]
+ br i1 %tmp1702, label %cond_next1712, label %bb1817
+
+bb2093: ; preds = %bb1820
+ %tmp2102 = add i32 %pb.1.50, 65 ; <i32> [#uses=0]
+ %tmp2236 = add i32 %pb.1.50, 72 ; <i32> [#uses=1]
+ %tmp2237 = sdiv i32 %tmp2236, 8 ; <i32> [#uses=2]
+ br i1 false, label %bb2543, label %bb2536.bb2396_crit_edge
+
+bb2536.bb2396_crit_edge: ; preds = %bb2093
+ ret i32 0
+
+bb2543: ; preds = %bb2093
+ br i1 false, label %cond_next2576, label %bb2690
+
+cond_next2576: ; preds = %bb2543
+ ret i32 0
+
+bb2682: ; preds = %bb2690
+ ret i32 0
+
+bb2690: ; preds = %bb2543
+ br i1 false, label %bb2682, label %bb2698
+
+bb2698: ; preds = %bb2690
+ br i1 false, label %cond_next2726, label %bb2831
+
+cond_next2726: ; preds = %bb2698
+ ret i32 0
+
+bb2831: ; preds = %bb2698
+ br i1 false, label %cond_next2859, label %bb2964
+
+cond_next2859: ; preds = %bb2831
+ br i1 false, label %bb2943, label %cond_true2866
+
+cond_true2866: ; preds = %cond_next2859
+ br i1 false, label %cond_true2874, label %cond_false2897
+
+cond_true2874: ; preds = %cond_true2866
+ ret i32 0
+
+cond_false2897: ; preds = %cond_true2866
+ ret i32 0
+
+bb2943: ; preds = %cond_next2859
+ ret i32 0
+
+bb2964: ; preds = %bb2831
+ br i1 false, label %cond_next2997, label %bb4589
+
+cond_next2997: ; preds = %bb2964
+ ret i32 0
+
+bb3103: ; preds = %bb4589
+ ret i32 0
+
+bb4589: ; preds = %bb2964
+ br i1 false, label %bb3103, label %bb4597
+
+bb4597: ; preds = %bb4589
+ br i1 false, label %cond_next4630, label %bb4744
+
+cond_next4630: ; preds = %bb4597
+ br i1 false, label %bb4744, label %cond_true4724
+
+cond_true4724: ; preds = %cond_next4630
+ br i1 false, label %bb4736, label %bb7531
+
+bb4736: ; preds = %cond_true4724
+ ret i32 0
+
+bb4744: ; preds = %cond_next4630, %bb4597
+ ret i32 0
+
+bb7531: ; preds = %cond_true4724
+ %v_addr.023.0.i6 = add i32 %tmp2237, -255 ; <i32> [#uses=1]
+ br label %bb.i14
+
+bb.i14: ; preds = %bb.i14, %bb7531
+ %n.021.0.i8 = phi i32 [ 0, %bb7531 ], [ %indvar.next, %bb.i14 ] ; <i32> [#uses=2]
+ %tmp..i9 = mul i32 %n.021.0.i8, -255 ; <i32> [#uses=1]
+ %tmp5.i11 = add i32 %v_addr.023.0.i6, %tmp..i9 ; <i32> [#uses=1]
+ %tmp10.i12 = icmp ugt i32 %tmp5.i11, 254 ; <i1> [#uses=1]
+ %indvar.next = add i32 %n.021.0.i8, 1 ; <i32> [#uses=1]
+ br i1 %tmp10.i12, label %bb.i14, label %bb12.loopexit.i18
+
+bb12.loopexit.i18: ; preds = %bb.i14
+ call void @llvm.memcpy.i32( i8* null, i8* null, i32 %tmp2237, i32 1 )
+ ret i32 0
+}
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32)
diff --git a/test/CodeGen/X86/2007-06-14-branchfold.ll b/test/CodeGen/X86/2007-06-14-branchfold.ll
new file mode 100644
index 0000000..2680b15
--- /dev/null
+++ b/test/CodeGen/X86/2007-06-14-branchfold.ll
@@ -0,0 +1,133 @@
+; RUN: llc < %s -march=x86 -mcpu=i686 | not grep jmp
+; check that branch folding understands FP_REG_KILL is not a branch
+
+target triple = "i686-pc-linux-gnu"
+ %struct.FRAME.c34003a = type { float, float }
+@report_E = global i8 0 ; <i8*> [#uses=0]
+
+define void @main() {
+entry:
+ %FRAME.31 = alloca %struct.FRAME.c34003a, align 8 ; <%struct.FRAME.c34003a*> [#uses=4]
+ %tmp20 = call i32 @report__ident_int( i32 -50 ) ; <i32> [#uses=1]
+ %tmp2021 = sitofp i32 %tmp20 to float ; <float> [#uses=5]
+ %tmp23 = fcmp ult float %tmp2021, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
+ %tmp26 = fcmp ugt float %tmp2021, 0x47EFFFFFE0000000 ; <i1> [#uses=1]
+ %bothcond = or i1 %tmp23, %tmp26 ; <i1> [#uses=1]
+ br i1 %bothcond, label %bb, label %bb30
+
+bb: ; preds = %entry
+ unwind
+
+bb30: ; preds = %entry
+ %tmp35 = call i32 @report__ident_int( i32 50 ) ; <i32> [#uses=1]
+ %tmp3536 = sitofp i32 %tmp35 to float ; <float> [#uses=4]
+ %tmp38 = fcmp ult float %tmp3536, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
+ %tmp44 = fcmp ugt float %tmp3536, 0x47EFFFFFE0000000 ; <i1> [#uses=1]
+ %bothcond226 = or i1 %tmp38, %tmp44 ; <i1> [#uses=1]
+ br i1 %bothcond226, label %bb47, label %bb49
+
+bb47: ; preds = %bb30
+ unwind
+
+bb49: ; preds = %bb30
+ %tmp60 = fcmp ult float %tmp3536, %tmp2021 ; <i1> [#uses=1]
+ %tmp60.not = xor i1 %tmp60, true ; <i1> [#uses=1]
+ %tmp65 = fcmp olt float %tmp2021, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
+ %bothcond227 = and i1 %tmp65, %tmp60.not ; <i1> [#uses=1]
+ br i1 %bothcond227, label %cond_true68, label %cond_next70
+
+cond_true68: ; preds = %bb49
+ unwind
+
+cond_next70: ; preds = %bb49
+ %tmp71 = call i32 @report__ident_int( i32 -30 ) ; <i32> [#uses=1]
+ %tmp7172 = sitofp i32 %tmp71 to float ; <float> [#uses=3]
+ %tmp74 = fcmp ult float %tmp7172, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
+ %tmp80 = fcmp ugt float %tmp7172, 0x47EFFFFFE0000000 ; <i1> [#uses=1]
+ %bothcond228 = or i1 %tmp74, %tmp80 ; <i1> [#uses=1]
+ br i1 %bothcond228, label %bb83, label %bb85
+
+bb83: ; preds = %cond_next70
+ unwind
+
+bb85: ; preds = %cond_next70
+ %tmp90 = getelementptr %struct.FRAME.c34003a* %FRAME.31, i32 0, i32 1 ; <float*> [#uses=3]
+ store float %tmp7172, float* %tmp90
+ %tmp92 = call i32 @report__ident_int( i32 30 ) ; <i32> [#uses=1]
+ %tmp9293 = sitofp i32 %tmp92 to float ; <float> [#uses=7]
+ %tmp95 = fcmp ult float %tmp9293, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
+ %tmp101 = fcmp ugt float %tmp9293, 0x47EFFFFFE0000000 ; <i1> [#uses=1]
+ %bothcond229 = or i1 %tmp95, %tmp101 ; <i1> [#uses=1]
+ br i1 %bothcond229, label %bb104, label %bb106
+
+bb104: ; preds = %bb85
+ unwind
+
+bb106: ; preds = %bb85
+ %tmp111 = getelementptr %struct.FRAME.c34003a* %FRAME.31, i32 0, i32 0 ; <float*> [#uses=2]
+ store float %tmp9293, float* %tmp111
+ %tmp123 = load float* %tmp90 ; <float> [#uses=4]
+ %tmp125 = fcmp ult float %tmp9293, %tmp123 ; <i1> [#uses=1]
+ br i1 %tmp125, label %cond_next147, label %cond_true128
+
+cond_true128: ; preds = %bb106
+ %tmp133 = fcmp olt float %tmp123, %tmp2021 ; <i1> [#uses=1]
+ %tmp142 = fcmp ogt float %tmp9293, %tmp3536 ; <i1> [#uses=1]
+ %bothcond230 = or i1 %tmp133, %tmp142 ; <i1> [#uses=1]
+ br i1 %bothcond230, label %bb145, label %cond_next147
+
+bb145: ; preds = %cond_true128
+ unwind
+
+cond_next147: ; preds = %cond_true128, %bb106
+ %tmp157 = fcmp ugt float %tmp123, -3.000000e+01 ; <i1> [#uses=1]
+ %tmp165 = fcmp ult float %tmp9293, -3.000000e+01 ; <i1> [#uses=1]
+ %bothcond231 = or i1 %tmp157, %tmp165 ; <i1> [#uses=1]
+ br i1 %bothcond231, label %bb168, label %bb169
+
+bb168: ; preds = %cond_next147
+ unwind
+
+bb169: ; preds = %cond_next147
+ %tmp176 = fcmp ugt float %tmp123, 3.000000e+01 ; <i1> [#uses=1]
+ %tmp184 = fcmp ult float %tmp9293, 3.000000e+01 ; <i1> [#uses=1]
+ %bothcond232 = or i1 %tmp176, %tmp184 ; <i1> [#uses=1]
+ br i1 %bothcond232, label %bb187, label %bb188
+
+bb187: ; preds = %bb169
+ unwind
+
+bb188: ; preds = %bb169
+ %tmp192 = call fastcc float @c34003a__ident.154( %struct.FRAME.c34003a* %FRAME.31, float 3.000000e+01 ) ; <float> [#uses=2]
+ %tmp194 = load float* %tmp90 ; <float> [#uses=1]
+ %tmp196 = fcmp ugt float %tmp194, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %tmp196, label %bb207, label %cond_next200
+
+cond_next200: ; preds = %bb188
+ %tmp202 = load float* %tmp111 ; <float> [#uses=1]
+ %tmp204 = fcmp ult float %tmp202, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %tmp204, label %bb207, label %bb208
+
+bb207: ; preds = %cond_next200, %bb188
+ unwind
+
+bb208: ; preds = %cond_next200
+ %tmp212 = call fastcc float @c34003a__ident.154( %struct.FRAME.c34003a* %FRAME.31, float 0.000000e+00 ) ; <float> [#uses=1]
+ %tmp214 = fcmp oge float %tmp212, %tmp192 ; <i1> [#uses=1]
+ %tmp217 = fcmp oge float %tmp192, 1.000000e+02 ; <i1> [#uses=1]
+ %tmp221 = or i1 %tmp214, %tmp217 ; <i1> [#uses=1]
+ br i1 %tmp221, label %cond_true224, label %UnifiedReturnBlock
+
+cond_true224: ; preds = %bb208
+ call void @abort( ) noreturn
+ ret void
+
+UnifiedReturnBlock: ; preds = %bb208
+ ret void
+}
+
+declare fastcc float @c34003a__ident.154(%struct.FRAME.c34003a* %CHAIN.32, float %x)
+
+declare i32 @report__ident_int(i32 %x)
+
+declare void @abort() noreturn
diff --git a/test/CodeGen/X86/2007-06-15-IntToMMX.ll b/test/CodeGen/X86/2007-06-15-IntToMMX.ll
new file mode 100644
index 0000000..6128d8b
--- /dev/null
+++ b/test/CodeGen/X86/2007-06-15-IntToMMX.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep paddusw
+@R = external global <1 x i64> ; <<1 x i64>*> [#uses=1]
+
+define void @foo(<1 x i64> %A, <1 x i64> %B) {
+entry:
+ %tmp4 = bitcast <1 x i64> %B to <4 x i16> ; <<4 x i16>> [#uses=1]
+ %tmp6 = bitcast <1 x i64> %A to <4 x i16> ; <<4 x i16>> [#uses=1]
+ %tmp7 = tail call <4 x i16> @llvm.x86.mmx.paddus.w( <4 x i16> %tmp6, <4 x i16> %tmp4 ) ; <<4 x i16>> [#uses=1]
+ %tmp8 = bitcast <4 x i16> %tmp7 to <1 x i64> ; <<1 x i64>> [#uses=1]
+ store <1 x i64> %tmp8, <1 x i64>* @R
+ tail call void @llvm.x86.mmx.emms( )
+ ret void
+}
+
+declare <4 x i16> @llvm.x86.mmx.paddus.w(<4 x i16>, <4 x i16>)
+
+declare void @llvm.x86.mmx.emms()
diff --git a/test/CodeGen/X86/2007-06-28-X86-64-isel.ll b/test/CodeGen/X86/2007-06-28-X86-64-isel.ll
new file mode 100644
index 0000000..9d42c49
--- /dev/null
+++ b/test/CodeGen/X86/2007-06-28-X86-64-isel.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse2
+
+define void @test() {
+ %tmp1 = call <8 x i16> @llvm.x86.sse2.pmins.w( <8 x i16> zeroinitializer, <8 x i16> bitcast (<4 x i32> < i32 7, i32 7, i32 7, i32 7 > to <8 x i16>) )
+ %tmp2 = bitcast <8 x i16> %tmp1 to <4 x i32>
+ br i1 false, label %bb1, label %bb2
+
+bb2:
+ %tmp38007.i = extractelement <4 x i32> %tmp2, i32 3
+ ret void
+
+bb1:
+ ret void
+}
+
+declare <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16>, <8 x i16>)
diff --git a/test/CodeGen/X86/2007-06-29-DAGCombinerBug.ll b/test/CodeGen/X86/2007-06-29-DAGCombinerBug.ll
new file mode 100644
index 0000000..d2d6388
--- /dev/null
+++ b/test/CodeGen/X86/2007-06-29-DAGCombinerBug.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+
+define void @test() {
+entry:
+ br i1 false, label %bb13944.preheader, label %cond_true418
+
+cond_true418: ; preds = %entry
+ ret void
+
+bb13944.preheader: ; preds = %entry
+ br i1 false, label %bb3517, label %bb13968.preheader
+
+bb3517: ; preds = %bb13944.preheader
+ br i1 false, label %cond_false7408, label %cond_next11422
+
+cond_false7408: ; preds = %bb3517
+ switch i32 0, label %cond_false10578 [
+ i32 7, label %cond_next11422
+ i32 6, label %cond_true7828
+ i32 1, label %cond_true10095
+ i32 3, label %cond_true10095
+ i32 5, label %cond_true10176
+ i32 24, label %cond_true10176
+ ]
+
+cond_true7828: ; preds = %cond_false7408
+ br i1 false, label %cond_next8191, label %cond_true8045
+
+cond_true8045: ; preds = %cond_true7828
+ ret void
+
+cond_next8191: ; preds = %cond_true7828
+ %tmp8234 = sub <4 x i32> < i32 939524096, i32 939524096, i32 939524096, i32 939524096 >, zeroinitializer ; <<4 x i32>> [#uses=0]
+ ret void
+
+cond_true10095: ; preds = %cond_false7408, %cond_false7408
+ ret void
+
+cond_true10176: ; preds = %cond_false7408, %cond_false7408
+ ret void
+
+cond_false10578: ; preds = %cond_false7408
+ ret void
+
+cond_next11422: ; preds = %cond_false7408, %bb3517
+ ret void
+
+bb13968.preheader: ; preds = %bb13944.preheader
+ ret void
+}
diff --git a/test/CodeGen/X86/2007-06-29-VecFPConstantCSEBug.ll b/test/CodeGen/X86/2007-06-29-VecFPConstantCSEBug.ll
new file mode 100644
index 0000000..dc11eec9
--- /dev/null
+++ b/test/CodeGen/X86/2007-06-29-VecFPConstantCSEBug.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+
+define void @test(<4 x float>* %arg) {
+ %tmp89 = getelementptr <4 x float>* %arg, i64 3
+ %tmp1144 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, zeroinitializer
+ store <4 x float> %tmp1144, <4 x float>* null
+ %tmp1149 = load <4 x float>* %tmp89
+ %tmp1150 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1149
+ store <4 x float> %tmp1150, <4 x float>* %tmp89
+ ret void
+}
diff --git a/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll b/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll
new file mode 100644
index 0000000..2c513f1
--- /dev/null
+++ b/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {movd %rsi, %mm0}
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {movd %rdi, %mm1}
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {paddusw %mm0, %mm1}
+
+@R = external global <1 x i64> ; <<1 x i64>*> [#uses=1]
+
+define void @foo(<1 x i64> %A, <1 x i64> %B) nounwind {
+entry:
+ %tmp4 = bitcast <1 x i64> %B to <4 x i16> ; <<4 x i16>> [#uses=1]
+ %tmp6 = bitcast <1 x i64> %A to <4 x i16> ; <<4 x i16>> [#uses=1]
+ %tmp7 = tail call <4 x i16> @llvm.x86.mmx.paddus.w( <4 x i16> %tmp6, <4 x i16> %tmp4 ) ; <<4 x i16>> [#uses=1]
+ %tmp8 = bitcast <4 x i16> %tmp7 to <1 x i64> ; <<1 x i64>> [#uses=1]
+ store <1 x i64> %tmp8, <1 x i64>* @R
+ tail call void @llvm.x86.mmx.emms( )
+ ret void
+}
+
+declare <4 x i16> @llvm.x86.mmx.paddus.w(<4 x i16>, <4 x i16>)
+
+declare void @llvm.x86.mmx.emms()
diff --git a/test/CodeGen/X86/2007-07-10-StackerAssert.ll b/test/CodeGen/X86/2007-07-10-StackerAssert.ll
new file mode 100644
index 0000000..d611677
--- /dev/null
+++ b/test/CodeGen/X86/2007-07-10-StackerAssert.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu -mcpu=athlon -relocation-model=pic
+; PR1545
+
[email protected] = external constant [56 x i8] ; <[56 x i8]*> [#uses=1]
+
+declare void @PR_LogPrint(i8*, ...)
+
+define i32 @_ZN13nsPrintEngine19SetupToPrintContentEP16nsIDeviceContextP12nsIDOMWindow() {
+entry:
+ br i1 false, label %cond_true122, label %cond_next453
+
+cond_true122: ; preds = %entry
+ br i1 false, label %bb164, label %cond_true136
+
+cond_true136: ; preds = %cond_true122
+ ret i32 0
+
+bb164: ; preds = %cond_true122
+ br i1 false, label %bb383, label %cond_true354
+
+cond_true354: ; preds = %bb164
+ ret i32 0
+
+bb383: ; preds = %bb164
+ %tmp408 = load float* null ; <float> [#uses=2]
+ br i1 false, label %cond_true425, label %cond_next443
+
+cond_true425: ; preds = %bb383
+ %tmp430 = load float* null ; <float> [#uses=1]
+ %tmp432 = fsub float %tmp430, %tmp408 ; <float> [#uses=1]
+ %tmp432433 = fpext float %tmp432 to double ; <double> [#uses=1]
+ %tmp434435 = fpext float %tmp408 to double ; <double> [#uses=1]
+ call void (i8*, ...)* @PR_LogPrint( i8* getelementptr ([56 x i8]* @.str97, i32 0, i32 0), double 0.000000e+00, double %tmp434435, double %tmp432433 )
+ ret i32 0
+
+cond_next443: ; preds = %bb383
+ ret i32 0
+
+cond_next453: ; preds = %entry
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2007-07-18-Vector-Extract.ll b/test/CodeGen/X86/2007-07-18-Vector-Extract.ll
new file mode 100644
index 0000000..8625b27
--- /dev/null
+++ b/test/CodeGen/X86/2007-07-18-Vector-Extract.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse | grep {movq (%rdi), %rax}
+; RUN: llc < %s -march=x86-64 -mattr=+sse | grep {movq 8(%rdi), %rax}
+define i64 @foo_0(<2 x i64>* %val) {
+entry:
+ %val12 = getelementptr <2 x i64>* %val, i32 0, i32 0 ; <i64*> [#uses=1]
+ %tmp7 = load i64* %val12 ; <i64> [#uses=1]
+ ret i64 %tmp7
+}
+
+define i64 @foo_1(<2 x i64>* %val) {
+entry:
+ %tmp2.gep = getelementptr <2 x i64>* %val, i32 0, i32 1 ; <i64*> [#uses=1]
+ %tmp4 = load i64* %tmp2.gep ; <i64> [#uses=1]
+ ret i64 %tmp4
+}
diff --git a/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll b/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll
new file mode 100644
index 0000000..3cd8052
--- /dev/null
+++ b/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 | not grep movl
+
+define i8 @t(i8 zeroext %x, i8 zeroext %y) zeroext {
+ %tmp2 = add i8 %x, 2
+ %tmp4 = add i8 %y, -2
+ %tmp5 = mul i8 %tmp4, %tmp2
+ ret i8 %tmp5
+}
diff --git a/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll b/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
new file mode 100644
index 0000000..7768f36
--- /dev/null
+++ b/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
@@ -0,0 +1,235 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep "movb %ah, %r"
+
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, [4 x i8], i64 }
+ %struct.PyBoolScalarObject = type { i64, %struct._typeobject*, i8 }
+ %struct.PyBufferProcs = type { i64 (%struct.PyObject*, i64, i8**)*, i64 (%struct.PyObject*, i64, i8**)*, i64 (%struct.PyObject*, i64*)*, i64 (%struct.PyObject*, i64, i8**)* }
+ %struct.PyGetSetDef = type { i8*, %struct.PyObject* (%struct.PyObject*, i8*)*, i32 (%struct.PyObject*, %struct.PyObject*, i8*)*, i8*, i8* }
+ %struct.PyMappingMethods = type { i64 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)* }
+ %struct.PyMemberDef = type opaque
+ %struct.PyMethodDef = type { i8*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, i32, i8* }
+ %struct.PyNumberMethods = type { %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, i32 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, i32 (%struct.PyObject**, %struct.PyObject**)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)* }
+ %struct.PyObject = type { i64, %struct._typeobject* }
+ %struct.PySequenceMethods = type { i64 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, i64)*, %struct.PyObject* (%struct.PyObject*, i64)*, %struct.PyObject* (%struct.PyObject*, i64, i64)*, i32 (%struct.PyObject*, i64, %struct.PyObject*)*, i32 (%struct.PyObject*, i64, i64, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, i64)* }
+ %struct.PyTupleObject = type { i64, %struct._typeobject*, i64, [1 x %struct.PyObject*] }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+ %struct._typeobject = type { i64, %struct._typeobject*, i64, i8*, i64, i64, void (%struct.PyObject*)*, i32 (%struct.PyObject*, %struct.FILE*, i32)*, %struct.PyObject* (%struct.PyObject*, i8*)*, i32 (%struct.PyObject*, i8*, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyNumberMethods*, %struct.PySequenceMethods*, %struct.PyMappingMethods*, i64 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyBufferProcs*, i64, i8*, i32 (%struct.PyObject*, i32 (%struct.PyObject*, i8*)*, i8*)*, i32 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, i32)*, i64, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyMethodDef*, %struct.PyMemberDef*, %struct.PyGetSetDef*, %struct._typeobject*, %struct.PyObject*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, i64, i32 (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct._typeobject*, i64)*, %struct.PyObject* (%struct._typeobject*, %struct.PyObject*, %struct.PyObject*)*, void (i8*)*, i32 (%struct.PyObject*)*, %struct.PyObject*, %struct.PyObject*, %struct.PyObject*, %struct.PyObject*, %struct.PyObject*, void (%struct.PyObject*)* }
+@PyArray_API = external global i8** ; <i8***> [#uses=4]
+@PyUFunc_API = external global i8** ; <i8***> [#uses=4]
[email protected] = external constant [14 x i8] ; <[14 x i8]*> [#uses=1]
+
+define %struct.PyObject* @ubyte_divmod(%struct.PyObject* %a, %struct.PyObject* %b) {
+entry:
+ %arg1 = alloca i8, align 1 ; <i8*> [#uses=3]
+ %arg2 = alloca i8, align 1 ; <i8*> [#uses=3]
+ %first = alloca i32, align 4 ; <i32*> [#uses=2]
+ %bufsize = alloca i32, align 4 ; <i32*> [#uses=1]
+ %errmask = alloca i32, align 4 ; <i32*> [#uses=2]
+ %errobj = alloca %struct.PyObject*, align 8 ; <%struct.PyObject**> [#uses=2]
+ %tmp3.i = call fastcc i32 @_ubyte_convert_to_ctype( %struct.PyObject* %a, i8* %arg1 ) ; <i32> [#uses=2]
+ %tmp5.i = icmp slt i32 %tmp3.i, 0 ; <i1> [#uses=1]
+ br i1 %tmp5.i, label %_ubyte_convert2_to_ctypes.exit, label %cond_next.i
+
+cond_next.i: ; preds = %entry
+ %tmp11.i = call fastcc i32 @_ubyte_convert_to_ctype( %struct.PyObject* %b, i8* %arg2 ) ; <i32> [#uses=2]
+ %tmp13.i = icmp slt i32 %tmp11.i, 0 ; <i1> [#uses=1]
+ %retval.i = select i1 %tmp13.i, i32 %tmp11.i, i32 0 ; <i32> [#uses=1]
+ switch i32 %retval.i, label %bb35 [
+ i32 -2, label %bb17
+ i32 -1, label %bb4
+ ]
+
+_ubyte_convert2_to_ctypes.exit: ; preds = %entry
+ switch i32 %tmp3.i, label %bb35 [
+ i32 -2, label %bb17
+ i32 -1, label %bb4
+ ]
+
+bb4: ; preds = %_ubyte_convert2_to_ctypes.exit, %cond_next.i
+ %tmp5 = load i8*** @PyArray_API, align 8 ; <i8**> [#uses=1]
+ %tmp6 = getelementptr i8** %tmp5, i64 2 ; <i8**> [#uses=1]
+ %tmp7 = load i8** %tmp6 ; <i8*> [#uses=1]
+ %tmp78 = bitcast i8* %tmp7 to %struct._typeobject* ; <%struct._typeobject*> [#uses=1]
+ %tmp9 = getelementptr %struct._typeobject* %tmp78, i32 0, i32 12 ; <%struct.PyNumberMethods**> [#uses=1]
+ %tmp10 = load %struct.PyNumberMethods** %tmp9 ; <%struct.PyNumberMethods*> [#uses=1]
+ %tmp11 = getelementptr %struct.PyNumberMethods* %tmp10, i32 0, i32 5 ; <%struct.PyObject* (%struct.PyObject*, %struct.PyObject*)**> [#uses=1]
+ %tmp12 = load %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)** %tmp11 ; <%struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*> [#uses=1]
+ %tmp15 = call %struct.PyObject* %tmp12( %struct.PyObject* %a, %struct.PyObject* %b ) ; <%struct.PyObject*> [#uses=1]
+ ret %struct.PyObject* %tmp15
+
+bb17: ; preds = %_ubyte_convert2_to_ctypes.exit, %cond_next.i
+ %tmp18 = call %struct.PyObject* @PyErr_Occurred( ) ; <%struct.PyObject*> [#uses=1]
+ %tmp19 = icmp eq %struct.PyObject* %tmp18, null ; <i1> [#uses=1]
+ br i1 %tmp19, label %cond_next, label %UnifiedReturnBlock
+
+cond_next: ; preds = %bb17
+ %tmp22 = load i8*** @PyArray_API, align 8 ; <i8**> [#uses=1]
+ %tmp23 = getelementptr i8** %tmp22, i64 10 ; <i8**> [#uses=1]
+ %tmp24 = load i8** %tmp23 ; <i8*> [#uses=1]
+ %tmp2425 = bitcast i8* %tmp24 to %struct._typeobject* ; <%struct._typeobject*> [#uses=1]
+ %tmp26 = getelementptr %struct._typeobject* %tmp2425, i32 0, i32 12 ; <%struct.PyNumberMethods**> [#uses=1]
+ %tmp27 = load %struct.PyNumberMethods** %tmp26 ; <%struct.PyNumberMethods*> [#uses=1]
+ %tmp28 = getelementptr %struct.PyNumberMethods* %tmp27, i32 0, i32 5 ; <%struct.PyObject* (%struct.PyObject*, %struct.PyObject*)**> [#uses=1]
+ %tmp29 = load %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)** %tmp28 ; <%struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*> [#uses=1]
+ %tmp32 = call %struct.PyObject* %tmp29( %struct.PyObject* %a, %struct.PyObject* %b ) ; <%struct.PyObject*> [#uses=1]
+ ret %struct.PyObject* %tmp32
+
+bb35: ; preds = %_ubyte_convert2_to_ctypes.exit, %cond_next.i
+ %tmp36 = load i8*** @PyUFunc_API, align 8 ; <i8**> [#uses=1]
+ %tmp37 = getelementptr i8** %tmp36, i64 27 ; <i8**> [#uses=1]
+ %tmp38 = load i8** %tmp37 ; <i8*> [#uses=1]
+ %tmp3839 = bitcast i8* %tmp38 to void ()* ; <void ()*> [#uses=1]
+ call void %tmp3839( )
+ %tmp40 = load i8* %arg2, align 1 ; <i8> [#uses=4]
+ %tmp1.i = icmp eq i8 %tmp40, 0 ; <i1> [#uses=2]
+ br i1 %tmp1.i, label %cond_true.i, label %cond_false.i
+
+cond_true.i: ; preds = %bb35
+ %tmp3.i196 = call i32 @feraiseexcept( i32 4 ) ; <i32> [#uses=0]
+ %tmp46207 = load i8* %arg2, align 1 ; <i8> [#uses=3]
+ %tmp48208 = load i8* %arg1, align 1 ; <i8> [#uses=2]
+ %tmp1.i197210 = icmp eq i8 %tmp48208, 0 ; <i1> [#uses=1]
+ %tmp4.i212 = icmp eq i8 %tmp46207, 0 ; <i1> [#uses=1]
+ %tmp7.i198213 = or i1 %tmp1.i197210, %tmp4.i212 ; <i1> [#uses=1]
+ br i1 %tmp7.i198213, label %cond_true.i200, label %cond_next17.i
+
+cond_false.i: ; preds = %bb35
+ %tmp42 = load i8* %arg1, align 1 ; <i8> [#uses=3]
+ %tmp7.i = udiv i8 %tmp42, %tmp40 ; <i8> [#uses=2]
+ %tmp1.i197 = icmp eq i8 %tmp42, 0 ; <i1> [#uses=1]
+ %tmp7.i198 = or i1 %tmp1.i197, %tmp1.i ; <i1> [#uses=1]
+ br i1 %tmp7.i198, label %cond_true.i200, label %cond_next17.i
+
+cond_true.i200: ; preds = %cond_false.i, %cond_true.i
+ %out.0 = phi i8 [ 0, %cond_true.i ], [ %tmp7.i, %cond_false.i ] ; <i8> [#uses=2]
+ %tmp46202.0 = phi i8 [ %tmp46207, %cond_true.i ], [ %tmp40, %cond_false.i ] ; <i8> [#uses=1]
+ %tmp11.i199 = icmp eq i8 %tmp46202.0, 0 ; <i1> [#uses=1]
+ br i1 %tmp11.i199, label %cond_true14.i, label %ubyte_ctype_remainder.exit
+
+cond_true14.i: ; preds = %cond_true.i200
+ %tmp15.i = call i32 @feraiseexcept( i32 4 ) ; <i32> [#uses=0]
+ br label %ubyte_ctype_remainder.exit
+
+cond_next17.i: ; preds = %cond_false.i, %cond_true.i
+ %out.1 = phi i8 [ 0, %cond_true.i ], [ %tmp7.i, %cond_false.i ] ; <i8> [#uses=1]
+ %tmp46202.1 = phi i8 [ %tmp46207, %cond_true.i ], [ %tmp40, %cond_false.i ] ; <i8> [#uses=1]
+ %tmp48205.1 = phi i8 [ %tmp48208, %cond_true.i ], [ %tmp42, %cond_false.i ] ; <i8> [#uses=1]
+ %tmp20.i = urem i8 %tmp48205.1, %tmp46202.1 ; <i8> [#uses=1]
+ br label %ubyte_ctype_remainder.exit
+
+ubyte_ctype_remainder.exit: ; preds = %cond_next17.i, %cond_true14.i, %cond_true.i200
+ %out2.0 = phi i8 [ %tmp20.i, %cond_next17.i ], [ 0, %cond_true14.i ], [ 0, %cond_true.i200 ] ; <i8> [#uses=1]
+ %out.2 = phi i8 [ %out.1, %cond_next17.i ], [ %out.0, %cond_true14.i ], [ %out.0, %cond_true.i200 ] ; <i8> [#uses=1]
+ %tmp52 = load i8*** @PyUFunc_API, align 8 ; <i8**> [#uses=1]
+ %tmp53 = getelementptr i8** %tmp52, i64 28 ; <i8**> [#uses=1]
+ %tmp54 = load i8** %tmp53 ; <i8*> [#uses=1]
+ %tmp5455 = bitcast i8* %tmp54 to i32 ()* ; <i32 ()*> [#uses=1]
+ %tmp56 = call i32 %tmp5455( ) ; <i32> [#uses=2]
+ %tmp58 = icmp eq i32 %tmp56, 0 ; <i1> [#uses=1]
+ br i1 %tmp58, label %cond_next89, label %cond_true61
+
+cond_true61: ; preds = %ubyte_ctype_remainder.exit
+ %tmp62 = load i8*** @PyUFunc_API, align 8 ; <i8**> [#uses=1]
+ %tmp63 = getelementptr i8** %tmp62, i64 25 ; <i8**> [#uses=1]
+ %tmp64 = load i8** %tmp63 ; <i8*> [#uses=1]
+ %tmp6465 = bitcast i8* %tmp64 to i32 (i8*, i32*, i32*, %struct.PyObject**)* ; <i32 (i8*, i32*, i32*, %struct.PyObject**)*> [#uses=1]
+ %tmp67 = call i32 %tmp6465( i8* getelementptr ([14 x i8]* @.str5, i32 0, i64 0), i32* %bufsize, i32* %errmask, %struct.PyObject** %errobj ) ; <i32> [#uses=1]
+ %tmp68 = icmp slt i32 %tmp67, 0 ; <i1> [#uses=1]
+ br i1 %tmp68, label %UnifiedReturnBlock, label %cond_next73
+
+cond_next73: ; preds = %cond_true61
+ store i32 1, i32* %first, align 4
+ %tmp74 = load i8*** @PyUFunc_API, align 8 ; <i8**> [#uses=1]
+ %tmp75 = getelementptr i8** %tmp74, i64 29 ; <i8**> [#uses=1]
+ %tmp76 = load i8** %tmp75 ; <i8*> [#uses=1]
+ %tmp7677 = bitcast i8* %tmp76 to i32 (i32, %struct.PyObject*, i32, i32*)* ; <i32 (i32, %struct.PyObject*, i32, i32*)*> [#uses=1]
+ %tmp79 = load %struct.PyObject** %errobj, align 8 ; <%struct.PyObject*> [#uses=1]
+ %tmp80 = load i32* %errmask, align 4 ; <i32> [#uses=1]
+ %tmp82 = call i32 %tmp7677( i32 %tmp80, %struct.PyObject* %tmp79, i32 %tmp56, i32* %first ) ; <i32> [#uses=1]
+ %tmp83 = icmp eq i32 %tmp82, 0 ; <i1> [#uses=1]
+ br i1 %tmp83, label %cond_next89, label %UnifiedReturnBlock
+
+cond_next89: ; preds = %cond_next73, %ubyte_ctype_remainder.exit
+ %tmp90 = call %struct.PyObject* @PyTuple_New( i64 2 ) ; <%struct.PyObject*> [#uses=9]
+ %tmp92 = icmp eq %struct.PyObject* %tmp90, null ; <i1> [#uses=1]
+ br i1 %tmp92, label %UnifiedReturnBlock, label %cond_next97
+
+cond_next97: ; preds = %cond_next89
+ %tmp98 = load i8*** @PyArray_API, align 8 ; <i8**> [#uses=1]
+ %tmp99 = getelementptr i8** %tmp98, i64 25 ; <i8**> [#uses=1]
+ %tmp100 = load i8** %tmp99 ; <i8*> [#uses=1]
+ %tmp100101 = bitcast i8* %tmp100 to %struct._typeobject* ; <%struct._typeobject*> [#uses=2]
+ %tmp102 = getelementptr %struct._typeobject* %tmp100101, i32 0, i32 38 ; <%struct.PyObject* (%struct._typeobject*, i64)**> [#uses=1]
+ %tmp103 = load %struct.PyObject* (%struct._typeobject*, i64)** %tmp102 ; <%struct.PyObject* (%struct._typeobject*, i64)*> [#uses=1]
+ %tmp108 = call %struct.PyObject* %tmp103( %struct._typeobject* %tmp100101, i64 0 ) ; <%struct.PyObject*> [#uses=3]
+ %tmp110 = icmp eq %struct.PyObject* %tmp108, null ; <i1> [#uses=1]
+ br i1 %tmp110, label %cond_true113, label %cond_next135
+
+cond_true113: ; preds = %cond_next97
+ %tmp115 = getelementptr %struct.PyObject* %tmp90, i32 0, i32 0 ; <i64*> [#uses=2]
+ %tmp116 = load i64* %tmp115 ; <i64> [#uses=1]
+ %tmp117 = add i64 %tmp116, -1 ; <i64> [#uses=2]
+ store i64 %tmp117, i64* %tmp115
+ %tmp123 = icmp eq i64 %tmp117, 0 ; <i1> [#uses=1]
+ br i1 %tmp123, label %cond_true126, label %UnifiedReturnBlock
+
+cond_true126: ; preds = %cond_true113
+ %tmp128 = getelementptr %struct.PyObject* %tmp90, i32 0, i32 1 ; <%struct._typeobject**> [#uses=1]
+ %tmp129 = load %struct._typeobject** %tmp128 ; <%struct._typeobject*> [#uses=1]
+ %tmp130 = getelementptr %struct._typeobject* %tmp129, i32 0, i32 6 ; <void (%struct.PyObject*)**> [#uses=1]
+ %tmp131 = load void (%struct.PyObject*)** %tmp130 ; <void (%struct.PyObject*)*> [#uses=1]
+ call void %tmp131( %struct.PyObject* %tmp90 )
+ ret %struct.PyObject* null
+
+cond_next135: ; preds = %cond_next97
+ %tmp136137 = bitcast %struct.PyObject* %tmp108 to %struct.PyBoolScalarObject* ; <%struct.PyBoolScalarObject*> [#uses=1]
+ %tmp139 = getelementptr %struct.PyBoolScalarObject* %tmp136137, i32 0, i32 2 ; <i8*> [#uses=1]
+ store i8 %out.2, i8* %tmp139
+ %tmp140141 = bitcast %struct.PyObject* %tmp90 to %struct.PyTupleObject* ; <%struct.PyTupleObject*> [#uses=2]
+ %tmp143 = getelementptr %struct.PyTupleObject* %tmp140141, i32 0, i32 3, i64 0 ; <%struct.PyObject**> [#uses=1]
+ store %struct.PyObject* %tmp108, %struct.PyObject** %tmp143
+ %tmp145 = load i8*** @PyArray_API, align 8 ; <i8**> [#uses=1]
+ %tmp146 = getelementptr i8** %tmp145, i64 25 ; <i8**> [#uses=1]
+ %tmp147 = load i8** %tmp146 ; <i8*> [#uses=1]
+ %tmp147148 = bitcast i8* %tmp147 to %struct._typeobject* ; <%struct._typeobject*> [#uses=2]
+ %tmp149 = getelementptr %struct._typeobject* %tmp147148, i32 0, i32 38 ; <%struct.PyObject* (%struct._typeobject*, i64)**> [#uses=1]
+ %tmp150 = load %struct.PyObject* (%struct._typeobject*, i64)** %tmp149 ; <%struct.PyObject* (%struct._typeobject*, i64)*> [#uses=1]
+ %tmp155 = call %struct.PyObject* %tmp150( %struct._typeobject* %tmp147148, i64 0 ) ; <%struct.PyObject*> [#uses=3]
+ %tmp157 = icmp eq %struct.PyObject* %tmp155, null ; <i1> [#uses=1]
+ br i1 %tmp157, label %cond_true160, label %cond_next182
+
+cond_true160: ; preds = %cond_next135
+ %tmp162 = getelementptr %struct.PyObject* %tmp90, i32 0, i32 0 ; <i64*> [#uses=2]
+ %tmp163 = load i64* %tmp162 ; <i64> [#uses=1]
+ %tmp164 = add i64 %tmp163, -1 ; <i64> [#uses=2]
+ store i64 %tmp164, i64* %tmp162
+ %tmp170 = icmp eq i64 %tmp164, 0 ; <i1> [#uses=1]
+ br i1 %tmp170, label %cond_true173, label %UnifiedReturnBlock
+
+cond_true173: ; preds = %cond_true160
+ %tmp175 = getelementptr %struct.PyObject* %tmp90, i32 0, i32 1 ; <%struct._typeobject**> [#uses=1]
+ %tmp176 = load %struct._typeobject** %tmp175 ; <%struct._typeobject*> [#uses=1]
+ %tmp177 = getelementptr %struct._typeobject* %tmp176, i32 0, i32 6 ; <void (%struct.PyObject*)**> [#uses=1]
+ %tmp178 = load void (%struct.PyObject*)** %tmp177 ; <void (%struct.PyObject*)*> [#uses=1]
+ call void %tmp178( %struct.PyObject* %tmp90 )
+ ret %struct.PyObject* null
+
+cond_next182: ; preds = %cond_next135
+ %tmp183184 = bitcast %struct.PyObject* %tmp155 to %struct.PyBoolScalarObject* ; <%struct.PyBoolScalarObject*> [#uses=1]
+ %tmp186 = getelementptr %struct.PyBoolScalarObject* %tmp183184, i32 0, i32 2 ; <i8*> [#uses=1]
+ store i8 %out2.0, i8* %tmp186
+ %tmp190 = getelementptr %struct.PyTupleObject* %tmp140141, i32 0, i32 3, i64 1 ; <%struct.PyObject**> [#uses=1]
+ store %struct.PyObject* %tmp155, %struct.PyObject** %tmp190
+ ret %struct.PyObject* %tmp90
+
+UnifiedReturnBlock: ; preds = %cond_true160, %cond_true113, %cond_next89, %cond_next73, %cond_true61, %bb17
+ ret %struct.PyObject* null
+}
+
+declare i32 @feraiseexcept(i32)
+
+declare fastcc i32 @_ubyte_convert_to_ctype(%struct.PyObject*, i8*)
+
+declare %struct.PyObject* @PyErr_Occurred()
+
+declare %struct.PyObject* @PyTuple_New(i64)
diff --git a/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll b/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
new file mode 100644
index 0000000..e93092f
--- /dev/null
+++ b/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 | grep {movsbl}
+
+@X = global i32 0 ; <i32*> [#uses=1]
+
+define i8 @_Z3fooi(i32 %x) signext {
+entry:
+ store i32 %x, i32* @X, align 4
+ %retval67 = trunc i32 %x to i8 ; <i8> [#uses=1]
+ ret i8 %retval67
+}
diff --git a/test/CodeGen/X86/2007-08-13-AppendingLinkage.ll b/test/CodeGen/X86/2007-08-13-AppendingLinkage.ll
new file mode 100644
index 0000000..c90a85f1
--- /dev/null
+++ b/test/CodeGen/X86/2007-08-13-AppendingLinkage.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 | not grep drectve
+; PR1607
+
+%hlvm_programs_element = type { i8*, i32 (i32, i8**)* }
+@hlvm_programs = appending constant [1 x %hlvm_programs_element]
+zeroinitializer
+
+define %hlvm_programs_element* @hlvm_get_programs() {
+entry:
+ ret %hlvm_programs_element* getelementptr([1 x %hlvm_programs_element]*
+ @hlvm_programs, i32 0, i32 0)
+}
diff --git a/test/CodeGen/X86/2007-09-05-InvalidAsm.ll b/test/CodeGen/X86/2007-09-05-InvalidAsm.ll
new file mode 100644
index 0000000..5acb051
--- /dev/null
+++ b/test/CodeGen/X86/2007-09-05-InvalidAsm.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -x86-asm-syntax=intel | not grep {lea\[\[:space:\]\]R}
+
+ %struct.AGenericCall = type { %struct.AGenericManager*, %struct.ComponentParameters*, i32* }
+ %struct.AGenericManager = type <{ i8 }>
+ %struct.ComponentInstanceRecord = type opaque
+ %struct.ComponentParameters = type { [1 x i64] }
+
+define i32 @_ZN12AGenericCall10MapIDPtrAtEsRP23ComponentInstanceRecord(%struct.AGenericCall* %this, i16 signext %param, %struct.ComponentInstanceRecord** %instance) {
+entry:
+ %tmp4 = icmp slt i16 %param, 0 ; <i1> [#uses=1]
+ br i1 %tmp4, label %cond_true, label %cond_next
+
+cond_true: ; preds = %entry
+ %tmp1415 = shl i16 %param, 3 ; <i16> [#uses=1]
+ %tmp17 = getelementptr %struct.AGenericCall* %this, i32 0, i32 1 ; <%struct.ComponentParameters**> [#uses=1]
+ %tmp18 = load %struct.ComponentParameters** %tmp17, align 8 ; <%struct.ComponentParameters*> [#uses=1]
+ %tmp1920 = bitcast %struct.ComponentParameters* %tmp18 to i8* ; <i8*> [#uses=1]
+ %tmp212223 = sext i16 %tmp1415 to i64 ; <i64> [#uses=1]
+ %tmp24 = getelementptr i8* %tmp1920, i64 %tmp212223 ; <i8*> [#uses=1]
+ %tmp2425 = bitcast i8* %tmp24 to i64* ; <i64*> [#uses=1]
+ %tmp28 = load i64* %tmp2425, align 8 ; <i64> [#uses=1]
+ %tmp2829 = inttoptr i64 %tmp28 to i32* ; <i32*> [#uses=1]
+ %tmp31 = getelementptr %struct.AGenericCall* %this, i32 0, i32 2 ; <i32**> [#uses=1]
+ store i32* %tmp2829, i32** %tmp31, align 8
+ br label %cond_next
+
+cond_next: ; preds = %cond_true, %entry
+ %tmp4243 = shl i16 %param, 3 ; <i16> [#uses=1]
+ %tmp46 = getelementptr %struct.AGenericCall* %this, i32 0, i32 1 ; <%struct.ComponentParameters**> [#uses=1]
+ %tmp47 = load %struct.ComponentParameters** %tmp46, align 8 ; <%struct.ComponentParameters*> [#uses=1]
+ %tmp4849 = bitcast %struct.ComponentParameters* %tmp47 to i8* ; <i8*> [#uses=1]
+ %tmp505152 = sext i16 %tmp4243 to i64 ; <i64> [#uses=1]
+ %tmp53 = getelementptr i8* %tmp4849, i64 %tmp505152 ; <i8*> [#uses=1]
+ %tmp5354 = bitcast i8* %tmp53 to i64* ; <i64*> [#uses=1]
+ %tmp58 = load i64* %tmp5354, align 8 ; <i64> [#uses=1]
+ %tmp59 = icmp eq i64 %tmp58, 0 ; <i1> [#uses=1]
+ br i1 %tmp59, label %UnifiedReturnBlock, label %cond_true63
+
+cond_true63: ; preds = %cond_next
+ %tmp65 = getelementptr %struct.AGenericCall* %this, i32 0, i32 0 ; <%struct.AGenericManager**> [#uses=1]
+ %tmp66 = load %struct.AGenericManager** %tmp65, align 8 ; <%struct.AGenericManager*> [#uses=1]
+ %tmp69 = tail call i32 @_ZN15AGenericManager24DefaultComponentInstanceERP23ComponentInstanceRecord( %struct.AGenericManager* %tmp66, %struct.ComponentInstanceRecord** %instance ) ; <i32> [#uses=1]
+ ret i32 %tmp69
+
+UnifiedReturnBlock: ; preds = %cond_next
+ ret i32 undef
+}
+
+declare i32 @_ZN15AGenericManager24DefaultComponentInstanceERP23ComponentInstanceRecord(%struct.AGenericManager*, %struct.ComponentInstanceRecord**)
diff --git a/test/CodeGen/X86/2007-09-06-ExtWeakAliasee.ll b/test/CodeGen/X86/2007-09-06-ExtWeakAliasee.ll
new file mode 100644
index 0000000..c5d2a46
--- /dev/null
+++ b/test/CodeGen/X86/2007-09-06-ExtWeakAliasee.ll
@@ -0,0 +1,4 @@
+; RUN: llc < %s -march=x86 | grep weak | count 2
+@__gthrw_pthread_once = alias weak i32 (i32*, void ()*)* @pthread_once ; <i32 (i32*, void ()*)*> [#uses=0]
+
+declare extern_weak i32 @pthread_once(i32*, void ()*)
diff --git a/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll b/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll
new file mode 100644
index 0000000..56ee2a3
--- /dev/null
+++ b/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll
@@ -0,0 +1,65 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin -enable-eh | grep {isNullOrNil].eh"} | count 2
+
+ %struct.NSString = type { }
+ %struct._objc__method_prototype_list = type opaque
+ %struct._objc_category = type { i8*, i8*, %struct._objc_method_list*, %struct._objc_method_list*, %struct._objc_protocol**, i32, %struct._prop_list_t* }
+ %struct._objc_method = type { %struct.objc_selector*, i8*, i8* }
+ %struct._objc_method_list = type opaque
+ %struct._objc_module = type { i32, i32, i8*, %struct._objc_symtab* }
+ %struct._objc_protocol = type { %struct._objc_protocol_extension*, i8*, %struct._objc_protocol**, %struct._objc__method_prototype_list*, %struct._objc__method_prototype_list* }
+ %struct._objc_protocol_extension = type opaque
+ %struct._objc_symtab = type { i32, %struct.objc_selector**, i16, i16, [1 x i8*] }
+ %struct._prop_list_t = type opaque
+ %struct.anon = type { %struct._objc__method_prototype_list*, i32, [1 x %struct._objc_method] }
+ %struct.objc_selector = type opaque
+@"\01L_OBJC_SYMBOLS" = internal global { i32, i32, i16, i16, [1 x %struct._objc_category*] } {
+ i32 0,
+ i32 0,
+ i16 0,
+ i16 1,
+ [1 x %struct._objc_category*] [ %struct._objc_category* bitcast ({ i8*, i8*, %struct._objc_method_list*, i32, i32, i32, i32 }* @"\01L_OBJC_CATEGORY_NSString_local" to %struct._objc_category*) ] }, section "__OBJC,__symbols,regular,no_dead_strip" ; <{ i32, i32, i16, i16, [1 x %struct._objc_category*] }*> [#uses=2]
+@"\01L_OBJC_CATEGORY_INSTANCE_METHODS_NSString_local" = internal global { i32, i32, [1 x %struct._objc_method] } {
+ i32 0,
+ i32 1,
+ [1 x %struct._objc_method] [ %struct._objc_method {
+ %struct.objc_selector* bitcast ([12 x i8]* @"\01L_OBJC_METH_VAR_NAME_0" to %struct.objc_selector*),
+ i8* getelementptr ([7 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0),
+ i8* bitcast (i8 (%struct.NSString*, %struct.objc_selector*) signext * @"-[NSString(local) isNullOrNil]" to i8*) } ] }, section "__OBJC,__cat_inst_meth,regular,no_dead_strip" ; <{ i32, i32, [1 x %struct._objc_method] }*> [#uses=3]
+@"\01L_OBJC_CATEGORY_NSString_local" = internal global { i8*, i8*, %struct._objc_method_list*, i32, i32, i32, i32 } {
+ i8* getelementptr ([6 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0),
+ i8* getelementptr ([9 x i8]* @"\01L_OBJC_CLASS_NAME_1", i32 0, i32 0),
+ %struct._objc_method_list* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_CATEGORY_INSTANCE_METHODS_NSString_local" to %struct._objc_method_list*),
+ i32 0,
+ i32 0,
+ i32 28,
+ i32 0 }, section "__OBJC,__category,regular,no_dead_strip" ; <{ i8*, i8*, %struct._objc_method_list*, i32, i32, i32, i32 }*> [#uses=2]
+@"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] zeroinitializer, section "__OBJC,__image_info,regular" ; <[2 x i32]*> [#uses=1]
+@"\01L_OBJC_MODULES" = internal global %struct._objc_module {
+ i32 7,
+ i32 16,
+ i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0),
+ %struct._objc_symtab* bitcast ({ i32, i32, i16, i16, [1 x %struct._objc_category*] }* @"\01L_OBJC_SYMBOLS" to %struct._objc_symtab*) }, section "__OBJC,__module_info,regular,no_dead_strip" ; <%struct._objc_module*> [#uses=1]
+@"\01.objc_class_ref_NSString" = internal global i8* @"\01.objc_class_name_NSString" ; <i8**> [#uses=0]
+@"\01.objc_class_name_NSString" = external global i8 ; <i8*> [#uses=1]
+@"\01.objc_category_name_NSString_local" = constant i32 0 ; <i32*> [#uses=1]
+@"\01L_OBJC_CLASS_NAME_2" = internal global [1 x i8] zeroinitializer, section "__TEXT,__cstring,cstring_literals" ; <[1 x i8]*> [#uses=2]
+@"\01L_OBJC_CLASS_NAME_1" = internal global [9 x i8] c"NSString\00", section "__TEXT,__cstring,cstring_literals" ; <[9 x i8]*> [#uses=2]
+@"\01L_OBJC_CLASS_NAME_0" = internal global [6 x i8] c"local\00", section "__TEXT,__cstring,cstring_literals" ; <[6 x i8]*> [#uses=2]
+@"\01L_OBJC_METH_VAR_NAME_0" = internal global [12 x i8] c"isNullOrNil\00", section "__TEXT,__cstring,cstring_literals" ; <[12 x i8]*> [#uses=3]
+@"\01L_OBJC_METH_VAR_TYPE_0" = internal global [7 x i8] c"c8@0:4\00", section "__TEXT,__cstring,cstring_literals" ; <[7 x i8]*> [#uses=2]
[email protected] = appending global [11 x i8*] [ i8* bitcast ({ i32, i32, i16, i16, [1 x %struct._objc_category*] }* @"\01L_OBJC_SYMBOLS" to i8*), i8* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_CATEGORY_INSTANCE_METHODS_NSString_local" to i8*), i8* bitcast ({ i8*, i8*, %struct._objc_method_list*, i32, i32, i32, i32 }* @"\01L_OBJC_CATEGORY_NSString_local" to i8*), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*), i8* bitcast (%struct._objc_module* @"\01L_OBJC_MODULES" to i8*), i8* bitcast (i32* @"\01.objc_category_name_NSString_local" to i8*), i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0), i8* getelementptr ([9 x i8]* @"\01L_OBJC_CLASS_NAME_1", i32 0, i32 0), i8* getelementptr ([6 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i8* getelementptr ([12 x i8]* @"\01L_OBJC_METH_VAR_NAME_0", i32 0, i32 0), i8* getelementptr ([7 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0) ], section "llvm.metadata" ; <[11 x i8*]*> [#uses=0]
+
+define internal i8 @"-[NSString(local) isNullOrNil]"(%struct.NSString* %self, %struct.objc_selector* %_cmd) signext {
+entry:
+ %self_addr = alloca %struct.NSString* ; <%struct.NSString**> [#uses=1]
+ %_cmd_addr = alloca %struct.objc_selector* ; <%struct.objc_selector**> [#uses=1]
+ %retval = alloca i8, align 1 ; <i8*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store %struct.NSString* %self, %struct.NSString** %self_addr
+ store %struct.objc_selector* %_cmd, %struct.objc_selector** %_cmd_addr
+ br label %return
+
+return: ; preds = %entry
+ %retval1 = load i8* %retval ; <i8> [#uses=1]
+ ret i8 %retval1
+}
diff --git a/test/CodeGen/X86/2007-09-18-ShuffleXformBug.ll b/test/CodeGen/X86/2007-09-18-ShuffleXformBug.ll
new file mode 100644
index 0000000..0ae1897
--- /dev/null
+++ b/test/CodeGen/X86/2007-09-18-ShuffleXformBug.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep -- -86
+
+define i16 @f(<4 x float>* %tmp116117.i1061.i) nounwind {
+entry:
+ alloca [4 x <4 x float>] ; <[4 x <4 x float>]*>:0 [#uses=167]
+ alloca [4 x <4 x float>] ; <[4 x <4 x float>]*>:1 [#uses=170]
+ alloca [4 x <4 x i32>] ; <[4 x <4 x i32>]*>:2 [#uses=12]
+ %.sub6235.i = getelementptr [4 x <4 x float>]* %0, i32 0, i32 0 ; <<4 x float>*> [#uses=76]
+ %.sub.i = getelementptr [4 x <4 x float>]* %1, i32 0, i32 0 ; <<4 x float>*> [#uses=59]
+
+ %tmp124.i1062.i = getelementptr <4 x float>* %tmp116117.i1061.i, i32 63 ; <<4 x float>*> [#uses=1]
+ %tmp125.i1063.i = load <4 x float>* %tmp124.i1062.i ; <<4 x float>> [#uses=5]
+ %tmp828.i1077.i = shufflevector <4 x float> %tmp125.i1063.i, <4 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x float>> [#uses=4]
+ %tmp704.i1085.i = load <4 x float>* %.sub6235.i ; <<4 x float>> [#uses=1]
+ %tmp712.i1086.i = call <4 x float> @llvm.x86.sse.max.ps( <4 x float> %tmp704.i1085.i, <4 x float> %tmp828.i1077.i ) ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp712.i1086.i, <4 x float>* %.sub.i
+
+ %tmp2587.i1145.gep.i = getelementptr [4 x <4 x float>]* %1, i32 0, i32 0, i32 2 ; <float*> [#uses=1]
+ %tmp5334.i = load float* %tmp2587.i1145.gep.i ; <float> [#uses=5]
+ %tmp2723.i1170.i = insertelement <4 x float> undef, float %tmp5334.i, i32 2 ; <<4 x float>> [#uses=5]
+ store <4 x float> %tmp2723.i1170.i, <4 x float>* %.sub6235.i
+
+ %tmp1406.i1367.i = shufflevector <4 x float> %tmp2723.i1170.i, <4 x float> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x float>> [#uses=1]
+ %tmp84.i1413.i = load <4 x float>* %.sub6235.i ; <<4 x float>> [#uses=1]
+ %tmp89.i1415.i = fmul <4 x float> %tmp84.i1413.i, %tmp1406.i1367.i ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp89.i1415.i, <4 x float>* %.sub.i
+ ret i16 0
+}
+
+declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>)
diff --git a/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll b/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
new file mode 100644
index 0000000..4d69715
--- /dev/null
+++ b/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin8"
+
+define x86_fp80 @foo(x86_fp80 %x) nounwind{
+entry:
+ %tmp2 = call x86_fp80 @llvm.sqrt.f80( x86_fp80 %x )
+ ret x86_fp80 %tmp2
+
+; CHECK: foo:
+; CHECK: fldt 4(%esp)
+; CHECK-NEXT: fsqrt
+; CHECK-NEXT: ret
+}
+
+declare x86_fp80 @llvm.sqrt.f80(x86_fp80)
+
+define x86_fp80 @bar(x86_fp80 %x) nounwind {
+entry:
+ %tmp2 = call x86_fp80 @llvm.powi.f80( x86_fp80 %x, i32 3 )
+ ret x86_fp80 %tmp2
+; CHECK: bar:
+; CHECK: fldt 4(%esp)
+; CHECK-NEXT: fld %st(0)
+; CHECK-NEXT: fmul %st(1)
+; CHECK-NEXT: fmulp %st(1)
+; CHECK-NEXT: ret
+}
+
+declare x86_fp80 @llvm.powi.f80(x86_fp80, i32)
diff --git a/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll b/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll
new file mode 100644
index 0000000..6fc8ec9
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86 | not grep pushf
+
+ %struct.gl_texture_image = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8* }
+ %struct.gl_texture_object = type { i32, i32, i32, float, [4 x i32], i32, i32, i32, i32, i32, float, [11 x %struct.gl_texture_image*], [1024 x i8], i32, i32, i32, i8, i8*, i8, void (%struct.gl_texture_object*, i32, float*, float*, float*, float*, i8*, i8*, i8*, i8*)*, %struct.gl_texture_object* }
+
+define fastcc void @sample_3d_linear(%struct.gl_texture_object* %tObj, %struct.gl_texture_image* %img, float %s, float %t, float %r, i8* %red, i8* %green, i8* %blue, i8* %alpha) {
+entry:
+ %tmp15 = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp16 = icmp eq i32 %tmp15, 10497 ; <i1> [#uses=1]
+ %tmp2152 = call float @floorf( float 0.000000e+00 ) ; <float> [#uses=0]
+ br i1 %tmp16, label %cond_true, label %cond_false
+
+cond_true: ; preds = %entry
+ ret void
+
+cond_false: ; preds = %entry
+ ret void
+}
+
+declare float @floorf(float)
diff --git a/test/CodeGen/X86/2007-10-05-3AddrConvert.ll b/test/CodeGen/X86/2007-10-05-3AddrConvert.ll
new file mode 100644
index 0000000..67323e8
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-05-3AddrConvert.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s -march=x86 | grep lea
+
+ %struct.anon = type { [3 x double], double, %struct.node*, [64 x %struct.bnode*], [64 x %struct.bnode*] }
+ %struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, %struct.bnode*, %struct.bnode* }
+ %struct.node = type { i16, double, [3 x double], i32, i32 }
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
+entry:
+ %0 = malloc %struct.anon ; <%struct.anon*> [#uses=2]
+ %1 = getelementptr %struct.anon* %0, i32 0, i32 2 ; <%struct.node**> [#uses=1]
+ br label %bb14.i
+
+bb14.i: ; preds = %bb14.i, %entry
+ %i8.0.reg2mem.0.i = phi i32 [ 0, %entry ], [ %2, %bb14.i ] ; <i32> [#uses=1]
+ %2 = add i32 %i8.0.reg2mem.0.i, 1 ; <i32> [#uses=2]
+ %exitcond74.i = icmp eq i32 %2, 32 ; <i1> [#uses=1]
+ br i1 %exitcond74.i, label %bb32.i, label %bb14.i
+
+bb32.i: ; preds = %bb32.i, %bb14.i
+ %tmp.0.reg2mem.0.i = phi i32 [ %indvar.next63.i, %bb32.i ], [ 0, %bb14.i ] ; <i32> [#uses=1]
+ %indvar.next63.i = add i32 %tmp.0.reg2mem.0.i, 1 ; <i32> [#uses=2]
+ %exitcond64.i = icmp eq i32 %indvar.next63.i, 64 ; <i1> [#uses=1]
+ br i1 %exitcond64.i, label %bb47.loopexit.i, label %bb32.i
+
+bb.i.i: ; preds = %bb47.loopexit.i
+ unreachable
+
+stepsystem.exit.i: ; preds = %bb47.loopexit.i
+ store %struct.node* null, %struct.node** %1, align 4
+ br label %bb.i6.i
+
+bb.i6.i: ; preds = %bb.i6.i, %stepsystem.exit.i
+ %tmp.0.i.i = add i32 0, -1 ; <i32> [#uses=1]
+ %3 = icmp slt i32 %tmp.0.i.i, 0 ; <i1> [#uses=1]
+ br i1 %3, label %bb107.i.i, label %bb.i6.i
+
+bb107.i.i: ; preds = %bb107.i.i, %bb.i6.i
+ %q_addr.0.i.i.in = phi %struct.bnode** [ null, %bb107.i.i ], [ %4, %bb.i6.i ] ; <%struct.bnode**> [#uses=1]
+ %q_addr.0.i.i = load %struct.bnode** %q_addr.0.i.i.in ; <%struct.bnode*> [#uses=0]
+ br label %bb107.i.i
+
+bb47.loopexit.i: ; preds = %bb32.i
+ %4 = getelementptr %struct.anon* %0, i32 0, i32 4, i32 0 ; <%struct.bnode**> [#uses=1]
+ %5 = icmp eq %struct.node* null, null ; <i1> [#uses=1]
+ br i1 %5, label %stepsystem.exit.i, label %bb.i.i
+}
diff --git a/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll b/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
new file mode 100644
index 0000000..fc11347
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -march=x86 | not grep movb
+
+define i16 @f(i32* %bp, i32* %ss) signext {
+entry:
+ br label %cond_next127
+
+cond_next127: ; preds = %cond_next391, %entry
+ %v.1 = phi i32 [ undef, %entry ], [ %tmp411, %cond_next391 ] ; <i32> [#uses=1]
+ %tmp149 = mul i32 0, %v.1 ; <i32> [#uses=0]
+ %tmp254 = and i32 0, 15 ; <i32> [#uses=1]
+ %tmp256 = and i32 0, 15 ; <i32> [#uses=2]
+ br i1 false, label %cond_true267, label %cond_next391
+
+cond_true267: ; preds = %cond_next127
+ ret i16 0
+
+cond_next391: ; preds = %cond_next127
+ %tmp393 = load i32* %ss, align 4 ; <i32> [#uses=1]
+ %tmp395 = load i32* %bp, align 4 ; <i32> [#uses=2]
+ %tmp396 = shl i32 %tmp393, %tmp395 ; <i32> [#uses=2]
+ %tmp398 = sub i32 32, %tmp256 ; <i32> [#uses=2]
+ %tmp399 = lshr i32 %tmp396, %tmp398 ; <i32> [#uses=1]
+ %tmp405 = lshr i32 %tmp396, 31 ; <i32> [#uses=1]
+ %tmp406 = add i32 %tmp405, -1 ; <i32> [#uses=1]
+ %tmp409 = lshr i32 %tmp406, %tmp398 ; <i32> [#uses=1]
+ %tmp411 = sub i32 %tmp399, %tmp409 ; <i32> [#uses=1]
+ %tmp422445 = add i32 %tmp254, 0 ; <i32> [#uses=1]
+ %tmp426447 = add i32 %tmp395, %tmp256 ; <i32> [#uses=1]
+ store i32 %tmp426447, i32* %bp, align 4
+ %tmp429448 = icmp ult i32 %tmp422445, 63 ; <i1> [#uses=1]
+ br i1 %tmp429448, label %cond_next127, label %UnifiedReturnBlock
+
+UnifiedReturnBlock: ; preds = %cond_next391
+ ret i16 0
+}
diff --git a/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll b/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll
new file mode 100644
index 0000000..ea1bbc4
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll
@@ -0,0 +1,45 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep addss | not grep esp
+
+define fastcc void @fht(float* %fz, i16 signext %n) {
+entry:
+ br i1 true, label %bb171.preheader, label %bb431
+
+bb171.preheader: ; preds = %entry
+ %tmp176 = fadd float 0.000000e+00, 1.000000e+00 ; <float> [#uses=2]
+ %gi.1 = getelementptr float* %fz, i32 0 ; <float*> [#uses=2]
+ %tmp240 = load float* %gi.1, align 4 ; <float> [#uses=1]
+ %tmp242 = fsub float %tmp240, 0.000000e+00 ; <float> [#uses=2]
+ %tmp251 = getelementptr float* %fz, i32 0 ; <float*> [#uses=1]
+ %tmp252 = load float* %tmp251, align 4 ; <float> [#uses=1]
+ %tmp258 = getelementptr float* %fz, i32 0 ; <float*> [#uses=2]
+ %tmp259 = load float* %tmp258, align 4 ; <float> [#uses=2]
+ %tmp261 = fmul float %tmp259, %tmp176 ; <float> [#uses=1]
+ %tmp262 = fsub float 0.000000e+00, %tmp261 ; <float> [#uses=2]
+ %tmp269 = fmul float %tmp252, %tmp176 ; <float> [#uses=1]
+ %tmp276 = fmul float %tmp259, 0.000000e+00 ; <float> [#uses=1]
+ %tmp277 = fadd float %tmp269, %tmp276 ; <float> [#uses=2]
+ %tmp281 = getelementptr float* %fz, i32 0 ; <float*> [#uses=1]
+ %tmp282 = load float* %tmp281, align 4 ; <float> [#uses=2]
+ %tmp284 = fsub float %tmp282, %tmp277 ; <float> [#uses=1]
+ %tmp291 = fadd float %tmp282, %tmp277 ; <float> [#uses=1]
+ %tmp298 = fsub float 0.000000e+00, %tmp262 ; <float> [#uses=1]
+ %tmp305 = fadd float 0.000000e+00, %tmp262 ; <float> [#uses=1]
+ %tmp315 = fmul float 0.000000e+00, %tmp291 ; <float> [#uses=1]
+ %tmp318 = fmul float 0.000000e+00, %tmp298 ; <float> [#uses=1]
+ %tmp319 = fadd float %tmp315, %tmp318 ; <float> [#uses=1]
+ %tmp329 = fadd float 0.000000e+00, %tmp319 ; <float> [#uses=1]
+ store float %tmp329, float* null, align 4
+ %tmp336 = fsub float %tmp242, 0.000000e+00 ; <float> [#uses=1]
+ store float %tmp336, float* %tmp258, align 4
+ %tmp343 = fadd float %tmp242, 0.000000e+00 ; <float> [#uses=1]
+ store float %tmp343, float* null, align 4
+ %tmp355 = fmul float 0.000000e+00, %tmp305 ; <float> [#uses=1]
+ %tmp358 = fmul float 0.000000e+00, %tmp284 ; <float> [#uses=1]
+ %tmp359 = fadd float %tmp355, %tmp358 ; <float> [#uses=1]
+ %tmp369 = fadd float 0.000000e+00, %tmp359 ; <float> [#uses=1]
+ store float %tmp369, float* %gi.1, align 4
+ ret void
+
+bb431: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll b/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
new file mode 100644
index 0000000..a3872ad
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll
@@ -0,0 +1,57 @@
+; RUN: llc < %s -march=x86 | grep sarl | not grep esp
+
+define i16 @t(i16* %qmatrix, i16* %dct, i16* %acBaseTable, i16* %acExtTable, i16 signext %acBaseRes, i16 signext %acMaskRes, i16 signext %acExtRes, i32* %bitptr, i32* %source, i32 %markerPrefix, i8** %byteptr, i32 %scale, i32 %round, i32 %bits) signext {
+entry:
+ br label %cond_next127
+
+cond_next127: ; preds = %cond_next391, %entry
+ %tmp151 = add i32 0, %round ; <i32> [#uses=1]
+ %tmp153 = ashr i32 %tmp151, %scale ; <i32> [#uses=1]
+ %tmp158 = xor i32 0, %tmp153 ; <i32> [#uses=1]
+ %tmp160 = or i32 %tmp158, 0 ; <i32> [#uses=1]
+ %tmp180181 = sext i16 0 to i32 ; <i32> [#uses=1]
+ %tmp183 = add i32 %tmp160, 1 ; <i32> [#uses=1]
+ br i1 false, label %cond_true188, label %cond_next245
+
+cond_true188: ; preds = %cond_next127
+ ret i16 0
+
+cond_next245: ; preds = %cond_next127
+ %tmp253444 = lshr i32 %tmp180181, 4 ; <i32> [#uses=1]
+ %tmp254 = and i32 %tmp253444, 15 ; <i32> [#uses=1]
+ br i1 false, label %cond_true267, label %cond_next391
+
+cond_true267: ; preds = %cond_next245
+ %tmp269 = load i8** %byteptr, align 4 ; <i8*> [#uses=3]
+ %tmp270 = load i8* %tmp269, align 1 ; <i8> [#uses=1]
+ %tmp270271 = zext i8 %tmp270 to i32 ; <i32> [#uses=1]
+ %tmp272 = getelementptr i8* %tmp269, i32 1 ; <i8*> [#uses=2]
+ store i8* %tmp272, i8** %byteptr, align 4
+ %tmp276 = load i8* %tmp272, align 1 ; <i8> [#uses=1]
+ %tmp278 = getelementptr i8* %tmp269, i32 2 ; <i8*> [#uses=1]
+ store i8* %tmp278, i8** %byteptr, align 4
+ %tmp286 = icmp eq i32 %tmp270271, %markerPrefix ; <i1> [#uses=1]
+ %cond = icmp eq i8 %tmp276, 0 ; <i1> [#uses=1]
+ %bothcond = and i1 %tmp286, %cond ; <i1> [#uses=1]
+ br i1 %bothcond, label %cond_true294, label %cond_next327
+
+cond_true294: ; preds = %cond_true267
+ ret i16 0
+
+cond_next327: ; preds = %cond_true267
+ br i1 false, label %cond_true343, label %cond_next391
+
+cond_true343: ; preds = %cond_next327
+ %tmp345 = load i8** %byteptr, align 4 ; <i8*> [#uses=1]
+ store i8* null, i8** %byteptr, align 4
+ store i8* %tmp345, i8** %byteptr, align 4
+ br label %cond_next391
+
+cond_next391: ; preds = %cond_true343, %cond_next327, %cond_next245
+ %tmp422445 = add i32 %tmp254, %tmp183 ; <i32> [#uses=1]
+ %tmp429448 = icmp ult i32 %tmp422445, 63 ; <i1> [#uses=1]
+ br i1 %tmp429448, label %cond_next127, label %UnifiedReturnBlock
+
+UnifiedReturnBlock: ; preds = %cond_next391
+ ret i16 0
+}
diff --git a/test/CodeGen/X86/2007-10-14-CoalescerCrash.ll b/test/CodeGen/X86/2007-10-14-CoalescerCrash.ll
new file mode 100644
index 0000000..8a55935
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-14-CoalescerCrash.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin
+
+ %struct._Unwind_Context = type { }
+
+define i32 @execute_stack_op(i8* %op_ptr, i8* %op_end, %struct._Unwind_Context* %context, i64 %initial) {
+entry:
+ br i1 false, label %bb, label %return
+
+bb: ; preds = %bb31, %entry
+ br i1 false, label %bb6, label %bb31
+
+bb6: ; preds = %bb
+ %tmp10 = load i64* null, align 8 ; <i64> [#uses=1]
+ %tmp16 = load i64* null, align 8 ; <i64> [#uses=1]
+ br i1 false, label %bb23, label %bb31
+
+bb23: ; preds = %bb6
+ %tmp2526.cast = and i64 %tmp16, 4294967295 ; <i64> [#uses=1]
+ %tmp27 = ashr i64 %tmp10, %tmp2526.cast ; <i64> [#uses=1]
+ br label %bb31
+
+bb31: ; preds = %bb23, %bb6, %bb
+ %result.0 = phi i64 [ %tmp27, %bb23 ], [ 0, %bb ], [ 0, %bb6 ] ; <i64> [#uses=0]
+ br i1 false, label %bb, label %return
+
+return: ; preds = %bb31, %entry
+ ret i32 undef
+}
diff --git a/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll b/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll
new file mode 100644
index 0000000..1e4ae84
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll
@@ -0,0 +1,400 @@
+; RUN: llc < %s -mtriple=x86_64-linux-gnu
+; PR1729
+
+ %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.VEC_edge = type { i32, i32, [1 x %struct.edge_def*] }
+ %struct.VEC_tree = type { i32, i32, [1 x %struct.tree_node*] }
+ %struct._IO_FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct._IO_FILE*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i64, i32, [20 x i8] }
+ %struct._IO_marker = type { %struct._IO_marker*, %struct._IO_FILE*, i32 }
+ %struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
+ %struct.addr_diff_vec_flags = type <{ i8, i8, i8, i8 }>
+ %struct.alloc_pool_def = type { i8*, i64, i64, %struct.alloc_pool_list_def*, i64, i64, i64, %struct.alloc_pool_list_def*, i64, i64 }
+ %struct.alloc_pool_list_def = type { %struct.alloc_pool_list_def* }
+ %struct.basic_block_def = type { %struct.rtx_def*, %struct.rtx_def*, %struct.tree_node*, %struct.VEC_edge*, %struct.VEC_edge*, %struct.bitmap_head_def*, %struct.bitmap_head_def*, i8*, %struct.loop*, [2 x %struct.et_node*], %struct.basic_block_def*, %struct.basic_block_def*, %struct.reorder_block_def*, %struct.bb_ann_d*, i64, i32, i32, i32, i32 }
+ %struct.bb_ann_d = type opaque
+ %struct.bitmap_element_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, [2 x i64] }
+ %struct.bitmap_head_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, %struct.bitmap_obstack* }
+ %struct.bitmap_obstack = type { %struct.bitmap_element_def*, %struct.bitmap_head_def*, %struct.obstack }
+ %struct.cselib_val_struct = type opaque
+ %struct.dataflow_d = type opaque
+ %struct.die_struct = type opaque
+ %struct.edge_def = type { %struct.basic_block_def*, %struct.basic_block_def*, %struct.edge_def_insns, i8*, %struct.location_t*, i32, i32, i64, i32 }
+ %struct.edge_def_insns = type { %struct.rtx_def* }
+ %struct.edge_iterator = type { i32, %struct.VEC_edge** }
+ %struct.eh_status = type opaque
+ %struct.elt_list = type opaque
+ %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }
+ %struct.et_node = type opaque
+ %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+ %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, %struct.tree_node*, i8, i8, i8 }
+ %struct.ht_identifier = type { i8*, i32, i32 }
+ %struct.initial_value_struct = type opaque
+ %struct.lang_decl = type opaque
+ %struct.lang_type = type opaque
+ %struct.language_function = type opaque
+ %struct.location_t = type { i8*, i32 }
+ %struct.loop = type opaque
+ %struct.machine_function = type { %struct.stack_local_entry*, i8*, %struct.rtx_def*, i32, i32, i32, i32, i32 }
+ %struct.mem_attrs = type { i64, %struct.tree_node*, %struct.rtx_def*, %struct.rtx_def*, i32 }
+ %struct.obstack = type { i64, %struct._obstack_chunk*, i8*, i8*, i8*, i64, i32, %struct._obstack_chunk* (i8*, i64)*, void (i8*, %struct._obstack_chunk*)*, i8*, i8 }
+ %struct.phi_arg_d = type { %struct.tree_node*, i8 }
+ %struct.ptr_info_def = type opaque
+ %struct.real_value = type opaque
+ %struct.reg_attrs = type { %struct.tree_node*, i64 }
+ %struct.reg_info_def = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.reorder_block_def = type { %struct.rtx_def*, %struct.rtx_def*, %struct.basic_block_def*, %struct.basic_block_def*, %struct.basic_block_def*, i32, i32, i32 }
+ %struct.rtunion = type { i8* }
+ %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }
+ %struct.rtx_def = type { i16, i8, i8, %struct.u }
+ %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
+ %struct.simple_bitmap_def = type { i32, i32, i32, [1 x i64] }
+ %struct.stack_local_entry = type opaque
+ %struct.temp_slot = type opaque
+ %struct.tree_binfo = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.VEC_tree*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.VEC_tree }
+ %struct.tree_block = type { %struct.tree_common, i32, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node* }
+ %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 }
+ %struct.tree_complex = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node* }
+ %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_decl_u1 = type { i64 }
+ %struct.tree_decl_u1_a = type <{ i32 }>
+ %struct.tree_decl_u2 = type { %struct.function* }
+ %struct.tree_exp = type { %struct.tree_common, %struct.location_t*, i32, %struct.tree_node*, [1 x %struct.tree_node*] }
+ %struct.tree_identifier = type { %struct.tree_common, %struct.ht_identifier }
+ %struct.tree_int_cst = type { %struct.tree_common, %struct.tree_int_cst_lowhi }
+ %struct.tree_int_cst_lowhi = type { i64, i64 }
+ %struct.tree_list = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node* }
+ %struct.tree_node = type { %struct.tree_decl }
+ %struct.tree_phi_node = type { %struct.tree_common, %struct.tree_node*, i32, i32, i32, %struct.basic_block_def*, %struct.dataflow_d*, [1 x %struct.phi_arg_d] }
+ %struct.tree_real_cst = type { %struct.tree_common, %struct.real_value* }
+ %struct.tree_ssa_name = type { %struct.tree_common, %struct.tree_node*, i32, %struct.ptr_info_def*, %struct.tree_node*, i8* }
+ %struct.tree_statement_list = type { %struct.tree_common, %struct.tree_statement_list_node*, %struct.tree_statement_list_node* }
+ %struct.tree_statement_list_node = type { %struct.tree_statement_list_node*, %struct.tree_statement_list_node*, %struct.tree_node* }
+ %struct.tree_string = type { %struct.tree_common, i32, [1 x i8] }
+ %struct.tree_type = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i32, i16, i8, i8, i32, %struct.tree_node*, %struct.tree_node*, %struct.rtunion, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_type* }
+ %struct.tree_type_symtab = type { i8* }
+ %struct.tree_value_handle = type { %struct.tree_common, %struct.value_set*, i32 }
+ %struct.tree_vec = type { %struct.tree_common, i32, [1 x %struct.tree_node*] }
+ %struct.tree_vector = type { %struct.tree_common, %struct.tree_node* }
+ %struct.u = type { [1 x %struct.rtunion] }
+ %struct.value_set = type opaque
+ %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+ %struct.varasm_status = type opaque
+ %struct.varray_data = type { [1 x i64] }
+ %struct.varray_head_tag = type { i64, i64, i32, i8*, %struct.varray_data }
+ %union.tree_ann_d = type opaque
+@first_edge_aux_obj = external global i8* ; <i8**> [#uses=0]
+@first_block_aux_obj = external global i8* ; <i8**> [#uses=0]
+@n_edges = external global i32 ; <i32*> [#uses=0]
+@ENTRY_BLOCK_PTR = external global %struct.basic_block_def* ; <%struct.basic_block_def**> [#uses=0]
+@EXIT_BLOCK_PTR = external global %struct.basic_block_def* ; <%struct.basic_block_def**> [#uses=0]
+@n_basic_blocks = external global i32 ; <i32*> [#uses=0]
[email protected] = external constant [9 x i8] ; <[9 x i8]*> [#uses=0]
+@rbi_pool = external global %struct.alloc_pool_def* ; <%struct.alloc_pool_def**> [#uses=0]
+@__FUNCTION__.19643 = external constant [18 x i8] ; <[18 x i8]*> [#uses=0]
[email protected] = external constant [20 x i8] ; <[20 x i8]*> [#uses=0]
+@__FUNCTION__.19670 = external constant [15 x i8] ; <[15 x i8]*> [#uses=0]
+@basic_block_info = external global %struct.varray_head_tag* ; <%struct.varray_head_tag**> [#uses=0]
+@last_basic_block = external global i32 ; <i32*> [#uses=0]
+@__FUNCTION__.19696 = external constant [14 x i8] ; <[14 x i8]*> [#uses=0]
+@__FUNCTION__.20191 = external constant [20 x i8] ; <[20 x i8]*> [#uses=0]
+@block_aux_obstack = external global %struct.obstack ; <%struct.obstack*> [#uses=0]
+@__FUNCTION__.20301 = external constant [20 x i8] ; <[20 x i8]*> [#uses=0]
+@__FUNCTION__.20316 = external constant [19 x i8] ; <[19 x i8]*> [#uses=0]
+@edge_aux_obstack = external global %struct.obstack ; <%struct.obstack*> [#uses=0]
+@stderr = external global %struct._IO_FILE* ; <%struct._IO_FILE**> [#uses=0]
+@__FUNCTION__.20463 = external constant [11 x i8] ; <[11 x i8]*> [#uses=0]
[email protected] = external constant [7 x i8] ; <[7 x i8]*> [#uses=0]
[email protected] = external constant [6 x i8] ; <[6 x i8]*> [#uses=0]
[email protected] = external constant [4 x i8] ; <[4 x i8]*> [#uses=0]
[email protected] = external constant [11 x i8] ; <[11 x i8]*> [#uses=0]
[email protected] = external constant [8 x i8] ; <[8 x i8]*> [#uses=0]
[email protected] = external constant [4 x i8] ; <[4 x i8]*> [#uses=0]
[email protected] = external constant [13 x i8*] ; <[13 x i8*]*> [#uses=0]
[email protected] = external constant [9 x i8] ; <[9 x i8]*> [#uses=0]
[email protected] = external constant [3 x i8] ; <[3 x i8]*> [#uses=0]
[email protected] = external constant [7 x i8] ; <[7 x i8]*> [#uses=0]
[email protected] = external constant [3 x i8] ; <[3 x i8]*> [#uses=0]
[email protected] = external constant [5 x i8] ; <[5 x i8]*> [#uses=0]
[email protected] = external constant [9 x i8] ; <[9 x i8]*> [#uses=0]
[email protected] = external constant [13 x i8] ; <[13 x i8]*> [#uses=0]
[email protected] = external constant [12 x i8] ; <[12 x i8]*> [#uses=0]
[email protected] = external constant [8 x i8] ; <[8 x i8]*> [#uses=0]
[email protected] = external constant [10 x i8] ; <[10 x i8]*> [#uses=0]
[email protected] = external constant [5 x i8] ; <[5 x i8]*> [#uses=0]
[email protected] = external constant [6 x i8] ; <[6 x i8]*> [#uses=0]
[email protected] = external constant [5 x i8] ; <[5 x i8]*> [#uses=0]
[email protected] = external constant [3 x i8] ; <[3 x i8]*> [#uses=0]
[email protected] = external constant [3 x i8] ; <[3 x i8]*> [#uses=0]
+@__FUNCTION__.19709 = external constant [20 x i8] ; <[20 x i8]*> [#uses=0]
[email protected] = external constant [5 x i8] ; <[5 x i8]*> [#uses=0]
[email protected] = external constant [10 x i8] ; <[10 x i8]*> [#uses=0]
+@__FUNCTION__.19813 = external constant [19 x i8] ; <[19 x i8]*> [#uses=0]
[email protected] = external constant [7 x i8] ; <[7 x i8]*> [#uses=0]
[email protected] = external constant [6 x i8] ; <[6 x i8]*> [#uses=0]
[email protected] = external global i1 ; <i1*> [#uses=0]
+@__FUNCTION__.20244 = external constant [21 x i8] ; <[21 x i8]*> [#uses=0]
+@__FUNCTION__.19601 = external constant [12 x i8] ; <[12 x i8]*> [#uses=0]
+@__FUNCTION__.14571 = external constant [8 x i8] ; <[8 x i8]*> [#uses=0]
+@__FUNCTION__.14535 = external constant [13 x i8] ; <[13 x i8]*> [#uses=0]
[email protected] = external constant [28 x i8] ; <[28 x i8]*> [#uses=0]
+@__FUNCTION__.14589 = external constant [8 x i8] ; <[8 x i8]*> [#uses=0]
+@__FUNCTION__.19792 = external constant [12 x i8] ; <[12 x i8]*> [#uses=0]
+@__FUNCTION__.19851 = external constant [19 x i8] ; <[19 x i8]*> [#uses=0]
+@profile_status = external global i32 ; <i32*> [#uses=0]
[email protected] = external constant [46 x i8] ; <[46 x i8]*> [#uses=0]
[email protected] = external constant [49 x i8] ; <[49 x i8]*> [#uses=0]
[email protected] = external constant [54 x i8] ; <[54 x i8]*> [#uses=0]
[email protected] = external constant [49 x i8] ; <[49 x i8]*> [#uses=1]
+@__FUNCTION__.19948 = external constant [15 x i8] ; <[15 x i8]*> [#uses=0]
+@reg_n_info = external global %struct.varray_head_tag* ; <%struct.varray_head_tag**> [#uses=0]
+@reload_completed = external global i32 ; <i32*> [#uses=0]
[email protected] = external constant [15 x i8] ; <[15 x i8]*> [#uses=0]
[email protected] = external constant [43 x i8] ; <[43 x i8]*> [#uses=0]
[email protected] = external constant [13 x i8] ; <[13 x i8]*> [#uses=0]
[email protected] = external constant [1 x i8] ; <[1 x i8]*> [#uses=0]
[email protected] = external constant [2 x i8] ; <[2 x i8]*> [#uses=0]
[email protected] = external constant [16 x i8] ; <[16 x i8]*> [#uses=0]
+@cfun = external global %struct.function* ; <%struct.function**> [#uses=0]
[email protected] = external constant [14 x i8] ; <[14 x i8]*> [#uses=0]
[email protected] = external constant [11 x i8] ; <[11 x i8]*> [#uses=0]
[email protected] = external constant [20 x i8] ; <[20 x i8]*> [#uses=0]
[email protected] = external constant [17 x i8] ; <[17 x i8]*> [#uses=0]
[email protected] = external constant [19 x i8] ; <[19 x i8]*> [#uses=0]
+@mode_size = external global [48 x i8] ; <[48 x i8]*> [#uses=0]
+@target_flags = external global i32 ; <i32*> [#uses=0]
[email protected] = external constant [11 x i8] ; <[11 x i8]*> [#uses=0]
+@reg_class_names = external global [0 x i8*] ; <[0 x i8*]*> [#uses=0]
[email protected] = external constant [10 x i8] ; <[10 x i8]*> [#uses=0]
[email protected] = external constant [13 x i8] ; <[13 x i8]*> [#uses=0]
[email protected] = external constant [19 x i8] ; <[19 x i8]*> [#uses=0]
[email protected] = external constant [12 x i8] ; <[12 x i8]*> [#uses=0]
[email protected] = external constant [10 x i8] ; <[10 x i8]*> [#uses=0]
[email protected] = external constant [3 x i8] ; <[3 x i8]*> [#uses=0]
[email protected] = external constant [29 x i8] ; <[29 x i8]*> [#uses=0]
[email protected] = external constant [17 x i8] ; <[17 x i8]*> [#uses=0]
[email protected] = external constant [19 x i8] ; <[19 x i8]*> [#uses=0]
[email protected] = external constant [22 x i8] ; <[22 x i8]*> [#uses=0]
[email protected] = external constant [10 x i8] ; <[10 x i8]*> [#uses=0]
[email protected] = external constant [12 x i8] ; <[12 x i8]*> [#uses=0]
[email protected] = external constant [26 x i8] ; <[26 x i8]*> [#uses=0]
[email protected] = external constant [15 x i8] ; <[15 x i8]*> [#uses=0]
[email protected] = external constant [14 x i8] ; <[14 x i8]*> [#uses=0]
[email protected] = external constant [26 x i8] ; <[26 x i8]*> [#uses=0]
[email protected] = external constant [24 x i8] ; <[24 x i8]*> [#uses=0]
[email protected] = external global i1 ; <i1*> [#uses=0]
+@__FUNCTION__.20369 = external constant [20 x i8] ; <[20 x i8]*> [#uses=0]
+@__FUNCTION__.20442 = external constant [19 x i8] ; <[19 x i8]*> [#uses=0]
+@bb_bitnames.20476 = external constant [6 x i8*] ; <[6 x i8*]*> [#uses=0]
[email protected] = external constant [6 x i8] ; <[6 x i8]*> [#uses=0]
[email protected] = external constant [4 x i8] ; <[4 x i8]*> [#uses=0]
[email protected] = external constant [10 x i8] ; <[10 x i8]*> [#uses=0]
[email protected] = external constant [8 x i8] ; <[8 x i8]*> [#uses=0]
[email protected] = external constant [17 x i8] ; <[17 x i8]*> [#uses=0]
[email protected] = external constant [11 x i8] ; <[11 x i8]*> [#uses=0]
[email protected] = external constant [15 x i8] ; <[15 x i8]*> [#uses=0]
[email protected] = external constant [3 x i8] ; <[3 x i8]*> [#uses=0]
[email protected] = external constant [3 x i8] ; <[3 x i8]*> [#uses=0]
+@__FUNCTION__.20520 = external constant [32 x i8] ; <[32 x i8]*> [#uses=0]
+@dump_file = external global %struct._IO_FILE* ; <%struct._IO_FILE**> [#uses=0]
[email protected] = external constant [86 x i8] ; <[86 x i8]*> [#uses=0]
[email protected] = external constant [94 x i8] ; <[94 x i8]*> [#uses=0]
+@reg_obstack = external global %struct.bitmap_obstack ; <%struct.bitmap_obstack*> [#uses=0]
+
+declare void @init_flow()
+
+declare i8* @ggc_alloc_cleared_stat(i64)
+
+declare fastcc void @free_edge(%struct.edge_def*)
+
+declare void @ggc_free(i8*)
+
+declare %struct.basic_block_def* @alloc_block()
+
+declare void @alloc_rbi_pool()
+
+declare %struct.alloc_pool_def* @create_alloc_pool(i8*, i64, i64)
+
+declare void @free_rbi_pool()
+
+declare void @free_alloc_pool(%struct.alloc_pool_def*)
+
+declare void @initialize_bb_rbi(%struct.basic_block_def*)
+
+declare void @fancy_abort(i8*, i32, i8*)
+
+declare i8* @pool_alloc(%struct.alloc_pool_def*)
+
+declare void @llvm.memset.i64(i8*, i8, i64, i32)
+
+declare void @link_block(%struct.basic_block_def*, %struct.basic_block_def*)
+
+declare void @unlink_block(%struct.basic_block_def*)
+
+declare void @compact_blocks()
+
+declare void @varray_check_failed(%struct.varray_head_tag*, i64, i8*, i32, i8*)
+
+declare void @expunge_block(%struct.basic_block_def*)
+
+declare void @clear_bb_flags()
+
+declare void @alloc_aux_for_block(%struct.basic_block_def*, i32)
+
+declare void @_obstack_newchunk(%struct.obstack*, i32)
+
+declare void @clear_aux_for_blocks()
+
+declare void @free_aux_for_blocks()
+
+declare void @obstack_free(%struct.obstack*, i8*)
+
+declare void @alloc_aux_for_edge(%struct.edge_def*, i32)
+
+declare void @debug_bb(%struct.basic_block_def*)
+
+declare void @dump_bb(%struct.basic_block_def*, %struct._IO_FILE*, i32)
+
+declare %struct.basic_block_def* @debug_bb_n(i32)
+
+declare void @dump_edge_info(%struct._IO_FILE*, %struct.edge_def*, i32)
+
+declare i32 @fputs_unlocked(i8* noalias , %struct._IO_FILE* noalias )
+
+declare i32 @fprintf(%struct._IO_FILE* noalias , i8* noalias , ...)
+
+declare i64 @fwrite(i8*, i64, i64, i8*)
+
+declare i32 @__overflow(%struct._IO_FILE*, i32)
+
+declare %struct.edge_def* @unchecked_make_edge(%struct.basic_block_def*, %struct.basic_block_def*, i32)
+
+declare i8* @vec_gc_p_reserve(i8*, i32)
+
+declare void @vec_assert_fail(i8*, i8*, i8*, i32, i8*)
+
+declare void @execute_on_growing_pred(%struct.edge_def*)
+
+declare %struct.edge_def* @make_edge(%struct.basic_block_def*, %struct.basic_block_def*, i32)
+
+declare %struct.edge_def* @find_edge(%struct.basic_block_def*, %struct.basic_block_def*)
+
+declare %struct.edge_def* @make_single_succ_edge(%struct.basic_block_def*, %struct.basic_block_def*, i32)
+
+declare %struct.edge_def* @cached_make_edge(%struct.simple_bitmap_def**, %struct.basic_block_def*, %struct.basic_block_def*, i32)
+
+declare void @redirect_edge_succ(%struct.edge_def*, %struct.basic_block_def*)
+
+declare void @execute_on_shrinking_pred(%struct.edge_def*)
+
+declare void @alloc_aux_for_blocks(i32)
+
+declare i8* @xmalloc(i64)
+
+declare i32 @_obstack_begin(%struct.obstack*, i32, i32, i8* (i64)*, void (i8*)*)
+
+declare void @free(i8*)
+
+declare void @clear_edges()
+
+declare void @remove_edge(%struct.edge_def*)
+
+declare %struct.edge_def* @redirect_edge_succ_nodup(%struct.edge_def*, %struct.basic_block_def*)
+
+declare void @redirect_edge_pred(%struct.edge_def*, %struct.basic_block_def*)
+
+define void @check_bb_profile(%struct.basic_block_def* %bb, %struct._IO_FILE* %file) {
+entry:
+ br i1 false, label %cond_false759.preheader, label %cond_false149.preheader
+
+cond_false149.preheader: ; preds = %entry
+ ret void
+
+cond_false759.preheader: ; preds = %entry
+ br i1 false, label %cond_next873, label %cond_true794
+
+bb644: ; preds = %cond_next873
+ ret void
+
+cond_true794: ; preds = %cond_false759.preheader
+ ret void
+
+cond_next873: ; preds = %cond_false759.preheader
+ br i1 false, label %bb882, label %bb644
+
+bb882: ; preds = %cond_next873
+ br i1 false, label %cond_true893, label %cond_next901
+
+cond_true893: ; preds = %bb882
+ br label %cond_false1036
+
+cond_next901: ; preds = %bb882
+ ret void
+
+bb929: ; preds = %cond_next1150
+ %tmp934 = add i64 0, %lsum.11225.0 ; <i64> [#uses=1]
+ br i1 false, label %cond_next979, label %cond_true974
+
+cond_true974: ; preds = %bb929
+ ret void
+
+cond_next979: ; preds = %bb929
+ br label %cond_false1036
+
+cond_false1036: ; preds = %cond_next979, %cond_true893
+ %lsum.11225.0 = phi i64 [ 0, %cond_true893 ], [ %tmp934, %cond_next979 ] ; <i64> [#uses=2]
+ br i1 false, label %cond_next1056, label %cond_true1051
+
+cond_true1051: ; preds = %cond_false1036
+ ret void
+
+cond_next1056: ; preds = %cond_false1036
+ br i1 false, label %cond_next1150, label %cond_true1071
+
+cond_true1071: ; preds = %cond_next1056
+ ret void
+
+cond_next1150: ; preds = %cond_next1056
+ %tmp1156 = icmp eq %struct.edge_def* null, null ; <i1> [#uses=1]
+ br i1 %tmp1156, label %bb1159, label %bb929
+
+bb1159: ; preds = %cond_next1150
+ br i1 false, label %cond_true1169, label %UnifiedReturnBlock
+
+cond_true1169: ; preds = %bb1159
+ %tmp11741175 = trunc i64 %lsum.11225.0 to i32 ; <i32> [#uses=1]
+ %tmp1178 = tail call i32 (%struct._IO_FILE* noalias , i8* noalias , ...)* @fprintf( %struct._IO_FILE* %file noalias , i8* getelementptr ([49 x i8]* @.str32, i32 0, i64 0) noalias , i32 %tmp11741175, i32 0 ) ; <i32> [#uses=0]
+ ret void
+
+UnifiedReturnBlock: ; preds = %bb1159
+ ret void
+}
+
+declare void @dump_flow_info(%struct._IO_FILE*)
+
+declare i32 @max_reg_num()
+
+declare void @rtl_check_failed_flag(i8*, %struct.rtx_def*, i8*, i32, i8*)
+
+declare i32 @reg_preferred_class(i32)
+
+declare i32 @reg_alternate_class(i32)
+
+declare i8 @maybe_hot_bb_p(%struct.basic_block_def*) zeroext
+
+declare i8 @probably_never_executed_bb_p(%struct.basic_block_def*) zeroext
+
+declare void @dump_regset(%struct.bitmap_head_def*, %struct._IO_FILE*)
+
+declare void @debug_flow_info()
+
+declare void @alloc_aux_for_edges(i32)
+
+declare void @clear_aux_for_edges()
+
+declare void @free_aux_for_edges()
+
+declare void @brief_dump_cfg(%struct._IO_FILE*)
+
+declare i32 @fputc(i32, i8*)
+
+declare void @update_bb_profile_for_threading(%struct.basic_block_def*, i32, i64, %struct.edge_def*)
diff --git a/test/CodeGen/X86/2007-10-16-CoalescerCrash.ll b/test/CodeGen/X86/2007-10-16-CoalescerCrash.ll
new file mode 100644
index 0000000..fbcac50
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-16-CoalescerCrash.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin
+
+define i64 @__ashldi3(i64 %u, i64 %b) {
+entry:
+ br i1 false, label %UnifiedReturnBlock, label %cond_next
+
+cond_next: ; preds = %entry
+ %tmp9 = sub i64 32, %b ; <i64> [#uses=2]
+ %tmp11 = icmp slt i64 %tmp9, 1 ; <i1> [#uses=1]
+ %tmp2180 = trunc i64 %u to i32 ; <i32> [#uses=2]
+ %tmp2223 = trunc i64 %tmp9 to i32 ; <i32> [#uses=2]
+ br i1 %tmp11, label %cond_true14, label %cond_false
+
+cond_true14: ; preds = %cond_next
+ %tmp24 = sub i32 0, %tmp2223 ; <i32> [#uses=1]
+ %tmp25 = shl i32 %tmp2180, %tmp24 ; <i32> [#uses=1]
+ %tmp2569 = zext i32 %tmp25 to i64 ; <i64> [#uses=1]
+ %tmp256970 = shl i64 %tmp2569, 32 ; <i64> [#uses=1]
+ ret i64 %tmp256970
+
+cond_false: ; preds = %cond_next
+ %tmp35 = lshr i32 %tmp2180, %tmp2223 ; <i32> [#uses=1]
+ %tmp54 = or i32 %tmp35, 0 ; <i32> [#uses=1]
+ %tmp5464 = zext i32 %tmp54 to i64 ; <i64> [#uses=1]
+ %tmp546465 = shl i64 %tmp5464, 32 ; <i64> [#uses=1]
+ %tmp546465.ins = or i64 %tmp546465, 0 ; <i64> [#uses=1]
+ ret i64 %tmp546465.ins
+
+UnifiedReturnBlock:
+ ret i64 %u
+}
diff --git a/test/CodeGen/X86/2007-10-16-IllegalAsm.ll b/test/CodeGen/X86/2007-10-16-IllegalAsm.ll
new file mode 100644
index 0000000..6d0cb47
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-16-IllegalAsm.ll
@@ -0,0 +1,272 @@
+; RUN: llc < %s -mtriple=x86_64-linux-gnu | grep movb | not grep x
+; PR1734
+
+ %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.eh_status = type opaque
+ %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }
+ %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+ %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, %struct.tree_node*, i8, i8, i8 }
+ %struct.initial_value_struct = type opaque
+ %struct.lang_decl = type opaque
+ %struct.lang_type = type opaque
+ %struct.language_function = type opaque
+ %struct.location_t = type { i8*, i32 }
+ %struct.machine_function = type { %struct.stack_local_entry*, i8*, %struct.rtx_def*, i32, i32, i32, i32, i32 }
+ %struct.rtunion = type { i8* }
+ %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }
+ %struct.rtx_def = type { i16, i8, i8, %struct.u }
+ %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
+ %struct.stack_local_entry = type opaque
+ %struct.temp_slot = type opaque
+ %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 }
+ %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_decl_u1 = type { i64 }
+ %struct.tree_decl_u2 = type { %struct.function* }
+ %struct.tree_node = type { %struct.tree_decl }
+ %struct.tree_type = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i32, i16, i8, i8, i32, %struct.tree_node*, %struct.tree_node*, %struct.rtunion, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_type* }
+ %struct.u = type { [1 x %struct.rtunion] }
+ %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+ %struct.varasm_status = type opaque
+ %struct.varray_data = type { [1 x i64] }
+ %struct.varray_head_tag = type { i64, i64, i32, i8*, %struct.varray_data }
+ %union.tree_ann_d = type opaque
[email protected] = external constant [28 x i8] ; <[28 x i8]*> [#uses=1]
+@tree_code_type = external constant [0 x i32] ; <[0 x i32]*> [#uses=5]
+@global_trees = external global [47 x %struct.tree_node*] ; <[47 x %struct.tree_node*]*> [#uses=1]
+@mode_size = external global [48 x i8] ; <[48 x i8]*> [#uses=1]
+@__FUNCTION__.22683 = external constant [12 x i8] ; <[12 x i8]*> [#uses=1]
+
+define void @layout_type(%struct.tree_node* %type) {
+entry:
+ %tmp15 = icmp eq %struct.tree_node* %type, null ; <i1> [#uses=1]
+ br i1 %tmp15, label %cond_true, label %cond_false
+
+cond_true: ; preds = %entry
+ tail call void @fancy_abort( i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1713, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
+ unreachable
+
+cond_false: ; preds = %entry
+ %tmp19 = load %struct.tree_node** getelementptr ([47 x %struct.tree_node*]* @global_trees, i32 0, i64 0), align 8 ; <%struct.tree_node*> [#uses=1]
+ %tmp21 = icmp eq %struct.tree_node* %tmp19, %type ; <i1> [#uses=1]
+ br i1 %tmp21, label %UnifiedReturnBlock, label %cond_next25
+
+cond_next25: ; preds = %cond_false
+ %tmp30 = getelementptr %struct.tree_node* %type, i32 0, i32 0, i32 0, i32 3 ; <i8*> [#uses=1]
+ %tmp3031 = bitcast i8* %tmp30 to i32* ; <i32*> [#uses=6]
+ %tmp32 = load i32* %tmp3031, align 8 ; <i32> [#uses=3]
+ %tmp3435 = trunc i32 %tmp32 to i8 ; <i8> [#uses=3]
+ %tmp34353637 = zext i8 %tmp3435 to i64 ; <i64> [#uses=1]
+ %tmp38 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp34353637 ; <i32*> [#uses=1]
+ %tmp39 = load i32* %tmp38, align 4 ; <i32> [#uses=1]
+ %tmp40 = icmp eq i32 %tmp39, 2 ; <i1> [#uses=4]
+ br i1 %tmp40, label %cond_next46, label %cond_true43
+
+cond_true43: ; preds = %cond_next25
+ tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1719, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
+ unreachable
+
+cond_next46: ; preds = %cond_next25
+ %tmp4950 = bitcast %struct.tree_node* %type to %struct.tree_type* ; <%struct.tree_type*> [#uses=2]
+ %tmp51 = getelementptr %struct.tree_type* %tmp4950, i32 0, i32 2 ; <%struct.tree_node**> [#uses=2]
+ %tmp52 = load %struct.tree_node** %tmp51, align 8 ; <%struct.tree_node*> [#uses=1]
+ %tmp53 = icmp eq %struct.tree_node* %tmp52, null ; <i1> [#uses=1]
+ br i1 %tmp53, label %cond_next57, label %UnifiedReturnBlock
+
+cond_next57: ; preds = %cond_next46
+ %tmp65 = and i32 %tmp32, 255 ; <i32> [#uses=1]
+ switch i32 %tmp65, label %UnifiedReturnBlock [
+ i32 6, label %bb140
+ i32 7, label %bb69
+ i32 8, label %bb140
+ i32 13, label %bb478
+ i32 23, label %bb
+ ]
+
+bb: ; preds = %cond_next57
+ tail call void @fancy_abort( i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1727, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
+ unreachable
+
+bb69: ; preds = %cond_next57
+ br i1 %tmp40, label %cond_next91, label %cond_true88
+
+cond_true88: ; preds = %bb69
+ tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1730, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
+ unreachable
+
+cond_next91: ; preds = %bb69
+ %tmp96 = getelementptr %struct.tree_node* %type, i32 0, i32 0, i32 8 ; <i8*> [#uses=1]
+ %tmp9697 = bitcast i8* %tmp96 to i32* ; <i32*> [#uses=2]
+ %tmp98 = load i32* %tmp9697, align 8 ; <i32> [#uses=2]
+ %tmp100101552 = and i32 %tmp98, 511 ; <i32> [#uses=1]
+ %tmp102 = icmp eq i32 %tmp100101552, 0 ; <i1> [#uses=1]
+ br i1 %tmp102, label %cond_true105, label %bb140
+
+cond_true105: ; preds = %cond_next91
+ br i1 %tmp40, label %cond_next127, label %cond_true124
+
+cond_true124: ; preds = %cond_true105
+ tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1731, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
+ unreachable
+
+cond_next127: ; preds = %cond_true105
+ %tmp136 = or i32 %tmp98, 1 ; <i32> [#uses=1]
+ %tmp137 = and i32 %tmp136, -511 ; <i32> [#uses=1]
+ store i32 %tmp137, i32* %tmp9697, align 8
+ br label %bb140
+
+bb140: ; preds = %cond_next127, %cond_next91, %cond_next57, %cond_next57
+ switch i8 %tmp3435, label %cond_true202 [
+ i8 6, label %cond_next208
+ i8 9, label %cond_next208
+ i8 7, label %cond_next208
+ i8 8, label %cond_next208
+ i8 10, label %cond_next208
+ ]
+
+cond_true202: ; preds = %bb140
+ tail call void (%struct.tree_node*, i8*, i32, i8*, ...)* @tree_check_failed( %struct.tree_node* %type, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1738, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0), i32 9, i32 6, i32 7, i32 8, i32 10, i32 0 )
+ unreachable
+
+cond_next208: ; preds = %bb140, %bb140, %bb140, %bb140, %bb140
+ %tmp213 = getelementptr %struct.tree_type* %tmp4950, i32 0, i32 14 ; <%struct.tree_node**> [#uses=1]
+ %tmp214 = load %struct.tree_node** %tmp213, align 8 ; <%struct.tree_node*> [#uses=2]
+ %tmp217 = getelementptr %struct.tree_node* %tmp214, i32 0, i32 0, i32 0, i32 3 ; <i8*> [#uses=1]
+ %tmp217218 = bitcast i8* %tmp217 to i32* ; <i32*> [#uses=1]
+ %tmp219 = load i32* %tmp217218, align 8 ; <i32> [#uses=1]
+ %tmp221222 = trunc i32 %tmp219 to i8 ; <i8> [#uses=1]
+ %tmp223 = icmp eq i8 %tmp221222, 24 ; <i1> [#uses=1]
+ br i1 %tmp223, label %cond_true226, label %cond_next340
+
+cond_true226: ; preds = %cond_next208
+ switch i8 %tmp3435, label %cond_true288 [
+ i8 6, label %cond_next294
+ i8 9, label %cond_next294
+ i8 7, label %cond_next294
+ i8 8, label %cond_next294
+ i8 10, label %cond_next294
+ ]
+
+cond_true288: ; preds = %cond_true226
+ tail call void (%struct.tree_node*, i8*, i32, i8*, ...)* @tree_check_failed( %struct.tree_node* %type, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1739, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0), i32 9, i32 6, i32 7, i32 8, i32 10, i32 0 )
+ unreachable
+
+cond_next294: ; preds = %cond_true226, %cond_true226, %cond_true226, %cond_true226, %cond_true226
+ %tmp301 = tail call i32 @tree_int_cst_sgn( %struct.tree_node* %tmp214 ) ; <i32> [#uses=1]
+ %tmp302 = icmp sgt i32 %tmp301, -1 ; <i1> [#uses=1]
+ br i1 %tmp302, label %cond_true305, label %cond_next340
+
+cond_true305: ; preds = %cond_next294
+ %tmp313 = load i32* %tmp3031, align 8 ; <i32> [#uses=2]
+ %tmp315316 = trunc i32 %tmp313 to i8 ; <i8> [#uses=1]
+ %tmp315316317318 = zext i8 %tmp315316 to i64 ; <i64> [#uses=1]
+ %tmp319 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp315316317318 ; <i32*> [#uses=1]
+ %tmp320 = load i32* %tmp319, align 4 ; <i32> [#uses=1]
+ %tmp321 = icmp eq i32 %tmp320, 2 ; <i1> [#uses=1]
+ br i1 %tmp321, label %cond_next327, label %cond_true324
+
+cond_true324: ; preds = %cond_true305
+ tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1740, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
+ unreachable
+
+cond_next327: ; preds = %cond_true305
+ %tmp338 = or i32 %tmp313, 8192 ; <i32> [#uses=1]
+ store i32 %tmp338, i32* %tmp3031, align 8
+ br label %cond_next340
+
+cond_next340: ; preds = %cond_next327, %cond_next294, %cond_next208
+ %tmp348 = load i32* %tmp3031, align 8 ; <i32> [#uses=1]
+ %tmp350351 = trunc i32 %tmp348 to i8 ; <i8> [#uses=1]
+ %tmp350351352353 = zext i8 %tmp350351 to i64 ; <i64> [#uses=1]
+ %tmp354 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp350351352353 ; <i32*> [#uses=1]
+ %tmp355 = load i32* %tmp354, align 4 ; <i32> [#uses=1]
+ %tmp356 = icmp eq i32 %tmp355, 2 ; <i1> [#uses=1]
+ br i1 %tmp356, label %cond_next385, label %cond_true359
+
+cond_true359: ; preds = %cond_next340
+ tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1742, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
+ unreachable
+
+cond_next385: ; preds = %cond_next340
+ %tmp390 = getelementptr %struct.tree_node* %type, i32 0, i32 0, i32 8 ; <i8*> [#uses=1]
+ %tmp390391 = bitcast i8* %tmp390 to i32* ; <i32*> [#uses=3]
+ %tmp392 = load i32* %tmp390391, align 8 ; <i32> [#uses=1]
+ %tmp394 = and i32 %tmp392, 511 ; <i32> [#uses=1]
+ %tmp397 = tail call i32 @smallest_mode_for_size( i32 %tmp394, i32 2 ) ; <i32> [#uses=1]
+ %tmp404 = load i32* %tmp390391, align 8 ; <i32> [#uses=1]
+ %tmp397398405 = shl i32 %tmp397, 9 ; <i32> [#uses=1]
+ %tmp407 = and i32 %tmp397398405, 65024 ; <i32> [#uses=1]
+ %tmp408 = and i32 %tmp404, -65025 ; <i32> [#uses=1]
+ %tmp409 = or i32 %tmp408, %tmp407 ; <i32> [#uses=2]
+ store i32 %tmp409, i32* %tmp390391, align 8
+ %tmp417 = load i32* %tmp3031, align 8 ; <i32> [#uses=1]
+ %tmp419420 = trunc i32 %tmp417 to i8 ; <i8> [#uses=1]
+ %tmp419420421422 = zext i8 %tmp419420 to i64 ; <i64> [#uses=1]
+ %tmp423 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp419420421422 ; <i32*> [#uses=1]
+ %tmp424 = load i32* %tmp423, align 4 ; <i32> [#uses=1]
+ %tmp425 = icmp eq i32 %tmp424, 2 ; <i1> [#uses=1]
+ br i1 %tmp425, label %cond_next454, label %cond_true428
+
+cond_true428: ; preds = %cond_next385
+ tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1744, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
+ unreachable
+
+cond_next454: ; preds = %cond_next385
+ lshr i32 %tmp409, 9 ; <i32>:0 [#uses=1]
+ trunc i32 %0 to i8 ; <i8>:1 [#uses=1]
+ %tmp463464 = and i8 %1, 127 ; <i8> [#uses=1]
+ %tmp463464465466 = zext i8 %tmp463464 to i64 ; <i64> [#uses=1]
+ %tmp467 = getelementptr [48 x i8]* @mode_size, i32 0, i64 %tmp463464465466 ; <i8*> [#uses=1]
+ %tmp468 = load i8* %tmp467, align 1 ; <i8> [#uses=1]
+ %tmp468469553 = zext i8 %tmp468 to i16 ; <i16> [#uses=1]
+ %tmp470471 = shl i16 %tmp468469553, 3 ; <i16> [#uses=1]
+ %tmp470471472 = zext i16 %tmp470471 to i64 ; <i64> [#uses=1]
+ %tmp473 = tail call %struct.tree_node* @size_int_kind( i64 %tmp470471472, i32 2 ) ; <%struct.tree_node*> [#uses=1]
+ store %struct.tree_node* %tmp473, %struct.tree_node** %tmp51, align 8
+ ret void
+
+bb478: ; preds = %cond_next57
+ br i1 %tmp40, label %cond_next500, label %cond_true497
+
+cond_true497: ; preds = %bb478
+ tail call void @tree_class_check_failed( %struct.tree_node* %type, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1755, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
+ unreachable
+
+cond_next500: ; preds = %bb478
+ %tmp506 = getelementptr %struct.tree_node* %type, i32 0, i32 0, i32 0, i32 1 ; <%struct.tree_node**> [#uses=1]
+ %tmp507 = load %struct.tree_node** %tmp506, align 8 ; <%struct.tree_node*> [#uses=2]
+ %tmp511 = getelementptr %struct.tree_node* %tmp507, i32 0, i32 0, i32 0, i32 3 ; <i8*> [#uses=1]
+ %tmp511512 = bitcast i8* %tmp511 to i32* ; <i32*> [#uses=1]
+ %tmp513 = load i32* %tmp511512, align 8 ; <i32> [#uses=2]
+ %tmp515516 = trunc i32 %tmp513 to i8 ; <i8> [#uses=1]
+ %tmp515516517518 = zext i8 %tmp515516 to i64 ; <i64> [#uses=1]
+ %tmp519 = getelementptr [0 x i32]* @tree_code_type, i32 0, i64 %tmp515516517518 ; <i32*> [#uses=1]
+ %tmp520 = load i32* %tmp519, align 4 ; <i32> [#uses=1]
+ %tmp521 = icmp eq i32 %tmp520, 2 ; <i1> [#uses=1]
+ br i1 %tmp521, label %cond_next527, label %cond_true524
+
+cond_true524: ; preds = %cond_next500
+ tail call void @tree_class_check_failed( %struct.tree_node* %tmp507, i32 2, i8* getelementptr ([28 x i8]* @.str, i32 0, i64 0), i32 1755, i8* getelementptr ([12 x i8]* @__FUNCTION__.22683, i32 0, i32 0) )
+ unreachable
+
+cond_next527: ; preds = %cond_next500
+ %tmp545 = and i32 %tmp513, 8192 ; <i32> [#uses=1]
+ %tmp547 = and i32 %tmp32, -8193 ; <i32> [#uses=1]
+ %tmp548 = or i32 %tmp547, %tmp545 ; <i32> [#uses=1]
+ store i32 %tmp548, i32* %tmp3031, align 8
+ ret void
+
+UnifiedReturnBlock: ; preds = %cond_next57, %cond_next46, %cond_false
+ ret void
+}
+
+declare void @fancy_abort(i8*, i32, i8*)
+
+declare void @tree_class_check_failed(%struct.tree_node*, i32, i8*, i32, i8*)
+
+declare i32 @smallest_mode_for_size(i32, i32)
+
+declare %struct.tree_node* @size_int_kind(i64, i32)
+
+declare void @tree_check_failed(%struct.tree_node*, i8*, i32, i8*, ...)
+
+declare i32 @tree_int_cst_sgn(%struct.tree_node*)
diff --git a/test/CodeGen/X86/2007-10-16-fp80_select.ll b/test/CodeGen/X86/2007-10-16-fp80_select.ll
new file mode 100644
index 0000000..3f9845c
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-16-fp80_select.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin9"
+ %struct.wxPoint2DInt = type { i32, i32 }
+
+define x86_fp80 @_ZNK12wxPoint2DInt14GetVectorAngleEv(%struct.wxPoint2DInt* %this) {
+entry:
+ br i1 false, label %cond_true, label %UnifiedReturnBlock
+
+cond_true: ; preds = %entry
+ %tmp8 = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp9 = icmp sgt i32 %tmp8, -1 ; <i1> [#uses=1]
+ %retval = select i1 %tmp9, x86_fp80 0xK4005B400000000000000, x86_fp80 0xK40078700000000000000 ; <x86_fp80> [#uses=1]
+ ret x86_fp80 %retval
+
+UnifiedReturnBlock: ; preds = %entry
+ ret x86_fp80 0xK4005B400000000000000
+}
diff --git a/test/CodeGen/X86/2007-10-17-IllegalAsm.ll b/test/CodeGen/X86/2007-10-17-IllegalAsm.ll
new file mode 100644
index 0000000..c0bb55e
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-17-IllegalAsm.ll
@@ -0,0 +1,87 @@
+; RUN: llc < %s -mtriple=x86_64-linux-gnu | grep addb | not grep x
+; RUN: llc < %s -mtriple=x86_64-linux-gnu | grep cmpb | not grep x
+; PR1734
+
+target triple = "x86_64-unknown-linux-gnu"
+ %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.eh_status = type opaque
+ %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }
+ %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+ %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, %struct.tree_node*, i8, i8, i8 }
+ %struct.initial_value_struct = type opaque
+ %struct.lang_decl = type opaque
+ %struct.language_function = type opaque
+ %struct.location_t = type { i8*, i32 }
+ %struct.machine_function = type { %struct.stack_local_entry*, i8*, %struct.rtx_def*, i32, i32, i32, i32, i32 }
+ %struct.rtunion = type { i8* }
+ %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }
+ %struct.rtx_def = type { i16, i8, i8, %struct.u }
+ %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
+ %struct.stack_local_entry = type opaque
+ %struct.temp_slot = type opaque
+ %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 }
+ %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_decl_u1 = type { i64 }
+ %struct.tree_decl_u2 = type { %struct.function* }
+ %struct.tree_node = type { %struct.tree_decl }
+ %struct.u = type { [1 x %struct.rtunion] }
+ %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+ %struct.varasm_status = type opaque
+ %struct.varray_data = type { [1 x i64] }
+ %struct.varray_head_tag = type { i64, i64, i32, i8*, %struct.varray_data }
+ %union.tree_ann_d = type opaque
+
+define void @layout_type(%struct.tree_node* %type) {
+entry:
+ %tmp32 = load i32* null, align 8 ; <i32> [#uses=3]
+ %tmp3435 = trunc i32 %tmp32 to i8 ; <i8> [#uses=1]
+ %tmp53 = icmp eq %struct.tree_node* null, null ; <i1> [#uses=1]
+ br i1 %tmp53, label %cond_next57, label %UnifiedReturnBlock
+
+cond_next57: ; preds = %entry
+ %tmp65 = and i32 %tmp32, 255 ; <i32> [#uses=1]
+ switch i32 %tmp65, label %UnifiedReturnBlock [
+ i32 6, label %bb140
+ i32 7, label %bb140
+ i32 8, label %bb140
+ i32 13, label %bb478
+ ]
+
+bb140: ; preds = %cond_next57, %cond_next57, %cond_next57
+ %tmp219 = load i32* null, align 8 ; <i32> [#uses=1]
+ %tmp221222 = trunc i32 %tmp219 to i8 ; <i8> [#uses=1]
+ %tmp223 = icmp eq i8 %tmp221222, 24 ; <i1> [#uses=1]
+ br i1 %tmp223, label %cond_true226, label %cond_next340
+
+cond_true226: ; preds = %bb140
+ switch i8 %tmp3435, label %cond_true288 [
+ i8 6, label %cond_next340
+ i8 9, label %cond_next340
+ i8 7, label %cond_next340
+ i8 8, label %cond_next340
+ i8 10, label %cond_next340
+ ]
+
+cond_true288: ; preds = %cond_true226
+ unreachable
+
+cond_next340: ; preds = %cond_true226, %cond_true226, %cond_true226, %cond_true226, %cond_true226, %bb140
+ ret void
+
+bb478: ; preds = %cond_next57
+ br i1 false, label %cond_next500, label %cond_true497
+
+cond_true497: ; preds = %bb478
+ unreachable
+
+cond_next500: ; preds = %bb478
+ %tmp513 = load i32* null, align 8 ; <i32> [#uses=1]
+ %tmp545 = and i32 %tmp513, 8192 ; <i32> [#uses=1]
+ %tmp547 = and i32 %tmp32, -8193 ; <i32> [#uses=1]
+ %tmp548 = or i32 %tmp547, %tmp545 ; <i32> [#uses=1]
+ store i32 %tmp548, i32* null, align 8
+ ret void
+
+UnifiedReturnBlock: ; preds = %cond_next57, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll b/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll
new file mode 100644
index 0000000..600bd1f
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll
@@ -0,0 +1,84 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | grep inc | not grep PTR
+
+define i16 @t(i32* %bitptr, i32* %source, i8** %byteptr, i32 %scale, i32 %round) signext {
+entry:
+ br label %bb
+
+bb: ; preds = %cond_next391, %entry
+ %cnt.0 = phi i32 [ 0, %entry ], [ %tmp422445, %cond_next391 ] ; <i32> [#uses=1]
+ %v.1 = phi i32 [ undef, %entry ], [ %tmp411, %cond_next391 ] ; <i32> [#uses=0]
+ br i1 false, label %cond_true, label %cond_next127
+
+cond_true: ; preds = %bb
+ store i8* null, i8** %byteptr, align 4
+ store i8* null, i8** %byteptr, align 4
+ br label %cond_next127
+
+cond_next127: ; preds = %cond_true, %bb
+ %tmp151 = add i32 0, %round ; <i32> [#uses=1]
+ %tmp153 = ashr i32 %tmp151, %scale ; <i32> [#uses=2]
+ %tmp154155 = trunc i32 %tmp153 to i16 ; <i16> [#uses=1]
+ %tmp154155156 = sext i16 %tmp154155 to i32 ; <i32> [#uses=1]
+ %tmp158 = xor i32 %tmp154155156, %tmp153 ; <i32> [#uses=1]
+ %tmp160 = or i32 %tmp158, %cnt.0 ; <i32> [#uses=1]
+ %tmp171 = load i32* %bitptr, align 4 ; <i32> [#uses=1]
+ %tmp180181 = sext i16 0 to i32 ; <i32> [#uses=3]
+ %tmp183 = add i32 %tmp160, 1 ; <i32> [#uses=1]
+ br i1 false, label %cond_true188, label %cond_next245
+
+cond_true188: ; preds = %cond_next127
+ ret i16 0
+
+cond_next245: ; preds = %cond_next127
+ %tmp249 = ashr i32 %tmp180181, 8 ; <i32> [#uses=1]
+ %tmp250 = add i32 %tmp171, %tmp249 ; <i32> [#uses=1]
+ %tmp253444 = lshr i32 %tmp180181, 4 ; <i32> [#uses=1]
+ %tmp254 = and i32 %tmp253444, 15 ; <i32> [#uses=1]
+ %tmp256 = and i32 %tmp180181, 15 ; <i32> [#uses=2]
+ %tmp264 = icmp ugt i32 %tmp250, 15 ; <i1> [#uses=1]
+ br i1 %tmp264, label %cond_true267, label %cond_next391
+
+cond_true267: ; preds = %cond_next245
+ store i8* null, i8** %byteptr, align 4
+ store i8* null, i8** %byteptr, align 4
+ br i1 false, label %cond_true289, label %cond_next327
+
+cond_true289: ; preds = %cond_true267
+ ret i16 0
+
+cond_next327: ; preds = %cond_true267
+ br i1 false, label %cond_true343, label %cond_next385
+
+cond_true343: ; preds = %cond_next327
+ %tmp345 = load i8** %byteptr, align 4 ; <i8*> [#uses=1]
+ store i8* null, i8** %byteptr, align 4
+ br i1 false, label %cond_next385, label %cond_true352
+
+cond_true352: ; preds = %cond_true343
+ store i8* %tmp345, i8** %byteptr, align 4
+ br i1 false, label %cond_true364, label %cond_next385
+
+cond_true364: ; preds = %cond_true352
+ ret i16 0
+
+cond_next385: ; preds = %cond_true352, %cond_true343, %cond_next327
+ br label %cond_next391
+
+cond_next391: ; preds = %cond_next385, %cond_next245
+ %tmp393 = load i32* %source, align 4 ; <i32> [#uses=1]
+ %tmp395 = load i32* %bitptr, align 4 ; <i32> [#uses=2]
+ %tmp396 = shl i32 %tmp393, %tmp395 ; <i32> [#uses=1]
+ %tmp398 = sub i32 32, %tmp256 ; <i32> [#uses=1]
+ %tmp405 = lshr i32 %tmp396, 31 ; <i32> [#uses=1]
+ %tmp406 = add i32 %tmp405, -1 ; <i32> [#uses=1]
+ %tmp409 = lshr i32 %tmp406, %tmp398 ; <i32> [#uses=1]
+ %tmp411 = sub i32 0, %tmp409 ; <i32> [#uses=1]
+ %tmp422445 = add i32 %tmp254, %tmp183 ; <i32> [#uses=2]
+ %tmp426447 = add i32 %tmp395, %tmp256 ; <i32> [#uses=1]
+ store i32 %tmp426447, i32* %bitptr, align 4
+ %tmp429448 = icmp ult i32 %tmp422445, 63 ; <i1> [#uses=1]
+ br i1 %tmp429448, label %bb, label %UnifiedReturnBlock
+
+UnifiedReturnBlock: ; preds = %cond_next391
+ ret i16 0
+}
diff --git a/test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll b/test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll
new file mode 100644
index 0000000..984094d
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+; PR1748
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i32 @kernel_init(i8* %unused) {
+entry:
+ call void asm sideeffect "foo ${0:q}", "=*imr"( i64* null )
+ ret i32 0
+}
+
diff --git a/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll b/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
new file mode 100644
index 0000000..86d3bbf
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 | grep mov | count 1
+
+define i16 @t() signext {
+entry:
+ %tmp180 = load i16* null, align 2 ; <i16> [#uses=3]
+ %tmp180181 = sext i16 %tmp180 to i32 ; <i32> [#uses=1]
+ %tmp185 = icmp slt i16 %tmp180, 0 ; <i1> [#uses=1]
+ br i1 %tmp185, label %cond_true188, label %cond_next245
+
+cond_true188: ; preds = %entry
+ %tmp195196 = trunc i16 %tmp180 to i8 ; <i8> [#uses=0]
+ ret i16 0
+
+cond_next245: ; preds = %entry
+ %tmp256 = and i32 %tmp180181, 15 ; <i32> [#uses=0]
+ ret i16 0
+}
diff --git a/test/CodeGen/X86/2007-10-30-LSRCrash.ll b/test/CodeGen/X86/2007-10-30-LSRCrash.ll
new file mode 100644
index 0000000..42db98b
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-30-LSRCrash.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -march=x86
+
+define i32 @unique(i8* %full, i32 %p, i32 %len, i32 %mode, i32 %verbos, i32 %flags) {
+entry:
+ br i1 false, label %cond_true15, label %cond_next107
+
+cond_true15: ; preds = %entry
+ br i1 false, label %bb98.preheader, label %bb
+
+bb: ; preds = %cond_true15
+ ret i32 0
+
+bb98.preheader: ; preds = %cond_true15
+ br i1 false, label %bb103, label %bb69.outer
+
+bb76.split: ; preds = %bb69.outer.split.split, %bb69.us208
+ br i1 false, label %bb103, label %bb69.outer
+
+bb69.outer: ; preds = %bb76.split, %bb98.preheader
+ %from.0.reg2mem.0.ph.rec = phi i32 [ %tmp75.rec, %bb76.split ], [ 0, %bb98.preheader ] ; <i32> [#uses=1]
+ %tmp75.rec = add i32 %from.0.reg2mem.0.ph.rec, 1 ; <i32> [#uses=2]
+ %tmp75 = getelementptr i8* null, i32 %tmp75.rec ; <i8*> [#uses=6]
+ br i1 false, label %bb69.us208, label %bb69.outer.split.split
+
+bb69.us208: ; preds = %bb69.outer
+ switch i32 0, label %bb76.split [
+ i32 47, label %bb89
+ i32 58, label %bb89
+ i32 92, label %bb89
+ ]
+
+bb69.outer.split.split: ; preds = %bb69.outer
+ switch i8 0, label %bb76.split [
+ i8 47, label %bb89
+ i8 58, label %bb89
+ i8 92, label %bb89
+ ]
+
+bb89: ; preds = %bb69.outer.split.split, %bb69.outer.split.split, %bb69.outer.split.split, %bb69.us208, %bb69.us208, %bb69.us208
+ %tmp75.lcssa189 = phi i8* [ %tmp75, %bb69.us208 ], [ %tmp75, %bb69.us208 ], [ %tmp75, %bb69.us208 ], [ %tmp75, %bb69.outer.split.split ], [ %tmp75, %bb69.outer.split.split ], [ %tmp75, %bb69.outer.split.split ] ; <i8*> [#uses=0]
+ ret i32 0
+
+bb103: ; preds = %bb76.split, %bb98.preheader
+ ret i32 0
+
+cond_next107: ; preds = %entry
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2007-10-31-extractelement-i64.ll b/test/CodeGen/X86/2007-10-31-extractelement-i64.ll
new file mode 100644
index 0000000..1b8e67d
--- /dev/null
+++ b/test/CodeGen/X86/2007-10-31-extractelement-i64.ll
@@ -0,0 +1,82 @@
+; RUN: llc < %s -march=x86 -mattr=sse2
+; ModuleID = 'yyy.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin8"
+
+define <1 x i64> @a(<2 x i64> %__A) {
+entry:
+ %__A_addr = alloca <2 x i64> ; <<2 x i64>*> [#uses=2]
+ %retval = alloca <1 x i64>, align 8 ; <<1 x i64>*> [#uses=3]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store <2 x i64> %__A, <2 x i64>* %__A_addr
+ %tmp = load <2 x i64>* %__A_addr, align 16 ; <<2 x i64>> [#uses=1]
+ %tmp1 = bitcast <2 x i64> %tmp to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp2 = extractelement <2 x i64> %tmp1, i32 0 ; <i64> [#uses=1]
+ %tmp3 = bitcast i64 %tmp2 to <1 x i64> ; <<1 x i64>> [#uses=1]
+ store <1 x i64> %tmp3, <1 x i64>* %retval, align 8
+ %tmp4 = load <1 x i64>* %retval, align 8 ; <<1 x i64>> [#uses=0]
+ br label %return
+
+return: ; preds = %entry
+ %retval5 = load <1 x i64>* %retval ; <<1 x i64>> [#uses=1]
+ ret <1 x i64> %retval5
+}
+
+define <1 x i64> @b(<2 x i64> %__A) {
+entry:
+ %__A_addr = alloca <2 x i64> ; <<2 x i64>*> [#uses=2]
+ %retval = alloca <1 x i64>, align 8 ; <<1 x i64>*> [#uses=3]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store <2 x i64> %__A, <2 x i64>* %__A_addr
+ %tmp = load <2 x i64>* %__A_addr, align 16 ; <<2 x i64>> [#uses=1]
+ %tmp1 = bitcast <2 x i64> %tmp to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp2 = extractelement <2 x i64> %tmp1, i32 1 ; <i64> [#uses=1]
+ %tmp3 = bitcast i64 %tmp2 to <1 x i64> ; <<1 x i64>> [#uses=1]
+ store <1 x i64> %tmp3, <1 x i64>* %retval, align 8
+ %tmp4 = load <1 x i64>* %retval, align 8 ; <<1 x i64>> [#uses=0]
+ br label %return
+
+return: ; preds = %entry
+ %retval5 = load <1 x i64>* %retval ; <<1 x i64>> [#uses=1]
+ ret <1 x i64> %retval5
+}
+
+define i64 @c(<2 x i64> %__A) {
+entry:
+ %__A_addr = alloca <2 x i64> ; <<2 x i64>*> [#uses=2]
+ %retval = alloca i64, align 8 ; <i64*> [#uses=2]
+ %tmp = alloca i64, align 8 ; <i64*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store <2 x i64> %__A, <2 x i64>* %__A_addr
+ %tmp1 = load <2 x i64>* %__A_addr, align 16 ; <<2 x i64>> [#uses=1]
+ %tmp2 = bitcast <2 x i64> %tmp1 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp3 = extractelement <2 x i64> %tmp2, i32 0 ; <i64> [#uses=1]
+ store i64 %tmp3, i64* %tmp, align 8
+ %tmp4 = load i64* %tmp, align 8 ; <i64> [#uses=1]
+ store i64 %tmp4, i64* %retval, align 8
+ br label %return
+
+return: ; preds = %entry
+ %retval5 = load i64* %retval ; <i64> [#uses=1]
+ ret i64 %retval5
+}
+
+define i64 @d(<2 x i64> %__A) {
+entry:
+ %__A_addr = alloca <2 x i64> ; <<2 x i64>*> [#uses=2]
+ %retval = alloca i64, align 8 ; <i64*> [#uses=2]
+ %tmp = alloca i64, align 8 ; <i64*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store <2 x i64> %__A, <2 x i64>* %__A_addr
+ %tmp1 = load <2 x i64>* %__A_addr, align 16 ; <<2 x i64>> [#uses=1]
+ %tmp2 = bitcast <2 x i64> %tmp1 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp3 = extractelement <2 x i64> %tmp2, i32 1 ; <i64> [#uses=1]
+ store i64 %tmp3, i64* %tmp, align 8
+ %tmp4 = load i64* %tmp, align 8 ; <i64> [#uses=1]
+ store i64 %tmp4, i64* %retval, align 8
+ br label %return
+
+return: ; preds = %entry
+ %retval5 = load i64* %retval ; <i64> [#uses=1]
+ ret i64 %retval5
+}
diff --git a/test/CodeGen/X86/2007-11-01-ISelCrash.ll b/test/CodeGen/X86/2007-11-01-ISelCrash.ll
new file mode 100644
index 0000000..019c6a8
--- /dev/null
+++ b/test/CodeGen/X86/2007-11-01-ISelCrash.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86
+
+ %"struct.K::JL" = type <{ i8 }>
+ %struct.jv = type { i64 }
+
+declare fastcc i64 @f(i32, %"struct.K::JL"*, i8*, i8*, %struct.jv*)
+
+define void @t(%"struct.K::JL"* %obj, i8* %name, i8* %sig, %struct.jv* %args) {
+entry:
+ %tmp5 = tail call fastcc i64 @f( i32 1, %"struct.K::JL"* %obj, i8* %name, i8* %sig, %struct.jv* %args ) ; <i64> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/X86/2007-11-02-BadAsm.ll b/test/CodeGen/X86/2007-11-02-BadAsm.ll
new file mode 100644
index 0000000..4e11cda
--- /dev/null
+++ b/test/CodeGen/X86/2007-11-02-BadAsm.ll
@@ -0,0 +1,144 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movl | not grep rax
+
+ %struct.color_sample = type { i64 }
+ %struct.gs_matrix = type { float, i64, float, i64, float, i64, float, i64, float, i64, float, i64 }
+ %struct.ref = type { %struct.color_sample, i16, i16 }
+ %struct.status = type { %struct.gs_matrix, i8*, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i32 }
+
+define i32 @ztype1imagepath(%struct.ref* %op) {
+entry:
+ br i1 false, label %cond_next, label %UnifiedReturnBlock
+
+cond_next: ; preds = %entry
+ br i1 false, label %cond_next68, label %UnifiedReturnBlock
+
+cond_next68: ; preds = %cond_next
+ %tmp5.i.i = malloc i8, i32 0 ; <i8*> [#uses=2]
+ br i1 false, label %bb81.outer.i, label %xit.i
+
+bb81.outer.i: ; preds = %bb87.i, %cond_next68
+ %tmp67.i = add i32 0, 1 ; <i32> [#uses=1]
+ br label %bb81.i
+
+bb61.i: ; preds = %bb81.i
+ %tmp71.i = getelementptr i8* %tmp5.i.i, i64 0 ; <i8*> [#uses=1]
+ %tmp72.i = load i8* %tmp71.i, align 1 ; <i8> [#uses=1]
+ %tmp73.i = icmp eq i8 %tmp72.i, 0 ; <i1> [#uses=1]
+ br i1 %tmp73.i, label %bb81.i, label %xit.i
+
+bb81.i: ; preds = %bb61.i, %bb81.outer.i
+ br i1 false, label %bb87.i, label %bb61.i
+
+bb87.i: ; preds = %bb81.i
+ br i1 false, label %bb81.outer.i, label %xit.i
+
+xit.i: ; preds = %bb87.i, %bb61.i, %cond_next68
+ %lsbx.0.reg2mem.1.i = phi i32 [ 0, %cond_next68 ], [ 0, %bb61.i ], [ %tmp67.i, %bb87.i ] ; <i32> [#uses=1]
+ %tmp6162.i.i = fptrunc double 0.000000e+00 to float ; <float> [#uses=1]
+ %tmp67.i15.i = fptrunc double 0.000000e+00 to float ; <float> [#uses=1]
+ %tmp24.i27.i = icmp eq i64 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp24.i27.i, label %cond_next.i79.i, label %cond_true.i34.i
+
+cond_true.i34.i: ; preds = %xit.i
+ ret i32 0
+
+cond_next.i79.i: ; preds = %xit.i
+ %phitmp167.i = fptosi double 0.000000e+00 to i64 ; <i64> [#uses=1]
+ %tmp142143.i = fpext float %tmp6162.i.i to double ; <double> [#uses=1]
+ %tmp2.i139.i = fadd double %tmp142143.i, 5.000000e-01 ; <double> [#uses=1]
+ %tmp23.i140.i = fptosi double %tmp2.i139.i to i64 ; <i64> [#uses=1]
+ br i1 false, label %cond_true.i143.i, label %round_coord.exit148.i
+
+cond_true.i143.i: ; preds = %cond_next.i79.i
+ %tmp8.i142.i = icmp sgt i64 %tmp23.i140.i, -32768 ; <i1> [#uses=1]
+ br i1 %tmp8.i142.i, label %cond_true11.i145.i, label %round_coord.exit148.i
+
+cond_true11.i145.i: ; preds = %cond_true.i143.i
+ ret i32 0
+
+round_coord.exit148.i: ; preds = %cond_true.i143.i, %cond_next.i79.i
+ %tmp144149.i = phi i32 [ 32767, %cond_next.i79.i ], [ -32767, %cond_true.i143.i ] ; <i32> [#uses=1]
+ store i32 %tmp144149.i, i32* null, align 8
+ %tmp147148.i = fpext float %tmp67.i15.i to double ; <double> [#uses=1]
+ %tmp2.i128.i = fadd double %tmp147148.i, 5.000000e-01 ; <double> [#uses=1]
+ %tmp23.i129.i = fptosi double %tmp2.i128.i to i64 ; <i64> [#uses=2]
+ %tmp5.i130.i = icmp slt i64 %tmp23.i129.i, 32768 ; <i1> [#uses=1]
+ br i1 %tmp5.i130.i, label %cond_true.i132.i, label %round_coord.exit137.i
+
+cond_true.i132.i: ; preds = %round_coord.exit148.i
+ %tmp8.i131.i = icmp sgt i64 %tmp23.i129.i, -32768 ; <i1> [#uses=1]
+ br i1 %tmp8.i131.i, label %cond_true11.i134.i, label %round_coord.exit137.i
+
+cond_true11.i134.i: ; preds = %cond_true.i132.i
+ br label %round_coord.exit137.i
+
+round_coord.exit137.i: ; preds = %cond_true11.i134.i, %cond_true.i132.i, %round_coord.exit148.i
+ %tmp149138.i = phi i32 [ 0, %cond_true11.i134.i ], [ 32767, %round_coord.exit148.i ], [ -32767, %cond_true.i132.i ] ; <i32> [#uses=1]
+ br i1 false, label %cond_true.i121.i, label %round_coord.exit126.i
+
+cond_true.i121.i: ; preds = %round_coord.exit137.i
+ br i1 false, label %cond_true11.i123.i, label %round_coord.exit126.i
+
+cond_true11.i123.i: ; preds = %cond_true.i121.i
+ br label %round_coord.exit126.i
+
+round_coord.exit126.i: ; preds = %cond_true11.i123.i, %cond_true.i121.i, %round_coord.exit137.i
+ %tmp153127.i = phi i32 [ 0, %cond_true11.i123.i ], [ 32767, %round_coord.exit137.i ], [ -32767, %cond_true.i121.i ] ; <i32> [#uses=1]
+ br i1 false, label %cond_true.i110.i, label %round_coord.exit115.i
+
+cond_true.i110.i: ; preds = %round_coord.exit126.i
+ br i1 false, label %cond_true11.i112.i, label %round_coord.exit115.i
+
+cond_true11.i112.i: ; preds = %cond_true.i110.i
+ br label %round_coord.exit115.i
+
+round_coord.exit115.i: ; preds = %cond_true11.i112.i, %cond_true.i110.i, %round_coord.exit126.i
+ %tmp157116.i = phi i32 [ 0, %cond_true11.i112.i ], [ 32767, %round_coord.exit126.i ], [ -32767, %cond_true.i110.i ] ; <i32> [#uses=2]
+ br i1 false, label %cond_true.i99.i, label %round_coord.exit104.i
+
+cond_true.i99.i: ; preds = %round_coord.exit115.i
+ br i1 false, label %cond_true11.i101.i, label %round_coord.exit104.i
+
+cond_true11.i101.i: ; preds = %cond_true.i99.i
+ %tmp1213.i100.i = trunc i64 %phitmp167.i to i32 ; <i32> [#uses=1]
+ br label %cond_next172.i
+
+round_coord.exit104.i: ; preds = %cond_true.i99.i, %round_coord.exit115.i
+ %UnifiedRetVal.i102.i = phi i32 [ 32767, %round_coord.exit115.i ], [ -32767, %cond_true.i99.i ] ; <i32> [#uses=1]
+ %tmp164.i = call fastcc i32 @put_int( %struct.status* null, i32 %tmp157116.i ) ; <i32> [#uses=0]
+ br label %cond_next172.i
+
+cond_next172.i: ; preds = %round_coord.exit104.i, %cond_true11.i101.i
+ %tmp161105.reg2mem.0.i = phi i32 [ %tmp1213.i100.i, %cond_true11.i101.i ], [ %UnifiedRetVal.i102.i, %round_coord.exit104.i ] ; <i32> [#uses=1]
+ %tmp174.i = icmp eq i32 %tmp153127.i, 0 ; <i1> [#uses=1]
+ %bothcond.i = and i1 false, %tmp174.i ; <i1> [#uses=1]
+ %tmp235.i = call fastcc i32 @put_int( %struct.status* null, i32 %tmp149138.i ) ; <i32> [#uses=0]
+ %tmp245.i = load i8** null, align 8 ; <i8*> [#uses=2]
+ %tmp246.i = getelementptr i8* %tmp245.i, i64 1 ; <i8*> [#uses=1]
+ br i1 %bothcond.i, label %cond_next254.i, label %bb259.i
+
+cond_next254.i: ; preds = %cond_next172.i
+ store i8 13, i8* %tmp245.i, align 1
+ br label %bb259.i
+
+bb259.i: ; preds = %cond_next254.i, %cond_next172.i
+ %storemerge.i = phi i8* [ %tmp246.i, %cond_next254.i ], [ null, %cond_next172.i ] ; <i8*> [#uses=0]
+ %tmp261.i = shl i32 %lsbx.0.reg2mem.1.i, 2 ; <i32> [#uses=1]
+ store i32 %tmp261.i, i32* null, align 8
+ %tmp270.i = add i32 0, %tmp157116.i ; <i32> [#uses=1]
+ store i32 %tmp270.i, i32* null, align 8
+ %tmp275.i = add i32 0, %tmp161105.reg2mem.0.i ; <i32> [#uses=0]
+ br i1 false, label %trace_cells.exit.i, label %bb.preheader.i.i
+
+bb.preheader.i.i: ; preds = %bb259.i
+ ret i32 0
+
+trace_cells.exit.i: ; preds = %bb259.i
+ free i8* %tmp5.i.i
+ ret i32 0
+
+UnifiedReturnBlock: ; preds = %cond_next, %entry
+ ret i32 -20
+}
+
+declare fastcc i32 @put_int(%struct.status*, i32)
diff --git a/test/CodeGen/X86/2007-11-03-x86-64-q-constraint.ll b/test/CodeGen/X86/2007-11-03-x86-64-q-constraint.ll
new file mode 100644
index 0000000..27ec826
--- /dev/null
+++ b/test/CodeGen/X86/2007-11-03-x86-64-q-constraint.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s
+; PR1763
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @yield() {
+ %tmp9 = call i64 asm sideeffect "xchgb ${0:b},$1", "=q,*m,0,~{dirflag},~{fpsr},~{flags},~{memory}"( i64* null, i64 0 ) ; <i64>
+ ret void
+}
diff --git a/test/CodeGen/X86/2007-11-04-LiveIntervalCrash.ll b/test/CodeGen/X86/2007-11-04-LiveIntervalCrash.ll
new file mode 100644
index 0000000..4045618
--- /dev/null
+++ b/test/CodeGen/X86/2007-11-04-LiveIntervalCrash.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
+; PR1766
+
+ %struct.dentry = type { %struct.dentry_operations* }
+ %struct.dentry_operations = type { i32 (%struct.dentry*, %struct.qstr*)* }
+ %struct.qstr = type { i32, i32, i8* }
+
+define %struct.dentry* @d_hash_and_lookup(%struct.dentry* %dir, %struct.qstr* %name) {
+entry:
+ br i1 false, label %bb37, label %bb
+
+bb: ; preds = %bb, %entry
+ %name8.0.reg2mem.0.rec = phi i64 [ %indvar.next, %bb ], [ 0, %entry ] ; <i64> [#uses=1]
+ %hash.0.reg2mem.0 = phi i64 [ %tmp27, %bb ], [ 0, %entry ] ; <i64> [#uses=1]
+ %tmp13 = load i8* null, align 1 ; <i8> [#uses=1]
+ %tmp1314 = zext i8 %tmp13 to i64 ; <i64> [#uses=1]
+ %tmp25 = lshr i64 %tmp1314, 4 ; <i64> [#uses=1]
+ %tmp22 = add i64 %tmp25, %hash.0.reg2mem.0 ; <i64> [#uses=1]
+ %tmp26 = add i64 %tmp22, 0 ; <i64> [#uses=1]
+ %tmp27 = mul i64 %tmp26, 11 ; <i64> [#uses=2]
+ %indvar.next = add i64 %name8.0.reg2mem.0.rec, 1 ; <i64> [#uses=2]
+ %exitcond = icmp eq i64 %indvar.next, 0 ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb37.loopexit, label %bb
+
+bb37.loopexit: ; preds = %bb
+ %phitmp = trunc i64 %tmp27 to i32 ; <i32> [#uses=1]
+ br label %bb37
+
+bb37: ; preds = %bb37.loopexit, %entry
+ %hash.0.reg2mem.1 = phi i32 [ %phitmp, %bb37.loopexit ], [ 0, %entry ] ; <i32> [#uses=1]
+ store i32 %hash.0.reg2mem.1, i32* null, align 8
+ %tmp75 = tail call i32 null( %struct.dentry* %dir, %struct.qstr* %name ) ; <i32> [#uses=0]
+ %tmp84 = tail call i32 (...)* @d_lookup( %struct.dentry* %dir, %struct.qstr* %name ) ; <i32> [#uses=0]
+ ret %struct.dentry* null
+}
+
+declare i32 @d_lookup(...)
diff --git a/test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll b/test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll
new file mode 100644
index 0000000..6b871aa
--- /dev/null
+++ b/test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
+; PR1767
+
+define void @xor_sse_2(i64 %bytes, i64* %p1, i64* %p2) {
+entry:
+ %p2_addr = alloca i64* ; <i64**> [#uses=2]
+ %lines = alloca i32 ; <i32*> [#uses=2]
+ store i64* %p2, i64** %p2_addr, align 8
+ %tmp1 = lshr i64 %bytes, 8 ; <i64> [#uses=1]
+ %tmp12 = trunc i64 %tmp1 to i32 ; <i32> [#uses=2]
+ store i32 %tmp12, i32* %lines, align 4
+ %tmp6 = call i64* asm sideeffect "foo",
+"=r,=*r,=*r,r,0,1,2,~{dirflag},~{fpsr},~{flags},~{memory}"( i64** %p2_addr,
+i32* %lines, i64 256, i64* %p1, i64* %p2, i32 %tmp12 ) ; <i64*> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll b/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll
new file mode 100644
index 0000000..8e586a7
--- /dev/null
+++ b/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -relocation-model=static | grep {foo _str$}
+; PR1761
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin8"
+@str = internal constant [12 x i8] c"init/main.c\00" ; <[12 x i8]*> [#uses=1]
+
+define i32 @unknown_bootoption() {
+entry:
+ tail call void asm sideeffect "foo ${0:c}\0A", "i,~{dirflag},~{fpsr},~{flags}"( i8* getelementptr ([12 x i8]* @str, i32 0, i64 0) )
+ ret i32 undef
+}
diff --git a/test/CodeGen/X86/2007-11-06-InstrSched.ll b/test/CodeGen/X86/2007-11-06-InstrSched.ll
new file mode 100644
index 0000000..f6db0d0
--- /dev/null
+++ b/test/CodeGen/X86/2007-11-06-InstrSched.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep lea
+
+define float @foo(i32* %x, float* %y, i32 %c) nounwind {
+entry:
+ %tmp2132 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
+ br i1 %tmp2132, label %bb23, label %bb18
+
+bb18: ; preds = %bb18, %entry
+ %i.0.reg2mem.0 = phi i32 [ 0, %entry ], [ %tmp17, %bb18 ] ; <i32> [#uses=3]
+ %res.0.reg2mem.0 = phi float [ 0.000000e+00, %entry ], [ %tmp14, %bb18 ] ; <float> [#uses=1]
+ %tmp3 = getelementptr i32* %x, i32 %i.0.reg2mem.0 ; <i32*> [#uses=1]
+ %tmp4 = load i32* %tmp3, align 4 ; <i32> [#uses=1]
+ %tmp45 = sitofp i32 %tmp4 to float ; <float> [#uses=1]
+ %tmp8 = getelementptr float* %y, i32 %i.0.reg2mem.0 ; <float*> [#uses=1]
+ %tmp9 = load float* %tmp8, align 4 ; <float> [#uses=1]
+ %tmp11 = fmul float %tmp9, %tmp45 ; <float> [#uses=1]
+ %tmp14 = fadd float %tmp11, %res.0.reg2mem.0 ; <float> [#uses=2]
+ %tmp17 = add i32 %i.0.reg2mem.0, 1 ; <i32> [#uses=2]
+ %tmp21 = icmp ult i32 %tmp17, %c ; <i1> [#uses=1]
+ br i1 %tmp21, label %bb18, label %bb23
+
+bb23: ; preds = %bb18, %entry
+ %res.0.reg2mem.1 = phi float [ 0.000000e+00, %entry ], [ %tmp14, %bb18 ] ; <float> [#uses=1]
+ ret float %res.0.reg2mem.1
+}
diff --git a/test/CodeGen/X86/2007-11-07-MulBy4.ll b/test/CodeGen/X86/2007-11-07-MulBy4.ll
new file mode 100644
index 0000000..d5b630b
--- /dev/null
+++ b/test/CodeGen/X86/2007-11-07-MulBy4.ll
@@ -0,0 +1,129 @@
+; RUN: llc < %s -march=x86 | not grep imul
+
+ %struct.eebb = type { %struct.eebb*, i16* }
+ %struct.hf = type { %struct.hf*, i16*, i8*, i32, i32, %struct.eebb*, i32, i32, i8*, i8*, i8*, i8*, i16*, i8*, i16*, %struct.ri, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [30 x i32], %struct.eebb, i32, i8* }
+ %struct.foo_data = type { i32, i32, i32, i32*, i32, i32, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i16*, i16*, i16*, i16*, i32, i32, i32, %struct.ri*, i8*, %struct.hf* }
+ %struct.ri = type { %struct.ri*, i32, i8*, i16*, i32*, i32 }
+
+define fastcc i32 @foo(i16* %eptr, i8* %ecode, %struct.foo_data* %md, i32 %ims) {
+entry:
+ %tmp36 = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp37 = icmp ult i32 0, %tmp36 ; <i1> [#uses=1]
+ br i1 %tmp37, label %cond_next79, label %cond_true
+
+cond_true: ; preds = %entry
+ ret i32 0
+
+cond_next79: ; preds = %entry
+ %tmp85 = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp86 = icmp ult i32 0, %tmp85 ; <i1> [#uses=1]
+ br i1 %tmp86, label %cond_next130, label %cond_true89
+
+cond_true89: ; preds = %cond_next79
+ ret i32 0
+
+cond_next130: ; preds = %cond_next79
+ %tmp173 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br i1 %tmp173, label %cond_next201, label %cond_true176
+
+cond_true176: ; preds = %cond_next130
+ ret i32 0
+
+cond_next201: ; preds = %cond_next130
+ switch i32 0, label %bb19955 [
+ i32 0, label %bb1266
+ i32 1, label %bb5018
+ i32 2, label %bb5075
+ i32 3, label %cond_true5534
+ i32 4, label %cond_true5534
+ i32 5, label %bb6039
+ i32 6, label %bb6181
+ i32 7, label %bb6323
+ i32 8, label %bb6463
+ i32 9, label %bb6605
+ i32 10, label %bb6746
+ i32 11, label %cond_next5871
+ i32 16, label %bb5452
+ i32 17, label %bb5395
+ i32 19, label %bb4883
+ i32 20, label %bb5136
+ i32 23, label %bb12899
+ i32 64, label %bb2162
+ i32 69, label %bb1447
+ i32 70, label %bb1737
+ i32 71, label %bb1447
+ i32 72, label %bb1737
+ i32 73, label %cond_true1984
+ i32 75, label %bb740
+ i32 80, label %bb552
+ ]
+
+bb552: ; preds = %cond_next201
+ ret i32 0
+
+bb740: ; preds = %cond_next201
+ ret i32 0
+
+bb1266: ; preds = %cond_next201
+ ret i32 0
+
+bb1447: ; preds = %cond_next201, %cond_next201
+ ret i32 0
+
+bb1737: ; preds = %cond_next201, %cond_next201
+ ret i32 0
+
+cond_true1984: ; preds = %cond_next201
+ ret i32 0
+
+bb2162: ; preds = %cond_next201
+ ret i32 0
+
+bb4883: ; preds = %cond_next201
+ ret i32 0
+
+bb5018: ; preds = %cond_next201
+ ret i32 0
+
+bb5075: ; preds = %cond_next201
+ ret i32 0
+
+bb5136: ; preds = %cond_next201
+ ret i32 0
+
+bb5395: ; preds = %cond_next201
+ ret i32 0
+
+bb5452: ; preds = %cond_next201
+ ret i32 0
+
+cond_true5534: ; preds = %cond_next201, %cond_next201
+ ret i32 0
+
+cond_next5871: ; preds = %cond_next201
+ ret i32 0
+
+bb6039: ; preds = %cond_next201
+ ret i32 0
+
+bb6181: ; preds = %cond_next201
+ ret i32 0
+
+bb6323: ; preds = %cond_next201
+ ret i32 0
+
+bb6463: ; preds = %cond_next201
+ ret i32 0
+
+bb6605: ; preds = %cond_next201
+ ret i32 0
+
+bb6746: ; preds = %cond_next201
+ ret i32 0
+
+bb12899: ; preds = %cond_next201
+ ret i32 0
+
+bb19955: ; preds = %cond_next201
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll b/test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll
new file mode 100644
index 0000000..9c004f9
--- /dev/null
+++ b/test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll
@@ -0,0 +1,68 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=att | grep movl | count 2
+; RUN: llc < %s -march=x86 -x86-asm-syntax=att | not grep movb
+
+ %struct.double_int = type { i64, i64 }
+ %struct.tree_common = type <{ i8, [3 x i8] }>
+ %struct.tree_int_cst = type { %struct.tree_common, %struct.double_int }
+ %struct.tree_node = type { %struct.tree_int_cst }
+@tree_code_type = external constant [0 x i32] ; <[0 x i32]*> [#uses=1]
+
+define i32 @simple_cst_equal(%struct.tree_node* %t1, %struct.tree_node* %t2) nounwind {
+entry:
+ %tmp2526 = bitcast %struct.tree_node* %t1 to i32* ; <i32*> [#uses=1]
+ br i1 false, label %UnifiedReturnBlock, label %bb21
+
+bb21: ; preds = %entry
+ %tmp27 = load i32* %tmp2526, align 4 ; <i32> [#uses=1]
+ %tmp29 = and i32 %tmp27, 255 ; <i32> [#uses=3]
+ %tmp2930 = trunc i32 %tmp29 to i8 ; <i8> [#uses=1]
+ %tmp37 = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp39 = and i32 %tmp37, 255 ; <i32> [#uses=2]
+ %tmp3940 = trunc i32 %tmp39 to i8 ; <i8> [#uses=1]
+ %tmp43 = add i32 %tmp29, -3 ; <i32> [#uses=1]
+ %tmp44 = icmp ult i32 %tmp43, 3 ; <i1> [#uses=1]
+ br i1 %tmp44, label %bb47.split, label %bb76
+
+bb47.split: ; preds = %bb21
+ ret i32 0
+
+bb76: ; preds = %bb21
+ br i1 false, label %bb82, label %bb146.split
+
+bb82: ; preds = %bb76
+ %tmp94 = getelementptr [0 x i32]* @tree_code_type, i32 0, i32 %tmp39 ; <i32*> [#uses=1]
+ %tmp95 = load i32* %tmp94, align 4 ; <i32> [#uses=1]
+ %tmp9596 = trunc i32 %tmp95 to i8 ; <i8> [#uses=1]
+ %tmp98 = add i8 %tmp9596, -4 ; <i8> [#uses=1]
+ %tmp99 = icmp ugt i8 %tmp98, 5 ; <i1> [#uses=1]
+ br i1 %tmp99, label %bb102, label %bb106
+
+bb102: ; preds = %bb82
+ ret i32 0
+
+bb106: ; preds = %bb82
+ ret i32 0
+
+bb146.split: ; preds = %bb76
+ %tmp149 = icmp eq i8 %tmp2930, %tmp3940 ; <i1> [#uses=1]
+ br i1 %tmp149, label %bb153, label %UnifiedReturnBlock
+
+bb153: ; preds = %bb146.split
+ switch i32 %tmp29, label %UnifiedReturnBlock [
+ i32 0, label %bb155
+ i32 1, label %bb187
+ ]
+
+bb155: ; preds = %bb153
+ ret i32 0
+
+bb187: ; preds = %bb153
+ %tmp198 = icmp eq %struct.tree_node* %t1, %t2 ; <i1> [#uses=1]
+ br i1 %tmp198, label %bb201, label %UnifiedReturnBlock
+
+bb201: ; preds = %bb187
+ ret i32 0
+
+UnifiedReturnBlock: ; preds = %bb187, %bb153, %bb146.split, %entry
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll b/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
new file mode 100644
index 0000000..721d4c9
--- /dev/null
+++ b/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
@@ -0,0 +1,86 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
+; Increment in loop bb.i28.i adjusted to 2, to prevent loop reversal from
+; kicking in.
+
+declare fastcc void @rdft(i32, i32, double*, i32*, double*)
+
+define fastcc void @mp_sqrt(i32 %n, i32 %radix, i32* %in, i32* %out, i32* %tmp1, i32* %tmp2, i32 %nfft, double* %tmp1fft, double* %tmp2fft, i32* %ip, double* %w) nounwind {
+entry:
+ br label %bb.i5
+
+bb.i5: ; preds = %bb.i5, %entry
+ %nfft_init.0.i = phi i32 [ 1, %entry ], [ %tmp7.i3, %bb.i5 ] ; <i32> [#uses=1]
+ %foo = phi i1 [1, %entry], [0, %bb.i5]
+ %tmp7.i3 = shl i32 %nfft_init.0.i, 1 ; <i32> [#uses=2]
+ br i1 %foo, label %bb.i5, label %mp_unexp_mp2d.exit.i
+
+mp_unexp_mp2d.exit.i: ; preds = %bb.i5
+ br i1 %foo, label %cond_next.i, label %cond_true.i
+
+cond_true.i: ; preds = %mp_unexp_mp2d.exit.i
+ ret void
+
+cond_next.i: ; preds = %mp_unexp_mp2d.exit.i
+ %tmp22.i = sdiv i32 0, 2 ; <i32> [#uses=2]
+ br i1 %foo, label %cond_true29.i, label %cond_next36.i
+
+cond_true29.i: ; preds = %cond_next.i
+ ret void
+
+cond_next36.i: ; preds = %cond_next.i
+ store i32 %tmp22.i, i32* null, align 4
+ %tmp8.i14.i = select i1 %foo, i32 1, i32 0 ; <i32> [#uses=1]
+ br label %bb.i28.i
+
+bb.i28.i: ; preds = %bb.i28.i, %cond_next36.i
+; CHECK: %bb.i28.i
+; CHECK: addl $2
+; CHECK: addl $2
+ %j.0.reg2mem.0.i16.i = phi i32 [ 0, %cond_next36.i ], [ %indvar.next39.i, %bb.i28.i ] ; <i32> [#uses=2]
+ %din_addr.1.reg2mem.0.i17.i = phi double [ 0.000000e+00, %cond_next36.i ], [ %tmp16.i25.i, %bb.i28.i ] ; <double> [#uses=1]
+ %tmp1.i18.i = fptosi double %din_addr.1.reg2mem.0.i17.i to i32 ; <i32> [#uses=2]
+ %tmp4.i19.i = icmp slt i32 %tmp1.i18.i, %radix ; <i1> [#uses=1]
+ %x.0.i21.i = select i1 %tmp4.i19.i, i32 %tmp1.i18.i, i32 0 ; <i32> [#uses=1]
+ %tmp41.sum.i = add i32 %j.0.reg2mem.0.i16.i, 2 ; <i32> [#uses=0]
+ %tmp1213.i23.i = sitofp i32 %x.0.i21.i to double ; <double> [#uses=1]
+ %tmp15.i24.i = fsub double 0.000000e+00, %tmp1213.i23.i ; <double> [#uses=1]
+ %tmp16.i25.i = fmul double 0.000000e+00, %tmp15.i24.i ; <double> [#uses=1]
+ %indvar.next39.i = add i32 %j.0.reg2mem.0.i16.i, 2 ; <i32> [#uses=2]
+ %exitcond40.i = icmp eq i32 %indvar.next39.i, %tmp8.i14.i ; <i1> [#uses=1]
+ br i1 %exitcond40.i, label %mp_unexp_d2mp.exit29.i, label %bb.i28.i
+
+mp_unexp_d2mp.exit29.i: ; preds = %bb.i28.i
+ %tmp46.i = sub i32 0, %tmp22.i ; <i32> [#uses=1]
+ store i32 %tmp46.i, i32* null, align 4
+ br i1 %exitcond40.i, label %bb.i.i, label %mp_sqrt_init.exit
+
+bb.i.i: ; preds = %bb.i.i, %mp_unexp_d2mp.exit29.i
+ br label %bb.i.i
+
+mp_sqrt_init.exit: ; preds = %mp_unexp_d2mp.exit29.i
+ tail call fastcc void @mp_mul_csqu( i32 0, double* %tmp1fft )
+ tail call fastcc void @rdft( i32 0, i32 -1, double* null, i32* %ip, double* %w )
+ tail call fastcc void @mp_mul_d2i( i32 0, i32 %radix, i32 0, double* %tmp1fft, i32* %tmp2 )
+ br i1 %exitcond40.i, label %cond_false.i, label %cond_true36.i
+
+cond_true36.i: ; preds = %mp_sqrt_init.exit
+ ret void
+
+cond_false.i: ; preds = %mp_sqrt_init.exit
+ tail call fastcc void @mp_round( i32 0, i32 %radix, i32 0, i32* %out )
+ tail call fastcc void @mp_add( i32 0, i32 %radix, i32* %tmp1, i32* %tmp2, i32* %tmp1 )
+ tail call fastcc void @mp_sub( i32 0, i32 %radix, i32* %in, i32* %tmp2, i32* %tmp2 )
+ tail call fastcc void @mp_round( i32 0, i32 %radix, i32 0, i32* %tmp1 )
+ tail call fastcc void @mp_mul_d2i( i32 0, i32 %radix, i32 %tmp7.i3, double* %tmp2fft, i32* %tmp2 )
+ ret void
+}
+
+declare fastcc void @mp_add(i32, i32, i32*, i32*, i32*)
+
+declare fastcc void @mp_sub(i32, i32, i32*, i32*, i32*)
+
+declare fastcc void @mp_round(i32, i32, i32, i32*)
+
+declare fastcc void @mp_mul_csqu(i32, double*)
+
+declare fastcc void @mp_mul_d2i(i32, i32, i32, double*, i32*)
diff --git a/test/CodeGen/X86/2007-12-11-FoldImpDefSpill.ll b/test/CodeGen/X86/2007-12-11-FoldImpDefSpill.ll
new file mode 100644
index 0000000..ca995cc
--- /dev/null
+++ b/test/CodeGen/X86/2007-12-11-FoldImpDefSpill.ll
@@ -0,0 +1,680 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin | not grep IMPLICIT_DEF
+
+ %struct.__sbuf = type { i8*, i32 }
+ %struct.ggBRDF = type { i32 (...)** }
+ %"struct.ggBST<ggMaterial>" = type { %"struct.ggBSTNode<ggMaterial>"*, i32 }
+ %"struct.ggBST<ggRasterSurfaceTexture>" = type { %"struct.ggBSTNode<ggRasterSurfaceTexture>"*, i32 }
+ %"struct.ggBST<ggSolidTexture>" = type { %"struct.ggBSTNode<ggSolidTexture>"*, i32 }
+ %"struct.ggBST<ggSpectrum>" = type { %"struct.ggBSTNode<ggSpectrum>"*, i32 }
+ %"struct.ggBST<mrObjectRecord>" = type { %"struct.ggBSTNode<mrObjectRecord>"*, i32 }
+ %"struct.ggBSTNode<ggMaterial>" = type { %"struct.ggBSTNode<ggMaterial>"*, %"struct.ggBSTNode<ggMaterial>"*, %struct.ggString, %struct.ggMaterial* }
+ %"struct.ggBSTNode<ggRasterSurfaceTexture>" = type { %"struct.ggBSTNode<ggRasterSurfaceTexture>"*, %"struct.ggBSTNode<ggRasterSurfaceTexture>"*, %struct.ggString, %struct.ggRasterSurfaceTexture* }
+ %"struct.ggBSTNode<ggSolidTexture>" = type { %"struct.ggBSTNode<ggSolidTexture>"*, %"struct.ggBSTNode<ggSolidTexture>"*, %struct.ggString, %struct.ggBRDF* }
+ %"struct.ggBSTNode<ggSpectrum>" = type { %"struct.ggBSTNode<ggSpectrum>"*, %"struct.ggBSTNode<ggSpectrum>"*, %struct.ggString, %struct.ggSpectrum* }
+ %"struct.ggBSTNode<mrObjectRecord>" = type { %"struct.ggBSTNode<mrObjectRecord>"*, %"struct.ggBSTNode<mrObjectRecord>"*, %struct.ggString, %struct.mrObjectRecord* }
+ %"struct.ggDictionary<ggMaterial>" = type { %"struct.ggBST<ggMaterial>" }
+ %"struct.ggDictionary<ggRasterSurfaceTexture>" = type { %"struct.ggBST<ggRasterSurfaceTexture>" }
+ %"struct.ggDictionary<ggSolidTexture>" = type { %"struct.ggBST<ggSolidTexture>" }
+ %"struct.ggDictionary<ggSpectrum>" = type { %"struct.ggBST<ggSpectrum>" }
+ %"struct.ggDictionary<mrObjectRecord>" = type { %"struct.ggBST<mrObjectRecord>" }
+ %struct.ggHAffineMatrix3 = type { %struct.ggHMatrix3 }
+ %struct.ggHBoxMatrix3 = type { %struct.ggHAffineMatrix3 }
+ %struct.ggHMatrix3 = type { [4 x [4 x double]] }
+ %struct.ggMaterial = type { i32 (...)**, %struct.ggBRDF* }
+ %struct.ggPoint3 = type { [3 x double] }
+ %"struct.ggRGBPixel<char>" = type { [3 x i8], i8 }
+ %"struct.ggRaster<ggRGBPixel<unsigned char> >" = type { i32, i32, %"struct.ggRGBPixel<char>"* }
+ %struct.ggRasterSurfaceTexture = type { %"struct.ggRaster<ggRGBPixel<unsigned char> >"* }
+ %struct.ggSolidNoise3 = type { i32, [256 x %struct.ggPoint3], [256 x i32] }
+ %struct.ggSpectrum = type { [8 x float] }
+ %struct.ggString = type { %"struct.ggString::StringRep"* }
+ %"struct.ggString::StringRep" = type { i32, i32, [1 x i8] }
+ %"struct.ggTrain<mrPixelRenderer*>" = type { %struct.ggBRDF**, i32, i32 }
+ %struct.mrObjectRecord = type { %struct.ggHBoxMatrix3, %struct.ggHBoxMatrix3, %struct.mrSurfaceList, %struct.ggMaterial*, i32, %struct.ggRasterSurfaceTexture*, %struct.ggBRDF*, i32, i32 }
+ %struct.mrScene = type { %struct.ggSpectrum, %struct.ggSpectrum, %struct.ggBRDF*, %struct.ggBRDF*, %struct.ggBRDF*, i32, double, %"struct.ggDictionary<mrObjectRecord>", %"struct.ggDictionary<ggRasterSurfaceTexture>", %"struct.ggDictionary<ggSolidTexture>", %"struct.ggDictionary<ggSpectrum>", %"struct.ggDictionary<ggMaterial>" }
+ %struct.mrSurfaceList = type { %struct.ggBRDF, %"struct.ggTrain<mrPixelRenderer*>" }
+ %"struct.std::__codecvt_abstract_base<char,char,__mbstate_t>" = type { %"struct.std::locale::facet" }
+ %"struct.std::basic_ios<char,std::char_traits<char> >" = type { %"struct.std::ios_base", %"struct.std::basic_ostream<char,std::char_traits<char> >"*, i8, i8, %"struct.std::basic_streambuf<char,std::char_traits<char> >"*, %"struct.std::ctype<char>"*, %"struct.std::__codecvt_abstract_base<char,char,__mbstate_t>"*, %"struct.std::__codecvt_abstract_base<char,char,__mbstate_t>"* }
+ %"struct.std::basic_istream<char,std::char_traits<char> >" = type { i32 (...)**, i32, %"struct.std::basic_ios<char,std::char_traits<char> >" }
+ %"struct.std::basic_ostream<char,std::char_traits<char> >" = type { i32 (...)**, %"struct.std::basic_ios<char,std::char_traits<char> >" }
+ %"struct.std::basic_streambuf<char,std::char_traits<char> >" = type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %"struct.std::locale" }
+ %"struct.std::ctype<char>" = type { %"struct.std::locale::facet", i32*, i8, i32*, i32*, i32*, i8, [256 x i8], [256 x i8], i8 }
+ %"struct.std::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, %"struct.std::ios_base::_Callback_list"*, %struct.__sbuf, [8 x %struct.__sbuf], i32, %struct.__sbuf*, %"struct.std::locale" }
+ %"struct.std::ios_base::_Callback_list" = type { %"struct.std::ios_base::_Callback_list"*, void (i32, %"struct.std::ios_base"*, i32)*, i32, i32 }
+ %"struct.std::locale" = type { %"struct.std::locale::_Impl"* }
+ %"struct.std::locale::_Impl" = type { i32, %"struct.std::locale::facet"**, i32, %"struct.std::locale::facet"**, i8** }
+ %"struct.std::locale::facet" = type { i32 (...)**, i32 }
[email protected] = external constant [7 x i8] ; <[7 x i8]*> [#uses=1]
[email protected] = external constant [11 x i8] ; <[11 x i8]*> [#uses=1]
+
+define fastcc void @_ZN7mrScene4ReadERSi(%struct.mrScene* %this, %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces) {
+entry:
+ %tmp6.i.i8288 = invoke i8* @_Znam( i32 12 )
+ to label %_ZN8ggStringC1Ei.exit unwind label %lpad ; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit: ; preds = %entry
+ %tmp6.i.i8995 = invoke i8* @_Znam( i32 12 )
+ to label %_ZN8ggStringC1Ei.exit96 unwind label %lpad3825 ; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit96: ; preds = %_ZN8ggStringC1Ei.exit
+ %tmp6.i.i97103 = invoke i8* @_Znam( i32 12 )
+ to label %_ZN8ggStringC1Ei.exit104 unwind label %lpad3829 ; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit104: ; preds = %_ZN8ggStringC1Ei.exit96
+ %tmp6.i.i105111 = invoke i8* @_Znam( i32 12 )
+ to label %_ZN8ggStringC1Ei.exit112 unwind label %lpad3833 ; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit112: ; preds = %_ZN8ggStringC1Ei.exit104
+ %tmp6.i.i122128 = invoke i8* @_Znam( i32 12 )
+ to label %_ZN8ggStringC1Ei.exit129 unwind label %lpad3837 ; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit129: ; preds = %_ZN8ggStringC1Ei.exit112
+ %tmp6.i.i132138 = invoke i8* @_Znam( i32 12 )
+ to label %_ZN8ggStringC1Ei.exit139 unwind label %lpad3841 ; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit139: ; preds = %_ZN8ggStringC1Ei.exit129
+ %tmp295 = invoke i8* @_Znwm( i32 16 )
+ to label %invcont294 unwind label %lpad3845 ; <i8*> [#uses=0]
+
+invcont294: ; preds = %_ZN8ggStringC1Ei.exit139
+ %tmp10.i.i141 = invoke i8* @_Znam( i32 16 )
+ to label %_ZN13mrSurfaceListC1Ev.exit unwind label %lpad3849 ; <i8*> [#uses=0]
+
+_ZN13mrSurfaceListC1Ev.exit: ; preds = %invcont294
+ %tmp3.i148 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+ to label %tmp3.i.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i.noexc: ; preds = %_ZN13mrSurfaceListC1Ev.exit
+ %tmp15.i149 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+ to label %tmp15.i.noexc unwind label %lpad3845 ; <i8*> [#uses=0]
+
+tmp15.i.noexc: ; preds = %tmp3.i.noexc
+ br i1 false, label %bb308, label %bb.i
+
+bb.i: ; preds = %tmp15.i.noexc
+ ret void
+
+bb308: ; preds = %tmp15.i.noexc
+ br i1 false, label %bb3743.preheader, label %bb315
+
+bb3743.preheader: ; preds = %bb308
+ %tmp16.i3862 = getelementptr %struct.ggPoint3* null, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %tmp16.i3859 = getelementptr %struct.ggPoint3* null, i32 0, i32 0, i32 0 ; <double*> [#uses=3]
+ br label %bb3743
+
+bb315: ; preds = %bb308
+ ret void
+
+bb333: ; preds = %invcont3758, %invcont335
+ %tmp3.i167180 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+ to label %tmp3.i167.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i167.noexc: ; preds = %bb333
+ %tmp15.i182 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+ to label %tmp15.i.noexc181 unwind label %lpad3845 ; <i8*> [#uses=0]
+
+tmp15.i.noexc181: ; preds = %tmp3.i167.noexc
+ br i1 false, label %invcont335, label %bb.i178
+
+bb.i178: ; preds = %tmp15.i.noexc181
+ ret void
+
+invcont335: ; preds = %tmp15.i.noexc181
+ br i1 false, label %bb3743, label %bb333
+
+bb345: ; preds = %invcont3758
+ br i1 false, label %bb353, label %bb360
+
+bb353: ; preds = %bb345
+ %tmp356 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null )
+ to label %bb3743 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+bb360: ; preds = %bb345
+ br i1 false, label %bb368, label %bb374
+
+bb368: ; preds = %bb360
+ %tmp373 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null )
+ to label %bb3743 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+bb374: ; preds = %bb360
+ br i1 false, label %bb396, label %bb421
+
+bb396: ; preds = %bb374
+ ret void
+
+bb421: ; preds = %bb374
+ br i1 false, label %bb429, label %bb530
+
+bb429: ; preds = %bb421
+ ret void
+
+bb530: ; preds = %bb421
+ br i1 false, label %bb538, label %bb673
+
+bb538: ; preds = %bb530
+ ret void
+
+bb673: ; preds = %bb530
+ br i1 false, label %bb681, label %bb778
+
+bb681: ; preds = %bb673
+ ret void
+
+bb778: ; preds = %bb673
+ br i1 false, label %bb786, label %bb891
+
+bb786: ; preds = %bb778
+ ret void
+
+bb891: ; preds = %bb778
+ br i1 false, label %bb899, label %bb998
+
+bb899: ; preds = %bb891
+ ret void
+
+bb998: ; preds = %bb891
+ br i1 false, label %bb1168, label %bb1190
+
+bb1168: ; preds = %bb998
+ ret void
+
+bb1190: ; preds = %bb998
+ br i1 false, label %bb1198, label %bb1220
+
+bb1198: ; preds = %bb1190
+ ret void
+
+bb1220: ; preds = %bb1190
+ br i1 false, label %bb1228, label %bb1250
+
+bb1228: ; preds = %bb1220
+ ret void
+
+bb1250: ; preds = %bb1220
+ br i1 false, label %bb1258, label %bb1303
+
+bb1258: ; preds = %bb1250
+ ret void
+
+bb1303: ; preds = %bb1250
+ br i1 false, label %bb1311, label %bb1366
+
+bb1311: ; preds = %bb1303
+ ret void
+
+bb1366: ; preds = %bb1303
+ br i1 false, label %bb1374, label %bb1432
+
+bb1374: ; preds = %bb1366
+ ret void
+
+bb1432: ; preds = %bb1366
+ br i1 false, label %bb1440, label %bb1495
+
+bb1440: ; preds = %bb1432
+ ret void
+
+bb1495: ; preds = %bb1432
+ br i1 false, label %bb1503, label %bb1561
+
+bb1503: ; preds = %bb1495
+ ret void
+
+bb1561: ; preds = %bb1495
+ br i1 false, label %bb1569, label %bb1624
+
+bb1569: ; preds = %bb1561
+ ret void
+
+bb1624: ; preds = %bb1561
+ br i1 false, label %bb1632, label %bb1654
+
+bb1632: ; preds = %bb1624
+ store double 0.000000e+00, double* %tmp16.i3859, align 8
+ %tmp3.i38383852 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+ to label %tmp3.i3838.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i3838.noexc: ; preds = %bb1632
+ %tmp15.i38473853 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+ to label %tmp15.i3847.noexc unwind label %lpad3845 ; <i8*> [#uses=0]
+
+tmp15.i3847.noexc: ; preds = %tmp3.i3838.noexc
+ br i1 false, label %invcont1634, label %bb.i3850
+
+bb.i3850: ; preds = %tmp15.i3847.noexc
+ ret void
+
+invcont1634: ; preds = %tmp15.i3847.noexc
+ %tmp3.i38173831 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+ to label %tmp3.i3817.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i3817.noexc: ; preds = %invcont1634
+ %tmp15.i38263832 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+ to label %tmp15.i3826.noexc unwind label %lpad3845 ; <i8*> [#uses=0]
+
+tmp15.i3826.noexc: ; preds = %tmp3.i3817.noexc
+ br i1 false, label %invcont1636, label %bb.i3829
+
+bb.i3829: ; preds = %tmp15.i3826.noexc
+ ret void
+
+invcont1636: ; preds = %tmp15.i3826.noexc
+ %tmp8.i38083811 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* %tmp16.i3862 )
+ to label %tmp8.i3808.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+tmp8.i3808.noexc: ; preds = %invcont1636
+ %tmp9.i38093812 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp8.i38083811, double* null )
+ to label %tmp9.i3809.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+tmp9.i3809.noexc: ; preds = %tmp8.i3808.noexc
+ %tmp10.i38103813 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp9.i38093812, double* null )
+ to label %invcont1638 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+invcont1638: ; preds = %tmp9.i3809.noexc
+ %tmp8.i37983801 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* %tmp16.i3859 )
+ to label %tmp8.i3798.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+tmp8.i3798.noexc: ; preds = %invcont1638
+ %tmp9.i37993802 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp8.i37983801, double* null )
+ to label %tmp9.i3799.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+tmp9.i3799.noexc: ; preds = %tmp8.i3798.noexc
+ %tmp10.i38003803 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp9.i37993802, double* null )
+ to label %invcont1640 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+invcont1640: ; preds = %tmp9.i3799.noexc
+ %tmp3.i3778 = load double* %tmp16.i3859, align 8 ; <double> [#uses=1]
+ %tmp1643 = invoke i8* @_Znwm( i32 76 )
+ to label %invcont1642 unwind label %lpad3845 ; <i8*> [#uses=0]
+
+invcont1642: ; preds = %invcont1640
+ %tmp18.i3770 = fsub double %tmp3.i3778, 0.000000e+00 ; <double> [#uses=0]
+ invoke fastcc void @_ZN7mrScene9AddObjectEP9mrSurfaceRK8ggStringS4_i( %struct.mrScene* %this, %struct.ggBRDF* null, %struct.ggString* null, %struct.ggString* null, i32 0 )
+ to label %bb3743 unwind label %lpad3845
+
+bb1654: ; preds = %bb1624
+ br i1 false, label %bb1662, label %bb1693
+
+bb1662: ; preds = %bb1654
+ %tmp3.i37143728 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+ to label %tmp3.i3714.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i3714.noexc: ; preds = %bb1662
+ %tmp15.i37233729 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+ to label %tmp15.i3723.noexc unwind label %lpad3845 ; <i8*> [#uses=0]
+
+tmp15.i3723.noexc: ; preds = %tmp3.i3714.noexc
+ ret void
+
+bb1693: ; preds = %bb1654
+ br i1 false, label %bb1701, label %bb1745
+
+bb1701: ; preds = %bb1693
+ %tmp3.i36493663 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+ to label %tmp3.i3649.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i3649.noexc: ; preds = %bb1701
+ ret void
+
+bb1745: ; preds = %bb1693
+ br i1 false, label %bb1753, label %bb1797
+
+bb1753: ; preds = %bb1745
+ ret void
+
+bb1797: ; preds = %bb1745
+ br i1 false, label %bb1805, label %bb1847
+
+bb1805: ; preds = %bb1797
+ ret void
+
+bb1847: ; preds = %bb1797
+ br i1 false, label %bb1855, label %bb1897
+
+bb1855: ; preds = %bb1847
+ %tmp3.i34633477 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+ to label %tmp3.i3463.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i3463.noexc: ; preds = %bb1855
+ %tmp15.i34723478 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+ to label %tmp15.i3472.noexc unwind label %lpad3845 ; <i8*> [#uses=0]
+
+tmp15.i3472.noexc: ; preds = %tmp3.i3463.noexc
+ br i1 false, label %invcont1857, label %bb.i3475
+
+bb.i3475: ; preds = %tmp15.i3472.noexc
+ invoke fastcc void @_ZN8ggStringaSEPKc( %struct.ggString* null, i8* null )
+ to label %invcont1857 unwind label %lpad3845
+
+invcont1857: ; preds = %bb.i3475, %tmp15.i3472.noexc
+ %tmp1860 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null )
+ to label %invcont1859 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+invcont1859: ; preds = %invcont1857
+ %tmp1862 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp1860, double* null )
+ to label %invcont1861 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+invcont1861: ; preds = %invcont1859
+ %tmp1864 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp1862, double* null )
+ to label %invcont1863 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+invcont1863: ; preds = %invcont1861
+ %tmp1866 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp1864, double* null )
+ to label %invcont1865 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+invcont1865: ; preds = %invcont1863
+ %tmp1868 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp1866, double* null )
+ to label %invcont1867 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+invcont1867: ; preds = %invcont1865
+ %tmp1881 = invoke i8 @_ZNKSt9basic_iosIcSt11char_traitsIcEE4goodEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) zeroext
+ to label %invcont1880 unwind label %lpad3845 ; <i8> [#uses=0]
+
+invcont1880: ; preds = %invcont1867
+ %tmp1883 = invoke i8* @_Znwm( i32 24 )
+ to label %invcont1882 unwind label %lpad3845 ; <i8*> [#uses=0]
+
+invcont1882: ; preds = %invcont1880
+ invoke fastcc void @_ZN7mrScene9AddObjectEP9mrSurfaceRK8ggStringS4_i( %struct.mrScene* %this, %struct.ggBRDF* null, %struct.ggString* null, %struct.ggString* null, i32 0 )
+ to label %bb3743 unwind label %lpad3845
+
+bb1897: ; preds = %bb1847
+ br i1 false, label %bb1905, label %bb1947
+
+bb1905: ; preds = %bb1897
+ ret void
+
+bb1947: ; preds = %bb1897
+ br i1 false, label %bb1955, label %bb2000
+
+bb1955: ; preds = %bb1947
+ ret void
+
+bb2000: ; preds = %bb1947
+ br i1 false, label %bb2008, label %bb2053
+
+bb2008: ; preds = %bb2000
+ ret void
+
+bb2053: ; preds = %bb2000
+ br i1 false, label %bb2061, label %bb2106
+
+bb2061: ; preds = %bb2053
+ %tmp3.i32433257 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+ to label %tmp3.i3243.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i3243.noexc: ; preds = %bb2061
+ %tmp15.i32523258 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+ to label %bb.i3255 unwind label %lpad3845 ; <i8*> [#uses=0]
+
+bb.i3255: ; preds = %tmp3.i3243.noexc
+ invoke fastcc void @_ZN8ggStringaSEPKc( %struct.ggString* null, i8* null )
+ to label %invcont2063 unwind label %lpad3845
+
+invcont2063: ; preds = %bb.i3255
+ ret void
+
+bb2106: ; preds = %bb2053
+ %tmp7.i3214 = call i32 @strcmp( i8* %tmp5.i161, i8* getelementptr ([7 x i8]* @.str80, i32 0, i32 0) ) nounwind readonly ; <i32> [#uses=0]
+ br i1 false, label %bb2114, label %bb2136
+
+bb2114: ; preds = %bb2106
+ %tmp3.i31923206 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+ to label %tmp3.i3192.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i3192.noexc: ; preds = %bb2114
+ %tmp15.i32013207 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+ to label %tmp15.i3201.noexc unwind label %lpad3845 ; <i8*> [#uses=0]
+
+tmp15.i3201.noexc: ; preds = %tmp3.i3192.noexc
+ br i1 false, label %invcont2116, label %bb.i3204
+
+bb.i3204: ; preds = %tmp15.i3201.noexc
+ ret void
+
+invcont2116: ; preds = %tmp15.i3201.noexc
+ %tmp3.i31713185 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+ to label %tmp3.i3171.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i3171.noexc: ; preds = %invcont2116
+ %tmp15.i31803186 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+ to label %tmp15.i3180.noexc unwind label %lpad3845 ; <i8*> [#uses=0]
+
+tmp15.i3180.noexc: ; preds = %tmp3.i3171.noexc
+ br i1 false, label %invcont2118, label %bb.i3183
+
+bb.i3183: ; preds = %tmp15.i3180.noexc
+ ret void
+
+invcont2118: ; preds = %tmp15.i3180.noexc
+ %tmp8.i31623165 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null )
+ to label %tmp8.i3162.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+tmp8.i3162.noexc: ; preds = %invcont2118
+ %tmp9.i31633166 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp8.i31623165, double* null )
+ to label %tmp9.i3163.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+tmp9.i3163.noexc: ; preds = %tmp8.i3162.noexc
+ %tmp10.i31643167 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp9.i31633166, double* null )
+ to label %invcont2120 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+invcont2120: ; preds = %tmp9.i3163.noexc
+ %tmp2123 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null )
+ to label %invcont2122 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+invcont2122: ; preds = %invcont2120
+ %tmp2125 = invoke i8* @_Znwm( i32 36 )
+ to label %invcont2124 unwind label %lpad3845 ; <i8*> [#uses=0]
+
+invcont2124: ; preds = %invcont2122
+ invoke fastcc void @_ZN7mrScene9AddObjectEP9mrSurfaceRK8ggStringS4_i( %struct.mrScene* %this, %struct.ggBRDF* null, %struct.ggString* null, %struct.ggString* null, i32 0 )
+ to label %bb3743 unwind label %lpad3845
+
+bb2136: ; preds = %bb2106
+ %tmp7.i3128 = call i32 @strcmp( i8* %tmp5.i161, i8* getelementptr ([11 x i8]* @.str81, i32 0, i32 0) ) nounwind readonly ; <i32> [#uses=0]
+ br i1 false, label %bb2144, label %bb3336
+
+bb2144: ; preds = %bb2136
+ %tmp6.i.i31173123 = invoke i8* @_Znam( i32 12 )
+ to label %_ZN8ggStringC1Ei.exit3124 unwind label %lpad3845 ; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit3124: ; preds = %bb2144
+ %tmp3.i30983112 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+ to label %tmp3.i3098.noexc unwind label %lpad3921 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i3098.noexc: ; preds = %_ZN8ggStringC1Ei.exit3124
+ %tmp15.i31073113 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+ to label %tmp15.i3107.noexc unwind label %lpad3921 ; <i8*> [#uses=0]
+
+tmp15.i3107.noexc: ; preds = %tmp3.i3098.noexc
+ br i1 false, label %invcont2147, label %bb.i3110
+
+bb.i3110: ; preds = %tmp15.i3107.noexc
+ ret void
+
+invcont2147: ; preds = %tmp15.i3107.noexc
+ %tmp2161 = invoke i8 @_ZNKSt9basic_iosIcSt11char_traitsIcEE4goodEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) zeroext
+ to label %invcont2160 unwind label %lpad3921 ; <i8> [#uses=0]
+
+invcont2160: ; preds = %invcont2147
+ %tmp4.i30933094 = invoke fastcc %struct.ggSpectrum* @_ZN5ggBSTI10ggSpectrumE4findERK8ggString3( %"struct.ggBSTNode<ggSpectrum>"* null, %struct.ggString* null )
+ to label %invcont2164 unwind label %lpad3921 ; <%struct.ggSpectrum*> [#uses=0]
+
+invcont2164: ; preds = %invcont2160
+ br i1 false, label %bb2170, label %bb2181
+
+bb2170: ; preds = %invcont2164
+ ret void
+
+bb2181: ; preds = %invcont2164
+ invoke fastcc void @_ZN8ggStringD1Ev( %struct.ggString* null )
+ to label %bb3743 unwind label %lpad3845
+
+bb3336: ; preds = %bb2136
+ br i1 false, label %bb3344, label %bb3734
+
+bb3344: ; preds = %bb3336
+ %tmp6.i.i773779 = invoke i8* @_Znam( i32 12 )
+ to label %_ZN8ggStringC1Ei.exit780 unwind label %lpad3845 ; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit780: ; preds = %bb3344
+ %tmp6.i.i765771 = invoke i8* @_Znam( i32 12 )
+ to label %_ZN8ggStringC1Ei.exit772 unwind label %lpad4025 ; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit772: ; preds = %_ZN8ggStringC1Ei.exit780
+ %tmp3.i746760 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+ to label %tmp3.i746.noexc unwind label %lpad4029 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i746.noexc: ; preds = %_ZN8ggStringC1Ei.exit772
+ %tmp15.i755761 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+ to label %tmp15.i755.noexc unwind label %lpad4029 ; <i8*> [#uses=0]
+
+tmp15.i755.noexc: ; preds = %tmp3.i746.noexc
+ br i1 false, label %invcont3348, label %bb.i758
+
+bb.i758: ; preds = %tmp15.i755.noexc
+ ret void
+
+invcont3348: ; preds = %tmp15.i755.noexc
+ %tmp3.i726740 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+ to label %tmp3.i726.noexc unwind label %lpad4029 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i726.noexc: ; preds = %invcont3348
+ %tmp15.i735741 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+ to label %tmp15.i735.noexc unwind label %lpad4029 ; <i8*> [#uses=0]
+
+tmp15.i735.noexc: ; preds = %tmp3.i726.noexc
+ br i1 false, label %bb3458, label %bb.i738
+
+bb.i738: ; preds = %tmp15.i735.noexc
+ ret void
+
+bb3458: ; preds = %tmp15.i735.noexc
+ br i1 false, label %bb3466, label %bb3491
+
+bb3466: ; preds = %bb3458
+ %tmp3469 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null )
+ to label %invcont3468 unwind label %lpad4029 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+invcont3468: ; preds = %bb3466
+ %tmp3471 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp3469, double* null )
+ to label %invcont3470 unwind label %lpad4029 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+invcont3470: ; preds = %invcont3468
+ %tmp3473 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERi( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp3471, i32* null )
+ to label %invcont3472 unwind label %lpad4029 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+invcont3472: ; preds = %invcont3470
+ %tmp3475 = invoke i8* @_Znwm( i32 7196 )
+ to label %invcont3474 unwind label %lpad4029 ; <i8*> [#uses=1]
+
+invcont3474: ; preds = %invcont3472
+ invoke fastcc void @_ZN13ggSolidNoise3C1Ev( %struct.ggSolidNoise3* null )
+ to label %_ZN22ggCoverageSolidTextureC1Eddi.exit unwind label %lpad4045
+
+_ZN22ggCoverageSolidTextureC1Eddi.exit: ; preds = %invcont3474
+ %tmp34823483 = bitcast i8* %tmp3475 to %struct.ggBRDF* ; <%struct.ggBRDF*> [#uses=2]
+ invoke fastcc void @_ZN5ggBSTI14ggSolidTextureE17InsertIntoSubtreeERK8ggStringPS0_RP9ggBSTNodeIS0_E( %"struct.ggBST<ggSolidTexture>"* null, %struct.ggString* null, %struct.ggBRDF* %tmp34823483, %"struct.ggBSTNode<ggSolidTexture>"** null )
+ to label %bb3662 unwind label %lpad4029
+
+bb3491: ; preds = %bb3458
+ ret void
+
+bb3662: ; preds = %_ZN22ggCoverageSolidTextureC1Eddi.exit
+ invoke fastcc void @_ZN8ggStringD1Ev( %struct.ggString* null )
+ to label %invcont3663 unwind label %lpad4025
+
+invcont3663: ; preds = %bb3662
+ invoke fastcc void @_ZN8ggStringD1Ev( %struct.ggString* null )
+ to label %bb3743 unwind label %lpad3845
+
+bb3734: ; preds = %bb3336
+ ret void
+
+bb3743: ; preds = %invcont3663, %bb2181, %invcont2124, %invcont1882, %invcont1642, %bb368, %bb353, %invcont335, %bb3743.preheader
+ %tex1.3 = phi %struct.ggBRDF* [ undef, %bb3743.preheader ], [ %tex1.3, %bb368 ], [ %tex1.3, %invcont1642 ], [ %tex1.3, %invcont1882 ], [ %tex1.3, %invcont2124 ], [ %tex1.3, %bb2181 ], [ %tex1.3, %invcont335 ], [ %tmp34823483, %invcont3663 ], [ %tex1.3, %bb353 ] ; <%struct.ggBRDF*> [#uses=7]
+ %tmp3.i312325 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+ to label %tmp3.i312.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i312.noexc: ; preds = %bb3743
+ %tmp15.i327 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+ to label %tmp15.i.noexc326 unwind label %lpad3845 ; <i8*> [#uses=0]
+
+tmp15.i.noexc326: ; preds = %tmp3.i312.noexc
+ br i1 false, label %invcont3745, label %bb.i323
+
+bb.i323: ; preds = %tmp15.i.noexc326
+ ret void
+
+invcont3745: ; preds = %tmp15.i.noexc326
+ %tmp3759 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+ to label %invcont3758 unwind label %lpad3845 ; <i8*> [#uses=0]
+
+invcont3758: ; preds = %invcont3745
+ %tmp5.i161 = getelementptr %"struct.ggString::StringRep"* null, i32 0, i32 2, i32 0 ; <i8*> [#uses=2]
+ br i1 false, label %bb333, label %bb345
+
+lpad: ; preds = %entry
+ ret void
+
+lpad3825: ; preds = %_ZN8ggStringC1Ei.exit
+ ret void
+
+lpad3829: ; preds = %_ZN8ggStringC1Ei.exit96
+ ret void
+
+lpad3833: ; preds = %_ZN8ggStringC1Ei.exit104
+ ret void
+
+lpad3837: ; preds = %_ZN8ggStringC1Ei.exit112
+ ret void
+
+lpad3841: ; preds = %_ZN8ggStringC1Ei.exit129
+ ret void
+
+lpad3845: ; preds = %invcont3745, %tmp3.i312.noexc, %bb3743, %invcont3663, %bb3344, %bb2181, %bb2144, %invcont2124, %invcont2122, %invcont2120, %tmp9.i3163.noexc, %tmp8.i3162.noexc, %invcont2118, %tmp3.i3171.noexc, %invcont2116, %tmp3.i3192.noexc, %bb2114, %bb.i3255, %tmp3.i3243.noexc, %bb2061, %invcont1882, %invcont1880, %invcont1867, %invcont1865, %invcont1863, %invcont1861, %invcont1859, %invcont1857, %bb.i3475, %tmp3.i3463.noexc, %bb1855, %bb1701, %tmp3.i3714.noexc, %bb1662, %invcont1642, %invcont1640, %tmp9.i3799.noexc, %tmp8.i3798.noexc, %invcont1638, %tmp9.i3809.noexc, %tmp8.i3808.noexc, %invcont1636, %tmp3.i3817.noexc, %invcont1634, %tmp3.i3838.noexc, %bb1632, %bb368, %bb353, %tmp3.i167.noexc, %bb333, %tmp3.i.noexc, %_ZN13mrSurfaceListC1Ev.exit, %_ZN8ggStringC1Ei.exit139
+ ret void
+
+lpad3849: ; preds = %invcont294
+ ret void
+
+lpad3921: ; preds = %invcont2160, %invcont2147, %tmp3.i3098.noexc, %_ZN8ggStringC1Ei.exit3124
+ ret void
+
+lpad4025: ; preds = %bb3662, %_ZN8ggStringC1Ei.exit780
+ ret void
+
+lpad4029: ; preds = %_ZN22ggCoverageSolidTextureC1Eddi.exit, %invcont3472, %invcont3470, %invcont3468, %bb3466, %tmp3.i726.noexc, %invcont3348, %tmp3.i746.noexc, %_ZN8ggStringC1Ei.exit772
+ ret void
+
+lpad4045: ; preds = %invcont3474
+ ret void
+}
+
+declare fastcc void @_ZN8ggStringD1Ev(%struct.ggString*)
+
+declare i8* @_Znam(i32)
+
+declare fastcc void @_ZN8ggStringaSEPKc(%struct.ggString*, i8*)
+
+declare i32 @strcmp(i8*, i8*) nounwind readonly
+
+declare %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERi(%"struct.std::basic_istream<char,std::char_traits<char> >"*, i32*)
+
+declare i8* @_Znwm(i32)
+
+declare i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv(%"struct.std::basic_ios<char,std::char_traits<char> >"*)
+
+declare %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd(%"struct.std::basic_istream<char,std::char_traits<char> >"*, double*)
+
+declare %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_(%"struct.std::basic_istream<char,std::char_traits<char> >"*, i8*)
+
+declare fastcc void @_ZN13ggSolidNoise3C1Ev(%struct.ggSolidNoise3*)
+
+declare i8 @_ZNKSt9basic_iosIcSt11char_traitsIcEE4goodEv(%"struct.std::basic_ios<char,std::char_traits<char> >"*) zeroext
+
+declare fastcc %struct.ggSpectrum* @_ZN5ggBSTI10ggSpectrumE4findERK8ggString3(%"struct.ggBSTNode<ggSpectrum>"*, %struct.ggString*)
+
+declare fastcc void @_ZN5ggBSTI14ggSolidTextureE17InsertIntoSubtreeERK8ggStringPS0_RP9ggBSTNodeIS0_E(%"struct.ggBST<ggSolidTexture>"*, %struct.ggString*, %struct.ggBRDF*, %"struct.ggBSTNode<ggSolidTexture>"**)
+
+declare fastcc void @_ZN7mrScene9AddObjectEP9mrSurfaceRK8ggStringS4_i(%struct.mrScene*, %struct.ggBRDF*, %struct.ggString*, %struct.ggString*, i32)
diff --git a/test/CodeGen/X86/2007-12-16-BURRSchedCrash.ll b/test/CodeGen/X86/2007-12-16-BURRSchedCrash.ll
new file mode 100644
index 0000000..455de91
--- /dev/null
+++ b/test/CodeGen/X86/2007-12-16-BURRSchedCrash.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu
+; PR1799
+
+ %struct.c34007g__designated___XUB = type { i32, i32, i32, i32 }
+ %struct.c34007g__pkg__parent = type { i32*, %struct.c34007g__designated___XUB* }
+
+define void @_ada_c34007g() {
+entry:
+ %x8 = alloca %struct.c34007g__pkg__parent, align 8 ; <%struct.c34007g__pkg__parent*> [#uses=2]
+ br i1 true, label %bb1271, label %bb848
+
+bb848: ; preds = %entry
+ ret void
+
+bb1271: ; preds = %bb898
+ %tmp1272 = getelementptr %struct.c34007g__pkg__parent* %x8, i32 0, i32 0 ; <i32**> [#uses=1]
+ %x82167 = bitcast %struct.c34007g__pkg__parent* %x8 to i64* ; <i64*> [#uses=1]
+ br i1 true, label %bb4668, label %bb848
+
+bb4668: ; preds = %bb4648
+ %tmp5464 = load i64* %x82167, align 8 ; <i64> [#uses=1]
+ %tmp5467 = icmp ne i64 0, %tmp5464 ; <i1> [#uses=1]
+ %tmp5470 = load i32** %tmp1272, align 8 ; <i32*> [#uses=1]
+ %tmp5471 = icmp eq i32* %tmp5470, null ; <i1> [#uses=1]
+ call fastcc void @c34007g__pkg__create.311( %struct.c34007g__pkg__parent* null, i32 7, i32 9, i32 2, i32 4, i32 1 )
+ %tmp5475 = or i1 %tmp5471, %tmp5467 ; <i1> [#uses=1]
+ %tmp5497 = or i1 %tmp5475, false ; <i1> [#uses=1]
+ br i1 %tmp5497, label %bb848, label %bb5507
+
+bb5507: ; preds = %bb4668
+ ret void
+
+}
+
+declare fastcc void @c34007g__pkg__create.311(%struct.c34007g__pkg__parent*, i32, i32, i32, i32, i32)
diff --git a/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll b/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll
new file mode 100644
index 0000000..265d968
--- /dev/null
+++ b/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=x86 | grep {(%esp)} | count 2
+; PR1872
+
+ %struct.c34007g__designated___XUB = type { i32, i32, i32, i32 }
+ %struct.c34007g__pkg__parent = type { i32*, %struct.c34007g__designated___XUB* }
+
+define void @_ada_c34007g() {
+entry:
+ %x8 = alloca %struct.c34007g__pkg__parent, align 8 ; <%struct.c34007g__pkg__parent*> [#uses=2]
+ %tmp1272 = getelementptr %struct.c34007g__pkg__parent* %x8, i32 0, i32 0 ; <i32**> [#uses=1]
+ %x82167 = bitcast %struct.c34007g__pkg__parent* %x8 to i64* ; <i64*> [#uses=1]
+ br i1 true, label %bb4668, label %bb848
+
+bb4668: ; preds = %bb4648
+ %tmp5464 = load i64* %x82167, align 8 ; <i64> [#uses=1]
+ %tmp5467 = icmp ne i64 0, %tmp5464 ; <i1> [#uses=1]
+ %tmp5470 = load i32** %tmp1272, align 8 ; <i32*> [#uses=1]
+ %tmp5471 = icmp eq i32* %tmp5470, null ; <i1> [#uses=1]
+ %tmp5475 = or i1 %tmp5471, %tmp5467 ; <i1> [#uses=1]
+ %tmp5497 = or i1 %tmp5475, false ; <i1> [#uses=1]
+ br i1 %tmp5497, label %bb848, label %bb5507
+
+bb848: ; preds = %entry
+ ret void
+
+bb5507: ; preds = %bb4668
+ ret void
+}
diff --git a/test/CodeGen/X86/2008-01-08-IllegalCMP.ll b/test/CodeGen/X86/2008-01-08-IllegalCMP.ll
new file mode 100644
index 0000000..7aec613
--- /dev/null
+++ b/test/CodeGen/X86/2008-01-08-IllegalCMP.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i686-pc-linux-gnu"
+
+define i64 @__absvdi2(i64 %a) nounwind {
+entry:
+ %w.0 = select i1 false, i64 0, i64 %a ; <i64> [#uses=2]
+ %tmp9 = icmp slt i64 %w.0, 0 ; <i1> [#uses=1]
+ br i1 %tmp9, label %bb12, label %bb13
+
+bb12: ; preds = %entry
+ unreachable
+
+bb13: ; preds = %entry
+ ret i64 %w.0
+}
diff --git a/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll b/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll
new file mode 100644
index 0000000..b040095
--- /dev/null
+++ b/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=x86 | not grep pushf
+
+ %struct.indexentry = type { i32, i8*, i8*, i8*, i8*, i8* }
+
+define i32 @_bfd_stab_section_find_nearest_line(i32 %offset) nounwind {
+entry:
+ %tmp910 = add i32 0, %offset ; <i32> [#uses=1]
+ br i1 true, label %bb951, label %bb917
+
+bb917: ; preds = %entry
+ ret i32 0
+
+bb951: ; preds = %bb986, %entry
+ %tmp955 = sdiv i32 0, 2 ; <i32> [#uses=3]
+ %tmp961 = getelementptr %struct.indexentry* null, i32 %tmp955, i32 0 ; <i32*> [#uses=1]
+ br i1 true, label %bb986, label %bb967
+
+bb967: ; preds = %bb951
+ ret i32 0
+
+bb986: ; preds = %bb951
+ %tmp993 = load i32* %tmp961, align 4 ; <i32> [#uses=1]
+ %tmp995 = icmp ugt i32 %tmp993, %tmp910 ; <i1> [#uses=2]
+ %tmp1002 = add i32 %tmp955, 1 ; <i32> [#uses=1]
+ %low.0 = select i1 %tmp995, i32 0, i32 %tmp1002 ; <i32> [#uses=1]
+ %high.0 = select i1 %tmp995, i32 %tmp955, i32 0 ; <i32> [#uses=1]
+ %tmp1006 = icmp eq i32 %low.0, %high.0 ; <i1> [#uses=1]
+ br i1 %tmp1006, label %UnifiedReturnBlock, label %bb951
+
+UnifiedReturnBlock: ; preds = %bb986
+ ret i32 1
+}
diff --git a/test/CodeGen/X86/2008-01-09-LongDoubleSin.ll b/test/CodeGen/X86/2008-01-09-LongDoubleSin.ll
new file mode 100644
index 0000000..6997d53
--- /dev/null
+++ b/test/CodeGen/X86/2008-01-09-LongDoubleSin.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -o - | grep sinl
+
+target triple = "i686-pc-linux-gnu"
+
+define x86_fp80 @f(x86_fp80 %x) nounwind {
+entry:
+ %tmp2 = tail call x86_fp80 @sinl( x86_fp80 %x ) nounwind readonly ; <x86_fp80> [#uses=1]
+ ret x86_fp80 %tmp2
+}
+
+declare x86_fp80 @sinl(x86_fp80) nounwind readonly
diff --git a/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll b/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll
new file mode 100644
index 0000000..d795610
--- /dev/null
+++ b/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -regalloc=local
+
+define void @SolveCubic(double %a, double %b, double %c, double %d, i32* %solutions, double* %x) {
+entry:
+ %tmp71 = load x86_fp80* null, align 16 ; <x86_fp80> [#uses=1]
+ %tmp72 = fdiv x86_fp80 %tmp71, 0xKC000C000000000000000 ; <x86_fp80> [#uses=1]
+ %tmp73 = fadd x86_fp80 0xK00000000000000000000, %tmp72 ; <x86_fp80> [#uses=1]
+ %tmp7374 = fptrunc x86_fp80 %tmp73 to double ; <double> [#uses=1]
+ store double %tmp7374, double* null, align 8
+ %tmp81 = load double* null, align 8 ; <double> [#uses=1]
+ %tmp82 = fadd double %tmp81, 0x401921FB54442D18 ; <double> [#uses=1]
+ %tmp83 = fdiv double %tmp82, 3.000000e+00 ; <double> [#uses=1]
+ %tmp84 = call double @cos( double %tmp83 ) ; <double> [#uses=1]
+ %tmp85 = fmul double 0.000000e+00, %tmp84 ; <double> [#uses=1]
+ %tmp8586 = fpext double %tmp85 to x86_fp80 ; <x86_fp80> [#uses=1]
+ %tmp87 = load x86_fp80* null, align 16 ; <x86_fp80> [#uses=1]
+ %tmp88 = fdiv x86_fp80 %tmp87, 0xKC000C000000000000000 ; <x86_fp80> [#uses=1]
+ %tmp89 = fadd x86_fp80 %tmp8586, %tmp88 ; <x86_fp80> [#uses=1]
+ %tmp8990 = fptrunc x86_fp80 %tmp89 to double ; <double> [#uses=1]
+ store double %tmp8990, double* null, align 8
+ %tmp97 = load double* null, align 8 ; <double> [#uses=1]
+ %tmp98 = fadd double %tmp97, 0x402921FB54442D18 ; <double> [#uses=1]
+ %tmp99 = fdiv double %tmp98, 3.000000e+00 ; <double> [#uses=1]
+ %tmp100 = call double @cos( double %tmp99 ) ; <double> [#uses=1]
+ %tmp101 = fmul double 0.000000e+00, %tmp100 ; <double> [#uses=1]
+ %tmp101102 = fpext double %tmp101 to x86_fp80 ; <x86_fp80> [#uses=1]
+ %tmp103 = load x86_fp80* null, align 16 ; <x86_fp80> [#uses=1]
+ %tmp104 = fdiv x86_fp80 %tmp103, 0xKC000C000000000000000 ; <x86_fp80> [#uses=1]
+ %tmp105 = fadd x86_fp80 %tmp101102, %tmp104 ; <x86_fp80> [#uses=1]
+ %tmp105106 = fptrunc x86_fp80 %tmp105 to double ; <double> [#uses=1]
+ store double %tmp105106, double* null, align 8
+ ret void
+}
+
+declare double @cos(double)
diff --git a/test/CodeGen/X86/2008-01-16-InvalidDAGCombineXform.ll b/test/CodeGen/X86/2008-01-16-InvalidDAGCombineXform.ll
new file mode 100644
index 0000000..e91f52e
--- /dev/null
+++ b/test/CodeGen/X86/2008-01-16-InvalidDAGCombineXform.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=x86 | not grep IMPLICIT_DEF
+
+ %struct.node_t = type { double*, %struct.node_t*, %struct.node_t**, double**, double*, i32, i32 }
+
+define void @localize_local_bb19_bb(%struct.node_t** %cur_node) {
+newFuncRoot:
+ %tmp1 = load %struct.node_t** %cur_node, align 4 ; <%struct.node_t*> [#uses=1]
+ %tmp2 = getelementptr %struct.node_t* %tmp1, i32 0, i32 4 ; <double**> [#uses=1]
+ %tmp3 = load double** %tmp2, align 4 ; <double*> [#uses=1]
+ %tmp4 = load %struct.node_t** %cur_node, align 4 ; <%struct.node_t*> [#uses=1]
+ %tmp5 = getelementptr %struct.node_t* %tmp4, i32 0, i32 4 ; <double**> [#uses=1]
+ store double* %tmp3, double** %tmp5, align 4
+ %tmp6 = load %struct.node_t** %cur_node, align 4 ; <%struct.node_t*> [#uses=1]
+ %tmp7 = getelementptr %struct.node_t* %tmp6, i32 0, i32 3 ; <double***> [#uses=1]
+ %tmp8 = load double*** %tmp7, align 4 ; <double**> [#uses=1]
+ %tmp9 = load %struct.node_t** %cur_node, align 4 ; <%struct.node_t*> [#uses=1]
+ %tmp10 = getelementptr %struct.node_t* %tmp9, i32 0, i32 3 ; <double***> [#uses=1]
+ store double** %tmp8, double*** %tmp10, align 4
+ %tmp11 = load %struct.node_t** %cur_node, align 4 ; <%struct.node_t*> [#uses=1]
+ %tmp12 = getelementptr %struct.node_t* %tmp11, i32 0, i32 0 ; <double**> [#uses=1]
+ %tmp13 = load double** %tmp12, align 4 ; <double*> [#uses=1]
+ %tmp14 = load %struct.node_t** %cur_node, align 4 ; <%struct.node_t*> [#uses=1]
+ %tmp15 = getelementptr %struct.node_t* %tmp14, i32 0, i32 0 ; <double**> [#uses=1]
+ store double* %tmp13, double** %tmp15, align 4
+ %tmp16 = load %struct.node_t** %cur_node, align 4 ; <%struct.node_t*> [#uses=1]
+ %tmp17 = getelementptr %struct.node_t* %tmp16, i32 0, i32 1 ; <%struct.node_t**> [#uses=1]
+ %tmp18 = load %struct.node_t** %tmp17, align 4 ; <%struct.node_t*> [#uses=1]
+ store %struct.node_t* %tmp18, %struct.node_t** %cur_node, align 4
+ ret void
+}
diff --git a/test/CodeGen/X86/2008-01-16-Trampoline.ll b/test/CodeGen/X86/2008-01-16-Trampoline.ll
new file mode 100644
index 0000000..704b2ba
--- /dev/null
+++ b/test/CodeGen/X86/2008-01-16-Trampoline.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86-64
+
+ %struct.FRAME.gnat__perfect_hash_generators__select_char_position__build_identical_keys_sets = type { i32, i32, void (i32, i32)*, i8 (i32, i32)* }
+
+define fastcc i32 @gnat__perfect_hash_generators__select_char_position__build_identical_keys_sets.5146(i64 %table.0.0, i64 %table.0.1, i32 %last, i32 %pos) {
+entry:
+ %tramp22 = call i8* @llvm.init.trampoline( i8* null, i8* bitcast (void (%struct.FRAME.gnat__perfect_hash_generators__select_char_position__build_identical_keys_sets*, i32, i32)* @gnat__perfect_hash_generators__select_char_position__build_identical_keys_sets__move.5177 to i8*), i8* null ) ; <i8*> [#uses=0]
+ unreachable
+}
+
+declare void @gnat__perfect_hash_generators__select_char_position__build_identical_keys_sets__move.5177(%struct.FRAME.gnat__perfect_hash_generators__select_char_position__build_identical_keys_sets* nest , i32, i32) nounwind
+
+declare i8* @llvm.init.trampoline(i8*, i8*, i8*) nounwind
diff --git a/test/CodeGen/X86/2008-01-25-EmptyFunction.ll b/test/CodeGen/X86/2008-01-25-EmptyFunction.ll
new file mode 100644
index 0000000..387645f
--- /dev/null
+++ b/test/CodeGen/X86/2008-01-25-EmptyFunction.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 | grep {.byte 0}
+target triple = "i686-apple-darwin8"
+
+
+define void @bork() noreturn nounwind {
+entry:
+ unreachable
+}
diff --git a/test/CodeGen/X86/2008-02-05-ISelCrash.ll b/test/CodeGen/X86/2008-02-05-ISelCrash.ll
new file mode 100644
index 0000000..443a32d
--- /dev/null
+++ b/test/CodeGen/X86/2008-02-05-ISelCrash.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86
+; PR1975
+
+@nodes = external global i64 ; <i64*> [#uses=2]
+
+define fastcc i32 @ab(i32 %alpha, i32 %beta) nounwind {
+entry:
+ %tmp1 = load i64* @nodes, align 8 ; <i64> [#uses=1]
+ %tmp2 = add i64 %tmp1, 1 ; <i64> [#uses=1]
+ store i64 %tmp2, i64* @nodes, align 8
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll b/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll
new file mode 100644
index 0000000..d2d5149
--- /dev/null
+++ b/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep xor | grep CPI
+
+define void @casin({ double, double }* sret %agg.result, double %z.0, double %z.1) nounwind {
+entry:
+ %memtmp = alloca { double, double }, align 8 ; <{ double, double }*> [#uses=3]
+ %tmp4 = fsub double -0.000000e+00, %z.1 ; <double> [#uses=1]
+ call void @casinh( { double, double }* sret %memtmp, double %tmp4, double %z.0 ) nounwind
+ %tmp19 = getelementptr { double, double }* %memtmp, i32 0, i32 0 ; <double*> [#uses=1]
+ %tmp20 = load double* %tmp19, align 8 ; <double> [#uses=1]
+ %tmp22 = getelementptr { double, double }* %memtmp, i32 0, i32 1 ; <double*> [#uses=1]
+ %tmp23 = load double* %tmp22, align 8 ; <double> [#uses=1]
+ %tmp32 = fsub double -0.000000e+00, %tmp20 ; <double> [#uses=1]
+ %tmp37 = getelementptr { double, double }* %agg.result, i32 0, i32 0 ; <double*> [#uses=1]
+ store double %tmp23, double* %tmp37, align 8
+ %tmp40 = getelementptr { double, double }* %agg.result, i32 0, i32 1 ; <double*> [#uses=1]
+ store double %tmp32, double* %tmp40, align 8
+ ret void
+}
+
+declare void @casinh({ double, double }* sret , double, double) nounwind
diff --git a/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll b/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll
new file mode 100644
index 0000000..b772d77
--- /dev/null
+++ b/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll
@@ -0,0 +1,99 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep andpd | not grep esp
+
+declare double @llvm.sqrt.f64(double) nounwind readnone
+
+declare fastcc void @ApplyGivens(double**, double, double, i32, i32, i32, i32) nounwind
+
+declare double @fabs(double)
+
+define void @main_bb114_2E_outer_2E_i_bb3_2E_i27(double** %tmp12.sub.i.i, [51 x double*]* %tmp12.i.i.i, i32 %i.0.reg2mem.0.ph.i, i32 %tmp11688.i, i32 %tmp19.i, i32 %tmp24.i, [51 x double*]* %tmp12.i.i) {
+newFuncRoot:
+ br label %bb3.i27
+
+bb111.i77.bb121.i_crit_edge.exitStub: ; preds = %bb111.i77
+ ret void
+
+bb3.i27: ; preds = %bb111.i77.bb3.i27_crit_edge, %newFuncRoot
+ %indvar94.i = phi i32 [ 0, %newFuncRoot ], [ %tmp113.i76, %bb111.i77.bb3.i27_crit_edge ] ; <i32> [#uses=6]
+ %tmp6.i20 = getelementptr [51 x double*]* %tmp12.i.i, i32 0, i32 %indvar94.i ; <double**> [#uses=1]
+ %tmp7.i21 = load double** %tmp6.i20, align 4 ; <double*> [#uses=2]
+ %tmp10.i = add i32 %indvar94.i, %i.0.reg2mem.0.ph.i ; <i32> [#uses=5]
+ %tmp11.i22 = getelementptr double* %tmp7.i21, i32 %tmp10.i ; <double*> [#uses=1]
+ %tmp12.i23 = load double* %tmp11.i22, align 8 ; <double> [#uses=4]
+ %tmp20.i24 = add i32 %tmp19.i, %indvar94.i ; <i32> [#uses=3]
+ %tmp21.i = getelementptr double* %tmp7.i21, i32 %tmp20.i24 ; <double*> [#uses=1]
+ %tmp22.i25 = load double* %tmp21.i, align 8 ; <double> [#uses=3]
+ %tmp1.i.i26 = fcmp oeq double %tmp12.i23, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %tmp1.i.i26, label %bb3.i27.Givens.exit.i49_crit_edge, label %bb5.i.i31
+
+bb5.i.i31: ; preds = %bb3.i27
+ %tmp7.i.i28 = call double @fabs( double %tmp12.i23 ) nounwind ; <double> [#uses=1]
+ %tmp9.i.i29 = call double @fabs( double %tmp22.i25 ) nounwind ; <double> [#uses=1]
+ %tmp10.i.i30 = fcmp ogt double %tmp7.i.i28, %tmp9.i.i29 ; <i1> [#uses=1]
+ br i1 %tmp10.i.i30, label %bb13.i.i37, label %bb30.i.i43
+
+bb13.i.i37: ; preds = %bb5.i.i31
+ %tmp15.i.i32 = fsub double -0.000000e+00, %tmp22.i25 ; <double> [#uses=1]
+ %tmp17.i.i33 = fdiv double %tmp15.i.i32, %tmp12.i23 ; <double> [#uses=3]
+ %tmp20.i4.i = fmul double %tmp17.i.i33, %tmp17.i.i33 ; <double> [#uses=1]
+ %tmp21.i.i34 = fadd double %tmp20.i4.i, 1.000000e+00 ; <double> [#uses=1]
+ %tmp22.i.i35 = call double @llvm.sqrt.f64( double %tmp21.i.i34 ) nounwind ; <double> [#uses=1]
+ %tmp23.i5.i = fdiv double 1.000000e+00, %tmp22.i.i35 ; <double> [#uses=2]
+ %tmp28.i.i36 = fmul double %tmp23.i5.i, %tmp17.i.i33 ; <double> [#uses=1]
+ br label %Givens.exit.i49
+
+bb30.i.i43: ; preds = %bb5.i.i31
+ %tmp32.i.i38 = fsub double -0.000000e+00, %tmp12.i23 ; <double> [#uses=1]
+ %tmp34.i.i39 = fdiv double %tmp32.i.i38, %tmp22.i25 ; <double> [#uses=3]
+ %tmp37.i6.i = fmul double %tmp34.i.i39, %tmp34.i.i39 ; <double> [#uses=1]
+ %tmp38.i.i40 = fadd double %tmp37.i6.i, 1.000000e+00 ; <double> [#uses=1]
+ %tmp39.i7.i = call double @llvm.sqrt.f64( double %tmp38.i.i40 ) nounwind ; <double> [#uses=1]
+ %tmp40.i.i41 = fdiv double 1.000000e+00, %tmp39.i7.i ; <double> [#uses=2]
+ %tmp45.i.i42 = fmul double %tmp40.i.i41, %tmp34.i.i39 ; <double> [#uses=1]
+ br label %Givens.exit.i49
+
+Givens.exit.i49: ; preds = %bb3.i27.Givens.exit.i49_crit_edge, %bb30.i.i43, %bb13.i.i37
+ %s.0.i44 = phi double [ %tmp45.i.i42, %bb30.i.i43 ], [ %tmp23.i5.i, %bb13.i.i37 ], [ 0.000000e+00, %bb3.i27.Givens.exit.i49_crit_edge ] ; <double> [#uses=2]
+ %c.0.i45 = phi double [ %tmp40.i.i41, %bb30.i.i43 ], [ %tmp28.i.i36, %bb13.i.i37 ], [ 1.000000e+00, %bb3.i27.Givens.exit.i49_crit_edge ] ; <double> [#uses=2]
+ %tmp26.i46 = add i32 %tmp24.i, %indvar94.i ; <i32> [#uses=2]
+ %tmp27.i47 = icmp slt i32 %tmp26.i46, 51 ; <i1> [#uses=1]
+ %min.i48 = select i1 %tmp27.i47, i32 %tmp26.i46, i32 50 ; <i32> [#uses=1]
+ call fastcc void @ApplyGivens( double** %tmp12.sub.i.i, double %s.0.i44, double %c.0.i45, i32 %tmp20.i24, i32 %tmp10.i, i32 %indvar94.i, i32 %min.i48 ) nounwind
+ br label %codeRepl
+
+codeRepl: ; preds = %Givens.exit.i49
+ call void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb_2E_i48_2E_i( i32 %tmp10.i, i32 %tmp20.i24, double %s.0.i44, double %c.0.i45, [51 x double*]* %tmp12.i.i.i )
+ br label %ApplyRGivens.exit49.i
+
+ApplyRGivens.exit49.i: ; preds = %codeRepl
+ %tmp10986.i = icmp sgt i32 %tmp11688.i, %tmp10.i ; <i1> [#uses=1]
+ br i1 %tmp10986.i, label %ApplyRGivens.exit49.i.bb52.i57_crit_edge, label %ApplyRGivens.exit49.i.bb111.i77_crit_edge
+
+codeRepl1: ; preds = %ApplyRGivens.exit49.i.bb52.i57_crit_edge
+ call void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb52_2E_i57( i32 %tmp10.i, double** %tmp12.sub.i.i, [51 x double*]* %tmp12.i.i.i, i32 %i.0.reg2mem.0.ph.i, i32 %tmp11688.i, i32 %tmp19.i, i32 %tmp24.i, [51 x double*]* %tmp12.i.i )
+ br label %bb105.i.bb111.i77_crit_edge
+
+bb111.i77: ; preds = %bb105.i.bb111.i77_crit_edge, %ApplyRGivens.exit49.i.bb111.i77_crit_edge
+ %tmp113.i76 = add i32 %indvar94.i, 1 ; <i32> [#uses=2]
+ %tmp118.i = icmp sgt i32 %tmp11688.i, %tmp113.i76 ; <i1> [#uses=1]
+ br i1 %tmp118.i, label %bb111.i77.bb3.i27_crit_edge, label %bb111.i77.bb121.i_crit_edge.exitStub
+
+bb3.i27.Givens.exit.i49_crit_edge: ; preds = %bb3.i27
+ br label %Givens.exit.i49
+
+ApplyRGivens.exit49.i.bb52.i57_crit_edge: ; preds = %ApplyRGivens.exit49.i
+ br label %codeRepl1
+
+ApplyRGivens.exit49.i.bb111.i77_crit_edge: ; preds = %ApplyRGivens.exit49.i
+ br label %bb111.i77
+
+bb105.i.bb111.i77_crit_edge: ; preds = %codeRepl1
+ br label %bb111.i77
+
+bb111.i77.bb3.i27_crit_edge: ; preds = %bb111.i77
+ br label %bb3.i27
+}
+
+declare void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb_2E_i48_2E_i(i32, i32, double, double, [51 x double*]*)
+
+declare void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb52_2E_i57(i32, double**, [51 x double*]*, i32, i32, i32, i32, [51 x double*]*)
diff --git a/test/CodeGen/X86/2008-02-14-BitMiscompile.ll b/test/CodeGen/X86/2008-02-14-BitMiscompile.ll
new file mode 100644
index 0000000..1983f1d
--- /dev/null
+++ b/test/CodeGen/X86/2008-02-14-BitMiscompile.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 | grep and
+define i32 @test(i1 %A) {
+ %B = zext i1 %A to i32 ; <i32> [#uses=1]
+ %C = sub i32 0, %B ; <i32> [#uses=1]
+ %D = and i32 %C, 255 ; <i32> [#uses=1]
+ ret i32 %D
+}
+
diff --git a/test/CodeGen/X86/2008-02-18-TailMergingBug.ll b/test/CodeGen/X86/2008-02-18-TailMergingBug.ll
new file mode 100644
index 0000000..7463a0e
--- /dev/null
+++ b/test/CodeGen/X86/2008-02-18-TailMergingBug.ll
@@ -0,0 +1,219 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah -stats |& grep {Number of block tails merged} | grep 9
+; PR1909
+
[email protected] = internal constant [48 x i8] c"transformed bounds: (%.2f, %.2f), (%.2f, %.2f)\0A\00" ; <[48 x i8]*> [#uses=1]
+
+define void @minmax(float* %result) nounwind optsize {
+entry:
+ %tmp2 = load float* %result, align 4 ; <float> [#uses=6]
+ %tmp4 = getelementptr float* %result, i32 2 ; <float*> [#uses=5]
+ %tmp5 = load float* %tmp4, align 4 ; <float> [#uses=10]
+ %tmp7 = getelementptr float* %result, i32 4 ; <float*> [#uses=5]
+ %tmp8 = load float* %tmp7, align 4 ; <float> [#uses=8]
+ %tmp10 = getelementptr float* %result, i32 6 ; <float*> [#uses=3]
+ %tmp11 = load float* %tmp10, align 4 ; <float> [#uses=8]
+ %tmp12 = fcmp olt float %tmp8, %tmp11 ; <i1> [#uses=5]
+ br i1 %tmp12, label %bb, label %bb21
+
+bb: ; preds = %entry
+ %tmp23469 = fcmp olt float %tmp5, %tmp8 ; <i1> [#uses=1]
+ br i1 %tmp23469, label %bb26, label %bb30
+
+bb21: ; preds = %entry
+ %tmp23 = fcmp olt float %tmp5, %tmp11 ; <i1> [#uses=1]
+ br i1 %tmp23, label %bb26, label %bb30
+
+bb26: ; preds = %bb21, %bb
+ %tmp52471 = fcmp olt float %tmp2, %tmp5 ; <i1> [#uses=1]
+ br i1 %tmp52471, label %bb111, label %bb59
+
+bb30: ; preds = %bb21, %bb
+ br i1 %tmp12, label %bb40, label %bb50
+
+bb40: ; preds = %bb30
+ %tmp52473 = fcmp olt float %tmp2, %tmp8 ; <i1> [#uses=1]
+ br i1 %tmp52473, label %bb111, label %bb59
+
+bb50: ; preds = %bb30
+ %tmp52 = fcmp olt float %tmp2, %tmp11 ; <i1> [#uses=1]
+ br i1 %tmp52, label %bb111, label %bb59
+
+bb59: ; preds = %bb50, %bb40, %bb26
+ br i1 %tmp12, label %bb72, label %bb80
+
+bb72: ; preds = %bb59
+ %tmp82475 = fcmp olt float %tmp5, %tmp8 ; <i1> [#uses=2]
+ %brmerge786 = or i1 %tmp82475, %tmp12 ; <i1> [#uses=1]
+ %tmp4.mux787 = select i1 %tmp82475, float* %tmp4, float* %tmp7 ; <float*> [#uses=1]
+ br i1 %brmerge786, label %bb111, label %bb103
+
+bb80: ; preds = %bb59
+ %tmp82 = fcmp olt float %tmp5, %tmp11 ; <i1> [#uses=2]
+ %brmerge = or i1 %tmp82, %tmp12 ; <i1> [#uses=1]
+ %tmp4.mux = select i1 %tmp82, float* %tmp4, float* %tmp7 ; <float*> [#uses=1]
+ br i1 %brmerge, label %bb111, label %bb103
+
+bb103: ; preds = %bb80, %bb72
+ br label %bb111
+
+bb111: ; preds = %bb103, %bb80, %bb72, %bb50, %bb40, %bb26
+ %iftmp.0.0.in = phi float* [ %tmp10, %bb103 ], [ %result, %bb26 ], [ %result, %bb40 ], [ %result, %bb50 ], [ %tmp4.mux, %bb80 ], [ %tmp4.mux787, %bb72 ] ; <float*> [#uses=1]
+ %iftmp.0.0 = load float* %iftmp.0.0.in ; <float> [#uses=1]
+ %tmp125 = fcmp ogt float %tmp8, %tmp11 ; <i1> [#uses=5]
+ br i1 %tmp125, label %bb128, label %bb136
+
+bb128: ; preds = %bb111
+ %tmp138477 = fcmp ogt float %tmp5, %tmp8 ; <i1> [#uses=1]
+ br i1 %tmp138477, label %bb141, label %bb145
+
+bb136: ; preds = %bb111
+ %tmp138 = fcmp ogt float %tmp5, %tmp11 ; <i1> [#uses=1]
+ br i1 %tmp138, label %bb141, label %bb145
+
+bb141: ; preds = %bb136, %bb128
+ %tmp167479 = fcmp ogt float %tmp2, %tmp5 ; <i1> [#uses=1]
+ br i1 %tmp167479, label %bb226, label %bb174
+
+bb145: ; preds = %bb136, %bb128
+ br i1 %tmp125, label %bb155, label %bb165
+
+bb155: ; preds = %bb145
+ %tmp167481 = fcmp ogt float %tmp2, %tmp8 ; <i1> [#uses=1]
+ br i1 %tmp167481, label %bb226, label %bb174
+
+bb165: ; preds = %bb145
+ %tmp167 = fcmp ogt float %tmp2, %tmp11 ; <i1> [#uses=1]
+ br i1 %tmp167, label %bb226, label %bb174
+
+bb174: ; preds = %bb165, %bb155, %bb141
+ br i1 %tmp125, label %bb187, label %bb195
+
+bb187: ; preds = %bb174
+ %tmp197483 = fcmp ogt float %tmp5, %tmp8 ; <i1> [#uses=2]
+ %brmerge790 = or i1 %tmp197483, %tmp125 ; <i1> [#uses=1]
+ %tmp4.mux791 = select i1 %tmp197483, float* %tmp4, float* %tmp7 ; <float*> [#uses=1]
+ br i1 %brmerge790, label %bb226, label %bb218
+
+bb195: ; preds = %bb174
+ %tmp197 = fcmp ogt float %tmp5, %tmp11 ; <i1> [#uses=2]
+ %brmerge788 = or i1 %tmp197, %tmp125 ; <i1> [#uses=1]
+ %tmp4.mux789 = select i1 %tmp197, float* %tmp4, float* %tmp7 ; <float*> [#uses=1]
+ br i1 %brmerge788, label %bb226, label %bb218
+
+bb218: ; preds = %bb195, %bb187
+ br label %bb226
+
+bb226: ; preds = %bb218, %bb195, %bb187, %bb165, %bb155, %bb141
+ %iftmp.7.0.in = phi float* [ %tmp10, %bb218 ], [ %result, %bb141 ], [ %result, %bb155 ], [ %result, %bb165 ], [ %tmp4.mux789, %bb195 ], [ %tmp4.mux791, %bb187 ] ; <float*> [#uses=1]
+ %iftmp.7.0 = load float* %iftmp.7.0.in ; <float> [#uses=1]
+ %tmp229 = getelementptr float* %result, i32 1 ; <float*> [#uses=7]
+ %tmp230 = load float* %tmp229, align 4 ; <float> [#uses=6]
+ %tmp232 = getelementptr float* %result, i32 3 ; <float*> [#uses=5]
+ %tmp233 = load float* %tmp232, align 4 ; <float> [#uses=10]
+ %tmp235 = getelementptr float* %result, i32 5 ; <float*> [#uses=5]
+ %tmp236 = load float* %tmp235, align 4 ; <float> [#uses=8]
+ %tmp238 = getelementptr float* %result, i32 7 ; <float*> [#uses=3]
+ %tmp239 = load float* %tmp238, align 4 ; <float> [#uses=8]
+ %tmp240 = fcmp olt float %tmp236, %tmp239 ; <i1> [#uses=5]
+ br i1 %tmp240, label %bb243, label %bb251
+
+bb243: ; preds = %bb226
+ %tmp253485 = fcmp olt float %tmp233, %tmp236 ; <i1> [#uses=1]
+ br i1 %tmp253485, label %bb256, label %bb260
+
+bb251: ; preds = %bb226
+ %tmp253 = fcmp olt float %tmp233, %tmp239 ; <i1> [#uses=1]
+ br i1 %tmp253, label %bb256, label %bb260
+
+bb256: ; preds = %bb251, %bb243
+ %tmp282487 = fcmp olt float %tmp230, %tmp233 ; <i1> [#uses=1]
+ br i1 %tmp282487, label %bb341, label %bb289
+
+bb260: ; preds = %bb251, %bb243
+ br i1 %tmp240, label %bb270, label %bb280
+
+bb270: ; preds = %bb260
+ %tmp282489 = fcmp olt float %tmp230, %tmp236 ; <i1> [#uses=1]
+ br i1 %tmp282489, label %bb341, label %bb289
+
+bb280: ; preds = %bb260
+ %tmp282 = fcmp olt float %tmp230, %tmp239 ; <i1> [#uses=1]
+ br i1 %tmp282, label %bb341, label %bb289
+
+bb289: ; preds = %bb280, %bb270, %bb256
+ br i1 %tmp240, label %bb302, label %bb310
+
+bb302: ; preds = %bb289
+ %tmp312491 = fcmp olt float %tmp233, %tmp236 ; <i1> [#uses=2]
+ %brmerge793 = or i1 %tmp312491, %tmp240 ; <i1> [#uses=1]
+ %tmp232.mux794 = select i1 %tmp312491, float* %tmp232, float* %tmp235 ; <float*> [#uses=1]
+ br i1 %brmerge793, label %bb341, label %bb333
+
+bb310: ; preds = %bb289
+ %tmp312 = fcmp olt float %tmp233, %tmp239 ; <i1> [#uses=2]
+ %brmerge792 = or i1 %tmp312, %tmp240 ; <i1> [#uses=1]
+ %tmp232.mux = select i1 %tmp312, float* %tmp232, float* %tmp235 ; <float*> [#uses=1]
+ br i1 %brmerge792, label %bb341, label %bb333
+
+bb333: ; preds = %bb310, %bb302
+ br label %bb341
+
+bb341: ; preds = %bb333, %bb310, %bb302, %bb280, %bb270, %bb256
+ %iftmp.14.0.in = phi float* [ %tmp238, %bb333 ], [ %tmp229, %bb280 ], [ %tmp229, %bb270 ], [ %tmp229, %bb256 ], [ %tmp232.mux, %bb310 ], [ %tmp232.mux794, %bb302 ] ; <float*> [#uses=1]
+ %iftmp.14.0 = load float* %iftmp.14.0.in ; <float> [#uses=1]
+ %tmp355 = fcmp ogt float %tmp236, %tmp239 ; <i1> [#uses=5]
+ br i1 %tmp355, label %bb358, label %bb366
+
+bb358: ; preds = %bb341
+ %tmp368493 = fcmp ogt float %tmp233, %tmp236 ; <i1> [#uses=1]
+ br i1 %tmp368493, label %bb371, label %bb375
+
+bb366: ; preds = %bb341
+ %tmp368 = fcmp ogt float %tmp233, %tmp239 ; <i1> [#uses=1]
+ br i1 %tmp368, label %bb371, label %bb375
+
+bb371: ; preds = %bb366, %bb358
+ %tmp397495 = fcmp ogt float %tmp230, %tmp233 ; <i1> [#uses=1]
+ br i1 %tmp397495, label %bb456, label %bb404
+
+bb375: ; preds = %bb366, %bb358
+ br i1 %tmp355, label %bb385, label %bb395
+
+bb385: ; preds = %bb375
+ %tmp397497 = fcmp ogt float %tmp230, %tmp236 ; <i1> [#uses=1]
+ br i1 %tmp397497, label %bb456, label %bb404
+
+bb395: ; preds = %bb375
+ %tmp397 = fcmp ogt float %tmp230, %tmp239 ; <i1> [#uses=1]
+ br i1 %tmp397, label %bb456, label %bb404
+
+bb404: ; preds = %bb395, %bb385, %bb371
+ br i1 %tmp355, label %bb417, label %bb425
+
+bb417: ; preds = %bb404
+ %tmp427499 = fcmp ogt float %tmp233, %tmp236 ; <i1> [#uses=2]
+ %brmerge797 = or i1 %tmp427499, %tmp355 ; <i1> [#uses=1]
+ %tmp232.mux798 = select i1 %tmp427499, float* %tmp232, float* %tmp235 ; <float*> [#uses=1]
+ br i1 %brmerge797, label %bb456, label %bb448
+
+bb425: ; preds = %bb404
+ %tmp427 = fcmp ogt float %tmp233, %tmp239 ; <i1> [#uses=2]
+ %brmerge795 = or i1 %tmp427, %tmp355 ; <i1> [#uses=1]
+ %tmp232.mux796 = select i1 %tmp427, float* %tmp232, float* %tmp235 ; <float*> [#uses=1]
+ br i1 %brmerge795, label %bb456, label %bb448
+
+bb448: ; preds = %bb425, %bb417
+ br label %bb456
+
+bb456: ; preds = %bb448, %bb425, %bb417, %bb395, %bb385, %bb371
+ %iftmp.21.0.in = phi float* [ %tmp238, %bb448 ], [ %tmp229, %bb395 ], [ %tmp229, %bb385 ], [ %tmp229, %bb371 ], [ %tmp232.mux796, %bb425 ], [ %tmp232.mux798, %bb417 ] ; <float*> [#uses=1]
+ %iftmp.21.0 = load float* %iftmp.21.0.in ; <float> [#uses=1]
+ %tmp458459 = fpext float %iftmp.21.0 to double ; <double> [#uses=1]
+ %tmp460461 = fpext float %iftmp.7.0 to double ; <double> [#uses=1]
+ %tmp462463 = fpext float %iftmp.14.0 to double ; <double> [#uses=1]
+ %tmp464465 = fpext float %iftmp.0.0 to double ; <double> [#uses=1]
+ %tmp467 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([48 x i8]* @.str, i32 0, i32 0), double %tmp464465, double %tmp462463, double %tmp460461, double %tmp458459 ) nounwind ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @printf(i8*, ...) nounwind
diff --git a/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll b/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll
new file mode 100644
index 0000000..5115e48
--- /dev/null
+++ b/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s | grep {a:} | not grep ax
+; RUN: llc < %s | grep {b:} | not grep ax
+; PR2078
+; The clobber list says that "ax" is clobbered. Make sure that eax isn't
+; allocated to the input/output register.
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+@pixels = weak global i32 0 ; <i32*> [#uses=2]
+
+define void @test() nounwind {
+entry:
+ %tmp = load i32* @pixels, align 4 ; <i32> [#uses=1]
+ %tmp1 = tail call i32 asm sideeffect "a: $0 $1", "=r,0,~{dirflag},~{fpsr},~{flags},~{ax}"( i32 %tmp ) nounwind ; <i32> [#uses=1]
+ store i32 %tmp1, i32* @pixels, align 4
+ ret void
+}
+
+define void @test2(i16* %block, i8* %pixels, i32 %line_size) nounwind {
+entry:
+ %tmp1 = getelementptr i16* %block, i32 64 ; <i16*> [#uses=1]
+ %tmp3 = tail call i8* asm sideeffect "b: $0 $1 $2", "=r,r,0,~{dirflag},~{fpsr},~{flags},~{ax}"( i16* %tmp1, i8* %pixels ) nounwind ; <i8*> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll b/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll
new file mode 100644
index 0000000..6b1eefe
--- /dev/null
+++ b/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -regalloc=local -march=x86 -mattr=+mmx | grep esi
+; PR2082
+; Local register allocator was refusing to use ESI, EDI, and EBP so it ran out of
+; registers.
+define void @transpose4x4(i8* %dst, i8* %src, i32 %dst_stride, i32 %src_stride) {
+entry:
+ %dst_addr = alloca i8* ; <i8**> [#uses=5]
+ %src_addr = alloca i8* ; <i8**> [#uses=5]
+ %dst_stride_addr = alloca i32 ; <i32*> [#uses=4]
+ %src_stride_addr = alloca i32 ; <i32*> [#uses=4]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i8* %dst, i8** %dst_addr
+ store i8* %src, i8** %src_addr
+ store i32 %dst_stride, i32* %dst_stride_addr
+ store i32 %src_stride, i32* %src_stride_addr
+ %tmp = load i8** %dst_addr, align 4 ; <i8*> [#uses=1]
+ %tmp1 = getelementptr i8* %tmp, i32 0 ; <i8*> [#uses=1]
+ %tmp12 = bitcast i8* %tmp1 to i32* ; <i32*> [#uses=1]
+ %tmp3 = load i8** %dst_addr, align 4 ; <i8*> [#uses=1]
+ %tmp4 = load i32* %dst_stride_addr, align 4 ; <i32> [#uses=1]
+ %tmp5 = getelementptr i8* %tmp3, i32 %tmp4 ; <i8*> [#uses=1]
+ %tmp56 = bitcast i8* %tmp5 to i32* ; <i32*> [#uses=1]
+ %tmp7 = load i32* %dst_stride_addr, align 4 ; <i32> [#uses=1]
+ %tmp8 = mul i32 %tmp7, 2 ; <i32> [#uses=1]
+ %tmp9 = load i8** %dst_addr, align 4 ; <i8*> [#uses=1]
+ %tmp10 = getelementptr i8* %tmp9, i32 %tmp8 ; <i8*> [#uses=1]
+ %tmp1011 = bitcast i8* %tmp10 to i32* ; <i32*> [#uses=1]
+ %tmp13 = load i32* %dst_stride_addr, align 4 ; <i32> [#uses=1]
+ %tmp14 = mul i32 %tmp13, 3 ; <i32> [#uses=1]
+ %tmp15 = load i8** %dst_addr, align 4 ; <i8*> [#uses=1]
+ %tmp16 = getelementptr i8* %tmp15, i32 %tmp14 ; <i8*> [#uses=1]
+ %tmp1617 = bitcast i8* %tmp16 to i32* ; <i32*> [#uses=1]
+ %tmp18 = load i8** %src_addr, align 4 ; <i8*> [#uses=1]
+ %tmp19 = getelementptr i8* %tmp18, i32 0 ; <i8*> [#uses=1]
+ %tmp1920 = bitcast i8* %tmp19 to i32* ; <i32*> [#uses=1]
+ %tmp21 = load i8** %src_addr, align 4 ; <i8*> [#uses=1]
+ %tmp22 = load i32* %src_stride_addr, align 4 ; <i32> [#uses=1]
+ %tmp23 = getelementptr i8* %tmp21, i32 %tmp22 ; <i8*> [#uses=1]
+ %tmp2324 = bitcast i8* %tmp23 to i32* ; <i32*> [#uses=1]
+ %tmp25 = load i32* %src_stride_addr, align 4 ; <i32> [#uses=1]
+ %tmp26 = mul i32 %tmp25, 2 ; <i32> [#uses=1]
+ %tmp27 = load i8** %src_addr, align 4 ; <i8*> [#uses=1]
+ %tmp28 = getelementptr i8* %tmp27, i32 %tmp26 ; <i8*> [#uses=1]
+ %tmp2829 = bitcast i8* %tmp28 to i32* ; <i32*> [#uses=1]
+ %tmp30 = load i32* %src_stride_addr, align 4 ; <i32> [#uses=1]
+ %tmp31 = mul i32 %tmp30, 3 ; <i32> [#uses=1]
+ %tmp32 = load i8** %src_addr, align 4 ; <i8*> [#uses=1]
+ %tmp33 = getelementptr i8* %tmp32, i32 %tmp31 ; <i8*> [#uses=1]
+ %tmp3334 = bitcast i8* %tmp33 to i32* ; <i32*> [#uses=1]
+ call void asm sideeffect "movd $4, %mm0 \0A\09movd $5, %mm1 \0A\09movd $6, %mm2 \0A\09movd $7, %mm3 \0A\09punpcklbw %mm1, %mm0 \0A\09punpcklbw %mm3, %mm2 \0A\09movq %mm0, %mm1 \0A\09punpcklwd %mm2, %mm0 \0A\09punpckhwd %mm2, %mm1 \0A\09movd %mm0, $0 \0A\09punpckhdq %mm0, %mm0 \0A\09movd %mm0, $1 \0A\09movd %mm1, $2 \0A\09punpckhdq %mm1, %mm1 \0A\09movd %mm1, $3 \0A\09", "=*m,=*m,=*m,=*m,*m,*m,*m,*m,~{dirflag},~{fpsr},~{flags}"( i32* %tmp12, i32* %tmp56, i32* %tmp1011, i32* %tmp1617, i32* %tmp1920, i32* %tmp2324, i32* %tmp2829, i32* %tmp3334 ) nounwind
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2008-02-22-ReMatBug.ll b/test/CodeGen/X86/2008-02-22-ReMatBug.ll
new file mode 100644
index 0000000..8d6bb0d
--- /dev/null
+++ b/test/CodeGen/X86/2008-02-22-ReMatBug.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=x86 -stats |& grep {Number of re-materialization} | grep 3
+; rdar://5761454
+
+ %struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }
+
+define %struct.quad_struct* @MakeTree(i32 %size, i32 %center_x, i32 %center_y, i32 %lo_proc, i32 %hi_proc, %struct.quad_struct* %parent, i32 %ct, i32 %level) nounwind {
+entry:
+ br i1 true, label %bb43.i, label %bb.i
+
+bb.i: ; preds = %entry
+ ret %struct.quad_struct* null
+
+bb43.i: ; preds = %entry
+ br i1 true, label %CheckOutside.exit40.i, label %bb11.i38.i
+
+bb11.i38.i: ; preds = %bb43.i
+ ret %struct.quad_struct* null
+
+CheckOutside.exit40.i: ; preds = %bb43.i
+ br i1 true, label %CheckOutside.exit30.i, label %bb11.i28.i
+
+bb11.i28.i: ; preds = %CheckOutside.exit40.i
+ ret %struct.quad_struct* null
+
+CheckOutside.exit30.i: ; preds = %CheckOutside.exit40.i
+ br i1 true, label %CheckOutside.exit20.i, label %bb11.i18.i
+
+bb11.i18.i: ; preds = %CheckOutside.exit30.i
+ ret %struct.quad_struct* null
+
+CheckOutside.exit20.i: ; preds = %CheckOutside.exit30.i
+ br i1 true, label %bb34, label %bb11.i8.i
+
+bb11.i8.i: ; preds = %CheckOutside.exit20.i
+ ret %struct.quad_struct* null
+
+bb34: ; preds = %CheckOutside.exit20.i
+ %tmp15.reg2mem.0 = sdiv i32 %size, 2 ; <i32> [#uses=7]
+ %tmp85 = sub i32 %center_y, %tmp15.reg2mem.0 ; <i32> [#uses=2]
+ %tmp88 = sub i32 %center_x, %tmp15.reg2mem.0 ; <i32> [#uses=2]
+ %tmp92 = tail call %struct.quad_struct* @MakeTree( i32 %tmp15.reg2mem.0, i32 %tmp88, i32 %tmp85, i32 0, i32 %hi_proc, %struct.quad_struct* null, i32 2, i32 0 ) nounwind ; <%struct.quad_struct*> [#uses=0]
+ %tmp99 = add i32 0, %hi_proc ; <i32> [#uses=1]
+ %tmp100 = sdiv i32 %tmp99, 2 ; <i32> [#uses=1]
+ %tmp110 = tail call %struct.quad_struct* @MakeTree( i32 %tmp15.reg2mem.0, i32 0, i32 %tmp85, i32 0, i32 %tmp100, %struct.quad_struct* null, i32 3, i32 0 ) nounwind ; <%struct.quad_struct*> [#uses=0]
+ %tmp122 = add i32 %tmp15.reg2mem.0, %center_y ; <i32> [#uses=2]
+ %tmp129 = tail call %struct.quad_struct* @MakeTree( i32 %tmp15.reg2mem.0, i32 0, i32 %tmp122, i32 0, i32 0, %struct.quad_struct* null, i32 1, i32 0 ) nounwind ; <%struct.quad_struct*> [#uses=0]
+ %tmp147 = tail call %struct.quad_struct* @MakeTree( i32 %tmp15.reg2mem.0, i32 %tmp88, i32 %tmp122, i32 %lo_proc, i32 0, %struct.quad_struct* null, i32 0, i32 0 ) nounwind ; <%struct.quad_struct*> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/X86/2008-02-25-InlineAsmBug.ll b/test/CodeGen/X86/2008-02-25-InlineAsmBug.ll
new file mode 100644
index 0000000..1d31859
--- /dev/null
+++ b/test/CodeGen/X86/2008-02-25-InlineAsmBug.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu -mattr=+sse2
+; PR2076
+
+define void @h264_h_loop_filter_luma_mmx2(i8* %pix, i32 %stride, i32 %alpha, i32 %beta, i8* %tc0) nounwind {
+entry:
+ %tmp164 = getelementptr [16 x i32]* null, i32 0, i32 11 ; <i32*> [#uses=1]
+ %tmp169 = getelementptr [16 x i32]* null, i32 0, i32 13 ; <i32*> [#uses=1]
+ %tmp174 = getelementptr [16 x i32]* null, i32 0, i32 15 ; <i32*> [#uses=1]
+ %tmp154.sum317 = add i32 0, %stride ; <i32> [#uses=1]
+ %tmp154.sum315 = mul i32 %stride, 6 ; <i32> [#uses=1]
+ %tmp154.sum = mul i32 %stride, 7 ; <i32> [#uses=1]
+ %pix_addr.0327.rec = mul i32 0, 0 ; <i32> [#uses=4]
+ br i1 false, label %bb292, label %bb32
+
+bb32: ; preds = %entry
+ %pix_addr.0327.sum340 = add i32 %pix_addr.0327.rec, 0 ; <i32> [#uses=1]
+ %tmp154 = getelementptr i8* %pix, i32 %pix_addr.0327.sum340 ; <i8*> [#uses=1]
+ %tmp177178 = bitcast i8* %tmp154 to i32* ; <i32*> [#uses=1]
+ %pix_addr.0327.sum339 = add i32 %pix_addr.0327.rec, %tmp154.sum317 ; <i32> [#uses=1]
+ %tmp181 = getelementptr i8* %pix, i32 %pix_addr.0327.sum339 ; <i8*> [#uses=1]
+ %tmp181182 = bitcast i8* %tmp181 to i32* ; <i32*> [#uses=1]
+ %pix_addr.0327.sum338 = add i32 %pix_addr.0327.rec, %tmp154.sum315 ; <i32> [#uses=1]
+ %tmp186 = getelementptr i8* %pix, i32 %pix_addr.0327.sum338 ; <i8*> [#uses=1]
+ %tmp186187 = bitcast i8* %tmp186 to i32* ; <i32*> [#uses=1]
+ %pix_addr.0327.sum337 = add i32 %pix_addr.0327.rec, %tmp154.sum ; <i32> [#uses=1]
+ %tmp191 = getelementptr i8* %pix, i32 %pix_addr.0327.sum337 ; <i8*> [#uses=1]
+ %tmp191192 = bitcast i8* %tmp191 to i32* ; <i32*> [#uses=1]
+ call void asm sideeffect "movd $4, %mm0 \0A\09movd $5, %mm1 \0A\09movd $6, %mm2 \0A\09movd $7, %mm3 \0A\09punpcklbw %mm1, %mm0 \0A\09punpcklbw %mm3, %mm2 \0A\09movq %mm0, %mm1 \0A\09punpcklwd %mm2, %mm0 \0A\09punpckhwd %mm2, %mm1 \0A\09movd %mm0, $0 \0A\09punpckhdq %mm0, %mm0 \0A\09movd %mm0, $1 \0A\09movd %mm1, $2 \0A\09punpckhdq %mm1, %mm1 \0A\09movd %mm1, $3 \0A\09", "=*m,=*m,=*m,=*m,*m,*m,*m,*m,~{dirflag},~{fpsr},~{flags}"( i32* null, i32* %tmp164, i32* %tmp169, i32* %tmp174, i32* %tmp177178, i32* %tmp181182, i32* %tmp186187, i32* %tmp191192 ) nounwind
+ unreachable
+
+bb292: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll b/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll
new file mode 100644
index 0000000..6615b8c
--- /dev/null
+++ b/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -march=x86-64
+
+ %struct.XX = type <{ i8 }>
+ %struct.YY = type { i64 }
+ %struct.ZZ = type opaque
+
+define i8 @f(%struct.XX*** %fontMap, %struct.XX* %uen) signext {
+entry:
+ %tmp45 = add i16 0, 1 ; <i16> [#uses=2]
+ br i1 false, label %bb124, label %bb53
+
+bb53: ; preds = %entry
+ %tmp55 = call %struct.YY** @AA( i64 1, %struct.XX* %uen ) ; <%struct.YY**> [#uses=3]
+ %tmp2728128 = load %struct.XX** null ; <%struct.XX*> [#uses=1]
+ %tmp61 = load %struct.YY** %tmp55, align 8 ; <%struct.YY*> [#uses=1]
+ %tmp62 = getelementptr %struct.YY* %tmp61, i32 0, i32 0 ; <i64*> [#uses=1]
+ %tmp63 = load i64* %tmp62, align 8 ; <i64> [#uses=1]
+ %tmp6566 = zext i16 %tmp45 to i64 ; <i64> [#uses=1]
+ %tmp67 = shl i64 %tmp6566, 1 ; <i64> [#uses=1]
+ call void @BB( %struct.YY** %tmp55, i64 %tmp67, i8 signext 0, %struct.XX* %uen )
+ %tmp121131 = icmp eq i16 %tmp45, 1 ; <i1> [#uses=1]
+ br i1 %tmp121131, label %bb124, label %bb70.preheader
+
+bb70.preheader: ; preds = %bb53
+ %tmp72 = bitcast %struct.XX* %tmp2728128 to %struct.ZZ*** ; <%struct.ZZ***> [#uses=1]
+ br label %bb70
+
+bb70: ; preds = %bb119, %bb70.preheader
+ %indvar133 = phi i32 [ %indvar.next134, %bb119 ], [ 0, %bb70.preheader ] ; <i32> [#uses=2]
+ %tmp.135 = trunc i64 %tmp63 to i32 ; <i32> [#uses=1]
+ %tmp136 = shl i32 %indvar133, 1 ; <i32> [#uses=1]
+ %DD = add i32 %tmp136, %tmp.135 ; <i32> [#uses=1]
+ %tmp73 = load %struct.ZZ*** %tmp72, align 8 ; <%struct.ZZ**> [#uses=0]
+ br i1 false, label %bb119, label %bb77
+
+bb77: ; preds = %bb70
+ %tmp8384 = trunc i32 %DD to i16 ; <i16> [#uses=1]
+ %tmp85 = sub i16 0, %tmp8384 ; <i16> [#uses=1]
+ store i16 %tmp85, i16* null, align 8
+ call void @CC( %struct.YY** %tmp55, i64 0, i64 2, i8* null, %struct.XX* %uen )
+ ret i8 0
+
+bb119: ; preds = %bb70
+ %indvar.next134 = add i32 %indvar133, 1 ; <i32> [#uses=1]
+ br label %bb70
+
+bb124: ; preds = %bb53, %entry
+ ret i8 undef
+}
+
+declare %struct.YY** @AA(i64, %struct.XX*)
+
+declare void @BB(%struct.YY**, i64, i8 signext , %struct.XX*)
+
+declare void @CC(%struct.YY**, i64, i64, i8*, %struct.XX*)
diff --git a/test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll b/test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll
new file mode 100644
index 0000000..0b4eb3a
--- /dev/null
+++ b/test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+
+define void @dct_unquantize_h263_intra_mmx(i16* %block, i32 %n, i32 %qscale) nounwind {
+entry:
+ %tmp1 = shl i32 %qscale, 1 ; <i32> [#uses=1]
+ br i1 false, label %bb46, label %bb59
+
+bb46: ; preds = %entry
+ ret void
+
+bb59: ; preds = %entry
+ tail call void asm sideeffect "movd $1, %mm6 \0A\09packssdw %mm6, %mm6 \0A\09packssdw %mm6, %mm6 \0A\09movd $2, %mm5 \0A\09pxor %mm7, %mm7 \0A\09packssdw %mm5, %mm5 \0A\09packssdw %mm5, %mm5 \0A\09psubw %mm5, %mm7 \0A\09pxor %mm4, %mm4 \0A\09.align 1<<4\0A\091: \0A\09movq ($0, $3), %mm0 \0A\09movq 8($0, $3), %mm1 \0A\09pmullw %mm6, %mm0 \0A\09pmullw %mm6, %mm1 \0A\09movq ($0, $3), %mm2 \0A\09movq 8($0, $3), %mm3 \0A\09pcmpgtw %mm4, %mm2 \0A\09pcmpgtw %mm4, %mm3 \0A\09pxor %mm2, %mm0 \0A\09pxor %mm3, %mm1 \0A\09paddw %mm7, %mm0 \0A\09paddw %mm7, %mm1 \0A\09pxor %mm0, %mm2 \0A\09pxor %mm1, %mm3 \0A\09pcmpeqw %mm7, %mm0 \0A\09pcmpeqw %mm7, %mm1 \0A\09pandn %mm2, %mm0 \0A\09pandn %mm3, %mm1 \0A\09movq %mm0, ($0, $3) \0A\09movq %mm1, 8($0, $3) \0A\09add $$16, $3 \0A\09jng 1b \0A\09", "r,imr,imr,r,~{dirflag},~{fpsr},~{flags},~{memory}"( i16* null, i32 %tmp1, i32 0, i32 0 ) nounwind
+ ret void
+}
diff --git a/test/CodeGen/X86/2008-02-27-DeadSlotElimBug.ll b/test/CodeGen/X86/2008-02-27-DeadSlotElimBug.ll
new file mode 100644
index 0000000..ad7950c
--- /dev/null
+++ b/test/CodeGen/X86/2008-02-27-DeadSlotElimBug.ll
@@ -0,0 +1,66 @@
+; RUN: llc < %s -march=x86
+
+ %struct.CompAtom = type <{ %struct.Position, float, i32 }>
+ %struct.Lattice = type { %struct.Position, %struct.Position, %struct.Position, %struct.Position, %struct.Position, %struct.Position, %struct.Position, i32, i32, i32 }
+ %struct.Position = type { double, double, double }
+
+define fastcc %struct.CompAtom* @_ZNK7Lattice6createEP8CompAtomii(%struct.Lattice* %this, %struct.CompAtom* %d, i32 %n, i32 %i) {
+entry:
+ %tmp18 = tail call i8* @_Znam( i32 0 ) ; <i8*> [#uses=1]
+ %tmp1819 = bitcast i8* %tmp18 to %struct.CompAtom* ; <%struct.CompAtom*> [#uses=4]
+ %tmp3286 = icmp eq i32 %n, 0 ; <i1> [#uses=1]
+ br i1 %tmp3286, label %bb35, label %bb24
+
+bb24: ; preds = %bb24, %entry
+ %tmp9.0.reg2mem.0.rec = phi i32 [ %indvar.next, %bb24 ], [ 0, %entry ] ; <i32> [#uses=3]
+ %tmp3.i.i = getelementptr %struct.CompAtom* %tmp1819, i32 %tmp9.0.reg2mem.0.rec, i32 0, i32 1 ; <double*> [#uses=0]
+ %tmp5.i.i = getelementptr %struct.CompAtom* %tmp1819, i32 %tmp9.0.reg2mem.0.rec, i32 0, i32 2 ; <double*> [#uses=1]
+ store double -9.999900e+04, double* %tmp5.i.i, align 4
+ %indvar.next = add i32 %tmp9.0.reg2mem.0.rec, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %n ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb35, label %bb24
+
+bb35: ; preds = %bb24, %entry
+ %tmp42 = sdiv i32 %i, 9 ; <i32> [#uses=1]
+ %tmp43 = add i32 %tmp42, -1 ; <i32> [#uses=1]
+ %tmp4344 = sitofp i32 %tmp43 to double ; <double> [#uses=1]
+ %tmp17.i76 = fmul double %tmp4344, 0.000000e+00 ; <double> [#uses=1]
+ %tmp48 = sdiv i32 %i, 3 ; <i32> [#uses=1]
+ %tmp49 = srem i32 %tmp48, 3 ; <i32> [#uses=1]
+ %tmp50 = add i32 %tmp49, -1 ; <i32> [#uses=1]
+ %tmp5051 = sitofp i32 %tmp50 to double ; <double> [#uses=1]
+ %tmp17.i63 = fmul double %tmp5051, 0.000000e+00 ; <double> [#uses=1]
+ %tmp55 = srem i32 %i, 3 ; <i32> [#uses=1]
+ %tmp56 = add i32 %tmp55, -1 ; <i32> [#uses=1]
+ %tmp5657 = sitofp i32 %tmp56 to double ; <double> [#uses=1]
+ %tmp15.i49 = getelementptr %struct.Lattice* %this, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ %tmp16.i50 = load double* %tmp15.i49, align 4 ; <double> [#uses=1]
+ %tmp17.i = fmul double %tmp5657, %tmp16.i50 ; <double> [#uses=1]
+ %tmp20.i39 = fadd double %tmp17.i, %tmp17.i63 ; <double> [#uses=1]
+ %tmp20.i23 = fadd double %tmp20.i39, %tmp17.i76 ; <double> [#uses=1]
+ br i1 false, label %bb58.preheader, label %bb81
+
+bb58.preheader: ; preds = %bb35
+ %smax = select i1 false, i32 1, i32 %n ; <i32> [#uses=1]
+ br label %bb58
+
+bb58: ; preds = %bb58, %bb58.preheader
+ %tmp20.i7 = getelementptr %struct.CompAtom* %d, i32 0, i32 2 ; <i32*> [#uses=2]
+ %tmp25.i = getelementptr %struct.CompAtom* %tmp1819, i32 0, i32 2 ; <i32*> [#uses=2]
+ %tmp74.i = load i32* %tmp20.i7, align 1 ; <i32> [#uses=1]
+ %tmp82.i = and i32 %tmp74.i, 134217728 ; <i32> [#uses=1]
+ %tmp85.i = or i32 0, %tmp82.i ; <i32> [#uses=1]
+ store i32 %tmp85.i, i32* %tmp25.i, align 1
+ %tmp88.i = load i32* %tmp20.i7, align 1 ; <i32> [#uses=1]
+ %tmp95.i = and i32 %tmp88.i, -268435456 ; <i32> [#uses=1]
+ %tmp97.i = or i32 0, %tmp95.i ; <i32> [#uses=1]
+ store i32 %tmp97.i, i32* %tmp25.i, align 1
+ %tmp6.i = fadd double 0.000000e+00, %tmp20.i23 ; <double> [#uses=0]
+ %exitcond96 = icmp eq i32 0, %smax ; <i1> [#uses=1]
+ br i1 %exitcond96, label %bb81, label %bb58
+
+bb81: ; preds = %bb58, %bb35
+ ret %struct.CompAtom* %tmp1819
+}
+
+declare i8* @_Znam(i32)
diff --git a/test/CodeGen/X86/2008-02-27-PEICrash.ll b/test/CodeGen/X86/2008-02-27-PEICrash.ll
new file mode 100644
index 0000000..d842967
--- /dev/null
+++ b/test/CodeGen/X86/2008-02-27-PEICrash.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+
+define i64 @__divsc3(float %a, float %b, float %c, float %d) nounwind readnone {
+entry:
+ br i1 false, label %bb56, label %bb33
+
+bb33: ; preds = %entry
+ br label %bb56
+
+bb56: ; preds = %bb33, %entry
+ %tmp36.pn = phi float [ 0.000000e+00, %bb33 ], [ 0.000000e+00, %entry ] ; <float> [#uses=1]
+ %b.pn509 = phi float [ %b, %bb33 ], [ %a, %entry ] ; <float> [#uses=1]
+ %a.pn = phi float [ %a, %bb33 ], [ %b, %entry ] ; <float> [#uses=1]
+ %tmp41.pn508 = phi float [ 0.000000e+00, %bb33 ], [ 0.000000e+00, %entry ] ; <float> [#uses=1]
+ %tmp51.pn = phi float [ 0.000000e+00, %bb33 ], [ %a, %entry ] ; <float> [#uses=1]
+ %tmp44.pn = fmul float %tmp36.pn, %b.pn509 ; <float> [#uses=1]
+ %tmp46.pn = fadd float %tmp44.pn, %a.pn ; <float> [#uses=1]
+ %tmp53.pn = fsub float 0.000000e+00, %tmp51.pn ; <float> [#uses=1]
+ %x.0 = fdiv float %tmp46.pn, %tmp41.pn508 ; <float> [#uses=1]
+ %y.0 = fdiv float %tmp53.pn, 0.000000e+00 ; <float> [#uses=1]
+ br i1 false, label %bb433, label %bb98
+
+bb98: ; preds = %bb56
+ %tmp102 = fmul float 0.000000e+00, %a ; <float> [#uses=1]
+ %tmp106 = fmul float 0.000000e+00, %b ; <float> [#uses=1]
+ br label %bb433
+
+bb433: ; preds = %bb98, %bb56
+ %x.1 = phi float [ %tmp102, %bb98 ], [ %x.0, %bb56 ] ; <float> [#uses=0]
+ %y.1 = phi float [ %tmp106, %bb98 ], [ %y.0, %bb56 ] ; <float> [#uses=1]
+ %tmp460 = fadd float %y.1, 0.000000e+00 ; <float> [#uses=0]
+ ret i64 0
+}
diff --git a/test/CodeGen/X86/2008-03-06-frem-fpstack.ll b/test/CodeGen/X86/2008-03-06-frem-fpstack.ll
new file mode 100644
index 0000000..70a83b5
--- /dev/null
+++ b/test/CodeGen/X86/2008-03-06-frem-fpstack.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86 -mcpu=i386
+; PR2122
+define float @func(float %a, float %b) nounwind {
+entry:
+ %tmp3 = frem float %a, %b ; <float> [#uses=1]
+ ret float %tmp3
+}
diff --git a/test/CodeGen/X86/2008-03-07-APIntBug.ll b/test/CodeGen/X86/2008-03-07-APIntBug.ll
new file mode 100644
index 0000000..84e4827
--- /dev/null
+++ b/test/CodeGen/X86/2008-03-07-APIntBug.ll
@@ -0,0 +1,94 @@
+; RUN: llc < %s -march=x86 -mcpu=i386 | not grep 255
+
+ %struct.CONSTRAINT = type { i32, i32, i32, i32 }
+ %struct.FIRST_UNION = type { %struct.anon }
+ %struct.FOURTH_UNION = type { %struct.CONSTRAINT }
+ %struct.LIST = type { %struct.rec*, %struct.rec* }
+ %struct.SECOND_UNION = type { { i16, i8, i8 } }
+ %struct.THIRD_UNION = type { { [2 x i32], [2 x i32] } }
+ %struct.anon = type { i8, i8, i32 }
+ %struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, %struct.rec*, { %struct.rec* }, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i32 }
+ %struct.rec = type { %struct.head_type }
+ %struct.symbol_type = type <{ [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i16, i16, i8, i8, i8, i8 }>
+ %struct.word_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, [4 x i8] }
+
+define void @InsertSym_bb1163(%struct.rec** %s) {
+newFuncRoot:
+ br label %bb1163
+bb1233.exitStub: ; preds = %bb1163
+ ret void
+bb1163: ; preds = %newFuncRoot
+ %tmp1164 = load %struct.rec** %s, align 4 ; <%struct.rec*> [#uses=1]
+ %tmp1165 = getelementptr %struct.rec* %tmp1164, i32 0, i32 0 ; <%struct.head_type*> [#uses=1]
+ %tmp11651166 = bitcast %struct.head_type* %tmp1165 to %struct.symbol_type* ; <%struct.symbol_type*> [#uses=1]
+ %tmp1167 = getelementptr %struct.symbol_type* %tmp11651166, i32 0, i32 3 ; <%struct.rec**> [#uses=1]
+ %tmp1168 = load %struct.rec** %tmp1167, align 1 ; <%struct.rec*> [#uses=2]
+ %tmp1169 = load %struct.rec** %s, align 4 ; <%struct.rec*> [#uses=1]
+ %tmp1170 = getelementptr %struct.rec* %tmp1169, i32 0, i32 0 ; <%struct.head_type*> [#uses=1]
+ %tmp11701171 = bitcast %struct.head_type* %tmp1170 to %struct.symbol_type* ; <%struct.symbol_type*> [#uses=1]
+ %tmp1172 = getelementptr %struct.symbol_type* %tmp11701171, i32 0, i32 3 ; <%struct.rec**> [#uses=1]
+ %tmp1173 = load %struct.rec** %tmp1172, align 1 ; <%struct.rec*> [#uses=2]
+ %tmp1174 = getelementptr %struct.rec* %tmp1173, i32 0, i32 0 ; <%struct.head_type*> [#uses=1]
+ %tmp11741175 = bitcast %struct.head_type* %tmp1174 to %struct.word_type* ; <%struct.word_type*> [#uses=1]
+ %tmp1176 = getelementptr %struct.word_type* %tmp11741175, i32 0, i32 2 ; <%struct.SECOND_UNION*> [#uses=1]
+ %tmp1177 = getelementptr %struct.SECOND_UNION* %tmp1176, i32 0, i32 0 ; <{ i16, i8, i8 }*> [#uses=1]
+ %tmp11771178 = bitcast { i16, i8, i8 }* %tmp1177 to <{ i8, i8, i8, i8 }>* ; <<{ i8, i8, i8, i8 }>*> [#uses=1]
+ %tmp1179 = getelementptr <{ i8, i8, i8, i8 }>* %tmp11771178, i32 0, i32 2 ; <i8*> [#uses=2]
+ %mask1180 = and i8 1, 1 ; <i8> [#uses=2]
+ %tmp1181 = load i8* %tmp1179, align 1 ; <i8> [#uses=1]
+ %tmp1182 = shl i8 %mask1180, 7 ; <i8> [#uses=1]
+ %tmp1183 = and i8 %tmp1181, 127 ; <i8> [#uses=1]
+ %tmp1184 = or i8 %tmp1183, %tmp1182 ; <i8> [#uses=1]
+ store i8 %tmp1184, i8* %tmp1179, align 1
+ %mask1185 = and i8 %mask1180, 1 ; <i8> [#uses=0]
+ %tmp1186 = getelementptr %struct.rec* %tmp1173, i32 0, i32 0 ; <%struct.head_type*> [#uses=1]
+ %tmp11861187 = bitcast %struct.head_type* %tmp1186 to %struct.word_type* ; <%struct.word_type*> [#uses=1]
+ %tmp1188 = getelementptr %struct.word_type* %tmp11861187, i32 0, i32 2 ; <%struct.SECOND_UNION*> [#uses=1]
+ %tmp1189 = getelementptr %struct.SECOND_UNION* %tmp1188, i32 0, i32 0 ; <{ i16, i8, i8 }*> [#uses=1]
+ %tmp11891190 = bitcast { i16, i8, i8 }* %tmp1189 to <{ i8, i8, i8, i8 }>* ; <<{ i8, i8, i8, i8 }>*> [#uses=1]
+ %tmp1191 = getelementptr <{ i8, i8, i8, i8 }>* %tmp11891190, i32 0, i32 2 ; <i8*> [#uses=1]
+ %tmp1192 = load i8* %tmp1191, align 1 ; <i8> [#uses=1]
+ %tmp1193 = lshr i8 %tmp1192, 7 ; <i8> [#uses=1]
+ %mask1194 = and i8 %tmp1193, 1 ; <i8> [#uses=2]
+ %mask1195 = and i8 %mask1194, 1 ; <i8> [#uses=0]
+ %tmp1196 = getelementptr %struct.rec* %tmp1168, i32 0, i32 0 ; <%struct.head_type*> [#uses=1]
+ %tmp11961197 = bitcast %struct.head_type* %tmp1196 to %struct.word_type* ; <%struct.word_type*> [#uses=1]
+ %tmp1198 = getelementptr %struct.word_type* %tmp11961197, i32 0, i32 2 ; <%struct.SECOND_UNION*> [#uses=1]
+ %tmp1199 = getelementptr %struct.SECOND_UNION* %tmp1198, i32 0, i32 0 ; <{ i16, i8, i8 }*> [#uses=1]
+ %tmp11991200 = bitcast { i16, i8, i8 }* %tmp1199 to <{ i8, i8, i8, i8 }>* ; <<{ i8, i8, i8, i8 }>*> [#uses=1]
+ %tmp1201 = getelementptr <{ i8, i8, i8, i8 }>* %tmp11991200, i32 0, i32 1 ; <i8*> [#uses=2]
+ %mask1202 = and i8 %mask1194, 1 ; <i8> [#uses=2]
+ %tmp1203 = load i8* %tmp1201, align 1 ; <i8> [#uses=1]
+ %tmp1204 = shl i8 %mask1202, 1 ; <i8> [#uses=1]
+ %tmp1205 = and i8 %tmp1204, 2 ; <i8> [#uses=1]
+ %tmp1206 = and i8 %tmp1203, -3 ; <i8> [#uses=1]
+ %tmp1207 = or i8 %tmp1206, %tmp1205 ; <i8> [#uses=1]
+ store i8 %tmp1207, i8* %tmp1201, align 1
+ %mask1208 = and i8 %mask1202, 1 ; <i8> [#uses=0]
+ %tmp1209 = getelementptr %struct.rec* %tmp1168, i32 0, i32 0 ; <%struct.head_type*> [#uses=1]
+ %tmp12091210 = bitcast %struct.head_type* %tmp1209 to %struct.word_type* ; <%struct.word_type*> [#uses=1]
+ %tmp1211 = getelementptr %struct.word_type* %tmp12091210, i32 0, i32 2 ; <%struct.SECOND_UNION*> [#uses=1]
+ %tmp1212 = getelementptr %struct.SECOND_UNION* %tmp1211, i32 0, i32 0 ; <{ i16, i8, i8 }*> [#uses=1]
+ %tmp12121213 = bitcast { i16, i8, i8 }* %tmp1212 to <{ i8, i8, i8, i8 }>* ; <<{ i8, i8, i8, i8 }>*> [#uses=1]
+ %tmp1214 = getelementptr <{ i8, i8, i8, i8 }>* %tmp12121213, i32 0, i32 1 ; <i8*> [#uses=1]
+ %tmp1215 = load i8* %tmp1214, align 1 ; <i8> [#uses=1]
+ %tmp1216 = shl i8 %tmp1215, 6 ; <i8> [#uses=1]
+ %tmp1217 = lshr i8 %tmp1216, 7 ; <i8> [#uses=1]
+ %mask1218 = and i8 %tmp1217, 1 ; <i8> [#uses=2]
+ %mask1219 = and i8 %mask1218, 1 ; <i8> [#uses=0]
+ %tmp1220 = load %struct.rec** %s, align 4 ; <%struct.rec*> [#uses=1]
+ %tmp1221 = getelementptr %struct.rec* %tmp1220, i32 0, i32 0 ; <%struct.head_type*> [#uses=1]
+ %tmp12211222 = bitcast %struct.head_type* %tmp1221 to %struct.word_type* ; <%struct.word_type*> [#uses=1]
+ %tmp1223 = getelementptr %struct.word_type* %tmp12211222, i32 0, i32 2 ; <%struct.SECOND_UNION*> [#uses=1]
+ %tmp1224 = getelementptr %struct.SECOND_UNION* %tmp1223, i32 0, i32 0 ; <{ i16, i8, i8 }*> [#uses=1]
+ %tmp12241225 = bitcast { i16, i8, i8 }* %tmp1224 to <{ i8, i8, i8, i8 }>* ; <<{ i8, i8, i8, i8 }>*> [#uses=1]
+ %tmp1226 = getelementptr <{ i8, i8, i8, i8 }>* %tmp12241225, i32 0, i32 1 ; <i8*> [#uses=2]
+ %mask1227 = and i8 %mask1218, 1 ; <i8> [#uses=2]
+ %tmp1228 = load i8* %tmp1226, align 1 ; <i8> [#uses=1]
+ %tmp1229 = and i8 %mask1227, 1 ; <i8> [#uses=1]
+ %tmp1230 = and i8 %tmp1228, -2 ; <i8> [#uses=1]
+ %tmp1231 = or i8 %tmp1230, %tmp1229 ; <i8> [#uses=1]
+ store i8 %tmp1231, i8* %tmp1226, align 1
+ %mask1232 = and i8 %mask1227, 1 ; <i8> [#uses=0]
+ br label %bb1233.exitStub
+}
diff --git a/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll b/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll
new file mode 100644
index 0000000..cd2d609
--- /dev/null
+++ b/test/CodeGen/X86/2008-03-10-RegAllocInfLoop.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu -relocation-model=pic -disable-fp-elim
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu -relocation-model=pic -disable-fp-elim -schedule-livein-copies | not grep {Number of register spills}
+; PR2134
+
+declare fastcc i8* @w_addchar(i8*, i32*, i32*, i8 signext ) nounwind
+
+define x86_stdcallcc i32 @parse_backslash(i8** inreg %word, i32* inreg %word_length, i32* inreg %max_length) nounwind {
+entry:
+ %tmp6 = load i8* null, align 1 ; <i8> [#uses=1]
+ br label %bb13
+bb13: ; preds = %entry
+ %tmp26 = call fastcc i8* @w_addchar( i8* null, i32* %word_length, i32* %max_length, i8 signext %tmp6 ) nounwind ; <i8*> [#uses=1]
+ store i8* %tmp26, i8** %word, align 4
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2008-03-12-ThreadLocalAlias.ll b/test/CodeGen/X86/2008-03-12-ThreadLocalAlias.ll
new file mode 100644
index 0000000..e673d31
--- /dev/null
+++ b/test/CodeGen/X86/2008-03-12-ThreadLocalAlias.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -relocation-model=pic | grep TLSGD | count 2
+; PR2137
+
+; ModuleID = '1.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+ %struct.__res_state = type { i32 }
+@__resp = thread_local global %struct.__res_state* @_res ; <%struct.__res_state**> [#uses=1]
+@_res = global %struct.__res_state zeroinitializer, section ".bss" ; <%struct.__res_state*> [#uses=1]
+
+@__libc_resp = hidden alias %struct.__res_state** @__resp ; <%struct.__res_state**> [#uses=2]
+
+define i32 @foo() {
+entry:
+ %retval = alloca i32 ; <i32*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %tmp = load %struct.__res_state** @__libc_resp, align 4 ; <%struct.__res_state*> [#uses=1]
+ %tmp1 = getelementptr %struct.__res_state* %tmp, i32 0, i32 0 ; <i32*> [#uses=1]
+ store i32 0, i32* %tmp1, align 4
+ br label %return
+return: ; preds = %entry
+ %retval2 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval2
+}
+
+define i32 @bar() {
+entry:
+ %retval = alloca i32 ; <i32*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %tmp = load %struct.__res_state** @__libc_resp, align 4 ; <%struct.__res_state*> [#uses=1]
+ %tmp1 = getelementptr %struct.__res_state* %tmp, i32 0, i32 0 ; <i32*> [#uses=1]
+ store i32 1, i32* %tmp1, align 4
+ br label %return
+return: ; preds = %entry
+ %retval2 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval2
+}
diff --git a/test/CodeGen/X86/2008-03-13-TwoAddrPassCrash.ll b/test/CodeGen/X86/2008-03-13-TwoAddrPassCrash.ll
new file mode 100644
index 0000000..c6ba22e
--- /dev/null
+++ b/test/CodeGen/X86/2008-03-13-TwoAddrPassCrash.ll
@@ -0,0 +1,68 @@
+; RUN: llc < %s -march=x86
+
+define i16 @t(i32 %depth) signext nounwind {
+entry:
+ br i1 false, label %bb74, label %bb
+bb: ; preds = %entry
+ ret i16 0
+bb74: ; preds = %entry
+ switch i32 0, label %bail [
+ i32 17, label %bb84
+ i32 18, label %bb81
+ i32 33, label %bb80
+ i32 34, label %bb84
+ ]
+bb80: ; preds = %bb74
+ switch i32 %depth, label %bb103 [
+ i32 16, label %bb96
+ i32 32, label %bb91
+ i32 846624121, label %bb96
+ i32 1094862674, label %bb91
+ i32 1096368963, label %bb91
+ i32 1111970369, label %bb91
+ i32 1278555445, label %bb96
+ i32 1278555701, label %bb96
+ i32 1380401729, label %bb91
+ i32 1668118891, label %bb91
+ i32 1916022840, label %bb91
+ i32 1983131704, label %bb91
+ i32 2037741171, label %bb96
+ i32 2037741173, label %bb96
+ ]
+bb81: ; preds = %bb74
+ ret i16 0
+bb84: ; preds = %bb74, %bb74
+ switch i32 %depth, label %bb103 [
+ i32 16, label %bb96
+ i32 32, label %bb91
+ i32 846624121, label %bb96
+ i32 1094862674, label %bb91
+ i32 1096368963, label %bb91
+ i32 1111970369, label %bb91
+ i32 1278555445, label %bb96
+ i32 1278555701, label %bb96
+ i32 1380401729, label %bb91
+ i32 1668118891, label %bb91
+ i32 1916022840, label %bb91
+ i32 1983131704, label %bb91
+ i32 2037741171, label %bb96
+ i32 2037741173, label %bb96
+ ]
+bb91: ; preds = %bb84, %bb84, %bb84, %bb84, %bb84, %bb84, %bb84, %bb84, %bb80, %bb80, %bb80, %bb80, %bb80, %bb80, %bb80, %bb80
+ %wMB.0.reg2mem.0 = phi i16 [ 16, %bb80 ], [ 16, %bb80 ], [ 16, %bb80 ], [ 16, %bb80 ], [ 16, %bb80 ], [ 16, %bb80 ], [ 16, %bb80 ], [ 16, %bb80 ], [ 0, %bb84 ], [ 0, %bb84 ], [ 0, %bb84 ], [ 0, %bb84 ], [ 0, %bb84 ], [ 0, %bb84 ], [ 0, %bb84 ], [ 0, %bb84 ] ; <i16> [#uses=2]
+ %tmp941478 = shl i16 %wMB.0.reg2mem.0, 2 ; <i16> [#uses=1]
+ br label %bb103
+bb96: ; preds = %bb84, %bb84, %bb84, %bb84, %bb84, %bb84, %bb80, %bb80, %bb80, %bb80, %bb80, %bb80
+ ret i16 0
+bb103: ; preds = %bb91, %bb84, %bb80
+ %wMB.0.reg2mem.2 = phi i16 [ %wMB.0.reg2mem.0, %bb91 ], [ 16, %bb80 ], [ 0, %bb84 ] ; <i16> [#uses=1]
+ %bBump.0 = phi i16 [ %tmp941478, %bb91 ], [ 16, %bb80 ], [ 0, %bb84 ] ; <i16> [#uses=0]
+ br i1 false, label %bb164, label %UnifiedReturnBlock
+bb164: ; preds = %bb103
+ %tmp167168 = sext i16 %wMB.0.reg2mem.2 to i32 ; <i32> [#uses=0]
+ ret i16 0
+bail: ; preds = %bb74
+ ret i16 0
+UnifiedReturnBlock: ; preds = %bb103
+ ret i16 0
+}
diff --git a/test/CodeGen/X86/2008-03-14-SpillerCrash.ll b/test/CodeGen/X86/2008-03-14-SpillerCrash.ll
new file mode 100644
index 0000000..8946415
--- /dev/null
+++ b/test/CodeGen/X86/2008-03-14-SpillerCrash.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu
+; PR2138
+
+ %struct.__locale_struct = type { [13 x %struct.locale_data*], i16*, i32*, i32*, [13 x i8*] }
+ %struct.anon = type { i8* }
+ %struct.locale_data = type { i8*, i8*, i32, i32, { void (%struct.locale_data*)*, %struct.anon }, i32, i32, i32, [0 x %struct.locale_data_value] }
+ %struct.locale_data_value = type { i32* }
+
+@wcstoll_l = alias i64 (i32*, i32**, i32, %struct.__locale_struct*)* @__wcstoll_l ; <i64 (i32*, i32**, i32, %struct.__locale_struct*)*> [#uses=0]
+
+define i64 @____wcstoll_l_internal(i32* %nptr, i32** %endptr, i32 %base, i32 %group, %struct.__locale_struct* %loc) nounwind {
+entry:
+ %tmp27 = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp83 = getelementptr i32* %nptr, i32 1 ; <i32*> [#uses=1]
+ %tmp233 = add i32 0, -48 ; <i32> [#uses=1]
+ br label %bb271.us
+bb271.us: ; preds = %entry
+ br label %bb374.outer
+bb311.split: ; preds = %bb305.us
+ %tmp313 = add i32 %tmp378.us, -48 ; <i32> [#uses=1]
+ br i1 false, label %bb374.outer, label %bb383
+bb327.split: ; preds = %bb314.us
+ ret i64 0
+bb374.outer: ; preds = %bb311.split, %bb271.us
+ %tmp370371552.pn.in = phi i32 [ %tmp233, %bb271.us ], [ %tmp313, %bb311.split ] ; <i32> [#uses=1]
+ %tmp278279.pn = phi i64 [ 0, %bb271.us ], [ %tmp373.reg2mem.0.ph, %bb311.split ] ; <i64> [#uses=1]
+ %s.5.ph = phi i32* [ null, %bb271.us ], [ %tmp376.us, %bb311.split ] ; <i32*> [#uses=1]
+ %tmp366367550.pn = sext i32 %base to i64 ; <i64> [#uses=1]
+ %tmp370371552.pn = zext i32 %tmp370371552.pn.in to i64 ; <i64> [#uses=1]
+ %tmp369551.pn = mul i64 %tmp278279.pn, %tmp366367550.pn ; <i64> [#uses=1]
+ %tmp373.reg2mem.0.ph = add i64 %tmp370371552.pn, %tmp369551.pn ; <i64> [#uses=1]
+ br label %bb374.us
+bb374.us: ; preds = %bb314.us, %bb374.outer
+ %tmp376.us = getelementptr i32* %s.5.ph, i32 0 ; <i32*> [#uses=3]
+ %tmp378.us = load i32* %tmp376.us, align 4 ; <i32> [#uses=2]
+ %tmp302.us = icmp eq i32* %tmp376.us, %tmp83 ; <i1> [#uses=1]
+ %bothcond484.us = or i1 false, %tmp302.us ; <i1> [#uses=1]
+ br i1 %bothcond484.us, label %bb383, label %bb305.us
+bb305.us: ; preds = %bb374.us
+ br i1 false, label %bb311.split, label %bb314.us
+bb314.us: ; preds = %bb305.us
+ %tmp320.us = icmp eq i32 %tmp378.us, %tmp27 ; <i1> [#uses=1]
+ br i1 %tmp320.us, label %bb374.us, label %bb327.split
+bb383: ; preds = %bb374.us, %bb311.split
+ ret i64 0
+}
+
+declare i64 @__wcstoll_l(i32*, i32**, i32, %struct.__locale_struct*) nounwind
diff --git a/test/CodeGen/X86/2008-03-18-CoalescerBug.ll b/test/CodeGen/X86/2008-03-18-CoalescerBug.ll
new file mode 100644
index 0000000..ccc4d75
--- /dev/null
+++ b/test/CodeGen/X86/2008-03-18-CoalescerBug.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim | grep movss | count 1
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim -stats |& grep {Number of re-materialization} | grep 1
+
+ %struct..0objc_object = type opaque
+ %struct.OhBoy = type { }
+ %struct.BooHoo = type { i32 }
+ %struct.objc_selector = type opaque
[email protected] = appending global [1 x i8*] [ i8* bitcast (void (%struct.OhBoy*, %struct.objc_selector*, i32, %struct.BooHoo*)* @"-[MessageHeaderDisplay adjustFontSizeBy:viewingState:]" to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define void @"-[MessageHeaderDisplay adjustFontSizeBy:viewingState:]"(%struct.OhBoy* %self, %struct.objc_selector* %_cmd, i32 %delta, %struct.BooHoo* %viewingState) nounwind {
+entry:
+ %tmp19 = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp24 = tail call float bitcast (void (%struct..0objc_object*, ...)* @objc_msgSend_fpret to float (%struct..0objc_object*, %struct.objc_selector*)*)( %struct..0objc_object* null, %struct.objc_selector* null ) nounwind ; <float> [#uses=2]
+ %tmp30 = icmp sgt i32 %delta, 0 ; <i1> [#uses=1]
+ br i1 %tmp30, label %bb33, label %bb87.preheader
+bb33: ; preds = %entry
+ %tmp28 = fadd float 0.000000e+00, %tmp24 ; <float> [#uses=1]
+ %tmp35 = fcmp ogt float %tmp28, 1.800000e+01 ; <i1> [#uses=1]
+ br i1 %tmp35, label %bb38, label %bb87.preheader
+bb38: ; preds = %bb33
+ %tmp53 = add i32 %tmp19, %delta ; <i32> [#uses=2]
+ br i1 false, label %bb50, label %bb43
+bb43: ; preds = %bb38
+ store i32 %tmp53, i32* null, align 4
+ ret void
+bb50: ; preds = %bb38
+ %tmp56 = fsub float 1.800000e+01, %tmp24 ; <float> [#uses=1]
+ %tmp57 = fcmp ugt float 0.000000e+00, %tmp56 ; <i1> [#uses=1]
+ br i1 %tmp57, label %bb64, label %bb87.preheader
+bb64: ; preds = %bb50
+ ret void
+bb87.preheader: ; preds = %bb50, %bb33, %entry
+ %usableDelta.0 = phi i32 [ %delta, %entry ], [ %delta, %bb33 ], [ %tmp53, %bb50 ] ; <i32> [#uses=1]
+ %tmp100 = tail call %struct..0objc_object* (%struct..0objc_object*, %struct.objc_selector*, ...)* @objc_msgSend( %struct..0objc_object* null, %struct.objc_selector* null, %struct..0objc_object* null ) nounwind ; <%struct..0objc_object*> [#uses=2]
+ %tmp106 = tail call %struct..0objc_object* (%struct..0objc_object*, %struct.objc_selector*, ...)* @objc_msgSend( %struct..0objc_object* %tmp100, %struct.objc_selector* null ) nounwind ; <%struct..0objc_object*> [#uses=0]
+ %umax = select i1 false, i32 1, i32 0 ; <i32> [#uses=1]
+ br label %bb108
+bb108: ; preds = %bb108, %bb87.preheader
+ %attachmentIndex.0.reg2mem.0 = phi i32 [ 0, %bb87.preheader ], [ %indvar.next, %bb108 ] ; <i32> [#uses=2]
+ %tmp114 = tail call %struct..0objc_object* (%struct..0objc_object*, %struct.objc_selector*, ...)* @objc_msgSend( %struct..0objc_object* %tmp100, %struct.objc_selector* null, i32 %attachmentIndex.0.reg2mem.0 ) nounwind ; <%struct..0objc_object*> [#uses=1]
+ %tmp121 = tail call %struct..0objc_object* (%struct..0objc_object*, %struct.objc_selector*, ...)* @objc_msgSend( %struct..0objc_object* %tmp114, %struct.objc_selector* null, i32 %usableDelta.0 ) nounwind ; <%struct..0objc_object*> [#uses=0]
+ %indvar.next = add i32 %attachmentIndex.0.reg2mem.0, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %umax ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb130, label %bb108
+bb130: ; preds = %bb108
+ ret void
+}
+
+declare %struct..0objc_object* @objc_msgSend(%struct..0objc_object*, %struct.objc_selector*, ...)
+
+declare void @objc_msgSend_fpret(%struct..0objc_object*, ...)
diff --git a/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll b/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll
new file mode 100644
index 0000000..eaa883c
--- /dev/null
+++ b/test/CodeGen/X86/2008-03-19-DAGCombinerBug.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86
+
+define i32 @t() nounwind {
+entry:
+ %tmp54 = add i32 0, 1 ; <i32> [#uses=1]
+ br i1 false, label %bb71, label %bb77
+bb71: ; preds = %entry
+ %tmp74 = shl i32 %tmp54, 1 ; <i32> [#uses=1]
+ %tmp76 = ashr i32 %tmp74, 3 ; <i32> [#uses=1]
+ br label %bb77
+bb77: ; preds = %bb71, %entry
+ %payLoadSize.0 = phi i32 [ %tmp76, %bb71 ], [ 0, %entry ] ; <i32> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/X86/2008-03-23-DarwinAsmComments.ll b/test/CodeGen/X86/2008-03-23-DarwinAsmComments.ll
new file mode 100644
index 0000000..4dc3a10
--- /dev/null
+++ b/test/CodeGen/X86/2008-03-23-DarwinAsmComments.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -asm-verbose | grep {#} | not grep -v {##}
+
+ %struct.AGenericCall = type { %struct.AGenericManager*, %struct.ComponentParameters*, i32* }
+ %struct.AGenericManager = type <{ i8 }>
+ %struct.ComponentInstanceRecord = type opaque
+ %struct.ComponentParameters = type { [1 x i64] }
+
+define i32 @_ZN12AGenericCall10MapIDPtrAtEsRP23ComponentInstanceRecord(%struct.AGenericCall* %this, i16 signext %param, %struct.ComponentInstanceRecord** %instance) {
+entry:
+ %tmp4 = icmp slt i16 %param, 0 ; <i1> [#uses=1]
+ br i1 %tmp4, label %cond_true, label %cond_next
+
+cond_true: ; preds = %entry
+ %tmp1415 = shl i16 %param, 3 ; <i16> [#uses=1]
+ %tmp17 = getelementptr %struct.AGenericCall* %this, i32 0, i32 1 ; <%struct.ComponentParameters**> [#uses=1]
+ %tmp18 = load %struct.ComponentParameters** %tmp17, align 8 ; <%struct.ComponentParameters*> [#uses=1]
+ %tmp1920 = bitcast %struct.ComponentParameters* %tmp18 to i8* ; <i8*> [#uses=1]
+ %tmp212223 = sext i16 %tmp1415 to i64 ; <i64> [#uses=1]
+ %tmp24 = getelementptr i8* %tmp1920, i64 %tmp212223 ; <i8*> [#uses=1]
+ %tmp2425 = bitcast i8* %tmp24 to i64* ; <i64*> [#uses=1]
+ %tmp28 = load i64* %tmp2425, align 8 ; <i64> [#uses=1]
+ %tmp2829 = inttoptr i64 %tmp28 to i32* ; <i32*> [#uses=1]
+ %tmp31 = getelementptr %struct.AGenericCall* %this, i32 0, i32 2 ; <i32**> [#uses=1]
+ store i32* %tmp2829, i32** %tmp31, align 8
+ br label %cond_next
+
+cond_next: ; preds = %cond_true, %entry
+ %tmp4243 = shl i16 %param, 3 ; <i16> [#uses=1]
+ %tmp46 = getelementptr %struct.AGenericCall* %this, i32 0, i32 1 ; <%struct.ComponentParameters**> [#uses=1]
+ %tmp47 = load %struct.ComponentParameters** %tmp46, align 8 ; <%struct.ComponentParameters*> [#uses=1]
+ %tmp4849 = bitcast %struct.ComponentParameters* %tmp47 to i8* ; <i8*> [#uses=1]
+ %tmp505152 = sext i16 %tmp4243 to i64 ; <i64> [#uses=1]
+ %tmp53 = getelementptr i8* %tmp4849, i64 %tmp505152 ; <i8*> [#uses=1]
+ %tmp5354 = bitcast i8* %tmp53 to i64* ; <i64*> [#uses=1]
+ %tmp58 = load i64* %tmp5354, align 8 ; <i64> [#uses=1]
+ %tmp59 = icmp eq i64 %tmp58, 0 ; <i1> [#uses=1]
+ br i1 %tmp59, label %UnifiedReturnBlock, label %cond_true63
+
+cond_true63: ; preds = %cond_next
+ %tmp65 = getelementptr %struct.AGenericCall* %this, i32 0, i32 0 ; <%struct.AGenericManager**> [#uses=1]
+ %tmp66 = load %struct.AGenericManager** %tmp65, align 8 ; <%struct.AGenericManager*> [#uses=1]
+ %tmp69 = tail call i32 @_ZN15AGenericManager24DefaultComponentInstanceERP23ComponentInstanceRecord( %struct.AGenericManager* %tmp66, %struct.ComponentInstanceRecord** %instance ) ; <i32> [#uses=1]
+ ret i32 %tmp69
+
+UnifiedReturnBlock: ; preds = %cond_next
+ ret i32 undef
+}
+
+declare i32 @_ZN15AGenericManager24DefaultComponentInstanceERP23ComponentInstanceRecord(%struct.AGenericManager*, %struct.ComponentInstanceRecord**)
diff --git a/test/CodeGen/X86/2008-03-25-TwoAddrPassBug.ll b/test/CodeGen/X86/2008-03-25-TwoAddrPassBug.ll
new file mode 100644
index 0000000..2d868e0
--- /dev/null
+++ b/test/CodeGen/X86/2008-03-25-TwoAddrPassBug.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+
+define void @t() {
+entry:
+ %tmp455 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> < i32 1, i32 0, i32 3, i32 2 > ; <<4 x float>> [#uses=1]
+ %tmp457 = fmul <4 x float> zeroinitializer, %tmp455 ; <<4 x float>> [#uses=2]
+ %tmp461 = shufflevector <4 x float> %tmp457, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
+ %tmp465 = shufflevector <4 x float> %tmp457, <4 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x float>> [#uses=1]
+ %tmp466 = fsub <4 x float> %tmp461, %tmp465 ; <<4 x float>> [#uses=1]
+ %tmp536 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp466, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x float>> [#uses=1]
+ %tmp542 = shufflevector <4 x float> %tmp536, <4 x float> zeroinitializer, <4 x i32> < i32 6, i32 7, i32 2, i32 3 > ; <<4 x float>> [#uses=1]
+ %tmp580 = bitcast <4 x float> %tmp542 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp582 = and <4 x i32> %tmp580, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %tmp591 = or <4 x i32> %tmp582, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %tmp592 = bitcast <4 x i32> %tmp591 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp609 = fdiv <4 x float> < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 >, %tmp592 ; <<4 x float>> [#uses=1]
+ %tmp652 = shufflevector <4 x float> %tmp609, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x float>> [#uses=1]
+ %tmp662 = fmul <4 x float> zeroinitializer, %tmp652 ; <<4 x float>> [#uses=1]
+ %tmp678 = shufflevector <4 x float> %tmp662, <4 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x float>> [#uses=1]
+ %tmp753 = fmul <4 x float> zeroinitializer, %tmp678 ; <<4 x float>> [#uses=1]
+ %tmp754 = fsub <4 x float> zeroinitializer, %tmp753 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp754, <4 x float>* null, align 16
+ unreachable
+}
diff --git a/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll b/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll
new file mode 100644
index 0000000..305968ac
--- /dev/null
+++ b/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -disable-fp-elim | grep add | grep 12 | not grep non_lazy_ptr
+; Don't fold re-materialized load into a two address instruction
+
+ %"struct.Smarts::Runnable" = type { i32 (...)**, i32 }
+ %struct.__sbuf = type { i8*, i32 }
+ %"struct.std::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, %"struct.std::ios_base::_Callback_list"*, %struct.__sbuf, [8 x %struct.__sbuf], i32, %struct.__sbuf*, %"struct.std::locale" }
+ %"struct.std::ios_base::_Callback_list" = type { %"struct.std::ios_base::_Callback_list"*, void (i32, %"struct.std::ios_base"*, i32)*, i32, i32 }
+ %"struct.std::locale" = type { %"struct.std::locale::_Impl"* }
+ %"struct.std::locale::_Impl" = type { i32, %"struct.Smarts::Runnable"**, i32, %"struct.Smarts::Runnable"**, i8** }
+@_ZTVSt9basic_iosIcSt11char_traitsIcEE = external constant [4 x i32 (...)*] ; <[4 x i32 (...)*]*> [#uses=1]
+@_ZTTSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE = external constant [4 x i8*] ; <[4 x i8*]*> [#uses=1]
+@_ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE = external constant [10 x i32 (...)*] ; <[10 x i32 (...)*]*> [#uses=2]
+@_ZTVSt15basic_streambufIcSt11char_traitsIcEE = external constant [16 x i32 (...)*] ; <[16 x i32 (...)*]*> [#uses=1]
+@_ZTVSt15basic_stringbufIcSt11char_traitsIcESaIcEE = external constant [16 x i32 (...)*] ; <[16 x i32 (...)*]*> [#uses=1]
+
+define void @_GLOBAL__I__ZN5Pooma5pinfoE() nounwind {
+entry:
+ store i32 (...)** getelementptr ([10 x i32 (...)*]* @_ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i32 8), i32 (...)*** null, align 4
+ %tmp96.i.i142.i = call i8* @_Znwm( i32 180 ) nounwind ; <i8*> [#uses=2]
+ call void @_ZNSt8ios_baseC2Ev( %"struct.std::ios_base"* null ) nounwind
+ store i32 (...)** getelementptr ([4 x i32 (...)*]* @_ZTVSt9basic_iosIcSt11char_traitsIcEE, i32 0, i32 2), i32 (...)*** null, align 4
+ store i32 (...)** null, i32 (...)*** null, align 4
+ %ctg2242.i.i163.i = getelementptr i8* %tmp96.i.i142.i, i32 0 ; <i8*> [#uses=1]
+ %tmp150.i.i164.i = load i8** getelementptr ([4 x i8*]* @_ZTTSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i64 2), align 4 ; <i8*> [#uses=1]
+ %tmp150151.i.i165.i = bitcast i8* %tmp150.i.i164.i to i32 (...)** ; <i32 (...)**> [#uses=1]
+ %tmp153.i.i166.i = bitcast i8* %ctg2242.i.i163.i to i32 (...)*** ; <i32 (...)***> [#uses=1]
+ store i32 (...)** %tmp150151.i.i165.i, i32 (...)*** %tmp153.i.i166.i, align 4
+ %tmp159.i.i167.i = bitcast i8* %tmp96.i.i142.i to i32 (...)*** ; <i32 (...)***> [#uses=1]
+ store i32 (...)** getelementptr ([10 x i32 (...)*]* @_ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i32 3), i32 (...)*** %tmp159.i.i167.i, align 4
+ store i32 (...)** getelementptr ([16 x i32 (...)*]* @_ZTVSt15basic_streambufIcSt11char_traitsIcEE, i32 0, i32 2), i32 (...)*** null, align 4
+ call void @_ZNSt6localeC1Ev( %"struct.std::locale"* null ) nounwind
+ store i32 (...)** getelementptr ([16 x i32 (...)*]* @_ZTVSt15basic_stringbufIcSt11char_traitsIcESaIcEE, i32 0, i32 2), i32 (...)*** null, align 4
+ unreachable
+}
+
+declare i8* @_Znwm(i32)
+
+declare void @_ZNSt8ios_baseC2Ev(%"struct.std::ios_base"*)
+
+declare void @_ZNSt6localeC1Ev(%"struct.std::locale"*) nounwind
diff --git a/test/CodeGen/X86/2008-04-02-unnamedEH.ll b/test/CodeGen/X86/2008-04-02-unnamedEH.ll
new file mode 100644
index 0000000..27bbbaa
--- /dev/null
+++ b/test/CodeGen/X86/2008-04-02-unnamedEH.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+
+define void @_Z3bazv() {
+ call void @0( ) ; <i32>:1 [#uses=0]
+ ret void
+}
+
+define internal void @""() {
+ call i32 @_Z3barv( ) ; <i32>:4 [#uses=1]
+ ret void
+}
+; CHECK: unnamed_1.eh
+
+declare i32 @_Z3barv()
diff --git a/test/CodeGen/X86/2008-04-08-CoalescerCrash.ll b/test/CodeGen/X86/2008-04-08-CoalescerCrash.ll
new file mode 100644
index 0000000..dc8c097
--- /dev/null
+++ b/test/CodeGen/X86/2008-04-08-CoalescerCrash.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx
+
+define i32 @t2() nounwind {
+entry:
+ tail call void asm sideeffect "# top of block", "~{dirflag},~{fpsr},~{flags},~{di},~{si},~{dx},~{cx},~{ax}"( ) nounwind
+ tail call void asm sideeffect ".file \224443946.c\22", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
+ tail call void asm sideeffect ".line 8", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
+ %tmp1 = tail call <2 x i32> asm sideeffect "movd $1, $0", "=={mm4},{bp},~{dirflag},~{fpsr},~{flags},~{memory}"( i32 undef ) nounwind ; <<2 x i32>> [#uses=1]
+ tail call void asm sideeffect ".file \224443946.c\22", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
+ tail call void asm sideeffect ".line 9", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
+ %tmp3 = tail call i32 asm sideeffect "movd $1, $0", "=={bp},{mm3},~{dirflag},~{fpsr},~{flags},~{memory}"( <2 x i32> undef ) nounwind ; <i32> [#uses=1]
+ tail call void asm sideeffect ".file \224443946.c\22", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
+ tail call void asm sideeffect ".line 10", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
+ tail call void asm sideeffect "movntq $0, 0($1,$2)", "{mm0},{di},{bp},~{dirflag},~{fpsr},~{flags},~{memory}"( <2 x i32> undef, i32 undef, i32 %tmp3 ) nounwind
+ tail call void asm sideeffect ".file \224443946.c\22", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
+ tail call void asm sideeffect ".line 11", "~{dirflag},~{fpsr},~{flags}"( ) nounwind
+ %tmp8 = tail call i32 asm sideeffect "movd $1, $0", "=={bp},{mm4},~{dirflag},~{fpsr},~{flags},~{memory}"( <2 x i32> %tmp1 ) nounwind ; <i32> [#uses=0]
+ ret i32 undef
+}
diff --git a/test/CodeGen/X86/2008-04-09-BranchFolding.ll b/test/CodeGen/X86/2008-04-09-BranchFolding.ll
new file mode 100644
index 0000000..41fbdd19
--- /dev/null
+++ b/test/CodeGen/X86/2008-04-09-BranchFolding.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -march=x86 | not grep jmp
+
+ %struct..0anon = type { i32 }
+ %struct.binding_level = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.binding_level*, i8, i8, i8, i8, i8, i32, %struct.tree_node* }
+ %struct.lang_decl = type opaque
+ %struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] }
+ %struct.tree_decl = type { [12 x i8], i8*, i32, %struct.tree_node*, i32, i8, i8, i8, i8, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct..0anon, { %struct.rtx_def* }, %struct.tree_node*, %struct.lang_decl* }
+ %struct.tree_node = type { %struct.tree_decl }
+
+define fastcc %struct.tree_node* @pushdecl(%struct.tree_node* %x) nounwind {
+entry:
+ %tmp3.i40 = icmp eq %struct.binding_level* null, null ; <i1> [#uses=2]
+ br i1 false, label %bb143, label %bb140
+bb140: ; preds = %entry
+ br i1 %tmp3.i40, label %bb160, label %bb17.i
+bb17.i: ; preds = %bb140
+ ret %struct.tree_node* null
+bb143: ; preds = %entry
+ %tmp8.i43 = load %struct.tree_node** null, align 4 ; <%struct.tree_node*> [#uses=1]
+ br i1 %tmp3.i40, label %bb160, label %bb9.i48
+bb9.i48: ; preds = %bb143
+ ret %struct.tree_node* null
+bb160: ; preds = %bb143, %bb140
+ %t.0.reg2mem.0 = phi %struct.tree_node* [ null, %bb140 ], [ %tmp8.i43, %bb143 ] ; <%struct.tree_node*> [#uses=1]
+ %tmp162 = icmp eq %struct.tree_node* %t.0.reg2mem.0, null ; <i1> [#uses=2]
+ br i1 %tmp162, label %bb174, label %bb165
+bb165: ; preds = %bb160
+ br label %bb174
+bb174: ; preds = %bb165, %bb160
+ %line.0 = phi i32 [ 0, %bb165 ], [ undef, %bb160 ] ; <i32> [#uses=1]
+ %file.0 = phi i8* [ null, %bb165 ], [ undef, %bb160 ] ; <i8*> [#uses=1]
+ br i1 %tmp162, label %bb344, label %bb73.i
+bb73.i: ; preds = %bb174
+ br i1 false, label %bb226.i, label %bb220.i
+bb220.i: ; preds = %bb73.i
+ ret %struct.tree_node* null
+bb226.i: ; preds = %bb73.i
+ br i1 false, label %bb260, label %bb273.i
+bb273.i: ; preds = %bb226.i
+ ret %struct.tree_node* null
+bb260: ; preds = %bb226.i
+ tail call void (i8*, i32, ...)* @pedwarn_with_file_and_line( i8* %file.0, i32 %line.0, i8* null ) nounwind
+ ret %struct.tree_node* null
+bb344: ; preds = %bb174
+ ret %struct.tree_node* null
+}
+
+declare void @pedwarn_with_file_and_line(i8*, i32, ...) nounwind
diff --git a/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll b/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
new file mode 100644
index 0000000..2aea9c5
--- /dev/null
+++ b/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local
+; PR5534
+
+ %struct.CGPoint = type { double, double }
+ %struct.NSArray = type { %struct.NSObject }
+ %struct.NSAssertionHandler = type { %struct.NSObject, i8* }
+ %struct.NSDockTile = type { %struct.NSObject, %struct.NSObject*, i8*, %struct.NSView*, %struct.NSView*, %struct.NSView*, %struct.NSArray*, %struct._SPFlags, %struct.CGPoint, [5 x %struct.NSObject*] }
+ %struct.NSDocument = type { %struct.NSObject, %struct.NSWindow*, %struct.NSObject*, %struct.NSURL*, %struct.NSArray*, %struct.NSPrintInfo*, i64, %struct.NSView*, %struct.NSObject*, %struct.NSObject*, %struct.NSUndoManager*, %struct._BCFlags2, %struct.NSArray* }
+ %struct.AA = type { %struct.NSObject, %struct.NSDocument*, %struct.NSURL*, %struct.NSArray*, %struct.NSArray* }
+ %struct.NSError = type { %struct.NSObject, i8*, i64, %struct.NSArray*, %struct.NSArray* }
+ %struct.NSImage = type { %struct.NSObject, %struct.NSArray*, %struct.CGPoint, %struct._BCFlags2, %struct.NSObject*, %struct._NSImageAuxiliary* }
+ %struct.NSMutableArray = type { %struct.NSArray }
+ %struct.NSObject = type { %struct.NSObject* }
+ %struct.NSPrintInfo = type { %struct.NSObject, %struct.NSMutableArray*, %struct.NSObject* }
+ %struct.NSRect = type { %struct.CGPoint, %struct.CGPoint }
+ %struct.NSRegion = type opaque
+ %struct.NSResponder = type { %struct.NSObject, %struct.NSObject* }
+ %struct.NSToolbar = type { %struct.NSObject, %struct.NSArray*, %struct.NSMutableArray*, %struct.NSMutableArray*, %struct.NSArray*, %struct.NSObject*, %struct.NSArray*, i8*, %struct.NSObject*, %struct.NSWindow*, %struct.NSObject*, %struct.NSObject*, i64, %struct._BCFlags2, i64, %struct.NSObject* }
+ %struct.NSURL = type { %struct.NSObject, %struct.NSArray*, %struct.NSURL*, i8*, i8* }
+ %struct.NSUndoManager = type { %struct.NSObject, %struct.NSObject*, %struct.NSObject*, %struct.NSArray*, i64, %struct._SPFlags, %struct.NSObject*, i8*, i8*, i8* }
+ %struct.NSView = type { %struct.NSResponder, %struct.NSRect, %struct.NSRect, %struct.NSObject*, %struct.NSObject*, %struct.NSWindow*, %struct.NSObject*, %struct.NSObject*, %struct.NSObject*, %struct.NSObject*, %struct._NSViewAuxiliary*, %struct._BCFlags, %struct._SPFlags }
+ %struct.NSWindow = type { %struct.NSResponder, %struct.NSRect, %struct.NSObject*, %struct.NSObject*, %struct.NSResponder*, %struct.NSView*, %struct.NSView*, %struct.NSObject*, %struct.NSObject*, i32, i64, i32, %struct.NSArray*, %struct.NSObject*, i8, i8, i8, i8, i8*, i8*, %struct.NSImage*, i32, %struct.NSMutableArray*, %struct.NSURL*, %struct.CGPoint*, %struct.NSArray*, %struct.NSArray*, %struct.__wFlags, %struct.NSObject*, %struct.NSView*, %struct.NSWindowAuxiliary* }
+ %struct.NSWindowAuxiliary = type { %struct.NSObject, %struct.NSArray*, %struct.NSDockTile*, %struct._NSWindowAnimator*, %struct.NSRect, i32, %struct.NSAssertionHandler*, %struct.NSUndoManager*, %struct.NSWindowController*, %struct.NSAssertionHandler*, %struct.NSObject*, i32, %struct.__CFRunLoopObserver*, %struct.__CFRunLoopObserver*, %struct.NSArray*, %struct.NSArray*, %struct.NSView*, %struct.NSRegion*, %struct.NSWindow*, %struct.NSWindow*, %struct.NSArray*, %struct.NSMutableArray*, %struct.NSArray*, %struct.NSWindow*, %struct.CGPoint, %struct.NSObject*, i8*, i8*, i32, %struct.NSObject*, %struct.NSArray*, double, %struct.CGPoint, %struct.NSArray*, %struct.NSMutableArray*, %struct.NSMutableArray*, %struct.NSWindow*, %struct.NSView*, %struct.NSArray*, %struct.__auxWFlags, i32, i8*, double, %struct.NSObject*, %struct.NSObject*, %struct.__CFArray*, %struct.NSRegion*, %struct.NSArray*, %struct.NSRect, %struct.NSToolbar*, %struct.NSRect, %struct.NSMutableArray* }
+ %struct.NSWindowController = type { %struct.NSResponder, %struct.NSWindow*, %struct.NSArray*, %struct.NSDocument*, %struct.NSArray*, %struct.NSObject*, %struct._SPFlags, %struct.NSArray*, %struct.NSObject* }
+ %struct._BCFlags = type <{ i8, i8, i8, i8 }>
+ %struct._BCFlags2 = type <{ i8, [3 x i8] }>
+ %struct._NSImageAuxiliary = type opaque
+ %struct._NSViewAuxiliary = type opaque
+ %struct._NSWindowAnimator = type opaque
+ %struct._SPFlags = type <{ i32 }>
+ %struct.__CFArray = type opaque
+ %struct.__CFRunLoopObserver = type opaque
+ %struct.__auxWFlags = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i16 }
+ %struct.__wFlags = type <{ i8, i8, i8, i8, i8, i8, i8, i8 }>
+ %struct._message_ref_t = type { %struct.NSObject* (%struct.NSObject*, %struct._message_ref_t*, ...)*, %struct.objc_selector* }
+ %struct.objc_selector = type opaque
+@"\01L_OBJC_MESSAGE_REF_228" = internal global %struct._message_ref_t zeroinitializer ; <%struct._message_ref_t*> [#uses=1]
[email protected] = appending global [1 x i8*] [ i8* bitcast (void (%struct.AA*, %struct._message_ref_t*, %struct.NSError*, i64, %struct.NSObject*, %struct.objc_selector*, i8*)* @"-[AA BB:optionIndex:delegate:CC:contextInfo:]" to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define void @"-[AA BB:optionIndex:delegate:CC:contextInfo:]"(%struct.AA* %self, %struct._message_ref_t* %_cmd, %struct.NSError* %inError, i64 %inOptionIndex, %struct.NSObject* %inDelegate, %struct.objc_selector* %inDidRecoverSelector, i8* %inContextInfo) {
+entry:
+ %tmp105 = load %struct.NSArray** null, align 8 ; <%struct.NSArray*> [#uses=1]
+ %tmp107 = load %struct.NSObject** null, align 8 ; <%struct.NSObject*> [#uses=1]
+ call void null( %struct.NSObject* %tmp107, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_228", %struct.NSArray* %tmp105, i8 signext 0 )
+ %tmp111 = call %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...)* @objc_msgSend( %struct.NSObject* null, %struct.objc_selector* null, i32 0, i8* null ) ; <%struct.NSObject*> [#uses=0]
+ ret void
+}
+
+declare %struct.NSObject* @objc_msgSend(%struct.NSObject*, %struct.objc_selector*, ...)
diff --git a/test/CodeGen/X86/2008-04-16-CoalescerBug.ll b/test/CodeGen/X86/2008-04-16-CoalescerBug.ll
new file mode 100644
index 0000000..3ccc0fe
--- /dev/null
+++ b/test/CodeGen/X86/2008-04-16-CoalescerBug.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=x86
+
+define void @Hubba(i8* %saveunder, i32 %firstBlob, i32 %select) nounwind {
+entry:
+ br i1 false, label %bb53.us, label %bb53
+bb53.us: ; preds = %bb94.us, %bb53.us, %entry
+ switch i8 1, label %bb71.us [
+ i8 0, label %bb53.us
+ i8 1, label %bb94.us
+ ]
+bb94.us: ; preds = %bb71.us, %bb53.us
+ %result.0.us = phi i32 [ %tmp93.us, %bb71.us ], [ 0, %bb53.us ] ; <i32> [#uses=2]
+ %tmp101.us = lshr i32 %result.0.us, 3 ; <i32> [#uses=1]
+ %result.0163.us = trunc i32 %result.0.us to i16 ; <i16> [#uses=2]
+ shl i16 %result.0163.us, 7 ; <i16>:0 [#uses=1]
+ %tmp106.us = and i16 %0, -1024 ; <i16> [#uses=1]
+ shl i16 %result.0163.us, 2 ; <i16>:1 [#uses=1]
+ %tmp109.us = and i16 %1, -32 ; <i16> [#uses=1]
+ %tmp111112.us = trunc i32 %tmp101.us to i16 ; <i16> [#uses=1]
+ %tmp110.us = or i16 %tmp109.us, %tmp111112.us ; <i16> [#uses=1]
+ %tmp113.us = or i16 %tmp110.us, %tmp106.us ; <i16> [#uses=1]
+ store i16 %tmp113.us, i16* null, align 2
+ br label %bb53.us
+bb71.us: ; preds = %bb53.us
+ %tmp80.us = load i8* null, align 1 ; <i8> [#uses=1]
+ %tmp8081.us = zext i8 %tmp80.us to i32 ; <i32> [#uses=1]
+ %tmp87.us = mul i32 %tmp8081.us, 0 ; <i32> [#uses=1]
+ %tmp92.us = add i32 0, %tmp87.us ; <i32> [#uses=1]
+ %tmp93.us = udiv i32 %tmp92.us, 255 ; <i32> [#uses=1]
+ br label %bb94.us
+bb53: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2008-04-16-ReMatBug.ll b/test/CodeGen/X86/2008-04-16-ReMatBug.ll
new file mode 100644
index 0000000..6e8891b
--- /dev/null
+++ b/test/CodeGen/X86/2008-04-16-ReMatBug.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep movw | not grep {, %e}
+
+ %struct.DBC_t = type { i32, i8*, i16, %struct.DBC_t*, i8*, i8*, i8*, i8*, i8*, %struct.DBC_t*, i32, i32, i32, i32, i8*, i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16, i32*, i8, i16, %struct.DRVOPT*, i16 }
+ %struct.DRVOPT = type { i16, i32, i8, %struct.DRVOPT* }
+ %struct.GENV_t = type { i32, i8*, i16, i8*, i8*, i32, i32, i32, i32, %struct.DBC_t*, i16 }
+ %struct.pthread_mutex_t = type { i32, [40 x i8] }
+@iodbcdm_global_lock = external global %struct.pthread_mutex_t ; <%struct.pthread_mutex_t*> [#uses=1]
+
+define i16 @SQLDriversW(i8* %henv, i16 zeroext %fDir, i32* %szDrvDesc, i16 signext %cbDrvDescMax, i16* %pcbDrvDesc, i32* %szDrvAttr, i16 signext %cbDrvAttrMax, i16* %pcbDrvAttr) signext nounwind {
+entry:
+ %tmp12 = bitcast i8* %henv to %struct.GENV_t* ; <%struct.GENV_t*> [#uses=1]
+ br i1 true, label %bb28, label %bb
+bb: ; preds = %entry
+ ret i16 0
+bb28: ; preds = %entry
+ br i1 false, label %bb37, label %done
+bb37: ; preds = %bb28
+ %tmp46 = getelementptr %struct.GENV_t* %tmp12, i32 0, i32 10 ; <i16*> [#uses=1]
+ store i16 0, i16* %tmp46, align 4
+ br i1 false, label %bb74, label %bb92
+bb74: ; preds = %bb37
+ br label %bb92
+bb92: ; preds = %bb74, %bb37
+ %tmp95180 = shl i16 %cbDrvAttrMax, 2 ; <i16> [#uses=1]
+ %tmp100178 = shl i16 %cbDrvDescMax, 2 ; <i16> [#uses=1]
+ %tmp113 = tail call i16 @SQLDrivers_Internal( i8* %henv, i16 zeroext %fDir, i8* null, i16 signext %tmp100178, i16* %pcbDrvDesc, i8* null, i16 signext %tmp95180, i16* %pcbDrvAttr, i8 zeroext 87 ) signext nounwind ; <i16> [#uses=1]
+ br i1 false, label %done, label %bb137
+bb137: ; preds = %bb92
+ ret i16 0
+done: ; preds = %bb92, %bb28
+ %retcode.0 = phi i16 [ -2, %bb28 ], [ %tmp113, %bb92 ] ; <i16> [#uses=2]
+ br i1 false, label %bb167, label %bb150
+bb150: ; preds = %done
+ %tmp157158 = sext i16 %retcode.0 to i32 ; <i32> [#uses=1]
+ tail call void @trace_SQLDriversW( i32 1, i32 %tmp157158, i8* %henv, i16 zeroext %fDir, i32* %szDrvDesc, i16 signext %cbDrvDescMax, i16* %pcbDrvDesc, i32* %szDrvAttr, i16 signext %cbDrvAttrMax, i16* %pcbDrvAttr ) nounwind
+ ret i16 0
+bb167: ; preds = %done
+ %tmp168 = tail call i32 @pthread_mutex_unlock( %struct.pthread_mutex_t* @iodbcdm_global_lock ) nounwind ; <i32> [#uses=0]
+ ret i16 %retcode.0
+}
+
+declare i32 @pthread_mutex_unlock(%struct.pthread_mutex_t*)
+
+declare i16 @SQLDrivers_Internal(i8*, i16 zeroext , i8*, i16 signext , i16*, i8*, i16 signext , i16*, i8 zeroext ) signext nounwind
+
+declare void @trace_SQLDriversW(i32, i32, i8*, i16 zeroext , i32*, i16 signext , i16*, i32*, i16 signext , i16*)
diff --git a/test/CodeGen/X86/2008-04-17-CoalescerBug.ll b/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
new file mode 100644
index 0000000..ac48285
--- /dev/null
+++ b/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
@@ -0,0 +1,171 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep xorl | grep {%e}
+; Make sure xorl operands are 32-bit registers.
+
+ %struct.tm = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8* }
+ %struct.wxDateTime = type { %struct.wxLongLong }
+ %"struct.wxDateTime::TimeZone" = type { i32 }
+ %struct.wxLongLong = type { i64 }
+ %struct.wxString = type { %struct.wxStringBase }
+ %struct.wxStringBase = type { i32* }
[email protected] = external constant [27 x i32] ; <[27 x i32]*> [#uses=1]
[email protected] = external constant [14 x i32] ; <[14 x i32]*> [#uses=1]
+@_ZZNK10wxDateTime5GetTmERKNS_8TimeZoneEE12__FUNCTION__ = external constant [6 x i8] ; <[6 x i8]*> [#uses=1]
[email protected] = external constant [29 x i32] ; <[29 x i32]*> [#uses=1]
[email protected] = external constant [5 x i32] ; <[5 x i32]*> [#uses=1]
+
+define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(%struct.wxString* noalias sret %agg.result, %struct.wxDateTime* %this, i32* %format, %"struct.wxDateTime::TimeZone"* %tz, i1 %foo) {
+entry:
+ br i1 %foo, label %bb116.i, label %bb115.critedge.i
+bb115.critedge.i: ; preds = %entry
+ ret void
+bb116.i: ; preds = %entry
+ br i1 %foo, label %bb52.i.i, label %bb3118
+bb3118: ; preds = %bb116.i
+ ret void
+bb52.i.i: ; preds = %bb116.i
+ br i1 %foo, label %bb142.i, label %bb115.critedge.i.i
+bb115.critedge.i.i: ; preds = %bb52.i.i
+ ret void
+bb142.i: ; preds = %bb52.i.i
+ br i1 %foo, label %bb161.i, label %bb182.i
+bb161.i: ; preds = %bb142.i
+ br label %bb3261
+bb182.i: ; preds = %bb142.i
+ ret void
+bb3261: ; preds = %bb7834, %bb161.i
+ %tmp3263 = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp3264 = icmp eq i32 %tmp3263, 37 ; <i1> [#uses=1]
+ br i1 %tmp3264, label %bb3306, label %bb3267
+bb3267: ; preds = %bb3261
+ ret void
+bb3306: ; preds = %bb3261
+ %tmp3310 = invoke %struct.wxStringBase* @_ZN12wxStringBaseaSEPKw( %struct.wxStringBase* null, i32* getelementptr ([5 x i32]* @.str89, i32 0, i32 0) )
+ to label %bb3314 unwind label %lpad ; <%struct.wxStringBase*> [#uses=0]
+bb3314: ; preds = %bb3306
+ %tmp3316 = load i32* null, align 4 ; <i32> [#uses=1]
+ switch i32 %tmp3316, label %bb7595 [
+ i32 0, label %bb7819
+ i32 37, label %bb7806
+ i32 66, label %bb3477
+ i32 72, label %bb5334
+ i32 73, label %bb5484
+ i32 77, label %bb6118
+ i32 83, label %bb6406
+ i32 85, label %bb6556
+ i32 87, label %bb6708
+ i32 89, label %bb7308
+ i32 98, label %bb3477
+ i32 99, label %bb3626
+ i32 100, label %bb5184
+ i32 106, label %bb5657
+ i32 108, label %bb5809
+ i32 109, label %bb5968
+ i32 119, label %bb6860
+ i32 120, label %bb3626
+ i32 121, label %bb7158
+ ]
+bb3477: ; preds = %bb3314, %bb3314
+ ret void
+bb3626: ; preds = %bb3314, %bb3314
+ ret void
+bb5184: ; preds = %bb3314
+ ret void
+bb5334: ; preds = %bb3314
+ ret void
+bb5484: ; preds = %bb3314
+ ret void
+bb5657: ; preds = %bb3314
+ %tmp5661 = invoke i16 @_ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE( %struct.wxDateTime* %this, %"struct.wxDateTime::TimeZone"* %tz ) zeroext
+ to label %invcont5660 unwind label %lpad ; <i16> [#uses=0]
+invcont5660: ; preds = %bb5657
+ ret void
+bb5809: ; preds = %bb3314
+ %tmp61.i.i8486 = icmp sgt i64 0, -1 ; <i1> [#uses=1]
+ %tmp95.i.i8490 = icmp slt i64 0, 2147483647000 ; <i1> [#uses=1]
+ %bothcond9308 = and i1 %tmp61.i.i8486, %tmp95.i.i8490 ; <i1> [#uses=1]
+ br i1 %bothcond9308, label %bb91.i8504, label %bb115.critedge.i.i8492
+bb115.critedge.i.i8492: ; preds = %bb5809
+ ret void
+bb91.i8504: ; preds = %bb5809
+ br i1 %foo, label %bb155.i8541, label %bb182.i8560
+bb155.i8541: ; preds = %bb91.i8504
+ %tmp156.i85398700 = invoke %struct.tm* @gmtime_r( i32* null, %struct.tm* null )
+ to label %bb182.i8560 unwind label %lpad ; <%struct.tm*> [#uses=1]
+bb182.i8560: ; preds = %bb155.i8541, %bb91.i8504
+ %tm48.0.i8558 = phi %struct.tm* [ null, %bb91.i8504 ], [ %tmp156.i85398700, %bb155.i8541 ] ; <%struct.tm*> [#uses=0]
+ br i1 %foo, label %bb278.i8617, label %bb187.i8591
+bb187.i8591: ; preds = %bb182.i8560
+ %tmp245.i8588 = srem i64 0, 86400000 ; <i64> [#uses=1]
+ br i1 %foo, label %bb264.i8592, label %bb265.i8606
+bb264.i8592: ; preds = %bb187.i8591
+ ret void
+bb265.i8606: ; preds = %bb187.i8591
+ %tmp268269.i8593 = trunc i64 %tmp245.i8588 to i32 ; <i32> [#uses=1]
+ %tmp273.i8594 = srem i32 %tmp268269.i8593, 1000 ; <i32> [#uses=1]
+ %tmp273274.i8595 = trunc i32 %tmp273.i8594 to i16 ; <i16> [#uses=1]
+ br label %invcont5814
+bb278.i8617: ; preds = %bb182.i8560
+ %timeOnly50.0.i8622 = add i32 0, 0 ; <i32> [#uses=1]
+ br i1 %foo, label %bb440.i8663, label %bb448.i8694
+bb440.i8663: ; preds = %bb278.i8617
+ invoke void @_Z10wxOnAssertPKwiPKcS0_S0_( i32* getelementptr ([27 x i32]* @.str, i32 0, i32 0), i32 1717, i8* getelementptr ([6 x i8]* @_ZZNK10wxDateTime5GetTmERKNS_8TimeZoneEE12__FUNCTION__, i32 0, i32 0), i32* getelementptr ([29 x i32]* @.str33, i32 0, i32 0), i32* getelementptr ([14 x i32]* @.str4, i32 0, i32 0) )
+ to label %bb448.i8694 unwind label %lpad
+bb448.i8694: ; preds = %bb440.i8663, %bb278.i8617
+ %tmp477.i8669 = srem i32 %timeOnly50.0.i8622, 1000 ; <i32> [#uses=1]
+ %tmp477478.i8670 = trunc i32 %tmp477.i8669 to i16 ; <i16> [#uses=1]
+ br label %invcont5814
+invcont5814: ; preds = %bb448.i8694, %bb265.i8606
+ %tmp812.0.0 = phi i16 [ %tmp477478.i8670, %bb448.i8694 ], [ %tmp273274.i8595, %bb265.i8606 ] ; <i16> [#uses=1]
+ %tmp58165817 = zext i16 %tmp812.0.0 to i32 ; <i32> [#uses=1]
+ invoke void (%struct.wxString*, i32*, ...)* @_ZN8wxString6FormatEPKwz( %struct.wxString* noalias sret null, i32* null, i32 %tmp58165817 )
+ to label %invcont5831 unwind label %lpad
+invcont5831: ; preds = %invcont5814
+ %tmp5862 = invoke i8 @_ZN12wxStringBase10ConcatSelfEmPKwm( %struct.wxStringBase* null, i32 0, i32* null, i32 0 ) zeroext
+ to label %bb7834 unwind label %lpad8185 ; <i8> [#uses=0]
+bb5968: ; preds = %bb3314
+ invoke void (%struct.wxString*, i32*, ...)* @_ZN8wxString6FormatEPKwz( %struct.wxString* noalias sret null, i32* null, i32 0 )
+ to label %invcont5981 unwind label %lpad
+invcont5981: ; preds = %bb5968
+ ret void
+bb6118: ; preds = %bb3314
+ ret void
+bb6406: ; preds = %bb3314
+ ret void
+bb6556: ; preds = %bb3314
+ ret void
+bb6708: ; preds = %bb3314
+ ret void
+bb6860: ; preds = %bb3314
+ ret void
+bb7158: ; preds = %bb3314
+ ret void
+bb7308: ; preds = %bb3314
+ ret void
+bb7595: ; preds = %bb3314
+ ret void
+bb7806: ; preds = %bb3314
+ %tmp7814 = invoke %struct.wxStringBase* @_ZN12wxStringBase6appendEmw( %struct.wxStringBase* null, i32 1, i32 0 )
+ to label %bb7834 unwind label %lpad ; <%struct.wxStringBase*> [#uses=0]
+bb7819: ; preds = %bb3314
+ ret void
+bb7834: ; preds = %bb7806, %invcont5831
+ br label %bb3261
+lpad: ; preds = %bb7806, %bb5968, %invcont5814, %bb440.i8663, %bb155.i8541, %bb5657, %bb3306
+ ret void
+lpad8185: ; preds = %invcont5831
+ ret void
+}
+
+declare void @_Z10wxOnAssertPKwiPKcS0_S0_(i32*, i32, i8*, i32*, i32*)
+
+declare i8 @_ZN12wxStringBase10ConcatSelfEmPKwm(%struct.wxStringBase*, i32, i32*, i32) zeroext
+
+declare %struct.tm* @gmtime_r(i32*, %struct.tm*)
+
+declare i16 @_ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE(%struct.wxDateTime*, %"struct.wxDateTime::TimeZone"*) zeroext
+
+declare %struct.wxStringBase* @_ZN12wxStringBase6appendEmw(%struct.wxStringBase*, i32, i32)
+
+declare %struct.wxStringBase* @_ZN12wxStringBaseaSEPKw(%struct.wxStringBase*, i32*)
+
+declare void @_ZN8wxString6FormatEPKwz(%struct.wxString* noalias sret , i32*, ...)
diff --git a/test/CodeGen/X86/2008-04-24-MemCpyBug.ll b/test/CodeGen/X86/2008-04-24-MemCpyBug.ll
new file mode 100644
index 0000000..6389267
--- /dev/null
+++ b/test/CodeGen/X86/2008-04-24-MemCpyBug.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 | not grep 120
+; Don't accidentally add the offset twice for trailing bytes.
+
+ %struct.S63 = type { [63 x i8] }
+@g1s63 = external global %struct.S63 ; <%struct.S63*> [#uses=1]
+
+declare void @test63(%struct.S63* byval align 4 ) nounwind
+
+define void @testit63_entry_2E_ce() nounwind {
+ tail call void @test63( %struct.S63* byval align 4 @g1s63 ) nounwind
+ ret void
+}
diff --git a/test/CodeGen/X86/2008-04-24-pblendw-fold-crash.ll b/test/CodeGen/X86/2008-04-24-pblendw-fold-crash.ll
new file mode 100644
index 0000000..4eaca17c
--- /dev/null
+++ b/test/CodeGen/X86/2008-04-24-pblendw-fold-crash.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mattr=+sse41
+; rdar://5886601
+; gcc testsuite: gcc.target/i386/sse4_1-pblendw.c
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+
+define i32 @main() nounwind {
+entry:
+ %tmp122 = load <2 x i64>* null, align 16 ; <<2 x i64>> [#uses=1]
+ %tmp126 = bitcast <2 x i64> %tmp122 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp129 = call <8 x i16> @llvm.x86.sse41.pblendw( <8 x i16> zeroinitializer, <8 x i16> %tmp126, i32 2 ) nounwind ; <<8 x i16>> [#uses=0]
+ ret i32 0
+}
+
+declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i32) nounwind
diff --git a/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll b/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
new file mode 100644
index 0000000..38d6aa6
--- /dev/null
+++ b/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s | grep {1 \$2 3}
+; rdar://5720231
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+
+define void @test() nounwind {
+entry:
+ tail call void asm sideeffect " ${0:c} $1 ${2:c} ", "imr,imr,i,~{dirflag},~{fpsr},~{flags}"( i32 1, i32 2, i32 3 ) nounwind
+ ret void
+}
+
diff --git a/test/CodeGen/X86/2008-04-28-CoalescerBug.ll b/test/CodeGen/X86/2008-04-28-CoalescerBug.ll
new file mode 100644
index 0000000..5b97eb7
--- /dev/null
+++ b/test/CodeGen/X86/2008-04-28-CoalescerBug.ll
@@ -0,0 +1,167 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movl > %t
+; RUN: not grep {r\[abcd\]x} %t
+; RUN: not grep {r\[ds\]i} %t
+; RUN: not grep {r\[bs\]p} %t
+
+ %struct.BITMAP = type { i16, i16, i32, i32, i32, i32, i32, i32, i8*, i8* }
+ %struct.BltData = type { float, float, float, float }
+ %struct.BltDepth = type { i32, i8**, i32, %struct.BITMAP* (%struct.BltDepth**, %struct.BITMAP*, i32, i32, float*, float, i32)*, i32 (%struct.BltDepth**, %struct.BltOp*)*, i32 (%struct.BltDepth**, %struct.BltOp*, %struct.BltImg*)*, i32 (%struct.BltDepth**, %struct.BltOp*, %struct.BltSh*)*, [28 x [2 x [2 x i32]]]*, %struct.BltData* }
+ %struct.BltImg = type { i32, i8, i8, i8, float, float*, float*, i32, i32, float*, i32 (i8*, i8*, i8**, i32*, i8**, i32*)*, i8* }
+ %struct.BltOp = type { i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i8* }
+ %struct.BltSh = type { i8, i8, i8, i8, float, float*, float*, float*, float*, i32, i32, float*, float*, float* }
+
+define void @t(%struct.BltDepth* %depth, %struct.BltOp* %bop, i32 %mode) nounwind {
+entry:
+ switch i32 %mode, label %return [
+ i32 1, label %bb2898.us
+ i32 18, label %bb13086.preheader
+ ]
+
+bb13086.preheader: ; preds = %entry
+ %tmp13098 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ %tmp13238 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br label %bb13088
+
+bb2898.us: ; preds = %bb2898.us, %entry
+ br label %bb2898.us
+
+bb13088: ; preds = %bb13572, %bb13567, %bb13107, %bb13086.preheader
+ br i1 %tmp13098, label %bb13107, label %bb13101
+
+bb13101: ; preds = %bb13088
+ br label %bb13107
+
+bb13107: ; preds = %bb13101, %bb13088
+ %iftmp.684.0 = phi i32 [ 0, %bb13101 ], [ 65535, %bb13088 ] ; <i32> [#uses=2]
+ %tmp13111 = load i64* null, align 8 ; <i64> [#uses=3]
+ %tmp13116 = lshr i64 %tmp13111, 16 ; <i64> [#uses=1]
+ %tmp1311613117 = trunc i64 %tmp13116 to i32 ; <i32> [#uses=1]
+ %tmp13118 = and i32 %tmp1311613117, 65535 ; <i32> [#uses=1]
+ %tmp13120 = lshr i64 %tmp13111, 32 ; <i64> [#uses=1]
+ %tmp1312013121 = trunc i64 %tmp13120 to i32 ; <i32> [#uses=1]
+ %tmp13122 = and i32 %tmp1312013121, 65535 ; <i32> [#uses=2]
+ %tmp13124 = lshr i64 %tmp13111, 48 ; <i64> [#uses=1]
+ %tmp1312413125 = trunc i64 %tmp13124 to i32 ; <i32> [#uses=2]
+ %tmp1314013141not = xor i16 0, -1 ; <i16> [#uses=1]
+ %tmp1314013141not13142 = zext i16 %tmp1314013141not to i32 ; <i32> [#uses=3]
+ %tmp13151 = mul i32 %tmp13122, %tmp1314013141not13142 ; <i32> [#uses=1]
+ %tmp13154 = mul i32 %tmp1312413125, %tmp1314013141not13142 ; <i32> [#uses=1]
+ %tmp13157 = mul i32 %iftmp.684.0, %tmp1314013141not13142 ; <i32> [#uses=1]
+ %tmp13171 = add i32 %tmp13151, 1 ; <i32> [#uses=1]
+ %tmp13172 = add i32 %tmp13171, 0 ; <i32> [#uses=1]
+ %tmp13176 = add i32 %tmp13154, 1 ; <i32> [#uses=1]
+ %tmp13177 = add i32 %tmp13176, 0 ; <i32> [#uses=1]
+ %tmp13181 = add i32 %tmp13157, 1 ; <i32> [#uses=1]
+ %tmp13182 = add i32 %tmp13181, 0 ; <i32> [#uses=1]
+ %tmp13188 = lshr i32 %tmp13172, 16 ; <i32> [#uses=1]
+ %tmp13190 = lshr i32 %tmp13177, 16 ; <i32> [#uses=1]
+ %tmp13192 = lshr i32 %tmp13182, 16 ; <i32> [#uses=1]
+ %tmp13198 = sub i32 %tmp13118, 0 ; <i32> [#uses=1]
+ %tmp13201 = sub i32 %tmp13122, %tmp13188 ; <i32> [#uses=1]
+ %tmp13204 = sub i32 %tmp1312413125, %tmp13190 ; <i32> [#uses=1]
+ %tmp13207 = sub i32 %iftmp.684.0, %tmp13192 ; <i32> [#uses=1]
+ %tmp1320813209 = zext i32 %tmp13204 to i64 ; <i64> [#uses=1]
+ %tmp13211 = shl i64 %tmp1320813209, 48 ; <i64> [#uses=1]
+ %tmp1321213213 = zext i32 %tmp13201 to i64 ; <i64> [#uses=1]
+ %tmp13214 = shl i64 %tmp1321213213, 32 ; <i64> [#uses=1]
+ %tmp13215 = and i64 %tmp13214, 281470681743360 ; <i64> [#uses=1]
+ %tmp1321713218 = zext i32 %tmp13198 to i64 ; <i64> [#uses=1]
+ %tmp13219 = shl i64 %tmp1321713218, 16 ; <i64> [#uses=1]
+ %tmp13220 = and i64 %tmp13219, 4294901760 ; <i64> [#uses=1]
+ %tmp13216 = or i64 %tmp13211, 0 ; <i64> [#uses=1]
+ %tmp13221 = or i64 %tmp13216, %tmp13215 ; <i64> [#uses=1]
+ %tmp13225 = or i64 %tmp13221, %tmp13220 ; <i64> [#uses=4]
+ %tmp1322713228 = trunc i32 %tmp13207 to i16 ; <i16> [#uses=4]
+ %tmp13233 = icmp eq i16 %tmp1322713228, 0 ; <i1> [#uses=1]
+ br i1 %tmp13233, label %bb13088, label %bb13236
+
+bb13236: ; preds = %bb13107
+ br i1 false, label %bb13567, label %bb13252
+
+bb13252: ; preds = %bb13236
+ %tmp1329013291 = zext i16 %tmp1322713228 to i64 ; <i64> [#uses=8]
+ %tmp13296 = lshr i64 %tmp13225, 16 ; <i64> [#uses=1]
+ %tmp13297 = and i64 %tmp13296, 65535 ; <i64> [#uses=1]
+ %tmp13299 = lshr i64 %tmp13225, 32 ; <i64> [#uses=1]
+ %tmp13300 = and i64 %tmp13299, 65535 ; <i64> [#uses=1]
+ %tmp13302 = lshr i64 %tmp13225, 48 ; <i64> [#uses=1]
+ %tmp13306 = sub i64 %tmp1329013291, 0 ; <i64> [#uses=0]
+ %tmp13309 = sub i64 %tmp1329013291, %tmp13297 ; <i64> [#uses=1]
+ %tmp13312 = sub i64 %tmp1329013291, %tmp13300 ; <i64> [#uses=1]
+ %tmp13315 = sub i64 %tmp1329013291, %tmp13302 ; <i64> [#uses=1]
+ %tmp13318 = mul i64 %tmp1329013291, %tmp1329013291 ; <i64> [#uses=1]
+ br i1 false, label %bb13339, label %bb13324
+
+bb13324: ; preds = %bb13252
+ br i1 false, label %bb13339, label %bb13330
+
+bb13330: ; preds = %bb13324
+ %tmp13337 = sdiv i64 0, 0 ; <i64> [#uses=1]
+ br label %bb13339
+
+bb13339: ; preds = %bb13330, %bb13324, %bb13252
+ %r0120.0 = phi i64 [ %tmp13337, %bb13330 ], [ 0, %bb13252 ], [ 4294836225, %bb13324 ] ; <i64> [#uses=1]
+ br i1 false, label %bb13360, label %bb13345
+
+bb13345: ; preds = %bb13339
+ br i1 false, label %bb13360, label %bb13351
+
+bb13351: ; preds = %bb13345
+ %tmp13354 = mul i64 0, %tmp13318 ; <i64> [#uses=1]
+ %tmp13357 = sub i64 %tmp1329013291, %tmp13309 ; <i64> [#uses=1]
+ %tmp13358 = sdiv i64 %tmp13354, %tmp13357 ; <i64> [#uses=1]
+ br label %bb13360
+
+bb13360: ; preds = %bb13351, %bb13345, %bb13339
+ %r1121.0 = phi i64 [ %tmp13358, %bb13351 ], [ 0, %bb13339 ], [ 4294836225, %bb13345 ] ; <i64> [#uses=1]
+ br i1 false, label %bb13402, label %bb13387
+
+bb13387: ; preds = %bb13360
+ br label %bb13402
+
+bb13402: ; preds = %bb13387, %bb13360
+ %r3123.0 = phi i64 [ 0, %bb13360 ], [ 4294836225, %bb13387 ] ; <i64> [#uses=1]
+ %tmp13404 = icmp eq i16 %tmp1322713228, -1 ; <i1> [#uses=1]
+ br i1 %tmp13404, label %bb13435, label %bb13407
+
+bb13407: ; preds = %bb13402
+ br label %bb13435
+
+bb13435: ; preds = %bb13407, %bb13402
+ %r0120.1 = phi i64 [ 0, %bb13407 ], [ %r0120.0, %bb13402 ] ; <i64> [#uses=0]
+ %r1121.1 = phi i64 [ 0, %bb13407 ], [ %r1121.0, %bb13402 ] ; <i64> [#uses=0]
+ %r3123.1 = phi i64 [ 0, %bb13407 ], [ %r3123.0, %bb13402 ] ; <i64> [#uses=0]
+ %tmp13450 = mul i64 0, %tmp13312 ; <i64> [#uses=0]
+ %tmp13455 = mul i64 0, %tmp13315 ; <i64> [#uses=0]
+ %tmp13461 = add i64 0, %tmp1329013291 ; <i64> [#uses=1]
+ %tmp13462 = mul i64 %tmp13461, 65535 ; <i64> [#uses=1]
+ %tmp13466 = sub i64 %tmp13462, 0 ; <i64> [#uses=1]
+ %tmp13526 = add i64 %tmp13466, 1 ; <i64> [#uses=1]
+ %tmp13527 = add i64 %tmp13526, 0 ; <i64> [#uses=1]
+ %tmp13528 = ashr i64 %tmp13527, 16 ; <i64> [#uses=4]
+ %tmp13536 = sub i64 %tmp13528, 0 ; <i64> [#uses=1]
+ %tmp13537 = shl i64 %tmp13536, 32 ; <i64> [#uses=1]
+ %tmp13538 = and i64 %tmp13537, 281470681743360 ; <i64> [#uses=1]
+ %tmp13542 = sub i64 %tmp13528, 0 ; <i64> [#uses=1]
+ %tmp13543 = shl i64 %tmp13542, 16 ; <i64> [#uses=1]
+ %tmp13544 = and i64 %tmp13543, 4294901760 ; <i64> [#uses=1]
+ %tmp13548 = sub i64 %tmp13528, 0 ; <i64> [#uses=1]
+ %tmp13549 = and i64 %tmp13548, 65535 ; <i64> [#uses=1]
+ %tmp13539 = or i64 %tmp13538, 0 ; <i64> [#uses=1]
+ %tmp13545 = or i64 %tmp13539, %tmp13549 ; <i64> [#uses=1]
+ %tmp13550 = or i64 %tmp13545, %tmp13544 ; <i64> [#uses=1]
+ %tmp1355213553 = trunc i64 %tmp13528 to i16 ; <i16> [#uses=1]
+ br label %bb13567
+
+bb13567: ; preds = %bb13435, %bb13236
+ %tsp1040.0.0 = phi i64 [ %tmp13550, %bb13435 ], [ %tmp13225, %bb13236 ] ; <i64> [#uses=0]
+ %tsp1040.1.0 = phi i16 [ %tmp1355213553, %bb13435 ], [ %tmp1322713228, %bb13236 ] ; <i16> [#uses=1]
+ br i1 %tmp13238, label %bb13088, label %bb13572
+
+bb13572: ; preds = %bb13567
+ store i16 %tsp1040.1.0, i16* null, align 2
+ br label %bb13088
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2008-04-28-CyclicSchedUnit.ll b/test/CodeGen/X86/2008-04-28-CyclicSchedUnit.ll
new file mode 100644
index 0000000..6e8e98d
--- /dev/null
+++ b/test/CodeGen/X86/2008-04-28-CyclicSchedUnit.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86
+
+define i64 @t(i64 %maxIdleDuration) nounwind {
+ call void asm sideeffect "wrmsr", "{cx},A,~{dirflag},~{fpsr},~{flags}"( i32 416, i64 0 ) nounwind
+ unreachable
+}
diff --git a/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll b/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
new file mode 100644
index 0000000..a708224
--- /dev/null
+++ b/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -enable-unsafe-fp-math -march=x86 | grep jnp
+; rdar://5902801
+
+declare void @test2()
+
+define i32 @test(double %p) nounwind {
+ %tmp5 = fcmp uno double %p, 0.000000e+00
+ br i1 %tmp5, label %bb, label %UnifiedReturnBlock
+bb:
+ call void @test2()
+ ret i32 17
+UnifiedReturnBlock:
+ ret i32 42
+}
+
diff --git a/test/CodeGen/X86/2008-05-09-PHIElimBug.ll b/test/CodeGen/X86/2008-05-09-PHIElimBug.ll
new file mode 100644
index 0000000..cea00760
--- /dev/null
+++ b/test/CodeGen/X86/2008-05-09-PHIElimBug.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86
+
+ %struct.V = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x i32>, float*, float*, float*, float*, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, i32, i32, i32, i32, i32, i32, i32, i32 }
+
+define fastcc void @t() nounwind {
+entry:
+ br i1 false, label %bb23816.preheader, label %bb23821
+
+bb23816.preheader: ; preds = %entry
+ %tmp23735 = and i32 0, 2 ; <i32> [#uses=0]
+ br label %bb23830
+
+bb23821: ; preds = %entry
+ br i1 false, label %bb23830, label %bb23827
+
+bb23827: ; preds = %bb23821
+ %tmp23829 = getelementptr %struct.V* null, i32 0, i32 42 ; <i32*> [#uses=0]
+ br label %bb23830
+
+bb23830: ; preds = %bb23827, %bb23821, %bb23816.preheader
+ %scaledInDst.2.reg2mem.5 = phi i8 [ undef, %bb23827 ], [ undef, %bb23821 ], [ undef, %bb23816.preheader ] ; <i8> [#uses=1]
+ %toBool35047 = icmp eq i8 %scaledInDst.2.reg2mem.5, 0 ; <i1> [#uses=1]
+ %bothcond39107 = or i1 %toBool35047, false ; <i1> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll b/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll
new file mode 100644
index 0000000..5ceb546
--- /dev/null
+++ b/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+
+define fastcc void @glgVectorFloatConversion() nounwind {
+ %tmp12745 = load <4 x float>* null, align 16 ; <<4 x float>> [#uses=1]
+ %tmp12773 = insertelement <4 x float> %tmp12745, float 1.000000e+00, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp12774 = insertelement <4 x float> %tmp12773, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp12775 = insertelement <4 x float> %tmp12774, float 1.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp12775, <4 x float>* null, align 16
+ unreachable
+}
diff --git a/test/CodeGen/X86/2008-05-12-tailmerge-5.ll b/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
new file mode 100644
index 0000000..4852e89
--- /dev/null
+++ b/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
@@ -0,0 +1,145 @@
+; RUN: llc < %s | grep abort | count 1
+; Calls to abort should all be merged
+
+; ModuleID = '5898899.c'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin8"
+ %struct.BoundaryAlignment = type { [3 x i8], i8, i16, i16, i8, [2 x i8] }
+
+define void @passing2(i64 %str.0, i64 %str.1, i16 signext %s, i32 %j, i8 signext %c, i16 signext %t, i16 signext %u, i8 signext %d) nounwind optsize {
+entry:
+ %str_addr = alloca %struct.BoundaryAlignment ; <%struct.BoundaryAlignment*> [#uses=7]
+ %s_addr = alloca i16 ; <i16*> [#uses=1]
+ %j_addr = alloca i32 ; <i32*> [#uses=2]
+ %c_addr = alloca i8 ; <i8*> [#uses=2]
+ %t_addr = alloca i16 ; <i16*> [#uses=2]
+ %u_addr = alloca i16 ; <i16*> [#uses=2]
+ %d_addr = alloca i8 ; <i8*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %tmp = bitcast %struct.BoundaryAlignment* %str_addr to { i64, i64 }* ; <{ i64, i64 }*> [#uses=1]
+ %tmp1 = getelementptr { i64, i64 }* %tmp, i32 0, i32 0 ; <i64*> [#uses=1]
+ store i64 %str.0, i64* %tmp1
+ %tmp2 = bitcast %struct.BoundaryAlignment* %str_addr to { i64, i64 }* ; <{ i64, i64 }*> [#uses=1]
+ %tmp3 = getelementptr { i64, i64 }* %tmp2, i32 0, i32 1 ; <i64*> [#uses=1]
+ %bc = bitcast i64* %tmp3 to i8* ; <i8*> [#uses=2]
+ %byte = trunc i64 %str.1 to i8 ; <i8> [#uses=1]
+ store i8 %byte, i8* %bc
+ %shft = lshr i64 %str.1, 8 ; <i64> [#uses=2]
+ %Loc = getelementptr i8* %bc, i32 1 ; <i8*> [#uses=2]
+ %byte4 = trunc i64 %shft to i8 ; <i8> [#uses=1]
+ store i8 %byte4, i8* %Loc
+ %shft5 = lshr i64 %shft, 8 ; <i64> [#uses=2]
+ %Loc6 = getelementptr i8* %Loc, i32 1 ; <i8*> [#uses=2]
+ %byte7 = trunc i64 %shft5 to i8 ; <i8> [#uses=1]
+ store i8 %byte7, i8* %Loc6
+ %shft8 = lshr i64 %shft5, 8 ; <i64> [#uses=2]
+ %Loc9 = getelementptr i8* %Loc6, i32 1 ; <i8*> [#uses=2]
+ %byte10 = trunc i64 %shft8 to i8 ; <i8> [#uses=1]
+ store i8 %byte10, i8* %Loc9
+ %shft11 = lshr i64 %shft8, 8 ; <i64> [#uses=0]
+ %Loc12 = getelementptr i8* %Loc9, i32 1 ; <i8*> [#uses=0]
+ store i16 %s, i16* %s_addr
+ store i32 %j, i32* %j_addr
+ store i8 %c, i8* %c_addr
+ store i16 %t, i16* %t_addr
+ store i16 %u, i16* %u_addr
+ store i8 %d, i8* %d_addr
+ %tmp13 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 0 ; <[3 x i8]*> [#uses=1]
+ %tmp1314 = bitcast [3 x i8]* %tmp13 to i32* ; <i32*> [#uses=1]
+ %tmp15 = load i32* %tmp1314, align 4 ; <i32> [#uses=1]
+ %tmp16 = shl i32 %tmp15, 14 ; <i32> [#uses=1]
+ %tmp17 = ashr i32 %tmp16, 23 ; <i32> [#uses=1]
+ %tmp1718 = trunc i32 %tmp17 to i16 ; <i16> [#uses=1]
+ %sextl = shl i16 %tmp1718, 7 ; <i16> [#uses=1]
+ %sextr = ashr i16 %sextl, 7 ; <i16> [#uses=2]
+ %sextl19 = shl i16 %sextr, 7 ; <i16> [#uses=1]
+ %sextr20 = ashr i16 %sextl19, 7 ; <i16> [#uses=0]
+ %sextl21 = shl i16 %sextr, 7 ; <i16> [#uses=1]
+ %sextr22 = ashr i16 %sextl21, 7 ; <i16> [#uses=1]
+ %sextr2223 = sext i16 %sextr22 to i32 ; <i32> [#uses=1]
+ %tmp24 = load i32* %j_addr, align 4 ; <i32> [#uses=1]
+ %tmp25 = icmp ne i32 %sextr2223, %tmp24 ; <i1> [#uses=1]
+ %tmp2526 = zext i1 %tmp25 to i8 ; <i8> [#uses=1]
+ %toBool = icmp ne i8 %tmp2526, 0 ; <i1> [#uses=1]
+ br i1 %toBool, label %bb, label %bb27
+
+bb: ; preds = %entry
+ call void (...)* @abort( ) noreturn nounwind
+ unreachable
+
+bb27: ; preds = %entry
+ %tmp28 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 1 ; <i8*> [#uses=1]
+ %tmp29 = load i8* %tmp28, align 4 ; <i8> [#uses=1]
+ %tmp30 = load i8* %c_addr, align 1 ; <i8> [#uses=1]
+ %tmp31 = icmp ne i8 %tmp29, %tmp30 ; <i1> [#uses=1]
+ %tmp3132 = zext i1 %tmp31 to i8 ; <i8> [#uses=1]
+ %toBool33 = icmp ne i8 %tmp3132, 0 ; <i1> [#uses=1]
+ br i1 %toBool33, label %bb34, label %bb35
+
+bb34: ; preds = %bb27
+ call void (...)* @abort( ) noreturn nounwind
+ unreachable
+
+bb35: ; preds = %bb27
+ %tmp36 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 2 ; <i16*> [#uses=1]
+ %tmp37 = load i16* %tmp36, align 4 ; <i16> [#uses=1]
+ %tmp38 = shl i16 %tmp37, 7 ; <i16> [#uses=1]
+ %tmp39 = ashr i16 %tmp38, 7 ; <i16> [#uses=1]
+ %sextl40 = shl i16 %tmp39, 7 ; <i16> [#uses=1]
+ %sextr41 = ashr i16 %sextl40, 7 ; <i16> [#uses=2]
+ %sextl42 = shl i16 %sextr41, 7 ; <i16> [#uses=1]
+ %sextr43 = ashr i16 %sextl42, 7 ; <i16> [#uses=0]
+ %sextl44 = shl i16 %sextr41, 7 ; <i16> [#uses=1]
+ %sextr45 = ashr i16 %sextl44, 7 ; <i16> [#uses=1]
+ %tmp46 = load i16* %t_addr, align 2 ; <i16> [#uses=1]
+ %tmp47 = icmp ne i16 %sextr45, %tmp46 ; <i1> [#uses=1]
+ %tmp4748 = zext i1 %tmp47 to i8 ; <i8> [#uses=1]
+ %toBool49 = icmp ne i8 %tmp4748, 0 ; <i1> [#uses=1]
+ br i1 %toBool49, label %bb50, label %bb51
+
+bb50: ; preds = %bb35
+ call void (...)* @abort( ) noreturn nounwind
+ unreachable
+
+bb51: ; preds = %bb35
+ %tmp52 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 3 ; <i16*> [#uses=1]
+ %tmp53 = load i16* %tmp52, align 4 ; <i16> [#uses=1]
+ %tmp54 = shl i16 %tmp53, 7 ; <i16> [#uses=1]
+ %tmp55 = ashr i16 %tmp54, 7 ; <i16> [#uses=1]
+ %sextl56 = shl i16 %tmp55, 7 ; <i16> [#uses=1]
+ %sextr57 = ashr i16 %sextl56, 7 ; <i16> [#uses=2]
+ %sextl58 = shl i16 %sextr57, 7 ; <i16> [#uses=1]
+ %sextr59 = ashr i16 %sextl58, 7 ; <i16> [#uses=0]
+ %sextl60 = shl i16 %sextr57, 7 ; <i16> [#uses=1]
+ %sextr61 = ashr i16 %sextl60, 7 ; <i16> [#uses=1]
+ %tmp62 = load i16* %u_addr, align 2 ; <i16> [#uses=1]
+ %tmp63 = icmp ne i16 %sextr61, %tmp62 ; <i1> [#uses=1]
+ %tmp6364 = zext i1 %tmp63 to i8 ; <i8> [#uses=1]
+ %toBool65 = icmp ne i8 %tmp6364, 0 ; <i1> [#uses=1]
+ br i1 %toBool65, label %bb66, label %bb67
+
+bb66: ; preds = %bb51
+ call void (...)* @abort( ) noreturn nounwind
+ unreachable
+
+bb67: ; preds = %bb51
+ %tmp68 = getelementptr %struct.BoundaryAlignment* %str_addr, i32 0, i32 4 ; <i8*> [#uses=1]
+ %tmp69 = load i8* %tmp68, align 4 ; <i8> [#uses=1]
+ %tmp70 = load i8* %d_addr, align 1 ; <i8> [#uses=1]
+ %tmp71 = icmp ne i8 %tmp69, %tmp70 ; <i1> [#uses=1]
+ %tmp7172 = zext i1 %tmp71 to i8 ; <i8> [#uses=1]
+ %toBool73 = icmp ne i8 %tmp7172, 0 ; <i1> [#uses=1]
+ br i1 %toBool73, label %bb74, label %bb75
+
+bb74: ; preds = %bb67
+ call void (...)* @abort( ) noreturn nounwind
+ unreachable
+
+bb75: ; preds = %bb67
+ br label %return
+
+return: ; preds = %bb75
+ ret void
+}
+
+declare void @abort(...) noreturn nounwind
diff --git a/test/CodeGen/X86/2008-05-21-CoalescerBug.ll b/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
new file mode 100644
index 0000000..9cf50f4
--- /dev/null
+++ b/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
@@ -0,0 +1,98 @@
+; RUN: llc < %s -march=x86 -O0 -fast-isel=false | grep mov | count 5
+; PR2343
+
+ %llvm.dbg.anchor.type = type { i32, i32 }
+ %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.VEC_basic_block_base = type { i32, i32, [1 x %struct.basic_block_def*] }
+ %struct.VEC_basic_block_gc = type { %struct.VEC_basic_block_base }
+ %struct.VEC_edge_base = type { i32, i32, [1 x %struct.edge_def*] }
+ %struct.VEC_edge_gc = type { %struct.VEC_edge_base }
+ %struct.VEC_rtx_base = type { i32, i32, [1 x %struct.rtx_def*] }
+ %struct.VEC_rtx_gc = type { %struct.VEC_rtx_base }
+ %struct.VEC_temp_slot_p_base = type { i32, i32, [1 x %struct.temp_slot*] }
+ %struct.VEC_temp_slot_p_gc = type { %struct.VEC_temp_slot_p_base }
+ %struct.VEC_tree_base = type { i32, i32, [1 x %struct.tree_node*] }
+ %struct.VEC_tree_gc = type { %struct.VEC_tree_base }
+ %struct.__sbuf = type { i8*, i32 }
+ %struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
+ %struct.basic_block_def = type { %struct.tree_node*, %struct.VEC_edge_gc*, %struct.VEC_edge_gc*, i8*, %struct.loop*, [2 x %struct.et_node*], %struct.basic_block_def*, %struct.basic_block_def*, %struct.basic_block_il_dependent, %struct.tree_node*, %struct.edge_prediction*, i64, i32, i32, i32, i32 }
+ %struct.basic_block_il_dependent = type { %struct.rtl_bb_info* }
+ %struct.bitmap_element_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, [4 x i32] }
+ %struct.bitmap_head_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, %struct.bitmap_obstack* }
+ %struct.bitmap_obstack = type { %struct.bitmap_element_def*, %struct.bitmap_head_def*, %struct.obstack }
+ %struct.block_symbol = type { [3 x %struct.cfg_stats_d], %struct.object_block*, i64 }
+ %struct.cfg_stats_d = type { i32 }
+ %struct.control_flow_graph = type { %struct.basic_block_def*, %struct.basic_block_def*, %struct.VEC_basic_block_gc*, i32, i32, i32, %struct.VEC_basic_block_gc*, i32 }
+ %struct.def_optype_d = type { %struct.def_optype_d*, %struct.tree_node** }
+ %struct.edge_def = type { %struct.basic_block_def*, %struct.basic_block_def*, %struct.edge_def_insns, i8*, %struct.__sbuf*, i32, i32, i64, i32 }
+ %struct.edge_def_insns = type { %struct.rtx_def* }
+ %struct.edge_prediction = type { %struct.edge_prediction*, %struct.edge_def*, i32, i32 }
+ %struct.eh_status = type opaque
+ %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.__sbuf, i32, i8*, %struct.rtx_def** }
+ %struct.et_node = type opaque
+ %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+ %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.control_flow_graph*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.VEC_temp_slot_p_gc*, %struct.temp_slot*, %struct.var_refs_queue*, i32, i32, i32, i32, %struct.machine_function*, i32, i32, %struct.language_function*, %struct.htab*, %struct.rtx_def*, i32, i32, i32, %struct.__sbuf, %struct.VEC_tree_gc*, %struct.tree_node*, i8*, i8*, i8*, i8*, i8*, %struct.tree_node*, i8, i8, i8, i8, i8, i8 }
+ %struct.htab = type { i32 (i8*)*, i32 (i8*, i8*)*, void (i8*)*, i8**, i32, i32, i32, i32, i32, i8* (i32, i32)*, void (i8*)*, i8*, i8* (i8*, i32, i32)*, void (i8*, i8*)*, i32 }
+ %struct.initial_value_struct = type opaque
+ %struct.lang_decl = type opaque
+ %struct.language_function = type opaque
+ %struct.loop = type { i32, %struct.basic_block_def*, %struct.basic_block_def*, %llvm.dbg.anchor.type, i32, i32, i32, i32, %struct.loop**, i32, %struct.loop*, %struct.loop*, %struct.loop*, %struct.loop*, i8*, %struct.tree_node*, %struct.tree_node*, %struct.nb_iter_bound*, %struct.edge_def*, i32 }
+ %struct.machine_function = type opaque
+ %struct.maydef_optype_d = type { %struct.maydef_optype_d*, %struct.tree_node*, %struct.tree_node*, %struct.ssa_use_operand_d }
+ %struct.nb_iter_bound = type { %struct.tree_node*, %struct.tree_node*, %struct.nb_iter_bound* }
+ %struct.object_block = type { %struct.section*, i32, i64, %struct.VEC_rtx_gc*, %struct.VEC_rtx_gc* }
+ %struct.obstack = type { i32, %struct._obstack_chunk*, i8*, i8*, i8*, i32, i32, %struct._obstack_chunk* (i8*, i32)*, void (i8*, %struct._obstack_chunk*)*, i8*, i8 }
+ %struct.rtl_bb_info = type { %struct.rtx_def*, %struct.rtx_def*, %struct.bitmap_head_def*, %struct.bitmap_head_def*, %struct.rtx_def*, %struct.rtx_def*, i32 }
+ %struct.rtx_def = type { i16, i8, i8, %struct.u }
+ %struct.section = type { %struct.unnamed_section }
+ %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
+ %struct.ssa_use_operand_d = type { %struct.ssa_use_operand_d*, %struct.ssa_use_operand_d*, %struct.tree_node*, %struct.tree_node** }
+ %struct.stmt_ann_d = type { %struct.tree_ann_common_d, i8, %struct.basic_block_def*, %struct.stmt_operands_d, %struct.bitmap_head_def*, i32, i8* }
+ %struct.stmt_operands_d = type { %struct.def_optype_d*, %struct.use_optype_d*, %struct.maydef_optype_d*, %struct.vuse_optype_d*, %struct.maydef_optype_d* }
+ %struct.temp_slot = type opaque
+ %struct.tree_ann_common_d = type { i32, i8*, %struct.tree_node* }
+ %struct.tree_ann_d = type { %struct.stmt_ann_d }
+ %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_ann_d*, i8, i8, i8, i8, i8 }
+ %struct.tree_decl_common = type { %struct.tree_decl_minimal, %struct.tree_node*, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_decl_minimal = type { %struct.tree_common, %struct.__sbuf, i32, %struct.tree_node*, %struct.tree_node* }
+ %struct.tree_decl_non_common = type { %struct.tree_decl_with_vis, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node* }
+ %struct.tree_decl_u1 = type { i64 }
+ %struct.tree_decl_with_rtl = type { %struct.tree_decl_common, %struct.rtx_def*, i32 }
+ %struct.tree_decl_with_vis = type { %struct.tree_decl_with_rtl, %struct.tree_node*, %struct.tree_node*, i8, i8, i8 }
+ %struct.tree_function_decl = type { %struct.tree_decl_non_common, i8, i8, i64, %struct.function* }
+ %struct.tree_node = type { %struct.tree_function_decl }
+ %struct.u = type { %struct.block_symbol }
+ %struct.unnamed_section = type { %struct.cfg_stats_d, void (i8*)*, i8*, %struct.section* }
+ %struct.use_optype_d = type { %struct.use_optype_d*, %struct.ssa_use_operand_d }
+ %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+ %struct.varasm_status = type opaque
+ %struct.vuse_optype_d = type { %struct.vuse_optype_d*, %struct.tree_node*, %struct.ssa_use_operand_d }
[email protected] = appending global [1 x i8*] [ i8* bitcast (%struct.edge_def* (%struct.edge_def*, %struct.basic_block_def*)* @tree_redirect_edge_and_branch to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define %struct.edge_def* @tree_redirect_edge_and_branch(%struct.edge_def* %e1, %struct.basic_block_def* %dest2) nounwind {
+entry:
+ br label %bb497
+
+bb483: ; preds = %bb497
+ %tmp496 = load %struct.tree_node** null, align 4 ; <%struct.tree_node*> [#uses=1]
+ br label %bb497
+
+bb497: ; preds = %bb483, %entry
+ %cases.0 = phi %struct.tree_node* [ %tmp496, %bb483 ], [ null, %entry ] ; <%struct.tree_node*> [#uses=1]
+ %last.0 = phi %struct.tree_node* [ %cases.0, %bb483 ], [ undef, %entry ] ; <%struct.tree_node*> [#uses=1]
+ %foo = phi i1 [ 0, %bb483 ], [ 1, %entry ]
+ br i1 %foo, label %bb483, label %bb502
+
+bb502: ; preds = %bb497
+ br i1 %foo, label %bb507, label %bb841
+
+bb507: ; preds = %bb502
+ %tmp517 = getelementptr %struct.tree_node* %last.0, i32 0, i32 0 ; <%struct.tree_function_decl*> [#uses=1]
+ %tmp517518 = bitcast %struct.tree_function_decl* %tmp517 to %struct.tree_common* ; <%struct.tree_common*> [#uses=1]
+ %tmp519 = getelementptr %struct.tree_common* %tmp517518, i32 0, i32 0 ; <%struct.tree_node**> [#uses=1]
+ store %struct.tree_node* null, %struct.tree_node** %tmp519, align 4
+ br label %bb841
+
+bb841: ; preds = %bb507, %bb502
+ unreachable
+}
diff --git a/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll b/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll
new file mode 100644
index 0000000..19a7354
--- /dev/null
+++ b/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movups | count 2
+
+define void @a(<4 x float>* %x) nounwind {
+entry:
+ %tmp2 = load <4 x float>* %x, align 1
+ %inv = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %tmp2)
+ store <4 x float> %inv, <4 x float>* %x, align 1
+ ret void
+}
+
+declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>)
diff --git a/test/CodeGen/X86/2008-05-28-CoalescerBug.ll b/test/CodeGen/X86/2008-05-28-CoalescerBug.ll
new file mode 100644
index 0000000..32bf8d4
--- /dev/null
+++ b/test/CodeGen/X86/2008-05-28-CoalescerBug.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
+; PR2289
+
+define void @_ada_ca11001() {
+entry:
+ %tmp59 = call i16 @ca11001_0__cartesian_assign( i8 zeroext 0, i8 zeroext 0, i16 undef ) ; <i16> [#uses=0]
+ unreachable
+}
+
+declare i16 @ca11001_0__cartesian_assign(i8 zeroext , i8 zeroext , i16)
diff --git a/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll b/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll
new file mode 100644
index 0000000..f1a19ec
--- /dev/null
+++ b/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=local
+
+@_ZTVN10Evaluation10GridOutputILi3EEE = external constant [5 x i32 (...)*] ; <[5 x i32 (...)*]*> [#uses=1]
+
+declare i8* @llvm.eh.exception() nounwind
+
+declare i8* @_Znwm(i32)
+
+declare i8* @__cxa_begin_catch(i8*) nounwind
+
+define i32 @main(i32 %argc, i8** %argv) {
+entry:
+ br i1 false, label %bb37, label %bb34
+
+bb34: ; preds = %entry
+ ret i32 1
+
+bb37: ; preds = %entry
+ %tmp12.i.i.i.i.i66 = invoke i8* @_Znwm( i32 12 )
+ to label %tmp12.i.i.i.i.i.noexc65 unwind label %lpad243 ; <i8*> [#uses=0]
+
+tmp12.i.i.i.i.i.noexc65: ; preds = %bb37
+ unreachable
+
+lpad243: ; preds = %bb37
+ %eh_ptr244 = call i8* @llvm.eh.exception( ) ; <i8*> [#uses=1]
+ store i32 (...)** getelementptr ([5 x i32 (...)*]* @_ZTVN10Evaluation10GridOutputILi3EEE, i32 0, i32 2), i32 (...)*** null, align 8
+ %tmp133 = call i8* @__cxa_begin_catch( i8* %eh_ptr244 ) nounwind ; <i8*> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/X86/2008-06-04-MemCpyLoweringBug.ll b/test/CodeGen/X86/2008-06-04-MemCpyLoweringBug.ll
new file mode 100644
index 0000000..236b7cd
--- /dev/null
+++ b/test/CodeGen/X86/2008-06-04-MemCpyLoweringBug.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim | grep subl | grep 24
+
+ %struct.argument_t = type { i8*, %struct.argument_t*, i32, %struct.ipc_type_t*, i32, void (...)*, void (...)*, void (...)*, void (...)*, void (...)*, i8*, i8*, i8*, i8*, i8*, i32, i32, i32, %struct.routine*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, %struct.argument_t*, i32, i32, i32, i32, i32, i32 }
+ %struct.ipc_type_t = type { i8*, %struct.ipc_type_t*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, i32, i32, i32, i32, %struct.ipc_type_t*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8* }
+ %struct.routine = type opaque
+@"\01LC" = external constant [11 x i8] ; <[11 x i8]*> [#uses=1]
+
+define i8* @InArgMsgField(%struct.argument_t* %arg, i8* %str) nounwind {
+entry:
+ %who = alloca [20 x i8] ; <[20 x i8]*> [#uses=1]
+ %who1 = getelementptr [20 x i8]* %who, i32 0, i32 0 ; <i8*> [#uses=2]
+ call void @llvm.memset.i32( i8* %who1, i8 0, i32 20, i32 1 )
+ call void @llvm.memcpy.i32( i8* %who1, i8* getelementptr ([11 x i8]* @"\01LC", i32 0, i32 0), i32 11, i32 1 )
+ unreachable
+}
+
+declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind
diff --git a/test/CodeGen/X86/2008-06-13-NotVolatileLoadStore.ll b/test/CodeGen/X86/2008-06-13-NotVolatileLoadStore.ll
new file mode 100644
index 0000000..90af387
--- /dev/null
+++ b/test/CodeGen/X86/2008-06-13-NotVolatileLoadStore.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86 | not grep movsd
+; RUN: llc < %s -march=x86 | grep movw
+; RUN: llc < %s -march=x86 | grep addw
+; These transforms are turned off for volatile loads and stores.
+; Check that they weren't turned off for all loads and stores!
+
+@atomic = global double 0.000000e+00 ; <double*> [#uses=1]
+@atomic2 = global double 0.000000e+00 ; <double*> [#uses=1]
+@ioport = global i32 0 ; <i32*> [#uses=1]
+@ioport2 = global i32 0 ; <i32*> [#uses=1]
+
+define i16 @f(i64 %x) {
+ %b = bitcast i64 %x to double ; <double> [#uses=1]
+ store double %b, double* @atomic
+ store double 0.000000e+00, double* @atomic2
+ %l = load i32* @ioport ; <i32> [#uses=1]
+ %t = trunc i32 %l to i16 ; <i16> [#uses=1]
+ %l2 = load i32* @ioport2 ; <i32> [#uses=1]
+ %tmp = lshr i32 %l2, 16 ; <i32> [#uses=1]
+ %t2 = trunc i32 %tmp to i16 ; <i16> [#uses=1]
+ %f = add i16 %t, %t2 ; <i16> [#uses=1]
+ ret i16 %f
+}
diff --git a/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll b/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll
new file mode 100644
index 0000000..500cd1f
--- /dev/null
+++ b/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movsd | count 5
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movl | count 2
+
+@atomic = global double 0.000000e+00 ; <double*> [#uses=1]
+@atomic2 = global double 0.000000e+00 ; <double*> [#uses=1]
+@anything = global i64 0 ; <i64*> [#uses=1]
+@ioport = global i32 0 ; <i32*> [#uses=2]
+
+define i16 @f(i64 %x, double %y) {
+ %b = bitcast i64 %x to double ; <double> [#uses=1]
+ volatile store double %b, double* @atomic ; one processor operation only
+ volatile store double 0.000000e+00, double* @atomic2 ; one processor operation only
+ %b2 = bitcast double %y to i64 ; <i64> [#uses=1]
+ volatile store i64 %b2, i64* @anything ; may transform to store of double
+ %l = volatile load i32* @ioport ; must not narrow
+ %t = trunc i32 %l to i16 ; <i16> [#uses=1]
+ %l2 = volatile load i32* @ioport ; must not narrow
+ %tmp = lshr i32 %l2, 16 ; <i32> [#uses=1]
+ %t2 = trunc i32 %tmp to i16 ; <i16> [#uses=1]
+ %f = add i16 %t, %t2 ; <i16> [#uses=1]
+ ret i16 %f
+}
diff --git a/test/CodeGen/X86/2008-06-16-SubregsBug.ll b/test/CodeGen/X86/2008-06-16-SubregsBug.ll
new file mode 100644
index 0000000..4d4819a
--- /dev/null
+++ b/test/CodeGen/X86/2008-06-16-SubregsBug.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep mov | count 4
+
+define i16 @test(i16* %tmp179) nounwind {
+ %tmp180 = load i16* %tmp179, align 2 ; <i16> [#uses=2]
+ %tmp184 = and i16 %tmp180, -1024 ; <i16> [#uses=1]
+ %tmp186 = icmp eq i16 %tmp184, -32768 ; <i1> [#uses=1]
+ br i1 %tmp186, label %bb189, label %bb288
+
+bb189: ; preds = %0
+ ret i16 %tmp180
+
+bb288: ; preds = %0
+ ret i16 32
+}
diff --git a/test/CodeGen/X86/2008-06-18-BadShuffle.ll b/test/CodeGen/X86/2008-06-18-BadShuffle.ll
new file mode 100644
index 0000000..66f9065
--- /dev/null
+++ b/test/CodeGen/X86/2008-06-18-BadShuffle.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 -mcpu=i386 -mattr=+sse2 | grep pinsrw
+
+; Test to make sure we actually insert the bottom element of the vector
+define <8 x i16> @a(<8 x i16> %a) nounwind {
+entry:
+ shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> < i32 0, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8 >
+ %add = add <8 x i16> %0, %a
+ ret <8 x i16> %add
+}
+
diff --git a/test/CodeGen/X86/2008-06-25-VecISelBug.ll b/test/CodeGen/X86/2008-06-25-VecISelBug.ll
new file mode 100644
index 0000000..72d1907
--- /dev/null
+++ b/test/CodeGen/X86/2008-06-25-VecISelBug.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep pslldq
+
+define void @t() nounwind {
+entry:
+ %tmp1 = shufflevector <4 x float> zeroinitializer, <4 x float> < float 0.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00 >, <4 x i32> < i32 0, i32 1, i32 4, i32 5 >
+ %tmp2 = insertelement <4 x float> %tmp1, float 1.000000e+00, i32 3
+ store <4 x float> %tmp2, <4 x float>* null, align 16
+ unreachable
+}
diff --git a/test/CodeGen/X86/2008-07-07-DanglingDeadInsts.ll b/test/CodeGen/X86/2008-07-07-DanglingDeadInsts.ll
new file mode 100644
index 0000000..46341fc
--- /dev/null
+++ b/test/CodeGen/X86/2008-07-07-DanglingDeadInsts.ll
@@ -0,0 +1,99 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin9
+
+ %struct.ogg_stream_state = type { i8*, i32, i32, i32, i32*, i64*, i32, i32, i32, i32, [282 x i8], i32, i32, i32, i32, i32, i64, i64 }
+ %struct.res_state = type { i32, i32, i32, i32, float*, float*, i32, i32 }
+ %struct.vorbis_comment = type { i8**, i32*, i32, i8* }
+
+declare i32 @strlen(i8*) nounwind readonly
+
+define i32 @res_init(%struct.res_state* %state, i32 %channels, i32 %outfreq, i32 %infreq, i32 %op1, ...) nounwind {
+entry:
+ br i1 false, label %bb95, label %bb
+
+bb: ; preds = %entry
+ br i1 false, label %bb95, label %bb24
+
+bb24: ; preds = %bb
+ br i1 false, label %bb40.preheader, label %bb26
+
+bb26: ; preds = %bb24
+ ret i32 -1
+
+bb40.preheader: ; preds = %bb24
+ br i1 false, label %bb39, label %bb49.outer
+
+bb39: ; preds = %bb39, %bb40.preheader
+ shl i32 0, 1 ; <i32>:0 [#uses=0]
+ br i1 false, label %bb39, label %bb49.outer
+
+bb49.outer: ; preds = %bb39, %bb40.preheader
+ getelementptr %struct.res_state* %state, i32 0, i32 3 ; <i32*>:1 [#uses=0]
+ getelementptr %struct.res_state* %state, i32 0, i32 7 ; <i32*>:2 [#uses=0]
+ %base10.1 = select i1 false, float* null, float* null ; <float*> [#uses=1]
+ br label %bb74
+
+bb69: ; preds = %bb74
+ br label %bb71
+
+bb71: ; preds = %bb74, %bb69
+ store float 0.000000e+00, float* null, align 4
+ add i32 0, 1 ; <i32>:3 [#uses=1]
+ %indvar.next137 = add i32 %indvar136, 1 ; <i32> [#uses=1]
+ br i1 false, label %bb74, label %bb73
+
+bb73: ; preds = %bb71
+ %.rec = add i32 %base10.2.ph.rec, 1 ; <i32> [#uses=2]
+ getelementptr float* %base10.1, i32 %.rec ; <float*>:4 [#uses=1]
+ br label %bb74
+
+bb74: ; preds = %bb73, %bb71, %bb49.outer
+ %N13.1.ph = phi i32 [ 0, %bb49.outer ], [ 0, %bb73 ], [ %N13.1.ph, %bb71 ] ; <i32> [#uses=1]
+ %dest12.2.ph = phi float* [ null, %bb49.outer ], [ %4, %bb73 ], [ %dest12.2.ph, %bb71 ] ; <float*> [#uses=1]
+ %x8.0.ph = phi i32 [ 0, %bb49.outer ], [ %3, %bb73 ], [ %x8.0.ph, %bb71 ] ; <i32> [#uses=1]
+ %base10.2.ph.rec = phi i32 [ 0, %bb49.outer ], [ %.rec, %bb73 ], [ %base10.2.ph.rec, %bb71 ] ; <i32> [#uses=2]
+ %indvar136 = phi i32 [ %indvar.next137, %bb71 ], [ 0, %bb73 ], [ 0, %bb49.outer ] ; <i32> [#uses=1]
+ br i1 false, label %bb71, label %bb69
+
+bb95: ; preds = %bb, %entry
+ ret i32 -1
+}
+
+define i32 @read_resampled(i8* %d, float** %buffer, i32 %samples) nounwind {
+entry:
+ br i1 false, label %bb17.preheader, label %bb30
+
+bb17.preheader: ; preds = %entry
+ load i32* null, align 4 ; <i32>:0 [#uses=0]
+ br label %bb16
+
+bb16: ; preds = %bb16, %bb17.preheader
+ %i1.036 = phi i32 [ 0, %bb17.preheader ], [ %1, %bb16 ] ; <i32> [#uses=1]
+ add i32 %i1.036, 1 ; <i32>:1 [#uses=2]
+ icmp ult i32 %1, 0 ; <i1>:2 [#uses=0]
+ br label %bb16
+
+bb30: ; preds = %entry
+ ret i32 0
+}
+
+define i32 @ogg_stream_reset_serialno(%struct.ogg_stream_state* %os, i32 %serialno) nounwind {
+entry:
+ unreachable
+}
+
+define void @vorbis_lsp_to_curve(float* %curve, i32* %map, i32 %n, i32 %ln, float* %lsp, i32 %m, float %amp, float %ampoffset) nounwind {
+entry:
+ unreachable
+}
+
+define i32 @vorbis_comment_query_count(%struct.vorbis_comment* %vc, i8* %tag) nounwind {
+entry:
+ %strlen = call i32 @strlen( i8* null ) ; <i32> [#uses=1]
+ %endptr = getelementptr i8* null, i32 %strlen ; <i8*> [#uses=0]
+ unreachable
+}
+
+define fastcc i32 @push(%struct.res_state* %state, float* %pool, i32* %poolfill, i32* %offset, float* %dest, i32 %dststep, float* %source, i32 %srcstep, i32 %srclen) nounwind {
+entry:
+ unreachable
+}
diff --git a/test/CodeGen/X86/2008-07-09-ELFSectionAttributes.ll b/test/CodeGen/X86/2008-07-09-ELFSectionAttributes.ll
new file mode 100644
index 0000000..1a786ef7
--- /dev/null
+++ b/test/CodeGen/X86/2008-07-09-ELFSectionAttributes.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s | grep ax
+; PR2024
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+
+define i32 @foo(i32 %A, i32 %B) nounwind section ".init.text" {
+entry:
+ tail call i32 @bar( i32 %A, i32 %B ) nounwind ; <i32>:0 [#uses=1]
+ ret i32 %0
+}
+
+declare i32 @bar(i32, i32)
diff --git a/test/CodeGen/X86/2008-07-11-SHLBy1.ll b/test/CodeGen/X86/2008-07-11-SHLBy1.ll
new file mode 100644
index 0000000..ff2b05f
--- /dev/null
+++ b/test/CodeGen/X86/2008-07-11-SHLBy1.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=x86-64 -o - | not grep shr
+define i128 @sl(i128 %x) {
+ %t = shl i128 %x, 1
+ ret i128 %t
+}
diff --git a/test/CodeGen/X86/2008-07-11-SpillerBug.ll b/test/CodeGen/X86/2008-07-11-SpillerBug.ll
new file mode 100644
index 0000000..cd99c0e
--- /dev/null
+++ b/test/CodeGen/X86/2008-07-11-SpillerBug.ll
@@ -0,0 +1,54 @@
+; RUN: llc < %s -march=x86 -relocation-model=static -disable-fp-elim -post-RA-scheduler=false -asm-verbose=0 | FileCheck %s
+; PR2536
+
+
+; CHECK: movw %cx
+; CHECK-NEXT: andl $65534, %
+; CHECK-NEXT: movl %
+; CHECK-NEXT: movl $17
+
+@g_5 = external global i16 ; <i16*> [#uses=2]
+@g_107 = external global i16 ; <i16*> [#uses=1]
+@g_229 = external global i32 ; <i32*> [#uses=1]
+@g_227 = external global i16 ; <i16*> [#uses=1]
+
+define i32 @func_54(i32 %p_55, i16 zeroext %p_56) nounwind {
+entry:
+ load i16* @g_5, align 2 ; <i16>:0 [#uses=1]
+ zext i16 %0 to i32 ; <i32>:1 [#uses=1]
+ %.mask = and i32 %1, 65534 ; <i32> [#uses=1]
+ icmp eq i32 %.mask, 0 ; <i1>:2 [#uses=1]
+ load i32* @g_229, align 4 ; <i32>:3 [#uses=1]
+ load i16* @g_227, align 2 ; <i16>:4 [#uses=1]
+ icmp eq i16 %4, 0 ; <i1>:5 [#uses=1]
+ load i16* @g_5, align 2 ; <i16>:6 [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb7.preheader, %entry
+ %indvar4 = phi i32 [ 0, %entry ], [ %indvar.next5, %bb7.preheader ] ; <i32> [#uses=1]
+ %p_56_addr.1.reg2mem.0 = phi i16 [ %p_56, %entry ], [ %p_56_addr.0, %bb7.preheader ] ; <i16> [#uses=2]
+ br i1 %2, label %bb7.preheader, label %bb5
+
+bb5: ; preds = %bb
+ store i16 %6, i16* @g_107, align 2
+ br label %bb7.preheader
+
+bb7.preheader: ; preds = %bb5, %bb
+ icmp eq i16 %p_56_addr.1.reg2mem.0, 0 ; <i1>:7 [#uses=1]
+ %.0 = select i1 %7, i32 1, i32 %3 ; <i32> [#uses=1]
+ urem i32 1, %.0 ; <i32>:8 [#uses=1]
+ icmp eq i32 %8, 0 ; <i1>:9 [#uses=1]
+ %.not = xor i1 %9, true ; <i1> [#uses=1]
+ %.not1 = xor i1 %5, true ; <i1> [#uses=1]
+ %brmerge = or i1 %.not, %.not1 ; <i1> [#uses=1]
+ %iftmp.6.0 = select i1 %brmerge, i32 3, i32 0 ; <i32> [#uses=1]
+ mul i32 %iftmp.6.0, %3 ; <i32>:10 [#uses=1]
+ icmp eq i32 %10, 0 ; <i1>:11 [#uses=1]
+ %p_56_addr.0 = select i1 %11, i16 %p_56_addr.1.reg2mem.0, i16 1 ; <i16> [#uses=1]
+ %indvar.next5 = add i32 %indvar4, 1 ; <i32> [#uses=2]
+ %exitcond6 = icmp eq i32 %indvar.next5, 17 ; <i1> [#uses=1]
+ br i1 %exitcond6, label %bb25, label %bb
+
+bb25: ; preds = %bb7.preheader
+ ret i32 1
+}
diff --git a/test/CodeGen/X86/2008-07-16-CoalescerCrash.ll b/test/CodeGen/X86/2008-07-16-CoalescerCrash.ll
new file mode 100644
index 0000000..f56604b
--- /dev/null
+++ b/test/CodeGen/X86/2008-07-16-CoalescerCrash.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin
+
+ %struct.SV = type { i8*, i64, i64 }
+@"\01LC25" = external constant [8 x i8] ; <[8 x i8]*> [#uses=1]
+
+declare void @Perl_sv_catpvf(%struct.SV*, i8*, ...) nounwind
+
+declare fastcc i64 @Perl_utf8n_to_uvuni(i8*, i64, i64*, i64) nounwind
+
+define fastcc i8* @Perl_pv_uni_display(%struct.SV* %dsv, i8* %spv, i64 %len, i64 %pvlim, i64 %flags) nounwind {
+entry:
+ br i1 false, label %bb, label %bb40
+
+bb: ; preds = %entry
+ tail call fastcc i64 @Perl_utf8n_to_uvuni( i8* null, i64 13, i64* null, i64 255 ) nounwind ; <i64>:0 [#uses=1]
+ br i1 false, label %bb6, label %bb33
+
+bb6: ; preds = %bb
+ br i1 false, label %bb30, label %bb31
+
+bb30: ; preds = %bb6
+ unreachable
+
+bb31: ; preds = %bb6
+ icmp eq i8 0, 0 ; <i1>:1 [#uses=0]
+ br label %bb33
+
+bb33: ; preds = %bb31, %bb
+ tail call void (%struct.SV*, i8*, ...)* @Perl_sv_catpvf( %struct.SV* %dsv, i8* getelementptr ([8 x i8]* @"\01LC25", i32 0, i64 0), i64 %0 ) nounwind
+ unreachable
+
+bb40: ; preds = %entry
+ ret i8* null
+}
diff --git a/test/CodeGen/X86/2008-07-19-movups-spills.ll b/test/CodeGen/X86/2008-07-19-movups-spills.ll
new file mode 100644
index 0000000..98919ee
--- /dev/null
+++ b/test/CodeGen/X86/2008-07-19-movups-spills.ll
@@ -0,0 +1,636 @@
+; RUN: llc < %s -mtriple=i686-pc-linux -realign-stack=1 -mattr=sse2 | grep movaps | count 75
+; RUN: llc < %s -mtriple=i686-pc-linux -realign-stack=0 -mattr=sse2 | grep movaps | count 1
+; PR2539
+
+external global <4 x float>, align 1 ; <<4 x float>*>:0 [#uses=2]
+external global <4 x float>, align 1 ; <<4 x float>*>:1 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:2 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:3 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:4 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:5 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:6 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:7 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:8 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:9 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:10 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:11 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:12 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:13 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:14 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:15 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:16 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:17 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:18 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:19 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:20 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:21 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:22 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:23 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:24 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:25 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:26 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:27 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:28 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:29 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:30 [#uses=1]
+external global <4 x float>, align 1 ; <<4 x float>*>:31 [#uses=1]
+
+declare void @abort()
+
+define void @""() {
+ load <4 x float>* @0, align 1 ; <<4 x float>>:1 [#uses=2]
+ load <4 x float>* @1, align 1 ; <<4 x float>>:2 [#uses=3]
+ load <4 x float>* @2, align 1 ; <<4 x float>>:3 [#uses=4]
+ load <4 x float>* @3, align 1 ; <<4 x float>>:4 [#uses=5]
+ load <4 x float>* @4, align 1 ; <<4 x float>>:5 [#uses=6]
+ load <4 x float>* @5, align 1 ; <<4 x float>>:6 [#uses=7]
+ load <4 x float>* @6, align 1 ; <<4 x float>>:7 [#uses=8]
+ load <4 x float>* @7, align 1 ; <<4 x float>>:8 [#uses=9]
+ load <4 x float>* @8, align 1 ; <<4 x float>>:9 [#uses=10]
+ load <4 x float>* @9, align 1 ; <<4 x float>>:10 [#uses=11]
+ load <4 x float>* @10, align 1 ; <<4 x float>>:11 [#uses=12]
+ load <4 x float>* @11, align 1 ; <<4 x float>>:12 [#uses=13]
+ load <4 x float>* @12, align 1 ; <<4 x float>>:13 [#uses=14]
+ load <4 x float>* @13, align 1 ; <<4 x float>>:14 [#uses=15]
+ load <4 x float>* @14, align 1 ; <<4 x float>>:15 [#uses=16]
+ load <4 x float>* @15, align 1 ; <<4 x float>>:16 [#uses=17]
+ load <4 x float>* @16, align 1 ; <<4 x float>>:17 [#uses=18]
+ load <4 x float>* @17, align 1 ; <<4 x float>>:18 [#uses=19]
+ load <4 x float>* @18, align 1 ; <<4 x float>>:19 [#uses=20]
+ load <4 x float>* @19, align 1 ; <<4 x float>>:20 [#uses=21]
+ load <4 x float>* @20, align 1 ; <<4 x float>>:21 [#uses=22]
+ load <4 x float>* @21, align 1 ; <<4 x float>>:22 [#uses=23]
+ load <4 x float>* @22, align 1 ; <<4 x float>>:23 [#uses=24]
+ load <4 x float>* @23, align 1 ; <<4 x float>>:24 [#uses=25]
+ load <4 x float>* @24, align 1 ; <<4 x float>>:25 [#uses=26]
+ load <4 x float>* @25, align 1 ; <<4 x float>>:26 [#uses=27]
+ load <4 x float>* @26, align 1 ; <<4 x float>>:27 [#uses=28]
+ load <4 x float>* @27, align 1 ; <<4 x float>>:28 [#uses=29]
+ load <4 x float>* @28, align 1 ; <<4 x float>>:29 [#uses=30]
+ load <4 x float>* @29, align 1 ; <<4 x float>>:30 [#uses=31]
+ load <4 x float>* @30, align 1 ; <<4 x float>>:31 [#uses=32]
+ load <4 x float>* @31, align 1 ; <<4 x float>>:32 [#uses=33]
+ fmul <4 x float> %1, %1 ; <<4 x float>>:33 [#uses=1]
+ fmul <4 x float> %33, %2 ; <<4 x float>>:34 [#uses=1]
+ fmul <4 x float> %34, %3 ; <<4 x float>>:35 [#uses=1]
+ fmul <4 x float> %35, %4 ; <<4 x float>>:36 [#uses=1]
+ fmul <4 x float> %36, %5 ; <<4 x float>>:37 [#uses=1]
+ fmul <4 x float> %37, %6 ; <<4 x float>>:38 [#uses=1]
+ fmul <4 x float> %38, %7 ; <<4 x float>>:39 [#uses=1]
+ fmul <4 x float> %39, %8 ; <<4 x float>>:40 [#uses=1]
+ fmul <4 x float> %40, %9 ; <<4 x float>>:41 [#uses=1]
+ fmul <4 x float> %41, %10 ; <<4 x float>>:42 [#uses=1]
+ fmul <4 x float> %42, %11 ; <<4 x float>>:43 [#uses=1]
+ fmul <4 x float> %43, %12 ; <<4 x float>>:44 [#uses=1]
+ fmul <4 x float> %44, %13 ; <<4 x float>>:45 [#uses=1]
+ fmul <4 x float> %45, %14 ; <<4 x float>>:46 [#uses=1]
+ fmul <4 x float> %46, %15 ; <<4 x float>>:47 [#uses=1]
+ fmul <4 x float> %47, %16 ; <<4 x float>>:48 [#uses=1]
+ fmul <4 x float> %48, %17 ; <<4 x float>>:49 [#uses=1]
+ fmul <4 x float> %49, %18 ; <<4 x float>>:50 [#uses=1]
+ fmul <4 x float> %50, %19 ; <<4 x float>>:51 [#uses=1]
+ fmul <4 x float> %51, %20 ; <<4 x float>>:52 [#uses=1]
+ fmul <4 x float> %52, %21 ; <<4 x float>>:53 [#uses=1]
+ fmul <4 x float> %53, %22 ; <<4 x float>>:54 [#uses=1]
+ fmul <4 x float> %54, %23 ; <<4 x float>>:55 [#uses=1]
+ fmul <4 x float> %55, %24 ; <<4 x float>>:56 [#uses=1]
+ fmul <4 x float> %56, %25 ; <<4 x float>>:57 [#uses=1]
+ fmul <4 x float> %57, %26 ; <<4 x float>>:58 [#uses=1]
+ fmul <4 x float> %58, %27 ; <<4 x float>>:59 [#uses=1]
+ fmul <4 x float> %59, %28 ; <<4 x float>>:60 [#uses=1]
+ fmul <4 x float> %60, %29 ; <<4 x float>>:61 [#uses=1]
+ fmul <4 x float> %61, %30 ; <<4 x float>>:62 [#uses=1]
+ fmul <4 x float> %62, %31 ; <<4 x float>>:63 [#uses=1]
+ fmul <4 x float> %63, %32 ; <<4 x float>>:64 [#uses=3]
+ fmul <4 x float> %2, %2 ; <<4 x float>>:65 [#uses=1]
+ fmul <4 x float> %65, %3 ; <<4 x float>>:66 [#uses=1]
+ fmul <4 x float> %66, %4 ; <<4 x float>>:67 [#uses=1]
+ fmul <4 x float> %67, %5 ; <<4 x float>>:68 [#uses=1]
+ fmul <4 x float> %68, %6 ; <<4 x float>>:69 [#uses=1]
+ fmul <4 x float> %69, %7 ; <<4 x float>>:70 [#uses=1]
+ fmul <4 x float> %70, %8 ; <<4 x float>>:71 [#uses=1]
+ fmul <4 x float> %71, %9 ; <<4 x float>>:72 [#uses=1]
+ fmul <4 x float> %72, %10 ; <<4 x float>>:73 [#uses=1]
+ fmul <4 x float> %73, %11 ; <<4 x float>>:74 [#uses=1]
+ fmul <4 x float> %74, %12 ; <<4 x float>>:75 [#uses=1]
+ fmul <4 x float> %75, %13 ; <<4 x float>>:76 [#uses=1]
+ fmul <4 x float> %76, %14 ; <<4 x float>>:77 [#uses=1]
+ fmul <4 x float> %77, %15 ; <<4 x float>>:78 [#uses=1]
+ fmul <4 x float> %78, %16 ; <<4 x float>>:79 [#uses=1]
+ fmul <4 x float> %79, %17 ; <<4 x float>>:80 [#uses=1]
+ fmul <4 x float> %80, %18 ; <<4 x float>>:81 [#uses=1]
+ fmul <4 x float> %81, %19 ; <<4 x float>>:82 [#uses=1]
+ fmul <4 x float> %82, %20 ; <<4 x float>>:83 [#uses=1]
+ fmul <4 x float> %83, %21 ; <<4 x float>>:84 [#uses=1]
+ fmul <4 x float> %84, %22 ; <<4 x float>>:85 [#uses=1]
+ fmul <4 x float> %85, %23 ; <<4 x float>>:86 [#uses=1]
+ fmul <4 x float> %86, %24 ; <<4 x float>>:87 [#uses=1]
+ fmul <4 x float> %87, %25 ; <<4 x float>>:88 [#uses=1]
+ fmul <4 x float> %88, %26 ; <<4 x float>>:89 [#uses=1]
+ fmul <4 x float> %89, %27 ; <<4 x float>>:90 [#uses=1]
+ fmul <4 x float> %90, %28 ; <<4 x float>>:91 [#uses=1]
+ fmul <4 x float> %91, %29 ; <<4 x float>>:92 [#uses=1]
+ fmul <4 x float> %92, %30 ; <<4 x float>>:93 [#uses=1]
+ fmul <4 x float> %93, %31 ; <<4 x float>>:94 [#uses=1]
+ fmul <4 x float> %94, %32 ; <<4 x float>>:95 [#uses=1]
+ fmul <4 x float> %3, %3 ; <<4 x float>>:96 [#uses=1]
+ fmul <4 x float> %96, %4 ; <<4 x float>>:97 [#uses=1]
+ fmul <4 x float> %97, %5 ; <<4 x float>>:98 [#uses=1]
+ fmul <4 x float> %98, %6 ; <<4 x float>>:99 [#uses=1]
+ fmul <4 x float> %99, %7 ; <<4 x float>>:100 [#uses=1]
+ fmul <4 x float> %100, %8 ; <<4 x float>>:101 [#uses=1]
+ fmul <4 x float> %101, %9 ; <<4 x float>>:102 [#uses=1]
+ fmul <4 x float> %102, %10 ; <<4 x float>>:103 [#uses=1]
+ fmul <4 x float> %103, %11 ; <<4 x float>>:104 [#uses=1]
+ fmul <4 x float> %104, %12 ; <<4 x float>>:105 [#uses=1]
+ fmul <4 x float> %105, %13 ; <<4 x float>>:106 [#uses=1]
+ fmul <4 x float> %106, %14 ; <<4 x float>>:107 [#uses=1]
+ fmul <4 x float> %107, %15 ; <<4 x float>>:108 [#uses=1]
+ fmul <4 x float> %108, %16 ; <<4 x float>>:109 [#uses=1]
+ fmul <4 x float> %109, %17 ; <<4 x float>>:110 [#uses=1]
+ fmul <4 x float> %110, %18 ; <<4 x float>>:111 [#uses=1]
+ fmul <4 x float> %111, %19 ; <<4 x float>>:112 [#uses=1]
+ fmul <4 x float> %112, %20 ; <<4 x float>>:113 [#uses=1]
+ fmul <4 x float> %113, %21 ; <<4 x float>>:114 [#uses=1]
+ fmul <4 x float> %114, %22 ; <<4 x float>>:115 [#uses=1]
+ fmul <4 x float> %115, %23 ; <<4 x float>>:116 [#uses=1]
+ fmul <4 x float> %116, %24 ; <<4 x float>>:117 [#uses=1]
+ fmul <4 x float> %117, %25 ; <<4 x float>>:118 [#uses=1]
+ fmul <4 x float> %118, %26 ; <<4 x float>>:119 [#uses=1]
+ fmul <4 x float> %119, %27 ; <<4 x float>>:120 [#uses=1]
+ fmul <4 x float> %120, %28 ; <<4 x float>>:121 [#uses=1]
+ fmul <4 x float> %121, %29 ; <<4 x float>>:122 [#uses=1]
+ fmul <4 x float> %122, %30 ; <<4 x float>>:123 [#uses=1]
+ fmul <4 x float> %123, %31 ; <<4 x float>>:124 [#uses=1]
+ fmul <4 x float> %124, %32 ; <<4 x float>>:125 [#uses=1]
+ fmul <4 x float> %4, %4 ; <<4 x float>>:126 [#uses=1]
+ fmul <4 x float> %126, %5 ; <<4 x float>>:127 [#uses=1]
+ fmul <4 x float> %127, %6 ; <<4 x float>>:128 [#uses=1]
+ fmul <4 x float> %128, %7 ; <<4 x float>>:129 [#uses=1]
+ fmul <4 x float> %129, %8 ; <<4 x float>>:130 [#uses=1]
+ fmul <4 x float> %130, %9 ; <<4 x float>>:131 [#uses=1]
+ fmul <4 x float> %131, %10 ; <<4 x float>>:132 [#uses=1]
+ fmul <4 x float> %132, %11 ; <<4 x float>>:133 [#uses=1]
+ fmul <4 x float> %133, %12 ; <<4 x float>>:134 [#uses=1]
+ fmul <4 x float> %134, %13 ; <<4 x float>>:135 [#uses=1]
+ fmul <4 x float> %135, %14 ; <<4 x float>>:136 [#uses=1]
+ fmul <4 x float> %136, %15 ; <<4 x float>>:137 [#uses=1]
+ fmul <4 x float> %137, %16 ; <<4 x float>>:138 [#uses=1]
+ fmul <4 x float> %138, %17 ; <<4 x float>>:139 [#uses=1]
+ fmul <4 x float> %139, %18 ; <<4 x float>>:140 [#uses=1]
+ fmul <4 x float> %140, %19 ; <<4 x float>>:141 [#uses=1]
+ fmul <4 x float> %141, %20 ; <<4 x float>>:142 [#uses=1]
+ fmul <4 x float> %142, %21 ; <<4 x float>>:143 [#uses=1]
+ fmul <4 x float> %143, %22 ; <<4 x float>>:144 [#uses=1]
+ fmul <4 x float> %144, %23 ; <<4 x float>>:145 [#uses=1]
+ fmul <4 x float> %145, %24 ; <<4 x float>>:146 [#uses=1]
+ fmul <4 x float> %146, %25 ; <<4 x float>>:147 [#uses=1]
+ fmul <4 x float> %147, %26 ; <<4 x float>>:148 [#uses=1]
+ fmul <4 x float> %148, %27 ; <<4 x float>>:149 [#uses=1]
+ fmul <4 x float> %149, %28 ; <<4 x float>>:150 [#uses=1]
+ fmul <4 x float> %150, %29 ; <<4 x float>>:151 [#uses=1]
+ fmul <4 x float> %151, %30 ; <<4 x float>>:152 [#uses=1]
+ fmul <4 x float> %152, %31 ; <<4 x float>>:153 [#uses=1]
+ fmul <4 x float> %153, %32 ; <<4 x float>>:154 [#uses=1]
+ fmul <4 x float> %5, %5 ; <<4 x float>>:155 [#uses=1]
+ fmul <4 x float> %155, %6 ; <<4 x float>>:156 [#uses=1]
+ fmul <4 x float> %156, %7 ; <<4 x float>>:157 [#uses=1]
+ fmul <4 x float> %157, %8 ; <<4 x float>>:158 [#uses=1]
+ fmul <4 x float> %158, %9 ; <<4 x float>>:159 [#uses=1]
+ fmul <4 x float> %159, %10 ; <<4 x float>>:160 [#uses=1]
+ fmul <4 x float> %160, %11 ; <<4 x float>>:161 [#uses=1]
+ fmul <4 x float> %161, %12 ; <<4 x float>>:162 [#uses=1]
+ fmul <4 x float> %162, %13 ; <<4 x float>>:163 [#uses=1]
+ fmul <4 x float> %163, %14 ; <<4 x float>>:164 [#uses=1]
+ fmul <4 x float> %164, %15 ; <<4 x float>>:165 [#uses=1]
+ fmul <4 x float> %165, %16 ; <<4 x float>>:166 [#uses=1]
+ fmul <4 x float> %166, %17 ; <<4 x float>>:167 [#uses=1]
+ fmul <4 x float> %167, %18 ; <<4 x float>>:168 [#uses=1]
+ fmul <4 x float> %168, %19 ; <<4 x float>>:169 [#uses=1]
+ fmul <4 x float> %169, %20 ; <<4 x float>>:170 [#uses=1]
+ fmul <4 x float> %170, %21 ; <<4 x float>>:171 [#uses=1]
+ fmul <4 x float> %171, %22 ; <<4 x float>>:172 [#uses=1]
+ fmul <4 x float> %172, %23 ; <<4 x float>>:173 [#uses=1]
+ fmul <4 x float> %173, %24 ; <<4 x float>>:174 [#uses=1]
+ fmul <4 x float> %174, %25 ; <<4 x float>>:175 [#uses=1]
+ fmul <4 x float> %175, %26 ; <<4 x float>>:176 [#uses=1]
+ fmul <4 x float> %176, %27 ; <<4 x float>>:177 [#uses=1]
+ fmul <4 x float> %177, %28 ; <<4 x float>>:178 [#uses=1]
+ fmul <4 x float> %178, %29 ; <<4 x float>>:179 [#uses=1]
+ fmul <4 x float> %179, %30 ; <<4 x float>>:180 [#uses=1]
+ fmul <4 x float> %180, %31 ; <<4 x float>>:181 [#uses=1]
+ fmul <4 x float> %181, %32 ; <<4 x float>>:182 [#uses=1]
+ fmul <4 x float> %6, %6 ; <<4 x float>>:183 [#uses=1]
+ fmul <4 x float> %183, %7 ; <<4 x float>>:184 [#uses=1]
+ fmul <4 x float> %184, %8 ; <<4 x float>>:185 [#uses=1]
+ fmul <4 x float> %185, %9 ; <<4 x float>>:186 [#uses=1]
+ fmul <4 x float> %186, %10 ; <<4 x float>>:187 [#uses=1]
+ fmul <4 x float> %187, %11 ; <<4 x float>>:188 [#uses=1]
+ fmul <4 x float> %188, %12 ; <<4 x float>>:189 [#uses=1]
+ fmul <4 x float> %189, %13 ; <<4 x float>>:190 [#uses=1]
+ fmul <4 x float> %190, %14 ; <<4 x float>>:191 [#uses=1]
+ fmul <4 x float> %191, %15 ; <<4 x float>>:192 [#uses=1]
+ fmul <4 x float> %192, %16 ; <<4 x float>>:193 [#uses=1]
+ fmul <4 x float> %193, %17 ; <<4 x float>>:194 [#uses=1]
+ fmul <4 x float> %194, %18 ; <<4 x float>>:195 [#uses=1]
+ fmul <4 x float> %195, %19 ; <<4 x float>>:196 [#uses=1]
+ fmul <4 x float> %196, %20 ; <<4 x float>>:197 [#uses=1]
+ fmul <4 x float> %197, %21 ; <<4 x float>>:198 [#uses=1]
+ fmul <4 x float> %198, %22 ; <<4 x float>>:199 [#uses=1]
+ fmul <4 x float> %199, %23 ; <<4 x float>>:200 [#uses=1]
+ fmul <4 x float> %200, %24 ; <<4 x float>>:201 [#uses=1]
+ fmul <4 x float> %201, %25 ; <<4 x float>>:202 [#uses=1]
+ fmul <4 x float> %202, %26 ; <<4 x float>>:203 [#uses=1]
+ fmul <4 x float> %203, %27 ; <<4 x float>>:204 [#uses=1]
+ fmul <4 x float> %204, %28 ; <<4 x float>>:205 [#uses=1]
+ fmul <4 x float> %205, %29 ; <<4 x float>>:206 [#uses=1]
+ fmul <4 x float> %206, %30 ; <<4 x float>>:207 [#uses=1]
+ fmul <4 x float> %207, %31 ; <<4 x float>>:208 [#uses=1]
+ fmul <4 x float> %208, %32 ; <<4 x float>>:209 [#uses=1]
+ fmul <4 x float> %7, %7 ; <<4 x float>>:210 [#uses=1]
+ fmul <4 x float> %210, %8 ; <<4 x float>>:211 [#uses=1]
+ fmul <4 x float> %211, %9 ; <<4 x float>>:212 [#uses=1]
+ fmul <4 x float> %212, %10 ; <<4 x float>>:213 [#uses=1]
+ fmul <4 x float> %213, %11 ; <<4 x float>>:214 [#uses=1]
+ fmul <4 x float> %214, %12 ; <<4 x float>>:215 [#uses=1]
+ fmul <4 x float> %215, %13 ; <<4 x float>>:216 [#uses=1]
+ fmul <4 x float> %216, %14 ; <<4 x float>>:217 [#uses=1]
+ fmul <4 x float> %217, %15 ; <<4 x float>>:218 [#uses=1]
+ fmul <4 x float> %218, %16 ; <<4 x float>>:219 [#uses=1]
+ fmul <4 x float> %219, %17 ; <<4 x float>>:220 [#uses=1]
+ fmul <4 x float> %220, %18 ; <<4 x float>>:221 [#uses=1]
+ fmul <4 x float> %221, %19 ; <<4 x float>>:222 [#uses=1]
+ fmul <4 x float> %222, %20 ; <<4 x float>>:223 [#uses=1]
+ fmul <4 x float> %223, %21 ; <<4 x float>>:224 [#uses=1]
+ fmul <4 x float> %224, %22 ; <<4 x float>>:225 [#uses=1]
+ fmul <4 x float> %225, %23 ; <<4 x float>>:226 [#uses=1]
+ fmul <4 x float> %226, %24 ; <<4 x float>>:227 [#uses=1]
+ fmul <4 x float> %227, %25 ; <<4 x float>>:228 [#uses=1]
+ fmul <4 x float> %228, %26 ; <<4 x float>>:229 [#uses=1]
+ fmul <4 x float> %229, %27 ; <<4 x float>>:230 [#uses=1]
+ fmul <4 x float> %230, %28 ; <<4 x float>>:231 [#uses=1]
+ fmul <4 x float> %231, %29 ; <<4 x float>>:232 [#uses=1]
+ fmul <4 x float> %232, %30 ; <<4 x float>>:233 [#uses=1]
+ fmul <4 x float> %233, %31 ; <<4 x float>>:234 [#uses=1]
+ fmul <4 x float> %234, %32 ; <<4 x float>>:235 [#uses=1]
+ fmul <4 x float> %8, %8 ; <<4 x float>>:236 [#uses=1]
+ fmul <4 x float> %236, %9 ; <<4 x float>>:237 [#uses=1]
+ fmul <4 x float> %237, %10 ; <<4 x float>>:238 [#uses=1]
+ fmul <4 x float> %238, %11 ; <<4 x float>>:239 [#uses=1]
+ fmul <4 x float> %239, %12 ; <<4 x float>>:240 [#uses=1]
+ fmul <4 x float> %240, %13 ; <<4 x float>>:241 [#uses=1]
+ fmul <4 x float> %241, %14 ; <<4 x float>>:242 [#uses=1]
+ fmul <4 x float> %242, %15 ; <<4 x float>>:243 [#uses=1]
+ fmul <4 x float> %243, %16 ; <<4 x float>>:244 [#uses=1]
+ fmul <4 x float> %244, %17 ; <<4 x float>>:245 [#uses=1]
+ fmul <4 x float> %245, %18 ; <<4 x float>>:246 [#uses=1]
+ fmul <4 x float> %246, %19 ; <<4 x float>>:247 [#uses=1]
+ fmul <4 x float> %247, %20 ; <<4 x float>>:248 [#uses=1]
+ fmul <4 x float> %248, %21 ; <<4 x float>>:249 [#uses=1]
+ fmul <4 x float> %249, %22 ; <<4 x float>>:250 [#uses=1]
+ fmul <4 x float> %250, %23 ; <<4 x float>>:251 [#uses=1]
+ fmul <4 x float> %251, %24 ; <<4 x float>>:252 [#uses=1]
+ fmul <4 x float> %252, %25 ; <<4 x float>>:253 [#uses=1]
+ fmul <4 x float> %253, %26 ; <<4 x float>>:254 [#uses=1]
+ fmul <4 x float> %254, %27 ; <<4 x float>>:255 [#uses=1]
+ fmul <4 x float> %255, %28 ; <<4 x float>>:256 [#uses=1]
+ fmul <4 x float> %256, %29 ; <<4 x float>>:257 [#uses=1]
+ fmul <4 x float> %257, %30 ; <<4 x float>>:258 [#uses=1]
+ fmul <4 x float> %258, %31 ; <<4 x float>>:259 [#uses=1]
+ fmul <4 x float> %259, %32 ; <<4 x float>>:260 [#uses=1]
+ fmul <4 x float> %9, %9 ; <<4 x float>>:261 [#uses=1]
+ fmul <4 x float> %261, %10 ; <<4 x float>>:262 [#uses=1]
+ fmul <4 x float> %262, %11 ; <<4 x float>>:263 [#uses=1]
+ fmul <4 x float> %263, %12 ; <<4 x float>>:264 [#uses=1]
+ fmul <4 x float> %264, %13 ; <<4 x float>>:265 [#uses=1]
+ fmul <4 x float> %265, %14 ; <<4 x float>>:266 [#uses=1]
+ fmul <4 x float> %266, %15 ; <<4 x float>>:267 [#uses=1]
+ fmul <4 x float> %267, %16 ; <<4 x float>>:268 [#uses=1]
+ fmul <4 x float> %268, %17 ; <<4 x float>>:269 [#uses=1]
+ fmul <4 x float> %269, %18 ; <<4 x float>>:270 [#uses=1]
+ fmul <4 x float> %270, %19 ; <<4 x float>>:271 [#uses=1]
+ fmul <4 x float> %271, %20 ; <<4 x float>>:272 [#uses=1]
+ fmul <4 x float> %272, %21 ; <<4 x float>>:273 [#uses=1]
+ fmul <4 x float> %273, %22 ; <<4 x float>>:274 [#uses=1]
+ fmul <4 x float> %274, %23 ; <<4 x float>>:275 [#uses=1]
+ fmul <4 x float> %275, %24 ; <<4 x float>>:276 [#uses=1]
+ fmul <4 x float> %276, %25 ; <<4 x float>>:277 [#uses=1]
+ fmul <4 x float> %277, %26 ; <<4 x float>>:278 [#uses=1]
+ fmul <4 x float> %278, %27 ; <<4 x float>>:279 [#uses=1]
+ fmul <4 x float> %279, %28 ; <<4 x float>>:280 [#uses=1]
+ fmul <4 x float> %280, %29 ; <<4 x float>>:281 [#uses=1]
+ fmul <4 x float> %281, %30 ; <<4 x float>>:282 [#uses=1]
+ fmul <4 x float> %282, %31 ; <<4 x float>>:283 [#uses=1]
+ fmul <4 x float> %283, %32 ; <<4 x float>>:284 [#uses=1]
+ fmul <4 x float> %10, %10 ; <<4 x float>>:285 [#uses=1]
+ fmul <4 x float> %285, %11 ; <<4 x float>>:286 [#uses=1]
+ fmul <4 x float> %286, %12 ; <<4 x float>>:287 [#uses=1]
+ fmul <4 x float> %287, %13 ; <<4 x float>>:288 [#uses=1]
+ fmul <4 x float> %288, %14 ; <<4 x float>>:289 [#uses=1]
+ fmul <4 x float> %289, %15 ; <<4 x float>>:290 [#uses=1]
+ fmul <4 x float> %290, %16 ; <<4 x float>>:291 [#uses=1]
+ fmul <4 x float> %291, %17 ; <<4 x float>>:292 [#uses=1]
+ fmul <4 x float> %292, %18 ; <<4 x float>>:293 [#uses=1]
+ fmul <4 x float> %293, %19 ; <<4 x float>>:294 [#uses=1]
+ fmul <4 x float> %294, %20 ; <<4 x float>>:295 [#uses=1]
+ fmul <4 x float> %295, %21 ; <<4 x float>>:296 [#uses=1]
+ fmul <4 x float> %296, %22 ; <<4 x float>>:297 [#uses=1]
+ fmul <4 x float> %297, %23 ; <<4 x float>>:298 [#uses=1]
+ fmul <4 x float> %298, %24 ; <<4 x float>>:299 [#uses=1]
+ fmul <4 x float> %299, %25 ; <<4 x float>>:300 [#uses=1]
+ fmul <4 x float> %300, %26 ; <<4 x float>>:301 [#uses=1]
+ fmul <4 x float> %301, %27 ; <<4 x float>>:302 [#uses=1]
+ fmul <4 x float> %302, %28 ; <<4 x float>>:303 [#uses=1]
+ fmul <4 x float> %303, %29 ; <<4 x float>>:304 [#uses=1]
+ fmul <4 x float> %304, %30 ; <<4 x float>>:305 [#uses=1]
+ fmul <4 x float> %305, %31 ; <<4 x float>>:306 [#uses=1]
+ fmul <4 x float> %306, %32 ; <<4 x float>>:307 [#uses=1]
+ fmul <4 x float> %11, %11 ; <<4 x float>>:308 [#uses=1]
+ fmul <4 x float> %308, %12 ; <<4 x float>>:309 [#uses=1]
+ fmul <4 x float> %309, %13 ; <<4 x float>>:310 [#uses=1]
+ fmul <4 x float> %310, %14 ; <<4 x float>>:311 [#uses=1]
+ fmul <4 x float> %311, %15 ; <<4 x float>>:312 [#uses=1]
+ fmul <4 x float> %312, %16 ; <<4 x float>>:313 [#uses=1]
+ fmul <4 x float> %313, %17 ; <<4 x float>>:314 [#uses=1]
+ fmul <4 x float> %314, %18 ; <<4 x float>>:315 [#uses=1]
+ fmul <4 x float> %315, %19 ; <<4 x float>>:316 [#uses=1]
+ fmul <4 x float> %316, %20 ; <<4 x float>>:317 [#uses=1]
+ fmul <4 x float> %317, %21 ; <<4 x float>>:318 [#uses=1]
+ fmul <4 x float> %318, %22 ; <<4 x float>>:319 [#uses=1]
+ fmul <4 x float> %319, %23 ; <<4 x float>>:320 [#uses=1]
+ fmul <4 x float> %320, %24 ; <<4 x float>>:321 [#uses=1]
+ fmul <4 x float> %321, %25 ; <<4 x float>>:322 [#uses=1]
+ fmul <4 x float> %322, %26 ; <<4 x float>>:323 [#uses=1]
+ fmul <4 x float> %323, %27 ; <<4 x float>>:324 [#uses=1]
+ fmul <4 x float> %324, %28 ; <<4 x float>>:325 [#uses=1]
+ fmul <4 x float> %325, %29 ; <<4 x float>>:326 [#uses=1]
+ fmul <4 x float> %326, %30 ; <<4 x float>>:327 [#uses=1]
+ fmul <4 x float> %327, %31 ; <<4 x float>>:328 [#uses=1]
+ fmul <4 x float> %328, %32 ; <<4 x float>>:329 [#uses=1]
+ fmul <4 x float> %12, %12 ; <<4 x float>>:330 [#uses=1]
+ fmul <4 x float> %330, %13 ; <<4 x float>>:331 [#uses=1]
+ fmul <4 x float> %331, %14 ; <<4 x float>>:332 [#uses=1]
+ fmul <4 x float> %332, %15 ; <<4 x float>>:333 [#uses=1]
+ fmul <4 x float> %333, %16 ; <<4 x float>>:334 [#uses=1]
+ fmul <4 x float> %334, %17 ; <<4 x float>>:335 [#uses=1]
+ fmul <4 x float> %335, %18 ; <<4 x float>>:336 [#uses=1]
+ fmul <4 x float> %336, %19 ; <<4 x float>>:337 [#uses=1]
+ fmul <4 x float> %337, %20 ; <<4 x float>>:338 [#uses=1]
+ fmul <4 x float> %338, %21 ; <<4 x float>>:339 [#uses=1]
+ fmul <4 x float> %339, %22 ; <<4 x float>>:340 [#uses=1]
+ fmul <4 x float> %340, %23 ; <<4 x float>>:341 [#uses=1]
+ fmul <4 x float> %341, %24 ; <<4 x float>>:342 [#uses=1]
+ fmul <4 x float> %342, %25 ; <<4 x float>>:343 [#uses=1]
+ fmul <4 x float> %343, %26 ; <<4 x float>>:344 [#uses=1]
+ fmul <4 x float> %344, %27 ; <<4 x float>>:345 [#uses=1]
+ fmul <4 x float> %345, %28 ; <<4 x float>>:346 [#uses=1]
+ fmul <4 x float> %346, %29 ; <<4 x float>>:347 [#uses=1]
+ fmul <4 x float> %347, %30 ; <<4 x float>>:348 [#uses=1]
+ fmul <4 x float> %348, %31 ; <<4 x float>>:349 [#uses=1]
+ fmul <4 x float> %349, %32 ; <<4 x float>>:350 [#uses=1]
+ fmul <4 x float> %13, %13 ; <<4 x float>>:351 [#uses=1]
+ fmul <4 x float> %351, %14 ; <<4 x float>>:352 [#uses=1]
+ fmul <4 x float> %352, %15 ; <<4 x float>>:353 [#uses=1]
+ fmul <4 x float> %353, %16 ; <<4 x float>>:354 [#uses=1]
+ fmul <4 x float> %354, %17 ; <<4 x float>>:355 [#uses=1]
+ fmul <4 x float> %355, %18 ; <<4 x float>>:356 [#uses=1]
+ fmul <4 x float> %356, %19 ; <<4 x float>>:357 [#uses=1]
+ fmul <4 x float> %357, %20 ; <<4 x float>>:358 [#uses=1]
+ fmul <4 x float> %358, %21 ; <<4 x float>>:359 [#uses=1]
+ fmul <4 x float> %359, %22 ; <<4 x float>>:360 [#uses=1]
+ fmul <4 x float> %360, %23 ; <<4 x float>>:361 [#uses=1]
+ fmul <4 x float> %361, %24 ; <<4 x float>>:362 [#uses=1]
+ fmul <4 x float> %362, %25 ; <<4 x float>>:363 [#uses=1]
+ fmul <4 x float> %363, %26 ; <<4 x float>>:364 [#uses=1]
+ fmul <4 x float> %364, %27 ; <<4 x float>>:365 [#uses=1]
+ fmul <4 x float> %365, %28 ; <<4 x float>>:366 [#uses=1]
+ fmul <4 x float> %366, %29 ; <<4 x float>>:367 [#uses=1]
+ fmul <4 x float> %367, %30 ; <<4 x float>>:368 [#uses=1]
+ fmul <4 x float> %368, %31 ; <<4 x float>>:369 [#uses=1]
+ fmul <4 x float> %369, %32 ; <<4 x float>>:370 [#uses=1]
+ fmul <4 x float> %14, %14 ; <<4 x float>>:371 [#uses=1]
+ fmul <4 x float> %371, %15 ; <<4 x float>>:372 [#uses=1]
+ fmul <4 x float> %372, %16 ; <<4 x float>>:373 [#uses=1]
+ fmul <4 x float> %373, %17 ; <<4 x float>>:374 [#uses=1]
+ fmul <4 x float> %374, %18 ; <<4 x float>>:375 [#uses=1]
+ fmul <4 x float> %375, %19 ; <<4 x float>>:376 [#uses=1]
+ fmul <4 x float> %376, %20 ; <<4 x float>>:377 [#uses=1]
+ fmul <4 x float> %377, %21 ; <<4 x float>>:378 [#uses=1]
+ fmul <4 x float> %378, %22 ; <<4 x float>>:379 [#uses=1]
+ fmul <4 x float> %379, %23 ; <<4 x float>>:380 [#uses=1]
+ fmul <4 x float> %380, %24 ; <<4 x float>>:381 [#uses=1]
+ fmul <4 x float> %381, %25 ; <<4 x float>>:382 [#uses=1]
+ fmul <4 x float> %382, %26 ; <<4 x float>>:383 [#uses=1]
+ fmul <4 x float> %383, %27 ; <<4 x float>>:384 [#uses=1]
+ fmul <4 x float> %384, %28 ; <<4 x float>>:385 [#uses=1]
+ fmul <4 x float> %385, %29 ; <<4 x float>>:386 [#uses=1]
+ fmul <4 x float> %386, %30 ; <<4 x float>>:387 [#uses=1]
+ fmul <4 x float> %387, %31 ; <<4 x float>>:388 [#uses=1]
+ fmul <4 x float> %388, %32 ; <<4 x float>>:389 [#uses=1]
+ fmul <4 x float> %15, %15 ; <<4 x float>>:390 [#uses=1]
+ fmul <4 x float> %390, %16 ; <<4 x float>>:391 [#uses=1]
+ fmul <4 x float> %391, %17 ; <<4 x float>>:392 [#uses=1]
+ fmul <4 x float> %392, %18 ; <<4 x float>>:393 [#uses=1]
+ fmul <4 x float> %393, %19 ; <<4 x float>>:394 [#uses=1]
+ fmul <4 x float> %394, %20 ; <<4 x float>>:395 [#uses=1]
+ fmul <4 x float> %395, %21 ; <<4 x float>>:396 [#uses=1]
+ fmul <4 x float> %396, %22 ; <<4 x float>>:397 [#uses=1]
+ fmul <4 x float> %397, %23 ; <<4 x float>>:398 [#uses=1]
+ fmul <4 x float> %398, %24 ; <<4 x float>>:399 [#uses=1]
+ fmul <4 x float> %399, %25 ; <<4 x float>>:400 [#uses=1]
+ fmul <4 x float> %400, %26 ; <<4 x float>>:401 [#uses=1]
+ fmul <4 x float> %401, %27 ; <<4 x float>>:402 [#uses=1]
+ fmul <4 x float> %402, %28 ; <<4 x float>>:403 [#uses=1]
+ fmul <4 x float> %403, %29 ; <<4 x float>>:404 [#uses=1]
+ fmul <4 x float> %404, %30 ; <<4 x float>>:405 [#uses=1]
+ fmul <4 x float> %405, %31 ; <<4 x float>>:406 [#uses=1]
+ fmul <4 x float> %406, %32 ; <<4 x float>>:407 [#uses=1]
+ fmul <4 x float> %16, %16 ; <<4 x float>>:408 [#uses=1]
+ fmul <4 x float> %408, %17 ; <<4 x float>>:409 [#uses=1]
+ fmul <4 x float> %409, %18 ; <<4 x float>>:410 [#uses=1]
+ fmul <4 x float> %410, %19 ; <<4 x float>>:411 [#uses=1]
+ fmul <4 x float> %411, %20 ; <<4 x float>>:412 [#uses=1]
+ fmul <4 x float> %412, %21 ; <<4 x float>>:413 [#uses=1]
+ fmul <4 x float> %413, %22 ; <<4 x float>>:414 [#uses=1]
+ fmul <4 x float> %414, %23 ; <<4 x float>>:415 [#uses=1]
+ fmul <4 x float> %415, %24 ; <<4 x float>>:416 [#uses=1]
+ fmul <4 x float> %416, %25 ; <<4 x float>>:417 [#uses=1]
+ fmul <4 x float> %417, %26 ; <<4 x float>>:418 [#uses=1]
+ fmul <4 x float> %418, %27 ; <<4 x float>>:419 [#uses=1]
+ fmul <4 x float> %419, %28 ; <<4 x float>>:420 [#uses=1]
+ fmul <4 x float> %420, %29 ; <<4 x float>>:421 [#uses=1]
+ fmul <4 x float> %421, %30 ; <<4 x float>>:422 [#uses=1]
+ fmul <4 x float> %422, %31 ; <<4 x float>>:423 [#uses=1]
+ fmul <4 x float> %423, %32 ; <<4 x float>>:424 [#uses=1]
+ fmul <4 x float> %17, %17 ; <<4 x float>>:425 [#uses=1]
+ fmul <4 x float> %425, %18 ; <<4 x float>>:426 [#uses=1]
+ fmul <4 x float> %426, %19 ; <<4 x float>>:427 [#uses=1]
+ fmul <4 x float> %427, %20 ; <<4 x float>>:428 [#uses=1]
+ fmul <4 x float> %428, %21 ; <<4 x float>>:429 [#uses=1]
+ fmul <4 x float> %429, %22 ; <<4 x float>>:430 [#uses=1]
+ fmul <4 x float> %430, %23 ; <<4 x float>>:431 [#uses=1]
+ fmul <4 x float> %431, %24 ; <<4 x float>>:432 [#uses=1]
+ fmul <4 x float> %432, %25 ; <<4 x float>>:433 [#uses=1]
+ fmul <4 x float> %433, %26 ; <<4 x float>>:434 [#uses=1]
+ fmul <4 x float> %434, %27 ; <<4 x float>>:435 [#uses=1]
+ fmul <4 x float> %435, %28 ; <<4 x float>>:436 [#uses=1]
+ fmul <4 x float> %436, %29 ; <<4 x float>>:437 [#uses=1]
+ fmul <4 x float> %437, %30 ; <<4 x float>>:438 [#uses=1]
+ fmul <4 x float> %438, %31 ; <<4 x float>>:439 [#uses=1]
+ fmul <4 x float> %439, %32 ; <<4 x float>>:440 [#uses=1]
+ fmul <4 x float> %18, %18 ; <<4 x float>>:441 [#uses=1]
+ fmul <4 x float> %441, %19 ; <<4 x float>>:442 [#uses=1]
+ fmul <4 x float> %442, %20 ; <<4 x float>>:443 [#uses=1]
+ fmul <4 x float> %443, %21 ; <<4 x float>>:444 [#uses=1]
+ fmul <4 x float> %444, %22 ; <<4 x float>>:445 [#uses=1]
+ fmul <4 x float> %445, %23 ; <<4 x float>>:446 [#uses=1]
+ fmul <4 x float> %446, %24 ; <<4 x float>>:447 [#uses=1]
+ fmul <4 x float> %447, %25 ; <<4 x float>>:448 [#uses=1]
+ fmul <4 x float> %448, %26 ; <<4 x float>>:449 [#uses=1]
+ fmul <4 x float> %449, %27 ; <<4 x float>>:450 [#uses=1]
+ fmul <4 x float> %450, %28 ; <<4 x float>>:451 [#uses=1]
+ fmul <4 x float> %451, %29 ; <<4 x float>>:452 [#uses=1]
+ fmul <4 x float> %452, %30 ; <<4 x float>>:453 [#uses=1]
+ fmul <4 x float> %453, %31 ; <<4 x float>>:454 [#uses=1]
+ fmul <4 x float> %454, %32 ; <<4 x float>>:455 [#uses=1]
+ fmul <4 x float> %19, %19 ; <<4 x float>>:456 [#uses=1]
+ fmul <4 x float> %456, %20 ; <<4 x float>>:457 [#uses=1]
+ fmul <4 x float> %457, %21 ; <<4 x float>>:458 [#uses=1]
+ fmul <4 x float> %458, %22 ; <<4 x float>>:459 [#uses=1]
+ fmul <4 x float> %459, %23 ; <<4 x float>>:460 [#uses=1]
+ fmul <4 x float> %460, %24 ; <<4 x float>>:461 [#uses=1]
+ fmul <4 x float> %461, %25 ; <<4 x float>>:462 [#uses=1]
+ fmul <4 x float> %462, %26 ; <<4 x float>>:463 [#uses=1]
+ fmul <4 x float> %463, %27 ; <<4 x float>>:464 [#uses=1]
+ fmul <4 x float> %464, %28 ; <<4 x float>>:465 [#uses=1]
+ fmul <4 x float> %465, %29 ; <<4 x float>>:466 [#uses=1]
+ fmul <4 x float> %466, %30 ; <<4 x float>>:467 [#uses=1]
+ fmul <4 x float> %467, %31 ; <<4 x float>>:468 [#uses=1]
+ fmul <4 x float> %468, %32 ; <<4 x float>>:469 [#uses=1]
+ fmul <4 x float> %20, %20 ; <<4 x float>>:470 [#uses=1]
+ fmul <4 x float> %470, %21 ; <<4 x float>>:471 [#uses=1]
+ fmul <4 x float> %471, %22 ; <<4 x float>>:472 [#uses=1]
+ fmul <4 x float> %472, %23 ; <<4 x float>>:473 [#uses=1]
+ fmul <4 x float> %473, %24 ; <<4 x float>>:474 [#uses=1]
+ fmul <4 x float> %474, %25 ; <<4 x float>>:475 [#uses=1]
+ fmul <4 x float> %475, %26 ; <<4 x float>>:476 [#uses=1]
+ fmul <4 x float> %476, %27 ; <<4 x float>>:477 [#uses=1]
+ fmul <4 x float> %477, %28 ; <<4 x float>>:478 [#uses=1]
+ fmul <4 x float> %478, %29 ; <<4 x float>>:479 [#uses=1]
+ fmul <4 x float> %479, %30 ; <<4 x float>>:480 [#uses=1]
+ fmul <4 x float> %480, %31 ; <<4 x float>>:481 [#uses=1]
+ fmul <4 x float> %481, %32 ; <<4 x float>>:482 [#uses=1]
+ fmul <4 x float> %21, %21 ; <<4 x float>>:483 [#uses=1]
+ fmul <4 x float> %483, %22 ; <<4 x float>>:484 [#uses=1]
+ fmul <4 x float> %484, %23 ; <<4 x float>>:485 [#uses=1]
+ fmul <4 x float> %485, %24 ; <<4 x float>>:486 [#uses=1]
+ fmul <4 x float> %486, %25 ; <<4 x float>>:487 [#uses=1]
+ fmul <4 x float> %487, %26 ; <<4 x float>>:488 [#uses=1]
+ fmul <4 x float> %488, %27 ; <<4 x float>>:489 [#uses=1]
+ fmul <4 x float> %489, %28 ; <<4 x float>>:490 [#uses=1]
+ fmul <4 x float> %490, %29 ; <<4 x float>>:491 [#uses=1]
+ fmul <4 x float> %491, %30 ; <<4 x float>>:492 [#uses=1]
+ fmul <4 x float> %492, %31 ; <<4 x float>>:493 [#uses=1]
+ fmul <4 x float> %493, %32 ; <<4 x float>>:494 [#uses=1]
+ fmul <4 x float> %22, %22 ; <<4 x float>>:495 [#uses=1]
+ fmul <4 x float> %495, %23 ; <<4 x float>>:496 [#uses=1]
+ fmul <4 x float> %496, %24 ; <<4 x float>>:497 [#uses=1]
+ fmul <4 x float> %497, %25 ; <<4 x float>>:498 [#uses=1]
+ fmul <4 x float> %498, %26 ; <<4 x float>>:499 [#uses=1]
+ fmul <4 x float> %499, %27 ; <<4 x float>>:500 [#uses=1]
+ fmul <4 x float> %500, %28 ; <<4 x float>>:501 [#uses=1]
+ fmul <4 x float> %501, %29 ; <<4 x float>>:502 [#uses=1]
+ fmul <4 x float> %502, %30 ; <<4 x float>>:503 [#uses=1]
+ fmul <4 x float> %503, %31 ; <<4 x float>>:504 [#uses=1]
+ fmul <4 x float> %504, %32 ; <<4 x float>>:505 [#uses=1]
+ fmul <4 x float> %23, %23 ; <<4 x float>>:506 [#uses=1]
+ fmul <4 x float> %506, %24 ; <<4 x float>>:507 [#uses=1]
+ fmul <4 x float> %507, %25 ; <<4 x float>>:508 [#uses=1]
+ fmul <4 x float> %508, %26 ; <<4 x float>>:509 [#uses=1]
+ fmul <4 x float> %509, %27 ; <<4 x float>>:510 [#uses=1]
+ fmul <4 x float> %510, %28 ; <<4 x float>>:511 [#uses=1]
+ fmul <4 x float> %511, %29 ; <<4 x float>>:512 [#uses=1]
+ fmul <4 x float> %512, %30 ; <<4 x float>>:513 [#uses=1]
+ fmul <4 x float> %513, %31 ; <<4 x float>>:514 [#uses=1]
+ fmul <4 x float> %514, %32 ; <<4 x float>>:515 [#uses=1]
+ fmul <4 x float> %24, %24 ; <<4 x float>>:516 [#uses=1]
+ fmul <4 x float> %516, %25 ; <<4 x float>>:517 [#uses=1]
+ fmul <4 x float> %517, %26 ; <<4 x float>>:518 [#uses=1]
+ fmul <4 x float> %518, %27 ; <<4 x float>>:519 [#uses=1]
+ fmul <4 x float> %519, %28 ; <<4 x float>>:520 [#uses=1]
+ fmul <4 x float> %520, %29 ; <<4 x float>>:521 [#uses=1]
+ fmul <4 x float> %521, %30 ; <<4 x float>>:522 [#uses=1]
+ fmul <4 x float> %522, %31 ; <<4 x float>>:523 [#uses=1]
+ fmul <4 x float> %523, %32 ; <<4 x float>>:524 [#uses=1]
+ fmul <4 x float> %25, %25 ; <<4 x float>>:525 [#uses=1]
+ fmul <4 x float> %525, %26 ; <<4 x float>>:526 [#uses=1]
+ fmul <4 x float> %526, %27 ; <<4 x float>>:527 [#uses=1]
+ fmul <4 x float> %527, %28 ; <<4 x float>>:528 [#uses=1]
+ fmul <4 x float> %528, %29 ; <<4 x float>>:529 [#uses=1]
+ fmul <4 x float> %529, %30 ; <<4 x float>>:530 [#uses=1]
+ fmul <4 x float> %530, %31 ; <<4 x float>>:531 [#uses=1]
+ fmul <4 x float> %531, %32 ; <<4 x float>>:532 [#uses=1]
+ fmul <4 x float> %26, %26 ; <<4 x float>>:533 [#uses=1]
+ fmul <4 x float> %533, %27 ; <<4 x float>>:534 [#uses=1]
+ fmul <4 x float> %534, %28 ; <<4 x float>>:535 [#uses=1]
+ fmul <4 x float> %535, %29 ; <<4 x float>>:536 [#uses=1]
+ fmul <4 x float> %536, %30 ; <<4 x float>>:537 [#uses=1]
+ fmul <4 x float> %537, %31 ; <<4 x float>>:538 [#uses=1]
+ fmul <4 x float> %538, %32 ; <<4 x float>>:539 [#uses=1]
+ fmul <4 x float> %27, %27 ; <<4 x float>>:540 [#uses=1]
+ fmul <4 x float> %540, %28 ; <<4 x float>>:541 [#uses=1]
+ fmul <4 x float> %541, %29 ; <<4 x float>>:542 [#uses=1]
+ fmul <4 x float> %542, %30 ; <<4 x float>>:543 [#uses=1]
+ fmul <4 x float> %543, %31 ; <<4 x float>>:544 [#uses=1]
+ fmul <4 x float> %544, %32 ; <<4 x float>>:545 [#uses=1]
+ fmul <4 x float> %28, %28 ; <<4 x float>>:546 [#uses=1]
+ fmul <4 x float> %546, %29 ; <<4 x float>>:547 [#uses=1]
+ fmul <4 x float> %547, %30 ; <<4 x float>>:548 [#uses=1]
+ fmul <4 x float> %548, %31 ; <<4 x float>>:549 [#uses=1]
+ fmul <4 x float> %549, %32 ; <<4 x float>>:550 [#uses=1]
+ fmul <4 x float> %29, %29 ; <<4 x float>>:551 [#uses=1]
+ fmul <4 x float> %551, %30 ; <<4 x float>>:552 [#uses=1]
+ fmul <4 x float> %552, %31 ; <<4 x float>>:553 [#uses=1]
+ fmul <4 x float> %553, %32 ; <<4 x float>>:554 [#uses=1]
+ fmul <4 x float> %30, %30 ; <<4 x float>>:555 [#uses=1]
+ fmul <4 x float> %555, %31 ; <<4 x float>>:556 [#uses=1]
+ fmul <4 x float> %556, %32 ; <<4 x float>>:557 [#uses=1]
+ fmul <4 x float> %31, %31 ; <<4 x float>>:558 [#uses=1]
+ fmul <4 x float> %558, %32 ; <<4 x float>>:559 [#uses=1]
+ fmul <4 x float> %32, %32 ; <<4 x float>>:560 [#uses=1]
+ fadd <4 x float> %64, %64 ; <<4 x float>>:561 [#uses=1]
+ fadd <4 x float> %561, %64 ; <<4 x float>>:562 [#uses=1]
+ fadd <4 x float> %562, %95 ; <<4 x float>>:563 [#uses=1]
+ fadd <4 x float> %563, %125 ; <<4 x float>>:564 [#uses=1]
+ fadd <4 x float> %564, %154 ; <<4 x float>>:565 [#uses=1]
+ fadd <4 x float> %565, %182 ; <<4 x float>>:566 [#uses=1]
+ fadd <4 x float> %566, %209 ; <<4 x float>>:567 [#uses=1]
+ fadd <4 x float> %567, %235 ; <<4 x float>>:568 [#uses=1]
+ fadd <4 x float> %568, %260 ; <<4 x float>>:569 [#uses=1]
+ fadd <4 x float> %569, %284 ; <<4 x float>>:570 [#uses=1]
+ fadd <4 x float> %570, %307 ; <<4 x float>>:571 [#uses=1]
+ fadd <4 x float> %571, %329 ; <<4 x float>>:572 [#uses=1]
+ fadd <4 x float> %572, %350 ; <<4 x float>>:573 [#uses=1]
+ fadd <4 x float> %573, %370 ; <<4 x float>>:574 [#uses=1]
+ fadd <4 x float> %574, %389 ; <<4 x float>>:575 [#uses=1]
+ fadd <4 x float> %575, %407 ; <<4 x float>>:576 [#uses=1]
+ fadd <4 x float> %576, %424 ; <<4 x float>>:577 [#uses=1]
+ fadd <4 x float> %577, %440 ; <<4 x float>>:578 [#uses=1]
+ fadd <4 x float> %578, %455 ; <<4 x float>>:579 [#uses=1]
+ fadd <4 x float> %579, %469 ; <<4 x float>>:580 [#uses=1]
+ fadd <4 x float> %580, %482 ; <<4 x float>>:581 [#uses=1]
+ fadd <4 x float> %581, %494 ; <<4 x float>>:582 [#uses=1]
+ fadd <4 x float> %582, %505 ; <<4 x float>>:583 [#uses=1]
+ fadd <4 x float> %583, %515 ; <<4 x float>>:584 [#uses=1]
+ fadd <4 x float> %584, %524 ; <<4 x float>>:585 [#uses=1]
+ fadd <4 x float> %585, %532 ; <<4 x float>>:586 [#uses=1]
+ fadd <4 x float> %586, %539 ; <<4 x float>>:587 [#uses=1]
+ fadd <4 x float> %587, %545 ; <<4 x float>>:588 [#uses=1]
+ fadd <4 x float> %588, %550 ; <<4 x float>>:589 [#uses=1]
+ fadd <4 x float> %589, %554 ; <<4 x float>>:590 [#uses=1]
+ fadd <4 x float> %590, %557 ; <<4 x float>>:591 [#uses=1]
+ fadd <4 x float> %591, %559 ; <<4 x float>>:592 [#uses=1]
+ fadd <4 x float> %592, %560 ; <<4 x float>>:593 [#uses=1]
+ store <4 x float> %593, <4 x float>* @0, align 1
+ ret void
+}
diff --git a/test/CodeGen/X86/2008-07-22-CombinerCrash.ll b/test/CodeGen/X86/2008-07-22-CombinerCrash.ll
new file mode 100644
index 0000000..0f67145
--- /dev/null
+++ b/test/CodeGen/X86/2008-07-22-CombinerCrash.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+; PR2566
+
+external global i16 ; <i16*>:0 [#uses=1]
+external global <4 x i16> ; <<4 x i16>*>:1 [#uses=1]
+
+declare void @abort()
+
+define void @t() nounwind {
+ load i16* @0 ; <i16>:1 [#uses=1]
+ zext i16 %1 to i64 ; <i64>:2 [#uses=1]
+ bitcast i64 %2 to <4 x i16> ; <<4 x i16>>:3 [#uses=1]
+ shufflevector <4 x i16> %3, <4 x i16> undef, <4 x i32> zeroinitializer ; <<4 x i16>>:4 [#uses=1]
+ store <4 x i16> %4, <4 x i16>* @1
+ ret void
+}
diff --git a/test/CodeGen/X86/2008-07-23-VSetCC.ll b/test/CodeGen/X86/2008-07-23-VSetCC.ll
new file mode 100644
index 0000000..684ca5c
--- /dev/null
+++ b/test/CodeGen/X86/2008-07-23-VSetCC.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=x86 -mcpu=pentium
+; PR2575
+
+define void @entry(i32 %m_task_id, i32 %start_x, i32 %end_x) nounwind {
+ br i1 false, label %bb.nph, label %._crit_edge
+
+bb.nph: ; preds = %bb.nph, %0
+ %X = icmp sgt <4 x i32> zeroinitializer, < i32 -128, i32 -128, i32 -128, i32 -128 > ; <<4 x i32>>:1 [#uses=1]
+ sext <4 x i1> %X to <4 x i32>
+ extractelement <4 x i32> %1, i32 3 ; <i32>:2 [#uses=1]
+ lshr i32 %2, 31 ; <i32>:3 [#uses=1]
+ trunc i32 %3 to i1 ; <i1>:4 [#uses=1]
+ select i1 %4, i32 -1, i32 0 ; <i32>:5 [#uses=1]
+ insertelement <4 x i32> zeroinitializer, i32 %5, i32 3 ; <<4 x i32>>:6 [#uses=1]
+ and <4 x i32> zeroinitializer, %6 ; <<4 x i32>>:7 [#uses=1]
+ bitcast <4 x i32> %7 to <4 x float> ; <<4 x float>>:8 [#uses=1]
+ fmul <4 x float> zeroinitializer, %8 ; <<4 x float>>:9 [#uses=1]
+ bitcast <4 x float> %9 to <4 x i32> ; <<4 x i32>>:10 [#uses=1]
+ or <4 x i32> %10, zeroinitializer ; <<4 x i32>>:11 [#uses=1]
+ bitcast <4 x i32> %11 to <4 x float> ; <<4 x float>>:12 [#uses=1]
+ fmul <4 x float> %12, < float 1.000000e+02, float 1.000000e+02, float 1.000000e+02, float 1.000000e+02 > ; <<4 x float>>:13 [#uses=1]
+ fsub <4 x float> %13, < float 1.000000e+02, float 1.000000e+02, float 1.000000e+02, float 1.000000e+02 > ; <<4 x float>>:14 [#uses=1]
+ extractelement <4 x float> %14, i32 3 ; <float>:15 [#uses=1]
+ call float @fmaxf( float 0.000000e+00, float %15 ) ; <float>:16 [#uses=0]
+ br label %bb.nph
+
+._crit_edge: ; preds = %0
+ ret void
+}
+
+
+declare float @fmaxf(float, float)
diff --git a/test/CodeGen/X86/2008-08-05-SpillerBug.ll b/test/CodeGen/X86/2008-08-05-SpillerBug.ll
new file mode 100644
index 0000000..67e14ff
--- /dev/null
+++ b/test/CodeGen/X86/2008-08-05-SpillerBug.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 58
+; PR2568
+
+@g_3 = external global i16 ; <i16*> [#uses=1]
+@g_5 = external global i32 ; <i32*> [#uses=3]
+
+declare i32 @func_15(i16 signext , i16 signext , i32) nounwind
+
+define void @func_9_entry_2E_ce(i8 %p_11) nounwind {
+newFuncRoot:
+ br label %entry.ce
+
+entry.ce.ret.exitStub: ; preds = %entry.ce
+ ret void
+
+entry.ce: ; preds = %newFuncRoot
+ load i16* @g_3, align 2 ; <i16>:0 [#uses=1]
+ icmp sgt i16 %0, 0 ; <i1>:1 [#uses=1]
+ zext i1 %1 to i32 ; <i32>:2 [#uses=1]
+ load i32* @g_5, align 4 ; <i32>:3 [#uses=4]
+ icmp ugt i32 %2, %3 ; <i1>:4 [#uses=1]
+ zext i1 %4 to i32 ; <i32>:5 [#uses=1]
+ icmp eq i32 %3, 0 ; <i1>:6 [#uses=1]
+ %.0 = select i1 %6, i32 1, i32 %3 ; <i32> [#uses=1]
+ urem i32 1, %.0 ; <i32>:7 [#uses=2]
+ sext i8 %p_11 to i16 ; <i16>:8 [#uses=1]
+ trunc i32 %3 to i16 ; <i16>:9 [#uses=1]
+ tail call i32 @func_15( i16 signext %8, i16 signext %9, i32 1 ) nounwind ; <i32>:10 [#uses=0]
+ load i32* @g_5, align 4 ; <i32>:11 [#uses=1]
+ trunc i32 %11 to i16 ; <i16>:12 [#uses=1]
+ tail call i32 @func_15( i16 signext %12, i16 signext 1, i32 %7 ) nounwind ; <i32>:13 [#uses=0]
+ sext i8 %p_11 to i32 ; <i32>:14 [#uses=1]
+ %p_11.lobit = lshr i8 %p_11, 7 ; <i8> [#uses=1]
+ %tmp = zext i8 %p_11.lobit to i32 ; <i32> [#uses=1]
+ %tmp.not = xor i32 %tmp, 1 ; <i32> [#uses=1]
+ %.015 = ashr i32 %14, %tmp.not ; <i32> [#uses=2]
+ icmp eq i32 %.015, 0 ; <i1>:15 [#uses=1]
+ %.016 = select i1 %15, i32 1, i32 %.015 ; <i32> [#uses=1]
+ udiv i32 %7, %.016 ; <i32>:16 [#uses=1]
+ icmp ult i32 %5, %16 ; <i1>:17 [#uses=1]
+ zext i1 %17 to i32 ; <i32>:18 [#uses=1]
+ store i32 %18, i32* @g_5, align 4
+ br label %entry.ce.ret.exitStub
+}
diff --git a/test/CodeGen/X86/2008-08-06-RewriterBug.ll b/test/CodeGen/X86/2008-08-06-RewriterBug.ll
new file mode 100644
index 0000000..4428035
--- /dev/null
+++ b/test/CodeGen/X86/2008-08-06-RewriterBug.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -march=x86
+; PR2596
+
+@data = external global [400 x i64] ; <[400 x i64]*> [#uses=5]
+
+define void @foo(double* noalias, double* noalias) {
+ load i64* getelementptr ([400 x i64]* @data, i32 0, i64 200), align 4 ; <i64>:3 [#uses=1]
+ load i64* getelementptr ([400 x i64]* @data, i32 0, i64 199), align 4 ; <i64>:4 [#uses=1]
+ load i64* getelementptr ([400 x i64]* @data, i32 0, i64 198), align 4 ; <i64>:5 [#uses=2]
+ load i64* getelementptr ([400 x i64]* @data, i32 0, i64 197), align 4 ; <i64>:6 [#uses=1]
+ br i1 false, label %28, label %7
+
+; <label>:7 ; preds = %2
+ load double** getelementptr (double** bitcast ([400 x i64]* @data to double**), i64 180), align 8 ; <double*>:8 [#uses=1]
+ bitcast double* %8 to double* ; <double*>:9 [#uses=1]
+ ptrtoint double* %9 to i64 ; <i64>:10 [#uses=1]
+ mul i64 %4, %3 ; <i64>:11 [#uses=1]
+ add i64 0, %11 ; <i64>:12 [#uses=1]
+ shl i64 %12, 3 ; <i64>:13 [#uses=1]
+ sub i64 %10, %13 ; <i64>:14 [#uses=1]
+ add i64 %5, 0 ; <i64>:15 [#uses=1]
+ shl i64 %15, 3 ; <i64>:16 [#uses=1]
+ bitcast i64 %16 to i64 ; <i64>:17 [#uses=1]
+ mul i64 %6, %5 ; <i64>:18 [#uses=1]
+ add i64 0, %18 ; <i64>:19 [#uses=1]
+ shl i64 %19, 3 ; <i64>:20 [#uses=1]
+ sub i64 %17, %20 ; <i64>:21 [#uses=1]
+ add i64 0, %21 ; <i64>:22 [#uses=1]
+ add i64 0, %14 ; <i64>:23 [#uses=1]
+ br label %24
+
+; <label>:24 ; preds = %24, %7
+ phi i64 [ 0, %24 ], [ %22, %7 ] ; <i64>:25 [#uses=1]
+ phi i64 [ 0, %24 ], [ %23, %7 ] ; <i64>:26 [#uses=0]
+ add i64 %25, 24 ; <i64>:27 [#uses=0]
+ br label %24
+
+; <label>:28 ; preds = %2
+ unreachable
+}
diff --git a/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll b/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll
new file mode 100644
index 0000000..32f6ca0
--- /dev/null
+++ b/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movzbl
+
+define i32 @foo(<4 x float> %a, <4 x float> %b) nounwind {
+entry:
+ tail call i32 @llvm.x86.sse.ucomige.ss( <4 x float> %a, <4 x float> %b ) nounwind readnone
+ ret i32 %0
+}
+
+declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone
diff --git a/test/CodeGen/X86/2008-08-19-SubAndFetch.ll b/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
new file mode 100644
index 0000000..8475e8d
--- /dev/null
+++ b/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+@var = external global i64 ; <i64*> [#uses=1]
+
+define i32 @main() nounwind {
+entry:
+; CHECK: main:
+; CHECK: lock
+; CHECK: decq
+ tail call i64 @llvm.atomic.load.sub.i64.p0i64( i64* @var, i64 1 ) ; <i64>:0 [#uses=0]
+ unreachable
+}
+
+declare i64 @llvm.atomic.load.sub.i64.p0i64(i64*, i64) nounwind
diff --git a/test/CodeGen/X86/2008-08-23-64Bit-maskmovq.ll b/test/CodeGen/X86/2008-08-23-64Bit-maskmovq.ll
new file mode 100644
index 0000000..c76dd7d
--- /dev/null
+++ b/test/CodeGen/X86/2008-08-23-64Bit-maskmovq.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=x86-64
+
+ %struct.DrawHelper = type { void (i32, %struct.QT_FT_Span*, i8*)*, void (i32, %struct.QT_FT_Span*, i8*)*, void (%struct.QRasterBuffer*, i32, i32, i32, i8*, i32, i32, i32)*, void (%struct.QRasterBuffer*, i32, i32, i32, i8*, i32, i32, i32)*, void (%struct.QRasterBuffer*, i32, i32, i32, i32, i32)* }
+ %struct.QBasicAtomic = type { i32 }
+ %struct.QClipData = type { i32, %"struct.QClipData::ClipLine"*, i32, i32, %struct.QT_FT_Span*, i32, i32, i32, i32 }
+ %"struct.QClipData::ClipLine" = type { i32, %struct.QT_FT_Span* }
+ %struct.QRasterBuffer = type { %struct.QRect, %struct.QRect, %struct.QRegion, %struct.QRegion, %struct.QClipData*, %struct.QClipData*, i8, i8, i32, i32, i32, i32, %struct.DrawHelper*, i32, i32, i32, i8* }
+ %struct.QRect = type { i32, i32, i32, i32 }
+ %struct.QRegion = type { %"struct.QRegion::QRegionData"* }
+ %"struct.QRegion::QRegionData" = type { %struct.QBasicAtomic, %struct._XRegion*, i8*, %struct.QRegionPrivate* }
+ %struct.QRegionPrivate = type opaque
+ %struct.QT_FT_Span = type { i16, i16, i16, i8 }
+ %struct._XRegion = type opaque
+
+define hidden void @_Z24qt_bitmapblit16_sse3dnowP13QRasterBufferiijPKhiii(%struct.QRasterBuffer* %rasterBuffer, i32 %x, i32 %y, i32 %color, i8* %src, i32 %width, i32 %height, i32 %stride) nounwind {
+entry:
+ br i1 false, label %bb.nph144.split, label %bb133
+
+bb.nph144.split: ; preds = %entry
+ tail call void @llvm.x86.mmx.maskmovq( <8 x i8> zeroinitializer, <8 x i8> zeroinitializer, i8* null ) nounwind
+ unreachable
+
+bb133: ; preds = %entry
+ ret void
+}
+
+declare void @llvm.x86.mmx.maskmovq(<8 x i8>, <8 x i8>, i8*) nounwind
diff --git a/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll b/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
new file mode 100644
index 0000000..eacb4a5
--- /dev/null
+++ b/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll
@@ -0,0 +1,59 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movd | count 1
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movq
+; PR2677
+
+
+ %struct.Bigint = type { %struct.Bigint*, i32, i32, i32, i32, [1 x i32] }
+
+define double @_Z7qstrtodPKcPS0_Pb(i8* %s00, i8** %se, i8* %ok) nounwind {
+entry:
+ br i1 false, label %bb151, label %bb163
+
+bb151: ; preds = %entry
+ br label %bb163
+
+bb163: ; preds = %bb151, %entry
+ %tmp366 = load double* null, align 8 ; <double> [#uses=1]
+ %tmp368 = fmul double %tmp366, 0.000000e+00 ; <double> [#uses=1]
+ %tmp368226 = bitcast double %tmp368 to i64 ; <i64> [#uses=1]
+ br label %bb5.i
+
+bb5.i: ; preds = %bb5.i57.i, %bb163
+ %b.0.i = phi %struct.Bigint* [ null, %bb163 ], [ %tmp9.i.i41.i, %bb5.i57.i ] ; <%struct.Bigint*> [#uses=1]
+ %tmp3.i7.i728 = load i32* null, align 4 ; <i32> [#uses=1]
+ br label %bb.i27.i
+
+bb.i27.i: ; preds = %bb.i27.i, %bb5.i
+ %tmp23.i20.i = lshr i32 0, 16 ; <i32> [#uses=1]
+ br i1 false, label %bb.i27.i, label %bb5.i57.i
+
+bb5.i57.i: ; preds = %bb.i27.i
+ %tmp50.i35.i = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp51.i36.i = add i32 %tmp50.i35.i, 1 ; <i32> [#uses=2]
+ %tmp2.i.i37.i = shl i32 1, %tmp51.i36.i ; <i32> [#uses=2]
+ %tmp4.i.i38.i = shl i32 %tmp2.i.i37.i, 2 ; <i32> [#uses=1]
+ %tmp7.i.i39.i = add i32 %tmp4.i.i38.i, 28 ; <i32> [#uses=1]
+ %tmp8.i.i40.i = malloc i8, i32 %tmp7.i.i39.i ; <i8*> [#uses=1]
+ %tmp9.i.i41.i = bitcast i8* %tmp8.i.i40.i to %struct.Bigint* ; <%struct.Bigint*> [#uses=2]
+ store i32 %tmp51.i36.i, i32* null, align 8
+ store i32 %tmp2.i.i37.i, i32* null, align 4
+ free %struct.Bigint* %b.0.i
+ store i32 %tmp23.i20.i, i32* null, align 4
+ %tmp74.i61.i = add i32 %tmp3.i7.i728, 1 ; <i32> [#uses=1]
+ store i32 %tmp74.i61.i, i32* null, align 4
+ br i1 false, label %bb5.i, label %bb7.i
+
+bb7.i: ; preds = %bb5.i57.i
+ %tmp514 = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp515 = sext i32 %tmp514 to i64 ; <i64> [#uses=1]
+ %tmp516 = shl i64 %tmp515, 2 ; <i64> [#uses=1]
+ %tmp517 = add i64 %tmp516, 8 ; <i64> [#uses=1]
+ %tmp519 = getelementptr %struct.Bigint* %tmp9.i.i41.i, i32 0, i32 3 ; <i32*> [#uses=1]
+ %tmp523 = bitcast i32* %tmp519 to i8* ; <i8*> [#uses=1]
+ call void @llvm.memcpy.i64( i8* null, i8* %tmp523, i64 %tmp517, i32 1 )
+ %tmp524136 = bitcast i64 %tmp368226 to double ; <double> [#uses=1]
+ store double %tmp524136, double* null
+ unreachable
+}
+
+declare void @llvm.memcpy.i64(i8*, i8*, i64, i32) nounwind
diff --git a/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll b/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
new file mode 100644
index 0000000..101b3c5
--- /dev/null
+++ b/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -mcpu=core2 | grep pxor | count 2
+; RUN: llc < %s -mcpu=core2 | not grep movapd
+; PR2715
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+ %struct.XPTTypeDescriptorPrefix = type { i8 }
+ %struct.nsISupports = type { i32 (...)** }
+ %struct.nsXPTCMiniVariant = type { %"struct.nsXPTCMiniVariant::._39" }
+ %"struct.nsXPTCMiniVariant::._39" = type { i64 }
+ %struct.nsXPTCVariant = type { %struct.nsXPTCMiniVariant, i8*, %struct.nsXPTType, i8 }
+ %struct.nsXPTType = type { %struct.XPTTypeDescriptorPrefix }
+
+define i32 @XPTC_InvokeByIndex(%struct.nsISupports* %that, i32 %methodIndex, i32 %paramCount, %struct.nsXPTCVariant* %params) nounwind {
+entry:
+ call void asm sideeffect "", "{xmm0},{xmm1},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},~{dirflag},~{fpsr},~{flags}"( double undef, double undef, double undef, double 1.0, double undef, double 0.0, double undef, double 0.0 ) nounwind
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll b/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
new file mode 100644
index 0000000..b92c789
--- /dev/null
+++ b/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
@@ -0,0 +1,17 @@
+; Check that eh_return & unwind_init were properly lowered
+; RUN: llc < %s | grep %ebp | count 7
+; RUN: llc < %s | grep %ecx | count 5
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i386-pc-linux"
+
+define i8* @test(i32 %a, i8* %b) {
+entry:
+ call void @llvm.eh.unwind.init()
+ %foo = alloca i32
+ call void @llvm.eh.return.i32(i32 %a, i8* %b)
+ unreachable
+}
+
+declare void @llvm.eh.return.i32(i32, i8*)
+declare void @llvm.eh.unwind.init()
diff --git a/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll b/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll
new file mode 100644
index 0000000..00ab735
--- /dev/null
+++ b/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll
@@ -0,0 +1,17 @@
+; Check that eh_return & unwind_init were properly lowered
+; RUN: llc < %s | grep %rbp | count 5
+; RUN: llc < %s | grep %rcx | count 3
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i8* @test(i64 %a, i8* %b) {
+entry:
+ call void @llvm.eh.unwind.init()
+ %foo = alloca i32
+ call void @llvm.eh.return.i64(i64 %a, i8* %b)
+ unreachable
+}
+
+declare void @llvm.eh.return.i64(i64, i8*)
+declare void @llvm.eh.unwind.init()
diff --git a/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll b/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll
new file mode 100644
index 0000000..60be0d5
--- /dev/null
+++ b/test/CodeGen/X86/2008-09-05-sinttofp-2xi32.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep cvttpd2pi | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep cvtpi2pd | count 1
+; PR2687
+
+define <2 x double> @a(<2 x i32> %x) nounwind {
+entry:
+ %y = sitofp <2 x i32> %x to <2 x double>
+ ret <2 x double> %y
+}
+
+define <2 x i32> @b(<2 x double> %x) nounwind {
+entry:
+ %y = fptosi <2 x double> %x to <2 x i32>
+ ret <2 x i32> %y
+}
diff --git a/test/CodeGen/X86/2008-09-09-LinearScanBug.ll b/test/CodeGen/X86/2008-09-09-LinearScanBug.ll
new file mode 100644
index 0000000..b3312d9
--- /dev/null
+++ b/test/CodeGen/X86/2008-09-09-LinearScanBug.ll
@@ -0,0 +1,65 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin
+; PR2757
+
+@g_3 = external global i32 ; <i32*> [#uses=1]
+
+define i32 @func_125(i32 %p_126, i32 %p_128, i32 %p_129) nounwind {
+entry:
+ %tmp2.i = load i32* @g_3 ; <i32> [#uses=2]
+ %conv = trunc i32 %tmp2.i to i16 ; <i16> [#uses=3]
+ br label %forcond1.preheader.i.i7
+
+forcond1.preheader.i.i7: ; preds = %forinc6.i.i25, %entry
+ %p_86.addr.06.i.i4 = phi i32 [ 0, %entry ], [ %sub.i.i.i23, %forinc6.i.i25 ] ; <i32> [#uses=1]
+ %p_87.addr.15.i.i5 = phi i32 [ 0, %entry ], [ %p_87.addr.0.lcssa.i.i21, %forinc6.i.i25 ] ; <i32> [#uses=2]
+ br i1 false, label %forinc6.i.i25, label %forinc.i.i11
+
+forinc.i.i11: ; preds = %forcond1.backedge.i.i20, %forcond1.preheader.i.i7
+ %p_87.addr.02.i.i8 = phi i32 [ %p_87.addr.15.i.i5, %forcond1.preheader.i.i7 ], [ %p_87.addr.0.be.i.i18, %forcond1.backedge.i.i20 ] ; <i32> [#uses=1]
+ %conv.i.i9 = trunc i32 %p_87.addr.02.i.i8 to i8 ; <i8> [#uses=1]
+ br i1 false, label %land_rhs3.i.i.i14, label %lor_rhs.i.i.i17
+
+land_rhs3.i.i.i14: ; preds = %forinc.i.i11
+ br i1 false, label %forcond1.backedge.i.i20, label %lor_rhs.i.i.i17
+
+lor_rhs.i.i.i17: ; preds = %land_rhs3.i.i.i14, %forinc.i.i11
+ %conv29.i.i.i15 = sext i8 %conv.i.i9 to i32 ; <i32> [#uses=1]
+ %add.i.i.i16 = add i32 %conv29.i.i.i15, 1 ; <i32> [#uses=1]
+ br label %forcond1.backedge.i.i20
+
+forcond1.backedge.i.i20: ; preds = %lor_rhs.i.i.i17, %land_rhs3.i.i.i14
+ %p_87.addr.0.be.i.i18 = phi i32 [ %add.i.i.i16, %lor_rhs.i.i.i17 ], [ 0, %land_rhs3.i.i.i14 ] ; <i32> [#uses=3]
+ %tobool3.i.i19 = icmp eq i32 %p_87.addr.0.be.i.i18, 0 ; <i1> [#uses=1]
+ br i1 %tobool3.i.i19, label %forinc6.i.i25, label %forinc.i.i11
+
+forinc6.i.i25: ; preds = %forcond1.backedge.i.i20, %forcond1.preheader.i.i7
+ %p_87.addr.0.lcssa.i.i21 = phi i32 [ %p_87.addr.15.i.i5, %forcond1.preheader.i.i7 ], [ %p_87.addr.0.be.i.i18, %forcond1.backedge.i.i20 ] ; <i32> [#uses=1]
+ %conv.i.i.i22 = and i32 %p_86.addr.06.i.i4, 255 ; <i32> [#uses=1]
+ %sub.i.i.i23 = add i32 %conv.i.i.i22, -1 ; <i32> [#uses=2]
+ %phitmp.i.i24 = icmp eq i32 %sub.i.i.i23, 0 ; <i1> [#uses=1]
+ br i1 %phitmp.i.i24, label %func_106.exit27, label %forcond1.preheader.i.i7
+
+func_106.exit27: ; preds = %forinc6.i.i25
+ %cmp = icmp ne i32 %tmp2.i, 1 ; <i1> [#uses=3]
+ %cmp.ext = zext i1 %cmp to i32 ; <i32> [#uses=1]
+ br i1 %cmp, label %safe_mod_int16_t_s_s.exit, label %lor_rhs.i
+
+lor_rhs.i: ; preds = %func_106.exit27
+ %tobool.i = xor i1 %cmp, true ; <i1> [#uses=1]
+ %or.cond.i = or i1 false, %tobool.i ; <i1> [#uses=1]
+ br i1 %or.cond.i, label %ifend.i, label %safe_mod_int16_t_s_s.exit
+
+ifend.i: ; preds = %lor_rhs.i
+ %conv6.i = sext i16 %conv to i32 ; <i32> [#uses=1]
+ %rem.i = urem i32 %conv6.i, %cmp.ext ; <i32> [#uses=1]
+ %conv8.i = trunc i32 %rem.i to i16 ; <i16> [#uses=1]
+ br label %safe_mod_int16_t_s_s.exit
+
+safe_mod_int16_t_s_s.exit: ; preds = %ifend.i, %lor_rhs.i, %func_106.exit27
+ %call31 = phi i16 [ %conv8.i, %ifend.i ], [ %conv, %func_106.exit27 ], [ %conv, %lor_rhs.i ] ; <i16> [#uses=1]
+ %conv4 = sext i16 %call31 to i32 ; <i32> [#uses=1]
+ %call5 = tail call i32 (...)* @func_104( i32 %conv4 ) ; <i32> [#uses=0]
+ ret i32 undef
+}
+
+declare i32 @func_104(...)
diff --git a/test/CodeGen/X86/2008-09-11-CoalescerBug.ll b/test/CodeGen/X86/2008-09-11-CoalescerBug.ll
new file mode 100644
index 0000000..108f243
--- /dev/null
+++ b/test/CodeGen/X86/2008-09-11-CoalescerBug.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -march=x86
+; PR2783
+
+@g_15 = external global i16 ; <i16*> [#uses=2]
+
+define i32 @func_3(i32 %p_5) nounwind {
+entry:
+ %0 = srem i32 1, 0 ; <i32> [#uses=2]
+ %1 = load i16* @g_15, align 2 ; <i16> [#uses=1]
+ %2 = zext i16 %1 to i32 ; <i32> [#uses=1]
+ %3 = and i32 %2, 1 ; <i32> [#uses=1]
+ %4 = tail call i32 (...)* @rshift_u_s( i32 1 ) nounwind ; <i32> [#uses=1]
+ %5 = icmp slt i32 %4, 2 ; <i1> [#uses=1]
+ %6 = zext i1 %5 to i32 ; <i32> [#uses=1]
+ %7 = icmp sge i32 %3, %6 ; <i1> [#uses=1]
+ %8 = zext i1 %7 to i32 ; <i32> [#uses=1]
+ %9 = load i16* @g_15, align 2 ; <i16> [#uses=1]
+ %10 = icmp eq i16 %9, 0 ; <i1> [#uses=1]
+ %11 = zext i1 %10 to i32 ; <i32> [#uses=1]
+ %12 = tail call i32 (...)* @func_20( i32 1 ) nounwind ; <i32> [#uses=1]
+ %13 = icmp sge i32 %11, %12 ; <i1> [#uses=1]
+ %14 = zext i1 %13 to i32 ; <i32> [#uses=1]
+ %15 = sub i32 %8, %14 ; <i32> [#uses=1]
+ %16 = icmp ult i32 %15, 2 ; <i1> [#uses=1]
+ %17 = zext i1 %16 to i32 ; <i32> [#uses=1]
+ %18 = icmp ugt i32 %0, 3 ; <i1> [#uses=1]
+ %or.cond = or i1 false, %18 ; <i1> [#uses=1]
+ %19 = select i1 %or.cond, i32 0, i32 %0 ; <i32> [#uses=1]
+ %.0 = lshr i32 %17, %19 ; <i32> [#uses=1]
+ %20 = tail call i32 (...)* @func_7( i32 %.0 ) nounwind ; <i32> [#uses=0]
+ ret i32 undef
+}
+
+declare i32 @rshift_u_s(...)
+
+declare i32 @func_20(...)
+
+declare i32 @func_7(...)
diff --git a/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll b/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
new file mode 100644
index 0000000..534f990
--- /dev/null
+++ b/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=x86
+; PR2748
+
+@g_73 = external global i32 ; <i32*> [#uses=1]
+@g_5 = external global i32 ; <i32*> [#uses=1]
+
+define i32 @func_44(i16 signext %p_46) nounwind {
+entry:
+ %0 = load i32* @g_5, align 4 ; <i32> [#uses=1]
+ %1 = ashr i32 %0, 1 ; <i32> [#uses=1]
+ %2 = icmp sgt i32 %1, 1 ; <i1> [#uses=1]
+ %3 = zext i1 %2 to i32 ; <i32> [#uses=1]
+ %4 = load i32* @g_73, align 4 ; <i32> [#uses=1]
+ %5 = zext i16 %p_46 to i64 ; <i64> [#uses=1]
+ %6 = sub i64 0, %5 ; <i64> [#uses=1]
+ %7 = trunc i64 %6 to i8 ; <i8> [#uses=2]
+ %8 = trunc i32 %4 to i8 ; <i8> [#uses=2]
+ %9 = icmp eq i8 %8, 0 ; <i1> [#uses=1]
+ br i1 %9, label %bb11, label %bb12
+
+bb11: ; preds = %entry
+ %10 = urem i8 %7, %8 ; <i8> [#uses=1]
+ br label %bb12
+
+bb12: ; preds = %bb11, %entry
+ %.014.in = phi i8 [ %10, %bb11 ], [ %7, %entry ] ; <i8> [#uses=1]
+ %11 = icmp ne i8 %.014.in, 0 ; <i1> [#uses=1]
+ %12 = zext i1 %11 to i32 ; <i32> [#uses=1]
+ %13 = tail call i32 (...)* @func_48( i32 %12, i32 %3, i32 0 ) nounwind ; <i32> [#uses=0]
+ ret i32 undef
+}
+
+declare i32 @func_48(...)
diff --git a/test/CodeGen/X86/2008-09-17-inline-asm-1.ll b/test/CodeGen/X86/2008-09-17-inline-asm-1.ll
new file mode 100644
index 0000000..74429c3
--- /dev/null
+++ b/test/CodeGen/X86/2008-09-17-inline-asm-1.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=x86 | not grep "movl %eax, %eax"
+; RUN: llc < %s -march=x86 | not grep "movl %edx, %edx"
+; RUN: llc < %s -march=x86 | not grep "movl (%eax), %eax"
+; RUN: llc < %s -march=x86 | not grep "movl (%edx), %edx"
+; RUN: llc < %s -march=x86 -regalloc=local | not grep "movl %eax, %eax"
+; RUN: llc < %s -march=x86 -regalloc=local | not grep "movl %edx, %edx"
+; RUN: llc < %s -march=x86 -regalloc=local | not grep "movl (%eax), %eax"
+; RUN: llc < %s -march=x86 -regalloc=local | not grep "movl (%edx), %edx"
+
+; %0 must not be put in EAX or EDX.
+; In the first asm, $0 and $2 must not be put in EAX.
+; In the second asm, $0 and $2 must not be put in EDX.
+; This is kind of hard to test thoroughly, but the things above should continue
+; to pass, I think.
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+@x = common global i32 0 ; <i32*> [#uses=1]
+
+define i32 @aci(i32* %pw) nounwind {
+entry:
+ %0 = load i32* @x, align 4 ; <i32> [#uses=1]
+ %asmtmp = tail call { i32, i32 } asm "movl $0, %eax\0A\090:\0A\09test %eax, %eax\0A\09je 1f\0A\09movl %eax, $2\0A\09incl $2\0A\09lock\0A\09cmpxchgl $2, $0\0A\09jne 0b\0A\091:", "=*m,=&{ax},=&r,*m,~{dirflag},~{fpsr},~{flags},~{memory},~{cc}"(i32* %pw, i32* %pw) nounwind ; <{ i32, i32 }> [#uses=0]
+ %asmtmp2 = tail call { i32, i32 } asm "movl $0, %edx\0A\090:\0A\09test %edx, %edx\0A\09je 1f\0A\09movl %edx, $2\0A\09incl $2\0A\09lock\0A\09cmpxchgl $2, $0\0A\09jne 0b\0A\091:", "=*m,=&{dx},=&r,*m,~{dirflag},~{fpsr},~{flags},~{memory},~{cc}"(i32* %pw, i32* %pw) nounwind ; <{ i32, i32 }> [#uses=1]
+ %asmresult3 = extractvalue { i32, i32 } %asmtmp2, 0 ; <i32> [#uses=1]
+ %1 = add i32 %asmresult3, %0 ; <i32> [#uses=1]
+ ret i32 %1
+}
diff --git a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
new file mode 100644
index 0000000..e3b6fdf
--- /dev/null
+++ b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86 | grep "#%ebp %esi %edi 8(%edx) %eax (%ebx)"
+; RUN: llc < %s -march=x86 -regalloc=local | grep "#%edi %ebp %edx 8(%ebx) %eax (%esi)"
+; The 1st, 2nd, 3rd and 5th registers above must all be different. The registers
+; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
+; operand. There are many combinations that work; this is what llc puts out now.
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+ %struct.foo = type { i32, i32, i8* }
+
+define i32 @get(%struct.foo* %c, i8* %state) nounwind {
+entry:
+ %0 = getelementptr %struct.foo* %c, i32 0, i32 0 ; <i32*> [#uses=2]
+ %1 = getelementptr %struct.foo* %c, i32 0, i32 1 ; <i32*> [#uses=2]
+ %2 = getelementptr %struct.foo* %c, i32 0, i32 2 ; <i8**> [#uses=2]
+ %3 = load i32* %0, align 4 ; <i32> [#uses=1]
+ %4 = load i32* %1, align 4 ; <i32> [#uses=1]
+ %5 = load i8* %state, align 1 ; <i8> [#uses=1]
+ %asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#$0 $1 $2 $3 $4 $5", "=&r,=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %2, i8* %state, i32 %3, i32 %4, i8** %2, i8 %5) nounwind ; <{ i32, i32, i32, i32 }> [#uses=3]
+ %asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0 ; <i32> [#uses=1]
+ %asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1 ; <i32> [#uses=1]
+ store i32 %asmresult1, i32* %0
+ %asmresult2 = extractvalue { i32, i32, i32, i32 } %asmtmp, 2 ; <i32> [#uses=1]
+ store i32 %asmresult2, i32* %1
+ ret i32 %asmresult
+}
diff --git a/test/CodeGen/X86/2008-09-19-RegAllocBug.ll b/test/CodeGen/X86/2008-09-19-RegAllocBug.ll
new file mode 100644
index 0000000..a8f2912
--- /dev/null
+++ b/test/CodeGen/X86/2008-09-19-RegAllocBug.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin
+; PR2808
+
+@g_3 = external global i32 ; <i32*> [#uses=1]
+
+define i32 @func_4() nounwind {
+entry:
+ %0 = load i32* @g_3, align 4 ; <i32> [#uses=2]
+ %1 = trunc i32 %0 to i8 ; <i8> [#uses=1]
+ %2 = sub i8 1, %1 ; <i8> [#uses=1]
+ %3 = sext i8 %2 to i32 ; <i32> [#uses=1]
+ %.0 = ashr i32 %3, select (i1 icmp ne (i8 zext (i1 icmp ugt (i32 ptrtoint (i32 ()* @func_4 to i32), i32 3) to i8), i8 0), i32 0, i32 ptrtoint (i32 ()* @func_4 to i32)) ; <i32> [#uses=1]
+ %4 = urem i32 %0, %.0 ; <i32> [#uses=1]
+ %5 = icmp eq i32 %4, 0 ; <i1> [#uses=1]
+ br i1 %5, label %return, label %bb4
+
+bb4: ; preds = %entry
+ ret i32 undef
+
+return: ; preds = %entry
+ ret i32 undef
+}
diff --git a/test/CodeGen/X86/2008-09-25-sseregparm-1.ll b/test/CodeGen/X86/2008-09-25-sseregparm-1.ll
new file mode 100644
index 0000000..c92a8f4
--- /dev/null
+++ b/test/CodeGen/X86/2008-09-25-sseregparm-1.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movs | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep fld | count 2
+; check 'inreg' attribute for sse_regparm
+
+define double @foo1() inreg nounwind {
+ ret double 1.0
+}
+
+define float @foo2() inreg nounwind {
+ ret float 1.0
+}
+
+define double @bar() nounwind {
+ ret double 1.0
+}
+
+define float @bar2() nounwind {
+ ret float 1.0
+}
diff --git a/test/CodeGen/X86/2008-09-26-FrameAddrBug.ll b/test/CodeGen/X86/2008-09-26-FrameAddrBug.ll
new file mode 100644
index 0000000..f1ada28
--- /dev/null
+++ b/test/CodeGen/X86/2008-09-26-FrameAddrBug.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin9
+
+ %struct._Unwind_Context = type { [18 x i8*], i8*, i8*, i8*, %struct.dwarf_eh_bases, i32, i32, i32, [18 x i8] }
+ %struct._Unwind_Exception = type { i64, void (i32, %struct._Unwind_Exception*)*, i32, i32, [3 x i32] }
+ %struct.dwarf_eh_bases = type { i8*, i8*, i8* }
+
+declare fastcc void @uw_init_context_1(%struct._Unwind_Context*, i8*, i8*)
+
+declare i8* @llvm.eh.dwarf.cfa(i32) nounwind
+
+define hidden void @_Unwind_Resume(%struct._Unwind_Exception* %exc) noreturn noreturn {
+entry:
+ %0 = call i8* @llvm.eh.dwarf.cfa(i32 0) ; <i8*> [#uses=1]
+ call fastcc void @uw_init_context_1(%struct._Unwind_Context* null, i8* %0, i8* null)
+ unreachable
+}
diff --git a/test/CodeGen/X86/2008-09-29-ReMatBug.ll b/test/CodeGen/X86/2008-09-29-ReMatBug.ll
new file mode 100644
index 0000000..c36cf39
--- /dev/null
+++ b/test/CodeGen/X86/2008-09-29-ReMatBug.ll
@@ -0,0 +1,85 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -disable-fp-elim
+
+ %struct..0objc_selector = type opaque
+ %struct.NSString = type opaque
+ %struct.XCStringList = type { i32, %struct._XCStringListNode* }
+ %struct._XCStringListNode = type { [3 x i8], [0 x i8], i8 }
+ %struct.__builtin_CFString = type { i32*, i32, i8*, i32 }
+internal constant %struct.__builtin_CFString { i32* getelementptr ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr ([3 x i8]* @"\01LC", i32 0, i32 0), i32 2 } ; <%struct.__builtin_CFString*>:0 [#uses=1]
+@__CFConstantStringClassReference = external global [0 x i32] ; <[0 x i32]*> [#uses=1]
+@"\01LC" = internal constant [3 x i8] c"NO\00" ; <[3 x i8]*> [#uses=1]
+@"\01LC1" = internal constant [1 x i8] zeroinitializer ; <[1 x i8]*> [#uses=1]
[email protected] = appending global [1 x i8*] [ i8* bitcast (%struct.NSString* (%struct.XCStringList*, %struct..0objc_selector*)* @"-[XCStringList stringRepresentation]" to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define %struct.NSString* @"-[XCStringList stringRepresentation]"(%struct.XCStringList* %self, %struct..0objc_selector* %_cmd) nounwind {
+entry:
+ %0 = load i32* null, align 4 ; <i32> [#uses=1]
+ %1 = and i32 %0, 16777215 ; <i32> [#uses=1]
+ %2 = icmp eq i32 %1, 0 ; <i1> [#uses=1]
+ br i1 %2, label %bb44, label %bb4
+
+bb4: ; preds = %entry
+ %3 = load %struct._XCStringListNode** null, align 4 ; <%struct._XCStringListNode*> [#uses=2]
+ %4 = icmp eq %struct._XCStringListNode* %3, null ; <i1> [#uses=1]
+ %5 = bitcast %struct._XCStringListNode* %3 to i32* ; <i32*> [#uses=1]
+ br label %bb37.outer
+
+bb6: ; preds = %bb37
+ br label %bb19
+
+bb19: ; preds = %bb37, %bb6
+ %.rle = phi i32 [ 0, %bb6 ], [ %10, %bb37 ] ; <i32> [#uses=1]
+ %bufptr.0.lcssa = phi i8* [ null, %bb6 ], [ null, %bb37 ] ; <i8*> [#uses=2]
+ %6 = and i32 %.rle, 16777215 ; <i32> [#uses=1]
+ %7 = icmp eq i32 %6, 0 ; <i1> [#uses=1]
+ br i1 %7, label %bb25.split, label %bb37
+
+bb25.split: ; preds = %bb19
+ call void @foo(i8* getelementptr ([1 x i8]* @"\01LC1", i32 0, i32 0)) nounwind nounwind
+ br label %bb35.outer
+
+bb34: ; preds = %bb35, %bb35, %bb35, %bb35
+ %8 = getelementptr i8* %bufptr.0.lcssa, i32 %totalLength.0.ph ; <i8*> [#uses=1]
+ store i8 92, i8* %8, align 1
+ br label %bb35.outer
+
+bb35.outer: ; preds = %bb34, %bb25.split
+ %totalLength.0.ph = add i32 0, %totalLength.1.ph ; <i32> [#uses=2]
+ br label %bb35
+
+bb35: ; preds = %bb35, %bb35.outer
+ %9 = load i8* null, align 1 ; <i8> [#uses=1]
+ switch i8 %9, label %bb35 [
+ i8 0, label %bb37.outer
+ i8 32, label %bb34
+ i8 92, label %bb34
+ i8 34, label %bb34
+ i8 39, label %bb34
+ ]
+
+bb37.outer: ; preds = %bb35, %bb4
+ %totalLength.1.ph = phi i32 [ 0, %bb4 ], [ %totalLength.0.ph, %bb35 ] ; <i32> [#uses=1]
+ %bufptr.1.ph = phi i8* [ null, %bb4 ], [ %bufptr.0.lcssa, %bb35 ] ; <i8*> [#uses=2]
+ br i1 %4, label %bb39.split, label %bb37
+
+bb37: ; preds = %bb37.outer, %bb19
+ %10 = load i32* %5, align 4 ; <i32> [#uses=1]
+ br i1 false, label %bb6, label %bb19
+
+bb39.split: ; preds = %bb37.outer
+ %11 = bitcast i8* null to %struct.NSString* ; <%struct.NSString*> [#uses=2]
+ %12 = icmp eq i8* null, %bufptr.1.ph ; <i1> [#uses=1]
+ br i1 %12, label %bb44, label %bb42
+
+bb42: ; preds = %bb39.split
+ call void @quux(i8* %bufptr.1.ph) nounwind nounwind
+ ret %struct.NSString* %11
+
+bb44: ; preds = %bb39.split, %entry
+ %.0 = phi %struct.NSString* [ bitcast (%struct.__builtin_CFString* @0 to %struct.NSString*), %entry ], [ %11, %bb39.split ] ; <%struct.NSString*> [#uses=1]
+ ret %struct.NSString* %.0
+}
+
+declare void @foo(i8*)
+
+declare void @quux(i8*)
diff --git a/test/CodeGen/X86/2008-09-29-VolatileBug.ll b/test/CodeGen/X86/2008-09-29-VolatileBug.ll
new file mode 100644
index 0000000..935c4c5
--- /dev/null
+++ b/test/CodeGen/X86/2008-09-29-VolatileBug.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 | not grep movz
+; PR2835
+
+@g_407 = internal global i32 0 ; <i32*> [#uses=1]
[email protected] = appending global [1 x i8*] [ i8* bitcast (i32 ()* @main to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define i32 @main() nounwind {
+entry:
+ %0 = volatile load i32* @g_407, align 4 ; <i32> [#uses=1]
+ %1 = trunc i32 %0 to i8 ; <i8> [#uses=1]
+ %2 = tail call i32 @func_45(i8 zeroext %1) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
+
+declare i32 @func_45(i8 zeroext) nounwind
diff --git a/test/CodeGen/X86/2008-10-02-Atomics32-2.ll b/test/CodeGen/X86/2008-10-02-Atomics32-2.ll
new file mode 100644
index 0000000..b48c4ad
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-02-Atomics32-2.ll
@@ -0,0 +1,969 @@
+; RUN: llc < %s -march=x86 > %t
+;; This version includes 64-bit version of binary operators (in 32-bit mode).
+;; Swap, cmp-and-swap not supported yet in this mode.
+; ModuleID = 'Atomics.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+@sc = common global i8 0 ; <i8*> [#uses=52]
+@uc = common global i8 0 ; <i8*> [#uses=112]
+@ss = common global i16 0 ; <i16*> [#uses=15]
+@us = common global i16 0 ; <i16*> [#uses=15]
+@si = common global i32 0 ; <i32*> [#uses=15]
+@ui = common global i32 0 ; <i32*> [#uses=23]
+@sl = common global i32 0 ; <i32*> [#uses=15]
+@ul = common global i32 0 ; <i32*> [#uses=15]
+@sll = common global i64 0, align 8 ; <i64*> [#uses=13]
+@ull = common global i64 0, align 8 ; <i64*> [#uses=13]
+
+define void @test_op_ignore() nounwind {
+entry:
+ %0 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @sc, i8 1) ; <i8> [#uses=0]
+ %1 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @uc, i8 1) ; <i8> [#uses=0]
+ %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %3 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %2, i16 1) ; <i16> [#uses=0]
+ %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %5 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %4, i16 1) ; <i16> [#uses=0]
+ %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %7 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %6, i32 1) ; <i32> [#uses=0]
+ %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %9 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %8, i32 1) ; <i32> [#uses=0]
+ %10 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %11 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %10, i32 1) ; <i32> [#uses=0]
+ %12 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %13 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %12, i32 1) ; <i32> [#uses=0]
+ %14 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %15 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %14, i64 1) ; <i64> [#uses=0]
+ %16 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %17 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %16, i64 1) ; <i64> [#uses=0]
+ %18 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @sc, i8 1) ; <i8> [#uses=0]
+ %19 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @uc, i8 1) ; <i8> [#uses=0]
+ %20 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %21 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %20, i16 1) ; <i16> [#uses=0]
+ %22 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %23 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %22, i16 1) ; <i16> [#uses=0]
+ %24 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %25 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %24, i32 1) ; <i32> [#uses=0]
+ %26 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %27 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %26, i32 1) ; <i32> [#uses=0]
+ %28 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %29 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %28, i32 1) ; <i32> [#uses=0]
+ %30 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %31 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %30, i32 1) ; <i32> [#uses=0]
+ %32 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %33 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %32, i64 1) ; <i64> [#uses=0]
+ %34 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %35 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %34, i64 1) ; <i64> [#uses=0]
+ %36 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @sc, i8 1) ; <i8> [#uses=0]
+ %37 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @uc, i8 1) ; <i8> [#uses=0]
+ %38 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %39 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %38, i16 1) ; <i16> [#uses=0]
+ %40 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %41 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %40, i16 1) ; <i16> [#uses=0]
+ %42 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %43 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %42, i32 1) ; <i32> [#uses=0]
+ %44 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %45 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %44, i32 1) ; <i32> [#uses=0]
+ %46 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %47 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %46, i32 1) ; <i32> [#uses=0]
+ %48 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %49 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %48, i32 1) ; <i32> [#uses=0]
+ %50 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %51 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %50, i64 1) ; <i64> [#uses=0]
+ %52 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %53 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %52, i64 1) ; <i64> [#uses=0]
+ %54 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @sc, i8 1) ; <i8> [#uses=0]
+ %55 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @uc, i8 1) ; <i8> [#uses=0]
+ %56 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %57 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %56, i16 1) ; <i16> [#uses=0]
+ %58 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %59 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %58, i16 1) ; <i16> [#uses=0]
+ %60 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %61 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %60, i32 1) ; <i32> [#uses=0]
+ %62 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %63 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %62, i32 1) ; <i32> [#uses=0]
+ %64 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %65 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %64, i32 1) ; <i32> [#uses=0]
+ %66 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %67 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %66, i32 1) ; <i32> [#uses=0]
+ %68 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %69 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %68, i64 1) ; <i64> [#uses=0]
+ %70 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %71 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %70, i64 1) ; <i64> [#uses=0]
+ %72 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @sc, i8 1) ; <i8> [#uses=0]
+ %73 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @uc, i8 1) ; <i8> [#uses=0]
+ %74 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %75 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %74, i16 1) ; <i16> [#uses=0]
+ %76 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %77 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %76, i16 1) ; <i16> [#uses=0]
+ %78 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %79 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %78, i32 1) ; <i32> [#uses=0]
+ %80 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %81 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %80, i32 1) ; <i32> [#uses=0]
+ %82 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %83 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %82, i32 1) ; <i32> [#uses=0]
+ %84 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %85 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %84, i32 1) ; <i32> [#uses=0]
+ %86 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %87 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %86, i64 1) ; <i64> [#uses=0]
+ %88 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %89 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %88, i64 1) ; <i64> [#uses=0]
+ %90 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @sc, i8 1) ; <i8> [#uses=0]
+ %91 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @uc, i8 1) ; <i8> [#uses=0]
+ %92 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %93 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %92, i16 1) ; <i16> [#uses=0]
+ %94 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %95 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %94, i16 1) ; <i16> [#uses=0]
+ %96 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %97 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %96, i32 1) ; <i32> [#uses=0]
+ %98 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %99 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %98, i32 1) ; <i32> [#uses=0]
+ %100 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %101 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %100, i32 1) ; <i32> [#uses=0]
+ %102 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %103 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %102, i32 1) ; <i32> [#uses=0]
+ %104 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %105 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %104, i64 1) ; <i64> [#uses=0]
+ %106 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %107 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %106, i64 1) ; <i64> [#uses=0]
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.add.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.add.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.sub.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.sub.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.sub.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.or.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.or.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.or.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.xor.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.xor.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.xor.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.and.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.and.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.and.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.nand.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.nand.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.nand.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.nand.i64.p0i64(i64*, i64) nounwind
+
+define void @test_fetch_and_op() nounwind {
+entry:
+ %0 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @sc, i8 11) ; <i8> [#uses=1]
+ store i8 %0, i8* @sc, align 1
+ %1 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @uc, i8 11) ; <i8> [#uses=1]
+ store i8 %1, i8* @uc, align 1
+ %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %3 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %2, i16 11) ; <i16> [#uses=1]
+ store i16 %3, i16* @ss, align 2
+ %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %5 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %4, i16 11) ; <i16> [#uses=1]
+ store i16 %5, i16* @us, align 2
+ %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %7 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %6, i32 11) ; <i32> [#uses=1]
+ store i32 %7, i32* @si, align 4
+ %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %9 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %8, i32 11) ; <i32> [#uses=1]
+ store i32 %9, i32* @ui, align 4
+ %10 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %11 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %10, i32 11) ; <i32> [#uses=1]
+ store i32 %11, i32* @sl, align 4
+ %12 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %13 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %12, i32 11) ; <i32> [#uses=1]
+ store i32 %13, i32* @ul, align 4
+ %14 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %15 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %14, i64 11) ; <i64> [#uses=1]
+ store i64 %15, i64* @sll, align 8
+ %16 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %17 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %16, i64 11) ; <i64> [#uses=1]
+ store i64 %17, i64* @ull, align 8
+ %18 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @sc, i8 11) ; <i8> [#uses=1]
+ store i8 %18, i8* @sc, align 1
+ %19 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @uc, i8 11) ; <i8> [#uses=1]
+ store i8 %19, i8* @uc, align 1
+ %20 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %21 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %20, i16 11) ; <i16> [#uses=1]
+ store i16 %21, i16* @ss, align 2
+ %22 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %23 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %22, i16 11) ; <i16> [#uses=1]
+ store i16 %23, i16* @us, align 2
+ %24 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %25 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %24, i32 11) ; <i32> [#uses=1]
+ store i32 %25, i32* @si, align 4
+ %26 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %27 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %26, i32 11) ; <i32> [#uses=1]
+ store i32 %27, i32* @ui, align 4
+ %28 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %29 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %28, i32 11) ; <i32> [#uses=1]
+ store i32 %29, i32* @sl, align 4
+ %30 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %31 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %30, i32 11) ; <i32> [#uses=1]
+ store i32 %31, i32* @ul, align 4
+ %32 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %33 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %32, i64 11) ; <i64> [#uses=1]
+ store i64 %33, i64* @sll, align 8
+ %34 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %35 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %34, i64 11) ; <i64> [#uses=1]
+ store i64 %35, i64* @ull, align 8
+ %36 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @sc, i8 11) ; <i8> [#uses=1]
+ store i8 %36, i8* @sc, align 1
+ %37 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @uc, i8 11) ; <i8> [#uses=1]
+ store i8 %37, i8* @uc, align 1
+ %38 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %39 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %38, i16 11) ; <i16> [#uses=1]
+ store i16 %39, i16* @ss, align 2
+ %40 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %41 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %40, i16 11) ; <i16> [#uses=1]
+ store i16 %41, i16* @us, align 2
+ %42 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %43 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %42, i32 11) ; <i32> [#uses=1]
+ store i32 %43, i32* @si, align 4
+ %44 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %45 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %44, i32 11) ; <i32> [#uses=1]
+ store i32 %45, i32* @ui, align 4
+ %46 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %47 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %46, i32 11) ; <i32> [#uses=1]
+ store i32 %47, i32* @sl, align 4
+ %48 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %49 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %48, i32 11) ; <i32> [#uses=1]
+ store i32 %49, i32* @ul, align 4
+ %50 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %51 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %50, i64 11) ; <i64> [#uses=1]
+ store i64 %51, i64* @sll, align 8
+ %52 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %53 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %52, i64 11) ; <i64> [#uses=1]
+ store i64 %53, i64* @ull, align 8
+ %54 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @sc, i8 11) ; <i8> [#uses=1]
+ store i8 %54, i8* @sc, align 1
+ %55 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @uc, i8 11) ; <i8> [#uses=1]
+ store i8 %55, i8* @uc, align 1
+ %56 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %57 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %56, i16 11) ; <i16> [#uses=1]
+ store i16 %57, i16* @ss, align 2
+ %58 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %59 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %58, i16 11) ; <i16> [#uses=1]
+ store i16 %59, i16* @us, align 2
+ %60 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %61 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %60, i32 11) ; <i32> [#uses=1]
+ store i32 %61, i32* @si, align 4
+ %62 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %63 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %62, i32 11) ; <i32> [#uses=1]
+ store i32 %63, i32* @ui, align 4
+ %64 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %65 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %64, i32 11) ; <i32> [#uses=1]
+ store i32 %65, i32* @sl, align 4
+ %66 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %67 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %66, i32 11) ; <i32> [#uses=1]
+ store i32 %67, i32* @ul, align 4
+ %68 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %69 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %68, i64 11) ; <i64> [#uses=1]
+ store i64 %69, i64* @sll, align 8
+ %70 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %71 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %70, i64 11) ; <i64> [#uses=1]
+ store i64 %71, i64* @ull, align 8
+ %72 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @sc, i8 11) ; <i8> [#uses=1]
+ store i8 %72, i8* @sc, align 1
+ %73 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @uc, i8 11) ; <i8> [#uses=1]
+ store i8 %73, i8* @uc, align 1
+ %74 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %75 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %74, i16 11) ; <i16> [#uses=1]
+ store i16 %75, i16* @ss, align 2
+ %76 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %77 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %76, i16 11) ; <i16> [#uses=1]
+ store i16 %77, i16* @us, align 2
+ %78 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %79 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %78, i32 11) ; <i32> [#uses=1]
+ store i32 %79, i32* @si, align 4
+ %80 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %81 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %80, i32 11) ; <i32> [#uses=1]
+ store i32 %81, i32* @ui, align 4
+ %82 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %83 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %82, i32 11) ; <i32> [#uses=1]
+ store i32 %83, i32* @sl, align 4
+ %84 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %85 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %84, i32 11) ; <i32> [#uses=1]
+ store i32 %85, i32* @ul, align 4
+ %86 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %87 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %86, i64 11) ; <i64> [#uses=1]
+ store i64 %87, i64* @sll, align 8
+ %88 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %89 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %88, i64 11) ; <i64> [#uses=1]
+ store i64 %89, i64* @ull, align 8
+ %90 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @sc, i8 11) ; <i8> [#uses=1]
+ store i8 %90, i8* @sc, align 1
+ %91 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @uc, i8 11) ; <i8> [#uses=1]
+ store i8 %91, i8* @uc, align 1
+ %92 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %93 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %92, i16 11) ; <i16> [#uses=1]
+ store i16 %93, i16* @ss, align 2
+ %94 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %95 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %94, i16 11) ; <i16> [#uses=1]
+ store i16 %95, i16* @us, align 2
+ %96 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %97 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %96, i32 11) ; <i32> [#uses=1]
+ store i32 %97, i32* @si, align 4
+ %98 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %99 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %98, i32 11) ; <i32> [#uses=1]
+ store i32 %99, i32* @ui, align 4
+ %100 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %101 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %100, i32 11) ; <i32> [#uses=1]
+ store i32 %101, i32* @sl, align 4
+ %102 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %103 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %102, i32 11) ; <i32> [#uses=1]
+ store i32 %103, i32* @ul, align 4
+ %104 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %105 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %104, i64 11) ; <i64> [#uses=1]
+ store i64 %105, i64* @sll, align 8
+ %106 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %107 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %106, i64 11) ; <i64> [#uses=1]
+ store i64 %107, i64* @ull, align 8
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define void @test_op_and_fetch() nounwind {
+entry:
+ %0 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %1 = zext i8 %0 to i32 ; <i32> [#uses=1]
+ %2 = trunc i32 %1 to i8 ; <i8> [#uses=2]
+ %3 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @sc, i8 %2) ; <i8> [#uses=1]
+ %4 = add i8 %3, %2 ; <i8> [#uses=1]
+ store i8 %4, i8* @sc, align 1
+ %5 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %6 = zext i8 %5 to i32 ; <i32> [#uses=1]
+ %7 = trunc i32 %6 to i8 ; <i8> [#uses=2]
+ %8 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @uc, i8 %7) ; <i8> [#uses=1]
+ %9 = add i8 %8, %7 ; <i8> [#uses=1]
+ store i8 %9, i8* @uc, align 1
+ %10 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %11 = zext i8 %10 to i32 ; <i32> [#uses=1]
+ %12 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %13 = trunc i32 %11 to i16 ; <i16> [#uses=2]
+ %14 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %12, i16 %13) ; <i16> [#uses=1]
+ %15 = add i16 %14, %13 ; <i16> [#uses=1]
+ store i16 %15, i16* @ss, align 2
+ %16 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %17 = zext i8 %16 to i32 ; <i32> [#uses=1]
+ %18 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %19 = trunc i32 %17 to i16 ; <i16> [#uses=2]
+ %20 = call i16 @llvm.atomic.load.add.i16.p0i16(i16* %18, i16 %19) ; <i16> [#uses=1]
+ %21 = add i16 %20, %19 ; <i16> [#uses=1]
+ store i16 %21, i16* @us, align 2
+ %22 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %23 = zext i8 %22 to i32 ; <i32> [#uses=2]
+ %24 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %25 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %24, i32 %23) ; <i32> [#uses=1]
+ %26 = add i32 %25, %23 ; <i32> [#uses=1]
+ store i32 %26, i32* @si, align 4
+ %27 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %28 = zext i8 %27 to i32 ; <i32> [#uses=2]
+ %29 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %30 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %29, i32 %28) ; <i32> [#uses=1]
+ %31 = add i32 %30, %28 ; <i32> [#uses=1]
+ store i32 %31, i32* @ui, align 4
+ %32 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %33 = zext i8 %32 to i32 ; <i32> [#uses=2]
+ %34 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %35 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %34, i32 %33) ; <i32> [#uses=1]
+ %36 = add i32 %35, %33 ; <i32> [#uses=1]
+ store i32 %36, i32* @sl, align 4
+ %37 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %38 = zext i8 %37 to i32 ; <i32> [#uses=2]
+ %39 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %40 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* %39, i32 %38) ; <i32> [#uses=1]
+ %41 = add i32 %40, %38 ; <i32> [#uses=1]
+ store i32 %41, i32* @ul, align 4
+ %42 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %43 = zext i8 %42 to i64 ; <i64> [#uses=2]
+ %44 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %45 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %44, i64 %43) ; <i64> [#uses=1]
+ %46 = add i64 %45, %43 ; <i64> [#uses=1]
+ store i64 %46, i64* @sll, align 8
+ %47 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %48 = zext i8 %47 to i64 ; <i64> [#uses=2]
+ %49 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %50 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %49, i64 %48) ; <i64> [#uses=1]
+ %51 = add i64 %50, %48 ; <i64> [#uses=1]
+ store i64 %51, i64* @ull, align 8
+ %52 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %53 = zext i8 %52 to i32 ; <i32> [#uses=1]
+ %54 = trunc i32 %53 to i8 ; <i8> [#uses=2]
+ %55 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @sc, i8 %54) ; <i8> [#uses=1]
+ %56 = sub i8 %55, %54 ; <i8> [#uses=1]
+ store i8 %56, i8* @sc, align 1
+ %57 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %58 = zext i8 %57 to i32 ; <i32> [#uses=1]
+ %59 = trunc i32 %58 to i8 ; <i8> [#uses=2]
+ %60 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @uc, i8 %59) ; <i8> [#uses=1]
+ %61 = sub i8 %60, %59 ; <i8> [#uses=1]
+ store i8 %61, i8* @uc, align 1
+ %62 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %63 = zext i8 %62 to i32 ; <i32> [#uses=1]
+ %64 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %65 = trunc i32 %63 to i16 ; <i16> [#uses=2]
+ %66 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %64, i16 %65) ; <i16> [#uses=1]
+ %67 = sub i16 %66, %65 ; <i16> [#uses=1]
+ store i16 %67, i16* @ss, align 2
+ %68 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %69 = zext i8 %68 to i32 ; <i32> [#uses=1]
+ %70 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %71 = trunc i32 %69 to i16 ; <i16> [#uses=2]
+ %72 = call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %70, i16 %71) ; <i16> [#uses=1]
+ %73 = sub i16 %72, %71 ; <i16> [#uses=1]
+ store i16 %73, i16* @us, align 2
+ %74 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %75 = zext i8 %74 to i32 ; <i32> [#uses=2]
+ %76 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %77 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %76, i32 %75) ; <i32> [#uses=1]
+ %78 = sub i32 %77, %75 ; <i32> [#uses=1]
+ store i32 %78, i32* @si, align 4
+ %79 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %80 = zext i8 %79 to i32 ; <i32> [#uses=2]
+ %81 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %82 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %81, i32 %80) ; <i32> [#uses=1]
+ %83 = sub i32 %82, %80 ; <i32> [#uses=1]
+ store i32 %83, i32* @ui, align 4
+ %84 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %85 = zext i8 %84 to i32 ; <i32> [#uses=2]
+ %86 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %87 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %86, i32 %85) ; <i32> [#uses=1]
+ %88 = sub i32 %87, %85 ; <i32> [#uses=1]
+ store i32 %88, i32* @sl, align 4
+ %89 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %90 = zext i8 %89 to i32 ; <i32> [#uses=2]
+ %91 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %92 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %91, i32 %90) ; <i32> [#uses=1]
+ %93 = sub i32 %92, %90 ; <i32> [#uses=1]
+ store i32 %93, i32* @ul, align 4
+ %94 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %95 = zext i8 %94 to i64 ; <i64> [#uses=2]
+ %96 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %97 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %96, i64 %95) ; <i64> [#uses=1]
+ %98 = sub i64 %97, %95 ; <i64> [#uses=1]
+ store i64 %98, i64* @sll, align 8
+ %99 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %100 = zext i8 %99 to i64 ; <i64> [#uses=2]
+ %101 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %102 = call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %101, i64 %100) ; <i64> [#uses=1]
+ %103 = sub i64 %102, %100 ; <i64> [#uses=1]
+ store i64 %103, i64* @ull, align 8
+ %104 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %105 = zext i8 %104 to i32 ; <i32> [#uses=1]
+ %106 = trunc i32 %105 to i8 ; <i8> [#uses=2]
+ %107 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @sc, i8 %106) ; <i8> [#uses=1]
+ %108 = or i8 %107, %106 ; <i8> [#uses=1]
+ store i8 %108, i8* @sc, align 1
+ %109 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %110 = zext i8 %109 to i32 ; <i32> [#uses=1]
+ %111 = trunc i32 %110 to i8 ; <i8> [#uses=2]
+ %112 = call i8 @llvm.atomic.load.or.i8.p0i8(i8* @uc, i8 %111) ; <i8> [#uses=1]
+ %113 = or i8 %112, %111 ; <i8> [#uses=1]
+ store i8 %113, i8* @uc, align 1
+ %114 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %115 = zext i8 %114 to i32 ; <i32> [#uses=1]
+ %116 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %117 = trunc i32 %115 to i16 ; <i16> [#uses=2]
+ %118 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %116, i16 %117) ; <i16> [#uses=1]
+ %119 = or i16 %118, %117 ; <i16> [#uses=1]
+ store i16 %119, i16* @ss, align 2
+ %120 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %121 = zext i8 %120 to i32 ; <i32> [#uses=1]
+ %122 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %123 = trunc i32 %121 to i16 ; <i16> [#uses=2]
+ %124 = call i16 @llvm.atomic.load.or.i16.p0i16(i16* %122, i16 %123) ; <i16> [#uses=1]
+ %125 = or i16 %124, %123 ; <i16> [#uses=1]
+ store i16 %125, i16* @us, align 2
+ %126 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %127 = zext i8 %126 to i32 ; <i32> [#uses=2]
+ %128 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %129 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %128, i32 %127) ; <i32> [#uses=1]
+ %130 = or i32 %129, %127 ; <i32> [#uses=1]
+ store i32 %130, i32* @si, align 4
+ %131 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %132 = zext i8 %131 to i32 ; <i32> [#uses=2]
+ %133 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %134 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %133, i32 %132) ; <i32> [#uses=1]
+ %135 = or i32 %134, %132 ; <i32> [#uses=1]
+ store i32 %135, i32* @ui, align 4
+ %136 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %137 = zext i8 %136 to i32 ; <i32> [#uses=2]
+ %138 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %139 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %138, i32 %137) ; <i32> [#uses=1]
+ %140 = or i32 %139, %137 ; <i32> [#uses=1]
+ store i32 %140, i32* @sl, align 4
+ %141 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %142 = zext i8 %141 to i32 ; <i32> [#uses=2]
+ %143 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %144 = call i32 @llvm.atomic.load.or.i32.p0i32(i32* %143, i32 %142) ; <i32> [#uses=1]
+ %145 = or i32 %144, %142 ; <i32> [#uses=1]
+ store i32 %145, i32* @ul, align 4
+ %146 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %147 = zext i8 %146 to i64 ; <i64> [#uses=2]
+ %148 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %149 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %148, i64 %147) ; <i64> [#uses=1]
+ %150 = or i64 %149, %147 ; <i64> [#uses=1]
+ store i64 %150, i64* @sll, align 8
+ %151 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %152 = zext i8 %151 to i64 ; <i64> [#uses=2]
+ %153 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %154 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %153, i64 %152) ; <i64> [#uses=1]
+ %155 = or i64 %154, %152 ; <i64> [#uses=1]
+ store i64 %155, i64* @ull, align 8
+ %156 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %157 = zext i8 %156 to i32 ; <i32> [#uses=1]
+ %158 = trunc i32 %157 to i8 ; <i8> [#uses=2]
+ %159 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @sc, i8 %158) ; <i8> [#uses=1]
+ %160 = xor i8 %159, %158 ; <i8> [#uses=1]
+ store i8 %160, i8* @sc, align 1
+ %161 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %162 = zext i8 %161 to i32 ; <i32> [#uses=1]
+ %163 = trunc i32 %162 to i8 ; <i8> [#uses=2]
+ %164 = call i8 @llvm.atomic.load.xor.i8.p0i8(i8* @uc, i8 %163) ; <i8> [#uses=1]
+ %165 = xor i8 %164, %163 ; <i8> [#uses=1]
+ store i8 %165, i8* @uc, align 1
+ %166 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %167 = zext i8 %166 to i32 ; <i32> [#uses=1]
+ %168 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %169 = trunc i32 %167 to i16 ; <i16> [#uses=2]
+ %170 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %168, i16 %169) ; <i16> [#uses=1]
+ %171 = xor i16 %170, %169 ; <i16> [#uses=1]
+ store i16 %171, i16* @ss, align 2
+ %172 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %173 = zext i8 %172 to i32 ; <i32> [#uses=1]
+ %174 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %175 = trunc i32 %173 to i16 ; <i16> [#uses=2]
+ %176 = call i16 @llvm.atomic.load.xor.i16.p0i16(i16* %174, i16 %175) ; <i16> [#uses=1]
+ %177 = xor i16 %176, %175 ; <i16> [#uses=1]
+ store i16 %177, i16* @us, align 2
+ %178 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %179 = zext i8 %178 to i32 ; <i32> [#uses=2]
+ %180 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %181 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %180, i32 %179) ; <i32> [#uses=1]
+ %182 = xor i32 %181, %179 ; <i32> [#uses=1]
+ store i32 %182, i32* @si, align 4
+ %183 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %184 = zext i8 %183 to i32 ; <i32> [#uses=2]
+ %185 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %186 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %185, i32 %184) ; <i32> [#uses=1]
+ %187 = xor i32 %186, %184 ; <i32> [#uses=1]
+ store i32 %187, i32* @ui, align 4
+ %188 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %189 = zext i8 %188 to i32 ; <i32> [#uses=2]
+ %190 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %191 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %190, i32 %189) ; <i32> [#uses=1]
+ %192 = xor i32 %191, %189 ; <i32> [#uses=1]
+ store i32 %192, i32* @sl, align 4
+ %193 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %194 = zext i8 %193 to i32 ; <i32> [#uses=2]
+ %195 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %196 = call i32 @llvm.atomic.load.xor.i32.p0i32(i32* %195, i32 %194) ; <i32> [#uses=1]
+ %197 = xor i32 %196, %194 ; <i32> [#uses=1]
+ store i32 %197, i32* @ul, align 4
+ %198 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %199 = zext i8 %198 to i64 ; <i64> [#uses=2]
+ %200 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %201 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %200, i64 %199) ; <i64> [#uses=1]
+ %202 = xor i64 %201, %199 ; <i64> [#uses=1]
+ store i64 %202, i64* @sll, align 8
+ %203 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %204 = zext i8 %203 to i64 ; <i64> [#uses=2]
+ %205 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %206 = call i64 @llvm.atomic.load.xor.i64.p0i64(i64* %205, i64 %204) ; <i64> [#uses=1]
+ %207 = xor i64 %206, %204 ; <i64> [#uses=1]
+ store i64 %207, i64* @ull, align 8
+ %208 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %209 = zext i8 %208 to i32 ; <i32> [#uses=1]
+ %210 = trunc i32 %209 to i8 ; <i8> [#uses=2]
+ %211 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @sc, i8 %210) ; <i8> [#uses=1]
+ %212 = and i8 %211, %210 ; <i8> [#uses=1]
+ store i8 %212, i8* @sc, align 1
+ %213 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %214 = zext i8 %213 to i32 ; <i32> [#uses=1]
+ %215 = trunc i32 %214 to i8 ; <i8> [#uses=2]
+ %216 = call i8 @llvm.atomic.load.and.i8.p0i8(i8* @uc, i8 %215) ; <i8> [#uses=1]
+ %217 = and i8 %216, %215 ; <i8> [#uses=1]
+ store i8 %217, i8* @uc, align 1
+ %218 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %219 = zext i8 %218 to i32 ; <i32> [#uses=1]
+ %220 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %221 = trunc i32 %219 to i16 ; <i16> [#uses=2]
+ %222 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %220, i16 %221) ; <i16> [#uses=1]
+ %223 = and i16 %222, %221 ; <i16> [#uses=1]
+ store i16 %223, i16* @ss, align 2
+ %224 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %225 = zext i8 %224 to i32 ; <i32> [#uses=1]
+ %226 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %227 = trunc i32 %225 to i16 ; <i16> [#uses=2]
+ %228 = call i16 @llvm.atomic.load.and.i16.p0i16(i16* %226, i16 %227) ; <i16> [#uses=1]
+ %229 = and i16 %228, %227 ; <i16> [#uses=1]
+ store i16 %229, i16* @us, align 2
+ %230 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %231 = zext i8 %230 to i32 ; <i32> [#uses=2]
+ %232 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %233 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %232, i32 %231) ; <i32> [#uses=1]
+ %234 = and i32 %233, %231 ; <i32> [#uses=1]
+ store i32 %234, i32* @si, align 4
+ %235 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %236 = zext i8 %235 to i32 ; <i32> [#uses=2]
+ %237 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %238 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %237, i32 %236) ; <i32> [#uses=1]
+ %239 = and i32 %238, %236 ; <i32> [#uses=1]
+ store i32 %239, i32* @ui, align 4
+ %240 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %241 = zext i8 %240 to i32 ; <i32> [#uses=2]
+ %242 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %243 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %242, i32 %241) ; <i32> [#uses=1]
+ %244 = and i32 %243, %241 ; <i32> [#uses=1]
+ store i32 %244, i32* @sl, align 4
+ %245 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %246 = zext i8 %245 to i32 ; <i32> [#uses=2]
+ %247 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %248 = call i32 @llvm.atomic.load.and.i32.p0i32(i32* %247, i32 %246) ; <i32> [#uses=1]
+ %249 = and i32 %248, %246 ; <i32> [#uses=1]
+ store i32 %249, i32* @ul, align 4
+ %250 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %251 = zext i8 %250 to i64 ; <i64> [#uses=2]
+ %252 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %253 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %252, i64 %251) ; <i64> [#uses=1]
+ %254 = and i64 %253, %251 ; <i64> [#uses=1]
+ store i64 %254, i64* @sll, align 8
+ %255 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %256 = zext i8 %255 to i64 ; <i64> [#uses=2]
+ %257 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %258 = call i64 @llvm.atomic.load.and.i64.p0i64(i64* %257, i64 %256) ; <i64> [#uses=1]
+ %259 = and i64 %258, %256 ; <i64> [#uses=1]
+ store i64 %259, i64* @ull, align 8
+ %260 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %261 = zext i8 %260 to i32 ; <i32> [#uses=1]
+ %262 = trunc i32 %261 to i8 ; <i8> [#uses=2]
+ %263 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @sc, i8 %262) ; <i8> [#uses=1]
+ %264 = xor i8 %263, -1 ; <i8> [#uses=1]
+ %265 = and i8 %264, %262 ; <i8> [#uses=1]
+ store i8 %265, i8* @sc, align 1
+ %266 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %267 = zext i8 %266 to i32 ; <i32> [#uses=1]
+ %268 = trunc i32 %267 to i8 ; <i8> [#uses=2]
+ %269 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @uc, i8 %268) ; <i8> [#uses=1]
+ %270 = xor i8 %269, -1 ; <i8> [#uses=1]
+ %271 = and i8 %270, %268 ; <i8> [#uses=1]
+ store i8 %271, i8* @uc, align 1
+ %272 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %273 = zext i8 %272 to i32 ; <i32> [#uses=1]
+ %274 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %275 = trunc i32 %273 to i16 ; <i16> [#uses=2]
+ %276 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %274, i16 %275) ; <i16> [#uses=1]
+ %277 = xor i16 %276, -1 ; <i16> [#uses=1]
+ %278 = and i16 %277, %275 ; <i16> [#uses=1]
+ store i16 %278, i16* @ss, align 2
+ %279 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %280 = zext i8 %279 to i32 ; <i32> [#uses=1]
+ %281 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %282 = trunc i32 %280 to i16 ; <i16> [#uses=2]
+ %283 = call i16 @llvm.atomic.load.nand.i16.p0i16(i16* %281, i16 %282) ; <i16> [#uses=1]
+ %284 = xor i16 %283, -1 ; <i16> [#uses=1]
+ %285 = and i16 %284, %282 ; <i16> [#uses=1]
+ store i16 %285, i16* @us, align 2
+ %286 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %287 = zext i8 %286 to i32 ; <i32> [#uses=2]
+ %288 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %289 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %288, i32 %287) ; <i32> [#uses=1]
+ %290 = xor i32 %289, -1 ; <i32> [#uses=1]
+ %291 = and i32 %290, %287 ; <i32> [#uses=1]
+ store i32 %291, i32* @si, align 4
+ %292 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %293 = zext i8 %292 to i32 ; <i32> [#uses=2]
+ %294 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %295 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %294, i32 %293) ; <i32> [#uses=1]
+ %296 = xor i32 %295, -1 ; <i32> [#uses=1]
+ %297 = and i32 %296, %293 ; <i32> [#uses=1]
+ store i32 %297, i32* @ui, align 4
+ %298 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %299 = zext i8 %298 to i32 ; <i32> [#uses=2]
+ %300 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %301 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %300, i32 %299) ; <i32> [#uses=1]
+ %302 = xor i32 %301, -1 ; <i32> [#uses=1]
+ %303 = and i32 %302, %299 ; <i32> [#uses=1]
+ store i32 %303, i32* @sl, align 4
+ %304 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %305 = zext i8 %304 to i32 ; <i32> [#uses=2]
+ %306 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %307 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* %306, i32 %305) ; <i32> [#uses=1]
+ %308 = xor i32 %307, -1 ; <i32> [#uses=1]
+ %309 = and i32 %308, %305 ; <i32> [#uses=1]
+ store i32 %309, i32* @ul, align 4
+ %310 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %311 = zext i8 %310 to i64 ; <i64> [#uses=2]
+ %312 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ %313 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %312, i64 %311) ; <i64> [#uses=1]
+ %314 = xor i64 %313, -1 ; <i64> [#uses=1]
+ %315 = and i64 %314, %311 ; <i64> [#uses=1]
+ store i64 %315, i64* @sll, align 8
+ %316 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %317 = zext i8 %316 to i64 ; <i64> [#uses=2]
+ %318 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ %319 = call i64 @llvm.atomic.load.nand.i64.p0i64(i64* %318, i64 %317) ; <i64> [#uses=1]
+ %320 = xor i64 %319, -1 ; <i64> [#uses=1]
+ %321 = and i64 %320, %317 ; <i64> [#uses=1]
+ store i64 %321, i64* @ull, align 8
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define void @test_compare_and_swap() nounwind {
+entry:
+ %0 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %1 = zext i8 %0 to i32 ; <i32> [#uses=1]
+ %2 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %3 = zext i8 %2 to i32 ; <i32> [#uses=1]
+ %4 = trunc i32 %3 to i8 ; <i8> [#uses=1]
+ %5 = trunc i32 %1 to i8 ; <i8> [#uses=1]
+ %6 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @sc, i8 %4, i8 %5) ; <i8> [#uses=1]
+ store i8 %6, i8* @sc, align 1
+ %7 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %8 = zext i8 %7 to i32 ; <i32> [#uses=1]
+ %9 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %10 = zext i8 %9 to i32 ; <i32> [#uses=1]
+ %11 = trunc i32 %10 to i8 ; <i8> [#uses=1]
+ %12 = trunc i32 %8 to i8 ; <i8> [#uses=1]
+ %13 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @uc, i8 %11, i8 %12) ; <i8> [#uses=1]
+ store i8 %13, i8* @uc, align 1
+ %14 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %15 = sext i8 %14 to i16 ; <i16> [#uses=1]
+ %16 = zext i16 %15 to i32 ; <i32> [#uses=1]
+ %17 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %18 = zext i8 %17 to i32 ; <i32> [#uses=1]
+ %19 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %20 = trunc i32 %18 to i16 ; <i16> [#uses=1]
+ %21 = trunc i32 %16 to i16 ; <i16> [#uses=1]
+ %22 = call i16 @llvm.atomic.cmp.swap.i16.p0i16(i16* %19, i16 %20, i16 %21) ; <i16> [#uses=1]
+ store i16 %22, i16* @ss, align 2
+ %23 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %24 = sext i8 %23 to i16 ; <i16> [#uses=1]
+ %25 = zext i16 %24 to i32 ; <i32> [#uses=1]
+ %26 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %27 = zext i8 %26 to i32 ; <i32> [#uses=1]
+ %28 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %29 = trunc i32 %27 to i16 ; <i16> [#uses=1]
+ %30 = trunc i32 %25 to i16 ; <i16> [#uses=1]
+ %31 = call i16 @llvm.atomic.cmp.swap.i16.p0i16(i16* %28, i16 %29, i16 %30) ; <i16> [#uses=1]
+ store i16 %31, i16* @us, align 2
+ %32 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %33 = sext i8 %32 to i32 ; <i32> [#uses=1]
+ %34 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %35 = zext i8 %34 to i32 ; <i32> [#uses=1]
+ %36 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %37 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %36, i32 %35, i32 %33) ; <i32> [#uses=1]
+ store i32 %37, i32* @si, align 4
+ %38 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %39 = sext i8 %38 to i32 ; <i32> [#uses=1]
+ %40 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %41 = zext i8 %40 to i32 ; <i32> [#uses=1]
+ %42 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %43 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %42, i32 %41, i32 %39) ; <i32> [#uses=1]
+ store i32 %43, i32* @ui, align 4
+ %44 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %45 = sext i8 %44 to i32 ; <i32> [#uses=1]
+ %46 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %47 = zext i8 %46 to i32 ; <i32> [#uses=1]
+ %48 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %49 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %48, i32 %47, i32 %45) ; <i32> [#uses=1]
+ store i32 %49, i32* @sl, align 4
+ %50 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %51 = sext i8 %50 to i32 ; <i32> [#uses=1]
+ %52 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %53 = zext i8 %52 to i32 ; <i32> [#uses=1]
+ %54 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %55 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %54, i32 %53, i32 %51) ; <i32> [#uses=1]
+ store i32 %55, i32* @ul, align 4
+ %56 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %57 = zext i8 %56 to i32 ; <i32> [#uses=1]
+ %58 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %59 = zext i8 %58 to i32 ; <i32> [#uses=1]
+ %60 = trunc i32 %59 to i8 ; <i8> [#uses=2]
+ %61 = trunc i32 %57 to i8 ; <i8> [#uses=1]
+ %62 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @sc, i8 %60, i8 %61) ; <i8> [#uses=1]
+ %63 = icmp eq i8 %62, %60 ; <i1> [#uses=1]
+ %64 = zext i1 %63 to i8 ; <i8> [#uses=1]
+ %65 = zext i8 %64 to i32 ; <i32> [#uses=1]
+ store i32 %65, i32* @ui, align 4
+ %66 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %67 = zext i8 %66 to i32 ; <i32> [#uses=1]
+ %68 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %69 = zext i8 %68 to i32 ; <i32> [#uses=1]
+ %70 = trunc i32 %69 to i8 ; <i8> [#uses=2]
+ %71 = trunc i32 %67 to i8 ; <i8> [#uses=1]
+ %72 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @uc, i8 %70, i8 %71) ; <i8> [#uses=1]
+ %73 = icmp eq i8 %72, %70 ; <i1> [#uses=1]
+ %74 = zext i1 %73 to i8 ; <i8> [#uses=1]
+ %75 = zext i8 %74 to i32 ; <i32> [#uses=1]
+ store i32 %75, i32* @ui, align 4
+ %76 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %77 = sext i8 %76 to i16 ; <i16> [#uses=1]
+ %78 = zext i16 %77 to i32 ; <i32> [#uses=1]
+ %79 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %80 = zext i8 %79 to i32 ; <i32> [#uses=1]
+ %81 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %82 = trunc i32 %80 to i16 ; <i16> [#uses=2]
+ %83 = trunc i32 %78 to i16 ; <i16> [#uses=1]
+ %84 = call i16 @llvm.atomic.cmp.swap.i16.p0i16(i16* %81, i16 %82, i16 %83) ; <i16> [#uses=1]
+ %85 = icmp eq i16 %84, %82 ; <i1> [#uses=1]
+ %86 = zext i1 %85 to i8 ; <i8> [#uses=1]
+ %87 = zext i8 %86 to i32 ; <i32> [#uses=1]
+ store i32 %87, i32* @ui, align 4
+ %88 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %89 = sext i8 %88 to i16 ; <i16> [#uses=1]
+ %90 = zext i16 %89 to i32 ; <i32> [#uses=1]
+ %91 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %92 = zext i8 %91 to i32 ; <i32> [#uses=1]
+ %93 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %94 = trunc i32 %92 to i16 ; <i16> [#uses=2]
+ %95 = trunc i32 %90 to i16 ; <i16> [#uses=1]
+ %96 = call i16 @llvm.atomic.cmp.swap.i16.p0i16(i16* %93, i16 %94, i16 %95) ; <i16> [#uses=1]
+ %97 = icmp eq i16 %96, %94 ; <i1> [#uses=1]
+ %98 = zext i1 %97 to i8 ; <i8> [#uses=1]
+ %99 = zext i8 %98 to i32 ; <i32> [#uses=1]
+ store i32 %99, i32* @ui, align 4
+ %100 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %101 = sext i8 %100 to i32 ; <i32> [#uses=1]
+ %102 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %103 = zext i8 %102 to i32 ; <i32> [#uses=2]
+ %104 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %105 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %104, i32 %103, i32 %101) ; <i32> [#uses=1]
+ %106 = icmp eq i32 %105, %103 ; <i1> [#uses=1]
+ %107 = zext i1 %106 to i8 ; <i8> [#uses=1]
+ %108 = zext i8 %107 to i32 ; <i32> [#uses=1]
+ store i32 %108, i32* @ui, align 4
+ %109 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %110 = sext i8 %109 to i32 ; <i32> [#uses=1]
+ %111 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %112 = zext i8 %111 to i32 ; <i32> [#uses=2]
+ %113 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %114 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %113, i32 %112, i32 %110) ; <i32> [#uses=1]
+ %115 = icmp eq i32 %114, %112 ; <i1> [#uses=1]
+ %116 = zext i1 %115 to i8 ; <i8> [#uses=1]
+ %117 = zext i8 %116 to i32 ; <i32> [#uses=1]
+ store i32 %117, i32* @ui, align 4
+ %118 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %119 = sext i8 %118 to i32 ; <i32> [#uses=1]
+ %120 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %121 = zext i8 %120 to i32 ; <i32> [#uses=2]
+ %122 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %123 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %122, i32 %121, i32 %119) ; <i32> [#uses=1]
+ %124 = icmp eq i32 %123, %121 ; <i1> [#uses=1]
+ %125 = zext i1 %124 to i8 ; <i8> [#uses=1]
+ %126 = zext i8 %125 to i32 ; <i32> [#uses=1]
+ store i32 %126, i32* @ui, align 4
+ %127 = load i8* @sc, align 1 ; <i8> [#uses=1]
+ %128 = sext i8 %127 to i32 ; <i32> [#uses=1]
+ %129 = load i8* @uc, align 1 ; <i8> [#uses=1]
+ %130 = zext i8 %129 to i32 ; <i32> [#uses=2]
+ %131 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %132 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* %131, i32 %130, i32 %128) ; <i32> [#uses=1]
+ %133 = icmp eq i32 %132, %130 ; <i1> [#uses=1]
+ %134 = zext i1 %133 to i8 ; <i8> [#uses=1]
+ %135 = zext i8 %134 to i32 ; <i32> [#uses=1]
+ store i32 %135, i32* @ui, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8*, i8, i8) nounwind
+
+declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16*, i16, i16) nounwind
+
+declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind
+
+define void @test_lock() nounwind {
+entry:
+ %0 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @sc, i8 1) ; <i8> [#uses=1]
+ store i8 %0, i8* @sc, align 1
+ %1 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @uc, i8 1) ; <i8> [#uses=1]
+ store i8 %1, i8* @uc, align 1
+ %2 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ %3 = call i16 @llvm.atomic.swap.i16.p0i16(i16* %2, i16 1) ; <i16> [#uses=1]
+ store i16 %3, i16* @ss, align 2
+ %4 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ %5 = call i16 @llvm.atomic.swap.i16.p0i16(i16* %4, i16 1) ; <i16> [#uses=1]
+ store i16 %5, i16* @us, align 2
+ %6 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ %7 = call i32 @llvm.atomic.swap.i32.p0i32(i32* %6, i32 1) ; <i32> [#uses=1]
+ store i32 %7, i32* @si, align 4
+ %8 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ %9 = call i32 @llvm.atomic.swap.i32.p0i32(i32* %8, i32 1) ; <i32> [#uses=1]
+ store i32 %9, i32* @ui, align 4
+ %10 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ %11 = call i32 @llvm.atomic.swap.i32.p0i32(i32* %10, i32 1) ; <i32> [#uses=1]
+ store i32 %11, i32* @sl, align 4
+ %12 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ %13 = call i32 @llvm.atomic.swap.i32.p0i32(i32* %12, i32 1) ; <i32> [#uses=1]
+ store i32 %13, i32* @ul, align 4
+ call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
+ volatile store i8 0, i8* @sc, align 1
+ volatile store i8 0, i8* @uc, align 1
+ %14 = bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*> [#uses=1]
+ volatile store i16 0, i16* %14, align 2
+ %15 = bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*> [#uses=1]
+ volatile store i16 0, i16* %15, align 2
+ %16 = bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*> [#uses=1]
+ volatile store i32 0, i32* %16, align 4
+ %17 = bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*> [#uses=1]
+ volatile store i32 0, i32* %17, align 4
+ %18 = bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*> [#uses=1]
+ volatile store i32 0, i32* %18, align 4
+ %19 = bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*> [#uses=1]
+ volatile store i32 0, i32* %19, align 4
+ %20 = bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*> [#uses=1]
+ volatile store i64 0, i64* %20, align 8
+ %21 = bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*> [#uses=1]
+ volatile store i64 0, i64* %21, align 8
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.swap.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.swap.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind
+
+declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind
diff --git a/test/CodeGen/X86/2008-10-06-MMXISelBug.ll b/test/CodeGen/X86/2008-10-06-MMXISelBug.ll
new file mode 100644
index 0000000..7f7b1a4
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-06-MMXISelBug.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2
+; PR2850
+
+@tmp_V2i = common global <2 x i32> zeroinitializer ; <<2 x i32>*> [#uses=2]
+
+define void @f0() nounwind {
+entry:
+ %0 = load <2 x i32>* @tmp_V2i, align 8 ; <<2 x i32>> [#uses=1]
+ %1 = shufflevector <2 x i32> %0, <2 x i32> undef, <2 x i32> zeroinitializer ; <<2 x i32>> [#uses=1]
+ store <2 x i32> %1, <2 x i32>* @tmp_V2i, align 8
+ ret void
+}
diff --git a/test/CodeGen/X86/2008-10-06-x87ld-nan-1.ll b/test/CodeGen/X86/2008-10-06-x87ld-nan-1.ll
new file mode 100644
index 0000000..a135cd4
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-06-x87ld-nan-1.ll
@@ -0,0 +1,13 @@
+; ModuleID = 'nan.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-f80:32:32-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3,-sse | grep fldl
+; This NaN should be shortened to a double (not a float).
+
+declare x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 %f)
+
+define i32 @main() {
+entry_nan.main:
+ call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 0xK7FFFC001234000000800)
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll b/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll
new file mode 100644
index 0000000..bd48105
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll
@@ -0,0 +1,18 @@
+; ModuleID = 'nan.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-f80:32:32-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3,-sse | grep fldt | count 3
+; it is not safe to shorten any of these NaNs.
+
+declare x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 %f)
+
+@_D3nan4rvale = global x86_fp80 0xK7FFF8001234000000000 ; <x86_fp80*> [#uses=1]
+
+define i32 @main() {
+entry_nan.main:
+ %tmp = load x86_fp80* @_D3nan4rvale ; <x86_fp80> [#uses=1]
+ call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 %tmp)
+ call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 0xK7FFF8001234000000000)
+ call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 0xK7FFFC001234000000400)
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2008-10-07-SSEISelBug.ll b/test/CodeGen/X86/2008-10-07-SSEISelBug.ll
new file mode 100644
index 0000000..bc57612
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-07-SSEISelBug.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=x86 -mattr=+sse,-sse2
+
+define <4 x float> @f(float %w) nounwind {
+entry:
+ %retval = alloca <4 x float> ; <<4 x float>*> [#uses=2]
+ %w.addr = alloca float ; <float*> [#uses=2]
+ %.compoundliteral = alloca <4 x float> ; <<4 x float>*> [#uses=2]
+ store float %w, float* %w.addr
+ %tmp = load float* %w.addr ; <float> [#uses=1]
+ %0 = insertelement <4 x float> undef, float %tmp, i32 0 ; <<4 x float>> [#uses=1]
+ %1 = insertelement <4 x float> %0, float 0.000000e+00, i32 1 ; <<4 x float>> [#uses=1]
+ %2 = insertelement <4 x float> %1, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
+ %3 = insertelement <4 x float> %2, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
+ store <4 x float> %3, <4 x float>* %.compoundliteral
+ %tmp1 = load <4 x float>* %.compoundliteral ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp1, <4 x float>* %retval
+ br label %return
+
+return: ; preds = %entry
+ %4 = load <4 x float>* %retval ; <<4 x float>> [#uses=1]
+ ret <4 x float> %4
+}
diff --git a/test/CodeGen/X86/2008-10-11-CallCrash.ll b/test/CodeGen/X86/2008-10-11-CallCrash.ll
new file mode 100644
index 0000000..efc6125
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-11-CallCrash.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s
+; PR2735
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin7"
+@g_385 = external global i32 ; <i32*> [#uses=1]
+
+define i32 @func_45(i64 %p_46, i32 %p_48) nounwind {
+entry:
+ %0 = tail call i32 (...)* @lshift_s_u(i64 %p_46, i64 0) nounwind ; <i32> [#uses=0]
+ %1 = load i32* @g_385, align 4 ; <i32> [#uses=1]
+ %2 = shl i32 %1, 1 ; <i32> [#uses=1]
+ %3 = and i32 %2, 32 ; <i32> [#uses=1]
+ %4 = tail call i32 (...)* @func_87(i32 undef, i32 %p_48, i32 1) nounwind ; <i32> [#uses=1]
+ %5 = add i32 %3, %4 ; <i32> [#uses=1]
+ %6 = tail call i32 (...)* @div_rhs(i32 %5) nounwind ; <i32> [#uses=0]
+ ret i32 undef
+}
+
+declare i32 @lshift_s_u(...)
+declare i32 @func_87(...)
+declare i32 @div_rhs(...)
diff --git a/test/CodeGen/X86/2008-10-13-CoalescerBug.ll b/test/CodeGen/X86/2008-10-13-CoalescerBug.ll
new file mode 100644
index 0000000..4d3f8c2
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-13-CoalescerBug.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=x86
+; PR2775
+
+define i32 @func_77(i8 zeroext %p_79) nounwind {
+entry:
+ %0 = tail call i32 (...)* @func_43(i32 1) nounwind ; <i32> [#uses=1]
+ %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %bb3, label %bb
+
+bb: ; preds = %entry
+ br label %bb3
+
+bb3: ; preds = %bb, %entry
+ %p_79_addr.0 = phi i8 [ 0, %bb ], [ %p_79, %entry ] ; <i8> [#uses=1]
+ %2 = zext i8 %p_79_addr.0 to i32 ; <i32> [#uses=2]
+ %3 = zext i1 false to i32 ; <i32> [#uses=2]
+ %4 = tail call i32 (...)* @rshift_u_s(i32 1) nounwind ; <i32> [#uses=0]
+ %5 = lshr i32 %2, %2 ; <i32> [#uses=3]
+ %6 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br i1 %6, label %bb6, label %bb9
+
+bb6: ; preds = %bb3
+ %7 = ashr i32 %5, %3 ; <i32> [#uses=1]
+ %8 = icmp eq i32 %7, 0 ; <i1> [#uses=1]
+ %9 = select i1 %8, i32 %3, i32 0 ; <i32> [#uses=1]
+ %. = shl i32 %5, %9 ; <i32> [#uses=1]
+ br label %bb9
+
+bb9: ; preds = %bb6, %bb3
+ %.0 = phi i32 [ %., %bb6 ], [ %5, %bb3 ] ; <i32> [#uses=0]
+ br i1 false, label %return, label %bb10
+
+bb10: ; preds = %bb9
+ ret i32 undef
+
+return: ; preds = %bb9
+ ret i32 undef
+}
+
+declare i32 @func_43(...)
+
+declare i32 @rshift_u_s(...)
diff --git a/test/CodeGen/X86/2008-10-16-SpillerBug.ll b/test/CodeGen/X86/2008-10-16-SpillerBug.ll
new file mode 100644
index 0000000..b8ca364
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-16-SpillerBug.ll
@@ -0,0 +1,155 @@
+; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | grep {andl.*7.*edi}
+
+ %struct.XXDActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 }
+ %struct.XXDAlphaTest = type { float, i16, i8, i8 }
+ %struct.XXDArrayRange = type { i8, i8, i8, i8 }
+ %struct.XXDBlendMode = type { i16, i16, i16, i16, %struct.XXTColor4, i16, i16, i8, i8, i8, i8 }
+ %struct.XXDClearColor = type { double, %struct.XXTColor4, %struct.XXTColor4, float, i32 }
+ %struct.XXDClipPlane = type { i32, [6 x %struct.XXTColor4] }
+ %struct.XXDColorBuffer = type { i16, i8, i8, [8 x i16], i8, i8, i8, i8 }
+ %struct.XXDColorMatrix = type { [16 x float]*, %struct.XXDImagingCC }
+ %struct.XXDConvolution = type { %struct.XXTColor4, %struct.XXDImagingCC, i16, i16, [0 x i32], float*, i32, i32 }
+ %struct.XXDDepthTest = type { i16, i16, i8, i8, i8, i8, double, double }
+ %struct.XXDFixedFunction = type { %struct.YYToken* }
+ %struct.XXDFogMode = type { %struct.XXTColor4, float, float, float, float, float, i16, i16, i16, i8, i8 }
+ %struct.XXDHintMode = type { i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 }
+ %struct.XXDHistogram = type { %struct.XXTFixedColor4*, i32, i16, i8, i8 }
+ %struct.XXDImagingCC = type { { float, float }, { float, float }, { float, float }, { float, float } }
+ %struct.XXDImagingSubset = type { %struct.XXDConvolution, %struct.XXDConvolution, %struct.XXDConvolution, %struct.XXDColorMatrix, %struct.XXDMinmax, %struct.XXDHistogram, %struct.XXDImagingCC, %struct.XXDImagingCC, %struct.XXDImagingCC, %struct.XXDImagingCC, i32, [0 x i32] }
+ %struct.XXDLight = type { %struct.XXTColor4, %struct.XXTColor4, %struct.XXTColor4, %struct.XXTColor4, %struct.XXTCoord3, float, float, float, float, float, %struct.XXTCoord3, float, %struct.XXTCoord3, float, %struct.XXTCoord3, float, float, float, float, float }
+ %struct.XXDLightModel = type { %struct.XXTColor4, [8 x %struct.XXDLight], [2 x %struct.XXDMaterial], i32, i16, i16, i16, i8, i8, i8, i8, i8, i8 }
+ %struct.XXDLightProduct = type { %struct.XXTColor4, %struct.XXTColor4, %struct.XXTColor4 }
+ %struct.XXDLineMode = type { float, i32, i16, i16, i8, i8, i8, i8 }
+ %struct.XXDLogicOp = type { i16, i8, i8 }
+ %struct.XXDMaskMode = type { i32, [3 x i32], i8, i8, i8, i8, i8, i8, i8, i8 }
+ %struct.XXDMaterial = type { %struct.XXTColor4, %struct.XXTColor4, %struct.XXTColor4, %struct.XXTColor4, float, float, float, float, [8 x %struct.XXDLightProduct], %struct.XXTColor4, [8 x i32] }
+ %struct.XXDMinmax = type { %struct.XXDMinmaxTable*, i16, i8, i8, [0 x i32] }
+ %struct.XXDMinmaxTable = type { %struct.XXTColor4, %struct.XXTColor4 }
+ %struct.XXDMultisample = type { float, i8, i8, i8, i8, i8, i8, i8, i8 }
+ %struct.XXDPipelineProgramState = type { i8, i8, i8, i8, [0 x i32], %struct.XXTColor4* }
+ %struct.XXDPixelMap = type { i32*, float*, float*, float*, float*, float*, float*, float*, float*, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.XXDPixelMode = type { float, float, %struct.XXDPixelStore, %struct.XXDPixelTransfer, %struct.XXDPixelMap, %struct.XXDImagingSubset, i32, i32 }
+ %struct.XXDPixelPack = type { i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8 }
+ %struct.XXDPixelStore = type { %struct.XXDPixelPack, %struct.XXDPixelPack }
+ %struct.XXDPixelTransfer = type { float, float, float, float, float, float, float, float, float, float, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float }
+ %struct.XXDPointMode = type { float, float, float, float, %struct.XXTCoord3, float, i8, i8, i8, i8, i16, i16, i32, i16, i16 }
+ %struct.XXDPolygonMode = type { [128 x i8], float, float, i16, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8 }
+ %struct.XXDRegisterCombiners = type { i8, i8, i8, i8, i32, [2 x %struct.XXTColor4], [8 x %struct.XXDRegisterCombinersPerStageState], %struct.XXDRegisterCombinersFinalStageState }
+ %struct.XXDRegisterCombinersFinalStageState = type { i8, i8, i8, i8, [7 x %struct.XXDRegisterCombinersPerVariableState] }
+ %struct.XXDRegisterCombinersPerPortionState = type { [4 x %struct.XXDRegisterCombinersPerVariableState], i8, i8, i8, i8, i16, i16, i16, i16, i16, i16 }
+ %struct.XXDRegisterCombinersPerStageState = type { [2 x %struct.XXDRegisterCombinersPerPortionState], [2 x %struct.XXTColor4] }
+ %struct.XXDRegisterCombinersPerVariableState = type { i16, i16, i16, i16 }
+ %struct.XXDScissorTest = type { %struct.XXTFixedColor4, i8, i8, i8, i8 }
+ %struct.XXDState = type <{ i16, i16, i16, i16, i32, i32, [256 x %struct.XXTColor4], [128 x %struct.XXTColor4], %struct.XXDViewport, %struct.XXDTransform, %struct.XXDLightModel, %struct.XXDActiveTextureTargets, %struct.XXDAlphaTest, %struct.XXDBlendMode, %struct.XXDClearColor, %struct.XXDColorBuffer, %struct.XXDDepthTest, %struct.XXDArrayRange, %struct.XXDFogMode, %struct.XXDHintMode, %struct.XXDLineMode, %struct.XXDLogicOp, %struct.XXDMaskMode, %struct.XXDPixelMode, %struct.XXDPointMode, %struct.XXDPolygonMode, %struct.XXDScissorTest, i32, %struct.XXDStencilTest, [8 x %struct.XXDTextureMode], [16 x %struct.XXDTextureImageMode], %struct.XXDArrayRange, [8 x %struct.XXDTextureCoordGen], %struct.XXDClipPlane, %struct.XXDMultisample, %struct.XXDRegisterCombiners, %struct.XXDArrayRange, %struct.XXDArrayRange, [3 x %struct.XXDPipelineProgramState], %struct.XXDArrayRange, %struct.XXDTransformFeedback, i32*, %struct.XXDFixedFunction, [3 x i32], [2 x i32] }>
+ %struct.XXDStencilTest = type { [3 x { i32, i32, i16, i16, i16, i16 }], i32, [4 x i8] }
+ %struct.XXDTextureCoordGen = type { { i16, i16, %struct.XXTColor4, %struct.XXTColor4 }, { i16, i16, %struct.XXTColor4, %struct.XXTColor4 }, { i16, i16, %struct.XXTColor4, %struct.XXTColor4 }, { i16, i16, %struct.XXTColor4, %struct.XXTColor4 }, i8, i8, i8, i8 }
+ %struct.XXDTextureImageMode = type { float }
+ %struct.XXDTextureMode = type { %struct.XXTColor4, i32, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, float, float, i16, i16, i16, i16, i16, i16, [4 x i16], i8, i8, i8, i8, [3 x float], [4 x float], float, float }
+ %struct.XXDTextureRec = type opaque
+ %struct.XXDTransform = type <{ [24 x [16 x float]], [24 x [16 x float]], [16 x float], float, float, float, float, float, i8, i8, i8, i8, i32, i32, i32, i16, i16, i8, i8, i8, i8, i32 }>
+ %struct.XXDTransformFeedback = type { i8, i8, i8, i8, [0 x i32], [16 x i32], [16 x i32] }
+ %struct.XXDViewport = type { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, double, double, i32, i32, i32, i32, float, float, float, float }
+ %struct.XXTColor4 = type { float, float, float, float }
+ %struct.XXTCoord3 = type { float, float, float }
+ %struct.XXTFixedColor4 = type { i32, i32, i32, i32 }
+ %struct.XXVMTextures = type { [16 x %struct.XXDTextureRec*] }
+ %struct.XXVMVPContext = type { i32 }
+ %struct.XXVMVPStack = type { i32, i32 }
+ %struct.YYToken = type { { i16, i16, i32 } }
+ %struct._XXVMConstants = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, float, float, float, float, float, float, float, float, float, float, float, float, [256 x float], [4096 x i8], [8 x float], [48 x float], [128 x float], [528 x i8], { void (i8*, i8*, i32, i8*)*, float (float)*, float (float)*, float (float)*, i32 (float)* } }
[email protected] = appending global [1 x i8*] [ i8* bitcast (void (%struct.XXDState*, <4 x float>*, <4 x float>**, %struct._XXVMConstants*, %struct.YYToken*, %struct.XXVMVPContext*, %struct.XXVMTextures*, %struct.XXVMVPStack*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, [4 x <4 x float>]*, i32*, <4 x i32>*, i64)* @t to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define void @t(%struct.XXDState* %gldst, <4 x float>* %prgrm, <4 x float>** %buffs, %struct._XXVMConstants* %cnstn, %struct.YYToken* %pstrm, %struct.XXVMVPContext* %vmctx, %struct.XXVMTextures* %txtrs, %struct.XXVMVPStack* %vpstk, <4 x float>* %atr0, <4 x float>* %atr1, <4 x float>* %atr2, <4 x float>* %atr3, <4 x float>* %vtx0, <4 x float>* %vtx1, <4 x float>* %vtx2, <4 x float>* %vtx3, [4 x <4 x float>]* %tmpGbl, i32* %oldMsk, <4 x i32>* %adrGbl, i64 %key_token) nounwind {
+entry:
+ %0 = trunc i64 %key_token to i32 ; <i32> [#uses=1]
+ %1 = getelementptr %struct.YYToken* %pstrm, i32 %0 ; <%struct.YYToken*> [#uses=5]
+ br label %bb1132
+
+bb51: ; preds = %bb1132
+ %2 = getelementptr %struct.YYToken* %1, i32 %operation.0.rec, i32 0, i32 0 ; <i16*> [#uses=1]
+ %3 = load i16* %2, align 1 ; <i16> [#uses=3]
+ %4 = lshr i16 %3, 6 ; <i16> [#uses=1]
+ %5 = trunc i16 %4 to i8 ; <i8> [#uses=1]
+ %6 = zext i8 %5 to i32 ; <i32> [#uses=1]
+ %7 = trunc i16 %3 to i8 ; <i8> [#uses=1]
+ %8 = and i8 %7, 7 ; <i8> [#uses=1]
+ %mask5556 = zext i8 %8 to i32 ; <i32> [#uses=3]
+ %.sum1324 = add i32 %mask5556, 2 ; <i32> [#uses=1]
+ %.rec = add i32 %operation.0.rec, %.sum1324 ; <i32> [#uses=1]
+ %9 = bitcast %struct.YYToken* %operation.0 to i32* ; <i32*> [#uses=1]
+ %10 = load i32* %9, align 1 ; <i32> [#uses=1]
+ %11 = lshr i32 %10, 16 ; <i32> [#uses=2]
+ %12 = trunc i32 %11 to i8 ; <i8> [#uses=1]
+ %13 = and i8 %12, 1 ; <i8> [#uses=1]
+ %14 = lshr i16 %3, 15 ; <i16> [#uses=1]
+ %15 = trunc i16 %14 to i8 ; <i8> [#uses=1]
+ %16 = or i8 %13, %15 ; <i8> [#uses=1]
+ %17 = icmp eq i8 %16, 0 ; <i1> [#uses=1]
+ br i1 %17, label %bb94, label %bb75
+
+bb75: ; preds = %bb51
+ %18 = getelementptr %struct.YYToken* %1, i32 0, i32 0, i32 0 ; <i16*> [#uses=1]
+ %19 = load i16* %18, align 4 ; <i16> [#uses=1]
+ %20 = load i16* null, align 2 ; <i16> [#uses=1]
+ %21 = zext i16 %19 to i64 ; <i64> [#uses=1]
+ %22 = zext i16 %20 to i64 ; <i64> [#uses=1]
+ %23 = shl i64 %22, 16 ; <i64> [#uses=1]
+ %.ins1177 = or i64 %23, %21 ; <i64> [#uses=1]
+ %.ins1175 = or i64 %.ins1177, 0 ; <i64> [#uses=1]
+ %24 = and i32 %11, 1 ; <i32> [#uses=1]
+ %.neg1333 = sub i32 %mask5556, %24 ; <i32> [#uses=1]
+ %.neg1335 = sub i32 %.neg1333, 0 ; <i32> [#uses=1]
+ %25 = sub i32 %.neg1335, 0 ; <i32> [#uses=1]
+ br label %bb94
+
+bb94: ; preds = %bb75, %bb51
+ %extraToken.0 = phi i64 [ %.ins1175, %bb75 ], [ %extraToken.1, %bb51 ] ; <i64> [#uses=1]
+ %argCount.0 = phi i32 [ %25, %bb75 ], [ %mask5556, %bb51 ] ; <i32> [#uses=1]
+ %operation.0.sum1392 = add i32 %operation.0.rec, 1 ; <i32> [#uses=2]
+ %26 = getelementptr %struct.YYToken* %1, i32 %operation.0.sum1392, i32 0, i32 0 ; <i16*> [#uses=1]
+ %27 = load i16* %26, align 4 ; <i16> [#uses=1]
+ %28 = getelementptr %struct.YYToken* %1, i32 %operation.0.sum1392, i32 0, i32 1 ; <i16*> [#uses=1]
+ %29 = load i16* %28, align 2 ; <i16> [#uses=1]
+ store i16 %27, i16* null, align 8
+ store i16 %29, i16* null, align 2
+ br i1 false, label %bb1132, label %bb110
+
+bb110: ; preds = %bb94
+ switch i32 %6, label %bb1078 [
+ i32 30, label %bb960
+ i32 32, label %bb801
+ i32 38, label %bb809
+ i32 78, label %bb1066
+ ]
+
+bb801: ; preds = %bb110
+ unreachable
+
+bb809: ; preds = %bb110
+ unreachable
+
+bb960: ; preds = %bb110
+ %30 = icmp eq i32 %argCount.0, 1 ; <i1> [#uses=1]
+ br i1 %30, label %bb962, label %bb965
+
+bb962: ; preds = %bb960
+ unreachable
+
+bb965: ; preds = %bb960
+ unreachable
+
+bb1066: ; preds = %bb110
+ unreachable
+
+bb1078: ; preds = %bb110
+ unreachable
+
+bb1132: ; preds = %bb94, %entry
+ %extraToken.1 = phi i64 [ undef, %entry ], [ %extraToken.0, %bb94 ] ; <i64> [#uses=1]
+ %operation.0.rec = phi i32 [ 0, %entry ], [ %.rec, %bb94 ] ; <i32> [#uses=4]
+ %operation.0 = getelementptr %struct.YYToken* %1, i32 %operation.0.rec ; <%struct.YYToken*> [#uses=1]
+ br i1 false, label %bb1134, label %bb51
+
+bb1134: ; preds = %bb1132
+ ret void
+}
diff --git a/test/CodeGen/X86/2008-10-16-VecUnaryOp.ll b/test/CodeGen/X86/2008-10-16-VecUnaryOp.ll
new file mode 100644
index 0000000..de4c1e7
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-16-VecUnaryOp.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+; PR2762
+define void @foo(<4 x i32>* %p, <4 x double>* %q) {
+ %n = load <4 x i32>* %p
+ %z = sitofp <4 x i32> %n to <4 x double>
+ store <4 x double> %z, <4 x double>* %q
+ ret void
+}
diff --git a/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll b/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll
new file mode 100644
index 0000000..b2e6061
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86-64
+
+define void @test(i64 %x) nounwind {
+entry:
+ tail call void asm sideeffect "ASM: $0", "r,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
+ ret void
+}
+
diff --git a/test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll b/test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll
new file mode 100644
index 0000000..353d1c7
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86-64
+
+; from gcc.c-torture/compile/920520-1.c
+
+define i32 @g() nounwind {
+entry:
+ call void asm sideeffect "$0", "r"(double 1.500000e+00) nounwind
+ ret i32 0
+}
+
diff --git a/test/CodeGen/X86/2008-10-24-FlippedCompare.ll b/test/CodeGen/X86/2008-10-24-FlippedCompare.ll
new file mode 100644
index 0000000..421b931
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-24-FlippedCompare.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o - | not grep {ucomiss\[^,\]*esp}
+
+define void @f(float %wt) {
+entry:
+ %0 = fcmp ogt float %wt, 0.000000e+00 ; <i1> [#uses=1]
+ %1 = tail call i32 @g(i32 44) ; <i32> [#uses=3]
+ %2 = inttoptr i32 %1 to i8* ; <i8*> [#uses=2]
+ br i1 %0, label %bb, label %bb1
+
+bb: ; preds = %entry
+ ret void
+
+bb1: ; preds = %entry
+ ret void
+}
+
+declare i32 @g(i32)
diff --git a/test/CodeGen/X86/2008-10-27-CoalescerBug.ll b/test/CodeGen/X86/2008-10-27-CoalescerBug.ll
new file mode 100644
index 0000000..afeb358
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-27-CoalescerBug.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -stats |& not grep {Number of register spills}
+
+define fastcc void @fourn(double* %data, i32 %isign) nounwind {
+entry:
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %indvar93 = phi i32 [ 0, %entry ], [ %idim.030, %bb ] ; <i32> [#uses=2]
+ %idim.030 = add i32 %indvar93, 1 ; <i32> [#uses=1]
+ %0 = add i32 %indvar93, 2 ; <i32> [#uses=1]
+ %1 = icmp sgt i32 %0, 2 ; <i1> [#uses=1]
+ br i1 %1, label %bb30.loopexit, label %bb
+
+bb3: ; preds = %bb30.loopexit, %bb25, %bb3
+ %2 = load i32* null, align 4 ; <i32> [#uses=1]
+ %3 = mul i32 %2, 0 ; <i32> [#uses=1]
+ %4 = icmp slt i32 0, %3 ; <i1> [#uses=1]
+ br i1 %4, label %bb18, label %bb3
+
+bb18: ; preds = %bb3
+ %5 = fdiv double %11, 0.000000e+00 ; <double> [#uses=1]
+ %6 = tail call double @sin(double %5) nounwind readonly ; <double> [#uses=1]
+ br label %bb24.preheader
+
+bb22.preheader: ; preds = %bb24.preheader, %bb22.preheader
+ br label %bb22.preheader
+
+bb25: ; preds = %bb24.preheader
+ %7 = fmul double 0.000000e+00, %6 ; <double> [#uses=0]
+ %8 = add i32 %i3.122100, 0 ; <i32> [#uses=1]
+ %9 = icmp sgt i32 %8, 0 ; <i1> [#uses=1]
+ br i1 %9, label %bb3, label %bb24.preheader
+
+bb24.preheader: ; preds = %bb25, %bb18
+ %i3.122100 = or i32 0, 1 ; <i32> [#uses=2]
+ %10 = icmp slt i32 0, %i3.122100 ; <i1> [#uses=1]
+ br i1 %10, label %bb25, label %bb22.preheader
+
+bb30.loopexit: ; preds = %bb
+ %11 = fmul double 0.000000e+00, 0x401921FB54442D1C ; <double> [#uses=1]
+ br label %bb3
+}
+
+declare double @sin(double) nounwind readonly
diff --git a/test/CodeGen/X86/2008-10-27-StackRealignment.ll b/test/CodeGen/X86/2008-10-27-StackRealignment.ll
new file mode 100644
index 0000000..784bc72
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-27-StackRealignment.ll
@@ -0,0 +1,22 @@
+; Linux doesn't support stack realignment for functions with allocas (PR2888).
+; Until it does, we shouldn't use movaps to access the stack. On targets with
+; sufficiently aligned stack (e.g. darwin) we should.
+
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu -mcpu=yonah | not grep movaps
+; RUN: llc < %s -mtriple=i686-apple-darwin9 -mcpu=yonah | grep movaps | count 2
+
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+
+define void @foo(i32 %t) nounwind {
+ %tmp1210 = alloca i8, i32 32, align 4
+ call void @llvm.memset.i64(i8* %tmp1210, i8 0, i64 32, i32 4)
+
+ %x = alloca i8, i32 %t
+ call void @dummy(i8* %x)
+ ret void
+}
+
+declare void @dummy(i8* %x)
+declare void @llvm.memset.i64(i8*, i8, i64, i32) nounwind
diff --git a/test/CodeGen/X86/2008-10-29-ExpandVAARG.ll b/test/CodeGen/X86/2008-10-29-ExpandVAARG.ll
new file mode 100644
index 0000000..7ad94f1
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-29-ExpandVAARG.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86
+; PR2977
+define i8* @ap_php_conv_p2(){
+entry:
+ %ap.addr = alloca i8* ; <i8**> [#uses=36]
+ br label %sw.bb301
+sw.bb301:
+ %0 = va_arg i8** %ap.addr, i64 ; <i64> [#uses=1]
+ br label %sw.bb301
+}
diff --git a/test/CodeGen/X86/2008-11-03-F80VAARG.ll b/test/CodeGen/X86/2008-11-03-F80VAARG.ll
new file mode 100644
index 0000000..507799b
--- /dev/null
+++ b/test/CodeGen/X86/2008-11-03-F80VAARG.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 -o - | not grep 10
+
+declare void @llvm.va_start(i8*) nounwind
+
+declare void @llvm.va_copy(i8*, i8*) nounwind
+
+declare void @llvm.va_end(i8*) nounwind
+
+define x86_fp80 @test(...) nounwind {
+ %ap = alloca i8* ; <i8**> [#uses=3]
+ %v1 = bitcast i8** %ap to i8* ; <i8*> [#uses=1]
+ call void @llvm.va_start(i8* %v1)
+ %t1 = va_arg i8** %ap, x86_fp80 ; <x86_fp80> [#uses=1]
+ %t2 = va_arg i8** %ap, x86_fp80 ; <x86_fp80> [#uses=1]
+ %t = fadd x86_fp80 %t1, %t2 ; <x86_fp80> [#uses=1]
+ ret x86_fp80 %t
+}
diff --git a/test/CodeGen/X86/2008-11-06-testb.ll b/test/CodeGen/X86/2008-11-06-testb.ll
new file mode 100644
index 0000000..f8f317c
--- /dev/null
+++ b/test/CodeGen/X86/2008-11-06-testb.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep testb
+
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.5"
+ %struct.x = type <{ i8, i8, i16 }>
+
+define i32 @foo(%struct.x* %p) nounwind {
+entry:
+ %0 = getelementptr %struct.x* %p, i32 0, i32 0 ; <i8*> [#uses=1]
+ store i8 55, i8* %0, align 1
+ %1 = bitcast %struct.x* %p to i32* ; <i32*> [#uses=1]
+ %2 = load i32* %1, align 1 ; <i32> [#uses=1]
+ %3 = and i32 %2, 512 ; <i32> [#uses=1]
+ %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1]
+ br i1 %4, label %bb5, label %bb
+
+bb: ; preds = %entry
+ %5 = tail call i32 (...)* @xx() nounwind ; <i32> [#uses=1]
+ ret i32 %5
+
+bb5: ; preds = %entry
+ ret i32 0
+}
+
+declare i32 @xx(...)
diff --git a/test/CodeGen/X86/2008-11-13-inlineasm-3.ll b/test/CodeGen/X86/2008-11-13-inlineasm-3.ll
new file mode 100644
index 0000000..1dc97fc
--- /dev/null
+++ b/test/CodeGen/X86/2008-11-13-inlineasm-3.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu
+; PR 1779
+; Using 'A' constraint and a tied constraint together used to crash.
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i686-pc-linux-gnu"
+ %struct.linux_dirent64 = type { i64, i64, i16, i8, [0 x i8] }
+
+define i32 @sys_getdents64(i32 %fd, %struct.linux_dirent64* %dirent, i32 %count) {
+entry:
+ br i1 true, label %cond_next29, label %UnifiedReturnBlock
+
+cond_next29: ; preds = %entry
+ %tmp83 = call i32 asm sideeffect "1:\09movl %eax,0($2)\0A2:\09movl %edx,4($2)\0A3:\0A.section .fixup,\22ax\22\0A4:\09movl $3,$0\0A\09jmp 3b\0A.previous\0A .section __ex_table,\22a\22\0A .balign 4 \0A .long 1b,4b\0A .previous\0A .section __ex_table,\22a\22\0A .balign 4 \0A .long 2b,4b\0A .previous\0A", "=r,A,r,i,0,~{dirflag},~{fpsr},~{flags}"(i64 0, i64* null, i32 -14, i32 0) nounwind ; <i32> [#uses=0]
+ br label %UnifiedReturnBlock
+
+UnifiedReturnBlock: ; preds = %entry
+ ret i32 -14
+}
diff --git a/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll b/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll
new file mode 100644
index 0000000..2e114ab
--- /dev/null
+++ b/test/CodeGen/X86/2008-11-29-DivideConstant16bit.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu | grep -- -1985 | count 1
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i686-pc-linux-gnu"
+
+define zeroext i16 @a(i16 zeroext %x) nounwind {
+entry:
+ %div = udiv i16 %x, 33 ; <i32> [#uses=1]
+ ret i16 %div
+}
diff --git a/test/CodeGen/X86/2008-11-29-DivideConstant16bitSigned.ll b/test/CodeGen/X86/2008-11-29-DivideConstant16bitSigned.ll
new file mode 100644
index 0000000..7c811af
--- /dev/null
+++ b/test/CodeGen/X86/2008-11-29-DivideConstant16bitSigned.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu | grep -- -1985
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i686-pc-linux-gnu"
+
+define signext i16 @a(i16 signext %x) nounwind {
+entry:
+ %div = sdiv i16 %x, 33 ; <i32> [#uses=1]
+ ret i16 %div
+}
diff --git a/test/CodeGen/X86/2008-11-29-ULT-Sign.ll b/test/CodeGen/X86/2008-11-29-ULT-Sign.ll
new file mode 100644
index 0000000..6dca141
--- /dev/null
+++ b/test/CodeGen/X86/2008-11-29-ULT-Sign.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu | grep "jns" | count 1
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i686-pc-linux-gnu"
+
+define i32 @a(i32 %x) nounwind {
+entry:
+ %cmp = icmp ult i32 %x, -2147483648 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ %call = call i32 (...)* @b() ; <i32> [#uses=0]
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ br label %return
+
+return: ; preds = %if.end
+ ret i32 undef
+}
+
+declare i32 @b(...)
+
diff --git a/test/CodeGen/X86/2008-12-01-SpillerAssert.ll b/test/CodeGen/X86/2008-12-01-SpillerAssert.ll
new file mode 100644
index 0000000..d96d806
--- /dev/null
+++ b/test/CodeGen/X86/2008-12-01-SpillerAssert.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
+; PR3124
+
+ %struct.cpuinfo_x86 = type { i8, i8, i8, i8, i32, i8, i8, i8, i32, i32, [9 x i32], [16 x i8], [64 x i8], i32, i32, i32, i64, %struct.cpumask_t, i16, i16, i16, i16, i16, i16, i16, i16, i32 }
+ %struct.cpumask_t = type { [1 x i64] }
[email protected] = external constant [70 x i8] ; <[70 x i8]*> [#uses=1]
+
+declare i32 @printk(i8*, ...)
+
+define void @display_cacheinfo(%struct.cpuinfo_x86* %c) nounwind section ".cpuinit.text" {
+entry:
+ %asmtmp = tail call { i32, i32, i32, i32 } asm "cpuid", "={ax},={bx},={cx},={dx},0,2,~{dirflag},~{fpsr},~{flags}"(i32 -2147483643, i32 0) nounwind ; <{ i32, i32, i32, i32 }> [#uses=0]
+ %0 = tail call i32 (i8*, ...)* @printk(i8* getelementptr ([70 x i8]* @.str10, i32 0, i64 0), i32 0, i32 0, i32 0, i32 0) nounwind ; <i32> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/X86/2008-12-01-loop-iv-used-outside-loop.ll b/test/CodeGen/X86/2008-12-01-loop-iv-used-outside-loop.ll
new file mode 100644
index 0000000..1f8bd45
--- /dev/null
+++ b/test/CodeGen/X86/2008-12-01-loop-iv-used-outside-loop.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | not grep lea
+; The inner loop should use [reg] addressing, not [reg+reg] addressing.
+; rdar://6403965
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.5"
+
+define i8* @test(i8* %Q, i32* %L) nounwind {
+entry:
+ br label %bb1
+
+bb: ; preds = %bb1, %bb1
+ %indvar.next = add i32 %P.0.rec, 1 ; <i32> [#uses=1]
+ br label %bb1
+
+bb1: ; preds = %bb, %entry
+ %P.0.rec = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
+ %P.0 = getelementptr i8* %Q, i32 %P.0.rec ; <i8*> [#uses=2]
+ %0 = load i8* %P.0, align 1 ; <i8> [#uses=1]
+ switch i8 %0, label %bb3 [
+ i8 12, label %bb
+ i8 42, label %bb
+ ]
+
+bb3: ; preds = %bb1
+ %P.0.sum = add i32 %P.0.rec, 2 ; <i32> [#uses=1]
+ %1 = getelementptr i8* %Q, i32 %P.0.sum ; <i8*> [#uses=1]
+ store i8 4, i8* %1, align 1
+ ret i8* %P.0
+}
diff --git a/test/CodeGen/X86/2008-12-02-IllegalResultType.ll b/test/CodeGen/X86/2008-12-02-IllegalResultType.ll
new file mode 100644
index 0000000..4b72cb9
--- /dev/null
+++ b/test/CodeGen/X86/2008-12-02-IllegalResultType.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s
+; PR3117
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+@g_118 = external global i8 ; <i8*> [#uses=1]
+@g_7 = external global i32 ; <i32*> [#uses=1]
+
+define i32 @func_73(i32 %p_74) nounwind {
+entry:
+ %0 = load i32* @g_7, align 4 ; <i32> [#uses=1]
+ %1 = or i8 0, 118 ; <i8> [#uses=1]
+ %2 = zext i8 %1 to i64 ; <i64> [#uses=1]
+ %3 = icmp ne i32 %0, 0 ; <i1> [#uses=1]
+ %4 = zext i1 %3 to i64 ; <i64> [#uses=1]
+ %5 = or i64 %4, -758998846 ; <i64> [#uses=3]
+ %6 = icmp sle i64 %2, %5 ; <i1> [#uses=1]
+ %7 = zext i1 %6 to i8 ; <i8> [#uses=1]
+ %8 = or i8 %7, 118 ; <i8> [#uses=1]
+ %9 = zext i8 %8 to i64 ; <i64> [#uses=1]
+ %10 = icmp sle i64 %9, 0 ; <i1> [#uses=1]
+ %11 = zext i1 %10 to i8 ; <i8> [#uses=1]
+ %12 = or i8 %11, 118 ; <i8> [#uses=1]
+ %13 = zext i8 %12 to i64 ; <i64> [#uses=1]
+ %14 = icmp sle i64 %13, %5 ; <i1> [#uses=1]
+ %15 = zext i1 %14 to i8 ; <i8> [#uses=1]
+ %16 = or i8 %15, 118 ; <i8> [#uses=1]
+ %17 = zext i8 %16 to i64 ; <i64> [#uses=1]
+ %18 = icmp sle i64 %17, 0 ; <i1> [#uses=1]
+ %19 = zext i1 %18 to i8 ; <i8> [#uses=1]
+ %20 = or i8 %19, 118 ; <i8> [#uses=1]
+ %21 = zext i8 %20 to i64 ; <i64> [#uses=1]
+ %22 = icmp sle i64 %21, %5 ; <i1> [#uses=1]
+ %23 = zext i1 %22 to i8 ; <i8> [#uses=1]
+ %24 = or i8 %23, 118 ; <i8> [#uses=1]
+ store i8 %24, i8* @g_118, align 1
+ ret i32 undef
+}
diff --git a/test/CodeGen/X86/2008-12-02-dagcombine-1.ll b/test/CodeGen/X86/2008-12-02-dagcombine-1.ll
new file mode 100644
index 0000000..fe5bff3
--- /dev/null
+++ b/test/CodeGen/X86/2008-12-02-dagcombine-1.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86 | grep "(%esp)" | count 2
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.5"
+; a - a should be found and removed, leaving refs to only L and P
+define i8* @test(i8* %a, i8* %L, i8* %P) nounwind {
+entry:
+ %0 = ptrtoint i8* %a to i32
+ %1 = sub i32 -2, %0
+ %2 = ptrtoint i8* %P to i32
+ %3 = sub i32 0, %2
+ %4 = ptrtoint i8* %L to i32
+ %5 = add i32 %4, %3
+ %6 = add i32 %5, %1 ; <i32> [#uses=1]
+ %7 = getelementptr i8* %a, i32 %6 ; <i8*> [#uses=1]
+ br label %return
+
+return: ; preds = %bb3
+ ret i8* %7
+}
diff --git a/test/CodeGen/X86/2008-12-02-dagcombine-2.ll b/test/CodeGen/X86/2008-12-02-dagcombine-2.ll
new file mode 100644
index 0000000..4cb1b42
--- /dev/null
+++ b/test/CodeGen/X86/2008-12-02-dagcombine-2.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 | grep "(%esp)" | count 2
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.5"
+; a - a should be found and removed, leaving refs to only L and P
+define i8* @test(i8* %a, i8* %L, i8* %P) nounwind {
+entry:
+ %0 = ptrtoint i8* %a to i32
+ %1 = ptrtoint i8* %P to i32
+ %2 = sub i32 %1, %0
+ %3 = ptrtoint i8* %L to i32
+ %4 = sub i32 %2, %3 ; <i32> [#uses=1]
+ %5 = getelementptr i8* %a, i32 %4 ; <i8*> [#uses=1]
+ br label %return
+
+return: ; preds = %bb3
+ ret i8* %5
+}
diff --git a/test/CodeGen/X86/2008-12-02-dagcombine-3.ll b/test/CodeGen/X86/2008-12-02-dagcombine-3.ll
new file mode 100644
index 0000000..d5a676a7
--- /dev/null
+++ b/test/CodeGen/X86/2008-12-02-dagcombine-3.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 | grep add | count 2
+; RUN: llc < %s -march=x86 | grep sub | grep -v subsections | count 1
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.5"
+; this should be rearranged to have two +s and one -
+define i32 @test(i8* %a, i8* %L, i8* %P) nounwind {
+entry:
+ %0 = ptrtoint i8* %P to i32
+ %1 = sub i32 -2, %0
+ %2 = ptrtoint i8* %L to i32
+ %3 = ptrtoint i8* %a to i32
+ %4 = sub i32 %2, %3 ; <i32> [#uses=1]
+ %5 = add i32 %1, %4 ; <i32> [#uses=1]
+ br label %return
+
+return: ; preds = %bb3
+ ret i32 %5
+}
diff --git a/test/CodeGen/X86/2008-12-05-SpillerCrash.ll b/test/CodeGen/X86/2008-12-05-SpillerCrash.ll
new file mode 100644
index 0000000..7fd2e6f
--- /dev/null
+++ b/test/CodeGen/X86/2008-12-05-SpillerCrash.ll
@@ -0,0 +1,237 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin9.5 -mattr=+sse41 -relocation-model=pic
+
+ %struct.XXActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 }
+ %struct.XXAlphaTest = type { float, i16, i8, i8 }
+ %struct.XXArrayRange = type { i8, i8, i8, i8 }
+ %struct.XXBlendMode = type { i16, i16, i16, i16, %struct.ZZIColor4, i16, i16, i8, i8, i8, i8 }
+ %struct.XXBBRec = type opaque
+ %struct.XXBBstate = type { %struct.ZZGTransformKey, %struct.ZZGTransformKey, %struct.XXProgramLimits, %struct.XXProgramLimits, i8, i8, i8, i8, %struct.ZZSBB, %struct.ZZSBB, [4 x %struct.ZZSBB], %struct.ZZSBB, %struct.ZZSBB, %struct.ZZSBB, [8 x %struct.ZZSBB], %struct.ZZSBB }
+ %struct.XXClearColor = type { double, %struct.ZZIColor4, %struct.ZZIColor4, float, i32 }
+ %struct.XXClipPlane = type { i32, [6 x %struct.ZZIColor4] }
+ %struct.XXColorBB = type { i16, i8, i8, [8 x i16], i8, i8, i8, i8 }
+ %struct.XXColorMatrix = type { [16 x float]*, %struct.XXImagingColorScale }
+ %struct.XXConfig = type { i32, float, %struct.ZZGTransformKey, %struct.ZZGTransformKey, i8, i8, i8, i8, i8, i8, i16, i32, i32, i32, %struct.XXPixelFormatInfo, %struct.XXPointLineLimits, %struct.XXPointLineLimits, %struct.XXRenderFeatures, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.XXTextureLimits, [3 x %struct.XXPipelineProgramLimits], %struct.XXFragmentProgramLimits, %struct.XXVertexProgramLimits, %struct.XXGeometryShaderLimits, %struct.XXProgramLimits, %struct.XXGeometryShaderLimits, %struct.XXVertexDescriptor*, %struct.XXVertexDescriptor*, [3 x i32], [4 x i32], [0 x i32] }
+ %struct.XXContextRec = type { float, float, float, float, float, float, float, float, %struct.ZZIColor4, %struct.ZZIColor4, %struct.YYFPContext, [16 x [2 x %struct.PPStreamToken]], %struct.ZZGProcessor, %struct._YYConstants*, void (%struct.XXContextRec*, i32, i32, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, i32)*, %struct._YYFunction*, %struct.PPStreamToken*, void (%struct.XXContextRec*, %struct.XXVertex*)*, void (%struct.XXContextRec*, %struct.XXVertex*, %struct.XXVertex*)*, void (%struct.XXContextRec*, %struct.XXVertex*, %struct.XXVertex*, %struct.XXVertex*)*, %struct._YYFunction*, %struct._YYFunction*, %struct._YYFunction*, [4 x i32], [3 x i32], [3 x i32], float, float, float, %struct.PPStreamToken, i32, %struct.ZZSDrawable, %struct.XXFramebufferRec*, %struct.XXFramebufferRec*, %struct.XXRect, %struct.XXFormat, %struct.XXFormat, %struct.XXFormat, %struct.XXConfig*, %struct.XXBBstate, %struct.XXBBstate, %struct.XXSharedRec*, %struct.XXState*, %struct.XXPluginState*, %struct.XXVertex*, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, %struct.XXProgramRec*, %struct.XXPipelineProgramRec*, %struct.YYTextures, %struct.XXStippleData, i8, i16, i8, i32, i32, i32, %struct.XXQueryRec*, %struct.XXQueryRec*, %struct.XXFallback, { void (i8*, i8*, i32, i8*)* } }
+ %struct.XXConvolution = type { %struct.ZZIColor4, %struct.XXImagingColorScale, i16, i16, [0 x i32], float*, i32, i32 }
+ %struct.XXCurrent16A = type { [8 x %struct.ZZIColor4], [16 x %struct.ZZIColor4], %struct.ZZIColor4, %struct.XXPointLineLimits, float, %struct.XXPointLineLimits, float, [4 x float], %struct.XXPointLineLimits, float, float, float, float, i8, i8, i8, i8 }
+ %struct.XXDepthTest = type { i16, i16, i8, i8, i8, i8, double, double }
+ %struct.XXDrawableWindow = type { i32, i32, i32 }
+ %struct.XXFallback = type { float*, %struct.XXRenderDispatch*, %struct.XXConfig*, i8*, i8*, i32, i32 }
+ %struct.XXFenceRec = type opaque
+ %struct.XXFixedFunction = type { %struct.PPStreamToken* }
+ %struct.XXFogMode = type { %struct.ZZIColor4, float, float, float, float, float, i16, i16, i16, i8, i8 }
+ %struct.XXFormat = type { i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8, i32, i32, i32 }
+ %struct.XXFragmentProgramLimits = type { i32, i32, i32, i16, i16, i32, i32 }
+ %struct.XXFramebufferAttachment = type { i16, i16, i32, i32, i32 }
+ %struct.XXFramebufferData = type { [10 x %struct.XXFramebufferAttachment], [8 x i16], i16, i16, i16, i8, i8, i32, i32 }
+ %struct.XXFramebufferRec = type { %struct.XXFramebufferData*, %struct.XXPluginFramebufferData*, %struct.XXFormat, i8, i8, i8, i8 }
+ %struct.XXGeometryShaderLimits = type { i32, i32, i32, i32, i32 }
+ %struct.XXHintMode = type { i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 }
+ %struct.XXHistogram = type { %struct.XXProgramLimits*, i32, i16, i8, i8 }
+ %struct.XXImagingColorScale = type { %struct.ZZTCoord2, %struct.ZZTCoord2, %struct.ZZTCoord2, %struct.ZZTCoord2 }
+ %struct.XXImagingSubset = type { %struct.XXConvolution, %struct.XXConvolution, %struct.XXConvolution, %struct.XXColorMatrix, %struct.XXMinmax, %struct.XXHistogram, %struct.XXImagingColorScale, %struct.XXImagingColorScale, %struct.XXImagingColorScale, %struct.XXImagingColorScale, i32, [0 x i32] }
+ %struct.XXLight = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.XXPointLineLimits, float, float, float, float, float, %struct.XXPointLineLimits, float, %struct.XXPointLineLimits, float, %struct.XXPointLineLimits, float, float, float, float, float }
+ %struct.XXLightModel = type { %struct.ZZIColor4, [8 x %struct.XXLight], [2 x %struct.XXMaterial], i32, i16, i16, i16, i8, i8, i8, i8, i8, i8 }
+ %struct.XXLightProduct = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4 }
+ %struct.XXLineMode = type { float, i32, i16, i16, i8, i8, i8, i8 }
+ %struct.XXLogicOp = type { i16, i8, i8 }
+ %struct.XXMaskMode = type { i32, [3 x i32], i8, i8, i8, i8, i8, i8, i8, i8 }
+ %struct.XXMaterial = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, float, float, float, float, [8 x %struct.XXLightProduct], %struct.ZZIColor4, [8 x i32] }
+ %struct.XXMinmax = type { %struct.XXMinmaxTable*, i16, i8, i8, [0 x i32] }
+ %struct.XXMinmaxTable = type { %struct.ZZIColor4, %struct.ZZIColor4 }
+ %struct.XXMipmaplevel = type { [4 x i32], [4 x i32], [4 x float], [4 x i32], i32, i32, float*, i8*, i16, i16, i16, i16, [2 x float] }
+ %struct.XXMultisample = type { float, i8, i8, i8, i8, i8, i8, i8, i8 }
+ %struct.XXPipelineProgramData = type { i16, i8, i8, i32, %struct.PPStreamToken*, i64, %struct.ZZIColor4*, i32, [0 x i32] }
+ %struct.XXPipelineProgramLimits = type { i32, i16, i16, i32, i16, i16, i32, i32 }
+ %struct.XXPipelineProgramRec = type { %struct.XXPipelineProgramData*, %struct.PPStreamToken*, %struct.XXContextRec*, { %struct._YYFunction*, \2, \2, [20 x i32], [64 x i32], i32, i32, i32 }*, i32, i32 }
+ %struct.XXPipelineProgramState = type { i8, i8, i8, i8, [0 x i32], %struct.ZZIColor4* }
+ %struct.XXPixelFormatInfo = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
+ %struct.XXPixelMap = type { i32*, float*, float*, float*, float*, float*, float*, float*, float*, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.XXPixelMode = type { float, float, %struct.XXPixelStore, %struct.XXPixelTransfer, %struct.XXPixelMap, %struct.XXImagingSubset, i32, i32 }
+ %struct.XXPixelPack = type { i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8 }
+ %struct.XXPixelStore = type { %struct.XXPixelPack, %struct.XXPixelPack }
+ %struct.XXPixelTransfer = type { float, float, float, float, float, float, float, float, float, float, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float }
+ %struct.XXPluginFramebufferData = type { [10 x %struct.XXTextureRec*], i8, i8, i8, i8 }
+ %struct.XXPluginProgramData = type { [3 x %struct.XXPipelineProgramRec*], %struct.XXBBRec**, i32, [0 x i32] }
+ %struct.XXPluginState = type { [16 x [5 x %struct.XXTextureRec*]], [3 x %struct.XXTextureRec*], [3 x %struct.XXPipelineProgramRec*], [3 x %struct.XXPipelineProgramRec*], %struct.XXProgramRec*, %struct.XXVertexArrayRec*, [16 x %struct.XXBBRec*], %struct.XXFramebufferRec*, %struct.XXFramebufferRec* }
+ %struct.XXPointLineLimits = type { float, float, float }
+ %struct.XXPointMode = type { float, float, float, float, %struct.XXPointLineLimits, float, i8, i8, i8, i8, i16, i16, i32, i16, i16 }
+ %struct.XXPolygonMode = type { [128 x i8], float, float, i16, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8 }
+ %struct.XXProgramData = type { i32, i32, i32, i32, %struct.PPStreamToken*, i32*, i32, i32, i32, i32, i8, i8, i8, i8, [0 x i32] }
+ %struct.XXProgramLimits = type { i32, i32, i32, i32 }
+ %struct.XXProgramRec = type { %struct.XXProgramData*, %struct.XXPluginProgramData*, %struct.ZZIColor4**, i32 }
+ %struct.XXQueryRec = type { i32, i32, %struct.XXQueryRec* }
+ %struct.XXRect = type { i32, i32, i32, i32, i32, i32 }
+ %struct.XXRegisterCombiners = type { i8, i8, i8, i8, i32, [2 x %struct.ZZIColor4], [8 x %struct.XXRegisterCombinersPerStageState], %struct.XXRegisterCombinersFinalStageState }
+ %struct.XXRegisterCombinersFinalStageState = type { i8, i8, i8, i8, [7 x %struct.XXRegisterCombinersPerVariableState] }
+ %struct.XXRegisterCombinersPerPortionState = type { [4 x %struct.XXRegisterCombinersPerVariableState], i8, i8, i8, i8, i16, i16, i16, i16, i16, i16 }
+ %struct.XXRegisterCombinersPerStageState = type { [2 x %struct.XXRegisterCombinersPerPortionState], [2 x %struct.ZZIColor4] }
+ %struct.XXRegisterCombinersPerVariableState = type { i16, i16, i16, i16 }
+ %struct.XXRenderDispatch = type { void (%struct.XXContextRec*, i32, float)*, void (%struct.XXContextRec*, i32)*, i32 (%struct.XXContextRec*, i32, i32, i32, i32, i32, i32, i8*, i32, %struct.XXBBRec*)*, i32 (%struct.XXContextRec*, %struct.XXVertex*, i32, i32, i32, i32, i8*, i32, %struct.XXBBRec*)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32, i32, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32, float, float, i8*, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex**, i32)*, void (%struct.XXContextRec*, %struct.XXVertex**, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex**, i32, i32)*, i8* (%struct.XXContextRec*, i32, i32*)*, void (%struct.XXContextRec*, i32, i32, i32)*, i8* (%struct.XXContextRec*, i32, i32, i32, i32, i32)*, void (%struct.XXContextRec*, i32, i32, i32, i32, i32, i8*)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*, %struct.XXFenceRec*)*, void (%struct.XXContextRec*, i32, %struct.XXQueryRec*)*, void (%struct.XXContextRec*, %struct.XXQueryRec*)*, i32 (%struct.XXContextRec*, i32, i32, i32, i32, i32, i8*, %struct.ZZIColor4*, %struct.XXCurrent16A*)*, i32 (%struct.XXContextRec*, %struct.XXTextureRec*, i32, i32, i32, i32, i32, i32, i32, i32, i32)*, i32 (%struct.XXContextRec*, %struct.XXTextureRec*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i32, %struct.XXBBRec*)*, i32 (%struct.XXContextRec*, %struct.XXTextureRec*, i32)*, i32 (%struct.XXContextRec*, %struct.XXBBRec*, i32, i32, i8*)*, void (%struct.XXContextRec*, i32)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)*, i32 (%struct.XXContextRec*, %struct.XXQueryRec*)*, void (%struct.XXContextRec*)* }
+ %struct.XXRenderFeatures = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
+ %struct.XXSWRSurfaceRec = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i8*, [4 x i8*], i32 }
+ %struct.XXScissorTest = type { %struct.XXProgramLimits, i8, i8, i8, i8 }
+ %struct.XXSharedData = type { }
+ %struct.XXSharedRec = type { %struct.__ZZarrayelementDrawInfoListType, %struct.XXSharedData*, i32, i8, i8, i8, i8 }
+ %struct.XXState = type <{ i16, i16, i16, i16, i32, i32, [256 x %struct.ZZIColor4], [128 x %struct.ZZIColor4], %struct.XXViewport, %struct.XXTransform, %struct.XXLightModel, %struct.XXActiveTextureTargets, %struct.XXAlphaTest, %struct.XXBlendMode, %struct.XXClearColor, %struct.XXColorBB, %struct.XXDepthTest, %struct.XXArrayRange, %struct.XXFogMode, %struct.XXHintMode, %struct.XXLineMode, %struct.XXLogicOp, %struct.XXMaskMode, %struct.XXPixelMode, %struct.XXPointMode, %struct.XXPolygonMode, %struct.XXScissorTest, i32, %struct.XXStencilTest, [8 x %struct.XXTextureMode], [16 x %struct.XXTextureImageMode], %struct.XXArrayRange, [8 x %struct.XXTextureCoordGen], %struct.XXClipPlane, %struct.XXMultisample, %struct.XXRegisterCombiners, %struct.XXArrayRange, %struct.XXArrayRange, [3 x %struct.XXPipelineProgramState], %struct.XXArrayRange, %struct.XXTransformFeedback, i32*, %struct.XXFixedFunction, [1 x i32] }>
+ %struct.XXStencilTest = type { [3 x { i32, i32, i16, i16, i16, i16 }], i32, [4 x i8] }
+ %struct.XXStippleData = type { i32, i16, i16, [32 x [32 x i8]] }
+ %struct.XXTextureCoordGen = type { { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, i8, i8, i8, i8 }
+ %struct.XXTextureGeomState = type { i16, i16, i16, i16, i16, i8, i8, i8, i8, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, [6 x i16], [6 x i16] }
+ %struct.XXTextureImageMode = type { float }
+ %struct.XXTextureLevel = type { i32, i32, i16, i16, i16, i8, i8, i16, i16, i16, i16, i8* }
+ %struct.XXTextureLimits = type { float, float, i16, i16, i16, i16, i16, i16, i16, i16, i16, i8, i8, [16 x i16], i32 }
+ %struct.XXTextureMode = type { %struct.ZZIColor4, i32, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, float, float, i16, i16, i16, i16, i16, i16, [4 x i16], i8, i8, i8, i8, [3 x float], [4 x float], float, float }
+ %struct.XXTextureParamState = type { i16, i16, i16, i16, i16, i16, %struct.ZZIColor4, float, float, float, float, i16, i16, i16, i16, float, i16, i8, i8, i32, i8* }
+ %struct.XXTextureRec = type { [4 x float], %struct.XXTextureState*, %struct.XXMipmaplevel*, %struct.XXMipmaplevel*, float, float, float, float, i8, i8, i8, i8, i16, i16, i16, i16, i32, float, [2 x %struct.PPStreamToken] }
+ %struct.XXTextureState = type { i16, i8, i8, i16, i16, float, i32, %struct.XXSWRSurfaceRec*, %struct.XXTextureParamState, %struct.XXTextureGeomState, i16, i16, i8*, %struct.XXTextureLevel, [1 x [15 x %struct.XXTextureLevel]] }
+ %struct.XXTransform = type <{ [24 x [16 x float]], [24 x [16 x float]], [16 x float], float, float, float, float, float, i8, i8, i8, i8, i32, i32, i32, i16, i16, i8, i8, i8, i8, i32 }>
+ %struct.XXTransformFeedback = type { i8, i8, i8, i8, [0 x i32], [16 x i32], [16 x i32] }
+ %struct.XXVertex = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.XXPointLineLimits, float, %struct.ZZIColor4, float, i8, i8, i8, i8, float, float, i32, i32, i32, i32, [4 x float], [2 x %struct.XXMaterial*], [2 x i32], [8 x %struct.ZZIColor4] }
+ %struct.XXVertexArrayRec = type opaque
+ %struct.XXVertexDescriptor = type { i8, i8, i8, i8, [0 x i32] }
+ %struct.XXVertexProgramLimits = type { i16, i16, i32, i32 }
+ %struct.XXViewport = type { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, double, double, i32, i32, i32, i32, float, float, float, float }
+ %struct.ZZGColorTable = type { i32, i32, i32, i8* }
+ %struct.ZZGOperation = type { i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, %struct.ZZGColorTable, %struct.ZZGColorTable, %struct.ZZGColorTable }
+ %struct.ZZGProcessor = type { void (%struct.XXPixelMode*, %struct.ZZGOperation*, %struct._ZZGProcessorData*, %union._ZZGFunctionKey*)*, %struct._YYFunction*, %union._ZZGFunctionKey*, %struct._ZZGProcessorData* }
+ %struct.ZZGTransformKey = type { i32, i32 }
+ %struct.ZZIColor4 = type { float, float, float, float }
+ %struct.ZZSBB = type { i8* }
+ %struct.ZZSDrawable = type { %struct.ZZSWindowRec* }
+ %struct.ZZSWindowRec = type { %struct.ZZGTransformKey, %struct.ZZGTransformKey, i32, i32, %struct.ZZSDrawable, i8*, i8*, i8*, i8*, i8*, [4 x i8*], i32, i16, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8, %struct.XXDrawableWindow, i32, i32, i8*, i8* }
+ %struct.ZZTCoord2 = type { float, float }
+ %struct.YYFPContext = type { float, i32, i32, i32, float, [3 x float] }
+ %struct.YYFragmentAttrib = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, [8 x <4 x float>] }
+ %struct.YYTextures = type { [16 x %struct.XXTextureRec*] }
+ %struct.PPStreamToken = type { { i16, i16, i32 } }
+ %struct._ZZGProcessorData = type { void (i8*, i8*, i32, i32, i32, i32, i32, i32, i32)*, void (i8*, i8*, i32, i32, i32, i32, i32, i32, i32)*, i8* (i32)*, void (i8*)* }
+ %struct._YYConstants = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, float, float, float, float, float, float, float, float, float, float, float, float, [256 x float], [4096 x i8], [8 x float], [48 x float], [128 x float], [528 x i8], { void (i8*, i8*, i32, i8*)*, float (float)*, float (float)*, float (float)*, i32 (float)* } }
+ %struct._YYFunction = type opaque
+ %struct.__ZZarrayelementDrawInfoListType = type { i32, [40 x i8] }
+ %union._ZZGFunctionKey = type opaque
[email protected] = appending global [1 x i8*] [ i8* bitcast (void (%struct.XXContextRec*, i32, i32, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, i32)* @t to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define void @t(%struct.XXContextRec* %ctx, i32 %x, i32 %y, %struct.YYFragmentAttrib* %start, %struct.YYFragmentAttrib* %deriv, i32 %num_frags) nounwind {
+entry:
+ %tmp7485.i.i.i = xor <4 x i32> zeroinitializer, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %tmp8382.i.i.i = extractelement <4 x i32> zeroinitializer, i32 1 ; <i32> [#uses=1]
+ %tmp8383.i.i.i = extractelement <4 x i32> zeroinitializer, i32 2 ; <i32> [#uses=2]
+ %tmp8384.i.i.i = extractelement <4 x i32> zeroinitializer, i32 3 ; <i32> [#uses=2]
+ br label %bb7551.i.i.i
+
+bb4426.i.i.i: ; preds = %bb7551.i.i.i
+ %0 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8383.i.i.i, i32 3 ; <[4 x i32]*> [#uses=1]
+ %1 = bitcast [4 x i32]* %0 to <4 x i32>* ; <<4 x i32>*> [#uses=1]
+ %2 = load <4 x i32>* %1, align 16 ; <<4 x i32>> [#uses=1]
+ %3 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8384.i.i.i, i32 3 ; <[4 x i32]*> [#uses=1]
+ %4 = bitcast [4 x i32]* %3 to <4 x i32>* ; <<4 x i32>*> [#uses=1]
+ %5 = load <4 x i32>* %4, align 16 ; <<4 x i32>> [#uses=1]
+ %6 = shufflevector <4 x i32> %2, <4 x i32> %5, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x i32>> [#uses=1]
+ %7 = bitcast <4 x i32> %6 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %8 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %7, <2 x i32> < i32 1, i32 3 > ; <<2 x i64>> [#uses=1]
+ %9 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8382.i.i.i, i32 6 ; <float**> [#uses=1]
+ %10 = load float** %9, align 4 ; <float*> [#uses=1]
+ %11 = bitcast float* %10 to i8* ; <i8*> [#uses=1]
+ %12 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8383.i.i.i, i32 6 ; <float**> [#uses=1]
+ %13 = load float** %12, align 4 ; <float*> [#uses=1]
+ %14 = bitcast float* %13 to i8* ; <i8*> [#uses=1]
+ %15 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8384.i.i.i, i32 6 ; <float**> [#uses=1]
+ %16 = load float** %15, align 4 ; <float*> [#uses=1]
+ %17 = bitcast float* %16 to i8* ; <i8*> [#uses=1]
+ %tmp7308.i.i.i = and <2 x i64> zeroinitializer, %8 ; <<2 x i64>> [#uses=1]
+ %18 = bitcast <2 x i64> %tmp7308.i.i.i to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %19 = mul <4 x i32> %18, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %20 = add <4 x i32> %19, zeroinitializer ; <<4 x i32>> [#uses=3]
+ %21 = load i32* null, align 4 ; <i32> [#uses=0]
+ %22 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> zeroinitializer) nounwind readnone ; <<4 x float>> [#uses=1]
+ %23 = fmul <4 x float> %22, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1]
+ %tmp2114.i119.i.i = extractelement <4 x i32> %20, i32 1 ; <i32> [#uses=1]
+ %24 = shl i32 %tmp2114.i119.i.i, 2 ; <i32> [#uses=1]
+ %25 = getelementptr i8* %11, i32 %24 ; <i8*> [#uses=1]
+ %26 = bitcast i8* %25 to i32* ; <i32*> [#uses=1]
+ %27 = load i32* %26, align 4 ; <i32> [#uses=1]
+ %28 = or i32 %27, -16777216 ; <i32> [#uses=1]
+ %tmp1927.i120.i.i = insertelement <4 x i32> undef, i32 %28, i32 0 ; <<4 x i32>> [#uses=1]
+ %29 = bitcast <4 x i32> %tmp1927.i120.i.i to <16 x i8> ; <<16 x i8>> [#uses=1]
+ %30 = shufflevector <16 x i8> %29, <16 x i8> < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef >, <16 x i32> < i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23 > ; <<16 x i8>> [#uses=1]
+ %31 = bitcast <16 x i8> %30 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %32 = shufflevector <8 x i16> %31, <8 x i16> < i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef >, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1]
+ %33 = bitcast <8 x i16> %32 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %34 = shufflevector <4 x i32> %33, <4 x i32> undef, <4 x i32> < i32 2, i32 1, i32 0, i32 3 > ; <<4 x i32>> [#uses=1]
+ %35 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %34) nounwind readnone ; <<4 x float>> [#uses=1]
+ %36 = fmul <4 x float> %35, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1]
+ %tmp2113.i124.i.i = extractelement <4 x i32> %20, i32 2 ; <i32> [#uses=1]
+ %37 = shl i32 %tmp2113.i124.i.i, 2 ; <i32> [#uses=1]
+ %38 = getelementptr i8* %14, i32 %37 ; <i8*> [#uses=1]
+ %39 = bitcast i8* %38 to i32* ; <i32*> [#uses=1]
+ %40 = load i32* %39, align 4 ; <i32> [#uses=1]
+ %41 = or i32 %40, -16777216 ; <i32> [#uses=1]
+ %tmp1963.i125.i.i = insertelement <4 x i32> undef, i32 %41, i32 0 ; <<4 x i32>> [#uses=1]
+ %42 = bitcast <4 x i32> %tmp1963.i125.i.i to <16 x i8> ; <<16 x i8>> [#uses=1]
+ %43 = shufflevector <16 x i8> %42, <16 x i8> < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef >, <16 x i32> < i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23 > ; <<16 x i8>> [#uses=1]
+ %44 = bitcast <16 x i8> %43 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %45 = shufflevector <8 x i16> %44, <8 x i16> < i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef >, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1]
+ %46 = bitcast <8 x i16> %45 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %47 = shufflevector <4 x i32> %46, <4 x i32> undef, <4 x i32> < i32 2, i32 1, i32 0, i32 3 > ; <<4 x i32>> [#uses=1]
+ %48 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %47) nounwind readnone ; <<4 x float>> [#uses=1]
+ %49 = fmul <4 x float> %48, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1]
+ %tmp2112.i129.i.i = extractelement <4 x i32> %20, i32 3 ; <i32> [#uses=1]
+ %50 = shl i32 %tmp2112.i129.i.i, 2 ; <i32> [#uses=1]
+ %51 = getelementptr i8* %17, i32 %50 ; <i8*> [#uses=1]
+ %52 = bitcast i8* %51 to i32* ; <i32*> [#uses=1]
+ %53 = load i32* %52, align 4 ; <i32> [#uses=1]
+ %54 = or i32 %53, -16777216 ; <i32> [#uses=1]
+ %tmp1999.i130.i.i = insertelement <4 x i32> undef, i32 %54, i32 0 ; <<4 x i32>> [#uses=1]
+ %55 = bitcast <4 x i32> %tmp1999.i130.i.i to <16 x i8> ; <<16 x i8>> [#uses=1]
+ %56 = shufflevector <16 x i8> %55, <16 x i8> < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef >, <16 x i32> < i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23 > ; <<16 x i8>> [#uses=1]
+ %57 = bitcast <16 x i8> %56 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %58 = shufflevector <8 x i16> %57, <8 x i16> < i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef >, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1]
+ %59 = bitcast <8 x i16> %58 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %60 = shufflevector <4 x i32> %59, <4 x i32> undef, <4 x i32> < i32 2, i32 1, i32 0, i32 3 > ; <<4 x i32>> [#uses=1]
+ %61 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %60) nounwind readnone ; <<4 x float>> [#uses=1]
+ %62 = fmul <4 x float> %61, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1]
+ %63 = fmul <4 x float> %23, zeroinitializer ; <<4 x float>> [#uses=1]
+ %64 = fadd <4 x float> zeroinitializer, %63 ; <<4 x float>> [#uses=1]
+ %65 = fmul <4 x float> %36, zeroinitializer ; <<4 x float>> [#uses=1]
+ %66 = fadd <4 x float> zeroinitializer, %65 ; <<4 x float>> [#uses=1]
+ %67 = fmul <4 x float> %49, zeroinitializer ; <<4 x float>> [#uses=1]
+ %68 = fadd <4 x float> zeroinitializer, %67 ; <<4 x float>> [#uses=1]
+ %69 = fmul <4 x float> %62, zeroinitializer ; <<4 x float>> [#uses=1]
+ %70 = fadd <4 x float> zeroinitializer, %69 ; <<4 x float>> [#uses=1]
+ %tmp7452.i.i.i = bitcast <4 x float> %64 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp7454.i.i.i = and <4 x i32> %tmp7452.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %tmp7459.i.i.i = or <4 x i32> %tmp7454.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %tmp7460.i.i.i = bitcast <4 x i32> %tmp7459.i.i.i to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp7468.i.i.i = bitcast <4 x float> %66 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp7470.i.i.i = and <4 x i32> %tmp7468.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %tmp7475.i.i.i = or <4 x i32> %tmp7470.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %tmp7476.i.i.i = bitcast <4 x i32> %tmp7475.i.i.i to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp7479.i.i.i = bitcast <4 x float> %.279.1.i to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp7480.i.i.i = and <4 x i32> zeroinitializer, %tmp7479.i.i.i ; <<4 x i32>> [#uses=1]
+ %tmp7484.i.i.i = bitcast <4 x float> %68 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp7486.i.i.i = and <4 x i32> %tmp7484.i.i.i, %tmp7485.i.i.i ; <<4 x i32>> [#uses=1]
+ %tmp7491.i.i.i = or <4 x i32> %tmp7486.i.i.i, %tmp7480.i.i.i ; <<4 x i32>> [#uses=1]
+ %tmp7492.i.i.i = bitcast <4 x i32> %tmp7491.i.i.i to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp7495.i.i.i = bitcast <4 x float> %.380.1.i to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp7496.i.i.i = and <4 x i32> zeroinitializer, %tmp7495.i.i.i ; <<4 x i32>> [#uses=1]
+ %tmp7500.i.i.i = bitcast <4 x float> %70 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp7502.i.i.i = and <4 x i32> %tmp7500.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %tmp7507.i.i.i = or <4 x i32> %tmp7502.i.i.i, %tmp7496.i.i.i ; <<4 x i32>> [#uses=1]
+ %tmp7508.i.i.i = bitcast <4 x i32> %tmp7507.i.i.i to <4 x float> ; <<4 x float>> [#uses=1]
+ %indvar.next.i.i.i = add i32 %aniso.0.i.i.i, 1 ; <i32> [#uses=1]
+ br label %bb7551.i.i.i
+
+bb7551.i.i.i: ; preds = %bb4426.i.i.i, %entry
+ %.077.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7460.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=0]
+ %.178.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7476.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=0]
+ %.279.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7492.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=1]
+ %.380.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7508.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=1]
+ %aniso.0.i.i.i = phi i32 [ 0, %entry ], [ %indvar.next.i.i.i, %bb4426.i.i.i ] ; <i32> [#uses=1]
+ br i1 false, label %glvmInterpretFPTransformFour6.exit, label %bb4426.i.i.i
+
+glvmInterpretFPTransformFour6.exit: ; preds = %bb7551.i.i.i
+ unreachable
+}
+
+declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
diff --git a/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll b/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll
new file mode 100644
index 0000000..e97b63d
--- /dev/null
+++ b/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu | grep ^.L_Z1fv.eh
+; RUN: llc < %s -march=x86 -mtriple=i686-unknown-linux-gnu | grep ^.L_Z1fv.eh
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin9 | grep ^__Z1fv.eh
+; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 | grep ^__Z1fv.eh
+
+define void @_Z1fv() {
+entry:
+ br label %return
+
+return:
+ ret void
+}
diff --git a/test/CodeGen/X86/2008-12-16-BadShift.ll b/test/CodeGen/X86/2008-12-16-BadShift.ll
new file mode 100644
index 0000000..6c70c5b
--- /dev/null
+++ b/test/CodeGen/X86/2008-12-16-BadShift.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s | not grep shrl
+; Note: this test is really trying to make sure that the shift
+; returns the right result; shrl is most likely wrong,
+; but if CodeGen starts legitimately using an shrl here,
+; please adjust the test appropriately.
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
[email protected] = internal constant [6 x i8] c"%lld\0A\00" ; <[6 x i8]*> [#uses=1]
+
+define i64 @mebbe_shift(i32 %xx, i32 %test) nounwind {
+entry:
+ %conv = zext i32 %xx to i64 ; <i64> [#uses=1]
+ %tobool = icmp ne i32 %test, 0 ; <i1> [#uses=1]
+ %shl = select i1 %tobool, i64 3, i64 0 ; <i64> [#uses=1]
+ %x.0 = shl i64 %conv, %shl ; <i64> [#uses=1]
+ ret i64 %x.0
+}
+
diff --git a/test/CodeGen/X86/2008-12-16-dagcombine-4.ll b/test/CodeGen/X86/2008-12-16-dagcombine-4.ll
new file mode 100644
index 0000000..3080d08
--- /dev/null
+++ b/test/CodeGen/X86/2008-12-16-dagcombine-4.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 | grep "(%esp)" | count 2
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.5"
+; a - a should be found and removed, leaving refs to only L and P
+define i32 @test(i32 %a, i32 %L, i32 %P) nounwind {
+entry:
+ %0 = sub i32 %a, %L
+ %1 = add i32 %P, %0
+ %2 = sub i32 %1, %a
+ br label %return
+
+return: ; preds = %bb3
+ ret i32 %2
+}
diff --git a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll
new file mode 100644
index 0000000..a6cabc4
--- /dev/null
+++ b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -asm-verbose=0 | FileCheck %s
+; PR3149
+; Make sure the copy after inline asm is not coalesced away.
+
+; CHECK: ## InlineAsm End
+; CHECK-NEXT: BB1_2:
+; CHECK-NEXT: movl %esi, %eax
+
+
+@"\01LC" = internal constant [7 x i8] c"n0=%d\0A\00" ; <[7 x i8]*> [#uses=1]
[email protected] = appending global [1 x i8*] [ i8* bitcast (i32 (i64, i64)* @umoddi3 to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define i32 @umoddi3(i64 %u, i64 %v) nounwind noinline {
+entry:
+ %0 = trunc i64 %v to i32 ; <i32> [#uses=2]
+ %1 = trunc i64 %u to i32 ; <i32> [#uses=4]
+ %2 = lshr i64 %u, 32 ; <i64> [#uses=1]
+ %3 = trunc i64 %2 to i32 ; <i32> [#uses=2]
+ %4 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([7 x i8]* @"\01LC", i32 0, i32 0), i32 %1) nounwind ; <i32> [#uses=0]
+ %5 = icmp ult i32 %1, %0 ; <i1> [#uses=1]
+ br i1 %5, label %bb2, label %bb
+
+bb: ; preds = %entry
+ %6 = lshr i64 %v, 32 ; <i64> [#uses=1]
+ %7 = trunc i64 %6 to i32 ; <i32> [#uses=1]
+ %asmtmp = tail call { i32, i32 } asm "subl $5,$1\0A\09sbbl $3,$0", "=r,=&r,0,imr,1,imr,~{dirflag},~{fpsr},~{flags}"(i32 %3, i32 %7, i32 %1, i32 %0) nounwind ; <{ i32, i32 }> [#uses=2]
+ %asmresult = extractvalue { i32, i32 } %asmtmp, 0 ; <i32> [#uses=1]
+ %asmresult1 = extractvalue { i32, i32 } %asmtmp, 1 ; <i32> [#uses=1]
+ br label %bb2
+
+bb2: ; preds = %bb, %entry
+ %n1.0 = phi i32 [ %asmresult, %bb ], [ %3, %entry ] ; <i32> [#uses=1]
+ %n0.0 = phi i32 [ %asmresult1, %bb ], [ %1, %entry ] ; <i32> [#uses=1]
+ %8 = add i32 %n0.0, %n1.0 ; <i32> [#uses=1]
+ ret i32 %8
+}
+
+declare i32 @printf(i8*, ...) nounwind
diff --git a/test/CodeGen/X86/2008-12-22-dagcombine-5.ll b/test/CodeGen/X86/2008-12-22-dagcombine-5.ll
new file mode 100644
index 0000000..75773e0
--- /dev/null
+++ b/test/CodeGen/X86/2008-12-22-dagcombine-5.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 | grep "(%esp)" | count 2
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.5"
+; -(-a) - a should be found and removed, leaving refs to only L and P
+define i32 @test(i32 %a, i32 %L, i32 %P) nounwind {
+entry:
+ %0 = sub i32 %L, %a
+ %1 = sub i32 %P, %0
+ %2 = sub i32 %1, %a
+ br label %return
+
+return: ; preds = %bb3
+ ret i32 %2
+}
diff --git a/test/CodeGen/X86/2008-12-23-crazy-address.ll b/test/CodeGen/X86/2008-12-23-crazy-address.ll
new file mode 100644
index 0000000..2edcaea
--- /dev/null
+++ b/test/CodeGen/X86/2008-12-23-crazy-address.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=x86 -relocation-model=static | grep {lea.*X.*esp} | count 2
+
+@X = external global [0 x i32]
+
+define void @foo() nounwind {
+entry:
+ %Y = alloca i32
+ call void @frob(i32* %Y) nounwind
+ %Y3 = bitcast i32* %Y to i8*
+ %ctg2 = getelementptr i8* %Y3, i32 ptrtoint ([0 x i32]* @X to i32)
+ %0 = ptrtoint i8* %ctg2 to i32
+ call void @borf(i32 %0) nounwind
+ ret void
+}
+
+define void @bar(i32 %i) nounwind {
+entry:
+ %Y = alloca [10 x i32]
+ %0 = getelementptr [10 x i32]* %Y, i32 0, i32 0
+ call void @frob(i32* %0) nounwind
+ %1 = getelementptr [0 x i32]* @X, i32 0, i32 %i
+ %2 = getelementptr [10 x i32]* %Y, i32 0, i32 0
+ %3 = ptrtoint i32* %2 to i32
+ %4 = bitcast i32* %1 to i8*
+ %ctg2 = getelementptr i8* %4, i32 %3
+ %5 = ptrtoint i8* %ctg2 to i32
+ call void @borf(i32 %5) nounwind
+ ret void
+}
+
+declare void @frob(i32*)
+
+declare void @borf(i32)
diff --git a/test/CodeGen/X86/2008-12-23-dagcombine-6.ll b/test/CodeGen/X86/2008-12-23-dagcombine-6.ll
new file mode 100644
index 0000000..bae9283
--- /dev/null
+++ b/test/CodeGen/X86/2008-12-23-dagcombine-6.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 | grep "(%esp)" | count 4
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.5"
+; a - a should be found and removed, leaving refs to only L and P
+define i32 @test(i32 %a, i32 %L, i32 %P) nounwind {
+entry:
+ %0 = add i32 %a, %L
+ %1 = add i32 %P, %0
+ %2 = sub i32 %1, %a
+ br label %return
+
+return: ; preds = %bb3
+ ret i32 %2
+}
+define i32 @test2(i32 %a, i32 %L, i32 %P) nounwind {
+entry:
+ %0 = add i32 %L, %a
+ %1 = add i32 %P, %0
+ %2 = sub i32 %1, %a
+ br label %return
+
+return: ; preds = %bb3
+ ret i32 %2
+}
diff --git a/test/CodeGen/X86/2009-01-12-CoalescerBug.ll b/test/CodeGen/X86/2009-01-12-CoalescerBug.ll
new file mode 100644
index 0000000..27a7113
--- /dev/null
+++ b/test/CodeGen/X86/2009-01-12-CoalescerBug.ll
@@ -0,0 +1,84 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | grep movq | count 2
+; PR3311
+
+ %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.VEC_basic_block_base = type { i32, i32, [1 x %struct.basic_block_def*] }
+ %struct.VEC_basic_block_gc = type { %struct.VEC_basic_block_base }
+ %struct.VEC_edge_base = type { i32, i32, [1 x %struct.edge_def*] }
+ %struct.VEC_edge_gc = type { %struct.VEC_edge_base }
+ %struct.VEC_rtx_base = type { i32, i32, [1 x %struct.rtx_def*] }
+ %struct.VEC_rtx_gc = type { %struct.VEC_rtx_base }
+ %struct.VEC_temp_slot_p_base = type { i32, i32, [1 x %struct.temp_slot*] }
+ %struct.VEC_temp_slot_p_gc = type { %struct.VEC_temp_slot_p_base }
+ %struct.VEC_tree_base = type { i32, i32, [1 x %struct.tree_node*] }
+ %struct.VEC_tree_gc = type { %struct.VEC_tree_base }
+ %struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
+ %struct.basic_block_def = type { %struct.tree_node*, %struct.VEC_edge_gc*, %struct.VEC_edge_gc*, i8*, %struct.loop*, [2 x %struct.et_node*], %struct.basic_block_def*, %struct.basic_block_def*, %struct.basic_block_il_dependent, %struct.tree_node*, %struct.edge_prediction*, i64, i32, i32, i32, i32 }
+ %struct.basic_block_il_dependent = type { %struct.rtl_bb_info* }
+ %struct.bitmap_element_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, [2 x i64] }
+ %struct.bitmap_head_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, %struct.bitmap_obstack* }
+ %struct.bitmap_obstack = type { %struct.bitmap_element_def*, %struct.bitmap_head_def*, %struct.obstack }
+ %struct.block_symbol = type { [3 x %struct.rtunion], %struct.object_block*, i64 }
+ %struct.c_arg_info = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i8 }
+ %struct.c_language_function = type { %struct.stmt_tree_s }
+ %struct.c_switch = type opaque
+ %struct.control_flow_graph = type { %struct.basic_block_def*, %struct.basic_block_def*, %struct.VEC_basic_block_gc*, i32, i32, i32, %struct.VEC_basic_block_gc*, i32 }
+ %struct.edge_def = type { %struct.basic_block_def*, %struct.basic_block_def*, %struct.edge_def_insns, i8*, %struct.location_t*, i32, i32, i64, i32 }
+ %struct.edge_def_insns = type { %struct.rtx_def* }
+ %struct.edge_prediction = type opaque
+ %struct.eh_status = type opaque
+ %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }
+ %struct.et_node = type opaque
+ %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+ %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.control_flow_graph*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.VEC_temp_slot_p_gc*, %struct.temp_slot*, %struct.var_refs_queue*, i32, i32, i32, i32, %struct.machine_function*, i32, i32, %struct.language_function*, %struct.htab*, %struct.rtx_def*, i32, i32, i32, %struct.location_t, %struct.VEC_tree_gc*, %struct.tree_node*, i8*, i8*, i8*, i8*, i8*, %struct.tree_node*, i8, i8, i8, i8, i8, i8 }
+ %struct.htab = type { i32 (i8*)*, i32 (i8*, i8*)*, void (i8*)*, i8**, i64, i64, i64, i32, i32, i8* (i64, i64)*, void (i8*)*, i8*, i8* (i8*, i64, i64)*, void (i8*, i8*)*, i32 }
+ %struct.initial_value_struct = type opaque
+ %struct.lang_decl = type { i8 }
+ %struct.language_function = type { %struct.c_language_function, %struct.tree_node*, %struct.tree_node*, %struct.c_switch*, %struct.c_arg_info*, i32, i32, i32, i32 }
+ %struct.location_t = type { i8*, i32 }
+ %struct.loop = type opaque
+ %struct.machine_function = type { %struct.stack_local_entry*, i8*, %struct.rtx_def*, i32, i32, [4 x i32], i32, i32, i32 }
+ %struct.object_block = type { %struct.section*, i32, i64, %struct.VEC_rtx_gc*, %struct.VEC_rtx_gc* }
+ %struct.obstack = type { i64, %struct._obstack_chunk*, i8*, i8*, i8*, i64, i32, %struct._obstack_chunk* (i8*, i64)*, void (i8*, %struct._obstack_chunk*)*, i8*, i8 }
+ %struct.omp_clause_subcode = type { i32 }
+ %struct.rtl_bb_info = type { %struct.rtx_def*, %struct.rtx_def*, %struct.bitmap_head_def*, %struct.bitmap_head_def*, %struct.rtx_def*, %struct.rtx_def*, i32 }
+ %struct.rtunion = type { i8* }
+ %struct.rtx_def = type { i16, i8, i8, %struct.u }
+ %struct.section = type { %struct.unnamed_section }
+ %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }
+ %struct.stack_local_entry = type opaque
+ %struct.stmt_tree_s = type { %struct.tree_node*, i32 }
+ %struct.temp_slot = type opaque
+ %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 }
+ %struct.tree_decl_common = type { %struct.tree_decl_minimal, %struct.tree_node*, i8, i8, i8, i8, i8, i32, i32, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_decl_minimal = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, %struct.tree_node* }
+ %struct.tree_decl_non_common = type { %struct.tree_decl_with_vis, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node* }
+ %struct.tree_decl_with_rtl = type { %struct.tree_decl_common, %struct.rtx_def*, i32 }
+ %struct.tree_decl_with_vis = type { %struct.tree_decl_with_rtl, %struct.tree_node*, %struct.tree_node*, i8, i8, i8, i8 }
+ %struct.tree_function_decl = type { %struct.tree_decl_non_common, i32, i8, i8, i64, %struct.function* }
+ %struct.tree_node = type { %struct.tree_function_decl }
+ %struct.u = type { %struct.block_symbol }
+ %struct.unnamed_section = type { %struct.omp_clause_subcode, void (i8*)*, i8*, %struct.section* }
+ %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+ %struct.varasm_status = type opaque
+ %union.tree_ann_d = type opaque
[email protected] = external constant [31 x i8] ; <[31 x i8]*> [#uses=1]
+@integer_types = external global [11 x %struct.tree_node*] ; <[11 x %struct.tree_node*]*> [#uses=1]
+@__FUNCTION__.31164 = external constant [23 x i8], align 16 ; <[23 x i8]*> [#uses=1]
[email protected] = appending global [1 x i8*] [ i8* bitcast (i32 (i32, i32)* @c_common_type_for_size to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define i32 @c_common_type_for_size(i32 %bits, i32 %unsignedp) nounwind {
+entry:
+ %0 = load %struct.tree_node** getelementptr ([11 x %struct.tree_node*]* @integer_types, i32 0, i64 5), align 8 ; <%struct.tree_node*> [#uses=1]
+ br i1 false, label %bb16, label %bb
+
+bb: ; preds = %entry
+ tail call void @tree_class_check_failed(%struct.tree_node* %0, i32 2, i8* getelementptr ([31 x i8]* @.str1, i32 0, i64 0), i32 1785, i8* getelementptr ([23 x i8]* @__FUNCTION__.31164, i32 0, i32 0)) noreturn nounwind
+ unreachable
+
+bb16: ; preds = %entry
+ %tmp = add i32 %bits, %unsignedp ; <i32> [#uses=1]
+ ret i32 %tmp
+}
+
+declare void @tree_class_check_failed(%struct.tree_node*, i32, i8*, i32, i8*) noreturn
diff --git a/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll b/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll
new file mode 100644
index 0000000..9c71469
--- /dev/null
+++ b/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx -enable-legalize-types-checking
+
+declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
+
+define void @__mindd16(<16 x double>* sret %vec.result, <16 x double> %x, double %y) nounwind {
+entry:
+ %tmp3.i = shufflevector <16 x double> zeroinitializer, <16 x double> undef, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 > ; <<8 x double>> [#uses=1]
+ %tmp10.i.i = shufflevector <8 x double> %tmp3.i, <8 x double> undef, <4 x i32> < i32 4, i32 5, i32 6, i32 7 > ; <<4 x double>> [#uses=1]
+ %tmp3.i2.i.i = shufflevector <4 x double> %tmp10.i.i, <4 x double> undef, <2 x i32> < i32 0, i32 1 > ; <<2 x double>> [#uses=1]
+ %0 = tail call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> zeroinitializer, <2 x double> %tmp3.i2.i.i) nounwind ; <<2 x double>> [#uses=1]
+ %tmp5.i3.i.i = shufflevector <2 x double> %0, <2 x double> undef, <4 x i32> < i32 0, i32 1, i32 undef, i32 undef > ; <<4 x double>> [#uses=1]
+ %tmp6.i4.i.i = shufflevector <4 x double> zeroinitializer, <4 x double> %tmp5.i3.i.i, <4 x i32> < i32 4, i32 5, i32 2, i32 3 > ; <<4 x double>> [#uses=1]
+ %tmp14.i8.i.i = shufflevector <4 x double> %tmp6.i4.i.i, <4 x double> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 4, i32 5 > ; <<4 x double>> [#uses=1]
+ %tmp13.i.i = shufflevector <4 x double> %tmp14.i8.i.i, <4 x double> undef, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef > ; <<8 x double>> [#uses=1]
+ %tmp14.i.i = shufflevector <8 x double> zeroinitializer, <8 x double> %tmp13.i.i, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11 > ; <<8 x double>> [#uses=1]
+ %tmp5.i = shufflevector <8 x double> %tmp14.i.i, <8 x double> undef, <16 x i32> < i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef > ; <<16 x double>> [#uses=1]
+ %tmp6.i = shufflevector <16 x double> %x, <16 x double> %tmp5.i, <16 x i32> < i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15 > ; <<16 x double>> [#uses=1]
+ %tmp14.i = shufflevector <16 x double> %tmp6.i, <16 x double> zeroinitializer, <16 x i32> < i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23 > ; <<16 x double>> [#uses=1]
+ store <16 x double> %tmp14.i, <16 x double>* %vec.result
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-01-16-SchedulerBug.ll b/test/CodeGen/X86/2009-01-16-SchedulerBug.ll
new file mode 100644
index 0000000..99bef6c
--- /dev/null
+++ b/test/CodeGen/X86/2009-01-16-SchedulerBug.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin
+; rdar://6501631
+
+ %CF = type { %Register }
+ %XXV = type { i32 (...)** }
+ %Register = type { %"struct.XXC::BCFs", i32 }
+ %"struct.XXC::BCFs" = type { i32 }
+
+declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) nounwind
+
+define fastcc %XXV* @bar(%CF* %call_frame, %XXV** %exception) nounwind {
+prologue:
+ %param_x = load %XXV** null ; <%XXV*> [#uses=1]
+ %unique_1.i = ptrtoint %XXV* %param_x to i1 ; <i1> [#uses=1]
+ br i1 %unique_1.i, label %NextVerify42, label %FailedVerify
+
+NextVerify42: ; preds = %prologue
+ %param_y = load %XXV** null ; <%XXV*> [#uses=1]
+ %unique_1.i58 = ptrtoint %XXV* %param_y to i1 ; <i1> [#uses=1]
+ br i1 %unique_1.i58, label %function_setup.cont, label %FailedVerify
+
+function_setup.cont: ; preds = %NextVerify42
+ br i1 false, label %label13, label %label
+
+label: ; preds = %function_setup.cont
+ %has_exn = icmp eq %XXV* null, null ; <i1> [#uses=1]
+ br i1 %has_exn, label %kjsNumberLiteral.exit, label %handle_exception
+
+kjsNumberLiteral.exit: ; preds = %label
+ %0 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 0, i32 0) ; <{ i32, i1 }> [#uses=2]
+ %intAdd = extractvalue { i32, i1 } %0, 0 ; <i32> [#uses=2]
+ %intAddOverflow = extractvalue { i32, i1 } %0, 1 ; <i1> [#uses=1]
+ %toint56 = ashr i32 %intAdd, 1 ; <i32> [#uses=1]
+ %toFP57 = sitofp i32 %toint56 to double ; <double> [#uses=1]
+ br i1 %intAddOverflow, label %rematerializeAdd, label %label13
+
+label13: ; preds = %kjsNumberLiteral.exit, %function_setup.cont
+ %var_lr1.0 = phi double [ %toFP57, %kjsNumberLiteral.exit ], [ 0.000000e+00, %function_setup.cont ] ; <double> [#uses=0]
+ unreachable
+
+FailedVerify: ; preds = %NextVerify42, %prologue
+ ret %XXV* null
+
+rematerializeAdd: ; preds = %kjsNumberLiteral.exit
+ %rematerializedInt = sub i32 %intAdd, 0 ; <i32> [#uses=0]
+ ret %XXV* null
+
+handle_exception: ; preds = %label
+ ret %XXV* undef
+}
diff --git a/test/CodeGen/X86/2009-01-16-UIntToFP.ll b/test/CodeGen/X86/2009-01-16-UIntToFP.ll
new file mode 100644
index 0000000..2eab5f1
--- /dev/null
+++ b/test/CodeGen/X86/2009-01-16-UIntToFP.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=x86
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+
+define hidden float @__floatundisf(i64 %u) nounwind readnone {
+entry:
+ %0 = icmp ugt i64 %u, 9007199254740991 ; <i1> [#uses=1]
+ br i1 %0, label %bb, label %bb2
+
+bb: ; preds = %entry
+ %1 = and i64 %u, 2047 ; <i64> [#uses=1]
+ %2 = icmp eq i64 %1, 0 ; <i1> [#uses=1]
+ br i1 %2, label %bb2, label %bb1
+
+bb1: ; preds = %bb
+ %3 = or i64 %u, 2048 ; <i64> [#uses=1]
+ %4 = and i64 %3, -2048 ; <i64> [#uses=1]
+ br label %bb2
+
+bb2: ; preds = %bb1, %bb, %entry
+ %u_addr.0 = phi i64 [ %4, %bb1 ], [ %u, %entry ], [ %u, %bb ] ; <i64> [#uses=2]
+ %5 = lshr i64 %u_addr.0, 32 ; <i64> [#uses=1]
+ %6 = trunc i64 %5 to i32 ; <i32> [#uses=1]
+ %7 = uitofp i32 %6 to double ; <double> [#uses=1]
+ %8 = fmul double %7, 0x41F0000000000000 ; <double> [#uses=1]
+ %9 = trunc i64 %u_addr.0 to i32 ; <i32> [#uses=1]
+ %10 = uitofp i32 %9 to double ; <double> [#uses=1]
+ %11 = fadd double %10, %8 ; <double> [#uses=1]
+ %12 = fptrunc double %11 to float ; <float> [#uses=1]
+ ret float %12
+}
diff --git a/test/CodeGen/X86/2009-01-18-ConstantExprCrash.ll b/test/CodeGen/X86/2009-01-18-ConstantExprCrash.ll
new file mode 100644
index 0000000..f895336
--- /dev/null
+++ b/test/CodeGen/X86/2009-01-18-ConstantExprCrash.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s
+; rdar://6505632
+; reduced from 483.xalancbmk
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin7"
+ %"struct.std::basic_ostream<char,std::char_traits<char> >.base" = type { i32 (...)** }
+ %"struct.xercesc_2_5::ASCIIRangeFactory" = type { %"struct.std::basic_ostream<char,std::char_traits<char> >.base", i8, i8 }
+@_ZN11xercesc_2_5L17gIdeographicCharsE = external constant [7 x i16] ; <[7 x i16]*> [#uses=3]
+
+define void @_ZN11xercesc_2_515XMLRangeFactory11buildRangesEv(%"struct.xercesc_2_5::ASCIIRangeFactory"* %this) {
+entry:
+ br i1 false, label %bb5, label %return
+
+bb5: ; preds = %entry
+ br label %bb4.i.i
+
+bb4.i.i: ; preds = %bb4.i.i, %bb5
+ br i1 false, label %bb.i51, label %bb4.i.i
+
+bb.i51: ; preds = %bb.i51, %bb4.i.i
+ br i1 false, label %bb4.i.i70, label %bb.i51
+
+bb4.i.i70: ; preds = %bb4.i.i70, %bb.i51
+ br i1 false, label %_ZN11xercesc_2_59XMLString9stringLenEPKt.exit.i73, label %bb4.i.i70
+
+_ZN11xercesc_2_59XMLString9stringLenEPKt.exit.i73: ; preds = %bb4.i.i70
+ %0 = load i16* getelementptr ([7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE, i32 0, i32 add (i32 ashr (i32 sub (i32 ptrtoint (i16* getelementptr ([7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE, i32 0, i32 4) to i32), i32 ptrtoint ([7 x i16]* @_ZN11xercesc_2_5L17gIdeographicCharsE to i32)), i32 1), i32 1)), align 4 ; <i16> [#uses=0]
+ br label %bb4.i5.i141
+
+bb4.i5.i141: ; preds = %bb4.i5.i141, %_ZN11xercesc_2_59XMLString9stringLenEPKt.exit.i73
+ br label %bb4.i5.i141
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-01-25-NoSSE.ll b/test/CodeGen/X86/2009-01-25-NoSSE.ll
new file mode 100644
index 0000000..0583ef1
--- /dev/null
+++ b/test/CodeGen/X86/2009-01-25-NoSSE.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86-64 -mattr=-sse,-sse2 | not grep xmm
+; PR3402
+target datalayout =
+"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+ %struct.ktermios = type { i32, i32, i32, i32, i8, [19 x i8], i32, i32 }
+
+define void @foo() nounwind {
+entry:
+ %termios = alloca %struct.ktermios, align 8
+ %termios1 = bitcast %struct.ktermios* %termios to i8*
+ call void @llvm.memset.i64(i8* %termios1, i8 0, i64 44, i32 8)
+ call void @bar(%struct.ktermios* %termios) nounwind
+ ret void
+}
+
+declare void @llvm.memset.i64(i8* nocapture, i8, i64, i32) nounwind
+
+declare void @bar(%struct.ktermios*)
+
diff --git a/test/CodeGen/X86/2009-01-26-WrongCheck.ll b/test/CodeGen/X86/2009-01-26-WrongCheck.ll
new file mode 100644
index 0000000..117ff47
--- /dev/null
+++ b/test/CodeGen/X86/2009-01-26-WrongCheck.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86 -enable-legalize-types-checking
+; PR3393
+
+define void @foo(i32 inreg %x) {
+ %t709 = select i1 false, i32 0, i32 %x ; <i32> [#uses=1]
+ %t711 = add i32 %t709, 1 ; <i32> [#uses=4]
+ %t801 = icmp slt i32 %t711, 0 ; <i1> [#uses=1]
+ %t712 = zext i32 %t711 to i64 ; <i64> [#uses=1]
+ %t804 = select i1 %t801, i64 0, i64 %t712 ; <i64> [#uses=1]
+ store i64 %t804, i64* null
+ %t815 = icmp slt i32 %t711, 0 ; <i1> [#uses=1]
+ %t814 = sext i32 %t711 to i64 ; <i64> [#uses=1]
+ %t816 = select i1 %t815, i64 0, i64 %t814 ; <i64> [#uses=1]
+ store i64 %t816, i64* null
+ unreachable
+}
diff --git a/test/CodeGen/X86/2009-01-27-NullStrings.ll b/test/CodeGen/X86/2009-01-27-NullStrings.ll
new file mode 100644
index 0000000..8684f4a
--- /dev/null
+++ b/test/CodeGen/X86/2009-01-27-NullStrings.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin | FileCheck %s
+; CHECK: .section __TEXT,__cstring,cstring_literals
+
+@x = internal constant [1 x i8] zeroinitializer ; <[1 x i8]*> [#uses=1]
+
+@y = global [1 x i8]* @x
+
diff --git a/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll b/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll
new file mode 100644
index 0000000..ce3ea82
--- /dev/null
+++ b/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin9.6 -regalloc=local -disable-fp-elim
+; rdar://6538384
+
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.Lit = type { i32 }
+ %struct.StreamBuffer = type { %struct.FILE*, [1048576 x i8], i32, i32 }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+
+declare fastcc i32 @_Z8parseIntI12StreamBufferEiRT_(%struct.StreamBuffer*)
+
+declare i8* @llvm.eh.exception() nounwind
+
+define i32 @main(i32 %argc, i8** nocapture %argv) noreturn {
+entry:
+ %0 = invoke fastcc i32 @_Z8parseIntI12StreamBufferEiRT_(%struct.StreamBuffer* null)
+ to label %bb1.i16.i.i unwind label %lpad.i.i ; <i32> [#uses=0]
+
+bb1.i16.i.i: ; preds = %entry
+ br i1 false, label %bb.i.i.i.i, label %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i
+
+bb.i.i.i.i: ; preds = %bb1.i16.i.i
+ br label %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i
+
+_ZN3vecI3LitE4pushERKS0_.exit.i.i.i: ; preds = %bb.i.i.i.i, %bb1.i16.i.i
+ %lits.i.i.0.0 = phi %struct.Lit* [ null, %bb1.i16.i.i ], [ null, %bb.i.i.i.i ] ; <%struct.Lit*> [#uses=1]
+ %1 = invoke fastcc i32 @_Z8parseIntI12StreamBufferEiRT_(%struct.StreamBuffer* null)
+ to label %.noexc21.i.i unwind label %lpad.i.i ; <i32> [#uses=0]
+
+.noexc21.i.i: ; preds = %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i
+ unreachable
+
+lpad.i.i: ; preds = %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i, %entry
+ %lits.i.i.0.3 = phi %struct.Lit* [ %lits.i.i.0.0, %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i ], [ null, %entry ] ; <%struct.Lit*> [#uses=1]
+ %eh_ptr.i.i = call i8* @llvm.eh.exception() ; <i8*> [#uses=0]
+ free %struct.Lit* %lits.i.i.0.3
+ unreachable
+}
diff --git a/test/CodeGen/X86/2009-01-31-BigShift.ll b/test/CodeGen/X86/2009-01-31-BigShift.ll
new file mode 100644
index 0000000..4eb0ec1
--- /dev/null
+++ b/test/CodeGen/X86/2009-01-31-BigShift.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 | not grep and
+; PR3401
+
+define void @x(i288 %i) nounwind {
+ call void @add(i288 %i)
+ ret void
+}
+
+declare void @add(i288)
diff --git a/test/CodeGen/X86/2009-01-31-BigShift2.ll b/test/CodeGen/X86/2009-01-31-BigShift2.ll
new file mode 100644
index 0000000..9d24084
--- /dev/null
+++ b/test/CodeGen/X86/2009-01-31-BigShift2.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 | grep {mov.*56}
+; PR3449
+
+define void @test(<8 x double>* %P, i64* %Q) nounwind {
+ %A = load <8 x double>* %P ; <<8 x double>> [#uses=1]
+ %B = bitcast <8 x double> %A to i512 ; <i512> [#uses=1]
+ %C = lshr i512 %B, 448 ; <i512> [#uses=1]
+ %D = trunc i512 %C to i64 ; <i64> [#uses=1]
+ volatile store i64 %D, i64* %Q
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-01-31-BigShift3.ll b/test/CodeGen/X86/2009-01-31-BigShift3.ll
new file mode 100644
index 0000000..1b531e3
--- /dev/null
+++ b/test/CodeGen/X86/2009-01-31-BigShift3.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=x86
+; PR3450
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin7"
+ %struct.BitMap = type { i8* }
+ %struct.BitMapListStruct = type { %struct.BitMap, %struct.BitMapListStruct*, %struct.BitMapListStruct* }
+ %struct.Material = type { float, float, float, %struct.Material*, %struct.Material* }
+ %struct.ObjPoint = type { double, double, double, double, double, double }
+ %struct.ObjectStruct = type { [57 x i8], %struct.PointListStruct*, %struct.Poly3Struct*, %struct.Poly4Struct*, %struct.Texture*, %struct.Material*, %struct.Point, i32, i32, %struct.Point, %struct.Point, %struct.Point, %struct.ObjectStruct*, %struct.ObjectStruct*, i32, i32, i32, i32, i32, i32, i32, %struct.ObjectStruct*, %struct.ObjectStruct* }
+ %struct.Point = type { double, double, double }
+ %struct.PointListStruct = type { %struct.ObjPoint*, %struct.PointListStruct*, %struct.PointListStruct* }
+ %struct.Poly3Struct = type { [3 x %struct.ObjPoint*], %struct.Material*, %struct.Texture*, %struct.Poly3Struct*, %struct.Poly3Struct* }
+ %struct.Poly4Struct = type { [4 x %struct.ObjPoint*], %struct.Material*, %struct.Texture*, %struct.Poly4Struct*, %struct.Poly4Struct* }
+ %struct.Texture = type { %struct.Point, %struct.BitMapListStruct*, %struct.Point, %struct.Point, %struct.Point, %struct.Texture*, %struct.Texture* }
+
+define fastcc void @ScaleObjectAdd(%struct.ObjectStruct* %o, double %sx, double %sy, double %sz) nounwind {
+entry:
+ %sz101112.ins = or i960 0, 0 ; <i960> [#uses=1]
+ br i1 false, label %return, label %bb1.preheader
+
+bb1.preheader: ; preds = %entry
+ %0 = lshr i960 %sz101112.ins, 640 ; <i960> [#uses=0]
+ br label %bb1
+
+bb1: ; preds = %bb1, %bb1.preheader
+ br label %bb1
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-02-01-LargeMask.ll b/test/CodeGen/X86/2009-02-01-LargeMask.ll
new file mode 100644
index 0000000..c4042e6
--- /dev/null
+++ b/test/CodeGen/X86/2009-02-01-LargeMask.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=x86
+; PR3453
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+ %struct.cl_engine = type { i32, i16, i32, i8**, i8**, i8*, i8*, i8*, i8*, i8*, i8*, i8* }
+ %struct.cl_limits = type { i32, i32, i32, i32, i16, i32 }
+ %struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* }
+ %struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* }
+ %struct.cli_ac_patt = type { i16*, i16*, i16, i16, i8, i32, i32, i8*, i8*, i32, i16, i16, i16, i16, %struct.cli_ac_alt**, i8, i16, %struct.cli_ac_patt*, %struct.cli_ac_patt* }
+ %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 }
+ %struct.cli_ctx = type { i8**, i32*, %struct.cli_matcher*, %struct.cl_engine*, %struct.cl_limits*, i32, i32, i32, i32, %struct.cli_dconf* }
+ %struct.cli_dconf = type { i32, i32, i32, i32, i32, i32, i32 }
+ %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 }
+
+define fastcc i32 @cli_scanautoit(i32 %desc, %struct.cli_ctx* %ctx, i32 %offset) nounwind {
+entry:
+ br i1 false, label %bb.i49.i72, label %bb14
+
+bb.i49.i72: ; preds = %bb.i49.i72, %entry
+ %UNP.i1482.0 = phi i288 [ %.ins659, %bb.i49.i72 ], [ undef, %entry ] ; <i288> [#uses=1]
+ %0 = load i32* null, align 4 ; <i32> [#uses=1]
+ %1 = xor i32 %0, 17834 ; <i32> [#uses=1]
+ %2 = zext i32 %1 to i288 ; <i288> [#uses=1]
+ %3 = shl i288 %2, 160 ; <i288> [#uses=1]
+ %UNP.i1482.in658.mask = and i288 %UNP.i1482.0, -6277101733925179126504886505003981583386072424808101969921 ; <i288> [#uses=1]
+ %.ins659 = or i288 %3, %UNP.i1482.in658.mask ; <i288> [#uses=1]
+ br label %bb.i49.i72
+
+bb14: ; preds = %entry
+ ret i32 -123
+}
diff --git a/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll b/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll
new file mode 100644
index 0000000..e75af13
--- /dev/null
+++ b/test/CodeGen/X86/2009-02-03-AnalyzedTwice.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=x86
+; PR3411
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+@g_3 = external global i32 ; <i32*> [#uses=1]
+
+define void @bar(i64 %p_66) nounwind {
+entry:
+ br i1 false, label %bb, label %bb1
+
+bb: ; preds = %entry
+ unreachable
+
+bb1: ; preds = %entry
+ %0 = load i32* @g_3, align 4 ; <i32> [#uses=2]
+ %1 = sext i32 %0 to i64 ; <i64> [#uses=1]
+ %2 = or i64 %1, %p_66 ; <i64> [#uses=1]
+ %3 = shl i64 %2, 0 ; <i64> [#uses=1]
+ %4 = and i64 %3, %p_66 ; <i64> [#uses=1]
+ %5 = icmp eq i64 %4, 1 ; <i1> [#uses=1]
+ %6 = trunc i64 %p_66 to i32 ; <i32> [#uses=2]
+ %7 = or i32 %0, %6 ; <i32> [#uses=2]
+ %8 = sub i32 %7, %6 ; <i32> [#uses=1]
+ %iftmp.0.0 = select i1 %5, i32 %8, i32 %7 ; <i32> [#uses=1]
+ %9 = tail call i32 @foo(i32 %iftmp.0.0) nounwind ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @foo(i32)
diff --git a/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll b/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll
new file mode 100644
index 0000000..4880f62
--- /dev/null
+++ b/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s | grep p-92
+; PR3481
+; The offset should print as -92, not +17179869092
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+@p = common global [10 x i32] zeroinitializer, align 4 ; <[10 x i32]*>
+@g = global [1 x i32*] [ i32* bitcast (i8* getelementptr (i8* bitcast
+([10 x i32]* @p to i8*), i64 17179869092) to i32*) ], align 4
diff --git a/test/CodeGen/X86/2009-02-05-CoalescerBug.ll b/test/CodeGen/X86/2009-02-05-CoalescerBug.ll
new file mode 100644
index 0000000..0ffa8fd
--- /dev/null
+++ b/test/CodeGen/X86/2009-02-05-CoalescerBug.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movss | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movaps | count 4
+
+define i1 @t([2 x float]* %y, [2 x float]* %w, i32, [2 x float]* %x.pn59, i32 %smax190, i32 %j.1180, <4 x float> %wu.2179, <4 x float> %wr.2178, <4 x float>* %tmp89.out, <4 x float>* %tmp107.out, i32* %indvar.next218.out) nounwind {
+newFuncRoot:
+ %tmp82 = insertelement <4 x float> %wr.2178, float 0.000000e+00, i32 0 ; <<4 x float>> [#uses=1]
+ %tmp85 = insertelement <4 x float> %tmp82, float 0.000000e+00, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp87 = insertelement <4 x float> %tmp85, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp89 = insertelement <4 x float> %tmp87, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp89, <4 x float>* %tmp89.out
+ ret i1 false
+}
diff --git a/test/CodeGen/X86/2009-02-08-CoalescerBug.ll b/test/CodeGen/X86/2009-02-08-CoalescerBug.ll
new file mode 100644
index 0000000..908cc08
--- /dev/null
+++ b/test/CodeGen/X86/2009-02-08-CoalescerBug.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=x86
+; PR3486
+
+define i32 @foo(i8 signext %p_26) nounwind {
+entry:
+ %0 = icmp eq i8 %p_26, 0 ; <i1> [#uses=2]
+ %or.cond = or i1 false, %0 ; <i1> [#uses=2]
+ %iftmp.1.0 = zext i1 %or.cond to i16 ; <i16> [#uses=1]
+ br i1 %0, label %bb.i, label %bar.exit
+
+bb.i: ; preds = %entry
+ %1 = zext i1 %or.cond to i32 ; <i32> [#uses=1]
+ %2 = sdiv i32 %1, 0 ; <i32> [#uses=1]
+ %3 = trunc i32 %2 to i16 ; <i16> [#uses=1]
+ br label %bar.exit
+
+bar.exit: ; preds = %bb.i, %entry
+ %4 = phi i16 [ %3, %bb.i ], [ %iftmp.1.0, %entry ] ; <i16> [#uses=1]
+ %5 = trunc i16 %4 to i8 ; <i8> [#uses=1]
+ %6 = sext i8 %5 to i32 ; <i32> [#uses=1]
+ ret i32 %6
+}
diff --git a/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll b/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll
new file mode 100644
index 0000000..1284b0d
--- /dev/null
+++ b/test/CodeGen/X86/2009-02-11-codegenprepare-reuse.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s
+; PR3537
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.6"
+ %struct.GetBitContext = type <{ i8*, i8*, i32, i32 }>
+
+define i32 @alac_decode_frame() nounwind {
+entry:
+ %tmp2 = load i8** null ; <i8*> [#uses=2]
+ %tmp34 = getelementptr i8* %tmp2, i32 4 ; <i8*> [#uses=2]
+ %tmp5.i424 = bitcast i8* %tmp34 to i8** ; <i8**> [#uses=2]
+ %tmp15.i = getelementptr i8* %tmp2, i32 12 ; <i8*> [#uses=1]
+ %0 = bitcast i8* %tmp15.i to i32* ; <i32*> [#uses=1]
+ br i1 false, label %if.then43, label %if.end47
+
+if.then43: ; preds = %entry
+ ret i32 0
+
+if.end47: ; preds = %entry
+ %tmp5.i590 = load i8** %tmp5.i424 ; <i8*> [#uses=0]
+ store i32 19, i32* %0
+ %tmp6.i569 = load i8** %tmp5.i424 ; <i8*> [#uses=0]
+ %1 = call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 0) nounwind ; <i32> [#uses=0]
+ br i1 false, label %bb.nph, label %if.then63
+
+if.then63: ; preds = %if.end47
+ unreachable
+
+bb.nph: ; preds = %if.end47
+ %2 = bitcast i8* %tmp34 to %struct.GetBitContext* ; <%struct.GetBitContext*> [#uses=1]
+ %call9.i = call fastcc i32 @decode_scalar(%struct.GetBitContext* %2, i32 0, i32 0, i32 0) nounwind ; <i32> [#uses=0]
+ unreachable
+}
+
+declare fastcc i32 @decode_scalar(%struct.GetBitContext* nocapture, i32, i32, i32) nounwind
diff --git a/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll b/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll
new file mode 100644
index 0000000..72c7ee9
--- /dev/null
+++ b/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll
@@ -0,0 +1,76 @@
+; RUN: llc < %s
+; RUN: llc < %s -march=x86-64
+; PR3538
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9"
+ %llvm.dbg.anchor.type = type { i32, i32 }
+ %llvm.dbg.basictype.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, i32 }
+ %llvm.dbg.block.type = type { i32, { }* }
+ %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* }
+ %llvm.dbg.composite.type = type { i32, { }*, i8*, { }*, i32, i64, i64, i64, i32, { }*, { }* }
+ %llvm.dbg.subprogram.type = type { i32, { }*, { }*, i8*, i8*, i8*, { }*, i32, { }*, i1, i1 }
+ %llvm.dbg.subrange.type = type { i32, i64, i64 }
+ %llvm.dbg.variable.type = type { i32, { }*, i8*, { }*, i32, { }* }
[email protected]_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1]
[email protected] = internal constant [4 x i8] c"t.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1]
[email protected] = internal constant [2 x i8] c".\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1]
[email protected] = internal constant [6 x i8] c"clang\00", section "llvm.metadata" ; <[6 x i8]*> [#uses=1]
[email protected]_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([2 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([6 x i8]* @.str2, i32 0, i32 0), i1 false, i1 false, i8* null }, section "llvm.metadata" ; <%llvm.dbg.compile_unit.type*> [#uses=1]
[email protected] = internal constant [4 x i8] c"int\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1]
[email protected] = internal constant %llvm.dbg.basictype.type { i32 458788, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([4 x i8]* @.str3, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 0, i64 32, i64 32, i64 0, i32 0, i32 5 }, section "llvm.metadata" ; <%llvm.dbg.basictype.type*> [#uses=1]
[email protected] = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 46 }, section "llvm.metadata" ; <%llvm.dbg.anchor.type*> [#uses=1]
[email protected] = internal constant [5 x i8] c"test\00", section "llvm.metadata" ; <[5 x i8]*> [#uses=1]
[email protected] = internal constant %llvm.dbg.subprogram.type { i32 458798, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.subprograms to { }*), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* getelementptr ([5 x i8]* @.str4, i32 0, i32 0), i8* getelementptr ([5 x i8]* @.str4, i32 0, i32 0), i8* null, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 3, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), i1 false, i1 true }, section "llvm.metadata" ; <%llvm.dbg.subprogram.type*> [#uses=1]
[email protected] = internal constant [2 x i8] c"X\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1]
[email protected] = internal constant %llvm.dbg.variable.type { i32 459009, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*), i8* getelementptr ([2 x i8]* @.str5, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 3, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1]
[email protected] = internal constant %llvm.dbg.block.type { i32 458763, { }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*) }, section "llvm.metadata" ; <%llvm.dbg.block.type*> [#uses=1]
[email protected] = internal constant %llvm.dbg.subrange.type { i32 458785, i64 0, i64 0 }, section "llvm.metadata" ; <%llvm.dbg.subrange.type*> [#uses=1]
[email protected] = internal constant [1 x { }*] [{ }* bitcast (%llvm.dbg.subrange.type* @llvm.dbg.subrange to { }*)], section "llvm.metadata" ; <[1 x { }*]*> [#uses=1]
[email protected] = internal constant %llvm.dbg.composite.type { i32 458753, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i8* null, { }* null, i32 0, i64 0, i64 32, i64 0, i32 0, { }* bitcast (%llvm.dbg.basictype.type* @llvm.dbg.basictype to { }*), { }* bitcast ([1 x { }*]* @llvm.dbg.array to { }*) }, section "llvm.metadata" ; <%llvm.dbg.composite.type*> [#uses=1]
[email protected] = internal constant [2 x i8] c"Y\00", section "llvm.metadata" ; <[2 x i8]*> [#uses=1]
[email protected] = internal constant %llvm.dbg.variable.type { i32 459008, { }* bitcast (%llvm.dbg.block.type* @llvm.dbg.block to { }*), i8* getelementptr ([2 x i8]* @.str6, i32 0, i32 0), { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*), i32 4, { }* bitcast (%llvm.dbg.composite.type* @llvm.dbg.composite to { }*) }, section "llvm.metadata" ; <%llvm.dbg.variable.type*> [#uses=1]
+
+define i32 @test(i32 %X) nounwind {
+entry:
+ %retval = alloca i32 ; <i32*> [#uses=1]
+ %X.addr = alloca i32 ; <i32*> [#uses=3]
+ %saved_stack = alloca i8* ; <i8**> [#uses=2]
+ call void @llvm.dbg.func.start({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*))
+ store i32 %X, i32* %X.addr
+ %0 = bitcast i32* %X.addr to { }* ; <{ }*> [#uses=1]
+ call void @llvm.dbg.declare({ }* %0, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable to { }*))
+ call void @llvm.dbg.region.start({ }* bitcast (%llvm.dbg.block.type* @llvm.dbg.block to { }*))
+ call void @llvm.dbg.stoppoint(i32 4, i32 3, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*))
+ %1 = call i8* @llvm.stacksave() ; <i8*> [#uses=1]
+ store i8* %1, i8** %saved_stack
+ %tmp = load i32* %X.addr ; <i32> [#uses=1]
+ %2 = mul i32 4, %tmp ; <i32> [#uses=1]
+ %vla = alloca i8, i32 %2 ; <i8*> [#uses=1]
+ %tmp1 = bitcast i8* %vla to i32* ; <i32*> [#uses=1]
+ %3 = bitcast i32* %tmp1 to { }* ; <{ }*> [#uses=1]
+ call void @llvm.dbg.declare({ }* %3, { }* bitcast (%llvm.dbg.variable.type* @llvm.dbg.variable7 to { }*))
+ call void @llvm.dbg.stoppoint(i32 5, i32 1, { }* bitcast (%llvm.dbg.compile_unit.type* @llvm.dbg.compile_unit to { }*))
+ call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.block.type* @llvm.dbg.block to { }*))
+ br label %cleanup
+
+cleanup: ; preds = %entry
+ %tmp2 = load i8** %saved_stack ; <i8*> [#uses=1]
+ call void @llvm.stackrestore(i8* %tmp2)
+ call void @llvm.dbg.region.end({ }* bitcast (%llvm.dbg.subprogram.type* @llvm.dbg.subprogram to { }*))
+ %4 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %4
+}
+
+declare void @llvm.dbg.func.start({ }*) nounwind
+
+declare void @llvm.dbg.declare({ }*, { }*) nounwind
+
+declare void @llvm.dbg.region.start({ }*) nounwind
+
+declare void @llvm.dbg.stoppoint(i32, i32, { }*) nounwind
+
+declare i8* @llvm.stacksave() nounwind
+
+declare void @llvm.stackrestore(i8*) nounwind
+
+declare void @llvm.dbg.region.end({ }*) nounwind
diff --git a/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll b/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
new file mode 100644
index 0000000..2e148ad
--- /dev/null
+++ b/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 | grep {\$-81920} | count 3
+; RUN: llc < %s -march=x86 | grep {\$4294885376} | count 1
+
+; ModuleID = 'shant.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.6"
+
+define void @f() nounwind {
+entry:
+ call void asm sideeffect "foo $0", "n,~{dirflag},~{fpsr},~{flags}"(i32 -81920) nounwind
+ call void asm sideeffect "foo $0", "i,~{dirflag},~{fpsr},~{flags}"(i32 -81920) nounwind
+ call void asm sideeffect "foo $0", "e,~{dirflag},~{fpsr},~{flags}"(i32 -81920) nounwind
+ call void asm sideeffect "foo $0", "Z,~{dirflag},~{fpsr},~{flags}"(i64 4294885376) nounwind
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-02-12-SpillerBug.ll b/test/CodeGen/X86/2009-02-12-SpillerBug.ll
new file mode 100644
index 0000000..4f8a5e7
--- /dev/null
+++ b/test/CodeGen/X86/2009-02-12-SpillerBug.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin8
+; PR3561
+
+define hidden void @__mulxc3({ x86_fp80, x86_fp80 }* noalias nocapture sret %agg.result, x86_fp80 %a, x86_fp80 %b, x86_fp80 %c, x86_fp80 %d) nounwind {
+entry:
+ %0 = fmul x86_fp80 %b, %d ; <x86_fp80> [#uses=1]
+ %1 = fsub x86_fp80 0xK00000000000000000000, %0 ; <x86_fp80> [#uses=1]
+ %2 = fadd x86_fp80 0xK00000000000000000000, 0xK00000000000000000000 ; <x86_fp80> [#uses=1]
+ %3 = fcmp uno x86_fp80 %1, 0xK00000000000000000000 ; <i1> [#uses=1]
+ %4 = fcmp uno x86_fp80 %2, 0xK00000000000000000000 ; <i1> [#uses=1]
+ %or.cond = and i1 %3, %4 ; <i1> [#uses=1]
+ br i1 %or.cond, label %bb47, label %bb71
+
+bb47: ; preds = %entry
+ %5 = fcmp uno x86_fp80 %a, 0xK00000000000000000000 ; <i1> [#uses=1]
+ br i1 %5, label %bb60, label %bb62
+
+bb60: ; preds = %bb47
+ %6 = tail call x86_fp80 @copysignl(x86_fp80 0xK00000000000000000000, x86_fp80 %a) nounwind readnone ; <x86_fp80> [#uses=0]
+ br label %bb62
+
+bb62: ; preds = %bb60, %bb47
+ unreachable
+
+bb71: ; preds = %entry
+ ret void
+}
+
+declare x86_fp80 @copysignl(x86_fp80, x86_fp80) nounwind readnone
diff --git a/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll b/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll
new file mode 100644
index 0000000..58a7f9f
--- /dev/null
+++ b/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll
@@ -0,0 +1,71 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin8 -pre-alloc-split
+
+define i32 @main() nounwind {
+bb4.i.thread:
+ br label %bb5.i4
+
+bb16: ; preds = %bb111.i
+ %phitmp = add i32 %indvar.reg2mem.4, 1 ; <i32> [#uses=2]
+ switch i32 %indvar.reg2mem.4, label %bb100.i [
+ i32 0, label %bb5.i4
+ i32 1, label %bb5.i4
+ i32 2, label %bb5.i4
+ i32 5, label %bb.i14.i
+ i32 6, label %bb.i14.i
+ i32 7, label %bb.i14.i
+ ]
+
+bb5.i4: ; preds = %bb16, %bb16, %bb16, %bb4.i.thread
+ br i1 false, label %bb102.i, label %bb103.i
+
+bb.i14.i: ; preds = %bb16, %bb16, %bb16
+ %0 = malloc [600 x i32] ; <[600 x i32]*> [#uses=0]
+ %1 = icmp eq i32 %phitmp, 7 ; <i1> [#uses=1]
+ %tl.0.i = select i1 %1, float 1.000000e+02, float 1.000000e+00 ; <float> [#uses=1]
+ %2 = icmp eq i32 %phitmp, 8 ; <i1> [#uses=1]
+ %tu.0.i = select i1 %2, float 1.000000e+02, float 1.000000e+00 ; <float> [#uses=1]
+ br label %bb30.i
+
+bb30.i: ; preds = %bb36.i, %bb.i14.i
+ %i.1173.i = phi i32 [ 0, %bb.i14.i ], [ %indvar.next240.i, %bb36.i ] ; <i32> [#uses=3]
+ %3 = icmp eq i32 0, %i.1173.i ; <i1> [#uses=1]
+ br i1 %3, label %bb33.i, label %bb34.i
+
+bb33.i: ; preds = %bb30.i
+ store float %tl.0.i, float* null, align 4
+ br label %bb36.i
+
+bb34.i: ; preds = %bb30.i
+ %4 = icmp eq i32 0, %i.1173.i ; <i1> [#uses=1]
+ br i1 %4, label %bb35.i, label %bb36.i
+
+bb35.i: ; preds = %bb34.i
+ store float %tu.0.i, float* null, align 4
+ br label %bb36.i
+
+bb36.i: ; preds = %bb35.i, %bb34.i, %bb33.i
+ %indvar.next240.i = add i32 %i.1173.i, 1 ; <i32> [#uses=1]
+ br label %bb30.i
+
+bb100.i: ; preds = %bb16
+ ret i32 0
+
+bb102.i: ; preds = %bb5.i4
+ br label %bb103.i
+
+bb103.i: ; preds = %bb102.i, %bb5.i4
+ %indvar.reg2mem.4 = phi i32 [ 0, %bb5.i4 ], [ 0, %bb102.i ] ; <i32> [#uses=2]
+ %n.0.reg2mem.1.i = phi i32 [ 0, %bb102.i ], [ 0, %bb5.i4 ] ; <i32> [#uses=1]
+ %5 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br i1 %5, label %bb111.i, label %bb108.i
+
+bb108.i: ; preds = %bb103.i
+ ret i32 0
+
+bb111.i: ; preds = %bb103.i
+ %6 = icmp sgt i32 %n.0.reg2mem.1.i, 7 ; <i1> [#uses=1]
+ br i1 %6, label %bb16, label %bb112.i
+
+bb112.i: ; preds = %bb111.i
+ unreachable
+}
diff --git a/test/CodeGen/X86/2009-02-21-ExtWeakInitializer.ll b/test/CodeGen/X86/2009-02-21-ExtWeakInitializer.ll
new file mode 100644
index 0000000..b3dd13c
--- /dev/null
+++ b/test/CodeGen/X86/2009-02-21-ExtWeakInitializer.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s | grep weak | count 3
+; PR3629
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "x86_64-unknown-freebsd7.1"
+module asm ".ident\09\22$FreeBSD$\22"
+ %struct.anon = type <{ %struct.uart_devinfo* }>
+ %struct.lock_object = type <{ i8*, i32, i32, %struct.witness* }>
+ %struct.mtx = type <{ %struct.lock_object, i64 }>
+ %struct.uart_bas = type <{ i64, i64, i32, i32, i32, i8, i8, i8, i8 }>
+ %struct.uart_class = type opaque
+ %struct.uart_devinfo = type <{ %struct.anon, %struct.uart_ops*, %struct.uart_bas, i32, i32, i32, i32, i32, i8, i8, i8, i8, i32 (%struct.uart_softc*)*, i32 (%struct.uart_softc*)*, i8*, %struct.mtx* }>
+ %struct.uart_ops = type <{ i32 (%struct.uart_bas*)*, void (%struct.uart_bas*, i32, i32, i32, i32)*, void (%struct.uart_bas*)*, void (%struct.uart_bas*, i32)*, i32 (%struct.uart_bas*)*, i32 (%struct.uart_bas*, %struct.mtx*)* }>
+ %struct.uart_softc = type opaque
+ %struct.witness = type opaque
+
+@uart_classes = internal global [3 x %struct.uart_class*] [%struct.uart_class* @uart_ns8250_class, %struct.uart_class* @uart_sab82532_class, %struct.uart_class* @uart_z8530_class], align 8 ; <[3 x %struct.uart_class*]*> [#uses=1]
+@uart_ns8250_class = extern_weak global %struct.uart_class ; <%struct.uart_class*> [#uses=1]
+@uart_sab82532_class = extern_weak global %struct.uart_class ; <%struct.uart_class*> [#uses=1]
+@uart_z8530_class = extern_weak global %struct.uart_class ; <%struct.uart_class*> [#uses=1]
diff --git a/test/CodeGen/X86/2009-02-25-CommuteBug.ll b/test/CodeGen/X86/2009-02-25-CommuteBug.ll
new file mode 100644
index 0000000..7ea6998
--- /dev/null
+++ b/test/CodeGen/X86/2009-02-25-CommuteBug.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -stats |& not grep commuted
+; rdar://6608609
+
+define <2 x double> @t(<2 x double> %A, <2 x double> %B, <2 x double> %C) nounwind readnone {
+entry:
+ %tmp.i2 = bitcast <2 x double> %B to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp2.i = or <2 x i64> %tmp.i2, <i64 4607632778762754458, i64 4607632778762754458> ; <<2 x i64>> [#uses=1]
+ %tmp3.i = bitcast <2 x i64> %tmp2.i to <2 x double> ; <<2 x double>> [#uses=1]
+ %0 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %A, <2 x double> %tmp3.i) nounwind readnone ; <<2 x double>> [#uses=1]
+ %tmp.i = fadd <2 x double> %0, %C ; <<2 x double>> [#uses=1]
+ ret <2 x double> %tmp.i
+}
+
+declare <2 x double> @llvm.x86.sse2.add.sd(<2 x double>, <2 x double>) nounwind readnone
diff --git a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
new file mode 100644
index 0000000..a4d642b
--- /dev/null
+++ b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& not grep {machine-licm}
+; rdar://6627786
+
+target triple = "x86_64-apple-darwin10.0"
+ %struct.Key = type { i64 }
+ %struct.__Rec = type opaque
+ %struct.__vv = type { }
+
+define %struct.__vv* @t(%struct.Key* %desc, i64 %p) nounwind ssp {
+entry:
+ br label %bb4
+
+bb4: ; preds = %bb.i, %bb26, %bb4, %entry
+ %0 = call i32 (...)* @xxGetOffsetForCode(i32 undef) nounwind ; <i32> [#uses=0]
+ %ins = or i64 %p, 2097152 ; <i64> [#uses=1]
+ %1 = call i32 (...)* @xxCalculateMidType(%struct.Key* %desc, i32 0) nounwind ; <i32> [#uses=1]
+ %cond = icmp eq i32 %1, 1 ; <i1> [#uses=1]
+ br i1 %cond, label %bb26, label %bb4
+
+bb26: ; preds = %bb4
+ %2 = and i64 %ins, 15728640 ; <i64> [#uses=1]
+ %cond.i = icmp eq i64 %2, 1048576 ; <i1> [#uses=1]
+ br i1 %cond.i, label %bb.i, label %bb4
+
+bb.i: ; preds = %bb26
+ %3 = load i32* null, align 4 ; <i32> [#uses=1]
+ %4 = uitofp i32 %3 to float ; <float> [#uses=1]
+ %.sum13.i = add i64 0, 4 ; <i64> [#uses=1]
+ %5 = getelementptr i8* null, i64 %.sum13.i ; <i8*> [#uses=1]
+ %6 = bitcast i8* %5 to i32* ; <i32*> [#uses=1]
+ %7 = load i32* %6, align 4 ; <i32> [#uses=1]
+ %8 = uitofp i32 %7 to float ; <float> [#uses=1]
+ %.sum.i = add i64 0, 8 ; <i64> [#uses=1]
+ %9 = getelementptr i8* null, i64 %.sum.i ; <i8*> [#uses=1]
+ %10 = bitcast i8* %9 to i32* ; <i32*> [#uses=1]
+ %11 = load i32* %10, align 4 ; <i32> [#uses=1]
+ %12 = uitofp i32 %11 to float ; <float> [#uses=1]
+ %13 = insertelement <4 x float> undef, float %4, i32 0 ; <<4 x float>> [#uses=1]
+ %14 = insertelement <4 x float> %13, float %8, i32 1 ; <<4 x float>> [#uses=1]
+ %15 = insertelement <4 x float> %14, float %12, i32 2 ; <<4 x float>> [#uses=1]
+ store <4 x float> %15, <4 x float>* null, align 16
+ br label %bb4
+}
+
+declare i32 @xxGetOffsetForCode(...)
+
+declare i32 @xxCalculateMidType(...)
diff --git a/test/CodeGen/X86/2009-03-03-BTHang.ll b/test/CodeGen/X86/2009-03-03-BTHang.ll
new file mode 100644
index 0000000..bb95925
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-03-BTHang.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=x86
+; rdar://6642541
+
+ %struct.HandleBlock = type { [30 x i32], [990 x i8*], %struct.HandleBlockTrailer }
+ %struct.HandleBlockTrailer = type { %struct.HandleBlock* }
+
+define hidden zeroext i8 @IsHandleAllocatedFromPool(i8** %h) nounwind optsize {
+entry:
+ %0 = ptrtoint i8** %h to i32 ; <i32> [#uses=2]
+ %1 = and i32 %0, -4096 ; <i32> [#uses=1]
+ %2 = inttoptr i32 %1 to %struct.HandleBlock* ; <%struct.HandleBlock*> [#uses=3]
+ %3 = getelementptr %struct.HandleBlock* %2, i32 0, i32 0, i32 0 ; <i32*> [#uses=1]
+ %4 = load i32* %3, align 4096 ; <i32> [#uses=1]
+ %5 = icmp eq i32 %4, 1751280747 ; <i1> [#uses=1]
+ br i1 %5, label %bb, label %bb1
+
+bb: ; preds = %entry
+ %6 = getelementptr %struct.HandleBlock* %2, i32 0, i32 1 ; <[990 x i8*]*> [#uses=1]
+ %7 = ptrtoint [990 x i8*]* %6 to i32 ; <i32> [#uses=1]
+ %8 = sub i32 %0, %7 ; <i32> [#uses=2]
+ %9 = lshr i32 %8, 2 ; <i32> [#uses=1]
+ %10 = ashr i32 %8, 7 ; <i32> [#uses=1]
+ %11 = and i32 %10, 134217727 ; <i32> [#uses=1]
+ %12 = getelementptr %struct.HandleBlock* %2, i32 0, i32 0, i32 %11 ; <i32*> [#uses=1]
+ %not.i = and i32 %9, 31 ; <i32> [#uses=1]
+ %13 = xor i32 %not.i, 31 ; <i32> [#uses=1]
+ %14 = shl i32 1, %13 ; <i32> [#uses=1]
+ %15 = load i32* %12, align 4 ; <i32> [#uses=1]
+ %16 = and i32 %15, %14 ; <i32> [#uses=1]
+ %17 = icmp eq i32 %16, 0 ; <i1> [#uses=1]
+ %tmp = zext i1 %17 to i8 ; <i8> [#uses=1]
+ ret i8 %tmp
+
+bb1: ; preds = %entry
+ ret i8 0
+}
+
diff --git a/test/CodeGen/X86/2009-03-03-BitcastLongDouble.ll b/test/CodeGen/X86/2009-03-03-BitcastLongDouble.ll
new file mode 100644
index 0000000..9deeceb
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-03-BitcastLongDouble.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86
+; PR3686
+; rdar://6661799
+
+define i32 @x(i32 %y) nounwind readnone {
+entry:
+ %tmp14 = zext i32 %y to i80 ; <i80> [#uses=1]
+ %tmp15 = bitcast i80 %tmp14 to x86_fp80 ; <x86_fp80> [#uses=1]
+ %add = fadd x86_fp80 %tmp15, 0xK3FFF8000000000000000 ; <x86_fp80> [#uses=1]
+ %tmp11 = bitcast x86_fp80 %add to i80 ; <i80> [#uses=1]
+ %tmp10 = trunc i80 %tmp11 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp10
+}
+
diff --git a/test/CodeGen/X86/2009-03-05-burr-list-crash.ll b/test/CodeGen/X86/2009-03-05-burr-list-crash.ll
new file mode 100644
index 0000000..411a0c9
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-05-burr-list-crash.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+external global i32 ; <i32*>:0 [#uses=1]
+
+declare i64 @strlen(i8* nocapture) nounwind readonly
+
+define fastcc i8* @1(i8*) nounwind {
+ br i1 false, label %3, label %2
+
+; <label>:2 ; preds = %1
+ ret i8* %0
+
+; <label>:3 ; preds = %1
+ %4 = call i64 @strlen(i8* %0) nounwind readonly ; <i64> [#uses=1]
+ %5 = trunc i64 %4 to i32 ; <i32> [#uses=2]
+ %6 = load i32* @0, align 4 ; <i32> [#uses=1]
+ %7 = sub i32 %5, %6 ; <i32> [#uses=2]
+ %8 = sext i32 %5 to i64 ; <i64> [#uses=1]
+ %9 = sext i32 %7 to i64 ; <i64> [#uses=1]
+ %10 = sub i64 %8, %9 ; <i64> [#uses=1]
+ %11 = getelementptr i8* %0, i64 %10 ; <i8*> [#uses=1]
+ %12 = icmp sgt i32 %7, 0 ; <i1> [#uses=1]
+ br i1 %12, label %13, label %14
+
+; <label>:13 ; preds = %13, %3
+ br label %13
+
+; <label>:14 ; preds = %3
+ %15 = call noalias i8* @make_temp_file(i8* %11) nounwind ; <i8*> [#uses=0]
+ unreachable
+}
+
+declare noalias i8* @make_temp_file(i8*)
diff --git a/test/CodeGen/X86/2009-03-07-FPConstSelect.ll b/test/CodeGen/X86/2009-03-07-FPConstSelect.ll
new file mode 100644
index 0000000..39caddc
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-07-FPConstSelect.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah | not grep xmm
+; This should do a single load into the fp stack for the return, not diddle with xmm registers.
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin7"
+
+define float @f(i32 %x) nounwind readnone {
+entry:
+ %0 = icmp eq i32 %x, 0 ; <i1> [#uses=1]
+ %iftmp.0.0 = select i1 %0, float 4.200000e+01, float 2.300000e+01
+ ret float %iftmp.0.0
+}
diff --git a/test/CodeGen/X86/2009-03-09-APIntCrash.ll b/test/CodeGen/X86/2009-03-09-APIntCrash.ll
new file mode 100644
index 0000000..896c968
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-09-APIntCrash.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86-64
+; PR3763
+ %struct.__block_descriptor = type { i64, i64 }
+
+define %struct.__block_descriptor @evUTCTime() nounwind {
+entry:
+ br i1 false, label %if.then, label %return
+
+if.then: ; preds = %entry
+ %srcval18 = load i128* null, align 8 ; <i128> [#uses=1]
+ %tmp15 = lshr i128 %srcval18, 64 ; <i128> [#uses=1]
+ %tmp9 = mul i128 %tmp15, 18446744073709551616000 ; <i128> [#uses=1]
+ br label %return
+
+return: ; preds = %if.then, %entry
+ %retval.0 = phi i128 [ %tmp9, %if.then ], [ undef, %entry ] ; <i128> [#uses=0]
+ ret %struct.__block_descriptor undef
+}
+
+define i128 @test(i128 %arg) nounwind {
+ %A = shl i128 1, 92
+ %B = sub i128 0, %A
+ %C = mul i128 %arg, %B
+ ret i128 %C ;; should codegen to neg(shift)
+}
diff --git a/test/CodeGen/X86/2009-03-09-SpillerBug.ll b/test/CodeGen/X86/2009-03-09-SpillerBug.ll
new file mode 100644
index 0000000..4224210
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-09-SpillerBug.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu
+; PR3706
+
+define void @__mulxc3(x86_fp80 %b) nounwind {
+entry:
+ %call = call x86_fp80 @y(x86_fp80* null, x86_fp80* null) ; <x86_fp80> [#uses=0]
+ %cmp = fcmp ord x86_fp80 %b, 0xK00000000000000000000 ; <i1> [#uses=1]
+ %sub = fsub x86_fp80 %b, %b ; <x86_fp80> [#uses=1]
+ %cmp7 = fcmp uno x86_fp80 %sub, 0xK00000000000000000000 ; <i1> [#uses=1]
+ %and12 = and i1 %cmp7, %cmp ; <i1> [#uses=1]
+ %and = zext i1 %and12 to i32 ; <i32> [#uses=1]
+ %conv9 = sitofp i32 %and to x86_fp80 ; <x86_fp80> [#uses=1]
+ store x86_fp80 %conv9, x86_fp80* null
+ store x86_fp80 %b, x86_fp80* null
+ ret void
+}
+
+declare x86_fp80 @y(x86_fp80*, x86_fp80*)
diff --git a/test/CodeGen/X86/2009-03-10-CoalescerBug.ll b/test/CodeGen/X86/2009-03-10-CoalescerBug.ll
new file mode 100644
index 0000000..90dff88
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-10-CoalescerBug.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin
+; rdar://r6661945
+
+ %struct.WINDOW = type { i16, i16, i16, i16, i16, i16, i16, i32, i32, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.ldat*, i16, i16, i32, i32, %struct.WINDOW*, %struct.pdat, i16, %struct.cchar_t }
+ %struct.cchar_t = type { i32, [5 x i32] }
+ %struct.ldat = type { %struct.cchar_t*, i16, i16, i16 }
+ %struct.pdat = type { i16, i16, i16, i16, i16, i16 }
+
+define i32 @pnoutrefresh(%struct.WINDOW* %win, i32 %pminrow, i32 %pmincol, i32 %sminrow, i32 %smincol, i32 %smaxrow, i32 %smaxcol) nounwind optsize ssp {
+entry:
+ %0 = load i16* null, align 4 ; <i16> [#uses=2]
+ %1 = icmp sgt i16 0, %0 ; <i1> [#uses=1]
+ br i1 %1, label %bb12, label %bb13
+
+bb12: ; preds = %entry
+ %2 = sext i16 %0 to i32 ; <i32> [#uses=1]
+ %3 = sub i32 %2, 0 ; <i32> [#uses=1]
+ %4 = add i32 %3, %smaxrow ; <i32> [#uses=2]
+ %5 = trunc i32 %4 to i16 ; <i16> [#uses=1]
+ %6 = add i16 0, %5 ; <i16> [#uses=1]
+ br label %bb13
+
+bb13: ; preds = %bb12, %entry
+ %pmaxrow.0 = phi i16 [ %6, %bb12 ], [ 0, %entry ] ; <i16> [#uses=0]
+ %smaxrow_addr.0 = phi i32 [ %4, %bb12 ], [ %smaxrow, %entry ] ; <i32> [#uses=1]
+ %7 = trunc i32 %smaxrow_addr.0 to i16 ; <i16> [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2009-03-11-CoalescerBug.ll b/test/CodeGen/X86/2009-03-11-CoalescerBug.ll
new file mode 100644
index 0000000..d5ba93e
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-11-CoalescerBug.ll
@@ -0,0 +1,85 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin9 -stats |& grep regcoalescing | grep commuting
+
+@lookupTable5B = external global [64 x i32], align 32 ; <[64 x i32]*> [#uses=1]
+@lookupTable3B = external global [16 x i32], align 32 ; <[16 x i32]*> [#uses=1]
+@disparity0 = external global i32 ; <i32*> [#uses=5]
+@disparity1 = external global i32 ; <i32*> [#uses=3]
+
+define i32 @calc(i32 %theWord, i32 %k) nounwind {
+entry:
+ %0 = lshr i32 %theWord, 3 ; <i32> [#uses=1]
+ %1 = and i32 %0, 31 ; <i32> [#uses=1]
+ %2 = shl i32 %k, 5 ; <i32> [#uses=1]
+ %3 = or i32 %1, %2 ; <i32> [#uses=1]
+ %4 = and i32 %theWord, 7 ; <i32> [#uses=1]
+ %5 = shl i32 %k, 3 ; <i32> [#uses=1]
+ %6 = or i32 %5, %4 ; <i32> [#uses=1]
+ %7 = getelementptr [64 x i32]* @lookupTable5B, i32 0, i32 %3 ; <i32*> [#uses=1]
+ %8 = load i32* %7, align 4 ; <i32> [#uses=5]
+ %9 = getelementptr [16 x i32]* @lookupTable3B, i32 0, i32 %6 ; <i32*> [#uses=1]
+ %10 = load i32* %9, align 4 ; <i32> [#uses=5]
+ %11 = and i32 %8, 65536 ; <i32> [#uses=1]
+ %12 = icmp eq i32 %11, 0 ; <i1> [#uses=1]
+ br i1 %12, label %bb1, label %bb
+
+bb: ; preds = %entry
+ %13 = and i32 %8, 994 ; <i32> [#uses=1]
+ %14 = load i32* @disparity0, align 4 ; <i32> [#uses=2]
+ store i32 %14, i32* @disparity1, align 4
+ br label %bb8
+
+bb1: ; preds = %entry
+ %15 = lshr i32 %8, 18 ; <i32> [#uses=1]
+ %16 = and i32 %15, 1 ; <i32> [#uses=1]
+ %17 = load i32* @disparity0, align 4 ; <i32> [#uses=4]
+ %18 = icmp eq i32 %16, %17 ; <i1> [#uses=1]
+ %not = select i1 %18, i32 0, i32 994 ; <i32> [#uses=1]
+ %.masked = and i32 %8, 994 ; <i32> [#uses=1]
+ %result.1 = xor i32 %not, %.masked ; <i32> [#uses=2]
+ %19 = and i32 %8, 524288 ; <i32> [#uses=1]
+ %20 = icmp eq i32 %19, 0 ; <i1> [#uses=1]
+ br i1 %20, label %bb7, label %bb6
+
+bb6: ; preds = %bb1
+ %21 = xor i32 %17, 1 ; <i32> [#uses=2]
+ store i32 %21, i32* @disparity1, align 4
+ br label %bb8
+
+bb7: ; preds = %bb1
+ store i32 %17, i32* @disparity1, align 4
+ br label %bb8
+
+bb8: ; preds = %bb7, %bb6, %bb
+ %22 = phi i32 [ %17, %bb7 ], [ %21, %bb6 ], [ %14, %bb ] ; <i32> [#uses=4]
+ %result.0 = phi i32 [ %result.1, %bb7 ], [ %result.1, %bb6 ], [ %13, %bb ] ; <i32> [#uses=2]
+ %23 = and i32 %10, 65536 ; <i32> [#uses=1]
+ %24 = icmp eq i32 %23, 0 ; <i1> [#uses=1]
+ br i1 %24, label %bb10, label %bb9
+
+bb9: ; preds = %bb8
+ %25 = and i32 %10, 29 ; <i32> [#uses=1]
+ %26 = or i32 %result.0, %25 ; <i32> [#uses=1]
+ store i32 %22, i32* @disparity0, align 4
+ ret i32 %26
+
+bb10: ; preds = %bb8
+ %27 = lshr i32 %10, 18 ; <i32> [#uses=1]
+ %28 = and i32 %27, 1 ; <i32> [#uses=1]
+ %29 = icmp eq i32 %28, %22 ; <i1> [#uses=1]
+ %not13 = select i1 %29, i32 0, i32 29 ; <i32> [#uses=1]
+ %.masked20 = and i32 %10, 29 ; <i32> [#uses=1]
+ %.pn = xor i32 %not13, %.masked20 ; <i32> [#uses=1]
+ %result.3 = or i32 %.pn, %result.0 ; <i32> [#uses=2]
+ %30 = and i32 %10, 524288 ; <i32> [#uses=1]
+ %31 = icmp eq i32 %30, 0 ; <i1> [#uses=1]
+ br i1 %31, label %bb17, label %bb16
+
+bb16: ; preds = %bb10
+ %32 = xor i32 %22, 1 ; <i32> [#uses=1]
+ store i32 %32, i32* @disparity0, align 4
+ ret i32 %result.3
+
+bb17: ; preds = %bb10
+ store i32 %22, i32* @disparity0, align 4
+ ret i32 %result.3
+}
diff --git a/test/CodeGen/X86/2009-03-12-CPAlignBug.ll b/test/CodeGen/X86/2009-03-12-CPAlignBug.ll
new file mode 100644
index 0000000..3564f01
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-12-CPAlignBug.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 | not grep {.space}
+; rdar://6668548
+
+declare double @llvm.sqrt.f64(double) nounwind readonly
+
+declare double @fabs(double)
+
+declare double @llvm.pow.f64(double, double) nounwind readonly
+
+define void @SolveCubic_bb1(i32* %solutions, double* %x, x86_fp80 %.reload, x86_fp80 %.reload5, x86_fp80 %.reload6, double %.reload8) nounwind {
+newFuncRoot:
+ br label %bb1
+
+bb1.ret.exitStub: ; preds = %bb1
+ ret void
+
+bb1: ; preds = %newFuncRoot
+ store i32 1, i32* %solutions, align 4
+ %0 = tail call double @llvm.sqrt.f64(double %.reload8) ; <double> [#uses=1]
+ %1 = fptrunc x86_fp80 %.reload6 to double ; <double> [#uses=1]
+ %2 = tail call double @fabs(double %1) nounwind readnone ; <double> [#uses=1]
+ %3 = fadd double %0, %2 ; <double> [#uses=1]
+ %4 = tail call double @llvm.pow.f64(double %3, double 0x3FD5555555555555) ; <double> [#uses=1]
+ %5 = fpext double %4 to x86_fp80 ; <x86_fp80> [#uses=2]
+ %6 = fdiv x86_fp80 %.reload5, %5 ; <x86_fp80> [#uses=1]
+ %7 = fadd x86_fp80 %5, %6 ; <x86_fp80> [#uses=1]
+ %8 = fptrunc x86_fp80 %7 to double ; <double> [#uses=1]
+ %9 = fcmp olt x86_fp80 %.reload6, 0xK00000000000000000000 ; <i1> [#uses=1]
+ %iftmp.6.0 = select i1 %9, double 1.000000e+00, double -1.000000e+00 ; <double> [#uses=1]
+ %10 = fmul double %8, %iftmp.6.0 ; <double> [#uses=1]
+ %11 = fpext double %10 to x86_fp80 ; <x86_fp80> [#uses=1]
+ %12 = fdiv x86_fp80 %.reload, 0xKC000C000000000000000 ; <x86_fp80> [#uses=1]
+ %13 = fadd x86_fp80 %11, %12 ; <x86_fp80> [#uses=1]
+ %14 = fptrunc x86_fp80 %13 to double ; <double> [#uses=1]
+ store double %14, double* %x, align 1
+ br label %bb1.ret.exitStub
+}
diff --git a/test/CodeGen/X86/2009-03-13-PHIElimBug.ll b/test/CodeGen/X86/2009-03-13-PHIElimBug.ll
new file mode 100644
index 0000000..ad7f9f7
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-13-PHIElimBug.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=x86 | FileCheck %s
+; Check the register copy comes after the call to f and before the call to g
+; PR3784
+
+declare i32 @f()
+
+declare i32 @g()
+
+define i32 @phi() {
+entry:
+ %a = call i32 @f() ; <i32> [#uses=1]
+ %b = invoke i32 @g()
+ to label %cont unwind label %lpad ; <i32> [#uses=1]
+
+cont: ; preds = %entry
+ %x = phi i32 [ %b, %entry ] ; <i32> [#uses=0]
+ %aa = call i32 @g() ; <i32> [#uses=1]
+ %bb = invoke i32 @g()
+ to label %cont2 unwind label %lpad ; <i32> [#uses=1]
+
+cont2: ; preds = %cont
+ %xx = phi i32 [ %bb, %cont ] ; <i32> [#uses=1]
+ ret i32 %xx
+
+lpad: ; preds = %cont, %entry
+ %y = phi i32 [ %a, %entry ], [ %aa, %cont ] ; <i32> [#uses=1]
+ ret i32 %y
+}
+
+; CHECK: call{{.*}}f
+; CHECK-NEXT: Llabel1:
+; CHECK-NEXT: movl %eax, %esi
diff --git a/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll b/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll
new file mode 100644
index 0000000..11c4101
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 -asm-verbose | FileCheck %s
+; Check that register copies in the landing pad come after the EH_LABEL
+
+declare i32 @f()
+
+define i32 @phi(i32 %x) {
+entry:
+ %a = invoke i32 @f()
+ to label %cont unwind label %lpad ; <i32> [#uses=1]
+
+cont: ; preds = %entry
+ %b = invoke i32 @f()
+ to label %cont2 unwind label %lpad ; <i32> [#uses=1]
+
+cont2: ; preds = %cont
+ ret i32 %b
+
+lpad: ; preds = %cont, %entry
+ %v = phi i32 [ %x, %entry ], [ %a, %cont ] ; <i32> [#uses=1]
+ ret i32 %v
+}
+
+; CHECK: lpad
+; CHECK-NEXT: Llabel
diff --git a/test/CodeGen/X86/2009-03-16-SpillerBug.ll b/test/CodeGen/X86/2009-03-16-SpillerBug.ll
new file mode 100644
index 0000000..80e7639
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-16-SpillerBug.ll
@@ -0,0 +1,167 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -stats |& grep virtregrewriter | not grep {stores unfolded}
+; rdar://6682365
+
+; Do not clobber a register if another spill slot is available in it and it's marked "do not clobber".
+
+ %struct.CAST_KEY = type { [32 x i32], i32 }
+@CAST_S_table0 = constant [2 x i32] [i32 821772500, i32 -1616838901], align 32 ; <[2 x i32]*> [#uses=0]
+@CAST_S_table4 = constant [2 x i32] [i32 2127105028, i32 745436345], align 32 ; <[2 x i32]*> [#uses=6]
+@CAST_S_table5 = constant [2 x i32] [i32 -151351395, i32 749497569], align 32 ; <[2 x i32]*> [#uses=5]
+@CAST_S_table6 = constant [2 x i32] [i32 -2048901095, i32 858518887], align 32 ; <[2 x i32]*> [#uses=4]
+@CAST_S_table7 = constant [2 x i32] [i32 -501862387, i32 -1143078916], align 32 ; <[2 x i32]*> [#uses=5]
+@CAST_S_table1 = constant [2 x i32] [i32 522195092, i32 -284448933], align 32 ; <[2 x i32]*> [#uses=0]
+@CAST_S_table2 = constant [2 x i32] [i32 -1913667008, i32 637164959], align 32 ; <[2 x i32]*> [#uses=0]
+@CAST_S_table3 = constant [2 x i32] [i32 -1649212384, i32 532081118], align 32 ; <[2 x i32]*> [#uses=0]
+
+define void @CAST_set_key(%struct.CAST_KEY* nocapture %key, i32 %len, i8* nocapture %data) nounwind ssp {
+bb1.thread:
+ %0 = getelementptr [16 x i32]* null, i32 0, i32 5 ; <i32*> [#uses=1]
+ %1 = getelementptr [16 x i32]* null, i32 0, i32 8 ; <i32*> [#uses=1]
+ %2 = load i32* null, align 4 ; <i32> [#uses=1]
+ %3 = shl i32 %2, 24 ; <i32> [#uses=1]
+ %4 = load i32* null, align 4 ; <i32> [#uses=1]
+ %5 = shl i32 %4, 16 ; <i32> [#uses=1]
+ %6 = load i32* null, align 4 ; <i32> [#uses=1]
+ %7 = or i32 %5, %3 ; <i32> [#uses=1]
+ %8 = or i32 %7, %6 ; <i32> [#uses=1]
+ %9 = or i32 %8, 0 ; <i32> [#uses=1]
+ %10 = load i32* null, align 4 ; <i32> [#uses=1]
+ %11 = shl i32 %10, 24 ; <i32> [#uses=1]
+ %12 = load i32* %0, align 4 ; <i32> [#uses=1]
+ %13 = shl i32 %12, 16 ; <i32> [#uses=1]
+ %14 = load i32* null, align 4 ; <i32> [#uses=1]
+ %15 = or i32 %13, %11 ; <i32> [#uses=1]
+ %16 = or i32 %15, %14 ; <i32> [#uses=1]
+ %17 = or i32 %16, 0 ; <i32> [#uses=1]
+ br label %bb11
+
+bb11: ; preds = %bb11, %bb1.thread
+ %18 = phi i32 [ %110, %bb11 ], [ 0, %bb1.thread ] ; <i32> [#uses=1]
+ %19 = phi i32 [ %112, %bb11 ], [ 0, %bb1.thread ] ; <i32> [#uses=0]
+ %20 = phi i32 [ 0, %bb11 ], [ 0, %bb1.thread ] ; <i32> [#uses=0]
+ %21 = phi i32 [ %113, %bb11 ], [ 0, %bb1.thread ] ; <i32> [#uses=1]
+ %X.0.0 = phi i32 [ %9, %bb1.thread ], [ %92, %bb11 ] ; <i32> [#uses=0]
+ %X.1.0 = phi i32 [ %17, %bb1.thread ], [ 0, %bb11 ] ; <i32> [#uses=0]
+ %22 = getelementptr [2 x i32]* @CAST_S_table6, i32 0, i32 %21 ; <i32*> [#uses=0]
+ %23 = getelementptr [2 x i32]* @CAST_S_table5, i32 0, i32 %18 ; <i32*> [#uses=0]
+ %24 = load i32* null, align 4 ; <i32> [#uses=1]
+ %25 = xor i32 0, %24 ; <i32> [#uses=1]
+ %26 = xor i32 %25, 0 ; <i32> [#uses=1]
+ %27 = xor i32 %26, 0 ; <i32> [#uses=4]
+ %28 = and i32 %27, 255 ; <i32> [#uses=2]
+ %29 = lshr i32 %27, 8 ; <i32> [#uses=1]
+ %30 = and i32 %29, 255 ; <i32> [#uses=2]
+ %31 = lshr i32 %27, 16 ; <i32> [#uses=1]
+ %32 = and i32 %31, 255 ; <i32> [#uses=1]
+ %33 = getelementptr [2 x i32]* @CAST_S_table4, i32 0, i32 %28 ; <i32*> [#uses=1]
+ %34 = load i32* %33, align 4 ; <i32> [#uses=2]
+ %35 = getelementptr [2 x i32]* @CAST_S_table5, i32 0, i32 %30 ; <i32*> [#uses=1]
+ %36 = load i32* %35, align 4 ; <i32> [#uses=2]
+ %37 = xor i32 %34, 0 ; <i32> [#uses=1]
+ %38 = xor i32 %37, %36 ; <i32> [#uses=1]
+ %39 = xor i32 %38, 0 ; <i32> [#uses=1]
+ %40 = xor i32 %39, 0 ; <i32> [#uses=1]
+ %41 = xor i32 %40, 0 ; <i32> [#uses=3]
+ %42 = lshr i32 %41, 8 ; <i32> [#uses=1]
+ %43 = and i32 %42, 255 ; <i32> [#uses=2]
+ %44 = lshr i32 %41, 16 ; <i32> [#uses=1]
+ %45 = and i32 %44, 255 ; <i32> [#uses=1]
+ %46 = getelementptr [2 x i32]* @CAST_S_table4, i32 0, i32 %43 ; <i32*> [#uses=1]
+ %47 = load i32* %46, align 4 ; <i32> [#uses=1]
+ %48 = load i32* null, align 4 ; <i32> [#uses=1]
+ %49 = xor i32 %47, 0 ; <i32> [#uses=1]
+ %50 = xor i32 %49, %48 ; <i32> [#uses=1]
+ %51 = xor i32 %50, 0 ; <i32> [#uses=1]
+ %52 = xor i32 %51, 0 ; <i32> [#uses=1]
+ %53 = xor i32 %52, 0 ; <i32> [#uses=2]
+ %54 = and i32 %53, 255 ; <i32> [#uses=1]
+ %55 = lshr i32 %53, 24 ; <i32> [#uses=1]
+ %56 = getelementptr [2 x i32]* @CAST_S_table6, i32 0, i32 %55 ; <i32*> [#uses=1]
+ %57 = load i32* %56, align 4 ; <i32> [#uses=1]
+ %58 = xor i32 0, %57 ; <i32> [#uses=1]
+ %59 = xor i32 %58, 0 ; <i32> [#uses=1]
+ %60 = xor i32 %59, 0 ; <i32> [#uses=1]
+ store i32 %60, i32* null, align 4
+ %61 = getelementptr [2 x i32]* @CAST_S_table4, i32 0, i32 0 ; <i32*> [#uses=1]
+ %62 = load i32* %61, align 4 ; <i32> [#uses=1]
+ %63 = getelementptr [2 x i32]* @CAST_S_table7, i32 0, i32 %54 ; <i32*> [#uses=1]
+ %64 = load i32* %63, align 4 ; <i32> [#uses=1]
+ %65 = xor i32 0, %64 ; <i32> [#uses=1]
+ %66 = xor i32 %65, 0 ; <i32> [#uses=1]
+ store i32 %66, i32* null, align 4
+ %67 = getelementptr [2 x i32]* @CAST_S_table7, i32 0, i32 %45 ; <i32*> [#uses=1]
+ %68 = load i32* %67, align 4 ; <i32> [#uses=1]
+ %69 = xor i32 %36, %34 ; <i32> [#uses=1]
+ %70 = xor i32 %69, 0 ; <i32> [#uses=1]
+ %71 = xor i32 %70, %68 ; <i32> [#uses=1]
+ %72 = xor i32 %71, 0 ; <i32> [#uses=1]
+ store i32 %72, i32* null, align 4
+ %73 = getelementptr [2 x i32]* @CAST_S_table4, i32 0, i32 %32 ; <i32*> [#uses=1]
+ %74 = load i32* %73, align 4 ; <i32> [#uses=2]
+ %75 = load i32* null, align 4 ; <i32> [#uses=1]
+ %76 = getelementptr [2 x i32]* @CAST_S_table6, i32 0, i32 %43 ; <i32*> [#uses=1]
+ %77 = load i32* %76, align 4 ; <i32> [#uses=1]
+ %78 = getelementptr [2 x i32]* @CAST_S_table7, i32 0, i32 0 ; <i32*> [#uses=1]
+ %79 = load i32* %78, align 4 ; <i32> [#uses=1]
+ %80 = getelementptr [2 x i32]* @CAST_S_table7, i32 0, i32 %30 ; <i32*> [#uses=1]
+ %81 = load i32* %80, align 4 ; <i32> [#uses=2]
+ %82 = xor i32 %75, %74 ; <i32> [#uses=1]
+ %83 = xor i32 %82, %77 ; <i32> [#uses=1]
+ %84 = xor i32 %83, %79 ; <i32> [#uses=1]
+ %85 = xor i32 %84, %81 ; <i32> [#uses=1]
+ store i32 %85, i32* null, align 4
+ %86 = getelementptr [2 x i32]* @CAST_S_table5, i32 0, i32 %28 ; <i32*> [#uses=1]
+ %87 = load i32* %86, align 4 ; <i32> [#uses=1]
+ %88 = xor i32 %74, %41 ; <i32> [#uses=1]
+ %89 = xor i32 %88, %87 ; <i32> [#uses=1]
+ %90 = xor i32 %89, 0 ; <i32> [#uses=1]
+ %91 = xor i32 %90, %81 ; <i32> [#uses=1]
+ %92 = xor i32 %91, 0 ; <i32> [#uses=3]
+ %93 = lshr i32 %92, 16 ; <i32> [#uses=1]
+ %94 = and i32 %93, 255 ; <i32> [#uses=1]
+ store i32 %94, i32* null, align 4
+ %95 = lshr i32 %92, 24 ; <i32> [#uses=2]
+ %96 = getelementptr [2 x i32]* @CAST_S_table4, i32 0, i32 %95 ; <i32*> [#uses=1]
+ %97 = load i32* %96, align 4 ; <i32> [#uses=1]
+ %98 = getelementptr [2 x i32]* @CAST_S_table5, i32 0, i32 0 ; <i32*> [#uses=1]
+ %99 = load i32* %98, align 4 ; <i32> [#uses=1]
+ %100 = load i32* null, align 4 ; <i32> [#uses=0]
+ %101 = xor i32 %97, 0 ; <i32> [#uses=1]
+ %102 = xor i32 %101, %99 ; <i32> [#uses=1]
+ %103 = xor i32 %102, 0 ; <i32> [#uses=1]
+ %104 = xor i32 %103, 0 ; <i32> [#uses=0]
+ store i32 0, i32* null, align 4
+ %105 = xor i32 0, %27 ; <i32> [#uses=1]
+ %106 = xor i32 %105, 0 ; <i32> [#uses=1]
+ %107 = xor i32 %106, 0 ; <i32> [#uses=1]
+ %108 = xor i32 %107, 0 ; <i32> [#uses=1]
+ %109 = xor i32 %108, %62 ; <i32> [#uses=3]
+ %110 = and i32 %109, 255 ; <i32> [#uses=1]
+ %111 = lshr i32 %109, 16 ; <i32> [#uses=1]
+ %112 = and i32 %111, 255 ; <i32> [#uses=1]
+ %113 = lshr i32 %109, 24 ; <i32> [#uses=3]
+ store i32 %113, i32* %1, align 4
+ %114 = load i32* null, align 4 ; <i32> [#uses=1]
+ %115 = xor i32 0, %114 ; <i32> [#uses=1]
+ %116 = xor i32 %115, 0 ; <i32> [#uses=1]
+ %117 = xor i32 %116, 0 ; <i32> [#uses=1]
+ %K.0.sum42 = or i32 0, 12 ; <i32> [#uses=1]
+ %118 = getelementptr [32 x i32]* null, i32 0, i32 %K.0.sum42 ; <i32*> [#uses=1]
+ store i32 %117, i32* %118, align 4
+ %119 = getelementptr [2 x i32]* @CAST_S_table5, i32 0, i32 0 ; <i32*> [#uses=0]
+ store i32 0, i32* null, align 4
+ %120 = getelementptr [2 x i32]* @CAST_S_table6, i32 0, i32 %113 ; <i32*> [#uses=1]
+ %121 = load i32* %120, align 4 ; <i32> [#uses=1]
+ %122 = xor i32 0, %121 ; <i32> [#uses=1]
+ store i32 %122, i32* null, align 4
+ %123 = getelementptr [2 x i32]* @CAST_S_table4, i32 0, i32 0 ; <i32*> [#uses=1]
+ %124 = load i32* %123, align 4 ; <i32> [#uses=1]
+ %125 = getelementptr [2 x i32]* @CAST_S_table7, i32 0, i32 %95 ; <i32*> [#uses=1]
+ %126 = load i32* %125, align 4 ; <i32> [#uses=1]
+ %127 = xor i32 0, %124 ; <i32> [#uses=1]
+ %128 = xor i32 %127, 0 ; <i32> [#uses=1]
+ %129 = xor i32 %128, %126 ; <i32> [#uses=1]
+ %130 = xor i32 %129, 0 ; <i32> [#uses=1]
+ store i32 %130, i32* null, align 4
+ br label %bb11
+}
diff --git a/test/CodeGen/X86/2009-03-23-LinearScanBug.ll b/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
new file mode 100644
index 0000000..06dfdc0
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-23-LinearScanBug.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -O0
+
+define fastcc void @optimize_bit_field() nounwind {
+bb4:
+ %a = load i32* null ; <i32> [#uses=1]
+ %s = load i32* getelementptr (i32* null, i32 1) ; <i32> [#uses=1]
+ %z = load i32* getelementptr (i32* null, i32 2) ; <i32> [#uses=1]
+ %r = bitcast i32 0 to i32 ; <i32> [#uses=1]
+ %q = trunc i32 %z to i8 ; <i8> [#uses=1]
+ %b = icmp eq i8 0, %q ; <i1> [#uses=1]
+ br i1 %b, label %bb73, label %bb72
+
+bb72: ; preds = %bb4
+ %f = tail call fastcc i32 @gen_lowpart(i32 %r, i32 %a) nounwind ; <i32> [#uses=1]
+ br label %bb73
+
+bb73: ; preds = %bb72, %bb4
+ %y = phi i32 [ %f, %bb72 ], [ %s, %bb4 ] ; <i32> [#uses=1]
+ store i32 %y, i32* getelementptr (i32* null, i32 3)
+ unreachable
+}
+
+declare fastcc i32 @gen_lowpart(i32, i32) nounwind
diff --git a/test/CodeGen/X86/2009-03-23-MultiUseSched.ll b/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
new file mode 100644
index 0000000..b5873ba
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
@@ -0,0 +1,242 @@
+; RUN: llc < %s -mtriple=x86_64-linux -relocation-model=static -stats -info-output-file - > %t
+; RUN: not grep spill %t
+; RUN: not grep {%rsp} %t
+; RUN: not grep {%rbp} %t
+
+; The register-pressure scheduler should be able to schedule this in a
+; way that does not require spills.
+
+@X = external global i64 ; <i64*> [#uses=25]
+
+define fastcc i64 @foo() nounwind {
+ %tmp = volatile load i64* @X ; <i64> [#uses=7]
+ %tmp1 = volatile load i64* @X ; <i64> [#uses=5]
+ %tmp2 = volatile load i64* @X ; <i64> [#uses=3]
+ %tmp3 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp4 = volatile load i64* @X ; <i64> [#uses=5]
+ %tmp5 = volatile load i64* @X ; <i64> [#uses=3]
+ %tmp6 = volatile load i64* @X ; <i64> [#uses=2]
+ %tmp7 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp8 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp9 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp10 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp11 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp12 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp13 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp14 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp15 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp16 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp17 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp18 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp19 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp20 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp21 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp22 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp23 = volatile load i64* @X ; <i64> [#uses=1]
+ %tmp24 = call i64 @llvm.bswap.i64(i64 %tmp8) ; <i64> [#uses=1]
+ %tmp25 = add i64 %tmp6, %tmp5 ; <i64> [#uses=1]
+ %tmp26 = add i64 %tmp25, %tmp4 ; <i64> [#uses=1]
+ %tmp27 = add i64 %tmp7, %tmp4 ; <i64> [#uses=1]
+ %tmp28 = add i64 %tmp27, %tmp26 ; <i64> [#uses=1]
+ %tmp29 = add i64 %tmp28, %tmp24 ; <i64> [#uses=2]
+ %tmp30 = add i64 %tmp2, %tmp1 ; <i64> [#uses=1]
+ %tmp31 = add i64 %tmp30, %tmp ; <i64> [#uses=1]
+ %tmp32 = add i64 %tmp2, %tmp1 ; <i64> [#uses=1]
+ %tmp33 = add i64 %tmp31, %tmp32 ; <i64> [#uses=1]
+ %tmp34 = add i64 %tmp29, %tmp3 ; <i64> [#uses=5]
+ %tmp35 = add i64 %tmp33, %tmp ; <i64> [#uses=1]
+ %tmp36 = add i64 %tmp35, %tmp29 ; <i64> [#uses=7]
+ %tmp37 = call i64 @llvm.bswap.i64(i64 %tmp9) ; <i64> [#uses=1]
+ %tmp38 = add i64 %tmp4, %tmp5 ; <i64> [#uses=1]
+ %tmp39 = add i64 %tmp38, %tmp34 ; <i64> [#uses=1]
+ %tmp40 = add i64 %tmp6, %tmp37 ; <i64> [#uses=1]
+ %tmp41 = add i64 %tmp40, %tmp39 ; <i64> [#uses=1]
+ %tmp42 = add i64 %tmp41, %tmp34 ; <i64> [#uses=2]
+ %tmp43 = add i64 %tmp1, %tmp ; <i64> [#uses=1]
+ %tmp44 = add i64 %tmp36, %tmp43 ; <i64> [#uses=1]
+ %tmp45 = add i64 %tmp1, %tmp ; <i64> [#uses=1]
+ %tmp46 = add i64 %tmp44, %tmp45 ; <i64> [#uses=1]
+ %tmp47 = add i64 %tmp42, %tmp2 ; <i64> [#uses=5]
+ %tmp48 = add i64 %tmp36, %tmp46 ; <i64> [#uses=1]
+ %tmp49 = add i64 %tmp48, %tmp42 ; <i64> [#uses=7]
+ %tmp50 = call i64 @llvm.bswap.i64(i64 %tmp10) ; <i64> [#uses=1]
+ %tmp51 = add i64 %tmp34, %tmp4 ; <i64> [#uses=1]
+ %tmp52 = add i64 %tmp51, %tmp47 ; <i64> [#uses=1]
+ %tmp53 = add i64 %tmp5, %tmp50 ; <i64> [#uses=1]
+ %tmp54 = add i64 %tmp53, %tmp52 ; <i64> [#uses=1]
+ %tmp55 = add i64 %tmp54, %tmp47 ; <i64> [#uses=2]
+ %tmp56 = add i64 %tmp36, %tmp ; <i64> [#uses=1]
+ %tmp57 = add i64 %tmp49, %tmp56 ; <i64> [#uses=1]
+ %tmp58 = add i64 %tmp36, %tmp ; <i64> [#uses=1]
+ %tmp59 = add i64 %tmp57, %tmp58 ; <i64> [#uses=1]
+ %tmp60 = add i64 %tmp55, %tmp1 ; <i64> [#uses=5]
+ %tmp61 = add i64 %tmp49, %tmp59 ; <i64> [#uses=1]
+ %tmp62 = add i64 %tmp61, %tmp55 ; <i64> [#uses=7]
+ %tmp63 = call i64 @llvm.bswap.i64(i64 %tmp11) ; <i64> [#uses=1]
+ %tmp64 = add i64 %tmp47, %tmp34 ; <i64> [#uses=1]
+ %tmp65 = add i64 %tmp64, %tmp60 ; <i64> [#uses=1]
+ %tmp66 = add i64 %tmp4, %tmp63 ; <i64> [#uses=1]
+ %tmp67 = add i64 %tmp66, %tmp65 ; <i64> [#uses=1]
+ %tmp68 = add i64 %tmp67, %tmp60 ; <i64> [#uses=2]
+ %tmp69 = add i64 %tmp49, %tmp36 ; <i64> [#uses=1]
+ %tmp70 = add i64 %tmp62, %tmp69 ; <i64> [#uses=1]
+ %tmp71 = add i64 %tmp49, %tmp36 ; <i64> [#uses=1]
+ %tmp72 = add i64 %tmp70, %tmp71 ; <i64> [#uses=1]
+ %tmp73 = add i64 %tmp68, %tmp ; <i64> [#uses=5]
+ %tmp74 = add i64 %tmp62, %tmp72 ; <i64> [#uses=1]
+ %tmp75 = add i64 %tmp74, %tmp68 ; <i64> [#uses=7]
+ %tmp76 = call i64 @llvm.bswap.i64(i64 %tmp12) ; <i64> [#uses=1]
+ %tmp77 = add i64 %tmp60, %tmp47 ; <i64> [#uses=1]
+ %tmp78 = add i64 %tmp77, %tmp73 ; <i64> [#uses=1]
+ %tmp79 = add i64 %tmp34, %tmp76 ; <i64> [#uses=1]
+ %tmp80 = add i64 %tmp79, %tmp78 ; <i64> [#uses=1]
+ %tmp81 = add i64 %tmp80, %tmp73 ; <i64> [#uses=2]
+ %tmp82 = add i64 %tmp62, %tmp49 ; <i64> [#uses=1]
+ %tmp83 = add i64 %tmp75, %tmp82 ; <i64> [#uses=1]
+ %tmp84 = add i64 %tmp62, %tmp49 ; <i64> [#uses=1]
+ %tmp85 = add i64 %tmp83, %tmp84 ; <i64> [#uses=1]
+ %tmp86 = add i64 %tmp81, %tmp36 ; <i64> [#uses=5]
+ %tmp87 = add i64 %tmp75, %tmp85 ; <i64> [#uses=1]
+ %tmp88 = add i64 %tmp87, %tmp81 ; <i64> [#uses=7]
+ %tmp89 = call i64 @llvm.bswap.i64(i64 %tmp13) ; <i64> [#uses=1]
+ %tmp90 = add i64 %tmp73, %tmp60 ; <i64> [#uses=1]
+ %tmp91 = add i64 %tmp90, %tmp86 ; <i64> [#uses=1]
+ %tmp92 = add i64 %tmp47, %tmp89 ; <i64> [#uses=1]
+ %tmp93 = add i64 %tmp92, %tmp91 ; <i64> [#uses=1]
+ %tmp94 = add i64 %tmp93, %tmp86 ; <i64> [#uses=2]
+ %tmp95 = add i64 %tmp75, %tmp62 ; <i64> [#uses=1]
+ %tmp96 = add i64 %tmp88, %tmp95 ; <i64> [#uses=1]
+ %tmp97 = add i64 %tmp75, %tmp62 ; <i64> [#uses=1]
+ %tmp98 = add i64 %tmp96, %tmp97 ; <i64> [#uses=1]
+ %tmp99 = add i64 %tmp94, %tmp49 ; <i64> [#uses=5]
+ %tmp100 = add i64 %tmp88, %tmp98 ; <i64> [#uses=1]
+ %tmp101 = add i64 %tmp100, %tmp94 ; <i64> [#uses=7]
+ %tmp102 = call i64 @llvm.bswap.i64(i64 %tmp14) ; <i64> [#uses=1]
+ %tmp103 = add i64 %tmp86, %tmp73 ; <i64> [#uses=1]
+ %tmp104 = add i64 %tmp103, %tmp99 ; <i64> [#uses=1]
+ %tmp105 = add i64 %tmp102, %tmp60 ; <i64> [#uses=1]
+ %tmp106 = add i64 %tmp105, %tmp104 ; <i64> [#uses=1]
+ %tmp107 = add i64 %tmp106, %tmp99 ; <i64> [#uses=2]
+ %tmp108 = add i64 %tmp88, %tmp75 ; <i64> [#uses=1]
+ %tmp109 = add i64 %tmp101, %tmp108 ; <i64> [#uses=1]
+ %tmp110 = add i64 %tmp88, %tmp75 ; <i64> [#uses=1]
+ %tmp111 = add i64 %tmp109, %tmp110 ; <i64> [#uses=1]
+ %tmp112 = add i64 %tmp107, %tmp62 ; <i64> [#uses=5]
+ %tmp113 = add i64 %tmp101, %tmp111 ; <i64> [#uses=1]
+ %tmp114 = add i64 %tmp113, %tmp107 ; <i64> [#uses=7]
+ %tmp115 = call i64 @llvm.bswap.i64(i64 %tmp15) ; <i64> [#uses=1]
+ %tmp116 = add i64 %tmp99, %tmp86 ; <i64> [#uses=1]
+ %tmp117 = add i64 %tmp116, %tmp112 ; <i64> [#uses=1]
+ %tmp118 = add i64 %tmp115, %tmp73 ; <i64> [#uses=1]
+ %tmp119 = add i64 %tmp118, %tmp117 ; <i64> [#uses=1]
+ %tmp120 = add i64 %tmp119, %tmp112 ; <i64> [#uses=2]
+ %tmp121 = add i64 %tmp101, %tmp88 ; <i64> [#uses=1]
+ %tmp122 = add i64 %tmp114, %tmp121 ; <i64> [#uses=1]
+ %tmp123 = add i64 %tmp101, %tmp88 ; <i64> [#uses=1]
+ %tmp124 = add i64 %tmp122, %tmp123 ; <i64> [#uses=1]
+ %tmp125 = add i64 %tmp120, %tmp75 ; <i64> [#uses=5]
+ %tmp126 = add i64 %tmp114, %tmp124 ; <i64> [#uses=1]
+ %tmp127 = add i64 %tmp126, %tmp120 ; <i64> [#uses=7]
+ %tmp128 = call i64 @llvm.bswap.i64(i64 %tmp16) ; <i64> [#uses=1]
+ %tmp129 = add i64 %tmp112, %tmp99 ; <i64> [#uses=1]
+ %tmp130 = add i64 %tmp129, %tmp125 ; <i64> [#uses=1]
+ %tmp131 = add i64 %tmp128, %tmp86 ; <i64> [#uses=1]
+ %tmp132 = add i64 %tmp131, %tmp130 ; <i64> [#uses=1]
+ %tmp133 = add i64 %tmp132, %tmp125 ; <i64> [#uses=2]
+ %tmp134 = add i64 %tmp114, %tmp101 ; <i64> [#uses=1]
+ %tmp135 = add i64 %tmp127, %tmp134 ; <i64> [#uses=1]
+ %tmp136 = add i64 %tmp114, %tmp101 ; <i64> [#uses=1]
+ %tmp137 = add i64 %tmp135, %tmp136 ; <i64> [#uses=1]
+ %tmp138 = add i64 %tmp133, %tmp88 ; <i64> [#uses=5]
+ %tmp139 = add i64 %tmp127, %tmp137 ; <i64> [#uses=1]
+ %tmp140 = add i64 %tmp139, %tmp133 ; <i64> [#uses=7]
+ %tmp141 = call i64 @llvm.bswap.i64(i64 %tmp17) ; <i64> [#uses=1]
+ %tmp142 = add i64 %tmp125, %tmp112 ; <i64> [#uses=1]
+ %tmp143 = add i64 %tmp142, %tmp138 ; <i64> [#uses=1]
+ %tmp144 = add i64 %tmp141, %tmp99 ; <i64> [#uses=1]
+ %tmp145 = add i64 %tmp144, %tmp143 ; <i64> [#uses=1]
+ %tmp146 = add i64 %tmp145, %tmp138 ; <i64> [#uses=2]
+ %tmp147 = add i64 %tmp127, %tmp114 ; <i64> [#uses=1]
+ %tmp148 = add i64 %tmp140, %tmp147 ; <i64> [#uses=1]
+ %tmp149 = add i64 %tmp127, %tmp114 ; <i64> [#uses=1]
+ %tmp150 = add i64 %tmp148, %tmp149 ; <i64> [#uses=1]
+ %tmp151 = add i64 %tmp146, %tmp101 ; <i64> [#uses=5]
+ %tmp152 = add i64 %tmp140, %tmp150 ; <i64> [#uses=1]
+ %tmp153 = add i64 %tmp152, %tmp146 ; <i64> [#uses=7]
+ %tmp154 = call i64 @llvm.bswap.i64(i64 %tmp18) ; <i64> [#uses=1]
+ %tmp155 = add i64 %tmp138, %tmp125 ; <i64> [#uses=1]
+ %tmp156 = add i64 %tmp155, %tmp151 ; <i64> [#uses=1]
+ %tmp157 = add i64 %tmp154, %tmp112 ; <i64> [#uses=1]
+ %tmp158 = add i64 %tmp157, %tmp156 ; <i64> [#uses=1]
+ %tmp159 = add i64 %tmp158, %tmp151 ; <i64> [#uses=2]
+ %tmp160 = add i64 %tmp140, %tmp127 ; <i64> [#uses=1]
+ %tmp161 = add i64 %tmp153, %tmp160 ; <i64> [#uses=1]
+ %tmp162 = add i64 %tmp140, %tmp127 ; <i64> [#uses=1]
+ %tmp163 = add i64 %tmp161, %tmp162 ; <i64> [#uses=1]
+ %tmp164 = add i64 %tmp159, %tmp114 ; <i64> [#uses=5]
+ %tmp165 = add i64 %tmp153, %tmp163 ; <i64> [#uses=1]
+ %tmp166 = add i64 %tmp165, %tmp159 ; <i64> [#uses=7]
+ %tmp167 = call i64 @llvm.bswap.i64(i64 %tmp19) ; <i64> [#uses=1]
+ %tmp168 = add i64 %tmp151, %tmp138 ; <i64> [#uses=1]
+ %tmp169 = add i64 %tmp168, %tmp164 ; <i64> [#uses=1]
+ %tmp170 = add i64 %tmp167, %tmp125 ; <i64> [#uses=1]
+ %tmp171 = add i64 %tmp170, %tmp169 ; <i64> [#uses=1]
+ %tmp172 = add i64 %tmp171, %tmp164 ; <i64> [#uses=2]
+ %tmp173 = add i64 %tmp153, %tmp140 ; <i64> [#uses=1]
+ %tmp174 = add i64 %tmp166, %tmp173 ; <i64> [#uses=1]
+ %tmp175 = add i64 %tmp153, %tmp140 ; <i64> [#uses=1]
+ %tmp176 = add i64 %tmp174, %tmp175 ; <i64> [#uses=1]
+ %tmp177 = add i64 %tmp172, %tmp127 ; <i64> [#uses=5]
+ %tmp178 = add i64 %tmp166, %tmp176 ; <i64> [#uses=1]
+ %tmp179 = add i64 %tmp178, %tmp172 ; <i64> [#uses=6]
+ %tmp180 = call i64 @llvm.bswap.i64(i64 %tmp20) ; <i64> [#uses=1]
+ %tmp181 = add i64 %tmp164, %tmp151 ; <i64> [#uses=1]
+ %tmp182 = add i64 %tmp181, %tmp177 ; <i64> [#uses=1]
+ %tmp183 = add i64 %tmp180, %tmp138 ; <i64> [#uses=1]
+ %tmp184 = add i64 %tmp183, %tmp182 ; <i64> [#uses=1]
+ %tmp185 = add i64 %tmp184, %tmp177 ; <i64> [#uses=2]
+ %tmp186 = add i64 %tmp166, %tmp153 ; <i64> [#uses=1]
+ %tmp187 = add i64 %tmp179, %tmp186 ; <i64> [#uses=1]
+ %tmp188 = add i64 %tmp166, %tmp153 ; <i64> [#uses=1]
+ %tmp189 = add i64 %tmp187, %tmp188 ; <i64> [#uses=1]
+ %tmp190 = add i64 %tmp185, %tmp140 ; <i64> [#uses=4]
+ %tmp191 = add i64 %tmp179, %tmp189 ; <i64> [#uses=1]
+ %tmp192 = add i64 %tmp191, %tmp185 ; <i64> [#uses=4]
+ %tmp193 = call i64 @llvm.bswap.i64(i64 %tmp21) ; <i64> [#uses=1]
+ %tmp194 = add i64 %tmp177, %tmp164 ; <i64> [#uses=1]
+ %tmp195 = add i64 %tmp194, %tmp190 ; <i64> [#uses=1]
+ %tmp196 = add i64 %tmp193, %tmp151 ; <i64> [#uses=1]
+ %tmp197 = add i64 %tmp196, %tmp195 ; <i64> [#uses=1]
+ %tmp198 = add i64 %tmp197, %tmp190 ; <i64> [#uses=2]
+ %tmp199 = add i64 %tmp179, %tmp166 ; <i64> [#uses=1]
+ %tmp200 = add i64 %tmp192, %tmp199 ; <i64> [#uses=1]
+ %tmp201 = add i64 %tmp179, %tmp166 ; <i64> [#uses=1]
+ %tmp202 = add i64 %tmp200, %tmp201 ; <i64> [#uses=1]
+ %tmp203 = add i64 %tmp198, %tmp153 ; <i64> [#uses=3]
+ %tmp204 = add i64 %tmp192, %tmp202 ; <i64> [#uses=1]
+ %tmp205 = add i64 %tmp204, %tmp198 ; <i64> [#uses=2]
+ %tmp206 = call i64 @llvm.bswap.i64(i64 %tmp22) ; <i64> [#uses=1]
+ %tmp207 = add i64 %tmp190, %tmp177 ; <i64> [#uses=1]
+ %tmp208 = add i64 %tmp207, %tmp203 ; <i64> [#uses=1]
+ %tmp209 = add i64 %tmp206, %tmp164 ; <i64> [#uses=1]
+ %tmp210 = add i64 %tmp209, %tmp208 ; <i64> [#uses=1]
+ %tmp211 = add i64 %tmp210, %tmp203 ; <i64> [#uses=2]
+ %tmp212 = add i64 %tmp192, %tmp179 ; <i64> [#uses=1]
+ %tmp213 = add i64 %tmp205, %tmp212 ; <i64> [#uses=1]
+ %tmp214 = add i64 %tmp192, %tmp179 ; <i64> [#uses=1]
+ %tmp215 = add i64 %tmp213, %tmp214 ; <i64> [#uses=1]
+ %tmp216 = add i64 %tmp211, %tmp166 ; <i64> [#uses=2]
+ %tmp217 = add i64 %tmp205, %tmp215 ; <i64> [#uses=1]
+ %tmp218 = add i64 %tmp217, %tmp211 ; <i64> [#uses=1]
+ %tmp219 = call i64 @llvm.bswap.i64(i64 %tmp23) ; <i64> [#uses=2]
+ volatile store i64 %tmp219, i64* @X, align 8
+ %tmp220 = add i64 %tmp203, %tmp190 ; <i64> [#uses=1]
+ %tmp221 = add i64 %tmp220, %tmp216 ; <i64> [#uses=1]
+ %tmp222 = add i64 %tmp219, %tmp177 ; <i64> [#uses=1]
+ %tmp223 = add i64 %tmp222, %tmp221 ; <i64> [#uses=1]
+ %tmp224 = add i64 %tmp223, %tmp216 ; <i64> [#uses=1]
+ %tmp225 = add i64 %tmp224, %tmp218 ; <i64> [#uses=1]
+ ret i64 %tmp225
+}
+
+declare i64 @llvm.bswap.i64(i64) nounwind readnone
diff --git a/test/CodeGen/X86/2009-03-23-i80-fp80.ll b/test/CodeGen/X86/2009-03-23-i80-fp80.ll
new file mode 100644
index 0000000..e542325
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-23-i80-fp80.ll
@@ -0,0 +1,14 @@
+; RUN: opt < %s -instcombine -S | grep 302245289961712575840256
+; RUN: opt < %s -instcombine -S | grep K40018000000000000000
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin9"
+
+define i80 @from() {
+ %tmp = bitcast x86_fp80 0xK4000C000000000000000 to i80
+ ret i80 %tmp
+}
+
+define x86_fp80 @to() {
+ %tmp = bitcast i80 302259125019767858003968 to x86_fp80
+ ret x86_fp80 %tmp
+}
diff --git a/test/CodeGen/X86/2009-03-25-TestBug.ll b/test/CodeGen/X86/2009-03-25-TestBug.ll
new file mode 100644
index 0000000..f40fddc
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-25-TestBug.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86 -o %t
+; RUN: not grep and %t
+; RUN: not grep shr %t
+; rdar://6661955
+
+@hello = internal constant [7 x i8] c"hello\0A\00"
+@world = internal constant [7 x i8] c"world\0A\00"
+
+define void @func(i32* %b) nounwind {
+bb1579.i.i: ; preds = %bb1514.i.i, %bb191.i.i
+ %tmp176 = load i32* %b, align 4
+ %tmp177 = and i32 %tmp176, 2
+ %tmp178 = icmp eq i32 %tmp177, 0
+ br i1 %tmp178, label %hello, label %world
+
+hello:
+ %h = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8]* @hello, i32 0, i32 0))
+ ret void
+
+world:
+ %w = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8]* @world, i32 0, i32 0))
+ ret void
+}
+
+declare i32 @printf(i8*, ...) nounwind
diff --git a/test/CodeGen/X86/2009-03-26-NoImplicitFPBug.ll b/test/CodeGen/X86/2009-03-26-NoImplicitFPBug.ll
new file mode 100644
index 0000000..f486479
--- /dev/null
+++ b/test/CodeGen/X86/2009-03-26-NoImplicitFPBug.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+
+define double @t(double %x) nounwind ssp noimplicitfloat {
+entry:
+ br i1 false, label %return, label %bb3
+
+bb3: ; preds = %entry
+ ret double 0.000000e+00
+
+return: ; preds = %entry
+ ret double undef
+}
diff --git a/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll b/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll
new file mode 100644
index 0000000..97bbd93
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-09-InlineAsmCrash.ll
@@ -0,0 +1,165 @@
+; RUN: llc < %s
+; rdar://6774324
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin10.0"
+ type <{ i32, %1 }> ; type %0
+ type <{ [216 x i8] }> ; type %1
+ type <{ %3, %4*, %28*, i64, i32, %6, %6, i32, i32, i32, i32, void (i8*, i32)*, i8*, %29*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [2 x i8*], i32, %30, i32, %24, %4*, %4*, i64, i64, i32, i32, void (i32, %2*)*, i32, i32, i32, i32, i32, i32, i32, i32, %24, i64, i64, i64, i64, i64, %21, i32, i32, %21, i32, %31*, %3, %33, %34, %9*, i32, i32, %3, %3, %35, %41*, %42*, %11, i32, i32, i32, i8, i8, i8, i8, %69*, %69, %9*, %9*, [11 x %61], %3, i8*, i32, i64, i64, i32, i32, i32, i64 }> ; type %2
+ type <{ %3*, %3* }> ; type %3
+ type <{ %3, i32, %2*, %2*, %2*, %5*, i32, i32, %21, i64, i64, i64, i32, %22, %9*, %6, %4*, %23 }> ; type %4
+ type <{ %3, %3, %4*, %4*, i32, %6, %9*, %9*, %5*, %20* }> ; type %5
+ type <{ %7, i16, i8, i8, %8 }> ; type %6
+ type <{ i32 }> ; type %7
+ type <{ i8*, i8*, [2 x i32], i16, i8, i8, i8*, i8, i8, i8, i8, i8* }> ; type %8
+ type <{ %10, %13, %15, i32, i32, i32, i32, %9*, %9*, %16*, i32, %17*, i64, i32 }> ; type %9
+ type <{ i32, i32, %11 }> ; type %10
+ type <{ %12 }> ; type %11
+ type <{ [12 x i8] }> ; type %12
+ type <{ %14 }> ; type %13
+ type <{ [40 x i8] }> ; type %14
+ type <{ [4 x i8] }> ; type %15
+ type <{ %15, %15 }> ; type %16
+ type <{ %17*, %17*, %9*, i32, %18*, %19* }> ; type %17
+ type opaque ; type %18
+ type <{ i32, i32, %9*, %9*, i32, i32 }> ; type %19
+ type <{ %5*, %20*, %20*, %20* }> ; type %20
+ type <{ %3, %3*, void (i8*, i8*)*, i8*, i8*, i64 }> ; type %21
+ type <{ i32, [4 x i32], i32, i32, [128 x %3] }> ; type %22
+ type <{ %24, %24, %24, %24*, %24*, %24*, %25, %26, %27, i32, i32, i8* }> ; type %23
+ type <{ i64, i32, i32, i32 }> ; type %24
+ type <{ i32, i32 }> ; type %25
+ type <{ i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32 }> ; type %26
+ type <{ [16 x %17*], i32 }> ; type %27
+ type <{ i8, i8, i8, i8, %7, %3 }> ; type %28
+ type <{ i32, %11*, i8*, i8*, %11* }> ; type %29
+ type <{ i32, i32, i32, i32, i64 }> ; type %30
+ type <{ %32*, %3, %3, i32, i32, i32, %5* }> ; type %31
+ type opaque ; type %32
+ type <{ [44 x i8] }> ; type %33
+ type <{ %17* }> ; type %34
+ type <{ %36, %36*, i32, [4 x %40], i32, i32, i64, i32 }> ; type %35
+ type <{ i8*, %0*, %37*, i64, %39, i32, %39, %6, i64, i64, i8*, i32 }> ; type %36
+ type <{ i32, i32, i8, i8, i8, i8, i8, i8, i8, i8, %38 }> ; type %37
+ type <{ i16, i16, i8, i8, i16, i32, i16, i16, i32, i16, i16, i32, i32, [8 x [8 x i16]], [8 x [16 x i16]], [96 x i8] }> ; type %38
+ type <{ i8, i8, i8, i8, i8, i8, i8, i8 }> ; type %39
+ type <{ i64 }> ; type %40
+ type <{ %11, i32, i32, i32, %42*, %3, i8*, %3, %5*, %32*, i32, i32, i32, i32, i32, i32, i32, %59, %60, i64, i64, i32, %11, %9*, %9*, %9*, [11 x %61], %9*, %9*, %9*, %9*, %9*, [3 x %9*], %62*, %3, %3, i32, i32, %9*, %9*, i32, %67*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, %68*, [2 x i32], i64, i64, i32 }> ; type %41
+ type <{ %43, %44, %47*, i64, i64, i64, i32, %11, %54, %46*, %46*, i32, i32, i32, i32, i32, i32, i32 }> ; type %42
+ type <{ i16, i8, i8, i32, i32 }> ; type %43
+ type <{ %45, i32, i32 }> ; type %44
+ type <{ %46*, %46*, i64, i64 }> ; type %45
+ type <{ %45, %15, i64, i8, i8, i8, i8, i16, i16 }> ; type %46
+ type <{ i64*, i64, %48*, i32, i32, i32, %6, %53, i32, i64, i64*, i64*, %48*, %48*, %48*, i32 }> ; type %47
+ type <{ %3, %43, i64, %49*, i32, i32, i32, i32, %48*, %48*, i64, %50*, i64, %52*, i32, i16, i16, i8, i8, i8, i8, %3, %3, i64, i32, i32, i32, i8*, i32, i8, i8, i8, i8, %3 }> ; type %48
+ type <{ %3, %3, %49*, %48*, i64, i8, i8, i8, i8, i32, i8, i8, i8, i8 }> ; type %49
+ type <{ i32, %51* }> ; type %50
+ type <{ void (%50*)*, void (%50*)*, i32 (%50*, %52*, i32)*, i32 (%50*)*, i32 (%50*, i64, i32, i32, i32*)*, i32 (%50*, i64, i32, i64*, i32*, i32, i32, i32)*, i32 (%50*, i64, i32)*, i32 (%50*, i64, i64, i32)*, i32 (%50*, i64, i64, i32)*, i32 (%50*, i32)*, i32 (%50*)*, i8* }> ; type %51
+ type <{ i32, %48* }> ; type %52
+ type <{ i32, i32, i32 }> ; type %53
+ type <{ %11, %55*, i32, %53, i64 }> ; type %54
+ type <{ %3, i32, i32, i32, i32, i32, [64 x i8], %56 }> ; type %55
+ type <{ %57, %58, %58 }> ; type %56
+ type <{ i64, i64, i64, i64, i64 }> ; type %57
+ type <{ i64, i64, i64, i64, i64, i64, i64, i64 }> ; type %58
+ type <{ [2 x i32] }> ; type %59
+ type <{ [8 x i32] }> ; type %60
+ type <{ %9*, i32, i32, i32 }> ; type %61
+ type <{ %11, i32, %11, i32, i32, %63*, i32, %64*, %65, i32, i32, i32, i32, %41* }> ; type %62
+ type <{ %10*, i32, %15, %15 }> ; type %63
+ type opaque ; type %64
+ type <{ i32, %66*, %66*, %66**, %66*, %66** }> ; type %65
+ type <{ %63, i32, %62*, %66*, %66* }> ; type %66
+ type <{ i32, i32, [0 x %39] }> ; type %67
+ type opaque ; type %68
+ type <{ %69*, void (%69*, %2*)* }> ; type %69
+ type <{ %70*, %2*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i32, %71, i32, i32, i64, i64, i64, %72, i8*, i8*, %73, %4*, %79*, %81*, %39*, %84, i32, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i32, i64*, i32, i64*, i8*, i32, [256 x i32], i64, i64, %86, %77*, i64, i64, %88*, %2*, %2* }> ; type %70
+ type <{ %3, i64, i32, i32 }> ; type %71
+ type <{ i64, i64, i64 }> ; type %72
+ type <{ %73*, %73*, %73*, %73*, %74*, %75*, %76*, %70*, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, [3 x %78*], i8*, i8* }> ; type %73
+ type <{ %74*, %74*, %75*, %76*, %73*, i32, i32, i32, i32, i32, i8*, i8* }> ; type %74
+ type <{ %75*, %73*, %74*, %76*, i32, i32, i32, i32, %78*, i8*, i8* }> ; type %75
+ type <{ %76*, %73*, %74*, %75*, i32, i32, i32, i32, i8*, i8*, %77* }> ; type %76
+ type opaque ; type %77
+ type <{ %78*, %75*, i8, i8, i8, i8, i16, i16, i16, i8, i8, i32, [0 x %73*] }> ; type %78
+ type <{ i32, i32, i32, [20 x %80] }> ; type %79
+ type <{ i64*, i8* }> ; type %80
+ type <{ [256 x %39], [19 x %39], i8, i8, i8, i8, i8, i8, i8, i8, %82, i8, i8, i8, i8, i8, i8, i8, i8, %82, %83 }> ; type %81
+ type <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16 }> ; type %82
+ type <{ [16 x i64], i64 }> ; type %83
+ type <{ %82*, %85, %85, %39*, i32 }> ; type %84
+ type <{ i16, %39* }> ; type %85
+ type <{ %87, i8* }> ; type %86
+ type <{ i32, i32, i32, i8, i8, i16, i32, i32, i32, i32, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }> ; type %87
+ type <{ i64, i64, i32, i32, i32, i32 }> ; type %88
+ type <{ i32, i32, i32, i32, i32, i32, i32 }> ; type %89
+@kernel_stack_size = external global i32 ; <i32*> [#uses=1]
+
+define void @test(%0*) nounwind {
+ %2 = tail call %2* asm sideeffect "mov %gs:${1:P},$0", "=r,i,~{dirflag},~{fpsr},~{flags}"(i32 ptrtoint (%2** getelementptr (%70* null, i32 0, i32 1) to i32)) nounwind ; <%2*> [#uses=1]
+ %3 = getelementptr %2* %2, i32 0, i32 15 ; <i32*> [#uses=1]
+ %4 = load i32* %3 ; <i32> [#uses=2]
+ %5 = icmp eq i32 %4, 0 ; <i1> [#uses=1]
+ br i1 %5, label %47, label %6
+
+; <label>:6 ; preds = %1
+ %7 = load i32* @kernel_stack_size ; <i32> [#uses=1]
+ %8 = add i32 %7, %4 ; <i32> [#uses=1]
+ %9 = inttoptr i32 %8 to %89* ; <%89*> [#uses=12]
+ %10 = tail call %2* asm sideeffect "mov %gs:${1:P},$0", "=r,i,~{dirflag},~{fpsr},~{flags}"(i32 ptrtoint (%2** getelementptr (%70* null, i32 0, i32 1) to i32)) nounwind ; <%2*> [#uses=1]
+ %11 = getelementptr %2* %10, i32 0, i32 65, i32 1 ; <%36**> [#uses=1]
+ %12 = load %36** %11 ; <%36*> [#uses=1]
+ %13 = getelementptr %36* %12, i32 0, i32 1 ; <%0**> [#uses=1]
+ %14 = load %0** %13 ; <%0*> [#uses=1]
+ %15 = icmp eq %0* %14, %0 ; <i1> [#uses=1]
+ br i1 %15, label %40, label %16
+
+; <label>:16 ; preds = %6
+ %17 = getelementptr %0* %0, i32 0, i32 1 ; <%1*> [#uses=1]
+ %18 = getelementptr %89* %9, i32 -1, i32 0 ; <i32*> [#uses=1]
+ %19 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 32 ; <i8*> [#uses=1]
+ %20 = bitcast i8* %19 to i32* ; <i32*> [#uses=1]
+ %21 = load i32* %20 ; <i32> [#uses=1]
+ store i32 %21, i32* %18
+ %22 = getelementptr %89* %9, i32 -1, i32 1 ; <i32*> [#uses=1]
+ %23 = ptrtoint %1* %17 to i32 ; <i32> [#uses=1]
+ store i32 %23, i32* %22
+ %24 = getelementptr %89* %9, i32 -1, i32 2 ; <i32*> [#uses=1]
+ %25 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 24 ; <i8*> [#uses=1]
+ %26 = bitcast i8* %25 to i32* ; <i32*> [#uses=1]
+ %27 = load i32* %26 ; <i32> [#uses=1]
+ store i32 %27, i32* %24
+ %28 = getelementptr %89* %9, i32 -1, i32 3 ; <i32*> [#uses=1]
+ %29 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 16 ; <i8*> [#uses=1]
+ %30 = bitcast i8* %29 to i32* ; <i32*> [#uses=1]
+ %31 = load i32* %30 ; <i32> [#uses=1]
+ store i32 %31, i32* %28
+ %32 = getelementptr %89* %9, i32 -1, i32 4 ; <i32*> [#uses=1]
+ %33 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 20 ; <i8*> [#uses=1]
+ %34 = bitcast i8* %33 to i32* ; <i32*> [#uses=1]
+ %35 = load i32* %34 ; <i32> [#uses=1]
+ store i32 %35, i32* %32
+ %36 = getelementptr %89* %9, i32 -1, i32 5 ; <i32*> [#uses=1]
+ %37 = getelementptr %0* %0, i32 0, i32 1, i32 0, i32 56 ; <i8*> [#uses=1]
+ %38 = bitcast i8* %37 to i32* ; <i32*> [#uses=1]
+ %39 = load i32* %38 ; <i32> [#uses=1]
+ store i32 %39, i32* %36
+ ret void
+
+; <label>:40 ; preds = %6
+ %41 = getelementptr %89* %9, i32 -1, i32 0 ; <i32*> [#uses=1]
+ tail call void asm sideeffect "movl %ebx, $0", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %41) nounwind
+ %42 = getelementptr %89* %9, i32 -1, i32 1 ; <i32*> [#uses=1]
+ tail call void asm sideeffect "movl %esp, $0", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %42) nounwind
+ %43 = getelementptr %89* %9, i32 -1, i32 2 ; <i32*> [#uses=1]
+ tail call void asm sideeffect "movl %ebp, $0", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %43) nounwind
+ %44 = getelementptr %89* %9, i32 -1, i32 3 ; <i32*> [#uses=1]
+ tail call void asm sideeffect "movl %edi, $0", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %44) nounwind
+ %45 = getelementptr %89* %9, i32 -1, i32 4 ; <i32*> [#uses=1]
+ tail call void asm sideeffect "movl %esi, $0", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %45) nounwind
+ %46 = getelementptr %89* %9, i32 -1, i32 5 ; <i32*> [#uses=1]
+ tail call void asm sideeffect "movl $$1f, $0\0A1:", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %46) nounwind
+ ret void
+
+; <label>:47 ; preds = %1
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll b/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
new file mode 100644
index 0000000..27f11cf
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -fast-isel
+; radr://6772169
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin10"
+ type { i32, i1 } ; type %0
+
+declare %0 @llvm.sadd.with.overflow.i32(i32, i32) nounwind
+
+define fastcc i32 @test() nounwind {
+entry:
+ %tmp1 = call %0 @llvm.sadd.with.overflow.i32(i32 1, i32 0)
+ %tmp2 = extractvalue %0 %tmp1, 1
+ br i1 %tmp2, label %.backedge, label %BB3
+
+BB3:
+ %tmp4 = extractvalue %0 %tmp1, 0
+ br label %.backedge
+
+.backedge:
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2009-04-12-picrel.ll b/test/CodeGen/X86/2009-04-12-picrel.ll
new file mode 100644
index 0000000..f1942801
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-12-picrel.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small > %t
+; RUN: grep leaq %t | count 1
+
+@dst = external global [131072 x i32]
+@ptr = external global i32*
+
+define void @off01(i64 %i) nounwind {
+entry:
+ %.sum = add i64 %i, 16
+ %0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %.sum
+ store i32* %0, i32** @ptr, align 8
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll b/test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll
new file mode 100644
index 0000000..ff8cf0a
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin
+; rdar://6781755
+; PR3934
+
+ type { i32, i32 } ; type %0
+
+define void @bn_sqr_comba8(i32* nocapture %r, i32* %a) nounwind {
+entry:
+ %asmtmp23 = tail call %0 asm "mulq $3", "={ax},={dx},{ax},*m,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32* %a) nounwind ; <%0> [#uses=1]
+ %asmresult25 = extractvalue %0 %asmtmp23, 1 ; <i32> [#uses=1]
+ %asmtmp26 = tail call %0 asm "addq $0,$0; adcq $2,$1", "={dx},=r,imr,0,1,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 %asmresult25, i32 0) nounwind ; <%0> [#uses=1]
+ %asmresult27 = extractvalue %0 %asmtmp26, 0 ; <i32> [#uses=1]
+ %asmtmp29 = tail call %0 asm "addq $0,$0; adcq $2,$1", "={ax},={dx},imr,0,1,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 0, i32 %asmresult27) nounwind ; <%0> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-04-13-2AddrAssert.ll b/test/CodeGen/X86/2009-04-13-2AddrAssert.ll
new file mode 100644
index 0000000..4362ba4
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-13-2AddrAssert.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s
+; rdar://6781755
+; PR3934
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "x86_64-undermydesk-freebsd8.0"
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
+entry:
+ %call = tail call i32 (...)* @getpid() ; <i32> [#uses=1]
+ %conv = trunc i32 %call to i16 ; <i16> [#uses=1]
+ %0 = tail call i16 asm "xchgb ${0:h}, ${0:b}","=Q,0,~{dirflag},~{fpsr},~{flags}"(i16 %conv) nounwind ; <i16> [#uses=0]
+ ret i32 undef
+}
+
+declare i32 @getpid(...)
diff --git a/test/CodeGen/X86/2009-04-14-IllegalRegs.ll b/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
new file mode 100644
index 0000000..bfa3eaa
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-14-IllegalRegs.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -O0 -regalloc=local | not grep sil
+; rdar://6787136
+
+ %struct.X = type { i8, [32 x i8] }
[email protected] = appending global [1 x i8*] [i8* bitcast (i32 ()* @z to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define i32 @z() nounwind ssp {
+entry:
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ %xxx = alloca %struct.X ; <%struct.X*> [#uses=6]
+ %0 = alloca i32 ; <i32*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %1 = getelementptr %struct.X* %xxx, i32 0, i32 1 ; <[32 x i8]*> [#uses=1]
+ %2 = getelementptr [32 x i8]* %1, i32 0, i32 31 ; <i8*> [#uses=1]
+ store i8 48, i8* %2, align 1
+ %3 = getelementptr %struct.X* %xxx, i32 0, i32 1 ; <[32 x i8]*> [#uses=1]
+ %4 = getelementptr [32 x i8]* %3, i32 0, i32 31 ; <i8*> [#uses=1]
+ %5 = load i8* %4, align 1 ; <i8> [#uses=1]
+ %6 = getelementptr %struct.X* %xxx, i32 0, i32 1 ; <[32 x i8]*> [#uses=1]
+ %7 = getelementptr [32 x i8]* %6, i32 0, i32 0 ; <i8*> [#uses=1]
+ store i8 %5, i8* %7, align 1
+ %8 = getelementptr %struct.X* %xxx, i32 0, i32 0 ; <i8*> [#uses=1]
+ store i8 15, i8* %8, align 1
+ %9 = call i32 (...)* bitcast (i32 (%struct.X*, %struct.X*)* @f to i32 (...)*)(%struct.X* byval align 4 %xxx, %struct.X* byval align 4 %xxx) nounwind ; <i32> [#uses=1]
+ store i32 %9, i32* %0, align 4
+ %10 = load i32* %0, align 4 ; <i32> [#uses=1]
+ store i32 %10, i32* %retval, align 4
+ br label %return
+
+return: ; preds = %entry
+ %retval1 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval1
+}
+
+declare i32 @f(%struct.X* byval align 4, %struct.X* byval align 4) nounwind ssp
diff --git a/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll b/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll
new file mode 100644
index 0000000..f46eed4
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll
@@ -0,0 +1,141 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of modref unfolded}
+; XFAIL: *
+; 69408 removed the opportunity for this optimization to work
+
+ %struct.SHA512_CTX = type { [8 x i64], i64, i64, %struct.anon, i32, i32 }
+ %struct.anon = type { [16 x i64] }
+@K512 = external constant [80 x i64], align 32 ; <[80 x i64]*> [#uses=2]
+
+define fastcc void @sha512_block_data_order(%struct.SHA512_CTX* nocapture %ctx, i8* nocapture %in, i64 %num) nounwind ssp {
+entry:
+ br label %bb349
+
+bb349: ; preds = %bb349, %entry
+ %e.0489 = phi i64 [ 0, %entry ], [ %e.0, %bb349 ] ; <i64> [#uses=3]
+ %b.0472 = phi i64 [ 0, %entry ], [ %87, %bb349 ] ; <i64> [#uses=2]
+ %asmtmp356 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 41, i64 %e.0489) nounwind ; <i64> [#uses=1]
+ %0 = xor i64 0, %asmtmp356 ; <i64> [#uses=1]
+ %1 = add i64 0, %0 ; <i64> [#uses=1]
+ %2 = add i64 %1, 0 ; <i64> [#uses=1]
+ %3 = add i64 %2, 0 ; <i64> [#uses=1]
+ %4 = add i64 %3, 0 ; <i64> [#uses=5]
+ %asmtmp372 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 34, i64 %4) nounwind ; <i64> [#uses=1]
+ %asmtmp373 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 39, i64 %4) nounwind ; <i64> [#uses=0]
+ %5 = xor i64 %asmtmp372, 0 ; <i64> [#uses=0]
+ %6 = xor i64 0, %b.0472 ; <i64> [#uses=1]
+ %7 = and i64 %4, %6 ; <i64> [#uses=1]
+ %8 = xor i64 %7, 0 ; <i64> [#uses=1]
+ %9 = add i64 0, %8 ; <i64> [#uses=1]
+ %10 = add i64 %9, 0 ; <i64> [#uses=2]
+ %asmtmp377 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 61, i64 0) nounwind ; <i64> [#uses=1]
+ %11 = xor i64 0, %asmtmp377 ; <i64> [#uses=1]
+ %12 = add i64 0, %11 ; <i64> [#uses=1]
+ %13 = add i64 %12, 0 ; <i64> [#uses=1]
+ %not381 = xor i64 0, -1 ; <i64> [#uses=1]
+ %14 = and i64 %e.0489, %not381 ; <i64> [#uses=1]
+ %15 = xor i64 0, %14 ; <i64> [#uses=1]
+ %16 = add i64 %15, 0 ; <i64> [#uses=1]
+ %17 = add i64 %16, %13 ; <i64> [#uses=1]
+ %18 = add i64 %17, 0 ; <i64> [#uses=1]
+ %19 = add i64 %18, 0 ; <i64> [#uses=2]
+ %20 = add i64 %19, %b.0472 ; <i64> [#uses=3]
+ %21 = add i64 %19, 0 ; <i64> [#uses=1]
+ %22 = add i64 %21, 0 ; <i64> [#uses=1]
+ %23 = add i32 0, 12 ; <i32> [#uses=1]
+ %24 = and i32 %23, 12 ; <i32> [#uses=1]
+ %25 = zext i32 %24 to i64 ; <i64> [#uses=1]
+ %26 = getelementptr [16 x i64]* null, i64 0, i64 %25 ; <i64*> [#uses=0]
+ %27 = add i64 0, %e.0489 ; <i64> [#uses=1]
+ %28 = add i64 %27, 0 ; <i64> [#uses=1]
+ %29 = add i64 %28, 0 ; <i64> [#uses=1]
+ %30 = add i64 %29, 0 ; <i64> [#uses=2]
+ %31 = and i64 %10, %4 ; <i64> [#uses=1]
+ %32 = xor i64 0, %31 ; <i64> [#uses=1]
+ %33 = add i64 %30, 0 ; <i64> [#uses=3]
+ %34 = add i64 %30, %32 ; <i64> [#uses=1]
+ %35 = add i64 %34, 0 ; <i64> [#uses=1]
+ %36 = and i64 %33, %20 ; <i64> [#uses=1]
+ %37 = xor i64 %36, 0 ; <i64> [#uses=1]
+ %38 = add i64 %37, 0 ; <i64> [#uses=1]
+ %39 = add i64 %38, 0 ; <i64> [#uses=1]
+ %40 = add i64 %39, 0 ; <i64> [#uses=1]
+ %41 = add i64 %40, 0 ; <i64> [#uses=1]
+ %42 = add i64 %41, %4 ; <i64> [#uses=3]
+ %43 = or i32 0, 6 ; <i32> [#uses=1]
+ %44 = and i32 %43, 14 ; <i32> [#uses=1]
+ %45 = zext i32 %44 to i64 ; <i64> [#uses=1]
+ %46 = getelementptr [16 x i64]* null, i64 0, i64 %45 ; <i64*> [#uses=1]
+ %not417 = xor i64 %42, -1 ; <i64> [#uses=1]
+ %47 = and i64 %20, %not417 ; <i64> [#uses=1]
+ %48 = xor i64 0, %47 ; <i64> [#uses=1]
+ %49 = getelementptr [80 x i64]* @K512, i64 0, i64 0 ; <i64*> [#uses=1]
+ %50 = load i64* %49, align 8 ; <i64> [#uses=1]
+ %51 = add i64 %48, 0 ; <i64> [#uses=1]
+ %52 = add i64 %51, 0 ; <i64> [#uses=1]
+ %53 = add i64 %52, 0 ; <i64> [#uses=1]
+ %54 = add i64 %53, %50 ; <i64> [#uses=2]
+ %asmtmp420 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 34, i64 0) nounwind ; <i64> [#uses=1]
+ %asmtmp421 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 39, i64 0) nounwind ; <i64> [#uses=1]
+ %55 = xor i64 %asmtmp420, 0 ; <i64> [#uses=1]
+ %56 = xor i64 %55, %asmtmp421 ; <i64> [#uses=1]
+ %57 = add i64 %54, %10 ; <i64> [#uses=5]
+ %58 = add i64 %54, 0 ; <i64> [#uses=1]
+ %59 = add i64 %58, %56 ; <i64> [#uses=2]
+ %60 = or i32 0, 7 ; <i32> [#uses=1]
+ %61 = and i32 %60, 15 ; <i32> [#uses=1]
+ %62 = zext i32 %61 to i64 ; <i64> [#uses=1]
+ %63 = getelementptr [16 x i64]* null, i64 0, i64 %62 ; <i64*> [#uses=2]
+ %64 = load i64* null, align 8 ; <i64> [#uses=1]
+ %65 = lshr i64 %64, 6 ; <i64> [#uses=1]
+ %66 = xor i64 0, %65 ; <i64> [#uses=1]
+ %67 = xor i64 %66, 0 ; <i64> [#uses=1]
+ %68 = load i64* %46, align 8 ; <i64> [#uses=1]
+ %69 = load i64* null, align 8 ; <i64> [#uses=1]
+ %70 = add i64 %68, 0 ; <i64> [#uses=1]
+ %71 = add i64 %70, %67 ; <i64> [#uses=1]
+ %72 = add i64 %71, %69 ; <i64> [#uses=1]
+ %asmtmp427 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 18, i64 %57) nounwind ; <i64> [#uses=1]
+ %asmtmp428 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 41, i64 %57) nounwind ; <i64> [#uses=1]
+ %73 = xor i64 %asmtmp427, 0 ; <i64> [#uses=1]
+ %74 = xor i64 %73, %asmtmp428 ; <i64> [#uses=1]
+ %75 = and i64 %57, %42 ; <i64> [#uses=1]
+ %not429 = xor i64 %57, -1 ; <i64> [#uses=1]
+ %76 = and i64 %33, %not429 ; <i64> [#uses=1]
+ %77 = xor i64 %75, %76 ; <i64> [#uses=1]
+ %78 = getelementptr [80 x i64]* @K512, i64 0, i64 0 ; <i64*> [#uses=1]
+ %79 = load i64* %78, align 16 ; <i64> [#uses=1]
+ %80 = add i64 %77, %20 ; <i64> [#uses=1]
+ %81 = add i64 %80, %72 ; <i64> [#uses=1]
+ %82 = add i64 %81, %74 ; <i64> [#uses=1]
+ %83 = add i64 %82, %79 ; <i64> [#uses=1]
+ %asmtmp432 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 34, i64 %59) nounwind ; <i64> [#uses=1]
+ %asmtmp433 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 39, i64 %59) nounwind ; <i64> [#uses=1]
+ %84 = xor i64 %asmtmp432, 0 ; <i64> [#uses=1]
+ %85 = xor i64 %84, %asmtmp433 ; <i64> [#uses=1]
+ %86 = add i64 %83, %22 ; <i64> [#uses=2]
+ %87 = add i64 0, %85 ; <i64> [#uses=1]
+ %asmtmp435 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 8, i64 0) nounwind ; <i64> [#uses=1]
+ %88 = xor i64 0, %asmtmp435 ; <i64> [#uses=1]
+ %89 = load i64* null, align 8 ; <i64> [#uses=3]
+ %asmtmp436 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 19, i64 %89) nounwind ; <i64> [#uses=1]
+ %asmtmp437 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 61, i64 %89) nounwind ; <i64> [#uses=1]
+ %90 = lshr i64 %89, 6 ; <i64> [#uses=1]
+ %91 = xor i64 %asmtmp436, %90 ; <i64> [#uses=1]
+ %92 = xor i64 %91, %asmtmp437 ; <i64> [#uses=1]
+ %93 = load i64* %63, align 8 ; <i64> [#uses=1]
+ %94 = load i64* null, align 8 ; <i64> [#uses=1]
+ %95 = add i64 %93, %88 ; <i64> [#uses=1]
+ %96 = add i64 %95, %92 ; <i64> [#uses=1]
+ %97 = add i64 %96, %94 ; <i64> [#uses=2]
+ store i64 %97, i64* %63, align 8
+ %98 = and i64 %86, %57 ; <i64> [#uses=1]
+ %not441 = xor i64 %86, -1 ; <i64> [#uses=1]
+ %99 = and i64 %42, %not441 ; <i64> [#uses=1]
+ %100 = xor i64 %98, %99 ; <i64> [#uses=1]
+ %101 = add i64 %100, %33 ; <i64> [#uses=1]
+ %102 = add i64 %101, %97 ; <i64> [#uses=1]
+ %103 = add i64 %102, 0 ; <i64> [#uses=1]
+ %104 = add i64 %103, 0 ; <i64> [#uses=1]
+ %e.0 = add i64 %104, %35 ; <i64> [#uses=1]
+ br label %bb349
+}
diff --git a/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll b/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll
new file mode 100644
index 0000000..d7b9463
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll
@@ -0,0 +1,121 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 83
+; rdar://6802189
+
+; Test if linearscan is unfavoring registers for allocation to allow more reuse
+; of reloads from stack slots.
+
+ %struct.SHA_CTX = type { i32, i32, i32, i32, i32, i32, i32, [16 x i32], i32 }
+
+define fastcc void @sha1_block_data_order(%struct.SHA_CTX* nocapture %c, i8* %p, i64 %num) nounwind {
+entry:
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %asmtmp511 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=3]
+ %asmtmp513 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; <i32> [#uses=2]
+ %asmtmp516 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; <i32> [#uses=1]
+ %asmtmp517 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=2]
+ %0 = xor i32 0, %asmtmp513 ; <i32> [#uses=0]
+ %1 = add i32 0, %asmtmp517 ; <i32> [#uses=1]
+ %2 = add i32 %1, 0 ; <i32> [#uses=1]
+ %3 = add i32 %2, 0 ; <i32> [#uses=1]
+ %asmtmp519 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; <i32> [#uses=1]
+ %4 = xor i32 0, %asmtmp511 ; <i32> [#uses=1]
+ %asmtmp520 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %4) nounwind ; <i32> [#uses=2]
+ %5 = xor i32 0, %asmtmp516 ; <i32> [#uses=1]
+ %6 = xor i32 %5, %asmtmp519 ; <i32> [#uses=1]
+ %7 = add i32 %asmtmp513, -899497514 ; <i32> [#uses=1]
+ %8 = add i32 %7, %asmtmp520 ; <i32> [#uses=1]
+ %9 = add i32 %8, %6 ; <i32> [#uses=1]
+ %10 = add i32 %9, 0 ; <i32> [#uses=1]
+ %asmtmp523 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=1]
+ %asmtmp525 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %3) nounwind ; <i32> [#uses=2]
+ %11 = xor i32 0, %asmtmp525 ; <i32> [#uses=1]
+ %12 = add i32 0, %11 ; <i32> [#uses=1]
+ %13 = add i32 %12, 0 ; <i32> [#uses=2]
+ %asmtmp528 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %10) nounwind ; <i32> [#uses=1]
+ %14 = xor i32 0, %asmtmp520 ; <i32> [#uses=1]
+ %asmtmp529 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %14) nounwind ; <i32> [#uses=1]
+ %asmtmp530 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %13) nounwind ; <i32> [#uses=1]
+ %15 = add i32 0, %asmtmp530 ; <i32> [#uses=1]
+ %16 = xor i32 0, %asmtmp523 ; <i32> [#uses=1]
+ %asmtmp532 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %16) nounwind ; <i32> [#uses=2]
+ %asmtmp533 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %15) nounwind ; <i32> [#uses=1]
+ %17 = xor i32 %13, %asmtmp528 ; <i32> [#uses=1]
+ %18 = xor i32 %17, 0 ; <i32> [#uses=1]
+ %19 = add i32 %asmtmp525, -899497514 ; <i32> [#uses=1]
+ %20 = add i32 %19, %asmtmp532 ; <i32> [#uses=1]
+ %21 = add i32 %20, %18 ; <i32> [#uses=1]
+ %22 = add i32 %21, %asmtmp533 ; <i32> [#uses=1]
+ %23 = xor i32 0, %asmtmp511 ; <i32> [#uses=1]
+ %24 = xor i32 %23, 0 ; <i32> [#uses=1]
+ %asmtmp535 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %24) nounwind ; <i32> [#uses=3]
+ %25 = add i32 0, %asmtmp535 ; <i32> [#uses=1]
+ %26 = add i32 %25, 0 ; <i32> [#uses=1]
+ %27 = add i32 %26, 0 ; <i32> [#uses=1]
+ %28 = xor i32 0, %asmtmp529 ; <i32> [#uses=0]
+ %29 = xor i32 %22, 0 ; <i32> [#uses=1]
+ %30 = xor i32 %29, 0 ; <i32> [#uses=1]
+ %31 = add i32 0, %30 ; <i32> [#uses=1]
+ %32 = add i32 %31, 0 ; <i32> [#uses=3]
+ %asmtmp541 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=2]
+ %asmtmp542 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %32) nounwind ; <i32> [#uses=1]
+ %33 = add i32 0, %asmtmp541 ; <i32> [#uses=1]
+ %34 = add i32 %33, 0 ; <i32> [#uses=1]
+ %35 = add i32 %34, %asmtmp542 ; <i32> [#uses=1]
+ %asmtmp543 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %27) nounwind ; <i32> [#uses=2]
+ %36 = xor i32 0, %asmtmp535 ; <i32> [#uses=0]
+ %37 = xor i32 %32, 0 ; <i32> [#uses=1]
+ %38 = xor i32 %37, %asmtmp543 ; <i32> [#uses=1]
+ %39 = add i32 0, %38 ; <i32> [#uses=1]
+ %40 = add i32 %39, 0 ; <i32> [#uses=2]
+ %asmtmp546 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %32) nounwind ; <i32> [#uses=1]
+ %asmtmp547 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=2]
+ %41 = add i32 0, -899497514 ; <i32> [#uses=1]
+ %42 = add i32 %41, %asmtmp547 ; <i32> [#uses=1]
+ %43 = add i32 %42, 0 ; <i32> [#uses=1]
+ %44 = add i32 %43, 0 ; <i32> [#uses=3]
+ %asmtmp549 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %35) nounwind ; <i32> [#uses=2]
+ %45 = xor i32 0, %asmtmp541 ; <i32> [#uses=1]
+ %asmtmp550 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %45) nounwind ; <i32> [#uses=2]
+ %asmtmp551 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %44) nounwind ; <i32> [#uses=1]
+ %46 = xor i32 %40, %asmtmp546 ; <i32> [#uses=1]
+ %47 = xor i32 %46, %asmtmp549 ; <i32> [#uses=1]
+ %48 = add i32 %asmtmp543, -899497514 ; <i32> [#uses=1]
+ %49 = add i32 %48, %asmtmp550 ; <i32> [#uses=1]
+ %50 = add i32 %49, %47 ; <i32> [#uses=1]
+ %51 = add i32 %50, %asmtmp551 ; <i32> [#uses=1]
+ %asmtmp552 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %40) nounwind ; <i32> [#uses=2]
+ %52 = xor i32 %44, %asmtmp549 ; <i32> [#uses=1]
+ %53 = xor i32 %52, %asmtmp552 ; <i32> [#uses=1]
+ %54 = add i32 0, %53 ; <i32> [#uses=1]
+ %55 = add i32 %54, 0 ; <i32> [#uses=2]
+ %asmtmp555 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %44) nounwind ; <i32> [#uses=2]
+ %56 = xor i32 0, %asmtmp532 ; <i32> [#uses=1]
+ %57 = xor i32 %56, %asmtmp547 ; <i32> [#uses=1]
+ %asmtmp556 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %57) nounwind ; <i32> [#uses=1]
+ %58 = add i32 0, %asmtmp556 ; <i32> [#uses=1]
+ %59 = add i32 %58, 0 ; <i32> [#uses=1]
+ %60 = add i32 %59, 0 ; <i32> [#uses=1]
+ %asmtmp558 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %51) nounwind ; <i32> [#uses=1]
+ %61 = xor i32 %asmtmp517, %asmtmp511 ; <i32> [#uses=1]
+ %62 = xor i32 %61, %asmtmp535 ; <i32> [#uses=1]
+ %63 = xor i32 %62, %asmtmp550 ; <i32> [#uses=1]
+ %asmtmp559 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %63) nounwind ; <i32> [#uses=1]
+ %64 = xor i32 %55, %asmtmp555 ; <i32> [#uses=1]
+ %65 = xor i32 %64, %asmtmp558 ; <i32> [#uses=1]
+ %asmtmp561 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %55) nounwind ; <i32> [#uses=1]
+ %66 = add i32 %asmtmp552, -899497514 ; <i32> [#uses=1]
+ %67 = add i32 %66, %65 ; <i32> [#uses=1]
+ %68 = add i32 %67, %asmtmp559 ; <i32> [#uses=1]
+ %69 = add i32 %68, 0 ; <i32> [#uses=1]
+ %70 = add i32 %69, 0 ; <i32> [#uses=1]
+ store i32 %70, i32* null, align 4
+ %71 = add i32 0, %60 ; <i32> [#uses=1]
+ store i32 %71, i32* null, align 4
+ %72 = add i32 0, %asmtmp561 ; <i32> [#uses=1]
+ store i32 %72, i32* null, align 4
+ %73 = add i32 0, %asmtmp555 ; <i32> [#uses=1]
+ store i32 %73, i32* null, align 4
+ br label %bb
+}
diff --git a/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll b/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
new file mode 100644
index 0000000..abbe97a
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
@@ -0,0 +1,31 @@
+; RUN: llc -mtriple=i386-apple-darwin10.0 -relocation-model=pic -asm-verbose=false \
+; RUN: -disable-fp-elim -mattr=-sse41,-sse3,+sse2 -post-RA-scheduler=false < %s | \
+; RUN: FileCheck %s
+; rdar://6808032
+
+; CHECK: pextrw $14
+; CHECK-NEXT: movzbl
+; CHECK-NEXT: (%ebp)
+; CHECK-NEXT: pinsrw
+
+define void @update(i8** %args_list) nounwind {
+entry:
+ %cmp.i = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br i1 %cmp.i, label %if.then.i, label %test_cl.exit
+
+if.then.i: ; preds = %entry
+ %val = load <16 x i8> addrspace(1)* null ; <<16 x i8>> [#uses=8]
+ %tmp10.i = shufflevector <16 x i8> <i8 0, i8 0, i8 0, i8 undef, i8 0, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef>, <16 x i8> %val, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 4, i32 undef, i32 6, i32 undef, i32 29, i32 undef, i32 10, i32 11, i32 12, i32 undef, i32 undef, i32 undef> ; <<16 x i8>> [#uses=1]
+ %tmp17.i = shufflevector <16 x i8> %tmp10.i, <16 x i8> %val, <16 x i32> <i32 0, i32 1, i32 2, i32 18, i32 4, i32 undef, i32 6, i32 undef, i32 8, i32 undef, i32 10, i32 11, i32 12, i32 undef, i32 undef, i32 undef> ; <<16 x i8>> [#uses=1]
+ %tmp24.i = shufflevector <16 x i8> %tmp17.i, <16 x i8> %val, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 24, i32 6, i32 undef, i32 8, i32 undef, i32 10, i32 11, i32 12, i32 undef, i32 undef, i32 undef> ; <<16 x i8>> [#uses=1]
+ %tmp31.i = shufflevector <16 x i8> %tmp24.i, <16 x i8> %val, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 undef, i32 8, i32 undef, i32 10, i32 11, i32 12, i32 21, i32 undef, i32 undef> ; <<16 x i8>> [#uses=1]
+ %tmp38.i = shufflevector <16 x i8> %tmp31.i, <16 x i8> %val, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 27, i32 8, i32 undef, i32 10, i32 11, i32 12, i32 13, i32 undef, i32 undef> ; <<16 x i8>> [#uses=1]
+ %tmp45.i = shufflevector <16 x i8> %tmp38.i, <16 x i8> %val, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 undef, i32 10, i32 11, i32 12, i32 13, i32 29, i32 undef> ; <<16 x i8>> [#uses=1]
+ %tmp52.i = shufflevector <16 x i8> %tmp45.i, <16 x i8> %val, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 21, i32 10, i32 11, i32 12, i32 13, i32 14, i32 undef> ; <<16 x i8>> [#uses=1]
+ %tmp59.i = shufflevector <16 x i8> %tmp52.i, <16 x i8> %val, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 20> ; <<16 x i8>> [#uses=1]
+ store <16 x i8> %tmp59.i, <16 x i8> addrspace(1)* null
+ ret void
+
+test_cl.exit: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-04-24.ll b/test/CodeGen/X86/2009-04-24.ll
new file mode 100644
index 0000000..c1ec45f
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-24.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -regalloc=local -relocation-model=pic > %t
+; RUN: grep {leal.*TLSGD.*___tls_get_addr} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=local -relocation-model=pic > %t2
+; RUN: grep {leaq.*TLSGD.*__tls_get_addr} %t2
+; PR4004
+
+@i = thread_local global i32 15
+
+define i32 @f() {
+entry:
+ %tmp1 = load i32* @i
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/X86/2009-04-25-CoalescerBug.ll b/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
new file mode 100644
index 0000000..94d3eb2
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-25-CoalescerBug.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86-64 | grep mov | count 2
+; rdar://6806252
+
+define i64 @test(i32* %tmp13) nounwind {
+entry:
+ br label %while.cond
+
+while.cond: ; preds = %while.cond, %entry
+ %tmp15 = load i32* %tmp13 ; <i32> [#uses=2]
+ %bf.lo = lshr i32 %tmp15, 1 ; <i32> [#uses=1]
+ %bf.lo.cleared = and i32 %bf.lo, 2147483647 ; <i32> [#uses=1]
+ %conv = zext i32 %bf.lo.cleared to i64 ; <i64> [#uses=1]
+ %bf.lo.cleared25 = and i32 %tmp15, 1 ; <i32> [#uses=1]
+ %tobool = icmp ne i32 %bf.lo.cleared25, 0 ; <i1> [#uses=1]
+ br i1 %tobool, label %while.cond, label %while.end
+
+while.end: ; preds = %while.cond
+ ret i64 %conv
+}
diff --git a/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll b/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll
new file mode 100644
index 0000000..7981a52
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-27-CoalescerAssert.ll
@@ -0,0 +1,1457 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
+; PR4034
+
+ %struct.BiContextType = type { i16, i8 }
+ %struct.Bitstream = type { i32, i32, i32, i32, i8*, i32 }
+ %struct.DataPartition = type { %struct.Bitstream*, %struct.DecodingEnvironment, i32 (%struct.SyntaxElement*, %struct.ImageParameters*, %struct.DataPartition*)* }
+ %struct.DecRefPicMarking_t = type { i32, i32, i32, i32, i32, %struct.DecRefPicMarking_t* }
+ %struct.DecodingEnvironment = type { i32, i32, i32, i32, i32, i8*, i32* }
+ %struct.ImageParameters = type { i32, i32, i32, i32, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [16 x [16 x i16]], [6 x [32 x i32]], [16 x [16 x i32]], [4 x [12 x [4 x [4 x i32]]]], [16 x i32], i8**, i32*, i32***, i32**, i32, i32, i32, i32, %struct.Slice*, %struct.Macroblock*, i32, i32, i32, i32, i32, i32, %struct.DecRefPicMarking_t*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32***, i32***, i32****, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x [2 x i32]], [3 x [2 x i32]], i32, i32, i64, i64, %struct.timeb, %struct.timeb, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.Macroblock = type { i32, [2 x i32], i32, i32, %struct.Macroblock*, %struct.Macroblock*, i32, [2 x [4 x [4 x [2 x i32]]]], i32, i64, i64, i32, i32, [4 x i8], [4 x i8], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.MotionInfoContexts = type { [4 x [11 x %struct.BiContextType]], [2 x [9 x %struct.BiContextType]], [2 x [10 x %struct.BiContextType]], [2 x [6 x %struct.BiContextType]], [4 x %struct.BiContextType], [4 x %struct.BiContextType], [3 x %struct.BiContextType] }
+ %struct.PixelPos = type { i32, i32, i32, i32, i32, i32 }
+ %struct.Slice = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.DataPartition*, %struct.MotionInfoContexts*, %struct.TextureInfoContexts*, i32, i32*, i32*, i32*, i32, i32*, i32*, i32*, i32 (%struct.ImageParameters*, %struct.inp_par*)*, i32, i32, i32, i32 }
+ %struct.SyntaxElement = type { i32, i32, i32, i32, i32, i32, i32, i32, void (i32, i32, i32*, i32*)*, void (%struct.SyntaxElement*, %struct.ImageParameters*, %struct.DecodingEnvironment*)* }
+ %struct.TextureInfoContexts = type { [2 x %struct.BiContextType], [4 x %struct.BiContextType], [3 x [4 x %struct.BiContextType]], [10 x [4 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [5 x %struct.BiContextType]], [10 x [5 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]], [10 x [15 x %struct.BiContextType]] }
+ %struct.inp_par = type { [1000 x i8], [1000 x i8], [1000 x i8], i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.timeb = type { i64, i16, i16, i16 }
+@get_mb_block_pos = external global void (i32, i32*, i32*)* ; <void (i32, i32*, i32*)**> [#uses=1]
+@img = external global %struct.ImageParameters* ; <%struct.ImageParameters**> [#uses=14]
[email protected] = appending global [1 x i8*] [i8* bitcast (void (i32, i32, i32, i32, %struct.PixelPos*)* @getAffNeighbour to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define void @getAffNeighbour(i32 %curr_mb_nr, i32 %xN, i32 %yN, i32 %is_chroma, %struct.PixelPos* %pix) nounwind {
+entry:
+ %Opq.sa.calc = add i32 0, 2 ; <i32> [#uses=2]
+ %0 = load %struct.ImageParameters** @img, align 8 ; <%struct.ImageParameters*> [#uses=3]
+ %1 = getelementptr %struct.ImageParameters* %0, i64 0, i32 39 ; <%struct.Macroblock**> [#uses=1]
+ %2 = load %struct.Macroblock** %1, align 8 ; <%struct.Macroblock*> [#uses=24]
+ %3 = zext i32 %curr_mb_nr to i64 ; <i64> [#uses=24]
+ %4 = sext i32 %is_chroma to i64 ; <i64> [#uses=8]
+ br label %meshBB392
+
+entry.fragment: ; preds = %meshBB392
+ %Opq.sa.calc747 = add i32 %Opq.sa.calc921, 70 ; <i32> [#uses=0]
+ %5 = getelementptr %struct.ImageParameters* %0, i64 0, i32 119, i64 %4, i64 0 ; <i32*> [#uses=1]
+ %6 = load i32* %5, align 4 ; <i32> [#uses=2]
+ %7 = getelementptr %struct.ImageParameters* %0, i64 0, i32 119, i64 %4, i64 1 ; <i32*> [#uses=1]
+ %8 = load i32* %7, align 4 ; <i32> [#uses=5]
+ br label %entry.fragment181
+
+entry.fragment181: ; preds = %entry.fragment
+ %Opq.sa.calc863 = add i32 %Opq.sa.calc921, -50 ; <i32> [#uses=4]
+ %9 = getelementptr %struct.PixelPos* %pix, i64 0, i32 0 ; <i32*> [#uses=4]
+ store i32 0, i32* %9, align 4
+ %10 = add i32 %8, -1 ; <i32> [#uses=6]
+ %11 = icmp slt i32 %10, %yN ; <i1> [#uses=1]
+ br i1 %11, label %meshBB448, label %bb
+
+bb: ; preds = %entry.fragment181
+ %Opq.sa.calc460 = add i32 %Opq.sa.calc863, 50 ; <i32> [#uses=0]
+ %12 = add i32 %6, -1 ; <i32> [#uses=5]
+ %13 = icmp slt i32 %12, %xN ; <i1> [#uses=1]
+ br label %bb.fragment
+
+bb.fragment: ; preds = %bb
+ %Opq.sa.calc976 = add i32 %Opq.sa.calc863, 13 ; <i32> [#uses=3]
+ %.not8 = icmp sgt i32 %yN, -1 ; <i1> [#uses=1]
+ %14 = icmp sgt i32 %8, %yN ; <i1> [#uses=1]
+ %or.cond.not = and i1 %14, %.not8 ; <i1> [#uses=3]
+ %or.cond1 = and i1 %or.cond.not, %13 ; <i1> [#uses=1]
+ br i1 %or.cond1, label %meshBB396, label %bb3
+
+bb3: ; preds = %bb.fragment
+ %Opq.sa.calc462 = sub i32 %Opq.sa.calc976, -152 ; <i32> [#uses=5]
+ %Opq.sa.calc461 = sub i32 %Opq.sa.calc462, 168 ; <i32> [#uses=2]
+ %15 = icmp slt i32 %xN, 0 ; <i1> [#uses=1]
+ br i1 %15, label %bb4, label %meshBB404
+
+bb4: ; preds = %bb3
+ %Opq.sa.calc467 = xor i32 %Opq.sa.calc462, 171 ; <i32> [#uses=2]
+ %Opq.sa.calc465 = sub i32 %Opq.sa.calc467, %Opq.sa.calc462 ; <i32> [#uses=1]
+ %Opq.sa.calc466 = xor i32 %Opq.sa.calc465, -164 ; <i32> [#uses=1]
+ %16 = icmp slt i32 %yN, 0 ; <i1> [#uses=1]
+ br i1 %16, label %meshBB428, label %meshBB392
+
+bb5: ; preds = %meshBB428
+ %Opq.sa.calc470 = sub i32 %Opq.sa.calc897, -49 ; <i32> [#uses=1]
+ %17 = getelementptr %struct.Macroblock* %2, i64 %3, i32 20 ; <i32*> [#uses=1]
+ %18 = load i32* %17, align 4 ; <i32> [#uses=1]
+ br label %bb5.fragment
+
+bb5.fragment: ; preds = %bb5
+ %Opq.sa.calc873 = sub i32 %Opq.sa.calc470, 169 ; <i32> [#uses=7]
+ %19 = icmp eq i32 %18, 0 ; <i1> [#uses=1]
+ %20 = and i32 %curr_mb_nr, 1 ; <i32> [#uses=1]
+ %21 = icmp eq i32 %20, 0 ; <i1> [#uses=2]
+ br i1 %19, label %bb6, label %bb13
+
+bb6: ; preds = %bb5.fragment
+ %Opq.sa.calc473 = xor i32 %Opq.sa.calc873, 81 ; <i32> [#uses=1]
+ br i1 %21, label %bb7, label %meshBB348
+
+bb7: ; preds = %bb6
+ %Opq.sa.calc476 = add i32 %Opq.sa.calc873, -58 ; <i32> [#uses=1]
+ %22 = getelementptr %struct.Macroblock* %2, i64 %3, i32 25 ; <i32*> [#uses=1]
+ %23 = load i32* %22, align 8 ; <i32> [#uses=1]
+ %24 = add i32 %23, 1 ; <i32> [#uses=1]
+ %25 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=1]
+ br label %meshBB388
+
+bb7.fragment: ; preds = %meshBB388
+ %Opq.sa.calc709 = sub i32 %Opq.sa.calc886, 143 ; <i32> [#uses=1]
+ %Opq.sa.calc707 = add i32 %Opq.sa.calc709, %Opq.sa.calc886 ; <i32> [#uses=1]
+ %Opq.sa.calc708 = xor i32 %Opq.sa.calc707, 474 ; <i32> [#uses=0]
+ store i32 %.SV194.phi, i32* %.SV196.phi, align 4
+ %26 = getelementptr %struct.Macroblock* %.load17.SV.phi, i64 %.load36.SV.phi, i32 29 ; <i32*> [#uses=1]
+ %27 = load i32* %26, align 8 ; <i32> [#uses=2]
+ store i32 %27, i32* %.load67.SV.phi, align 4
+ br label %bb96
+
+bb8: ; preds = %meshBB348
+ %Opq.sa.calc479 = sub i32 %Opq.sa.calc805, 141 ; <i32> [#uses=1]
+ %28 = getelementptr %struct.Macroblock* %2, i64 %3, i32 22 ; <i32*> [#uses=2]
+ %29 = load i32* %28, align 4 ; <i32> [#uses=2]
+ %30 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=2]
+ br label %meshBB368
+
+bb8.fragment: ; preds = %meshBB368
+ %Opq.sa.calc765 = sub i32 %Opq.sa.calc768, -115 ; <i32> [#uses=2]
+ store i32 %.SV198.phi, i32* %.SV200.phi, align 4
+ %31 = getelementptr %struct.Macroblock* %.load16.SV.phi, i64 %.load35.SV.phi, i32 26 ; <i32*> [#uses=2]
+ %32 = load i32* %31, align 4 ; <i32> [#uses=4]
+ store i32 %32, i32* %.load66.SV.phi, align 4
+ %33 = load i32* %31, align 4 ; <i32> [#uses=1]
+ %34 = icmp eq i32 %33, 0 ; <i1> [#uses=1]
+ br i1 %34, label %bb96, label %bb9
+
+bb9: ; preds = %bb8.fragment
+ %Opq.sa.calc482 = xor i32 %Opq.sa.calc765, 163 ; <i32> [#uses=0]
+ %35 = load %struct.ImageParameters** @img, align 8 ; <%struct.ImageParameters*> [#uses=1]
+ %36 = getelementptr %struct.ImageParameters* %35, i64 0, i32 39 ; <%struct.Macroblock**> [#uses=1]
+ %37 = load %struct.Macroblock** %36, align 8 ; <%struct.Macroblock*> [#uses=1]
+ %38 = load i32* %.SV76.phi, align 4 ; <i32> [#uses=1]
+ br label %bb9.fragment
+
+bb9.fragment: ; preds = %bb9
+ %Opq.sa.calc999 = add i32 %Opq.sa.calc765, -44 ; <i32> [#uses=1]
+ %39 = sext i32 %38 to i64 ; <i64> [#uses=1]
+ %40 = getelementptr %struct.Macroblock* %37, i64 %39, i32 20 ; <i32*> [#uses=1]
+ %41 = load i32* %40, align 4 ; <i32> [#uses=1]
+ %42 = icmp eq i32 %41, 0 ; <i1> [#uses=1]
+ br i1 %42, label %bb96, label %bb11
+
+bb11: ; preds = %bb9.fragment
+ %Opq.sa.calc485 = sub i32 %Opq.sa.calc999, 200 ; <i32> [#uses=2]
+ %43 = add i32 %.SV78.phi, 1 ; <i32> [#uses=1]
+ br label %meshBB332
+
+bb11.fragment: ; preds = %meshBB332
+ %Opq.sa.calc954 = xor i32 %Opq.link.mask859, 233 ; <i32> [#uses=0]
+ store i32 %.SV206.phi, i32* %.load81.SV.phi, align 4
+ %44 = add i32 %.load50.SV.phi, %yN ; <i32> [#uses=1]
+ %45 = ashr i32 %44, 1 ; <i32> [#uses=1]
+ br label %bb96
+
+bb13: ; preds = %bb5.fragment
+ %Opq.sa.calc490 = xor i32 %Opq.sa.calc873, 175 ; <i32> [#uses=1]
+ %Opq.sa.calc488 = sub i32 %Opq.sa.calc490, %Opq.sa.calc873 ; <i32> [#uses=1]
+ %Opq.sa.calc489 = sub i32 %Opq.sa.calc488, 133 ; <i32> [#uses=1]
+ %46 = getelementptr %struct.Macroblock* %2, i64 %3, i32 25 ; <i32*> [#uses=1]
+ br label %meshBB360
+
+bb13.fragment: ; preds = %meshBB360
+ %Opq.sa.calc870 = add i32 %Opq.sa.calc866, -129 ; <i32> [#uses=3]
+ %47 = load i32* %.SV208.phi, align 8 ; <i32> [#uses=3]
+ br i1 %.load74.SV.phi, label %bb14, label %meshBB412
+
+bb14: ; preds = %bb13.fragment
+ %Opq.sa.calc493 = add i32 %Opq.sa.calc870, 103 ; <i32> [#uses=1]
+ %48 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=2]
+ store i32 %47, i32* %48, align 4
+ %49 = getelementptr %struct.Macroblock* %2, i64 %3, i32 29 ; <i32*> [#uses=2]
+ br label %bb14.fragment
+
+bb14.fragment: ; preds = %bb14
+ %Opq.sa.calc723 = sub i32 %Opq.sa.calc493, 117 ; <i32> [#uses=4]
+ %50 = load i32* %49, align 8 ; <i32> [#uses=4]
+ store i32 %50, i32* %.SV52.phi1113, align 4
+ %51 = load i32* %49, align 8 ; <i32> [#uses=1]
+ %52 = icmp eq i32 %51, 0 ; <i1> [#uses=1]
+ br i1 %52, label %meshBB, label %bb15
+
+bb15: ; preds = %bb14.fragment
+ %Opq.sa.calc496 = sub i32 %Opq.sa.calc723, -8 ; <i32> [#uses=1]
+ %53 = load %struct.ImageParameters** @img, align 8 ; <%struct.ImageParameters*> [#uses=1]
+ %54 = getelementptr %struct.ImageParameters* %53, i64 0, i32 39 ; <%struct.Macroblock**> [#uses=1]
+ %55 = load %struct.Macroblock** %54, align 8 ; <%struct.Macroblock*> [#uses=1]
+ %56 = load i32* %.SV208.phi, align 8 ; <i32> [#uses=1]
+ br label %meshBB324
+
+bb15.fragment: ; preds = %meshBB324
+ %Opq.sa.calc925 = xor i32 %Opq.sa.calc750, 215 ; <i32> [#uses=2]
+ %57 = sext i32 %.SV214.phi to i64 ; <i64> [#uses=1]
+ %58 = getelementptr %struct.Macroblock* %.SV212.phi, i64 %57, i32 20 ; <i32*> [#uses=1]
+ %59 = load i32* %58, align 4 ; <i32> [#uses=1]
+ %60 = icmp eq i32 %59, 0 ; <i1> [#uses=1]
+ br i1 %60, label %bb16, label %bb96
+
+bb16: ; preds = %bb15.fragment
+ %Opq.sa.calc499 = sub i32 %Opq.sa.calc925, -140 ; <i32> [#uses=0]
+ %61 = add i32 %.SV87.phi, 1 ; <i32> [#uses=1]
+ br label %bb16.fragment
+
+bb16.fragment: ; preds = %bb16
+ %Opq.sa.calc968 = add i32 %Opq.sa.calc925, 129 ; <i32> [#uses=0]
+ store i32 %61, i32* %.SV91.phi, align 4
+ %62 = shl i32 %yN, 1 ; <i32> [#uses=1]
+ br label %bb96
+
+bb19: ; preds = %meshBB412
+ %Opq.sa.calc502 = sub i32 %Opq.sa.calc932, -94 ; <i32> [#uses=0]
+ %63 = add i32 %.SV87.phi1030, 1 ; <i32> [#uses=1]
+ %64 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=1]
+ br label %bb19.fragment
+
+bb19.fragment: ; preds = %bb19
+ %Opq.sa.calc880 = xor i32 %Opq.sa.calc932, 246 ; <i32> [#uses=0]
+ store i32 %63, i32* %64, align 4
+ %65 = getelementptr %struct.Macroblock* %2, i64 %3, i32 29 ; <i32*> [#uses=1]
+ %66 = load i32* %65, align 8 ; <i32> [#uses=2]
+ store i32 %66, i32* %.SV52.phi1186, align 4
+ br label %bb96
+
+bb21: ; preds = %meshBB392
+ %Opq.sa.calc505 = add i32 %Opq.sa.calc921, -40 ; <i32> [#uses=2]
+ br i1 %or.cond.not.SV.phi, label %meshBB360, label %bb97
+
+bb23: ; preds = %meshBB360
+ %Opq.sa.calc509 = xor i32 %Opq.sa.calc866, 70 ; <i32> [#uses=1]
+ %Opq.sa.calc508 = sub i32 %Opq.sa.calc509, -19 ; <i32> [#uses=0]
+ %67 = getelementptr %struct.Macroblock* %2, i64 %3, i32 20 ; <i32*> [#uses=1]
+ %68 = load i32* %67, align 4 ; <i32> [#uses=1]
+ %69 = icmp eq i32 %68, 0 ; <i1> [#uses=1]
+ %70 = and i32 %curr_mb_nr, 1 ; <i32> [#uses=1]
+ %71 = icmp eq i32 %70, 0 ; <i1> [#uses=2]
+ br label %bb23.fragment
+
+bb23.fragment: ; preds = %bb23
+ %Opq.sa.calc847 = sub i32 %Opq.sa.calc866, -9 ; <i32> [#uses=2]
+ %72 = getelementptr %struct.Macroblock* %2, i64 %3, i32 22 ; <i32*> [#uses=3]
+ %73 = load i32* %72, align 4 ; <i32> [#uses=3]
+ %74 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=3]
+ store i32 %73, i32* %74, align 4
+ br label %bb23.fragment182
+
+bb23.fragment182: ; preds = %bb23.fragment
+ %Opq.sa.calc744 = xor i32 %Opq.sa.calc847, 152 ; <i32> [#uses=4]
+ %Opq.sa.calc742 = add i32 %Opq.sa.calc744, %Opq.sa.calc847 ; <i32> [#uses=1]
+ %Opq.sa.calc743 = add i32 %Opq.sa.calc742, -149 ; <i32> [#uses=2]
+ %75 = getelementptr %struct.Macroblock* %2, i64 %3, i32 26 ; <i32*> [#uses=2]
+ %76 = load i32* %75, align 4 ; <i32> [#uses=3]
+ store i32 %76, i32* %.SV52.phi1113, align 4
+ %77 = load i32* %75, align 4 ; <i32> [#uses=1]
+ %78 = icmp ne i32 %77, 0 ; <i1> [#uses=2]
+ br i1 %69, label %meshBB344, label %meshBB432
+
+bb24: ; preds = %meshBB344
+ %Opq.sa.calc512 = add i32 %Opq.sa.calc716, -55 ; <i32> [#uses=3]
+ br i1 %.SV96.phi, label %bb25, label %bb32
+
+bb25: ; preds = %bb24
+ %Opq.sa.calc515 = sub i32 %Opq.sa.calc716, 18 ; <i32> [#uses=1]
+ br i1 %.SV135.phi, label %bb26, label %bb96
+
+bb26: ; preds = %bb25
+ %Opq.sa.calc519 = xor i32 %Opq.sa.calc515, 23 ; <i32> [#uses=2]
+ %Opq.sa.calc518 = xor i32 %Opq.sa.calc519, 84 ; <i32> [#uses=1]
+ %79 = load %struct.ImageParameters** @img, align 8 ; <%struct.ImageParameters*> [#uses=1]
+ %80 = getelementptr %struct.ImageParameters* %79, i64 0, i32 39 ; <%struct.Macroblock**> [#uses=1]
+ %81 = load %struct.Macroblock** %80, align 8 ; <%struct.Macroblock*> [#uses=1]
+ %82 = load i32* %.SV99.phi, align 4 ; <i32> [#uses=1]
+ br label %meshBB340
+
+bb26.fragment: ; preds = %meshBB340
+ %Opq.sa.calc918 = xor i32 %Opq.sa.calc754, 228 ; <i32> [#uses=4]
+ %Opq.sa.calc916 = add i32 %Opq.sa.calc918, %Opq.sa.calc754 ; <i32> [#uses=1]
+ %Opq.sa.calc917 = add i32 %Opq.sa.calc916, -237 ; <i32> [#uses=1]
+ %83 = sext i32 %.SV230.phi to i64 ; <i64> [#uses=1]
+ %84 = getelementptr %struct.Macroblock* %.SV228.phi, i64 %83, i32 20 ; <i32*> [#uses=1]
+ %85 = load i32* %84, align 4 ; <i32> [#uses=1]
+ %86 = icmp eq i32 %85, 0 ; <i1> [#uses=1]
+ br i1 %86, label %meshBB420, label %meshBB356
+
+bb28: ; preds = %meshBB356
+ %Opq.sa.calc522 = xor i32 %Opq.sa.calc983, 107 ; <i32> [#uses=2]
+ %87 = and i32 %yN, 1 ; <i32> [#uses=1]
+ %88 = icmp eq i32 %87, 0 ; <i1> [#uses=1]
+ br i1 %88, label %bb29, label %bb30
+
+bb29: ; preds = %bb28
+ %Opq.sa.calc525 = xor i32 %Opq.sa.calc522, 151 ; <i32> [#uses=2]
+ %89 = ashr i32 %yN, 1 ; <i32> [#uses=1]
+ br label %meshBB340
+
+bb30: ; preds = %bb28
+ %Opq.sa.calc528 = sub i32 %Opq.sa.calc522, -64 ; <i32> [#uses=1]
+ %90 = add i32 %.SV104.phi1160, 1 ; <i32> [#uses=1]
+ br label %bb30.fragment
+
+bb30.fragment: ; preds = %bb30
+ %Opq.sa.calc791 = add i32 %Opq.sa.calc528, -14 ; <i32> [#uses=0]
+ store i32 %90, i32* %.SV111.phi1159, align 4
+ %91 = ashr i32 %yN, 1 ; <i32> [#uses=1]
+ br label %bb96
+
+bb32: ; preds = %bb24
+ %Opq.sa.calc531 = xor i32 %Opq.sa.calc512, 50 ; <i32> [#uses=1]
+ br i1 %.SV135.phi, label %bb33, label %meshBB324
+
+bb33: ; preds = %bb32
+ %Opq.sa.calc534 = sub i32 %Opq.sa.calc512, -75 ; <i32> [#uses=2]
+ %92 = load %struct.ImageParameters** @img, align 8 ; <%struct.ImageParameters*> [#uses=1]
+ %93 = getelementptr %struct.ImageParameters* %92, i64 0, i32 39 ; <%struct.Macroblock**> [#uses=1]
+ %94 = load %struct.Macroblock** %93, align 8 ; <%struct.Macroblock*> [#uses=1]
+ %95 = load i32* %.SV99.phi, align 4 ; <i32> [#uses=1]
+ br label %bb33.fragment
+
+bb33.fragment: ; preds = %bb33
+ %Opq.sa.calc712 = add i32 %Opq.sa.calc534, -109 ; <i32> [#uses=3]
+ %96 = sext i32 %95 to i64 ; <i64> [#uses=1]
+ %97 = getelementptr %struct.Macroblock* %94, i64 %96, i32 20 ; <i32*> [#uses=1]
+ %98 = load i32* %97, align 4 ; <i32> [#uses=1]
+ %99 = icmp eq i32 %98, 0 ; <i1> [#uses=1]
+ br i1 %99, label %bb34, label %meshBB
+
+bb34: ; preds = %bb33.fragment
+ %Opq.sa.calc537 = add i32 %Opq.sa.calc712, 8 ; <i32> [#uses=1]
+ %100 = add i32 %.SV104.phi, 1 ; <i32> [#uses=1]
+ br label %meshBB328
+
+bb34.fragment: ; preds = %meshBB328
+ %Opq.sa.calc965 = xor i32 %Opq.sa.calc787, 251 ; <i32> [#uses=0]
+ store i32 %.SV238.phi, i32* %.load116.SV.phi, align 4
+ br label %bb96
+
+bb35: ; preds = %meshBB
+ %Opq.sa.calc541 = add i32 %Opq.sa.calc828, -112 ; <i32> [#uses=3]
+ %Opq.sa.calc540 = xor i32 %Opq.sa.calc541, 3 ; <i32> [#uses=1]
+ %101 = and i32 %yN, 1 ; <i32> [#uses=1]
+ %102 = icmp eq i32 %101, 0 ; <i1> [#uses=1]
+ br i1 %102, label %meshBB372, label %meshBB448
+
+bb36: ; preds = %meshBB372
+ %Opq.sa.calc544 = sub i32 %Opq.sa.calc812, -10 ; <i32> [#uses=0]
+ %103 = add i32 %.SV43.phi1015, %yN ; <i32> [#uses=1]
+ br label %bb36.fragment
+
+bb36.fragment: ; preds = %bb36
+ %Opq.sa.calc762 = add i32 %Opq.sa.calc812, -69 ; <i32> [#uses=0]
+ %104 = ashr i32 %103, 1 ; <i32> [#uses=1]
+ br label %bb96
+
+bb37: ; preds = %meshBB448
+ %Opq.sa.calc547 = add i32 %Opq.sa.calc958, -49 ; <i32> [#uses=1]
+ %105 = add i32 %.SV104.phi1157, 1 ; <i32> [#uses=1]
+ br label %meshBB348
+
+bb37.fragment: ; preds = %meshBB348
+ %Opq.sa.calc728 = add i32 %Opq.sa.calc805, -5 ; <i32> [#uses=0]
+ store i32 %.SV242.phi, i32* %.load115.SV.phi, align 4
+ %106 = add i32 %.load48.SV.phi, %yN ; <i32> [#uses=1]
+ %107 = ashr i32 %106, 1 ; <i32> [#uses=1]
+ br label %bb96
+
+bb39: ; preds = %meshBB432
+ %Opq.sa.calc550 = sub i32 %Opq.sa.calc798, -214 ; <i32> [#uses=0]
+ br i1 %.SV96.phi1038, label %bb40, label %bb48
+
+bb40: ; preds = %bb39
+ %Opq.sa.calc554 = xor i32 %Opq.sa.calc798, 14 ; <i32> [#uses=4]
+ %Opq.sa.calc553 = sub i32 %Opq.sa.calc554, 7 ; <i32> [#uses=1]
+ br i1 %.SV135.phi1039, label %meshBB336, label %meshBB444
+
+bb41: ; preds = %meshBB336
+ %Opq.sa.calc557 = sub i32 %Opq.sa.calc979, 143 ; <i32> [#uses=1]
+ %108 = load %struct.ImageParameters** @img, align 8 ; <%struct.ImageParameters*> [#uses=1]
+ %109 = getelementptr %struct.ImageParameters* %108, i64 0, i32 39 ; <%struct.Macroblock**> [#uses=1]
+ %110 = load %struct.Macroblock** %109, align 8 ; <%struct.Macroblock*> [#uses=1]
+ %111 = load i32* %.SV99.phi1128, align 4 ; <i32> [#uses=1]
+ br label %bb41.fragment
+
+bb41.fragment: ; preds = %bb41
+ %Opq.sa.calc987 = xor i32 %Opq.sa.calc557, 213 ; <i32> [#uses=4]
+ %112 = sext i32 %111 to i64 ; <i64> [#uses=1]
+ %113 = getelementptr %struct.Macroblock* %110, i64 %112, i32 20 ; <i32*> [#uses=1]
+ %114 = load i32* %113, align 4 ; <i32> [#uses=1]
+ %115 = icmp eq i32 %114, 0 ; <i1> [#uses=1]
+ br i1 %115, label %bb42, label %bb96
+
+bb42: ; preds = %bb41.fragment
+ %Opq.sa.calc560 = add i32 %Opq.sa.calc987, -221 ; <i32> [#uses=1]
+ %116 = ashr i32 %.SV43.phi1230, 1 ; <i32> [#uses=1]
+ %117 = icmp sgt i32 %116, %yN ; <i1> [#uses=1]
+ br i1 %117, label %meshBB432, label %bb44
+
+bb43: ; preds = %meshBB432
+ %Opq.sa.calc563 = xor i32 %Opq.sa.calc798, 31 ; <i32> [#uses=0]
+ %118 = shl i32 %yN, 1 ; <i32> [#uses=1]
+ br label %bb96
+
+bb44: ; preds = %bb42
+ %Opq.sa.calc566 = sub i32 %Opq.sa.calc987, 217 ; <i32> [#uses=1]
+ %119 = add i32 %.SV104.phi1127, 1 ; <i32> [#uses=1]
+ br label %meshBB332
+
+bb44.fragment: ; preds = %meshBB332
+ %Opq.sa.calc894 = add i32 %Opq.sa.calc856, -200 ; <i32> [#uses=1]
+ store i32 %.SV248.phi, i32* %.load114.SV.phi, align 4
+ %120 = shl i32 %yN, 1 ; <i32> [#uses=1]
+ %121 = sub i32 %120, %.load46.SV.phi ; <i32> [#uses=1]
+ br label %meshBB376
+
+bb48: ; preds = %bb39
+ %Opq.sa.calc569 = sub i32 %Opq.sa.calc798, -110 ; <i32> [#uses=1]
+ br i1 %.SV135.phi1039, label %bb49, label %bb96
+
+bb49: ; preds = %bb48
+ %Opq.sa.calc572 = add i32 %Opq.sa.calc798, 84 ; <i32> [#uses=0]
+ %122 = load %struct.ImageParameters** @img, align 8 ; <%struct.ImageParameters*> [#uses=1]
+ %123 = getelementptr %struct.ImageParameters* %122, i64 0, i32 39 ; <%struct.Macroblock**> [#uses=1]
+ %124 = load %struct.Macroblock** %123, align 8 ; <%struct.Macroblock*> [#uses=1]
+ %125 = load i32* %.SV99.phi1037, align 4 ; <i32> [#uses=1]
+ br label %bb49.fragment
+
+bb49.fragment: ; preds = %bb49
+ %Opq.sa.calc860 = sub i32 %Opq.sa.calc569, 114 ; <i32> [#uses=5]
+ %126 = sext i32 %125 to i64 ; <i64> [#uses=1]
+ %127 = getelementptr %struct.Macroblock* %124, i64 %126, i32 20 ; <i32*> [#uses=1]
+ %128 = load i32* %127, align 4 ; <i32> [#uses=1]
+ %129 = icmp eq i32 %128, 0 ; <i1> [#uses=1]
+ br i1 %129, label %bb50, label %meshBB380
+
+bb50: ; preds = %bb49.fragment
+ %Opq.sa.calc577 = add i32 %Opq.sa.calc860, 12 ; <i32> [#uses=2]
+ %130 = ashr i32 %.SV43.phi1178, 1 ; <i32> [#uses=1]
+ %131 = icmp sgt i32 %130, %yN ; <i1> [#uses=1]
+ br i1 %131, label %meshBB328, label %bb52
+
+bb51: ; preds = %meshBB328
+ %Opq.sa.calc580 = xor i32 %Opq.sa.calc787, 194 ; <i32> [#uses=0]
+ %132 = shl i32 %yN, 1 ; <i32> [#uses=1]
+ %133 = or i32 %132, 1 ; <i32> [#uses=1]
+ br label %bb96
+
+bb52: ; preds = %bb50
+ %Opq.sa.calc584 = sub i32 %Opq.sa.calc860, -65 ; <i32> [#uses=2]
+ %Opq.sa.calc583 = sub i32 %Opq.sa.calc584, 50 ; <i32> [#uses=1]
+ %134 = add i32 %.SV104.phi1036, 1 ; <i32> [#uses=1]
+ store i32 %134, i32* %.SV111.phi1035, align 4
+ br label %meshBB384
+
+bb52.fragment: ; preds = %meshBB384
+ %Opq.sa.calc844 = add i32 %Opq.sa.calc901, -214 ; <i32> [#uses=1]
+ %135 = shl i32 %yN, 1 ; <i32> [#uses=1]
+ %136 = or i32 %135, 1 ; <i32> [#uses=1]
+ %137 = sub i32 %136, %.load44.SV.phi ; <i32> [#uses=1]
+ br label %meshBB388
+
+bb54: ; preds = %meshBB380
+ %Opq.sa.calc589 = add i32 %Opq.sa.calc946, 108 ; <i32> [#uses=1]
+ %138 = add i32 %.SV104.phi1124, 1 ; <i32> [#uses=1]
+ br label %bb54.fragment
+
+bb54.fragment: ; preds = %bb54
+ %Opq.sa.calc883 = xor i32 %Opq.sa.calc589, 119 ; <i32> [#uses=2]
+ store i32 %138, i32* %.SV111.phi1123, align 4
+ br label %meshBB440
+
+bb56: ; preds = %meshBB404
+ %Opq.sa.calc592 = sub i32 %Opq.sa.calc939, 87 ; <i32> [#uses=2]
+ %.not4 = icmp sgt i32 %xN, -1 ; <i1> [#uses=1]
+ %139 = icmp sgt i32 %.SV40.phi, %xN ; <i1> [#uses=1]
+ br label %meshBB364
+
+bb56.fragment: ; preds = %meshBB364
+ %Opq.sa.calc1002 = xor i32 %Opq.link.mask737, 77 ; <i32> [#uses=6]
+ %or.cond5 = and i1 %.SV256.phi, %.not4.SV.phi ; <i1> [#uses=1]
+ %140 = icmp slt i32 %yN, 0 ; <i1> [#uses=2]
+ br i1 %or.cond5, label %bb58, label %bb83
+
+bb58: ; preds = %bb56.fragment
+ %Opq.sa.calc596 = xor i32 %Opq.sa.calc1002, 73 ; <i32> [#uses=1]
+ %Opq.sa.calc595 = add i32 %Opq.sa.calc596, 147 ; <i32> [#uses=0]
+ br i1 %140, label %bb59, label %bb76
+
+bb59: ; preds = %bb58
+ %Opq.sa.calc599 = add i32 %Opq.sa.calc1002, 151 ; <i32> [#uses=0]
+ %141 = getelementptr %struct.Macroblock* %2, i64 %3, i32 20 ; <i32*> [#uses=1]
+ %142 = load i32* %141, align 4 ; <i32> [#uses=1]
+ br label %bb59.fragment
+
+bb59.fragment: ; preds = %bb59
+ %Opq.sa.calc731 = sub i32 %Opq.sa.calc1002, -161 ; <i32> [#uses=3]
+ %143 = icmp eq i32 %142, 0 ; <i1> [#uses=1]
+ %144 = and i32 %curr_mb_nr, 1 ; <i32> [#uses=1]
+ %145 = icmp eq i32 %144, 0 ; <i1> [#uses=2]
+ br i1 %143, label %bb60, label %bb68
+
+bb60: ; preds = %bb59.fragment
+ %Opq.sa.calc602 = xor i32 %Opq.sa.calc731, 1 ; <i32> [#uses=2]
+ br i1 %145, label %bb61, label %bb66
+
+bb61: ; preds = %bb60
+ %Opq.sa.calc605 = xor i32 %Opq.sa.calc731, 57 ; <i32> [#uses=1]
+ %146 = getelementptr %struct.Macroblock* %2, i64 %3, i32 23 ; <i32*> [#uses=2]
+ %147 = load i32* %146, align 8 ; <i32> [#uses=3]
+ %148 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=3]
+ br label %bb61.fragment
+
+bb61.fragment: ; preds = %bb61
+ %Opq.sa.calc700 = sub i32 %Opq.sa.calc605, 108 ; <i32> [#uses=3]
+ store i32 %147, i32* %148, align 4
+ %149 = getelementptr %struct.Macroblock* %2, i64 %3, i32 27 ; <i32*> [#uses=4]
+ %150 = load i32* %149, align 8 ; <i32> [#uses=1]
+ %151 = icmp eq i32 %150, 0 ; <i1> [#uses=1]
+ br i1 %151, label %bb65, label %bb62
+
+bb62: ; preds = %bb61.fragment
+ %Opq.sa.calc608 = add i32 %Opq.sa.calc700, -94 ; <i32> [#uses=1]
+ %152 = load %struct.ImageParameters** @img, align 8 ; <%struct.ImageParameters*> [#uses=2]
+ %153 = getelementptr %struct.ImageParameters* %152, i64 0, i32 45 ; <i32*> [#uses=1]
+ %154 = load i32* %153, align 4 ; <i32> [#uses=1]
+ %155 = icmp eq i32 %154, 1 ; <i1> [#uses=1]
+ br i1 %155, label %bb63, label %bb64
+
+bb63: ; preds = %bb62
+ %Opq.sa.calc611 = add i32 %Opq.sa.calc700, -101 ; <i32> [#uses=2]
+ %156 = getelementptr %struct.ImageParameters* %152, i64 0, i32 39 ; <%struct.Macroblock**> [#uses=1]
+ %157 = load %struct.Macroblock** %156, align 8 ; <%struct.Macroblock*> [#uses=1]
+ %158 = load i32* %146, align 8 ; <i32> [#uses=1]
+ br label %meshBB452
+
+bb63.fragment: ; preds = %meshBB452
+ %Opq.sa.calc891 = add i32 %Opq.link.mask823, 18 ; <i32> [#uses=2]
+ %Opq.sa.calc890 = add i32 %Opq.sa.calc891, -3 ; <i32> [#uses=2]
+ %159 = sext i32 %.SV266.phi to i64 ; <i64> [#uses=1]
+ %160 = getelementptr %struct.Macroblock* %.SV264.phi, i64 %159, i32 20 ; <i32*> [#uses=1]
+ %161 = load i32* %160, align 4 ; <i32> [#uses=1]
+ %162 = icmp eq i32 %161, 0 ; <i1> [#uses=1]
+ br i1 %162, label %bb64, label %meshBB456
+
+bb64: ; preds = %bb63.fragment, %bb62
+ %.SV38.phi1132 = phi i64 [ %.SV38.phi1110, %bb63.fragment ], [ %.SV38.phi1098, %bb62 ] ; <i64> [#uses=1]
+ %.SV52.phi1131 = phi i32* [ %.SV52.phi1109, %bb63.fragment ], [ %.SV52.phi1097, %bb62 ] ; <i32*> [#uses=1]
+ %.SV68.phi1130 = phi i32 [ %.SV68.phi1108, %bb63.fragment ], [ %.SV68.phi1096, %bb62 ] ; <i32> [#uses=1]
+ %.SV70.phi1129 = phi i32 [ %.SV70.phi1107, %bb63.fragment ], [ %.SV70.phi1095, %bb62 ] ; <i32> [#uses=1]
+ %Opq.link.SV615.phi = phi i32 [ %Opq.sa.calc890, %bb63.fragment ], [ %Opq.sa.calc608, %bb62 ] ; <i32> [#uses=1]
+ %.SV150.phi = phi i32* [ %.SV150.phi1060, %bb63.fragment ], [ %148, %bb62 ] ; <i32*> [#uses=1]
+ %.SV152.phi = phi i32* [ %.SV152.phi1059, %bb63.fragment ], [ %149, %bb62 ] ; <i32*> [#uses=1]
+ %.SV148.phi = phi i32 [ %.SV148.phi1057, %bb63.fragment ], [ %147, %bb62 ] ; <i32> [#uses=1]
+ %Opq.link.mask = and i32 %Opq.link.SV615.phi, 1 ; <i32> [#uses=1]
+ %Opq.sa.calc614 = add i32 %Opq.link.mask, 189 ; <i32> [#uses=1]
+ %163 = add i32 %.SV148.phi, 1 ; <i32> [#uses=1]
+ store i32 %163, i32* %.SV150.phi, align 4
+ br label %bb65
+
+bb65: ; preds = %meshBB456, %bb64, %bb61.fragment
+ %.SV38.phi1144 = phi i64 [ %.SV38.phi1137, %meshBB456 ], [ %.SV38.phi1098, %bb61.fragment ], [ %.SV38.phi1132, %bb64 ] ; <i64> [#uses=1]
+ %.SV52.phi1143 = phi i32* [ %.SV52.phi1136, %meshBB456 ], [ %.SV52.phi1097, %bb61.fragment ], [ %.SV52.phi1131, %bb64 ] ; <i32*> [#uses=1]
+ %.SV68.phi1142 = phi i32 [ %.SV68.phi1135, %meshBB456 ], [ %.SV68.phi1096, %bb61.fragment ], [ %.SV68.phi1130, %bb64 ] ; <i32> [#uses=1]
+ %.SV70.phi1141 = phi i32 [ %.SV70.phi1134, %meshBB456 ], [ %.SV70.phi1095, %bb61.fragment ], [ %.SV70.phi1129, %bb64 ] ; <i32> [#uses=1]
+ %.SV152.phi1058 = phi i32* [ %.SV152.phi1133, %meshBB456 ], [ %149, %bb61.fragment ], [ %.SV152.phi, %bb64 ] ; <i32*> [#uses=1]
+ %Opq.link.SV618.phi = phi i32 [ %Opq.sa.calc816, %meshBB456 ], [ %Opq.sa.calc700, %bb61.fragment ], [ %Opq.sa.calc614, %bb64 ] ; <i32> [#uses=1]
+ %Opq.link.mask620 = and i32 %Opq.link.SV618.phi, 40 ; <i32> [#uses=1]
+ %Opq.sa.calc617 = add i32 %Opq.link.mask620, -35 ; <i32> [#uses=2]
+ %164 = load i32* %.SV152.phi1058, align 8 ; <i32> [#uses=1]
+ br label %meshBB436
+
+bb65.fragment: ; preds = %meshBB436
+ %Opq.sa.calc832 = add i32 %Opq.link.mask706, 1 ; <i32> [#uses=2]
+ store i32 %.SV268.phi, i32* %.load62.SV.phi, align 4
+ br label %meshBB364
+
+bb66: ; preds = %bb60
+ %Opq.sa.calc621 = add i32 %Opq.sa.calc602, -217 ; <i32> [#uses=1]
+ %165 = add i32 %curr_mb_nr, -1 ; <i32> [#uses=1]
+ %166 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=1]
+ br label %meshBB420
+
+bb66.fragment: ; preds = %meshBB420
+ %Opq.sa.calc795 = xor i32 %Opq.sa.calc837, 105 ; <i32> [#uses=2]
+ %Opq.sa.calc794 = sub i32 %Opq.sa.calc795, 167 ; <i32> [#uses=1]
+ store i32 %.SV270.phi, i32* %.SV272.phi, align 4
+ store i32 1, i32* %.load61.SV.phi, align 4
+ br label %meshBB444
+
+bb68: ; preds = %bb59.fragment
+ %Opq.sa.calc624 = sub i32 %Opq.sa.calc731, 229 ; <i32> [#uses=3]
+ %167 = getelementptr %struct.Macroblock* %2, i64 %3, i32 23 ; <i32*> [#uses=1]
+ br label %meshBB344
+
+bb68.fragment: ; preds = %meshBB344
+ %Opq.sa.calc784 = sub i32 %Opq.link.mask722, 3 ; <i32> [#uses=5]
+ %168 = load i32* %.SV274.phi, align 8 ; <i32> [#uses=3]
+ br i1 %.load144.SV.phi, label %bb69, label %meshBB412
+
+bb69: ; preds = %bb68.fragment
+ %Opq.sa.calc627 = add i32 %Opq.sa.calc784, 163 ; <i32> [#uses=0]
+ %169 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=2]
+ store i32 %168, i32* %169, align 4
+ %170 = getelementptr %struct.Macroblock* %2, i64 %3, i32 27 ; <i32*> [#uses=2]
+ br label %bb69.fragment
+
+bb69.fragment: ; preds = %bb69
+ %Opq.sa.calc996 = sub i32 %Opq.sa.calc784, -9 ; <i32> [#uses=3]
+ %Opq.sa.calc994 = sub i32 %Opq.sa.calc996, %Opq.sa.calc784 ; <i32> [#uses=1]
+ %Opq.sa.calc995 = sub i32 %Opq.sa.calc994, 3 ; <i32> [#uses=2]
+ %171 = load i32* %170, align 8 ; <i32> [#uses=3]
+ store i32 %171, i32* %.SV52.phi1170, align 4
+ %172 = load i32* %170, align 8 ; <i32> [#uses=1]
+ %173 = icmp eq i32 %172, 0 ; <i1> [#uses=1]
+ br i1 %173, label %meshBB396, label %meshBB400
+
+bb70: ; preds = %meshBB400
+ %Opq.sa.calc630 = add i32 %Opq.sa.calc824, -203 ; <i32> [#uses=2]
+ %174 = load %struct.ImageParameters** @img, align 8 ; <%struct.ImageParameters*> [#uses=1]
+ %175 = getelementptr %struct.ImageParameters* %174, i64 0, i32 39 ; <%struct.Macroblock**> [#uses=1]
+ %176 = load %struct.Macroblock** %175, align 8 ; <%struct.Macroblock*> [#uses=1]
+ %177 = load i32* %.SV156.phi, align 8 ; <i32> [#uses=1]
+ br label %meshBB428
+
+bb70.fragment: ; preds = %meshBB428
+ %Opq.sa.calc739 = xor i32 %Opq.sa.calc897, 213 ; <i32> [#uses=2]
+ %Opq.sa.calc738 = sub i32 %Opq.sa.calc739, 1 ; <i32> [#uses=2]
+ %178 = sext i32 %.SV280.phi to i64 ; <i64> [#uses=1]
+ %179 = getelementptr %struct.Macroblock* %.SV278.phi, i64 %178, i32 20 ; <i32*> [#uses=1]
+ %180 = load i32* %179, align 4 ; <i32> [#uses=1]
+ %181 = icmp eq i32 %180, 0 ; <i1> [#uses=1]
+ br i1 %181, label %meshBB452, label %meshBB356
+
+bb71: ; preds = %meshBB452
+ %Opq.sa.calc633 = xor i32 %Opq.sa.calc820, 118 ; <i32> [#uses=1]
+ %182 = add i32 %.SV158.phi1106, 1 ; <i32> [#uses=1]
+ br label %meshBB352
+
+bb71.fragment: ; preds = %meshBB352
+ %Opq.sa.calc809 = sub i32 %Opq.sa.calc876, 17 ; <i32> [#uses=2]
+ store i32 %.SV282.phi, i32* %.load163.SV.phi, align 4
+ %183 = shl i32 %yN, 1 ; <i32> [#uses=1]
+ br label %meshBB436
+
+bb74: ; preds = %meshBB412
+ %Opq.sa.calc636 = xor i32 %Opq.sa.calc932, 233 ; <i32> [#uses=1]
+ %184 = add i32 %.SV158.phi1063, 1 ; <i32> [#uses=1]
+ %185 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=1]
+ br label %bb74.fragment
+
+bb74.fragment: ; preds = %bb74
+ %Opq.sa.calc1011 = sub i32 %Opq.sa.calc636, -19 ; <i32> [#uses=0]
+ store i32 %184, i32* %185, align 4
+ %186 = getelementptr %struct.Macroblock* %2, i64 %3, i32 27 ; <i32*> [#uses=1]
+ %187 = load i32* %186, align 8 ; <i32> [#uses=2]
+ store i32 %187, i32* %.SV52.phi1186, align 4
+ br label %bb96
+
+bb76: ; preds = %bb58
+ %Opq.sa.calc640 = xor i32 %Opq.sa.calc1002, 71 ; <i32> [#uses=4]
+ %Opq.sa.calc639 = xor i32 %Opq.sa.calc640, 219 ; <i32> [#uses=0]
+ %188 = icmp eq i32 %yN, 0 ; <i1> [#uses=1]
+ br i1 %188, label %bb77, label %bb79
+
+bb77: ; preds = %bb76
+ %Opq.sa.calc643 = add i32 %Opq.sa.calc640, 2 ; <i32> [#uses=2]
+ %189 = load %struct.ImageParameters** @img, align 8 ; <%struct.ImageParameters*> [#uses=1]
+ %190 = getelementptr %struct.ImageParameters* %189, i64 0, i32 45 ; <i32*> [#uses=1]
+ %191 = load i32* %190, align 4 ; <i32> [#uses=1]
+ %192 = icmp eq i32 %191, 2 ; <i1> [#uses=1]
+ br i1 %192, label %meshBB416, label %bb79
+
+bb78: ; preds = %meshBB416
+ %Opq.sa.calc647 = xor i32 %Opq.sa.calc971, 25 ; <i32> [#uses=2]
+ %Opq.sa.calc646 = sub i32 %Opq.sa.calc647, 29 ; <i32> [#uses=0]
+ %193 = getelementptr %struct.Macroblock* %2, i64 %3, i32 23 ; <i32*> [#uses=1]
+ %194 = load i32* %193, align 8 ; <i32> [#uses=1]
+ %195 = add i32 %194, 1 ; <i32> [#uses=1]
+ br label %bb78.fragment
+
+bb78.fragment: ; preds = %bb78
+ %Opq.sa.calc850 = sub i32 %Opq.sa.calc647, -93 ; <i32> [#uses=0]
+ %196 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=1]
+ store i32 %195, i32* %196, align 4
+ store i32 1, i32* %.SV52.phi1200, align 4
+ %197 = add i32 %yN, -1 ; <i32> [#uses=1]
+ br label %bb98
+
+bb79: ; preds = %bb77, %bb76
+ %Opq.link.SV652.phi = phi i32 [ %Opq.sa.calc643, %bb77 ], [ %Opq.sa.calc640, %bb76 ] ; <i32> [#uses=1]
+ %Opq.link.mask654 = and i32 %Opq.link.SV652.phi, 8 ; <i32> [#uses=1]
+ %Opq.sa.calc651 = sub i32 %Opq.link.mask654, -2 ; <i32> [#uses=3]
+ %Opq.sa.calc650 = xor i32 %Opq.sa.calc651, 1 ; <i32> [#uses=2]
+ br i1 %or.cond.not.SV.phi1094, label %meshBB456, label %meshBB352
+
+bb81: ; preds = %meshBB456
+ %Opq.sa.calc655 = add i32 %Opq.sa.calc816, 56 ; <i32> [#uses=0]
+ %198 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=1]
+ store i32 %curr_mb_nr, i32* %198, align 4
+ store i32 1, i32* %.SV52.phi1136, align 4
+ br label %bb98
+
+bb83: ; preds = %bb56.fragment
+ %Opq.sa.calc658 = sub i32 %Opq.sa.calc1002, 73 ; <i32> [#uses=3]
+ br i1 %140, label %bb84, label %meshBB424
+
+bb84: ; preds = %bb83
+ %Opq.sa.calc661 = xor i32 %Opq.sa.calc658, 22 ; <i32> [#uses=1]
+ %199 = getelementptr %struct.Macroblock* %2, i64 %3, i32 20 ; <i32*> [#uses=1]
+ %200 = load i32* %199, align 4 ; <i32> [#uses=1]
+ br label %meshBB400
+
+bb84.fragment: ; preds = %meshBB400
+ %Opq.sa.calc802 = xor i32 %Opq.sa.calc824, 240 ; <i32> [#uses=3]
+ %201 = icmp eq i32 %.SV290.phi, 0 ; <i1> [#uses=1]
+ %202 = and i32 %curr_mb_nr, 1 ; <i32> [#uses=1]
+ %203 = icmp eq i32 %202, 0 ; <i1> [#uses=2]
+ br i1 %201, label %meshBB372, label %bb89
+
+bb85: ; preds = %meshBB372
+ %Opq.sa.calc667 = sub i32 %Opq.sa.calc812, 20 ; <i32> [#uses=3]
+ %Opq.sa.calc666 = sub i32 %Opq.sa.calc667, 84 ; <i32> [#uses=2]
+ %Opq.sa.calc664 = add i32 %Opq.sa.calc666, %Opq.sa.calc667 ; <i32> [#uses=1]
+ %Opq.sa.calc665 = add i32 %Opq.sa.calc664, -112 ; <i32> [#uses=2]
+ br i1 %.SV167.phi, label %meshBB336, label %meshBB440
+
+bb86: ; preds = %meshBB336
+ %Opq.sa.calc670 = sub i32 %Opq.sa.calc979, 35 ; <i32> [#uses=1]
+ %204 = getelementptr %struct.Macroblock* %2, i64 %3, i32 24 ; <i32*> [#uses=1]
+ %205 = load i32* %204, align 4 ; <i32> [#uses=1]
+ %206 = add i32 %205, 1 ; <i32> [#uses=1]
+ %207 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=1]
+ br label %bb86.fragment
+
+bb86.fragment: ; preds = %bb86
+ %Opq.sa.calc943 = xor i32 %Opq.sa.calc670, 123 ; <i32> [#uses=2]
+ store i32 %206, i32* %207, align 4
+ %208 = getelementptr %struct.Macroblock* %2, i64 %3, i32 28 ; <i32*> [#uses=1]
+ %209 = load i32* %208, align 4 ; <i32> [#uses=2]
+ store i32 %209, i32* %.SV52.phi1234, align 4
+ br label %meshBB424
+
+bb87: ; preds = %meshBB440
+ %Opq.sa.calc674 = xor i32 %Opq.sa.calc990, 44 ; <i32> [#uses=1]
+ %Opq.sa.calc673 = xor i32 %Opq.sa.calc674, 160 ; <i32> [#uses=1]
+ store i32 0, i32* %.SV52.phi1235, align 4
+ br label %meshBB408
+
+bb89: ; preds = %bb84.fragment
+ %Opq.sa.calc677 = sub i32 %Opq.sa.calc802, -183 ; <i32> [#uses=1]
+ %210 = getelementptr %struct.Macroblock* %2, i64 %3, i32 24 ; <i32*> [#uses=2]
+ br label %bb89.fragment
+
+bb89.fragment: ; preds = %bb89
+ %Opq.sa.calc962 = add i32 %Opq.sa.calc677, -188 ; <i32> [#uses=3]
+ %211 = load i32* %210, align 4 ; <i32> [#uses=3]
+ br i1 %203, label %bb90, label %meshBB408
+
+bb90: ; preds = %bb89.fragment
+ %Opq.sa.calc680 = xor i32 %Opq.sa.calc962, 92 ; <i32> [#uses=1]
+ %212 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=2]
+ store i32 %211, i32* %212, align 4
+ %213 = getelementptr %struct.Macroblock* %2, i64 %3, i32 28 ; <i32*> [#uses=2]
+ br label %bb90.fragment
+
+bb90.fragment: ; preds = %bb90
+ %Opq.sa.calc773 = sub i32 %Opq.sa.calc680, 60 ; <i32> [#uses=3]
+ %Opq.sa.calc772 = add i32 %Opq.sa.calc773, -25 ; <i32> [#uses=2]
+ %214 = load i32* %213, align 4 ; <i32> [#uses=3]
+ store i32 %214, i32* %.SV52.phi1190, align 4
+ %215 = load i32* %213, align 4 ; <i32> [#uses=1]
+ %216 = icmp eq i32 %215, 0 ; <i1> [#uses=1]
+ br i1 %216, label %meshBB416, label %meshBB368
+
+bb91: ; preds = %meshBB368
+ %Opq.sa.calc683 = sub i32 %Opq.sa.calc768, -7 ; <i32> [#uses=0]
+ %217 = load %struct.ImageParameters** @img, align 8 ; <%struct.ImageParameters*> [#uses=1]
+ %218 = getelementptr %struct.ImageParameters* %217, i64 0, i32 39 ; <%struct.Macroblock**> [#uses=1]
+ %219 = load %struct.Macroblock** %218, align 8 ; <%struct.Macroblock*> [#uses=1]
+ %220 = load i32* %.SV170.phi, align 4 ; <i32> [#uses=1]
+ br label %bb91.fragment
+
+bb91.fragment: ; preds = %bb91
+ %Opq.sa.calc853 = xor i32 %Opq.sa.calc768, 8 ; <i32> [#uses=1]
+ %221 = sext i32 %220 to i64 ; <i64> [#uses=1]
+ %222 = getelementptr %struct.Macroblock* %219, i64 %221, i32 20 ; <i32*> [#uses=1]
+ %223 = load i32* %222, align 4 ; <i32> [#uses=1]
+ %224 = icmp eq i32 %223, 0 ; <i1> [#uses=1]
+ br i1 %224, label %bb92, label %bb96
+
+bb92: ; preds = %bb91.fragment
+ %Opq.sa.calc686 = xor i32 %Opq.sa.calc853, 2 ; <i32> [#uses=1]
+ %225 = add i32 %.SV172.phi, 1 ; <i32> [#uses=1]
+ br label %bb92.fragment
+
+bb92.fragment: ; preds = %bb92
+ %Opq.sa.calc1005 = xor i32 %Opq.sa.calc686, 130 ; <i32> [#uses=2]
+ store i32 %225, i32* %.SV176.phi, align 4
+ %226 = shl i32 %yN, 1 ; <i32> [#uses=1]
+ br label %meshBB380
+
+bb95: ; preds = %meshBB408
+ %Opq.sa.calc689 = xor i32 %Opq.sa.calc912, 207 ; <i32> [#uses=3]
+ %227 = add i32 %.SV172.phi1074, 1 ; <i32> [#uses=1]
+ %228 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=1]
+ br label %meshBB384
+
+bb95.fragment: ; preds = %meshBB384
+ %Opq.sa.calc841 = sub i32 %Opq.sa.calc901, 76 ; <i32> [#uses=0]
+ store i32 %.SV306.phi, i32* %.SV308.phi, align 4
+ %229 = getelementptr %struct.Macroblock* %.load.SV.phi, i64 %.load20.SV.phi, i32 28 ; <i32*> [#uses=1]
+ %230 = load i32* %229, align 4 ; <i32> [#uses=2]
+ store i32 %230, i32* %.load53.SV.phi, align 4
+ br label %bb96
+
+bb96: ; preds = %meshBB444, %meshBB440, %meshBB436, %meshBB424, %meshBB420, %meshBB416, %meshBB396, %meshBB388, %meshBB380, %meshBB376, %meshBB364, %meshBB356, %meshBB340, %meshBB324, %meshBB, %bb95.fragment, %bb91.fragment, %bb74.fragment, %bb51, %bb48, %bb43, %bb41.fragment, %bb37.fragment, %bb36.fragment, %bb34.fragment, %bb30.fragment, %bb25, %bb19.fragment, %bb16.fragment, %bb15.fragment, %bb11.fragment, %bb9.fragment, %bb8.fragment, %bb7.fragment
+ %.SV38.phi1087 = phi i64 [ %.SV38.phi1224, %meshBB444 ], [ %.SV38.phi1210, %meshBB440 ], [ %.SV38.phi1147, %meshBB436 ], [ %.SV38.phi1197, %meshBB424 ], [ %.SV38.phi1194, %meshBB420 ], [ %.SV38.phi1201, %meshBB416 ], [ %.SV38.phi, %meshBB396 ], [ %.SV38.phi1118, %meshBB388 ], [ %.SV38.phi1207, %meshBB380 ], [ %.SV38.phi1153, %meshBB376 ], [ %.SV38.phi1098, %meshBB364 ], [ %.SV38.phi1121, %meshBB356 ], [ %.SV38.phi1167, %meshBB340 ], [ %.SV38.phi1175, %meshBB324 ], [ %.SV38.phi1183, %meshBB ], [ %.SV38.phi1164, %bb91.fragment ], [ %.SV38.phi1179, %bb48 ], [ %.SV38.phi1231, %bb41.fragment ], [ %.SV38.phi1172, %bb25 ], [ %.SV38.phi1175, %bb15.fragment ], [ %.SV38.phi1164, %bb9.fragment ], [ %.SV38.phi1164, %bb8.fragment ], [ %.SV38.phi1221, %bb95.fragment ], [ %.SV38.phi1187, %bb74.fragment ], [ %.SV38.phi1227, %bb51 ], [ %.SV38.phi1179, %bb43 ], [ %.SV38.phi1103, %bb37.fragment ], [ %.SV38.phi1214, %bb36.fragment ], [ %.SV38.phi1227, %bb34.fragment ], [ %.SV38.phi1121, %bb30.fragment ], [ %.SV38.phi1187, %bb19.fragment ], [ %.SV38.phi1175, %bb16.fragment ], [ %.SV38.phi1204, %bb11.fragment ], [ %.SV38.phi1118, %bb7.fragment ] ; <i64> [#uses=2]
+ %.SV68.phi1086 = phi i32 [ %.SV68.phi1223, %meshBB444 ], [ %.SV68.phi1209, %meshBB440 ], [ %.SV68.phi1146, %meshBB436 ], [ %.SV68.phi1196, %meshBB424 ], [ %.SV68.phi1193, %meshBB420 ], [ %.SV68.phi1199, %meshBB416 ], [ %.SV68.phi, %meshBB396 ], [ %.SV68.phi1117, %meshBB388 ], [ %.SV68.phi1206, %meshBB380 ], [ %.SV68.phi1152, %meshBB376 ], [ %.SV68.phi1096, %meshBB364 ], [ %.SV68.phi1120, %meshBB356 ], [ %.SV68.phi1166, %meshBB340 ], [ %.SV68.phi1174, %meshBB324 ], [ %.SV68.phi1181, %meshBB ], [ %.SV68.phi1162, %bb91.fragment ], [ %.SV68.phi1177, %bb48 ], [ %.SV68.phi1229, %bb41.fragment ], [ %.SV68.phi1169, %bb25 ], [ %.SV68.phi1174, %bb15.fragment ], [ %.SV68.phi1162, %bb9.fragment ], [ %.SV68.phi1162, %bb8.fragment ], [ %.SV68.phi1220, %bb95.fragment ], [ %.SV68.phi1185, %bb74.fragment ], [ %.SV68.phi1226, %bb51 ], [ %.SV68.phi1177, %bb43 ], [ %.SV68.phi1100, %bb37.fragment ], [ %.SV68.phi1212, %bb36.fragment ], [ %.SV68.phi1226, %bb34.fragment ], [ %.SV68.phi1120, %bb30.fragment ], [ %.SV68.phi1185, %bb19.fragment ], [ %.SV68.phi1174, %bb16.fragment ], [ %.SV68.phi1203, %bb11.fragment ], [ %.SV68.phi1117, %bb7.fragment ] ; <i32> [#uses=2]
+ %.SV70.phi1085 = phi i32 [ %.SV70.phi1222, %meshBB444 ], [ %.SV70.phi1208, %meshBB440 ], [ %.SV70.phi1145, %meshBB436 ], [ %.SV70.phi1195, %meshBB424 ], [ %.SV70.phi1192, %meshBB420 ], [ %.SV70.phi1198, %meshBB416 ], [ %.SV70.phi, %meshBB396 ], [ %.SV70.phi1116, %meshBB388 ], [ %.SV70.phi1205, %meshBB380 ], [ %.SV70.phi1151, %meshBB376 ], [ %.SV70.phi1095, %meshBB364 ], [ %.SV70.phi1119, %meshBB356 ], [ %.SV70.phi1165, %meshBB340 ], [ %.SV70.phi1173, %meshBB324 ], [ %.SV70.phi1180, %meshBB ], [ %.SV70.phi1161, %bb91.fragment ], [ %.SV70.phi1176, %bb48 ], [ %.SV70.phi1228, %bb41.fragment ], [ %.SV70.phi1168, %bb25 ], [ %.SV70.phi1173, %bb15.fragment ], [ %.SV70.phi1161, %bb9.fragment ], [ %.SV70.phi1161, %bb8.fragment ], [ %.SV70.phi1219, %bb95.fragment ], [ %.SV70.phi1184, %bb74.fragment ], [ %.SV70.phi1225, %bb51 ], [ %.SV70.phi1176, %bb43 ], [ %.SV70.phi1099, %bb37.fragment ], [ %.SV70.phi1211, %bb36.fragment ], [ %.SV70.phi1225, %bb34.fragment ], [ %.SV70.phi1119, %bb30.fragment ], [ %.SV70.phi1184, %bb19.fragment ], [ %.SV70.phi1173, %bb16.fragment ], [ %.SV70.phi1202, %bb11.fragment ], [ %.SV70.phi1116, %bb7.fragment ] ; <i32> [#uses=2]
+ %.SV.phi = phi i32 [ %.SV.phi1048, %meshBB444 ], [ %.SV.phi1056, %meshBB440 ], [ %.SV.phi1067, %meshBB436 ], [ %.SV.phi1072, %meshBB424 ], [ %.SV.phi1044, %meshBB420 ], [ %.SV.phi1076, %meshBB416 ], [ %.SV.phi1065, %meshBB396 ], [ %.SV.phi1054, %meshBB388 ], [ %.SV.phi1052, %meshBB380 ], [ %.SV.phi1050, %meshBB376 ], [ %.SV.phi1062, %meshBB364 ], [ %.SV.phi1046, %meshBB356 ], [ %.SV.phi1042, %meshBB340 ], [ %.SV.phi1032, %meshBB324 ], [ %.SV.phi1034, %meshBB ], [ %.SV178.phi, %bb91.fragment ], [ %.SV118.phi1040, %bb48 ], [ %.SV118.phi1125, %bb41.fragment ], [ %.SV118.phi, %bb25 ], [ %.load94.SV.phi, %bb15.fragment ], [ %32, %bb9.fragment ], [ %32, %bb8.fragment ], [ %230, %bb95.fragment ], [ %187, %bb74.fragment ], [ %.SV118.phi1081, %bb51 ], [ %.SV118.phi1040, %bb43 ], [ %.load131.SV.phi, %bb37.fragment ], [ %.SV118.phi1154, %bb36.fragment ], [ %.load129.SV.phi, %bb34.fragment ], [ %.SV118.phi1158, %bb30.fragment ], [ %66, %bb19.fragment ], [ %.SV93.phi, %bb16.fragment ], [ %.load84.SV.phi, %bb11.fragment ], [ %27, %bb7.fragment ] ; <i32> [#uses=1]
+ %yM.0.SV.phi = phi i32 [ -1, %meshBB444 ], [ %yN, %meshBB440 ], [ %yM.0.SV.phi1066, %meshBB436 ], [ %yN, %meshBB424 ], [ %yN, %meshBB420 ], [ -1, %meshBB416 ], [ -1, %meshBB396 ], [ %yM.0.SV.phi1053, %meshBB388 ], [ %yM.0.SV.phi1051, %meshBB380 ], [ %yM.0.SV.phi1049, %meshBB376 ], [ %yN, %meshBB364 ], [ %yN, %meshBB356 ], [ %yM.0.SV.phi1041, %meshBB340 ], [ -1, %meshBB324 ], [ -1, %meshBB ], [ %yN, %bb91.fragment ], [ -1, %bb48 ], [ %yN, %bb41.fragment ], [ -1, %bb25 ], [ %yN, %bb15.fragment ], [ %yN, %bb9.fragment ], [ -1, %bb8.fragment ], [ %yN, %bb95.fragment ], [ %yN, %bb74.fragment ], [ %133, %bb51 ], [ %118, %bb43 ], [ %107, %bb37.fragment ], [ %104, %bb36.fragment ], [ %yN, %bb34.fragment ], [ %91, %bb30.fragment ], [ %yN, %bb19.fragment ], [ %62, %bb16.fragment ], [ %45, %bb11.fragment ], [ %yN, %bb7.fragment ] ; <i32> [#uses=2]
+ %Opq.sa.calc693 = add i32 0, 15 ; <i32> [#uses=2]
+ %Opq.sa.calc692 = xor i32 %Opq.sa.calc693, 8 ; <i32> [#uses=1]
+ %231 = icmp eq i32 %.SV.phi, 0 ; <i1> [#uses=1]
+ br i1 %231, label %bb97, label %meshBB404
+
+bb97: ; preds = %meshBB424, %meshBB408, %meshBB352, %bb96, %bb21
+ %.SV38.phi1150 = phi i64 [ %.SV38.phi1197, %meshBB424 ], [ %.SV38.phi1218, %meshBB408 ], [ %.SV38.phi1140, %meshBB352 ], [ %.SV38.phi1087, %bb96 ], [ %4, %bb21 ] ; <i64> [#uses=1]
+ %.SV68.phi1149 = phi i32 [ %.SV68.phi1196, %meshBB424 ], [ %.SV68.phi1216, %meshBB408 ], [ %.SV68.phi1139, %meshBB352 ], [ %.SV68.phi1086, %bb96 ], [ %.SV68.phi1021, %bb21 ] ; <i32> [#uses=1]
+ %.SV70.phi1148 = phi i32 [ %.SV70.phi1195, %meshBB424 ], [ %.SV70.phi1215, %meshBB408 ], [ %.SV70.phi1138, %meshBB352 ], [ %.SV70.phi1085, %bb96 ], [ %.SV70.phi1027, %bb21 ] ; <i32> [#uses=1]
+ %yM.0.reg2mem.0.SV.phi = phi i32 [ -1, %meshBB424 ], [ -1, %meshBB408 ], [ -1, %meshBB352 ], [ %yM.0.SV.phi, %bb96 ], [ -1, %bb21 ] ; <i32> [#uses=1]
+ %Opq.sa.calc694 = xor i32 0, 243 ; <i32> [#uses=1]
+ %232 = load %struct.ImageParameters** @img, align 8 ; <%struct.ImageParameters*> [#uses=1]
+ %233 = getelementptr %struct.ImageParameters* %232, i64 0, i32 45 ; <i32*> [#uses=1]
+ br label %bb97.fragment
+
+bb97.fragment: ; preds = %bb97
+ %Opq.sa.calc928 = xor i32 %Opq.sa.calc694, 128 ; <i32> [#uses=1]
+ %234 = load i32* %233, align 4 ; <i32> [#uses=1]
+ %235 = icmp eq i32 %234, 0 ; <i1> [#uses=1]
+ br i1 %235, label %return, label %bb98
+
+bb98: ; preds = %meshBB444, %meshBB404, %bb97.fragment, %bb81, %bb78.fragment
+ %.SV38.phi1093 = phi i64 [ %.SV38.phi1224, %meshBB444 ], [ %.SV38.phi1017, %meshBB404 ], [ %.SV38.phi1150, %bb97.fragment ], [ %.SV38.phi1137, %bb81 ], [ %.SV38.phi1201, %bb78.fragment ] ; <i64> [#uses=2]
+ %.SV68.phi1092 = phi i32 [ %.SV68.phi1223, %meshBB444 ], [ %.SV68.phi1023, %meshBB404 ], [ %.SV68.phi1149, %bb97.fragment ], [ %.SV68.phi1135, %bb81 ], [ %.SV68.phi1199, %bb78.fragment ] ; <i32> [#uses=2]
+ %.SV70.phi1091 = phi i32 [ %.SV70.phi1222, %meshBB444 ], [ %.SV70.phi1028, %meshBB404 ], [ %.SV70.phi1148, %bb97.fragment ], [ %.SV70.phi1134, %bb81 ], [ %.SV70.phi1198, %bb78.fragment ] ; <i32> [#uses=2]
+ %yM.0.reg2mem.1.SV.phi1068 = phi i32 [ %yN, %meshBB444 ], [ %yM.0.reg2mem.1.SV.phi1077, %meshBB404 ], [ %yM.0.reg2mem.0.SV.phi, %bb97.fragment ], [ %yN, %bb81 ], [ %197, %bb78.fragment ] ; <i32> [#uses=1]
+ %Opq.sa.calc695 = xor i32 0, 23 ; <i32> [#uses=2]
+ %236 = and i32 %.SV70.phi1091, %xN ; <i32> [#uses=1]
+ %237 = getelementptr %struct.PixelPos* %pix, i64 0, i32 2 ; <i32*> [#uses=2]
+ store i32 %236, i32* %237, align 4
+ %238 = and i32 %yM.0.reg2mem.1.SV.phi1068, %.SV68.phi1092 ; <i32> [#uses=1]
+ %239 = getelementptr %struct.PixelPos* %pix, i64 0, i32 3 ; <i32*> [#uses=2]
+ store i32 %238, i32* %239, align 4
+ %240 = getelementptr %struct.PixelPos* %pix, i64 0, i32 5 ; <i32*> [#uses=1]
+ br label %meshBB376
+
+bb98.fragment: ; preds = %meshBB376
+ %Opq.sa.calc1008 = sub i32 %Opq.link.mask911, 13 ; <i32> [#uses=1]
+ %241 = getelementptr %struct.PixelPos* %pix, i64 0, i32 4 ; <i32*> [#uses=4]
+ %242 = getelementptr %struct.PixelPos* %pix, i64 0, i32 1 ; <i32*> [#uses=1]
+ %243 = load i32* %242, align 4 ; <i32> [#uses=1]
+ %244 = load void (i32, i32*, i32*)** @get_mb_block_pos, align 8 ; <void (i32, i32*, i32*)*> [#uses=1]
+ tail call void %244(i32 %243, i32* %241, i32* %.SV317.phi) nounwind
+ %245 = load i32* %241, align 4 ; <i32> [#uses=1]
+ %246 = load %struct.ImageParameters** @img, align 8 ; <%struct.ImageParameters*> [#uses=1]
+ %247 = getelementptr %struct.ImageParameters* %246, i64 0, i32 119, i64 %.load39.SV.phi, i64 0 ; <i32*> [#uses=1]
+ %248 = load i32* %247, align 4 ; <i32> [#uses=1]
+ %249 = mul i32 %248, %245 ; <i32> [#uses=2]
+ store i32 %249, i32* %241, align 4
+ br label %bb98.fragment183
+
+bb98.fragment183: ; preds = %bb98.fragment
+ %Opq.sa.calc777 = sub i32 %Opq.sa.calc1008, -158 ; <i32> [#uses=1]
+ %Opq.sa.calc776 = sub i32 %Opq.sa.calc777, 46 ; <i32> [#uses=0]
+ %250 = load i32* %.SV317.phi, align 4 ; <i32> [#uses=1]
+ %251 = load %struct.ImageParameters** @img, align 8 ; <%struct.ImageParameters*> [#uses=1]
+ %252 = getelementptr %struct.ImageParameters* %251, i64 0, i32 119, i64 %.load39.SV.phi, i64 1 ; <i32*> [#uses=1]
+ %253 = load i32* %252, align 4 ; <i32> [#uses=1]
+ %254 = mul i32 %253, %250 ; <i32> [#uses=1]
+ %255 = load i32* %.SV313.phi, align 4 ; <i32> [#uses=1]
+ %256 = add i32 %255, %249 ; <i32> [#uses=1]
+ store i32 %256, i32* %241, align 4
+ %257 = load i32* %.SV315.phi, align 4 ; <i32> [#uses=1]
+ %258 = add i32 %257, %254 ; <i32> [#uses=1]
+ store i32 %258, i32* %.SV317.phi, align 4
+ ret void
+
+return: ; preds = %meshBB448, %meshBB396, %bb97.fragment
+ %Opq.link.SV697.phi = phi i32 [ %Opq.sa.calc957, %meshBB448 ], [ %Opq.sa.calc758, %meshBB396 ], [ %Opq.sa.calc928, %bb97.fragment ] ; <i32> [#uses=1]
+ %Opq.link.mask699 = and i32 %Opq.link.SV697.phi, 0 ; <i32> [#uses=1]
+ %Opq.sa.calc696 = add i32 %Opq.link.mask699, 238 ; <i32> [#uses=0]
+ ret void
+
+meshBB: ; preds = %bb33.fragment, %bb14.fragment
+ %.SV38.phi1183 = phi i64 [ %.SV38.phi1115, %bb14.fragment ], [ %.SV38.phi1172, %bb33.fragment ] ; <i64> [#uses=3]
+ %.SV68.phi1181 = phi i32 [ %.SV68.phi1112, %bb14.fragment ], [ %.SV68.phi1169, %bb33.fragment ] ; <i32> [#uses=3]
+ %.SV70.phi1180 = phi i32 [ %.SV70.phi1111, %bb14.fragment ], [ %.SV70.phi1168, %bb33.fragment ] ; <i32> [#uses=3]
+ %.SV104.phi1084 = phi i32 [ undef, %bb14.fragment ], [ %.SV104.phi, %bb33.fragment ] ; <i32> [#uses=1]
+ %.SV111.phi1083 = phi i32* [ undef, %bb14.fragment ], [ %.SV111.phi, %bb33.fragment ] ; <i32*> [#uses=1]
+ %.SV118.phi1082 = phi i32 [ undef, %bb14.fragment ], [ %.SV118.phi, %bb33.fragment ] ; <i32> [#uses=2]
+ %.SV.phi1034 = phi i32 [ %50, %bb14.fragment ], [ undef, %bb33.fragment ] ; <i32> [#uses=1]
+ %meshStackVariable.phi = phi i32 [ %Opq.sa.calc723, %bb14.fragment ], [ %Opq.sa.calc712, %bb33.fragment ] ; <i32> [#uses=1]
+ %Opq.link.SV829.phi = phi i32 [ %Opq.sa.calc723, %bb14.fragment ], [ %Opq.sa.calc534, %bb33.fragment ] ; <i32> [#uses=1]
+ %Opq.link.mask831 = and i32 %Opq.link.SV829.phi, 0 ; <i32> [#uses=1]
+ %Opq.sa.calc828 = sub i32 %Opq.link.mask831, -117 ; <i32> [#uses=2]
+ %meshCmp = icmp eq i32 %meshStackVariable.phi, 3 ; <i1> [#uses=1]
+ br i1 %meshCmp, label %bb35, label %bb96
+
+meshBB324: ; preds = %bb32, %bb15
+ %.SV38.phi1175 = phi i64 [ %.SV38.phi1172, %bb32 ], [ %.SV38.phi1115, %bb15 ] ; <i64> [#uses=3]
+ %.SV68.phi1174 = phi i32 [ %.SV68.phi1169, %bb32 ], [ %.SV68.phi1112, %bb15 ] ; <i32> [#uses=3]
+ %.SV70.phi1173 = phi i32 [ %.SV70.phi1168, %bb32 ], [ %.SV70.phi1111, %bb15 ] ; <i32> [#uses=3]
+ %.load94.SV.phi = phi i32 [ undef, %bb32 ], [ %50, %bb15 ] ; <i32> [#uses=1]
+ %.SV212.phi = phi %struct.Macroblock* [ undef, %bb32 ], [ %55, %bb15 ] ; <%struct.Macroblock*> [#uses=1]
+ %.SV214.phi = phi i32 [ undef, %bb32 ], [ %56, %bb15 ] ; <i32> [#uses=1]
+ %meshStackVariable325.phi = phi i32 [ %Opq.sa.calc531, %bb32 ], [ %Opq.sa.calc496, %bb15 ] ; <i32> [#uses=1]
+ %Opq.link.SV751.phi = phi i32 [ %Opq.sa.calc512, %bb32 ], [ %Opq.sa.calc723, %bb15 ] ; <i32> [#uses=1]
+ %.SV.phi1032 = phi i32 [ %.SV118.phi, %bb32 ], [ undef, %bb15 ] ; <i32> [#uses=1]
+ %.SV93.phi = phi i32 [ undef, %bb32 ], [ %50, %bb15 ] ; <i32> [#uses=1]
+ %.SV91.phi = phi i32* [ undef, %bb32 ], [ %48, %bb15 ] ; <i32*> [#uses=1]
+ %.SV87.phi = phi i32 [ undef, %bb32 ], [ %47, %bb15 ] ; <i32> [#uses=1]
+ %Opq.link.mask753 = and i32 %Opq.link.SV751.phi, 4 ; <i32> [#uses=1]
+ %Opq.sa.calc750 = add i32 %Opq.link.mask753, 203 ; <i32> [#uses=1]
+ %meshCmp327 = icmp eq i32 %meshStackVariable325.phi, 14 ; <i1> [#uses=1]
+ br i1 %meshCmp327, label %bb15.fragment, label %bb96
+
+meshBB328: ; preds = %bb50, %bb34
+ %.SV38.phi1227 = phi i64 [ %.SV38.phi1179, %bb50 ], [ %.SV38.phi1172, %bb34 ] ; <i64> [#uses=2]
+ %.SV68.phi1226 = phi i32 [ %.SV68.phi1177, %bb50 ], [ %.SV68.phi1169, %bb34 ] ; <i32> [#uses=2]
+ %.SV70.phi1225 = phi i32 [ %.SV70.phi1176, %bb50 ], [ %.SV70.phi1168, %bb34 ] ; <i32> [#uses=2]
+ %.SV118.phi1081 = phi i32 [ %.SV118.phi1040, %bb50 ], [ %.SV118.phi, %bb34 ] ; <i32> [#uses=1]
+ %.load129.SV.phi = phi i32 [ undef, %bb50 ], [ %.SV118.phi, %bb34 ] ; <i32> [#uses=1]
+ %.load116.SV.phi = phi i32* [ undef, %bb50 ], [ %.SV111.phi, %bb34 ] ; <i32*> [#uses=1]
+ %.SV238.phi = phi i32 [ undef, %bb50 ], [ %100, %bb34 ] ; <i32> [#uses=1]
+ %meshStackVariable329.phi = phi i32 [ %Opq.sa.calc577, %bb50 ], [ %Opq.sa.calc537, %bb34 ] ; <i32> [#uses=1]
+ %Opq.link.SV788.phi = phi i32 [ %Opq.sa.calc577, %bb50 ], [ %Opq.sa.calc712, %bb34 ] ; <i32> [#uses=1]
+ %Opq.link.mask790 = and i32 %Opq.link.SV788.phi, 1 ; <i32> [#uses=1]
+ %Opq.sa.calc787 = sub i32 %Opq.link.mask790, -227 ; <i32> [#uses=2]
+ %meshCmp331 = icmp eq i32 %meshStackVariable329.phi, 11 ; <i1> [#uses=1]
+ br i1 %meshCmp331, label %bb34.fragment, label %bb51
+
+meshBB332: ; preds = %bb44, %bb11
+ %.SV38.phi1204 = phi i64 [ %.SV38.phi1231, %bb44 ], [ %.SV38.phi1164, %bb11 ] ; <i64> [#uses=2]
+ %.SV68.phi1203 = phi i32 [ %.SV68.phi1229, %bb44 ], [ %.SV68.phi1162, %bb11 ] ; <i32> [#uses=2]
+ %.SV70.phi1202 = phi i32 [ %.SV70.phi1228, %bb44 ], [ %.SV70.phi1161, %bb11 ] ; <i32> [#uses=2]
+ %.load127.SV.phi = phi i32 [ %.SV118.phi1125, %bb44 ], [ undef, %bb11 ] ; <i32> [#uses=1]
+ %.load114.SV.phi = phi i32* [ %.SV111.phi1126, %bb44 ], [ undef, %bb11 ] ; <i32*> [#uses=1]
+ %.load46.SV.phi = phi i32 [ %.SV43.phi1230, %bb44 ], [ undef, %bb11 ] ; <i32> [#uses=1]
+ %.SV248.phi = phi i32 [ %119, %bb44 ], [ undef, %bb11 ] ; <i32> [#uses=1]
+ %.load84.SV.phi = phi i32 [ undef, %bb44 ], [ %32, %bb11 ] ; <i32> [#uses=1]
+ %.load81.SV.phi = phi i32* [ undef, %bb44 ], [ %.SV80.phi, %bb11 ] ; <i32*> [#uses=1]
+ %.load50.SV.phi = phi i32 [ undef, %bb44 ], [ %.SV43.phi1163, %bb11 ] ; <i32> [#uses=1]
+ %.SV206.phi = phi i32 [ undef, %bb44 ], [ %43, %bb11 ] ; <i32> [#uses=1]
+ %meshStackVariable333.phi = phi i32 [ %Opq.sa.calc566, %bb44 ], [ %Opq.sa.calc485, %bb11 ] ; <i32> [#uses=1]
+ %Opq.link.SV857.phi = phi i32 [ %Opq.sa.calc987, %bb44 ], [ %Opq.sa.calc485, %bb11 ] ; <i32> [#uses=1]
+ %Opq.link.mask859 = and i32 %Opq.link.SV857.phi, 4 ; <i32> [#uses=2]
+ %Opq.sa.calc856 = add i32 %Opq.link.mask859, 204 ; <i32> [#uses=2]
+ %meshCmp335 = icmp eq i32 %meshStackVariable333.phi, 4 ; <i1> [#uses=1]
+ br i1 %meshCmp335, label %bb11.fragment, label %bb44.fragment
+
+meshBB336: ; preds = %bb85, %bb40
+ %.SV52.phi1234 = phi i32* [ %.SV52.phi1213, %bb85 ], [ undef, %bb40 ] ; <i32*> [#uses=1]
+ %.SV38.phi1231 = phi i64 [ %.SV38.phi1214, %bb85 ], [ %.SV38.phi1179, %bb40 ] ; <i64> [#uses=4]
+ %.SV43.phi1230 = phi i32 [ undef, %bb85 ], [ %.SV43.phi1178, %bb40 ] ; <i32> [#uses=3]
+ %.SV68.phi1229 = phi i32 [ %.SV68.phi1212, %bb85 ], [ %.SV68.phi1177, %bb40 ] ; <i32> [#uses=4]
+ %.SV70.phi1228 = phi i32 [ %.SV70.phi1211, %bb85 ], [ %.SV70.phi1176, %bb40 ] ; <i32> [#uses=4]
+ %.SV99.phi1128 = phi i32* [ undef, %bb85 ], [ %.SV99.phi1037, %bb40 ] ; <i32*> [#uses=1]
+ %.SV104.phi1127 = phi i32 [ undef, %bb85 ], [ %.SV104.phi1036, %bb40 ] ; <i32> [#uses=2]
+ %.SV111.phi1126 = phi i32* [ undef, %bb85 ], [ %.SV111.phi1035, %bb40 ] ; <i32*> [#uses=2]
+ %.SV118.phi1125 = phi i32 [ undef, %bb85 ], [ %.SV118.phi1040, %bb40 ] ; <i32> [#uses=3]
+ %meshStackVariable337.phi = phi i32 [ %Opq.sa.calc665, %bb85 ], [ %Opq.sa.calc553, %bb40 ] ; <i32> [#uses=1]
+ %Opq.link.SV980.phi = phi i32 [ %Opq.sa.calc667, %bb85 ], [ %Opq.sa.calc554, %bb40 ] ; <i32> [#uses=1]
+ %Opq.link.mask982 = and i32 %Opq.link.SV980.phi, 1 ; <i32> [#uses=1]
+ %Opq.sa.calc979 = sub i32 %Opq.link.mask982, -153 ; <i32> [#uses=2]
+ %meshCmp339 = icmp eq i32 %meshStackVariable337.phi, 4 ; <i1> [#uses=1]
+ br i1 %meshCmp339, label %bb41, label %bb86
+
+meshBB340: ; preds = %bb29, %bb26
+ %.SV38.phi1167 = phi i64 [ %.SV38.phi1121, %bb29 ], [ %.SV38.phi1172, %bb26 ] ; <i64> [#uses=3]
+ %.SV68.phi1166 = phi i32 [ %.SV68.phi1120, %bb29 ], [ %.SV68.phi1169, %bb26 ] ; <i32> [#uses=3]
+ %.SV70.phi1165 = phi i32 [ %.SV70.phi1119, %bb29 ], [ %.SV70.phi1168, %bb26 ] ; <i32> [#uses=3]
+ %.SV104.phi1080 = phi i32 [ undef, %bb29 ], [ %.SV104.phi, %bb26 ] ; <i32> [#uses=1]
+ %.SV111.phi1079 = phi i32* [ undef, %bb29 ], [ %.SV111.phi, %bb26 ] ; <i32*> [#uses=1]
+ %.SV118.phi1078 = phi i32 [ %.SV118.phi1158, %bb29 ], [ %.SV118.phi, %bb26 ] ; <i32> [#uses=1]
+ %.load123.SV.phi = phi i32 [ undef, %bb29 ], [ %.SV118.phi, %bb26 ] ; <i32> [#uses=2]
+ %.SV228.phi = phi %struct.Macroblock* [ undef, %bb29 ], [ %81, %bb26 ] ; <%struct.Macroblock*> [#uses=1]
+ %.SV230.phi = phi i32 [ undef, %bb29 ], [ %82, %bb26 ] ; <i32> [#uses=1]
+ %meshStackVariable341.phi = phi i32 [ %Opq.sa.calc525, %bb29 ], [ %Opq.sa.calc518, %bb26 ] ; <i32> [#uses=1]
+ %Opq.link.SV755.phi = phi i32 [ %Opq.sa.calc525, %bb29 ], [ %Opq.sa.calc519, %bb26 ] ; <i32> [#uses=1]
+ %.SV.phi1042 = phi i32 [ %.SV118.phi1158, %bb29 ], [ undef, %bb26 ] ; <i32> [#uses=1]
+ %yM.0.SV.phi1041 = phi i32 [ %89, %bb29 ], [ undef, %bb26 ] ; <i32> [#uses=1]
+ %Opq.link.mask757 = and i32 %Opq.link.SV755.phi, 12 ; <i32> [#uses=1]
+ %Opq.sa.calc754 = add i32 %Opq.link.mask757, 225 ; <i32> [#uses=2]
+ %meshCmp343 = icmp eq i32 %meshStackVariable341.phi, 9 ; <i1> [#uses=1]
+ br i1 %meshCmp343, label %bb26.fragment, label %bb96
+
+meshBB344: ; preds = %bb68, %bb23.fragment182
+ %.SV38.phi1172 = phi i64 [ %.SV38.phi1115, %bb23.fragment182 ], [ %.SV38.phi1098, %bb68 ] ; <i64> [#uses=8]
+ %.SV52.phi1170 = phi i32* [ undef, %bb23.fragment182 ], [ %.SV52.phi1097, %bb68 ] ; <i32*> [#uses=2]
+ %.SV68.phi1169 = phi i32 [ %.SV68.phi1112, %bb23.fragment182 ], [ %.SV68.phi1096, %bb68 ] ; <i32> [#uses=8]
+ %.SV70.phi1168 = phi i32 [ %.SV70.phi1111, %bb23.fragment182 ], [ %.SV70.phi1095, %bb68 ] ; <i32> [#uses=8]
+ %.load144.SV.phi = phi i1 [ undef, %bb23.fragment182 ], [ %145, %bb68 ] ; <i1> [#uses=1]
+ %.SV274.phi = phi i32* [ undef, %bb23.fragment182 ], [ %167, %bb68 ] ; <i32*> [#uses=2]
+ %.SV118.phi = phi i32 [ %76, %bb23.fragment182 ], [ undef, %bb68 ] ; <i32> [#uses=7]
+ %.SV135.phi = phi i1 [ %78, %bb23.fragment182 ], [ undef, %bb68 ] ; <i1> [#uses=2]
+ %meshStackVariable345.phi = phi i32 [ %Opq.sa.calc743, %bb23.fragment182 ], [ %Opq.sa.calc624, %bb68 ] ; <i32> [#uses=1]
+ %Opq.link.SV717.phi = phi i32 [ %Opq.sa.calc744, %bb23.fragment182 ], [ %Opq.sa.calc624, %bb68 ] ; <i32> [#uses=1]
+ %Opq.link.SV720.phi = phi i32 [ %Opq.sa.calc743, %bb23.fragment182 ], [ %Opq.sa.calc624, %bb68 ] ; <i32> [#uses=1]
+ %.SV96.phi = phi i1 [ %71, %bb23.fragment182 ], [ undef, %bb68 ] ; <i1> [#uses=1]
+ %.SV99.phi = phi i32* [ %72, %bb23.fragment182 ], [ undef, %bb68 ] ; <i32*> [#uses=2]
+ %.SV104.phi = phi i32 [ %73, %bb23.fragment182 ], [ undef, %bb68 ] ; <i32> [#uses=3]
+ %.SV111.phi = phi i32* [ %74, %bb23.fragment182 ], [ undef, %bb68 ] ; <i32*> [#uses=3]
+ %Opq.link.mask722 = and i32 %Opq.link.SV720.phi, 9 ; <i32> [#uses=3]
+ %Opq.link.mask719 = and i32 %Opq.link.SV717.phi, 0 ; <i32> [#uses=1]
+ %Opq.sa.calc715 = sub i32 %Opq.link.mask719, %Opq.link.mask722 ; <i32> [#uses=1]
+ %Opq.sa.calc716 = sub i32 %Opq.sa.calc715, -101 ; <i32> [#uses=2]
+ %meshCmp347 = icmp eq i32 %meshStackVariable345.phi, 9 ; <i1> [#uses=1]
+ br i1 %meshCmp347, label %bb68.fragment, label %bb24
+
+meshBB348: ; preds = %bb37, %bb6
+ %.SV38.phi1103 = phi i64 [ %.SV38.phi1014, %bb6 ], [ %.SV38.phi1019, %bb37 ] ; <i64> [#uses=2]
+ %.SV43.phi1102 = phi i32 [ %.SV43.phi, %bb6 ], [ %.SV43.phi1018, %bb37 ] ; <i32> [#uses=1]
+ %.SV52.phi1101 = phi i32* [ %.SV52.phi, %bb6 ], [ undef, %bb37 ] ; <i32*> [#uses=1]
+ %.SV68.phi1100 = phi i32 [ %.SV68.phi1020, %bb6 ], [ %.SV68.phi1025, %bb37 ] ; <i32> [#uses=2]
+ %.SV70.phi1099 = phi i32 [ %.SV70.phi1026, %bb6 ], [ %.SV70.phi1233, %bb37 ] ; <i32> [#uses=2]
+ %.load131.SV.phi = phi i32 [ undef, %bb6 ], [ %.SV118.phi1155, %bb37 ] ; <i32> [#uses=1]
+ %.load115.SV.phi = phi i32* [ undef, %bb6 ], [ %.SV111.phi1156, %bb37 ] ; <i32*> [#uses=1]
+ %.load48.SV.phi = phi i32 [ undef, %bb6 ], [ %.SV43.phi1018, %bb37 ] ; <i32> [#uses=1]
+ %.SV242.phi = phi i32 [ undef, %bb6 ], [ %105, %bb37 ] ; <i32> [#uses=1]
+ %meshStackVariable349.phi = phi i32 [ %Opq.sa.calc473, %bb6 ], [ %Opq.sa.calc547, %bb37 ] ; <i32> [#uses=1]
+ %Opq.link.SV806.phi = phi i32 [ %Opq.sa.calc873, %bb6 ], [ %Opq.sa.calc958, %bb37 ] ; <i32> [#uses=1]
+ %Opq.link.mask808 = and i32 %Opq.link.SV806.phi, 12 ; <i32> [#uses=1]
+ %Opq.sa.calc805 = sub i32 %Opq.link.mask808, -147 ; <i32> [#uses=3]
+ %meshCmp351 = icmp eq i32 %meshStackVariable349.phi, 13 ; <i1> [#uses=1]
+ br i1 %meshCmp351, label %bb37.fragment, label %bb8
+
+meshBB352: ; preds = %bb79, %bb71
+ %.SV38.phi1140 = phi i64 [ %.SV38.phi1110, %bb71 ], [ %.SV38.phi1098, %bb79 ] ; <i64> [#uses=2]
+ %.SV68.phi1139 = phi i32 [ %.SV68.phi1108, %bb71 ], [ %.SV68.phi1096, %bb79 ] ; <i32> [#uses=2]
+ %.SV70.phi1138 = phi i32 [ %.SV70.phi1107, %bb71 ], [ %.SV70.phi1095, %bb79 ] ; <i32> [#uses=2]
+ %.load166.SV.phi = phi i32 [ %.SV164.phi1104, %bb71 ], [ undef, %bb79 ] ; <i32> [#uses=1]
+ %.load163.SV.phi = phi i32* [ %.SV162.phi1105, %bb71 ], [ undef, %bb79 ] ; <i32*> [#uses=1]
+ %.SV282.phi = phi i32 [ %182, %bb71 ], [ undef, %bb79 ] ; <i32> [#uses=1]
+ %meshStackVariable353.phi = phi i32 [ %Opq.sa.calc633, %bb71 ], [ %Opq.sa.calc650, %bb79 ] ; <i32> [#uses=1]
+ %Opq.link.SV877.phi = phi i32 [ %Opq.sa.calc820, %bb71 ], [ %Opq.sa.calc650, %bb79 ] ; <i32> [#uses=1]
+ %Opq.link.mask879 = and i32 %Opq.link.SV877.phi, 1 ; <i32> [#uses=1]
+ %Opq.sa.calc876 = add i32 %Opq.link.mask879, 18 ; <i32> [#uses=1]
+ %meshCmp355 = icmp eq i32 %meshStackVariable353.phi, 11 ; <i1> [#uses=1]
+ br i1 %meshCmp355, label %bb97, label %bb71.fragment
+
+meshBB356: ; preds = %bb70.fragment, %bb26.fragment
+ %.SV104.phi1160 = phi i32 [ undef, %bb70.fragment ], [ %.SV104.phi1080, %bb26.fragment ] ; <i32> [#uses=1]
+ %.SV111.phi1159 = phi i32* [ undef, %bb70.fragment ], [ %.SV111.phi1079, %bb26.fragment ] ; <i32*> [#uses=1]
+ %.SV118.phi1158 = phi i32 [ undef, %bb70.fragment ], [ %.SV118.phi1078, %bb26.fragment ] ; <i32> [#uses=3]
+ %.SV38.phi1121 = phi i64 [ %.SV38.phi1014, %bb70.fragment ], [ %.SV38.phi1167, %bb26.fragment ] ; <i64> [#uses=3]
+ %.SV68.phi1120 = phi i32 [ %.SV68.phi1020, %bb70.fragment ], [ %.SV68.phi1166, %bb26.fragment ] ; <i32> [#uses=3]
+ %.SV70.phi1119 = phi i32 [ %.SV70.phi1026, %bb70.fragment ], [ %.SV70.phi1165, %bb26.fragment ] ; <i32> [#uses=3]
+ %.SV.phi1046 = phi i32 [ %.load165.SV.phi, %bb70.fragment ], [ %.load123.SV.phi, %bb26.fragment ] ; <i32> [#uses=1]
+ %meshStackVariable357.phi = phi i32 [ %Opq.sa.calc738, %bb70.fragment ], [ %Opq.sa.calc917, %bb26.fragment ] ; <i32> [#uses=1]
+ %Opq.link.SV984.phi = phi i32 [ %Opq.sa.calc738, %bb70.fragment ], [ %Opq.sa.calc918, %bb26.fragment ] ; <i32> [#uses=1]
+ %Opq.link.mask986 = and i32 %Opq.link.SV984.phi, 9 ; <i32> [#uses=1]
+ %Opq.sa.calc983 = xor i32 %Opq.link.mask986, 251 ; <i32> [#uses=1]
+ %meshCmp359 = icmp eq i32 %meshStackVariable357.phi, 9 ; <i1> [#uses=1]
+ br i1 %meshCmp359, label %bb28, label %bb96
+
+meshBB360: ; preds = %bb21, %bb13
+ %.SV38.phi1115 = phi i64 [ %4, %bb21 ], [ %.SV38.phi1014, %bb13 ] ; <i64> [#uses=5]
+ %.SV52.phi1113 = phi i32* [ %.SV52.phi1022, %bb21 ], [ %.SV52.phi, %bb13 ] ; <i32*> [#uses=3]
+ %.SV68.phi1112 = phi i32 [ %.SV68.phi1021, %bb21 ], [ %.SV68.phi1020, %bb13 ] ; <i32> [#uses=5]
+ %.SV70.phi1111 = phi i32 [ %.SV70.phi1027, %bb21 ], [ %.SV70.phi1026, %bb13 ] ; <i32> [#uses=5]
+ %.load74.SV.phi = phi i1 [ undef, %bb21 ], [ %21, %bb13 ] ; <i1> [#uses=1]
+ %.SV208.phi = phi i32* [ undef, %bb21 ], [ %46, %bb13 ] ; <i32*> [#uses=2]
+ %meshStackVariable361.phi = phi i32 [ %Opq.sa.calc505, %bb21 ], [ %Opq.sa.calc489, %bb13 ] ; <i32> [#uses=1]
+ %Opq.link.SV867.phi = phi i32 [ %Opq.sa.calc505, %bb21 ], [ %Opq.sa.calc873, %bb13 ] ; <i32> [#uses=1]
+ %Opq.link.mask869 = and i32 %Opq.link.SV867.phi, 1 ; <i32> [#uses=1]
+ %Opq.sa.calc866 = add i32 %Opq.link.mask869, 148 ; <i32> [#uses=4]
+ %meshCmp363 = icmp eq i32 %meshStackVariable361.phi, 16 ; <i1> [#uses=1]
+ br i1 %meshCmp363, label %bb13.fragment, label %bb23
+
+meshBB364: ; preds = %bb65.fragment, %bb56
+ %.SV38.phi1098 = phi i64 [ %.SV38.phi1017, %bb56 ], [ %.SV38.phi1147, %bb65.fragment ] ; <i64> [#uses=11]
+ %.SV52.phi1097 = phi i32* [ %.SV52.phi1024, %bb56 ], [ undef, %bb65.fragment ] ; <i32*> [#uses=8]
+ %.SV68.phi1096 = phi i32 [ %.SV68.phi1023, %bb56 ], [ %.SV68.phi1146, %bb65.fragment ] ; <i32> [#uses=11]
+ %.SV70.phi1095 = phi i32 [ %.SV70.phi1028, %bb56 ], [ %.SV70.phi1145, %bb65.fragment ] ; <i32> [#uses=11]
+ %or.cond.not.SV.phi1094 = phi i1 [ %or.cond.not.SV.phi1029, %bb56 ], [ undef, %bb65.fragment ] ; <i1> [#uses=1]
+ %.SV.phi1062 = phi i32 [ undef, %bb56 ], [ %.SV268.phi, %bb65.fragment ] ; <i32> [#uses=1]
+ %.not4.SV.phi = phi i1 [ %.not4, %bb56 ], [ undef, %bb65.fragment ] ; <i1> [#uses=1]
+ %.SV256.phi = phi i1 [ %139, %bb56 ], [ undef, %bb65.fragment ] ; <i1> [#uses=1]
+ %meshStackVariable365.phi = phi i32 [ %Opq.sa.calc592, %bb56 ], [ %Opq.sa.calc832, %bb65.fragment ] ; <i32> [#uses=1]
+ %Opq.link.SV735.phi = phi i32 [ %Opq.sa.calc592, %bb56 ], [ %Opq.sa.calc832, %bb65.fragment ] ; <i32> [#uses=1]
+ %Opq.link.mask737 = and i32 %Opq.link.SV735.phi, 0 ; <i32> [#uses=2]
+ %Opq.sa.calc734 = sub i32 %Opq.link.mask737, -242 ; <i32> [#uses=0]
+ %meshCmp367 = icmp eq i32 %meshStackVariable365.phi, 1 ; <i1> [#uses=1]
+ br i1 %meshCmp367, label %bb96, label %bb56.fragment
+
+meshBB368: ; preds = %bb90.fragment, %bb8
+ %.SV38.phi1164 = phi i64 [ %.SV38.phi1103, %bb8 ], [ %.SV38.phi1191, %bb90.fragment ] ; <i64> [#uses=5]
+ %.SV43.phi1163 = phi i32 [ %.SV43.phi1102, %bb8 ], [ undef, %bb90.fragment ] ; <i32> [#uses=1]
+ %.SV68.phi1162 = phi i32 [ %.SV68.phi1100, %bb8 ], [ %.SV68.phi1189, %bb90.fragment ] ; <i32> [#uses=5]
+ %.SV70.phi1161 = phi i32 [ %.SV70.phi1099, %bb8 ], [ %.SV70.phi1188, %bb90.fragment ] ; <i32> [#uses=5]
+ %.SV178.phi = phi i32 [ undef, %bb8 ], [ %214, %bb90.fragment ] ; <i32> [#uses=2]
+ %.SV176.phi = phi i32* [ undef, %bb8 ], [ %212, %bb90.fragment ] ; <i32*> [#uses=1]
+ %.SV170.phi = phi i32* [ undef, %bb8 ], [ %210, %bb90.fragment ] ; <i32*> [#uses=1]
+ %.SV172.phi = phi i32 [ undef, %bb8 ], [ %211, %bb90.fragment ] ; <i32> [#uses=1]
+ %.SV76.phi = phi i32* [ %28, %bb8 ], [ undef, %bb90.fragment ] ; <i32*> [#uses=1]
+ %.SV78.phi = phi i32 [ %29, %bb8 ], [ undef, %bb90.fragment ] ; <i32> [#uses=1]
+ %.SV80.phi = phi i32* [ %30, %bb8 ], [ undef, %bb90.fragment ] ; <i32*> [#uses=1]
+ %.load66.SV.phi = phi i32* [ %.SV52.phi1101, %bb8 ], [ undef, %bb90.fragment ] ; <i32*> [#uses=1]
+ %.load35.SV.phi = phi i64 [ %3, %bb8 ], [ undef, %bb90.fragment ] ; <i64> [#uses=1]
+ %.load16.SV.phi = phi %struct.Macroblock* [ %2, %bb8 ], [ undef, %bb90.fragment ] ; <%struct.Macroblock*> [#uses=1]
+ %.SV198.phi = phi i32 [ %29, %bb8 ], [ undef, %bb90.fragment ] ; <i32> [#uses=1]
+ %.SV200.phi = phi i32* [ %30, %bb8 ], [ undef, %bb90.fragment ] ; <i32*> [#uses=1]
+ %meshStackVariable369.phi = phi i32 [ %Opq.sa.calc479, %bb8 ], [ %Opq.sa.calc772, %bb90.fragment ] ; <i32> [#uses=1]
+ %Opq.link.SV769.phi = phi i32 [ %Opq.sa.calc805, %bb8 ], [ %Opq.sa.calc772, %bb90.fragment ] ; <i32> [#uses=1]
+ %Opq.link.mask771 = and i32 %Opq.link.SV769.phi, 2 ; <i32> [#uses=1]
+ %Opq.sa.calc768 = xor i32 %Opq.link.mask771, 135 ; <i32> [#uses=3]
+ %meshCmp371 = icmp eq i32 %meshStackVariable369.phi, 2 ; <i1> [#uses=1]
+ br i1 %meshCmp371, label %bb91, label %bb8.fragment
+
+meshBB372: ; preds = %bb84.fragment, %bb35
+ %.SV38.phi1214 = phi i64 [ %.SV38.phi1191, %bb84.fragment ], [ %.SV38.phi1183, %bb35 ] ; <i64> [#uses=3]
+ %.SV52.phi1213 = phi i32* [ %.SV52.phi1190, %bb84.fragment ], [ undef, %bb35 ] ; <i32*> [#uses=2]
+ %.SV68.phi1212 = phi i32 [ %.SV68.phi1189, %bb84.fragment ], [ %.SV68.phi1181, %bb35 ] ; <i32> [#uses=3]
+ %.SV70.phi1211 = phi i32 [ %.SV70.phi1188, %bb84.fragment ], [ %.SV70.phi1180, %bb35 ] ; <i32> [#uses=3]
+ %.SV118.phi1154 = phi i32 [ undef, %bb84.fragment ], [ %.SV118.phi1082, %bb35 ] ; <i32> [#uses=1]
+ %.SV167.phi = phi i1 [ %203, %bb84.fragment ], [ undef, %bb35 ] ; <i1> [#uses=1]
+ %meshStackVariable373.phi = phi i32 [ %Opq.sa.calc802, %bb84.fragment ], [ %Opq.sa.calc540, %bb35 ] ; <i32> [#uses=1]
+ %Opq.link.SV813.phi = phi i32 [ %Opq.sa.calc802, %bb84.fragment ], [ %Opq.sa.calc541, %bb35 ] ; <i32> [#uses=1]
+ %Opq.link.mask815 = and i32 %Opq.link.SV813.phi, 0 ; <i32> [#uses=1]
+ %Opq.sa.calc812 = sub i32 %Opq.link.mask815, -121 ; <i32> [#uses=3]
+ %meshCmp375 = icmp eq i32 %meshStackVariable373.phi, 6 ; <i1> [#uses=1]
+ br i1 %meshCmp375, label %bb36, label %bb85
+
+meshBB376: ; preds = %bb98, %bb44.fragment
+ %.SV38.phi1153 = phi i64 [ %.SV38.phi1093, %bb98 ], [ %.SV38.phi1204, %bb44.fragment ] ; <i64> [#uses=1]
+ %.SV68.phi1152 = phi i32 [ %.SV68.phi1092, %bb98 ], [ %.SV68.phi1203, %bb44.fragment ] ; <i32> [#uses=1]
+ %.SV70.phi1151 = phi i32 [ %.SV70.phi1091, %bb98 ], [ %.SV70.phi1202, %bb44.fragment ] ; <i32> [#uses=1]
+ %.load39.SV.phi = phi i64 [ %.SV38.phi1093, %bb98 ], [ undef, %bb44.fragment ] ; <i64> [#uses=2]
+ %.SV313.phi = phi i32* [ %237, %bb98 ], [ undef, %bb44.fragment ] ; <i32*> [#uses=1]
+ %.SV315.phi = phi i32* [ %239, %bb98 ], [ undef, %bb44.fragment ] ; <i32*> [#uses=1]
+ %.SV317.phi = phi i32* [ %240, %bb98 ], [ undef, %bb44.fragment ] ; <i32*> [#uses=3]
+ %.SV.phi1050 = phi i32 [ undef, %bb98 ], [ %.load127.SV.phi, %bb44.fragment ] ; <i32> [#uses=1]
+ %yM.0.SV.phi1049 = phi i32 [ undef, %bb98 ], [ %121, %bb44.fragment ] ; <i32> [#uses=1]
+ %meshStackVariable377.phi = phi i32 [ %Opq.sa.calc695, %bb98 ], [ %Opq.sa.calc894, %bb44.fragment ] ; <i32> [#uses=1]
+ %Opq.link.SV909.phi = phi i32 [ %Opq.sa.calc695, %bb98 ], [ %Opq.sa.calc856, %bb44.fragment ] ; <i32> [#uses=1]
+ %Opq.link.mask911 = and i32 %Opq.link.SV909.phi, 16 ; <i32> [#uses=2]
+ %Opq.sa.calc908 = add i32 %Opq.link.mask911, -11 ; <i32> [#uses=0]
+ %meshCmp379 = icmp eq i32 %meshStackVariable377.phi, 8 ; <i1> [#uses=1]
+ br i1 %meshCmp379, label %bb96, label %bb98.fragment
+
+meshBB380: ; preds = %bb92.fragment, %bb49.fragment
+ %.SV38.phi1207 = phi i64 [ %.SV38.phi1164, %bb92.fragment ], [ %.SV38.phi1179, %bb49.fragment ] ; <i64> [#uses=2]
+ %.SV68.phi1206 = phi i32 [ %.SV68.phi1162, %bb92.fragment ], [ %.SV68.phi1177, %bb49.fragment ] ; <i32> [#uses=2]
+ %.SV70.phi1205 = phi i32 [ %.SV70.phi1161, %bb92.fragment ], [ %.SV70.phi1176, %bb49.fragment ] ; <i32> [#uses=2]
+ %.SV104.phi1124 = phi i32 [ undef, %bb92.fragment ], [ %.SV104.phi1036, %bb49.fragment ] ; <i32> [#uses=1]
+ %.SV111.phi1123 = phi i32* [ undef, %bb92.fragment ], [ %.SV111.phi1035, %bb49.fragment ] ; <i32*> [#uses=1]
+ %.SV118.phi1122 = phi i32 [ undef, %bb92.fragment ], [ %.SV118.phi1040, %bb49.fragment ] ; <i32> [#uses=1]
+ %meshStackVariable381.phi = phi i32 [ %Opq.sa.calc1005, %bb92.fragment ], [ %Opq.sa.calc860, %bb49.fragment ] ; <i32> [#uses=1]
+ %Opq.link.SV947.phi = phi i32 [ %Opq.sa.calc1005, %bb92.fragment ], [ %Opq.sa.calc860, %bb49.fragment ] ; <i32> [#uses=1]
+ %.SV.phi1052 = phi i32 [ %.SV178.phi, %bb92.fragment ], [ undef, %bb49.fragment ] ; <i32> [#uses=1]
+ %yM.0.SV.phi1051 = phi i32 [ %226, %bb92.fragment ], [ undef, %bb49.fragment ] ; <i32> [#uses=1]
+ %Opq.link.mask949 = and i32 %Opq.link.SV947.phi, 1 ; <i32> [#uses=1]
+ %Opq.sa.calc946 = sub i32 %Opq.link.mask949, -4 ; <i32> [#uses=1]
+ %meshCmp383 = icmp eq i32 %meshStackVariable381.phi, 1 ; <i1> [#uses=1]
+ br i1 %meshCmp383, label %bb54, label %bb96
+
+meshBB384: ; preds = %bb95, %bb52
+ %.SV38.phi1221 = phi i64 [ %.SV38.phi1179, %bb52 ], [ %.SV38.phi1218, %bb95 ] ; <i64> [#uses=2]
+ %.SV68.phi1220 = phi i32 [ %.SV68.phi1177, %bb52 ], [ %.SV68.phi1216, %bb95 ] ; <i32> [#uses=2]
+ %.SV70.phi1219 = phi i32 [ %.SV70.phi1176, %bb52 ], [ %.SV70.phi1215, %bb95 ] ; <i32> [#uses=2]
+ %.load53.SV.phi = phi i32* [ undef, %bb52 ], [ %.SV52.phi1217, %bb95 ] ; <i32*> [#uses=1]
+ %.load20.SV.phi = phi i64 [ undef, %bb52 ], [ %3, %bb95 ] ; <i64> [#uses=1]
+ %.load.SV.phi = phi %struct.Macroblock* [ undef, %bb52 ], [ %2, %bb95 ] ; <%struct.Macroblock*> [#uses=1]
+ %.SV306.phi = phi i32 [ undef, %bb52 ], [ %227, %bb95 ] ; <i32> [#uses=1]
+ %.SV308.phi = phi i32* [ undef, %bb52 ], [ %228, %bb95 ] ; <i32*> [#uses=1]
+ %.load126.SV.phi = phi i32 [ %.SV118.phi1040, %bb52 ], [ undef, %bb95 ] ; <i32> [#uses=1]
+ %.load44.SV.phi = phi i32 [ %.SV43.phi1178, %bb52 ], [ undef, %bb95 ] ; <i32> [#uses=1]
+ %meshStackVariable385.phi = phi i32 [ %Opq.sa.calc583, %bb52 ], [ %Opq.sa.calc689, %bb95 ] ; <i32> [#uses=1]
+ %Opq.link.SV902.phi = phi i32 [ %Opq.sa.calc860, %bb52 ], [ %Opq.sa.calc689, %bb95 ] ; <i32> [#uses=1]
+ %Opq.link.SV905.phi = phi i32 [ %Opq.sa.calc584, %bb52 ], [ %Opq.sa.calc689, %bb95 ] ; <i32> [#uses=1]
+ %Opq.link.mask907 = and i32 %Opq.link.SV905.phi, 0 ; <i32> [#uses=0]
+ %Opq.link.mask904 = and i32 %Opq.link.SV902.phi, 1 ; <i32> [#uses=1]
+ %Opq.sa.calc901 = xor i32 %Opq.link.mask904, 227 ; <i32> [#uses=3]
+ %meshCmp387 = icmp eq i32 %meshStackVariable385.phi, 5 ; <i1> [#uses=1]
+ br i1 %meshCmp387, label %bb95.fragment, label %bb52.fragment
+
+meshBB388: ; preds = %bb52.fragment, %bb7
+ %.SV38.phi1118 = phi i64 [ %.SV38.phi1014, %bb7 ], [ %.SV38.phi1221, %bb52.fragment ] ; <i64> [#uses=2]
+ %.SV68.phi1117 = phi i32 [ %.SV68.phi1020, %bb7 ], [ %.SV68.phi1220, %bb52.fragment ] ; <i32> [#uses=2]
+ %.SV70.phi1116 = phi i32 [ %.SV70.phi1026, %bb7 ], [ %.SV70.phi1219, %bb52.fragment ] ; <i32> [#uses=2]
+ %.SV.phi1054 = phi i32 [ undef, %bb7 ], [ %.load126.SV.phi, %bb52.fragment ] ; <i32> [#uses=1]
+ %yM.0.SV.phi1053 = phi i32 [ undef, %bb7 ], [ %137, %bb52.fragment ] ; <i32> [#uses=1]
+ %.load67.SV.phi = phi i32* [ %.SV52.phi, %bb7 ], [ undef, %bb52.fragment ] ; <i32*> [#uses=1]
+ %.load36.SV.phi = phi i64 [ %3, %bb7 ], [ undef, %bb52.fragment ] ; <i64> [#uses=1]
+ %.load17.SV.phi = phi %struct.Macroblock* [ %2, %bb7 ], [ undef, %bb52.fragment ] ; <%struct.Macroblock*> [#uses=1]
+ %.SV194.phi = phi i32 [ %24, %bb7 ], [ undef, %bb52.fragment ] ; <i32> [#uses=1]
+ %.SV196.phi = phi i32* [ %25, %bb7 ], [ undef, %bb52.fragment ] ; <i32*> [#uses=1]
+ %meshStackVariable389.phi = phi i32 [ %Opq.sa.calc476, %bb7 ], [ %Opq.sa.calc844, %bb52.fragment ] ; <i32> [#uses=1]
+ %Opq.link.SV887.phi = phi i32 [ %Opq.sa.calc873, %bb7 ], [ %Opq.sa.calc901, %bb52.fragment ] ; <i32> [#uses=1]
+ %Opq.link.mask889 = and i32 %Opq.link.SV887.phi, 64 ; <i32> [#uses=1]
+ %Opq.sa.calc886 = sub i32 %Opq.link.mask889, -170 ; <i32> [#uses=2]
+ %meshCmp391 = icmp eq i32 %meshStackVariable389.phi, 12 ; <i1> [#uses=1]
+ br i1 %meshCmp391, label %bb96, label %bb7.fragment
+
+meshBB392: ; preds = %bb4, %entry
+ %meshStackVariable393.phi = phi i32 [ %Opq.sa.calc466, %bb4 ], [ %Opq.sa.calc, %entry ] ; <i32> [#uses=1]
+ %Opq.link.SV922.phi = phi i32 [ %Opq.sa.calc462, %bb4 ], [ %Opq.sa.calc, %entry ] ; <i32> [#uses=1]
+ %or.cond.not.SV.phi = phi i1 [ %or.cond.not, %bb4 ], [ undef, %entry ] ; <i1> [#uses=1]
+ %.SV70.phi1027 = phi i32 [ %12, %bb4 ], [ undef, %entry ] ; <i32> [#uses=2]
+ %.SV52.phi1022 = phi i32* [ %9, %bb4 ], [ undef, %entry ] ; <i32*> [#uses=1]
+ %.SV68.phi1021 = phi i32 [ %10, %bb4 ], [ undef, %entry ] ; <i32> [#uses=2]
+ %.SV43.phi1015 = phi i32 [ %8, %bb4 ], [ undef, %entry ] ; <i32> [#uses=3]
+ %Opq.link.mask924 = and i32 %Opq.link.SV922.phi, 2 ; <i32> [#uses=1]
+ %Opq.sa.calc921 = add i32 %Opq.link.mask924, 57 ; <i32> [#uses=3]
+ %meshCmp395 = icmp eq i32 %meshStackVariable393.phi, 2 ; <i1> [#uses=1]
+ br i1 %meshCmp395, label %entry.fragment, label %bb21
+
+meshBB396: ; preds = %bb69.fragment, %bb.fragment
+ %.SV.phi1065 = phi i32 [ undef, %bb.fragment ], [ %171, %bb69.fragment ] ; <i32> [#uses=1]
+ %meshStackVariable397.phi = phi i32 [ %Opq.sa.calc976, %bb.fragment ], [ %Opq.sa.calc995, %bb69.fragment ] ; <i32> [#uses=1]
+ %Opq.link.SV759.phi = phi i32 [ %Opq.sa.calc976, %bb.fragment ], [ %Opq.sa.calc995, %bb69.fragment ] ; <i32> [#uses=1]
+ %.SV70.phi = phi i32 [ %12, %bb.fragment ], [ %.SV70.phi1168, %bb69.fragment ] ; <i32> [#uses=1]
+ %.SV68.phi = phi i32 [ %10, %bb.fragment ], [ %.SV68.phi1169, %bb69.fragment ] ; <i32> [#uses=1]
+ %.SV38.phi = phi i64 [ %4, %bb.fragment ], [ %.SV38.phi1172, %bb69.fragment ] ; <i64> [#uses=1]
+ %Opq.link.mask761 = and i32 %Opq.link.SV759.phi, 6 ; <i32> [#uses=1]
+ %Opq.sa.calc758 = add i32 %Opq.link.mask761, 53 ; <i32> [#uses=1]
+ %meshCmp399 = icmp eq i32 %meshStackVariable397.phi, 6 ; <i1> [#uses=1]
+ br i1 %meshCmp399, label %bb96, label %return
+
+meshBB400: ; preds = %bb84, %bb69.fragment
+ %.SV38.phi1191 = phi i64 [ %.SV38.phi1098, %bb84 ], [ %.SV38.phi1172, %bb69.fragment ] ; <i64> [#uses=5]
+ %.SV52.phi1190 = phi i32* [ %.SV52.phi1097, %bb84 ], [ undef, %bb69.fragment ] ; <i32*> [#uses=3]
+ %.SV68.phi1189 = phi i32 [ %.SV68.phi1096, %bb84 ], [ %.SV68.phi1169, %bb69.fragment ] ; <i32> [#uses=5]
+ %.SV70.phi1188 = phi i32 [ %.SV70.phi1095, %bb84 ], [ %.SV70.phi1168, %bb69.fragment ] ; <i32> [#uses=5]
+ %.SV290.phi = phi i32 [ %200, %bb84 ], [ undef, %bb69.fragment ] ; <i32> [#uses=1]
+ %.SV164.phi = phi i32 [ undef, %bb84 ], [ %171, %bb69.fragment ] ; <i32> [#uses=2]
+ %meshStackVariable401.phi = phi i32 [ %Opq.sa.calc661, %bb84 ], [ %Opq.sa.calc996, %bb69.fragment ] ; <i32> [#uses=1]
+ %Opq.link.SV825.phi = phi i32 [ %Opq.sa.calc658, %bb84 ], [ %Opq.sa.calc996, %bb69.fragment ] ; <i32> [#uses=1]
+ %.SV162.phi = phi i32* [ undef, %bb84 ], [ %169, %bb69.fragment ] ; <i32*> [#uses=1]
+ %.SV156.phi = phi i32* [ undef, %bb84 ], [ %.SV274.phi, %bb69.fragment ] ; <i32*> [#uses=1]
+ %.SV158.phi = phi i32 [ undef, %bb84 ], [ %168, %bb69.fragment ] ; <i32> [#uses=1]
+ %Opq.link.mask827 = and i32 %Opq.link.SV825.phi, 4 ; <i32> [#uses=1]
+ %Opq.sa.calc824 = xor i32 %Opq.link.mask827, 228 ; <i32> [#uses=2]
+ %meshCmp403 = icmp eq i32 %meshStackVariable401.phi, 15 ; <i1> [#uses=1]
+ br i1 %meshCmp403, label %bb70, label %bb84.fragment
+
+meshBB404: ; preds = %bb96, %bb3
+ %yM.0.reg2mem.1.SV.phi1077 = phi i32 [ %yM.0.SV.phi, %bb96 ], [ undef, %bb3 ] ; <i32> [#uses=1]
+ %meshStackVariable405.phi = phi i32 [ %Opq.sa.calc692, %bb96 ], [ %Opq.sa.calc461, %bb3 ] ; <i32> [#uses=1]
+ %Opq.link.SV940.phi = phi i32 [ %Opq.sa.calc693, %bb96 ], [ %Opq.sa.calc461, %bb3 ] ; <i32> [#uses=1]
+ %or.cond.not.SV.phi1029 = phi i1 [ undef, %bb96 ], [ %or.cond.not, %bb3 ] ; <i1> [#uses=1]
+ %.SV70.phi1028 = phi i32 [ %.SV70.phi1085, %bb96 ], [ %12, %bb3 ] ; <i32> [#uses=2]
+ %.SV52.phi1024 = phi i32* [ undef, %bb96 ], [ %9, %bb3 ] ; <i32*> [#uses=1]
+ %.SV68.phi1023 = phi i32 [ %.SV68.phi1086, %bb96 ], [ %10, %bb3 ] ; <i32> [#uses=2]
+ %.SV38.phi1017 = phi i64 [ %.SV38.phi1087, %bb96 ], [ %4, %bb3 ] ; <i64> [#uses=2]
+ %.SV40.phi = phi i32 [ undef, %bb96 ], [ %6, %bb3 ] ; <i32> [#uses=1]
+ %Opq.link.mask942 = and i32 %Opq.link.SV940.phi, 6 ; <i32> [#uses=1]
+ %Opq.sa.calc939 = sub i32 %Opq.link.mask942, -87 ; <i32> [#uses=1]
+ %meshCmp407 = icmp eq i32 %meshStackVariable405.phi, 6 ; <i1> [#uses=1]
+ br i1 %meshCmp407, label %bb56, label %bb98
+
+meshBB408: ; preds = %bb89.fragment, %bb87
+ %.SV38.phi1218 = phi i64 [ %.SV38.phi1191, %bb89.fragment ], [ %.SV38.phi1210, %bb87 ] ; <i64> [#uses=2]
+ %.SV52.phi1217 = phi i32* [ %.SV52.phi1190, %bb89.fragment ], [ %.SV52.phi1235, %bb87 ] ; <i32*> [#uses=1]
+ %.SV68.phi1216 = phi i32 [ %.SV68.phi1189, %bb89.fragment ], [ %.SV68.phi1209, %bb87 ] ; <i32> [#uses=2]
+ %.SV70.phi1215 = phi i32 [ %.SV70.phi1188, %bb89.fragment ], [ %.SV70.phi1208, %bb87 ] ; <i32> [#uses=2]
+ %.SV172.phi1074 = phi i32 [ %211, %bb89.fragment ], [ undef, %bb87 ] ; <i32> [#uses=1]
+ %meshStackVariable409.phi = phi i32 [ %Opq.sa.calc962, %bb89.fragment ], [ %Opq.sa.calc673, %bb87 ] ; <i32> [#uses=1]
+ %Opq.link.SV913.phi = phi i32 [ %Opq.sa.calc962, %bb89.fragment ], [ %Opq.sa.calc990, %bb87 ] ; <i32> [#uses=1]
+ %Opq.link.mask915 = and i32 %Opq.link.SV913.phi, 9 ; <i32> [#uses=1]
+ %Opq.sa.calc912 = xor i32 %Opq.link.mask915, 195 ; <i32> [#uses=1]
+ %meshCmp411 = icmp eq i32 %meshStackVariable409.phi, 1 ; <i1> [#uses=1]
+ br i1 %meshCmp411, label %bb97, label %bb95
+
+meshBB412: ; preds = %bb68.fragment, %bb13.fragment
+ %.SV38.phi1187 = phi i64 [ %.SV38.phi1115, %bb13.fragment ], [ %.SV38.phi1172, %bb68.fragment ] ; <i64> [#uses=2]
+ %.SV52.phi1186 = phi i32* [ %.SV52.phi1113, %bb13.fragment ], [ %.SV52.phi1170, %bb68.fragment ] ; <i32*> [#uses=2]
+ %.SV68.phi1185 = phi i32 [ %.SV68.phi1112, %bb13.fragment ], [ %.SV68.phi1169, %bb68.fragment ] ; <i32> [#uses=2]
+ %.SV70.phi1184 = phi i32 [ %.SV70.phi1111, %bb13.fragment ], [ %.SV70.phi1168, %bb68.fragment ] ; <i32> [#uses=2]
+ %.SV158.phi1063 = phi i32 [ undef, %bb13.fragment ], [ %168, %bb68.fragment ] ; <i32> [#uses=1]
+ %.SV87.phi1030 = phi i32 [ %47, %bb13.fragment ], [ undef, %bb68.fragment ] ; <i32> [#uses=1]
+ %meshStackVariable413.phi = phi i32 [ %Opq.sa.calc870, %bb13.fragment ], [ %Opq.sa.calc784, %bb68.fragment ] ; <i32> [#uses=1]
+ %Opq.link.SV933.phi = phi i32 [ %Opq.sa.calc870, %bb13.fragment ], [ %Opq.link.mask722, %bb68.fragment ] ; <i32> [#uses=1]
+ %Opq.link.SV936.phi = phi i32 [ %Opq.sa.calc866, %bb13.fragment ], [ %Opq.sa.calc784, %bb68.fragment ] ; <i32> [#uses=1]
+ %Opq.link.mask938 = and i32 %Opq.link.SV936.phi, 4 ; <i32> [#uses=1]
+ %Opq.link.mask935 = and i32 %Opq.link.SV933.phi, 0 ; <i32> [#uses=1]
+ %Opq.sa.calc931 = sub i32 %Opq.link.mask935, %Opq.link.mask938 ; <i32> [#uses=1]
+ %Opq.sa.calc932 = xor i32 %Opq.sa.calc931, -51 ; <i32> [#uses=3]
+ %meshCmp415 = icmp eq i32 %meshStackVariable413.phi, 6 ; <i1> [#uses=1]
+ br i1 %meshCmp415, label %bb74, label %bb19
+
+meshBB416: ; preds = %bb90.fragment, %bb77
+ %.SV38.phi1201 = phi i64 [ %.SV38.phi1191, %bb90.fragment ], [ %.SV38.phi1098, %bb77 ] ; <i64> [#uses=2]
+ %.SV52.phi1200 = phi i32* [ undef, %bb90.fragment ], [ %.SV52.phi1097, %bb77 ] ; <i32*> [#uses=1]
+ %.SV68.phi1199 = phi i32 [ %.SV68.phi1189, %bb90.fragment ], [ %.SV68.phi1096, %bb77 ] ; <i32> [#uses=2]
+ %.SV70.phi1198 = phi i32 [ %.SV70.phi1188, %bb90.fragment ], [ %.SV70.phi1095, %bb77 ] ; <i32> [#uses=2]
+ %.SV.phi1076 = phi i32 [ %214, %bb90.fragment ], [ undef, %bb77 ] ; <i32> [#uses=1]
+ %meshStackVariable417.phi = phi i32 [ %Opq.sa.calc773, %bb90.fragment ], [ %Opq.sa.calc643, %bb77 ] ; <i32> [#uses=1]
+ %Opq.link.SV973.phi = phi i32 [ %Opq.sa.calc773, %bb90.fragment ], [ %Opq.sa.calc640, %bb77 ] ; <i32> [#uses=1]
+ %Opq.link.mask975 = and i32 %Opq.link.SV973.phi, 10 ; <i32> [#uses=1]
+ %Opq.sa.calc972 = xor i32 %Opq.link.mask975, 110 ; <i32> [#uses=1]
+ %Opq.sa.calc971 = add i32 %Opq.sa.calc972, -19 ; <i32> [#uses=1]
+ %meshCmp419 = icmp eq i32 %meshStackVariable417.phi, 12 ; <i1> [#uses=1]
+ br i1 %meshCmp419, label %bb78, label %bb96
+
+meshBB420: ; preds = %bb66, %bb26.fragment
+ %.SV38.phi1194 = phi i64 [ %.SV38.phi1098, %bb66 ], [ %.SV38.phi1167, %bb26.fragment ] ; <i64> [#uses=2]
+ %.SV68.phi1193 = phi i32 [ %.SV68.phi1096, %bb66 ], [ %.SV68.phi1166, %bb26.fragment ] ; <i32> [#uses=2]
+ %.SV70.phi1192 = phi i32 [ %.SV70.phi1095, %bb66 ], [ %.SV70.phi1165, %bb26.fragment ] ; <i32> [#uses=2]
+ %.load61.SV.phi = phi i32* [ %.SV52.phi1097, %bb66 ], [ undef, %bb26.fragment ] ; <i32*> [#uses=1]
+ %.SV270.phi = phi i32 [ %165, %bb66 ], [ undef, %bb26.fragment ] ; <i32> [#uses=1]
+ %.SV272.phi = phi i32* [ %166, %bb66 ], [ undef, %bb26.fragment ] ; <i32*> [#uses=1]
+ %.SV.phi1044 = phi i32 [ undef, %bb66 ], [ %.load123.SV.phi, %bb26.fragment ] ; <i32> [#uses=1]
+ %meshStackVariable421.phi = phi i32 [ %Opq.sa.calc621, %bb66 ], [ %Opq.sa.calc918, %bb26.fragment ] ; <i32> [#uses=1]
+ %Opq.link.SV838.phi = phi i32 [ %Opq.sa.calc602, %bb66 ], [ %Opq.sa.calc918, %bb26.fragment ] ; <i32> [#uses=1]
+ %Opq.link.mask840 = and i32 %Opq.link.SV838.phi, 9 ; <i32> [#uses=2]
+ %Opq.sa.calc837 = sub i32 %Opq.link.mask840, -202 ; <i32> [#uses=2]
+ %Opq.sa.calc835 = sub i32 %Opq.sa.calc837, %Opq.link.mask840 ; <i32> [#uses=1]
+ %Opq.sa.calc836 = xor i32 %Opq.sa.calc835, 176 ; <i32> [#uses=0]
+ %meshCmp423 = icmp eq i32 %meshStackVariable421.phi, 9 ; <i1> [#uses=1]
+ br i1 %meshCmp423, label %bb96, label %bb66.fragment
+
+meshBB424: ; preds = %bb86.fragment, %bb83
+ %.SV38.phi1197 = phi i64 [ %.SV38.phi1231, %bb86.fragment ], [ %.SV38.phi1098, %bb83 ] ; <i64> [#uses=2]
+ %.SV68.phi1196 = phi i32 [ %.SV68.phi1229, %bb86.fragment ], [ %.SV68.phi1096, %bb83 ] ; <i32> [#uses=2]
+ %.SV70.phi1195 = phi i32 [ %.SV70.phi1228, %bb86.fragment ], [ %.SV70.phi1095, %bb83 ] ; <i32> [#uses=2]
+ %.SV.phi1072 = phi i32 [ %209, %bb86.fragment ], [ undef, %bb83 ] ; <i32> [#uses=1]
+ %meshStackVariable425.phi = phi i32 [ %Opq.sa.calc943, %bb86.fragment ], [ %Opq.sa.calc658, %bb83 ] ; <i32> [#uses=1]
+ %Opq.link.SV951.phi = phi i32 [ %Opq.sa.calc943, %bb86.fragment ], [ %Opq.sa.calc1002, %bb83 ] ; <i32> [#uses=1]
+ %Opq.link.mask953 = and i32 %Opq.link.SV951.phi, 12 ; <i32> [#uses=1]
+ %Opq.sa.calc950 = sub i32 %Opq.link.mask953, -208 ; <i32> [#uses=0]
+ %meshCmp427 = icmp eq i32 %meshStackVariable425.phi, 4 ; <i1> [#uses=1]
+ br i1 %meshCmp427, label %bb97, label %bb96
+
+meshBB428: ; preds = %bb70, %bb4
+ %.SV158.phi1090 = phi i32 [ %.SV158.phi, %bb70 ], [ undef, %bb4 ] ; <i32> [#uses=1]
+ %.SV162.phi1089 = phi i32* [ %.SV162.phi, %bb70 ], [ undef, %bb4 ] ; <i32*> [#uses=1]
+ %.SV164.phi1088 = phi i32 [ %.SV164.phi, %bb70 ], [ undef, %bb4 ] ; <i32> [#uses=1]
+ %.load165.SV.phi = phi i32 [ %.SV164.phi, %bb70 ], [ undef, %bb4 ] ; <i32> [#uses=1]
+ %.SV278.phi = phi %struct.Macroblock* [ %176, %bb70 ], [ undef, %bb4 ] ; <%struct.Macroblock*> [#uses=1]
+ %.SV280.phi = phi i32 [ %177, %bb70 ], [ undef, %bb4 ] ; <i32> [#uses=1]
+ %meshStackVariable429.phi = phi i32 [ %Opq.sa.calc630, %bb70 ], [ %Opq.sa.calc467, %bb4 ] ; <i32> [#uses=1]
+ %Opq.link.SV898.phi = phi i32 [ %Opq.sa.calc630, %bb70 ], [ %Opq.sa.calc462, %bb4 ] ; <i32> [#uses=1]
+ %.SV70.phi1026 = phi i32 [ %.SV70.phi1188, %bb70 ], [ %12, %bb4 ] ; <i32> [#uses=5]
+ %.SV52.phi = phi i32* [ undef, %bb70 ], [ %9, %bb4 ] ; <i32*> [#uses=3]
+ %.SV68.phi1020 = phi i32 [ %.SV68.phi1189, %bb70 ], [ %10, %bb4 ] ; <i32> [#uses=5]
+ %.SV38.phi1014 = phi i64 [ %.SV38.phi1191, %bb70 ], [ %4, %bb4 ] ; <i64> [#uses=5]
+ %.SV43.phi = phi i32 [ undef, %bb70 ], [ %8, %bb4 ] ; <i32> [#uses=1]
+ %Opq.link.mask900 = and i32 %Opq.link.SV898.phi, 4 ; <i32> [#uses=1]
+ %Opq.sa.calc897 = xor i32 %Opq.link.mask900, 193 ; <i32> [#uses=3]
+ %meshCmp431 = icmp eq i32 %meshStackVariable429.phi, 5 ; <i1> [#uses=1]
+ br i1 %meshCmp431, label %bb5, label %bb70.fragment
+
+meshBB432: ; preds = %bb42, %bb23.fragment182
+ %.SV38.phi1179 = phi i64 [ %.SV38.phi1115, %bb23.fragment182 ], [ %.SV38.phi1231, %bb42 ] ; <i64> [#uses=7]
+ %.SV43.phi1178 = phi i32 [ %.SV43.phi1015, %bb23.fragment182 ], [ %.SV43.phi1230, %bb42 ] ; <i32> [#uses=3]
+ %.SV68.phi1177 = phi i32 [ %.SV68.phi1112, %bb23.fragment182 ], [ %.SV68.phi1229, %bb42 ] ; <i32> [#uses=7]
+ %.SV70.phi1176 = phi i32 [ %.SV70.phi1111, %bb23.fragment182 ], [ %.SV70.phi1228, %bb42 ] ; <i32> [#uses=7]
+ %.SV118.phi1040 = phi i32 [ %76, %bb23.fragment182 ], [ %.SV118.phi1125, %bb42 ] ; <i32> [#uses=7]
+ %.SV135.phi1039 = phi i1 [ %78, %bb23.fragment182 ], [ undef, %bb42 ] ; <i1> [#uses=2]
+ %meshStackVariable433.phi = phi i32 [ %Opq.sa.calc744, %bb23.fragment182 ], [ %Opq.sa.calc560, %bb42 ] ; <i32> [#uses=1]
+ %Opq.link.SV799.phi = phi i32 [ %Opq.sa.calc744, %bb23.fragment182 ], [ %Opq.sa.calc987, %bb42 ] ; <i32> [#uses=1]
+ %.SV96.phi1038 = phi i1 [ %71, %bb23.fragment182 ], [ undef, %bb42 ] ; <i1> [#uses=1]
+ %.SV99.phi1037 = phi i32* [ %72, %bb23.fragment182 ], [ undef, %bb42 ] ; <i32*> [#uses=2]
+ %.SV104.phi1036 = phi i32 [ %73, %bb23.fragment182 ], [ %.SV104.phi1127, %bb42 ] ; <i32> [#uses=3]
+ %.SV111.phi1035 = phi i32* [ %74, %bb23.fragment182 ], [ %.SV111.phi1126, %bb42 ] ; <i32*> [#uses=3]
+ %Opq.link.mask801 = and i32 %Opq.link.SV799.phi, 6 ; <i32> [#uses=1]
+ %Opq.sa.calc798 = xor i32 %Opq.link.mask801, 3 ; <i32> [#uses=5]
+ %meshCmp435 = icmp eq i32 %meshStackVariable433.phi, 1 ; <i1> [#uses=1]
+ br i1 %meshCmp435, label %bb43, label %bb39
+
+meshBB436: ; preds = %bb71.fragment, %bb65
+ %.SV38.phi1147 = phi i64 [ %.SV38.phi1144, %bb65 ], [ %.SV38.phi1140, %bb71.fragment ] ; <i64> [#uses=2]
+ %.SV68.phi1146 = phi i32 [ %.SV68.phi1142, %bb65 ], [ %.SV68.phi1139, %bb71.fragment ] ; <i32> [#uses=2]
+ %.SV70.phi1145 = phi i32 [ %.SV70.phi1141, %bb65 ], [ %.SV70.phi1138, %bb71.fragment ] ; <i32> [#uses=2]
+ %.SV.phi1067 = phi i32 [ undef, %bb65 ], [ %.load166.SV.phi, %bb71.fragment ] ; <i32> [#uses=1]
+ %yM.0.SV.phi1066 = phi i32 [ undef, %bb65 ], [ %183, %bb71.fragment ] ; <i32> [#uses=1]
+ %.load62.SV.phi = phi i32* [ %.SV52.phi1143, %bb65 ], [ undef, %bb71.fragment ] ; <i32*> [#uses=1]
+ %.SV268.phi = phi i32 [ %164, %bb65 ], [ undef, %bb71.fragment ] ; <i32> [#uses=2]
+ %meshStackVariable437.phi = phi i32 [ %Opq.sa.calc617, %bb65 ], [ %Opq.sa.calc809, %bb71.fragment ] ; <i32> [#uses=1]
+ %Opq.link.SV704.phi = phi i32 [ %Opq.sa.calc617, %bb65 ], [ %Opq.sa.calc809, %bb71.fragment ] ; <i32> [#uses=1]
+ %Opq.link.mask706 = and i32 %Opq.link.SV704.phi, 0 ; <i32> [#uses=2]
+ %Opq.sa.calc703 = add i32 %Opq.link.mask706, 216 ; <i32> [#uses=0]
+ %meshCmp439 = icmp eq i32 %meshStackVariable437.phi, 2 ; <i1> [#uses=1]
+ br i1 %meshCmp439, label %bb96, label %bb65.fragment
+
+meshBB440: ; preds = %bb85, %bb54.fragment
+ %.SV52.phi1235 = phi i32* [ %.SV52.phi1213, %bb85 ], [ undef, %bb54.fragment ] ; <i32*> [#uses=2]
+ %.SV38.phi1210 = phi i64 [ %.SV38.phi1214, %bb85 ], [ %.SV38.phi1207, %bb54.fragment ] ; <i64> [#uses=2]
+ %.SV68.phi1209 = phi i32 [ %.SV68.phi1212, %bb85 ], [ %.SV68.phi1206, %bb54.fragment ] ; <i32> [#uses=2]
+ %.SV70.phi1208 = phi i32 [ %.SV70.phi1211, %bb85 ], [ %.SV70.phi1205, %bb54.fragment ] ; <i32> [#uses=2]
+ %.SV.phi1056 = phi i32 [ undef, %bb85 ], [ %.SV118.phi1122, %bb54.fragment ] ; <i32> [#uses=1]
+ %meshStackVariable441.phi = phi i32 [ %Opq.sa.calc666, %bb85 ], [ %Opq.sa.calc883, %bb54.fragment ] ; <i32> [#uses=1]
+ %Opq.link.SV991.phi = phi i32 [ %Opq.sa.calc665, %bb85 ], [ %Opq.sa.calc883, %bb54.fragment ] ; <i32> [#uses=1]
+ %Opq.link.mask993 = and i32 %Opq.link.SV991.phi, 6 ; <i32> [#uses=1]
+ %Opq.sa.calc990 = xor i32 %Opq.link.mask993, 139 ; <i32> [#uses=2]
+ %meshCmp443 = icmp eq i32 %meshStackVariable441.phi, 6 ; <i1> [#uses=1]
+ br i1 %meshCmp443, label %bb96, label %bb87
+
+meshBB444: ; preds = %bb66.fragment, %bb40
+ %.SV38.phi1224 = phi i64 [ %.SV38.phi1194, %bb66.fragment ], [ %.SV38.phi1179, %bb40 ] ; <i64> [#uses=2]
+ %.SV68.phi1223 = phi i32 [ %.SV68.phi1193, %bb66.fragment ], [ %.SV68.phi1177, %bb40 ] ; <i32> [#uses=2]
+ %.SV70.phi1222 = phi i32 [ %.SV70.phi1192, %bb66.fragment ], [ %.SV70.phi1176, %bb40 ] ; <i32> [#uses=2]
+ %.SV.phi1048 = phi i32 [ undef, %bb66.fragment ], [ %.SV118.phi1040, %bb40 ] ; <i32> [#uses=1]
+ %meshStackVariable445.phi = phi i32 [ %Opq.sa.calc794, %bb66.fragment ], [ %Opq.sa.calc554, %bb40 ] ; <i32> [#uses=1]
+ %Opq.link.SV781.phi = phi i32 [ %Opq.sa.calc795, %bb66.fragment ], [ %Opq.sa.calc554, %bb40 ] ; <i32> [#uses=1]
+ %Opq.link.mask783 = and i32 %Opq.link.SV781.phi, 10 ; <i32> [#uses=1]
+ %Opq.sa.calc780 = add i32 %Opq.link.mask783, 1 ; <i32> [#uses=0]
+ %meshCmp447 = icmp eq i32 %meshStackVariable445.phi, 11 ; <i1> [#uses=1]
+ br i1 %meshCmp447, label %bb96, label %bb98
+
+meshBB448: ; preds = %bb35, %entry.fragment181
+ %.SV70.phi1233 = phi i32 [ undef, %entry.fragment181 ], [ %.SV70.phi1180, %bb35 ] ; <i32> [#uses=1]
+ %.SV104.phi1157 = phi i32 [ undef, %entry.fragment181 ], [ %.SV104.phi1084, %bb35 ] ; <i32> [#uses=1]
+ %.SV111.phi1156 = phi i32* [ undef, %entry.fragment181 ], [ %.SV111.phi1083, %bb35 ] ; <i32*> [#uses=1]
+ %.SV118.phi1155 = phi i32 [ undef, %entry.fragment181 ], [ %.SV118.phi1082, %bb35 ] ; <i32> [#uses=1]
+ %.SV68.phi1025 = phi i32 [ %10, %entry.fragment181 ], [ %.SV68.phi1181, %bb35 ] ; <i32> [#uses=1]
+ %meshStackVariable449.phi = phi i32 [ %Opq.sa.calc863, %entry.fragment181 ], [ %Opq.sa.calc541, %bb35 ] ; <i32> [#uses=1]
+ %Opq.link.SV959.phi = phi i32 [ %Opq.sa.calc863, %entry.fragment181 ], [ %Opq.sa.calc828, %bb35 ] ; <i32> [#uses=1]
+ %.SV38.phi1019 = phi i64 [ %4, %entry.fragment181 ], [ %.SV38.phi1183, %bb35 ] ; <i64> [#uses=1]
+ %.SV43.phi1018 = phi i32 [ %8, %entry.fragment181 ], [ %.SV43.phi1015, %bb35 ] ; <i32> [#uses=2]
+ %Opq.link.mask961 = and i32 %Opq.link.SV959.phi, 1 ; <i32> [#uses=1]
+ %Opq.sa.calc958 = xor i32 %Opq.link.mask961, 63 ; <i32> [#uses=3]
+ %Opq.sa.calc957 = xor i32 %Opq.sa.calc958, 126 ; <i32> [#uses=1]
+ %meshCmp451 = icmp eq i32 %meshStackVariable449.phi, 5 ; <i1> [#uses=1]
+ br i1 %meshCmp451, label %bb37, label %return
+
+meshBB452: ; preds = %bb70.fragment, %bb63
+ %.SV38.phi1110 = phi i64 [ %.SV38.phi1014, %bb70.fragment ], [ %.SV38.phi1098, %bb63 ] ; <i64> [#uses=3]
+ %.SV52.phi1109 = phi i32* [ undef, %bb70.fragment ], [ %.SV52.phi1097, %bb63 ] ; <i32*> [#uses=2]
+ %.SV68.phi1108 = phi i32 [ %.SV68.phi1020, %bb70.fragment ], [ %.SV68.phi1096, %bb63 ] ; <i32> [#uses=3]
+ %.SV70.phi1107 = phi i32 [ %.SV70.phi1026, %bb70.fragment ], [ %.SV70.phi1095, %bb63 ] ; <i32> [#uses=3]
+ %.SV158.phi1106 = phi i32 [ %.SV158.phi1090, %bb70.fragment ], [ undef, %bb63 ] ; <i32> [#uses=1]
+ %.SV162.phi1105 = phi i32* [ %.SV162.phi1089, %bb70.fragment ], [ undef, %bb63 ] ; <i32*> [#uses=1]
+ %.SV164.phi1104 = phi i32 [ %.SV164.phi1088, %bb70.fragment ], [ undef, %bb63 ] ; <i32> [#uses=1]
+ %.SV264.phi = phi %struct.Macroblock* [ undef, %bb70.fragment ], [ %157, %bb63 ] ; <%struct.Macroblock*> [#uses=1]
+ %.SV266.phi = phi i32 [ undef, %bb70.fragment ], [ %158, %bb63 ] ; <i32> [#uses=1]
+ %meshStackVariable453.phi = phi i32 [ %Opq.sa.calc739, %bb70.fragment ], [ %Opq.sa.calc611, %bb63 ] ; <i32> [#uses=1]
+ %Opq.link.SV821.phi = phi i32 [ %Opq.sa.calc897, %bb70.fragment ], [ %Opq.sa.calc611, %bb63 ] ; <i32> [#uses=1]
+ %.SV150.phi1060 = phi i32* [ undef, %bb70.fragment ], [ %148, %bb63 ] ; <i32*> [#uses=1]
+ %.SV152.phi1059 = phi i32* [ undef, %bb70.fragment ], [ %149, %bb63 ] ; <i32*> [#uses=2]
+ %.SV148.phi1057 = phi i32 [ undef, %bb70.fragment ], [ %147, %bb63 ] ; <i32> [#uses=1]
+ %Opq.link.mask823 = and i32 %Opq.link.SV821.phi, 4 ; <i32> [#uses=2]
+ %Opq.sa.calc820 = sub i32 %Opq.link.mask823, -97 ; <i32> [#uses=2]
+ %meshCmp455 = icmp eq i32 %meshStackVariable453.phi, 6 ; <i1> [#uses=1]
+ br i1 %meshCmp455, label %bb63.fragment, label %bb71
+
+meshBB456: ; preds = %bb79, %bb63.fragment
+ %.SV38.phi1137 = phi i64 [ %.SV38.phi1110, %bb63.fragment ], [ %.SV38.phi1098, %bb79 ] ; <i64> [#uses=2]
+ %.SV52.phi1136 = phi i32* [ %.SV52.phi1109, %bb63.fragment ], [ %.SV52.phi1097, %bb79 ] ; <i32*> [#uses=2]
+ %.SV68.phi1135 = phi i32 [ %.SV68.phi1108, %bb63.fragment ], [ %.SV68.phi1096, %bb79 ] ; <i32> [#uses=2]
+ %.SV70.phi1134 = phi i32 [ %.SV70.phi1107, %bb63.fragment ], [ %.SV70.phi1095, %bb79 ] ; <i32> [#uses=2]
+ %.SV152.phi1133 = phi i32* [ %.SV152.phi1059, %bb63.fragment ], [ undef, %bb79 ] ; <i32*> [#uses=1]
+ %meshStackVariable457.phi = phi i32 [ %Opq.sa.calc890, %bb63.fragment ], [ %Opq.sa.calc651, %bb79 ] ; <i32> [#uses=1]
+ %Opq.link.SV817.phi = phi i32 [ %Opq.sa.calc891, %bb63.fragment ], [ %Opq.sa.calc651, %bb79 ] ; <i32> [#uses=1]
+ %Opq.link.mask819 = and i32 %Opq.link.SV817.phi, 2 ; <i32> [#uses=1]
+ %Opq.sa.calc816 = add i32 %Opq.link.mask819, 186 ; <i32> [#uses=2]
+ %meshCmp459 = icmp eq i32 %meshStackVariable457.phi, 10 ; <i1> [#uses=1]
+ br i1 %meshCmp459, label %bb81, label %bb65
+}
diff --git a/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert.ll b/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert.ll
new file mode 100644
index 0000000..d77e528
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin9
+; PR4056
+
+define void @int163(i32 %p_4, i32 %p_5) nounwind {
+entry:
+ %0 = tail call i32 @bar(i32 1) nounwind ; <i32> [#uses=2]
+ %1 = icmp sgt i32 %0, 7 ; <i1> [#uses=1]
+ br i1 %1, label %foo.exit, label %bb.i
+
+bb.i: ; preds = %entry
+ %2 = lshr i32 1, %0 ; <i32> [#uses=1]
+ %3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
+ %4 = zext i1 %3 to i32 ; <i32> [#uses=1]
+ %.p_5 = shl i32 %p_5, %4 ; <i32> [#uses=1]
+ br label %foo.exit
+
+foo.exit: ; preds = %bb.i, %entry
+ %5 = phi i32 [ %.p_5, %bb.i ], [ %p_5, %entry ] ; <i32> [#uses=1]
+ %6 = icmp eq i32 %5, 0 ; <i1> [#uses=0]
+ %7 = tail call i32 @bar(i32 %p_5) nounwind ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @bar(i32)
diff --git a/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert2.ll b/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert2.ll
new file mode 100644
index 0000000..f025654
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-27-LiveIntervalsAssert2.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin9
+; PR4051
+
+define void @int163(i32 %p_4, i32 %p_5) nounwind {
+entry:
+ %0 = tail call i32 @foo(i32 1) nounwind ; <i32> [#uses=2]
+ %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %bb.i, label %bar.exit
+
+bb.i: ; preds = %entry
+ %2 = lshr i32 1, %0 ; <i32> [#uses=1]
+ %3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
+ %retval.i = select i1 %3, i32 1, i32 %p_5 ; <i32> [#uses=1]
+ br label %bar.exit
+
+bar.exit: ; preds = %bb.i, %entry
+ %4 = phi i32 [ %retval.i, %bb.i ], [ %p_5, %entry ] ; <i32> [#uses=1]
+ %5 = icmp eq i32 %4, 0 ; <i1> [#uses=0]
+ %6 = tail call i32 @foo(i32 %p_5) nounwind ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @foo(i32)
diff --git a/test/CodeGen/X86/2009-04-27-LiveIntervalsBug.ll b/test/CodeGen/X86/2009-04-27-LiveIntervalsBug.ll
new file mode 100644
index 0000000..0a2fcdb
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-27-LiveIntervalsBug.ll
@@ -0,0 +1,165 @@
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu | grep cmpxchgl | not grep eax
+; PR4076
+
+ type { i8, i8, i8 } ; type %0
+ type { i32, i8** } ; type %1
+ type { %3* } ; type %2
+ type { %4 } ; type %3
+ type { %5 } ; type %4
+ type { %6, i32, %7 } ; type %5
+ type { i8* } ; type %6
+ type { i32, [12 x i8] } ; type %7
+ type { %9 } ; type %8
+ type { %10, %11*, i8 } ; type %9
+ type { %11* } ; type %10
+ type { i32, %6, i8*, %12, %13*, i8, i32, %28, %29, i32, %30, i32, i32, i32, i8*, i8*, i8, i8 } ; type %11
+ type { %13* } ; type %12
+ type { %14, i32, %13*, %21 } ; type %13
+ type { %15, %16 } ; type %14
+ type { i32 (...)** } ; type %15
+ type { %17, i8* (i32)*, void (i8*)*, i8 } ; type %16
+ type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %18 } ; type %17
+ type { %19* } ; type %18
+ type { i32, %20**, i32, %20**, i8** } ; type %19
+ type { i32 (...)**, i32 } ; type %20
+ type { %22, %25*, i8, i8, %17*, %26*, %27*, %27* } ; type %21
+ type { i32 (...)**, i32, i32, i32, i32, i32, %23*, %24, [8 x %24], i32, %24*, %18 } ; type %22
+ type { %23*, void (i32, %22*, i32)*, i32, i32 } ; type %23
+ type { i8*, i32 } ; type %24
+ type { i32 (...)**, %21 } ; type %25
+ type { %20, i32*, i8, i32*, i32*, i16*, i8, [256 x i8], [256 x i8], i8 } ; type %26
+ type { %20 } ; type %27
+ type { void (%9*)*, i32 } ; type %28
+ type { %15* } ; type %29
+ type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8* } ; type %30
+@AtomicOps_Internalx86CPUFeatures = external global %0 ; <%0*> [#uses=1]
+internal constant [19 x i8] c"xxxxxxxxxxxxxxxxxx\00" ; <[19 x i8]*>:0 [#uses=1]
+internal constant [47 x i8] c"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\00" ; <[47 x i8]*>:1 [#uses=1]
+
+define i8** @func6(i8 zeroext, i32, i32, %1*) nounwind {
+; <label>:4
+ %5 = alloca i32, align 4 ; <i32*> [#uses=2]
+ %6 = alloca i32, align 4 ; <i32*> [#uses=2]
+ %7 = alloca %2, align 8 ; <%2*> [#uses=3]
+ %8 = alloca %8, align 8 ; <%8*> [#uses=2]
+ br label %17
+
+; <label>:9 ; preds = %17
+ %10 = getelementptr %1* %3, i32 %19, i32 0 ; <i32*> [#uses=1]
+ %11 = load i32* %10, align 4 ; <i32> [#uses=1]
+ %12 = icmp eq i32 %11, %2 ; <i1> [#uses=1]
+ br i1 %12, label %13, label %16
+
+; <label>:13 ; preds = %9
+ %14 = getelementptr %1* %3, i32 %19, i32 1 ; <i8***> [#uses=1]
+ %15 = load i8*** %14, align 4 ; <i8**> [#uses=1]
+ ret i8** %15
+
+; <label>:16 ; preds = %9
+ %indvar.next13 = add i32 %18, 1 ; <i32> [#uses=1]
+ br label %17
+
+; <label>:17 ; preds = %16, %4
+ %18 = phi i32 [ 0, %4 ], [ %indvar.next13, %16 ] ; <i32> [#uses=2]
+ %19 = add i32 %18, %1 ; <i32> [#uses=3]
+ %20 = icmp sgt i32 %19, 3 ; <i1> [#uses=1]
+ br i1 %20, label %21, label %9
+
+; <label>:21 ; preds = %17
+ call void @func5()
+ %22 = getelementptr %1* %3, i32 0, i32 0 ; <i32*> [#uses=1]
+ %23 = load i32* %22, align 4 ; <i32> [#uses=1]
+ %24 = icmp eq i32 %23, 0 ; <i1> [#uses=1]
+ br i1 %24, label %._crit_edge, label %._crit_edge1
+
+._crit_edge1: ; preds = %._crit_edge1, %21
+ %25 = phi i32 [ 0, %21 ], [ %26, %._crit_edge1 ] ; <i32> [#uses=1]
+ %26 = add i32 %25, 1 ; <i32> [#uses=4]
+ %27 = getelementptr %1* %3, i32 %26, i32 0 ; <i32*> [#uses=1]
+ %28 = load i32* %27, align 4 ; <i32> [#uses=1]
+ %29 = icmp ne i32 %28, 0 ; <i1> [#uses=1]
+ %30 = icmp ne i32 %26, 4 ; <i1> [#uses=1]
+ %31 = and i1 %29, %30 ; <i1> [#uses=1]
+ br i1 %31, label %._crit_edge1, label %._crit_edge
+
+._crit_edge: ; preds = %._crit_edge1, %21
+ %32 = phi i32 [ 0, %21 ], [ %26, %._crit_edge1 ] ; <i32> [#uses=3]
+ %33 = call i8* @pthread_getspecific(i32 0) nounwind ; <i8*> [#uses=2]
+ %34 = icmp ne i8* %33, null ; <i1> [#uses=1]
+ %35 = icmp eq i8 %0, 0 ; <i1> [#uses=1]
+ %36 = or i1 %34, %35 ; <i1> [#uses=1]
+ br i1 %36, label %._crit_edge4, label %37
+
+; <label>:37 ; preds = %._crit_edge
+ %38 = call i8* @func2(i32 2048) ; <i8*> [#uses=4]
+ call void @llvm.memset.i32(i8* %38, i8 0, i32 2048, i32 4)
+ %39 = call i32 @pthread_setspecific(i32 0, i8* %38) nounwind ; <i32> [#uses=2]
+ store i32 %39, i32* %5
+ store i32 0, i32* %6
+ %40 = icmp eq i32 %39, 0 ; <i1> [#uses=1]
+ br i1 %40, label %41, label %43
+
+; <label>:41 ; preds = %37
+ %42 = getelementptr %2* %7, i32 0, i32 0 ; <%3**> [#uses=1]
+ store %3* null, %3** %42, align 8
+ br label %._crit_edge4
+
+; <label>:43 ; preds = %37
+ %44 = call %3* @func1(i32* %5, i32* %6, i8* getelementptr ([47 x i8]* @1, i32 0, i32 0)) ; <%3*> [#uses=2]
+ %45 = getelementptr %2* %7, i32 0, i32 0 ; <%3**> [#uses=1]
+ store %3* %44, %3** %45, align 8
+ %46 = icmp eq %3* %44, null ; <i1> [#uses=1]
+ br i1 %46, label %._crit_edge4, label %47
+
+; <label>:47 ; preds = %43
+ call void @func4(%8* %8, i8* getelementptr ([19 x i8]* @0, i32 0, i32 0), i32 165, %2* %7)
+ call void @func3(%8* %8) noreturn
+ unreachable
+
+._crit_edge4: ; preds = %43, %41, %._crit_edge
+ %48 = phi i8* [ %38, %41 ], [ %33, %._crit_edge ], [ %38, %43 ] ; <i8*> [#uses=2]
+ %49 = bitcast i8* %48 to i8** ; <i8**> [#uses=3]
+ %50 = icmp ne i8* %48, null ; <i1> [#uses=1]
+ %51 = icmp slt i32 %32, 4 ; <i1> [#uses=1]
+ %52 = and i1 %50, %51 ; <i1> [#uses=1]
+ br i1 %52, label %53, label %._crit_edge6
+
+; <label>:53 ; preds = %._crit_edge4
+ %54 = getelementptr %1* %3, i32 %32, i32 0 ; <i32*> [#uses=1]
+ %55 = call i32 asm sideeffect "lock; cmpxchgl $1,$2", "={ax},q,*m,0,~{dirflag},~{fpsr},~{flags},~{memory}"(i32 %2, i32* %54, i32 0) nounwind ; <i32> [#uses=1]
+ %56 = load i8* getelementptr (%0* @AtomicOps_Internalx86CPUFeatures, i32 0, i32 0), align 8 ; <i8> [#uses=1]
+ %57 = icmp eq i8 %56, 0 ; <i1> [#uses=1]
+ br i1 %57, label %._crit_edge7, label %58
+
+; <label>:58 ; preds = %53
+ call void asm sideeffect "lfence", "~{dirflag},~{fpsr},~{flags},~{memory}"() nounwind
+ br label %._crit_edge7
+
+._crit_edge7: ; preds = %58, %53
+ %59 = icmp eq i32 %55, 0 ; <i1> [#uses=1]
+ br i1 %59, label %60, label %._crit_edge6
+
+._crit_edge6: ; preds = %._crit_edge7, %._crit_edge4
+ ret i8** %49
+
+; <label>:60 ; preds = %._crit_edge7
+ %61 = getelementptr %1* %3, i32 %32, i32 1 ; <i8***> [#uses=1]
+ store i8** %49, i8*** %61, align 4
+ ret i8** %49
+}
+
+declare %3* @func1(i32* nocapture, i32* nocapture, i8*)
+
+declare void @func5()
+
+declare void @func4(%8*, i8*, i32, %2*)
+
+declare void @func3(%8*) noreturn
+
+declare i8* @pthread_getspecific(i32) nounwind
+
+declare i8* @func2(i32)
+
+declare void @llvm.memset.i32(i8* nocapture, i8, i32, i32) nounwind
+
+declare i32 @pthread_setspecific(i32, i8*) nounwind
diff --git a/test/CodeGen/X86/2009-04-29-IndirectDestOperands.ll b/test/CodeGen/X86/2009-04-29-IndirectDestOperands.ll
new file mode 100644
index 0000000..a2fd2e4
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-29-IndirectDestOperands.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s | grep {movl.*%ebx, 8(%esi)}
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.0"
+
+define void @cpuid(i32* %data) nounwind {
+entry:
+ %arrayidx = getelementptr i32* %data, i32 1 ; <i32*> [#uses=1]
+ %arrayidx2 = getelementptr i32* %data, i32 2 ; <i32*> [#uses=1]
+ %arrayidx4 = getelementptr i32* %data, i32 3 ; <i32*> [#uses=1]
+ %arrayidx6 = getelementptr i32* %data, i32 4 ; <i32*> [#uses=1]
+ %arrayidx8 = getelementptr i32* %data, i32 5 ; <i32*> [#uses=1]
+ %tmp9 = load i32* %arrayidx8 ; <i32> [#uses=1]
+ %arrayidx11 = getelementptr i32* %data, i32 6 ; <i32*> [#uses=1]
+ %tmp12 = load i32* %arrayidx11 ; <i32> [#uses=1]
+ %arrayidx14 = getelementptr i32* %data, i32 7 ; <i32*> [#uses=1]
+ %tmp15 = load i32* %arrayidx14 ; <i32> [#uses=1]
+ %arrayidx17 = getelementptr i32* %data, i32 8 ; <i32*> [#uses=1]
+ %tmp18 = load i32* %arrayidx17 ; <i32> [#uses=1]
+ %0 = call i32 asm "cpuid", "={ax},=*{bx},=*{cx},=*{dx},{ax},{bx},{cx},{dx},~{dirflag},~{fpsr},~{flags}"(i32* %arrayidx2, i32* %arrayidx4, i32* %arrayidx6, i32 %tmp9, i32 %tmp12, i32 %tmp15, i32 %tmp18) nounwind ; <i32> [#uses=1]
+ store i32 %0, i32* %arrayidx
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-04-29-LinearScanBug.ll b/test/CodeGen/X86/2009-04-29-LinearScanBug.ll
new file mode 100644
index 0000000..6843723
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-29-LinearScanBug.ll
@@ -0,0 +1,215 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin10
+; rdar://6837009
+
+ type { %struct.pf_state*, %struct.pf_state*, %struct.pf_state*, i32 } ; type %0
+ type { %2 } ; type %1
+ type { %struct.pf_addr, %struct.pf_addr } ; type %2
+ type { %struct.in6_addr } ; type %3
+ type { [4 x i32] } ; type %4
+ type { %struct.pfi_dynaddr*, [4 x i8] } ; type %5
+ type { %struct.pfi_dynaddr*, %struct.pfi_dynaddr** } ; type %6
+ type { %struct.pfr_ktable*, %struct.pfr_ktable*, %struct.pfr_ktable*, i32 } ; type %7
+ type { %struct.pfr_ktable* } ; type %8
+ type { i8* } ; type %9
+ type { %11 } ; type %10
+ type { i8*, i8*, %struct.radix_node* } ; type %11
+ type { [2 x %struct.pf_rulequeue], %13, %13 } ; type %12
+ type { %struct.pf_rulequeue*, %struct.pf_rule**, i32, i32, i32 } ; type %13
+ type { %struct.pf_anchor*, %struct.pf_anchor*, %struct.pf_anchor*, i32 } ; type %14
+ type { %struct.pfi_kif*, %struct.pfi_kif*, %struct.pfi_kif*, i32 } ; type %15
+ type { %struct.ifnet*, %struct.ifnet** } ; type %16
+ type { %18 } ; type %17
+ type { %struct.pkthdr, %19 } ; type %18
+ type { %struct.m_ext, [176 x i8] } ; type %19
+ type { %struct.ifmultiaddr*, %struct.ifmultiaddr** } ; type %20
+ type { i32, %22 } ; type %21
+ type { i8*, [4 x i8] } ; type %22
+ type { %struct.tcphdr* } ; type %23
+ type { %struct.pf_ike_state } ; type %24
+ type { %struct.pf_state_key*, %struct.pf_state_key*, %struct.pf_state_key*, i32 } ; type %25
+ type { %struct.pf_src_node*, %struct.pf_src_node*, %struct.pf_src_node*, i32 } ; type %26
+ %struct.anon = type { %struct.pf_state*, %struct.pf_state** }
+ %struct.au_mask_t = type { i32, i32 }
+ %struct.bpf_if = type opaque
+ %struct.dlil_threading_info = type opaque
+ %struct.ether_header = type { [6 x i8], [6 x i8], i16 }
+ %struct.ext_refsq = type { %struct.ext_refsq*, %struct.ext_refsq* }
+ %struct.hook_desc = type { %struct.hook_desc_head, void (i8*)*, i8* }
+ %struct.hook_desc_head = type { %struct.hook_desc*, %struct.hook_desc** }
+ %struct.if_data_internal = type { i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, %struct.au_mask_t, i32, i32, i32 }
+ %struct.ifaddr = type { %struct.sockaddr*, %struct.sockaddr*, %struct.sockaddr*, %struct.ifnet*, %struct.ifaddrhead, void (i32, %struct.rtentry*, %struct.sockaddr*)*, i32, i32, i32, void (%struct.ifaddr*)*, void (%struct.ifaddr*, i32)*, i32 }
+ %struct.ifaddrhead = type { %struct.ifaddr*, %struct.ifaddr** }
+ %struct.ifmultiaddr = type { %20, %struct.sockaddr*, %struct.ifmultiaddr*, %struct.ifnet*, i32, i8*, i32, void (i8*)* }
+ %struct.ifmultihead = type { %struct.ifmultiaddr* }
+ %struct.ifnet = type { i8*, i8*, %16, %struct.ifaddrhead, i32, i32 (%struct.ifnet*, %struct.sockaddr*)*, i32, %struct.bpf_if*, i16, i16, i16, i16, i32, i8*, i32, %struct.if_data_internal, i32, i32 (%struct.ifnet*, %struct.mbuf*)*, i32 (%struct.ifnet*, i32, i8*)*, i32 (%struct.ifnet*, i32, i32 (%struct.ifnet*, %struct.mbuf*)*)*, void (%struct.ifnet*)*, i32 (%struct.ifnet*, %struct.mbuf*, i8*, i32*)*, void (%struct.ifnet*, %struct.kev_msg*)*, i32 (%struct.ifnet*, %struct.mbuf**, %struct.sockaddr*, i8*, i8*)*, i32, %struct.ifnet_filter_head, i32, i8*, i32, %struct.ifmultihead, i32, i32 (%struct.ifnet*, i32, %struct.ifnet_demux_desc*, i32)*, i32 (%struct.ifnet*, i32)*, %struct.proto_hash_entry*, i8*, %struct.dlil_threading_info*, i8*, %struct.ifqueue, [1 x i32], i32, %struct.ifprefixhead, %struct.lck_rw_t*, %21, i32, %struct.thread*, %struct.pfi_kif*, %struct.lck_mtx_t*, %struct.route }
+ %struct.ifnet_demux_desc = type { i32, i8*, i32 }
+ %struct.ifnet_filter = type opaque
+ %struct.ifnet_filter_head = type { %struct.ifnet_filter*, %struct.ifnet_filter** }
+ %struct.ifprefix = type { %struct.sockaddr*, %struct.ifnet*, %struct.ifprefixhead, i8, i8 }
+ %struct.ifprefixhead = type { %struct.ifprefix*, %struct.ifprefix** }
+ %struct.ifqueue = type { i8*, i8*, i32, i32, i32 }
+ %struct.in6_addr = type { %4 }
+ %struct.in_addr = type { i32 }
+ %struct.kev_d_vectors = type { i32, i8* }
+ %struct.kev_msg = type { i32, i32, i32, i32, [5 x %struct.kev_d_vectors] }
+ %struct.lck_mtx_t = type { [3 x i32] }
+ %struct.lck_rw_t = type <{ [3 x i32] }>
+ %struct.m_ext = type { i8*, void (i8*, i32, i8*)*, i32, i8*, %struct.ext_refsq, %struct.au_mask_t* }
+ %struct.m_hdr = type { %struct.mbuf*, %struct.mbuf*, i32, i8*, i16, i16 }
+ %struct.m_tag = type { %struct.packet_tags, i16, i16, i32 }
+ %struct.mbuf = type { %struct.m_hdr, %17 }
+ %struct.packet_tags = type { %struct.m_tag* }
+ %struct.pf_addr = type { %3 }
+ %struct.pf_addr_wrap = type <{ %1, %5, i8, i8, [6 x i8] }>
+ %struct.pf_anchor = type { %14, %14, %struct.pf_anchor*, %struct.pf_anchor_node, [64 x i8], [1024 x i8], %struct.pf_ruleset, i32, i32 }
+ %struct.pf_anchor_node = type { %struct.pf_anchor* }
+ %struct.pf_app_state = type { void (%struct.pf_state*, i32, i32, %struct.pf_pdesc*, %struct.pfi_kif*)*, i32 (%struct.pf_app_state*, %struct.pf_app_state*)*, i32 (%struct.pf_app_state*, %struct.pf_app_state*)*, %24 }
+ %struct.pf_ike_state = type { i64 }
+ %struct.pf_mtag = type { i8*, i32, i32, i16, i8, i8 }
+ %struct.pf_palist = type { %struct.pf_pooladdr*, %struct.pf_pooladdr** }
+ %struct.pf_pdesc = type { %struct.pf_threshold, i64, %23, %struct.pf_addr, %struct.pf_addr, %struct.pf_rule*, %struct.pf_addr*, %struct.pf_addr*, %struct.ether_header*, %struct.mbuf*, i32, %struct.pf_mtag*, i16*, i32, i16, i8, i8, i8, i8 }
+ %struct.pf_pool = type { %struct.pf_palist, [2 x i32], %struct.pf_pooladdr*, [4 x i8], %struct.in6_addr, %struct.pf_addr, i32, [2 x i16], i8, i8, [1 x i32] }
+ %struct.pf_pooladdr = type <{ %struct.pf_addr_wrap, %struct.pf_palist, [2 x i32], [16 x i8], %struct.pfi_kif*, [1 x i32] }>
+ %struct.pf_rule = type <{ %struct.pf_rule_addr, %struct.pf_rule_addr, [8 x %struct.pf_rule_ptr], [64 x i8], [16 x i8], [64 x i8], [64 x i8], [64 x i8], [64 x i8], [32 x i8], %struct.pf_rulequeue, [2 x i32], %struct.pf_pool, i64, [2 x i64], [2 x i64], %struct.pfi_kif*, [4 x i8], %struct.pf_anchor*, [4 x i8], %struct.pfr_ktable*, [4 x i8], i32, i32, [26 x i32], i32, i32, i32, i32, i32, i32, %struct.au_mask_t, i32, i32, i32, i32, i32, i32, i32, i16, i16, i16, i16, i16, [2 x i8], %struct.pf_rule_gid, %struct.pf_rule_gid, i32, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, [2 x i8] }>
+ %struct.pf_rule_addr = type <{ %struct.pf_addr_wrap, %struct.pf_rule_xport, i8, [7 x i8] }>
+ %struct.pf_rule_gid = type { [2 x i32], i8, [3 x i8] }
+ %struct.pf_rule_ptr = type { %struct.pf_rule*, [4 x i8] }
+ %struct.pf_rule_xport = type { i32, [4 x i8] }
+ %struct.pf_rulequeue = type { %struct.pf_rule*, %struct.pf_rule** }
+ %struct.pf_ruleset = type { [5 x %12], %struct.pf_anchor*, i32, i32, i32 }
+ %struct.pf_src_node = type <{ %26, %struct.pf_addr, %struct.pf_addr, %struct.pf_rule_ptr, %struct.pfi_kif*, [2 x i64], [2 x i64], i32, i32, %struct.pf_threshold, i64, i64, i8, i8, [2 x i8] }>
+ %struct.pf_state = type <{ i64, i32, i32, %struct.anon, %struct.anon, %0, %struct.pf_state_peer, %struct.pf_state_peer, %struct.pf_rule_ptr, %struct.pf_rule_ptr, %struct.pf_rule_ptr, %struct.pf_addr, %struct.hook_desc_head, %struct.pf_state_key*, %struct.pfi_kif*, %struct.pfi_kif*, %struct.pf_src_node*, %struct.pf_src_node*, [2 x i64], [2 x i64], i64, i64, i64, i16, i8, i8, i8, i8, [6 x i8] }>
+ %struct.pf_state_host = type { %struct.pf_addr, %struct.in_addr }
+ %struct.pf_state_key = type { %struct.pf_state_host, %struct.pf_state_host, %struct.pf_state_host, i8, i8, i8, i8, %struct.pf_app_state*, %25, %25, %struct.anon, i16 }
+ %struct.pf_state_peer = type { i32, i32, i32, i16, i8, i8, i16, i8, %struct.pf_state_scrub*, [3 x i8] }
+ %struct.pf_state_scrub = type { %struct.au_mask_t, i32, i32, i32, i16, i8, i8, i32 }
+ %struct.pf_threshold = type { i32, i32, i32, i32 }
+ %struct.pfi_dynaddr = type { %6, %struct.pf_addr, %struct.pf_addr, %struct.pf_addr, %struct.pf_addr, %struct.pfr_ktable*, %struct.pfi_kif*, i8*, i32, i32, i32, i8, i8 }
+ %struct.pfi_kif = type { [16 x i8], %15, [2 x [2 x [2 x i64]]], [2 x [2 x [2 x i64]]], i64, i32, i8*, %struct.ifnet*, i32, i32, %6 }
+ %struct.pfr_ktable = type { %struct.pfr_tstats, %7, %8, %struct.radix_node_head*, %struct.radix_node_head*, %struct.pfr_ktable*, %struct.pfr_ktable*, %struct.pf_ruleset*, i64, i32 }
+ %struct.pfr_table = type { [1024 x i8], [32 x i8], i32, i8 }
+ %struct.pfr_tstats = type { %struct.pfr_table, [2 x [3 x i64]], [2 x [3 x i64]], i64, i64, i64, i32, [2 x i32] }
+ %struct.pkthdr = type { i32, %struct.ifnet*, i8*, i32, i32, i32, i16, i16, %struct.packet_tags }
+ %struct.proto_hash_entry = type opaque
+ %struct.radix_mask = type { i16, i8, i8, %struct.radix_mask*, %9, i32 }
+ %struct.radix_node = type { %struct.radix_mask*, %struct.radix_node*, i16, i8, i8, %10 }
+ %struct.radix_node_head = type { %struct.radix_node*, i32, i32, %struct.radix_node* (i8*, i8*, %struct.radix_node_head*, %struct.radix_node*)*, %struct.radix_node* (i8*, i8*, %struct.radix_node_head*, %struct.radix_node*)*, %struct.radix_node* (i8*, i8*, %struct.radix_node_head*)*, %struct.radix_node* (i8*, i8*, %struct.radix_node_head*)*, %struct.radix_node* (i8*, %struct.radix_node_head*)*, %struct.radix_node* (i8*, %struct.radix_node_head*, i32 (%struct.radix_node*, i8*)*, i8*)*, %struct.radix_node* (i8*, i8*, %struct.radix_node_head*)*, %struct.radix_node* (i8*, i8*, %struct.radix_node_head*, i32 (%struct.radix_node*, i8*)*, i8*)*, %struct.radix_node* (i8*, %struct.radix_node_head*)*, i32 (%struct.radix_node_head*, i32 (%struct.radix_node*, i8*)*, i8*)*, i32 (%struct.radix_node_head*, i8*, i8*, i32 (%struct.radix_node*, i8*)*, i8*)*, void (%struct.radix_node*, %struct.radix_node_head*)*, [3 x %struct.radix_node], i32 }
+ %struct.route = type { %struct.rtentry*, i32, %struct.sockaddr }
+ %struct.rt_metrics = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x i32] }
+ %struct.rtentry = type { [2 x %struct.radix_node], %struct.sockaddr*, i32, i32, %struct.ifnet*, %struct.ifaddr*, %struct.sockaddr*, i8*, void (i8*)*, %struct.rt_metrics, %struct.rtentry*, %struct.rtentry*, i32, %struct.lck_mtx_t }
+ %struct.sockaddr = type { i8, i8, [14 x i8] }
+ %struct.tcphdr = type { i16, i16, i32, i32, i8, i8, i16, i16, i16 }
+ %struct.thread = type opaque
[email protected] = appending global [1 x i8*] [i8* bitcast (i32 (%struct.pf_state_key*, %struct.pf_state_key*)* @pf_state_compare_ext_gwy to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define fastcc i32 @pf_state_compare_ext_gwy(%struct.pf_state_key* nocapture %a, %struct.pf_state_key* nocapture %b) nounwind optsize ssp {
+entry:
+ %0 = zext i8 0 to i32 ; <i32> [#uses=2]
+ %1 = load i8* null, align 1 ; <i8> [#uses=2]
+ %2 = zext i8 %1 to i32 ; <i32> [#uses=1]
+ %3 = sub i32 %0, %2 ; <i32> [#uses=1]
+ %4 = icmp eq i8 0, %1 ; <i1> [#uses=1]
+ br i1 %4, label %bb1, label %bb79
+
+bb1: ; preds = %entry
+ %5 = load i8* null, align 4 ; <i8> [#uses=2]
+ %6 = zext i8 %5 to i32 ; <i32> [#uses=2]
+ %7 = getelementptr %struct.pf_state_key* %b, i32 0, i32 3 ; <i8*> [#uses=1]
+ %8 = load i8* %7, align 4 ; <i8> [#uses=2]
+ %9 = zext i8 %8 to i32 ; <i32> [#uses=1]
+ %10 = sub i32 %6, %9 ; <i32> [#uses=1]
+ %11 = icmp eq i8 %5, %8 ; <i1> [#uses=1]
+ br i1 %11, label %bb3, label %bb79
+
+bb3: ; preds = %bb1
+ switch i32 %0, label %bb23 [
+ i32 1, label %bb4
+ i32 6, label %bb6
+ i32 17, label %bb10
+ i32 47, label %bb17
+ i32 50, label %bb21
+ i32 58, label %bb4
+ ]
+
+bb4: ; preds = %bb3, %bb3
+ %12 = load i16* null, align 4 ; <i16> [#uses=1]
+ %13 = zext i16 %12 to i32 ; <i32> [#uses=1]
+ %14 = sub i32 0, %13 ; <i32> [#uses=1]
+ br i1 false, label %bb23, label %bb79
+
+bb6: ; preds = %bb3
+ %15 = load i16* null, align 4 ; <i16> [#uses=1]
+ %16 = zext i16 %15 to i32 ; <i32> [#uses=1]
+ %17 = sub i32 0, %16 ; <i32> [#uses=1]
+ ret i32 %17
+
+bb10: ; preds = %bb3
+ %18 = load i8* null, align 1 ; <i8> [#uses=2]
+ %19 = zext i8 %18 to i32 ; <i32> [#uses=1]
+ %20 = sub i32 0, %19 ; <i32> [#uses=1]
+ %21 = icmp eq i8 0, %18 ; <i1> [#uses=1]
+ br i1 %21, label %bb12, label %bb79
+
+bb12: ; preds = %bb10
+ %22 = load i16* null, align 4 ; <i16> [#uses=1]
+ %23 = zext i16 %22 to i32 ; <i32> [#uses=1]
+ %24 = sub i32 0, %23 ; <i32> [#uses=1]
+ ret i32 %24
+
+bb17: ; preds = %bb3
+ %25 = load i8* null, align 1 ; <i8> [#uses=2]
+ %26 = icmp eq i8 %25, 1 ; <i1> [#uses=1]
+ br i1 %26, label %bb18, label %bb23
+
+bb18: ; preds = %bb17
+ %27 = icmp eq i8 %25, 0 ; <i1> [#uses=1]
+ br i1 %27, label %bb19, label %bb23
+
+bb19: ; preds = %bb18
+ %28 = load i16* null, align 4 ; <i16> [#uses=1]
+ %29 = zext i16 %28 to i32 ; <i32> [#uses=1]
+ %30 = sub i32 0, %29 ; <i32> [#uses=1]
+ br i1 false, label %bb23, label %bb79
+
+bb21: ; preds = %bb3
+ %31 = getelementptr %struct.pf_state_key* %a, i32 0, i32 1, i32 1, i32 0 ; <i32*> [#uses=1]
+ %32 = load i32* %31, align 4 ; <i32> [#uses=2]
+ %33 = getelementptr %struct.pf_state_key* %b, i32 0, i32 1, i32 1, i32 0 ; <i32*> [#uses=1]
+ %34 = load i32* %33, align 4 ; <i32> [#uses=2]
+ %35 = sub i32 %32, %34 ; <i32> [#uses=1]
+ %36 = icmp eq i32 %32, %34 ; <i1> [#uses=1]
+ br i1 %36, label %bb23, label %bb79
+
+bb23: ; preds = %bb21, %bb19, %bb18, %bb17, %bb4, %bb3
+ %cond = icmp eq i32 %6, 2 ; <i1> [#uses=1]
+ br i1 %cond, label %bb24, label %bb70
+
+bb24: ; preds = %bb23
+ ret i32 1
+
+bb70: ; preds = %bb23
+ %37 = load i32 (%struct.pf_app_state*, %struct.pf_app_state*)** null, align 4 ; <i32 (%struct.pf_app_state*, %struct.pf_app_state*)*> [#uses=3]
+ br i1 false, label %bb78, label %bb73
+
+bb73: ; preds = %bb70
+ %38 = load i32 (%struct.pf_app_state*, %struct.pf_app_state*)** null, align 4 ; <i32 (%struct.pf_app_state*, %struct.pf_app_state*)*> [#uses=2]
+ %39 = icmp eq i32 (%struct.pf_app_state*, %struct.pf_app_state*)* %38, null ; <i1> [#uses=1]
+ br i1 %39, label %bb78, label %bb74
+
+bb74: ; preds = %bb73
+ %40 = ptrtoint i32 (%struct.pf_app_state*, %struct.pf_app_state*)* %37 to i32 ; <i32> [#uses=1]
+ %41 = sub i32 0, %40 ; <i32> [#uses=1]
+ %42 = icmp eq i32 (%struct.pf_app_state*, %struct.pf_app_state*)* %38, %37 ; <i1> [#uses=1]
+ br i1 %42, label %bb76, label %bb79
+
+bb76: ; preds = %bb74
+ %43 = tail call i32 %37(%struct.pf_app_state* null, %struct.pf_app_state* null) nounwind ; <i32> [#uses=1]
+ ret i32 %43
+
+bb78: ; preds = %bb73, %bb70
+ ret i32 0
+
+bb79: ; preds = %bb74, %bb21, %bb19, %bb10, %bb4, %bb1, %entry
+ %.0 = phi i32 [ %3, %entry ], [ %10, %bb1 ], [ %14, %bb4 ], [ %20, %bb10 ], [ %30, %bb19 ], [ %35, %bb21 ], [ %41, %bb74 ] ; <i32> [#uses=1]
+ ret i32 %.0
+}
diff --git a/test/CodeGen/X86/2009-04-29-RegAllocAssert.ll b/test/CodeGen/X86/2009-04-29-RegAllocAssert.ll
new file mode 100644
index 0000000..d1f9cf8
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-29-RegAllocAssert.ll
@@ -0,0 +1,117 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -disable-fp-elim -relocation-model=pic
+; PR4099
+
+ type { [62 x %struct.Bitvec*] } ; type %0
+ type { i8* } ; type %1
+ type { double } ; type %2
+ %struct..5sPragmaType = type { i8*, i32 }
+ %struct.AggInfo = type { i8, i8, i32, %struct.ExprList*, i32, %struct.AggInfo_col*, i32, i32, i32, %struct.AggInfo_func*, i32, i32 }
+ %struct.AggInfo_col = type { %struct.Table*, i32, i32, i32, i32, %struct.Expr* }
+ %struct.AggInfo_func = type { %struct.Expr*, %struct.FuncDef*, i32, i32 }
+ %struct.AuxData = type { i8*, void (i8*)* }
+ %struct.Bitvec = type { i32, i32, i32, %0 }
+ %struct.BtCursor = type { %struct.Btree*, %struct.BtShared*, %struct.BtCursor*, %struct.BtCursor*, i32 (i8*, i32, i8*, i32, i8*)*, i8*, i32, %struct.MemPage*, i32, %struct.CellInfo, i8, i8, i8*, i64, i32, i8, i32* }
+ %struct.BtLock = type { %struct.Btree*, i32, i8, %struct.BtLock* }
+ %struct.BtShared = type { %struct.Pager*, %struct.sqlite3*, %struct.BtCursor*, %struct.MemPage*, i8, i8, i8, i8, i8, i8, i8, i8, i32, i16, i16, i32, i32, i32, i32, i8, i32, i8*, void (i8*)*, %struct.sqlite3_mutex*, %struct.BusyHandler, i32, %struct.BtShared*, %struct.BtLock*, %struct.Btree* }
+ %struct.Btree = type { %struct.sqlite3*, %struct.BtShared*, i8, i8, i8, i32, %struct.Btree*, %struct.Btree* }
+ %struct.BtreeMutexArray = type { i32, [11 x %struct.Btree*] }
+ %struct.BusyHandler = type { i32 (i8*, i32)*, i8*, i32 }
+ %struct.CellInfo = type { i8*, i64, i32, i32, i16, i16, i16, i16 }
+ %struct.CollSeq = type { i8*, i8, i8, i8*, i32 (i8*, i32, i8*, i32, i8*)*, void (i8*)* }
+ %struct.Column = type { i8*, %struct.Expr*, i8*, i8*, i8, i8, i8, i8 }
+ %struct.Context = type { i64, i32, %struct.Fifo }
+ %struct.CountCtx = type { i64 }
+ %struct.Cursor = type { %struct.BtCursor*, i32, i64, i64, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i64, %struct.Btree*, i32, i8*, i64, i8*, %struct.KeyInfo*, i32, i64, %struct.sqlite3_vtab_cursor*, %struct.sqlite3_module*, i32, i32, i32*, i32*, i8* }
+ %struct.Db = type { i8*, %struct.Btree*, i8, i8, i8*, void (i8*)*, %struct.Schema* }
+ %struct.DbPage = type { %struct.Pager*, i32, %struct.DbPage*, %struct.DbPage*, %struct.PagerLruLink, %struct.DbPage*, i8, i8, i8, i8, i8, i16, %struct.DbPage*, %struct.DbPage*, i8* }
+ %struct.Expr = type { i8, i8, i16, %struct.CollSeq*, %struct.Expr*, %struct.Expr*, %struct.ExprList*, %struct..5sPragmaType, %struct..5sPragmaType, i32, i32, %struct.AggInfo*, i32, i32, %struct.Select*, %struct.Table*, i32 }
+ %struct.ExprList = type { i32, i32, i32, %struct.ExprList_item* }
+ %struct.ExprList_item = type { %struct.Expr*, i8*, i8, i8, i8 }
+ %struct.FKey = type { %struct.Table*, %struct.FKey*, i8*, %struct.FKey*, i32, %struct.sColMap*, i8, i8, i8, i8 }
+ %struct.Fifo = type { i32, %struct.FifoPage*, %struct.FifoPage* }
+ %struct.FifoPage = type { i32, i32, i32, %struct.FifoPage*, [1 x i64] }
+ %struct.FuncDef = type { i16, i8, i8, i8, i8*, %struct.FuncDef*, void (%struct.sqlite3_context*, i32, %struct.Mem**)*, void (%struct.sqlite3_context*, i32, %struct.Mem**)*, void (%struct.sqlite3_context*)*, [1 x i8] }
+ %struct.Hash = type { i8, i8, i32, i32, %struct.HashElem*, %struct._ht* }
+ %struct.HashElem = type { %struct.HashElem*, %struct.HashElem*, i8*, i8*, i32 }
+ %struct.IdList = type { %struct..5sPragmaType*, i32, i32 }
+ %struct.Index = type { i8*, i32, i32*, i32*, %struct.Table*, i32, i8, i8, i8*, %struct.Index*, %struct.Schema*, i8*, i8** }
+ %struct.KeyInfo = type { %struct.sqlite3*, i8, i8, i8, i32, i8*, [1 x %struct.CollSeq*] }
+ %struct.Mem = type { %struct.CountCtx, double, %struct.sqlite3*, i8*, i32, i16, i8, i8, void (i8*)* }
+ %struct.MemPage = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i16, i16, i16, i16, i16, i16, [5 x %struct._OvflCell], %struct.BtShared*, i8*, %struct.DbPage*, i32, %struct.MemPage* }
+ %struct.Module = type { %struct.sqlite3_module*, i8*, i8*, void (i8*)* }
+ %struct.Op = type { i8, i8, i8, i8, i32, i32, i32, %1 }
+ %struct.Pager = type { %struct.sqlite3_vfs*, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.Bitvec*, %struct.Bitvec*, i8*, i8*, i8*, i8*, %struct.sqlite3_file*, %struct.sqlite3_file*, %struct.sqlite3_file*, %struct.BusyHandler*, %struct.PagerLruList, %struct.DbPage*, %struct.DbPage*, %struct.DbPage*, i64, i64, i64, i64, i64, i32, void (%struct.DbPage*, i32)*, void (%struct.DbPage*, i32)*, i32, %struct.DbPage**, i8*, [16 x i8] }
+ %struct.PagerLruLink = type { %struct.DbPage*, %struct.DbPage* }
+ %struct.PagerLruList = type { %struct.DbPage*, %struct.DbPage*, %struct.DbPage* }
+ %struct.Schema = type { i32, %struct.Hash, %struct.Hash, %struct.Hash, %struct.Hash, %struct.Table*, i8, i8, i16, i32, %struct.sqlite3* }
+ %struct.Select = type { %struct.ExprList*, i8, i8, i8, i8, i8, i8, i8, %struct.SrcList*, %struct.Expr*, %struct.ExprList*, %struct.Expr*, %struct.ExprList*, %struct.Select*, %struct.Select*, %struct.Select*, %struct.Expr*, %struct.Expr*, i32, i32, [3 x i32] }
+ %struct.SrcList = type { i16, i16, [1 x %struct.SrcList_item] }
+ %struct.SrcList_item = type { i8*, i8*, i8*, %struct.Table*, %struct.Select*, i8, i8, i32, %struct.Expr*, %struct.IdList*, i64 }
+ %struct.Table = type { i8*, i32, %struct.Column*, i32, %struct.Index*, i32, %struct.Select*, i32, %struct.Trigger*, %struct.FKey*, i8*, %struct.Expr*, i32, i8, i8, i8, i8, i8, i8, i8, %struct.Module*, %struct.sqlite3_vtab*, i32, i8**, %struct.Schema* }
+ %struct.Trigger = type { i8*, i8*, i8, i8, %struct.Expr*, %struct.IdList*, %struct..5sPragmaType, %struct.Schema*, %struct.Schema*, %struct.TriggerStep*, %struct.Trigger* }
+ %struct.TriggerStep = type { i32, i32, %struct.Trigger*, %struct.Select*, %struct..5sPragmaType, %struct.Expr*, %struct.ExprList*, %struct.IdList*, %struct.TriggerStep*, %struct.TriggerStep* }
+ %struct.Vdbe = type { %struct.sqlite3*, %struct.Vdbe*, %struct.Vdbe*, i32, i32, %struct.Op*, i32, i32, i32*, %struct.Mem**, %struct.Mem*, i32, %struct.Cursor**, i32, %struct.Mem*, i8**, i32, i32, i32, %struct.Mem*, i32, i32, %struct.Fifo, i32, i32, %struct.Context*, i32, i32, i32, i32, i32, [25 x i32], i32, i32, i8**, i8*, %struct.Mem*, i8, i8, i8, i8, i8, i8, i32, i64, i32, %struct.BtreeMutexArray, i32, i8*, i32 }
+ %struct.VdbeFunc = type { %struct.FuncDef*, i32, [1 x %struct.AuxData] }
+ %struct._OvflCell = type { i8*, i16 }
+ %struct._ht = type { i32, %struct.HashElem* }
+ %struct.sColMap = type { i32, i8* }
+ %struct.sqlite3 = type { %struct.sqlite3_vfs*, i32, %struct.Db*, i32, i32, i32, i32, i8, i8, i8, i8, i32, %struct.CollSeq*, i64, i64, i32, i32, i32, %struct.sqlite3_mutex*, %struct.sqlite3InitInfo, i32, i8**, %struct.Vdbe*, i32, void (i8*, i8*)*, i8*, void (i8*, i8*, i64)*, i8*, i8*, i32 (i8*)*, i8*, void (i8*)*, i8*, void (i8*, i32, i8*, i8*, i64)*, void (i8*, %struct.sqlite3*, i32, i8*)*, void (i8*, %struct.sqlite3*, i32, i8*)*, i8*, %struct.Mem*, i8*, i8*, %2, i32 (i8*, i32, i8*, i8*, i8*, i8*)*, i8*, i32 (i8*)*, i8*, i32, %struct.Hash, %struct.Table*, %struct.sqlite3_vtab**, i32, %struct.Hash, %struct.Hash, %struct.BusyHandler, i32, [2 x %struct.Db], i8 }
+ %struct.sqlite3InitInfo = type { i32, i32, i8 }
+ %struct.sqlite3_context = type { %struct.FuncDef*, %struct.VdbeFunc*, %struct.Mem, %struct.Mem*, i32, %struct.CollSeq* }
+ %struct.sqlite3_file = type { %struct.sqlite3_io_methods* }
+ %struct.sqlite3_index_constraint = type { i32, i8, i8, i32 }
+ %struct.sqlite3_index_constraint_usage = type { i32, i8 }
+ %struct.sqlite3_index_info = type { i32, %struct.sqlite3_index_constraint*, i32, %struct.sqlite3_index_constraint_usage*, %struct.sqlite3_index_constraint_usage*, i32, i8*, i32, i32, double }
+ %struct.sqlite3_io_methods = type { i32, i32 (%struct.sqlite3_file*)*, i32 (%struct.sqlite3_file*, i8*, i32, i64)*, i32 (%struct.sqlite3_file*, i8*, i32, i64)*, i32 (%struct.sqlite3_file*, i64)*, i32 (%struct.sqlite3_file*, i32)*, i32 (%struct.sqlite3_file*, i64*)*, i32 (%struct.sqlite3_file*, i32)*, i32 (%struct.sqlite3_file*, i32)*, i32 (%struct.sqlite3_file*)*, i32 (%struct.sqlite3_file*, i32, i8*)*, i32 (%struct.sqlite3_file*)*, i32 (%struct.sqlite3_file*)* }
+ %struct.sqlite3_module = type { i32, i32 (%struct.sqlite3*, i8*, i32, i8**, %struct.sqlite3_vtab**, i8**)*, i32 (%struct.sqlite3*, i8*, i32, i8**, %struct.sqlite3_vtab**, i8**)*, i32 (%struct.sqlite3_vtab*, %struct.sqlite3_index_info*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*, %struct.sqlite3_vtab_cursor**)*, i32 (%struct.sqlite3_vtab_cursor*)*, i32 (%struct.sqlite3_vtab_cursor*, i32, i8*, i32, %struct.Mem**)*, i32 (%struct.sqlite3_vtab_cursor*)*, i32 (%struct.sqlite3_vtab_cursor*)*, i32 (%struct.sqlite3_vtab_cursor*, %struct.sqlite3_context*, i32)*, i32 (%struct.sqlite3_vtab_cursor*, i64*)*, i32 (%struct.sqlite3_vtab*, i32, %struct.Mem**, i64*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*, i32, i8*, void (%struct.sqlite3_context*, i32, %struct.Mem**)**, i8**)*, i32 (%struct.sqlite3_vtab*, i8*)* }
+ %struct.sqlite3_mutex = type opaque
+ %struct.sqlite3_vfs = type { i32, i32, i32, %struct.sqlite3_vfs*, i8*, i8*, i32 (%struct.sqlite3_vfs*, i8*, %struct.sqlite3_file*, i32, i32*)*, i32 (%struct.sqlite3_vfs*, i8*, i32)*, i32 (%struct.sqlite3_vfs*, i8*, i32)*, i32 (%struct.sqlite3_vfs*, i32, i8*)*, i32 (%struct.sqlite3_vfs*, i8*, i32, i8*)*, i8* (%struct.sqlite3_vfs*, i8*)*, void (%struct.sqlite3_vfs*, i32, i8*)*, i8* (%struct.sqlite3_vfs*, i8*, i8*)*, void (%struct.sqlite3_vfs*, i8*)*, i32 (%struct.sqlite3_vfs*, i32, i8*)*, i32 (%struct.sqlite3_vfs*, i32)*, i32 (%struct.sqlite3_vfs*, double*)* }
+ %struct.sqlite3_vtab = type { %struct.sqlite3_module*, i32, i8* }
+ %struct.sqlite3_vtab_cursor = type { %struct.sqlite3_vtab* }
+
+define fastcc void @dropCell(%struct.MemPage* nocapture %pPage, i32 %idx, i32 %sz) nounwind ssp {
+entry:
+ %0 = load i8** null, align 8 ; <i8*> [#uses=4]
+ %1 = or i32 0, 0 ; <i32> [#uses=1]
+ %2 = icmp slt i32 %sz, 4 ; <i1> [#uses=1]
+ %size_addr.0.i = select i1 %2, i32 4, i32 %sz ; <i32> [#uses=1]
+ br label %bb3.i
+
+bb3.i: ; preds = %bb3.i, %entry
+ %3 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ %or.cond.i = or i1 %3, false ; <i1> [#uses=1]
+ br i1 %or.cond.i, label %bb5.i, label %bb3.i
+
+bb5.i: ; preds = %bb3.i
+ %4 = getelementptr i8* %0, i64 0 ; <i8*> [#uses=1]
+ store i8 0, i8* %4, align 1
+ %5 = getelementptr i8* %0, i64 0 ; <i8*> [#uses=1]
+ store i8 0, i8* %5, align 1
+ %6 = add i32 %1, 2 ; <i32> [#uses=1]
+ %7 = zext i32 %6 to i64 ; <i64> [#uses=2]
+ %8 = getelementptr i8* %0, i64 %7 ; <i8*> [#uses=1]
+ %9 = lshr i32 %size_addr.0.i, 8 ; <i32> [#uses=1]
+ %10 = trunc i32 %9 to i8 ; <i8> [#uses=1]
+ store i8 %10, i8* %8, align 1
+ %.sum31.i = add i64 %7, 1 ; <i64> [#uses=1]
+ %11 = getelementptr i8* %0, i64 %.sum31.i ; <i8*> [#uses=1]
+ store i8 0, i8* %11, align 1
+ br label %bb11.outer.i
+
+bb11.outer.i: ; preds = %bb11.outer.i, %bb5.i
+ %12 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br i1 %12, label %bb12.i, label %bb11.outer.i
+
+bb12.i: ; preds = %bb11.outer.i
+ %i.08 = add i32 %idx, 1 ; <i32> [#uses=1]
+ %13 = icmp sgt i32 0, %i.08 ; <i1> [#uses=1]
+ br i1 %13, label %bb, label %bb2
+
+bb: ; preds = %bb12.i
+ br label %bb2
+
+bb2: ; preds = %bb, %bb12.i
+ %14 = getelementptr %struct.MemPage* %pPage, i64 0, i32 1 ; <i8*> [#uses=1]
+ store i8 1, i8* %14, align 1
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-04-scale.ll b/test/CodeGen/X86/2009-04-scale.ll
new file mode 100644
index 0000000..e4c756c
--- /dev/null
+++ b/test/CodeGen/X86/2009-04-scale.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-unknown-linux-gnu
+; PR3995
+
+ %struct.vtable = type { i32 (...)** }
+ %struct.array = type { %struct.impl, [256 x %struct.pair], [256 x %struct.pair], [256 x %struct.pair], [256 x %struct.pair], [256 x %struct.pair], [256 x %struct.pair] }
+ %struct.impl = type { %struct.vtable, i8, %struct.impl*, i32, i32, i64, i64 }
+ %struct.pair = type { i64, i64 }
+
+define void @test() {
+entry:
+ %0 = load i32* null, align 4 ; <i32> [#uses=1]
+ %1 = lshr i32 %0, 8 ; <i32> [#uses=1]
+ %2 = and i32 %1, 255 ; <i32> [#uses=1]
+ %3 = getelementptr %struct.array* null, i32 0, i32 3 ; <[256 x %struct.pair]*> [#uses=1]
+ %4 = getelementptr [256 x %struct.pair]* %3, i32 0, i32 %2 ; <%struct.pair*> [#uses=1]
+ %5 = getelementptr %struct.pair* %4, i32 0, i32 1 ; <i64*> [#uses=1]
+ %6 = load i64* %5, align 4 ; <i64> [#uses=1]
+ %7 = xor i64 0, %6 ; <i64> [#uses=1]
+ %8 = xor i64 %7, 0 ; <i64> [#uses=1]
+ %9 = xor i64 %8, 0 ; <i64> [#uses=1]
+ store i64 %9, i64* null, align 8
+ unreachable
+}
diff --git a/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll b/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll
new file mode 100644
index 0000000..738b5fb
--- /dev/null
+++ b/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -relocation-model=static > %t
+; RUN: grep "1: ._pv_cpu_ops+8" %t
+; RUN: grep "2: ._G" %t
+; PR4152
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.6"
+ %struct.pv_cpu_ops = type { i32, [2 x i32] }
+@pv_cpu_ops = external global %struct.pv_cpu_ops ; <%struct.pv_cpu_ops*> [#uses=1]
+@G = external global i32 ; <i32*> [#uses=1]
+
+define void @x() nounwind {
+entry:
+ tail call void asm sideeffect "1: $0", "i,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr (%struct.pv_cpu_ops* @pv_cpu_ops, i32 0, i32 1, i32 1)) nounwind
+ tail call void asm sideeffect "2: $0", "i,~{dirflag},~{fpsr},~{flags}"(i32* @G) nounwind
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-05-11-tailmerge-crash.ll b/test/CodeGen/X86/2009-05-11-tailmerge-crash.ll
new file mode 100644
index 0000000..a5e28c0
--- /dev/null
+++ b/test/CodeGen/X86/2009-05-11-tailmerge-crash.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86
+; PR4188
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.6"
+@g_9 = external global i32 ; <i32*> [#uses=1]
+
+define i32 @int86(i32 %p_87) nounwind {
+entry:
+ %0 = trunc i32 %p_87 to i8 ; <i8> [#uses=1]
+ %1 = icmp ne i8 %0, 0 ; <i1> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb.i, %bb, %entry
+ %2 = volatile load i32* @g_9, align 4 ; <i32> [#uses=2]
+ %3 = icmp sgt i32 %2, 1 ; <i1> [#uses=1]
+ %4 = and i1 %3, %1 ; <i1> [#uses=1]
+ br i1 %4, label %bb.i, label %bb
+
+bb.i: ; preds = %bb
+ %5 = icmp sgt i32 0, %2 ; <i1> [#uses=0]
+ br label %bb
+}
diff --git a/test/CodeGen/X86/2009-05-19-SingleElementExtractElement.ll b/test/CodeGen/X86/2009-05-19-SingleElementExtractElement.ll
new file mode 100644
index 0000000..6e062fb
--- /dev/null
+++ b/test/CodeGen/X86/2009-05-19-SingleElementExtractElement.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86-64
+; PR3886
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
+entry:
+ %a = call <1 x i64> @bar()
+ %tmp5.i = extractelement <1 x i64> %a, i32 0
+ %tmp11 = bitcast i64 %tmp5.i to <1 x i64>
+ %tmp8 = extractelement <1 x i64> %tmp11, i32 0
+ %call6 = call i32 (i64)* @foo(i64 %tmp8)
+ ret i32 undef
+}
+
+declare i32 @foo(i64)
+
+declare <1 x i64> @bar()
diff --git a/test/CodeGen/X86/2009-05-23-available_externally.ll b/test/CodeGen/X86/2009-05-23-available_externally.ll
new file mode 100644
index 0000000..94773d9
--- /dev/null
+++ b/test/CodeGen/X86/2009-05-23-available_externally.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -relocation-model=pic | grep atoi | grep PLT
+; PR4253
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i32 @foo(i8* %x) nounwind readonly {
+entry:
+ %call = tail call fastcc i32 @atoi(i8* %x) nounwind readonly ; <i32> [#uses=1]
+ ret i32 %call
+}
+
+define available_externally fastcc i32 @atoi(i8* %__nptr) nounwind readonly {
+entry:
+ %call = tail call i64 @strtol(i8* nocapture %__nptr, i8** null, i32 10) nounwind readonly ; <i64> [#uses=1]
+ %conv = trunc i64 %call to i32 ; <i32> [#uses=1]
+ ret i32 %conv
+}
+
+declare i64 @strtol(i8*, i8** nocapture, i32) nounwind
diff --git a/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll b/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll
new file mode 100644
index 0000000..3cd5416
--- /dev/null
+++ b/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s | FileCheck %s
+
+; Check that the shr(shl X, 56), 48) is not mistakenly turned into
+; a shr (X, -8) that gets subsequently "optimized away" as undef
+; PR4254
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i64 @foo(i64 %b) nounwind readnone {
+entry:
+; CHECK: foo:
+; CHECK: shlq $56, %rdi
+; CHECK: sarq $48, %rdi
+; CHECK: leaq 1(%rdi), %rax
+ %shl = shl i64 %b, 56 ; <i64> [#uses=1]
+ %shr = ashr i64 %shl, 48 ; <i64> [#uses=1]
+ %add5 = or i64 %shr, 1 ; <i64> [#uses=1]
+ ret i64 %add5
+}
diff --git a/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll b/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll
new file mode 100644
index 0000000..2fd42f4
--- /dev/null
+++ b/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -march=x86-64
+
+ %struct.tempsym_t = type { i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32 }
+
+define fastcc signext i8 @S_next_symbol(%struct.tempsym_t* %symptr) nounwind ssp {
+entry:
+ br label %bb116
+
+bb: ; preds = %bb116
+ switch i8 undef, label %bb14 [
+ i8 9, label %bb116
+ i8 32, label %bb116
+ i8 10, label %bb116
+ i8 13, label %bb116
+ i8 12, label %bb116
+ ]
+
+bb14: ; preds = %bb
+ br i1 undef, label %bb75, label %bb115
+
+bb75: ; preds = %bb14
+ %srcval16 = load i448* null, align 8 ; <i448> [#uses=1]
+ %tmp = zext i32 undef to i448 ; <i448> [#uses=1]
+ %tmp15 = shl i448 %tmp, 288 ; <i448> [#uses=1]
+ %mask = and i448 %srcval16, -2135987035423586845985235064014169866455883682256196619149693890381755748887481053010428711403521 ; <i448> [#uses=1]
+ %ins = or i448 %tmp15, %mask ; <i448> [#uses=1]
+ store i448 %ins, i448* null, align 8
+ ret i8 1
+
+bb115: ; preds = %bb14
+ ret i8 1
+
+bb116: ; preds = %bb, %bb, %bb, %bb, %bb, %entry
+ br i1 undef, label %bb, label %bb117
+
+bb117: ; preds = %bb116
+ ret i8 0
+}
diff --git a/test/CodeGen/X86/2009-05-30-ISelBug.ll b/test/CodeGen/X86/2009-05-30-ISelBug.ll
new file mode 100644
index 0000000..af552d4
--- /dev/null
+++ b/test/CodeGen/X86/2009-05-30-ISelBug.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=x86-64 | not grep {movzbl %\[abcd\]h,}
+
+define void @BZ2_bzDecompress_bb5_2E_outer_bb35_2E_i_bb54_2E_i(i32*, i32 %c_nblock_used.2.i, i32 %.reload51, i32* %.out, i32* %.out1, i32* %.out2, i32* %.out3) nounwind {
+newFuncRoot:
+ br label %bb54.i
+
+bb35.i.backedge.exitStub: ; preds = %bb54.i
+ store i32 %6, i32* %.out
+ store i32 %10, i32* %.out1
+ store i32 %11, i32* %.out2
+ store i32 %12, i32* %.out3
+ ret void
+
+bb54.i: ; preds = %newFuncRoot
+ %1 = zext i32 %.reload51 to i64 ; <i64> [#uses=1]
+ %2 = getelementptr i32* %0, i64 %1 ; <i32*> [#uses=1]
+ %3 = load i32* %2, align 4 ; <i32> [#uses=2]
+ %4 = lshr i32 %3, 8 ; <i32> [#uses=1]
+ %5 = and i32 %3, 255 ; <i32> [#uses=1]
+ %6 = add i32 %5, 4 ; <i32> [#uses=1]
+ %7 = zext i32 %4 to i64 ; <i64> [#uses=1]
+ %8 = getelementptr i32* %0, i64 %7 ; <i32*> [#uses=1]
+ %9 = load i32* %8, align 4 ; <i32> [#uses=2]
+ %10 = and i32 %9, 255 ; <i32> [#uses=1]
+ %11 = lshr i32 %9, 8 ; <i32> [#uses=1]
+ %12 = add i32 %c_nblock_used.2.i, 5 ; <i32> [#uses=1]
+ br label %bb35.i.backedge.exitStub
+}
diff --git a/test/CodeGen/X86/2009-06-02-RewriterBug.ll b/test/CodeGen/X86/2009-06-02-RewriterBug.ll
new file mode 100644
index 0000000..779f985
--- /dev/null
+++ b/test/CodeGen/X86/2009-06-02-RewriterBug.ll
@@ -0,0 +1,362 @@
+; RUN: llc < %s -mtriple=x86_64-undermydesk-freebsd8.0 -relocation-model=pic -disable-fp-elim
+; PR4225
+
+define void @sha256_block1(i32* nocapture %arr, i8* nocapture %in, i64 %num) nounwind {
+entry:
+ br i1 undef, label %while.end, label %bb.nph
+
+bb.nph: ; preds = %entry
+ br label %while.body
+
+while.body: ; preds = %for.end, %bb.nph
+ %indvar2787 = phi i64 [ 0, %bb.nph ], [ %indvar.next2788, %for.end ] ; <i64> [#uses=2]
+ %tmp2791 = mul i64 %indvar2787, 44 ; <i64> [#uses=0]
+ %ctg22996 = getelementptr i8* %in, i64 0 ; <i8*> [#uses=1]
+ %conv = zext i32 undef to i64 ; <i64> [#uses=1]
+ %conv11 = zext i32 undef to i64 ; <i64> [#uses=1]
+ %tmp18 = load i32* undef ; <i32> [#uses=1]
+ %conv19 = zext i32 %tmp18 to i64 ; <i64> [#uses=1]
+ %tmp30 = load i32* undef ; <i32> [#uses=1]
+ %conv31 = zext i32 %tmp30 to i64 ; <i64> [#uses=4]
+ %ptrincdec3065 = load i8* null ; <i8> [#uses=1]
+ %conv442709 = zext i8 %ptrincdec3065 to i64 ; <i64> [#uses=1]
+ %shl45 = shl i64 %conv442709, 16 ; <i64> [#uses=1]
+ %conv632707 = zext i8 undef to i64 ; <i64> [#uses=1]
+ %or = or i64 %shl45, 0 ; <i64> [#uses=1]
+ %or55 = or i64 %or, %conv632707 ; <i64> [#uses=1]
+ %or64 = or i64 %or55, 0 ; <i64> [#uses=1]
+ %shr85 = lshr i64 %conv31, 25 ; <i64> [#uses=0]
+ %add = add i64 %conv11, 1508970993 ; <i64> [#uses=1]
+ %add95 = add i64 %add, 0 ; <i64> [#uses=1]
+ %add98 = add i64 %add95, 0 ; <i64> [#uses=1]
+ %add99 = add i64 %add98, %or64 ; <i64> [#uses=1]
+ %add134 = add i64 %add99, 0 ; <i64> [#uses=4]
+ store i32 undef, i32* undef
+ %shl187 = shl i64 %add134, 21 ; <i64> [#uses=0]
+ %and203 = and i64 %add134, %conv31 ; <i64> [#uses=1]
+ %xor208 = xor i64 0, %and203 ; <i64> [#uses=1]
+ %add212 = add i64 0, %xor208 ; <i64> [#uses=1]
+ %add213 = add i64 %add212, 0 ; <i64> [#uses=1]
+ %add248 = add i64 %add213, 0 ; <i64> [#uses=3]
+ %conv2852690 = zext i8 undef to i64 ; <i64> [#uses=1]
+ %or277 = or i64 0, %conv2852690 ; <i64> [#uses=1]
+ %or286 = or i64 %or277, 0 ; <i64> [#uses=1]
+ %neg319 = xor i64 %add248, 4294967295 ; <i64> [#uses=1]
+ %and321 = and i64 %neg319, %conv31 ; <i64> [#uses=1]
+ %xor322 = xor i64 %and321, 0 ; <i64> [#uses=1]
+ %add314 = add i64 %conv, 2870763221 ; <i64> [#uses=1]
+ %add323 = add i64 %add314, %or286 ; <i64> [#uses=1]
+ %add326 = add i64 %add323, %xor322 ; <i64> [#uses=1]
+ %add327 = add i64 %add326, 0 ; <i64> [#uses=2]
+ %add362 = add i64 %add327, %conv19 ; <i64> [#uses=4]
+ %add365 = add i64 0, %add327 ; <i64> [#uses=3]
+ %shl409 = shl i64 %add362, 26 ; <i64> [#uses=0]
+ %and431 = and i64 %add362, %add248 ; <i64> [#uses=1]
+ %neg433 = xor i64 %add362, -1 ; <i64> [#uses=1]
+ %and435 = and i64 %add134, %neg433 ; <i64> [#uses=1]
+ %xor436 = xor i64 %and431, %and435 ; <i64> [#uses=1]
+ %add428 = add i64 %conv31, 3624381080 ; <i64> [#uses=1]
+ %add437 = add i64 %add428, 0 ; <i64> [#uses=1]
+ %add440 = add i64 %add437, %xor436 ; <i64> [#uses=1]
+ %add441 = add i64 %add440, 0 ; <i64> [#uses=1]
+ %shl443 = shl i64 %add365, 30 ; <i64> [#uses=1]
+ %and445 = lshr i64 %add365, 2 ; <i64> [#uses=1]
+ %shr446 = and i64 %and445, 1073741823 ; <i64> [#uses=1]
+ %or447 = or i64 %shr446, %shl443 ; <i64> [#uses=1]
+ %xor461 = xor i64 0, %or447 ; <i64> [#uses=1]
+ %add473 = add i64 %xor461, 0 ; <i64> [#uses=1]
+ %add479 = add i64 %add473, %add441 ; <i64> [#uses=3]
+ %conv4932682 = zext i8 undef to i64 ; <i64> [#uses=1]
+ %shl494 = shl i64 %conv4932682, 16 ; <i64> [#uses=1]
+ %ptrincdec4903012 = load i8* null ; <i8> [#uses=1]
+ %conv5032681 = zext i8 %ptrincdec4903012 to i64 ; <i64> [#uses=1]
+ %shl504 = shl i64 %conv5032681, 8 ; <i64> [#uses=1]
+ %ptrincdec5003009 = load i8* null ; <i8> [#uses=1]
+ %conv5132680 = zext i8 %ptrincdec5003009 to i64 ; <i64> [#uses=1]
+ %or495 = or i64 %shl494, 0 ; <i64> [#uses=1]
+ %or505 = or i64 %or495, %conv5132680 ; <i64> [#uses=1]
+ %or514 = or i64 %or505, %shl504 ; <i64> [#uses=1]
+ store i32 undef, i32* undef
+ %or540 = or i64 undef, 0 ; <i64> [#uses=0]
+ %add542 = add i64 %add134, 310598401 ; <i64> [#uses=1]
+ %add551 = add i64 %add542, %or514 ; <i64> [#uses=1]
+ %add554 = add i64 %add551, 0 ; <i64> [#uses=1]
+ %add555 = add i64 %add554, 0 ; <i64> [#uses=1]
+ %or561 = or i64 undef, undef ; <i64> [#uses=1]
+ %or567 = or i64 undef, undef ; <i64> [#uses=1]
+ %and572 = lshr i64 %add479, 22 ; <i64> [#uses=1]
+ %shr573 = and i64 %and572, 1023 ; <i64> [#uses=1]
+ %or574 = or i64 %shr573, 0 ; <i64> [#uses=1]
+ %xor568 = xor i64 %or567, %or574 ; <i64> [#uses=1]
+ %xor575 = xor i64 %xor568, %or561 ; <i64> [#uses=1]
+ %add587 = add i64 %xor575, 0 ; <i64> [#uses=1]
+ %add593 = add i64 %add587, %add555 ; <i64> [#uses=1]
+ %ptrincdec6043000 = load i8* null ; <i8> [#uses=1]
+ %conv6172676 = zext i8 %ptrincdec6043000 to i64 ; <i64> [#uses=1]
+ %shl618 = shl i64 %conv6172676, 8 ; <i64> [#uses=1]
+ %ptrincdec6142997 = load i8* %ctg22996 ; <i8> [#uses=1]
+ %conv6272675 = zext i8 %ptrincdec6142997 to i64 ; <i64> [#uses=1]
+ %or619 = or i64 0, %conv6272675 ; <i64> [#uses=1]
+ %or628 = or i64 %or619, %shl618 ; <i64> [#uses=1]
+ %add656 = add i64 %add248, 607225278 ; <i64> [#uses=1]
+ %add665 = add i64 %add656, %or628 ; <i64> [#uses=1]
+ %add668 = add i64 %add665, 0 ; <i64> [#uses=1]
+ %add669 = add i64 %add668, 0 ; <i64> [#uses=1]
+ %and699 = and i64 %add479, %add365 ; <i64> [#uses=1]
+ %xor700 = xor i64 0, %and699 ; <i64> [#uses=1]
+ %add701 = add i64 0, %xor700 ; <i64> [#uses=1]
+ %add707 = add i64 %add701, %add669 ; <i64> [#uses=4]
+ %ptrincdec6242994 = load i8* null ; <i8> [#uses=1]
+ %conv7122673 = zext i8 %ptrincdec6242994 to i64 ; <i64> [#uses=1]
+ %shl713 = shl i64 %conv7122673, 24 ; <i64> [#uses=1]
+ %conv7412670 = zext i8 undef to i64 ; <i64> [#uses=1]
+ %or723 = or i64 0, %shl713 ; <i64> [#uses=1]
+ %or733 = or i64 %or723, %conv7412670 ; <i64> [#uses=1]
+ %or742 = or i64 %or733, 0 ; <i64> [#uses=2]
+ %conv743 = trunc i64 %or742 to i32 ; <i32> [#uses=1]
+ store i32 %conv743, i32* undef
+ %xor762 = xor i64 undef, 0 ; <i64> [#uses=0]
+ %add770 = add i64 %add362, 1426881987 ; <i64> [#uses=1]
+ %add779 = add i64 %add770, %or742 ; <i64> [#uses=1]
+ %add782 = add i64 %add779, 0 ; <i64> [#uses=1]
+ %add783 = add i64 %add782, 0 ; <i64> [#uses=1]
+ %shl785 = shl i64 %add707, 30 ; <i64> [#uses=1]
+ %and787 = lshr i64 %add707, 2 ; <i64> [#uses=1]
+ %shr788 = and i64 %and787, 1073741823 ; <i64> [#uses=1]
+ %or789 = or i64 %shr788, %shl785 ; <i64> [#uses=1]
+ %shl791 = shl i64 %add707, 19 ; <i64> [#uses=0]
+ %xor803 = xor i64 0, %or789 ; <i64> [#uses=1]
+ %and813 = and i64 %add593, %add479 ; <i64> [#uses=1]
+ %xor814 = xor i64 0, %and813 ; <i64> [#uses=1]
+ %add815 = add i64 %xor803, %xor814 ; <i64> [#uses=1]
+ %add821 = add i64 %add815, %add783 ; <i64> [#uses=1]
+ %add1160 = add i64 0, %add707 ; <i64> [#uses=0]
+ %add1157 = add i64 undef, undef ; <i64> [#uses=0]
+ %ptrincdec11742940 = load i8* null ; <i8> [#uses=1]
+ %conv11872651 = zext i8 %ptrincdec11742940 to i64 ; <i64> [#uses=1]
+ %shl1188 = shl i64 %conv11872651, 8 ; <i64> [#uses=1]
+ %or1198 = or i64 0, %shl1188 ; <i64> [#uses=1]
+ store i32 undef, i32* undef
+ %add1226 = add i64 %or1198, 3248222580 ; <i64> [#uses=1]
+ %add1235 = add i64 %add1226, 0 ; <i64> [#uses=1]
+ %add1238 = add i64 %add1235, 0 ; <i64> [#uses=1]
+ %add1239 = add i64 %add1238, 0 ; <i64> [#uses=1]
+ br label %for.cond
+
+for.cond: ; preds = %for.body, %while.body
+ %add821.pn = phi i64 [ %add821, %while.body ], [ undef, %for.body ] ; <i64> [#uses=0]
+ %add1239.pn = phi i64 [ %add1239, %while.body ], [ 0, %for.body ] ; <i64> [#uses=0]
+ br i1 undef, label %for.end, label %for.body
+
+for.body: ; preds = %for.cond
+ br label %for.cond
+
+for.end: ; preds = %for.cond
+ %indvar.next2788 = add i64 %indvar2787, 1 ; <i64> [#uses=1]
+ br i1 undef, label %while.end, label %while.body
+
+while.end: ; preds = %for.end, %entry
+ ret void
+}
+
+define void @sha256_block2(i32* nocapture %arr, i8* nocapture %in, i64 %num) nounwind {
+entry:
+ br i1 undef, label %while.end, label %bb.nph
+
+bb.nph: ; preds = %entry
+ %arrayidx5 = getelementptr i32* %arr, i64 1 ; <i32*> [#uses=1]
+ %arrayidx9 = getelementptr i32* %arr, i64 2 ; <i32*> [#uses=2]
+ %arrayidx13 = getelementptr i32* %arr, i64 3 ; <i32*> [#uses=2]
+ %arrayidx25 = getelementptr i32* %arr, i64 6 ; <i32*> [#uses=1]
+ %arrayidx29 = getelementptr i32* %arr, i64 7 ; <i32*> [#uses=1]
+ br label %while.body
+
+while.body: ; preds = %for.end, %bb.nph
+ %tmp3 = load i32* %arr ; <i32> [#uses=2]
+ %conv = zext i32 %tmp3 to i64 ; <i64> [#uses=1]
+ %tmp10 = load i32* %arrayidx9 ; <i32> [#uses=1]
+ %conv11 = zext i32 %tmp10 to i64 ; <i64> [#uses=1]
+ %tmp14 = load i32* %arrayidx13 ; <i32> [#uses=3]
+ %conv15 = zext i32 %tmp14 to i64 ; <i64> [#uses=2]
+ %tmp18 = load i32* undef ; <i32> [#uses=2]
+ %conv19 = zext i32 %tmp18 to i64 ; <i64> [#uses=1]
+ %conv23 = zext i32 undef to i64 ; <i64> [#uses=1]
+ %tmp26 = load i32* %arrayidx25 ; <i32> [#uses=1]
+ %conv27 = zext i32 %tmp26 to i64 ; <i64> [#uses=1]
+ %tmp30 = load i32* %arrayidx29 ; <i32> [#uses=2]
+ %conv31 = zext i32 %tmp30 to i64 ; <i64> [#uses=5]
+ %shl72 = shl i64 %conv31, 26 ; <i64> [#uses=1]
+ %shr = lshr i64 %conv31, 6 ; <i64> [#uses=1]
+ %or74 = or i64 %shl72, %shr ; <i64> [#uses=1]
+ %shr85 = lshr i64 %conv31, 25 ; <i64> [#uses=0]
+ %xor87 = xor i64 0, %or74 ; <i64> [#uses=1]
+ %and902706 = and i32 %tmp30, %tmp3 ; <i32> [#uses=1]
+ %and90 = zext i32 %and902706 to i64 ; <i64> [#uses=1]
+ %xor94 = xor i64 0, %and90 ; <i64> [#uses=1]
+ %add = add i64 %conv11, 1508970993 ; <i64> [#uses=1]
+ %add95 = add i64 %add, %xor94 ; <i64> [#uses=1]
+ %add98 = add i64 %add95, %xor87 ; <i64> [#uses=1]
+ %add99 = add i64 %add98, 0 ; <i64> [#uses=2]
+ %xor130 = zext i32 undef to i64 ; <i64> [#uses=1]
+ %add134 = add i64 %add99, %conv27 ; <i64> [#uses=2]
+ %add131 = add i64 %xor130, 0 ; <i64> [#uses=1]
+ %add137 = add i64 %add131, %add99 ; <i64> [#uses=5]
+ %conv1422700 = zext i8 undef to i64 ; <i64> [#uses=1]
+ %shl143 = shl i64 %conv1422700, 24 ; <i64> [#uses=1]
+ %ptrincdec1393051 = load i8* undef ; <i8> [#uses=1]
+ %conv1512699 = zext i8 %ptrincdec1393051 to i64 ; <i64> [#uses=1]
+ %shl152 = shl i64 %conv1512699, 16 ; <i64> [#uses=1]
+ %conv1712697 = zext i8 undef to i64 ; <i64> [#uses=1]
+ %or153 = or i64 %shl152, %shl143 ; <i64> [#uses=1]
+ %or163 = or i64 %or153, %conv1712697 ; <i64> [#uses=1]
+ %or172 = or i64 %or163, 0 ; <i64> [#uses=1]
+ %and203 = and i64 %add134, %conv31 ; <i64> [#uses=1]
+ %xor208 = xor i64 0, %and203 ; <i64> [#uses=1]
+ %add200 = add i64 0, 2453635748 ; <i64> [#uses=1]
+ %add209 = add i64 %add200, %or172 ; <i64> [#uses=1]
+ %add212 = add i64 %add209, %xor208 ; <i64> [#uses=1]
+ %add213 = add i64 %add212, 0 ; <i64> [#uses=2]
+ %shl228 = shl i64 %add137, 10 ; <i64> [#uses=1]
+ %and230 = lshr i64 %add137, 22 ; <i64> [#uses=1]
+ %shr231 = and i64 %and230, 1023 ; <i64> [#uses=1]
+ %or232 = or i64 %shr231, %shl228 ; <i64> [#uses=1]
+ %xor226 = xor i64 0, %or232 ; <i64> [#uses=1]
+ %xor233 = xor i64 %xor226, 0 ; <i64> [#uses=1]
+ %and2362695 = zext i32 undef to i64 ; <i64> [#uses=1]
+ %xor240 = and i64 %add137, %and2362695 ; <i64> [#uses=1]
+ %and2432694 = and i32 %tmp18, %tmp14 ; <i32> [#uses=1]
+ %and243 = zext i32 %and2432694 to i64 ; <i64> [#uses=1]
+ %xor244 = xor i64 %xor240, %and243 ; <i64> [#uses=1]
+ %add248 = add i64 %add213, %conv23 ; <i64> [#uses=2]
+ %add245 = add i64 %xor233, %xor244 ; <i64> [#uses=1]
+ %add251 = add i64 %add245, %add213 ; <i64> [#uses=1]
+ %conv2752691 = zext i8 undef to i64 ; <i64> [#uses=1]
+ %shl276 = shl i64 %conv2752691, 8 ; <i64> [#uses=0]
+ %and317 = and i64 %add248, %add134 ; <i64> [#uses=1]
+ %neg319 = xor i64 %add248, 4294967295 ; <i64> [#uses=1]
+ %and321 = and i64 %neg319, %conv31 ; <i64> [#uses=1]
+ %xor322 = xor i64 %and321, %and317 ; <i64> [#uses=1]
+ %add314 = add i64 %conv, 2870763221 ; <i64> [#uses=1]
+ %add323 = add i64 %add314, 0 ; <i64> [#uses=1]
+ %add326 = add i64 %add323, %xor322 ; <i64> [#uses=1]
+ %add327 = add i64 %add326, 0 ; <i64> [#uses=2]
+ %and3502689 = xor i64 %add137, %conv15 ; <i64> [#uses=1]
+ %xor354 = and i64 %add251, %and3502689 ; <i64> [#uses=1]
+ %and357 = and i64 %add137, %conv15 ; <i64> [#uses=1]
+ %xor358 = xor i64 %xor354, %and357 ; <i64> [#uses=1]
+ %add362 = add i64 %add327, %conv19 ; <i64> [#uses=1]
+ %add359 = add i64 0, %xor358 ; <i64> [#uses=1]
+ %add365 = add i64 %add359, %add327 ; <i64> [#uses=1]
+ %add770 = add i64 %add362, 1426881987 ; <i64> [#uses=1]
+ %add779 = add i64 %add770, 0 ; <i64> [#uses=1]
+ %add782 = add i64 %add779, 0 ; <i64> [#uses=1]
+ %add783 = add i64 %add782, 0 ; <i64> [#uses=2]
+ %add818 = add i64 %add783, %add365 ; <i64> [#uses=1]
+ %add821 = add i64 0, %add783 ; <i64> [#uses=1]
+ store i32 undef, i32* undef
+ %add1046 = add i64 undef, undef ; <i64> [#uses=1]
+ %add1160 = add i64 undef, undef ; <i64> [#uses=1]
+ store i32 0, i32* undef
+ %add1235 = add i64 0, %add818 ; <i64> [#uses=1]
+ %add1238 = add i64 %add1235, 0 ; <i64> [#uses=1]
+ %add1239 = add i64 %add1238, 0 ; <i64> [#uses=1]
+ br label %for.cond
+
+for.cond: ; preds = %for.body, %while.body
+ %h.0 = phi i64 [ undef, %while.body ], [ %add2035, %for.body ] ; <i64> [#uses=1]
+ %g.0 = phi i64 [ %add1046, %while.body ], [ undef, %for.body ] ; <i64> [#uses=1]
+ %f.0 = phi i64 [ %add1160, %while.body ], [ undef, %for.body ] ; <i64> [#uses=1]
+ %add821.pn = phi i64 [ %add821, %while.body ], [ undef, %for.body ] ; <i64> [#uses=0]
+ %add1239.pn2648 = phi i64 [ %add1239, %while.body ], [ undef, %for.body ] ; <i64> [#uses=0]
+ %d.0 = phi i64 [ undef, %while.body ], [ %add2038, %for.body ] ; <i64> [#uses=2]
+ br i1 undef, label %for.end, label %for.body
+
+for.body: ; preds = %for.cond
+ %conv1390 = zext i32 undef to i64 ; <i64> [#uses=1]
+ %add1375 = add i64 0, %h.0 ; <i64> [#uses=1]
+ %add1384 = add i64 %add1375, 0 ; <i64> [#uses=1]
+ %add1391 = add i64 %add1384, %conv1390 ; <i64> [#uses=1]
+ %add1392 = add i64 %add1391, 0 ; <i64> [#uses=2]
+ %or1411 = or i64 0, undef ; <i64> [#uses=1]
+ %xor1405 = xor i64 0, %or1411 ; <i64> [#uses=1]
+ %xor1412 = xor i64 %xor1405, 0 ; <i64> [#uses=1]
+ %add1427 = add i64 %add1392, %d.0 ; <i64> [#uses=1]
+ %add1424 = add i64 %xor1412, 0 ; <i64> [#uses=1]
+ %add1430 = add i64 %add1424, %add1392 ; <i64> [#uses=5]
+ %tmp1438 = load i32* undef ; <i32> [#uses=1]
+ %conv1439 = zext i32 %tmp1438 to i64 ; <i64> [#uses=4]
+ %shl1441 = shl i64 %conv1439, 25 ; <i64> [#uses=1]
+ %shr1444 = lshr i64 %conv1439, 7 ; <i64> [#uses=1]
+ %or1445 = or i64 %shl1441, %shr1444 ; <i64> [#uses=1]
+ %shr1450 = lshr i64 %conv1439, 18 ; <i64> [#uses=1]
+ %or1451 = or i64 0, %shr1450 ; <i64> [#uses=1]
+ %shr1454 = lshr i64 %conv1439, 3 ; <i64> [#uses=1]
+ %xor1452 = xor i64 %or1451, %shr1454 ; <i64> [#uses=1]
+ %xor1455 = xor i64 %xor1452, %or1445 ; <i64> [#uses=1]
+ %conv1464 = zext i32 undef to i64 ; <i64> [#uses=4]
+ %shl1466 = shl i64 %conv1464, 15 ; <i64> [#uses=1]
+ %shr1469 = lshr i64 %conv1464, 17 ; <i64> [#uses=1]
+ %or1470 = or i64 %shl1466, %shr1469 ; <i64> [#uses=1]
+ %shr1475 = lshr i64 %conv1464, 19 ; <i64> [#uses=1]
+ %or1476 = or i64 0, %shr1475 ; <i64> [#uses=1]
+ %shr1479 = lshr i64 %conv1464, 10 ; <i64> [#uses=1]
+ %xor1477 = xor i64 %or1476, %shr1479 ; <i64> [#uses=1]
+ %xor1480 = xor i64 %xor1477, %or1470 ; <i64> [#uses=1]
+ %tmp1499 = load i32* null ; <i32> [#uses=1]
+ %conv1500 = zext i32 %tmp1499 to i64 ; <i64> [#uses=1]
+ %add1491 = add i64 %conv1500, 0 ; <i64> [#uses=1]
+ %add1501 = add i64 %add1491, %xor1455 ; <i64> [#uses=1]
+ %add1502 = add i64 %add1501, %xor1480 ; <i64> [#uses=1]
+ %conv1504 = and i64 %add1502, 4294967295 ; <i64> [#uses=1]
+ %tmp1541 = load i32* undef ; <i32> [#uses=1]
+ %conv1542 = zext i32 %tmp1541 to i64 ; <i64> [#uses=1]
+ %add1527 = add i64 %conv1542, %g.0 ; <i64> [#uses=1]
+ %add1536 = add i64 %add1527, 0 ; <i64> [#uses=1]
+ %add1543 = add i64 %add1536, %conv1504 ; <i64> [#uses=1]
+ %add1544 = add i64 %add1543, 0 ; <i64> [#uses=1]
+ %shl1546 = shl i64 %add1430, 30 ; <i64> [#uses=1]
+ %and1548 = lshr i64 %add1430, 2 ; <i64> [#uses=1]
+ %shr1549 = and i64 %and1548, 1073741823 ; <i64> [#uses=1]
+ %or1550 = or i64 %shr1549, %shl1546 ; <i64> [#uses=1]
+ %shl1552 = shl i64 %add1430, 19 ; <i64> [#uses=1]
+ %or1556 = or i64 0, %shl1552 ; <i64> [#uses=1]
+ %shl1559 = shl i64 %add1430, 10 ; <i64> [#uses=1]
+ %or1563 = or i64 0, %shl1559 ; <i64> [#uses=1]
+ %xor1557 = xor i64 %or1556, %or1563 ; <i64> [#uses=1]
+ %xor1564 = xor i64 %xor1557, %or1550 ; <i64> [#uses=1]
+ %add1576 = add i64 %xor1564, 0 ; <i64> [#uses=1]
+ %add1582 = add i64 %add1576, %add1544 ; <i64> [#uses=3]
+ store i32 undef, i32* undef
+ %tmp1693 = load i32* undef ; <i32> [#uses=1]
+ %conv1694 = zext i32 %tmp1693 to i64 ; <i64> [#uses=1]
+ %add1679 = add i64 %conv1694, %f.0 ; <i64> [#uses=1]
+ %add1688 = add i64 %add1679, 0 ; <i64> [#uses=1]
+ %add1695 = add i64 %add1688, 0 ; <i64> [#uses=1]
+ %add1696 = add i64 %add1695, 0 ; <i64> [#uses=1]
+ %shl1698 = shl i64 %add1582, 30 ; <i64> [#uses=0]
+ %shl1704 = shl i64 %add1582, 19 ; <i64> [#uses=0]
+ %add1734 = add i64 0, %add1696 ; <i64> [#uses=1]
+ %add1983 = add i64 0, %add1427 ; <i64> [#uses=1]
+ %add1992 = add i64 %add1983, 0 ; <i64> [#uses=1]
+ %add1999 = add i64 %add1992, 0 ; <i64> [#uses=1]
+ %add2000 = add i64 %add1999, 0 ; <i64> [#uses=2]
+ %and2030 = and i64 %add1734, %add1582 ; <i64> [#uses=1]
+ %xor2031 = xor i64 0, %and2030 ; <i64> [#uses=1]
+ %add2035 = add i64 %add2000, %add1430 ; <i64> [#uses=1]
+ %add2032 = add i64 0, %xor2031 ; <i64> [#uses=1]
+ %add2038 = add i64 %add2032, %add2000 ; <i64> [#uses=1]
+ store i32 0, i32* undef
+ br label %for.cond
+
+for.end: ; preds = %for.cond
+ store i32 undef, i32* %arrayidx5
+ store i32 undef, i32* %arrayidx9
+ %d.02641 = trunc i64 %d.0 to i32 ; <i32> [#uses=1]
+ %conv2524 = add i32 %tmp14, %d.02641 ; <i32> [#uses=1]
+ store i32 %conv2524, i32* %arrayidx13
+ %exitcond2789 = icmp eq i64 undef, %num ; <i1> [#uses=1]
+ br i1 %exitcond2789, label %while.end, label %while.body
+
+while.end: ; preds = %for.end, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
new file mode 100644
index 0000000..e6f3008
--- /dev/null
+++ b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s | grep "subq.*\\\$40, \\\%rsp"
+target triple = "x86_64-mingw64"
+
+define x86_fp80 @a(i64 %x) nounwind readnone {
+entry:
+ %conv = sitofp i64 %x to x86_fp80 ; <x86_fp80> [#uses=1]
+ ret x86_fp80 %conv
+}
+
diff --git a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
new file mode 100644
index 0000000..cb64bf2
--- /dev/null
+++ b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -o %t1
+; RUN: grep "subq.*\\\$72, \\\%rsp" %t1
+; RUN: grep "movaps \\\%xmm8, 32\\\(\\\%rsp\\\)" %t1
+; RUN: grep "movaps \\\%xmm7, 48\\\(\\\%rsp\\\)" %t1
+target triple = "x86_64-mingw64"
+
+define i32 @a() nounwind {
+entry:
+ tail call void asm sideeffect "", "~{xmm7},~{xmm8},~{dirflag},~{fpsr},~{flags}"() nounwind
+ ret i32 undef
+}
+
diff --git a/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll b/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll
new file mode 100644
index 0000000..9415732
--- /dev/null
+++ b/test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -march=x86
+
+ type { %struct.GAP } ; type %0
+ type { i16, i8, i8 } ; type %1
+ type { [2 x i32], [2 x i32] } ; type %2
+ type { %struct.rec* } ; type %3
+ %struct.FILE_POS = type { i8, i8, i16, i32 }
+ %struct.FIRST_UNION = type { %struct.FILE_POS }
+ %struct.FOURTH_UNION = type { %struct.STYLE }
+ %struct.GAP = type { i8, i8, i16 }
+ %struct.LIST = type { %struct.rec*, %struct.rec* }
+ %struct.SECOND_UNION = type { %1 }
+ %struct.STYLE = type { %0, %0, i16, i16, i32 }
+ %struct.THIRD_UNION = type { %2 }
+ %struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, %struct.rec*, %3, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i32 }
+ %struct.rec = type { %struct.head_type }
+
+define fastcc void @MinSize(%struct.rec* %x) nounwind {
+entry:
+ %tmp13 = load i8* undef, align 4 ; <i8> [#uses=3]
+ %tmp14 = zext i8 %tmp13 to i32 ; <i32> [#uses=2]
+ switch i32 %tmp14, label %bb1109 [
+ i32 42, label %bb246
+ ]
+
+bb246: ; preds = %entry, %entry
+ switch i8 %tmp13, label %bb249 [
+ i8 42, label %bb269
+ i8 44, label %bb269
+ ]
+
+bb249: ; preds = %bb246
+ %tmp3240 = icmp eq i8 %tmp13, 0 ; <i1> [#uses=1]
+ br i1 %tmp3240, label %bb974, label %bb269
+
+bb269:
+ %tmp3424 = getelementptr %struct.rec* %x, i32 0, i32 0, i32 0, i32 0, i32 1 ; <%struct.rec**> [#uses=0]
+ unreachable
+
+bb974:
+ unreachable
+
+bb1109: ; preds = %entry
+ call fastcc void @Image(i32 %tmp14) nounwind ; <i8*> [#uses=0]
+ unreachable
+}
+
+declare fastcc void @Image(i32) nounwind
diff --git a/test/CodeGen/X86/2009-06-05-ScalarToVectorByteMMX.ll b/test/CodeGen/X86/2009-06-05-ScalarToVectorByteMMX.ll
new file mode 100644
index 0000000..336f17e
--- /dev/null
+++ b/test/CodeGen/X86/2009-06-05-ScalarToVectorByteMMX.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx | not grep movl
+
+define <8 x i8> @a(i8 zeroext %x) nounwind {
+ %r = insertelement <8 x i8> undef, i8 %x, i32 0
+ ret <8 x i8> %r
+}
+
diff --git a/test/CodeGen/X86/2009-06-05-VZextByteShort.ll b/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
new file mode 100644
index 0000000..5c51480
--- /dev/null
+++ b/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 > %t1
+; RUN: grep movzwl %t1 | count 2
+; RUN: grep movzbl %t1 | count 2
+; RUN: grep movd %t1 | count 4
+
+define <4 x i16> @a(i32* %x1) nounwind {
+ %x2 = load i32* %x1
+ %x3 = lshr i32 %x2, 1
+ %x = trunc i32 %x3 to i16
+ %r = insertelement <4 x i16> zeroinitializer, i16 %x, i32 0
+ ret <4 x i16> %r
+}
+
+define <8 x i16> @b(i32* %x1) nounwind {
+ %x2 = load i32* %x1
+ %x3 = lshr i32 %x2, 1
+ %x = trunc i32 %x3 to i16
+ %r = insertelement <8 x i16> zeroinitializer, i16 %x, i32 0
+ ret <8 x i16> %r
+}
+
+define <8 x i8> @c(i32* %x1) nounwind {
+ %x2 = load i32* %x1
+ %x3 = lshr i32 %x2, 1
+ %x = trunc i32 %x3 to i8
+ %r = insertelement <8 x i8> zeroinitializer, i8 %x, i32 0
+ ret <8 x i8> %r
+}
+
+define <16 x i8> @d(i32* %x1) nounwind {
+ %x2 = load i32* %x1
+ %x3 = lshr i32 %x2, 1
+ %x = trunc i32 %x3 to i8
+ %r = insertelement <16 x i8> zeroinitializer, i8 %x, i32 0
+ ret <16 x i8> %r
+}
+
diff --git a/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll b/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll
new file mode 100644
index 0000000..8bb3dc6
--- /dev/null
+++ b/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+
+define <2 x i64> @_mm_insert_epi16(<2 x i64> %a, i32 %b, i32 %imm) nounwind readnone {
+entry:
+ %conv = bitcast <2 x i64> %a to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %conv2 = trunc i32 %b to i16 ; <i16> [#uses=1]
+ %and = and i32 %imm, 7 ; <i32> [#uses=1]
+ %vecins = insertelement <8 x i16> %conv, i16 %conv2, i32 %and ; <<8 x i16>> [#uses=1]
+ %conv6 = bitcast <8 x i16> %vecins to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %conv6
+}
diff --git a/test/CodeGen/X86/2009-06-05-sitofpCrash.ll b/test/CodeGen/X86/2009-06-05-sitofpCrash.ll
new file mode 100644
index 0000000..e361804
--- /dev/null
+++ b/test/CodeGen/X86/2009-06-05-sitofpCrash.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mattr=+sse
+; PR2598
+
+define <2 x float> @a(<2 x i32> %i) nounwind {
+ %r = sitofp <2 x i32> %i to <2 x float>
+ ret <2 x float> %r
+}
+
+define <2 x i32> @b(<2 x float> %i) nounwind {
+ %r = fptosi <2 x float> %i to <2 x i32>
+ ret <2 x i32> %r
+}
+
diff --git a/test/CodeGen/X86/2009-06-06-ConcatVectors.ll b/test/CodeGen/X86/2009-06-06-ConcatVectors.ll
new file mode 100644
index 0000000..92419fc
--- /dev/null
+++ b/test/CodeGen/X86/2009-06-06-ConcatVectors.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s
+
+define <2 x i64> @_mm_movpi64_pi64(<1 x i64> %a, <1 x i64> %b) nounwind readnone {
+entry:
+ %0 = shufflevector <1 x i64> %a, <1 x i64> %b, <2 x i32> <i32 0, i32 1>
+ ret <2 x i64> %0
+}
+
diff --git a/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll b/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll
new file mode 100644
index 0000000..07ef53e
--- /dev/null
+++ b/test/CodeGen/X86/2009-06-07-ExpandMMXBitcast.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx | grep movl | count 2
+
+define i64 @a(i32 %a, i32 %b) nounwind readnone {
+entry:
+ %0 = insertelement <2 x i32> undef, i32 %a, i32 0 ; <<2 x i32>> [#uses=1]
+ %1 = insertelement <2 x i32> %0, i32 %b, i32 1 ; <<2 x i32>> [#uses=1]
+ %conv = bitcast <2 x i32> %1 to i64 ; <i64> [#uses=1]
+ ret i64 %conv
+}
+
diff --git a/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll b/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
new file mode 100644
index 0000000..673e936
--- /dev/null
+++ b/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -tailcallopt -march=x86-64 -mattr=+sse2 -mtriple=x86_64-apple-darwin | grep fstpt
+; RUN: llc < %s -tailcallopt -march=x86-64 -mattr=+sse2 -mtriple=x86_64-apple-darwin | grep xmm
+
+; Check that x86-64 tail calls support x86_fp80 and v2f32 types. (Tail call
+; calling convention out of sync with standard c calling convention on x86_64)
+; Bug 4278.
+
+declare fastcc double @tailcallee(x86_fp80, <2 x float>)
+
+define fastcc double @tailcall() {
+entry:
+ %tmp = fpext float 1.000000e+00 to x86_fp80
+ %tmp2 = tail call fastcc double @tailcallee( x86_fp80 %tmp, <2 x float> <float 1.000000e+00, float 1.000000e+00>)
+ ret double %tmp2
+}
diff --git a/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll b/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll
new file mode 100644
index 0000000..feb5780
--- /dev/null
+++ b/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 -tailcallopt | not grep TAILCALL
+
+; Bug 4396. This tail call can NOT be optimized.
+
+declare fastcc i8* @_D3gcx2GC12mallocNoSyncMFmkZPv() nounwind
+
+define fastcc i8* @_D3gcx2GC12callocNoSyncMFmkZPv() nounwind {
+entry:
+ %tmp6 = tail call fastcc i8* @_D3gcx2GC12mallocNoSyncMFmkZPv() ; <i8*> [#uses=2]
+ %tmp9 = tail call i8* @memset(i8* %tmp6, i32 0, i64 2) ; <i8*> [#uses=0]
+ ret i8* %tmp6
+}
+
+declare i8* @memset(i8*, i32, i64)
diff --git a/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll b/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll
new file mode 100644
index 0000000..228cd48
--- /dev/null
+++ b/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 -mattr=+sse,-sse2
+; PR2484
+
+define <4 x float> @f4523(<4 x float> %a,<4 x float> %b) nounwind {
+entry:
+%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4,i32
+5,i32 2,i32 3>
+ret <4 x float> %shuffle
+}
diff --git a/test/CodeGen/X86/2009-07-06-TwoAddrAssert.ll b/test/CodeGen/X86/2009-07-06-TwoAddrAssert.ll
new file mode 100644
index 0000000..fcc71ae
--- /dev/null
+++ b/test/CodeGen/X86/2009-07-06-TwoAddrAssert.ll
@@ -0,0 +1,137 @@
+; RUN: llc < %s -march=x86 -mtriple=x86_64-unknown-freebsd7.2
+; PR4478
+
+ %struct.sockaddr = type <{ i8, i8, [14 x i8] }>
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+ br label %while.cond
+
+while.cond: ; preds = %sw.bb6, %entry
+ switch i32 undef, label %sw.default [
+ i32 -1, label %while.end
+ i32 119, label %sw.bb6
+ ]
+
+sw.bb6: ; preds = %while.cond
+ br i1 undef, label %if.then, label %while.cond
+
+if.then: ; preds = %sw.bb6
+ ret i32 1
+
+sw.default: ; preds = %while.cond
+ ret i32 1
+
+while.end: ; preds = %while.cond
+ br i1 undef, label %if.then15, label %if.end16
+
+if.then15: ; preds = %while.end
+ ret i32 1
+
+if.end16: ; preds = %while.end
+ br i1 undef, label %lor.lhs.false, label %if.then21
+
+lor.lhs.false: ; preds = %if.end16
+ br i1 undef, label %if.end22, label %if.then21
+
+if.then21: ; preds = %lor.lhs.false, %if.end16
+ ret i32 1
+
+if.end22: ; preds = %lor.lhs.false
+ br i1 undef, label %lor.lhs.false27, label %if.then51
+
+lor.lhs.false27: ; preds = %if.end22
+ br i1 undef, label %lor.lhs.false39, label %if.then51
+
+lor.lhs.false39: ; preds = %lor.lhs.false27
+ br i1 undef, label %if.end52, label %if.then51
+
+if.then51: ; preds = %lor.lhs.false39, %lor.lhs.false27, %if.end22
+ ret i32 1
+
+if.end52: ; preds = %lor.lhs.false39
+ br i1 undef, label %if.then57, label %if.end58
+
+if.then57: ; preds = %if.end52
+ ret i32 1
+
+if.end58: ; preds = %if.end52
+ br i1 undef, label %if.then64, label %if.end65
+
+if.then64: ; preds = %if.end58
+ ret i32 1
+
+if.end65: ; preds = %if.end58
+ br i1 undef, label %if.then71, label %if.end72
+
+if.then71: ; preds = %if.end65
+ ret i32 1
+
+if.end72: ; preds = %if.end65
+ br i1 undef, label %if.then83, label %if.end84
+
+if.then83: ; preds = %if.end72
+ ret i32 1
+
+if.end84: ; preds = %if.end72
+ br i1 undef, label %if.then101, label %if.end102
+
+if.then101: ; preds = %if.end84
+ ret i32 1
+
+if.end102: ; preds = %if.end84
+ br i1 undef, label %if.then113, label %if.end114
+
+if.then113: ; preds = %if.end102
+ ret i32 1
+
+if.end114: ; preds = %if.end102
+ br i1 undef, label %if.then209, label %if.end210
+
+if.then209: ; preds = %if.end114
+ ret i32 1
+
+if.end210: ; preds = %if.end114
+ br i1 undef, label %if.then219, label %if.end220
+
+if.then219: ; preds = %if.end210
+ ret i32 1
+
+if.end220: ; preds = %if.end210
+ br i1 undef, label %if.end243, label %lor.lhs.false230
+
+lor.lhs.false230: ; preds = %if.end220
+ unreachable
+
+if.end243: ; preds = %if.end220
+ br i1 undef, label %if.then249, label %if.end250
+
+if.then249: ; preds = %if.end243
+ ret i32 1
+
+if.end250: ; preds = %if.end243
+ br i1 undef, label %if.end261, label %if.then260
+
+if.then260: ; preds = %if.end250
+ ret i32 1
+
+if.end261: ; preds = %if.end250
+ br i1 undef, label %if.then270, label %if.end271
+
+if.then270: ; preds = %if.end261
+ ret i32 1
+
+if.end271: ; preds = %if.end261
+ %call.i = call i32 @arc4random() nounwind ; <i32> [#uses=1]
+ %rem.i = urem i32 %call.i, 16383 ; <i32> [#uses=1]
+ %rem1.i = trunc i32 %rem.i to i16 ; <i16> [#uses=1]
+ %conv2.i = or i16 %rem1.i, -16384 ; <i16> [#uses=1]
+ %0 = call i16 asm "xchgb ${0:h}, ${0:b}", "=Q,0,~{dirflag},~{fpsr},~{flags}"(i16 %conv2.i) nounwind ; <i16> [#uses=1]
+ store i16 %0, i16* undef
+ %call281 = call i32 @bind(i32 undef, %struct.sockaddr* undef, i32 16) nounwind ; <i32> [#uses=0]
+ unreachable
+}
+
+declare i32 @bind(i32, %struct.sockaddr*, i32)
+
+declare i32 @arc4random()
diff --git a/test/CodeGen/X86/2009-07-07-SplitICmp.ll b/test/CodeGen/X86/2009-07-07-SplitICmp.ll
new file mode 100644
index 0000000..eb9378b
--- /dev/null
+++ b/test/CodeGen/X86/2009-07-07-SplitICmp.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 -disable-mmx
+
+define void @test2(<2 x i32> %A, <2 x i32> %B, <2 x i32>* %C) nounwind {
+ %D = icmp sgt <2 x i32> %A, %B
+ %E = zext <2 x i1> %D to <2 x i32>
+ store <2 x i32> %E, <2 x i32>* %C
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-07-09-ExtractBoolFromVector.ll b/test/CodeGen/X86/2009-07-09-ExtractBoolFromVector.ll
new file mode 100644
index 0000000..0fdfdcb
--- /dev/null
+++ b/test/CodeGen/X86/2009-07-09-ExtractBoolFromVector.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86
+; PR3037
+
+define void @entry(<4 x i8>* %dest) {
+ %1 = xor <4 x i1> zeroinitializer, < i1 true, i1 true, i1 true, i1 true >
+ %2 = extractelement <4 x i1> %1, i32 3
+ %3 = zext i1 %2 to i8
+ %4 = insertelement <4 x i8> zeroinitializer, i8 %3, i32 3
+ store <4 x i8> %4, <4 x i8>* %dest, align 1
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-07-15-CoalescerBug.ll b/test/CodeGen/X86/2009-07-15-CoalescerBug.ll
new file mode 100644
index 0000000..eabaf77
--- /dev/null
+++ b/test/CodeGen/X86/2009-07-15-CoalescerBug.ll
@@ -0,0 +1,958 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10
+
+ %struct.ANY = type { i8* }
+ %struct.AV = type { %struct.XPVAV*, i32, i32 }
+ %struct.CLONE_PARAMS = type { %struct.AV*, i64, %struct.PerlInterpreter* }
+ %struct.CV = type { %struct.XPVCV*, i32, i32 }
+ %struct.DIR = type { i32, i64, i64, i8*, i32, i64, i64, i32, %struct.__darwin_pthread_mutex_t, %struct._telldir* }
+ %struct.GP = type { %struct.SV*, i32, %struct.io*, %struct.CV*, %struct.AV*, %struct.HV*, %struct.GV*, %struct.CV*, i32, i32, i32, i8* }
+ %struct.GV = type { %struct.XPVGV*, i32, i32 }
+ %struct.HE = type { %struct.HE*, %struct.HEK*, %struct.SV* }
+ %struct.HEK = type { i32, i32, [1 x i8] }
+ %struct.HV = type { %struct.XPVHV*, i32, i32 }
+ %struct.MAGIC = type { %struct.MAGIC*, %struct.MGVTBL*, i16, i8, i8, %struct.SV*, i8*, i32 }
+ %struct.MGVTBL = type { i32 (%struct.SV*, %struct.MAGIC*)*, i32 (%struct.SV*, %struct.MAGIC*)*, i32 (%struct.SV*, %struct.MAGIC*)*, i32 (%struct.SV*, %struct.MAGIC*)*, i32 (%struct.SV*, %struct.MAGIC*)*, i32 (%struct.SV*, %struct.MAGIC*, %struct.SV*, i8*, i32)*, i32 (%struct.MAGIC*, %struct.CLONE_PARAMS*)* }
+ %struct.OP = type { %struct.OP*, %struct.OP*, %struct.OP* ()*, i64, i16, i16, i8, i8 }
+ %struct.PMOP = type { %struct.OP*, %struct.OP*, %struct.OP* ()*, i64, i16, i16, i8, i8, %struct.OP*, %struct.OP*, %struct.OP*, %struct.OP*, %struct.PMOP*, %struct.REGEXP*, i32, i32, i8, %struct.HV* }
+ %struct.PerlIO_funcs = type { i64, i8*, i64, i32, i64 (%struct.PerlIOl**, i8*, %struct.SV*, %struct.PerlIO_funcs*)*, i64 (%struct.PerlIOl**)*, %struct.PerlIOl** (%struct.PerlIO_funcs*, %struct.PerlIO_list_t*, i64, i8*, i32, i32, i32, %struct.PerlIOl**, i32, %struct.SV**)*, i64 (%struct.PerlIOl**)*, %struct.SV* (%struct.PerlIOl**, %struct.CLONE_PARAMS*, i32)*, i64 (%struct.PerlIOl**)*, %struct.PerlIOl** (%struct.PerlIOl**, %struct.PerlIOl**, %struct.CLONE_PARAMS*, i32)*, i64 (%struct.PerlIOl**, i8*, i64)*, i64 (%struct.PerlIOl**, i8*, i64)*, i64 (%struct.PerlIOl**, i8*, i64)*, i64 (%struct.PerlIOl**, i64, i32)*, i64 (%struct.PerlIOl**)*, i64 (%struct.PerlIOl**)*, i64 (%struct.PerlIOl**)*, i64 (%struct.PerlIOl**)*, i64 (%struct.PerlIOl**)*, i64 (%struct.PerlIOl**)*, void (%struct.PerlIOl**)*, void (%struct.PerlIOl**)*, i8* (%struct.PerlIOl**)*, i64 (%struct.PerlIOl**)*, i8* (%struct.PerlIOl**)*, i64 (%struct.PerlIOl**)*, void (%struct.PerlIOl**, i8*, i64)* }
+ %struct.PerlIO_list_t = type { i64, i64, i64, %struct.PerlIO_pair_t* }
+ %struct.PerlIO_pair_t = type { %struct.PerlIO_funcs*, %struct.SV* }
+ %struct.PerlIOl = type { %struct.PerlIOl*, %struct.PerlIO_funcs*, i32 }
+ %struct.PerlInterpreter = type { i8 }
+ %struct.REGEXP = type { i32*, i32*, %struct.regnode*, %struct.reg_substr_data*, i8*, %struct.reg_data*, i8*, i32*, i32, i32, i32, i32, i32, i32, i32, i32, [1 x %struct.regnode] }
+ %struct.SV = type { i8*, i32, i32 }
+ %struct.XPVAV = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, %struct.SV**, %struct.SV*, i8 }
+ %struct.XPVCV = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, %struct.HV*, %struct.OP*, %struct.OP*, void (%struct.CV*)*, %struct.ANY, %struct.GV*, i8*, i64, %struct.AV*, %struct.CV*, i16, i32 }
+ %struct.XPVGV = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, %struct.GP*, i8*, i64, %struct.HV*, i8 }
+ %struct.XPVHV = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, i32, %struct.HE*, %struct.PMOP*, i8* }
+ %struct.XPVIO = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, %struct.PerlIOl**, %struct.PerlIOl**, %struct.anon, i64, i64, i64, i64, i8*, %struct.GV*, i8*, %struct.GV*, i8*, %struct.GV*, i16, i8, i8 }
+ %struct.__darwin_pthread_mutex_t = type { i64, [56 x i8] }
+ %struct._telldir = type opaque
+ %struct.anon = type { %struct.DIR* }
+ %struct.io = type { %struct.XPVIO*, i32, i32 }
+ %struct.reg_data = type { i32, i8*, [1 x i8*] }
+ %struct.reg_substr_data = type { [3 x %struct.reg_substr_datum] }
+ %struct.reg_substr_datum = type { i32, i32, %struct.SV*, %struct.SV* }
+ %struct.regnode = type { i8, i8, i16 }
+
+define i32 @Perl_yylex() nounwind ssp {
+entry:
+ br i1 undef, label %bb21, label %bb
+
+bb: ; preds = %entry
+ unreachable
+
+bb21: ; preds = %entry
+ switch i32 undef, label %bb103 [
+ i32 1, label %bb101
+ i32 4, label %bb75
+ i32 6, label %bb68
+ i32 7, label %bb67
+ i32 8, label %bb25
+ ]
+
+bb25: ; preds = %bb21
+ ret i32 41
+
+bb67: ; preds = %bb21
+ ret i32 40
+
+bb68: ; preds = %bb21
+ br i1 undef, label %bb69, label %bb70
+
+bb69: ; preds = %bb68
+ ret i32 undef
+
+bb70: ; preds = %bb68
+ unreachable
+
+bb75: ; preds = %bb21
+ unreachable
+
+bb101: ; preds = %bb21
+ unreachable
+
+bb103: ; preds = %bb21
+ switch i32 undef, label %bb104 [
+ i32 0, label %bb126
+ i32 4, label %fake_eof
+ i32 26, label %fake_eof
+ i32 34, label %bb1423
+ i32 36, label %bb1050
+ i32 37, label %bb534
+ i32 39, label %bb1412
+ i32 41, label %bb643
+ i32 44, label %bb544
+ i32 48, label %bb1406
+ i32 49, label %bb1406
+ i32 50, label %bb1406
+ i32 51, label %bb1406
+ i32 52, label %bb1406
+ i32 53, label %bb1406
+ i32 54, label %bb1406
+ i32 55, label %bb1406
+ i32 56, label %bb1406
+ i32 57, label %bb1406
+ i32 59, label %bb639
+ i32 65, label %keylookup
+ i32 66, label %keylookup
+ i32 67, label %keylookup
+ i32 68, label %keylookup
+ i32 69, label %keylookup
+ i32 70, label %keylookup
+ i32 71, label %keylookup
+ i32 72, label %keylookup
+ i32 73, label %keylookup
+ i32 74, label %keylookup
+ i32 75, label %keylookup
+ i32 76, label %keylookup
+ i32 77, label %keylookup
+ i32 78, label %keylookup
+ i32 79, label %keylookup
+ i32 80, label %keylookup
+ i32 81, label %keylookup
+ i32 82, label %keylookup
+ i32 83, label %keylookup
+ i32 84, label %keylookup
+ i32 85, label %keylookup
+ i32 86, label %keylookup
+ i32 87, label %keylookup
+ i32 88, label %keylookup
+ i32 89, label %keylookup
+ i32 90, label %keylookup
+ i32 92, label %bb1455
+ i32 95, label %keylookup
+ i32 96, label %bb1447
+ i32 97, label %keylookup
+ i32 98, label %keylookup
+ i32 99, label %keylookup
+ i32 100, label %keylookup
+ i32 101, label %keylookup
+ i32 102, label %keylookup
+ i32 103, label %keylookup
+ i32 104, label %keylookup
+ i32 105, label %keylookup
+ i32 106, label %keylookup
+ i32 107, label %keylookup
+ i32 108, label %keylookup
+ i32 109, label %keylookup
+ i32 110, label %keylookup
+ i32 111, label %keylookup
+ i32 112, label %keylookup
+ i32 113, label %keylookup
+ i32 114, label %keylookup
+ i32 115, label %keylookup
+ i32 116, label %keylookup
+ i32 117, label %keylookup
+ i32 118, label %keylookup
+ i32 119, label %keylookup
+ i32 120, label %keylookup
+ i32 121, label %keylookup
+ i32 122, label %keylookup
+ i32 126, label %bb544
+ ]
+
+bb104: ; preds = %bb103
+ unreachable
+
+bb126: ; preds = %bb103
+ ret i32 0
+
+fake_eof: ; preds = %bb1841, %bb103, %bb103
+ unreachable
+
+bb534: ; preds = %bb103
+ unreachable
+
+bb544: ; preds = %bb103, %bb103
+ ret i32 undef
+
+bb639: ; preds = %bb103
+ unreachable
+
+bb643: ; preds = %bb103
+ unreachable
+
+bb1050: ; preds = %bb103
+ unreachable
+
+bb1406: ; preds = %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103
+ unreachable
+
+bb1412: ; preds = %bb103
+ unreachable
+
+bb1423: ; preds = %bb103
+ unreachable
+
+bb1447: ; preds = %bb103
+ unreachable
+
+bb1455: ; preds = %bb103
+ unreachable
+
+keylookup: ; preds = %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103, %bb103
+ br i1 undef, label %bb1498, label %bb1496
+
+bb1496: ; preds = %keylookup
+ br i1 undef, label %bb1498, label %bb1510.preheader
+
+bb1498: ; preds = %bb1496, %keylookup
+ unreachable
+
+bb1510.preheader: ; preds = %bb1496
+ br i1 undef, label %bb1511, label %bb1518
+
+bb1511: ; preds = %bb1510.preheader
+ br label %bb1518
+
+bb1518: ; preds = %bb1511, %bb1510.preheader
+ switch i32 undef, label %bb741.i4285 [
+ i32 95, label %bb744.i4287
+ i32 115, label %bb852.i4394
+ ]
+
+bb741.i4285: ; preds = %bb1518
+ br label %Perl_keyword.exit4735
+
+bb744.i4287: ; preds = %bb1518
+ br label %Perl_keyword.exit4735
+
+bb852.i4394: ; preds = %bb1518
+ br i1 undef, label %bb861.i4404, label %bb856.i4399
+
+bb856.i4399: ; preds = %bb852.i4394
+ br label %Perl_keyword.exit4735
+
+bb861.i4404: ; preds = %bb852.i4394
+ br label %Perl_keyword.exit4735
+
+Perl_keyword.exit4735: ; preds = %bb861.i4404, %bb856.i4399, %bb744.i4287, %bb741.i4285
+ br i1 undef, label %bb1544, label %reserved_word
+
+bb1544: ; preds = %Perl_keyword.exit4735
+ br i1 undef, label %bb1565, label %bb1545
+
+bb1545: ; preds = %bb1544
+ br i1 undef, label %bb1563, label %bb1558
+
+bb1558: ; preds = %bb1545
+ %0 = load %struct.SV** undef ; <%struct.SV*> [#uses=1]
+ %1 = bitcast %struct.SV* %0 to %struct.GV* ; <%struct.GV*> [#uses=5]
+ br i1 undef, label %bb1563, label %bb1559
+
+bb1559: ; preds = %bb1558
+ br i1 undef, label %bb1560, label %bb1563
+
+bb1560: ; preds = %bb1559
+ br i1 undef, label %bb1563, label %bb1561
+
+bb1561: ; preds = %bb1560
+ br i1 undef, label %bb1562, label %bb1563
+
+bb1562: ; preds = %bb1561
+ br label %bb1563
+
+bb1563: ; preds = %bb1562, %bb1561, %bb1560, %bb1559, %bb1558, %bb1545
+ %gv19.3 = phi %struct.GV* [ %1, %bb1562 ], [ undef, %bb1545 ], [ %1, %bb1558 ], [ %1, %bb1559 ], [ %1, %bb1560 ], [ %1, %bb1561 ] ; <%struct.GV*> [#uses=0]
+ br i1 undef, label %bb1565, label %reserved_word
+
+bb1565: ; preds = %bb1563, %bb1544
+ br i1 undef, label %bb1573, label %bb1580
+
+bb1573: ; preds = %bb1565
+ br label %bb1580
+
+bb1580: ; preds = %bb1573, %bb1565
+ br i1 undef, label %bb1595, label %reserved_word
+
+bb1595: ; preds = %bb1580
+ br i1 undef, label %reserved_word, label %bb1597
+
+bb1597: ; preds = %bb1595
+ br i1 undef, label %reserved_word, label %bb1602
+
+bb1602: ; preds = %bb1597
+ br label %reserved_word
+
+reserved_word: ; preds = %bb1602, %bb1597, %bb1595, %bb1580, %bb1563, %Perl_keyword.exit4735
+ switch i32 undef, label %bb2012 [
+ i32 1, label %bb1819
+ i32 2, label %bb1830
+ i32 4, label %bb1841
+ i32 5, label %bb1841
+ i32 8, label %bb1880
+ i32 14, label %bb1894
+ i32 16, label %bb1895
+ i32 17, label %bb1896
+ i32 18, label %bb1897
+ i32 19, label %bb1898
+ i32 20, label %bb1899
+ i32 22, label %bb1906
+ i32 23, label %bb1928
+ i32 24, label %bb2555
+ i32 26, label %bb1929
+ i32 31, label %bb1921
+ i32 32, label %bb1930
+ i32 33, label %bb1905
+ i32 34, label %bb1936
+ i32 35, label %bb1927
+ i32 37, label %bb1962
+ i32 40, label %bb1951
+ i32 41, label %bb1946
+ i32 42, label %bb1968
+ i32 44, label %bb1969
+ i32 45, label %bb1970
+ i32 46, label %bb2011
+ i32 47, label %bb2006
+ i32 48, label %bb2007
+ i32 49, label %bb2009
+ i32 50, label %bb2010
+ i32 51, label %bb2008
+ i32 53, label %bb1971
+ i32 54, label %bb1982
+ i32 55, label %bb2005
+ i32 59, label %bb2081
+ i32 61, label %bb2087
+ i32 64, label %bb2080
+ i32 65, label %really_sub
+ i32 66, label %bb2079
+ i32 67, label %bb2089
+ i32 69, label %bb2155
+ i32 72, label %bb2137
+ i32 74, label %bb2138
+ i32 75, label %bb2166
+ i32 76, label %bb2144
+ i32 78, label %bb2145
+ i32 81, label %bb2102
+ i32 82, label %bb2108
+ i32 84, label %bb2114
+ i32 85, label %bb2115
+ i32 86, label %bb2116
+ i32 89, label %bb2146
+ i32 90, label %bb2147
+ i32 91, label %bb2148
+ i32 93, label %bb2154
+ i32 94, label %bb2167
+ i32 96, label %bb2091
+ i32 97, label %bb2090
+ i32 98, label %bb2088
+ i32 100, label %bb2173
+ i32 101, label %bb2174
+ i32 102, label %bb2175
+ i32 103, label %bb2180
+ i32 104, label %bb2181
+ i32 106, label %bb2187
+ i32 107, label %bb2188
+ i32 110, label %bb2206
+ i32 112, label %bb2217
+ i32 113, label %bb2218
+ i32 114, label %bb2199
+ i32 119, label %bb2205
+ i32 120, label %bb2229
+ i32 121, label %bb2233
+ i32 122, label %bb2234
+ i32 123, label %bb2235
+ i32 124, label %bb2236
+ i32 125, label %bb2237
+ i32 126, label %bb2238
+ i32 127, label %bb2239
+ i32 128, label %bb2268
+ i32 129, label %bb2267
+ i32 133, label %bb2276
+ i32 134, label %bb2348
+ i32 135, label %bb2337
+ i32 137, label %bb2239
+ i32 138, label %bb2367
+ i32 139, label %bb2368
+ i32 140, label %bb2369
+ i32 141, label %bb2357
+ i32 143, label %bb2349
+ i32 144, label %bb2350
+ i32 146, label %bb2356
+ i32 147, label %bb2370
+ i32 148, label %bb2445
+ i32 149, label %bb2453
+ i32 151, label %bb2381
+ i32 152, label %bb2457
+ i32 154, label %bb2516
+ i32 156, label %bb2522
+ i32 158, label %bb2527
+ i32 159, label %bb2537
+ i32 160, label %bb2503
+ i32 162, label %bb2504
+ i32 163, label %bb2464
+ i32 165, label %bb2463
+ i32 166, label %bb2538
+ i32 168, label %bb2515
+ i32 170, label %bb2549
+ i32 172, label %bb2566
+ i32 173, label %bb2595
+ i32 174, label %bb2565
+ i32 175, label %bb2567
+ i32 176, label %bb2568
+ i32 177, label %bb2569
+ i32 178, label %bb2570
+ i32 179, label %bb2594
+ i32 182, label %bb2571
+ i32 183, label %bb2572
+ i32 185, label %bb2593
+ i32 186, label %bb2583
+ i32 187, label %bb2596
+ i32 189, label %bb2602
+ i32 190, label %bb2603
+ i32 191, label %bb2604
+ i32 192, label %bb2605
+ i32 193, label %bb2606
+ i32 196, label %bb2617
+ i32 197, label %bb2618
+ i32 198, label %bb2619
+ i32 199, label %bb2627
+ i32 200, label %bb2625
+ i32 201, label %bb2626
+ i32 206, label %really_sub
+ i32 207, label %bb2648
+ i32 208, label %bb2738
+ i32 209, label %bb2739
+ i32 210, label %bb2740
+ i32 211, label %bb2742
+ i32 212, label %bb2741
+ i32 213, label %bb2737
+ i32 214, label %bb2743
+ i32 217, label %bb2758
+ i32 219, label %bb2764
+ i32 220, label %bb2765
+ i32 221, label %bb2744
+ i32 222, label %bb2766
+ i32 226, label %bb2785
+ i32 227, label %bb2783
+ i32 228, label %bb2784
+ i32 229, label %bb2790
+ i32 230, label %bb2797
+ i32 232, label %bb2782
+ i32 234, label %bb2791
+ i32 236, label %bb2815
+ i32 237, label %bb2818
+ i32 238, label %bb2819
+ i32 239, label %bb2820
+ i32 240, label %bb2817
+ i32 241, label %bb2816
+ i32 242, label %bb2821
+ i32 243, label %bb2826
+ i32 244, label %bb2829
+ i32 245, label %bb2830
+ ]
+
+bb1819: ; preds = %reserved_word
+ unreachable
+
+bb1830: ; preds = %reserved_word
+ unreachable
+
+bb1841: ; preds = %reserved_word, %reserved_word
+ br i1 undef, label %fake_eof, label %bb1842
+
+bb1842: ; preds = %bb1841
+ unreachable
+
+bb1880: ; preds = %reserved_word
+ unreachable
+
+bb1894: ; preds = %reserved_word
+ ret i32 undef
+
+bb1895: ; preds = %reserved_word
+ ret i32 301
+
+bb1896: ; preds = %reserved_word
+ ret i32 undef
+
+bb1897: ; preds = %reserved_word
+ ret i32 undef
+
+bb1898: ; preds = %reserved_word
+ ret i32 undef
+
+bb1899: ; preds = %reserved_word
+ ret i32 undef
+
+bb1905: ; preds = %reserved_word
+ ret i32 278
+
+bb1906: ; preds = %reserved_word
+ unreachable
+
+bb1921: ; preds = %reserved_word
+ ret i32 288
+
+bb1927: ; preds = %reserved_word
+ ret i32 undef
+
+bb1928: ; preds = %reserved_word
+ ret i32 undef
+
+bb1929: ; preds = %reserved_word
+ ret i32 undef
+
+bb1930: ; preds = %reserved_word
+ ret i32 undef
+
+bb1936: ; preds = %reserved_word
+ br i1 undef, label %bb2834, label %bb1937
+
+bb1937: ; preds = %bb1936
+ ret i32 undef
+
+bb1946: ; preds = %reserved_word
+ unreachable
+
+bb1951: ; preds = %reserved_word
+ ret i32 undef
+
+bb1962: ; preds = %reserved_word
+ ret i32 undef
+
+bb1968: ; preds = %reserved_word
+ ret i32 280
+
+bb1969: ; preds = %reserved_word
+ ret i32 276
+
+bb1970: ; preds = %reserved_word
+ ret i32 277
+
+bb1971: ; preds = %reserved_word
+ ret i32 288
+
+bb1982: ; preds = %reserved_word
+ br i1 undef, label %bb2834, label %bb1986
+
+bb1986: ; preds = %bb1982
+ ret i32 undef
+
+bb2005: ; preds = %reserved_word
+ ret i32 undef
+
+bb2006: ; preds = %reserved_word
+ ret i32 282
+
+bb2007: ; preds = %reserved_word
+ ret i32 282
+
+bb2008: ; preds = %reserved_word
+ ret i32 282
+
+bb2009: ; preds = %reserved_word
+ ret i32 282
+
+bb2010: ; preds = %reserved_word
+ ret i32 282
+
+bb2011: ; preds = %reserved_word
+ ret i32 282
+
+bb2012: ; preds = %reserved_word
+ unreachable
+
+bb2079: ; preds = %reserved_word
+ ret i32 undef
+
+bb2080: ; preds = %reserved_word
+ ret i32 282
+
+bb2081: ; preds = %reserved_word
+ ret i32 undef
+
+bb2087: ; preds = %reserved_word
+ ret i32 undef
+
+bb2088: ; preds = %reserved_word
+ ret i32 287
+
+bb2089: ; preds = %reserved_word
+ ret i32 287
+
+bb2090: ; preds = %reserved_word
+ ret i32 undef
+
+bb2091: ; preds = %reserved_word
+ ret i32 280
+
+bb2102: ; preds = %reserved_word
+ ret i32 282
+
+bb2108: ; preds = %reserved_word
+ ret i32 undef
+
+bb2114: ; preds = %reserved_word
+ ret i32 undef
+
+bb2115: ; preds = %reserved_word
+ ret i32 282
+
+bb2116: ; preds = %reserved_word
+ ret i32 282
+
+bb2137: ; preds = %reserved_word
+ ret i32 undef
+
+bb2138: ; preds = %reserved_word
+ ret i32 282
+
+bb2144: ; preds = %reserved_word
+ ret i32 undef
+
+bb2145: ; preds = %reserved_word
+ ret i32 282
+
+bb2146: ; preds = %reserved_word
+ ret i32 undef
+
+bb2147: ; preds = %reserved_word
+ ret i32 undef
+
+bb2148: ; preds = %reserved_word
+ ret i32 282
+
+bb2154: ; preds = %reserved_word
+ ret i32 undef
+
+bb2155: ; preds = %reserved_word
+ ret i32 282
+
+bb2166: ; preds = %reserved_word
+ ret i32 282
+
+bb2167: ; preds = %reserved_word
+ ret i32 undef
+
+bb2173: ; preds = %reserved_word
+ ret i32 274
+
+bb2174: ; preds = %reserved_word
+ ret i32 undef
+
+bb2175: ; preds = %reserved_word
+ br i1 undef, label %bb2834, label %bb2176
+
+bb2176: ; preds = %bb2175
+ ret i32 undef
+
+bb2180: ; preds = %reserved_word
+ ret i32 undef
+
+bb2181: ; preds = %reserved_word
+ ret i32 undef
+
+bb2187: ; preds = %reserved_word
+ ret i32 undef
+
+bb2188: ; preds = %reserved_word
+ ret i32 280
+
+bb2199: ; preds = %reserved_word
+ ret i32 295
+
+bb2205: ; preds = %reserved_word
+ ret i32 287
+
+bb2206: ; preds = %reserved_word
+ ret i32 287
+
+bb2217: ; preds = %reserved_word
+ ret i32 undef
+
+bb2218: ; preds = %reserved_word
+ ret i32 undef
+
+bb2229: ; preds = %reserved_word
+ unreachable
+
+bb2233: ; preds = %reserved_word
+ ret i32 undef
+
+bb2234: ; preds = %reserved_word
+ ret i32 undef
+
+bb2235: ; preds = %reserved_word
+ ret i32 undef
+
+bb2236: ; preds = %reserved_word
+ ret i32 undef
+
+bb2237: ; preds = %reserved_word
+ ret i32 undef
+
+bb2238: ; preds = %reserved_word
+ ret i32 undef
+
+bb2239: ; preds = %reserved_word, %reserved_word
+ unreachable
+
+bb2267: ; preds = %reserved_word
+ ret i32 280
+
+bb2268: ; preds = %reserved_word
+ ret i32 288
+
+bb2276: ; preds = %reserved_word
+ unreachable
+
+bb2337: ; preds = %reserved_word
+ ret i32 300
+
+bb2348: ; preds = %reserved_word
+ ret i32 undef
+
+bb2349: ; preds = %reserved_word
+ ret i32 undef
+
+bb2350: ; preds = %reserved_word
+ ret i32 undef
+
+bb2356: ; preds = %reserved_word
+ ret i32 undef
+
+bb2357: ; preds = %reserved_word
+ br i1 undef, label %bb2834, label %bb2358
+
+bb2358: ; preds = %bb2357
+ ret i32 undef
+
+bb2367: ; preds = %reserved_word
+ ret i32 undef
+
+bb2368: ; preds = %reserved_word
+ ret i32 270
+
+bb2369: ; preds = %reserved_word
+ ret i32 undef
+
+bb2370: ; preds = %reserved_word
+ unreachable
+
+bb2381: ; preds = %reserved_word
+ unreachable
+
+bb2445: ; preds = %reserved_word
+ unreachable
+
+bb2453: ; preds = %reserved_word
+ unreachable
+
+bb2457: ; preds = %reserved_word
+ unreachable
+
+bb2463: ; preds = %reserved_word
+ ret i32 286
+
+bb2464: ; preds = %reserved_word
+ unreachable
+
+bb2503: ; preds = %reserved_word
+ ret i32 280
+
+bb2504: ; preds = %reserved_word
+ ret i32 undef
+
+bb2515: ; preds = %reserved_word
+ ret i32 undef
+
+bb2516: ; preds = %reserved_word
+ ret i32 undef
+
+bb2522: ; preds = %reserved_word
+ unreachable
+
+bb2527: ; preds = %reserved_word
+ unreachable
+
+bb2537: ; preds = %reserved_word
+ ret i32 undef
+
+bb2538: ; preds = %reserved_word
+ ret i32 undef
+
+bb2549: ; preds = %reserved_word
+ unreachable
+
+bb2555: ; preds = %reserved_word
+ br i1 undef, label %bb2834, label %bb2556
+
+bb2556: ; preds = %bb2555
+ ret i32 undef
+
+bb2565: ; preds = %reserved_word
+ ret i32 undef
+
+bb2566: ; preds = %reserved_word
+ ret i32 undef
+
+bb2567: ; preds = %reserved_word
+ ret i32 undef
+
+bb2568: ; preds = %reserved_word
+ ret i32 undef
+
+bb2569: ; preds = %reserved_word
+ ret i32 undef
+
+bb2570: ; preds = %reserved_word
+ ret i32 undef
+
+bb2571: ; preds = %reserved_word
+ ret i32 undef
+
+bb2572: ; preds = %reserved_word
+ ret i32 undef
+
+bb2583: ; preds = %reserved_word
+ br i1 undef, label %bb2834, label %bb2584
+
+bb2584: ; preds = %bb2583
+ ret i32 undef
+
+bb2593: ; preds = %reserved_word
+ ret i32 282
+
+bb2594: ; preds = %reserved_word
+ ret i32 282
+
+bb2595: ; preds = %reserved_word
+ ret i32 undef
+
+bb2596: ; preds = %reserved_word
+ ret i32 undef
+
+bb2602: ; preds = %reserved_word
+ ret i32 undef
+
+bb2603: ; preds = %reserved_word
+ ret i32 undef
+
+bb2604: ; preds = %reserved_word
+ ret i32 undef
+
+bb2605: ; preds = %reserved_word
+ ret i32 undef
+
+bb2606: ; preds = %reserved_word
+ ret i32 undef
+
+bb2617: ; preds = %reserved_word
+ ret i32 undef
+
+bb2618: ; preds = %reserved_word
+ ret i32 undef
+
+bb2619: ; preds = %reserved_word
+ unreachable
+
+bb2625: ; preds = %reserved_word
+ ret i32 undef
+
+bb2626: ; preds = %reserved_word
+ ret i32 undef
+
+bb2627: ; preds = %reserved_word
+ ret i32 undef
+
+bb2648: ; preds = %reserved_word
+ ret i32 undef
+
+really_sub: ; preds = %reserved_word, %reserved_word
+ unreachable
+
+bb2737: ; preds = %reserved_word
+ ret i32 undef
+
+bb2738: ; preds = %reserved_word
+ ret i32 undef
+
+bb2739: ; preds = %reserved_word
+ ret i32 undef
+
+bb2740: ; preds = %reserved_word
+ ret i32 undef
+
+bb2741: ; preds = %reserved_word
+ ret i32 undef
+
+bb2742: ; preds = %reserved_word
+ ret i32 undef
+
+bb2743: ; preds = %reserved_word
+ ret i32 undef
+
+bb2744: ; preds = %reserved_word
+ unreachable
+
+bb2758: ; preds = %reserved_word
+ ret i32 undef
+
+bb2764: ; preds = %reserved_word
+ ret i32 282
+
+bb2765: ; preds = %reserved_word
+ ret i32 282
+
+bb2766: ; preds = %reserved_word
+ ret i32 undef
+
+bb2782: ; preds = %reserved_word
+ ret i32 273
+
+bb2783: ; preds = %reserved_word
+ ret i32 275
+
+bb2784: ; preds = %reserved_word
+ ret i32 undef
+
+bb2785: ; preds = %reserved_word
+ br i1 undef, label %bb2834, label %bb2786
+
+bb2786: ; preds = %bb2785
+ ret i32 undef
+
+bb2790: ; preds = %reserved_word
+ ret i32 undef
+
+bb2791: ; preds = %reserved_word
+ ret i32 undef
+
+bb2797: ; preds = %reserved_word
+ ret i32 undef
+
+bb2815: ; preds = %reserved_word
+ ret i32 undef
+
+bb2816: ; preds = %reserved_word
+ ret i32 272
+
+bb2817: ; preds = %reserved_word
+ ret i32 undef
+
+bb2818: ; preds = %reserved_word
+ ret i32 282
+
+bb2819: ; preds = %reserved_word
+ ret i32 undef
+
+bb2820: ; preds = %reserved_word
+ ret i32 282
+
+bb2821: ; preds = %reserved_word
+ unreachable
+
+bb2826: ; preds = %reserved_word
+ unreachable
+
+bb2829: ; preds = %reserved_word
+ ret i32 300
+
+bb2830: ; preds = %reserved_word
+ unreachable
+
+bb2834: ; preds = %bb2785, %bb2583, %bb2555, %bb2357, %bb2175, %bb1982, %bb1936
+ ret i32 283
+}
diff --git a/test/CodeGen/X86/2009-07-16-CoalescerBug.ll b/test/CodeGen/X86/2009-07-16-CoalescerBug.ll
new file mode 100644
index 0000000..48af440
--- /dev/null
+++ b/test/CodeGen/X86/2009-07-16-CoalescerBug.ll
@@ -0,0 +1,210 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10
+; rdar://7059496
+
+ %struct.brinfo = type <{ %struct.brinfo*, %struct.brinfo*, i8*, i32, i32, i32, i8, i8, i8, i8 }>
+ %struct.cadata = type <{ i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i32, i32, %struct.cmatcher*, i8*, i8*, i8*, i8*, i8*, i8*, i32, i8, i8, i8, i8 }>
+ %struct.cline = type <{ %struct.cline*, i32, i8, i8, i8, i8, i8*, i32, i8, i8, i8, i8, i8*, i32, i8, i8, i8, i8, i8*, i32, i32, %struct.cline*, %struct.cline*, i32, i32 }>
+ %struct.cmatch = type <{ i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i32, i8, i8, i8, i8, i32*, i32*, i8*, i8*, i32, i32, i32, i32, i16, i8, i8, i16, i8, i8 }>
+ %struct.cmatcher = type <{ i32, i8, i8, i8, i8, %struct.cmatcher*, i32, i8, i8, i8, i8, %struct.cpattern*, i32, i8, i8, i8, i8, %struct.cpattern*, i32, i8, i8, i8, i8, %struct.cpattern*, i32, i8, i8, i8, i8, %struct.cpattern*, i32, i8, i8, i8, i8 }>
+ %struct.cpattern = type <{ %struct.cpattern*, i32, i8, i8, i8, i8, %union.anon }>
+ %struct.patprog = type <{ i64, i64, i64, i64, i32, i32, i32, i32, i8, i8, i8, i8, i8, i8, i8, i8 }>
+ %union.anon = type <{ [8 x i8] }>
+
+define i32 @addmatches(%struct.cadata* %dat, i8** nocapture %argv) nounwind ssp {
+entry:
+ br i1 undef, label %if.else, label %if.then91
+
+if.then91: ; preds = %entry
+ br label %if.end96
+
+if.else: ; preds = %entry
+ br label %if.end96
+
+if.end96: ; preds = %if.else, %if.then91
+ br i1 undef, label %lor.lhs.false, label %if.then105
+
+lor.lhs.false: ; preds = %if.end96
+ br i1 undef, label %if.else139, label %if.then105
+
+if.then105: ; preds = %lor.lhs.false, %if.end96
+ unreachable
+
+if.else139: ; preds = %lor.lhs.false
+ br i1 undef, label %land.end, label %land.rhs
+
+land.rhs: ; preds = %if.else139
+ unreachable
+
+land.end: ; preds = %if.else139
+ br i1 undef, label %land.lhs.true285, label %if.then315
+
+land.lhs.true285: ; preds = %land.end
+ br i1 undef, label %if.end324, label %if.then322
+
+if.then315: ; preds = %land.end
+ unreachable
+
+if.then322: ; preds = %land.lhs.true285
+ unreachable
+
+if.end324: ; preds = %land.lhs.true285
+ br i1 undef, label %if.end384, label %if.then358
+
+if.then358: ; preds = %if.end324
+ unreachable
+
+if.end384: ; preds = %if.end324
+ br i1 undef, label %if.end394, label %land.lhs.true387
+
+land.lhs.true387: ; preds = %if.end384
+ unreachable
+
+if.end394: ; preds = %if.end384
+ br i1 undef, label %if.end498, label %land.lhs.true399
+
+land.lhs.true399: ; preds = %if.end394
+ br i1 undef, label %if.end498, label %if.then406
+
+if.then406: ; preds = %land.lhs.true399
+ unreachable
+
+if.end498: ; preds = %land.lhs.true399, %if.end394
+ br i1 undef, label %if.end514, label %if.then503
+
+if.then503: ; preds = %if.end498
+ unreachable
+
+if.end514: ; preds = %if.end498
+ br i1 undef, label %if.end585, label %if.then520
+
+if.then520: ; preds = %if.end514
+ br i1 undef, label %lor.lhs.false547, label %if.then560
+
+lor.lhs.false547: ; preds = %if.then520
+ unreachable
+
+if.then560: ; preds = %if.then520
+ br i1 undef, label %if.end585, label %land.lhs.true566
+
+land.lhs.true566: ; preds = %if.then560
+ br i1 undef, label %if.end585, label %if.then573
+
+if.then573: ; preds = %land.lhs.true566
+ unreachable
+
+if.end585: ; preds = %land.lhs.true566, %if.then560, %if.end514
+ br i1 undef, label %cond.true593, label %cond.false599
+
+cond.true593: ; preds = %if.end585
+ unreachable
+
+cond.false599: ; preds = %if.end585
+ br i1 undef, label %if.end647, label %if.then621
+
+if.then621: ; preds = %cond.false599
+ br i1 undef, label %cond.true624, label %cond.false630
+
+cond.true624: ; preds = %if.then621
+ br label %if.end647
+
+cond.false630: ; preds = %if.then621
+ unreachable
+
+if.end647: ; preds = %cond.true624, %cond.false599
+ br i1 undef, label %if.end723, label %if.then701
+
+if.then701: ; preds = %if.end647
+ br label %if.end723
+
+if.end723: ; preds = %if.then701, %if.end647
+ br i1 undef, label %if.else1090, label %if.then729
+
+if.then729: ; preds = %if.end723
+ br i1 undef, label %if.end887, label %if.then812
+
+if.then812: ; preds = %if.then729
+ unreachable
+
+if.end887: ; preds = %if.then729
+ br i1 undef, label %if.end972, label %if.then893
+
+if.then893: ; preds = %if.end887
+ br i1 undef, label %if.end919, label %if.then903
+
+if.then903: ; preds = %if.then893
+ unreachable
+
+if.end919: ; preds = %if.then893
+ br label %if.end972
+
+if.end972: ; preds = %if.end919, %if.end887
+ %sline.0 = phi %struct.cline* [ undef, %if.end919 ], [ null, %if.end887 ] ; <%struct.cline*> [#uses=5]
+ %bcs.0 = phi i32 [ undef, %if.end919 ], [ 0, %if.end887 ] ; <i32> [#uses=5]
+ br i1 undef, label %if.end1146, label %land.lhs.true975
+
+land.lhs.true975: ; preds = %if.end972
+ br i1 undef, label %if.end1146, label %if.then980
+
+if.then980: ; preds = %land.lhs.true975
+ br i1 undef, label %cond.false1025, label %cond.false1004
+
+cond.false1004: ; preds = %if.then980
+ unreachable
+
+cond.false1025: ; preds = %if.then980
+ br i1 undef, label %if.end1146, label %if.then1071
+
+if.then1071: ; preds = %cond.false1025
+ br i1 undef, label %if.then1074, label %if.end1081
+
+if.then1074: ; preds = %if.then1071
+ br label %if.end1081
+
+if.end1081: ; preds = %if.then1074, %if.then1071
+ %call1083 = call %struct.patprog* @patcompile(i8* undef, i32 0, i8** null) nounwind ssp ; <%struct.patprog*> [#uses=2]
+ br i1 undef, label %if.end1146, label %if.then1086
+
+if.then1086: ; preds = %if.end1081
+ br label %if.end1146
+
+if.else1090: ; preds = %if.end723
+ br i1 undef, label %if.end1146, label %land.lhs.true1093
+
+land.lhs.true1093: ; preds = %if.else1090
+ br i1 undef, label %if.end1146, label %if.then1098
+
+if.then1098: ; preds = %land.lhs.true1093
+ unreachable
+
+if.end1146: ; preds = %land.lhs.true1093, %if.else1090, %if.then1086, %if.end1081, %cond.false1025, %land.lhs.true975, %if.end972
+ %cp.0 = phi %struct.patprog* [ %call1083, %if.then1086 ], [ null, %if.end972 ], [ null, %land.lhs.true975 ], [ null, %cond.false1025 ], [ %call1083, %if.end1081 ], [ null, %if.else1090 ], [ null, %land.lhs.true1093 ] ; <%struct.patprog*> [#uses=1]
+ %sline.1 = phi %struct.cline* [ %sline.0, %if.then1086 ], [ %sline.0, %if.end972 ], [ %sline.0, %land.lhs.true975 ], [ %sline.0, %cond.false1025 ], [ %sline.0, %if.end1081 ], [ null, %if.else1090 ], [ null, %land.lhs.true1093 ] ; <%struct.cline*> [#uses=1]
+ %bcs.1 = phi i32 [ %bcs.0, %if.then1086 ], [ %bcs.0, %if.end972 ], [ %bcs.0, %land.lhs.true975 ], [ %bcs.0, %cond.false1025 ], [ %bcs.0, %if.end1081 ], [ 0, %if.else1090 ], [ 0, %land.lhs.true1093 ] ; <i32> [#uses=1]
+ br i1 undef, label %if.end1307, label %do.body1270
+
+do.body1270: ; preds = %if.end1146
+ unreachable
+
+if.end1307: ; preds = %if.end1146
+ br i1 undef, label %if.end1318, label %if.then1312
+
+if.then1312: ; preds = %if.end1307
+ unreachable
+
+if.end1318: ; preds = %if.end1307
+ br i1 undef, label %for.cond1330.preheader, label %if.then1323
+
+if.then1323: ; preds = %if.end1318
+ unreachable
+
+for.cond1330.preheader: ; preds = %if.end1318
+ %call1587 = call i8* @comp_match(i8* undef, i8* undef, i8* undef, %struct.patprog* %cp.0, %struct.cline** undef, i32 0, %struct.brinfo** undef, i32 0, %struct.brinfo** undef, i32 %bcs.1, i32* undef) nounwind ssp ; <i8*> [#uses=0]
+ %call1667 = call %struct.cmatch* @add_match_data(i32 0, i8* undef, i8* undef, %struct.cline* undef, i8* undef, i8* null, i8* undef, i8* undef, i8* undef, i8* undef, %struct.cline* null, i8* undef, %struct.cline* %sline.1, i8* undef, i32 undef, i32 undef) ssp ; <%struct.cmatch*> [#uses=0]
+ unreachable
+}
+
+declare %struct.patprog* @patcompile(i8*, i32, i8**) ssp
+
+declare i8* @comp_match(i8*, i8*, i8*, %struct.patprog*, %struct.cline**, i32, %struct.brinfo**, i32, %struct.brinfo**, i32, i32*) ssp
+
+declare %struct.cmatch* @add_match_data(i32, i8*, i8*, %struct.cline*, i8*, i8*, i8*, i8*, i8*, i8*, %struct.cline*, i8*, %struct.cline*, i8*, i32, i32) nounwind ssp
diff --git a/test/CodeGen/X86/2009-07-16-LoadFoldingBug.ll b/test/CodeGen/X86/2009-07-16-LoadFoldingBug.ll
new file mode 100644
index 0000000..e21c892
--- /dev/null
+++ b/test/CodeGen/X86/2009-07-16-LoadFoldingBug.ll
@@ -0,0 +1,102 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
+
+; CHECK: _foo:
+; CHECK: pavgw LCPI1_4(%rip)
+
+; rdar://7057804
+
+define void @foo(i16* %out8x8, i16* %in8x8, i32 %lastrow) optsize ssp {
+entry:
+ %0 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> <i16 6518, i16 6518, i16 6518, i16 6518, i16 6518, i16 6518, i16 6518, i16 6518>, <8 x i16> undef) nounwind readnone ; <<8 x i16>> [#uses=2]
+ %1 = call <8 x i16> @llvm.x86.sse2.pcmpeq.w(<8 x i16> %0, <8 x i16> <i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384>) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %2 = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> zeroinitializer, i32 14) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %3 = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %2, <8 x i16> zeroinitializer) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp.i.i10 = add <8 x i16> %0, %3 ; <<8 x i16>> [#uses=1]
+ %4 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> zeroinitializer, <8 x i16> %1) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %5 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %tmp.i.i10, <8 x i16> %4) nounwind readnone ; <<8 x i16>> [#uses=3]
+ %6 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> %5, <8 x i16> undef) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %7 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> <i16 6518, i16 6518, i16 6518, i16 6518, i16 6518, i16 6518, i16 6518, i16 6518>, <8 x i16> undef) nounwind readnone ; <<8 x i16>> [#uses=2]
+ %8 = call <8 x i16> @llvm.x86.sse2.pcmpeq.w(<8 x i16> %7, <8 x i16> <i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384>) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %9 = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> zeroinitializer, i32 14) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %10 = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %9, <8 x i16> zeroinitializer) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp.i.i8 = add <8 x i16> %7, %10 ; <<8 x i16>> [#uses=1]
+ %11 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> undef, <8 x i16> %8) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %12 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %tmp.i.i8, <8 x i16> %11) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %13 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> undef, <8 x i16> undef) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %14 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> %5, <8 x i16> undef) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %15 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %5, <8 x i16> undef) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %16 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %6, <8 x i16> undef) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %17 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %12, <8 x i16> undef) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %18 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> %13, <8 x i16> %15) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %19 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> undef, <8 x i16> %14) nounwind readnone ; <<8 x i16>> [#uses=2]
+ %20 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> undef, <8 x i16> undef) nounwind readnone ; <<8 x i16>> [#uses=4]
+ %21 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> undef, <8 x i16> %17) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %22 = bitcast <8 x i16> %21 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %23 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> <i16 23170, i16 23170, i16 23170, i16 23170, i16 23170, i16 23170, i16 23170, i16 23170>, <8 x i16> undef) nounwind readnone ; <<8 x i16>> [#uses=2]
+ %24 = call <8 x i16> @llvm.x86.sse2.pcmpeq.w(<8 x i16> %23, <8 x i16> <i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384>) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %25 = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> zeroinitializer, i32 14) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %26 = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %25, <8 x i16> zeroinitializer) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp.i.i6 = add <8 x i16> %23, %26 ; <<8 x i16>> [#uses=1]
+ %27 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> undef, <8 x i16> %24) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %28 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %tmp.i.i6, <8 x i16> %27) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %29 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> <i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170>, <8 x i16> undef) nounwind readnone ; <<8 x i16>> [#uses=2]
+ %30 = call <8 x i16> @llvm.x86.sse2.pcmpeq.w(<8 x i16> %29, <8 x i16> <i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384>) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %31 = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> zeroinitializer, i32 14) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %32 = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %31, <8 x i16> zeroinitializer) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp.i.i4 = add <8 x i16> %29, %32 ; <<8 x i16>> [#uses=1]
+ %33 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> undef, <8 x i16> %30) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %34 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %tmp.i.i4, <8 x i16> %33) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %35 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> <i16 23170, i16 23170, i16 23170, i16 23170, i16 23170, i16 23170, i16 23170, i16 23170>, <8 x i16> %20) nounwind readnone ; <<8 x i16>> [#uses=2]
+ %tmp.i2.i1 = mul <8 x i16> %20, <i16 23170, i16 23170, i16 23170, i16 23170, i16 23170, i16 23170, i16 23170, i16 23170> ; <<8 x i16>> [#uses=1]
+ %36 = call <8 x i16> @llvm.x86.sse2.pcmpeq.w(<8 x i16> %35, <8 x i16> <i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384>) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %37 = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %tmp.i2.i1, i32 14) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %38 = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %37, <8 x i16> zeroinitializer) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp.i.i2 = add <8 x i16> %35, %38 ; <<8 x i16>> [#uses=1]
+ %39 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> %19, <8 x i16> %36) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %40 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %tmp.i.i2, <8 x i16> %39) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %41 = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> <i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170>, <8 x i16> %20) nounwind readnone ; <<8 x i16>> [#uses=2]
+ %tmp.i2.i = mul <8 x i16> %20, <i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170> ; <<8 x i16>> [#uses=1]
+ %42 = call <8 x i16> @llvm.x86.sse2.pcmpeq.w(<8 x i16> %41, <8 x i16> <i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384, i16 16384>) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %43 = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %tmp.i2.i, i32 14) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %44 = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %43, <8 x i16> zeroinitializer) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp.i.i = add <8 x i16> %41, %44 ; <<8 x i16>> [#uses=1]
+ %45 = call <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16> %19, <8 x i16> %42) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %46 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %tmp.i.i, <8 x i16> %45) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %47 = call <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16> %18, <8 x i16> %16) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %48 = bitcast <8 x i16> %47 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %49 = bitcast <8 x i16> %28 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %50 = getelementptr i16* %out8x8, i64 8 ; <i16*> [#uses=1]
+ %51 = bitcast i16* %50 to <2 x i64>* ; <<2 x i64>*> [#uses=1]
+ store <2 x i64> %49, <2 x i64>* %51, align 16
+ %52 = bitcast <8 x i16> %40 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %53 = getelementptr i16* %out8x8, i64 16 ; <i16*> [#uses=1]
+ %54 = bitcast i16* %53 to <2 x i64>* ; <<2 x i64>*> [#uses=1]
+ store <2 x i64> %52, <2 x i64>* %54, align 16
+ %55 = getelementptr i16* %out8x8, i64 24 ; <i16*> [#uses=1]
+ %56 = bitcast i16* %55 to <2 x i64>* ; <<2 x i64>*> [#uses=1]
+ store <2 x i64> %48, <2 x i64>* %56, align 16
+ %57 = bitcast <8 x i16> %46 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %58 = getelementptr i16* %out8x8, i64 40 ; <i16*> [#uses=1]
+ %59 = bitcast i16* %58 to <2 x i64>* ; <<2 x i64>*> [#uses=1]
+ store <2 x i64> %57, <2 x i64>* %59, align 16
+ %60 = bitcast <8 x i16> %34 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %61 = getelementptr i16* %out8x8, i64 48 ; <i16*> [#uses=1]
+ %62 = bitcast i16* %61 to <2 x i64>* ; <<2 x i64>*> [#uses=1]
+ store <2 x i64> %60, <2 x i64>* %62, align 16
+ %63 = getelementptr i16* %out8x8, i64 56 ; <i16*> [#uses=1]
+ %64 = bitcast i16* %63 to <2 x i64>* ; <<2 x i64>*> [#uses=1]
+ store <2 x i64> %22, <2 x i64>* %64, align 16
+ ret void
+}
+
+declare <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+declare <8 x i16> @llvm.x86.sse2.pcmpeq.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32) nounwind readnone
diff --git a/test/CodeGen/X86/2009-07-17-StackColoringBug.ll b/test/CodeGen/X86/2009-07-17-StackColoringBug.ll
new file mode 100644
index 0000000..3e5bd34
--- /dev/null
+++ b/test/CodeGen/X86/2009-07-17-StackColoringBug.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu -disable-fp-elim -color-ss-with-regs | not grep dil
+; PR4552
+
+target triple = "i386-pc-linux-gnu"
+@g_8 = internal global i32 0 ; <i32*> [#uses=1]
+@g_72 = internal global i32 0 ; <i32*> [#uses=1]
[email protected] = appending global [1 x i8*] [i8* bitcast (i32 (i32, i8, i8)* @uint84 to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define i32 @uint84(i32 %p_15, i8 signext %p_17, i8 signext %p_19) nounwind {
+entry:
+ %g_72.promoted = load i32* @g_72 ; <i32> [#uses=1]
+ %g_8.promoted = load i32* @g_8 ; <i32> [#uses=1]
+ br label %bb
+
+bb: ; preds = %func_40.exit, %entry
+ %g_8.tmp.1 = phi i32 [ %g_8.promoted, %entry ], [ %g_8.tmp.0, %func_40.exit ] ; <i32> [#uses=3]
+ %g_72.tmp.1 = phi i32 [ %g_72.promoted, %entry ], [ %g_72.tmp.0, %func_40.exit ] ; <i32> [#uses=3]
+ %retval12.i4.i.i = trunc i32 %g_8.tmp.1 to i8 ; <i8> [#uses=2]
+ %0 = trunc i32 %g_72.tmp.1 to i8 ; <i8> [#uses=2]
+ %1 = mul i8 %retval12.i4.i.i, %0 ; <i8> [#uses=1]
+ %2 = icmp eq i8 %1, 0 ; <i1> [#uses=1]
+ br i1 %2, label %bb2.i.i, label %bb.i.i
+
+bb.i.i: ; preds = %bb
+ %3 = sext i8 %0 to i32 ; <i32> [#uses=1]
+ %4 = and i32 %3, 50295 ; <i32> [#uses=1]
+ %5 = icmp eq i32 %4, 0 ; <i1> [#uses=1]
+ br i1 %5, label %bb2.i.i, label %func_55.exit.i
+
+bb2.i.i: ; preds = %bb.i.i, %bb
+ br label %func_55.exit.i
+
+func_55.exit.i: ; preds = %bb2.i.i, %bb.i.i
+ %g_72.tmp.2 = phi i32 [ 1, %bb2.i.i ], [ %g_72.tmp.1, %bb.i.i ] ; <i32> [#uses=1]
+ %6 = phi i32 [ 1, %bb2.i.i ], [ %g_72.tmp.1, %bb.i.i ] ; <i32> [#uses=1]
+ %7 = trunc i32 %6 to i8 ; <i8> [#uses=2]
+ %8 = mul i8 %7, %retval12.i4.i.i ; <i8> [#uses=1]
+ %9 = icmp eq i8 %8, 0 ; <i1> [#uses=1]
+ br i1 %9, label %bb2.i4.i, label %bb.i3.i
+
+bb.i3.i: ; preds = %func_55.exit.i
+ %10 = sext i8 %7 to i32 ; <i32> [#uses=1]
+ %11 = and i32 %10, 50295 ; <i32> [#uses=1]
+ %12 = icmp eq i32 %11, 0 ; <i1> [#uses=1]
+ br i1 %12, label %bb2.i4.i, label %func_40.exit
+
+bb2.i4.i: ; preds = %bb.i3.i, %func_55.exit.i
+ br label %func_40.exit
+
+func_40.exit: ; preds = %bb2.i4.i, %bb.i3.i
+ %g_72.tmp.0 = phi i32 [ 1, %bb2.i4.i ], [ %g_72.tmp.2, %bb.i3.i ] ; <i32> [#uses=1]
+ %phitmp = icmp sgt i32 %g_8.tmp.1, 0 ; <i1> [#uses=1]
+ %g_8.tmp.0 = select i1 %phitmp, i32 %g_8.tmp.1, i32 1 ; <i32> [#uses=1]
+ br label %bb
+}
diff --git a/test/CodeGen/X86/2009-07-19-AsmExtraOperands.ll b/test/CodeGen/X86/2009-07-19-AsmExtraOperands.ll
new file mode 100644
index 0000000..a0095ab2
--- /dev/null
+++ b/test/CodeGen/X86/2009-07-19-AsmExtraOperands.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86-64
+; PR4583
+
+define i32 @atomic_cmpset_long(i64* %dst, i64 %exp, i64 %src) nounwind ssp noredzone noimplicitfloat {
+entry:
+ %0 = call i8 asm sideeffect "\09lock ; \09\09\09cmpxchgq $2,$1 ;\09 sete\09$0 ;\09\091:\09\09\09\09# atomic_cmpset_long", "={ax},=*m,r,{ax},*m,~{memory},~{dirflag},~{fpsr},~{flags}"(i64* undef, i64 undef, i64 undef, i64* undef) nounwind ; <i8> [#uses=0]
+ br label %1
+
+; <label>:1 ; preds = %entry
+ ret i32 undef
+}
diff --git a/test/CodeGen/X86/2009-07-20-CoalescerBug.ll b/test/CodeGen/X86/2009-07-20-CoalescerBug.ll
new file mode 100644
index 0000000..e99edd6
--- /dev/null
+++ b/test/CodeGen/X86/2009-07-20-CoalescerBug.ll
@@ -0,0 +1,165 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10
+; PR4587
+; rdar://7072590
+
+ %struct.re_pattern_buffer = type <{ i8*, i64, i64, i64, i8*, i64, i64, i8, i8, i8, i8, i8, i8, i8, i8 }>
+
+define fastcc i32 @regex_compile(i8* %pattern, i64 %size, i64 %syntax, %struct.re_pattern_buffer* nocapture %bufp) nounwind ssp {
+entry:
+ br i1 undef, label %return, label %if.end
+
+if.end: ; preds = %entry
+ %tmp35 = getelementptr %struct.re_pattern_buffer* %bufp, i64 0, i32 3 ; <i64*> [#uses=1]
+ store i64 %syntax, i64* %tmp35
+ store i32 undef, i32* undef
+ br i1 undef, label %if.then66, label %if.end102
+
+if.then66: ; preds = %if.end
+ br i1 false, label %if.else, label %if.then70
+
+if.then70: ; preds = %if.then66
+ %call74 = call i8* @xrealloc(i8* undef, i64 32) nounwind ssp ; <i8*> [#uses=0]
+ unreachable
+
+if.else: ; preds = %if.then66
+ br i1 false, label %do.body86, label %if.end99
+
+do.body86: ; preds = %if.else
+ br i1 false, label %do.end, label %if.then90
+
+if.then90: ; preds = %do.body86
+ unreachable
+
+do.end: ; preds = %do.body86
+ ret i32 12
+
+if.end99: ; preds = %if.else
+ br label %if.end102
+
+if.end102: ; preds = %if.end99, %if.end
+ br label %while.body
+
+while.body: ; preds = %if.end1126, %sw.bb532, %while.body, %if.end102
+ %laststart.2 = phi i8* [ null, %if.end102 ], [ %laststart.7.ph, %if.end1126 ], [ %laststart.2, %sw.bb532 ], [ %laststart.2, %while.body ] ; <i8*> [#uses=6]
+ %b.1 = phi i8* [ undef, %if.end102 ], [ %ctg29688, %if.end1126 ], [ %b.1, %sw.bb532 ], [ %b.1, %while.body ] ; <i8*> [#uses=5]
+ br i1 undef, label %while.body, label %if.end127
+
+if.end127: ; preds = %while.body
+ switch i32 undef, label %sw.bb532 [
+ i32 123, label %handle_interval
+ i32 92, label %do.body3527
+ ]
+
+sw.bb532: ; preds = %if.end127
+ br i1 undef, label %while.body, label %if.end808
+
+if.end808: ; preds = %sw.bb532
+ br i1 undef, label %while.cond1267.preheader, label %if.then811
+
+while.cond1267.preheader: ; preds = %if.end808
+ br i1 false, label %return, label %if.end1294
+
+if.then811: ; preds = %if.end808
+ %call817 = call fastcc i8* @skip_one_char(i8* %laststart.2) ssp ; <i8*> [#uses=0]
+ br i1 undef, label %cond.end834, label %lor.lhs.false827
+
+lor.lhs.false827: ; preds = %if.then811
+ br label %cond.end834
+
+cond.end834: ; preds = %lor.lhs.false827, %if.then811
+ br i1 undef, label %land.lhs.true838, label %while.cond979.preheader
+
+land.lhs.true838: ; preds = %cond.end834
+ br i1 undef, label %if.then842, label %while.cond979.preheader
+
+if.then842: ; preds = %land.lhs.true838
+ %conv851 = trunc i64 undef to i32 ; <i32> [#uses=1]
+ br label %while.cond979.preheader
+
+while.cond979.preheader: ; preds = %if.then842, %land.lhs.true838, %cond.end834
+ %startoffset.0.ph = phi i32 [ 0, %cond.end834 ], [ 0, %land.lhs.true838 ], [ %conv851, %if.then842 ] ; <i32> [#uses=2]
+ %laststart.7.ph = phi i8* [ %laststart.2, %cond.end834 ], [ %laststart.2, %land.lhs.true838 ], [ %laststart.2, %if.then842 ] ; <i8*> [#uses=3]
+ %b.4.ph = phi i8* [ %b.1, %cond.end834 ], [ %b.1, %land.lhs.true838 ], [ %b.1, %if.then842 ] ; <i8*> [#uses=3]
+ %ctg29688 = getelementptr i8* %b.4.ph, i64 6 ; <i8*> [#uses=1]
+ br label %while.cond979
+
+while.cond979: ; preds = %if.end1006, %while.cond979.preheader
+ %cmp991 = icmp ugt i64 undef, 0 ; <i1> [#uses=1]
+ br i1 %cmp991, label %do.body994, label %while.end1088
+
+do.body994: ; preds = %while.cond979
+ br i1 undef, label %return, label %if.end1006
+
+if.end1006: ; preds = %do.body994
+ %cmp1014 = icmp ugt i64 undef, 32768 ; <i1> [#uses=1]
+ %storemerge10953 = select i1 %cmp1014, i64 32768, i64 undef ; <i64> [#uses=1]
+ store i64 %storemerge10953, i64* undef
+ br i1 false, label %return, label %while.cond979
+
+while.end1088: ; preds = %while.cond979
+ br i1 undef, label %if.then1091, label %if.else1101
+
+if.then1091: ; preds = %while.end1088
+ store i8 undef, i8* undef
+ %idx.ext1132.pre = zext i32 %startoffset.0.ph to i64 ; <i64> [#uses=1]
+ %add.ptr1133.pre = getelementptr i8* %laststart.7.ph, i64 %idx.ext1132.pre ; <i8*> [#uses=1]
+ %sub.ptr.lhs.cast1135.pre = ptrtoint i8* %add.ptr1133.pre to i64 ; <i64> [#uses=1]
+ br label %if.end1126
+
+if.else1101: ; preds = %while.end1088
+ %cond1109 = select i1 undef, i32 18, i32 14 ; <i32> [#uses=1]
+ %idx.ext1112 = zext i32 %startoffset.0.ph to i64 ; <i64> [#uses=1]
+ %add.ptr1113 = getelementptr i8* %laststart.7.ph, i64 %idx.ext1112 ; <i8*> [#uses=2]
+ %sub.ptr.rhs.cast1121 = ptrtoint i8* %add.ptr1113 to i64 ; <i64> [#uses=1]
+ call fastcc void @insert_op1(i32 %cond1109, i8* %add.ptr1113, i32 undef, i8* %b.4.ph) ssp
+ br label %if.end1126
+
+if.end1126: ; preds = %if.else1101, %if.then1091
+ %sub.ptr.lhs.cast1135.pre-phi = phi i64 [ %sub.ptr.rhs.cast1121, %if.else1101 ], [ %sub.ptr.lhs.cast1135.pre, %if.then1091 ] ; <i64> [#uses=1]
+ %add.ptr1128 = getelementptr i8* %b.4.ph, i64 3 ; <i8*> [#uses=1]
+ %sub.ptr.rhs.cast1136 = ptrtoint i8* %add.ptr1128 to i64 ; <i64> [#uses=1]
+ %sub.ptr.sub1137 = sub i64 %sub.ptr.lhs.cast1135.pre-phi, %sub.ptr.rhs.cast1136 ; <i64> [#uses=1]
+ %sub.ptr.sub11378527 = trunc i64 %sub.ptr.sub1137 to i32 ; <i32> [#uses=1]
+ %conv1139 = add i32 %sub.ptr.sub11378527, -3 ; <i32> [#uses=1]
+ store i8 undef, i8* undef
+ %shr10.i8599 = lshr i32 %conv1139, 8 ; <i32> [#uses=1]
+ %conv6.i8600 = trunc i32 %shr10.i8599 to i8 ; <i8> [#uses=1]
+ store i8 %conv6.i8600, i8* undef
+ br label %while.body
+
+if.end1294: ; preds = %while.cond1267.preheader
+ ret i32 12
+
+do.body3527: ; preds = %if.end127
+ br i1 undef, label %do.end3536, label %if.then3531
+
+if.then3531: ; preds = %do.body3527
+ unreachable
+
+do.end3536: ; preds = %do.body3527
+ ret i32 5
+
+handle_interval: ; preds = %if.end127
+ br i1 undef, label %do.body4547, label %cond.false4583
+
+do.body4547: ; preds = %handle_interval
+ br i1 undef, label %do.end4556, label %if.then4551
+
+if.then4551: ; preds = %do.body4547
+ unreachable
+
+do.end4556: ; preds = %do.body4547
+ ret i32 9
+
+cond.false4583: ; preds = %handle_interval
+ unreachable
+
+return: ; preds = %if.end1006, %do.body994, %while.cond1267.preheader, %entry
+ ret i32 undef
+}
+
+declare i8* @xrealloc(i8*, i64) ssp
+
+declare fastcc i8* @skip_one_char(i8*) nounwind readonly ssp
+
+declare fastcc void @insert_op1(i32, i8*, i32, i8*) nounwind ssp
diff --git a/test/CodeGen/X86/2009-07-20-DAGCombineBug.ll b/test/CodeGen/X86/2009-07-20-DAGCombineBug.ll
new file mode 100644
index 0000000..e83b3a7
--- /dev/null
+++ b/test/CodeGen/X86/2009-07-20-DAGCombineBug.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=x86
+
+@bsBuff = internal global i32 0 ; <i32*> [#uses=1]
[email protected] = appending global [1 x i8*] [i8* bitcast (i32 ()* @bsGetUInt32 to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define fastcc i32 @bsGetUInt32() nounwind ssp {
+entry:
+ %bsBuff.promoted44 = load i32* @bsBuff ; <i32> [#uses=1]
+ %0 = add i32 0, -8 ; <i32> [#uses=1]
+ %1 = lshr i32 %bsBuff.promoted44, %0 ; <i32> [#uses=1]
+ %2 = shl i32 %1, 8 ; <i32> [#uses=1]
+ br label %bb3.i17
+
+bb3.i9: ; preds = %bb3.i17
+ br i1 false, label %bb2.i16, label %bb1.i15
+
+bb1.i15: ; preds = %bb3.i9
+ unreachable
+
+bb2.i16: ; preds = %bb3.i9
+ br label %bb3.i17
+
+bb3.i17: ; preds = %bb2.i16, %entry
+ br i1 false, label %bb3.i9, label %bsR.exit18
+
+bsR.exit18: ; preds = %bb3.i17
+ %3 = or i32 0, %2 ; <i32> [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll b/test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll
new file mode 100644
index 0000000..b9b09a3
--- /dev/null
+++ b/test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86-64
+; PR4669
+declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32)
+
+define <1 x i64> @test(i64 %t) {
+entry:
+ %t1 = insertelement <1 x i64> undef, i64 %t, i32 0
+ %t2 = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %t1, i32 48)
+ ret <1 x i64> %t2
+}
diff --git a/test/CodeGen/X86/2009-08-06-branchfolder-crash.ll b/test/CodeGen/X86/2009-08-06-branchfolder-crash.ll
new file mode 100644
index 0000000..b329c91
--- /dev/null
+++ b/test/CodeGen/X86/2009-08-06-branchfolder-crash.ll
@@ -0,0 +1,142 @@
+; RUN: llc < %s -O3
+; PR4626
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+@g_3 = common global i8 0, align 1 ; <i8*> [#uses=2]
+
+define signext i8 @safe_mul_func_int16_t_s_s(i32 %_si1, i8 signext %_si2) nounwind readnone {
+entry:
+ %tobool = icmp eq i32 %_si1, 0 ; <i1> [#uses=1]
+ %cmp = icmp sgt i8 %_si2, 0 ; <i1> [#uses=2]
+ %or.cond = or i1 %cmp, %tobool ; <i1> [#uses=1]
+ br i1 %or.cond, label %lor.rhs, label %land.lhs.true3
+
+land.lhs.true3: ; preds = %entry
+ %conv5 = sext i8 %_si2 to i32 ; <i32> [#uses=1]
+ %cmp7 = icmp slt i32 %conv5, %_si1 ; <i1> [#uses=1]
+ br i1 %cmp7, label %cond.end, label %lor.rhs
+
+lor.rhs: ; preds = %land.lhs.true3, %entry
+ %cmp10.not = icmp slt i32 %_si1, 1 ; <i1> [#uses=1]
+ %or.cond23 = and i1 %cmp, %cmp10.not ; <i1> [#uses=1]
+ br i1 %or.cond23, label %lor.end, label %cond.false
+
+lor.end: ; preds = %lor.rhs
+ %tobool19 = icmp ne i8 %_si2, 0 ; <i1> [#uses=2]
+ %lor.ext = zext i1 %tobool19 to i32 ; <i32> [#uses=1]
+ br i1 %tobool19, label %cond.end, label %cond.false
+
+cond.false: ; preds = %lor.end, %lor.rhs
+ %conv21 = sext i8 %_si2 to i32 ; <i32> [#uses=1]
+ br label %cond.end
+
+cond.end: ; preds = %cond.false, %lor.end, %land.lhs.true3
+ %cond = phi i32 [ %conv21, %cond.false ], [ 1, %land.lhs.true3 ], [ %lor.ext, %lor.end ] ; <i32> [#uses=1]
+ %conv22 = trunc i32 %cond to i8 ; <i8> [#uses=1]
+ ret i8 %conv22
+}
+
+define i32 @func_34(i8 signext %p_35) nounwind readonly {
+entry:
+ %tobool = icmp eq i8 %p_35, 0 ; <i1> [#uses=1]
+ br i1 %tobool, label %lor.lhs.false, label %if.then
+
+lor.lhs.false: ; preds = %entry
+ %tmp1 = load i8* @g_3 ; <i8> [#uses=1]
+ %tobool3 = icmp eq i8 %tmp1, 0 ; <i1> [#uses=1]
+ br i1 %tobool3, label %return, label %if.then
+
+if.then: ; preds = %lor.lhs.false, %entry
+ %tmp4 = load i8* @g_3 ; <i8> [#uses=1]
+ %conv5 = sext i8 %tmp4 to i32 ; <i32> [#uses=1]
+ ret i32 %conv5
+
+return: ; preds = %lor.lhs.false
+ ret i32 0
+}
+
+define void @foo(i32 %p_5) noreturn nounwind {
+entry:
+ %cmp = icmp sgt i32 %p_5, 0 ; <i1> [#uses=2]
+ %call = tail call i32 @safe() nounwind ; <i32> [#uses=1]
+ %conv1 = trunc i32 %call to i8 ; <i8> [#uses=3]
+ %tobool.i = xor i1 %cmp, true ; <i1> [#uses=3]
+ %cmp.i = icmp sgt i8 %conv1, 0 ; <i1> [#uses=3]
+ %or.cond.i = or i1 %cmp.i, %tobool.i ; <i1> [#uses=1]
+ br i1 %or.cond.i, label %lor.rhs.i, label %land.lhs.true3.i
+
+land.lhs.true3.i: ; preds = %entry
+ %xor = zext i1 %cmp to i32 ; <i32> [#uses=1]
+ %conv5.i = sext i8 %conv1 to i32 ; <i32> [#uses=1]
+ %cmp7.i = icmp slt i32 %conv5.i, %xor ; <i1> [#uses=1]
+ %cmp7.i.not = xor i1 %cmp7.i, true ; <i1> [#uses=1]
+ %or.cond23.i = and i1 %cmp.i, %tobool.i ; <i1> [#uses=1]
+ %or.cond = and i1 %cmp7.i.not, %or.cond23.i ; <i1> [#uses=1]
+ br i1 %or.cond, label %lor.end.i, label %for.inc
+
+lor.rhs.i: ; preds = %entry
+ %or.cond23.i.old = and i1 %cmp.i, %tobool.i ; <i1> [#uses=1]
+ br i1 %or.cond23.i.old, label %lor.end.i, label %for.inc
+
+lor.end.i: ; preds = %lor.rhs.i, %land.lhs.true3.i
+ %tobool19.i = icmp eq i8 %conv1, 0 ; <i1> [#uses=0]
+ br label %for.inc
+
+for.inc: ; preds = %for.inc, %lor.end.i, %lor.rhs.i, %land.lhs.true3.i
+ br label %for.inc
+}
+
+declare i32 @safe()
+
+define i32 @func_35(i8 signext %p_35) nounwind readonly {
+entry:
+ %tobool = icmp eq i8 %p_35, 0 ; <i1> [#uses=1]
+ br i1 %tobool, label %lor.lhs.false, label %if.then
+
+lor.lhs.false: ; preds = %entry
+ %tmp1 = load i8* @g_3 ; <i8> [#uses=1]
+ %tobool3 = icmp eq i8 %tmp1, 0 ; <i1> [#uses=1]
+ br i1 %tobool3, label %return, label %if.then
+
+if.then: ; preds = %lor.lhs.false, %entry
+ %tmp4 = load i8* @g_3 ; <i8> [#uses=1]
+ %conv5 = sext i8 %tmp4 to i32 ; <i32> [#uses=1]
+ ret i32 %conv5
+
+return: ; preds = %lor.lhs.false
+ ret i32 0
+}
+
+define void @bar(i32 %p_5) noreturn nounwind {
+entry:
+ %cmp = icmp sgt i32 %p_5, 0 ; <i1> [#uses=2]
+ %call = tail call i32 @safe() nounwind ; <i32> [#uses=1]
+ %conv1 = trunc i32 %call to i8 ; <i8> [#uses=3]
+ %tobool.i = xor i1 %cmp, true ; <i1> [#uses=3]
+ %cmp.i = icmp sgt i8 %conv1, 0 ; <i1> [#uses=3]
+ %or.cond.i = or i1 %cmp.i, %tobool.i ; <i1> [#uses=1]
+ br i1 %or.cond.i, label %lor.rhs.i, label %land.lhs.true3.i
+
+land.lhs.true3.i: ; preds = %entry
+ %xor = zext i1 %cmp to i32 ; <i32> [#uses=1]
+ %conv5.i = sext i8 %conv1 to i32 ; <i32> [#uses=1]
+ %cmp7.i = icmp slt i32 %conv5.i, %xor ; <i1> [#uses=1]
+ %cmp7.i.not = xor i1 %cmp7.i, true ; <i1> [#uses=1]
+ %or.cond23.i = and i1 %cmp.i, %tobool.i ; <i1> [#uses=1]
+ %or.cond = and i1 %cmp7.i.not, %or.cond23.i ; <i1> [#uses=1]
+ br i1 %or.cond, label %lor.end.i, label %for.inc
+
+lor.rhs.i: ; preds = %entry
+ %or.cond23.i.old = and i1 %cmp.i, %tobool.i ; <i1> [#uses=1]
+ br i1 %or.cond23.i.old, label %lor.end.i, label %for.inc
+
+lor.end.i: ; preds = %lor.rhs.i, %land.lhs.true3.i
+ %tobool19.i = icmp eq i8 %conv1, 0 ; <i1> [#uses=0]
+ br label %for.inc
+
+for.inc: ; preds = %for.inc, %lor.end.i, %lor.rhs.i, %land.lhs.true3.i
+ br label %for.inc
+}
+
+declare i32 @safe()
diff --git a/test/CodeGen/X86/2009-08-06-inlineasm.ll b/test/CodeGen/X86/2009-08-06-inlineasm.ll
new file mode 100644
index 0000000..cc2f3d8
--- /dev/null
+++ b/test/CodeGen/X86/2009-08-06-inlineasm.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s
+; PR4668
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+
+define i32 @x(i32 %qscale) nounwind {
+entry:
+ %temp_block = alloca [64 x i16], align 16 ; <[64 x i16]*> [#uses=0]
+ %tmp = call i32 asm sideeffect "xor %edx, %edx", "={dx},~{dirflag},~{fpsr},~{flags}"() nounwind ; <i32> [#uses=1]
+ br i1 undef, label %if.end78, label %if.then28
+
+if.then28: ; preds = %entry
+ br label %if.end78
+
+if.end78: ; preds = %if.then28, %entry
+ %level.1 = phi i32 [ %tmp, %if.then28 ], [ 0, %entry ] ; <i32> [#uses=1]
+ %add.ptr1 = getelementptr [64 x i16]* null, i32 0, i32 %qscale ; <i16*> [#uses=1]
+ %add.ptr2 = getelementptr [64 x i16]* null, i32 1, i32 %qscale ; <i16*> [#uses=1]
+ %add.ptr3 = getelementptr [64 x i16]* null, i32 2, i32 %qscale ; <i16*> [#uses=1]
+ %add.ptr4 = getelementptr [64 x i16]* null, i32 3, i32 %qscale ; <i16*> [#uses=1]
+ %add.ptr5 = getelementptr [64 x i16]* null, i32 4, i32 %qscale ; <i16*> [#uses=1]
+ %add.ptr6 = getelementptr [64 x i16]* null, i32 5, i32 %qscale ; <i16*> [#uses=1]
+ %tmp1 = call i32 asm sideeffect "nop", "={ax},r,r,r,r,r,0,~{dirflag},~{fpsr},~{flags}"(i16* %add.ptr6, i16* %add.ptr5, i16* %add.ptr4, i16* %add.ptr3, i16* %add.ptr2, i16* %add.ptr1) nounwind ; <i32> [#uses=0]
+ ret i32 %level.1
+}
diff --git a/test/CodeGen/X86/2009-08-08-CastError.ll b/test/CodeGen/X86/2009-08-08-CastError.ll
new file mode 100644
index 0000000..9456d91
--- /dev/null
+++ b/test/CodeGen/X86/2009-08-08-CastError.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=x86_64-mingw64 | grep movabsq
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+
+define <4 x float> @RecursiveTestFunc1(i8*) {
+EntryBlock:
+ %1 = call <4 x float> inttoptr (i64 5367207198 to <4 x float> (i8*, float, float, float, float)*)(i8* %0, float 8.000000e+00, float 5.000000e+00, float 3.000000e+00, float 4.000000e+00) ; <<4 x float>> [#uses=1]
+ ret <4 x float> %1
+}
diff --git a/test/CodeGen/X86/2009-08-12-badswitch.ll b/test/CodeGen/X86/2009-08-12-badswitch.ll
new file mode 100644
index 0000000..a94fce0
--- /dev/null
+++ b/test/CodeGen/X86/2009-08-12-badswitch.ll
@@ -0,0 +1,176 @@
+; RUN: llc < %s | grep LJT
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin10"
+
+declare void @f1() nounwind readnone
+declare void @f2() nounwind readnone
+declare void @f3() nounwind readnone
+declare void @f4() nounwind readnone
+declare void @f5() nounwind readnone
+declare void @f6() nounwind readnone
+declare void @f7() nounwind readnone
+declare void @f8() nounwind readnone
+declare void @f9() nounwind readnone
+declare void @f10() nounwind readnone
+declare void @f11() nounwind readnone
+declare void @f12() nounwind readnone
+declare void @f13() nounwind readnone
+declare void @f14() nounwind readnone
+declare void @f15() nounwind readnone
+declare void @f16() nounwind readnone
+declare void @f17() nounwind readnone
+declare void @f18() nounwind readnone
+declare void @f19() nounwind readnone
+declare void @f20() nounwind readnone
+declare void @f21() nounwind readnone
+declare void @f22() nounwind readnone
+declare void @f23() nounwind readnone
+declare void @f24() nounwind readnone
+declare void @f25() nounwind readnone
+declare void @f26() nounwind readnone
+
+define internal fastcc i32 @foo(i64 %bar) nounwind ssp {
+entry:
+ br label %bb49
+
+bb49:
+ switch i64 %bar, label %RETURN [
+ i64 2, label %RRETURN_2
+ i64 3, label %RRETURN_6
+ i64 4, label %RRETURN_7
+ i64 5, label %RRETURN_14
+ i64 6, label %RRETURN_15
+ i64 7, label %RRETURN_16
+ i64 8, label %RRETURN_17
+ i64 9, label %RRETURN_18
+ i64 10, label %RRETURN_19
+ i64 11, label %RRETURN_20
+ i64 12, label %RRETURN_21
+ i64 13, label %RRETURN_22
+ i64 14, label %RRETURN_24
+ i64 15, label %RRETURN_26
+ i64 16, label %RRETURN_27
+ i64 17, label %RRETURN_28
+ i64 18, label %RRETURN_29
+ i64 19, label %RRETURN_30
+ i64 20, label %RRETURN_31
+ i64 21, label %RRETURN_38
+ i64 22, label %RRETURN_40
+ i64 23, label %RRETURN_42
+ i64 24, label %RRETURN_44
+ i64 25, label %RRETURN_48
+ i64 26, label %RRETURN_52
+ i64 27, label %RRETURN_1
+ ]
+
+RETURN:
+ call void @f1()
+ br label %EXIT
+
+RRETURN_2: ; preds = %bb49
+ call void @f2()
+ br label %EXIT
+
+RRETURN_6: ; preds = %bb49
+ call void @f2()
+ br label %EXIT
+
+RRETURN_7: ; preds = %bb49
+ call void @f3()
+ br label %EXIT
+
+RRETURN_14: ; preds = %bb49
+ call void @f4()
+ br label %EXIT
+
+RRETURN_15: ; preds = %bb49
+ call void @f5()
+ br label %EXIT
+
+RRETURN_16: ; preds = %bb49
+ call void @f6()
+ br label %EXIT
+
+RRETURN_17: ; preds = %bb49
+ call void @f7()
+ br label %EXIT
+
+RRETURN_18: ; preds = %bb49
+ call void @f8()
+ br label %EXIT
+
+RRETURN_19: ; preds = %bb49
+ call void @f9()
+ br label %EXIT
+
+RRETURN_20: ; preds = %bb49
+ call void @f10()
+ br label %EXIT
+
+RRETURN_21: ; preds = %bb49
+ call void @f11()
+ br label %EXIT
+
+RRETURN_22: ; preds = %bb49
+ call void @f12()
+ br label %EXIT
+
+RRETURN_24: ; preds = %bb49
+ call void @f13()
+ br label %EXIT
+
+RRETURN_26: ; preds = %bb49
+ call void @f14()
+ br label %EXIT
+
+RRETURN_27: ; preds = %bb49
+ call void @f15()
+ br label %EXIT
+
+RRETURN_28: ; preds = %bb49
+ call void @f16()
+ br label %EXIT
+
+RRETURN_29: ; preds = %bb49
+ call void @f17()
+ br label %EXIT
+
+RRETURN_30: ; preds = %bb49
+ call void @f18()
+ br label %EXIT
+
+RRETURN_31: ; preds = %bb49
+ call void @f19()
+ br label %EXIT
+
+RRETURN_38: ; preds = %bb49
+ call void @f20()
+ br label %EXIT
+
+RRETURN_40: ; preds = %bb49
+ call void @f21()
+ br label %EXIT
+
+RRETURN_42: ; preds = %bb49
+ call void @f22()
+ br label %EXIT
+
+RRETURN_44: ; preds = %bb49
+ call void @f23()
+ br label %EXIT
+
+RRETURN_48: ; preds = %bb49
+ call void @f24()
+ br label %EXIT
+
+RRETURN_52: ; preds = %bb49
+ call void @f25()
+ br label %EXIT
+
+RRETURN_1: ; preds = %bb49
+ call void @f26()
+ br label %EXIT
+
+EXIT:
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2009-08-14-Win64MemoryIndirectArg.ll b/test/CodeGen/X86/2009-08-14-Win64MemoryIndirectArg.ll
new file mode 100644
index 0000000..6b0d6d9
--- /dev/null
+++ b/test/CodeGen/X86/2009-08-14-Win64MemoryIndirectArg.ll
@@ -0,0 +1,57 @@
+; RUN: llc < %s
+target triple = "x86_64-mingw"
+
+; ModuleID = 'mm.bc'
+ type opaque ; type %0
+ type opaque ; type %1
+
+define internal fastcc float @computeMipmappingRho(%0* %shaderExecutionStatePtr, i32 %index, <4 x float> %texCoord, <4 x float> %texCoordDX, <4 x float> %texCoordDY) readonly {
+indexCheckBlock:
+ %indexCmp = icmp ugt i32 %index, 16 ; <i1> [#uses=1]
+ br i1 %indexCmp, label %zeroReturnBlock, label %primitiveTextureFetchBlock
+
+primitiveTextureFetchBlock: ; preds = %indexCheckBlock
+ %pointerArithmeticTmp = bitcast %0* %shaderExecutionStatePtr to i8* ; <i8*> [#uses=1]
+ %pointerArithmeticTmp1 = getelementptr i8* %pointerArithmeticTmp, i64 1808 ; <i8*> [#uses=1]
+ %pointerArithmeticTmp2 = bitcast i8* %pointerArithmeticTmp1 to %1** ; <%1**> [#uses=1]
+ %primitivePtr = load %1** %pointerArithmeticTmp2 ; <%1*> [#uses=1]
+ %pointerArithmeticTmp3 = bitcast %1* %primitivePtr to i8* ; <i8*> [#uses=1]
+ %pointerArithmeticTmp4 = getelementptr i8* %pointerArithmeticTmp3, i64 19408 ; <i8*> [#uses=1]
+ %pointerArithmeticTmp5 = bitcast i8* %pointerArithmeticTmp4 to %1** ; <%1**> [#uses=1]
+ %primitiveTexturePtr = getelementptr %1** %pointerArithmeticTmp5, i32 %index ; <%1**> [#uses=1]
+ %primitiveTexturePtr6 = load %1** %primitiveTexturePtr ; <%1*> [#uses=2]
+ br label %textureCheckBlock
+
+textureCheckBlock: ; preds = %primitiveTextureFetchBlock
+ %texturePtrInt = ptrtoint %1* %primitiveTexturePtr6 to i64 ; <i64> [#uses=1]
+ %testTextureNULL = icmp eq i64 %texturePtrInt, 0 ; <i1> [#uses=1]
+ br i1 %testTextureNULL, label %zeroReturnBlock, label %rhoCalculateBlock
+
+rhoCalculateBlock: ; preds = %textureCheckBlock
+ %pointerArithmeticTmp7 = bitcast %1* %primitiveTexturePtr6 to i8* ; <i8*> [#uses=1]
+ %pointerArithmeticTmp8 = getelementptr i8* %pointerArithmeticTmp7, i64 640 ; <i8*> [#uses=1]
+ %pointerArithmeticTmp9 = bitcast i8* %pointerArithmeticTmp8 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %dimensionsPtr = load <4 x float>* %pointerArithmeticTmp9, align 1 ; <<4 x float>> [#uses=2]
+ %texDiffDX = fsub <4 x float> %texCoordDX, %texCoord ; <<4 x float>> [#uses=1]
+ %texDiffDY = fsub <4 x float> %texCoordDY, %texCoord ; <<4 x float>> [#uses=1]
+ %ddx = fmul <4 x float> %texDiffDX, %dimensionsPtr ; <<4 x float>> [#uses=2]
+ %ddx10 = fmul <4 x float> %texDiffDY, %dimensionsPtr ; <<4 x float>> [#uses=2]
+ %ddxSquared = fmul <4 x float> %ddx, %ddx ; <<4 x float>> [#uses=3]
+ %0 = shufflevector <4 x float> %ddxSquared, <4 x float> %ddxSquared, <4 x i32> <i32 1, i32 0, i32 0, i32 0> ; <<4 x float>> [#uses=1]
+ %dxSquared = fadd <4 x float> %ddxSquared, %0 ; <<4 x float>> [#uses=1]
+ %1 = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %dxSquared) ; <<4 x float>> [#uses=1]
+ %ddySquared = fmul <4 x float> %ddx10, %ddx10 ; <<4 x float>> [#uses=3]
+ %2 = shufflevector <4 x float> %ddySquared, <4 x float> %ddySquared, <4 x i32> <i32 1, i32 0, i32 0, i32 0> ; <<4 x float>> [#uses=1]
+ %dySquared = fadd <4 x float> %ddySquared, %2 ; <<4 x float>> [#uses=1]
+ %3 = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %dySquared) ; <<4 x float>> [#uses=1]
+ %4 = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %1, <4 x float> %3) ; <<4 x float>> [#uses=1]
+ %rho = extractelement <4 x float> %4, i32 0 ; <float> [#uses=1]
+ ret float %rho
+
+zeroReturnBlock: ; preds = %textureCheckBlock, %indexCheckBlock
+ ret float 0.000000e+00
+}
+
+declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
+
+declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind readnone
diff --git a/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll b/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll
new file mode 100644
index 0000000..5f6cf3b
--- /dev/null
+++ b/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-pc-linux | FileCheck %s
+
+@a = external global i96, align 4
+@b = external global i64, align 8
+
+define void @c() nounwind {
+; CHECK: movl a+8, %eax
+ %srcval1 = load i96* @a, align 4
+ %sroa.store.elt2 = lshr i96 %srcval1, 64
+ %tmp = trunc i96 %sroa.store.elt2 to i64
+; CHECK: movl %eax, b
+; CHECK: movl $0, b+4
+ store i64 %tmp, i64* @b, align 8
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-08-23-SubRegReuseUndo.ll b/test/CodeGen/X86/2009-08-23-SubRegReuseUndo.ll
new file mode 100644
index 0000000..790fd88
--- /dev/null
+++ b/test/CodeGen/X86/2009-08-23-SubRegReuseUndo.ll
@@ -0,0 +1,69 @@
+; RUN: llc < %s -march=x86
+; PR4753
+
+; This function has a sub-register reuse undone.
+
+@uint8 = external global i32 ; <i32*> [#uses=3]
+
+declare signext i8 @foo(i32, i8 signext) nounwind readnone
+
+declare signext i8 @bar(i32, i8 signext) nounwind readnone
+
+define i32 @uint80(i8 signext %p_52) nounwind {
+entry:
+ %0 = sext i8 %p_52 to i16 ; <i16> [#uses=1]
+ %1 = tail call i32 @func_24(i16 zeroext %0, i8 signext ptrtoint (i8 (i32, i8)* @foo to i8)) nounwind; <i32> [#uses=1]
+ %2 = trunc i32 %1 to i8 ; <i8> [#uses=1]
+ %3 = or i8 %2, 1 ; <i8> [#uses=1]
+ %4 = tail call i32 @safe(i32 1) nounwind ; <i32> [#uses=0]
+ %5 = tail call i32 @func_24(i16 zeroext 0, i8 signext undef) nounwind; <i32> [#uses=1]
+ %6 = trunc i32 %5 to i8 ; <i8> [#uses=1]
+ %7 = xor i8 %3, %p_52 ; <i8> [#uses=1]
+ %8 = xor i8 %7, %6 ; <i8> [#uses=1]
+ %9 = icmp ne i8 %p_52, 0 ; <i1> [#uses=1]
+ %10 = zext i1 %9 to i8 ; <i8> [#uses=1]
+ %11 = tail call i32 @func_24(i16 zeroext ptrtoint (i8 (i32, i8)* @bar to i16), i8 signext %10) nounwind; <i32> [#uses=1]
+ %12 = tail call i32 @func_24(i16 zeroext 0, i8 signext 1) nounwind; <i32> [#uses=0]
+ br i1 undef, label %bb2, label %bb
+
+bb: ; preds = %entry
+ br i1 undef, label %bb2, label %bb3
+
+bb2: ; preds = %bb, %entry
+ br label %bb3
+
+bb3: ; preds = %bb2, %bb
+ %iftmp.2.0 = phi i32 [ 0, %bb2 ], [ 1, %bb ] ; <i32> [#uses=1]
+ %13 = icmp ne i32 %11, %iftmp.2.0 ; <i1> [#uses=1]
+ %14 = tail call i32 @safe(i32 -2) nounwind ; <i32> [#uses=0]
+ %15 = zext i1 %13 to i8 ; <i8> [#uses=1]
+ %16 = tail call signext i8 @func_53(i8 signext undef, i8 signext 1, i8 signext %15, i8 signext %8) nounwind; <i8> [#uses=0]
+ br i1 undef, label %bb5, label %bb4
+
+bb4: ; preds = %bb3
+ %17 = volatile load i32* @uint8, align 4 ; <i32> [#uses=0]
+ br label %bb5
+
+bb5: ; preds = %bb4, %bb3
+ %18 = volatile load i32* @uint8, align 4 ; <i32> [#uses=0]
+ %19 = sext i8 undef to i16 ; <i16> [#uses=1]
+ %20 = tail call i32 @func_24(i16 zeroext %19, i8 signext 1) nounwind; <i32> [#uses=0]
+ br i1 undef, label %return, label %bb6.preheader
+
+bb6.preheader: ; preds = %bb5
+ %21 = sext i8 %p_52 to i32 ; <i32> [#uses=1]
+ %22 = volatile load i32* @uint8, align 4 ; <i32> [#uses=0]
+ %23 = tail call i32 (...)* @safefuncts(i32 %21, i32 1) nounwind; <i32> [#uses=0]
+ unreachable
+
+return: ; preds = %bb5
+ ret i32 undef
+}
+
+declare i32 @func_24(i16 zeroext, i8 signext)
+
+declare i32 @safe(i32)
+
+declare signext i8 @func_53(i8 signext, i8 signext, i8 signext, i8 signext)
+
+declare i32 @safefuncts(...)
diff --git a/test/CodeGen/X86/2009-08-23-linkerprivate.ll b/test/CodeGen/X86/2009-08-23-linkerprivate.ll
new file mode 100644
index 0000000..3da8f00
--- /dev/null
+++ b/test/CodeGen/X86/2009-08-23-linkerprivate.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin | FileCheck %s
+
+; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm'
+
+@"\01l_objc_msgSend_fixup_alloc" = linker_private hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16 ; <i32*> [#uses=0]
+
+; CHECK: .globl l_objc_msgSend_fixup_alloc
+; CHECK: .weak_definition l_objc_msgSend_fixup_alloc
diff --git a/test/CodeGen/X86/2009-09-07-CoalescerBug.ll b/test/CodeGen/X86/2009-09-07-CoalescerBug.ll
new file mode 100644
index 0000000..a5b4a79
--- /dev/null
+++ b/test/CodeGen/X86/2009-09-07-CoalescerBug.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-freebsd7.2 -code-model=kernel | FileCheck %s
+; PR4689
+
+%struct.__s = type { [8 x i8] }
+%struct.pcb = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i16, i8* }
+%struct.pcpu = type { i32*, i32*, i32*, i32*, %struct.pcb*, i64, i32, i32, i32, i32 }
+
+define i64 @hammer_time(i64 %modulep, i64 %physfree) nounwind ssp noredzone noimplicitfloat {
+; CHECK: hammer_time:
+; CHECK: movq $Xrsvd, %rax
+; CHECK: movq $Xrsvd, %rsi
+; CHECK: movq $Xrsvd, %rdi
+entry:
+ br i1 undef, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ br label %for.body
+
+for.body: ; preds = %for.inc, %if.end
+ switch i32 undef, label %if.then76 [
+ i32 9, label %for.inc
+ i32 10, label %for.inc
+ i32 11, label %for.inc
+ i32 12, label %for.inc
+ ]
+
+if.then76: ; preds = %for.body
+ unreachable
+
+for.inc: ; preds = %for.body, %for.body, %for.body, %for.body
+ br i1 undef, label %for.end, label %for.body
+
+for.end: ; preds = %for.inc
+ call void asm sideeffect "mov $1,%gs:$0", "=*m,r,~{dirflag},~{fpsr},~{flags}"(%struct.__s* bitcast (%struct.pcb** getelementptr (%struct.pcpu* null, i32 0, i32 4) to %struct.__s*), i64 undef) nounwind
+ br label %for.body170
+
+for.body170: ; preds = %for.body170, %for.end
+ store i64 or (i64 and (i64 or (i64 ptrtoint (void (i32, i32, i32, i32)* @Xrsvd to i64), i64 2097152), i64 2162687), i64 or (i64 or (i64 and (i64 shl (i64 ptrtoint (void (i32, i32, i32, i32)* @Xrsvd to i64), i64 32), i64 -281474976710656), i64 140737488355328), i64 15393162788864)), i64* undef
+ br i1 undef, label %for.end175, label %for.body170
+
+for.end175: ; preds = %for.body170
+ unreachable
+}
+
+declare void @Xrsvd(i32, i32, i32, i32) ssp noredzone noimplicitfloat
diff --git a/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll b/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll
new file mode 100644
index 0000000..7b5e871
--- /dev/null
+++ b/test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim | FileCheck %s
+
+; It's not legal to fold a load from 32-bit stack slot into a 64-bit
+; instruction. If done, the instruction does a 64-bit load and that's not
+; safe. This can happen we a subreg_to_reg 0 has been coalesced. One
+; exception is when the instruction that folds the load is a move, then we
+; can simply turn it into a 32-bit load from the stack slot.
+; rdar://7170444
+
+%struct.ComplexType = type { i32 }
+
+define i32 @t(i32 %clientPort, i32 %pluginID, i32 %requestID, i32 %objectID, i64 %serverIdentifier, i64 %argumentsData, i32 %argumentsLength) ssp {
+entry:
+; CHECK: _t:
+; CHECK: movl 16(%rbp),
+ %0 = zext i32 %argumentsLength to i64 ; <i64> [#uses=1]
+ %1 = zext i32 %clientPort to i64 ; <i64> [#uses=1]
+ %2 = inttoptr i64 %1 to %struct.ComplexType* ; <%struct.ComplexType*> [#uses=1]
+ %3 = invoke i8* @pluginInstance(i8* undef, i32 %pluginID)
+ to label %invcont unwind label %lpad ; <i8*> [#uses=1]
+
+invcont: ; preds = %entry
+ %4 = add i32 %requestID, %pluginID ; <i32> [#uses=0]
+ %5 = invoke zeroext i8 @invoke(i8* %3, i32 %objectID, i8* undef, i64 %argumentsData, i32 %argumentsLength, i64* undef, i32* undef)
+ to label %invcont1 unwind label %lpad ; <i8> [#uses=0]
+
+invcont1: ; preds = %invcont
+ %6 = getelementptr inbounds %struct.ComplexType* %2, i64 0, i32 0 ; <i32*> [#uses=1]
+ %7 = load i32* %6, align 4 ; <i32> [#uses=1]
+ invoke void @booleanAndDataReply(i32 %7, i32 undef, i32 %requestID, i32 undef, i64 undef, i32 undef)
+ to label %invcont2 unwind label %lpad
+
+invcont2: ; preds = %invcont1
+ ret i32 0
+
+lpad: ; preds = %invcont1, %invcont, %entry
+ %8 = call i32 @vm_deallocate(i32 undef, i64 0, i64 %0) ; <i32> [#uses=0]
+ unreachable
+}
+
+declare i32 @vm_deallocate(i32, i64, i64)
+
+declare i8* @pluginInstance(i8*, i32)
+
+declare zeroext i8 @invoke(i8*, i32, i8*, i64, i32, i64*, i32*)
+
+declare void @booleanAndDataReply(i32, i32, i32, i32, i64, i32)
diff --git a/test/CodeGen/X86/2009-09-10-SpillComments.ll b/test/CodeGen/X86/2009-09-10-SpillComments.ll
new file mode 100644
index 0000000..f9ca861
--- /dev/null
+++ b/test/CodeGen/X86/2009-09-10-SpillComments.ll
@@ -0,0 +1,108 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux | FileCheck %s
+
+; This test shouldn't require spills.
+
+; CHECK: subq $8, %rsp
+; CHECK-NOT: $rsp
+; CHECK: addq $8, %rsp
+
+ %struct..0anon = type { i32 }
+ %struct.rtvec_def = type { i32, [1 x %struct..0anon] }
+ %struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] }
+@rtx_format = external global [116 x i8*] ; <[116 x i8*]*> [#uses=1]
+@rtx_length = external global [117 x i32] ; <[117 x i32]*> [#uses=1]
+
+declare %struct.rtx_def* @fixup_memory_subreg(%struct.rtx_def*, %struct.rtx_def*, i32)
+
+define %struct.rtx_def* @walk_fixup_memory_subreg(%struct.rtx_def* %x, %struct.rtx_def* %insn) {
+entry:
+ %tmp2 = icmp eq %struct.rtx_def* %x, null ; <i1> [#uses=1]
+ br i1 %tmp2, label %UnifiedReturnBlock, label %cond_next
+
+cond_next: ; preds = %entry
+ %tmp6 = getelementptr %struct.rtx_def* %x, i32 0, i32 0 ; <i16*> [#uses=1]
+ %tmp7 = load i16* %tmp6 ; <i16> [#uses=2]
+ %tmp78 = zext i16 %tmp7 to i32 ; <i32> [#uses=2]
+ %tmp10 = icmp eq i16 %tmp7, 54 ; <i1> [#uses=1]
+ br i1 %tmp10, label %cond_true13, label %cond_next32
+
+cond_true13: ; preds = %cond_next
+ %tmp15 = getelementptr %struct.rtx_def* %x, i32 0, i32 3 ; <[1 x %struct..0anon]*> [#uses=1]
+ %tmp1718 = bitcast [1 x %struct..0anon]* %tmp15 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=1]
+ %tmp19 = load %struct.rtx_def** %tmp1718 ; <%struct.rtx_def*> [#uses=1]
+ %tmp20 = getelementptr %struct.rtx_def* %tmp19, i32 0, i32 0 ; <i16*> [#uses=1]
+ %tmp21 = load i16* %tmp20 ; <i16> [#uses=1]
+ %tmp22 = icmp eq i16 %tmp21, 57 ; <i1> [#uses=1]
+ br i1 %tmp22, label %cond_true25, label %cond_next32
+
+cond_true25: ; preds = %cond_true13
+ %tmp29 = tail call %struct.rtx_def* @fixup_memory_subreg( %struct.rtx_def* %x, %struct.rtx_def* %insn, i32 1 ) nounwind ; <%struct.rtx_def*> [#uses=1]
+ ret %struct.rtx_def* %tmp29
+
+cond_next32: ; preds = %cond_true13, %cond_next
+ %tmp34 = getelementptr [116 x i8*]* @rtx_format, i32 0, i32 %tmp78 ; <i8**> [#uses=1]
+ %tmp35 = load i8** %tmp34, align 4 ; <i8*> [#uses=1]
+ %tmp37 = getelementptr [117 x i32]* @rtx_length, i32 0, i32 %tmp78 ; <i32*> [#uses=1]
+ %tmp38 = load i32* %tmp37, align 4 ; <i32> [#uses=1]
+ %i.011 = add i32 %tmp38, -1 ; <i32> [#uses=2]
+ %tmp12513 = icmp sgt i32 %i.011, -1 ; <i1> [#uses=1]
+ br i1 %tmp12513, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %bb123, %cond_next32
+ %indvar = phi i32 [ %indvar.next26, %bb123 ], [ 0, %cond_next32 ] ; <i32> [#uses=2]
+ %i.01.0 = sub i32 %i.011, %indvar ; <i32> [#uses=5]
+ %tmp42 = getelementptr i8* %tmp35, i32 %i.01.0 ; <i8*> [#uses=2]
+ %tmp43 = load i8* %tmp42 ; <i8> [#uses=1]
+ switch i8 %tmp43, label %bb123 [
+ i8 101, label %cond_true47
+ i8 69, label %bb105.preheader
+ ]
+
+cond_true47: ; preds = %bb
+ %tmp52 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0 ; <%struct..0anon*> [#uses=1]
+ %tmp5354 = bitcast %struct..0anon* %tmp52 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=1]
+ %tmp55 = load %struct.rtx_def** %tmp5354 ; <%struct.rtx_def*> [#uses=1]
+ %tmp58 = tail call %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp55, %struct.rtx_def* %insn ) nounwind ; <%struct.rtx_def*> [#uses=1]
+ %tmp62 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0, i32 0 ; <i32*> [#uses=1]
+ %tmp58.c = ptrtoint %struct.rtx_def* %tmp58 to i32 ; <i32> [#uses=1]
+ store i32 %tmp58.c, i32* %tmp62
+ %tmp6816 = load i8* %tmp42 ; <i8> [#uses=1]
+ %tmp6917 = icmp eq i8 %tmp6816, 69 ; <i1> [#uses=1]
+ br i1 %tmp6917, label %bb105.preheader, label %bb123
+
+bb105.preheader: ; preds = %cond_true47, %bb
+ %tmp11020 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0 ; <%struct..0anon*> [#uses=1]
+ %tmp11111221 = bitcast %struct..0anon* %tmp11020 to %struct.rtvec_def** ; <%struct.rtvec_def**> [#uses=3]
+ %tmp11322 = load %struct.rtvec_def** %tmp11111221 ; <%struct.rtvec_def*> [#uses=1]
+ %tmp11423 = getelementptr %struct.rtvec_def* %tmp11322, i32 0, i32 0 ; <i32*> [#uses=1]
+ %tmp11524 = load i32* %tmp11423 ; <i32> [#uses=1]
+ %tmp11625 = icmp eq i32 %tmp11524, 0 ; <i1> [#uses=1]
+ br i1 %tmp11625, label %bb123, label %bb73
+
+bb73: ; preds = %bb73, %bb105.preheader
+ %j.019 = phi i32 [ %tmp104, %bb73 ], [ 0, %bb105.preheader ] ; <i32> [#uses=3]
+ %tmp81 = load %struct.rtvec_def** %tmp11111221 ; <%struct.rtvec_def*> [#uses=2]
+ %tmp92 = getelementptr %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019 ; <%struct..0anon*> [#uses=1]
+ %tmp9394 = bitcast %struct..0anon* %tmp92 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=1]
+ %tmp95 = load %struct.rtx_def** %tmp9394 ; <%struct.rtx_def*> [#uses=1]
+ %tmp98 = tail call %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp95, %struct.rtx_def* %insn ) nounwind ; <%struct.rtx_def*> [#uses=1]
+ %tmp101 = getelementptr %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019, i32 0 ; <i32*> [#uses=1]
+ %tmp98.c = ptrtoint %struct.rtx_def* %tmp98 to i32 ; <i32> [#uses=1]
+ store i32 %tmp98.c, i32* %tmp101
+ %tmp104 = add i32 %j.019, 1 ; <i32> [#uses=2]
+ %tmp113 = load %struct.rtvec_def** %tmp11111221 ; <%struct.rtvec_def*> [#uses=1]
+ %tmp114 = getelementptr %struct.rtvec_def* %tmp113, i32 0, i32 0 ; <i32*> [#uses=1]
+ %tmp115 = load i32* %tmp114 ; <i32> [#uses=1]
+ %tmp116 = icmp ult i32 %tmp104, %tmp115 ; <i1> [#uses=1]
+ br i1 %tmp116, label %bb73, label %bb123
+
+bb123: ; preds = %bb73, %bb105.preheader, %cond_true47, %bb
+ %i.0 = add i32 %i.01.0, -1 ; <i32> [#uses=1]
+ %tmp125 = icmp sgt i32 %i.0, -1 ; <i1> [#uses=1]
+ %indvar.next26 = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br i1 %tmp125, label %bb, label %UnifiedReturnBlock
+
+UnifiedReturnBlock: ; preds = %bb123, %cond_next32, %entry
+ %UnifiedRetVal = phi %struct.rtx_def* [ null, %entry ], [ %x, %cond_next32 ], [ %x, %bb123 ] ; <%struct.rtx_def*> [#uses=1]
+ ret %struct.rtx_def* %UnifiedRetVal
+}
diff --git a/test/CodeGen/X86/2009-09-16-CoalescerBug.ll b/test/CodeGen/X86/2009-09-16-CoalescerBug.ll
new file mode 100644
index 0000000..18b5a17
--- /dev/null
+++ b/test/CodeGen/X86/2009-09-16-CoalescerBug.ll
@@ -0,0 +1,64 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin10
+; PR4910
+
+%0 = type { i32, i32, i32, i32 }
+
+@boot_cpu_id = external global i32 ; <i32*> [#uses=1]
+@cpu_logical = common global i32 0, align 4 ; <i32*> [#uses=1]
+
+define void @topo_probe_0xb() nounwind ssp {
+entry:
+ br label %for.cond
+
+for.cond: ; preds = %for.inc38, %entry
+ %0 = phi i32 [ 0, %entry ], [ %inc40, %for.inc38 ] ; <i32> [#uses=3]
+ %cmp = icmp slt i32 %0, 3 ; <i1> [#uses=1]
+ br i1 %cmp, label %for.body, label %for.end41
+
+for.body: ; preds = %for.cond
+ %1 = tail call %0 asm sideeffect "cpuid", "={ax},={bx},={cx},={dx},0,{cx},~{dirflag},~{fpsr},~{flags}"(i32 11, i32 %0) nounwind ; <%0> [#uses=3]
+ %asmresult.i = extractvalue %0 %1, 0 ; <i32> [#uses=1]
+ %asmresult10.i = extractvalue %0 %1, 2 ; <i32> [#uses=1]
+ %and = and i32 %asmresult.i, 31 ; <i32> [#uses=2]
+ %shr42 = lshr i32 %asmresult10.i, 8 ; <i32> [#uses=1]
+ %and12 = and i32 %shr42, 255 ; <i32> [#uses=2]
+ %cmp14 = icmp eq i32 %and12, 0 ; <i1> [#uses=1]
+ br i1 %cmp14, label %for.end41, label %lor.lhs.false
+
+lor.lhs.false: ; preds = %for.body
+ %asmresult9.i = extractvalue %0 %1, 1 ; <i32> [#uses=1]
+ %and7 = and i32 %asmresult9.i, 65535 ; <i32> [#uses=1]
+ %cmp16 = icmp eq i32 %and7, 0 ; <i1> [#uses=1]
+ br i1 %cmp16, label %for.end41, label %for.cond17.preheader
+
+for.cond17.preheader: ; preds = %lor.lhs.false
+ %tmp24 = load i32* @boot_cpu_id ; <i32> [#uses=1]
+ %shr26 = ashr i32 %tmp24, %and ; <i32> [#uses=1]
+ br label %for.body20
+
+for.body20: ; preds = %for.body20, %for.cond17.preheader
+ %2 = phi i32 [ 0, %for.cond17.preheader ], [ %inc32, %for.body20 ] ; <i32> [#uses=2]
+ %cnt.143 = phi i32 [ 0, %for.cond17.preheader ], [ %inc.cnt.1, %for.body20 ] ; <i32> [#uses=1]
+ %shr23 = ashr i32 %2, %and ; <i32> [#uses=1]
+ %cmp27 = icmp eq i32 %shr23, %shr26 ; <i1> [#uses=1]
+ %inc = zext i1 %cmp27 to i32 ; <i32> [#uses=1]
+ %inc.cnt.1 = add i32 %inc, %cnt.143 ; <i32> [#uses=2]
+ %inc32 = add nsw i32 %2, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %inc32, 255 ; <i1> [#uses=1]
+ br i1 %exitcond, label %for.end, label %for.body20
+
+for.end: ; preds = %for.body20
+ %cmp34 = icmp eq i32 %and12, 1 ; <i1> [#uses=1]
+ br i1 %cmp34, label %if.then35, label %for.inc38
+
+if.then35: ; preds = %for.end
+ store i32 %inc.cnt.1, i32* @cpu_logical
+ br label %for.inc38
+
+for.inc38: ; preds = %for.end, %if.then35
+ %inc40 = add nsw i32 %0, 1 ; <i32> [#uses=1]
+ br label %for.cond
+
+for.end41: ; preds = %lor.lhs.false, %for.body, %for.cond
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll b/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll
new file mode 100644
index 0000000..8cb538b
--- /dev/null
+++ b/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin10 -post-RA-scheduler=true | FileCheck %s
+
+; PR4958
+
+define i32 @main() nounwind ssp {
+entry:
+; CHECK: main:
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ br label %bb
+
+bb: ; preds = %bb1, %entry
+; CHECK: addl $1
+; CHECK-NEXT: movl %e
+; CHECK-NEXT: adcl $0
+ %i.0 = phi i64 [ 0, %entry ], [ %0, %bb1 ] ; <i64> [#uses=1]
+ %0 = add nsw i64 %i.0, 1 ; <i64> [#uses=2]
+ %1 = icmp sgt i32 0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %bb2, label %bb1
+
+bb1: ; preds = %bb
+ %2 = icmp sle i64 %0, 1 ; <i1> [#uses=1]
+ br i1 %2, label %bb, label %bb2
+
+bb2: ; preds = %bb1, %bb
+ br label %return
+
+return: ; preds = %bb2
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/2009-09-19-earlyclobber.ll b/test/CodeGen/X86/2009-09-19-earlyclobber.ll
new file mode 100644
index 0000000..4f44cae
--- /dev/null
+++ b/test/CodeGen/X86/2009-09-19-earlyclobber.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s | FileCheck %s
+; ModuleID = '4964.c'
+; PR 4964
+; Registers other than RAX, RCX are OK, but they must be different.
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin10.0"
+ type { i64, i64 } ; type %0
+
+define i64 @flsst(i64 %find) nounwind ssp {
+entry:
+; CHECK: FOO %rax %rcx
+ %asmtmp = tail call %0 asm sideeffect "FOO $0 $1 $2", "=r,=&r,rm,~{dirflag},~{fpsr},~{flags},~{cc}"(i64 %find) nounwind ; <%0> [#uses=1]
+ %asmresult = extractvalue %0 %asmtmp, 0 ; <i64> [#uses=1]
+ ret i64 %asmresult
+}
diff --git a/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll b/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll
new file mode 100644
index 0000000..80b88358
--- /dev/null
+++ b/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin10.0 -relocation-model=pic | FileCheck %s
+
+define void @dot(i16* nocapture %A, i32 %As, i16* nocapture %B, i32 %Bs, i16* nocapture %C, i32 %N) nounwind ssp {
+; CHECK: dot:
+; CHECK: decl %
+; CHECK-NEXT: jne
+entry:
+ %0 = icmp sgt i32 %N, 0 ; <i1> [#uses=1]
+ br i1 %0, label %bb, label %bb2
+
+bb: ; preds = %bb, %entry
+ %i.03 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
+ %sum.04 = phi i32 [ 0, %entry ], [ %10, %bb ] ; <i32> [#uses=1]
+ %1 = mul i32 %i.03, %As ; <i32> [#uses=1]
+ %2 = getelementptr i16* %A, i32 %1 ; <i16*> [#uses=1]
+ %3 = load i16* %2, align 2 ; <i16> [#uses=1]
+ %4 = sext i16 %3 to i32 ; <i32> [#uses=1]
+ %5 = mul i32 %i.03, %Bs ; <i32> [#uses=1]
+ %6 = getelementptr i16* %B, i32 %5 ; <i16*> [#uses=1]
+ %7 = load i16* %6, align 2 ; <i16> [#uses=1]
+ %8 = sext i16 %7 to i32 ; <i32> [#uses=1]
+ %9 = mul i32 %8, %4 ; <i32> [#uses=1]
+ %10 = add i32 %9, %sum.04 ; <i32> [#uses=2]
+ %indvar.next = add i32 %i.03, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %N ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb1.bb2_crit_edge, label %bb
+
+bb1.bb2_crit_edge: ; preds = %bb
+ %phitmp = trunc i32 %10 to i16 ; <i16> [#uses=1]
+ br label %bb2
+
+bb2: ; preds = %entry, %bb1.bb2_crit_edge
+ %sum.0.lcssa = phi i16 [ %phitmp, %bb1.bb2_crit_edge ], [ 0, %entry ] ; <i16> [#uses=1]
+ store i16 %sum.0.lcssa, i16* %C, align 2
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-09-22-CoalescerBug.ll b/test/CodeGen/X86/2009-09-22-CoalescerBug.ll
new file mode 100644
index 0000000..33f35f8
--- /dev/null
+++ b/test/CodeGen/X86/2009-09-22-CoalescerBug.ll
@@ -0,0 +1,124 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp {
+entry:
+ br i1 undef, label %bb, label %bb1
+
+bb: ; preds = %entry
+ ret i32 3
+
+bb1: ; preds = %entry
+ br i1 undef, label %bb3, label %bb2
+
+bb2: ; preds = %bb1
+ ret i32 3
+
+bb3: ; preds = %bb1
+ br i1 undef, label %bb.i18, label %quantum_getwidth.exit
+
+bb.i18: ; preds = %bb.i18, %bb3
+ br i1 undef, label %bb.i18, label %quantum_getwidth.exit
+
+quantum_getwidth.exit: ; preds = %bb.i18, %bb3
+ br i1 undef, label %bb4, label %bb6.preheader
+
+bb4: ; preds = %quantum_getwidth.exit
+ unreachable
+
+bb6.preheader: ; preds = %quantum_getwidth.exit
+ br i1 undef, label %bb.i1, label %bb1.i2
+
+bb.i1: ; preds = %bb6.preheader
+ unreachable
+
+bb1.i2: ; preds = %bb6.preheader
+ br i1 undef, label %bb2.i, label %bb3.i4
+
+bb2.i: ; preds = %bb1.i2
+ unreachable
+
+bb3.i4: ; preds = %bb1.i2
+ br i1 undef, label %quantum_new_qureg.exit, label %bb4.i
+
+bb4.i: ; preds = %bb3.i4
+ unreachable
+
+quantum_new_qureg.exit: ; preds = %bb3.i4
+ br i1 undef, label %bb9, label %bb11.thread
+
+bb11.thread: ; preds = %quantum_new_qureg.exit
+ %.cast.i = zext i32 undef to i64 ; <i64> [#uses=1]
+ br label %bb.i37
+
+bb9: ; preds = %quantum_new_qureg.exit
+ unreachable
+
+bb.i37: ; preds = %bb.i37, %bb11.thread
+ %0 = load i64* undef, align 8 ; <i64> [#uses=1]
+ %1 = shl i64 %0, %.cast.i ; <i64> [#uses=1]
+ store i64 %1, i64* undef, align 8
+ br i1 undef, label %bb.i37, label %quantum_addscratch.exit
+
+quantum_addscratch.exit: ; preds = %bb.i37
+ br i1 undef, label %bb12.preheader, label %bb14
+
+bb12.preheader: ; preds = %quantum_addscratch.exit
+ unreachable
+
+bb14: ; preds = %quantum_addscratch.exit
+ br i1 undef, label %bb17, label %bb.nph
+
+bb.nph: ; preds = %bb14
+ unreachable
+
+bb17: ; preds = %bb14
+ br i1 undef, label %bb1.i7, label %quantum_measure.exit
+
+bb1.i7: ; preds = %bb17
+ br label %quantum_measure.exit
+
+quantum_measure.exit: ; preds = %bb1.i7, %bb17
+ switch i32 undef, label %bb21 [
+ i32 -1, label %bb18
+ i32 0, label %bb20
+ ]
+
+bb18: ; preds = %quantum_measure.exit
+ unreachable
+
+bb20: ; preds = %quantum_measure.exit
+ unreachable
+
+bb21: ; preds = %quantum_measure.exit
+ br i1 undef, label %quantum_frac_approx.exit, label %bb1.i
+
+bb1.i: ; preds = %bb21
+ unreachable
+
+quantum_frac_approx.exit: ; preds = %bb21
+ br i1 undef, label %bb25, label %bb26
+
+bb25: ; preds = %quantum_frac_approx.exit
+ unreachable
+
+bb26: ; preds = %quantum_frac_approx.exit
+ br i1 undef, label %quantum_gcd.exit, label %bb.i
+
+bb.i: ; preds = %bb.i, %bb26
+ br i1 undef, label %quantum_gcd.exit, label %bb.i
+
+quantum_gcd.exit: ; preds = %bb.i, %bb26
+ br i1 undef, label %bb32, label %bb33
+
+bb32: ; preds = %quantum_gcd.exit
+ br i1 undef, label %bb.i.i, label %quantum_delete_qureg.exit
+
+bb.i.i: ; preds = %bb32
+ ret i32 0
+
+quantum_delete_qureg.exit: ; preds = %bb32
+ ret i32 0
+
+bb33: ; preds = %quantum_gcd.exit
+ unreachable
+}
diff --git a/test/CodeGen/X86/2009-09-23-LiveVariablesBug.ll b/test/CodeGen/X86/2009-09-23-LiveVariablesBug.ll
new file mode 100644
index 0000000..d37d4b8
--- /dev/null
+++ b/test/CodeGen/X86/2009-09-23-LiveVariablesBug.ll
@@ -0,0 +1,91 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10
+
+; rdar://7247745
+
+%struct._lck_mtx_ = type { %union.anon }
+%struct._lck_rw_t_internal_ = type <{ i16, i8, i8, i32, i32, i32 }>
+%struct.anon = type { i64, i64, [2 x i8], i8, i8, i32 }
+%struct.memory_object = type { i32, i32, %struct.memory_object_pager_ops* }
+%struct.memory_object_control = type { i32, i32, %struct.vm_object* }
+%struct.memory_object_pager_ops = type { void (%struct.memory_object*)*, void (%struct.memory_object*)*, i32 (%struct.memory_object*, %struct.memory_object_control*, i32)*, i32 (%struct.memory_object*)*, i32 (%struct.memory_object*, i64, i32, i32, i32*)*, i32 (%struct.memory_object*, i64, i32, i64*, i32*, i32, i32, i32)*, i32 (%struct.memory_object*, i64, i32)*, i32 (%struct.memory_object*, i64, i64, i32)*, i32 (%struct.memory_object*, i64, i64, i32)*, i32 (%struct.memory_object*, i32)*, i32 (%struct.memory_object*)*, i8* }
+%struct.queue_entry = type { %struct.queue_entry*, %struct.queue_entry* }
+%struct.upl = type { %struct._lck_mtx_, i32, i32, %struct.vm_object*, i64, i32, i64, %struct.vm_object*, i32, i8* }
+%struct.upl_page_info = type <{ i32, i8, [3 x i8] }>
+%struct.vm_object = type { %struct.queue_entry, %struct._lck_rw_t_internal_, i64, %struct.vm_page*, i32, i32, i32, i32, %struct.vm_object*, %struct.vm_object*, i64, %struct.memory_object*, i64, %struct.memory_object_control*, i32, i16, i16, [2 x i8], i8, i8, %struct.queue_entry, %struct.queue_entry, i64, i32, i32, i32, i8*, i64, i8, i8, [2 x i8], %struct.queue_entry }
+%struct.vm_page = type { %struct.queue_entry, %struct.queue_entry, %struct.vm_page*, %struct.vm_object*, i64, [2 x i8], i8, i8, i32, i8, i8, i8, i8, i32 }
+%union.anon = type { %struct.anon }
+
+declare i64 @OSAddAtomic64(i64, i64*) noredzone noimplicitfloat
+
+define i32 @upl_commit_range(%struct.upl* %upl, i32 %offset, i32 %size, i32 %flags, %struct.upl_page_info* %page_list, i32 %count, i32* nocapture %empty) nounwind noredzone noimplicitfloat {
+entry:
+ br i1 undef, label %if.then, label %if.end
+
+if.end: ; preds = %entry
+ br i1 undef, label %if.end143, label %if.then136
+
+if.then136: ; preds = %if.end
+ unreachable
+
+if.end143: ; preds = %if.end
+ br i1 undef, label %if.else155, label %if.then153
+
+if.then153: ; preds = %if.end143
+ br label %while.cond
+
+if.else155: ; preds = %if.end143
+ unreachable
+
+while.cond: ; preds = %if.end1039, %if.then153
+ br i1 undef, label %if.then1138, label %while.body
+
+while.body: ; preds = %while.cond
+ br i1 undef, label %if.end260, label %if.then217
+
+if.then217: ; preds = %while.body
+ br i1 undef, label %if.end260, label %if.then230
+
+if.then230: ; preds = %if.then217
+ br i1 undef, label %if.then246, label %if.end260
+
+if.then246: ; preds = %if.then230
+ br label %if.end260
+
+if.end260: ; preds = %if.then246, %if.then230, %if.then217, %while.body
+ br i1 undef, label %if.end296, label %if.then266
+
+if.then266: ; preds = %if.end260
+ unreachable
+
+if.end296: ; preds = %if.end260
+ br i1 undef, label %if.end1039, label %if.end306
+
+if.end306: ; preds = %if.end296
+ br i1 undef, label %if.end796, label %if.then616
+
+if.then616: ; preds = %if.end306
+ br i1 undef, label %commit_next_page, label %do.body716
+
+do.body716: ; preds = %if.then616
+ %call721 = call i64 @OSAddAtomic64(i64 1, i64* undef) nounwind noredzone noimplicitfloat ; <i64> [#uses=0]
+ call void asm sideeffect "movq\090x0($0),%rdi\0A\09movq\090x8($0),%rsi\0A\09.section __DATA, __data\0A\09.globl __dtrace_probeDOLLAR${:uid}4794___vminfo____pgrec\0A\09__dtrace_probeDOLLAR${:uid}4794___vminfo____pgrec:.quad 1f\0A\09.text\0A\091:nop\0A\09nop\0A\09nop\0A\09", "r,~{memory},~{di},~{si},~{dirflag},~{fpsr},~{flags}"(i64* undef) nounwind
+ br label %commit_next_page
+
+if.end796: ; preds = %if.end306
+ unreachable
+
+commit_next_page: ; preds = %do.body716, %if.then616
+ br i1 undef, label %if.end1039, label %if.then1034
+
+if.then1034: ; preds = %commit_next_page
+ br label %if.end1039
+
+if.end1039: ; preds = %if.then1034, %commit_next_page, %if.end296
+ br label %while.cond
+
+if.then1138: ; preds = %while.cond
+ unreachable
+
+if.then: ; preds = %entry
+ ret i32 4
+}
diff --git a/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll b/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll
new file mode 100644
index 0000000..91c5440
--- /dev/null
+++ b/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll
@@ -0,0 +1,264 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -stats |& grep {machine-licm} | grep 2
+; rdar://7274692
+
+%0 = type { [125 x i32] }
+%1 = type { i32 }
+%struct..5sPragmaType = type { i8*, i32 }
+%struct.AggInfo = type { i8, i8, i32, %struct.ExprList*, i32, %struct.AggInfo_col*, i32, i32, i32, %struct.AggInfo_func*, i32, i32 }
+%struct.AggInfo_col = type { %struct.Table*, i32, i32, i32, i32, %struct.Expr* }
+%struct.AggInfo_func = type { %struct.Expr*, %struct.FuncDef*, i32, i32 }
+%struct.AuxData = type { i8*, void (i8*)* }
+%struct.Bitvec = type { i32, i32, i32, %0 }
+%struct.BtCursor = type { %struct.Btree*, %struct.BtShared*, %struct.BtCursor*, %struct.BtCursor*, i32 (i8*, i32, i8*, i32, i8*)*, i8*, i32, %struct.MemPage*, i32, %struct.CellInfo, i8, i8, i8*, i64, i32, i8, i32* }
+%struct.BtLock = type { %struct.Btree*, i32, i8, %struct.BtLock* }
+%struct.BtShared = type { %struct.Pager*, %struct.sqlite3*, %struct.BtCursor*, %struct.MemPage*, i8, i8, i8, i8, i8, i8, i8, i8, i32, i16, i16, i32, i32, i32, i32, i8, i32, i8*, void (i8*)*, %struct.sqlite3_mutex*, %struct.BusyHandler, i32, %struct.BtShared*, %struct.BtLock*, %struct.Btree* }
+%struct.Btree = type { %struct.sqlite3*, %struct.BtShared*, i8, i8, i8, i32, %struct.Btree*, %struct.Btree* }
+%struct.BtreeMutexArray = type { i32, [11 x %struct.Btree*] }
+%struct.BusyHandler = type { i32 (i8*, i32)*, i8*, i32 }
+%struct.CellInfo = type { i8*, i64, i32, i32, i16, i16, i16, i16 }
+%struct.CollSeq = type { i8*, i8, i8, i8*, i32 (i8*, i32, i8*, i32, i8*)*, void (i8*)* }
+%struct.Column = type { i8*, %struct.Expr*, i8*, i8*, i8, i8, i8, i8 }
+%struct.Context = type { i64, i32, %struct.Fifo }
+%struct.CountCtx = type { i64 }
+%struct.Cursor = type { %struct.BtCursor*, i32, i64, i64, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i64, %struct.Btree*, i32, i8*, i64, i8*, %struct.KeyInfo*, i32, i64, %struct.sqlite3_vtab_cursor*, %struct.sqlite3_module*, i32, i32, i32*, i32*, i8* }
+%struct.Db = type { i8*, %struct.Btree*, i8, i8, i8*, void (i8*)*, %struct.Schema* }
+%struct.DbPage = type { %struct.Pager*, i32, %struct.DbPage*, %struct.DbPage*, %struct.PagerLruLink, %struct.DbPage*, i8, i8, i8, i8, i8, i16, %struct.DbPage*, %struct.DbPage*, i8* }
+%struct.Expr = type { i8, i8, i16, %struct.CollSeq*, %struct.Expr*, %struct.Expr*, %struct.ExprList*, %struct..5sPragmaType, %struct..5sPragmaType, i32, i32, %struct.AggInfo*, i32, i32, %struct.Select*, %struct.Table*, i32 }
+%struct.ExprList = type { i32, i32, i32, %struct.ExprList_item* }
+%struct.ExprList_item = type { %struct.Expr*, i8*, i8, i8, i8 }
+%struct.FILE = type { i8*, i32, i32, i16, i16, %struct..5sPragmaType, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct..5sPragmaType, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct..5sPragmaType, i32, i64 }
+%struct.FKey = type { %struct.Table*, %struct.FKey*, i8*, %struct.FKey*, i32, %struct.sColMap*, i8, i8, i8, i8 }
+%struct.Fifo = type { i32, %struct.FifoPage*, %struct.FifoPage* }
+%struct.FifoPage = type { i32, i32, i32, %struct.FifoPage*, [1 x i64] }
+%struct.FuncDef = type { i16, i8, i8, i8, i8*, %struct.FuncDef*, void (%struct.sqlite3_context*, i32, %struct.Mem**)*, void (%struct.sqlite3_context*, i32, %struct.Mem**)*, void (%struct.sqlite3_context*)*, [1 x i8] }
+%struct.Hash = type { i8, i8, i32, i32, %struct.HashElem*, %struct._ht* }
+%struct.HashElem = type { %struct.HashElem*, %struct.HashElem*, i8*, i8*, i32 }
+%struct.IdList = type { %struct..5sPragmaType*, i32, i32 }
+%struct.Index = type { i8*, i32, i32*, i32*, %struct.Table*, i32, i8, i8, i8*, %struct.Index*, %struct.Schema*, i8*, i8** }
+%struct.KeyInfo = type { %struct.sqlite3*, i8, i8, i8, i32, i8*, [1 x %struct.CollSeq*] }
+%struct.Mem = type { %struct.CountCtx, double, %struct.sqlite3*, i8*, i32, i16, i8, i8, void (i8*)* }
+%struct.MemPage = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i16, i16, i16, i16, i16, i16, [5 x %struct._OvflCell], %struct.BtShared*, i8*, %struct.DbPage*, i32, %struct.MemPage* }
+%struct.Module = type { %struct.sqlite3_module*, i8*, i8*, void (i8*)* }
+%struct.Op = type { i8, i8, i8, i8, i32, i32, i32, %1 }
+%struct.Pager = type { %struct.sqlite3_vfs*, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.Bitvec*, %struct.Bitvec*, i8*, i8*, i8*, i8*, %struct.sqlite3_file*, %struct.sqlite3_file*, %struct.sqlite3_file*, %struct.BusyHandler*, %struct.PagerLruList, %struct.DbPage*, %struct.DbPage*, %struct.DbPage*, i64, i64, i64, i64, i64, i32, void (%struct.DbPage*, i32)*, void (%struct.DbPage*, i32)*, i32, %struct.DbPage**, i8*, [16 x i8] }
+%struct.PagerLruLink = type { %struct.DbPage*, %struct.DbPage* }
+%struct.PagerLruList = type { %struct.DbPage*, %struct.DbPage*, %struct.DbPage* }
+%struct.Schema = type { i32, %struct.Hash, %struct.Hash, %struct.Hash, %struct.Hash, %struct.Table*, i8, i8, i16, i32, %struct.sqlite3* }
+%struct.Select = type { %struct.ExprList*, i8, i8, i8, i8, i8, i8, i8, %struct.SrcList*, %struct.Expr*, %struct.ExprList*, %struct.Expr*, %struct.ExprList*, %struct.Select*, %struct.Select*, %struct.Select*, %struct.Expr*, %struct.Expr*, i32, i32, [3 x i32] }
+%struct.SrcList = type { i16, i16, [1 x %struct.SrcList_item] }
+%struct.SrcList_item = type { i8*, i8*, i8*, %struct.Table*, %struct.Select*, i8, i8, i32, %struct.Expr*, %struct.IdList*, i64 }
+%struct.Table = type { i8*, i32, %struct.Column*, i32, %struct.Index*, i32, %struct.Select*, i32, %struct.Trigger*, %struct.FKey*, i8*, %struct.Expr*, i32, i8, i8, i8, i8, i8, i8, i8, %struct.Module*, %struct.sqlite3_vtab*, i32, i8**, %struct.Schema* }
+%struct.Trigger = type { i8*, i8*, i8, i8, %struct.Expr*, %struct.IdList*, %struct..5sPragmaType, %struct.Schema*, %struct.Schema*, %struct.TriggerStep*, %struct.Trigger* }
+%struct.TriggerStep = type { i32, i32, %struct.Trigger*, %struct.Select*, %struct..5sPragmaType, %struct.Expr*, %struct.ExprList*, %struct.IdList*, %struct.TriggerStep*, %struct.TriggerStep* }
+%struct.Vdbe = type { %struct.sqlite3*, %struct.Vdbe*, %struct.Vdbe*, i32, i32, %struct.Op*, i32, i32, i32*, %struct.Mem**, %struct.Mem*, i32, %struct.Cursor**, i32, %struct.Mem*, i8**, i32, i32, i32, %struct.Mem*, i32, i32, %struct.Fifo, i32, i32, %struct.Context*, i32, i32, i32, i32, i32, [25 x i32], i32, i32, i8**, i8*, %struct.Mem*, i8, i8, i8, i8, i8, i8, i32, i64, i32, %struct.BtreeMutexArray, i32, i8*, i32 }
+%struct.VdbeFunc = type { %struct.FuncDef*, i32, [1 x %struct.AuxData] }
+%struct._OvflCell = type { i8*, i16 }
+%struct._RuneCharClass = type { [14 x i8], i32 }
+%struct._RuneEntry = type { i32, i32, i32, i32* }
+%struct._RuneLocale = type { [8 x i8], [32 x i8], i32 (i8*, i32, i8**)*, i32 (i32, i8*, i32, i8**)*, i32, [256 x i32], [256 x i32], [256 x i32], %struct._RuneRange, %struct._RuneRange, %struct._RuneRange, i8*, i32, i32, %struct._RuneCharClass* }
+%struct._RuneRange = type { i32, %struct._RuneEntry* }
+%struct.__sFILEX = type opaque
+%struct._ht = type { i32, %struct.HashElem* }
+%struct.callback_data = type { %struct.sqlite3*, i32, i32, %struct.FILE*, i32, i32, i32, i8*, [20 x i8], [100 x i32], [100 x i32], [20 x i8], %struct.previous_mode_data, [1024 x i8], i8* }
+%struct.previous_mode_data = type { i32, i32, i32, [100 x i32] }
+%struct.sColMap = type { i32, i8* }
+%struct.sqlite3 = type { %struct.sqlite3_vfs*, i32, %struct.Db*, i32, i32, i32, i32, i8, i8, i8, i8, i32, %struct.CollSeq*, i64, i64, i32, i32, i32, %struct.sqlite3_mutex*, %struct.sqlite3InitInfo, i32, i8**, %struct.Vdbe*, i32, void (i8*, i8*)*, i8*, void (i8*, i8*, i64)*, i8*, i8*, i32 (i8*)*, i8*, void (i8*)*, i8*, void (i8*, i32, i8*, i8*, i64)*, void (i8*, %struct.sqlite3*, i32, i8*)*, void (i8*, %struct.sqlite3*, i32, i8*)*, i8*, %struct.Mem*, i8*, i8*, %union.anon, i32 (i8*, i32, i8*, i8*, i8*, i8*)*, i8*, i32 (i8*)*, i8*, i32, %struct.Hash, %struct.Table*, %struct.sqlite3_vtab**, i32, %struct.Hash, %struct.Hash, %struct.BusyHandler, i32, [2 x %struct.Db], i8 }
+%struct.sqlite3InitInfo = type { i32, i32, i8 }
+%struct.sqlite3_context = type { %struct.FuncDef*, %struct.VdbeFunc*, %struct.Mem, %struct.Mem*, i32, %struct.CollSeq* }
+%struct.sqlite3_file = type { %struct.sqlite3_io_methods* }
+%struct.sqlite3_index_constraint = type { i32, i8, i8, i32 }
+%struct.sqlite3_index_constraint_usage = type { i32, i8 }
+%struct.sqlite3_index_info = type { i32, %struct.sqlite3_index_constraint*, i32, %struct.sqlite3_index_constraint_usage*, %struct.sqlite3_index_constraint_usage*, i32, i8*, i32, i32, double }
+%struct.sqlite3_io_methods = type { i32, i32 (%struct.sqlite3_file*)*, i32 (%struct.sqlite3_file*, i8*, i32, i64)*, i32 (%struct.sqlite3_file*, i8*, i32, i64)*, i32 (%struct.sqlite3_file*, i64)*, i32 (%struct.sqlite3_file*, i32)*, i32 (%struct.sqlite3_file*, i64*)*, i32 (%struct.sqlite3_file*, i32)*, i32 (%struct.sqlite3_file*, i32)*, i32 (%struct.sqlite3_file*)*, i32 (%struct.sqlite3_file*, i32, i8*)*, i32 (%struct.sqlite3_file*)*, i32 (%struct.sqlite3_file*)* }
+%struct.sqlite3_module = type { i32, i32 (%struct.sqlite3*, i8*, i32, i8**, %struct.sqlite3_vtab**, i8**)*, i32 (%struct.sqlite3*, i8*, i32, i8**, %struct.sqlite3_vtab**, i8**)*, i32 (%struct.sqlite3_vtab*, %struct.sqlite3_index_info*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*, %struct.sqlite3_vtab_cursor**)*, i32 (%struct.sqlite3_vtab_cursor*)*, i32 (%struct.sqlite3_vtab_cursor*, i32, i8*, i32, %struct.Mem**)*, i32 (%struct.sqlite3_vtab_cursor*)*, i32 (%struct.sqlite3_vtab_cursor*)*, i32 (%struct.sqlite3_vtab_cursor*, %struct.sqlite3_context*, i32)*, i32 (%struct.sqlite3_vtab_cursor*, i64*)*, i32 (%struct.sqlite3_vtab*, i32, %struct.Mem**, i64*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*, i32, i8*, void (%struct.sqlite3_context*, i32, %struct.Mem**)**, i8**)*, i32 (%struct.sqlite3_vtab*, i8*)* }
+%struct.sqlite3_mutex = type opaque
+%struct.sqlite3_vfs = type { i32, i32, i32, %struct.sqlite3_vfs*, i8*, i8*, i32 (%struct.sqlite3_vfs*, i8*, %struct.sqlite3_file*, i32, i32*)*, i32 (%struct.sqlite3_vfs*, i8*, i32)*, i32 (%struct.sqlite3_vfs*, i8*, i32)*, i32 (%struct.sqlite3_vfs*, i32, i8*)*, i32 (%struct.sqlite3_vfs*, i8*, i32, i8*)*, i8* (%struct.sqlite3_vfs*, i8*)*, void (%struct.sqlite3_vfs*, i32, i8*)*, i8* (%struct.sqlite3_vfs*, i8*, i8*)*, void (%struct.sqlite3_vfs*, i8*)*, i32 (%struct.sqlite3_vfs*, i32, i8*)*, i32 (%struct.sqlite3_vfs*, i32)*, i32 (%struct.sqlite3_vfs*, double*)* }
+%struct.sqlite3_vtab = type { %struct.sqlite3_module*, i32, i8* }
+%struct.sqlite3_vtab_cursor = type { %struct.sqlite3_vtab* }
+%union.anon = type { double }
+
+@_DefaultRuneLocale = external global %struct._RuneLocale ; <%struct._RuneLocale*> [#uses=2]
+@__stderrp = external global %struct.FILE* ; <%struct.FILE**> [#uses=1]
[email protected] = internal constant [16 x i8] c"Out of memory!\0A\00", align 1 ; <[16 x i8]*> [#uses=1]
[email protected] = appending global [1 x i8*] [i8* bitcast (void (%struct.callback_data*, i8*)* @set_table_name to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define fastcc void @set_table_name(%struct.callback_data* nocapture %p, i8* %zName) nounwind ssp {
+entry:
+ %0 = getelementptr inbounds %struct.callback_data* %p, i32 0, i32 7 ; <i8**> [#uses=3]
+ %1 = load i8** %0, align 4 ; <i8*> [#uses=2]
+ %2 = icmp eq i8* %1, null ; <i1> [#uses=1]
+ br i1 %2, label %bb1, label %bb
+
+bb: ; preds = %entry
+ free i8* %1
+ store i8* null, i8** %0, align 4
+ br label %bb1
+
+bb1: ; preds = %bb, %entry
+ %3 = icmp eq i8* %zName, null ; <i1> [#uses=1]
+ br i1 %3, label %return, label %bb2
+
+bb2: ; preds = %bb1
+ %4 = load i8* %zName, align 1 ; <i8> [#uses=2]
+ %5 = zext i8 %4 to i32 ; <i32> [#uses=2]
+ %6 = icmp sgt i8 %4, -1 ; <i1> [#uses=1]
+ br i1 %6, label %bb.i.i, label %bb1.i.i
+
+bb.i.i: ; preds = %bb2
+ %7 = getelementptr inbounds %struct._RuneLocale* @_DefaultRuneLocale, i32 0, i32 5, i32 %5 ; <i32*> [#uses=1]
+ %8 = load i32* %7, align 4 ; <i32> [#uses=1]
+ %9 = and i32 %8, 256 ; <i32> [#uses=1]
+ br label %isalpha.exit
+
+bb1.i.i: ; preds = %bb2
+ %10 = tail call i32 @__maskrune(i32 %5, i32 256) nounwind ; <i32> [#uses=1]
+ br label %isalpha.exit
+
+isalpha.exit: ; preds = %bb1.i.i, %bb.i.i
+ %storemerge.in.in.i.i = phi i32 [ %9, %bb.i.i ], [ %10, %bb1.i.i ] ; <i32> [#uses=1]
+ %storemerge.in.i.i = icmp eq i32 %storemerge.in.in.i.i, 0 ; <i1> [#uses=1]
+ br i1 %storemerge.in.i.i, label %bb3, label %bb5
+
+bb3: ; preds = %isalpha.exit
+ %11 = load i8* %zName, align 1 ; <i8> [#uses=2]
+ %12 = icmp eq i8 %11, 95 ; <i1> [#uses=1]
+ br i1 %12, label %bb5, label %bb12.preheader
+
+bb5: ; preds = %bb3, %isalpha.exit
+ %.pre = load i8* %zName, align 1 ; <i8> [#uses=1]
+ br label %bb12.preheader
+
+bb12.preheader: ; preds = %bb5, %bb3
+ %13 = phi i8 [ %.pre, %bb5 ], [ %11, %bb3 ] ; <i8> [#uses=1]
+ %needQuote.1.ph = phi i32 [ 0, %bb5 ], [ 1, %bb3 ] ; <i32> [#uses=2]
+ %14 = icmp eq i8 %13, 0 ; <i1> [#uses=1]
+ br i1 %14, label %bb13, label %bb7
+
+bb7: ; preds = %bb11, %bb12.preheader
+ %i.011 = phi i32 [ %tmp17, %bb11 ], [ 0, %bb12.preheader ] ; <i32> [#uses=2]
+ %n.110 = phi i32 [ %26, %bb11 ], [ 0, %bb12.preheader ] ; <i32> [#uses=3]
+ %needQuote.19 = phi i32 [ %needQuote.0, %bb11 ], [ %needQuote.1.ph, %bb12.preheader ] ; <i32> [#uses=2]
+ %scevgep16 = getelementptr i8* %zName, i32 %i.011 ; <i8*> [#uses=2]
+ %tmp17 = add i32 %i.011, 1 ; <i32> [#uses=2]
+ %scevgep18 = getelementptr i8* %zName, i32 %tmp17 ; <i8*> [#uses=1]
+ %15 = load i8* %scevgep16, align 1 ; <i8> [#uses=2]
+ %16 = zext i8 %15 to i32 ; <i32> [#uses=2]
+ %17 = icmp sgt i8 %15, -1 ; <i1> [#uses=1]
+ br i1 %17, label %bb.i.i2, label %bb1.i.i3
+
+bb.i.i2: ; preds = %bb7
+ %18 = getelementptr inbounds %struct._RuneLocale* @_DefaultRuneLocale, i32 0, i32 5, i32 %16 ; <i32*> [#uses=1]
+ %19 = load i32* %18, align 4 ; <i32> [#uses=1]
+ %20 = and i32 %19, 1280 ; <i32> [#uses=1]
+ br label %isalnum.exit
+
+bb1.i.i3: ; preds = %bb7
+ %21 = tail call i32 @__maskrune(i32 %16, i32 1280) nounwind ; <i32> [#uses=1]
+ br label %isalnum.exit
+
+isalnum.exit: ; preds = %bb1.i.i3, %bb.i.i2
+ %storemerge.in.in.i.i4 = phi i32 [ %20, %bb.i.i2 ], [ %21, %bb1.i.i3 ] ; <i32> [#uses=1]
+ %storemerge.in.i.i5 = icmp eq i32 %storemerge.in.in.i.i4, 0 ; <i1> [#uses=1]
+ br i1 %storemerge.in.i.i5, label %bb8, label %bb11
+
+bb8: ; preds = %isalnum.exit
+ %22 = load i8* %scevgep16, align 1 ; <i8> [#uses=2]
+ %23 = icmp eq i8 %22, 95 ; <i1> [#uses=1]
+ br i1 %23, label %bb11, label %bb9
+
+bb9: ; preds = %bb8
+ %24 = icmp eq i8 %22, 39 ; <i1> [#uses=1]
+ %25 = zext i1 %24 to i32 ; <i32> [#uses=1]
+ %.n.1 = add i32 %n.110, %25 ; <i32> [#uses=1]
+ br label %bb11
+
+bb11: ; preds = %bb9, %bb8, %isalnum.exit
+ %needQuote.0 = phi i32 [ 1, %bb9 ], [ %needQuote.19, %isalnum.exit ], [ %needQuote.19, %bb8 ] ; <i32> [#uses=2]
+ %n.0 = phi i32 [ %.n.1, %bb9 ], [ %n.110, %isalnum.exit ], [ %n.110, %bb8 ] ; <i32> [#uses=1]
+ %26 = add nsw i32 %n.0, 1 ; <i32> [#uses=2]
+ %27 = load i8* %scevgep18, align 1 ; <i8> [#uses=1]
+ %28 = icmp eq i8 %27, 0 ; <i1> [#uses=1]
+ br i1 %28, label %bb13, label %bb7
+
+bb13: ; preds = %bb11, %bb12.preheader
+ %n.1.lcssa = phi i32 [ 0, %bb12.preheader ], [ %26, %bb11 ] ; <i32> [#uses=2]
+ %needQuote.1.lcssa = phi i32 [ %needQuote.1.ph, %bb12.preheader ], [ %needQuote.0, %bb11 ] ; <i32> [#uses=1]
+ %29 = add nsw i32 %n.1.lcssa, 2 ; <i32> [#uses=1]
+ %30 = icmp eq i32 %needQuote.1.lcssa, 0 ; <i1> [#uses=3]
+ %n.1. = select i1 %30, i32 %n.1.lcssa, i32 %29 ; <i32> [#uses=1]
+ %31 = add nsw i32 %n.1., 1 ; <i32> [#uses=1]
+ %32 = malloc i8, i32 %31 ; <i8*> [#uses=7]
+ store i8* %32, i8** %0, align 4
+ %33 = icmp eq i8* %32, null ; <i1> [#uses=1]
+ br i1 %33, label %bb16, label %bb17
+
+bb16: ; preds = %bb13
+ %34 = load %struct.FILE** @__stderrp, align 4 ; <%struct.FILE*> [#uses=1]
+ %35 = bitcast %struct.FILE* %34 to i8* ; <i8*> [#uses=1]
+ %36 = tail call i32 @"\01_fwrite$UNIX2003"(i8* getelementptr inbounds ([16 x i8]* @.str10, i32 0, i32 0), i32 1, i32 15, i8* %35) nounwind ; <i32> [#uses=0]
+ tail call void @exit(i32 1) noreturn nounwind
+ unreachable
+
+bb17: ; preds = %bb13
+ br i1 %30, label %bb23.preheader, label %bb18
+
+bb18: ; preds = %bb17
+ store i8 39, i8* %32, align 4
+ br label %bb23.preheader
+
+bb23.preheader: ; preds = %bb18, %bb17
+ %n.3.ph = phi i32 [ 1, %bb18 ], [ 0, %bb17 ] ; <i32> [#uses=2]
+ %37 = load i8* %zName, align 1 ; <i8> [#uses=1]
+ %38 = icmp eq i8 %37, 0 ; <i1> [#uses=1]
+ br i1 %38, label %bb24, label %bb20
+
+bb20: ; preds = %bb22, %bb23.preheader
+ %storemerge18 = phi i32 [ %tmp, %bb22 ], [ 0, %bb23.preheader ] ; <i32> [#uses=2]
+ %n.37 = phi i32 [ %n.4, %bb22 ], [ %n.3.ph, %bb23.preheader ] ; <i32> [#uses=3]
+ %scevgep = getelementptr i8* %zName, i32 %storemerge18 ; <i8*> [#uses=1]
+ %tmp = add i32 %storemerge18, 1 ; <i32> [#uses=2]
+ %scevgep15 = getelementptr i8* %zName, i32 %tmp ; <i8*> [#uses=1]
+ %39 = load i8* %scevgep, align 1 ; <i8> [#uses=2]
+ %40 = getelementptr inbounds i8* %32, i32 %n.37 ; <i8*> [#uses=1]
+ store i8 %39, i8* %40, align 1
+ %41 = add nsw i32 %n.37, 1 ; <i32> [#uses=2]
+ %42 = icmp eq i8 %39, 39 ; <i1> [#uses=1]
+ br i1 %42, label %bb21, label %bb22
+
+bb21: ; preds = %bb20
+ %43 = getelementptr inbounds i8* %32, i32 %41 ; <i8*> [#uses=1]
+ store i8 39, i8* %43, align 1
+ %44 = add nsw i32 %n.37, 2 ; <i32> [#uses=1]
+ br label %bb22
+
+bb22: ; preds = %bb21, %bb20
+ %n.4 = phi i32 [ %44, %bb21 ], [ %41, %bb20 ] ; <i32> [#uses=2]
+ %45 = load i8* %scevgep15, align 1 ; <i8> [#uses=1]
+ %46 = icmp eq i8 %45, 0 ; <i1> [#uses=1]
+ br i1 %46, label %bb24, label %bb20
+
+bb24: ; preds = %bb22, %bb23.preheader
+ %n.3.lcssa = phi i32 [ %n.3.ph, %bb23.preheader ], [ %n.4, %bb22 ] ; <i32> [#uses=3]
+ br i1 %30, label %bb26, label %bb25
+
+bb25: ; preds = %bb24
+ %47 = getelementptr inbounds i8* %32, i32 %n.3.lcssa ; <i8*> [#uses=1]
+ store i8 39, i8* %47, align 1
+ %48 = add nsw i32 %n.3.lcssa, 1 ; <i32> [#uses=1]
+ br label %bb26
+
+bb26: ; preds = %bb25, %bb24
+ %n.5 = phi i32 [ %48, %bb25 ], [ %n.3.lcssa, %bb24 ] ; <i32> [#uses=1]
+ %49 = getelementptr inbounds i8* %32, i32 %n.5 ; <i8*> [#uses=1]
+ store i8 0, i8* %49, align 1
+ ret void
+
+return: ; preds = %bb1
+ ret void
+}
+
+declare i32 @"\01_fwrite$UNIX2003"(i8*, i32, i32, i8*)
+
+declare void @exit(i32) noreturn nounwind
+
+declare i32 @__maskrune(i32, i32)
diff --git a/test/CodeGen/X86/2009-10-14-LiveVariablesBug.ll b/test/CodeGen/X86/2009-10-14-LiveVariablesBug.ll
new file mode 100644
index 0000000..c1aa17c
--- /dev/null
+++ b/test/CodeGen/X86/2009-10-14-LiveVariablesBug.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin
+; rdar://7299435
+
+@i = internal global i32 0 ; <i32*> [#uses=1]
[email protected] = appending global [1 x i8*] [i8* bitcast (void (i16)* @foo to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define void @foo(i16 signext %source) nounwind ssp {
+entry:
+ %source_addr = alloca i16, align 2 ; <i16*> [#uses=2]
+ store i16 %source, i16* %source_addr
+ store i32 4, i32* @i, align 4
+ call void asm sideeffect "# top of block", "~{dirflag},~{fpsr},~{flags},~{edi},~{esi},~{edx},~{ecx},~{eax}"() nounwind
+ %asmtmp = call i16 asm sideeffect "movw $1, $0", "=={ax},*m,~{dirflag},~{fpsr},~{flags},~{memory}"(i16* %source_addr) nounwind ; <i16> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-10-19-EmergencySpill.ll b/test/CodeGen/X86/2009-10-19-EmergencySpill.ll
new file mode 100644
index 0000000..ba44a2e
--- /dev/null
+++ b/test/CodeGen/X86/2009-10-19-EmergencySpill.ll
@@ -0,0 +1,54 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -disable-fp-elim
+; rdar://7291624
+
+%union.RtreeCoord = type { float }
+%struct.RtreeCell = type { i64, [10 x %union.RtreeCoord] }
+%struct.Rtree = type { i32, i32*, i32, i32, i32, i32, i8*, i8* }
+%struct.RtreeNode = type { i32*, i64, i32, i32, i8*, i32* }
+
+define fastcc void @nodeOverwriteCell(%struct.Rtree* nocapture %pRtree, %struct.RtreeNode* nocapture %pNode, %struct.RtreeCell* nocapture %pCell, i32 %iCell) nounwind ssp {
+entry:
+ %0 = load i8** undef, align 8 ; <i8*> [#uses=2]
+ %1 = load i32* undef, align 8 ; <i32> [#uses=1]
+ %2 = mul i32 %1, %iCell ; <i32> [#uses=1]
+ %3 = add nsw i32 %2, 4 ; <i32> [#uses=1]
+ %4 = sext i32 %3 to i64 ; <i64> [#uses=2]
+ %5 = load i64* null, align 8 ; <i64> [#uses=2]
+ %6 = lshr i64 %5, 48 ; <i64> [#uses=1]
+ %7 = trunc i64 %6 to i8 ; <i8> [#uses=1]
+ store i8 %7, i8* undef, align 1
+ %8 = lshr i64 %5, 8 ; <i64> [#uses=1]
+ %9 = trunc i64 %8 to i8 ; <i8> [#uses=1]
+ %.sum4 = add i64 %4, 6 ; <i64> [#uses=1]
+ %10 = getelementptr inbounds i8* %0, i64 %.sum4 ; <i8*> [#uses=1]
+ store i8 %9, i8* %10, align 1
+ %11 = getelementptr inbounds %struct.Rtree* %pRtree, i64 0, i32 3 ; <i32*> [#uses=1]
+ br i1 undef, label %bb.nph, label %bb2
+
+bb.nph: ; preds = %entry
+ %tmp25 = add i64 %4, 11 ; <i64> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %bb.nph
+ %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i64> [#uses=3]
+ %scevgep = getelementptr %struct.RtreeCell* %pCell, i64 0, i32 1, i64 %indvar ; <%union.RtreeCoord*> [#uses=1]
+ %scevgep12 = bitcast %union.RtreeCoord* %scevgep to i32* ; <i32*> [#uses=1]
+ %tmp = shl i64 %indvar, 2 ; <i64> [#uses=1]
+ %tmp26 = add i64 %tmp, %tmp25 ; <i64> [#uses=1]
+ %scevgep27 = getelementptr i8* %0, i64 %tmp26 ; <i8*> [#uses=1]
+ %12 = load i32* %scevgep12, align 4 ; <i32> [#uses=1]
+ %13 = lshr i32 %12, 24 ; <i32> [#uses=1]
+ %14 = trunc i32 %13 to i8 ; <i8> [#uses=1]
+ store i8 %14, i8* undef, align 1
+ store i8 undef, i8* %scevgep27, align 1
+ %15 = load i32* %11, align 4 ; <i32> [#uses=1]
+ %16 = shl i32 %15, 1 ; <i32> [#uses=1]
+ %17 = icmp sgt i32 %16, undef ; <i1> [#uses=1]
+ %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1]
+ br i1 %17, label %bb, label %bb2
+
+bb2: ; preds = %bb, %entry
+ %18 = getelementptr inbounds %struct.RtreeNode* %pNode, i64 0, i32 3 ; <i32*> [#uses=1]
+ store i32 1, i32* %18, align 4
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll b/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll
new file mode 100644
index 0000000..d7f0c1a
--- /dev/null
+++ b/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll
@@ -0,0 +1,69 @@
+; RUN: llvm-as <%s | llc | FileCheck %s
+; PR 5247
+; check that cmp is not scheduled before the add
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
[email protected] = external constant [45 x i8] ; <[45 x i8]*> [#uses=1]
+@__profiling_callsite_timestamps_live = external global [1216 x i64] ; <[1216 x i64]*> [#uses=2]
+
+define i32 @cl_init(i32 %initoptions) nounwind {
+entry:
+ %retval.i = alloca i32 ; <i32*> [#uses=3]
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ %initoptions.addr = alloca i32 ; <i32*> [#uses=2]
+ tail call void asm sideeffect "cpuid", "~{ax},~{bx},~{cx},~{dx},~{memory},~{dirflag},~{fpsr},~{flags}"() nounwind
+ %0 = tail call i64 @llvm.readcyclecounter() nounwind ; <i64> [#uses=1]
+ store i32 %initoptions, i32* %initoptions.addr
+ %1 = bitcast i32* %initoptions.addr to { }* ; <{ }*> [#uses=0]
+ call void asm sideeffect "cpuid", "~{ax},~{bx},~{cx},~{dx},~{memory},~{dirflag},~{fpsr},~{flags}"() nounwind
+ %2 = call i64 @llvm.readcyclecounter() nounwind ; <i64> [#uses=1]
+ %call.i = call i32 @lt_dlinit() nounwind ; <i32> [#uses=1]
+ %tobool.i = icmp ne i32 %call.i, 0 ; <i1> [#uses=1]
+ br i1 %tobool.i, label %if.then.i, label %if.end.i
+
+if.then.i: ; preds = %entry
+ %call1.i = call i32 @warn_dlerror(i8* getelementptr inbounds ([45 x i8]* @.str76843, i32 0, i32 0)) nounwind ; <i32> [#uses=0]
+ store i32 -1, i32* %retval.i
+ br label %lt_init.exit
+
+if.end.i: ; preds = %entry
+ store i32 0, i32* %retval.i
+ br label %lt_init.exit
+
+lt_init.exit: ; preds = %if.end.i, %if.then.i
+ %3 = load i32* %retval.i ; <i32> [#uses=1]
+ call void asm sideeffect "cpuid", "~{ax},~{bx},~{cx},~{dx},~{memory},~{dirflag},~{fpsr},~{flags}"() nounwind
+ %4 = call i64 @llvm.readcyclecounter() nounwind ; <i64> [#uses=1]
+ %5 = sub i64 %4, %2 ; <i64> [#uses=1]
+ %6 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* getelementptr inbounds ([1216 x i64]* @__profiling_callsite_timestamps_live, i32 0, i32 51), i64 %5) nounwind ; <i64> [#uses=0]
+;CHECK: lock
+;CHECK-NEXT: {{xadd|addq}} %rdx, __profiling_callsite_timestamps_live
+;CHECK-NEXT: cmpl $0,
+;CHECK-NEXT: jne
+ %cmp = icmp eq i32 %3, 0 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %lt_init.exit
+ call void @cli_rarload()
+ br label %if.end
+
+if.end: ; preds = %if.then, %lt_init.exit
+ store i32 0, i32* %retval
+ %7 = load i32* %retval ; <i32> [#uses=1]
+ tail call void asm sideeffect "cpuid", "~{ax},~{bx},~{cx},~{dx},~{memory},~{dirflag},~{fpsr},~{flags}"() nounwind
+ %8 = tail call i64 @llvm.readcyclecounter() nounwind ; <i64> [#uses=1]
+ %9 = sub i64 %8, %0 ; <i64> [#uses=1]
+ %10 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* getelementptr inbounds ([1216 x i64]* @__profiling_callsite_timestamps_live, i32 0, i32 50), i64 %9) ; <i64> [#uses=0]
+ ret i32 %7
+}
+
+declare void @cli_rarload() nounwind
+
+declare i32 @lt_dlinit()
+
+declare i32 @warn_dlerror(i8*) nounwind
+
+declare i64 @llvm.atomic.load.add.i64.p0i64(i64* nocapture, i64) nounwind
+
+declare i64 @llvm.readcyclecounter() nounwind
diff --git a/test/CodeGen/X86/2009-10-25-RewriterBug.ll b/test/CodeGen/X86/2009-10-25-RewriterBug.ll
new file mode 100644
index 0000000..5b4e818
--- /dev/null
+++ b/test/CodeGen/X86/2009-10-25-RewriterBug.ll
@@ -0,0 +1,171 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim
+
+%struct.DecRefPicMarking_t = type { i32, i32, i32, i32, i32, %struct.DecRefPicMarking_t* }
+%struct.FrameStore = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.StorablePicture*, %struct.StorablePicture*, %struct.StorablePicture* }
+%struct.StorablePicture = type { i32, i32, i32, i32, i32, [50 x [6 x [33 x i64]]], [50 x [6 x [33 x i64]]], [50 x [6 x [33 x i64]]], [50 x [6 x [33 x i64]]], i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16**, i16***, i8*, i16**, i8***, i64***, i64***, i16****, i8**, i8**, %struct.StorablePicture*, %struct.StorablePicture*, %struct.StorablePicture*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [2 x i32], i32, %struct.DecRefPicMarking_t*, i32 }
+
+define fastcc void @insert_picture_in_dpb(%struct.FrameStore* nocapture %fs, %struct.StorablePicture* %p) nounwind ssp {
+entry:
+ %0 = getelementptr inbounds %struct.FrameStore* %fs, i64 0, i32 12 ; <%struct.StorablePicture**> [#uses=1]
+ %1 = icmp eq i32 undef, 0 ; <i1> [#uses=1]
+ br i1 %1, label %bb.i, label %bb36.i
+
+bb.i: ; preds = %entry
+ br i1 undef, label %bb3.i, label %bb14.preheader.i
+
+bb3.i: ; preds = %bb.i
+ unreachable
+
+bb14.preheader.i: ; preds = %bb.i
+ br i1 undef, label %bb9.i, label %bb20.preheader.i
+
+bb9.i: ; preds = %bb9.i, %bb14.preheader.i
+ br i1 undef, label %bb9.i, label %bb20.preheader.i
+
+bb20.preheader.i: ; preds = %bb9.i, %bb14.preheader.i
+ br i1 undef, label %bb18.i, label %bb29.preheader.i
+
+bb18.i: ; preds = %bb20.preheader.i
+ unreachable
+
+bb29.preheader.i: ; preds = %bb20.preheader.i
+ br i1 undef, label %bb24.i, label %bb30.i
+
+bb24.i: ; preds = %bb29.preheader.i
+ unreachable
+
+bb30.i: ; preds = %bb29.preheader.i
+ store i32 undef, i32* undef, align 8
+ br label %bb67.preheader.i
+
+bb36.i: ; preds = %entry
+ br label %bb67.preheader.i
+
+bb67.preheader.i: ; preds = %bb36.i, %bb30.i
+ %2 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=2]
+ %3 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=2]
+ %4 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=2]
+ %5 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %6 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %7 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %8 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %9 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %10 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %11 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %12 = phi %struct.StorablePicture* [ null, %bb36.i ], [ undef, %bb30.i ] ; <%struct.StorablePicture*> [#uses=1]
+ br i1 undef, label %bb38.i, label %bb68.i
+
+bb38.i: ; preds = %bb66.i, %bb67.preheader.i
+ %13 = phi %struct.StorablePicture* [ %37, %bb66.i ], [ %2, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %14 = phi %struct.StorablePicture* [ %38, %bb66.i ], [ %3, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %15 = phi %struct.StorablePicture* [ %39, %bb66.i ], [ %4, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %16 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %5, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %17 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %6, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %18 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %7, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %19 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %8, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %20 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %9, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %21 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %10, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %22 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %11, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %23 = phi %struct.StorablePicture* [ %40, %bb66.i ], [ %12, %bb67.preheader.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %indvar248.i = phi i64 [ %indvar.next249.i, %bb66.i ], [ 0, %bb67.preheader.i ] ; <i64> [#uses=3]
+ %storemerge52.i = trunc i64 %indvar248.i to i32 ; <i32> [#uses=1]
+ %24 = getelementptr inbounds %struct.StorablePicture* %23, i64 0, i32 19 ; <i32*> [#uses=0]
+ br i1 undef, label %bb.nph51.i, label %bb66.i
+
+bb.nph51.i: ; preds = %bb38.i
+ %25 = sdiv i32 %storemerge52.i, 8 ; <i32> [#uses=0]
+ br label %bb39.i
+
+bb39.i: ; preds = %bb64.i, %bb.nph51.i
+ %26 = phi %struct.StorablePicture* [ %17, %bb.nph51.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %27 = phi %struct.StorablePicture* [ %18, %bb.nph51.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=0]
+ %28 = phi %struct.StorablePicture* [ %19, %bb.nph51.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=0]
+ %29 = phi %struct.StorablePicture* [ %20, %bb.nph51.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=0]
+ %30 = phi %struct.StorablePicture* [ %21, %bb.nph51.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=0]
+ %31 = phi %struct.StorablePicture* [ %22, %bb.nph51.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=0]
+ br i1 undef, label %bb57.i, label %bb40.i
+
+bb40.i: ; preds = %bb39.i
+ br i1 undef, label %bb57.i, label %bb41.i
+
+bb41.i: ; preds = %bb40.i
+ %storemerge10.i = select i1 undef, i32 2, i32 4 ; <i32> [#uses=1]
+ %32 = zext i32 %storemerge10.i to i64 ; <i64> [#uses=1]
+ br i1 undef, label %bb45.i, label %bb47.i
+
+bb45.i: ; preds = %bb41.i
+ %33 = getelementptr inbounds %struct.StorablePicture* %26, i64 0, i32 5, i64 undef, i64 %32, i64 undef ; <i64*> [#uses=1]
+ %34 = load i64* %33, align 8 ; <i64> [#uses=1]
+ br label %bb47.i
+
+bb47.i: ; preds = %bb45.i, %bb41.i
+ %storemerge11.i = phi i64 [ %34, %bb45.i ], [ 0, %bb41.i ] ; <i64> [#uses=0]
+ %scevgep246.i = getelementptr i64* undef, i64 undef ; <i64*> [#uses=0]
+ br label %bb64.i
+
+bb57.i: ; preds = %bb40.i, %bb39.i
+ br i1 undef, label %bb58.i, label %bb60.i
+
+bb58.i: ; preds = %bb57.i
+ br label %bb60.i
+
+bb60.i: ; preds = %bb58.i, %bb57.i
+ %35 = load i64*** undef, align 8 ; <i64**> [#uses=1]
+ %scevgep256.i = getelementptr i64** %35, i64 %indvar248.i ; <i64**> [#uses=1]
+ %36 = load i64** %scevgep256.i, align 8 ; <i64*> [#uses=1]
+ %scevgep243.i = getelementptr i64* %36, i64 undef ; <i64*> [#uses=1]
+ store i64 -1, i64* %scevgep243.i, align 8
+ br label %bb64.i
+
+bb64.i: ; preds = %bb60.i, %bb47.i
+ br i1 undef, label %bb39.i, label %bb66.i
+
+bb66.i: ; preds = %bb64.i, %bb38.i
+ %37 = phi %struct.StorablePicture* [ %13, %bb38.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=2]
+ %38 = phi %struct.StorablePicture* [ %14, %bb38.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=2]
+ %39 = phi %struct.StorablePicture* [ %15, %bb38.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=2]
+ %40 = phi %struct.StorablePicture* [ %16, %bb38.i ], [ null, %bb64.i ] ; <%struct.StorablePicture*> [#uses=8]
+ %indvar.next249.i = add i64 %indvar248.i, 1 ; <i64> [#uses=1]
+ br i1 undef, label %bb38.i, label %bb68.i
+
+bb68.i: ; preds = %bb66.i, %bb67.preheader.i
+ %41 = phi %struct.StorablePicture* [ %2, %bb67.preheader.i ], [ %37, %bb66.i ] ; <%struct.StorablePicture*> [#uses=0]
+ %42 = phi %struct.StorablePicture* [ %3, %bb67.preheader.i ], [ %38, %bb66.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %43 = phi %struct.StorablePicture* [ %4, %bb67.preheader.i ], [ %39, %bb66.i ] ; <%struct.StorablePicture*> [#uses=1]
+ br i1 undef, label %bb.nph48.i, label %bb108.i
+
+bb.nph48.i: ; preds = %bb68.i
+ br label %bb80.i
+
+bb80.i: ; preds = %bb104.i, %bb.nph48.i
+ %44 = phi %struct.StorablePicture* [ %42, %bb.nph48.i ], [ null, %bb104.i ] ; <%struct.StorablePicture*> [#uses=1]
+ %45 = phi %struct.StorablePicture* [ %43, %bb.nph48.i ], [ null, %bb104.i ] ; <%struct.StorablePicture*> [#uses=1]
+ br i1 undef, label %bb.nph39.i, label %bb104.i
+
+bb.nph39.i: ; preds = %bb80.i
+ br label %bb81.i
+
+bb81.i: ; preds = %bb102.i, %bb.nph39.i
+ %46 = phi %struct.StorablePicture* [ %44, %bb.nph39.i ], [ %48, %bb102.i ] ; <%struct.StorablePicture*> [#uses=0]
+ %47 = phi %struct.StorablePicture* [ %45, %bb.nph39.i ], [ %48, %bb102.i ] ; <%struct.StorablePicture*> [#uses=0]
+ br i1 undef, label %bb83.i, label %bb82.i
+
+bb82.i: ; preds = %bb81.i
+ br i1 undef, label %bb83.i, label %bb101.i
+
+bb83.i: ; preds = %bb82.i, %bb81.i
+ br label %bb102.i
+
+bb101.i: ; preds = %bb82.i
+ br label %bb102.i
+
+bb102.i: ; preds = %bb101.i, %bb83.i
+ %48 = load %struct.StorablePicture** %0, align 8 ; <%struct.StorablePicture*> [#uses=2]
+ br i1 undef, label %bb81.i, label %bb104.i
+
+bb104.i: ; preds = %bb102.i, %bb80.i
+ br label %bb80.i
+
+bb108.i: ; preds = %bb68.i
+ unreachable
+}
diff --git a/test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll b/test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll
new file mode 100644
index 0000000..b5be65f
--- /dev/null
+++ b/test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin11 | FileCheck %s
+; rdar://7362871
+
+define void @bar(i32 %b, i32 %a) nounwind optsize ssp {
+entry:
+; CHECK: leal 15(%rsi), %edi
+; CHECK-NOT: movl
+; CHECK: _foo
+ %0 = add i32 %a, 15 ; <i32> [#uses=1]
+ %1 = zext i32 %0 to i64 ; <i64> [#uses=1]
+ tail call void @foo(i64 %1) nounwind
+ ret void
+}
+
+declare void @foo(i64)
diff --git a/test/CodeGen/X86/2009-11-13-VirtRegRewriterBug.ll b/test/CodeGen/X86/2009-11-13-VirtRegRewriterBug.ll
new file mode 100644
index 0000000..5398eef
--- /dev/null
+++ b/test/CodeGen/X86/2009-11-13-VirtRegRewriterBug.ll
@@ -0,0 +1,133 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -disable-fp-elim
+; rdar://7394770
+
+%struct.JVTLib_100487 = type <{ i8 }>
+
+define i32 @_Z13JVTLib_10335613JVTLib_10266513JVTLib_100579S_S_S_jPhj(i16* nocapture %ResidualX_Array.0, %struct.JVTLib_100487* nocapture byval align 4 %xqp, i16* nocapture %ResidualL_Array.0, i16* %ResidualDCZ_Array.0, i16* nocapture %ResidualACZ_FOArray.0, i32 %useFRextDequant, i8* nocapture %JVTLib_103357, i32 %use_field_scan) ssp {
+bb.nph:
+ %0 = shl i32 undef, 1 ; <i32> [#uses=2]
+ %mask133.masked.masked.masked.masked.masked.masked = or i640 undef, undef ; <i640> [#uses=1]
+ br label %bb
+
+bb: ; preds = %_ZL13JVTLib_105204PKsPK13JVTLib_105184PsPhjS5_j.exit, %bb.nph
+ br i1 undef, label %bb2, label %bb1
+
+bb1: ; preds = %bb
+ br i1 undef, label %bb.i, label %bb1.i
+
+bb2: ; preds = %bb
+ unreachable
+
+bb.i: ; preds = %bb1
+ br label %_ZL13JVTLib_105204PKsPK13JVTLib_105184PsPhjS5_j.exit
+
+bb1.i: ; preds = %bb1
+ br label %_ZL13JVTLib_105204PKsPK13JVTLib_105184PsPhjS5_j.exit
+
+_ZL13JVTLib_105204PKsPK13JVTLib_105184PsPhjS5_j.exit: ; preds = %bb1.i, %bb.i
+ br i1 undef, label %bb5, label %bb
+
+bb5: ; preds = %_ZL13JVTLib_105204PKsPK13JVTLib_105184PsPhjS5_j.exit
+ %mask271.masked.masked.masked.masked.masked.masked.masked = or i256 0, undef ; <i256> [#uses=2]
+ %mask266.masked.masked.masked.masked.masked.masked = or i256 %mask271.masked.masked.masked.masked.masked.masked.masked, undef ; <i256> [#uses=1]
+ %mask241.masked = or i256 undef, undef ; <i256> [#uses=1]
+ %ins237 = or i256 undef, 0 ; <i256> [#uses=1]
+ br i1 undef, label %bb9, label %bb10
+
+bb9: ; preds = %bb5
+ br i1 undef, label %bb12.i, label %_ZL13JVTLib_105255PKsPK13JVTLib_105184Psj.exit
+
+bb12.i: ; preds = %bb9
+ br label %_ZL13JVTLib_105255PKsPK13JVTLib_105184Psj.exit
+
+_ZL13JVTLib_105255PKsPK13JVTLib_105184Psj.exit: ; preds = %bb12.i, %bb9
+ ret i32 undef
+
+bb10: ; preds = %bb5
+ %1 = sext i16 undef to i32 ; <i32> [#uses=1]
+ %2 = sext i16 undef to i32 ; <i32> [#uses=1]
+ %3 = sext i16 undef to i32 ; <i32> [#uses=1]
+ %4 = sext i16 undef to i32 ; <i32> [#uses=1]
+ %5 = sext i16 undef to i32 ; <i32> [#uses=1]
+ %6 = sext i16 undef to i32 ; <i32> [#uses=1]
+ %tmp211 = lshr i256 %mask271.masked.masked.masked.masked.masked.masked.masked, 112 ; <i256> [#uses=0]
+ %7 = sext i16 undef to i32 ; <i32> [#uses=1]
+ %tmp208 = lshr i256 %mask266.masked.masked.masked.masked.masked.masked, 128 ; <i256> [#uses=1]
+ %tmp209 = trunc i256 %tmp208 to i16 ; <i16> [#uses=1]
+ %8 = sext i16 %tmp209 to i32 ; <i32> [#uses=1]
+ %9 = sext i16 undef to i32 ; <i32> [#uses=1]
+ %10 = sext i16 undef to i32 ; <i32> [#uses=1]
+ %tmp193 = lshr i256 %mask241.masked, 208 ; <i256> [#uses=1]
+ %tmp194 = trunc i256 %tmp193 to i16 ; <i16> [#uses=1]
+ %11 = sext i16 %tmp194 to i32 ; <i32> [#uses=1]
+ %tmp187 = lshr i256 %ins237, 240 ; <i256> [#uses=1]
+ %tmp188 = trunc i256 %tmp187 to i16 ; <i16> [#uses=1]
+ %12 = sext i16 %tmp188 to i32 ; <i32> [#uses=1]
+ %13 = add nsw i32 %4, %1 ; <i32> [#uses=1]
+ %14 = add nsw i32 %5, 0 ; <i32> [#uses=1]
+ %15 = add nsw i32 %6, %2 ; <i32> [#uses=1]
+ %16 = add nsw i32 %7, %3 ; <i32> [#uses=1]
+ %17 = add nsw i32 0, %8 ; <i32> [#uses=1]
+ %18 = add nsw i32 %11, %9 ; <i32> [#uses=1]
+ %19 = add nsw i32 0, %10 ; <i32> [#uses=1]
+ %20 = add nsw i32 %12, 0 ; <i32> [#uses=1]
+ %21 = add nsw i32 %17, %13 ; <i32> [#uses=2]
+ %22 = add nsw i32 %18, %14 ; <i32> [#uses=2]
+ %23 = add nsw i32 %19, %15 ; <i32> [#uses=2]
+ %24 = add nsw i32 %20, %16 ; <i32> [#uses=2]
+ %25 = add nsw i32 %22, %21 ; <i32> [#uses=2]
+ %26 = add nsw i32 %24, %23 ; <i32> [#uses=2]
+ %27 = sub i32 %21, %22 ; <i32> [#uses=1]
+ %28 = sub i32 %23, %24 ; <i32> [#uses=1]
+ %29 = add nsw i32 %26, %25 ; <i32> [#uses=1]
+ %30 = sub i32 %25, %26 ; <i32> [#uses=1]
+ %31 = sub i32 %27, %28 ; <i32> [#uses=1]
+ %32 = ashr i32 %29, 1 ; <i32> [#uses=2]
+ %33 = ashr i32 %30, 1 ; <i32> [#uses=2]
+ %34 = ashr i32 %31, 1 ; <i32> [#uses=2]
+ %35 = icmp sgt i32 %32, 32767 ; <i1> [#uses=1]
+ %o0_0.0.i = select i1 %35, i32 32767, i32 %32 ; <i32> [#uses=2]
+ %36 = icmp slt i32 %o0_0.0.i, -32768 ; <i1> [#uses=1]
+ %37 = icmp sgt i32 %33, 32767 ; <i1> [#uses=1]
+ %o1_0.0.i = select i1 %37, i32 32767, i32 %33 ; <i32> [#uses=2]
+ %38 = icmp slt i32 %o1_0.0.i, -32768 ; <i1> [#uses=1]
+ %39 = icmp sgt i32 %34, 32767 ; <i1> [#uses=1]
+ %o2_0.0.i = select i1 %39, i32 32767, i32 %34 ; <i32> [#uses=2]
+ %40 = icmp slt i32 %o2_0.0.i, -32768 ; <i1> [#uses=1]
+ %tmp101 = lshr i640 %mask133.masked.masked.masked.masked.masked.masked, 256 ; <i640> [#uses=1]
+ %41 = trunc i32 %o0_0.0.i to i16 ; <i16> [#uses=1]
+ %tmp358 = select i1 %36, i16 -32768, i16 %41 ; <i16> [#uses=2]
+ %42 = trunc i32 %o1_0.0.i to i16 ; <i16> [#uses=1]
+ %tmp347 = select i1 %38, i16 -32768, i16 %42 ; <i16> [#uses=1]
+ %43 = trunc i32 %o2_0.0.i to i16 ; <i16> [#uses=1]
+ %tmp335 = select i1 %40, i16 -32768, i16 %43 ; <i16> [#uses=1]
+ %44 = icmp sgt i16 %tmp358, -1 ; <i1> [#uses=2]
+ %..i24 = select i1 %44, i16 %tmp358, i16 undef ; <i16> [#uses=1]
+ %45 = icmp sgt i16 %tmp347, -1 ; <i1> [#uses=1]
+ %46 = icmp sgt i16 %tmp335, -1 ; <i1> [#uses=1]
+ %47 = zext i16 %..i24 to i32 ; <i32> [#uses=1]
+ %tmp = trunc i640 %tmp101 to i32 ; <i32> [#uses=1]
+ %48 = and i32 %tmp, 65535 ; <i32> [#uses=2]
+ %49 = mul i32 %47, %48 ; <i32> [#uses=1]
+ %50 = zext i16 undef to i32 ; <i32> [#uses=1]
+ %51 = mul i32 %50, %48 ; <i32> [#uses=1]
+ %52 = add i32 %49, %0 ; <i32> [#uses=1]
+ %53 = add i32 %51, %0 ; <i32> [#uses=1]
+ %54 = lshr i32 %52, undef ; <i32> [#uses=1]
+ %55 = lshr i32 %53, undef ; <i32> [#uses=1]
+ %56 = trunc i32 %54 to i16 ; <i16> [#uses=1]
+ %57 = trunc i32 %55 to i16 ; <i16> [#uses=1]
+ %vs16Out0_0.0.i = select i1 %44, i16 %56, i16 undef ; <i16> [#uses=1]
+ %vs16Out0_4.0.i = select i1 %45, i16 0, i16 undef ; <i16> [#uses=1]
+ %vs16Out1_0.0.i = select i1 %46, i16 %57, i16 undef ; <i16> [#uses=1]
+ br i1 undef, label %bb129.i, label %_ZL13JVTLib_105207PKsPK13JVTLib_105184Psj.exit
+
+bb129.i: ; preds = %bb10
+ br label %_ZL13JVTLib_105207PKsPK13JVTLib_105184Psj.exit
+
+_ZL13JVTLib_105207PKsPK13JVTLib_105184Psj.exit: ; preds = %bb129.i, %bb10
+ %58 = phi i16 [ %vs16Out0_4.0.i, %bb129.i ], [ undef, %bb10 ] ; <i16> [#uses=0]
+ %59 = phi i16 [ undef, %bb129.i ], [ %vs16Out1_0.0.i, %bb10 ] ; <i16> [#uses=0]
+ store i16 %vs16Out0_0.0.i, i16* %ResidualDCZ_Array.0, align 2
+ unreachable
+}
diff --git a/test/CodeGen/X86/2009-11-16-MachineLICM.ll b/test/CodeGen/X86/2009-11-16-MachineLICM.ll
new file mode 100644
index 0000000..8f274df
--- /dev/null
+++ b/test/CodeGen/X86/2009-11-16-MachineLICM.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; rdar://7395200
+
+@g = common global [4 x float] zeroinitializer, align 16 ; <[4 x float]*> [#uses=4]
+
+define void @foo(i32 %n, float* nocapture %x) nounwind ssp {
+entry:
+; CHECK: foo:
+ %0 = icmp sgt i32 %n, 0 ; <i1> [#uses=1]
+ br i1 %0, label %bb.nph, label %return
+
+bb.nph: ; preds = %entry
+; CHECK: movq _g@GOTPCREL(%rip), [[REG:%[a-z]+]]
+ %tmp = zext i32 %n to i64 ; <i64> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %bb.nph
+; CHECK: LBB1_2:
+ %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i64> [#uses=2]
+ %tmp9 = shl i64 %indvar, 2 ; <i64> [#uses=4]
+ %tmp1016 = or i64 %tmp9, 1 ; <i64> [#uses=1]
+ %scevgep = getelementptr float* %x, i64 %tmp1016 ; <float*> [#uses=1]
+ %tmp1117 = or i64 %tmp9, 2 ; <i64> [#uses=1]
+ %scevgep12 = getelementptr float* %x, i64 %tmp1117 ; <float*> [#uses=1]
+ %tmp1318 = or i64 %tmp9, 3 ; <i64> [#uses=1]
+ %scevgep14 = getelementptr float* %x, i64 %tmp1318 ; <float*> [#uses=1]
+ %x_addr.03 = getelementptr float* %x, i64 %tmp9 ; <float*> [#uses=1]
+ %1 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 0), align 16 ; <float> [#uses=1]
+ store float %1, float* %x_addr.03, align 4
+ %2 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 1), align 4 ; <float> [#uses=1]
+ store float %2, float* %scevgep, align 4
+ %3 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 2), align 8 ; <float> [#uses=1]
+ store float %3, float* %scevgep12, align 4
+ %4 = load float* getelementptr inbounds ([4 x float]* @g, i64 0, i64 3), align 4 ; <float> [#uses=1]
+ store float %4, float* %scevgep14, align 4
+ %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=2]
+ %exitcond = icmp eq i64 %indvar.next, %tmp ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll
new file mode 100644
index 0000000..3ce9edb
--- /dev/null
+++ b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; rdar://7396984
+
+@str = private constant [28 x i8] c"xxxxxxxxxxxxxxxxxxxxxxxxxxx\00", align 1
+
+define void @t(i32 %count) ssp nounwind {
+entry:
+; CHECK: t:
+; CHECK: movq ___stack_chk_guard@GOTPCREL(%rip)
+; CHECK: movups L_str(%rip), %xmm0
+ %tmp0 = alloca [60 x i8], align 1
+ %tmp1 = getelementptr inbounds [60 x i8]* %tmp0, i64 0, i64 0
+ br label %bb1
+
+bb1:
+; CHECK: LBB1_1:
+; CHECK: movaps %xmm0, (%rsp)
+ %tmp2 = phi i32 [ %tmp3, %bb1 ], [ 0, %entry ]
+ call void @llvm.memcpy.i64(i8* %tmp1, i8* getelementptr inbounds ([28 x i8]* @str, i64 0, i64 0), i64 28, i32 1)
+ %tmp3 = add i32 %tmp2, 1
+ %tmp4 = icmp eq i32 %tmp3, %count
+ br i1 %tmp4, label %bb2, label %bb1
+
+bb2:
+ ret void
+}
+
+declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind
diff --git a/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll b/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll
new file mode 100644
index 0000000..5c1a2bc
--- /dev/null
+++ b/test/CodeGen/X86/2009-11-17-UpdateTerminator.ll
@@ -0,0 +1,52 @@
+; RUN: llc -O3 < %s
+; This test fails with:
+; Assertion failed: (!B && "UpdateTerminators requires analyzable predecessors!"), function updateTerminator, MachineBasicBlock.cpp, line 255.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-darwin10.2"
+
+%"struct.llvm::InlineAsm::ConstraintInfo" = type { i32, i8, i8, i8, i8, %"struct.std::vector<std::basic_string<char, std::char_traits<char>, std::allocator<char> >,std::allocator<std::basic_string<char, std::char_traits<char>, std::allocator<char> > > >" }
+%"struct.std::_Vector_base<llvm::InlineAsm::ConstraintInfo,std::allocator<llvm::InlineAsm::ConstraintInfo> >" = type { %"struct.std::_Vector_base<llvm::InlineAsm::ConstraintInfo,std::allocator<llvm::InlineAsm::ConstraintInfo> >::_Vector_impl" }
+%"struct.std::_Vector_base<llvm::InlineAsm::ConstraintInfo,std::allocator<llvm::InlineAsm::ConstraintInfo> >::_Vector_impl" = type { %"struct.llvm::InlineAsm::ConstraintInfo"*, %"struct.llvm::InlineAsm::ConstraintInfo"*, %"struct.llvm::InlineAsm::ConstraintInfo"* }
+%"struct.std::_Vector_base<std::basic_string<char, std::char_traits<char>, std::allocator<char> >,std::allocator<std::basic_string<char, std::char_traits<char>, std::allocator<char> > > >" = type { %"struct.std::_Vector_base<std::basic_string<char, std::char_traits<char>, std::allocator<char> >,std::allocator<std::basic_string<char, std::char_traits<char>, std::allocator<char> > > >::_Vector_impl" }
+%"struct.std::_Vector_base<std::basic_string<char, std::char_traits<char>, std::allocator<char> >,std::allocator<std::basic_string<char, std::char_traits<char>, std::allocator<char> > > >::_Vector_impl" = type { %"struct.std::string"*, %"struct.std::string"*, %"struct.std::string"* }
+%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Alloc_hider" = type { i8* }
+%"struct.std::string" = type { %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Alloc_hider" }
+%"struct.std::vector<llvm::InlineAsm::ConstraintInfo,std::allocator<llvm::InlineAsm::ConstraintInfo> >" = type { %"struct.std::_Vector_base<llvm::InlineAsm::ConstraintInfo,std::allocator<llvm::InlineAsm::ConstraintInfo> >" }
+%"struct.std::vector<std::basic_string<char, std::char_traits<char>, std::allocator<char> >,std::allocator<std::basic_string<char, std::char_traits<char>, std::allocator<char> > > >" = type { %"struct.std::_Vector_base<std::basic_string<char, std::char_traits<char>, std::allocator<char> >,std::allocator<std::basic_string<char, std::char_traits<char>, std::allocator<char> > > >" }
+
+define zeroext i8 @_ZN4llvm9InlineAsm14ConstraintInfo5ParseENS_9StringRefERSt6vectorIS1_SaIS1_EE(%"struct.llvm::InlineAsm::ConstraintInfo"* nocapture %this, i64 %Str.0, i64 %Str.1, %"struct.std::vector<llvm::InlineAsm::ConstraintInfo,std::allocator<llvm::InlineAsm::ConstraintInfo> >"* nocapture %ConstraintsSoFar) nounwind ssp align 2 {
+entry:
+ br i1 undef, label %bb56, label %bb27.outer
+
+bb8: ; preds = %bb27.outer108, %bb13
+ switch i8 undef, label %bb27.outer [
+ i8 35, label %bb56
+ i8 37, label %bb14
+ i8 38, label %bb10
+ i8 42, label %bb56
+ ]
+
+bb27.outer: ; preds = %bb8, %entry
+ %I.2.ph = phi i8* [ undef, %entry ], [ %I.2.ph109, %bb8 ] ; <i8*> [#uses=2]
+ br label %bb27.outer108
+
+bb10: ; preds = %bb8
+ %toBool = icmp eq i8 0, 0 ; <i1> [#uses=1]
+ %or.cond = and i1 undef, %toBool ; <i1> [#uses=1]
+ br i1 %or.cond, label %bb13, label %bb56
+
+bb13: ; preds = %bb10
+ br i1 undef, label %bb27.outer108, label %bb8
+
+bb14: ; preds = %bb8
+ ret i8 1
+
+bb27.outer108: ; preds = %bb13, %bb27.outer
+ %I.2.ph109 = getelementptr i8* %I.2.ph, i64 undef ; <i8*> [#uses=1]
+ %scevgep = getelementptr i8* %I.2.ph, i64 undef ; <i8*> [#uses=0]
+ br label %bb8
+
+bb56: ; preds = %bb10, %bb8, %bb8, %entry
+ ret i8 1
+}
diff --git a/test/CodeGen/X86/2009-11-18-TwoAddrKill.ll b/test/CodeGen/X86/2009-11-18-TwoAddrKill.ll
new file mode 100644
index 0000000..0edaa70
--- /dev/null
+++ b/test/CodeGen/X86/2009-11-18-TwoAddrKill.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s
+; PR 5300
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
+target triple = "i386-pc-linux-gnu"
+
+@g_296 = external global i8, align 1 ; <i8*> [#uses=1]
+
+define noalias i8** @func_31(i32** nocapture %int8p_33, i8** nocapture %p_34, i8* nocapture %p_35) nounwind {
+entry:
+ %cmp.i = icmp sgt i16 undef, 234 ; <i1> [#uses=1]
+ %tmp17 = select i1 %cmp.i, i16 undef, i16 0 ; <i16> [#uses=2]
+ %conv8 = trunc i16 %tmp17 to i8 ; <i8> [#uses=3]
+ br i1 undef, label %cond.false.i29, label %land.lhs.true.i
+
+land.lhs.true.i: ; preds = %entry
+ %tobool5.i = icmp eq i32 undef, undef ; <i1> [#uses=1]
+ br i1 %tobool5.i, label %cond.false.i29, label %bar.exit
+
+cond.false.i29: ; preds = %land.lhs.true.i, %entry
+ %tmp = sub i8 0, %conv8 ; <i8> [#uses=1]
+ %mul.i = and i8 %conv8, %tmp ; <i8> [#uses=1]
+ br label %bar.exit
+
+bar.exit: ; preds = %cond.false.i29, %land.lhs.true.i
+ %call1231 = phi i8 [ %mul.i, %cond.false.i29 ], [ %conv8, %land.lhs.true.i ] ; <i8> [#uses=0]
+ %conv21 = trunc i16 %tmp17 to i8 ; <i8> [#uses=1]
+ store i8 %conv21, i8* @g_296
+ ret i8** undef
+}
diff --git a/test/CodeGen/X86/2009-11-25-ImpDefBug.ll b/test/CodeGen/X86/2009-11-25-ImpDefBug.ll
new file mode 100644
index 0000000..7606c0e
--- /dev/null
+++ b/test/CodeGen/X86/2009-11-25-ImpDefBug.ll
@@ -0,0 +1,116 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
+; pr5600
+
+%struct..0__pthread_mutex_s = type { i32, i32, i32, i32, i32, i32, %struct.__pthread_list_t }
+%struct.ASN1ObjHeader = type { i8, %"struct.__gmp_expr<__mpz_struct [1],__mpz_struct [1]>", i64, i32, i32, i32 }
+%struct.ASN1Object = type { i32 (...)**, i32, i32, i64 }
+%struct.ASN1Unit = type { [4 x i32 (%struct.ASN1ObjHeader*, %struct.ASN1Object**)*], %"struct.std::ASN1ObjList" }
+%"struct.__gmp_expr<__mpz_struct [1],__mpz_struct [1]>" = type { [1 x %struct.__mpz_struct] }
+%struct.__mpz_struct = type { i32, i32, i64* }
+%struct.__pthread_list_t = type { %struct.__pthread_list_t*, %struct.__pthread_list_t* }
+%struct.pthread_attr_t = type { i64, [48 x i8] }
+%struct.pthread_mutex_t = type { %struct..0__pthread_mutex_s }
+%struct.pthread_mutexattr_t = type { i32 }
+%"struct.std::ASN1ObjList" = type { %"struct.std::_Vector_base<ASN1Object*,std::allocator<ASN1Object*> >" }
+%"struct.std::_Vector_base<ASN1Object*,std::allocator<ASN1Object*> >" = type { %"struct.std::_Vector_base<ASN1Object*,std::allocator<ASN1Object*> >::_Vector_impl" }
+%"struct.std::_Vector_base<ASN1Object*,std::allocator<ASN1Object*> >::_Vector_impl" = type { %struct.ASN1Object**, %struct.ASN1Object**, %struct.ASN1Object** }
+%struct.xmstream = type { i8*, i64, i64, i64, i8 }
+
+declare void @_ZNSt6vectorIP10ASN1ObjectSaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%"struct.std::ASN1ObjList"* nocapture, i64, %struct.ASN1Object** nocapture)
+
+declare i32 @_Z17LoadObjectFromBERR8xmstreamPP10ASN1ObjectPPF10ASN1StatusP13ASN1ObjHeaderS3_E(%struct.xmstream*, %struct.ASN1Object**, i32 (%struct.ASN1ObjHeader*, %struct.ASN1Object**)**)
+
+define i32 @_ZN8ASN1Unit4loadER8xmstreamjm18ASN1LengthEncoding(%struct.ASN1Unit* %this, %struct.xmstream* nocapture %stream, i32 %numObjects, i64 %size, i32 %lEncoding) {
+entry:
+ br label %meshBB85
+
+bb5: ; preds = %bb13.fragment.cl135, %bb13.fragment.cl, %bb.i.i.bbcl.disp, %bb13.fragment
+ %0 = invoke i32 @_Z17LoadObjectFromBERR8xmstreamPP10ASN1ObjectPPF10ASN1StatusP13ASN1ObjHeaderS3_E(%struct.xmstream* undef, %struct.ASN1Object** undef, i32 (%struct.ASN1ObjHeader*, %struct.ASN1Object**)** undef)
+ to label %meshBB81.bbcl.disp unwind label %lpad ; <i32> [#uses=0]
+
+bb10.fragment: ; preds = %bb13.fragment.bbcl.disp
+ br i1 undef, label %bb1.i.fragment.bbcl.disp, label %bb.i.i.bbcl.disp
+
+bb1.i.fragment: ; preds = %bb1.i.fragment.bbcl.disp
+ invoke void @_ZNSt6vectorIP10ASN1ObjectSaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%"struct.std::ASN1ObjList"* undef, i64 undef, %struct.ASN1Object** undef)
+ to label %meshBB81.bbcl.disp unwind label %lpad
+
+bb13.fragment: ; preds = %bb13.fragment.bbcl.disp
+ br i1 undef, label %meshBB81.bbcl.disp, label %bb5
+
+bb.i4: ; preds = %bb.i4.bbcl.disp, %bb1.i.fragment.bbcl.disp
+ ret i32 undef
+
+bb1.i5: ; preds = %bb.i1
+ ret i32 undef
+
+lpad: ; preds = %bb1.i.fragment.cl, %bb1.i.fragment, %bb5
+ %.SV10.phi807 = phi i8* [ undef, %bb1.i.fragment.cl ], [ undef, %bb1.i.fragment ], [ undef, %bb5 ] ; <i8*> [#uses=1]
+ %1 = load i8* %.SV10.phi807, align 8 ; <i8> [#uses=0]
+ br i1 undef, label %meshBB81.bbcl.disp, label %bb13.fragment.bbcl.disp
+
+bb.i1: ; preds = %bb.i.i.bbcl.disp
+ br i1 undef, label %meshBB81.bbcl.disp, label %bb1.i5
+
+meshBB81: ; preds = %meshBB81.bbcl.disp, %bb.i.i.bbcl.disp
+ br i1 undef, label %meshBB81.bbcl.disp, label %bb.i4.bbcl.disp
+
+meshBB85: ; preds = %meshBB81.bbcl.disp, %bb.i4.bbcl.disp, %bb1.i.fragment.bbcl.disp, %bb.i.i.bbcl.disp, %entry
+ br i1 undef, label %meshBB81.bbcl.disp, label %bb13.fragment.bbcl.disp
+
+bb.i.i.bbcl.disp: ; preds = %bb10.fragment
+ switch i8 undef, label %meshBB85 [
+ i8 123, label %bb.i1
+ i8 97, label %bb5
+ i8 44, label %meshBB81
+ i8 1, label %meshBB81.cl
+ i8 51, label %meshBB81.cl141
+ ]
+
+bb1.i.fragment.cl: ; preds = %bb1.i.fragment.bbcl.disp
+ invoke void @_ZNSt6vectorIP10ASN1ObjectSaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%"struct.std::ASN1ObjList"* undef, i64 undef, %struct.ASN1Object** undef)
+ to label %meshBB81.bbcl.disp unwind label %lpad
+
+bb1.i.fragment.bbcl.disp: ; preds = %bb10.fragment
+ switch i8 undef, label %bb.i4 [
+ i8 97, label %bb1.i.fragment
+ i8 7, label %bb1.i.fragment.cl
+ i8 35, label %bb.i4.cl
+ i8 77, label %meshBB85
+ ]
+
+bb13.fragment.cl: ; preds = %bb13.fragment.bbcl.disp
+ br i1 undef, label %meshBB81.bbcl.disp, label %bb5
+
+bb13.fragment.cl135: ; preds = %bb13.fragment.bbcl.disp
+ br i1 undef, label %meshBB81.bbcl.disp, label %bb5
+
+bb13.fragment.bbcl.disp: ; preds = %meshBB85, %lpad
+ switch i8 undef, label %bb10.fragment [
+ i8 67, label %bb13.fragment.cl
+ i8 108, label %bb13.fragment
+ i8 58, label %bb13.fragment.cl135
+ ]
+
+bb.i4.cl: ; preds = %bb.i4.bbcl.disp, %bb1.i.fragment.bbcl.disp
+ ret i32 undef
+
+bb.i4.bbcl.disp: ; preds = %meshBB81.cl141, %meshBB81.cl, %meshBB81
+ switch i8 undef, label %bb.i4 [
+ i8 35, label %bb.i4.cl
+ i8 77, label %meshBB85
+ ]
+
+meshBB81.cl: ; preds = %meshBB81.bbcl.disp, %bb.i.i.bbcl.disp
+ br i1 undef, label %meshBB81.bbcl.disp, label %bb.i4.bbcl.disp
+
+meshBB81.cl141: ; preds = %meshBB81.bbcl.disp, %bb.i.i.bbcl.disp
+ br i1 undef, label %meshBB81.bbcl.disp, label %bb.i4.bbcl.disp
+
+meshBB81.bbcl.disp: ; preds = %meshBB81.cl141, %meshBB81.cl, %bb13.fragment.cl135, %bb13.fragment.cl, %bb1.i.fragment.cl, %meshBB85, %meshBB81, %bb.i1, %lpad, %bb13.fragment, %bb1.i.fragment, %bb5
+ switch i8 undef, label %meshBB85 [
+ i8 44, label %meshBB81
+ i8 1, label %meshBB81.cl
+ i8 51, label %meshBB81.cl141
+ ]
+}
diff --git a/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll b/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
new file mode 100644
index 0000000..1e7a418
--- /dev/null
+++ b/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; pr5391
+
+define void @t() nounwind ssp {
+entry:
+; CHECK: t:
+; CHECK: movl %ecx, %eax
+; CHECK: %eax = foo (%eax, %ecx)
+ %b = alloca i32 ; <i32*> [#uses=2]
+ %a = alloca i32 ; <i32*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %0 = load i32* %b, align 4 ; <i32> [#uses=1]
+ %1 = load i32* %b, align 4 ; <i32> [#uses=1]
+ %asmtmp = call i32 asm "$0 = foo ($1, $2)", "=&{ax},%0,r,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1) nounwind ; <i32> [#uses=1]
+ store i32 %asmtmp, i32* %a
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define void @t2() nounwind ssp {
+entry:
+; CHECK: t2:
+; CHECK: movl %eax, %ecx
+; CHECK: %ecx = foo (%ecx, %eax)
+ %b = alloca i32 ; <i32*> [#uses=2]
+ %a = alloca i32 ; <i32*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %0 = load i32* %b, align 4 ; <i32> [#uses=1]
+ %1 = load i32* %b, align 4 ; <i32> [#uses=1]
+ %asmtmp = call i32 asm "$0 = foo ($1, $2)", "=&r,%0,r,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1) nounwind ; <i32> [#uses=1]
+ store i32 %asmtmp, i32* %a
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll b/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll
new file mode 100644
index 0000000..f7ba661
--- /dev/null
+++ b/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll
@@ -0,0 +1,63 @@
+; RUN: llc -relocation-model=pic < %s | FileCheck %s
+; PR5723
+target datalayout = "e-p:64:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+%0 = type { [1 x i64] }
+%link = type { %0* }
+%test = type { i32, %link }
+
+@data = global [2 x i64] zeroinitializer, align 64 ; <[2 x i64]*> [#uses=1]
+@ptr = linkonce thread_local global [1 x i64] [i64 ptrtoint ([2 x i64]* @data to i64)], align 64 ; <[1 x i64]*> [#uses=1]
+@link_ptr = linkonce thread_local global [1 x i64] zeroinitializer, align 64 ; <[1 x i64]*> [#uses=1]
+@_dm_my_pe = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0]
+@_dm_pes_in_prog = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0]
+@_dm_npes_div_mult = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0]
+@_dm_npes_div_shift = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0]
+@_dm_pe_addr_loc = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0]
+@_dm_offset_addr_mask = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0]
+
+define void @leaf() nounwind {
+; CHECK: leaf:
+; CHECK-NOT: -8(%rsp)
+; CHECK: leaq link_ptr@TLSGD
+; CHECK: call __tls_get_addr@PLT
+"file foo2.c, line 14, bb1":
+ %p = alloca %test*, align 8 ; <%test**> [#uses=4]
+ br label %"file foo2.c, line 14, bb2"
+
+"file foo2.c, line 14, bb2": ; preds = %"file foo2.c, line 14, bb1"
+ br label %"@CFE_debug_label_0"
+
+"@CFE_debug_label_0": ; preds = %"file foo2.c, line 14, bb2"
+ %r = load %test** bitcast ([1 x i64]* @ptr to %test**), align 8 ; <%test*> [#uses=1]
+ store %test* %r, %test** %p, align 8
+ br label %"@CFE_debug_label_2"
+
+"@CFE_debug_label_2": ; preds = %"@CFE_debug_label_0"
+ %r1 = load %link** bitcast ([1 x i64]* @link_ptr to %link**), align 8 ; <%link*> [#uses=1]
+ %r2 = load %test** %p, align 8 ; <%test*> [#uses=1]
+ %r3 = ptrtoint %test* %r2 to i64 ; <i64> [#uses=1]
+ %r4 = inttoptr i64 %r3 to %link** ; <%link**> [#uses=1]
+ %r5 = getelementptr %link** %r4, i64 1 ; <%link**> [#uses=1]
+ store %link* %r1, %link** %r5, align 8
+ br label %"@CFE_debug_label_3"
+
+"@CFE_debug_label_3": ; preds = %"@CFE_debug_label_2"
+ %r6 = load %test** %p, align 8 ; <%test*> [#uses=1]
+ %r7 = ptrtoint %test* %r6 to i64 ; <i64> [#uses=1]
+ %r8 = inttoptr i64 %r7 to %link* ; <%link*> [#uses=1]
+ %r9 = getelementptr %link* %r8, i64 1 ; <%link*> [#uses=1]
+ store %link* %r9, %link** bitcast ([1 x i64]* @link_ptr to %link**), align 8
+ br label %"@CFE_debug_label_4"
+
+"@CFE_debug_label_4": ; preds = %"@CFE_debug_label_3"
+ %r10 = load %test** %p, align 8 ; <%test*> [#uses=1]
+ %r11 = ptrtoint %test* %r10 to i64 ; <i64> [#uses=1]
+ %r12 = inttoptr i64 %r11 to i32* ; <i32*> [#uses=1]
+ store i32 1, i32* %r12, align 4
+ br label %"@CFE_debug_label_5"
+
+"@CFE_debug_label_5": ; preds = %"@CFE_debug_label_4"
+ ret void
+}
diff --git a/test/CodeGen/X86/2009-12-12-CoalescerBug.ll b/test/CodeGen/X86/2009-12-12-CoalescerBug.ll
new file mode 100644
index 0000000..4e8f5fd
--- /dev/null
+++ b/test/CodeGen/X86/2009-12-12-CoalescerBug.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
+
+define i32 @do_loop(i32* nocapture %sdp, i32* nocapture %ddp, i8* %mdp, i8* nocapture %cdp, i32 %w) nounwind readonly optsize ssp {
+entry:
+ br label %bb
+
+bb: ; preds = %bb5, %entry
+ %mask.1.in = load i8* undef, align 1 ; <i8> [#uses=3]
+ %0 = icmp eq i8 %mask.1.in, 0 ; <i1> [#uses=1]
+ br i1 %0, label %bb5, label %bb1
+
+bb1: ; preds = %bb
+ br i1 undef, label %bb2, label %bb3
+
+bb2: ; preds = %bb1
+; CHECK: %bb2
+; CHECK: movb %ch, %al
+ %1 = zext i8 %mask.1.in to i32 ; <i32> [#uses=1]
+ %2 = zext i8 undef to i32 ; <i32> [#uses=1]
+ %3 = mul i32 %2, %1 ; <i32> [#uses=1]
+ %4 = add i32 %3, 1 ; <i32> [#uses=1]
+ %5 = add i32 %4, 0 ; <i32> [#uses=1]
+ %6 = lshr i32 %5, 8 ; <i32> [#uses=1]
+ %retval12.i = trunc i32 %6 to i8 ; <i8> [#uses=1]
+ br label %bb3
+
+bb3: ; preds = %bb2, %bb1
+ %mask.0.in = phi i8 [ %retval12.i, %bb2 ], [ %mask.1.in, %bb1 ] ; <i8> [#uses=1]
+ %7 = icmp eq i8 %mask.0.in, 0 ; <i1> [#uses=1]
+ br i1 %7, label %bb5, label %bb4
+
+bb4: ; preds = %bb3
+ br label %bb5
+
+bb5: ; preds = %bb4, %bb3, %bb
+ br i1 undef, label %bb6, label %bb
+
+bb6: ; preds = %bb5
+ ret i32 undef
+}
diff --git a/test/CodeGen/X86/20090313-signext.ll b/test/CodeGen/X86/20090313-signext.ll
new file mode 100644
index 0000000..de930d5
--- /dev/null
+++ b/test/CodeGen/X86/20090313-signext.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86-64 -relocation-model=pic > %t
+; RUN: grep {movswl %ax, %edi} %t
+; RUN: grep {movw (%rax), %ax} %t
+; XFAIL: *
+
+@x = common global i16 0
+
+define signext i16 @f() nounwind {
+entry:
+ %0 = tail call signext i16 @h() nounwind
+ %1 = sext i16 %0 to i32
+ tail call void @g(i32 %1) nounwind
+ %2 = load i16* @x, align 2
+ ret i16 %2
+}
+
+declare signext i16 @h()
+
+declare void @g(i32)
diff --git a/test/CodeGen/X86/2010-01-05-ZExt-Shl.ll b/test/CodeGen/X86/2010-01-05-ZExt-Shl.ll
new file mode 100644
index 0000000..e7004e2
--- /dev/null
+++ b/test/CodeGen/X86/2010-01-05-ZExt-Shl.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86-64
+; <rdar://problem/7499313>
+target triple = "i686-apple-darwin8"
+
+declare void @func2(i16 zeroext)
+
+define void @func1() nounwind {
+entry:
+ %t1 = icmp ne i8 undef, 0
+ %t2 = icmp eq i8 undef, 14
+ %t3 = and i1 %t1, %t2
+ %t4 = select i1 %t3, i16 0, i16 128
+ call void @func2(i16 zeroext %t4) nounwind
+ ret void
+}
diff --git a/test/CodeGen/X86/2010-01-07-ISelBug.ll b/test/CodeGen/X86/2010-01-07-ISelBug.ll
new file mode 100644
index 0000000..081fab7
--- /dev/null
+++ b/test/CodeGen/X86/2010-01-07-ISelBug.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10
+; rdar://r7519827
+
+define i32 @t() nounwind ssp {
+entry:
+ br label %if.end.i11
+
+if.end.i11: ; preds = %lor.lhs.false.i10, %lor.lhs.false.i10, %lor.lhs.false.i10
+ br i1 undef, label %for.body161, label %for.end197
+
+for.body161: ; preds = %if.end.i11
+ br label %for.end197
+
+for.end197: ; preds = %for.body161, %if.end.i11
+ %mlucEntry.4 = phi i96 [ undef, %for.body161 ], [ undef, %if.end.i11 ] ; <i96> [#uses=2]
+ store i96 %mlucEntry.4, i96* undef, align 8
+ %tmp172 = lshr i96 %mlucEntry.4, 64 ; <i96> [#uses=1]
+ %tmp173 = trunc i96 %tmp172 to i32 ; <i32> [#uses=1]
+ %tmp1.i1.i = call i32 @llvm.bswap.i32(i32 %tmp173) nounwind ; <i32> [#uses=1]
+ store i32 %tmp1.i1.i, i32* undef, align 8
+ unreachable
+
+if.then283: ; preds = %lor.lhs.false.i10, %do.end105, %for.end
+ ret i32 undef
+}
+
+declare i32 @llvm.bswap.i32(i32) nounwind readnone
diff --git a/test/CodeGen/X86/2010-01-07-UAMemFeature.ll b/test/CodeGen/X86/2010-01-07-UAMemFeature.ll
new file mode 100644
index 0000000..3728f15
--- /dev/null
+++ b/test/CodeGen/X86/2010-01-07-UAMemFeature.ll
@@ -0,0 +1,11 @@
+; RUN: llc -mcpu=yonah -mattr=vector-unaligned-mem -march=x86 < %s | FileCheck %s
+; CHECK: addps (
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define <4 x float> @foo(<4 x float>* %P, <4 x float> %In) nounwind {
+ %A = load <4 x float>* %P, align 4
+ %B = add <4 x float> %A, %In
+ ret <4 x float> %B
+}
diff --git a/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll b/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
new file mode 100644
index 0000000..172e1c7
--- /dev/null
+++ b/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
+; rdar://r7512579
+
+; PHI defs in the atomic loop should be used by the add / adc
+; instructions. They should not be dead.
+
+define void @t(i64* nocapture %p) nounwind ssp {
+entry:
+; CHECK: t:
+; CHECK: movl $1
+; CHECK: movl (%ebp), %eax
+; CHECK: movl 4(%ebp), %edx
+; CHECK: LBB1_1:
+; CHECK-NOT: movl $1
+; CHECK-NOT: movl $0
+; CHECK: addl
+; CHECK: adcl
+; CHECK: lock
+; CHECK: cmpxchg8b
+; CHECK: jne
+ tail call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+ %0 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 1) ; <i64> [#uses=0]
+ tail call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+ ret void
+}
+
+declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind
+
+declare i64 @llvm.atomic.load.add.i64.p0i64(i64* nocapture, i64) nounwind
diff --git a/test/CodeGen/X86/2010-01-11-ExtraPHIArg.ll b/test/CodeGen/X86/2010-01-11-ExtraPHIArg.ll
new file mode 100644
index 0000000..db98eef
--- /dev/null
+++ b/test/CodeGen/X86/2010-01-11-ExtraPHIArg.ll
@@ -0,0 +1,97 @@
+; RUN: llc -verify-machineinstrs < %s
+;
+; The lowering of a switch combined with constand folding would leave spurious extra arguments on a PHI instruction.
+;
+target triple = "x86_64-apple-darwin10"
+
+define void @foo() {
+ br label %cond_true813.i
+
+cond_true813.i: ; preds = %0
+ br i1 false, label %cond_true818.i, label %cond_next1146.i
+
+cond_true818.i: ; preds = %cond_true813.i
+ br i1 false, label %recog_memoized.exit52, label %cond_next1146.i
+
+recog_memoized.exit52: ; preds = %cond_true818.i
+ switch i32 0, label %bb886.i.preheader [
+ i32 0, label %bb907.i
+ i32 44, label %bb866.i
+ i32 103, label %bb874.i
+ i32 114, label %bb874.i
+ ]
+
+bb857.i: ; preds = %bb886.i, %bb866.i
+ %tmp862.i494.24 = phi i8* [ null, %bb866.i ], [ %tmp862.i494.26, %bb886.i ] ; <i8*> [#uses=1]
+ switch i32 0, label %bb886.i.preheader [
+ i32 0, label %bb907.i
+ i32 44, label %bb866.i
+ i32 103, label %bb874.i
+ i32 114, label %bb874.i
+ ]
+
+bb866.i.loopexit: ; preds = %bb874.i
+ br label %bb866.i
+
+bb866.i.loopexit31: ; preds = %cond_true903.i
+ br label %bb866.i
+
+bb866.i: ; preds = %bb866.i.loopexit31, %bb866.i.loopexit, %bb857.i, %recog_memoized.exit52
+ br i1 false, label %bb907.i, label %bb857.i
+
+bb874.i.preheader.loopexit: ; preds = %cond_true903.i, %cond_true903.i
+ ret void
+
+bb874.i: ; preds = %bb857.i, %bb857.i, %recog_memoized.exit52, %recog_memoized.exit52
+ switch i32 0, label %bb886.i.preheader.loopexit [
+ i32 0, label %bb907.i
+ i32 44, label %bb866.i.loopexit
+ i32 103, label %bb874.i.backedge
+ i32 114, label %bb874.i.backedge
+ ]
+
+bb874.i.backedge: ; preds = %bb874.i, %bb874.i
+ ret void
+
+bb886.i.preheader.loopexit: ; preds = %bb874.i
+ ret void
+
+bb886.i.preheader: ; preds = %bb857.i, %recog_memoized.exit52
+ %tmp862.i494.26 = phi i8* [ undef, %recog_memoized.exit52 ], [ %tmp862.i494.24, %bb857.i ] ; <i8*> [#uses=1]
+ br label %bb886.i
+
+bb886.i: ; preds = %cond_true903.i, %bb886.i.preheader
+ br i1 false, label %bb857.i, label %cond_true903.i
+
+cond_true903.i: ; preds = %bb886.i
+ switch i32 0, label %bb886.i [
+ i32 0, label %bb907.i
+ i32 44, label %bb866.i.loopexit31
+ i32 103, label %bb874.i.preheader.loopexit
+ i32 114, label %bb874.i.preheader.loopexit
+ ]
+
+bb907.i: ; preds = %cond_true903.i, %bb874.i, %bb866.i, %bb857.i, %recog_memoized.exit52
+ br i1 false, label %cond_next1146.i, label %cond_true910.i
+
+cond_true910.i: ; preds = %bb907.i
+ ret void
+
+cond_next1146.i: ; preds = %bb907.i, %cond_true818.i, %cond_true813.i
+ ret void
+
+bb2060.i: ; No predecessors!
+ br i1 false, label %cond_true2064.i, label %bb2067.i
+
+cond_true2064.i: ; preds = %bb2060.i
+ unreachable
+
+bb2067.i: ; preds = %bb2060.i
+ ret void
+
+cond_next3473: ; No predecessors!
+ ret void
+
+cond_next3521: ; No predecessors!
+ ret void
+}
diff --git a/test/CodeGen/X86/2010-01-13-OptExtBug.ll b/test/CodeGen/X86/2010-01-13-OptExtBug.ll
new file mode 100644
index 0000000..d49e2a8
--- /dev/null
+++ b/test/CodeGen/X86/2010-01-13-OptExtBug.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu
+; PR6027
+
+%class.OlsonTimeZone = type { i16, i32*, i8*, i16 }
+
+define void @XX(%class.OlsonTimeZone* %this) align 2 {
+entry:
+ %call = tail call i8* @_Z15uprv_malloc_4_2v()
+ %0 = bitcast i8* %call to double*
+ %tmp = getelementptr inbounds %class.OlsonTimeZone* %this, i32 0, i32 3
+ %tmp2 = load i16* %tmp
+ %tmp525 = getelementptr inbounds %class.OlsonTimeZone* %this, i32 0, i32 0
+ %tmp626 = load i16* %tmp525
+ %cmp27 = icmp slt i16 %tmp2, %tmp626
+ br i1 %cmp27, label %bb.nph, label %for.end
+
+for.cond:
+ %tmp6 = load i16* %tmp5
+ %cmp = icmp slt i16 %inc, %tmp6
+ %indvar.next = add i32 %indvar, 1
+ br i1 %cmp, label %for.body, label %for.end
+
+bb.nph:
+ %tmp10 = getelementptr inbounds %class.OlsonTimeZone* %this, i32 0, i32 2
+ %tmp17 = getelementptr inbounds %class.OlsonTimeZone* %this, i32 0, i32 1
+ %tmp5 = getelementptr inbounds %class.OlsonTimeZone* %this, i32 0, i32 0
+ %tmp29 = sext i16 %tmp2 to i32
+ %tmp31 = add i16 %tmp2, 1
+ %tmp32 = zext i16 %tmp31 to i32
+ br label %for.body
+
+for.body:
+ %indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %for.cond ]
+ %tmp30 = add i32 %indvar, %tmp29
+ %tmp33 = add i32 %indvar, %tmp32
+ %inc = trunc i32 %tmp33 to i16
+ %tmp11 = load i8** %tmp10
+ %arrayidx = getelementptr i8* %tmp11, i32 %tmp30
+ %tmp12 = load i8* %arrayidx
+ br label %for.cond
+
+for.end:
+ ret void
+}
+
+declare i8* @_Z15uprv_malloc_4_2v()
diff --git a/test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll b/test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll
new file mode 100644
index 0000000..5d96e4a
--- /dev/null
+++ b/test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=x86-64
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @numvec_(i32* noalias %ncelet, i32* noalias %ncel, i32* noalias %nfac, i32* noalias %nfabor, i32* noalias %lregis, i32* noalias %irveci, i32* noalias %irvecb, [0 x [2 x i32]]* noalias %ifacel, [0 x i32]* noalias %ifabor, [0 x i32]* noalias %inumfi, [0 x i32]* noalias %inumfb, [1 x i32]* noalias %iworkf, [0 x i32]* noalias %ismbs) {
+"file bug754399.f90, line 1, bb1":
+ %r1037 = bitcast <2 x double> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=1]
+ br label %"file bug754399.f90, line 184, in inner vector loop at depth 0, bb164"
+
+"file bug754399.f90, line 184, in inner vector loop at depth 0, bb164": ; preds = %"file bug754399.f90, line 184, in inner vector loop at depth 0, bb164", %"file bug754399.f90, line 1, bb1"
+ %tmp641 = add i64 0, 48 ; <i64> [#uses=1]
+ %tmp641642 = inttoptr i64 %tmp641 to <4 x i32>* ; <<4 x i32>*> [#uses=1]
+ %r1258 = load <4 x i32>* %tmp641642, align 4 ; <<4 x i32>> [#uses=2]
+ %r1295 = extractelement <4 x i32> %r1258, i32 3 ; <i32> [#uses=1]
+ %r1296 = sext i32 %r1295 to i64 ; <i64> [#uses=1]
+ %r1297 = add i64 %r1296, -1 ; <i64> [#uses=1]
+ %r1298183 = getelementptr [0 x i32]* %ismbs, i64 0, i64 %r1297 ; <i32*> [#uses=1]
+ %r1298184 = load i32* %r1298183, align 4 ; <i32> [#uses=1]
+ %r1301 = extractelement <4 x i32> %r1037, i32 3 ; <i32> [#uses=1]
+ %r1302 = mul i32 %r1298184, %r1301 ; <i32> [#uses=1]
+ %r1306 = insertelement <4 x i32> zeroinitializer, i32 %r1302, i32 3 ; <<4 x i32>> [#uses=1]
+ %r1321 = add <4 x i32> %r1306, %r1258 ; <<4 x i32>> [#uses=1]
+ %tmp643 = add i64 0, 48 ; <i64> [#uses=1]
+ %tmp643644 = inttoptr i64 %tmp643 to <4 x i32>* ; <<4 x i32>*> [#uses=1]
+ store <4 x i32> %r1321, <4 x i32>* %tmp643644, align 4
+ br label %"file bug754399.f90, line 184, in inner vector loop at depth 0, bb164"
+}
diff --git a/test/CodeGen/X86/2010-01-19-OptExtBug.ll b/test/CodeGen/X86/2010-01-19-OptExtBug.ll
new file mode 100644
index 0000000..cd8960b
--- /dev/null
+++ b/test/CodeGen/X86/2010-01-19-OptExtBug.ll
@@ -0,0 +1,57 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -relocation-model=pic -disable-fp-elim -stats |& not grep ext-opt
+
+define fastcc i8* @S_scan_str(i8* %start, i32 %keep_quoted, i32 %keep_delims) nounwind ssp {
+entry:
+ switch i8 undef, label %bb6 [
+ i8 9, label %bb5
+ i8 32, label %bb5
+ i8 10, label %bb5
+ i8 13, label %bb5
+ i8 12, label %bb5
+ ]
+
+bb5: ; preds = %entry, %entry, %entry, %entry, %entry
+ br label %bb6
+
+bb6: ; preds = %bb5, %entry
+ br i1 undef, label %bb7, label %bb9
+
+bb7: ; preds = %bb6
+ unreachable
+
+bb9: ; preds = %bb6
+ %0 = load i8* undef, align 1 ; <i8> [#uses=3]
+ br i1 undef, label %bb12, label %bb10
+
+bb10: ; preds = %bb9
+ br i1 undef, label %bb12, label %bb11
+
+bb11: ; preds = %bb10
+ unreachable
+
+bb12: ; preds = %bb10, %bb9
+ br i1 undef, label %bb13, label %bb14
+
+bb13: ; preds = %bb12
+ store i8 %0, i8* undef, align 1
+ %1 = zext i8 %0 to i32 ; <i32> [#uses=1]
+ br label %bb18
+
+bb14: ; preds = %bb12
+ br label %bb18
+
+bb18: ; preds = %bb14, %bb13
+ %termcode.0 = phi i32 [ %1, %bb13 ], [ undef, %bb14 ] ; <i32> [#uses=2]
+ %2 = icmp eq i8 %0, 0 ; <i1> [#uses=1]
+ br i1 %2, label %bb21, label %bb19
+
+bb19: ; preds = %bb18
+ br i1 undef, label %bb21, label %bb20
+
+bb20: ; preds = %bb19
+ br label %bb21
+
+bb21: ; preds = %bb20, %bb19, %bb18
+ %termcode.1 = phi i32 [ %termcode.0, %bb18 ], [ %termcode.0, %bb19 ], [ undef, %bb20 ] ; <i32> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/X86/2010-02-01-TaillCallCrash.ll b/test/CodeGen/X86/2010-02-01-TaillCallCrash.ll
new file mode 100644
index 0000000..2751174
--- /dev/null
+++ b/test/CodeGen/X86/2010-02-01-TaillCallCrash.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
+; PR6196
+
+%"char[]" = type [1 x i8]
+
[email protected] = external constant %"char[]", align 1 ; <%"char[]"*> [#uses=1]
+
+define i32 @regex_subst() nounwind {
+entry:
+ %0 = tail call i32 bitcast (%"char[]"* @.str to i32 (i32)*)(i32 0) nounwind ; <i32> [#uses=1]
+ ret i32 %0
+}
diff --git a/test/CodeGen/X86/2010-02-03-DualUndef.ll b/test/CodeGen/X86/2010-02-03-DualUndef.ll
new file mode 100644
index 0000000..d116ecc
--- /dev/null
+++ b/test/CodeGen/X86/2010-02-03-DualUndef.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=x86-64
+; PR6086
+define fastcc void @prepOutput() nounwind {
+bb: ; preds = %output.exit
+ br label %bb.i1
+
+bb.i1: ; preds = %bb7.i, %bb
+ br i1 undef, label %bb7.i, label %bb.nph.i
+
+bb.nph.i: ; preds = %bb.i1
+ br label %bb3.i
+
+bb3.i: ; preds = %bb5.i6, %bb.nph.i
+ %tmp10.i = trunc i64 undef to i32 ; <i32> [#uses=1]
+ br i1 undef, label %bb4.i, label %bb5.i6
+
+bb4.i: ; preds = %bb3.i
+ br label %bb5.i6
+
+bb5.i6: ; preds = %bb4.i, %bb3.i
+ %0 = phi i32 [ undef, %bb4.i ], [ undef, %bb3.i ] ; <i32> [#uses=1]
+ %1 = icmp slt i32 %0, %tmp10.i ; <i1> [#uses=1]
+ br i1 %1, label %bb7.i, label %bb3.i
+
+bb7.i: ; preds = %bb5.i6, %bb.i1
+ br label %bb.i1
+}
diff --git a/test/CodeGen/X86/2010-02-04-SchedulerBug.ll b/test/CodeGen/X86/2010-02-04-SchedulerBug.ll
new file mode 100644
index 0000000..c966e21d
--- /dev/null
+++ b/test/CodeGen/X86/2010-02-04-SchedulerBug.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin11
+; rdar://7604000
+
+%struct.a_t = type { i8*, i64*, i8*, i32, i32, i64*, i64*, i64* }
+%struct.b_t = type { i32, i32, i32, i32, i64, i64, i64, i64 }
+
+define void @t(i32 %cNum, i64 %max) nounwind optsize ssp noimplicitfloat {
+entry:
+ %0 = load %struct.b_t** null, align 4 ; <%struct.b_t*> [#uses=1]
+ %1 = getelementptr inbounds %struct.b_t* %0, i32 %cNum, i32 5 ; <i64*> [#uses=1]
+ %2 = load i64* %1, align 4 ; <i64> [#uses=1]
+ %3 = icmp ult i64 %2, %max ; <i1> [#uses=1]
+ %4 = getelementptr inbounds %struct.a_t* null, i32 0, i32 7 ; <i64**> [#uses=1]
+ %5 = load i64** %4, align 4 ; <i64*> [#uses=0]
+ %6 = load i64* null, align 4 ; <i64> [#uses=1]
+ br i1 %3, label %bb2, label %bb
+
+bb: ; preds = %entry
+ br label %bb3
+
+bb2: ; preds = %entry
+ %7 = or i64 %6, undef ; <i64> [#uses=1]
+ br label %bb3
+
+bb3: ; preds = %bb2, %bb
+ %misc_enables.0 = phi i64 [ undef, %bb ], [ %7, %bb2 ] ; <i64> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/X86/3addr-16bit.ll b/test/CodeGen/X86/3addr-16bit.ll
new file mode 100644
index 0000000..c51247a
--- /dev/null
+++ b/test/CodeGen/X86/3addr-16bit.ll
@@ -0,0 +1,95 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -asm-verbose=false | FileCheck %s -check-prefix=64BIT
+; rdar://7329206
+
+; In 32-bit the partial register stall would degrade performance.
+
+define zeroext i16 @t1(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
+entry:
+; 32BIT: t1:
+; 32BIT: movw 20(%esp), %ax
+; 32BIT-NOT: movw %ax, %cx
+; 32BIT: leal 1(%eax), %ecx
+
+; 64BIT: t1:
+; 64BIT-NOT: movw %si, %ax
+; 64BIT: leal 1(%rsi), %eax
+ %0 = icmp eq i16 %k, %c ; <i1> [#uses=1]
+ %1 = add i16 %k, 1 ; <i16> [#uses=3]
+ br i1 %0, label %bb, label %bb1
+
+bb: ; preds = %entry
+ tail call void @foo(i16 zeroext %1) nounwind
+ ret i16 %1
+
+bb1: ; preds = %entry
+ ret i16 %1
+}
+
+define zeroext i16 @t2(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
+entry:
+; 32BIT: t2:
+; 32BIT: movw 20(%esp), %ax
+; 32BIT-NOT: movw %ax, %cx
+; 32BIT: leal -1(%eax), %ecx
+
+; 64BIT: t2:
+; 64BIT-NOT: movw %si, %ax
+; 64BIT: leal -1(%rsi), %eax
+ %0 = icmp eq i16 %k, %c ; <i1> [#uses=1]
+ %1 = add i16 %k, -1 ; <i16> [#uses=3]
+ br i1 %0, label %bb, label %bb1
+
+bb: ; preds = %entry
+ tail call void @foo(i16 zeroext %1) nounwind
+ ret i16 %1
+
+bb1: ; preds = %entry
+ ret i16 %1
+}
+
+declare void @foo(i16 zeroext)
+
+define zeroext i16 @t3(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
+entry:
+; 32BIT: t3:
+; 32BIT: movw 20(%esp), %ax
+; 32BIT-NOT: movw %ax, %cx
+; 32BIT: leal 2(%eax), %ecx
+
+; 64BIT: t3:
+; 64BIT-NOT: movw %si, %ax
+; 64BIT: leal 2(%rsi), %eax
+ %0 = add i16 %k, 2 ; <i16> [#uses=3]
+ %1 = icmp eq i16 %k, %c ; <i1> [#uses=1]
+ br i1 %1, label %bb, label %bb1
+
+bb: ; preds = %entry
+ tail call void @foo(i16 zeroext %0) nounwind
+ ret i16 %0
+
+bb1: ; preds = %entry
+ ret i16 %0
+}
+
+define zeroext i16 @t4(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
+entry:
+; 32BIT: t4:
+; 32BIT: movw 16(%esp), %ax
+; 32BIT: movw 20(%esp), %cx
+; 32BIT-NOT: movw %cx, %dx
+; 32BIT: leal (%ecx,%eax), %edx
+
+; 64BIT: t4:
+; 64BIT-NOT: movw %si, %ax
+; 64BIT: leal (%rsi,%rdi), %eax
+ %0 = add i16 %k, %c ; <i16> [#uses=3]
+ %1 = icmp eq i16 %k, %c ; <i1> [#uses=1]
+ br i1 %1, label %bb, label %bb1
+
+bb: ; preds = %entry
+ tail call void @foo(i16 zeroext %0) nounwind
+ ret i16 %0
+
+bb1: ; preds = %entry
+ ret i16 %0
+}
diff --git a/test/CodeGen/X86/3addr-or.ll b/test/CodeGen/X86/3addr-or.ll
new file mode 100644
index 0000000..30a1f36
--- /dev/null
+++ b/test/CodeGen/X86/3addr-or.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; rdar://7527734
+
+define i32 @test(i32 %x) nounwind readnone ssp {
+entry:
+; CHECK: test:
+; CHECK: leal 3(%rdi), %eax
+ %0 = shl i32 %x, 5 ; <i32> [#uses=1]
+ %1 = or i32 %0, 3 ; <i32> [#uses=1]
+ ret i32 %1
+}
+
+define i64 @test2(i8 %A, i8 %B) nounwind {
+; CHECK: test2:
+; CHECK: shrq $4
+; CHECK-NOT: movq
+; CHECK-NOT: orq
+; CHECK: leaq
+; CHECK: ret
+ %C = zext i8 %A to i64 ; <i64> [#uses=1]
+ %D = shl i64 %C, 4 ; <i64> [#uses=1]
+ %E = and i64 %D, 48 ; <i64> [#uses=1]
+ %F = zext i8 %B to i64 ; <i64> [#uses=1]
+ %G = lshr i64 %F, 4 ; <i64> [#uses=1]
+ %H = or i64 %G, %E ; <i64> [#uses=1]
+ ret i64 %H
+}
diff --git a/test/CodeGen/X86/Atomics-32.ll b/test/CodeGen/X86/Atomics-32.ll
new file mode 100644
index 0000000..0e9b73e
--- /dev/null
+++ b/test/CodeGen/X86/Atomics-32.ll
@@ -0,0 +1,818 @@
+; RUN: llc < %s -march=x86 > %t
+;; Note the 64-bit variants are not supported yet (in 32-bit mode).
+; ModuleID = 'Atomics.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+@sc = common global i8 0 ; <i8*> [#uses=52]
+@uc = common global i8 0 ; <i8*> [#uses=100]
+@ss = common global i16 0 ; <i16*> [#uses=15]
+@us = common global i16 0 ; <i16*> [#uses=15]
+@si = common global i32 0 ; <i32*> [#uses=15]
+@ui = common global i32 0 ; <i32*> [#uses=23]
+@sl = common global i32 0 ; <i32*> [#uses=15]
+@ul = common global i32 0 ; <i32*> [#uses=15]
+
+define void @test_op_ignore() nounwind {
+entry:
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:0 [#uses=0]
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:1 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 1 ) ; <i16>:3 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 1 ) ; <i16>:5 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 1 ) ; <i32>:7 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 1 ) ; <i32>:9 [#uses=0]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:10 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %10, i32 1 ) ; <i32>:11 [#uses=0]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:12 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %12, i32 1 ) ; <i32>:13 [#uses=0]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:14 [#uses=0]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:15 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:16 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 1 ) ; <i16>:17 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:18 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 1 ) ; <i16>:19 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:20 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 1 ) ; <i32>:21 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:22 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 1 ) ; <i32>:23 [#uses=0]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:24 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %24, i32 1 ) ; <i32>:25 [#uses=0]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:26 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %26, i32 1 ) ; <i32>:27 [#uses=0]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:28 [#uses=0]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:29 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:30 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 1 ) ; <i16>:31 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:32 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 1 ) ; <i16>:33 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:34 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 1 ) ; <i32>:35 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:36 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 1 ) ; <i32>:37 [#uses=0]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:38 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %38, i32 1 ) ; <i32>:39 [#uses=0]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:40 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %40, i32 1 ) ; <i32>:41 [#uses=0]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:42 [#uses=0]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:43 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:44 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 1 ) ; <i16>:45 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:46 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 1 ) ; <i16>:47 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:48 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 1 ) ; <i32>:49 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:50 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 1 ) ; <i32>:51 [#uses=0]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:52 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %52, i32 1 ) ; <i32>:53 [#uses=0]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:54 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %54, i32 1 ) ; <i32>:55 [#uses=0]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:56 [#uses=0]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:57 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:58 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 1 ) ; <i16>:59 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:60 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 1 ) ; <i16>:61 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:62 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 1 ) ; <i32>:63 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:64 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 1 ) ; <i32>:65 [#uses=0]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:66 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %66, i32 1 ) ; <i32>:67 [#uses=0]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:68 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %68, i32 1 ) ; <i32>:69 [#uses=0]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:70 [#uses=0]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:71 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:72 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 1 ) ; <i16>:73 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:74 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 1 ) ; <i16>:75 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:76 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 1 ) ; <i32>:77 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:78 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 1 ) ; <i32>:79 [#uses=0]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:80 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %80, i32 1 ) ; <i32>:81 [#uses=0]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:82 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %82, i32 1 ) ; <i32>:83 [#uses=0]
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.add.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind
+
+declare i8 @llvm.atomic.load.sub.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.sub.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind
+
+declare i8 @llvm.atomic.load.or.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.or.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind
+
+declare i8 @llvm.atomic.load.xor.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.xor.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind
+
+declare i8 @llvm.atomic.load.and.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.and.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind
+
+declare i8 @llvm.atomic.load.nand.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.nand.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.nand.i32.p0i32(i32*, i32) nounwind
+
+define void @test_fetch_and_op() nounwind {
+entry:
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:0 [#uses=1]
+ store i8 %0, i8* @sc, align 1
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:1 [#uses=1]
+ store i8 %1, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 11 ) ; <i16>:3 [#uses=1]
+ store i16 %3, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 11 ) ; <i16>:5 [#uses=1]
+ store i16 %5, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 11 ) ; <i32>:7 [#uses=1]
+ store i32 %7, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 11 ) ; <i32>:9 [#uses=1]
+ store i32 %9, i32* @ui, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:10 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %10, i32 11 ) ; <i32>:11 [#uses=1]
+ store i32 %11, i32* @sl, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:12 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %12, i32 11 ) ; <i32>:13 [#uses=1]
+ store i32 %13, i32* @ul, align 4
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:14 [#uses=1]
+ store i8 %14, i8* @sc, align 1
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:15 [#uses=1]
+ store i8 %15, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:16 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 11 ) ; <i16>:17 [#uses=1]
+ store i16 %17, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:18 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 11 ) ; <i16>:19 [#uses=1]
+ store i16 %19, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:20 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 11 ) ; <i32>:21 [#uses=1]
+ store i32 %21, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:22 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 11 ) ; <i32>:23 [#uses=1]
+ store i32 %23, i32* @ui, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:24 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %24, i32 11 ) ; <i32>:25 [#uses=1]
+ store i32 %25, i32* @sl, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:26 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %26, i32 11 ) ; <i32>:27 [#uses=1]
+ store i32 %27, i32* @ul, align 4
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:28 [#uses=1]
+ store i8 %28, i8* @sc, align 1
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:29 [#uses=1]
+ store i8 %29, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:30 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 11 ) ; <i16>:31 [#uses=1]
+ store i16 %31, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:32 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 11 ) ; <i16>:33 [#uses=1]
+ store i16 %33, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:34 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 11 ) ; <i32>:35 [#uses=1]
+ store i32 %35, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:36 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 11 ) ; <i32>:37 [#uses=1]
+ store i32 %37, i32* @ui, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:38 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %38, i32 11 ) ; <i32>:39 [#uses=1]
+ store i32 %39, i32* @sl, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:40 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %40, i32 11 ) ; <i32>:41 [#uses=1]
+ store i32 %41, i32* @ul, align 4
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:42 [#uses=1]
+ store i8 %42, i8* @sc, align 1
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:43 [#uses=1]
+ store i8 %43, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:44 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 11 ) ; <i16>:45 [#uses=1]
+ store i16 %45, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:46 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 11 ) ; <i16>:47 [#uses=1]
+ store i16 %47, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:48 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 11 ) ; <i32>:49 [#uses=1]
+ store i32 %49, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:50 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 11 ) ; <i32>:51 [#uses=1]
+ store i32 %51, i32* @ui, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:52 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %52, i32 11 ) ; <i32>:53 [#uses=1]
+ store i32 %53, i32* @sl, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:54 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %54, i32 11 ) ; <i32>:55 [#uses=1]
+ store i32 %55, i32* @ul, align 4
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:56 [#uses=1]
+ store i8 %56, i8* @sc, align 1
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:57 [#uses=1]
+ store i8 %57, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:58 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 11 ) ; <i16>:59 [#uses=1]
+ store i16 %59, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:60 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 11 ) ; <i16>:61 [#uses=1]
+ store i16 %61, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:62 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 11 ) ; <i32>:63 [#uses=1]
+ store i32 %63, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:64 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 11 ) ; <i32>:65 [#uses=1]
+ store i32 %65, i32* @ui, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:66 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %66, i32 11 ) ; <i32>:67 [#uses=1]
+ store i32 %67, i32* @sl, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:68 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %68, i32 11 ) ; <i32>:69 [#uses=1]
+ store i32 %69, i32* @ul, align 4
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:70 [#uses=1]
+ store i8 %70, i8* @sc, align 1
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:71 [#uses=1]
+ store i8 %71, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:72 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 11 ) ; <i16>:73 [#uses=1]
+ store i16 %73, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:74 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 11 ) ; <i16>:75 [#uses=1]
+ store i16 %75, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:76 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 11 ) ; <i32>:77 [#uses=1]
+ store i32 %77, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:78 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 11 ) ; <i32>:79 [#uses=1]
+ store i32 %79, i32* @ui, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:80 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %80, i32 11 ) ; <i32>:81 [#uses=1]
+ store i32 %81, i32* @sl, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:82 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %82, i32 11 ) ; <i32>:83 [#uses=1]
+ store i32 %83, i32* @ul, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define void @test_op_and_fetch() nounwind {
+entry:
+ load i8* @uc, align 1 ; <i8>:0 [#uses=1]
+ zext i8 %0 to i32 ; <i32>:1 [#uses=1]
+ trunc i32 %1 to i8 ; <i8>:2 [#uses=2]
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 %2 ) ; <i8>:3 [#uses=1]
+ add i8 %3, %2 ; <i8>:4 [#uses=1]
+ store i8 %4, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:5 [#uses=1]
+ zext i8 %5 to i32 ; <i32>:6 [#uses=1]
+ trunc i32 %6 to i8 ; <i8>:7 [#uses=2]
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 %7 ) ; <i8>:8 [#uses=1]
+ add i8 %8, %7 ; <i8>:9 [#uses=1]
+ store i8 %9, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:10 [#uses=1]
+ zext i8 %10 to i32 ; <i32>:11 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:12 [#uses=1]
+ trunc i32 %11 to i16 ; <i16>:13 [#uses=2]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %12, i16 %13 ) ; <i16>:14 [#uses=1]
+ add i16 %14, %13 ; <i16>:15 [#uses=1]
+ store i16 %15, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:16 [#uses=1]
+ zext i8 %16 to i32 ; <i32>:17 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:18 [#uses=1]
+ trunc i32 %17 to i16 ; <i16>:19 [#uses=2]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %18, i16 %19 ) ; <i16>:20 [#uses=1]
+ add i16 %20, %19 ; <i16>:21 [#uses=1]
+ store i16 %21, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:22 [#uses=1]
+ zext i8 %22 to i32 ; <i32>:23 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:24 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %24, i32 %23 ) ; <i32>:25 [#uses=1]
+ add i32 %25, %23 ; <i32>:26 [#uses=1]
+ store i32 %26, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:27 [#uses=1]
+ zext i8 %27 to i32 ; <i32>:28 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:29 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %29, i32 %28 ) ; <i32>:30 [#uses=1]
+ add i32 %30, %28 ; <i32>:31 [#uses=1]
+ store i32 %31, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:32 [#uses=1]
+ zext i8 %32 to i32 ; <i32>:33 [#uses=2]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:34 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %34, i32 %33 ) ; <i32>:35 [#uses=1]
+ add i32 %35, %33 ; <i32>:36 [#uses=1]
+ store i32 %36, i32* @sl, align 4
+ load i8* @uc, align 1 ; <i8>:37 [#uses=1]
+ zext i8 %37 to i32 ; <i32>:38 [#uses=2]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:39 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %39, i32 %38 ) ; <i32>:40 [#uses=1]
+ add i32 %40, %38 ; <i32>:41 [#uses=1]
+ store i32 %41, i32* @ul, align 4
+ load i8* @uc, align 1 ; <i8>:42 [#uses=1]
+ zext i8 %42 to i32 ; <i32>:43 [#uses=1]
+ trunc i32 %43 to i8 ; <i8>:44 [#uses=2]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 %44 ) ; <i8>:45 [#uses=1]
+ sub i8 %45, %44 ; <i8>:46 [#uses=1]
+ store i8 %46, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:47 [#uses=1]
+ zext i8 %47 to i32 ; <i32>:48 [#uses=1]
+ trunc i32 %48 to i8 ; <i8>:49 [#uses=2]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 %49 ) ; <i8>:50 [#uses=1]
+ sub i8 %50, %49 ; <i8>:51 [#uses=1]
+ store i8 %51, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:52 [#uses=1]
+ zext i8 %52 to i32 ; <i32>:53 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:54 [#uses=1]
+ trunc i32 %53 to i16 ; <i16>:55 [#uses=2]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %54, i16 %55 ) ; <i16>:56 [#uses=1]
+ sub i16 %56, %55 ; <i16>:57 [#uses=1]
+ store i16 %57, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:58 [#uses=1]
+ zext i8 %58 to i32 ; <i32>:59 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:60 [#uses=1]
+ trunc i32 %59 to i16 ; <i16>:61 [#uses=2]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %60, i16 %61 ) ; <i16>:62 [#uses=1]
+ sub i16 %62, %61 ; <i16>:63 [#uses=1]
+ store i16 %63, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:64 [#uses=1]
+ zext i8 %64 to i32 ; <i32>:65 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:66 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %66, i32 %65 ) ; <i32>:67 [#uses=1]
+ sub i32 %67, %65 ; <i32>:68 [#uses=1]
+ store i32 %68, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:69 [#uses=1]
+ zext i8 %69 to i32 ; <i32>:70 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:71 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %71, i32 %70 ) ; <i32>:72 [#uses=1]
+ sub i32 %72, %70 ; <i32>:73 [#uses=1]
+ store i32 %73, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:74 [#uses=1]
+ zext i8 %74 to i32 ; <i32>:75 [#uses=2]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:76 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %76, i32 %75 ) ; <i32>:77 [#uses=1]
+ sub i32 %77, %75 ; <i32>:78 [#uses=1]
+ store i32 %78, i32* @sl, align 4
+ load i8* @uc, align 1 ; <i8>:79 [#uses=1]
+ zext i8 %79 to i32 ; <i32>:80 [#uses=2]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:81 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %81, i32 %80 ) ; <i32>:82 [#uses=1]
+ sub i32 %82, %80 ; <i32>:83 [#uses=1]
+ store i32 %83, i32* @ul, align 4
+ load i8* @uc, align 1 ; <i8>:84 [#uses=1]
+ zext i8 %84 to i32 ; <i32>:85 [#uses=1]
+ trunc i32 %85 to i8 ; <i8>:86 [#uses=2]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 %86 ) ; <i8>:87 [#uses=1]
+ or i8 %87, %86 ; <i8>:88 [#uses=1]
+ store i8 %88, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:89 [#uses=1]
+ zext i8 %89 to i32 ; <i32>:90 [#uses=1]
+ trunc i32 %90 to i8 ; <i8>:91 [#uses=2]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 %91 ) ; <i8>:92 [#uses=1]
+ or i8 %92, %91 ; <i8>:93 [#uses=1]
+ store i8 %93, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:94 [#uses=1]
+ zext i8 %94 to i32 ; <i32>:95 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:96 [#uses=1]
+ trunc i32 %95 to i16 ; <i16>:97 [#uses=2]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %96, i16 %97 ) ; <i16>:98 [#uses=1]
+ or i16 %98, %97 ; <i16>:99 [#uses=1]
+ store i16 %99, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:100 [#uses=1]
+ zext i8 %100 to i32 ; <i32>:101 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:102 [#uses=1]
+ trunc i32 %101 to i16 ; <i16>:103 [#uses=2]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %102, i16 %103 ) ; <i16>:104 [#uses=1]
+ or i16 %104, %103 ; <i16>:105 [#uses=1]
+ store i16 %105, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:106 [#uses=1]
+ zext i8 %106 to i32 ; <i32>:107 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:108 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %108, i32 %107 ) ; <i32>:109 [#uses=1]
+ or i32 %109, %107 ; <i32>:110 [#uses=1]
+ store i32 %110, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:111 [#uses=1]
+ zext i8 %111 to i32 ; <i32>:112 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:113 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %113, i32 %112 ) ; <i32>:114 [#uses=1]
+ or i32 %114, %112 ; <i32>:115 [#uses=1]
+ store i32 %115, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:116 [#uses=1]
+ zext i8 %116 to i32 ; <i32>:117 [#uses=2]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:118 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %118, i32 %117 ) ; <i32>:119 [#uses=1]
+ or i32 %119, %117 ; <i32>:120 [#uses=1]
+ store i32 %120, i32* @sl, align 4
+ load i8* @uc, align 1 ; <i8>:121 [#uses=1]
+ zext i8 %121 to i32 ; <i32>:122 [#uses=2]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:123 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %123, i32 %122 ) ; <i32>:124 [#uses=1]
+ or i32 %124, %122 ; <i32>:125 [#uses=1]
+ store i32 %125, i32* @ul, align 4
+ load i8* @uc, align 1 ; <i8>:126 [#uses=1]
+ zext i8 %126 to i32 ; <i32>:127 [#uses=1]
+ trunc i32 %127 to i8 ; <i8>:128 [#uses=2]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 %128 ) ; <i8>:129 [#uses=1]
+ xor i8 %129, %128 ; <i8>:130 [#uses=1]
+ store i8 %130, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:131 [#uses=1]
+ zext i8 %131 to i32 ; <i32>:132 [#uses=1]
+ trunc i32 %132 to i8 ; <i8>:133 [#uses=2]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 %133 ) ; <i8>:134 [#uses=1]
+ xor i8 %134, %133 ; <i8>:135 [#uses=1]
+ store i8 %135, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:136 [#uses=1]
+ zext i8 %136 to i32 ; <i32>:137 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:138 [#uses=1]
+ trunc i32 %137 to i16 ; <i16>:139 [#uses=2]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %138, i16 %139 ) ; <i16>:140 [#uses=1]
+ xor i16 %140, %139 ; <i16>:141 [#uses=1]
+ store i16 %141, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:142 [#uses=1]
+ zext i8 %142 to i32 ; <i32>:143 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:144 [#uses=1]
+ trunc i32 %143 to i16 ; <i16>:145 [#uses=2]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %144, i16 %145 ) ; <i16>:146 [#uses=1]
+ xor i16 %146, %145 ; <i16>:147 [#uses=1]
+ store i16 %147, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:148 [#uses=1]
+ zext i8 %148 to i32 ; <i32>:149 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:150 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %150, i32 %149 ) ; <i32>:151 [#uses=1]
+ xor i32 %151, %149 ; <i32>:152 [#uses=1]
+ store i32 %152, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:153 [#uses=1]
+ zext i8 %153 to i32 ; <i32>:154 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:155 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %155, i32 %154 ) ; <i32>:156 [#uses=1]
+ xor i32 %156, %154 ; <i32>:157 [#uses=1]
+ store i32 %157, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:158 [#uses=1]
+ zext i8 %158 to i32 ; <i32>:159 [#uses=2]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:160 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %160, i32 %159 ) ; <i32>:161 [#uses=1]
+ xor i32 %161, %159 ; <i32>:162 [#uses=1]
+ store i32 %162, i32* @sl, align 4
+ load i8* @uc, align 1 ; <i8>:163 [#uses=1]
+ zext i8 %163 to i32 ; <i32>:164 [#uses=2]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:165 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %165, i32 %164 ) ; <i32>:166 [#uses=1]
+ xor i32 %166, %164 ; <i32>:167 [#uses=1]
+ store i32 %167, i32* @ul, align 4
+ load i8* @uc, align 1 ; <i8>:168 [#uses=1]
+ zext i8 %168 to i32 ; <i32>:169 [#uses=1]
+ trunc i32 %169 to i8 ; <i8>:170 [#uses=2]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 %170 ) ; <i8>:171 [#uses=1]
+ and i8 %171, %170 ; <i8>:172 [#uses=1]
+ store i8 %172, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:173 [#uses=1]
+ zext i8 %173 to i32 ; <i32>:174 [#uses=1]
+ trunc i32 %174 to i8 ; <i8>:175 [#uses=2]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 %175 ) ; <i8>:176 [#uses=1]
+ and i8 %176, %175 ; <i8>:177 [#uses=1]
+ store i8 %177, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:178 [#uses=1]
+ zext i8 %178 to i32 ; <i32>:179 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:180 [#uses=1]
+ trunc i32 %179 to i16 ; <i16>:181 [#uses=2]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %180, i16 %181 ) ; <i16>:182 [#uses=1]
+ and i16 %182, %181 ; <i16>:183 [#uses=1]
+ store i16 %183, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:184 [#uses=1]
+ zext i8 %184 to i32 ; <i32>:185 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:186 [#uses=1]
+ trunc i32 %185 to i16 ; <i16>:187 [#uses=2]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %186, i16 %187 ) ; <i16>:188 [#uses=1]
+ and i16 %188, %187 ; <i16>:189 [#uses=1]
+ store i16 %189, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:190 [#uses=1]
+ zext i8 %190 to i32 ; <i32>:191 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:192 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %192, i32 %191 ) ; <i32>:193 [#uses=1]
+ and i32 %193, %191 ; <i32>:194 [#uses=1]
+ store i32 %194, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:195 [#uses=1]
+ zext i8 %195 to i32 ; <i32>:196 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:197 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %197, i32 %196 ) ; <i32>:198 [#uses=1]
+ and i32 %198, %196 ; <i32>:199 [#uses=1]
+ store i32 %199, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:200 [#uses=1]
+ zext i8 %200 to i32 ; <i32>:201 [#uses=2]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:202 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %202, i32 %201 ) ; <i32>:203 [#uses=1]
+ and i32 %203, %201 ; <i32>:204 [#uses=1]
+ store i32 %204, i32* @sl, align 4
+ load i8* @uc, align 1 ; <i8>:205 [#uses=1]
+ zext i8 %205 to i32 ; <i32>:206 [#uses=2]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:207 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %207, i32 %206 ) ; <i32>:208 [#uses=1]
+ and i32 %208, %206 ; <i32>:209 [#uses=1]
+ store i32 %209, i32* @ul, align 4
+ load i8* @uc, align 1 ; <i8>:210 [#uses=1]
+ zext i8 %210 to i32 ; <i32>:211 [#uses=1]
+ trunc i32 %211 to i8 ; <i8>:212 [#uses=2]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 %212 ) ; <i8>:213 [#uses=1]
+ xor i8 %213, -1 ; <i8>:214 [#uses=1]
+ and i8 %214, %212 ; <i8>:215 [#uses=1]
+ store i8 %215, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:216 [#uses=1]
+ zext i8 %216 to i32 ; <i32>:217 [#uses=1]
+ trunc i32 %217 to i8 ; <i8>:218 [#uses=2]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 %218 ) ; <i8>:219 [#uses=1]
+ xor i8 %219, -1 ; <i8>:220 [#uses=1]
+ and i8 %220, %218 ; <i8>:221 [#uses=1]
+ store i8 %221, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:222 [#uses=1]
+ zext i8 %222 to i32 ; <i32>:223 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:224 [#uses=1]
+ trunc i32 %223 to i16 ; <i16>:225 [#uses=2]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %224, i16 %225 ) ; <i16>:226 [#uses=1]
+ xor i16 %226, -1 ; <i16>:227 [#uses=1]
+ and i16 %227, %225 ; <i16>:228 [#uses=1]
+ store i16 %228, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:229 [#uses=1]
+ zext i8 %229 to i32 ; <i32>:230 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:231 [#uses=1]
+ trunc i32 %230 to i16 ; <i16>:232 [#uses=2]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %231, i16 %232 ) ; <i16>:233 [#uses=1]
+ xor i16 %233, -1 ; <i16>:234 [#uses=1]
+ and i16 %234, %232 ; <i16>:235 [#uses=1]
+ store i16 %235, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:236 [#uses=1]
+ zext i8 %236 to i32 ; <i32>:237 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:238 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %238, i32 %237 ) ; <i32>:239 [#uses=1]
+ xor i32 %239, -1 ; <i32>:240 [#uses=1]
+ and i32 %240, %237 ; <i32>:241 [#uses=1]
+ store i32 %241, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:242 [#uses=1]
+ zext i8 %242 to i32 ; <i32>:243 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:244 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %244, i32 %243 ) ; <i32>:245 [#uses=1]
+ xor i32 %245, -1 ; <i32>:246 [#uses=1]
+ and i32 %246, %243 ; <i32>:247 [#uses=1]
+ store i32 %247, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:248 [#uses=1]
+ zext i8 %248 to i32 ; <i32>:249 [#uses=2]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:250 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %250, i32 %249 ) ; <i32>:251 [#uses=1]
+ xor i32 %251, -1 ; <i32>:252 [#uses=1]
+ and i32 %252, %249 ; <i32>:253 [#uses=1]
+ store i32 %253, i32* @sl, align 4
+ load i8* @uc, align 1 ; <i8>:254 [#uses=1]
+ zext i8 %254 to i32 ; <i32>:255 [#uses=2]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:256 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %256, i32 %255 ) ; <i32>:257 [#uses=1]
+ xor i32 %257, -1 ; <i32>:258 [#uses=1]
+ and i32 %258, %255 ; <i32>:259 [#uses=1]
+ store i32 %259, i32* @ul, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define void @test_compare_and_swap() nounwind {
+entry:
+ load i8* @sc, align 1 ; <i8>:0 [#uses=1]
+ zext i8 %0 to i32 ; <i32>:1 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:2 [#uses=1]
+ zext i8 %2 to i32 ; <i32>:3 [#uses=1]
+ trunc i32 %3 to i8 ; <i8>:4 [#uses=1]
+ trunc i32 %1 to i8 ; <i8>:5 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %4, i8 %5 ) ; <i8>:6 [#uses=1]
+ store i8 %6, i8* @sc, align 1
+ load i8* @sc, align 1 ; <i8>:7 [#uses=1]
+ zext i8 %7 to i32 ; <i32>:8 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:9 [#uses=1]
+ zext i8 %9 to i32 ; <i32>:10 [#uses=1]
+ trunc i32 %10 to i8 ; <i8>:11 [#uses=1]
+ trunc i32 %8 to i8 ; <i8>:12 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %11, i8 %12 ) ; <i8>:13 [#uses=1]
+ store i8 %13, i8* @uc, align 1
+ load i8* @sc, align 1 ; <i8>:14 [#uses=1]
+ sext i8 %14 to i16 ; <i16>:15 [#uses=1]
+ zext i16 %15 to i32 ; <i32>:16 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:17 [#uses=1]
+ zext i8 %17 to i32 ; <i32>:18 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:19 [#uses=1]
+ trunc i32 %18 to i16 ; <i16>:20 [#uses=1]
+ trunc i32 %16 to i16 ; <i16>:21 [#uses=1]
+ call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %19, i16 %20, i16 %21 ) ; <i16>:22 [#uses=1]
+ store i16 %22, i16* @ss, align 2
+ load i8* @sc, align 1 ; <i8>:23 [#uses=1]
+ sext i8 %23 to i16 ; <i16>:24 [#uses=1]
+ zext i16 %24 to i32 ; <i32>:25 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:26 [#uses=1]
+ zext i8 %26 to i32 ; <i32>:27 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:28 [#uses=1]
+ trunc i32 %27 to i16 ; <i16>:29 [#uses=1]
+ trunc i32 %25 to i16 ; <i16>:30 [#uses=1]
+ call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %28, i16 %29, i16 %30 ) ; <i16>:31 [#uses=1]
+ store i16 %31, i16* @us, align 2
+ load i8* @sc, align 1 ; <i8>:32 [#uses=1]
+ sext i8 %32 to i32 ; <i32>:33 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:34 [#uses=1]
+ zext i8 %34 to i32 ; <i32>:35 [#uses=1]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:36 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %36, i32 %35, i32 %33 ) ; <i32>:37 [#uses=1]
+ store i32 %37, i32* @si, align 4
+ load i8* @sc, align 1 ; <i8>:38 [#uses=1]
+ sext i8 %38 to i32 ; <i32>:39 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:40 [#uses=1]
+ zext i8 %40 to i32 ; <i32>:41 [#uses=1]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:42 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %42, i32 %41, i32 %39 ) ; <i32>:43 [#uses=1]
+ store i32 %43, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:44 [#uses=1]
+ sext i8 %44 to i32 ; <i32>:45 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:46 [#uses=1]
+ zext i8 %46 to i32 ; <i32>:47 [#uses=1]
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:48 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %48, i32 %47, i32 %45 ) ; <i32>:49 [#uses=1]
+ store i32 %49, i32* @sl, align 4
+ load i8* @sc, align 1 ; <i8>:50 [#uses=1]
+ sext i8 %50 to i32 ; <i32>:51 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:52 [#uses=1]
+ zext i8 %52 to i32 ; <i32>:53 [#uses=1]
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:54 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %54, i32 %53, i32 %51 ) ; <i32>:55 [#uses=1]
+ store i32 %55, i32* @ul, align 4
+ load i8* @sc, align 1 ; <i8>:56 [#uses=1]
+ zext i8 %56 to i32 ; <i32>:57 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:58 [#uses=1]
+ zext i8 %58 to i32 ; <i32>:59 [#uses=1]
+ trunc i32 %59 to i8 ; <i8>:60 [#uses=2]
+ trunc i32 %57 to i8 ; <i8>:61 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %60, i8 %61 ) ; <i8>:62 [#uses=1]
+ icmp eq i8 %62, %60 ; <i1>:63 [#uses=1]
+ zext i1 %63 to i8 ; <i8>:64 [#uses=1]
+ zext i8 %64 to i32 ; <i32>:65 [#uses=1]
+ store i32 %65, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:66 [#uses=1]
+ zext i8 %66 to i32 ; <i32>:67 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:68 [#uses=1]
+ zext i8 %68 to i32 ; <i32>:69 [#uses=1]
+ trunc i32 %69 to i8 ; <i8>:70 [#uses=2]
+ trunc i32 %67 to i8 ; <i8>:71 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %70, i8 %71 ) ; <i8>:72 [#uses=1]
+ icmp eq i8 %72, %70 ; <i1>:73 [#uses=1]
+ zext i1 %73 to i8 ; <i8>:74 [#uses=1]
+ zext i8 %74 to i32 ; <i32>:75 [#uses=1]
+ store i32 %75, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:76 [#uses=1]
+ sext i8 %76 to i16 ; <i16>:77 [#uses=1]
+ zext i16 %77 to i32 ; <i32>:78 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:79 [#uses=1]
+ zext i8 %79 to i32 ; <i32>:80 [#uses=1]
+ trunc i32 %80 to i8 ; <i8>:81 [#uses=2]
+ trunc i32 %78 to i8 ; <i8>:82 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i16* @ss to i8*), i8 %81, i8 %82 ) ; <i8>:83 [#uses=1]
+ icmp eq i8 %83, %81 ; <i1>:84 [#uses=1]
+ zext i1 %84 to i8 ; <i8>:85 [#uses=1]
+ zext i8 %85 to i32 ; <i32>:86 [#uses=1]
+ store i32 %86, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:87 [#uses=1]
+ sext i8 %87 to i16 ; <i16>:88 [#uses=1]
+ zext i16 %88 to i32 ; <i32>:89 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:90 [#uses=1]
+ zext i8 %90 to i32 ; <i32>:91 [#uses=1]
+ trunc i32 %91 to i8 ; <i8>:92 [#uses=2]
+ trunc i32 %89 to i8 ; <i8>:93 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i16* @us to i8*), i8 %92, i8 %93 ) ; <i8>:94 [#uses=1]
+ icmp eq i8 %94, %92 ; <i1>:95 [#uses=1]
+ zext i1 %95 to i8 ; <i8>:96 [#uses=1]
+ zext i8 %96 to i32 ; <i32>:97 [#uses=1]
+ store i32 %97, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:98 [#uses=1]
+ sext i8 %98 to i32 ; <i32>:99 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:100 [#uses=1]
+ zext i8 %100 to i32 ; <i32>:101 [#uses=1]
+ trunc i32 %101 to i8 ; <i8>:102 [#uses=2]
+ trunc i32 %99 to i8 ; <i8>:103 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i32* @si to i8*), i8 %102, i8 %103 ) ; <i8>:104 [#uses=1]
+ icmp eq i8 %104, %102 ; <i1>:105 [#uses=1]
+ zext i1 %105 to i8 ; <i8>:106 [#uses=1]
+ zext i8 %106 to i32 ; <i32>:107 [#uses=1]
+ store i32 %107, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:108 [#uses=1]
+ sext i8 %108 to i32 ; <i32>:109 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:110 [#uses=1]
+ zext i8 %110 to i32 ; <i32>:111 [#uses=1]
+ trunc i32 %111 to i8 ; <i8>:112 [#uses=2]
+ trunc i32 %109 to i8 ; <i8>:113 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i32* @ui to i8*), i8 %112, i8 %113 ) ; <i8>:114 [#uses=1]
+ icmp eq i8 %114, %112 ; <i1>:115 [#uses=1]
+ zext i1 %115 to i8 ; <i8>:116 [#uses=1]
+ zext i8 %116 to i32 ; <i32>:117 [#uses=1]
+ store i32 %117, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:118 [#uses=1]
+ sext i8 %118 to i32 ; <i32>:119 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:120 [#uses=1]
+ zext i8 %120 to i32 ; <i32>:121 [#uses=1]
+ trunc i32 %121 to i8 ; <i8>:122 [#uses=2]
+ trunc i32 %119 to i8 ; <i8>:123 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i32* @sl to i8*), i8 %122, i8 %123 ) ; <i8>:124 [#uses=1]
+ icmp eq i8 %124, %122 ; <i1>:125 [#uses=1]
+ zext i1 %125 to i8 ; <i8>:126 [#uses=1]
+ zext i8 %126 to i32 ; <i32>:127 [#uses=1]
+ store i32 %127, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:128 [#uses=1]
+ sext i8 %128 to i32 ; <i32>:129 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:130 [#uses=1]
+ zext i8 %130 to i32 ; <i32>:131 [#uses=1]
+ trunc i32 %131 to i8 ; <i8>:132 [#uses=2]
+ trunc i32 %129 to i8 ; <i8>:133 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i32* @ul to i8*), i8 %132, i8 %133 ) ; <i8>:134 [#uses=1]
+ icmp eq i8 %134, %132 ; <i1>:135 [#uses=1]
+ zext i1 %135 to i8 ; <i8>:136 [#uses=1]
+ zext i8 %136 to i32 ; <i32>:137 [#uses=1]
+ store i32 %137, i32* @ui, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8*, i8, i8) nounwind
+
+declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16*, i16, i16) nounwind
+
+declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind
+
+define void @test_lock() nounwind {
+entry:
+ call i8 @llvm.atomic.swap.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:0 [#uses=1]
+ store i8 %0, i8* @sc, align 1
+ call i8 @llvm.atomic.swap.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:1 [#uses=1]
+ store i8 %1, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1]
+ call i16 @llvm.atomic.swap.i16.p0i16( i16* %2, i16 1 ) ; <i16>:3 [#uses=1]
+ store i16 %3, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1]
+ call i16 @llvm.atomic.swap.i16.p0i16( i16* %4, i16 1 ) ; <i16>:5 [#uses=1]
+ store i16 %5, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1]
+ call i32 @llvm.atomic.swap.i32.p0i32( i32* %6, i32 1 ) ; <i32>:7 [#uses=1]
+ store i32 %7, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1]
+ call i32 @llvm.atomic.swap.i32.p0i32( i32* %8, i32 1 ) ; <i32>:9 [#uses=1]
+ store i32 %9, i32* @ui, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:10 [#uses=1]
+ call i32 @llvm.atomic.swap.i32.p0i32( i32* %10, i32 1 ) ; <i32>:11 [#uses=1]
+ store i32 %11, i32* @sl, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:12 [#uses=1]
+ call i32 @llvm.atomic.swap.i32.p0i32( i32* %12, i32 1 ) ; <i32>:13 [#uses=1]
+ store i32 %13, i32* @ul, align 4
+ call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true, i1 false )
+ volatile store i8 0, i8* @sc, align 1
+ volatile store i8 0, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:14 [#uses=1]
+ volatile store i16 0, i16* %14, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:15 [#uses=1]
+ volatile store i16 0, i16* %15, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:16 [#uses=1]
+ volatile store i32 0, i32* %16, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:17 [#uses=1]
+ volatile store i32 0, i32* %17, align 4
+ bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:18 [#uses=1]
+ volatile store i32 0, i32* %18, align 4
+ bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:19 [#uses=1]
+ volatile store i32 0, i32* %19, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.swap.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.swap.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind
+
+declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind
diff --git a/test/CodeGen/X86/Atomics-64.ll b/test/CodeGen/X86/Atomics-64.ll
new file mode 100644
index 0000000..ac174b9
--- /dev/null
+++ b/test/CodeGen/X86/Atomics-64.ll
@@ -0,0 +1,1015 @@
+; RUN: llc < %s -march=x86-64 > %t
+; ModuleID = 'Atomics.c'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin8"
+@sc = common global i8 0 ; <i8*> [#uses=56]
+@uc = common global i8 0 ; <i8*> [#uses=116]
+@ss = common global i16 0 ; <i16*> [#uses=15]
+@us = common global i16 0 ; <i16*> [#uses=15]
+@si = common global i32 0 ; <i32*> [#uses=15]
+@ui = common global i32 0 ; <i32*> [#uses=25]
+@sl = common global i64 0 ; <i64*> [#uses=15]
+@ul = common global i64 0 ; <i64*> [#uses=15]
+@sll = common global i64 0 ; <i64*> [#uses=15]
+@ull = common global i64 0 ; <i64*> [#uses=15]
+
+define void @test_op_ignore() nounwind {
+entry:
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:0 [#uses=0]
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:1 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 1 ) ; <i16>:3 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 1 ) ; <i16>:5 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 1 ) ; <i32>:7 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 1 ) ; <i32>:9 [#uses=0]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:10 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %10, i64 1 ) ; <i64>:11 [#uses=0]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:12 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %12, i64 1 ) ; <i64>:13 [#uses=0]
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:14 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %14, i64 1 ) ; <i64>:15 [#uses=0]
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:16 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %16, i64 1 ) ; <i64>:17 [#uses=0]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:18 [#uses=0]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:19 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:20 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %20, i16 1 ) ; <i16>:21 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:22 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %22, i16 1 ) ; <i16>:23 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:24 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %24, i32 1 ) ; <i32>:25 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:26 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %26, i32 1 ) ; <i32>:27 [#uses=0]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:28 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %28, i64 1 ) ; <i64>:29 [#uses=0]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:30 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %30, i64 1 ) ; <i64>:31 [#uses=0]
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:32 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %32, i64 1 ) ; <i64>:33 [#uses=0]
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:34 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %34, i64 1 ) ; <i64>:35 [#uses=0]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:36 [#uses=0]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:37 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:38 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %38, i16 1 ) ; <i16>:39 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:40 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %40, i16 1 ) ; <i16>:41 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:42 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %42, i32 1 ) ; <i32>:43 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:44 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %44, i32 1 ) ; <i32>:45 [#uses=0]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:46 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %46, i64 1 ) ; <i64>:47 [#uses=0]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:48 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %48, i64 1 ) ; <i64>:49 [#uses=0]
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:50 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %50, i64 1 ) ; <i64>:51 [#uses=0]
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:52 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %52, i64 1 ) ; <i64>:53 [#uses=0]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:54 [#uses=0]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:55 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:56 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %56, i16 1 ) ; <i16>:57 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:58 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %58, i16 1 ) ; <i16>:59 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:60 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %60, i32 1 ) ; <i32>:61 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:62 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %62, i32 1 ) ; <i32>:63 [#uses=0]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:64 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %64, i64 1 ) ; <i64>:65 [#uses=0]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:66 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %66, i64 1 ) ; <i64>:67 [#uses=0]
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:68 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %68, i64 1 ) ; <i64>:69 [#uses=0]
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:70 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %70, i64 1 ) ; <i64>:71 [#uses=0]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:72 [#uses=0]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:73 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:74 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %74, i16 1 ) ; <i16>:75 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:76 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %76, i16 1 ) ; <i16>:77 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:78 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %78, i32 1 ) ; <i32>:79 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:80 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %80, i32 1 ) ; <i32>:81 [#uses=0]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:82 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %82, i64 1 ) ; <i64>:83 [#uses=0]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:84 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %84, i64 1 ) ; <i64>:85 [#uses=0]
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:86 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %86, i64 1 ) ; <i64>:87 [#uses=0]
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:88 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %88, i64 1 ) ; <i64>:89 [#uses=0]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:90 [#uses=0]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:91 [#uses=0]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:92 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %92, i16 1 ) ; <i16>:93 [#uses=0]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:94 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %94, i16 1 ) ; <i16>:95 [#uses=0]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:96 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %96, i32 1 ) ; <i32>:97 [#uses=0]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:98 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %98, i32 1 ) ; <i32>:99 [#uses=0]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:100 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %100, i64 1 ) ; <i64>:101 [#uses=0]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:102 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %102, i64 1 ) ; <i64>:103 [#uses=0]
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:104 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %104, i64 1 ) ; <i64>:105 [#uses=0]
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:106 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %106, i64 1 ) ; <i64>:107 [#uses=0]
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.add.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.add.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.sub.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.sub.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.sub.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.or.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.or.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.or.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.xor.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.xor.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.xor.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.and.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.and.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.and.i64.p0i64(i64*, i64) nounwind
+
+declare i8 @llvm.atomic.load.nand.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.load.nand.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.load.nand.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.load.nand.i64.p0i64(i64*, i64) nounwind
+
+define void @test_fetch_and_op() nounwind {
+entry:
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:0 [#uses=1]
+ store i8 %0, i8* @sc, align 1
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:1 [#uses=1]
+ store i8 %1, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 11 ) ; <i16>:3 [#uses=1]
+ store i16 %3, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 11 ) ; <i16>:5 [#uses=1]
+ store i16 %5, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 11 ) ; <i32>:7 [#uses=1]
+ store i32 %7, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 11 ) ; <i32>:9 [#uses=1]
+ store i32 %9, i32* @ui, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:10 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %10, i64 11 ) ; <i64>:11 [#uses=1]
+ store i64 %11, i64* @sl, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:12 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %12, i64 11 ) ; <i64>:13 [#uses=1]
+ store i64 %13, i64* @ul, align 8
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:14 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %14, i64 11 ) ; <i64>:15 [#uses=1]
+ store i64 %15, i64* @sll, align 8
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:16 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %16, i64 11 ) ; <i64>:17 [#uses=1]
+ store i64 %17, i64* @ull, align 8
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:18 [#uses=1]
+ store i8 %18, i8* @sc, align 1
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:19 [#uses=1]
+ store i8 %19, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:20 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %20, i16 11 ) ; <i16>:21 [#uses=1]
+ store i16 %21, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:22 [#uses=1]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %22, i16 11 ) ; <i16>:23 [#uses=1]
+ store i16 %23, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:24 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %24, i32 11 ) ; <i32>:25 [#uses=1]
+ store i32 %25, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:26 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %26, i32 11 ) ; <i32>:27 [#uses=1]
+ store i32 %27, i32* @ui, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:28 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %28, i64 11 ) ; <i64>:29 [#uses=1]
+ store i64 %29, i64* @sl, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:30 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %30, i64 11 ) ; <i64>:31 [#uses=1]
+ store i64 %31, i64* @ul, align 8
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:32 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %32, i64 11 ) ; <i64>:33 [#uses=1]
+ store i64 %33, i64* @sll, align 8
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:34 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %34, i64 11 ) ; <i64>:35 [#uses=1]
+ store i64 %35, i64* @ull, align 8
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:36 [#uses=1]
+ store i8 %36, i8* @sc, align 1
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:37 [#uses=1]
+ store i8 %37, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:38 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %38, i16 11 ) ; <i16>:39 [#uses=1]
+ store i16 %39, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:40 [#uses=1]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %40, i16 11 ) ; <i16>:41 [#uses=1]
+ store i16 %41, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:42 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %42, i32 11 ) ; <i32>:43 [#uses=1]
+ store i32 %43, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:44 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %44, i32 11 ) ; <i32>:45 [#uses=1]
+ store i32 %45, i32* @ui, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:46 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %46, i64 11 ) ; <i64>:47 [#uses=1]
+ store i64 %47, i64* @sl, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:48 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %48, i64 11 ) ; <i64>:49 [#uses=1]
+ store i64 %49, i64* @ul, align 8
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:50 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %50, i64 11 ) ; <i64>:51 [#uses=1]
+ store i64 %51, i64* @sll, align 8
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:52 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %52, i64 11 ) ; <i64>:53 [#uses=1]
+ store i64 %53, i64* @ull, align 8
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:54 [#uses=1]
+ store i8 %54, i8* @sc, align 1
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:55 [#uses=1]
+ store i8 %55, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:56 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %56, i16 11 ) ; <i16>:57 [#uses=1]
+ store i16 %57, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:58 [#uses=1]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %58, i16 11 ) ; <i16>:59 [#uses=1]
+ store i16 %59, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:60 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %60, i32 11 ) ; <i32>:61 [#uses=1]
+ store i32 %61, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:62 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %62, i32 11 ) ; <i32>:63 [#uses=1]
+ store i32 %63, i32* @ui, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:64 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %64, i64 11 ) ; <i64>:65 [#uses=1]
+ store i64 %65, i64* @sl, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:66 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %66, i64 11 ) ; <i64>:67 [#uses=1]
+ store i64 %67, i64* @ul, align 8
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:68 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %68, i64 11 ) ; <i64>:69 [#uses=1]
+ store i64 %69, i64* @sll, align 8
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:70 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %70, i64 11 ) ; <i64>:71 [#uses=1]
+ store i64 %71, i64* @ull, align 8
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:72 [#uses=1]
+ store i8 %72, i8* @sc, align 1
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:73 [#uses=1]
+ store i8 %73, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:74 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %74, i16 11 ) ; <i16>:75 [#uses=1]
+ store i16 %75, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:76 [#uses=1]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %76, i16 11 ) ; <i16>:77 [#uses=1]
+ store i16 %77, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:78 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %78, i32 11 ) ; <i32>:79 [#uses=1]
+ store i32 %79, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:80 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %80, i32 11 ) ; <i32>:81 [#uses=1]
+ store i32 %81, i32* @ui, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:82 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %82, i64 11 ) ; <i64>:83 [#uses=1]
+ store i64 %83, i64* @sl, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:84 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %84, i64 11 ) ; <i64>:85 [#uses=1]
+ store i64 %85, i64* @ul, align 8
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:86 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %86, i64 11 ) ; <i64>:87 [#uses=1]
+ store i64 %87, i64* @sll, align 8
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:88 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %88, i64 11 ) ; <i64>:89 [#uses=1]
+ store i64 %89, i64* @ull, align 8
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:90 [#uses=1]
+ store i8 %90, i8* @sc, align 1
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:91 [#uses=1]
+ store i8 %91, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:92 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %92, i16 11 ) ; <i16>:93 [#uses=1]
+ store i16 %93, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:94 [#uses=1]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %94, i16 11 ) ; <i16>:95 [#uses=1]
+ store i16 %95, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:96 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %96, i32 11 ) ; <i32>:97 [#uses=1]
+ store i32 %97, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:98 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %98, i32 11 ) ; <i32>:99 [#uses=1]
+ store i32 %99, i32* @ui, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:100 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %100, i64 11 ) ; <i64>:101 [#uses=1]
+ store i64 %101, i64* @sl, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:102 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %102, i64 11 ) ; <i64>:103 [#uses=1]
+ store i64 %103, i64* @ul, align 8
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:104 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %104, i64 11 ) ; <i64>:105 [#uses=1]
+ store i64 %105, i64* @sll, align 8
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:106 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %106, i64 11 ) ; <i64>:107 [#uses=1]
+ store i64 %107, i64* @ull, align 8
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define void @test_op_and_fetch() nounwind {
+entry:
+ load i8* @uc, align 1 ; <i8>:0 [#uses=1]
+ zext i8 %0 to i32 ; <i32>:1 [#uses=1]
+ trunc i32 %1 to i8 ; <i8>:2 [#uses=2]
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 %2 ) ; <i8>:3 [#uses=1]
+ add i8 %3, %2 ; <i8>:4 [#uses=1]
+ store i8 %4, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:5 [#uses=1]
+ zext i8 %5 to i32 ; <i32>:6 [#uses=1]
+ trunc i32 %6 to i8 ; <i8>:7 [#uses=2]
+ call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 %7 ) ; <i8>:8 [#uses=1]
+ add i8 %8, %7 ; <i8>:9 [#uses=1]
+ store i8 %9, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:10 [#uses=1]
+ zext i8 %10 to i32 ; <i32>:11 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:12 [#uses=1]
+ trunc i32 %11 to i16 ; <i16>:13 [#uses=2]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %12, i16 %13 ) ; <i16>:14 [#uses=1]
+ add i16 %14, %13 ; <i16>:15 [#uses=1]
+ store i16 %15, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:16 [#uses=1]
+ zext i8 %16 to i32 ; <i32>:17 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:18 [#uses=1]
+ trunc i32 %17 to i16 ; <i16>:19 [#uses=2]
+ call i16 @llvm.atomic.load.add.i16.p0i16( i16* %18, i16 %19 ) ; <i16>:20 [#uses=1]
+ add i16 %20, %19 ; <i16>:21 [#uses=1]
+ store i16 %21, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:22 [#uses=1]
+ zext i8 %22 to i32 ; <i32>:23 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:24 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %24, i32 %23 ) ; <i32>:25 [#uses=1]
+ add i32 %25, %23 ; <i32>:26 [#uses=1]
+ store i32 %26, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:27 [#uses=1]
+ zext i8 %27 to i32 ; <i32>:28 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:29 [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %29, i32 %28 ) ; <i32>:30 [#uses=1]
+ add i32 %30, %28 ; <i32>:31 [#uses=1]
+ store i32 %31, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:32 [#uses=1]
+ zext i8 %32 to i64 ; <i64>:33 [#uses=2]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:34 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %34, i64 %33 ) ; <i64>:35 [#uses=1]
+ add i64 %35, %33 ; <i64>:36 [#uses=1]
+ store i64 %36, i64* @sl, align 8
+ load i8* @uc, align 1 ; <i8>:37 [#uses=1]
+ zext i8 %37 to i64 ; <i64>:38 [#uses=2]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:39 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %39, i64 %38 ) ; <i64>:40 [#uses=1]
+ add i64 %40, %38 ; <i64>:41 [#uses=1]
+ store i64 %41, i64* @ul, align 8
+ load i8* @uc, align 1 ; <i8>:42 [#uses=1]
+ zext i8 %42 to i64 ; <i64>:43 [#uses=2]
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:44 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %44, i64 %43 ) ; <i64>:45 [#uses=1]
+ add i64 %45, %43 ; <i64>:46 [#uses=1]
+ store i64 %46, i64* @sll, align 8
+ load i8* @uc, align 1 ; <i8>:47 [#uses=1]
+ zext i8 %47 to i64 ; <i64>:48 [#uses=2]
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:49 [#uses=1]
+ call i64 @llvm.atomic.load.add.i64.p0i64( i64* %49, i64 %48 ) ; <i64>:50 [#uses=1]
+ add i64 %50, %48 ; <i64>:51 [#uses=1]
+ store i64 %51, i64* @ull, align 8
+ load i8* @uc, align 1 ; <i8>:52 [#uses=1]
+ zext i8 %52 to i32 ; <i32>:53 [#uses=1]
+ trunc i32 %53 to i8 ; <i8>:54 [#uses=2]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 %54 ) ; <i8>:55 [#uses=1]
+ sub i8 %55, %54 ; <i8>:56 [#uses=1]
+ store i8 %56, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:57 [#uses=1]
+ zext i8 %57 to i32 ; <i32>:58 [#uses=1]
+ trunc i32 %58 to i8 ; <i8>:59 [#uses=2]
+ call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 %59 ) ; <i8>:60 [#uses=1]
+ sub i8 %60, %59 ; <i8>:61 [#uses=1]
+ store i8 %61, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:62 [#uses=1]
+ zext i8 %62 to i32 ; <i32>:63 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:64 [#uses=1]
+ trunc i32 %63 to i16 ; <i16>:65 [#uses=2]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %64, i16 %65 ) ; <i16>:66 [#uses=1]
+ sub i16 %66, %65 ; <i16>:67 [#uses=1]
+ store i16 %67, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:68 [#uses=1]
+ zext i8 %68 to i32 ; <i32>:69 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:70 [#uses=1]
+ trunc i32 %69 to i16 ; <i16>:71 [#uses=2]
+ call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %70, i16 %71 ) ; <i16>:72 [#uses=1]
+ sub i16 %72, %71 ; <i16>:73 [#uses=1]
+ store i16 %73, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:74 [#uses=1]
+ zext i8 %74 to i32 ; <i32>:75 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:76 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %76, i32 %75 ) ; <i32>:77 [#uses=1]
+ sub i32 %77, %75 ; <i32>:78 [#uses=1]
+ store i32 %78, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:79 [#uses=1]
+ zext i8 %79 to i32 ; <i32>:80 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:81 [#uses=1]
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %81, i32 %80 ) ; <i32>:82 [#uses=1]
+ sub i32 %82, %80 ; <i32>:83 [#uses=1]
+ store i32 %83, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:84 [#uses=1]
+ zext i8 %84 to i64 ; <i64>:85 [#uses=2]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:86 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %86, i64 %85 ) ; <i64>:87 [#uses=1]
+ sub i64 %87, %85 ; <i64>:88 [#uses=1]
+ store i64 %88, i64* @sl, align 8
+ load i8* @uc, align 1 ; <i8>:89 [#uses=1]
+ zext i8 %89 to i64 ; <i64>:90 [#uses=2]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:91 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %91, i64 %90 ) ; <i64>:92 [#uses=1]
+ sub i64 %92, %90 ; <i64>:93 [#uses=1]
+ store i64 %93, i64* @ul, align 8
+ load i8* @uc, align 1 ; <i8>:94 [#uses=1]
+ zext i8 %94 to i64 ; <i64>:95 [#uses=2]
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:96 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %96, i64 %95 ) ; <i64>:97 [#uses=1]
+ sub i64 %97, %95 ; <i64>:98 [#uses=1]
+ store i64 %98, i64* @sll, align 8
+ load i8* @uc, align 1 ; <i8>:99 [#uses=1]
+ zext i8 %99 to i64 ; <i64>:100 [#uses=2]
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:101 [#uses=1]
+ call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %101, i64 %100 ) ; <i64>:102 [#uses=1]
+ sub i64 %102, %100 ; <i64>:103 [#uses=1]
+ store i64 %103, i64* @ull, align 8
+ load i8* @uc, align 1 ; <i8>:104 [#uses=1]
+ zext i8 %104 to i32 ; <i32>:105 [#uses=1]
+ trunc i32 %105 to i8 ; <i8>:106 [#uses=2]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 %106 ) ; <i8>:107 [#uses=1]
+ or i8 %107, %106 ; <i8>:108 [#uses=1]
+ store i8 %108, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:109 [#uses=1]
+ zext i8 %109 to i32 ; <i32>:110 [#uses=1]
+ trunc i32 %110 to i8 ; <i8>:111 [#uses=2]
+ call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 %111 ) ; <i8>:112 [#uses=1]
+ or i8 %112, %111 ; <i8>:113 [#uses=1]
+ store i8 %113, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:114 [#uses=1]
+ zext i8 %114 to i32 ; <i32>:115 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:116 [#uses=1]
+ trunc i32 %115 to i16 ; <i16>:117 [#uses=2]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %116, i16 %117 ) ; <i16>:118 [#uses=1]
+ or i16 %118, %117 ; <i16>:119 [#uses=1]
+ store i16 %119, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:120 [#uses=1]
+ zext i8 %120 to i32 ; <i32>:121 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:122 [#uses=1]
+ trunc i32 %121 to i16 ; <i16>:123 [#uses=2]
+ call i16 @llvm.atomic.load.or.i16.p0i16( i16* %122, i16 %123 ) ; <i16>:124 [#uses=1]
+ or i16 %124, %123 ; <i16>:125 [#uses=1]
+ store i16 %125, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:126 [#uses=1]
+ zext i8 %126 to i32 ; <i32>:127 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:128 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %128, i32 %127 ) ; <i32>:129 [#uses=1]
+ or i32 %129, %127 ; <i32>:130 [#uses=1]
+ store i32 %130, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:131 [#uses=1]
+ zext i8 %131 to i32 ; <i32>:132 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:133 [#uses=1]
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %133, i32 %132 ) ; <i32>:134 [#uses=1]
+ or i32 %134, %132 ; <i32>:135 [#uses=1]
+ store i32 %135, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:136 [#uses=1]
+ zext i8 %136 to i64 ; <i64>:137 [#uses=2]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:138 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %138, i64 %137 ) ; <i64>:139 [#uses=1]
+ or i64 %139, %137 ; <i64>:140 [#uses=1]
+ store i64 %140, i64* @sl, align 8
+ load i8* @uc, align 1 ; <i8>:141 [#uses=1]
+ zext i8 %141 to i64 ; <i64>:142 [#uses=2]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:143 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %143, i64 %142 ) ; <i64>:144 [#uses=1]
+ or i64 %144, %142 ; <i64>:145 [#uses=1]
+ store i64 %145, i64* @ul, align 8
+ load i8* @uc, align 1 ; <i8>:146 [#uses=1]
+ zext i8 %146 to i64 ; <i64>:147 [#uses=2]
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:148 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %148, i64 %147 ) ; <i64>:149 [#uses=1]
+ or i64 %149, %147 ; <i64>:150 [#uses=1]
+ store i64 %150, i64* @sll, align 8
+ load i8* @uc, align 1 ; <i8>:151 [#uses=1]
+ zext i8 %151 to i64 ; <i64>:152 [#uses=2]
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:153 [#uses=1]
+ call i64 @llvm.atomic.load.or.i64.p0i64( i64* %153, i64 %152 ) ; <i64>:154 [#uses=1]
+ or i64 %154, %152 ; <i64>:155 [#uses=1]
+ store i64 %155, i64* @ull, align 8
+ load i8* @uc, align 1 ; <i8>:156 [#uses=1]
+ zext i8 %156 to i32 ; <i32>:157 [#uses=1]
+ trunc i32 %157 to i8 ; <i8>:158 [#uses=2]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 %158 ) ; <i8>:159 [#uses=1]
+ xor i8 %159, %158 ; <i8>:160 [#uses=1]
+ store i8 %160, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:161 [#uses=1]
+ zext i8 %161 to i32 ; <i32>:162 [#uses=1]
+ trunc i32 %162 to i8 ; <i8>:163 [#uses=2]
+ call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 %163 ) ; <i8>:164 [#uses=1]
+ xor i8 %164, %163 ; <i8>:165 [#uses=1]
+ store i8 %165, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:166 [#uses=1]
+ zext i8 %166 to i32 ; <i32>:167 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:168 [#uses=1]
+ trunc i32 %167 to i16 ; <i16>:169 [#uses=2]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %168, i16 %169 ) ; <i16>:170 [#uses=1]
+ xor i16 %170, %169 ; <i16>:171 [#uses=1]
+ store i16 %171, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:172 [#uses=1]
+ zext i8 %172 to i32 ; <i32>:173 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:174 [#uses=1]
+ trunc i32 %173 to i16 ; <i16>:175 [#uses=2]
+ call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %174, i16 %175 ) ; <i16>:176 [#uses=1]
+ xor i16 %176, %175 ; <i16>:177 [#uses=1]
+ store i16 %177, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:178 [#uses=1]
+ zext i8 %178 to i32 ; <i32>:179 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:180 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %180, i32 %179 ) ; <i32>:181 [#uses=1]
+ xor i32 %181, %179 ; <i32>:182 [#uses=1]
+ store i32 %182, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:183 [#uses=1]
+ zext i8 %183 to i32 ; <i32>:184 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:185 [#uses=1]
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %185, i32 %184 ) ; <i32>:186 [#uses=1]
+ xor i32 %186, %184 ; <i32>:187 [#uses=1]
+ store i32 %187, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:188 [#uses=1]
+ zext i8 %188 to i64 ; <i64>:189 [#uses=2]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:190 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %190, i64 %189 ) ; <i64>:191 [#uses=1]
+ xor i64 %191, %189 ; <i64>:192 [#uses=1]
+ store i64 %192, i64* @sl, align 8
+ load i8* @uc, align 1 ; <i8>:193 [#uses=1]
+ zext i8 %193 to i64 ; <i64>:194 [#uses=2]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:195 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %195, i64 %194 ) ; <i64>:196 [#uses=1]
+ xor i64 %196, %194 ; <i64>:197 [#uses=1]
+ store i64 %197, i64* @ul, align 8
+ load i8* @uc, align 1 ; <i8>:198 [#uses=1]
+ zext i8 %198 to i64 ; <i64>:199 [#uses=2]
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:200 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %200, i64 %199 ) ; <i64>:201 [#uses=1]
+ xor i64 %201, %199 ; <i64>:202 [#uses=1]
+ store i64 %202, i64* @sll, align 8
+ load i8* @uc, align 1 ; <i8>:203 [#uses=1]
+ zext i8 %203 to i64 ; <i64>:204 [#uses=2]
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:205 [#uses=1]
+ call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %205, i64 %204 ) ; <i64>:206 [#uses=1]
+ xor i64 %206, %204 ; <i64>:207 [#uses=1]
+ store i64 %207, i64* @ull, align 8
+ load i8* @uc, align 1 ; <i8>:208 [#uses=1]
+ zext i8 %208 to i32 ; <i32>:209 [#uses=1]
+ trunc i32 %209 to i8 ; <i8>:210 [#uses=2]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 %210 ) ; <i8>:211 [#uses=1]
+ and i8 %211, %210 ; <i8>:212 [#uses=1]
+ store i8 %212, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:213 [#uses=1]
+ zext i8 %213 to i32 ; <i32>:214 [#uses=1]
+ trunc i32 %214 to i8 ; <i8>:215 [#uses=2]
+ call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 %215 ) ; <i8>:216 [#uses=1]
+ and i8 %216, %215 ; <i8>:217 [#uses=1]
+ store i8 %217, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:218 [#uses=1]
+ zext i8 %218 to i32 ; <i32>:219 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:220 [#uses=1]
+ trunc i32 %219 to i16 ; <i16>:221 [#uses=2]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %220, i16 %221 ) ; <i16>:222 [#uses=1]
+ and i16 %222, %221 ; <i16>:223 [#uses=1]
+ store i16 %223, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:224 [#uses=1]
+ zext i8 %224 to i32 ; <i32>:225 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:226 [#uses=1]
+ trunc i32 %225 to i16 ; <i16>:227 [#uses=2]
+ call i16 @llvm.atomic.load.and.i16.p0i16( i16* %226, i16 %227 ) ; <i16>:228 [#uses=1]
+ and i16 %228, %227 ; <i16>:229 [#uses=1]
+ store i16 %229, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:230 [#uses=1]
+ zext i8 %230 to i32 ; <i32>:231 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:232 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %232, i32 %231 ) ; <i32>:233 [#uses=1]
+ and i32 %233, %231 ; <i32>:234 [#uses=1]
+ store i32 %234, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:235 [#uses=1]
+ zext i8 %235 to i32 ; <i32>:236 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:237 [#uses=1]
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %237, i32 %236 ) ; <i32>:238 [#uses=1]
+ and i32 %238, %236 ; <i32>:239 [#uses=1]
+ store i32 %239, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:240 [#uses=1]
+ zext i8 %240 to i64 ; <i64>:241 [#uses=2]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:242 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %242, i64 %241 ) ; <i64>:243 [#uses=1]
+ and i64 %243, %241 ; <i64>:244 [#uses=1]
+ store i64 %244, i64* @sl, align 8
+ load i8* @uc, align 1 ; <i8>:245 [#uses=1]
+ zext i8 %245 to i64 ; <i64>:246 [#uses=2]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:247 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %247, i64 %246 ) ; <i64>:248 [#uses=1]
+ and i64 %248, %246 ; <i64>:249 [#uses=1]
+ store i64 %249, i64* @ul, align 8
+ load i8* @uc, align 1 ; <i8>:250 [#uses=1]
+ zext i8 %250 to i64 ; <i64>:251 [#uses=2]
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:252 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %252, i64 %251 ) ; <i64>:253 [#uses=1]
+ and i64 %253, %251 ; <i64>:254 [#uses=1]
+ store i64 %254, i64* @sll, align 8
+ load i8* @uc, align 1 ; <i8>:255 [#uses=1]
+ zext i8 %255 to i64 ; <i64>:256 [#uses=2]
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:257 [#uses=1]
+ call i64 @llvm.atomic.load.and.i64.p0i64( i64* %257, i64 %256 ) ; <i64>:258 [#uses=1]
+ and i64 %258, %256 ; <i64>:259 [#uses=1]
+ store i64 %259, i64* @ull, align 8
+ load i8* @uc, align 1 ; <i8>:260 [#uses=1]
+ zext i8 %260 to i32 ; <i32>:261 [#uses=1]
+ trunc i32 %261 to i8 ; <i8>:262 [#uses=2]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 %262 ) ; <i8>:263 [#uses=1]
+ xor i8 %263, -1 ; <i8>:264 [#uses=1]
+ and i8 %264, %262 ; <i8>:265 [#uses=1]
+ store i8 %265, i8* @sc, align 1
+ load i8* @uc, align 1 ; <i8>:266 [#uses=1]
+ zext i8 %266 to i32 ; <i32>:267 [#uses=1]
+ trunc i32 %267 to i8 ; <i8>:268 [#uses=2]
+ call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 %268 ) ; <i8>:269 [#uses=1]
+ xor i8 %269, -1 ; <i8>:270 [#uses=1]
+ and i8 %270, %268 ; <i8>:271 [#uses=1]
+ store i8 %271, i8* @uc, align 1
+ load i8* @uc, align 1 ; <i8>:272 [#uses=1]
+ zext i8 %272 to i32 ; <i32>:273 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:274 [#uses=1]
+ trunc i32 %273 to i16 ; <i16>:275 [#uses=2]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %274, i16 %275 ) ; <i16>:276 [#uses=1]
+ xor i16 %276, -1 ; <i16>:277 [#uses=1]
+ and i16 %277, %275 ; <i16>:278 [#uses=1]
+ store i16 %278, i16* @ss, align 2
+ load i8* @uc, align 1 ; <i8>:279 [#uses=1]
+ zext i8 %279 to i32 ; <i32>:280 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:281 [#uses=1]
+ trunc i32 %280 to i16 ; <i16>:282 [#uses=2]
+ call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %281, i16 %282 ) ; <i16>:283 [#uses=1]
+ xor i16 %283, -1 ; <i16>:284 [#uses=1]
+ and i16 %284, %282 ; <i16>:285 [#uses=1]
+ store i16 %285, i16* @us, align 2
+ load i8* @uc, align 1 ; <i8>:286 [#uses=1]
+ zext i8 %286 to i32 ; <i32>:287 [#uses=2]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:288 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %288, i32 %287 ) ; <i32>:289 [#uses=1]
+ xor i32 %289, -1 ; <i32>:290 [#uses=1]
+ and i32 %290, %287 ; <i32>:291 [#uses=1]
+ store i32 %291, i32* @si, align 4
+ load i8* @uc, align 1 ; <i8>:292 [#uses=1]
+ zext i8 %292 to i32 ; <i32>:293 [#uses=2]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:294 [#uses=1]
+ call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %294, i32 %293 ) ; <i32>:295 [#uses=1]
+ xor i32 %295, -1 ; <i32>:296 [#uses=1]
+ and i32 %296, %293 ; <i32>:297 [#uses=1]
+ store i32 %297, i32* @ui, align 4
+ load i8* @uc, align 1 ; <i8>:298 [#uses=1]
+ zext i8 %298 to i64 ; <i64>:299 [#uses=2]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:300 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %300, i64 %299 ) ; <i64>:301 [#uses=1]
+ xor i64 %301, -1 ; <i64>:302 [#uses=1]
+ and i64 %302, %299 ; <i64>:303 [#uses=1]
+ store i64 %303, i64* @sl, align 8
+ load i8* @uc, align 1 ; <i8>:304 [#uses=1]
+ zext i8 %304 to i64 ; <i64>:305 [#uses=2]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:306 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %306, i64 %305 ) ; <i64>:307 [#uses=1]
+ xor i64 %307, -1 ; <i64>:308 [#uses=1]
+ and i64 %308, %305 ; <i64>:309 [#uses=1]
+ store i64 %309, i64* @ul, align 8
+ load i8* @uc, align 1 ; <i8>:310 [#uses=1]
+ zext i8 %310 to i64 ; <i64>:311 [#uses=2]
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:312 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %312, i64 %311 ) ; <i64>:313 [#uses=1]
+ xor i64 %313, -1 ; <i64>:314 [#uses=1]
+ and i64 %314, %311 ; <i64>:315 [#uses=1]
+ store i64 %315, i64* @sll, align 8
+ load i8* @uc, align 1 ; <i8>:316 [#uses=1]
+ zext i8 %316 to i64 ; <i64>:317 [#uses=2]
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:318 [#uses=1]
+ call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %318, i64 %317 ) ; <i64>:319 [#uses=1]
+ xor i64 %319, -1 ; <i64>:320 [#uses=1]
+ and i64 %320, %317 ; <i64>:321 [#uses=1]
+ store i64 %321, i64* @ull, align 8
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define void @test_compare_and_swap() nounwind {
+entry:
+ load i8* @sc, align 1 ; <i8>:0 [#uses=1]
+ zext i8 %0 to i32 ; <i32>:1 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:2 [#uses=1]
+ zext i8 %2 to i32 ; <i32>:3 [#uses=1]
+ trunc i32 %3 to i8 ; <i8>:4 [#uses=1]
+ trunc i32 %1 to i8 ; <i8>:5 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %4, i8 %5 ) ; <i8>:6 [#uses=1]
+ store i8 %6, i8* @sc, align 1
+ load i8* @sc, align 1 ; <i8>:7 [#uses=1]
+ zext i8 %7 to i32 ; <i32>:8 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:9 [#uses=1]
+ zext i8 %9 to i32 ; <i32>:10 [#uses=1]
+ trunc i32 %10 to i8 ; <i8>:11 [#uses=1]
+ trunc i32 %8 to i8 ; <i8>:12 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %11, i8 %12 ) ; <i8>:13 [#uses=1]
+ store i8 %13, i8* @uc, align 1
+ load i8* @sc, align 1 ; <i8>:14 [#uses=1]
+ sext i8 %14 to i16 ; <i16>:15 [#uses=1]
+ zext i16 %15 to i32 ; <i32>:16 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:17 [#uses=1]
+ zext i8 %17 to i32 ; <i32>:18 [#uses=1]
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:19 [#uses=1]
+ trunc i32 %18 to i16 ; <i16>:20 [#uses=1]
+ trunc i32 %16 to i16 ; <i16>:21 [#uses=1]
+ call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %19, i16 %20, i16 %21 ) ; <i16>:22 [#uses=1]
+ store i16 %22, i16* @ss, align 2
+ load i8* @sc, align 1 ; <i8>:23 [#uses=1]
+ sext i8 %23 to i16 ; <i16>:24 [#uses=1]
+ zext i16 %24 to i32 ; <i32>:25 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:26 [#uses=1]
+ zext i8 %26 to i32 ; <i32>:27 [#uses=1]
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:28 [#uses=1]
+ trunc i32 %27 to i16 ; <i16>:29 [#uses=1]
+ trunc i32 %25 to i16 ; <i16>:30 [#uses=1]
+ call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %28, i16 %29, i16 %30 ) ; <i16>:31 [#uses=1]
+ store i16 %31, i16* @us, align 2
+ load i8* @sc, align 1 ; <i8>:32 [#uses=1]
+ sext i8 %32 to i32 ; <i32>:33 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:34 [#uses=1]
+ zext i8 %34 to i32 ; <i32>:35 [#uses=1]
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:36 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %36, i32 %35, i32 %33 ) ; <i32>:37 [#uses=1]
+ store i32 %37, i32* @si, align 4
+ load i8* @sc, align 1 ; <i8>:38 [#uses=1]
+ sext i8 %38 to i32 ; <i32>:39 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:40 [#uses=1]
+ zext i8 %40 to i32 ; <i32>:41 [#uses=1]
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:42 [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %42, i32 %41, i32 %39 ) ; <i32>:43 [#uses=1]
+ store i32 %43, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:44 [#uses=1]
+ sext i8 %44 to i64 ; <i64>:45 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:46 [#uses=1]
+ zext i8 %46 to i64 ; <i64>:47 [#uses=1]
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:48 [#uses=1]
+ call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %48, i64 %47, i64 %45 ) ; <i64>:49 [#uses=1]
+ store i64 %49, i64* @sl, align 8
+ load i8* @sc, align 1 ; <i8>:50 [#uses=1]
+ sext i8 %50 to i64 ; <i64>:51 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:52 [#uses=1]
+ zext i8 %52 to i64 ; <i64>:53 [#uses=1]
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:54 [#uses=1]
+ call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %54, i64 %53, i64 %51 ) ; <i64>:55 [#uses=1]
+ store i64 %55, i64* @ul, align 8
+ load i8* @sc, align 1 ; <i8>:56 [#uses=1]
+ sext i8 %56 to i64 ; <i64>:57 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:58 [#uses=1]
+ zext i8 %58 to i64 ; <i64>:59 [#uses=1]
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:60 [#uses=1]
+ call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %60, i64 %59, i64 %57 ) ; <i64>:61 [#uses=1]
+ store i64 %61, i64* @sll, align 8
+ load i8* @sc, align 1 ; <i8>:62 [#uses=1]
+ sext i8 %62 to i64 ; <i64>:63 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:64 [#uses=1]
+ zext i8 %64 to i64 ; <i64>:65 [#uses=1]
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:66 [#uses=1]
+ call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %66, i64 %65, i64 %63 ) ; <i64>:67 [#uses=1]
+ store i64 %67, i64* @ull, align 8
+ load i8* @sc, align 1 ; <i8>:68 [#uses=1]
+ zext i8 %68 to i32 ; <i32>:69 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:70 [#uses=1]
+ zext i8 %70 to i32 ; <i32>:71 [#uses=1]
+ trunc i32 %71 to i8 ; <i8>:72 [#uses=2]
+ trunc i32 %69 to i8 ; <i8>:73 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %72, i8 %73 ) ; <i8>:74 [#uses=1]
+ icmp eq i8 %74, %72 ; <i1>:75 [#uses=1]
+ zext i1 %75 to i8 ; <i8>:76 [#uses=1]
+ zext i8 %76 to i32 ; <i32>:77 [#uses=1]
+ store i32 %77, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:78 [#uses=1]
+ zext i8 %78 to i32 ; <i32>:79 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:80 [#uses=1]
+ zext i8 %80 to i32 ; <i32>:81 [#uses=1]
+ trunc i32 %81 to i8 ; <i8>:82 [#uses=2]
+ trunc i32 %79 to i8 ; <i8>:83 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %82, i8 %83 ) ; <i8>:84 [#uses=1]
+ icmp eq i8 %84, %82 ; <i1>:85 [#uses=1]
+ zext i1 %85 to i8 ; <i8>:86 [#uses=1]
+ zext i8 %86 to i32 ; <i32>:87 [#uses=1]
+ store i32 %87, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:88 [#uses=1]
+ sext i8 %88 to i16 ; <i16>:89 [#uses=1]
+ zext i16 %89 to i32 ; <i32>:90 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:91 [#uses=1]
+ zext i8 %91 to i32 ; <i32>:92 [#uses=1]
+ trunc i32 %92 to i8 ; <i8>:93 [#uses=2]
+ trunc i32 %90 to i8 ; <i8>:94 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i16* @ss to i8*), i8 %93, i8 %94 ) ; <i8>:95 [#uses=1]
+ icmp eq i8 %95, %93 ; <i1>:96 [#uses=1]
+ zext i1 %96 to i8 ; <i8>:97 [#uses=1]
+ zext i8 %97 to i32 ; <i32>:98 [#uses=1]
+ store i32 %98, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:99 [#uses=1]
+ sext i8 %99 to i16 ; <i16>:100 [#uses=1]
+ zext i16 %100 to i32 ; <i32>:101 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:102 [#uses=1]
+ zext i8 %102 to i32 ; <i32>:103 [#uses=1]
+ trunc i32 %103 to i8 ; <i8>:104 [#uses=2]
+ trunc i32 %101 to i8 ; <i8>:105 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i16* @us to i8*), i8 %104, i8 %105 ) ; <i8>:106 [#uses=1]
+ icmp eq i8 %106, %104 ; <i1>:107 [#uses=1]
+ zext i1 %107 to i8 ; <i8>:108 [#uses=1]
+ zext i8 %108 to i32 ; <i32>:109 [#uses=1]
+ store i32 %109, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:110 [#uses=1]
+ sext i8 %110 to i32 ; <i32>:111 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:112 [#uses=1]
+ zext i8 %112 to i32 ; <i32>:113 [#uses=1]
+ trunc i32 %113 to i8 ; <i8>:114 [#uses=2]
+ trunc i32 %111 to i8 ; <i8>:115 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i32* @si to i8*), i8 %114, i8 %115 ) ; <i8>:116 [#uses=1]
+ icmp eq i8 %116, %114 ; <i1>:117 [#uses=1]
+ zext i1 %117 to i8 ; <i8>:118 [#uses=1]
+ zext i8 %118 to i32 ; <i32>:119 [#uses=1]
+ store i32 %119, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:120 [#uses=1]
+ sext i8 %120 to i32 ; <i32>:121 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:122 [#uses=1]
+ zext i8 %122 to i32 ; <i32>:123 [#uses=1]
+ trunc i32 %123 to i8 ; <i8>:124 [#uses=2]
+ trunc i32 %121 to i8 ; <i8>:125 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i32* @ui to i8*), i8 %124, i8 %125 ) ; <i8>:126 [#uses=1]
+ icmp eq i8 %126, %124 ; <i1>:127 [#uses=1]
+ zext i1 %127 to i8 ; <i8>:128 [#uses=1]
+ zext i8 %128 to i32 ; <i32>:129 [#uses=1]
+ store i32 %129, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:130 [#uses=1]
+ sext i8 %130 to i64 ; <i64>:131 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:132 [#uses=1]
+ zext i8 %132 to i64 ; <i64>:133 [#uses=1]
+ trunc i64 %133 to i8 ; <i8>:134 [#uses=2]
+ trunc i64 %131 to i8 ; <i8>:135 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i64* @sl to i8*), i8 %134, i8 %135 ) ; <i8>:136 [#uses=1]
+ icmp eq i8 %136, %134 ; <i1>:137 [#uses=1]
+ zext i1 %137 to i8 ; <i8>:138 [#uses=1]
+ zext i8 %138 to i32 ; <i32>:139 [#uses=1]
+ store i32 %139, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:140 [#uses=1]
+ sext i8 %140 to i64 ; <i64>:141 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:142 [#uses=1]
+ zext i8 %142 to i64 ; <i64>:143 [#uses=1]
+ trunc i64 %143 to i8 ; <i8>:144 [#uses=2]
+ trunc i64 %141 to i8 ; <i8>:145 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i64* @ul to i8*), i8 %144, i8 %145 ) ; <i8>:146 [#uses=1]
+ icmp eq i8 %146, %144 ; <i1>:147 [#uses=1]
+ zext i1 %147 to i8 ; <i8>:148 [#uses=1]
+ zext i8 %148 to i32 ; <i32>:149 [#uses=1]
+ store i32 %149, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:150 [#uses=1]
+ sext i8 %150 to i64 ; <i64>:151 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:152 [#uses=1]
+ zext i8 %152 to i64 ; <i64>:153 [#uses=1]
+ trunc i64 %153 to i8 ; <i8>:154 [#uses=2]
+ trunc i64 %151 to i8 ; <i8>:155 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i64* @sll to i8*), i8 %154, i8 %155 ) ; <i8>:156 [#uses=1]
+ icmp eq i8 %156, %154 ; <i1>:157 [#uses=1]
+ zext i1 %157 to i8 ; <i8>:158 [#uses=1]
+ zext i8 %158 to i32 ; <i32>:159 [#uses=1]
+ store i32 %159, i32* @ui, align 4
+ load i8* @sc, align 1 ; <i8>:160 [#uses=1]
+ sext i8 %160 to i64 ; <i64>:161 [#uses=1]
+ load i8* @uc, align 1 ; <i8>:162 [#uses=1]
+ zext i8 %162 to i64 ; <i64>:163 [#uses=1]
+ trunc i64 %163 to i8 ; <i8>:164 [#uses=2]
+ trunc i64 %161 to i8 ; <i8>:165 [#uses=1]
+ call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* bitcast (i64* @ull to i8*), i8 %164, i8 %165 ) ; <i8>:166 [#uses=1]
+ icmp eq i8 %166, %164 ; <i1>:167 [#uses=1]
+ zext i1 %167 to i8 ; <i8>:168 [#uses=1]
+ zext i8 %168 to i32 ; <i32>:169 [#uses=1]
+ store i32 %169, i32* @ui, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8*, i8, i8) nounwind
+
+declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16*, i16, i16) nounwind
+
+declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind
+
+declare i64 @llvm.atomic.cmp.swap.i64.p0i64(i64*, i64, i64) nounwind
+
+define void @test_lock() nounwind {
+entry:
+ call i8 @llvm.atomic.swap.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:0 [#uses=1]
+ store i8 %0, i8* @sc, align 1
+ call i8 @llvm.atomic.swap.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:1 [#uses=1]
+ store i8 %1, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1]
+ call i16 @llvm.atomic.swap.i16.p0i16( i16* %2, i16 1 ) ; <i16>:3 [#uses=1]
+ store i16 %3, i16* @ss, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1]
+ call i16 @llvm.atomic.swap.i16.p0i16( i16* %4, i16 1 ) ; <i16>:5 [#uses=1]
+ store i16 %5, i16* @us, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1]
+ call i32 @llvm.atomic.swap.i32.p0i32( i32* %6, i32 1 ) ; <i32>:7 [#uses=1]
+ store i32 %7, i32* @si, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1]
+ call i32 @llvm.atomic.swap.i32.p0i32( i32* %8, i32 1 ) ; <i32>:9 [#uses=1]
+ store i32 %9, i32* @ui, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:10 [#uses=1]
+ call i64 @llvm.atomic.swap.i64.p0i64( i64* %10, i64 1 ) ; <i64>:11 [#uses=1]
+ store i64 %11, i64* @sl, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:12 [#uses=1]
+ call i64 @llvm.atomic.swap.i64.p0i64( i64* %12, i64 1 ) ; <i64>:13 [#uses=1]
+ store i64 %13, i64* @ul, align 8
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:14 [#uses=1]
+ call i64 @llvm.atomic.swap.i64.p0i64( i64* %14, i64 1 ) ; <i64>:15 [#uses=1]
+ store i64 %15, i64* @sll, align 8
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:16 [#uses=1]
+ call i64 @llvm.atomic.swap.i64.p0i64( i64* %16, i64 1 ) ; <i64>:17 [#uses=1]
+ store i64 %17, i64* @ull, align 8
+ call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true, i1 false )
+ volatile store i8 0, i8* @sc, align 1
+ volatile store i8 0, i8* @uc, align 1
+ bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:18 [#uses=1]
+ volatile store i16 0, i16* %18, align 2
+ bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:19 [#uses=1]
+ volatile store i16 0, i16* %19, align 2
+ bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:20 [#uses=1]
+ volatile store i32 0, i32* %20, align 4
+ bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:21 [#uses=1]
+ volatile store i32 0, i32* %21, align 4
+ bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:22 [#uses=1]
+ volatile store i64 0, i64* %22, align 8
+ bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:23 [#uses=1]
+ volatile store i64 0, i64* %23, align 8
+ bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:24 [#uses=1]
+ volatile store i64 0, i64* %24, align 8
+ bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:25 [#uses=1]
+ volatile store i64 0, i64* %25, align 8
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i8 @llvm.atomic.swap.i8.p0i8(i8*, i8) nounwind
+
+declare i16 @llvm.atomic.swap.i16.p0i16(i16*, i16) nounwind
+
+declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind
+
+declare i64 @llvm.atomic.swap.i64.p0i64(i64*, i64) nounwind
+
+declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind
diff --git a/test/CodeGen/X86/SwitchLowering.ll b/test/CodeGen/X86/SwitchLowering.ll
new file mode 100644
index 0000000..29a0e82
--- /dev/null
+++ b/test/CodeGen/X86/SwitchLowering.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=x86 | grep cmp | count 1
+; PR964
+
+define i8* @FindChar(i8* %CurPtr) {
+entry:
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
+ %CurPtr_addr.0.rec = bitcast i32 %indvar to i32 ; <i32> [#uses=1]
+ %gep.upgrd.1 = zext i32 %indvar to i64 ; <i64> [#uses=1]
+ %CurPtr_addr.0 = getelementptr i8* %CurPtr, i64 %gep.upgrd.1 ; <i8*> [#uses=1]
+ %tmp = load i8* %CurPtr_addr.0 ; <i8> [#uses=3]
+ %tmp2.rec = add i32 %CurPtr_addr.0.rec, 1 ; <i32> [#uses=1]
+ %tmp2 = getelementptr i8* %CurPtr, i32 %tmp2.rec ; <i8*> [#uses=1]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ switch i8 %tmp, label %bb [
+ i8 0, label %bb7
+ i8 120, label %bb7
+ ]
+
+bb7: ; preds = %bb, %bb
+ tail call void @foo( i8 %tmp )
+ ret i8* %tmp2
+}
+
+declare void @foo(i8)
+
diff --git a/test/CodeGen/X86/abi-isel.ll b/test/CodeGen/X86/abi-isel.ll
new file mode 100644
index 0000000..9208738
--- /dev/null
+++ b/test/CodeGen/X86/abi-isel.ll
@@ -0,0 +1,9646 @@
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-32-STATIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-32-PIC
+
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-64-STATIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-64-PIC
+
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-32-STATIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=dynamic-no-pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-32-DYNAMIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-32-PIC
+
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-64-STATIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC
+; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-64-PIC
+
+@src = external global [131072 x i32]
+@dst = external global [131072 x i32]
+@xsrc = external global [32 x i32]
+@xdst = external global [32 x i32]
+@ptr = external global i32*
+@dsrc = global [131072 x i32] zeroinitializer, align 32
+@ddst = global [131072 x i32] zeroinitializer, align 32
+@dptr = global i32* null
+@lsrc = internal global [131072 x i32] zeroinitializer
+@ldst = internal global [131072 x i32] zeroinitializer
+@lptr = internal global i32* null
+@ifunc = external global void ()*
+@difunc = global void ()* null
+@lifunc = internal global void ()* null
+@lxsrc = internal global [32 x i32] zeroinitializer, align 32
+@lxdst = internal global [32 x i32] zeroinitializer, align 32
+@dxsrc = global [32 x i32] zeroinitializer, align 32
+@dxdst = global [32 x i32] zeroinitializer, align 32
+
+define void @foo00() nounwind {
+entry:
+ %0 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 0), align 4
+ store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 0), align 4
+ ret void
+
+; LINUX-64-STATIC: foo00:
+; LINUX-64-STATIC: movl src(%rip), %eax
+; LINUX-64-STATIC: movl %eax, dst
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: foo00:
+; LINUX-32-STATIC: movl src, %eax
+; LINUX-32-STATIC-NEXT: movl %eax, dst
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: foo00:
+; LINUX-32-PIC: movl src, %eax
+; LINUX-32-PIC-NEXT: movl %eax, dst
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: foo00:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl (%rax), %eax
+; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _foo00:
+; DARWIN-32-STATIC: movl _src, %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _dst
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _foo00:
+; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _foo00:
+; DARWIN-32-PIC: call L1$pb
+; DARWIN-32-PIC-NEXT: L1$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L1$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L1$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _foo00:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl (%rax), %eax
+; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _foo00:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl (%rax), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _foo00:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl (%rax), %eax
+; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @fxo00() nounwind {
+entry:
+ %0 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 0), align 4
+ store i32 %0, i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 0), align 4
+ ret void
+
+; LINUX-64-STATIC: fxo00:
+; LINUX-64-STATIC: movl xsrc(%rip), %eax
+; LINUX-64-STATIC: movl %eax, xdst
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: fxo00:
+; LINUX-32-STATIC: movl xsrc, %eax
+; LINUX-32-STATIC-NEXT: movl %eax, xdst
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: fxo00:
+; LINUX-32-PIC: movl xsrc, %eax
+; LINUX-32-PIC-NEXT: movl %eax, xdst
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: fxo00:
+; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl (%rax), %eax
+; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _fxo00:
+; DARWIN-32-STATIC: movl _xsrc, %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _xdst
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _fxo00:
+; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _fxo00:
+; DARWIN-32-PIC: call L2$pb
+; DARWIN-32-PIC-NEXT: L2$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L2$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L2$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _fxo00:
+; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl (%rax), %eax
+; DARWIN-64-STATIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _fxo00:
+; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl (%rax), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _fxo00:
+; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl (%rax), %eax
+; DARWIN-64-PIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @foo01() nounwind {
+entry:
+ store i32* getelementptr ([131072 x i32]* @dst, i32 0, i32 0), i32** @ptr, align 8
+ ret void
+; LINUX-64-STATIC: foo01:
+; LINUX-64-STATIC: movq $dst, ptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: foo01:
+; LINUX-32-STATIC: movl $dst, ptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: foo01:
+; LINUX-32-PIC: movl $dst, ptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: foo01:
+; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _foo01:
+; DARWIN-32-STATIC: movl $_dst, _ptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _foo01:
+; DARWIN-32-DYNAMIC: movl L_dst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _foo01:
+; DARWIN-32-PIC: call L3$pb
+; DARWIN-32-PIC-NEXT: L3$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L3$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L3$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _foo01:
+; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _foo01:
+; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _foo01:
+; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @fxo01() nounwind {
+entry:
+ store i32* getelementptr ([32 x i32]* @xdst, i32 0, i32 0), i32** @ptr, align 8
+ ret void
+; LINUX-64-STATIC: fxo01:
+; LINUX-64-STATIC: movq $xdst, ptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: fxo01:
+; LINUX-32-STATIC: movl $xdst, ptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: fxo01:
+; LINUX-32-PIC: movl $xdst, ptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: fxo01:
+; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _fxo01:
+; DARWIN-32-STATIC: movl $_xdst, _ptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _fxo01:
+; DARWIN-32-DYNAMIC: movl L_xdst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _fxo01:
+; DARWIN-32-PIC: call L4$pb
+; DARWIN-32-PIC-NEXT: L4$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L4$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L4$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _fxo01:
+; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _fxo01:
+; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _fxo01:
+; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @foo02() nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 0), align 4
+ store i32 %1, i32* %0, align 4
+ ret void
+; LINUX-64-STATIC: foo02:
+; LINUX-64-STATIC: movl src(%rip), %
+; LINUX-64-STATIC: movq ptr(%rip), %
+; LINUX-64-STATIC: movl
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: foo02:
+; LINUX-32-STATIC: movl src, %eax
+; LINUX-32-STATIC-NEXT: movl ptr, %ecx
+; LINUX-32-STATIC-NEXT: movl %eax, (%ecx)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: foo02:
+; LINUX-32-PIC: movl src, %eax
+; LINUX-32-PIC-NEXT: movl ptr, %ecx
+; LINUX-32-PIC-NEXT: movl %eax, (%ecx)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: foo02:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl (%rax), %eax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _foo02:
+; DARWIN-32-STATIC: movl _src, %eax
+; DARWIN-32-STATIC-NEXT: movl _ptr, %ecx
+; DARWIN-32-STATIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _foo02:
+; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl (%ecx), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _foo02:
+; DARWIN-32-PIC: call L5$pb
+; DARWIN-32-PIC-NEXT: L5$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L5$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L5$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _foo02:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl (%rax), %eax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _foo02:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl (%rax), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _foo02:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl (%rax), %eax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @fxo02() nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 0), align 4
+ store i32 %1, i32* %0, align 4
+; LINUX-64-STATIC: fxo02:
+; LINUX-64-STATIC: movl xsrc(%rip), %
+; LINUX-64-STATIC: movq ptr(%rip), %
+; LINUX-64-STATIC: movl
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: fxo02:
+; LINUX-32-STATIC: movl xsrc, %eax
+; LINUX-32-STATIC-NEXT: movl ptr, %ecx
+; LINUX-32-STATIC-NEXT: movl %eax, (%ecx)
+; LINUX-32-STATIC-NEXT: ret
+ ret void
+
+; LINUX-32-PIC: fxo02:
+; LINUX-32-PIC: movl xsrc, %eax
+; LINUX-32-PIC-NEXT: movl ptr, %ecx
+; LINUX-32-PIC-NEXT: movl %eax, (%ecx)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: fxo02:
+; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl (%rax), %eax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _fxo02:
+; DARWIN-32-STATIC: movl _xsrc, %eax
+; DARWIN-32-STATIC-NEXT: movl _ptr, %ecx
+; DARWIN-32-STATIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _fxo02:
+; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl (%ecx), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _fxo02:
+; DARWIN-32-PIC: call L6$pb
+; DARWIN-32-PIC-NEXT: L6$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L6$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L6$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _fxo02:
+; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl (%rax), %eax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _fxo02:
+; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl (%rax), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _fxo02:
+; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl (%rax), %eax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @foo03() nounwind {
+entry:
+ %0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 0), align 32
+ store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 0), align 32
+ ret void
+; LINUX-64-STATIC: foo03:
+; LINUX-64-STATIC: movl dsrc(%rip), %eax
+; LINUX-64-STATIC: movl %eax, ddst
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: foo03:
+; LINUX-32-STATIC: movl dsrc, %eax
+; LINUX-32-STATIC-NEXT: movl %eax, ddst
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: foo03:
+; LINUX-32-PIC: movl dsrc, %eax
+; LINUX-32-PIC-NEXT: movl %eax, ddst
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: foo03:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl (%rax), %eax
+; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _foo03:
+; DARWIN-32-STATIC: movl _dsrc, %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _ddst
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _foo03:
+; DARWIN-32-DYNAMIC: movl _dsrc, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, _ddst
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _foo03:
+; DARWIN-32-PIC: call L7$pb
+; DARWIN-32-PIC-NEXT: L7$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl _dsrc-L7$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _ddst-L7$pb(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _foo03:
+; DARWIN-64-STATIC: movl _dsrc(%rip), %eax
+; DARWIN-64-STATIC-NEXT: movl %eax, _ddst(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _foo03:
+; DARWIN-64-DYNAMIC: movl _dsrc(%rip), %eax
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, _ddst(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _foo03:
+; DARWIN-64-PIC: movl _dsrc(%rip), %eax
+; DARWIN-64-PIC-NEXT: movl %eax, _ddst(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @foo04() nounwind {
+entry:
+ store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i32 0), i32** @dptr, align 8
+ ret void
+; LINUX-64-STATIC: foo04:
+; LINUX-64-STATIC: movq $ddst, dptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: foo04:
+; LINUX-32-STATIC: movl $ddst, dptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: foo04:
+; LINUX-32-PIC: movl $ddst, dptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: foo04:
+; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _foo04:
+; DARWIN-32-STATIC: movl $_ddst, _dptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _foo04:
+; DARWIN-32-DYNAMIC: movl $_ddst, _dptr
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _foo04:
+; DARWIN-32-PIC: call L8$pb
+; DARWIN-32-PIC-NEXT: L8$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal _ddst-L8$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L8$pb(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _foo04:
+; DARWIN-64-STATIC: leaq _ddst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _foo04:
+; DARWIN-64-DYNAMIC: leaq _ddst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _foo04:
+; DARWIN-64-PIC: leaq _ddst(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @foo05() nounwind {
+entry:
+ %0 = load i32** @dptr, align 8
+ %1 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 0), align 32
+ store i32 %1, i32* %0, align 4
+ ret void
+; LINUX-64-STATIC: foo05:
+; LINUX-64-STATIC: movl dsrc(%rip), %
+; LINUX-64-STATIC: movq dptr(%rip), %
+; LINUX-64-STATIC: movl
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: foo05:
+; LINUX-32-STATIC: movl dsrc, %eax
+; LINUX-32-STATIC-NEXT: movl dptr, %ecx
+; LINUX-32-STATIC-NEXT: movl %eax, (%ecx)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: foo05:
+; LINUX-32-PIC: movl dsrc, %eax
+; LINUX-32-PIC-NEXT: movl dptr, %ecx
+; LINUX-32-PIC-NEXT: movl %eax, (%ecx)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: foo05:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl (%rax), %eax
+; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _foo05:
+; DARWIN-32-STATIC: movl _dsrc, %eax
+; DARWIN-32-STATIC-NEXT: movl _dptr, %ecx
+; DARWIN-32-STATIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _foo05:
+; DARWIN-32-DYNAMIC: movl _dsrc, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _foo05:
+; DARWIN-32-PIC: call L9$pb
+; DARWIN-32-PIC-NEXT: L9$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl _dsrc-L9$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl _dptr-L9$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _foo05:
+; DARWIN-64-STATIC: movl _dsrc(%rip), %eax
+; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _foo05:
+; DARWIN-64-DYNAMIC: movl _dsrc(%rip), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _foo05:
+; DARWIN-64-PIC: movl _dsrc(%rip), %eax
+; DARWIN-64-PIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @foo06() nounwind {
+entry:
+ %0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 0), align 4
+ store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 0), align 4
+ ret void
+; LINUX-64-STATIC: foo06:
+; LINUX-64-STATIC: movl lsrc(%rip), %eax
+; LINUX-64-STATIC: movl %eax, ldst(%rip)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: foo06:
+; LINUX-32-STATIC: movl lsrc, %eax
+; LINUX-32-STATIC-NEXT: movl %eax, ldst
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: foo06:
+; LINUX-32-PIC: movl lsrc, %eax
+; LINUX-32-PIC-NEXT: movl %eax, ldst
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: foo06:
+; LINUX-64-PIC: movl lsrc(%rip), %eax
+; LINUX-64-PIC-NEXT: movl %eax, ldst(%rip)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _foo06:
+; DARWIN-32-STATIC: movl _lsrc, %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _ldst
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _foo06:
+; DARWIN-32-DYNAMIC: movl _lsrc, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, _ldst
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _foo06:
+; DARWIN-32-PIC: call L10$pb
+; DARWIN-32-PIC-NEXT: L10$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl _lsrc-L10$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _ldst-L10$pb(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _foo06:
+; DARWIN-64-STATIC: movl _lsrc(%rip), %eax
+; DARWIN-64-STATIC-NEXT: movl %eax, _ldst(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _foo06:
+; DARWIN-64-DYNAMIC: movl _lsrc(%rip), %eax
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, _ldst(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _foo06:
+; DARWIN-64-PIC: movl _lsrc(%rip), %eax
+; DARWIN-64-PIC-NEXT: movl %eax, _ldst(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @foo07() nounwind {
+entry:
+ store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i32 0), i32** @lptr, align 8
+ ret void
+; LINUX-64-STATIC: foo07:
+; LINUX-64-STATIC: movq $ldst, lptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: foo07:
+; LINUX-32-STATIC: movl $ldst, lptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: foo07:
+; LINUX-32-PIC: movl $ldst, lptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: foo07:
+; LINUX-64-PIC: leaq ldst(%rip), %rax
+; LINUX-64-PIC-NEXT: movq %rax, lptr(%rip)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _foo07:
+; DARWIN-32-STATIC: movl $_ldst, _lptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _foo07:
+; DARWIN-32-DYNAMIC: movl $_ldst, _lptr
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _foo07:
+; DARWIN-32-PIC: call L11$pb
+; DARWIN-32-PIC-NEXT: L11$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal _ldst-L11$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L11$pb(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _foo07:
+; DARWIN-64-STATIC: leaq _ldst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _foo07:
+; DARWIN-64-DYNAMIC: leaq _ldst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _foo07:
+; DARWIN-64-PIC: leaq _ldst(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @foo08() nounwind {
+entry:
+ %0 = load i32** @lptr, align 8
+ %1 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 0), align 4
+ store i32 %1, i32* %0, align 4
+ ret void
+; LINUX-64-STATIC: foo08:
+; LINUX-64-STATIC: movl lsrc(%rip), %
+; LINUX-64-STATIC: movq lptr(%rip), %
+; LINUX-64-STATIC: movl
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: foo08:
+; LINUX-32-STATIC: movl lsrc, %eax
+; LINUX-32-STATIC-NEXT: movl lptr, %ecx
+; LINUX-32-STATIC-NEXT: movl %eax, (%ecx)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: foo08:
+; LINUX-32-PIC: movl lsrc, %eax
+; LINUX-32-PIC-NEXT: movl lptr, %ecx
+; LINUX-32-PIC-NEXT: movl %eax, (%ecx)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: foo08:
+; LINUX-64-PIC: movl lsrc(%rip), %eax
+; LINUX-64-PIC-NEXT: movq lptr(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _foo08:
+; DARWIN-32-STATIC: movl _lsrc, %eax
+; DARWIN-32-STATIC-NEXT: movl _lptr, %ecx
+; DARWIN-32-STATIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _foo08:
+; DARWIN-32-DYNAMIC: movl _lsrc, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _foo08:
+; DARWIN-32-PIC: call L12$pb
+; DARWIN-32-PIC-NEXT: L12$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl _lsrc-L12$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl _lptr-L12$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _foo08:
+; DARWIN-64-STATIC: movl _lsrc(%rip), %eax
+; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _foo08:
+; DARWIN-64-DYNAMIC: movl _lsrc(%rip), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _foo08:
+; DARWIN-64-PIC: movl _lsrc(%rip), %eax
+; DARWIN-64-PIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, (%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @qux00() nounwind {
+entry:
+ %0 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16), align 4
+ store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16), align 4
+ ret void
+; LINUX-64-STATIC: qux00:
+; LINUX-64-STATIC: movl src+64(%rip), %eax
+; LINUX-64-STATIC: movl %eax, dst+64(%rip)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: qux00:
+; LINUX-32-STATIC: movl src+64, %eax
+; LINUX-32-STATIC-NEXT: movl %eax, dst+64
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: qux00:
+; LINUX-32-PIC: movl src+64, %eax
+; LINUX-32-PIC-NEXT: movl %eax, dst+64
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: qux00:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 64(%rax), %eax
+; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _qux00:
+; DARWIN-32-STATIC: movl _src+64, %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _dst+64
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _qux00:
+; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl 64(%eax), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, 64(%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _qux00:
+; DARWIN-32-PIC: call L13$pb
+; DARWIN-32-PIC-NEXT: L13$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L13$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L13$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _qux00:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 64(%rax), %eax
+; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _qux00:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _qux00:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 64(%rax), %eax
+; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @qxx00() nounwind {
+entry:
+ %0 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16), align 4
+ store i32 %0, i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16), align 4
+ ret void
+; LINUX-64-STATIC: qxx00:
+; LINUX-64-STATIC: movl xsrc+64(%rip), %eax
+; LINUX-64-STATIC: movl %eax, xdst+64(%rip)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: qxx00:
+; LINUX-32-STATIC: movl xsrc+64, %eax
+; LINUX-32-STATIC-NEXT: movl %eax, xdst+64
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: qxx00:
+; LINUX-32-PIC: movl xsrc+64, %eax
+; LINUX-32-PIC-NEXT: movl %eax, xdst+64
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: qxx00:
+; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 64(%rax), %eax
+; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _qxx00:
+; DARWIN-32-STATIC: movl _xsrc+64, %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _xdst+64
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _qxx00:
+; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl 64(%eax), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, 64(%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _qxx00:
+; DARWIN-32-PIC: call L14$pb
+; DARWIN-32-PIC-NEXT: L14$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L14$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L14$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _qxx00:
+; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 64(%rax), %eax
+; DARWIN-64-STATIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _qxx00:
+; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _qxx00:
+; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 64(%rax), %eax
+; DARWIN-64-PIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @qux01() nounwind {
+entry:
+ store i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16), i32** @ptr, align 8
+ ret void
+; LINUX-64-STATIC: qux01:
+; LINUX-64-STATIC: movq $dst+64, ptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: qux01:
+; LINUX-32-STATIC: movl $dst+64, ptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: qux01:
+; LINUX-32-PIC: movl $dst+64, ptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: qux01:
+; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: addq $64, %rax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _qux01:
+; DARWIN-32-STATIC: movl $_dst+64, _ptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _qux01:
+; DARWIN-32-DYNAMIC: movl L_dst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl $64, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _qux01:
+; DARWIN-32-PIC: call L15$pb
+; DARWIN-32-PIC-NEXT: L15$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L15$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: addl $64, %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L15$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _qux01:
+; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: addq $64, %rax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _qux01:
+; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: addq $64, %rax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _qux01:
+; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: addq $64, %rax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @qxx01() nounwind {
+entry:
+ store i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16), i32** @ptr, align 8
+ ret void
+; LINUX-64-STATIC: qxx01:
+; LINUX-64-STATIC: movq $xdst+64, ptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: qxx01:
+; LINUX-32-STATIC: movl $xdst+64, ptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: qxx01:
+; LINUX-32-PIC: movl $xdst+64, ptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: qxx01:
+; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: addq $64, %rax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _qxx01:
+; DARWIN-32-STATIC: movl $_xdst+64, _ptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _qxx01:
+; DARWIN-32-DYNAMIC: movl L_xdst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl $64, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _qxx01:
+; DARWIN-32-PIC: call L16$pb
+; DARWIN-32-PIC-NEXT: L16$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L16$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: addl $64, %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L16$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _qxx01:
+; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: addq $64, %rax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _qxx01:
+; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: addq $64, %rax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _qxx01:
+; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: addq $64, %rax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @qux02() nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16), align 4
+ %2 = getelementptr i32* %0, i64 16
+ store i32 %1, i32* %2, align 4
+; LINUX-64-STATIC: qux02:
+; LINUX-64-STATIC: movl src+64(%rip), %eax
+; LINUX-64-STATIC: movq ptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, 64(%rcx)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: qux02:
+; LINUX-32-STATIC: movl src+64, %eax
+; LINUX-32-STATIC-NEXT: movl ptr, %ecx
+; LINUX-32-STATIC-NEXT: movl %eax, 64(%ecx)
+; LINUX-32-STATIC-NEXT: ret
+ ret void
+
+; LINUX-32-PIC: qux02:
+; LINUX-32-PIC: movl src+64, %eax
+; LINUX-32-PIC-NEXT: movl ptr, %ecx
+; LINUX-32-PIC-NEXT: movl %eax, 64(%ecx)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: qux02:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 64(%rax), %eax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _qux02:
+; DARWIN-32-STATIC: movl _src+64, %eax
+; DARWIN-32-STATIC-NEXT: movl _ptr, %ecx
+; DARWIN-32-STATIC-NEXT: movl %eax, 64(%ecx)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _qux02:
+; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl 64(%eax), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl (%ecx), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, 64(%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _qux02:
+; DARWIN-32-PIC: call L17$pb
+; DARWIN-32-PIC-NEXT: L17$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L17$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L17$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _qux02:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 64(%rax), %eax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _qux02:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _qux02:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 64(%rax), %eax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @qxx02() nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16), align 4
+ %2 = getelementptr i32* %0, i64 16
+ store i32 %1, i32* %2, align 4
+; LINUX-64-STATIC: qxx02:
+; LINUX-64-STATIC: movl xsrc+64(%rip), %eax
+; LINUX-64-STATIC: movq ptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, 64(%rcx)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: qxx02:
+; LINUX-32-STATIC: movl xsrc+64, %eax
+; LINUX-32-STATIC-NEXT: movl ptr, %ecx
+; LINUX-32-STATIC-NEXT: movl %eax, 64(%ecx)
+; LINUX-32-STATIC-NEXT: ret
+ ret void
+
+; LINUX-32-PIC: qxx02:
+; LINUX-32-PIC: movl xsrc+64, %eax
+; LINUX-32-PIC-NEXT: movl ptr, %ecx
+; LINUX-32-PIC-NEXT: movl %eax, 64(%ecx)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: qxx02:
+; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 64(%rax), %eax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _qxx02:
+; DARWIN-32-STATIC: movl _xsrc+64, %eax
+; DARWIN-32-STATIC-NEXT: movl _ptr, %ecx
+; DARWIN-32-STATIC-NEXT: movl %eax, 64(%ecx)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _qxx02:
+; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl 64(%eax), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl (%ecx), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, 64(%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _qxx02:
+; DARWIN-32-PIC: call L18$pb
+; DARWIN-32-PIC-NEXT: L18$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L18$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L18$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _qxx02:
+; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 64(%rax), %eax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _qxx02:
+; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _qxx02:
+; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 64(%rax), %eax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @qux03() nounwind {
+entry:
+ %0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16), align 32
+ store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16), align 32
+ ret void
+; LINUX-64-STATIC: qux03:
+; LINUX-64-STATIC: movl dsrc+64(%rip), %eax
+; LINUX-64-STATIC: movl %eax, ddst+64(%rip)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: qux03:
+; LINUX-32-STATIC: movl dsrc+64, %eax
+; LINUX-32-STATIC-NEXT: movl %eax, ddst+64
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: qux03:
+; LINUX-32-PIC: movl dsrc+64, %eax
+; LINUX-32-PIC-NEXT: movl %eax, ddst+64
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: qux03:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 64(%rax), %eax
+; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _qux03:
+; DARWIN-32-STATIC: movl _dsrc+64, %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _ddst+64
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _qux03:
+; DARWIN-32-DYNAMIC: movl _dsrc+64, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, _ddst+64
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _qux03:
+; DARWIN-32-PIC: call L19$pb
+; DARWIN-32-PIC-NEXT: L19$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L19$pb)+64(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L19$pb)+64(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _qux03:
+; DARWIN-64-STATIC: movl _dsrc+64(%rip), %eax
+; DARWIN-64-STATIC-NEXT: movl %eax, _ddst+64(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _qux03:
+; DARWIN-64-DYNAMIC: movl _dsrc+64(%rip), %eax
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, _ddst+64(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _qux03:
+; DARWIN-64-PIC: movl _dsrc+64(%rip), %eax
+; DARWIN-64-PIC-NEXT: movl %eax, _ddst+64(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @qux04() nounwind {
+entry:
+ store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16), i32** @dptr, align 8
+ ret void
+; LINUX-64-STATIC: qux04:
+; LINUX-64-STATIC: movq $ddst+64, dptr(%rip)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: qux04:
+; LINUX-32-STATIC: movl $ddst+64, dptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: qux04:
+; LINUX-32-PIC: movl $ddst+64, dptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: qux04:
+; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: addq $64, %rax
+; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _qux04:
+; DARWIN-32-STATIC: movl $_ddst+64, _dptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _qux04:
+; DARWIN-32-DYNAMIC: movl $_ddst+64, _dptr
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _qux04:
+; DARWIN-32-PIC: call L20$pb
+; DARWIN-32-PIC-NEXT: L20$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal (_ddst-L20$pb)+64(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L20$pb(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _qux04:
+; DARWIN-64-STATIC: leaq _ddst+64(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _qux04:
+; DARWIN-64-DYNAMIC: leaq _ddst+64(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _qux04:
+; DARWIN-64-PIC: leaq _ddst+64(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @qux05() nounwind {
+entry:
+ %0 = load i32** @dptr, align 8
+ %1 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16), align 32
+ %2 = getelementptr i32* %0, i64 16
+ store i32 %1, i32* %2, align 4
+; LINUX-64-STATIC: qux05:
+; LINUX-64-STATIC: movl dsrc+64(%rip), %eax
+; LINUX-64-STATIC: movq dptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, 64(%rcx)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: qux05:
+; LINUX-32-STATIC: movl dsrc+64, %eax
+; LINUX-32-STATIC-NEXT: movl dptr, %ecx
+; LINUX-32-STATIC-NEXT: movl %eax, 64(%ecx)
+; LINUX-32-STATIC-NEXT: ret
+ ret void
+
+; LINUX-32-PIC: qux05:
+; LINUX-32-PIC: movl dsrc+64, %eax
+; LINUX-32-PIC-NEXT: movl dptr, %ecx
+; LINUX-32-PIC-NEXT: movl %eax, 64(%ecx)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: qux05:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 64(%rax), %eax
+; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _qux05:
+; DARWIN-32-STATIC: movl _dsrc+64, %eax
+; DARWIN-32-STATIC-NEXT: movl _dptr, %ecx
+; DARWIN-32-STATIC-NEXT: movl %eax, 64(%ecx)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _qux05:
+; DARWIN-32-DYNAMIC: movl _dsrc+64, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, 64(%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _qux05:
+; DARWIN-32-PIC: call L21$pb
+; DARWIN-32-PIC-NEXT: L21$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L21$pb)+64(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl _dptr-L21$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _qux05:
+; DARWIN-64-STATIC: movl _dsrc+64(%rip), %eax
+; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _qux05:
+; DARWIN-64-DYNAMIC: movl _dsrc+64(%rip), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _qux05:
+; DARWIN-64-PIC: movl _dsrc+64(%rip), %eax
+; DARWIN-64-PIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @qux06() nounwind {
+entry:
+ %0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16), align 4
+ store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16), align 4
+ ret void
+; LINUX-64-STATIC: qux06:
+; LINUX-64-STATIC: movl lsrc+64(%rip), %eax
+; LINUX-64-STATIC: movl %eax, ldst+64
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: qux06:
+; LINUX-32-STATIC: movl lsrc+64, %eax
+; LINUX-32-STATIC-NEXT: movl %eax, ldst+64
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: qux06:
+; LINUX-32-PIC: movl lsrc+64, %eax
+; LINUX-32-PIC-NEXT: movl %eax, ldst+64
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: qux06:
+; LINUX-64-PIC: movl lsrc+64(%rip), %eax
+; LINUX-64-PIC-NEXT: movl %eax, ldst+64(%rip)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _qux06:
+; DARWIN-32-STATIC: movl _lsrc+64, %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _ldst+64
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _qux06:
+; DARWIN-32-DYNAMIC: movl _lsrc+64, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, _ldst+64
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _qux06:
+; DARWIN-32-PIC: call L22$pb
+; DARWIN-32-PIC-NEXT: L22$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L22$pb)+64(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L22$pb)+64(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _qux06:
+; DARWIN-64-STATIC: movl _lsrc+64(%rip), %eax
+; DARWIN-64-STATIC-NEXT: movl %eax, _ldst+64(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _qux06:
+; DARWIN-64-DYNAMIC: movl _lsrc+64(%rip), %eax
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, _ldst+64(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _qux06:
+; DARWIN-64-PIC: movl _lsrc+64(%rip), %eax
+; DARWIN-64-PIC-NEXT: movl %eax, _ldst+64(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @qux07() nounwind {
+entry:
+ store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16), i32** @lptr, align 8
+ ret void
+; LINUX-64-STATIC: qux07:
+; LINUX-64-STATIC: movq $ldst+64, lptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: qux07:
+; LINUX-32-STATIC: movl $ldst+64, lptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: qux07:
+; LINUX-32-PIC: movl $ldst+64, lptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: qux07:
+; LINUX-64-PIC: leaq ldst+64(%rip), %rax
+; LINUX-64-PIC-NEXT: movq %rax, lptr(%rip)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _qux07:
+; DARWIN-32-STATIC: movl $_ldst+64, _lptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _qux07:
+; DARWIN-32-DYNAMIC: movl $_ldst+64, _lptr
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _qux07:
+; DARWIN-32-PIC: call L23$pb
+; DARWIN-32-PIC-NEXT: L23$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal (_ldst-L23$pb)+64(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L23$pb(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _qux07:
+; DARWIN-64-STATIC: leaq _ldst+64(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _qux07:
+; DARWIN-64-DYNAMIC: leaq _ldst+64(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _qux07:
+; DARWIN-64-PIC: leaq _ldst+64(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @qux08() nounwind {
+entry:
+ %0 = load i32** @lptr, align 8
+ %1 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16), align 4
+ %2 = getelementptr i32* %0, i64 16
+ store i32 %1, i32* %2, align 4
+; LINUX-64-STATIC: qux08:
+; LINUX-64-STATIC: movl lsrc+64(%rip), %eax
+; LINUX-64-STATIC: movq lptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, 64(%rcx)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: qux08:
+; LINUX-32-STATIC: movl lsrc+64, %eax
+; LINUX-32-STATIC-NEXT: movl lptr, %ecx
+; LINUX-32-STATIC-NEXT: movl %eax, 64(%ecx)
+; LINUX-32-STATIC-NEXT: ret
+ ret void
+
+; LINUX-32-PIC: qux08:
+; LINUX-32-PIC: movl lsrc+64, %eax
+; LINUX-32-PIC-NEXT: movl lptr, %ecx
+; LINUX-32-PIC-NEXT: movl %eax, 64(%ecx)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: qux08:
+; LINUX-64-PIC: movl lsrc+64(%rip), %eax
+; LINUX-64-PIC-NEXT: movq lptr(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _qux08:
+; DARWIN-32-STATIC: movl _lsrc+64, %eax
+; DARWIN-32-STATIC-NEXT: movl _lptr, %ecx
+; DARWIN-32-STATIC-NEXT: movl %eax, 64(%ecx)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _qux08:
+; DARWIN-32-DYNAMIC: movl _lsrc+64, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, 64(%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _qux08:
+; DARWIN-32-PIC: call L24$pb
+; DARWIN-32-PIC-NEXT: L24$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L24$pb)+64(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl _lptr-L24$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _qux08:
+; DARWIN-64-STATIC: movl _lsrc+64(%rip), %eax
+; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _qux08:
+; DARWIN-64-DYNAMIC: movl _lsrc+64(%rip), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _qux08:
+; DARWIN-64-PIC: movl _lsrc+64(%rip), %eax
+; DARWIN-64-PIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @ind00(i64 %i) nounwind {
+entry:
+ %0 = getelementptr [131072 x i32]* @src, i64 0, i64 %i
+ %1 = load i32* %0, align 4
+ %2 = getelementptr [131072 x i32]* @dst, i64 0, i64 %i
+ store i32 %1, i32* %2, align 4
+ ret void
+; LINUX-64-STATIC: ind00:
+; LINUX-64-STATIC: movl src(,%rdi,4), %eax
+; LINUX-64-STATIC: movl %eax, dst(,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: ind00:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl src(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl %ecx, dst(,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: ind00:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl src(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, dst(,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: ind00:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _ind00:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _src(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl %ecx, _dst(,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _ind00:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl (%ecx,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, (%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _ind00:
+; DARWIN-32-PIC: call L25$pb
+; DARWIN-32-PIC-NEXT: L25$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L25$pb(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L25$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _ind00:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _ind00:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _ind00:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @ixd00(i64 %i) nounwind {
+entry:
+ %0 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %i
+ %1 = load i32* %0, align 4
+ %2 = getelementptr [32 x i32]* @xdst, i64 0, i64 %i
+ store i32 %1, i32* %2, align 4
+ ret void
+; LINUX-64-STATIC: ixd00:
+; LINUX-64-STATIC: movl xsrc(,%rdi,4), %eax
+; LINUX-64-STATIC: movl %eax, xdst(,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: ixd00:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl xsrc(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl %ecx, xdst(,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: ixd00:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl xsrc(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, xdst(,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: ixd00:
+; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _ixd00:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _xsrc(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl %ecx, _xdst(,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _ixd00:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl (%ecx,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, (%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _ixd00:
+; DARWIN-32-PIC: call L26$pb
+; DARWIN-32-PIC-NEXT: L26$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L26$pb(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L26$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _ixd00:
+; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _ixd00:
+; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _ixd00:
+; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @ind01(i64 %i) nounwind {
+entry:
+ %0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %i
+ store i32* %0, i32** @ptr, align 8
+ ret void
+; LINUX-64-STATIC: ind01:
+; LINUX-64-STATIC: leaq dst(,%rdi,4), %rax
+; LINUX-64-STATIC: movq %rax, ptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: ind01:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal dst(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: movl %eax, ptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: ind01:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal dst(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: movl %eax, ptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: ind01:
+; LINUX-64-PIC: shlq $2, %rdi
+; LINUX-64-PIC-NEXT: addq dst@GOTPCREL(%rip), %rdi
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq %rdi, (%rax)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _ind01:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _dst(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _ptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _ind01:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: shll $2, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl L_dst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _ind01:
+; DARWIN-32-PIC: call L27$pb
+; DARWIN-32-PIC-NEXT: L27$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: shll $2, %ecx
+; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L27$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L27$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _ind01:
+; DARWIN-64-STATIC: shlq $2, %rdi
+; DARWIN-64-STATIC-NEXT: addq _dst@GOTPCREL(%rip), %rdi
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq %rdi, (%rax)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _ind01:
+; DARWIN-64-DYNAMIC: shlq $2, %rdi
+; DARWIN-64-DYNAMIC-NEXT: addq _dst@GOTPCREL(%rip), %rdi
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq %rdi, (%rax)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _ind01:
+; DARWIN-64-PIC: shlq $2, %rdi
+; DARWIN-64-PIC-NEXT: addq _dst@GOTPCREL(%rip), %rdi
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq %rdi, (%rax)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @ixd01(i64 %i) nounwind {
+entry:
+ %0 = getelementptr [32 x i32]* @xdst, i64 0, i64 %i
+ store i32* %0, i32** @ptr, align 8
+ ret void
+; LINUX-64-STATIC: ixd01:
+; LINUX-64-STATIC: leaq xdst(,%rdi,4), %rax
+; LINUX-64-STATIC: movq %rax, ptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: ixd01:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal xdst(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: movl %eax, ptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: ixd01:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal xdst(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: movl %eax, ptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: ixd01:
+; LINUX-64-PIC: shlq $2, %rdi
+; LINUX-64-PIC-NEXT: addq xdst@GOTPCREL(%rip), %rdi
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq %rdi, (%rax)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _ixd01:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _xdst(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _ptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _ixd01:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: shll $2, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl L_xdst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _ixd01:
+; DARWIN-32-PIC: call L28$pb
+; DARWIN-32-PIC-NEXT: L28$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: shll $2, %ecx
+; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L28$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L28$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _ixd01:
+; DARWIN-64-STATIC: shlq $2, %rdi
+; DARWIN-64-STATIC-NEXT: addq _xdst@GOTPCREL(%rip), %rdi
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq %rdi, (%rax)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _ixd01:
+; DARWIN-64-DYNAMIC: shlq $2, %rdi
+; DARWIN-64-DYNAMIC-NEXT: addq _xdst@GOTPCREL(%rip), %rdi
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq %rdi, (%rax)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _ixd01:
+; DARWIN-64-PIC: shlq $2, %rdi
+; DARWIN-64-PIC-NEXT: addq _xdst@GOTPCREL(%rip), %rdi
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq %rdi, (%rax)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @ind02(i64 %i) nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = getelementptr [131072 x i32]* @src, i64 0, i64 %i
+ %2 = load i32* %1, align 4
+ %3 = getelementptr i32* %0, i64 %i
+ store i32 %2, i32* %3, align 4
+ ret void
+; LINUX-64-STATIC: ind02:
+; LINUX-64-STATIC: movl src(,%rdi,4), %eax
+; LINUX-64-STATIC: movq ptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, (%rcx,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: ind02:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl src(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl ptr, %edx
+; LINUX-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: ind02:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl src(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl ptr, %edx
+; LINUX-32-PIC-NEXT: movl %ecx, (%edx,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: ind02:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _ind02:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _src(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl _ptr, %edx
+; DARWIN-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _ind02:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl (%ecx,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl (%edx), %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, (%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _ind02:
+; DARWIN-32-PIC: call L29$pb
+; DARWIN-32-PIC-NEXT: L29$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L29$pb(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L29$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _ind02:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _ind02:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _ind02:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @ixd02(i64 %i) nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %i
+ %2 = load i32* %1, align 4
+ %3 = getelementptr i32* %0, i64 %i
+ store i32 %2, i32* %3, align 4
+ ret void
+; LINUX-64-STATIC: ixd02:
+; LINUX-64-STATIC: movl xsrc(,%rdi,4), %eax
+; LINUX-64-STATIC: movq ptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, (%rcx,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: ixd02:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl xsrc(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl ptr, %edx
+; LINUX-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: ixd02:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl xsrc(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl ptr, %edx
+; LINUX-32-PIC-NEXT: movl %ecx, (%edx,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: ixd02:
+; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _ixd02:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _xsrc(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl _ptr, %edx
+; DARWIN-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _ixd02:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl (%ecx,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl (%edx), %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, (%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _ixd02:
+; DARWIN-32-PIC: call L30$pb
+; DARWIN-32-PIC-NEXT: L30$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L30$pb(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L30$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _ixd02:
+; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _ixd02:
+; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _ixd02:
+; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @ind03(i64 %i) nounwind {
+entry:
+ %0 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %i
+ %1 = load i32* %0, align 4
+ %2 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %i
+ store i32 %1, i32* %2, align 4
+ ret void
+; LINUX-64-STATIC: ind03:
+; LINUX-64-STATIC: movl dsrc(,%rdi,4), %eax
+; LINUX-64-STATIC: movl %eax, ddst(,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: ind03:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl dsrc(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl %ecx, ddst(,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: ind03:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl dsrc(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, ddst(,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: ind03:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _ind03:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _dsrc(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl %ecx, _ddst(,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _ind03:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _dsrc(,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, _ddst(,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _ind03:
+; DARWIN-32-PIC: call L31$pb
+; DARWIN-32-PIC-NEXT: L31$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl _dsrc-L31$pb(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl %edx, _ddst-L31$pb(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _ind03:
+; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: leaq _ddst(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _ind03:
+; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: leaq _ddst(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _ind03:
+; DARWIN-64-PIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: leaq _ddst(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @ind04(i64 %i) nounwind {
+entry:
+ %0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %i
+ store i32* %0, i32** @dptr, align 8
+ ret void
+; LINUX-64-STATIC: ind04:
+; LINUX-64-STATIC: leaq ddst(,%rdi,4), %rax
+; LINUX-64-STATIC: movq %rax, dptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: ind04:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal ddst(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: movl %eax, dptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: ind04:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal ddst(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: movl %eax, dptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: ind04:
+; LINUX-64-PIC: shlq $2, %rdi
+; LINUX-64-PIC-NEXT: addq ddst@GOTPCREL(%rip), %rdi
+; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq %rdi, (%rax)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _ind04:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _ddst(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _dptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _ind04:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: leal _ddst(,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, _dptr
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _ind04:
+; DARWIN-32-PIC: call L32$pb
+; DARWIN-32-PIC-NEXT: L32$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal _ddst-L32$pb(%eax,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L32$pb(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _ind04:
+; DARWIN-64-STATIC: leaq _ddst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq (%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _ind04:
+; DARWIN-64-DYNAMIC: leaq _ddst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq (%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _ind04:
+; DARWIN-64-PIC: leaq _ddst(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq (%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @ind05(i64 %i) nounwind {
+entry:
+ %0 = load i32** @dptr, align 8
+ %1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %i
+ %2 = load i32* %1, align 4
+ %3 = getelementptr i32* %0, i64 %i
+ store i32 %2, i32* %3, align 4
+ ret void
+; LINUX-64-STATIC: ind05:
+; LINUX-64-STATIC: movl dsrc(,%rdi,4), %eax
+; LINUX-64-STATIC: movq dptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, (%rcx,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: ind05:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl dsrc(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl dptr, %edx
+; LINUX-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: ind05:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl dsrc(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl dptr, %edx
+; LINUX-32-PIC-NEXT: movl %ecx, (%edx,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: ind05:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _ind05:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _dsrc(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl _dptr, %edx
+; DARWIN-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _ind05:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _dsrc(,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, (%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _ind05:
+; DARWIN-32-PIC: call L33$pb
+; DARWIN-32-PIC-NEXT: L33$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl _dsrc-L33$pb(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl _dptr-L33$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _ind05:
+; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _ind05:
+; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _ind05:
+; DARWIN-64-PIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @ind06(i64 %i) nounwind {
+entry:
+ %0 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %i
+ %1 = load i32* %0, align 4
+ %2 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %i
+ store i32 %1, i32* %2, align 4
+ ret void
+; LINUX-64-STATIC: ind06:
+; LINUX-64-STATIC: movl lsrc(,%rdi,4), %eax
+; LINUX-64-STATIC: movl %eax, ldst(,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: ind06:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl lsrc(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl %ecx, ldst(,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: ind06:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl lsrc(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, ldst(,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: ind06:
+; LINUX-64-PIC: leaq lsrc(%rip), %rax
+; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: leaq ldst(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _ind06:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _lsrc(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl %ecx, _ldst(,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _ind06:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _lsrc(,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, _ldst(,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _ind06:
+; DARWIN-32-PIC: call L34$pb
+; DARWIN-32-PIC-NEXT: L34$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl _lsrc-L34$pb(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl %edx, _ldst-L34$pb(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _ind06:
+; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: leaq _ldst(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _ind06:
+; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: leaq _ldst(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _ind06:
+; DARWIN-64-PIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: leaq _ldst(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @ind07(i64 %i) nounwind {
+entry:
+ %0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %i
+ store i32* %0, i32** @lptr, align 8
+ ret void
+; LINUX-64-STATIC: ind07:
+; LINUX-64-STATIC: leaq ldst(,%rdi,4), %rax
+; LINUX-64-STATIC: movq %rax, lptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: ind07:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal ldst(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: movl %eax, lptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: ind07:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal ldst(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: movl %eax, lptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: ind07:
+; LINUX-64-PIC: leaq ldst(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq (%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: movq %rax, lptr(%rip)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _ind07:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _ldst(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _lptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _ind07:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: leal _ldst(,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, _lptr
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _ind07:
+; DARWIN-32-PIC: call L35$pb
+; DARWIN-32-PIC-NEXT: L35$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal _ldst-L35$pb(%eax,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L35$pb(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _ind07:
+; DARWIN-64-STATIC: leaq _ldst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq (%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _ind07:
+; DARWIN-64-DYNAMIC: leaq _ldst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq (%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _ind07:
+; DARWIN-64-PIC: leaq _ldst(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq (%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @ind08(i64 %i) nounwind {
+entry:
+ %0 = load i32** @lptr, align 8
+ %1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %i
+ %2 = load i32* %1, align 4
+ %3 = getelementptr i32* %0, i64 %i
+ store i32 %2, i32* %3, align 4
+ ret void
+; LINUX-64-STATIC: ind08:
+; LINUX-64-STATIC: movl lsrc(,%rdi,4), %eax
+; LINUX-64-STATIC: movq lptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, (%rcx,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: ind08:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl lsrc(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl lptr, %edx
+; LINUX-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: ind08:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl lsrc(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl lptr, %edx
+; LINUX-32-PIC-NEXT: movl %ecx, (%edx,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: ind08:
+; LINUX-64-PIC: leaq lsrc(%rip), %rax
+; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq lptr(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _ind08:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _lsrc(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl _lptr, %edx
+; DARWIN-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _ind08:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _lsrc(,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, (%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _ind08:
+; DARWIN-32-PIC: call L36$pb
+; DARWIN-32-PIC-NEXT: L36$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl _lsrc-L36$pb(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl _lptr-L36$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _ind08:
+; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _ind08:
+; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _ind08:
+; DARWIN-64-PIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @off00(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 16
+ %1 = getelementptr [131072 x i32]* @src, i64 0, i64 %0
+ %2 = load i32* %1, align 4
+ %3 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
+ store i32 %2, i32* %3, align 4
+ ret void
+; LINUX-64-STATIC: off00:
+; LINUX-64-STATIC: movl src+64(,%rdi,4), %eax
+; LINUX-64-STATIC: movl %eax, dst+64(,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: off00:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl src+64(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl %ecx, dst+64(,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: off00:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl src+64(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, dst+64(,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: off00:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _off00:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _src+64(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl %ecx, _dst+64(,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _off00:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl 64(%ecx,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _off00:
+; DARWIN-32-PIC: call L37$pb
+; DARWIN-32-PIC-NEXT: L37$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L37$pb(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L37$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _off00:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _off00:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _off00:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @oxf00(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 16
+ %1 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %0
+ %2 = load i32* %1, align 4
+ %3 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
+ store i32 %2, i32* %3, align 4
+ ret void
+; LINUX-64-STATIC: oxf00:
+; LINUX-64-STATIC: movl xsrc+64(,%rdi,4), %eax
+; LINUX-64-STATIC: movl %eax, xdst+64(,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: oxf00:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl xsrc+64(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl %ecx, xdst+64(,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: oxf00:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl xsrc+64(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, xdst+64(,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: oxf00:
+; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _oxf00:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _xsrc+64(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl %ecx, _xdst+64(,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _oxf00:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl 64(%ecx,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _oxf00:
+; DARWIN-32-PIC: call L38$pb
+; DARWIN-32-PIC-NEXT: L38$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L38$pb(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L38$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _oxf00:
+; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _oxf00:
+; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _oxf00:
+; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @off01(i64 %i) nounwind {
+entry:
+ %.sum = add i64 %i, 16
+ %0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %.sum
+ store i32* %0, i32** @ptr, align 8
+ ret void
+; LINUX-64-STATIC: off01:
+; LINUX-64-STATIC: leaq dst+64(,%rdi,4), %rax
+; LINUX-64-STATIC: movq %rax, ptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: off01:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal dst+64(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: movl %eax, ptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: off01:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal dst+64(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: movl %eax, ptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: off01:
+; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _off01:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _dst+64(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _ptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _off01:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _off01:
+; DARWIN-32-PIC: call L39$pb
+; DARWIN-32-PIC-NEXT: L39$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L39$pb(%eax), %edx
+; DARWIN-32-PIC-NEXT: leal 64(%edx,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L39$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _off01:
+; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _off01:
+; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _off01:
+; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @oxf01(i64 %i) nounwind {
+entry:
+ %.sum = add i64 %i, 16
+ %0 = getelementptr [32 x i32]* @xdst, i64 0, i64 %.sum
+ store i32* %0, i32** @ptr, align 8
+ ret void
+; LINUX-64-STATIC: oxf01:
+; LINUX-64-STATIC: leaq xdst+64(,%rdi,4), %rax
+; LINUX-64-STATIC: movq %rax, ptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: oxf01:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal xdst+64(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: movl %eax, ptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: oxf01:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal xdst+64(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: movl %eax, ptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: oxf01:
+; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _oxf01:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _xdst+64(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _ptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _oxf01:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _oxf01:
+; DARWIN-32-PIC: call L40$pb
+; DARWIN-32-PIC-NEXT: L40$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L40$pb(%eax), %edx
+; DARWIN-32-PIC-NEXT: leal 64(%edx,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L40$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _oxf01:
+; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _oxf01:
+; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _oxf01:
+; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @off02(i64 %i) nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = add i64 %i, 16
+ %2 = getelementptr [131072 x i32]* @src, i64 0, i64 %1
+ %3 = load i32* %2, align 4
+ %4 = getelementptr i32* %0, i64 %1
+ store i32 %3, i32* %4, align 4
+ ret void
+; LINUX-64-STATIC: off02:
+; LINUX-64-STATIC: movl src+64(,%rdi,4), %eax
+; LINUX-64-STATIC: movq ptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, 64(%rcx,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: off02:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl src+64(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl ptr, %edx
+; LINUX-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: off02:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl src+64(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl ptr, %edx
+; LINUX-32-PIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: off02:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _off02:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _src+64(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl _ptr, %edx
+; DARWIN-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _off02:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl 64(%ecx,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl (%edx), %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _off02:
+; DARWIN-32-PIC: call L41$pb
+; DARWIN-32-PIC-NEXT: L41$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L41$pb(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L41$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _off02:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _off02:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _off02:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @oxf02(i64 %i) nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = add i64 %i, 16
+ %2 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %1
+ %3 = load i32* %2, align 4
+ %4 = getelementptr i32* %0, i64 %1
+ store i32 %3, i32* %4, align 4
+ ret void
+; LINUX-64-STATIC: oxf02:
+; LINUX-64-STATIC: movl xsrc+64(,%rdi,4), %eax
+; LINUX-64-STATIC: movq ptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, 64(%rcx,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: oxf02:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl xsrc+64(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl ptr, %edx
+; LINUX-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: oxf02:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl xsrc+64(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl ptr, %edx
+; LINUX-32-PIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: oxf02:
+; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _oxf02:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _xsrc+64(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl _ptr, %edx
+; DARWIN-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _oxf02:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl 64(%ecx,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl (%edx), %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _oxf02:
+; DARWIN-32-PIC: call L42$pb
+; DARWIN-32-PIC-NEXT: L42$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L42$pb(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L42$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _oxf02:
+; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _oxf02:
+; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _oxf02:
+; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @off03(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 16
+ %1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %0
+ %2 = load i32* %1, align 4
+ %3 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
+ store i32 %2, i32* %3, align 4
+ ret void
+; LINUX-64-STATIC: off03:
+; LINUX-64-STATIC: movl dsrc+64(,%rdi,4), %eax
+; LINUX-64-STATIC: movl %eax, ddst+64(,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: off03:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl dsrc+64(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl %ecx, ddst+64(,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: off03:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl dsrc+64(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, ddst+64(,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: off03:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _off03:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _dsrc+64(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl %ecx, _ddst+64(,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _off03:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _dsrc+64(,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, _ddst+64(,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _off03:
+; DARWIN-32-PIC: call L43$pb
+; DARWIN-32-PIC-NEXT: L43$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L43$pb)+64(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L43$pb)+64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _off03:
+; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: leaq _ddst(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _off03:
+; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: leaq _ddst(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _off03:
+; DARWIN-64-PIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: leaq _ddst(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @off04(i64 %i) nounwind {
+entry:
+ %.sum = add i64 %i, 16
+ %0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %.sum
+ store i32* %0, i32** @dptr, align 8
+ ret void
+; LINUX-64-STATIC: off04:
+; LINUX-64-STATIC: leaq ddst+64(,%rdi,4), %rax
+; LINUX-64-STATIC: movq %rax, dptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: off04:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal ddst+64(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: movl %eax, dptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: off04:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal ddst+64(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: movl %eax, dptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: off04:
+; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _off04:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _ddst+64(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _dptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _off04:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: leal _ddst+64(,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, _dptr
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _off04:
+; DARWIN-32-PIC: call L44$pb
+; DARWIN-32-PIC-NEXT: L44$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal (_ddst-L44$pb)+64(%eax,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L44$pb(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _off04:
+; DARWIN-64-STATIC: leaq _ddst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _off04:
+; DARWIN-64-DYNAMIC: leaq _ddst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _off04:
+; DARWIN-64-PIC: leaq _ddst(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @off05(i64 %i) nounwind {
+entry:
+ %0 = load i32** @dptr, align 8
+ %1 = add i64 %i, 16
+ %2 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %1
+ %3 = load i32* %2, align 4
+ %4 = getelementptr i32* %0, i64 %1
+ store i32 %3, i32* %4, align 4
+ ret void
+; LINUX-64-STATIC: off05:
+; LINUX-64-STATIC: movl dsrc+64(,%rdi,4), %eax
+; LINUX-64-STATIC: movq dptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, 64(%rcx,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: off05:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl dsrc+64(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl dptr, %edx
+; LINUX-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: off05:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl dsrc+64(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl dptr, %edx
+; LINUX-32-PIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: off05:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _off05:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _dsrc+64(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl _dptr, %edx
+; DARWIN-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _off05:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _dsrc+64(,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _off05:
+; DARWIN-32-PIC: call L45$pb
+; DARWIN-32-PIC-NEXT: L45$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L45$pb)+64(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl _dptr-L45$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _off05:
+; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _off05:
+; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _off05:
+; DARWIN-64-PIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @off06(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 16
+ %1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %0
+ %2 = load i32* %1, align 4
+ %3 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
+ store i32 %2, i32* %3, align 4
+ ret void
+; LINUX-64-STATIC: off06:
+; LINUX-64-STATIC: movl lsrc+64(,%rdi,4), %eax
+; LINUX-64-STATIC: movl %eax, ldst+64(,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: off06:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl lsrc+64(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl %ecx, ldst+64(,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: off06:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl lsrc+64(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, ldst+64(,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: off06:
+; LINUX-64-PIC: leaq lsrc(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: leaq ldst(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _off06:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _lsrc+64(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl %ecx, _ldst+64(,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _off06:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _lsrc+64(,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, _ldst+64(,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _off06:
+; DARWIN-32-PIC: call L46$pb
+; DARWIN-32-PIC-NEXT: L46$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L46$pb)+64(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L46$pb)+64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _off06:
+; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: leaq _ldst(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _off06:
+; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: leaq _ldst(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _off06:
+; DARWIN-64-PIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: leaq _ldst(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @off07(i64 %i) nounwind {
+entry:
+ %.sum = add i64 %i, 16
+ %0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %.sum
+ store i32* %0, i32** @lptr, align 8
+ ret void
+; LINUX-64-STATIC: off07:
+; LINUX-64-STATIC: leaq ldst+64(,%rdi,4), %rax
+; LINUX-64-STATIC: movq %rax, lptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: off07:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal ldst+64(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: movl %eax, lptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: off07:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal ldst+64(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: movl %eax, lptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: off07:
+; LINUX-64-PIC: leaq ldst(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: movq %rax, lptr(%rip)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _off07:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _ldst+64(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _lptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _off07:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: leal _ldst+64(,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, _lptr
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _off07:
+; DARWIN-32-PIC: call L47$pb
+; DARWIN-32-PIC-NEXT: L47$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal (_ldst-L47$pb)+64(%eax,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L47$pb(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _off07:
+; DARWIN-64-STATIC: leaq _ldst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _off07:
+; DARWIN-64-DYNAMIC: leaq _ldst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _off07:
+; DARWIN-64-PIC: leaq _ldst(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @off08(i64 %i) nounwind {
+entry:
+ %0 = load i32** @lptr, align 8
+ %1 = add i64 %i, 16
+ %2 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %1
+ %3 = load i32* %2, align 4
+ %4 = getelementptr i32* %0, i64 %1
+ store i32 %3, i32* %4, align 4
+ ret void
+; LINUX-64-STATIC: off08:
+; LINUX-64-STATIC: movl lsrc+64(,%rdi,4), %eax
+; LINUX-64-STATIC: movq lptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, 64(%rcx,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: off08:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl lsrc+64(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl lptr, %edx
+; LINUX-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: off08:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl lsrc+64(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl lptr, %edx
+; LINUX-32-PIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: off08:
+; LINUX-64-PIC: leaq lsrc(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq lptr(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _off08:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _lsrc+64(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl _lptr, %edx
+; DARWIN-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _off08:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _lsrc+64(,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 64(%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _off08:
+; DARWIN-32-PIC: call L48$pb
+; DARWIN-32-PIC-NEXT: L48$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L48$pb)+64(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl _lptr-L48$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _off08:
+; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _off08:
+; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _off08:
+; DARWIN-64-PIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @moo00(i64 %i) nounwind {
+entry:
+ %0 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 65536), align 4
+ store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536), align 4
+ ret void
+; LINUX-64-STATIC: moo00:
+; LINUX-64-STATIC: movl src+262144(%rip), %eax
+; LINUX-64-STATIC: movl %eax, dst+262144(%rip)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: moo00:
+; LINUX-32-STATIC: movl src+262144, %eax
+; LINUX-32-STATIC-NEXT: movl %eax, dst+262144
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: moo00:
+; LINUX-32-PIC: movl src+262144, %eax
+; LINUX-32-PIC-NEXT: movl %eax, dst+262144
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: moo00:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 262144(%rax), %eax
+; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _moo00:
+; DARWIN-32-STATIC: movl _src+262144, %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _dst+262144
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _moo00:
+; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl 262144(%eax), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, 262144(%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _moo00:
+; DARWIN-32-PIC: call L49$pb
+; DARWIN-32-PIC-NEXT: L49$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L49$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl 262144(%ecx), %ecx
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L49$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _moo00:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 262144(%rax), %eax
+; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _moo00:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _moo00:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 262144(%rax), %eax
+; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @moo01(i64 %i) nounwind {
+entry:
+ store i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536), i32** @ptr, align 8
+ ret void
+; LINUX-64-STATIC: moo01:
+; LINUX-64-STATIC: movq $dst+262144, ptr(%rip)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: moo01:
+; LINUX-32-STATIC: movl $dst+262144, ptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: moo01:
+; LINUX-32-PIC: movl $dst+262144, ptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: moo01:
+; LINUX-64-PIC: movl $262144, %eax
+; LINUX-64-PIC-NEXT: addq dst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _moo01:
+; DARWIN-32-STATIC: movl $_dst+262144, _ptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _moo01:
+; DARWIN-32-DYNAMIC: movl $262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl L_dst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _moo01:
+; DARWIN-32-PIC: call L50$pb
+; DARWIN-32-PIC-NEXT: L50$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl $262144, %ecx
+; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L50$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L50$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _moo01:
+; DARWIN-64-STATIC: movl $262144, %eax
+; DARWIN-64-STATIC-NEXT: addq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _moo01:
+; DARWIN-64-DYNAMIC: movl $262144, %eax
+; DARWIN-64-DYNAMIC-NEXT: addq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _moo01:
+; DARWIN-64-PIC: movl $262144, %eax
+; DARWIN-64-PIC-NEXT: addq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @moo02(i64 %i) nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 65536), align 4
+ %2 = getelementptr i32* %0, i64 65536
+ store i32 %1, i32* %2, align 4
+ ret void
+; LINUX-64-STATIC: moo02:
+; LINUX-64-STATIC: movl src+262144(%rip), %eax
+; LINUX-64-STATIC: movq ptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, 262144(%rcx)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: moo02:
+; LINUX-32-STATIC: movl src+262144, %eax
+; LINUX-32-STATIC-NEXT: movl ptr, %ecx
+; LINUX-32-STATIC-NEXT: movl %eax, 262144(%ecx)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: moo02:
+; LINUX-32-PIC: movl src+262144, %eax
+; LINUX-32-PIC-NEXT: movl ptr, %ecx
+; LINUX-32-PIC-NEXT: movl %eax, 262144(%ecx)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: moo02:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 262144(%rax), %eax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _moo02:
+; DARWIN-32-STATIC: movl _src+262144, %eax
+; DARWIN-32-STATIC-NEXT: movl _ptr, %ecx
+; DARWIN-32-STATIC-NEXT: movl %eax, 262144(%ecx)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _moo02:
+; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl 262144(%eax), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl (%ecx), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, 262144(%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _moo02:
+; DARWIN-32-PIC: call L51$pb
+; DARWIN-32-PIC-NEXT: L51$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L51$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl 262144(%ecx), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L51$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _moo02:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 262144(%rax), %eax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _moo02:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _moo02:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 262144(%rax), %eax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @moo03(i64 %i) nounwind {
+entry:
+ %0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 65536), align 32
+ store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536), align 32
+ ret void
+; LINUX-64-STATIC: moo03:
+; LINUX-64-STATIC: movl dsrc+262144(%rip), %eax
+; LINUX-64-STATIC: movl %eax, ddst+262144(%rip)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: moo03:
+; LINUX-32-STATIC: movl dsrc+262144, %eax
+; LINUX-32-STATIC-NEXT: movl %eax, ddst+262144
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: moo03:
+; LINUX-32-PIC: movl dsrc+262144, %eax
+; LINUX-32-PIC-NEXT: movl %eax, ddst+262144
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: moo03:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 262144(%rax), %eax
+; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _moo03:
+; DARWIN-32-STATIC: movl _dsrc+262144, %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _ddst+262144
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _moo03:
+; DARWIN-32-DYNAMIC: movl _dsrc+262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, _ddst+262144
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _moo03:
+; DARWIN-32-PIC: call L52$pb
+; DARWIN-32-PIC-NEXT: L52$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L52$pb)+262144(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L52$pb)+262144(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _moo03:
+; DARWIN-64-STATIC: movl _dsrc+262144(%rip), %eax
+; DARWIN-64-STATIC-NEXT: movl %eax, _ddst+262144(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _moo03:
+; DARWIN-64-DYNAMIC: movl _dsrc+262144(%rip), %eax
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, _ddst+262144(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _moo03:
+; DARWIN-64-PIC: movl _dsrc+262144(%rip), %eax
+; DARWIN-64-PIC-NEXT: movl %eax, _ddst+262144(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @moo04(i64 %i) nounwind {
+entry:
+ store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536), i32** @dptr, align 8
+ ret void
+; LINUX-64-STATIC: moo04:
+; LINUX-64-STATIC: movq $ddst+262144, dptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: moo04:
+; LINUX-32-STATIC: movl $ddst+262144, dptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: moo04:
+; LINUX-32-PIC: movl $ddst+262144, dptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: moo04:
+; LINUX-64-PIC: movl $262144, %eax
+; LINUX-64-PIC-NEXT: addq ddst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _moo04:
+; DARWIN-32-STATIC: movl $_ddst+262144, _dptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _moo04:
+; DARWIN-32-DYNAMIC: movl $_ddst+262144, _dptr
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _moo04:
+; DARWIN-32-PIC: call L53$pb
+; DARWIN-32-PIC-NEXT: L53$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal (_ddst-L53$pb)+262144(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L53$pb(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _moo04:
+; DARWIN-64-STATIC: leaq _ddst+262144(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _moo04:
+; DARWIN-64-DYNAMIC: leaq _ddst+262144(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _moo04:
+; DARWIN-64-PIC: leaq _ddst+262144(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @moo05(i64 %i) nounwind {
+entry:
+ %0 = load i32** @dptr, align 8
+ %1 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 65536), align 32
+ %2 = getelementptr i32* %0, i64 65536
+ store i32 %1, i32* %2, align 4
+ ret void
+; LINUX-64-STATIC: moo05:
+; LINUX-64-STATIC: movl dsrc+262144(%rip), %eax
+; LINUX-64-STATIC: movq dptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, 262144(%rcx)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: moo05:
+; LINUX-32-STATIC: movl dsrc+262144, %eax
+; LINUX-32-STATIC-NEXT: movl dptr, %ecx
+; LINUX-32-STATIC-NEXT: movl %eax, 262144(%ecx)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: moo05:
+; LINUX-32-PIC: movl dsrc+262144, %eax
+; LINUX-32-PIC-NEXT: movl dptr, %ecx
+; LINUX-32-PIC-NEXT: movl %eax, 262144(%ecx)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: moo05:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 262144(%rax), %eax
+; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _moo05:
+; DARWIN-32-STATIC: movl _dsrc+262144, %eax
+; DARWIN-32-STATIC-NEXT: movl _dptr, %ecx
+; DARWIN-32-STATIC-NEXT: movl %eax, 262144(%ecx)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _moo05:
+; DARWIN-32-DYNAMIC: movl _dsrc+262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, 262144(%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _moo05:
+; DARWIN-32-PIC: call L54$pb
+; DARWIN-32-PIC-NEXT: L54$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L54$pb)+262144(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl _dptr-L54$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _moo05:
+; DARWIN-64-STATIC: movl _dsrc+262144(%rip), %eax
+; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _moo05:
+; DARWIN-64-DYNAMIC: movl _dsrc+262144(%rip), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _moo05:
+; DARWIN-64-PIC: movl _dsrc+262144(%rip), %eax
+; DARWIN-64-PIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @moo06(i64 %i) nounwind {
+entry:
+ %0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 65536), align 4
+ store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536), align 4
+ ret void
+; LINUX-64-STATIC: moo06:
+; LINUX-64-STATIC: movl lsrc+262144(%rip), %eax
+; LINUX-64-STATIC: movl %eax, ldst+262144(%rip)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: moo06:
+; LINUX-32-STATIC: movl lsrc+262144, %eax
+; LINUX-32-STATIC-NEXT: movl %eax, ldst+262144
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: moo06:
+; LINUX-32-PIC: movl lsrc+262144, %eax
+; LINUX-32-PIC-NEXT: movl %eax, ldst+262144
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: moo06:
+; LINUX-64-PIC: movl lsrc+262144(%rip), %eax
+; LINUX-64-PIC-NEXT: movl %eax, ldst+262144(%rip)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _moo06:
+; DARWIN-32-STATIC: movl _lsrc+262144, %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _ldst+262144
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _moo06:
+; DARWIN-32-DYNAMIC: movl _lsrc+262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, _ldst+262144
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _moo06:
+; DARWIN-32-PIC: call L55$pb
+; DARWIN-32-PIC-NEXT: L55$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L55$pb)+262144(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L55$pb)+262144(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _moo06:
+; DARWIN-64-STATIC: movl _lsrc+262144(%rip), %eax
+; DARWIN-64-STATIC-NEXT: movl %eax, _ldst+262144(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _moo06:
+; DARWIN-64-DYNAMIC: movl _lsrc+262144(%rip), %eax
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, _ldst+262144(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _moo06:
+; DARWIN-64-PIC: movl _lsrc+262144(%rip), %eax
+; DARWIN-64-PIC-NEXT: movl %eax, _ldst+262144(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @moo07(i64 %i) nounwind {
+entry:
+ store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536), i32** @lptr, align 8
+ ret void
+; LINUX-64-STATIC: moo07:
+; LINUX-64-STATIC: movq $ldst+262144, lptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: moo07:
+; LINUX-32-STATIC: movl $ldst+262144, lptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: moo07:
+; LINUX-32-PIC: movl $ldst+262144, lptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: moo07:
+; LINUX-64-PIC: leaq ldst+262144(%rip), %rax
+; LINUX-64-PIC-NEXT: movq %rax, lptr(%rip)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _moo07:
+; DARWIN-32-STATIC: movl $_ldst+262144, _lptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _moo07:
+; DARWIN-32-DYNAMIC: movl $_ldst+262144, _lptr
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _moo07:
+; DARWIN-32-PIC: call L56$pb
+; DARWIN-32-PIC-NEXT: L56$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal (_ldst-L56$pb)+262144(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L56$pb(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _moo07:
+; DARWIN-64-STATIC: leaq _ldst+262144(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _moo07:
+; DARWIN-64-DYNAMIC: leaq _ldst+262144(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _moo07:
+; DARWIN-64-PIC: leaq _ldst+262144(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @moo08(i64 %i) nounwind {
+entry:
+ %0 = load i32** @lptr, align 8
+ %1 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 65536), align 4
+ %2 = getelementptr i32* %0, i64 65536
+ store i32 %1, i32* %2, align 4
+ ret void
+; LINUX-64-STATIC: moo08:
+; LINUX-64-STATIC: movl lsrc+262144(%rip), %eax
+; LINUX-64-STATIC: movq lptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, 262144(%rcx)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: moo08:
+; LINUX-32-STATIC: movl lsrc+262144, %eax
+; LINUX-32-STATIC-NEXT: movl lptr, %ecx
+; LINUX-32-STATIC-NEXT: movl %eax, 262144(%ecx)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: moo08:
+; LINUX-32-PIC: movl lsrc+262144, %eax
+; LINUX-32-PIC-NEXT: movl lptr, %ecx
+; LINUX-32-PIC-NEXT: movl %eax, 262144(%ecx)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: moo08:
+; LINUX-64-PIC: movl lsrc+262144(%rip), %eax
+; LINUX-64-PIC-NEXT: movq lptr(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _moo08:
+; DARWIN-32-STATIC: movl _lsrc+262144, %eax
+; DARWIN-32-STATIC-NEXT: movl _lptr, %ecx
+; DARWIN-32-STATIC-NEXT: movl %eax, 262144(%ecx)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _moo08:
+; DARWIN-32-DYNAMIC: movl _lsrc+262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, 262144(%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _moo08:
+; DARWIN-32-PIC: call L57$pb
+; DARWIN-32-PIC-NEXT: L57$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L57$pb)+262144(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl _lptr-L57$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _moo08:
+; DARWIN-64-STATIC: movl _lsrc+262144(%rip), %eax
+; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _moo08:
+; DARWIN-64-DYNAMIC: movl _lsrc+262144(%rip), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _moo08:
+; DARWIN-64-PIC: movl _lsrc+262144(%rip), %eax
+; DARWIN-64-PIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @big00(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 65536
+ %1 = getelementptr [131072 x i32]* @src, i64 0, i64 %0
+ %2 = load i32* %1, align 4
+ %3 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
+ store i32 %2, i32* %3, align 4
+ ret void
+; LINUX-64-STATIC: big00:
+; LINUX-64-STATIC: movl src+262144(,%rdi,4), %eax
+; LINUX-64-STATIC: movl %eax, dst+262144(,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: big00:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl src+262144(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl %ecx, dst+262144(,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: big00:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl src+262144(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, dst+262144(,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: big00:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _big00:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _src+262144(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl %ecx, _dst+262144(,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _big00:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl 262144(%ecx,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 262144(%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _big00:
+; DARWIN-32-PIC: call L58$pb
+; DARWIN-32-PIC-NEXT: L58$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L58$pb(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl 262144(%edx,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L58$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _big00:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _big00:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _big00:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @big01(i64 %i) nounwind {
+entry:
+ %.sum = add i64 %i, 65536
+ %0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %.sum
+ store i32* %0, i32** @ptr, align 8
+ ret void
+; LINUX-64-STATIC: big01:
+; LINUX-64-STATIC: leaq dst+262144(,%rdi,4), %rax
+; LINUX-64-STATIC: movq %rax, ptr(%rip)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: big01:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal dst+262144(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: movl %eax, ptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: big01:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal dst+262144(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: movl %eax, ptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: big01:
+; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _big01:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _dst+262144(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _ptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _big01:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _big01:
+; DARWIN-32-PIC: call L59$pb
+; DARWIN-32-PIC-NEXT: L59$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L59$pb(%eax), %edx
+; DARWIN-32-PIC-NEXT: leal 262144(%edx,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L59$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %ecx, (%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _big01:
+; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _big01:
+; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _big01:
+; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq %rax, (%rcx)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @big02(i64 %i) nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = add i64 %i, 65536
+ %2 = getelementptr [131072 x i32]* @src, i64 0, i64 %1
+ %3 = load i32* %2, align 4
+ %4 = getelementptr i32* %0, i64 %1
+ store i32 %3, i32* %4, align 4
+ ret void
+; LINUX-64-STATIC: big02:
+; LINUX-64-STATIC: movl src+262144(,%rdi,4), %eax
+; LINUX-64-STATIC: movq ptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, 262144(%rcx,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: big02:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl src+262144(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl ptr, %edx
+; LINUX-32-STATIC-NEXT: movl %ecx, 262144(%edx,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: big02:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl src+262144(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl ptr, %edx
+; LINUX-32-PIC-NEXT: movl %ecx, 262144(%edx,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: big02:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _big02:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _src+262144(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl _ptr, %edx
+; DARWIN-32-STATIC-NEXT: movl %ecx, 262144(%edx,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _big02:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl 262144(%ecx,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl (%edx), %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 262144(%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _big02:
+; DARWIN-32-PIC: call L60$pb
+; DARWIN-32-PIC-NEXT: L60$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L60$pb(%eax), %edx
+; DARWIN-32-PIC-NEXT: movl 262144(%edx,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L60$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _big02:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _big02:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _big02:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @big03(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 65536
+ %1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %0
+ %2 = load i32* %1, align 4
+ %3 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
+ store i32 %2, i32* %3, align 4
+ ret void
+; LINUX-64-STATIC: big03:
+; LINUX-64-STATIC: movl dsrc+262144(,%rdi,4), %eax
+; LINUX-64-STATIC: movl %eax, ddst+262144(,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: big03:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl dsrc+262144(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl %ecx, ddst+262144(,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: big03:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl dsrc+262144(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, ddst+262144(,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: big03:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _big03:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _dsrc+262144(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl %ecx, _ddst+262144(,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _big03:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _dsrc+262144(,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, _ddst+262144(,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _big03:
+; DARWIN-32-PIC: call L61$pb
+; DARWIN-32-PIC-NEXT: L61$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L61$pb)+262144(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L61$pb)+262144(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _big03:
+; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: leaq _ddst(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _big03:
+; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: leaq _ddst(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _big03:
+; DARWIN-64-PIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: leaq _ddst(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @big04(i64 %i) nounwind {
+entry:
+ %.sum = add i64 %i, 65536
+ %0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %.sum
+ store i32* %0, i32** @dptr, align 8
+ ret void
+; LINUX-64-STATIC: big04:
+; LINUX-64-STATIC: leaq ddst+262144(,%rdi,4), %rax
+; LINUX-64-STATIC: movq %rax, dptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: big04:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal ddst+262144(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: movl %eax, dptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: big04:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal ddst+262144(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: movl %eax, dptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: big04:
+; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _big04:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _ddst+262144(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _dptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _big04:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: leal _ddst+262144(,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, _dptr
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _big04:
+; DARWIN-32-PIC: call L62$pb
+; DARWIN-32-PIC-NEXT: L62$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal (_ddst-L62$pb)+262144(%eax,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L62$pb(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _big04:
+; DARWIN-64-STATIC: leaq _ddst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _big04:
+; DARWIN-64-DYNAMIC: leaq _ddst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _big04:
+; DARWIN-64-PIC: leaq _ddst(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: movq %rax, _dptr(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @big05(i64 %i) nounwind {
+entry:
+ %0 = load i32** @dptr, align 8
+ %1 = add i64 %i, 65536
+ %2 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %1
+ %3 = load i32* %2, align 4
+ %4 = getelementptr i32* %0, i64 %1
+ store i32 %3, i32* %4, align 4
+ ret void
+; LINUX-64-STATIC: big05:
+; LINUX-64-STATIC: movl dsrc+262144(,%rdi,4), %eax
+; LINUX-64-STATIC: movq dptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, 262144(%rcx,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: big05:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl dsrc+262144(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl dptr, %edx
+; LINUX-32-STATIC-NEXT: movl %ecx, 262144(%edx,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: big05:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl dsrc+262144(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl dptr, %edx
+; LINUX-32-PIC-NEXT: movl %ecx, 262144(%edx,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: big05:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _big05:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _dsrc+262144(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl _dptr, %edx
+; DARWIN-32-STATIC-NEXT: movl %ecx, 262144(%edx,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _big05:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _dsrc+262144(,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 262144(%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _big05:
+; DARWIN-32-PIC: call L63$pb
+; DARWIN-32-PIC-NEXT: L63$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl (_dsrc-L63$pb)+262144(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl _dptr-L63$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _big05:
+; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _big05:
+; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _big05:
+; DARWIN-64-PIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _dptr(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @big06(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 65536
+ %1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %0
+ %2 = load i32* %1, align 4
+ %3 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
+ store i32 %2, i32* %3, align 4
+ ret void
+; LINUX-64-STATIC: big06:
+; LINUX-64-STATIC: movl lsrc+262144(,%rdi,4), %eax
+; LINUX-64-STATIC: movl %eax, ldst+262144(,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: big06:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl lsrc+262144(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl %ecx, ldst+262144(,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: big06:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl lsrc+262144(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, ldst+262144(,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: big06:
+; LINUX-64-PIC: leaq lsrc(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: leaq ldst(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _big06:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _lsrc+262144(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl %ecx, _ldst+262144(,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _big06:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _lsrc+262144(,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, _ldst+262144(,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _big06:
+; DARWIN-32-PIC: call L64$pb
+; DARWIN-32-PIC-NEXT: L64$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L64$pb)+262144(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L64$pb)+262144(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _big06:
+; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: leaq _ldst(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _big06:
+; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: leaq _ldst(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _big06:
+; DARWIN-64-PIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: leaq _ldst(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @big07(i64 %i) nounwind {
+entry:
+ %.sum = add i64 %i, 65536
+ %0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %.sum
+ store i32* %0, i32** @lptr, align 8
+ ret void
+; LINUX-64-STATIC: big07:
+; LINUX-64-STATIC: leaq ldst+262144(,%rdi,4), %rax
+; LINUX-64-STATIC: movq %rax, lptr
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: big07:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal ldst+262144(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: movl %eax, lptr
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: big07:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal ldst+262144(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: movl %eax, lptr
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: big07:
+; LINUX-64-PIC: leaq ldst(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: movq %rax, lptr(%rip)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _big07:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _ldst+262144(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: movl %eax, _lptr
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _big07:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: leal _ldst+262144(,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl %eax, _lptr
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _big07:
+; DARWIN-32-PIC: call L65$pb
+; DARWIN-32-PIC-NEXT: L65$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal (_ldst-L65$pb)+262144(%eax,%ecx,4), %ecx
+; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L65$pb(%eax)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _big07:
+; DARWIN-64-STATIC: leaq _ldst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _big07:
+; DARWIN-64-DYNAMIC: leaq _ldst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _big07:
+; DARWIN-64-PIC: leaq _ldst(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: movq %rax, _lptr(%rip)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @big08(i64 %i) nounwind {
+entry:
+ %0 = load i32** @lptr, align 8
+ %1 = add i64 %i, 65536
+ %2 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %1
+ %3 = load i32* %2, align 4
+ %4 = getelementptr i32* %0, i64 %1
+ store i32 %3, i32* %4, align 4
+ ret void
+; LINUX-64-STATIC: big08:
+; LINUX-64-STATIC: movl lsrc+262144(,%rdi,4), %eax
+; LINUX-64-STATIC: movq lptr(%rip), %rcx
+; LINUX-64-STATIC: movl %eax, 262144(%rcx,%rdi,4)
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: big08:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl lsrc+262144(,%eax,4), %ecx
+; LINUX-32-STATIC-NEXT: movl lptr, %edx
+; LINUX-32-STATIC-NEXT: movl %ecx, 262144(%edx,%eax,4)
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: big08:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl lsrc+262144(,%eax,4), %ecx
+; LINUX-32-PIC-NEXT: movl lptr, %edx
+; LINUX-32-PIC-NEXT: movl %ecx, 262144(%edx,%eax,4)
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: big08:
+; LINUX-64-PIC: leaq lsrc(%rip), %rax
+; LINUX-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; LINUX-64-PIC-NEXT: movq lptr(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _big08:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _lsrc+262144(,%eax,4), %ecx
+; DARWIN-32-STATIC-NEXT: movl _lptr, %edx
+; DARWIN-32-STATIC-NEXT: movl %ecx, 262144(%edx,%eax,4)
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _big08:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _lsrc+262144(,%eax,4), %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %edx
+; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 262144(%edx,%eax,4)
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _big08:
+; DARWIN-32-PIC: call L66$pb
+; DARWIN-32-PIC-NEXT: L66$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl (_lsrc-L66$pb)+262144(%eax,%ecx,4), %edx
+; DARWIN-32-PIC-NEXT: movl _lptr-L66$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _big08:
+; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _big08:
+; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _big08:
+; DARWIN-64-PIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax
+; DARWIN-64-PIC-NEXT: movq _lptr(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bar00() nounwind {
+entry:
+ ret i8* bitcast ([131072 x i32]* @src to i8*)
+; LINUX-64-STATIC: bar00:
+; LINUX-64-STATIC: movl $src, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bar00:
+; LINUX-32-STATIC: movl $src, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bar00:
+; LINUX-32-PIC: movl $src, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bar00:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bar00:
+; DARWIN-32-STATIC: movl $_src, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bar00:
+; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bar00:
+; DARWIN-32-PIC: call L67$pb
+; DARWIN-32-PIC-NEXT: L67$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L67$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bar00:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bar00:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bar00:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bxr00() nounwind {
+entry:
+ ret i8* bitcast ([32 x i32]* @xsrc to i8*)
+; LINUX-64-STATIC: bxr00:
+; LINUX-64-STATIC: movl $xsrc, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bxr00:
+; LINUX-32-STATIC: movl $xsrc, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bxr00:
+; LINUX-32-PIC: movl $xsrc, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bxr00:
+; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bxr00:
+; DARWIN-32-STATIC: movl $_xsrc, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bxr00:
+; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bxr00:
+; DARWIN-32-PIC: call L68$pb
+; DARWIN-32-PIC-NEXT: L68$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L68$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bxr00:
+; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bxr00:
+; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bxr00:
+; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bar01() nounwind {
+entry:
+ ret i8* bitcast ([131072 x i32]* @dst to i8*)
+; LINUX-64-STATIC: bar01:
+; LINUX-64-STATIC: movl $dst, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bar01:
+; LINUX-32-STATIC: movl $dst, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bar01:
+; LINUX-32-PIC: movl $dst, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bar01:
+; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bar01:
+; DARWIN-32-STATIC: movl $_dst, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bar01:
+; DARWIN-32-DYNAMIC: movl L_dst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bar01:
+; DARWIN-32-PIC: call L69$pb
+; DARWIN-32-PIC-NEXT: L69$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L69$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bar01:
+; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bar01:
+; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bar01:
+; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bxr01() nounwind {
+entry:
+ ret i8* bitcast ([32 x i32]* @xdst to i8*)
+; LINUX-64-STATIC: bxr01:
+; LINUX-64-STATIC: movl $xdst, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bxr01:
+; LINUX-32-STATIC: movl $xdst, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bxr01:
+; LINUX-32-PIC: movl $xdst, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bxr01:
+; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bxr01:
+; DARWIN-32-STATIC: movl $_xdst, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bxr01:
+; DARWIN-32-DYNAMIC: movl L_xdst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bxr01:
+; DARWIN-32-PIC: call L70$pb
+; DARWIN-32-PIC-NEXT: L70$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L70$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bxr01:
+; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bxr01:
+; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bxr01:
+; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bar02() nounwind {
+entry:
+ ret i8* bitcast (i32** @ptr to i8*)
+; LINUX-64-STATIC: bar02:
+; LINUX-64-STATIC: movl $ptr, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bar02:
+; LINUX-32-STATIC: movl $ptr, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bar02:
+; LINUX-32-PIC: movl $ptr, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bar02:
+; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bar02:
+; DARWIN-32-STATIC: movl $_ptr, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bar02:
+; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bar02:
+; DARWIN-32-PIC: call L71$pb
+; DARWIN-32-PIC-NEXT: L71$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L71$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bar02:
+; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bar02:
+; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bar02:
+; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bar03() nounwind {
+entry:
+ ret i8* bitcast ([131072 x i32]* @dsrc to i8*)
+; LINUX-64-STATIC: bar03:
+; LINUX-64-STATIC: movl $dsrc, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bar03:
+; LINUX-32-STATIC: movl $dsrc, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bar03:
+; LINUX-32-PIC: movl $dsrc, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bar03:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bar03:
+; DARWIN-32-STATIC: movl $_dsrc, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bar03:
+; DARWIN-32-DYNAMIC: movl $_dsrc, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bar03:
+; DARWIN-32-PIC: call L72$pb
+; DARWIN-32-PIC-NEXT: L72$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal _dsrc-L72$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bar03:
+; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bar03:
+; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bar03:
+; DARWIN-64-PIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bar04() nounwind {
+entry:
+ ret i8* bitcast ([131072 x i32]* @ddst to i8*)
+; LINUX-64-STATIC: bar04:
+; LINUX-64-STATIC: movl $ddst, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bar04:
+; LINUX-32-STATIC: movl $ddst, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bar04:
+; LINUX-32-PIC: movl $ddst, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bar04:
+; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bar04:
+; DARWIN-32-STATIC: movl $_ddst, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bar04:
+; DARWIN-32-DYNAMIC: movl $_ddst, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bar04:
+; DARWIN-32-PIC: call L73$pb
+; DARWIN-32-PIC-NEXT: L73$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal _ddst-L73$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bar04:
+; DARWIN-64-STATIC: leaq _ddst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bar04:
+; DARWIN-64-DYNAMIC: leaq _ddst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bar04:
+; DARWIN-64-PIC: leaq _ddst(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bar05() nounwind {
+entry:
+ ret i8* bitcast (i32** @dptr to i8*)
+; LINUX-64-STATIC: bar05:
+; LINUX-64-STATIC: movl $dptr, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bar05:
+; LINUX-32-STATIC: movl $dptr, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bar05:
+; LINUX-32-PIC: movl $dptr, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bar05:
+; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bar05:
+; DARWIN-32-STATIC: movl $_dptr, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bar05:
+; DARWIN-32-DYNAMIC: movl $_dptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bar05:
+; DARWIN-32-PIC: call L74$pb
+; DARWIN-32-PIC-NEXT: L74$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal _dptr-L74$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bar05:
+; DARWIN-64-STATIC: leaq _dptr(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bar05:
+; DARWIN-64-DYNAMIC: leaq _dptr(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bar05:
+; DARWIN-64-PIC: leaq _dptr(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bar06() nounwind {
+entry:
+ ret i8* bitcast ([131072 x i32]* @lsrc to i8*)
+; LINUX-64-STATIC: bar06:
+; LINUX-64-STATIC: movl $lsrc, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bar06:
+; LINUX-32-STATIC: movl $lsrc, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bar06:
+; LINUX-32-PIC: movl $lsrc, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bar06:
+; LINUX-64-PIC: leaq lsrc(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bar06:
+; DARWIN-32-STATIC: movl $_lsrc, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bar06:
+; DARWIN-32-DYNAMIC: movl $_lsrc, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bar06:
+; DARWIN-32-PIC: call L75$pb
+; DARWIN-32-PIC-NEXT: L75$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal _lsrc-L75$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bar06:
+; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bar06:
+; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bar06:
+; DARWIN-64-PIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bar07() nounwind {
+entry:
+ ret i8* bitcast ([131072 x i32]* @ldst to i8*)
+; LINUX-64-STATIC: bar07:
+; LINUX-64-STATIC: movl $ldst, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bar07:
+; LINUX-32-STATIC: movl $ldst, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bar07:
+; LINUX-32-PIC: movl $ldst, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bar07:
+; LINUX-64-PIC: leaq ldst(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bar07:
+; DARWIN-32-STATIC: movl $_ldst, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bar07:
+; DARWIN-32-DYNAMIC: movl $_ldst, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bar07:
+; DARWIN-32-PIC: call L76$pb
+; DARWIN-32-PIC-NEXT: L76$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal _ldst-L76$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bar07:
+; DARWIN-64-STATIC: leaq _ldst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bar07:
+; DARWIN-64-DYNAMIC: leaq _ldst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bar07:
+; DARWIN-64-PIC: leaq _ldst(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bar08() nounwind {
+entry:
+ ret i8* bitcast (i32** @lptr to i8*)
+; LINUX-64-STATIC: bar08:
+; LINUX-64-STATIC: movl $lptr, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bar08:
+; LINUX-32-STATIC: movl $lptr, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bar08:
+; LINUX-32-PIC: movl $lptr, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bar08:
+; LINUX-64-PIC: leaq lptr(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bar08:
+; DARWIN-32-STATIC: movl $_lptr, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bar08:
+; DARWIN-32-DYNAMIC: movl $_lptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bar08:
+; DARWIN-32-PIC: call L77$pb
+; DARWIN-32-PIC-NEXT: L77$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal _lptr-L77$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bar08:
+; DARWIN-64-STATIC: leaq _lptr(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bar08:
+; DARWIN-64-DYNAMIC: leaq _lptr(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bar08:
+; DARWIN-64-PIC: leaq _lptr(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @har00() nounwind {
+entry:
+ ret i8* bitcast ([131072 x i32]* @src to i8*)
+; LINUX-64-STATIC: har00:
+; LINUX-64-STATIC: movl $src, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: har00:
+; LINUX-32-STATIC: movl $src, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: har00:
+; LINUX-32-PIC: movl $src, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: har00:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _har00:
+; DARWIN-32-STATIC: movl $_src, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _har00:
+; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _har00:
+; DARWIN-32-PIC: call L78$pb
+; DARWIN-32-PIC-NEXT: L78$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L78$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _har00:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _har00:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _har00:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @hxr00() nounwind {
+entry:
+ ret i8* bitcast ([32 x i32]* @xsrc to i8*)
+; LINUX-64-STATIC: hxr00:
+; LINUX-64-STATIC: movl $xsrc, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: hxr00:
+; LINUX-32-STATIC: movl $xsrc, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: hxr00:
+; LINUX-32-PIC: movl $xsrc, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: hxr00:
+; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _hxr00:
+; DARWIN-32-STATIC: movl $_xsrc, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _hxr00:
+; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _hxr00:
+; DARWIN-32-PIC: call L79$pb
+; DARWIN-32-PIC-NEXT: L79$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L79$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _hxr00:
+; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _hxr00:
+; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _hxr00:
+; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @har01() nounwind {
+entry:
+ ret i8* bitcast ([131072 x i32]* @dst to i8*)
+; LINUX-64-STATIC: har01:
+; LINUX-64-STATIC: movl $dst, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: har01:
+; LINUX-32-STATIC: movl $dst, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: har01:
+; LINUX-32-PIC: movl $dst, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: har01:
+; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _har01:
+; DARWIN-32-STATIC: movl $_dst, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _har01:
+; DARWIN-32-DYNAMIC: movl L_dst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _har01:
+; DARWIN-32-PIC: call L80$pb
+; DARWIN-32-PIC-NEXT: L80$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L80$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _har01:
+; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _har01:
+; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _har01:
+; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @hxr01() nounwind {
+entry:
+ ret i8* bitcast ([32 x i32]* @xdst to i8*)
+; LINUX-64-STATIC: hxr01:
+; LINUX-64-STATIC: movl $xdst, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: hxr01:
+; LINUX-32-STATIC: movl $xdst, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: hxr01:
+; LINUX-32-PIC: movl $xdst, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: hxr01:
+; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _hxr01:
+; DARWIN-32-STATIC: movl $_xdst, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _hxr01:
+; DARWIN-32-DYNAMIC: movl L_xdst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _hxr01:
+; DARWIN-32-PIC: call L81$pb
+; DARWIN-32-PIC-NEXT: L81$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L81$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _hxr01:
+; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _hxr01:
+; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _hxr01:
+; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @har02() nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = bitcast i32* %0 to i8*
+ ret i8* %1
+; LINUX-64-STATIC: har02:
+; LINUX-64-STATIC: movq ptr(%rip), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: har02:
+; LINUX-32-STATIC: movl ptr, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: har02:
+; LINUX-32-PIC: movl ptr, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: har02:
+; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq (%rax), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _har02:
+; DARWIN-32-STATIC: movl _ptr, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _har02:
+; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _har02:
+; DARWIN-32-PIC: call L82$pb
+; DARWIN-32-PIC-NEXT: L82$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L82$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _har02:
+; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq (%rax), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _har02:
+; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq (%rax), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _har02:
+; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq (%rax), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @har03() nounwind {
+entry:
+ ret i8* bitcast ([131072 x i32]* @dsrc to i8*)
+; LINUX-64-STATIC: har03:
+; LINUX-64-STATIC: movl $dsrc, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: har03:
+; LINUX-32-STATIC: movl $dsrc, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: har03:
+; LINUX-32-PIC: movl $dsrc, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: har03:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _har03:
+; DARWIN-32-STATIC: movl $_dsrc, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _har03:
+; DARWIN-32-DYNAMIC: movl $_dsrc, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _har03:
+; DARWIN-32-PIC: call L83$pb
+; DARWIN-32-PIC-NEXT: L83$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal _dsrc-L83$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _har03:
+; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _har03:
+; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _har03:
+; DARWIN-64-PIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @har04() nounwind {
+entry:
+ ret i8* bitcast ([131072 x i32]* @ddst to i8*)
+; LINUX-64-STATIC: har04:
+; LINUX-64-STATIC: movl $ddst, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: har04:
+; LINUX-32-STATIC: movl $ddst, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: har04:
+; LINUX-32-PIC: movl $ddst, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: har04:
+; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _har04:
+; DARWIN-32-STATIC: movl $_ddst, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _har04:
+; DARWIN-32-DYNAMIC: movl $_ddst, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _har04:
+; DARWIN-32-PIC: call L84$pb
+; DARWIN-32-PIC-NEXT: L84$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal _ddst-L84$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _har04:
+; DARWIN-64-STATIC: leaq _ddst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _har04:
+; DARWIN-64-DYNAMIC: leaq _ddst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _har04:
+; DARWIN-64-PIC: leaq _ddst(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @har05() nounwind {
+entry:
+ %0 = load i32** @dptr, align 8
+ %1 = bitcast i32* %0 to i8*
+ ret i8* %1
+; LINUX-64-STATIC: har05:
+; LINUX-64-STATIC: movq dptr(%rip), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: har05:
+; LINUX-32-STATIC: movl dptr, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: har05:
+; LINUX-32-PIC: movl dptr, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: har05:
+; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq (%rax), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _har05:
+; DARWIN-32-STATIC: movl _dptr, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _har05:
+; DARWIN-32-DYNAMIC: movl _dptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _har05:
+; DARWIN-32-PIC: call L85$pb
+; DARWIN-32-PIC-NEXT: L85$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl _dptr-L85$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _har05:
+; DARWIN-64-STATIC: movq _dptr(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _har05:
+; DARWIN-64-DYNAMIC: movq _dptr(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _har05:
+; DARWIN-64-PIC: movq _dptr(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @har06() nounwind {
+entry:
+ ret i8* bitcast ([131072 x i32]* @lsrc to i8*)
+; LINUX-64-STATIC: har06:
+; LINUX-64-STATIC: movl $lsrc, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: har06:
+; LINUX-32-STATIC: movl $lsrc, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: har06:
+; LINUX-32-PIC: movl $lsrc, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: har06:
+; LINUX-64-PIC: leaq lsrc(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _har06:
+; DARWIN-32-STATIC: movl $_lsrc, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _har06:
+; DARWIN-32-DYNAMIC: movl $_lsrc, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _har06:
+; DARWIN-32-PIC: call L86$pb
+; DARWIN-32-PIC-NEXT: L86$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal _lsrc-L86$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _har06:
+; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _har06:
+; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _har06:
+; DARWIN-64-PIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @har07() nounwind {
+entry:
+ ret i8* bitcast ([131072 x i32]* @ldst to i8*)
+; LINUX-64-STATIC: har07:
+; LINUX-64-STATIC: movl $ldst, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: har07:
+; LINUX-32-STATIC: movl $ldst, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: har07:
+; LINUX-32-PIC: movl $ldst, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: har07:
+; LINUX-64-PIC: leaq ldst(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _har07:
+; DARWIN-32-STATIC: movl $_ldst, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _har07:
+; DARWIN-32-DYNAMIC: movl $_ldst, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _har07:
+; DARWIN-32-PIC: call L87$pb
+; DARWIN-32-PIC-NEXT: L87$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal _ldst-L87$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _har07:
+; DARWIN-64-STATIC: leaq _ldst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _har07:
+; DARWIN-64-DYNAMIC: leaq _ldst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _har07:
+; DARWIN-64-PIC: leaq _ldst(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @har08() nounwind {
+entry:
+ %0 = load i32** @lptr, align 8
+ %1 = bitcast i32* %0 to i8*
+ ret i8* %1
+; LINUX-64-STATIC: har08:
+; LINUX-64-STATIC: movq lptr(%rip), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: har08:
+; LINUX-32-STATIC: movl lptr, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: har08:
+; LINUX-32-PIC: movl lptr, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: har08:
+; LINUX-64-PIC: movq lptr(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _har08:
+; DARWIN-32-STATIC: movl _lptr, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _har08:
+; DARWIN-32-DYNAMIC: movl _lptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _har08:
+; DARWIN-32-PIC: call L88$pb
+; DARWIN-32-PIC-NEXT: L88$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl _lptr-L88$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _har08:
+; DARWIN-64-STATIC: movq _lptr(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _har08:
+; DARWIN-64-DYNAMIC: movq _lptr(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _har08:
+; DARWIN-64-PIC: movq _lptr(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bat00() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16) to i8*)
+; LINUX-64-STATIC: bat00:
+; LINUX-64-STATIC: movl $src+64, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bat00:
+; LINUX-32-STATIC: movl $src+64, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bat00:
+; LINUX-32-PIC: movl $src+64, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bat00:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: addq $64, %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bat00:
+; DARWIN-32-STATIC: movl $_src+64, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bat00:
+; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl $64, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bat00:
+; DARWIN-32-PIC: call L89$pb
+; DARWIN-32-PIC-NEXT: L89$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L89$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: addl $64, %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bat00:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: addq $64, %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bat00:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: addq $64, %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bat00:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: addq $64, %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bxt00() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16) to i8*)
+; LINUX-64-STATIC: bxt00:
+; LINUX-64-STATIC: movl $xsrc+64, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bxt00:
+; LINUX-32-STATIC: movl $xsrc+64, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bxt00:
+; LINUX-32-PIC: movl $xsrc+64, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bxt00:
+; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: addq $64, %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bxt00:
+; DARWIN-32-STATIC: movl $_xsrc+64, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bxt00:
+; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl $64, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bxt00:
+; DARWIN-32-PIC: call L90$pb
+; DARWIN-32-PIC-NEXT: L90$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L90$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: addl $64, %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bxt00:
+; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: addq $64, %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bxt00:
+; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: addq $64, %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bxt00:
+; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: addq $64, %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bat01() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16) to i8*)
+; LINUX-64-STATIC: bat01:
+; LINUX-64-STATIC: movl $dst+64, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bat01:
+; LINUX-32-STATIC: movl $dst+64, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bat01:
+; LINUX-32-PIC: movl $dst+64, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bat01:
+; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: addq $64, %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bat01:
+; DARWIN-32-STATIC: movl $_dst+64, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bat01:
+; DARWIN-32-DYNAMIC: movl L_dst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl $64, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bat01:
+; DARWIN-32-PIC: call L91$pb
+; DARWIN-32-PIC-NEXT: L91$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L91$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: addl $64, %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bat01:
+; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: addq $64, %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bat01:
+; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: addq $64, %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bat01:
+; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: addq $64, %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bxt01() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16) to i8*)
+; LINUX-64-STATIC: bxt01:
+; LINUX-64-STATIC: movl $xdst+64, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bxt01:
+; LINUX-32-STATIC: movl $xdst+64, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bxt01:
+; LINUX-32-PIC: movl $xdst+64, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bxt01:
+; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: addq $64, %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bxt01:
+; DARWIN-32-STATIC: movl $_xdst+64, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bxt01:
+; DARWIN-32-DYNAMIC: movl L_xdst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl $64, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bxt01:
+; DARWIN-32-PIC: call L92$pb
+; DARWIN-32-PIC-NEXT: L92$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L92$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: addl $64, %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bxt01:
+; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: addq $64, %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bxt01:
+; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: addq $64, %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bxt01:
+; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: addq $64, %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bat02() nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = getelementptr i32* %0, i64 16
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: bat02:
+; LINUX-64-STATIC: movq ptr(%rip), %rax
+; LINUX-64-STATIC: addq $64, %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bat02:
+; LINUX-32-STATIC: movl ptr, %eax
+; LINUX-32-STATIC-NEXT: addl $64, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bat02:
+; LINUX-32-PIC: movl ptr, %eax
+; LINUX-32-PIC-NEXT: addl $64, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bat02:
+; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq (%rax), %rax
+; LINUX-64-PIC-NEXT: addq $64, %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bat02:
+; DARWIN-32-STATIC: movl _ptr, %eax
+; DARWIN-32-STATIC-NEXT: addl $64, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bat02:
+; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax
+; DARWIN-32-DYNAMIC-NEXT: addl $64, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bat02:
+; DARWIN-32-PIC: call L93$pb
+; DARWIN-32-PIC-NEXT: L93$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L93$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (%eax), %eax
+; DARWIN-32-PIC-NEXT: addl $64, %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bat02:
+; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq (%rax), %rax
+; DARWIN-64-STATIC-NEXT: addq $64, %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bat02:
+; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq (%rax), %rax
+; DARWIN-64-DYNAMIC-NEXT: addq $64, %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bat02:
+; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq (%rax), %rax
+; DARWIN-64-PIC-NEXT: addq $64, %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bat03() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16) to i8*)
+; LINUX-64-STATIC: bat03:
+; LINUX-64-STATIC: movl $dsrc+64, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bat03:
+; LINUX-32-STATIC: movl $dsrc+64, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bat03:
+; LINUX-32-PIC: movl $dsrc+64, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bat03:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: addq $64, %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bat03:
+; DARWIN-32-STATIC: movl $_dsrc+64, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bat03:
+; DARWIN-32-DYNAMIC: movl $_dsrc+64, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bat03:
+; DARWIN-32-PIC: call L94$pb
+; DARWIN-32-PIC-NEXT: L94$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal (_dsrc-L94$pb)+64(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bat03:
+; DARWIN-64-STATIC: leaq _dsrc+64(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bat03:
+; DARWIN-64-DYNAMIC: leaq _dsrc+64(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bat03:
+; DARWIN-64-PIC: leaq _dsrc+64(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bat04() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16) to i8*)
+; LINUX-64-STATIC: bat04:
+; LINUX-64-STATIC: movl $ddst+64, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bat04:
+; LINUX-32-STATIC: movl $ddst+64, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bat04:
+; LINUX-32-PIC: movl $ddst+64, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bat04:
+; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: addq $64, %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bat04:
+; DARWIN-32-STATIC: movl $_ddst+64, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bat04:
+; DARWIN-32-DYNAMIC: movl $_ddst+64, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bat04:
+; DARWIN-32-PIC: call L95$pb
+; DARWIN-32-PIC-NEXT: L95$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal (_ddst-L95$pb)+64(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bat04:
+; DARWIN-64-STATIC: leaq _ddst+64(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bat04:
+; DARWIN-64-DYNAMIC: leaq _ddst+64(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bat04:
+; DARWIN-64-PIC: leaq _ddst+64(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bat05() nounwind {
+entry:
+ %0 = load i32** @dptr, align 8
+ %1 = getelementptr i32* %0, i64 16
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: bat05:
+; LINUX-64-STATIC: movq dptr(%rip), %rax
+; LINUX-64-STATIC: addq $64, %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bat05:
+; LINUX-32-STATIC: movl dptr, %eax
+; LINUX-32-STATIC-NEXT: addl $64, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bat05:
+; LINUX-32-PIC: movl dptr, %eax
+; LINUX-32-PIC-NEXT: addl $64, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bat05:
+; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq (%rax), %rax
+; LINUX-64-PIC-NEXT: addq $64, %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bat05:
+; DARWIN-32-STATIC: movl _dptr, %eax
+; DARWIN-32-STATIC-NEXT: addl $64, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bat05:
+; DARWIN-32-DYNAMIC: movl _dptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl $64, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bat05:
+; DARWIN-32-PIC: call L96$pb
+; DARWIN-32-PIC-NEXT: L96$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl _dptr-L96$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: addl $64, %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bat05:
+; DARWIN-64-STATIC: movq _dptr(%rip), %rax
+; DARWIN-64-STATIC-NEXT: addq $64, %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bat05:
+; DARWIN-64-DYNAMIC: movq _dptr(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: addq $64, %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bat05:
+; DARWIN-64-PIC: movq _dptr(%rip), %rax
+; DARWIN-64-PIC-NEXT: addq $64, %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bat06() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16) to i8*)
+; LINUX-64-STATIC: bat06:
+; LINUX-64-STATIC: movl $lsrc+64, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bat06:
+; LINUX-32-STATIC: movl $lsrc+64, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bat06:
+; LINUX-32-PIC: movl $lsrc+64, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bat06:
+; LINUX-64-PIC: leaq lsrc+64(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bat06:
+; DARWIN-32-STATIC: movl $_lsrc+64, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bat06:
+; DARWIN-32-DYNAMIC: movl $_lsrc+64, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bat06:
+; DARWIN-32-PIC: call L97$pb
+; DARWIN-32-PIC-NEXT: L97$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal (_lsrc-L97$pb)+64(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bat06:
+; DARWIN-64-STATIC: leaq _lsrc+64(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bat06:
+; DARWIN-64-DYNAMIC: leaq _lsrc+64(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bat06:
+; DARWIN-64-PIC: leaq _lsrc+64(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bat07() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16) to i8*)
+; LINUX-64-STATIC: bat07:
+; LINUX-64-STATIC: movl $ldst+64, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bat07:
+; LINUX-32-STATIC: movl $ldst+64, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bat07:
+; LINUX-32-PIC: movl $ldst+64, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bat07:
+; LINUX-64-PIC: leaq ldst+64(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bat07:
+; DARWIN-32-STATIC: movl $_ldst+64, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bat07:
+; DARWIN-32-DYNAMIC: movl $_ldst+64, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bat07:
+; DARWIN-32-PIC: call L98$pb
+; DARWIN-32-PIC-NEXT: L98$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal (_ldst-L98$pb)+64(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bat07:
+; DARWIN-64-STATIC: leaq _ldst+64(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bat07:
+; DARWIN-64-DYNAMIC: leaq _ldst+64(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bat07:
+; DARWIN-64-PIC: leaq _ldst+64(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bat08() nounwind {
+entry:
+ %0 = load i32** @lptr, align 8
+ %1 = getelementptr i32* %0, i64 16
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: bat08:
+; LINUX-64-STATIC: movq lptr(%rip), %rax
+; LINUX-64-STATIC: addq $64, %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bat08:
+; LINUX-32-STATIC: movl lptr, %eax
+; LINUX-32-STATIC-NEXT: addl $64, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bat08:
+; LINUX-32-PIC: movl lptr, %eax
+; LINUX-32-PIC-NEXT: addl $64, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bat08:
+; LINUX-64-PIC: movq lptr(%rip), %rax
+; LINUX-64-PIC-NEXT: addq $64, %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bat08:
+; DARWIN-32-STATIC: movl _lptr, %eax
+; DARWIN-32-STATIC-NEXT: addl $64, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bat08:
+; DARWIN-32-DYNAMIC: movl _lptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl $64, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bat08:
+; DARWIN-32-PIC: call L99$pb
+; DARWIN-32-PIC-NEXT: L99$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl _lptr-L99$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: addl $64, %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bat08:
+; DARWIN-64-STATIC: movq _lptr(%rip), %rax
+; DARWIN-64-STATIC-NEXT: addq $64, %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bat08:
+; DARWIN-64-DYNAMIC: movq _lptr(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: addq $64, %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bat08:
+; DARWIN-64-PIC: movq _lptr(%rip), %rax
+; DARWIN-64-PIC-NEXT: addq $64, %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bam00() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([131072 x i32]* @src, i32 0, i64 65536) to i8*)
+; LINUX-64-STATIC: bam00:
+; LINUX-64-STATIC: movl $src+262144, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bam00:
+; LINUX-32-STATIC: movl $src+262144, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bam00:
+; LINUX-32-PIC: movl $src+262144, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bam00:
+; LINUX-64-PIC: movl $262144, %eax
+; LINUX-64-PIC-NEXT: addq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bam00:
+; DARWIN-32-STATIC: movl $_src+262144, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bam00:
+; DARWIN-32-DYNAMIC: movl $262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl L_src$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bam00:
+; DARWIN-32-PIC: call L100$pb
+; DARWIN-32-PIC-NEXT: L100$pb:
+; DARWIN-32-PIC-NEXT: popl %ecx
+; DARWIN-32-PIC-NEXT: movl $262144, %eax
+; DARWIN-32-PIC-NEXT: addl L_src$non_lazy_ptr-L100$pb(%ecx), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bam00:
+; DARWIN-64-STATIC: movl $262144, %eax
+; DARWIN-64-STATIC-NEXT: addq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bam00:
+; DARWIN-64-DYNAMIC: movl $262144, %eax
+; DARWIN-64-DYNAMIC-NEXT: addq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bam00:
+; DARWIN-64-PIC: movl $262144, %eax
+; DARWIN-64-PIC-NEXT: addq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bam01() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536) to i8*)
+; LINUX-64-STATIC: bam01:
+; LINUX-64-STATIC: movl $dst+262144, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bam01:
+; LINUX-32-STATIC: movl $dst+262144, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bam01:
+; LINUX-32-PIC: movl $dst+262144, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bam01:
+; LINUX-64-PIC: movl $262144, %eax
+; LINUX-64-PIC-NEXT: addq dst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bam01:
+; DARWIN-32-STATIC: movl $_dst+262144, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bam01:
+; DARWIN-32-DYNAMIC: movl $262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl L_dst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bam01:
+; DARWIN-32-PIC: call L101$pb
+; DARWIN-32-PIC-NEXT: L101$pb:
+; DARWIN-32-PIC-NEXT: popl %ecx
+; DARWIN-32-PIC-NEXT: movl $262144, %eax
+; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L101$pb(%ecx), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bam01:
+; DARWIN-64-STATIC: movl $262144, %eax
+; DARWIN-64-STATIC-NEXT: addq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bam01:
+; DARWIN-64-DYNAMIC: movl $262144, %eax
+; DARWIN-64-DYNAMIC-NEXT: addq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bam01:
+; DARWIN-64-PIC: movl $262144, %eax
+; DARWIN-64-PIC-NEXT: addq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bxm01() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 65536) to i8*)
+; LINUX-64-STATIC: bxm01:
+; LINUX-64-STATIC: movl $xdst+262144, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bxm01:
+; LINUX-32-STATIC: movl $xdst+262144, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bxm01:
+; LINUX-32-PIC: movl $xdst+262144, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bxm01:
+; LINUX-64-PIC: movl $262144, %eax
+; LINUX-64-PIC-NEXT: addq xdst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bxm01:
+; DARWIN-32-STATIC: movl $_xdst+262144, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bxm01:
+; DARWIN-32-DYNAMIC: movl $262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl L_xdst$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bxm01:
+; DARWIN-32-PIC: call L102$pb
+; DARWIN-32-PIC-NEXT: L102$pb:
+; DARWIN-32-PIC-NEXT: popl %ecx
+; DARWIN-32-PIC-NEXT: movl $262144, %eax
+; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L102$pb(%ecx), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bxm01:
+; DARWIN-64-STATIC: movl $262144, %eax
+; DARWIN-64-STATIC-NEXT: addq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bxm01:
+; DARWIN-64-DYNAMIC: movl $262144, %eax
+; DARWIN-64-DYNAMIC-NEXT: addq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bxm01:
+; DARWIN-64-PIC: movl $262144, %eax
+; DARWIN-64-PIC-NEXT: addq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bam02() nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = getelementptr i32* %0, i64 65536
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: bam02:
+; LINUX-64-STATIC: movl $262144, %eax
+; LINUX-64-STATIC: addq ptr(%rip), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bam02:
+; LINUX-32-STATIC: movl $262144, %eax
+; LINUX-32-STATIC-NEXT: addl ptr, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bam02:
+; LINUX-32-PIC: movl $262144, %eax
+; LINUX-32-PIC-NEXT: addl ptr, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bam02:
+; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl $262144, %eax
+; LINUX-64-PIC-NEXT: addq (%rcx), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bam02:
+; DARWIN-32-STATIC: movl $262144, %eax
+; DARWIN-32-STATIC-NEXT: addl _ptr, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bam02:
+; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: movl $262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl (%ecx), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bam02:
+; DARWIN-32-PIC: call L103$pb
+; DARWIN-32-PIC-NEXT: L103$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L103$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: movl $262144, %eax
+; DARWIN-32-PIC-NEXT: addl (%ecx), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bam02:
+; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC-NEXT: movl $262144, %eax
+; DARWIN-64-STATIC-NEXT: addq (%rcx), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bam02:
+; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC-NEXT: movl $262144, %eax
+; DARWIN-64-DYNAMIC-NEXT: addq (%rcx), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bam02:
+; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC-NEXT: movl $262144, %eax
+; DARWIN-64-PIC-NEXT: addq (%rcx), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bam03() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 65536) to i8*)
+; LINUX-64-STATIC: bam03:
+; LINUX-64-STATIC: movl $dsrc+262144, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bam03:
+; LINUX-32-STATIC: movl $dsrc+262144, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bam03:
+; LINUX-32-PIC: movl $dsrc+262144, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bam03:
+; LINUX-64-PIC: movl $262144, %eax
+; LINUX-64-PIC-NEXT: addq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bam03:
+; DARWIN-32-STATIC: movl $_dsrc+262144, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bam03:
+; DARWIN-32-DYNAMIC: movl $_dsrc+262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bam03:
+; DARWIN-32-PIC: call L104$pb
+; DARWIN-32-PIC-NEXT: L104$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal (_dsrc-L104$pb)+262144(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bam03:
+; DARWIN-64-STATIC: leaq _dsrc+262144(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bam03:
+; DARWIN-64-DYNAMIC: leaq _dsrc+262144(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bam03:
+; DARWIN-64-PIC: leaq _dsrc+262144(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bam04() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536) to i8*)
+; LINUX-64-STATIC: bam04:
+; LINUX-64-STATIC: movl $ddst+262144, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bam04:
+; LINUX-32-STATIC: movl $ddst+262144, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bam04:
+; LINUX-32-PIC: movl $ddst+262144, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bam04:
+; LINUX-64-PIC: movl $262144, %eax
+; LINUX-64-PIC-NEXT: addq ddst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bam04:
+; DARWIN-32-STATIC: movl $_ddst+262144, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bam04:
+; DARWIN-32-DYNAMIC: movl $_ddst+262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bam04:
+; DARWIN-32-PIC: call L105$pb
+; DARWIN-32-PIC-NEXT: L105$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal (_ddst-L105$pb)+262144(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bam04:
+; DARWIN-64-STATIC: leaq _ddst+262144(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bam04:
+; DARWIN-64-DYNAMIC: leaq _ddst+262144(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bam04:
+; DARWIN-64-PIC: leaq _ddst+262144(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bam05() nounwind {
+entry:
+ %0 = load i32** @dptr, align 8
+ %1 = getelementptr i32* %0, i64 65536
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: bam05:
+; LINUX-64-STATIC: movl $262144, %eax
+; LINUX-64-STATIC: addq dptr(%rip), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bam05:
+; LINUX-32-STATIC: movl $262144, %eax
+; LINUX-32-STATIC-NEXT: addl dptr, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bam05:
+; LINUX-32-PIC: movl $262144, %eax
+; LINUX-32-PIC-NEXT: addl dptr, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bam05:
+; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), %rcx
+; LINUX-64-PIC-NEXT: movl $262144, %eax
+; LINUX-64-PIC-NEXT: addq (%rcx), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bam05:
+; DARWIN-32-STATIC: movl $262144, %eax
+; DARWIN-32-STATIC-NEXT: addl _dptr, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bam05:
+; DARWIN-32-DYNAMIC: movl $262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl _dptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bam05:
+; DARWIN-32-PIC: call L106$pb
+; DARWIN-32-PIC-NEXT: L106$pb:
+; DARWIN-32-PIC-NEXT: popl %ecx
+; DARWIN-32-PIC-NEXT: movl $262144, %eax
+; DARWIN-32-PIC-NEXT: addl _dptr-L106$pb(%ecx), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bam05:
+; DARWIN-64-STATIC: movl $262144, %eax
+; DARWIN-64-STATIC-NEXT: addq _dptr(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bam05:
+; DARWIN-64-DYNAMIC: movl $262144, %eax
+; DARWIN-64-DYNAMIC-NEXT: addq _dptr(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bam05:
+; DARWIN-64-PIC: movl $262144, %eax
+; DARWIN-64-PIC-NEXT: addq _dptr(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bam06() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 65536) to i8*)
+; LINUX-64-STATIC: bam06:
+; LINUX-64-STATIC: movl $lsrc+262144, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bam06:
+; LINUX-32-STATIC: movl $lsrc+262144, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bam06:
+; LINUX-32-PIC: movl $lsrc+262144, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bam06:
+; LINUX-64-PIC: leaq lsrc+262144(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bam06:
+; DARWIN-32-STATIC: movl $_lsrc+262144, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bam06:
+; DARWIN-32-DYNAMIC: movl $_lsrc+262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bam06:
+; DARWIN-32-PIC: call L107$pb
+; DARWIN-32-PIC-NEXT: L107$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal (_lsrc-L107$pb)+262144(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bam06:
+; DARWIN-64-STATIC: leaq _lsrc+262144(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bam06:
+; DARWIN-64-DYNAMIC: leaq _lsrc+262144(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bam06:
+; DARWIN-64-PIC: leaq _lsrc+262144(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bam07() nounwind {
+entry:
+ ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536) to i8*)
+; LINUX-64-STATIC: bam07:
+; LINUX-64-STATIC: movl $ldst+262144, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bam07:
+; LINUX-32-STATIC: movl $ldst+262144, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bam07:
+; LINUX-32-PIC: movl $ldst+262144, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bam07:
+; LINUX-64-PIC: leaq ldst+262144(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bam07:
+; DARWIN-32-STATIC: movl $_ldst+262144, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bam07:
+; DARWIN-32-DYNAMIC: movl $_ldst+262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bam07:
+; DARWIN-32-PIC: call L108$pb
+; DARWIN-32-PIC-NEXT: L108$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal (_ldst-L108$pb)+262144(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bam07:
+; DARWIN-64-STATIC: leaq _ldst+262144(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bam07:
+; DARWIN-64-DYNAMIC: leaq _ldst+262144(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bam07:
+; DARWIN-64-PIC: leaq _ldst+262144(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @bam08() nounwind {
+entry:
+ %0 = load i32** @lptr, align 8
+ %1 = getelementptr i32* %0, i64 65536
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: bam08:
+; LINUX-64-STATIC: movl $262144, %eax
+; LINUX-64-STATIC: addq lptr(%rip), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: bam08:
+; LINUX-32-STATIC: movl $262144, %eax
+; LINUX-32-STATIC-NEXT: addl lptr, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: bam08:
+; LINUX-32-PIC: movl $262144, %eax
+; LINUX-32-PIC-NEXT: addl lptr, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: bam08:
+; LINUX-64-PIC: movl $262144, %eax
+; LINUX-64-PIC-NEXT: addq lptr(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _bam08:
+; DARWIN-32-STATIC: movl $262144, %eax
+; DARWIN-32-STATIC-NEXT: addl _lptr, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _bam08:
+; DARWIN-32-DYNAMIC: movl $262144, %eax
+; DARWIN-32-DYNAMIC-NEXT: addl _lptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _bam08:
+; DARWIN-32-PIC: call L109$pb
+; DARWIN-32-PIC-NEXT: L109$pb:
+; DARWIN-32-PIC-NEXT: popl %ecx
+; DARWIN-32-PIC-NEXT: movl $262144, %eax
+; DARWIN-32-PIC-NEXT: addl _lptr-L109$pb(%ecx), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _bam08:
+; DARWIN-64-STATIC: movl $262144, %eax
+; DARWIN-64-STATIC-NEXT: addq _lptr(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _bam08:
+; DARWIN-64-DYNAMIC: movl $262144, %eax
+; DARWIN-64-DYNAMIC-NEXT: addq _lptr(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _bam08:
+; DARWIN-64-PIC: movl $262144, %eax
+; DARWIN-64-PIC-NEXT: addq _lptr(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cat00(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 16
+ %1 = getelementptr [131072 x i32]* @src, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cat00:
+; LINUX-64-STATIC: leaq src+64(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cat00:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal src+64(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cat00:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal src+64(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cat00:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cat00:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _src+64(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cat00:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cat00:
+; DARWIN-32-PIC: call L110$pb
+; DARWIN-32-PIC-NEXT: L110$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L110$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cat00:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cat00:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cat00:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cxt00(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 16
+ %1 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cxt00:
+; LINUX-64-STATIC: leaq xsrc+64(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cxt00:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal xsrc+64(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cxt00:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal xsrc+64(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cxt00:
+; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cxt00:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _xsrc+64(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cxt00:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cxt00:
+; DARWIN-32-PIC: call L111$pb
+; DARWIN-32-PIC-NEXT: L111$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L111$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cxt00:
+; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cxt00:
+; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cxt00:
+; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cat01(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 16
+ %1 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cat01:
+; LINUX-64-STATIC: leaq dst+64(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cat01:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal dst+64(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cat01:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal dst+64(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cat01:
+; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cat01:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _dst+64(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cat01:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cat01:
+; DARWIN-32-PIC: call L112$pb
+; DARWIN-32-PIC-NEXT: L112$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L112$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cat01:
+; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cat01:
+; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cat01:
+; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cxt01(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 16
+ %1 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cxt01:
+; LINUX-64-STATIC: leaq xdst+64(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cxt01:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal xdst+64(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cxt01:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal xdst+64(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cxt01:
+; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cxt01:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _xdst+64(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cxt01:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cxt01:
+; DARWIN-32-PIC: call L113$pb
+; DARWIN-32-PIC-NEXT: L113$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L113$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cxt01:
+; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cxt01:
+; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cxt01:
+; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cat02(i64 %i) nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = add i64 %i, 16
+ %2 = getelementptr i32* %0, i64 %1
+ %3 = bitcast i32* %2 to i8*
+ ret i8* %3
+; LINUX-64-STATIC: cat02:
+; LINUX-64-STATIC: movq ptr(%rip), %rax
+; LINUX-64-STATIC: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cat02:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl ptr, %ecx
+; LINUX-32-STATIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cat02:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl ptr, %ecx
+; LINUX-32-PIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cat02:
+; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq (%rax), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cat02:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _ptr, %ecx
+; DARWIN-32-STATIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cat02:
+; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 64(%eax,%ecx,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cat02:
+; DARWIN-32-PIC: call L114$pb
+; DARWIN-32-PIC-NEXT: L114$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L114$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (%eax), %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cat02:
+; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq (%rax), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cat02:
+; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq (%rax), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cat02:
+; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq (%rax), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cat03(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 16
+ %1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cat03:
+; LINUX-64-STATIC: leaq dsrc+64(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cat03:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal dsrc+64(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cat03:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal dsrc+64(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cat03:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cat03:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _dsrc+64(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cat03:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: leal _dsrc+64(,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cat03:
+; DARWIN-32-PIC: call L115$pb
+; DARWIN-32-PIC-NEXT: L115$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal (_dsrc-L115$pb)+64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cat03:
+; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cat03:
+; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cat03:
+; DARWIN-64-PIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cat04(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 16
+ %1 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cat04:
+; LINUX-64-STATIC: leaq ddst+64(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cat04:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal ddst+64(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cat04:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal ddst+64(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cat04:
+; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cat04:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _ddst+64(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cat04:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: leal _ddst+64(,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cat04:
+; DARWIN-32-PIC: call L116$pb
+; DARWIN-32-PIC-NEXT: L116$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal (_ddst-L116$pb)+64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cat04:
+; DARWIN-64-STATIC: leaq _ddst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cat04:
+; DARWIN-64-DYNAMIC: leaq _ddst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cat04:
+; DARWIN-64-PIC: leaq _ddst(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cat05(i64 %i) nounwind {
+entry:
+ %0 = load i32** @dptr, align 8
+ %1 = add i64 %i, 16
+ %2 = getelementptr i32* %0, i64 %1
+ %3 = bitcast i32* %2 to i8*
+ ret i8* %3
+; LINUX-64-STATIC: cat05:
+; LINUX-64-STATIC: movq dptr(%rip), %rax
+; LINUX-64-STATIC: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cat05:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl dptr, %ecx
+; LINUX-32-STATIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cat05:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl dptr, %ecx
+; LINUX-32-PIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cat05:
+; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq (%rax), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cat05:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _dptr, %ecx
+; DARWIN-32-STATIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cat05:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cat05:
+; DARWIN-32-PIC: call L117$pb
+; DARWIN-32-PIC-NEXT: L117$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl _dptr-L117$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cat05:
+; DARWIN-64-STATIC: movq _dptr(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cat05:
+; DARWIN-64-DYNAMIC: movq _dptr(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cat05:
+; DARWIN-64-PIC: movq _dptr(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cat06(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 16
+ %1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cat06:
+; LINUX-64-STATIC: leaq lsrc+64(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cat06:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal lsrc+64(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cat06:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal lsrc+64(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cat06:
+; LINUX-64-PIC: leaq lsrc(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cat06:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _lsrc+64(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cat06:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: leal _lsrc+64(,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cat06:
+; DARWIN-32-PIC: call L118$pb
+; DARWIN-32-PIC-NEXT: L118$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal (_lsrc-L118$pb)+64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cat06:
+; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cat06:
+; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cat06:
+; DARWIN-64-PIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cat07(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 16
+ %1 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cat07:
+; LINUX-64-STATIC: leaq ldst+64(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cat07:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal ldst+64(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cat07:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal ldst+64(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cat07:
+; LINUX-64-PIC: leaq ldst(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cat07:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _ldst+64(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cat07:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: leal _ldst+64(,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cat07:
+; DARWIN-32-PIC: call L119$pb
+; DARWIN-32-PIC-NEXT: L119$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal (_ldst-L119$pb)+64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cat07:
+; DARWIN-64-STATIC: leaq _ldst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cat07:
+; DARWIN-64-DYNAMIC: leaq _ldst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cat07:
+; DARWIN-64-PIC: leaq _ldst(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cat08(i64 %i) nounwind {
+entry:
+ %0 = load i32** @lptr, align 8
+ %1 = add i64 %i, 16
+ %2 = getelementptr i32* %0, i64 %1
+ %3 = bitcast i32* %2 to i8*
+ ret i8* %3
+; LINUX-64-STATIC: cat08:
+; LINUX-64-STATIC: movq lptr(%rip), %rax
+; LINUX-64-STATIC: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cat08:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl lptr, %ecx
+; LINUX-32-STATIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cat08:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl lptr, %ecx
+; LINUX-32-PIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cat08:
+; LINUX-64-PIC: movq lptr(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cat08:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _lptr, %ecx
+; DARWIN-32-STATIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cat08:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cat08:
+; DARWIN-32-PIC: call L120$pb
+; DARWIN-32-PIC-NEXT: L120$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl _lptr-L120$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cat08:
+; DARWIN-64-STATIC: movq _lptr(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cat08:
+; DARWIN-64-DYNAMIC: movq _lptr(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cat08:
+; DARWIN-64-PIC: movq _lptr(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cam00(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 65536
+ %1 = getelementptr [131072 x i32]* @src, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cam00:
+; LINUX-64-STATIC: leaq src+262144(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cam00:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal src+262144(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cam00:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal src+262144(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cam00:
+; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cam00:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _src+262144(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cam00:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cam00:
+; DARWIN-32-PIC: call L121$pb
+; DARWIN-32-PIC-NEXT: L121$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L121$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cam00:
+; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cam00:
+; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cam00:
+; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cxm00(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 65536
+ %1 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cxm00:
+; LINUX-64-STATIC: leaq xsrc+262144(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cxm00:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal xsrc+262144(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cxm00:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal xsrc+262144(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cxm00:
+; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cxm00:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _xsrc+262144(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cxm00:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cxm00:
+; DARWIN-32-PIC: call L122$pb
+; DARWIN-32-PIC-NEXT: L122$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L122$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cxm00:
+; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cxm00:
+; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cxm00:
+; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cam01(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 65536
+ %1 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cam01:
+; LINUX-64-STATIC: leaq dst+262144(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cam01:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal dst+262144(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cam01:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal dst+262144(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cam01:
+; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cam01:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _dst+262144(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cam01:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cam01:
+; DARWIN-32-PIC: call L123$pb
+; DARWIN-32-PIC-NEXT: L123$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L123$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cam01:
+; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cam01:
+; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cam01:
+; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cxm01(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 65536
+ %1 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cxm01:
+; LINUX-64-STATIC: leaq xdst+262144(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cxm01:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal xdst+262144(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cxm01:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal xdst+262144(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cxm01:
+; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cxm01:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _xdst+262144(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cxm01:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cxm01:
+; DARWIN-32-PIC: call L124$pb
+; DARWIN-32-PIC-NEXT: L124$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L124$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cxm01:
+; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cxm01:
+; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cxm01:
+; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cam02(i64 %i) nounwind {
+entry:
+ %0 = load i32** @ptr, align 8
+ %1 = add i64 %i, 65536
+ %2 = getelementptr i32* %0, i64 %1
+ %3 = bitcast i32* %2 to i8*
+ ret i8* %3
+; LINUX-64-STATIC: cam02:
+; LINUX-64-STATIC: movq ptr(%rip), %rax
+; LINUX-64-STATIC: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cam02:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl ptr, %ecx
+; LINUX-32-STATIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cam02:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl ptr, %ecx
+; LINUX-32-PIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cam02:
+; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq (%rax), %rax
+; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cam02:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _ptr, %ecx
+; DARWIN-32-STATIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cam02:
+; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 262144(%eax,%ecx,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cam02:
+; DARWIN-32-PIC: call L125$pb
+; DARWIN-32-PIC-NEXT: L125$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L125$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: movl (%eax), %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cam02:
+; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: movq (%rax), %rax
+; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cam02:
+; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: movq (%rax), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cam02:
+; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: movq (%rax), %rax
+; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cam03(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 65536
+ %1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cam03:
+; LINUX-64-STATIC: leaq dsrc+262144(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cam03:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal dsrc+262144(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cam03:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal dsrc+262144(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cam03:
+; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cam03:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _dsrc+262144(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cam03:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: leal _dsrc+262144(,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cam03:
+; DARWIN-32-PIC: call L126$pb
+; DARWIN-32-PIC-NEXT: L126$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal (_dsrc-L126$pb)+262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cam03:
+; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cam03:
+; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cam03:
+; DARWIN-64-PIC: leaq _dsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cam04(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 65536
+ %1 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cam04:
+; LINUX-64-STATIC: leaq ddst+262144(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cam04:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal ddst+262144(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cam04:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal ddst+262144(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cam04:
+; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cam04:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _ddst+262144(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cam04:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: leal _ddst+262144(,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cam04:
+; DARWIN-32-PIC: call L127$pb
+; DARWIN-32-PIC-NEXT: L127$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal (_ddst-L127$pb)+262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cam04:
+; DARWIN-64-STATIC: leaq _ddst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cam04:
+; DARWIN-64-DYNAMIC: leaq _ddst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cam04:
+; DARWIN-64-PIC: leaq _ddst(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cam05(i64 %i) nounwind {
+entry:
+ %0 = load i32** @dptr, align 8
+ %1 = add i64 %i, 65536
+ %2 = getelementptr i32* %0, i64 %1
+ %3 = bitcast i32* %2 to i8*
+ ret i8* %3
+; LINUX-64-STATIC: cam05:
+; LINUX-64-STATIC: movq dptr(%rip), %rax
+; LINUX-64-STATIC: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cam05:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl dptr, %ecx
+; LINUX-32-STATIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cam05:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl dptr, %ecx
+; LINUX-32-PIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cam05:
+; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: movq (%rax), %rax
+; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cam05:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _dptr, %ecx
+; DARWIN-32-STATIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cam05:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cam05:
+; DARWIN-32-PIC: call L128$pb
+; DARWIN-32-PIC-NEXT: L128$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl _dptr-L128$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cam05:
+; DARWIN-64-STATIC: movq _dptr(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cam05:
+; DARWIN-64-DYNAMIC: movq _dptr(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cam05:
+; DARWIN-64-PIC: movq _dptr(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cam06(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 65536
+ %1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cam06:
+; LINUX-64-STATIC: leaq lsrc+262144(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cam06:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal lsrc+262144(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cam06:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal lsrc+262144(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cam06:
+; LINUX-64-PIC: leaq lsrc(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cam06:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _lsrc+262144(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cam06:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: leal _lsrc+262144(,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cam06:
+; DARWIN-32-PIC: call L129$pb
+; DARWIN-32-PIC-NEXT: L129$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal (_lsrc-L129$pb)+262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cam06:
+; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cam06:
+; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cam06:
+; DARWIN-64-PIC: leaq _lsrc(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cam07(i64 %i) nounwind {
+entry:
+ %0 = add i64 %i, 65536
+ %1 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
+ %2 = bitcast i32* %1 to i8*
+ ret i8* %2
+; LINUX-64-STATIC: cam07:
+; LINUX-64-STATIC: leaq ldst+262144(,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cam07:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: leal ldst+262144(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cam07:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: leal ldst+262144(,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cam07:
+; LINUX-64-PIC: leaq ldst(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cam07:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: leal _ldst+262144(,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cam07:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: leal _ldst+262144(,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cam07:
+; DARWIN-32-PIC: call L130$pb
+; DARWIN-32-PIC-NEXT: L130$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: leal (_ldst-L130$pb)+262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cam07:
+; DARWIN-64-STATIC: leaq _ldst(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cam07:
+; DARWIN-64-DYNAMIC: leaq _ldst(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cam07:
+; DARWIN-64-PIC: leaq _ldst(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define i8* @cam08(i64 %i) nounwind {
+entry:
+ %0 = load i32** @lptr, align 8
+ %1 = add i64 %i, 65536
+ %2 = getelementptr i32* %0, i64 %1
+ %3 = bitcast i32* %2 to i8*
+ ret i8* %3
+; LINUX-64-STATIC: cam08:
+; LINUX-64-STATIC: movq lptr(%rip), %rax
+; LINUX-64-STATIC: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: cam08:
+; LINUX-32-STATIC: movl 4(%esp), %eax
+; LINUX-32-STATIC-NEXT: movl lptr, %ecx
+; LINUX-32-STATIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: cam08:
+; LINUX-32-PIC: movl 4(%esp), %eax
+; LINUX-32-PIC-NEXT: movl lptr, %ecx
+; LINUX-32-PIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: cam08:
+; LINUX-64-PIC: movq lptr(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _cam08:
+; DARWIN-32-STATIC: movl 4(%esp), %eax
+; DARWIN-32-STATIC-NEXT: movl _lptr, %ecx
+; DARWIN-32-STATIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _cam08:
+; DARWIN-32-DYNAMIC: movl 4(%esp), %eax
+; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %ecx
+; DARWIN-32-DYNAMIC-NEXT: leal 262144(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _cam08:
+; DARWIN-32-PIC: call L131$pb
+; DARWIN-32-PIC-NEXT: L131$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx
+; DARWIN-32-PIC-NEXT: movl _lptr-L131$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _cam08:
+; DARWIN-64-STATIC: movq _lptr(%rip), %rax
+; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _cam08:
+; DARWIN-64-DYNAMIC: movq _lptr(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _cam08:
+; DARWIN-64-PIC: movq _lptr(%rip), %rax
+; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @lcallee() nounwind {
+entry:
+ call void @x() nounwind
+ call void @x() nounwind
+ call void @x() nounwind
+ call void @x() nounwind
+ call void @x() nounwind
+ call void @x() nounwind
+ call void @x() nounwind
+ ret void
+; LINUX-64-STATIC: lcallee:
+; LINUX-64-STATIC: callq x
+; LINUX-64-STATIC: callq x
+; LINUX-64-STATIC: callq x
+; LINUX-64-STATIC: callq x
+; LINUX-64-STATIC: callq x
+; LINUX-64-STATIC: callq x
+; LINUX-64-STATIC: callq x
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: lcallee:
+; LINUX-32-STATIC: subl $4, %esp
+; LINUX-32-STATIC-NEXT: call x
+; LINUX-32-STATIC-NEXT: call x
+; LINUX-32-STATIC-NEXT: call x
+; LINUX-32-STATIC-NEXT: call x
+; LINUX-32-STATIC-NEXT: call x
+; LINUX-32-STATIC-NEXT: call x
+; LINUX-32-STATIC-NEXT: call x
+; LINUX-32-STATIC-NEXT: addl $4, %esp
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: lcallee:
+; LINUX-32-PIC: subl $4, %esp
+; LINUX-32-PIC-NEXT: call x
+; LINUX-32-PIC-NEXT: call x
+; LINUX-32-PIC-NEXT: call x
+; LINUX-32-PIC-NEXT: call x
+; LINUX-32-PIC-NEXT: call x
+; LINUX-32-PIC-NEXT: call x
+; LINUX-32-PIC-NEXT: call x
+; LINUX-32-PIC-NEXT: addl $4, %esp
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: lcallee:
+; LINUX-64-PIC: subq $8, %rsp
+; LINUX-64-PIC-NEXT: callq x@PLT
+; LINUX-64-PIC-NEXT: callq x@PLT
+; LINUX-64-PIC-NEXT: callq x@PLT
+; LINUX-64-PIC-NEXT: callq x@PLT
+; LINUX-64-PIC-NEXT: callq x@PLT
+; LINUX-64-PIC-NEXT: callq x@PLT
+; LINUX-64-PIC-NEXT: callq x@PLT
+; LINUX-64-PIC-NEXT: addq $8, %rsp
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _lcallee:
+; DARWIN-32-STATIC: subl $12, %esp
+; DARWIN-32-STATIC-NEXT: call _x
+; DARWIN-32-STATIC-NEXT: call _x
+; DARWIN-32-STATIC-NEXT: call _x
+; DARWIN-32-STATIC-NEXT: call _x
+; DARWIN-32-STATIC-NEXT: call _x
+; DARWIN-32-STATIC-NEXT: call _x
+; DARWIN-32-STATIC-NEXT: call _x
+; DARWIN-32-STATIC-NEXT: addl $12, %esp
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _lcallee:
+; DARWIN-32-DYNAMIC: subl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: call L_x$stub
+; DARWIN-32-DYNAMIC-NEXT: call L_x$stub
+; DARWIN-32-DYNAMIC-NEXT: call L_x$stub
+; DARWIN-32-DYNAMIC-NEXT: call L_x$stub
+; DARWIN-32-DYNAMIC-NEXT: call L_x$stub
+; DARWIN-32-DYNAMIC-NEXT: call L_x$stub
+; DARWIN-32-DYNAMIC-NEXT: call L_x$stub
+; DARWIN-32-DYNAMIC-NEXT: addl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _lcallee:
+; DARWIN-32-PIC: subl $12, %esp
+; DARWIN-32-PIC-NEXT: call L_x$stub
+; DARWIN-32-PIC-NEXT: call L_x$stub
+; DARWIN-32-PIC-NEXT: call L_x$stub
+; DARWIN-32-PIC-NEXT: call L_x$stub
+; DARWIN-32-PIC-NEXT: call L_x$stub
+; DARWIN-32-PIC-NEXT: call L_x$stub
+; DARWIN-32-PIC-NEXT: call L_x$stub
+; DARWIN-32-PIC-NEXT: addl $12, %esp
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _lcallee:
+; DARWIN-64-STATIC: subq $8, %rsp
+; DARWIN-64-STATIC-NEXT: callq _x
+; DARWIN-64-STATIC-NEXT: callq _x
+; DARWIN-64-STATIC-NEXT: callq _x
+; DARWIN-64-STATIC-NEXT: callq _x
+; DARWIN-64-STATIC-NEXT: callq _x
+; DARWIN-64-STATIC-NEXT: callq _x
+; DARWIN-64-STATIC-NEXT: callq _x
+; DARWIN-64-STATIC-NEXT: addq $8, %rsp
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _lcallee:
+; DARWIN-64-DYNAMIC: subq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: callq _x
+; DARWIN-64-DYNAMIC-NEXT: callq _x
+; DARWIN-64-DYNAMIC-NEXT: callq _x
+; DARWIN-64-DYNAMIC-NEXT: callq _x
+; DARWIN-64-DYNAMIC-NEXT: callq _x
+; DARWIN-64-DYNAMIC-NEXT: callq _x
+; DARWIN-64-DYNAMIC-NEXT: callq _x
+; DARWIN-64-DYNAMIC-NEXT: addq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _lcallee:
+; DARWIN-64-PIC: subq $8, %rsp
+; DARWIN-64-PIC-NEXT: callq _x
+; DARWIN-64-PIC-NEXT: callq _x
+; DARWIN-64-PIC-NEXT: callq _x
+; DARWIN-64-PIC-NEXT: callq _x
+; DARWIN-64-PIC-NEXT: callq _x
+; DARWIN-64-PIC-NEXT: callq _x
+; DARWIN-64-PIC-NEXT: callq _x
+; DARWIN-64-PIC-NEXT: addq $8, %rsp
+; DARWIN-64-PIC-NEXT: ret
+}
+
+declare void @x()
+
+define internal void @dcallee() nounwind {
+entry:
+ call void @y() nounwind
+ call void @y() nounwind
+ call void @y() nounwind
+ call void @y() nounwind
+ call void @y() nounwind
+ call void @y() nounwind
+ call void @y() nounwind
+ ret void
+; LINUX-64-STATIC: dcallee:
+; LINUX-64-STATIC: callq y
+; LINUX-64-STATIC: callq y
+; LINUX-64-STATIC: callq y
+; LINUX-64-STATIC: callq y
+; LINUX-64-STATIC: callq y
+; LINUX-64-STATIC: callq y
+; LINUX-64-STATIC: callq y
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: dcallee:
+; LINUX-32-STATIC: subl $4, %esp
+; LINUX-32-STATIC-NEXT: call y
+; LINUX-32-STATIC-NEXT: call y
+; LINUX-32-STATIC-NEXT: call y
+; LINUX-32-STATIC-NEXT: call y
+; LINUX-32-STATIC-NEXT: call y
+; LINUX-32-STATIC-NEXT: call y
+; LINUX-32-STATIC-NEXT: call y
+; LINUX-32-STATIC-NEXT: addl $4, %esp
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: dcallee:
+; LINUX-32-PIC: subl $4, %esp
+; LINUX-32-PIC-NEXT: call y
+; LINUX-32-PIC-NEXT: call y
+; LINUX-32-PIC-NEXT: call y
+; LINUX-32-PIC-NEXT: call y
+; LINUX-32-PIC-NEXT: call y
+; LINUX-32-PIC-NEXT: call y
+; LINUX-32-PIC-NEXT: call y
+; LINUX-32-PIC-NEXT: addl $4, %esp
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: dcallee:
+; LINUX-64-PIC: subq $8, %rsp
+; LINUX-64-PIC-NEXT: callq y@PLT
+; LINUX-64-PIC-NEXT: callq y@PLT
+; LINUX-64-PIC-NEXT: callq y@PLT
+; LINUX-64-PIC-NEXT: callq y@PLT
+; LINUX-64-PIC-NEXT: callq y@PLT
+; LINUX-64-PIC-NEXT: callq y@PLT
+; LINUX-64-PIC-NEXT: callq y@PLT
+; LINUX-64-PIC-NEXT: addq $8, %rsp
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _dcallee:
+; DARWIN-32-STATIC: subl $12, %esp
+; DARWIN-32-STATIC-NEXT: call _y
+; DARWIN-32-STATIC-NEXT: call _y
+; DARWIN-32-STATIC-NEXT: call _y
+; DARWIN-32-STATIC-NEXT: call _y
+; DARWIN-32-STATIC-NEXT: call _y
+; DARWIN-32-STATIC-NEXT: call _y
+; DARWIN-32-STATIC-NEXT: call _y
+; DARWIN-32-STATIC-NEXT: addl $12, %esp
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _dcallee:
+; DARWIN-32-DYNAMIC: subl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: call L_y$stub
+; DARWIN-32-DYNAMIC-NEXT: call L_y$stub
+; DARWIN-32-DYNAMIC-NEXT: call L_y$stub
+; DARWIN-32-DYNAMIC-NEXT: call L_y$stub
+; DARWIN-32-DYNAMIC-NEXT: call L_y$stub
+; DARWIN-32-DYNAMIC-NEXT: call L_y$stub
+; DARWIN-32-DYNAMIC-NEXT: call L_y$stub
+; DARWIN-32-DYNAMIC-NEXT: addl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _dcallee:
+; DARWIN-32-PIC: subl $12, %esp
+; DARWIN-32-PIC-NEXT: call L_y$stub
+; DARWIN-32-PIC-NEXT: call L_y$stub
+; DARWIN-32-PIC-NEXT: call L_y$stub
+; DARWIN-32-PIC-NEXT: call L_y$stub
+; DARWIN-32-PIC-NEXT: call L_y$stub
+; DARWIN-32-PIC-NEXT: call L_y$stub
+; DARWIN-32-PIC-NEXT: call L_y$stub
+; DARWIN-32-PIC-NEXT: addl $12, %esp
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _dcallee:
+; DARWIN-64-STATIC: subq $8, %rsp
+; DARWIN-64-STATIC-NEXT: callq _y
+; DARWIN-64-STATIC-NEXT: callq _y
+; DARWIN-64-STATIC-NEXT: callq _y
+; DARWIN-64-STATIC-NEXT: callq _y
+; DARWIN-64-STATIC-NEXT: callq _y
+; DARWIN-64-STATIC-NEXT: callq _y
+; DARWIN-64-STATIC-NEXT: callq _y
+; DARWIN-64-STATIC-NEXT: addq $8, %rsp
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _dcallee:
+; DARWIN-64-DYNAMIC: subq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: callq _y
+; DARWIN-64-DYNAMIC-NEXT: callq _y
+; DARWIN-64-DYNAMIC-NEXT: callq _y
+; DARWIN-64-DYNAMIC-NEXT: callq _y
+; DARWIN-64-DYNAMIC-NEXT: callq _y
+; DARWIN-64-DYNAMIC-NEXT: callq _y
+; DARWIN-64-DYNAMIC-NEXT: callq _y
+; DARWIN-64-DYNAMIC-NEXT: addq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _dcallee:
+; DARWIN-64-PIC: subq $8, %rsp
+; DARWIN-64-PIC-NEXT: callq _y
+; DARWIN-64-PIC-NEXT: callq _y
+; DARWIN-64-PIC-NEXT: callq _y
+; DARWIN-64-PIC-NEXT: callq _y
+; DARWIN-64-PIC-NEXT: callq _y
+; DARWIN-64-PIC-NEXT: callq _y
+; DARWIN-64-PIC-NEXT: callq _y
+; DARWIN-64-PIC-NEXT: addq $8, %rsp
+; DARWIN-64-PIC-NEXT: ret
+}
+
+declare void @y()
+
+define void ()* @address() nounwind {
+entry:
+ ret void ()* @callee
+; LINUX-64-STATIC: address:
+; LINUX-64-STATIC: movl $callee, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: address:
+; LINUX-32-STATIC: movl $callee, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: address:
+; LINUX-32-PIC: movl $callee, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: address:
+; LINUX-64-PIC: movq callee@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _address:
+; DARWIN-32-STATIC: movl $_callee, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _address:
+; DARWIN-32-DYNAMIC: movl L_callee$non_lazy_ptr, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _address:
+; DARWIN-32-PIC: call L134$pb
+; DARWIN-32-PIC-NEXT: L134$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_callee$non_lazy_ptr-L134$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _address:
+; DARWIN-64-STATIC: movq _callee@GOTPCREL(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _address:
+; DARWIN-64-DYNAMIC: movq _callee@GOTPCREL(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _address:
+; DARWIN-64-PIC: movq _callee@GOTPCREL(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+declare void @callee()
+
+define void ()* @laddress() nounwind {
+entry:
+ ret void ()* @lcallee
+; LINUX-64-STATIC: laddress:
+; LINUX-64-STATIC: movl $lcallee, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: laddress:
+; LINUX-32-STATIC: movl $lcallee, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: laddress:
+; LINUX-32-PIC: movl $lcallee, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: laddress:
+; LINUX-64-PIC: movq lcallee@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _laddress:
+; DARWIN-32-STATIC: movl $_lcallee, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _laddress:
+; DARWIN-32-DYNAMIC: movl $_lcallee, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _laddress:
+; DARWIN-32-PIC: call L135$pb
+; DARWIN-32-PIC-NEXT: L135$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal _lcallee-L135$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _laddress:
+; DARWIN-64-STATIC: leaq _lcallee(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _laddress:
+; DARWIN-64-DYNAMIC: leaq _lcallee(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _laddress:
+; DARWIN-64-PIC: leaq _lcallee(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void ()* @daddress() nounwind {
+entry:
+ ret void ()* @dcallee
+; LINUX-64-STATIC: daddress:
+; LINUX-64-STATIC: movl $dcallee, %eax
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: daddress:
+; LINUX-32-STATIC: movl $dcallee, %eax
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: daddress:
+; LINUX-32-PIC: movl $dcallee, %eax
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: daddress:
+; LINUX-64-PIC: leaq dcallee(%rip), %rax
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _daddress:
+; DARWIN-32-STATIC: movl $_dcallee, %eax
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _daddress:
+; DARWIN-32-DYNAMIC: movl $_dcallee, %eax
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _daddress:
+; DARWIN-32-PIC: call L136$pb
+; DARWIN-32-PIC-NEXT: L136$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: leal _dcallee-L136$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _daddress:
+; DARWIN-64-STATIC: leaq _dcallee(%rip), %rax
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _daddress:
+; DARWIN-64-DYNAMIC: leaq _dcallee(%rip), %rax
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _daddress:
+; DARWIN-64-PIC: leaq _dcallee(%rip), %rax
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @caller() nounwind {
+entry:
+ call void @callee() nounwind
+ call void @callee() nounwind
+ ret void
+; LINUX-64-STATIC: caller:
+; LINUX-64-STATIC: callq callee
+; LINUX-64-STATIC: callq callee
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: caller:
+; LINUX-32-STATIC: subl $4, %esp
+; LINUX-32-STATIC-NEXT: call callee
+; LINUX-32-STATIC-NEXT: call callee
+; LINUX-32-STATIC-NEXT: addl $4, %esp
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: caller:
+; LINUX-32-PIC: subl $4, %esp
+; LINUX-32-PIC-NEXT: call callee
+; LINUX-32-PIC-NEXT: call callee
+; LINUX-32-PIC-NEXT: addl $4, %esp
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: caller:
+; LINUX-64-PIC: subq $8, %rsp
+; LINUX-64-PIC-NEXT: callq callee@PLT
+; LINUX-64-PIC-NEXT: callq callee@PLT
+; LINUX-64-PIC-NEXT: addq $8, %rsp
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _caller:
+; DARWIN-32-STATIC: subl $12, %esp
+; DARWIN-32-STATIC-NEXT: call _callee
+; DARWIN-32-STATIC-NEXT: call _callee
+; DARWIN-32-STATIC-NEXT: addl $12, %esp
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _caller:
+; DARWIN-32-DYNAMIC: subl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: call L_callee$stub
+; DARWIN-32-DYNAMIC-NEXT: call L_callee$stub
+; DARWIN-32-DYNAMIC-NEXT: addl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _caller:
+; DARWIN-32-PIC: subl $12, %esp
+; DARWIN-32-PIC-NEXT: call L_callee$stub
+; DARWIN-32-PIC-NEXT: call L_callee$stub
+; DARWIN-32-PIC-NEXT: addl $12, %esp
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _caller:
+; DARWIN-64-STATIC: subq $8, %rsp
+; DARWIN-64-STATIC-NEXT: callq _callee
+; DARWIN-64-STATIC-NEXT: callq _callee
+; DARWIN-64-STATIC-NEXT: addq $8, %rsp
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _caller:
+; DARWIN-64-DYNAMIC: subq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: callq _callee
+; DARWIN-64-DYNAMIC-NEXT: callq _callee
+; DARWIN-64-DYNAMIC-NEXT: addq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _caller:
+; DARWIN-64-PIC: subq $8, %rsp
+; DARWIN-64-PIC-NEXT: callq _callee
+; DARWIN-64-PIC-NEXT: callq _callee
+; DARWIN-64-PIC-NEXT: addq $8, %rsp
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @dcaller() nounwind {
+entry:
+ call void @dcallee() nounwind
+ call void @dcallee() nounwind
+ ret void
+; LINUX-64-STATIC: dcaller:
+; LINUX-64-STATIC: callq dcallee
+; LINUX-64-STATIC: callq dcallee
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: dcaller:
+; LINUX-32-STATIC: subl $4, %esp
+; LINUX-32-STATIC-NEXT: call dcallee
+; LINUX-32-STATIC-NEXT: call dcallee
+; LINUX-32-STATIC-NEXT: addl $4, %esp
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: dcaller:
+; LINUX-32-PIC: subl $4, %esp
+; LINUX-32-PIC-NEXT: call dcallee
+; LINUX-32-PIC-NEXT: call dcallee
+; LINUX-32-PIC-NEXT: addl $4, %esp
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: dcaller:
+; LINUX-64-PIC: subq $8, %rsp
+; LINUX-64-PIC-NEXT: callq dcallee
+; LINUX-64-PIC-NEXT: callq dcallee
+; LINUX-64-PIC-NEXT: addq $8, %rsp
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _dcaller:
+; DARWIN-32-STATIC: subl $12, %esp
+; DARWIN-32-STATIC-NEXT: call _dcallee
+; DARWIN-32-STATIC-NEXT: call _dcallee
+; DARWIN-32-STATIC-NEXT: addl $12, %esp
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _dcaller:
+; DARWIN-32-DYNAMIC: subl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: call _dcallee
+; DARWIN-32-DYNAMIC-NEXT: call _dcallee
+; DARWIN-32-DYNAMIC-NEXT: addl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _dcaller:
+; DARWIN-32-PIC: subl $12, %esp
+; DARWIN-32-PIC-NEXT: call _dcallee
+; DARWIN-32-PIC-NEXT: call _dcallee
+; DARWIN-32-PIC-NEXT: addl $12, %esp
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _dcaller:
+; DARWIN-64-STATIC: subq $8, %rsp
+; DARWIN-64-STATIC-NEXT: callq _dcallee
+; DARWIN-64-STATIC-NEXT: callq _dcallee
+; DARWIN-64-STATIC-NEXT: addq $8, %rsp
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _dcaller:
+; DARWIN-64-DYNAMIC: subq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: callq _dcallee
+; DARWIN-64-DYNAMIC-NEXT: callq _dcallee
+; DARWIN-64-DYNAMIC-NEXT: addq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _dcaller:
+; DARWIN-64-PIC: subq $8, %rsp
+; DARWIN-64-PIC-NEXT: callq _dcallee
+; DARWIN-64-PIC-NEXT: callq _dcallee
+; DARWIN-64-PIC-NEXT: addq $8, %rsp
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @lcaller() nounwind {
+entry:
+ call void @lcallee() nounwind
+ call void @lcallee() nounwind
+ ret void
+; LINUX-64-STATIC: lcaller:
+; LINUX-64-STATIC: callq lcallee
+; LINUX-64-STATIC: callq lcallee
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: lcaller:
+; LINUX-32-STATIC: subl $4, %esp
+; LINUX-32-STATIC-NEXT: call lcallee
+; LINUX-32-STATIC-NEXT: call lcallee
+; LINUX-32-STATIC-NEXT: addl $4, %esp
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: lcaller:
+; LINUX-32-PIC: subl $4, %esp
+; LINUX-32-PIC-NEXT: call lcallee
+; LINUX-32-PIC-NEXT: call lcallee
+; LINUX-32-PIC-NEXT: addl $4, %esp
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: lcaller:
+; LINUX-64-PIC: subq $8, %rsp
+; LINUX-64-PIC-NEXT: callq lcallee@PLT
+; LINUX-64-PIC-NEXT: callq lcallee@PLT
+; LINUX-64-PIC-NEXT: addq $8, %rsp
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _lcaller:
+; DARWIN-32-STATIC: subl $12, %esp
+; DARWIN-32-STATIC-NEXT: call _lcallee
+; DARWIN-32-STATIC-NEXT: call _lcallee
+; DARWIN-32-STATIC-NEXT: addl $12, %esp
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _lcaller:
+; DARWIN-32-DYNAMIC: subl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: call _lcallee
+; DARWIN-32-DYNAMIC-NEXT: call _lcallee
+; DARWIN-32-DYNAMIC-NEXT: addl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _lcaller:
+; DARWIN-32-PIC: subl $12, %esp
+; DARWIN-32-PIC-NEXT: call _lcallee
+; DARWIN-32-PIC-NEXT: call _lcallee
+; DARWIN-32-PIC-NEXT: addl $12, %esp
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _lcaller:
+; DARWIN-64-STATIC: subq $8, %rsp
+; DARWIN-64-STATIC-NEXT: callq _lcallee
+; DARWIN-64-STATIC-NEXT: callq _lcallee
+; DARWIN-64-STATIC-NEXT: addq $8, %rsp
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _lcaller:
+; DARWIN-64-DYNAMIC: subq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: callq _lcallee
+; DARWIN-64-DYNAMIC-NEXT: callq _lcallee
+; DARWIN-64-DYNAMIC-NEXT: addq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _lcaller:
+; DARWIN-64-PIC: subq $8, %rsp
+; DARWIN-64-PIC-NEXT: callq _lcallee
+; DARWIN-64-PIC-NEXT: callq _lcallee
+; DARWIN-64-PIC-NEXT: addq $8, %rsp
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @tailcaller() nounwind {
+entry:
+ call void @callee() nounwind
+ ret void
+; LINUX-64-STATIC: tailcaller:
+; LINUX-64-STATIC: callq callee
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: tailcaller:
+; LINUX-32-STATIC: subl $4, %esp
+; LINUX-32-STATIC-NEXT: call callee
+; LINUX-32-STATIC-NEXT: addl $4, %esp
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: tailcaller:
+; LINUX-32-PIC: subl $4, %esp
+; LINUX-32-PIC-NEXT: call callee
+; LINUX-32-PIC-NEXT: addl $4, %esp
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: tailcaller:
+; LINUX-64-PIC: subq $8, %rsp
+; LINUX-64-PIC-NEXT: callq callee@PLT
+; LINUX-64-PIC-NEXT: addq $8, %rsp
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _tailcaller:
+; DARWIN-32-STATIC: subl $12, %esp
+; DARWIN-32-STATIC-NEXT: call _callee
+; DARWIN-32-STATIC-NEXT: addl $12, %esp
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _tailcaller:
+; DARWIN-32-DYNAMIC: subl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: call L_callee$stub
+; DARWIN-32-DYNAMIC-NEXT: addl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _tailcaller:
+; DARWIN-32-PIC: subl $12, %esp
+; DARWIN-32-PIC-NEXT: call L_callee$stub
+; DARWIN-32-PIC-NEXT: addl $12, %esp
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _tailcaller:
+; DARWIN-64-STATIC: subq $8, %rsp
+; DARWIN-64-STATIC-NEXT: callq _callee
+; DARWIN-64-STATIC-NEXT: addq $8, %rsp
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _tailcaller:
+; DARWIN-64-DYNAMIC: subq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: callq _callee
+; DARWIN-64-DYNAMIC-NEXT: addq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _tailcaller:
+; DARWIN-64-PIC: subq $8, %rsp
+; DARWIN-64-PIC-NEXT: callq _callee
+; DARWIN-64-PIC-NEXT: addq $8, %rsp
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @dtailcaller() nounwind {
+entry:
+ call void @dcallee() nounwind
+ ret void
+; LINUX-64-STATIC: dtailcaller:
+; LINUX-64-STATIC: callq dcallee
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: dtailcaller:
+; LINUX-32-STATIC: subl $4, %esp
+; LINUX-32-STATIC-NEXT: call dcallee
+; LINUX-32-STATIC-NEXT: addl $4, %esp
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: dtailcaller:
+; LINUX-32-PIC: subl $4, %esp
+; LINUX-32-PIC-NEXT: call dcallee
+; LINUX-32-PIC-NEXT: addl $4, %esp
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: dtailcaller:
+; LINUX-64-PIC: subq $8, %rsp
+; LINUX-64-PIC-NEXT: callq dcallee
+; LINUX-64-PIC-NEXT: addq $8, %rsp
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _dtailcaller:
+; DARWIN-32-STATIC: subl $12, %esp
+; DARWIN-32-STATIC-NEXT: call _dcallee
+; DARWIN-32-STATIC-NEXT: addl $12, %esp
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _dtailcaller:
+; DARWIN-32-DYNAMIC: subl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: call _dcallee
+; DARWIN-32-DYNAMIC-NEXT: addl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _dtailcaller:
+; DARWIN-32-PIC: subl $12, %esp
+; DARWIN-32-PIC-NEXT: call _dcallee
+; DARWIN-32-PIC-NEXT: addl $12, %esp
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _dtailcaller:
+; DARWIN-64-STATIC: subq $8, %rsp
+; DARWIN-64-STATIC-NEXT: callq _dcallee
+; DARWIN-64-STATIC-NEXT: addq $8, %rsp
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _dtailcaller:
+; DARWIN-64-DYNAMIC: subq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: callq _dcallee
+; DARWIN-64-DYNAMIC-NEXT: addq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _dtailcaller:
+; DARWIN-64-PIC: subq $8, %rsp
+; DARWIN-64-PIC-NEXT: callq _dcallee
+; DARWIN-64-PIC-NEXT: addq $8, %rsp
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @ltailcaller() nounwind {
+entry:
+ call void @lcallee() nounwind
+ ret void
+; LINUX-64-STATIC: ltailcaller:
+; LINUX-64-STATIC: callq lcallee
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: ltailcaller:
+; LINUX-32-STATIC: subl $4, %esp
+; LINUX-32-STATIC-NEXT: call lcallee
+; LINUX-32-STATIC-NEXT: addl $4, %esp
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: ltailcaller:
+; LINUX-32-PIC: subl $4, %esp
+; LINUX-32-PIC-NEXT: call lcallee
+; LINUX-32-PIC-NEXT: addl $4, %esp
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: ltailcaller:
+; LINUX-64-PIC: subq $8, %rsp
+; LINUX-64-PIC-NEXT: callq lcallee@PLT
+; LINUX-64-PIC-NEXT: addq $8, %rsp
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _ltailcaller:
+; DARWIN-32-STATIC: subl $12, %esp
+; DARWIN-32-STATIC-NEXT: call _lcallee
+; DARWIN-32-STATIC-NEXT: addl $12, %esp
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _ltailcaller:
+; DARWIN-32-DYNAMIC: subl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: call _lcallee
+; DARWIN-32-DYNAMIC-NEXT: addl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _ltailcaller:
+; DARWIN-32-PIC: subl $12, %esp
+; DARWIN-32-PIC-NEXT: call _lcallee
+; DARWIN-32-PIC-NEXT: addl $12, %esp
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _ltailcaller:
+; DARWIN-64-STATIC: subq $8, %rsp
+; DARWIN-64-STATIC-NEXT: callq _lcallee
+; DARWIN-64-STATIC-NEXT: addq $8, %rsp
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _ltailcaller:
+; DARWIN-64-DYNAMIC: subq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: callq _lcallee
+; DARWIN-64-DYNAMIC-NEXT: addq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _ltailcaller:
+; DARWIN-64-PIC: subq $8, %rsp
+; DARWIN-64-PIC-NEXT: callq _lcallee
+; DARWIN-64-PIC-NEXT: addq $8, %rsp
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @icaller() nounwind {
+entry:
+ %0 = load void ()** @ifunc, align 8
+ call void %0() nounwind
+ %1 = load void ()** @ifunc, align 8
+ call void %1() nounwind
+ ret void
+; LINUX-64-STATIC: icaller:
+; LINUX-64-STATIC: callq *ifunc
+; LINUX-64-STATIC: callq *ifunc
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: icaller:
+; LINUX-32-STATIC: subl $4, %esp
+; LINUX-32-STATIC-NEXT: call *ifunc
+; LINUX-32-STATIC-NEXT: call *ifunc
+; LINUX-32-STATIC-NEXT: addl $4, %esp
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: icaller:
+; LINUX-32-PIC: subl $4, %esp
+; LINUX-32-PIC-NEXT: call *ifunc
+; LINUX-32-PIC-NEXT: call *ifunc
+; LINUX-32-PIC-NEXT: addl $4, %esp
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: icaller:
+; LINUX-64-PIC: pushq %rbx
+; LINUX-64-PIC-NEXT: movq ifunc@GOTPCREL(%rip), %rbx
+; LINUX-64-PIC-NEXT: callq *(%rbx)
+; LINUX-64-PIC-NEXT: callq *(%rbx)
+; LINUX-64-PIC-NEXT: popq %rbx
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _icaller:
+; DARWIN-32-STATIC: subl $12, %esp
+; DARWIN-32-STATIC-NEXT: call *_ifunc
+; DARWIN-32-STATIC-NEXT: call *_ifunc
+; DARWIN-32-STATIC-NEXT: addl $12, %esp
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _icaller:
+; DARWIN-32-DYNAMIC: pushl %esi
+; DARWIN-32-DYNAMIC-NEXT: subl $8, %esp
+; DARWIN-32-DYNAMIC-NEXT: movl L_ifunc$non_lazy_ptr, %esi
+; DARWIN-32-DYNAMIC-NEXT: call *(%esi)
+; DARWIN-32-DYNAMIC-NEXT: call *(%esi)
+; DARWIN-32-DYNAMIC-NEXT: addl $8, %esp
+; DARWIN-32-DYNAMIC-NEXT: popl %esi
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _icaller:
+; DARWIN-32-PIC: pushl %esi
+; DARWIN-32-PIC-NEXT: subl $8, %esp
+; DARWIN-32-PIC-NEXT: call L143$pb
+; DARWIN-32-PIC-NEXT: L143$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L143$pb(%eax), %esi
+; DARWIN-32-PIC-NEXT: call *(%esi)
+; DARWIN-32-PIC-NEXT: call *(%esi)
+; DARWIN-32-PIC-NEXT: addl $8, %esp
+; DARWIN-32-PIC-NEXT: popl %esi
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _icaller:
+; DARWIN-64-STATIC: pushq %rbx
+; DARWIN-64-STATIC-NEXT: movq _ifunc@GOTPCREL(%rip), %rbx
+; DARWIN-64-STATIC-NEXT: callq *(%rbx)
+; DARWIN-64-STATIC-NEXT: callq *(%rbx)
+; DARWIN-64-STATIC-NEXT: popq %rbx
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _icaller:
+; DARWIN-64-DYNAMIC: pushq %rbx
+; DARWIN-64-DYNAMIC-NEXT: movq _ifunc@GOTPCREL(%rip), %rbx
+; DARWIN-64-DYNAMIC-NEXT: callq *(%rbx)
+; DARWIN-64-DYNAMIC-NEXT: callq *(%rbx)
+; DARWIN-64-DYNAMIC-NEXT: popq %rbx
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _icaller:
+; DARWIN-64-PIC: pushq %rbx
+; DARWIN-64-PIC-NEXT: movq _ifunc@GOTPCREL(%rip), %rbx
+; DARWIN-64-PIC-NEXT: callq *(%rbx)
+; DARWIN-64-PIC-NEXT: callq *(%rbx)
+; DARWIN-64-PIC-NEXT: popq %rbx
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @dicaller() nounwind {
+entry:
+ %0 = load void ()** @difunc, align 8
+ call void %0() nounwind
+ %1 = load void ()** @difunc, align 8
+ call void %1() nounwind
+ ret void
+; LINUX-64-STATIC: dicaller:
+; LINUX-64-STATIC: callq *difunc
+; LINUX-64-STATIC: callq *difunc
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: dicaller:
+; LINUX-32-STATIC: subl $4, %esp
+; LINUX-32-STATIC-NEXT: call *difunc
+; LINUX-32-STATIC-NEXT: call *difunc
+; LINUX-32-STATIC-NEXT: addl $4, %esp
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: dicaller:
+; LINUX-32-PIC: subl $4, %esp
+; LINUX-32-PIC-NEXT: call *difunc
+; LINUX-32-PIC-NEXT: call *difunc
+; LINUX-32-PIC-NEXT: addl $4, %esp
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: dicaller:
+; LINUX-64-PIC: pushq %rbx
+; LINUX-64-PIC-NEXT: movq difunc@GOTPCREL(%rip), %rbx
+; LINUX-64-PIC-NEXT: callq *(%rbx)
+; LINUX-64-PIC-NEXT: callq *(%rbx)
+; LINUX-64-PIC-NEXT: popq %rbx
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _dicaller:
+; DARWIN-32-STATIC: subl $12, %esp
+; DARWIN-32-STATIC-NEXT: call *_difunc
+; DARWIN-32-STATIC-NEXT: call *_difunc
+; DARWIN-32-STATIC-NEXT: addl $12, %esp
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _dicaller:
+; DARWIN-32-DYNAMIC: subl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: call *_difunc
+; DARWIN-32-DYNAMIC-NEXT: call *_difunc
+; DARWIN-32-DYNAMIC-NEXT: addl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _dicaller:
+; DARWIN-32-PIC: pushl %esi
+; DARWIN-32-PIC-NEXT: subl $8, %esp
+; DARWIN-32-PIC-NEXT: call L144$pb
+; DARWIN-32-PIC-NEXT: L144$pb:
+; DARWIN-32-PIC-NEXT: popl %esi
+; DARWIN-32-PIC-NEXT: call *_difunc-L144$pb(%esi)
+; DARWIN-32-PIC-NEXT: call *_difunc-L144$pb(%esi)
+; DARWIN-32-PIC-NEXT: addl $8, %esp
+; DARWIN-32-PIC-NEXT: popl %esi
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _dicaller:
+; DARWIN-64-STATIC: subq $8, %rsp
+; DARWIN-64-STATIC-NEXT: callq *_difunc(%rip)
+; DARWIN-64-STATIC-NEXT: callq *_difunc(%rip)
+; DARWIN-64-STATIC-NEXT: addq $8, %rsp
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _dicaller:
+; DARWIN-64-DYNAMIC: subq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: callq *_difunc(%rip)
+; DARWIN-64-DYNAMIC-NEXT: callq *_difunc(%rip)
+; DARWIN-64-DYNAMIC-NEXT: addq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _dicaller:
+; DARWIN-64-PIC: subq $8, %rsp
+; DARWIN-64-PIC-NEXT: callq *_difunc(%rip)
+; DARWIN-64-PIC-NEXT: callq *_difunc(%rip)
+; DARWIN-64-PIC-NEXT: addq $8, %rsp
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @licaller() nounwind {
+entry:
+ %0 = load void ()** @lifunc, align 8
+ call void %0() nounwind
+ %1 = load void ()** @lifunc, align 8
+ call void %1() nounwind
+ ret void
+; LINUX-64-STATIC: licaller:
+; LINUX-64-STATIC: callq *lifunc
+; LINUX-64-STATIC: callq *lifunc
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: licaller:
+; LINUX-32-STATIC: subl $4, %esp
+; LINUX-32-STATIC-NEXT: call *lifunc
+; LINUX-32-STATIC-NEXT: call *lifunc
+; LINUX-32-STATIC-NEXT: addl $4, %esp
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: licaller:
+; LINUX-32-PIC: subl $4, %esp
+; LINUX-32-PIC-NEXT: call *lifunc
+; LINUX-32-PIC-NEXT: call *lifunc
+; LINUX-32-PIC-NEXT: addl $4, %esp
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: licaller:
+; LINUX-64-PIC: subq $8, %rsp
+; LINUX-64-PIC-NEXT: callq *lifunc(%rip)
+; LINUX-64-PIC-NEXT: callq *lifunc(%rip)
+; LINUX-64-PIC-NEXT: addq $8, %rsp
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _licaller:
+; DARWIN-32-STATIC: subl $12, %esp
+; DARWIN-32-STATIC-NEXT: call *_lifunc
+; DARWIN-32-STATIC-NEXT: call *_lifunc
+; DARWIN-32-STATIC-NEXT: addl $12, %esp
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _licaller:
+; DARWIN-32-DYNAMIC: subl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: call *_lifunc
+; DARWIN-32-DYNAMIC-NEXT: call *_lifunc
+; DARWIN-32-DYNAMIC-NEXT: addl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _licaller:
+; DARWIN-32-PIC: pushl %esi
+; DARWIN-32-PIC-NEXT: subl $8, %esp
+; DARWIN-32-PIC-NEXT: call L145$pb
+; DARWIN-32-PIC-NEXT: L145$pb:
+; DARWIN-32-PIC-NEXT: popl %esi
+; DARWIN-32-PIC-NEXT: call *_lifunc-L145$pb(%esi)
+; DARWIN-32-PIC-NEXT: call *_lifunc-L145$pb(%esi)
+; DARWIN-32-PIC-NEXT: addl $8, %esp
+; DARWIN-32-PIC-NEXT: popl %esi
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _licaller:
+; DARWIN-64-STATIC: subq $8, %rsp
+; DARWIN-64-STATIC-NEXT: callq *_lifunc(%rip)
+; DARWIN-64-STATIC-NEXT: callq *_lifunc(%rip)
+; DARWIN-64-STATIC-NEXT: addq $8, %rsp
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _licaller:
+; DARWIN-64-DYNAMIC: subq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: callq *_lifunc(%rip)
+; DARWIN-64-DYNAMIC-NEXT: callq *_lifunc(%rip)
+; DARWIN-64-DYNAMIC-NEXT: addq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _licaller:
+; DARWIN-64-PIC: subq $8, %rsp
+; DARWIN-64-PIC-NEXT: callq *_lifunc(%rip)
+; DARWIN-64-PIC-NEXT: callq *_lifunc(%rip)
+; DARWIN-64-PIC-NEXT: addq $8, %rsp
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @itailcaller() nounwind {
+entry:
+ %0 = load void ()** @ifunc, align 8
+ call void %0() nounwind
+ %1 = load void ()** @ifunc, align 8
+ call void %1() nounwind
+ ret void
+; LINUX-64-STATIC: itailcaller:
+; LINUX-64-STATIC: callq *ifunc
+; LINUX-64-STATIC: callq *ifunc
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: itailcaller:
+; LINUX-32-STATIC: subl $4, %esp
+; LINUX-32-STATIC-NEXT: call *ifunc
+; LINUX-32-STATIC-NEXT: call *ifunc
+; LINUX-32-STATIC-NEXT: addl $4, %esp
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: itailcaller:
+; LINUX-32-PIC: subl $4, %esp
+; LINUX-32-PIC-NEXT: call *ifunc
+; LINUX-32-PIC-NEXT: call *ifunc
+; LINUX-32-PIC-NEXT: addl $4, %esp
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: itailcaller:
+; LINUX-64-PIC: pushq %rbx
+; LINUX-64-PIC-NEXT: movq ifunc@GOTPCREL(%rip), %rbx
+; LINUX-64-PIC-NEXT: callq *(%rbx)
+; LINUX-64-PIC-NEXT: callq *(%rbx)
+; LINUX-64-PIC-NEXT: popq %rbx
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _itailcaller:
+; DARWIN-32-STATIC: subl $12, %esp
+; DARWIN-32-STATIC-NEXT: call *_ifunc
+; DARWIN-32-STATIC-NEXT: call *_ifunc
+; DARWIN-32-STATIC-NEXT: addl $12, %esp
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _itailcaller:
+; DARWIN-32-DYNAMIC: pushl %esi
+; DARWIN-32-DYNAMIC-NEXT: subl $8, %esp
+; DARWIN-32-DYNAMIC-NEXT: movl L_ifunc$non_lazy_ptr, %esi
+; DARWIN-32-DYNAMIC-NEXT: call *(%esi)
+; DARWIN-32-DYNAMIC-NEXT: call *(%esi)
+; DARWIN-32-DYNAMIC-NEXT: addl $8, %esp
+; DARWIN-32-DYNAMIC-NEXT: popl %esi
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _itailcaller:
+; DARWIN-32-PIC: pushl %esi
+; DARWIN-32-PIC-NEXT: subl $8, %esp
+; DARWIN-32-PIC-NEXT: call L146$pb
+; DARWIN-32-PIC-NEXT: L146$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L146$pb(%eax), %esi
+; DARWIN-32-PIC-NEXT: call *(%esi)
+; DARWIN-32-PIC-NEXT: call *(%esi)
+; DARWIN-32-PIC-NEXT: addl $8, %esp
+; DARWIN-32-PIC-NEXT: popl %esi
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _itailcaller:
+; DARWIN-64-STATIC: pushq %rbx
+; DARWIN-64-STATIC-NEXT: movq _ifunc@GOTPCREL(%rip), %rbx
+; DARWIN-64-STATIC-NEXT: callq *(%rbx)
+; DARWIN-64-STATIC-NEXT: callq *(%rbx)
+; DARWIN-64-STATIC-NEXT: popq %rbx
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _itailcaller:
+; DARWIN-64-DYNAMIC: pushq %rbx
+; DARWIN-64-DYNAMIC-NEXT: movq _ifunc@GOTPCREL(%rip), %rbx
+; DARWIN-64-DYNAMIC-NEXT: callq *(%rbx)
+; DARWIN-64-DYNAMIC-NEXT: callq *(%rbx)
+; DARWIN-64-DYNAMIC-NEXT: popq %rbx
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _itailcaller:
+; DARWIN-64-PIC: pushq %rbx
+; DARWIN-64-PIC-NEXT: movq _ifunc@GOTPCREL(%rip), %rbx
+; DARWIN-64-PIC-NEXT: callq *(%rbx)
+; DARWIN-64-PIC-NEXT: callq *(%rbx)
+; DARWIN-64-PIC-NEXT: popq %rbx
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @ditailcaller() nounwind {
+entry:
+ %0 = load void ()** @difunc, align 8
+ call void %0() nounwind
+ ret void
+; LINUX-64-STATIC: ditailcaller:
+; LINUX-64-STATIC: callq *difunc
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: ditailcaller:
+; LINUX-32-STATIC: subl $4, %esp
+; LINUX-32-STATIC-NEXT: call *difunc
+; LINUX-32-STATIC-NEXT: addl $4, %esp
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: ditailcaller:
+; LINUX-32-PIC: subl $4, %esp
+; LINUX-32-PIC-NEXT: call *difunc
+; LINUX-32-PIC-NEXT: addl $4, %esp
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: ditailcaller:
+; LINUX-64-PIC: subq $8, %rsp
+; LINUX-64-PIC-NEXT: movq difunc@GOTPCREL(%rip), %rax
+; LINUX-64-PIC-NEXT: callq *(%rax)
+; LINUX-64-PIC-NEXT: addq $8, %rsp
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _ditailcaller:
+; DARWIN-32-STATIC: subl $12, %esp
+; DARWIN-32-STATIC-NEXT: call *_difunc
+; DARWIN-32-STATIC-NEXT: addl $12, %esp
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _ditailcaller:
+; DARWIN-32-DYNAMIC: subl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: call *_difunc
+; DARWIN-32-DYNAMIC-NEXT: addl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _ditailcaller:
+; DARWIN-32-PIC: subl $12, %esp
+; DARWIN-32-PIC-NEXT: call L147$pb
+; DARWIN-32-PIC-NEXT: L147$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: call *_difunc-L147$pb(%eax)
+; DARWIN-32-PIC-NEXT: addl $12, %esp
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _ditailcaller:
+; DARWIN-64-STATIC: subq $8, %rsp
+; DARWIN-64-STATIC-NEXT: callq *_difunc(%rip)
+; DARWIN-64-STATIC-NEXT: addq $8, %rsp
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _ditailcaller:
+; DARWIN-64-DYNAMIC: subq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: callq *_difunc(%rip)
+; DARWIN-64-DYNAMIC-NEXT: addq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _ditailcaller:
+; DARWIN-64-PIC: callq *_difunc(%rip)
+; DARWIN-64-PIC-NEXT: addq $8, %rsp
+; DARWIN-64-PIC-NEXT: ret
+}
+
+define void @litailcaller() nounwind {
+entry:
+ %0 = load void ()** @lifunc, align 8
+ call void %0() nounwind
+ ret void
+; LINUX-64-STATIC: litailcaller:
+; LINUX-64-STATIC: callq *lifunc
+; LINUX-64-STATIC: ret
+
+; LINUX-32-STATIC: litailcaller:
+; LINUX-32-STATIC: subl $4, %esp
+; LINUX-32-STATIC-NEXT: call *lifunc
+; LINUX-32-STATIC-NEXT: addl $4, %esp
+; LINUX-32-STATIC-NEXT: ret
+
+; LINUX-32-PIC: litailcaller:
+; LINUX-32-PIC: subl $4, %esp
+; LINUX-32-PIC-NEXT: call *lifunc
+; LINUX-32-PIC-NEXT: addl $4, %esp
+; LINUX-32-PIC-NEXT: ret
+
+; LINUX-64-PIC: litailcaller:
+; LINUX-64-PIC: subq $8, %rsp
+; LINUX-64-PIC-NEXT: callq *lifunc(%rip)
+; LINUX-64-PIC-NEXT: addq $8, %rsp
+; LINUX-64-PIC-NEXT: ret
+
+; DARWIN-32-STATIC: _litailcaller:
+; DARWIN-32-STATIC: subl $12, %esp
+; DARWIN-32-STATIC-NEXT: call *_lifunc
+; DARWIN-32-STATIC-NEXT: addl $12, %esp
+; DARWIN-32-STATIC-NEXT: ret
+
+; DARWIN-32-DYNAMIC: _litailcaller:
+; DARWIN-32-DYNAMIC: subl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: call *_lifunc
+; DARWIN-32-DYNAMIC-NEXT: addl $12, %esp
+; DARWIN-32-DYNAMIC-NEXT: ret
+
+; DARWIN-32-PIC: _litailcaller:
+; DARWIN-32-PIC: subl $12, %esp
+; DARWIN-32-PIC-NEXT: call L148$pb
+; DARWIN-32-PIC-NEXT: L148$pb:
+; DARWIN-32-PIC-NEXT: popl %eax
+; DARWIN-32-PIC-NEXT: call *_lifunc-L148$pb(%eax)
+; DARWIN-32-PIC-NEXT: addl $12, %esp
+; DARWIN-32-PIC-NEXT: ret
+
+; DARWIN-64-STATIC: _litailcaller:
+; DARWIN-64-STATIC: subq $8, %rsp
+; DARWIN-64-STATIC-NEXT: callq *_lifunc(%rip)
+; DARWIN-64-STATIC-NEXT: addq $8, %rsp
+; DARWIN-64-STATIC-NEXT: ret
+
+; DARWIN-64-DYNAMIC: _litailcaller:
+; DARWIN-64-DYNAMIC: subq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: callq *_lifunc(%rip)
+; DARWIN-64-DYNAMIC-NEXT: addq $8, %rsp
+; DARWIN-64-DYNAMIC-NEXT: ret
+
+; DARWIN-64-PIC: _litailcaller:
+; DARWIN-64-PIC: subq $8, %rsp
+; DARWIN-64-PIC-NEXT: callq *_lifunc(%rip)
+; DARWIN-64-PIC-NEXT: addq $8, %rsp
+; DARWIN-64-PIC-NEXT: ret
+}
diff --git a/test/CodeGen/X86/add.ll b/test/CodeGen/X86/add.ll
new file mode 100644
index 0000000..3991a68
--- /dev/null
+++ b/test/CodeGen/X86/add.ll
@@ -0,0 +1,94 @@
+; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X64
+
+; The immediate can be encoded in a smaller way if the
+; instruction is a sub instead of an add.
+
+define i32 @test1(i32 inreg %a) nounwind {
+ %b = add i32 %a, 128
+ ret i32 %b
+; X32: subl $-128, %eax
+; X64: subl $-128,
+}
+define i64 @test2(i64 inreg %a) nounwind {
+ %b = add i64 %a, 2147483648
+ ret i64 %b
+; X32: addl $-2147483648, %eax
+; X64: subq $-2147483648,
+}
+define i64 @test3(i64 inreg %a) nounwind {
+ %b = add i64 %a, 128
+ ret i64 %b
+
+; X32: addl $128, %eax
+; X64: subq $-128,
+}
+
+define i1 @test4(i32 %v1, i32 %v2, i32* %X) nounwind {
+entry:
+ %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
+ %sum = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %overflow, label %normal
+
+normal:
+ store i32 0, i32* %X
+ br label %overflow
+
+overflow:
+ ret i1 false
+
+; X32: test4:
+; X32: addl
+; X32-NEXT: jo
+
+; X64: test4:
+; X64: addl %esi, %edi
+; X64-NEXT: jo
+}
+
+define i1 @test5(i32 %v1, i32 %v2, i32* %X) nounwind {
+entry:
+ %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
+ %sum = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %carry, label %normal
+
+normal:
+ store i32 0, i32* %X
+ br label %carry
+
+carry:
+ ret i1 false
+
+; X32: test5:
+; X32: addl
+; X32-NEXT: jb
+
+; X64: test5:
+; X64: addl %esi, %edi
+; X64-NEXT: jb
+}
+
+declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32)
+declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32)
+
+
+define i64 @test6(i64 %A, i32 %B) nounwind {
+ %tmp12 = zext i32 %B to i64 ; <i64> [#uses=1]
+ %tmp3 = shl i64 %tmp12, 32 ; <i64> [#uses=1]
+ %tmp5 = add i64 %tmp3, %A ; <i64> [#uses=1]
+ ret i64 %tmp5
+
+; X32: test6:
+; X32: movl 12(%esp), %edx
+; X32-NEXT: addl 8(%esp), %edx
+; X32-NEXT: movl 4(%esp), %eax
+; X32-NEXT: ret
+
+; X64: test6:
+; X64: shlq $32, %rsi
+; X64: leaq (%rsi,%rdi), %rax
+; X64: ret
+}
+
diff --git a/test/CodeGen/X86/addr-label-difference.ll b/test/CodeGen/X86/addr-label-difference.ll
new file mode 100644
index 0000000..547d6b5
--- /dev/null
+++ b/test/CodeGen/X86/addr-label-difference.ll
@@ -0,0 +1,22 @@
+; RUN: llc %s -o - | grep {__TEXT,__const}
+; PR5929
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
+target triple = "i386-apple-darwin10.0"
+
+; This array should go into the __TEXT,__const section, not into the
+; __DATA,__const section, because the elements don't need relocations.
[email protected] = internal constant [3 x i32] [i32 sub (i32 ptrtoint (i8* blockaddress(@test, %foo) to i32), i32 ptrtoint (i8* blockaddress(@test, %foo) to i32)), i32 sub (i32 ptrtoint (i8* blockaddress(@test, %bar) to i32), i32 ptrtoint (i8* blockaddress(@test, %foo) to i32)), i32 sub (i32 ptrtoint (i8* blockaddress(@test, %hack) to i32), i32 ptrtoint (i8* blockaddress(@test, %foo) to i32))] ; <[3 x i32]*> [#uses=1]
+
+define void @test(i32 %i) nounwind ssp {
+entry:
+ br label %foo
+
+foo: ; preds = %indirectgoto, %indirectgoto, %indirectgoto, %indirectgoto, %indirectgoto
+ br label %bar
+
+bar: ; preds = %foo, %indirectgoto
+ br label %hack
+
+hack: ; preds = %bar, %indirectgoto
+ ret void
+}
diff --git a/test/CodeGen/X86/aliases.ll b/test/CodeGen/X86/aliases.ll
new file mode 100644
index 0000000..3020eb3
--- /dev/null
+++ b/test/CodeGen/X86/aliases.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu -asm-verbose=false -o %t
+; RUN: grep { = } %t | count 7
+; RUN: grep set %t | count 16
+; RUN: grep globl %t | count 6
+; RUN: grep weak %t | count 1
+; RUN: grep hidden %t | count 1
+; RUN: grep protected %t | count 1
+
+@bar = external global i32
+@foo1 = alias i32* @bar
+@foo2 = alias i32* @bar
+
+%FunTy = type i32()
+
+declare i32 @foo_f()
+@bar_f = alias weak %FunTy* @foo_f
+
+@bar_i = alias internal i32* @bar
+
+@A = alias bitcast (i32* @bar to i64*)
+
+@bar_h = hidden alias i32* @bar
+
+@bar_p = protected alias i32* @bar
+
+define i32 @test() {
+entry:
+ %tmp = load i32* @foo1
+ %tmp1 = load i32* @foo2
+ %tmp0 = load i32* @bar_i
+ %tmp2 = call i32 @foo_f()
+ %tmp3 = add i32 %tmp, %tmp2
+ %tmp4 = call %FunTy* @bar_f()
+ %tmp5 = add i32 %tmp3, %tmp4
+ %tmp6 = add i32 %tmp1, %tmp5
+ %tmp7 = add i32 %tmp6, %tmp0
+ ret i32 %tmp7
+}
diff --git a/test/CodeGen/X86/aligned-comm.ll b/test/CodeGen/X86/aligned-comm.ll
new file mode 100644
index 0000000..7715869
--- /dev/null
+++ b/test/CodeGen/X86/aligned-comm.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -mtriple=i386-apple-darwin10 | grep {array,16512,7}
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | grep {array,16512,7}
+
+; Darwin 9+ should get alignment on common symbols.
+@array = common global [4128 x i32] zeroinitializer, align 128
diff --git a/test/CodeGen/X86/all-ones-vector.ll b/test/CodeGen/X86/all-ones-vector.ll
new file mode 100644
index 0000000..10fecad
--- /dev/null
+++ b/test/CodeGen/X86/all-ones-vector.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 -mattr=sse2 | grep pcmpeqd | count 4
+
+define <4 x i32> @ioo() nounwind {
+ ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
+}
+define <2 x i64> @loo() nounwind {
+ ret <2 x i64> <i64 -1, i64 -1>
+}
+define <2 x double> @doo() nounwind {
+ ret <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff>
+}
+define <4 x float> @foo() nounwind {
+ ret <4 x float> <float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000, float 0xffffffffe0000000>
+}
diff --git a/test/CodeGen/X86/alloca-align-rounding.ll b/test/CodeGen/X86/alloca-align-rounding.ll
new file mode 100644
index 0000000..f45e9b8
--- /dev/null
+++ b/test/CodeGen/X86/alloca-align-rounding.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin | grep and | count 1
+; RUN: llc < %s -march=x86-64 -mtriple=i686-pc-linux | grep and | count 1
+
+declare void @bar(<2 x i64>* %n)
+
+define void @foo(i32 %h) {
+ %p = alloca <2 x i64>, i32 %h
+ call void @bar(<2 x i64>* %p)
+ ret void
+}
+
+define void @foo2(i32 %h) {
+ %p = alloca <2 x i64>, i32 %h, align 32
+ call void @bar(<2 x i64>* %p)
+ ret void
+}
diff --git a/test/CodeGen/X86/and-or-fold.ll b/test/CodeGen/X86/and-or-fold.ll
new file mode 100644
index 0000000..7733b8a5
--- /dev/null
+++ b/test/CodeGen/X86/and-or-fold.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 | grep and | count 1
+
+; The dag combiner should fold together (x&127)|(y&16711680) -> (x|y)&c1
+; in this case.
+
+define i32 @test6(i32 %x, i16 %y) {
+ %tmp1 = zext i16 %y to i32 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 127 ; <i32> [#uses=1]
+ %tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
+ %tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
+ %tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
+ ret i32 %tmp6
+}
+
diff --git a/test/CodeGen/X86/and-su.ll b/test/CodeGen/X86/and-su.ll
new file mode 100644
index 0000000..38db88a
--- /dev/null
+++ b/test/CodeGen/X86/and-su.ll
@@ -0,0 +1,53 @@
+; RUN: llc < %s -march=x86 | FileCheck %s
+
+; Don't duplicate the load.
+
+define fastcc i32 @foo(i32* %p) nounwind {
+; CHECK: foo:
+; CHECK: andl $10, %eax
+; CHECK: je
+ %t0 = load i32* %p
+ %t2 = and i32 %t0, 10
+ %t3 = icmp ne i32 %t2, 0
+ br i1 %t3, label %bb63, label %bb76
+bb63:
+ ret i32 %t2
+bb76:
+ ret i32 0
+}
+
+define fastcc double @bar(i32 %hash, double %x, double %y) nounwind {
+entry:
+; CHECK: bar:
+ %0 = and i32 %hash, 15
+ %1 = icmp ult i32 %0, 8
+ br i1 %1, label %bb11, label %bb10
+
+bb10:
+; CHECK: bb10
+; CHECK: testb $1
+ %2 = and i32 %hash, 1
+ %3 = icmp eq i32 %2, 0
+ br i1 %3, label %bb13, label %bb11
+
+bb11:
+ %4 = fsub double -0.000000e+00, %x
+ br label %bb13
+
+bb13:
+; CHECK: bb13
+; CHECK: testb $2
+ %iftmp.9.0 = phi double [ %4, %bb11 ], [ %x, %bb10 ]
+ %5 = and i32 %hash, 2
+ %6 = icmp eq i32 %5, 0
+ br i1 %6, label %bb16, label %bb14
+
+bb14:
+ %7 = fsub double -0.000000e+00, %y
+ br label %bb16
+
+bb16:
+ %iftmp.10.0 = phi double [ %7, %bb14 ], [ %y, %bb13 ]
+ %8 = fadd double %iftmp.9.0, %iftmp.10.0
+ ret double %8
+}
diff --git a/test/CodeGen/X86/anyext.ll b/test/CodeGen/X86/anyext.ll
new file mode 100644
index 0000000..106fe83
--- /dev/null
+++ b/test/CodeGen/X86/anyext.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86-64 | grep movzbl | count 2
+
+; Use movzbl to avoid partial-register updates.
+
+define i32 @foo(i32 %p, i8 zeroext %x) nounwind {
+ %q = trunc i32 %p to i8
+ %r = udiv i8 %q, %x
+ %s = zext i8 %r to i32
+ %t = and i32 %s, 1
+ ret i32 %t
+}
+define i32 @bar(i32 %p, i16 zeroext %x) nounwind {
+ %q = trunc i32 %p to i16
+ %r = udiv i16 %q, %x
+ %s = zext i16 %r to i32
+ %t = and i32 %s, 1
+ ret i32 %t
+}
diff --git a/test/CodeGen/X86/arg-cast.ll b/test/CodeGen/X86/arg-cast.ll
new file mode 100644
index 0000000..c111514
--- /dev/null
+++ b/test/CodeGen/X86/arg-cast.ll
@@ -0,0 +1,18 @@
+; This should compile to movl $2147483647, %eax + andl only.
+; RUN: llc < %s | grep andl
+; RUN: llc < %s | not grep movsd
+; RUN: llc < %s | grep esp | not grep add
+; rdar://5736574
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin8"
+
+define i32 @foo(double %x) nounwind {
+entry:
+ %x15 = bitcast double %x to i64 ; <i64> [#uses=1]
+ %tmp713 = lshr i64 %x15, 32 ; <i64> [#uses=1]
+ %tmp714 = trunc i64 %tmp713 to i32 ; <i32> [#uses=1]
+ %tmp8 = and i32 %tmp714, 2147483647 ; <i32> [#uses=1]
+ ret i32 %tmp8
+}
+
diff --git a/test/CodeGen/X86/asm-block-labels.ll b/test/CodeGen/X86/asm-block-labels.ll
new file mode 100644
index 0000000..a43d430
--- /dev/null
+++ b/test/CodeGen/X86/asm-block-labels.ll
@@ -0,0 +1,41 @@
+; RUN: opt < %s -std-compile-opts | llc
+; ModuleID = 'block12.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin8"
+
+define void @bar() {
+entry:
+ br label %"LASM$foo"
+
+"LASM$foo": ; preds = %entry
+ call void asm sideeffect ".file \22block12.c\22", "~{dirflag},~{fpsr},~{flags}"( )
+ call void asm sideeffect ".line 1", "~{dirflag},~{fpsr},~{flags}"( )
+ call void asm sideeffect "int $$1", "~{dirflag},~{fpsr},~{flags},~{memory}"( )
+ call void asm sideeffect ".file \22block12.c\22", "~{dirflag},~{fpsr},~{flags}"( )
+ call void asm sideeffect ".line 2", "~{dirflag},~{fpsr},~{flags}"( )
+ call void asm sideeffect "brl ${0:l}", "X,~{dirflag},~{fpsr},~{flags},~{memory}"( label %"LASM$foo" )
+ br label %return
+
+return: ; preds = %"LASM$foo"
+ ret void
+}
+
+define void @baz() {
+entry:
+ call void asm sideeffect ".file \22block12.c\22", "~{dirflag},~{fpsr},~{flags}"( )
+ call void asm sideeffect ".line 3", "~{dirflag},~{fpsr},~{flags}"( )
+ call void asm sideeffect "brl ${0:l}", "X,~{dirflag},~{fpsr},~{flags},~{memory}"( label %"LASM$foo" )
+ call void asm sideeffect ".file \22block12.c\22", "~{dirflag},~{fpsr},~{flags}"( )
+ call void asm sideeffect ".line 4", "~{dirflag},~{fpsr},~{flags}"( )
+ call void asm sideeffect "int $$1", "~{dirflag},~{fpsr},~{flags},~{memory}"( )
+ br label %"LASM$foo"
+
+"LASM$foo": ; preds = %entry
+ call void asm sideeffect ".file \22block12.c\22", "~{dirflag},~{fpsr},~{flags}"( )
+ call void asm sideeffect ".line 5", "~{dirflag},~{fpsr},~{flags}"( )
+ call void asm sideeffect "int $$1", "~{dirflag},~{fpsr},~{flags},~{memory}"( )
+ br label %return
+
+return: ; preds = %"LASM$foo"
+ ret void
+}
diff --git a/test/CodeGen/X86/asm-global-imm.ll b/test/CodeGen/X86/asm-global-imm.ll
new file mode 100644
index 0000000..96da224
--- /dev/null
+++ b/test/CodeGen/X86/asm-global-imm.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86 -relocation-model=static | \
+; RUN: grep {test1 \$_GV}
+; RUN: llc < %s -march=x86 -relocation-model=static | \
+; RUN: grep {test2 _GV}
+; PR882
+
+target datalayout = "e-p:32:32"
+target triple = "i686-apple-darwin9.0.0d2"
+@GV = weak global i32 0 ; <i32*> [#uses=2]
+@str = external global [12 x i8] ; <[12 x i8]*> [#uses=1]
+
+define void @foo() {
+entry:
+ tail call void asm sideeffect "test1 $0", "i,~{dirflag},~{fpsr},~{flags}"( i32* @GV )
+ tail call void asm sideeffect "test2 ${0:c}", "i,~{dirflag},~{fpsr},~{flags}"( i32* @GV )
+ ret void
+}
+
+define void @unknown_bootoption() {
+entry:
+ call void asm sideeffect "ud2\0A\09.word ${0:c}\0A\09.long ${1:c}\0A", "i,i,~{dirflag},~{fpsr},~{flags}"( i32 235, i8* getelementptr ([12 x i8]* @str, i32 0, i64 0) )
+ ret void
+}
diff --git a/test/CodeGen/X86/asm-indirect-mem.ll b/test/CodeGen/X86/asm-indirect-mem.ll
new file mode 100644
index 0000000..c57aa99
--- /dev/null
+++ b/test/CodeGen/X86/asm-indirect-mem.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+; PR2267
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+
+define void @atomic_store_rel_int(i32* %p, i32 %v) nounwind {
+entry:
+ %asmtmp = tail call i32 asm sideeffect "xchgl $1,$0", "=*m,=r,*m,1,~{dirflag},~{fpsr},~{flags}"( i32* %p, i32* %p, i32 %v ) nounwind ; <i32> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/X86/asm-modifier-P.ll b/test/CodeGen/X86/asm-modifier-P.ll
new file mode 100644
index 0000000..6139da8
--- /dev/null
+++ b/test/CodeGen/X86/asm-modifier-P.ll
@@ -0,0 +1,79 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-unknown-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC-32
+; RUN: llc < %s -march=x86 -mtriple=i686-unknown-linux-gnu -relocation-model=static | FileCheck %s -check-prefix=CHECK-STATIC-32
+; RUN: llc < %s -march=x86-64 -relocation-model=static | FileCheck %s -check-prefix=CHECK-STATIC-64
+; RUN: llc < %s -march=x86-64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC-64
+; PR3379
+; XFAIL: *
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+@G = external global i32 ; <i32*> [#uses=1]
+
+declare void @bar(...)
+
+; extern int G;
+; void test1() {
+; asm("frob %0 x" : : "m"(G));
+; asm("frob %P0 x" : : "m"(G));
+;}
+
+define void @test1() nounwind {
+entry:
+; P suffix removes (rip) in -static 64-bit mode.
+
+; CHECK-PIC-64: test1:
+; CHECK-PIC-64: movq G@GOTPCREL(%rip), %rax
+; CHECK-PIC-64: frob (%rax) x
+; CHECK-PIC-64: frob (%rax) x
+
+; CHECK-STATIC-64: test1:
+; CHECK-STATIC-64: frob G(%rip) x
+; CHECK-STATIC-64: frob G x
+
+; CHECK-PIC-32: test1:
+; CHECK-PIC-32: frob G x
+; CHECK-PIC-32: frob G x
+
+; CHECK-STATIC-32: test1:
+; CHECK-STATIC-32: frob G x
+; CHECK-STATIC-32: frob G x
+
+ call void asm "frob $0 x", "*m"(i32* @G) nounwind
+ call void asm "frob ${0:P} x", "*m"(i32* @G) nounwind
+ ret void
+}
+
+define void @test3() nounwind {
+entry:
+; CHECK-STATIC-64: test3:
+; CHECK-STATIC-64: call bar
+; CHECK-STATIC-64: call test3
+; CHECK-STATIC-64: call $bar
+; CHECK-STATIC-64: call $test3
+
+; CHECK-STATIC-32: test3:
+; CHECK-STATIC-32: call bar
+; CHECK-STATIC-32: call test3
+; CHECK-STATIC-32: call $bar
+; CHECK-STATIC-32: call $test3
+
+; CHECK-PIC-64: test3:
+; CHECK-PIC-64: call bar@PLT
+; CHECK-PIC-64: call test3@PLT
+; CHECK-PIC-64: call $bar
+; CHECK-PIC-64: call $test3
+
+; CHECK-PIC-32: test3:
+; CHECK-PIC-32: call bar@PLT
+; CHECK-PIC-32: call test3@PLT
+; CHECK-PIC-32: call $bar
+; CHECK-PIC-32: call $test3
+
+
+; asm(" blah %P0" : : "X"(bar));
+ tail call void asm sideeffect "call ${0:P}", "X"(void (...)* @bar) nounwind
+ tail call void asm sideeffect "call ${0:P}", "X"(void (...)* bitcast (void ()* @test3 to void (...)*)) nounwind
+ tail call void asm sideeffect "call $0", "X"(void (...)* @bar) nounwind
+ tail call void asm sideeffect "call $0", "X"(void (...)* bitcast (void ()* @test3 to void (...)*)) nounwind
+ ret void
+}
diff --git a/test/CodeGen/X86/asm-modifier.ll b/test/CodeGen/X86/asm-modifier.ll
new file mode 100644
index 0000000..44f972e
--- /dev/null
+++ b/test/CodeGen/X86/asm-modifier.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s | FileCheck %s
+; ModuleID = 'asm.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.6"
+
+define i32 @test1() nounwind {
+entry:
+; CHECK: test1:
+; CHECK: movw %gs:6, %ax
+ %asmtmp.i = tail call i16 asm "movw\09%gs:${1:a}, ${0:w}", "=r,ir,~{dirflag},~{fpsr},~{flags}"(i32 6) nounwind ; <i16> [#uses=1]
+ %0 = zext i16 %asmtmp.i to i32 ; <i32> [#uses=1]
+ ret i32 %0
+}
+
+define zeroext i16 @test2(i32 %address) nounwind {
+entry:
+; CHECK: test2:
+; CHECK: movw %gs:(%eax), %ax
+ %asmtmp = tail call i16 asm "movw\09%gs:${1:a}, ${0:w}", "=r,ir,~{dirflag},~{fpsr},~{flags}"(i32 %address) nounwind ; <i16> [#uses=1]
+ ret i16 %asmtmp
+}
+
+@n = global i32 42 ; <i32*> [#uses=3]
+@y = common global i32 0 ; <i32*> [#uses=3]
+
+define void @test3() nounwind {
+entry:
+; CHECK: test3:
+; CHECK: movl _n, %eax
+ call void asm sideeffect "movl ${0:a}, %eax", "ir,~{dirflag},~{fpsr},~{flags},~{eax}"(i32* @n) nounwind
+ ret void
+}
+
+define void @test4() nounwind {
+entry:
+; CHECK: test4:
+; CHECK: movl L_y$non_lazy_ptr, %ecx
+; CHECK: movl (%ecx), %eax
+ call void asm sideeffect "movl ${0:a}, %eax", "ir,~{dirflag},~{fpsr},~{flags},~{eax}"(i32* @y) nounwind
+ ret void
+}
diff --git a/test/CodeGen/X86/atomic_add.ll b/test/CodeGen/X86/atomic_add.ll
new file mode 100644
index 0000000..d00f8e8
--- /dev/null
+++ b/test/CodeGen/X86/atomic_add.ll
@@ -0,0 +1,217 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+; rdar://7103704
+
+define void @sub1(i32* nocapture %p, i32 %v) nounwind ssp {
+entry:
+; CHECK: sub1:
+; CHECK: subl
+ %0 = tail call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %p, i32 %v) ; <i32> [#uses=0]
+ ret void
+}
+
+define void @inc4(i64* nocapture %p) nounwind ssp {
+entry:
+; CHECK: inc4:
+; CHECK: incq
+ %0 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 1) ; <i64> [#uses=0]
+ ret void
+}
+
+declare i64 @llvm.atomic.load.add.i64.p0i64(i64* nocapture, i64) nounwind
+
+define void @add8(i64* nocapture %p) nounwind ssp {
+entry:
+; CHECK: add8:
+; CHECK: addq $2
+ %0 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 2) ; <i64> [#uses=0]
+ ret void
+}
+
+define void @add4(i64* nocapture %p, i32 %v) nounwind ssp {
+entry:
+; CHECK: add4:
+; CHECK: addq
+ %0 = sext i32 %v to i64 ; <i64> [#uses=1]
+ %1 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 %0) ; <i64> [#uses=0]
+ ret void
+}
+
+define void @inc3(i8* nocapture %p) nounwind ssp {
+entry:
+; CHECK: inc3:
+; CHECK: incb
+ %0 = tail call i8 @llvm.atomic.load.add.i8.p0i8(i8* %p, i8 1) ; <i8> [#uses=0]
+ ret void
+}
+
+declare i8 @llvm.atomic.load.add.i8.p0i8(i8* nocapture, i8) nounwind
+
+define void @add7(i8* nocapture %p) nounwind ssp {
+entry:
+; CHECK: add7:
+; CHECK: addb $2
+ %0 = tail call i8 @llvm.atomic.load.add.i8.p0i8(i8* %p, i8 2) ; <i8> [#uses=0]
+ ret void
+}
+
+define void @add3(i8* nocapture %p, i32 %v) nounwind ssp {
+entry:
+; CHECK: add3:
+; CHECK: addb
+ %0 = trunc i32 %v to i8 ; <i8> [#uses=1]
+ %1 = tail call i8 @llvm.atomic.load.add.i8.p0i8(i8* %p, i8 %0) ; <i8> [#uses=0]
+ ret void
+}
+
+define void @inc2(i16* nocapture %p) nounwind ssp {
+entry:
+; CHECK: inc2:
+; CHECK: incw
+ %0 = tail call i16 @llvm.atomic.load.add.i16.p0i16(i16* %p, i16 1) ; <i16> [#uses=0]
+ ret void
+}
+
+declare i16 @llvm.atomic.load.add.i16.p0i16(i16* nocapture, i16) nounwind
+
+define void @add6(i16* nocapture %p) nounwind ssp {
+entry:
+; CHECK: add6:
+; CHECK: addw $2
+ %0 = tail call i16 @llvm.atomic.load.add.i16.p0i16(i16* %p, i16 2) ; <i16> [#uses=0]
+ ret void
+}
+
+define void @add2(i16* nocapture %p, i32 %v) nounwind ssp {
+entry:
+; CHECK: add2:
+; CHECK: addw
+ %0 = trunc i32 %v to i16 ; <i16> [#uses=1]
+ %1 = tail call i16 @llvm.atomic.load.add.i16.p0i16(i16* %p, i16 %0) ; <i16> [#uses=0]
+ ret void
+}
+
+define void @inc1(i32* nocapture %p) nounwind ssp {
+entry:
+; CHECK: inc1:
+; CHECK: incl
+ %0 = tail call i32 @llvm.atomic.load.add.i32.p0i32(i32* %p, i32 1) ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind
+
+define void @add5(i32* nocapture %p) nounwind ssp {
+entry:
+; CHECK: add5:
+; CHECK: addl $2
+ %0 = tail call i32 @llvm.atomic.load.add.i32.p0i32(i32* %p, i32 2) ; <i32> [#uses=0]
+ ret void
+}
+
+define void @add1(i32* nocapture %p, i32 %v) nounwind ssp {
+entry:
+; CHECK: add1:
+; CHECK: addl
+ %0 = tail call i32 @llvm.atomic.load.add.i32.p0i32(i32* %p, i32 %v) ; <i32> [#uses=0]
+ ret void
+}
+
+define void @dec4(i64* nocapture %p) nounwind ssp {
+entry:
+; CHECK: dec4:
+; CHECK: decq
+ %0 = tail call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %p, i64 1) ; <i64> [#uses=0]
+ ret void
+}
+
+declare i64 @llvm.atomic.load.sub.i64.p0i64(i64* nocapture, i64) nounwind
+
+define void @sub8(i64* nocapture %p) nounwind ssp {
+entry:
+; CHECK: sub8:
+; CHECK: subq $2
+ %0 = tail call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %p, i64 2) ; <i64> [#uses=0]
+ ret void
+}
+
+define void @sub4(i64* nocapture %p, i32 %v) nounwind ssp {
+entry:
+; CHECK: sub4:
+; CHECK: subq
+ %0 = sext i32 %v to i64 ; <i64> [#uses=1]
+ %1 = tail call i64 @llvm.atomic.load.sub.i64.p0i64(i64* %p, i64 %0) ; <i64> [#uses=0]
+ ret void
+}
+
+define void @dec3(i8* nocapture %p) nounwind ssp {
+entry:
+; CHECK: dec3:
+; CHECK: decb
+ %0 = tail call i8 @llvm.atomic.load.sub.i8.p0i8(i8* %p, i8 1) ; <i8> [#uses=0]
+ ret void
+}
+
+declare i8 @llvm.atomic.load.sub.i8.p0i8(i8* nocapture, i8) nounwind
+
+define void @sub7(i8* nocapture %p) nounwind ssp {
+entry:
+; CHECK: sub7:
+; CHECK: subb $2
+ %0 = tail call i8 @llvm.atomic.load.sub.i8.p0i8(i8* %p, i8 2) ; <i8> [#uses=0]
+ ret void
+}
+
+define void @sub3(i8* nocapture %p, i32 %v) nounwind ssp {
+entry:
+; CHECK: sub3:
+; CHECK: subb
+ %0 = trunc i32 %v to i8 ; <i8> [#uses=1]
+ %1 = tail call i8 @llvm.atomic.load.sub.i8.p0i8(i8* %p, i8 %0) ; <i8> [#uses=0]
+ ret void
+}
+
+define void @dec2(i16* nocapture %p) nounwind ssp {
+entry:
+; CHECK: dec2:
+; CHECK: decw
+ %0 = tail call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %p, i16 1) ; <i16> [#uses=0]
+ ret void
+}
+
+declare i16 @llvm.atomic.load.sub.i16.p0i16(i16* nocapture, i16) nounwind
+
+define void @sub6(i16* nocapture %p) nounwind ssp {
+entry:
+; CHECK: sub6:
+; CHECK: subw $2
+ %0 = tail call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %p, i16 2) ; <i16> [#uses=0]
+ ret void
+}
+
+define void @sub2(i16* nocapture %p, i32 %v) nounwind ssp {
+entry:
+; CHECK: sub2:
+; CHECK: subw
+ %0 = trunc i32 %v to i16 ; <i16> [#uses=1]
+ %1 = tail call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %p, i16 %0) ; <i16> [#uses=0]
+ ret void
+}
+
+define void @dec1(i32* nocapture %p) nounwind ssp {
+entry:
+; CHECK: dec1:
+; CHECK: decl
+ %0 = tail call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %p, i32 1) ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @llvm.atomic.load.sub.i32.p0i32(i32* nocapture, i32) nounwind
+
+define void @sub5(i32* nocapture %p) nounwind ssp {
+entry:
+; CHECK: sub5:
+; CHECK: subl $2
+ %0 = tail call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %p, i32 2) ; <i32> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/X86/atomic_op.ll b/test/CodeGen/X86/atomic_op.ll
new file mode 100644
index 0000000..3ef1887
--- /dev/null
+++ b/test/CodeGen/X86/atomic_op.ll
@@ -0,0 +1,94 @@
+; RUN: llc < %s -march=x86 -o %t1
+; RUN: grep "lock" %t1 | count 17
+; RUN: grep "xaddl" %t1 | count 4
+; RUN: grep "cmpxchgl" %t1 | count 13
+; RUN: grep "xchgl" %t1 | count 14
+; RUN: grep "cmova" %t1 | count 2
+; RUN: grep "cmovb" %t1 | count 2
+; RUN: grep "cmovg" %t1 | count 2
+; RUN: grep "cmovl" %t1 | count 2
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+
+define void @main(i32 %argc, i8** %argv) {
+entry:
+ %argc.addr = alloca i32 ; <i32*> [#uses=1]
+ %argv.addr = alloca i8** ; <i8***> [#uses=1]
+ %val1 = alloca i32 ; <i32*> [#uses=2]
+ %val2 = alloca i32 ; <i32*> [#uses=15]
+ %andt = alloca i32 ; <i32*> [#uses=2]
+ %ort = alloca i32 ; <i32*> [#uses=2]
+ %xort = alloca i32 ; <i32*> [#uses=2]
+ %old = alloca i32 ; <i32*> [#uses=18]
+ %temp = alloca i32 ; <i32*> [#uses=2]
+ store i32 %argc, i32* %argc.addr
+ store i8** %argv, i8*** %argv.addr
+ store i32 0, i32* %val1
+ store i32 31, i32* %val2
+ store i32 3855, i32* %andt
+ store i32 3855, i32* %ort
+ store i32 3855, i32* %xort
+ store i32 4, i32* %temp
+ %tmp = load i32* %temp ; <i32> [#uses=1]
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val1, i32 %tmp ) ; <i32>:0 [#uses=1]
+ store i32 %0, i32* %old
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 30 ) ; <i32>:1 [#uses=1]
+ store i32 %1, i32* %old
+ call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:2 [#uses=1]
+ store i32 %2, i32* %old
+ call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:3 [#uses=1]
+ store i32 %3, i32* %old
+ call i32 @llvm.atomic.load.and.i32.p0i32( i32* %andt, i32 4080 ) ; <i32>:4 [#uses=1]
+ store i32 %4, i32* %old
+ call i32 @llvm.atomic.load.or.i32.p0i32( i32* %ort, i32 4080 ) ; <i32>:5 [#uses=1]
+ store i32 %5, i32* %old
+ call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %xort, i32 4080 ) ; <i32>:6 [#uses=1]
+ store i32 %6, i32* %old
+ call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 16 ) ; <i32>:7 [#uses=1]
+ store i32 %7, i32* %old
+ %neg = sub i32 0, 1 ; <i32> [#uses=1]
+ call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 %neg ) ; <i32>:8 [#uses=1]
+ store i32 %8, i32* %old
+ call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:9 [#uses=1]
+ store i32 %9, i32* %old
+ call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 0 ) ; <i32>:10 [#uses=1]
+ store i32 %10, i32* %old
+ call i32 @llvm.atomic.load.umax.i32.p0i32( i32* %val2, i32 65535 ) ; <i32>:11 [#uses=1]
+ store i32 %11, i32* %old
+ call i32 @llvm.atomic.load.umax.i32.p0i32( i32* %val2, i32 10 ) ; <i32>:12 [#uses=1]
+ store i32 %12, i32* %old
+ call i32 @llvm.atomic.load.umin.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:13 [#uses=1]
+ store i32 %13, i32* %old
+ call i32 @llvm.atomic.load.umin.i32.p0i32( i32* %val2, i32 10 ) ; <i32>:14 [#uses=1]
+ store i32 %14, i32* %old
+ call i32 @llvm.atomic.swap.i32.p0i32( i32* %val2, i32 1976 ) ; <i32>:15 [#uses=1]
+ store i32 %15, i32* %old
+ %neg1 = sub i32 0, 10 ; <i32> [#uses=1]
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %val2, i32 %neg1, i32 1 ) ; <i32>:16 [#uses=1]
+ store i32 %16, i32* %old
+ call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %val2, i32 1976, i32 1 ) ; <i32>:17 [#uses=1]
+ store i32 %17, i32* %old
+ ret void
+}
+
+declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind
+
+declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind
+
+declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind
+
+declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind
+
+declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind
+
+declare i32 @llvm.atomic.load.min.i32.p0i32(i32*, i32) nounwind
+
+declare i32 @llvm.atomic.load.max.i32.p0i32(i32*, i32) nounwind
+
+declare i32 @llvm.atomic.load.umax.i32.p0i32(i32*, i32) nounwind
+
+declare i32 @llvm.atomic.load.umin.i32.p0i32(i32*, i32) nounwind
+
+declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind
+
+declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind
diff --git a/test/CodeGen/X86/attribute-sections.ll b/test/CodeGen/X86/attribute-sections.ll
new file mode 100644
index 0000000..3035334
--- /dev/null
+++ b/test/CodeGen/X86/attribute-sections.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX
+
+declare i32 @foo()
+@G0 = global i32 ()* @foo, section ".init_array"
+
+; LINUX: .section .init_array,"aw"
+; LINUX: .globl G0
+
+@G1 = global i32 ()* @foo, section ".fini_array"
+
+; LINUX: .section .fini_array,"aw"
+; LINUX: .globl G1
+
+@G2 = global i32 ()* @foo, section ".preinit_array"
+
+; LINUX: .section .preinit_array,"aw"
+; LINUX: .globl G2
+
diff --git a/test/CodeGen/X86/avoid-lea-scale2.ll b/test/CodeGen/X86/avoid-lea-scale2.ll
new file mode 100644
index 0000000..8003de2
--- /dev/null
+++ b/test/CodeGen/X86/avoid-lea-scale2.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86-64 | grep {leal.*-2(\[%\]rdi,\[%\]rdi)}
+
+define i32 @foo(i32 %x) nounwind readnone {
+ %t0 = shl i32 %x, 1
+ %t1 = add i32 %t0, -2
+ ret i32 %t1
+}
+
diff --git a/test/CodeGen/X86/avoid-loop-align-2.ll b/test/CodeGen/X86/avoid-loop-align-2.ll
new file mode 100644
index 0000000..fc9d1f0
--- /dev/null
+++ b/test/CodeGen/X86/avoid-loop-align-2.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=x86 | grep align | count 4
+
+; TODO: Is it a good idea to align inner loops? It's hard to know without
+; knowing what their trip counts are, or other dynamic information. For
+; now, CodeGen aligns all loops.
+
+@x = external global i32* ; <i32**> [#uses=1]
+
+define i32 @t(i32 %a, i32 %b) nounwind readonly ssp {
+entry:
+ %0 = icmp eq i32 %a, 0 ; <i1> [#uses=1]
+ br i1 %0, label %bb5, label %bb.nph12
+
+bb.nph12: ; preds = %entry
+ %1 = icmp eq i32 %b, 0 ; <i1> [#uses=1]
+ %2 = load i32** @x, align 8 ; <i32*> [#uses=1]
+ br i1 %1, label %bb2.preheader, label %bb2.preheader.us
+
+bb2.preheader.us: ; preds = %bb2.bb3_crit_edge.us, %bb.nph12
+ %indvar18 = phi i32 [ 0, %bb.nph12 ], [ %indvar.next19, %bb2.bb3_crit_edge.us ] ; <i32> [#uses=2]
+ %sum.111.us = phi i32 [ 0, %bb.nph12 ], [ %4, %bb2.bb3_crit_edge.us ] ; <i32> [#uses=0]
+ %tmp16 = mul i32 %indvar18, %a ; <i32> [#uses=1]
+ br label %bb1.us
+
+bb1.us: ; preds = %bb1.us, %bb2.preheader.us
+ %indvar = phi i32 [ 0, %bb2.preheader.us ], [ %indvar.next, %bb1.us ] ; <i32> [#uses=2]
+ %tmp17 = add i32 %indvar, %tmp16 ; <i32> [#uses=1]
+ %tmp. = zext i32 %tmp17 to i64 ; <i64> [#uses=1]
+ %3 = getelementptr i32* %2, i64 %tmp. ; <i32*> [#uses=1]
+ %4 = load i32* %3, align 4 ; <i32> [#uses=2]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %b ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb2.bb3_crit_edge.us, label %bb1.us
+
+bb2.bb3_crit_edge.us: ; preds = %bb1.us
+ %indvar.next19 = add i32 %indvar18, 1 ; <i32> [#uses=2]
+ %exitcond22 = icmp eq i32 %indvar.next19, %a ; <i1> [#uses=1]
+ br i1 %exitcond22, label %bb5, label %bb2.preheader.us
+
+bb2.preheader: ; preds = %bb2.preheader, %bb.nph12
+ %indvar24 = phi i32 [ %indvar.next25, %bb2.preheader ], [ 0, %bb.nph12 ] ; <i32> [#uses=1]
+ %indvar.next25 = add i32 %indvar24, 1 ; <i32> [#uses=2]
+ %exitcond28 = icmp eq i32 %indvar.next25, %a ; <i1> [#uses=1]
+ br i1 %exitcond28, label %bb5, label %bb2.preheader
+
+bb5: ; preds = %bb2.preheader, %bb2.bb3_crit_edge.us, %entry
+ %sum.1.lcssa = phi i32 [ 0, %entry ], [ 0, %bb2.preheader ], [ %4, %bb2.bb3_crit_edge.us ] ; <i32> [#uses=1]
+ ret i32 %sum.1.lcssa
+}
diff --git a/test/CodeGen/X86/avoid-loop-align.ll b/test/CodeGen/X86/avoid-loop-align.ll
new file mode 100644
index 0000000..d4c5c672
--- /dev/null
+++ b/test/CodeGen/X86/avoid-loop-align.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
+
+; CodeGen should align the top of the loop, which differs from the loop
+; header in this case.
+
+; CHECK: jmp LBB1_2
+; CHECK: .align
+; CHECK: LBB1_1:
+
+@A = common global [100 x i32] zeroinitializer, align 32 ; <[100 x i32]*> [#uses=1]
+
+define i8* @test(i8* %Q, i32* %L) nounwind {
+entry:
+ %tmp = tail call i32 (...)* @foo() nounwind ; <i32> [#uses=2]
+ %tmp1 = inttoptr i32 %tmp to i8* ; <i8*> [#uses=1]
+ br label %bb1
+
+bb: ; preds = %bb1, %bb1
+ %indvar.next = add i32 %P.0.rec, 1 ; <i32> [#uses=1]
+ br label %bb1
+
+bb1: ; preds = %bb, %entry
+ %P.0.rec = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
+ %P.0 = getelementptr i8* %tmp1, i32 %P.0.rec ; <i8*> [#uses=3]
+ %tmp2 = load i8* %P.0, align 1 ; <i8> [#uses=1]
+ switch i8 %tmp2, label %bb4 [
+ i8 12, label %bb
+ i8 42, label %bb
+ ]
+
+bb4: ; preds = %bb1
+ %tmp3 = ptrtoint i8* %P.0 to i32 ; <i32> [#uses=1]
+ %tmp4 = sub i32 %tmp3, %tmp ; <i32> [#uses=1]
+ %tmp5 = getelementptr [100 x i32]* @A, i32 0, i32 %tmp4 ; <i32*> [#uses=1]
+ store i32 4, i32* %tmp5, align 4
+ ret i8* %P.0
+}
+
+declare i32 @foo(...)
diff --git a/test/CodeGen/X86/bigstructret.ll b/test/CodeGen/X86/bigstructret.ll
new file mode 100644
index 0000000..633995d
--- /dev/null
+++ b/test/CodeGen/X86/bigstructret.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 -o %t
+; RUN: grep "movl .24601, 12(%ecx)" %t
+; RUN: grep "movl .48, 8(%ecx)" %t
+; RUN: grep "movl .24, 4(%ecx)" %t
+; RUN: grep "movl .12, (%ecx)" %t
+
+%0 = type { i32, i32, i32, i32 }
+
+define internal fastcc %0 @ReturnBigStruct() nounwind readnone {
+entry:
+ %0 = insertvalue %0 zeroinitializer, i32 12, 0
+ %1 = insertvalue %0 %0, i32 24, 1
+ %2 = insertvalue %0 %1, i32 48, 2
+ %3 = insertvalue %0 %2, i32 24601, 3
+ ret %0 %3
+}
+
diff --git a/test/CodeGen/X86/bigstructret2.ll b/test/CodeGen/X86/bigstructret2.ll
new file mode 100644
index 0000000..46e0fd2
--- /dev/null
+++ b/test/CodeGen/X86/bigstructret2.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -o %t
+
+%0 = type { i64, i64 }
+
+declare fastcc %0 @ReturnBigStruct() nounwind readnone
+
+define void @test(%0* %p) {
+ %1 = call fastcc %0 @ReturnBigStruct()
+ store %0 %1, %0* %p
+ ret void
+}
+
diff --git a/test/CodeGen/X86/bitcast-int-to-vector.ll b/test/CodeGen/X86/bitcast-int-to-vector.ll
new file mode 100644
index 0000000..4c25979
--- /dev/null
+++ b/test/CodeGen/X86/bitcast-int-to-vector.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86
+
+define i1 @foo(i64 %a)
+{
+ %t = bitcast i64 %a to <2 x float>
+ %r = extractelement <2 x float> %t, i32 0
+ %s = extractelement <2 x float> %t, i32 1
+ %b = fcmp uno float %r, %s
+ ret i1 %b
+}
diff --git a/test/CodeGen/X86/bitcast.ll b/test/CodeGen/X86/bitcast.ll
new file mode 100644
index 0000000..c34c675
--- /dev/null
+++ b/test/CodeGen/X86/bitcast.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86-64
+; PR1033
+
+define i64 @test1(double %t) {
+ %u = bitcast double %t to i64 ; <i64> [#uses=1]
+ ret i64 %u
+}
+
+define double @test2(i64 %t) {
+ %u = bitcast i64 %t to double ; <double> [#uses=1]
+ ret double %u
+}
+
+define i32 @test3(float %t) {
+ %u = bitcast float %t to i32 ; <i32> [#uses=1]
+ ret i32 %u
+}
+
+define float @test4(i32 %t) {
+ %u = bitcast i32 %t to float ; <float> [#uses=1]
+ ret float %u
+}
+
diff --git a/test/CodeGen/X86/bitcast2.ll b/test/CodeGen/X86/bitcast2.ll
new file mode 100644
index 0000000..48922b5
--- /dev/null
+++ b/test/CodeGen/X86/bitcast2.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86-64 | grep movd | count 2
+; RUN: llc < %s -march=x86-64 | not grep rsp
+
+define i64 @test1(double %A) {
+ %B = bitcast double %A to i64
+ ret i64 %B
+}
+
+define double @test2(i64 %A) {
+ %B = bitcast i64 %A to double
+ ret double %B
+}
+
diff --git a/test/CodeGen/X86/br-fold.ll b/test/CodeGen/X86/br-fold.ll
new file mode 100644
index 0000000..8af3bd1
--- /dev/null
+++ b/test/CodeGen/X86/br-fold.ll
@@ -0,0 +1,20 @@
+; RUN: llc -march=x86-64 < %s | FileCheck %s
+
+; CHECK: orq
+; CHECK-NEXT: jne
+
+@_ZN11xercesc_2_513SchemaSymbols21fgURI_SCHEMAFORSCHEMAE = external constant [33 x i16], align 32 ; <[33 x i16]*> [#uses=1]
+@_ZN11xercesc_2_56XMLUni16fgNotationStringE = external constant [9 x i16], align 16 ; <[9 x i16]*> [#uses=1]
+
+define fastcc void @foo() {
+entry:
+ br i1 icmp eq (i64 or (i64 ptrtoint ([33 x i16]* @_ZN11xercesc_2_513SchemaSymbols21fgURI_SCHEMAFORSCHEMAE to i64),
+ i64 ptrtoint ([9 x i16]* @_ZN11xercesc_2_56XMLUni16fgNotationStringE to i64)), i64 0),
+ label %bb8.i329, label %bb4.i.i318.preheader
+
+bb4.i.i318.preheader: ; preds = %bb6
+ unreachable
+
+bb8.i329: ; preds = %bb6
+ unreachable
+}
diff --git a/test/CodeGen/X86/brcond.ll b/test/CodeGen/X86/brcond.ll
new file mode 100644
index 0000000..130483a
--- /dev/null
+++ b/test/CodeGen/X86/brcond.ll
@@ -0,0 +1,69 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s
+; rdar://7475489
+
+define i32 @test1(i32 %a, i32 %b) nounwind ssp {
+entry:
+; CHECK: test1:
+; CHECK: xorb
+; CHECK-NOT: andb
+; CHECK-NOT: shrb
+; CHECK: testb $64
+ %0 = and i32 %a, 16384
+ %1 = icmp ne i32 %0, 0
+ %2 = and i32 %b, 16384
+ %3 = icmp ne i32 %2, 0
+ %4 = xor i1 %1, %3
+ br i1 %4, label %bb1, label %bb
+
+bb: ; preds = %entry
+ %5 = tail call i32 (...)* @foo() nounwind ; <i32> [#uses=1]
+ ret i32 %5
+
+bb1: ; preds = %entry
+ %6 = tail call i32 (...)* @bar() nounwind ; <i32> [#uses=1]
+ ret i32 %6
+}
+
+declare i32 @foo(...)
+
+declare i32 @bar(...)
+
+
+
+; PR3351 - (P == 0) & (Q == 0) -> (P|Q) == 0
+define i32 @test2(i32* %P, i32* %Q) nounwind ssp {
+entry:
+ %a = icmp eq i32* %P, null ; <i1> [#uses=1]
+ %b = icmp eq i32* %Q, null ; <i1> [#uses=1]
+ %c = and i1 %a, %b
+ br i1 %c, label %bb1, label %return
+
+bb1: ; preds = %entry
+ ret i32 4
+
+return: ; preds = %entry
+ ret i32 192
+; CHECK: test2:
+; CHECK: movl 4(%esp), %eax
+; CHECK-NEXT: orl 8(%esp), %eax
+; CHECK-NEXT: jne LBB2_2
+}
+
+; PR3351 - (P != 0) | (Q != 0) -> (P|Q) != 0
+define i32 @test3(i32* %P, i32* %Q) nounwind ssp {
+entry:
+ %a = icmp ne i32* %P, null ; <i1> [#uses=1]
+ %b = icmp ne i32* %Q, null ; <i1> [#uses=1]
+ %c = or i1 %a, %b
+ br i1 %c, label %bb1, label %return
+
+bb1: ; preds = %entry
+ ret i32 4
+
+return: ; preds = %entry
+ ret i32 192
+; CHECK: test3:
+; CHECK: movl 4(%esp), %eax
+; CHECK-NEXT: orl 8(%esp), %eax
+; CHECK-NEXT: je LBB3_2
+}
diff --git a/test/CodeGen/X86/break-anti-dependencies.ll b/test/CodeGen/X86/break-anti-dependencies.ll
new file mode 100644
index 0000000..972b3cd
--- /dev/null
+++ b/test/CodeGen/X86/break-anti-dependencies.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies=none > %t
+; RUN: grep {%xmm0} %t | count 14
+; RUN: not grep {%xmm1} %t
+; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies=critical > %t
+; RUN: grep {%xmm0} %t | count 7
+; RUN: grep {%xmm1} %t | count 7
+
+define void @goo(double* %r, double* %p, double* %q) nounwind {
+entry:
+ %0 = load double* %p, align 8
+ %1 = fadd double %0, 1.100000e+00
+ %2 = fmul double %1, 1.200000e+00
+ %3 = fadd double %2, 1.300000e+00
+ %4 = fmul double %3, 1.400000e+00
+ %5 = fadd double %4, 1.500000e+00
+ %6 = fptosi double %5 to i32
+ %7 = load double* %r, align 8
+ %8 = fadd double %7, 7.100000e+00
+ %9 = fmul double %8, 7.200000e+00
+ %10 = fadd double %9, 7.300000e+00
+ %11 = fmul double %10, 7.400000e+00
+ %12 = fadd double %11, 7.500000e+00
+ %13 = fptosi double %12 to i32
+ %14 = icmp slt i32 %6, %13
+ br i1 %14, label %bb, label %return
+
+bb:
+ store double 9.300000e+00, double* %q, align 8
+ ret void
+
+return:
+ ret void
+}
diff --git a/test/CodeGen/X86/break-sse-dep.ll b/test/CodeGen/X86/break-sse-dep.ll
new file mode 100644
index 0000000..acc0647
--- /dev/null
+++ b/test/CodeGen/X86/break-sse-dep.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | FileCheck %s
+
+define double @t1(float* nocapture %x) nounwind readonly ssp {
+entry:
+; CHECK: t1:
+; CHECK: movss (%rdi), %xmm0
+; CHECK; cvtss2sd %xmm0, %xmm0
+
+ %0 = load float* %x, align 4
+ %1 = fpext float %0 to double
+ ret double %1
+}
+
+define float @t2(double* nocapture %x) nounwind readonly ssp optsize {
+entry:
+; CHECK: t2:
+; CHECK; cvtsd2ss (%rdi), %xmm0
+ %0 = load double* %x, align 8
+ %1 = fptrunc double %0 to float
+ ret float %1
+}
diff --git a/test/CodeGen/X86/bss_pagealigned.ll b/test/CodeGen/X86/bss_pagealigned.ll
new file mode 100644
index 0000000..da95aca
--- /dev/null
+++ b/test/CodeGen/X86/bss_pagealigned.ll
@@ -0,0 +1,21 @@
+; RUN: llc --code-model=kernel -march=x86-64 <%s -asm-verbose=0 | FileCheck %s
+; PR4933
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+%struct.kmem_cache_order_objects = type { i64 }
+declare i8* @memset(i8*, i32, i64)
+define void @unxlate_dev_mem_ptr(i64 %phis, i8* %addr) nounwind {
+ %pte.addr.i = alloca %struct.kmem_cache_order_objects*
+ %call8 = call i8* @memset(i8* bitcast ([512 x %struct.kmem_cache_order_objects]* @bm_pte to i8*), i32 0, i64 4096)
+; CHECK: movq $bm_pte, %rdi
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: movl $4096, %edx
+; CHECK-NEXT: callq memset
+ ret void
+}
+@bm_pte = internal global [512 x %struct.kmem_cache_order_objects] zeroinitializer, section ".bss.page_aligned", align 4096
+; CHECK: .section .bss.page_aligned,"aw",@nobits
+; CHECK-NEXT: .align 4096
+; CHECK-NEXT: bm_pte:
+; CHECK-NEXT: .zero 4096
+; CHECK-NEXT: .size bm_pte, 4096
diff --git a/test/CodeGen/X86/bswap-inline-asm.ll b/test/CodeGen/X86/bswap-inline-asm.ll
new file mode 100644
index 0000000..5bf58fa
--- /dev/null
+++ b/test/CodeGen/X86/bswap-inline-asm.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: not grep APP %t
+; RUN: grep bswapq %t | count 2
+; RUN: grep bswapl %t | count 1
+
+define i64 @foo(i64 %x) nounwind {
+ %asmtmp = tail call i64 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
+ ret i64 %asmtmp
+}
+define i64 @bar(i64 %x) nounwind {
+ %asmtmp = tail call i64 asm "bswapq ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
+ ret i64 %asmtmp
+}
+define i32 @pen(i32 %x) nounwind {
+ %asmtmp = tail call i32 asm "bswapl ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind
+ ret i32 %asmtmp
+}
diff --git a/test/CodeGen/X86/bswap.ll b/test/CodeGen/X86/bswap.ll
new file mode 100644
index 0000000..0a72c1c
--- /dev/null
+++ b/test/CodeGen/X86/bswap.ll
@@ -0,0 +1,27 @@
+; bswap should be constant folded when it is passed a constant argument
+
+; RUN: llc < %s -march=x86 | \
+; RUN: grep bswapl | count 3
+; RUN: llc < %s -march=x86 | grep rolw | count 1
+
+declare i16 @llvm.bswap.i16(i16)
+
+declare i32 @llvm.bswap.i32(i32)
+
+declare i64 @llvm.bswap.i64(i64)
+
+define i16 @W(i16 %A) {
+ %Z = call i16 @llvm.bswap.i16( i16 %A ) ; <i16> [#uses=1]
+ ret i16 %Z
+}
+
+define i32 @X(i32 %A) {
+ %Z = call i32 @llvm.bswap.i32( i32 %A ) ; <i32> [#uses=1]
+ ret i32 %Z
+}
+
+define i64 @Y(i64 %A) {
+ %Z = call i64 @llvm.bswap.i64( i64 %A ) ; <i64> [#uses=1]
+ ret i64 %Z
+}
+
diff --git a/test/CodeGen/X86/bt.ll b/test/CodeGen/X86/bt.ll
new file mode 100644
index 0000000..ec447e5
--- /dev/null
+++ b/test/CodeGen/X86/bt.ll
@@ -0,0 +1,442 @@
+; RUN: llc < %s -march=x86 | grep btl | count 28
+; RUN: llc < %s -march=x86 -mcpu=pentium4 | grep btl | not grep esp
+; RUN: llc < %s -march=x86 -mcpu=penryn | grep btl | not grep esp
+; PR3253
+
+; The register+memory form of the BT instruction should be usable on
+; pentium4, however it is currently disabled due to the register+memory
+; form having different semantics than the register+register form.
+
+; Test these patterns:
+; (X & (1 << N)) != 0 --> BT(X, N).
+; ((X >>u N) & 1) != 0 --> BT(X, N).
+; as well as several variations:
+; - The second form can use an arithmetic shift.
+; - Either form can use == instead of !=.
+; - Either form can compare with an operand of the &
+; instead of with 0.
+; - The comparison can be commuted (only cases where neither
+; operand is constant are included).
+; - The and can be commuted.
+
+define void @test2(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
+ %tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @test2b(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 1, %tmp29
+ %tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @atest2(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
+ %tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @atest2b(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 1, %tmp29
+ %tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @test3(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = shl i32 1, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1]
+ %tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @test3b(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = shl i32 1, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %x, %tmp29
+ %tmp4 = icmp eq i32 %tmp3, 0 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @testne2(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
+ %tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @testne2b(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 1, %tmp29
+ %tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @atestne2(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
+ %tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @atestne2b(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 1, %tmp29
+ %tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @testne3(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = shl i32 1, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1]
+ %tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @testne3b(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = shl i32 1, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %x, %tmp29
+ %tmp4 = icmp ne i32 %tmp3, 0 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @query2(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
+ %tmp4 = icmp eq i32 %tmp3, 1 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @query2b(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 1, %tmp29
+ %tmp4 = icmp eq i32 %tmp3, 1 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @aquery2(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
+ %tmp4 = icmp eq i32 %tmp3, 1 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @aquery2b(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 1, %tmp29
+ %tmp4 = icmp eq i32 %tmp3, 1 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @query3(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = shl i32 1, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1]
+ %tmp4 = icmp eq i32 %tmp3, %tmp29 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @query3b(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = shl i32 1, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %x, %tmp29
+ %tmp4 = icmp eq i32 %tmp3, %tmp29 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @query3x(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = shl i32 1, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1]
+ %tmp4 = icmp eq i32 %tmp29, %tmp3 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @query3bx(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = shl i32 1, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %x, %tmp29
+ %tmp4 = icmp eq i32 %tmp29, %tmp3 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @queryne2(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
+ %tmp4 = icmp ne i32 %tmp3, 1 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @queryne2b(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = lshr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 1, %tmp29
+ %tmp4 = icmp ne i32 %tmp3, 1 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @aqueryne2(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp29, 1 ; <i32> [#uses=1]
+ %tmp4 = icmp ne i32 %tmp3, 1 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @aqueryne2b(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = ashr i32 %x, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 1, %tmp29
+ %tmp4 = icmp ne i32 %tmp3, 1 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @queryne3(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = shl i32 1, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1]
+ %tmp4 = icmp ne i32 %tmp3, %tmp29 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @queryne3b(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = shl i32 1, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %x, %tmp29
+ %tmp4 = icmp ne i32 %tmp3, %tmp29 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @queryne3x(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = shl i32 1, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp29, %x ; <i32> [#uses=1]
+ %tmp4 = icmp ne i32 %tmp29, %tmp3 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @queryne3bx(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp29 = shl i32 1, %n ; <i32> [#uses=1]
+ %tmp3 = and i32 %x, %tmp29
+ %tmp4 = icmp ne i32 %tmp29, %tmp3 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+declare void @foo()
diff --git a/test/CodeGen/X86/byval.ll b/test/CodeGen/X86/byval.ll
new file mode 100644
index 0000000..af36e1b
--- /dev/null
+++ b/test/CodeGen/X86/byval.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86-64 | grep {movq 8(%rsp), %rax}
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep {movl 8(%esp), %edx} %t
+; RUN: grep {movl 4(%esp), %eax} %t
+
+%struct.s = type { i64, i64, i64 }
+
+define i64 @f(%struct.s* byval %a) {
+entry:
+ %tmp2 = getelementptr %struct.s* %a, i32 0, i32 0
+ %tmp3 = load i64* %tmp2, align 8
+ ret i64 %tmp3
+}
diff --git a/test/CodeGen/X86/byval2.ll b/test/CodeGen/X86/byval2.ll
new file mode 100644
index 0000000..71129f5
--- /dev/null
+++ b/test/CodeGen/X86/byval2.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=x86-64 | grep rep.movsq | count 2
+; RUN: llc < %s -march=x86 | grep rep.movsl | count 2
+
+%struct.s = type { i64, i64, i64, i64, i64, i64, i64, i64,
+ i64, i64, i64, i64, i64, i64, i64, i64,
+ i64 }
+
+define void @g(i64 %a, i64 %b, i64 %c) {
+entry:
+ %d = alloca %struct.s, align 16
+ %tmp = getelementptr %struct.s* %d, i32 0, i32 0
+ store i64 %a, i64* %tmp, align 16
+ %tmp2 = getelementptr %struct.s* %d, i32 0, i32 1
+ store i64 %b, i64* %tmp2, align 16
+ %tmp4 = getelementptr %struct.s* %d, i32 0, i32 2
+ store i64 %c, i64* %tmp4, align 16
+ call void @f( %struct.s* %d byval)
+ call void @f( %struct.s* %d byval)
+ ret void
+}
+
+declare void @f(%struct.s* byval)
diff --git a/test/CodeGen/X86/byval3.ll b/test/CodeGen/X86/byval3.ll
new file mode 100644
index 0000000..504e0be
--- /dev/null
+++ b/test/CodeGen/X86/byval3.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=x86-64 | grep rep.movsq | count 2
+; RUN: llc < %s -march=x86 | grep rep.movsl | count 2
+
+%struct.s = type { i32, i32, i32, i32, i32, i32, i32, i32,
+ i32, i32, i32, i32, i32, i32, i32, i32,
+ i32, i32, i32, i32, i32, i32, i32, i32,
+ i32, i32, i32, i32, i32, i32, i32, i32,
+ i32 }
+
+define void @g(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6) nounwind {
+entry:
+ %d = alloca %struct.s, align 16
+ %tmp = getelementptr %struct.s* %d, i32 0, i32 0
+ store i32 %a1, i32* %tmp, align 16
+ %tmp2 = getelementptr %struct.s* %d, i32 0, i32 1
+ store i32 %a2, i32* %tmp2, align 16
+ %tmp4 = getelementptr %struct.s* %d, i32 0, i32 2
+ store i32 %a3, i32* %tmp4, align 16
+ %tmp6 = getelementptr %struct.s* %d, i32 0, i32 3
+ store i32 %a4, i32* %tmp6, align 16
+ %tmp8 = getelementptr %struct.s* %d, i32 0, i32 4
+ store i32 %a5, i32* %tmp8, align 16
+ %tmp10 = getelementptr %struct.s* %d, i32 0, i32 5
+ store i32 %a6, i32* %tmp10, align 16
+ call void @f( %struct.s* %d byval)
+ call void @f( %struct.s* %d byval)
+ ret void
+}
+
+declare void @f(%struct.s* byval)
diff --git a/test/CodeGen/X86/byval4.ll b/test/CodeGen/X86/byval4.ll
new file mode 100644
index 0000000..4db9d65
--- /dev/null
+++ b/test/CodeGen/X86/byval4.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -march=x86-64 | grep rep.movsq | count 2
+; RUN: llc < %s -march=x86 | grep rep.movsl | count 2
+
+%struct.s = type { i16, i16, i16, i16, i16, i16, i16, i16,
+ i16, i16, i16, i16, i16, i16, i16, i16,
+ i16, i16, i16, i16, i16, i16, i16, i16,
+ i16, i16, i16, i16, i16, i16, i16, i16,
+ i16, i16, i16, i16, i16, i16, i16, i16,
+ i16, i16, i16, i16, i16, i16, i16, i16,
+ i16, i16, i16, i16, i16, i16, i16, i16,
+ i16, i16, i16, i16, i16, i16, i16, i16,
+ i16 }
+
+
+define void @g(i16 signext %a1, i16 signext %a2, i16 signext %a3,
+ i16 signext %a4, i16 signext %a5, i16 signext %a6) nounwind {
+entry:
+ %a = alloca %struct.s, align 16
+ %tmp = getelementptr %struct.s* %a, i32 0, i32 0
+ store i16 %a1, i16* %tmp, align 16
+ %tmp2 = getelementptr %struct.s* %a, i32 0, i32 1
+ store i16 %a2, i16* %tmp2, align 16
+ %tmp4 = getelementptr %struct.s* %a, i32 0, i32 2
+ store i16 %a3, i16* %tmp4, align 16
+ %tmp6 = getelementptr %struct.s* %a, i32 0, i32 3
+ store i16 %a4, i16* %tmp6, align 16
+ %tmp8 = getelementptr %struct.s* %a, i32 0, i32 4
+ store i16 %a5, i16* %tmp8, align 16
+ %tmp10 = getelementptr %struct.s* %a, i32 0, i32 5
+ store i16 %a6, i16* %tmp10, align 16
+ call void @f( %struct.s* %a byval )
+ call void @f( %struct.s* %a byval )
+ ret void
+}
+
+declare void @f(%struct.s* byval)
diff --git a/test/CodeGen/X86/byval5.ll b/test/CodeGen/X86/byval5.ll
new file mode 100644
index 0000000..69c115b
--- /dev/null
+++ b/test/CodeGen/X86/byval5.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -march=x86-64 | grep rep.movsq | count 2
+; RUN: llc < %s -march=x86 | grep rep.movsl | count 2
+
+%struct.s = type { i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8, i8, i8, i8, i8, i8, i8, i8,
+ i8 }
+
+
+define void @g(i8 signext %a1, i8 signext %a2, i8 signext %a3,
+ i8 signext %a4, i8 signext %a5, i8 signext %a6) {
+entry:
+ %a = alloca %struct.s
+ %tmp = getelementptr %struct.s* %a, i32 0, i32 0
+ store i8 %a1, i8* %tmp, align 8
+ %tmp2 = getelementptr %struct.s* %a, i32 0, i32 1
+ store i8 %a2, i8* %tmp2, align 8
+ %tmp4 = getelementptr %struct.s* %a, i32 0, i32 2
+ store i8 %a3, i8* %tmp4, align 8
+ %tmp6 = getelementptr %struct.s* %a, i32 0, i32 3
+ store i8 %a4, i8* %tmp6, align 8
+ %tmp8 = getelementptr %struct.s* %a, i32 0, i32 4
+ store i8 %a5, i8* %tmp8, align 8
+ %tmp10 = getelementptr %struct.s* %a, i32 0, i32 5
+ store i8 %a6, i8* %tmp10, align 8
+ call void @f( %struct.s* %a byval )
+ call void @f( %struct.s* %a byval )
+ ret void
+}
+
+declare void @f(%struct.s* byval)
diff --git a/test/CodeGen/X86/byval6.ll b/test/CodeGen/X86/byval6.ll
new file mode 100644
index 0000000..b060369
--- /dev/null
+++ b/test/CodeGen/X86/byval6.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86 | grep add | not grep 16
+
+ %struct.W = type { x86_fp80, x86_fp80 }
+@B = global %struct.W { x86_fp80 0xK4001A000000000000000, x86_fp80 0xK4001C000000000000000 }, align 32
[email protected] = internal constant %struct.W { x86_fp80 0xK4001E000000000000000, x86_fp80 0xK40028000000000000000 }
+
+define i32 @main() nounwind {
+entry:
+ tail call void (i32, ...)* @bar( i32 3, %struct.W* byval @.cpx ) nounwind
+ tail call void (i32, ...)* @baz( i32 3, %struct.W* byval @B ) nounwind
+ ret i32 undef
+}
+
+declare void @bar(i32, ...)
+
+declare void @baz(i32, ...)
diff --git a/test/CodeGen/X86/byval7.ll b/test/CodeGen/X86/byval7.ll
new file mode 100644
index 0000000..0da93ba
--- /dev/null
+++ b/test/CodeGen/X86/byval7.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah | egrep {add|lea} | grep 16
+
+ %struct.S = type { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>,
+ <2 x i64> }
+
+define i32 @main() nounwind {
+entry:
+ %s = alloca %struct.S ; <%struct.S*> [#uses=2]
+ %tmp15 = getelementptr %struct.S* %s, i32 0, i32 0 ; <<2 x i64>*> [#uses=1]
+ store <2 x i64> < i64 8589934595, i64 1 >, <2 x i64>* %tmp15, align 16
+ call void @t( i32 1, %struct.S* byval %s ) nounwind
+ ret i32 0
+}
+
+declare void @t(i32, %struct.S* byval )
diff --git a/test/CodeGen/X86/call-imm.ll b/test/CodeGen/X86/call-imm.ll
new file mode 100644
index 0000000..87785bc
--- /dev/null
+++ b/test/CodeGen/X86/call-imm.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -mtriple=i386-darwin-apple -relocation-model=static | grep {call.*12345678}
+; RUN: llc < %s -mtriple=i386-darwin-apple -relocation-model=pic | not grep {call.*12345678}
+; RUN: llc < %s -mtriple=i386-pc-linux -relocation-model=dynamic-no-pic | grep {call.*12345678}
+
+; Call to immediate is not safe on x86-64 unless we *know* that the
+; call will be within 32-bits pcrel from the dest immediate.
+
+; RUN: llc < %s -march=x86-64 | grep {call.*\*%rax}
+
+; PR3666
+; PR3773
+; rdar://6904453
+
+define i32 @main() nounwind {
+entry:
+ %0 = call i32 inttoptr (i32 12345678 to i32 (i32)*)(i32 0) nounwind ; <i32> [#uses=1]
+ ret i32 %0
+}
diff --git a/test/CodeGen/X86/call-push.ll b/test/CodeGen/X86/call-push.ll
new file mode 100644
index 0000000..02cbccc
--- /dev/null
+++ b/test/CodeGen/X86/call-push.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim | FileCheck %s
+
+ %struct.decode_t = type { i8, i8, i8, i8, i16, i8, i8, %struct.range_t** }
+ %struct.range_t = type { float, float, i32, i32, i32, [0 x i8] }
+
+define i32 @decode_byte(%struct.decode_t* %decode) nounwind {
+; CHECK: decode_byte:
+; CHECK: pushl
+; CHECK: popl
+; CHECK: popl
+; CHECK: jmp
+entry:
+ %tmp2 = getelementptr %struct.decode_t* %decode, i32 0, i32 4 ; <i16*> [#uses=1]
+ %tmp23 = bitcast i16* %tmp2 to i32* ; <i32*> [#uses=1]
+ %tmp4 = load i32* %tmp23 ; <i32> [#uses=1]
+ %tmp514 = lshr i32 %tmp4, 24 ; <i32> [#uses=1]
+ %tmp56 = trunc i32 %tmp514 to i8 ; <i8> [#uses=1]
+ %tmp7 = icmp eq i8 %tmp56, 0 ; <i1> [#uses=1]
+ br i1 %tmp7, label %UnifiedReturnBlock, label %cond_true
+
+cond_true: ; preds = %entry
+ %tmp10 = tail call i32 @f( %struct.decode_t* %decode ) ; <i32> [#uses=1]
+ ret i32 %tmp10
+
+UnifiedReturnBlock: ; preds = %entry
+ ret i32 0
+}
+
+declare i32 @f(%struct.decode_t*)
diff --git a/test/CodeGen/X86/change-compare-stride-0.ll b/test/CodeGen/X86/change-compare-stride-0.ll
new file mode 100644
index 0000000..d520a6f
--- /dev/null
+++ b/test/CodeGen/X86/change-compare-stride-0.ll
@@ -0,0 +1,77 @@
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep {cmpl \$-478,} %t
+; RUN: not grep inc %t
+; RUN: not grep {leal 1(} %t
+; RUN: not grep {leal -1(} %t
+; RUN: grep dec %t | count 1
+
+define void @borf(i8* nocapture %in, i8* nocapture %out) nounwind {
+bb4.thread:
+ br label %bb2.outer
+
+bb2.outer: ; preds = %bb4, %bb4.thread
+ %indvar18 = phi i32 [ 0, %bb4.thread ], [ %indvar.next28, %bb4 ] ; <i32> [#uses=3]
+ %tmp34 = mul i32 %indvar18, 65535 ; <i32> [#uses=1]
+ %i.0.reg2mem.0.ph = add i32 %tmp34, 639 ; <i32> [#uses=1]
+ %0 = and i32 %i.0.reg2mem.0.ph, 65535 ; <i32> [#uses=1]
+ %1 = mul i32 %0, 480 ; <i32> [#uses=1]
+ %tmp20 = mul i32 %indvar18, -478 ; <i32> [#uses=1]
+ br label %bb2
+
+bb2: ; preds = %bb2, %bb2.outer
+ %indvar = phi i32 [ 0, %bb2.outer ], [ %indvar.next, %bb2 ] ; <i32> [#uses=3]
+ %ctg2 = getelementptr i8* %out, i32 %tmp20 ; <i8*> [#uses=1]
+ %tmp21 = ptrtoint i8* %ctg2 to i32 ; <i32> [#uses=1]
+ %tmp23 = sub i32 %tmp21, %indvar ; <i32> [#uses=1]
+ %out_addr.0.reg2mem.0 = inttoptr i32 %tmp23 to i8* ; <i8*> [#uses=1]
+ %tmp25 = mul i32 %indvar, 65535 ; <i32> [#uses=1]
+ %j.0.reg2mem.0 = add i32 %tmp25, 479 ; <i32> [#uses=1]
+ %2 = and i32 %j.0.reg2mem.0, 65535 ; <i32> [#uses=1]
+ %3 = add i32 %1, %2 ; <i32> [#uses=9]
+ %4 = add i32 %3, -481 ; <i32> [#uses=1]
+ %5 = getelementptr i8* %in, i32 %4 ; <i8*> [#uses=1]
+ %6 = load i8* %5, align 1 ; <i8> [#uses=1]
+ %7 = add i32 %3, -480 ; <i32> [#uses=1]
+ %8 = getelementptr i8* %in, i32 %7 ; <i8*> [#uses=1]
+ %9 = load i8* %8, align 1 ; <i8> [#uses=1]
+ %10 = add i32 %3, -479 ; <i32> [#uses=1]
+ %11 = getelementptr i8* %in, i32 %10 ; <i8*> [#uses=1]
+ %12 = load i8* %11, align 1 ; <i8> [#uses=1]
+ %13 = add i32 %3, -1 ; <i32> [#uses=1]
+ %14 = getelementptr i8* %in, i32 %13 ; <i8*> [#uses=1]
+ %15 = load i8* %14, align 1 ; <i8> [#uses=1]
+ %16 = getelementptr i8* %in, i32 %3 ; <i8*> [#uses=1]
+ %17 = load i8* %16, align 1 ; <i8> [#uses=1]
+ %18 = add i32 %3, 1 ; <i32> [#uses=1]
+ %19 = getelementptr i8* %in, i32 %18 ; <i8*> [#uses=1]
+ %20 = load i8* %19, align 1 ; <i8> [#uses=1]
+ %21 = add i32 %3, 481 ; <i32> [#uses=1]
+ %22 = getelementptr i8* %in, i32 %21 ; <i8*> [#uses=1]
+ %23 = load i8* %22, align 1 ; <i8> [#uses=1]
+ %24 = add i32 %3, 480 ; <i32> [#uses=1]
+ %25 = getelementptr i8* %in, i32 %24 ; <i8*> [#uses=1]
+ %26 = load i8* %25, align 1 ; <i8> [#uses=1]
+ %27 = add i32 %3, 479 ; <i32> [#uses=1]
+ %28 = getelementptr i8* %in, i32 %27 ; <i8*> [#uses=1]
+ %29 = load i8* %28, align 1 ; <i8> [#uses=1]
+ %30 = add i8 %9, %6 ; <i8> [#uses=1]
+ %31 = add i8 %30, %12 ; <i8> [#uses=1]
+ %32 = add i8 %31, %15 ; <i8> [#uses=1]
+ %33 = add i8 %32, %17 ; <i8> [#uses=1]
+ %34 = add i8 %33, %20 ; <i8> [#uses=1]
+ %35 = add i8 %34, %23 ; <i8> [#uses=1]
+ %36 = add i8 %35, %26 ; <i8> [#uses=1]
+ %37 = add i8 %36, %29 ; <i8> [#uses=1]
+ store i8 %37, i8* %out_addr.0.reg2mem.0, align 1
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, 478 ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb4, label %bb2
+
+bb4: ; preds = %bb2
+ %indvar.next28 = add i32 %indvar18, 1 ; <i32> [#uses=2]
+ %exitcond29 = icmp eq i32 %indvar.next28, 638 ; <i1> [#uses=1]
+ br i1 %exitcond29, label %return, label %bb2.outer
+
+return: ; preds = %bb4
+ ret void
+}
diff --git a/test/CodeGen/X86/change-compare-stride-1.ll b/test/CodeGen/X86/change-compare-stride-1.ll
new file mode 100644
index 0000000..a9ddbdb
--- /dev/null
+++ b/test/CodeGen/X86/change-compare-stride-1.ll
@@ -0,0 +1,86 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: grep {cmpq \$-478,} %t
+; RUN: not grep inc %t
+; RUN: not grep {leal 1(} %t
+; RUN: not grep {leal -1(} %t
+; RUN: grep dec %t | count 1
+
+define void @borf(i8* nocapture %in, i8* nocapture %out) nounwind {
+bb4.thread:
+ br label %bb2.outer
+
+bb2.outer: ; preds = %bb4, %bb4.thread
+ %indvar19 = phi i64 [ 0, %bb4.thread ], [ %indvar.next29, %bb4 ] ; <i64> [#uses=3]
+ %indvar31 = trunc i64 %indvar19 to i16 ; <i16> [#uses=1]
+ %i.0.reg2mem.0.ph = sub i16 639, %indvar31 ; <i16> [#uses=1]
+ %0 = zext i16 %i.0.reg2mem.0.ph to i32 ; <i32> [#uses=1]
+ %1 = mul i32 %0, 480 ; <i32> [#uses=1]
+ %tmp21 = mul i64 %indvar19, -478 ; <i64> [#uses=1]
+ br label %bb2
+
+bb2: ; preds = %bb2, %bb2.outer
+ %indvar = phi i64 [ 0, %bb2.outer ], [ %indvar.next, %bb2 ] ; <i64> [#uses=3]
+ %indvar16 = trunc i64 %indvar to i16 ; <i16> [#uses=1]
+ %ctg2 = getelementptr i8* %out, i64 %tmp21 ; <i8*> [#uses=1]
+ %tmp22 = ptrtoint i8* %ctg2 to i64 ; <i64> [#uses=1]
+ %tmp24 = sub i64 %tmp22, %indvar ; <i64> [#uses=1]
+ %out_addr.0.reg2mem.0 = inttoptr i64 %tmp24 to i8* ; <i8*> [#uses=1]
+ %j.0.reg2mem.0 = sub i16 479, %indvar16 ; <i16> [#uses=1]
+ %2 = zext i16 %j.0.reg2mem.0 to i32 ; <i32> [#uses=1]
+ %3 = add i32 %1, %2 ; <i32> [#uses=9]
+ %4 = add i32 %3, -481 ; <i32> [#uses=1]
+ %5 = zext i32 %4 to i64 ; <i64> [#uses=1]
+ %6 = getelementptr i8* %in, i64 %5 ; <i8*> [#uses=1]
+ %7 = load i8* %6, align 1 ; <i8> [#uses=1]
+ %8 = add i32 %3, -480 ; <i32> [#uses=1]
+ %9 = zext i32 %8 to i64 ; <i64> [#uses=1]
+ %10 = getelementptr i8* %in, i64 %9 ; <i8*> [#uses=1]
+ %11 = load i8* %10, align 1 ; <i8> [#uses=1]
+ %12 = add i32 %3, -479 ; <i32> [#uses=1]
+ %13 = zext i32 %12 to i64 ; <i64> [#uses=1]
+ %14 = getelementptr i8* %in, i64 %13 ; <i8*> [#uses=1]
+ %15 = load i8* %14, align 1 ; <i8> [#uses=1]
+ %16 = add i32 %3, -1 ; <i32> [#uses=1]
+ %17 = zext i32 %16 to i64 ; <i64> [#uses=1]
+ %18 = getelementptr i8* %in, i64 %17 ; <i8*> [#uses=1]
+ %19 = load i8* %18, align 1 ; <i8> [#uses=1]
+ %20 = zext i32 %3 to i64 ; <i64> [#uses=1]
+ %21 = getelementptr i8* %in, i64 %20 ; <i8*> [#uses=1]
+ %22 = load i8* %21, align 1 ; <i8> [#uses=1]
+ %23 = add i32 %3, 1 ; <i32> [#uses=1]
+ %24 = zext i32 %23 to i64 ; <i64> [#uses=1]
+ %25 = getelementptr i8* %in, i64 %24 ; <i8*> [#uses=1]
+ %26 = load i8* %25, align 1 ; <i8> [#uses=1]
+ %27 = add i32 %3, 481 ; <i32> [#uses=1]
+ %28 = zext i32 %27 to i64 ; <i64> [#uses=1]
+ %29 = getelementptr i8* %in, i64 %28 ; <i8*> [#uses=1]
+ %30 = load i8* %29, align 1 ; <i8> [#uses=1]
+ %31 = add i32 %3, 480 ; <i32> [#uses=1]
+ %32 = zext i32 %31 to i64 ; <i64> [#uses=1]
+ %33 = getelementptr i8* %in, i64 %32 ; <i8*> [#uses=1]
+ %34 = load i8* %33, align 1 ; <i8> [#uses=1]
+ %35 = add i32 %3, 479 ; <i32> [#uses=1]
+ %36 = zext i32 %35 to i64 ; <i64> [#uses=1]
+ %37 = getelementptr i8* %in, i64 %36 ; <i8*> [#uses=1]
+ %38 = load i8* %37, align 1 ; <i8> [#uses=1]
+ %39 = add i8 %11, %7 ; <i8> [#uses=1]
+ %40 = add i8 %39, %15 ; <i8> [#uses=1]
+ %41 = add i8 %40, %19 ; <i8> [#uses=1]
+ %42 = add i8 %41, %22 ; <i8> [#uses=1]
+ %43 = add i8 %42, %26 ; <i8> [#uses=1]
+ %44 = add i8 %43, %30 ; <i8> [#uses=1]
+ %45 = add i8 %44, %34 ; <i8> [#uses=1]
+ %46 = add i8 %45, %38 ; <i8> [#uses=1]
+ store i8 %46, i8* %out_addr.0.reg2mem.0, align 1
+ %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=2]
+ %exitcond = icmp eq i64 %indvar.next, 478 ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb4, label %bb2
+
+bb4: ; preds = %bb2
+ %indvar.next29 = add i64 %indvar19, 1 ; <i64> [#uses=2]
+ %exitcond30 = icmp eq i64 %indvar.next29, 638 ; <i1> [#uses=1]
+ br i1 %exitcond30, label %return, label %bb2.outer
+
+return: ; preds = %bb4
+ ret void
+}
diff --git a/test/CodeGen/X86/clz.ll b/test/CodeGen/X86/clz.ll
new file mode 100644
index 0000000..3f27187
--- /dev/null
+++ b/test/CodeGen/X86/clz.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86 | grep bsr | count 2
+; RUN: llc < %s -march=x86 | grep bsf
+; RUN: llc < %s -march=x86 | grep cmov | count 3
+
+define i32 @t1(i32 %x) nounwind {
+ %tmp = tail call i32 @llvm.ctlz.i32( i32 %x )
+ ret i32 %tmp
+}
+
+declare i32 @llvm.ctlz.i32(i32) nounwind readnone
+
+define i32 @t2(i32 %x) nounwind {
+ %tmp = tail call i32 @llvm.cttz.i32( i32 %x )
+ ret i32 %tmp
+}
+
+declare i32 @llvm.cttz.i32(i32) nounwind readnone
+
+define i16 @t3(i16 %x, i16 %y) nounwind {
+entry:
+ %tmp1 = add i16 %x, %y
+ %tmp2 = tail call i16 @llvm.ctlz.i16( i16 %tmp1 ) ; <i16> [#uses=1]
+ ret i16 %tmp2
+}
+
+declare i16 @llvm.ctlz.i16(i16) nounwind readnone
diff --git a/test/CodeGen/X86/cmov.ll b/test/CodeGen/X86/cmov.ll
new file mode 100644
index 0000000..39d9d1e
--- /dev/null
+++ b/test/CodeGen/X86/cmov.ll
@@ -0,0 +1,157 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+
+define i32 @test1(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
+entry:
+; CHECK: test1:
+; CHECK: btl
+; CHECK-NEXT: movl $12, %eax
+; CHECK-NEXT: cmovael (%rcx), %eax
+; CHECK-NEXT: ret
+
+ %0 = lshr i32 %x, %n ; <i32> [#uses=1]
+ %1 = and i32 %0, 1 ; <i32> [#uses=1]
+ %toBool = icmp eq i32 %1, 0 ; <i1> [#uses=1]
+ %v = load i32* %vp
+ %.0 = select i1 %toBool, i32 %v, i32 12 ; <i32> [#uses=1]
+ ret i32 %.0
+}
+define i32 @test2(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
+entry:
+; CHECK: test2:
+; CHECK: btl
+; CHECK-NEXT: movl $12, %eax
+; CHECK-NEXT: cmovbl (%rcx), %eax
+; CHECK-NEXT: ret
+
+ %0 = lshr i32 %x, %n ; <i32> [#uses=1]
+ %1 = and i32 %0, 1 ; <i32> [#uses=1]
+ %toBool = icmp eq i32 %1, 0 ; <i1> [#uses=1]
+ %v = load i32* %vp
+ %.0 = select i1 %toBool, i32 12, i32 %v ; <i32> [#uses=1]
+ ret i32 %.0
+}
+
+
+; x86's 32-bit cmov doesn't clobber the high 32 bits of the destination
+; if the condition is false. An explicit zero-extend (movl) is needed
+; after the cmov.
+
+declare void @bar(i64) nounwind
+
+define void @test3(i64 %a, i64 %b, i1 %p) nounwind {
+; CHECK: test3:
+; CHECK: cmovnel %edi, %esi
+; CHECK-NEXT: movl %esi, %edi
+
+ %c = trunc i64 %a to i32
+ %d = trunc i64 %b to i32
+ %e = select i1 %p, i32 %c, i32 %d
+ %f = zext i32 %e to i64
+ call void @bar(i64 %f)
+ ret void
+}
+
+
+
+; CodeGen shouldn't try to do a setne after an expanded 8-bit conditional
+; move without recomputing EFLAGS, because the expansion of the conditional
+; move with control flow may clobber EFLAGS (e.g., with xor, to set the
+; register to zero).
+
+; The test is a little awkward; the important part is that there's a test before the
+; setne.
+; PR4814
+
+
+@g_3 = external global i8 ; <i8*> [#uses=1]
+@g_96 = external global i8 ; <i8*> [#uses=2]
+@g_100 = external global i8 ; <i8*> [#uses=2]
+@_2E_str = external constant [15 x i8], align 1 ; <[15 x i8]*> [#uses=1]
+
+define i32 @test4() nounwind {
+entry:
+ %0 = load i8* @g_3, align 1 ; <i8> [#uses=2]
+ %1 = sext i8 %0 to i32 ; <i32> [#uses=1]
+ %.lobit.i = lshr i8 %0, 7 ; <i8> [#uses=1]
+ %tmp.i = zext i8 %.lobit.i to i32 ; <i32> [#uses=1]
+ %tmp.not.i = xor i32 %tmp.i, 1 ; <i32> [#uses=1]
+ %iftmp.17.0.i.i = ashr i32 %1, %tmp.not.i ; <i32> [#uses=1]
+ %retval56.i.i = trunc i32 %iftmp.17.0.i.i to i8 ; <i8> [#uses=1]
+ %2 = icmp eq i8 %retval56.i.i, 0 ; <i1> [#uses=2]
+ %g_96.promoted.i = load i8* @g_96 ; <i8> [#uses=3]
+ %3 = icmp eq i8 %g_96.promoted.i, 0 ; <i1> [#uses=2]
+ br i1 %3, label %func_4.exit.i, label %bb.i.i.i
+
+bb.i.i.i: ; preds = %entry
+ %4 = volatile load i8* @g_100, align 1 ; <i8> [#uses=0]
+ br label %func_4.exit.i
+
+; CHECK: test4:
+; CHECK: g_100
+; CHECK: testb
+; CHECK: testb %al, %al
+; CHECK-NEXT: setne %al
+; CHECK-NEXT: testb
+
+func_4.exit.i: ; preds = %bb.i.i.i, %entry
+ %.not.i = xor i1 %2, true ; <i1> [#uses=1]
+ %brmerge.i = or i1 %3, %.not.i ; <i1> [#uses=1]
+ %.mux.i = select i1 %2, i8 %g_96.promoted.i, i8 0 ; <i8> [#uses=1]
+ br i1 %brmerge.i, label %func_1.exit, label %bb.i.i
+
+bb.i.i: ; preds = %func_4.exit.i
+ %5 = volatile load i8* @g_100, align 1 ; <i8> [#uses=0]
+ br label %func_1.exit
+
+func_1.exit: ; preds = %bb.i.i, %func_4.exit.i
+ %g_96.tmp.0.i = phi i8 [ %g_96.promoted.i, %bb.i.i ], [ %.mux.i, %func_4.exit.i ] ; <i8> [#uses=2]
+ store i8 %g_96.tmp.0.i, i8* @g_96
+ %6 = zext i8 %g_96.tmp.0.i to i32 ; <i32> [#uses=1]
+ %7 = tail call i32 (i8*, ...)* @printf(i8* noalias getelementptr ([15 x i8]* @_2E_str, i64 0, i64 0), i32 %6) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
+
+declare i32 @printf(i8* nocapture, ...) nounwind
+
+
+; Should compile to setcc | -2.
+; rdar://6668608
+define i32 @test5(i32* nocapture %P) nounwind readonly {
+entry:
+; CHECK: test5:
+; CHECK: setg %al
+; CHECK: movzbl %al, %eax
+; CHECK: orl $-2, %eax
+; CHECK: ret
+
+ %0 = load i32* %P, align 4 ; <i32> [#uses=1]
+ %1 = icmp sgt i32 %0, 41 ; <i1> [#uses=1]
+ %iftmp.0.0 = select i1 %1, i32 -1, i32 -2 ; <i32> [#uses=1]
+ ret i32 %iftmp.0.0
+}
+
+define i32 @test6(i32* nocapture %P) nounwind readonly {
+entry:
+; CHECK: test6:
+; CHECK: setl %al
+; CHECK: movzbl %al, %eax
+; CHECK: leal 4(%rax,%rax,8), %eax
+; CHECK: ret
+ %0 = load i32* %P, align 4 ; <i32> [#uses=1]
+ %1 = icmp sgt i32 %0, 41 ; <i1> [#uses=1]
+ %iftmp.0.0 = select i1 %1, i32 4, i32 13 ; <i32> [#uses=1]
+ ret i32 %iftmp.0.0
+}
+
+
+; Don't try to use a 16-bit conditional move to do an 8-bit select,
+; because it isn't worth it. Just use a branch instead.
+define i8 @test7(i1 inreg %c, i8 inreg %a, i8 inreg %b) nounwind {
+; CHECK: test7:
+; CHECK: testb $1, %dil
+; CHECK-NEXT: jne LBB
+
+ %d = select i1 %c, i8 %a, i8 %b
+ ret i8 %d
+}
diff --git a/test/CodeGen/X86/cmp-test.ll b/test/CodeGen/X86/cmp-test.ll
new file mode 100644
index 0000000..898c09b
--- /dev/null
+++ b/test/CodeGen/X86/cmp-test.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=x86 | grep cmp | count 1
+; RUN: llc < %s -march=x86 | grep test | count 1
+
+define i32 @f1(i32 %X, i32* %y) {
+ %tmp = load i32* %y ; <i32> [#uses=1]
+ %tmp.upgrd.1 = icmp eq i32 %tmp, 0 ; <i1> [#uses=1]
+ br i1 %tmp.upgrd.1, label %ReturnBlock, label %cond_true
+
+cond_true: ; preds = %0
+ ret i32 1
+
+ReturnBlock: ; preds = %0
+ ret i32 0
+}
+
+define i32 @f2(i32 %X, i32* %y) {
+ %tmp = load i32* %y ; <i32> [#uses=1]
+ %tmp1 = shl i32 %tmp, 3 ; <i32> [#uses=1]
+ %tmp1.upgrd.2 = icmp eq i32 %tmp1, 0 ; <i1> [#uses=1]
+ br i1 %tmp1.upgrd.2, label %ReturnBlock, label %cond_true
+
+cond_true: ; preds = %0
+ ret i32 1
+
+ReturnBlock: ; preds = %0
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/cmp0.ll b/test/CodeGen/X86/cmp0.ll
new file mode 100644
index 0000000..48784488
--- /dev/null
+++ b/test/CodeGen/X86/cmp0.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+define i64 @test0(i64 %x) nounwind {
+ %t = icmp eq i64 %x, 0
+ %r = zext i1 %t to i64
+ ret i64 %r
+; CHECK: test0:
+; CHECK: testq %rdi, %rdi
+; CHECK: sete %al
+; CHECK: movzbl %al, %eax
+; CHECK: ret
+}
+
+define i64 @test1(i64 %x) nounwind {
+ %t = icmp slt i64 %x, 1
+ %r = zext i1 %t to i64
+ ret i64 %r
+; CHECK: test1:
+; CHECK: testq %rdi, %rdi
+; CHECK: setle %al
+; CHECK: movzbl %al, %eax
+; CHECK: ret
+}
+
diff --git a/test/CodeGen/X86/cmp2.ll b/test/CodeGen/X86/cmp2.ll
new file mode 100644
index 0000000..9a8e00c
--- /dev/null
+++ b/test/CodeGen/X86/cmp2.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep ucomisd | grep CPI | count 2
+
+define i32 @test(double %A) nounwind {
+ entry:
+ %tmp2 = fcmp ogt double %A, 1.500000e+02; <i1> [#uses=1]
+ %tmp5 = fcmp ult double %A, 7.500000e+01; <i1> [#uses=1]
+ %bothcond = or i1 %tmp2, %tmp5; <i1> [#uses=1]
+ br i1 %bothcond, label %bb8, label %bb12
+
+ bb8:; preds = %entry
+ %tmp9 = tail call i32 (...)* @foo( ) nounwind ; <i32> [#uses=1]
+ ret i32 %tmp9
+
+ bb12:; preds = %entry
+ ret i32 32
+}
+
+declare i32 @foo(...)
diff --git a/test/CodeGen/X86/coalesce-esp.ll b/test/CodeGen/X86/coalesce-esp.ll
new file mode 100644
index 0000000..0fe4e56
--- /dev/null
+++ b/test/CodeGen/X86/coalesce-esp.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s | grep {movl %esp, %eax}
+; PR4572
+
+; Don't coalesce with %esp if it would end up putting %esp in
+; the index position of an address, because that can't be
+; encoded on x86. It would actually be slightly better to
+; swap the address operands though, since there's no scale.
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-mingw32"
+ %"struct.std::valarray<unsigned int>" = type { i32, i32* }
+
+define void @_ZSt17__gslice_to_indexjRKSt8valarrayIjES2_RS0_(i32 %__o, %"struct.std::valarray<unsigned int>"* nocapture %__l, %"struct.std::valarray<unsigned int>"* nocapture %__s, %"struct.std::valarray<unsigned int>"* nocapture %__i) nounwind {
+entry:
+ %0 = alloca i32, i32 undef, align 4 ; <i32*> [#uses=1]
+ br i1 undef, label %return, label %bb4
+
+bb4: ; preds = %bb7.backedge, %entry
+ %indvar = phi i32 [ %indvar.next, %bb7.backedge ], [ 0, %entry ] ; <i32> [#uses=2]
+ %scevgep24.sum = sub i32 undef, %indvar ; <i32> [#uses=2]
+ %scevgep25 = getelementptr i32* %0, i32 %scevgep24.sum ; <i32*> [#uses=1]
+ %scevgep27 = getelementptr i32* undef, i32 %scevgep24.sum ; <i32*> [#uses=1]
+ %1 = load i32* %scevgep27, align 4 ; <i32> [#uses=0]
+ br i1 undef, label %bb7.backedge, label %bb5
+
+bb5: ; preds = %bb4
+ store i32 0, i32* %scevgep25, align 4
+ br label %bb7.backedge
+
+bb7.backedge: ; preds = %bb5, %bb4
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br label %bb4
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/coalescer-commute1.ll b/test/CodeGen/X86/coalescer-commute1.ll
new file mode 100644
index 0000000..8aa0bfd
--- /dev/null
+++ b/test/CodeGen/X86/coalescer-commute1.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps
+; PR1877
+
+@NNTOT = weak global i32 0 ; <i32*> [#uses=1]
+@G = weak global float 0.000000e+00 ; <float*> [#uses=1]
+
+define void @runcont(i32* %source) nounwind {
+entry:
+ %tmp10 = load i32* @NNTOT, align 4 ; <i32> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %neuron.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
+ %thesum.0 = phi float [ 0.000000e+00, %entry ], [ %tmp6, %bb ] ; <float> [#uses=1]
+ %tmp2 = getelementptr i32* %source, i32 %neuron.0 ; <i32*> [#uses=1]
+ %tmp3 = load i32* %tmp2, align 4 ; <i32> [#uses=1]
+ %tmp34 = sitofp i32 %tmp3 to float ; <float> [#uses=1]
+ %tmp6 = fadd float %tmp34, %thesum.0 ; <float> [#uses=2]
+ %indvar.next = add i32 %neuron.0, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %tmp10 ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb13, label %bb
+
+bb13: ; preds = %bb
+ volatile store float %tmp6, float* @G, align 4
+ ret void
+}
diff --git a/test/CodeGen/X86/coalescer-commute2.ll b/test/CodeGen/X86/coalescer-commute2.ll
new file mode 100644
index 0000000..5d10bba
--- /dev/null
+++ b/test/CodeGen/X86/coalescer-commute2.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=x86-64 | grep paddw | count 2
+; RUN: llc < %s -march=x86-64 | not grep mov
+
+; The 2-addr pass should ensure that identical code is produced for these functions
+; no extra copy should be generated.
+
+define <2 x i64> @test1(<2 x i64> %x, <2 x i64> %y) nounwind {
+entry:
+ %tmp6 = bitcast <2 x i64> %y to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp8 = bitcast <2 x i64> %x to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp9 = add <8 x i16> %tmp8, %tmp6 ; <<8 x i16>> [#uses=1]
+ %tmp10 = bitcast <8 x i16> %tmp9 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp10
+}
+
+define <2 x i64> @test2(<2 x i64> %x, <2 x i64> %y) nounwind {
+entry:
+ %tmp6 = bitcast <2 x i64> %x to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp8 = bitcast <2 x i64> %y to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp9 = add <8 x i16> %tmp8, %tmp6 ; <<8 x i16>> [#uses=1]
+ %tmp10 = bitcast <8 x i16> %tmp9 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp10
+}
+
+
+; The coalescer should commute the add to avoid a copy.
+define <4 x float> @test3(<4 x float> %V) {
+entry:
+ %tmp8 = shufflevector <4 x float> %V, <4 x float> undef,
+ <4 x i32> < i32 3, i32 2, i32 1, i32 0 >
+ %add = fadd <4 x float> %tmp8, %V
+ ret <4 x float> %add
+}
+
diff --git a/test/CodeGen/X86/coalescer-commute3.ll b/test/CodeGen/X86/coalescer-commute3.ll
new file mode 100644
index 0000000..e5bd448
--- /dev/null
+++ b/test/CodeGen/X86/coalescer-commute3.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | grep mov | count 6
+
+ %struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }
+
+define i32 @perimeter(%struct.quad_struct* %tree, i32 %size) nounwind {
+entry:
+ switch i32 %size, label %UnifiedReturnBlock [
+ i32 2, label %bb
+ i32 0, label %bb50
+ ]
+
+bb: ; preds = %entry
+ %tmp31 = tail call i32 @perimeter( %struct.quad_struct* null, i32 0 ) nounwind ; <i32> [#uses=1]
+ %tmp40 = tail call i32 @perimeter( %struct.quad_struct* null, i32 0 ) nounwind ; <i32> [#uses=1]
+ %tmp33 = add i32 0, %tmp31 ; <i32> [#uses=1]
+ %tmp42 = add i32 %tmp33, %tmp40 ; <i32> [#uses=1]
+ ret i32 %tmp42
+
+bb50: ; preds = %entry
+ ret i32 0
+
+UnifiedReturnBlock: ; preds = %entry
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/coalescer-commute4.ll b/test/CodeGen/X86/coalescer-commute4.ll
new file mode 100644
index 0000000..02a9781
--- /dev/null
+++ b/test/CodeGen/X86/coalescer-commute4.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps
+; PR1501
+
+define float @foo(i32* %x, float* %y, i32 %c) nounwind {
+entry:
+ %tmp2132 = icmp eq i32 %c, 0 ; <i1> [#uses=2]
+ br i1 %tmp2132, label %bb23, label %bb.preheader
+
+bb.preheader: ; preds = %entry
+ %umax = select i1 %tmp2132, i32 1, i32 %c ; <i32> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %bb.preheader
+ %i.0.reg2mem.0 = phi i32 [ 0, %bb.preheader ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
+ %res.0.reg2mem.0 = phi float [ 0.000000e+00, %bb.preheader ], [ %tmp14, %bb ] ; <float> [#uses=1]
+ %tmp3 = getelementptr i32* %x, i32 %i.0.reg2mem.0 ; <i32*> [#uses=1]
+ %tmp4 = load i32* %tmp3, align 4 ; <i32> [#uses=1]
+ %tmp45 = sitofp i32 %tmp4 to float ; <float> [#uses=1]
+ %tmp8 = getelementptr float* %y, i32 %i.0.reg2mem.0 ; <float*> [#uses=1]
+ %tmp9 = load float* %tmp8, align 4 ; <float> [#uses=1]
+ %tmp11 = fmul float %tmp9, %tmp45 ; <float> [#uses=1]
+ %tmp14 = fadd float %tmp11, %res.0.reg2mem.0 ; <float> [#uses=2]
+ %indvar.next = add i32 %i.0.reg2mem.0, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %umax ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb23, label %bb
+
+bb23: ; preds = %bb, %entry
+ %res.0.reg2mem.1 = phi float [ 0.000000e+00, %entry ], [ %tmp14, %bb ] ; <float> [#uses=1]
+ ret float %res.0.reg2mem.1
+}
diff --git a/test/CodeGen/X86/coalescer-commute5.ll b/test/CodeGen/X86/coalescer-commute5.ll
new file mode 100644
index 0000000..510d115
--- /dev/null
+++ b/test/CodeGen/X86/coalescer-commute5.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps
+
+define i32 @t() {
+entry:
+ br i1 true, label %bb1664, label %bb1656
+bb1656: ; preds = %entry
+ ret i32 0
+bb1664: ; preds = %entry
+ %tmp4297 = bitcast <16 x i8> zeroinitializer to <2 x i64> ; <<2 x i64>> [#uses=2]
+ %tmp4351 = call <16 x i8> @llvm.x86.sse2.pcmpeq.b( <16 x i8> zeroinitializer, <16 x i8> zeroinitializer ) nounwind readnone ; <<16 x i8>> [#uses=0]
+ br i1 false, label %bb5310, label %bb4743
+bb4743: ; preds = %bb1664
+ %tmp4360.not28 = or <2 x i64> zeroinitializer, %tmp4297 ; <<2 x i64>> [#uses=1]
+ br label %bb5310
+bb5310: ; preds = %bb4743, %bb1664
+ %tmp4360.not28.pn = phi <2 x i64> [ %tmp4360.not28, %bb4743 ], [ %tmp4297, %bb1664 ] ; <<2 x i64>> [#uses=1]
+ %tmp4415.not.pn = or <2 x i64> zeroinitializer, %tmp4360.not28.pn ; <<2 x i64>> [#uses=0]
+ ret i32 0
+}
+
+declare <16 x i8> @llvm.x86.sse2.pcmpeq.b(<16 x i8>, <16 x i8>) nounwind readnone
diff --git a/test/CodeGen/X86/coalescer-cross.ll b/test/CodeGen/X86/coalescer-cross.ll
new file mode 100644
index 0000000..7d6f399
--- /dev/null
+++ b/test/CodeGen/X86/coalescer-cross.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin10 | not grep movaps
+; rdar://6509240
+
+ type { %struct.TValue } ; type %0
+ type { %struct.L_Umaxalign, i32, %struct.Node* } ; type %1
+ %struct.CallInfo = type { %struct.TValue*, %struct.TValue*, %struct.TValue*, i32*, i32, i32 }
+ %struct.GCObject = type { %struct.lua_State }
+ %struct.L_Umaxalign = type { double }
+ %struct.Mbuffer = type { i8*, i32, i32 }
+ %struct.Node = type { %struct.TValue, %struct.TKey }
+ %struct.TKey = type { %1 }
+ %struct.TString = type { %struct.anon }
+ %struct.TValue = type { %struct.L_Umaxalign, i32 }
+ %struct.Table = type { %struct.GCObject*, i8, i8, i8, i8, %struct.Table*, %struct.TValue*, %struct.Node*, %struct.Node*, %struct.GCObject*, i32 }
+ %struct.UpVal = type { %struct.GCObject*, i8, i8, %struct.TValue*, %0 }
+ %struct.anon = type { %struct.GCObject*, i8, i8, i8, i32, i32 }
+ %struct.global_State = type { %struct.stringtable, i8* (i8*, i8*, i32, i32)*, i8*, i8, i8, i32, %struct.GCObject*, %struct.GCObject**, %struct.GCObject*, %struct.GCObject*, %struct.GCObject*, %struct.GCObject*, %struct.Mbuffer, i32, i32, i32, i32, i32, i32, i32 (%struct.lua_State*)*, %struct.TValue, %struct.lua_State*, %struct.UpVal, [9 x %struct.Table*], [17 x %struct.TString*] }
+ %struct.lua_Debug = type { i32, i8*, i8*, i8*, i8*, i32, i32, i32, i32, [60 x i8], i32 }
+ %struct.lua_State = type { %struct.GCObject*, i8, i8, i8, %struct.TValue*, %struct.TValue*, %struct.global_State*, %struct.CallInfo*, i32*, %struct.TValue*, %struct.TValue*, %struct.CallInfo*, %struct.CallInfo*, i32, i32, i16, i16, i8, i8, i32, i32, void (%struct.lua_State*, %struct.lua_Debug*)*, %struct.TValue, %struct.TValue, %struct.GCObject*, %struct.GCObject*, %struct.lua_longjmp*, i32 }
+ %struct.lua_longjmp = type { %struct.lua_longjmp*, [18 x i32], i32 }
+ %struct.stringtable = type { %struct.GCObject**, i32, i32 }
[email protected] = appending global [1 x i8*] [i8* bitcast (i32 (%struct.lua_State*)* @os_clock to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define i32 @os_clock(%struct.lua_State* nocapture %L) nounwind ssp {
+entry:
+ %0 = tail call i32 @"\01_clock$UNIX2003"() nounwind ; <i32> [#uses=1]
+ %1 = uitofp i32 %0 to double ; <double> [#uses=1]
+ %2 = fdiv double %1, 1.000000e+06 ; <double> [#uses=1]
+ %3 = getelementptr %struct.lua_State* %L, i32 0, i32 4 ; <%struct.TValue**> [#uses=3]
+ %4 = load %struct.TValue** %3, align 4 ; <%struct.TValue*> [#uses=2]
+ %5 = getelementptr %struct.TValue* %4, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ store double %2, double* %5, align 4
+ %6 = getelementptr %struct.TValue* %4, i32 0, i32 1 ; <i32*> [#uses=1]
+ store i32 3, i32* %6, align 4
+ %7 = load %struct.TValue** %3, align 4 ; <%struct.TValue*> [#uses=1]
+ %8 = getelementptr %struct.TValue* %7, i32 1 ; <%struct.TValue*> [#uses=1]
+ store %struct.TValue* %8, %struct.TValue** %3, align 4
+ ret i32 1
+}
+
+declare i32 @"\01_clock$UNIX2003"()
diff --git a/test/CodeGen/X86/coalescer-remat.ll b/test/CodeGen/X86/coalescer-remat.ll
new file mode 100644
index 0000000..4db520f
--- /dev/null
+++ b/test/CodeGen/X86/coalescer-remat.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep xor | count 3
+
+@val = internal global i64 0 ; <i64*> [#uses=1]
+@"\01LC" = internal constant [7 x i8] c"0x%lx\0A\00" ; <[7 x i8]*> [#uses=1]
+
+define i32 @main() nounwind {
+entry:
+ %0 = tail call i64 @llvm.atomic.cmp.swap.i64.p0i64(i64* @val, i64 0, i64 1) ; <i64> [#uses=1]
+ %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([7 x i8]* @"\01LC", i32 0, i64 0), i64 %0) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
+
+declare i64 @llvm.atomic.cmp.swap.i64.p0i64(i64*, i64, i64) nounwind
+
+declare i32 @printf(i8*, ...) nounwind
diff --git a/test/CodeGen/X86/code_placement.ll b/test/CodeGen/X86/code_placement.ll
new file mode 100644
index 0000000..9747183
--- /dev/null
+++ b/test/CodeGen/X86/code_placement.ll
@@ -0,0 +1,136 @@
+; RUN: llc -march=x86 < %s | FileCheck %s
+
+@Te0 = external global [256 x i32] ; <[256 x i32]*> [#uses=5]
+@Te1 = external global [256 x i32] ; <[256 x i32]*> [#uses=4]
+@Te3 = external global [256 x i32] ; <[256 x i32]*> [#uses=2]
+
+define void @t(i8* nocapture %in, i8* nocapture %out, i32* nocapture %rk, i32 %r) nounwind ssp {
+entry:
+ %0 = load i32* %rk, align 4 ; <i32> [#uses=1]
+ %1 = getelementptr i32* %rk, i64 1 ; <i32*> [#uses=1]
+ %2 = load i32* %1, align 4 ; <i32> [#uses=1]
+ %tmp15 = add i32 %r, -1 ; <i32> [#uses=1]
+ %tmp.16 = zext i32 %tmp15 to i64 ; <i64> [#uses=2]
+ br label %bb
+; CHECK: jmp
+; CHECK-NEXT: align
+
+bb: ; preds = %bb1, %entry
+ %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %bb1 ] ; <i64> [#uses=3]
+ %s1.0 = phi i32 [ %2, %entry ], [ %56, %bb1 ] ; <i32> [#uses=2]
+ %s0.0 = phi i32 [ %0, %entry ], [ %43, %bb1 ] ; <i32> [#uses=2]
+ %tmp18 = shl i64 %indvar, 4 ; <i64> [#uses=4]
+ %rk26 = bitcast i32* %rk to i8* ; <i8*> [#uses=6]
+ %3 = lshr i32 %s0.0, 24 ; <i32> [#uses=1]
+ %4 = zext i32 %3 to i64 ; <i64> [#uses=1]
+ %5 = getelementptr [256 x i32]* @Te0, i64 0, i64 %4 ; <i32*> [#uses=1]
+ %6 = load i32* %5, align 4 ; <i32> [#uses=1]
+ %7 = lshr i32 %s1.0, 16 ; <i32> [#uses=1]
+ %8 = and i32 %7, 255 ; <i32> [#uses=1]
+ %9 = zext i32 %8 to i64 ; <i64> [#uses=1]
+ %10 = getelementptr [256 x i32]* @Te1, i64 0, i64 %9 ; <i32*> [#uses=1]
+ %11 = load i32* %10, align 4 ; <i32> [#uses=1]
+ %ctg2.sum2728 = or i64 %tmp18, 8 ; <i64> [#uses=1]
+ %12 = getelementptr i8* %rk26, i64 %ctg2.sum2728 ; <i8*> [#uses=1]
+ %13 = bitcast i8* %12 to i32* ; <i32*> [#uses=1]
+ %14 = load i32* %13, align 4 ; <i32> [#uses=1]
+ %15 = xor i32 %11, %6 ; <i32> [#uses=1]
+ %16 = xor i32 %15, %14 ; <i32> [#uses=3]
+ %17 = lshr i32 %s1.0, 24 ; <i32> [#uses=1]
+ %18 = zext i32 %17 to i64 ; <i64> [#uses=1]
+ %19 = getelementptr [256 x i32]* @Te0, i64 0, i64 %18 ; <i32*> [#uses=1]
+ %20 = load i32* %19, align 4 ; <i32> [#uses=1]
+ %21 = and i32 %s0.0, 255 ; <i32> [#uses=1]
+ %22 = zext i32 %21 to i64 ; <i64> [#uses=1]
+ %23 = getelementptr [256 x i32]* @Te3, i64 0, i64 %22 ; <i32*> [#uses=1]
+ %24 = load i32* %23, align 4 ; <i32> [#uses=1]
+ %ctg2.sum2930 = or i64 %tmp18, 12 ; <i64> [#uses=1]
+ %25 = getelementptr i8* %rk26, i64 %ctg2.sum2930 ; <i8*> [#uses=1]
+ %26 = bitcast i8* %25 to i32* ; <i32*> [#uses=1]
+ %27 = load i32* %26, align 4 ; <i32> [#uses=1]
+ %28 = xor i32 %24, %20 ; <i32> [#uses=1]
+ %29 = xor i32 %28, %27 ; <i32> [#uses=4]
+ %30 = lshr i32 %16, 24 ; <i32> [#uses=1]
+ %31 = zext i32 %30 to i64 ; <i64> [#uses=1]
+ %32 = getelementptr [256 x i32]* @Te0, i64 0, i64 %31 ; <i32*> [#uses=1]
+ %33 = load i32* %32, align 4 ; <i32> [#uses=2]
+ %exitcond = icmp eq i64 %indvar, %tmp.16 ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb2, label %bb1
+
+bb1: ; preds = %bb
+ %ctg2.sum31 = add i64 %tmp18, 16 ; <i64> [#uses=1]
+ %34 = getelementptr i8* %rk26, i64 %ctg2.sum31 ; <i8*> [#uses=1]
+ %35 = bitcast i8* %34 to i32* ; <i32*> [#uses=1]
+ %36 = lshr i32 %29, 16 ; <i32> [#uses=1]
+ %37 = and i32 %36, 255 ; <i32> [#uses=1]
+ %38 = zext i32 %37 to i64 ; <i64> [#uses=1]
+ %39 = getelementptr [256 x i32]* @Te1, i64 0, i64 %38 ; <i32*> [#uses=1]
+ %40 = load i32* %39, align 4 ; <i32> [#uses=1]
+ %41 = load i32* %35, align 4 ; <i32> [#uses=1]
+ %42 = xor i32 %40, %33 ; <i32> [#uses=1]
+ %43 = xor i32 %42, %41 ; <i32> [#uses=1]
+ %44 = lshr i32 %29, 24 ; <i32> [#uses=1]
+ %45 = zext i32 %44 to i64 ; <i64> [#uses=1]
+ %46 = getelementptr [256 x i32]* @Te0, i64 0, i64 %45 ; <i32*> [#uses=1]
+ %47 = load i32* %46, align 4 ; <i32> [#uses=1]
+ %48 = and i32 %16, 255 ; <i32> [#uses=1]
+ %49 = zext i32 %48 to i64 ; <i64> [#uses=1]
+ %50 = getelementptr [256 x i32]* @Te3, i64 0, i64 %49 ; <i32*> [#uses=1]
+ %51 = load i32* %50, align 4 ; <i32> [#uses=1]
+ %ctg2.sum32 = add i64 %tmp18, 20 ; <i64> [#uses=1]
+ %52 = getelementptr i8* %rk26, i64 %ctg2.sum32 ; <i8*> [#uses=1]
+ %53 = bitcast i8* %52 to i32* ; <i32*> [#uses=1]
+ %54 = load i32* %53, align 4 ; <i32> [#uses=1]
+ %55 = xor i32 %51, %47 ; <i32> [#uses=1]
+ %56 = xor i32 %55, %54 ; <i32> [#uses=1]
+ %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1]
+ br label %bb
+
+bb2: ; preds = %bb
+ %tmp10 = shl i64 %tmp.16, 4 ; <i64> [#uses=2]
+ %ctg2.sum = add i64 %tmp10, 16 ; <i64> [#uses=1]
+ %tmp1213 = getelementptr i8* %rk26, i64 %ctg2.sum ; <i8*> [#uses=1]
+ %57 = bitcast i8* %tmp1213 to i32* ; <i32*> [#uses=1]
+ %58 = and i32 %33, -16777216 ; <i32> [#uses=1]
+ %59 = lshr i32 %29, 16 ; <i32> [#uses=1]
+ %60 = and i32 %59, 255 ; <i32> [#uses=1]
+ %61 = zext i32 %60 to i64 ; <i64> [#uses=1]
+ %62 = getelementptr [256 x i32]* @Te1, i64 0, i64 %61 ; <i32*> [#uses=1]
+ %63 = load i32* %62, align 4 ; <i32> [#uses=1]
+ %64 = and i32 %63, 16711680 ; <i32> [#uses=1]
+ %65 = or i32 %64, %58 ; <i32> [#uses=1]
+ %66 = load i32* %57, align 4 ; <i32> [#uses=1]
+ %67 = xor i32 %65, %66 ; <i32> [#uses=2]
+ %68 = lshr i32 %29, 8 ; <i32> [#uses=1]
+ %69 = zext i32 %68 to i64 ; <i64> [#uses=1]
+ %70 = getelementptr [256 x i32]* @Te0, i64 0, i64 %69 ; <i32*> [#uses=1]
+ %71 = load i32* %70, align 4 ; <i32> [#uses=1]
+ %72 = and i32 %71, -16777216 ; <i32> [#uses=1]
+ %73 = and i32 %16, 255 ; <i32> [#uses=1]
+ %74 = zext i32 %73 to i64 ; <i64> [#uses=1]
+ %75 = getelementptr [256 x i32]* @Te1, i64 0, i64 %74 ; <i32*> [#uses=1]
+ %76 = load i32* %75, align 4 ; <i32> [#uses=1]
+ %77 = and i32 %76, 16711680 ; <i32> [#uses=1]
+ %78 = or i32 %77, %72 ; <i32> [#uses=1]
+ %ctg2.sum25 = add i64 %tmp10, 20 ; <i64> [#uses=1]
+ %79 = getelementptr i8* %rk26, i64 %ctg2.sum25 ; <i8*> [#uses=1]
+ %80 = bitcast i8* %79 to i32* ; <i32*> [#uses=1]
+ %81 = load i32* %80, align 4 ; <i32> [#uses=1]
+ %82 = xor i32 %78, %81 ; <i32> [#uses=2]
+ %83 = lshr i32 %67, 24 ; <i32> [#uses=1]
+ %84 = trunc i32 %83 to i8 ; <i8> [#uses=1]
+ store i8 %84, i8* %out, align 1
+ %85 = lshr i32 %67, 16 ; <i32> [#uses=1]
+ %86 = trunc i32 %85 to i8 ; <i8> [#uses=1]
+ %87 = getelementptr i8* %out, i64 1 ; <i8*> [#uses=1]
+ store i8 %86, i8* %87, align 1
+ %88 = getelementptr i8* %out, i64 4 ; <i8*> [#uses=1]
+ %89 = lshr i32 %82, 24 ; <i32> [#uses=1]
+ %90 = trunc i32 %89 to i8 ; <i8> [#uses=1]
+ store i8 %90, i8* %88, align 1
+ %91 = lshr i32 %82, 16 ; <i32> [#uses=1]
+ %92 = trunc i32 %91 to i8 ; <i8> [#uses=1]
+ %93 = getelementptr i8* %out, i64 5 ; <i8*> [#uses=1]
+ store i8 %92, i8* %93, align 1
+ ret void
+}
diff --git a/test/CodeGen/X86/codegen-dce.ll b/test/CodeGen/X86/codegen-dce.ll
new file mode 100644
index 0000000..d83efaf
--- /dev/null
+++ b/test/CodeGen/X86/codegen-dce.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -march=x86 -stats |& grep {codegen-dce} | grep {Number of dead instructions deleted}
+
+ %struct.anon = type { [3 x double], double, %struct.node*, [64 x %struct.bnode*], [64 x %struct.bnode*] }
+ %struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, %struct.bnode*, %struct.bnode* }
+ %struct.node = type { i16, double, [3 x double], i32, i32 }
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
+entry:
+ %0 = malloc %struct.anon ; <%struct.anon*> [#uses=2]
+ %1 = getelementptr %struct.anon* %0, i32 0, i32 2 ; <%struct.node**> [#uses=1]
+ br label %bb14.i
+
+bb14.i: ; preds = %bb14.i, %entry
+ %i8.0.reg2mem.0.i = phi i32 [ 0, %entry ], [ %2, %bb14.i ] ; <i32> [#uses=1]
+ %2 = add i32 %i8.0.reg2mem.0.i, 1 ; <i32> [#uses=2]
+ %exitcond74.i = icmp eq i32 %2, 32 ; <i1> [#uses=1]
+ br i1 %exitcond74.i, label %bb32.i, label %bb14.i
+
+bb32.i: ; preds = %bb32.i, %bb14.i
+ %tmp.0.reg2mem.0.i = phi i32 [ %indvar.next63.i, %bb32.i ], [ 0, %bb14.i ] ; <i32> [#uses=1]
+ %indvar.next63.i = add i32 %tmp.0.reg2mem.0.i, 1 ; <i32> [#uses=2]
+ %exitcond64.i = icmp eq i32 %indvar.next63.i, 64 ; <i1> [#uses=1]
+ br i1 %exitcond64.i, label %bb47.loopexit.i, label %bb32.i
+
+bb.i.i: ; preds = %bb47.loopexit.i
+ unreachable
+
+stepsystem.exit.i: ; preds = %bb47.loopexit.i
+ store %struct.node* null, %struct.node** %1, align 4
+ br label %bb.i6.i
+
+bb.i6.i: ; preds = %bb.i6.i, %stepsystem.exit.i
+ br i1 false, label %bb107.i.i, label %bb.i6.i
+
+bb107.i.i: ; preds = %bb107.i.i, %bb.i6.i
+ %q_addr.0.i.i.in = phi %struct.bnode** [ null, %bb107.i.i ], [ %3, %bb.i6.i ] ; <%struct.bnode**> [#uses=0]
+ br label %bb107.i.i
+
+bb47.loopexit.i: ; preds = %bb32.i
+ %3 = getelementptr %struct.anon* %0, i32 0, i32 4, i32 0 ; <%struct.bnode**> [#uses=1]
+ %4 = icmp eq %struct.node* null, null ; <i1> [#uses=1]
+ br i1 %4, label %stepsystem.exit.i, label %bb.i.i
+}
diff --git a/test/CodeGen/X86/codegen-prepare-cast.ll b/test/CodeGen/X86/codegen-prepare-cast.ll
new file mode 100644
index 0000000..2a8ead8
--- /dev/null
+++ b/test/CodeGen/X86/codegen-prepare-cast.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86-64
+; PR4297
+
+target datalayout =
+"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+ %"byte[]" = type { i64, i8* }
+ %"char[][]" = type { i64, %"byte[]"* }
[email protected] = external constant [7 x i8] ; <[7 x i8]*> [#uses=1]
+
+define fastcc i32 @_Dmain(%"char[][]" %unnamed) {
+entry:
+ %tmp = getelementptr [7 x i8]* @.str, i32 0, i32 0 ; <i8*> [#uses=1]
+ br i1 undef, label %foreachbody, label %foreachend
+
+foreachbody: ; preds = %entry
+ %tmp4 = getelementptr i8* %tmp, i32 undef ; <i8*> [#uses=1]
+ %tmp5 = load i8* %tmp4 ; <i8> [#uses=0]
+ unreachable
+
+foreachend: ; preds = %entry
+ ret i32 0
+}
+
diff --git a/test/CodeGen/X86/codegen-prepare-extload.ll b/test/CodeGen/X86/codegen-prepare-extload.ll
new file mode 100644
index 0000000..9f57d53
--- /dev/null
+++ b/test/CodeGen/X86/codegen-prepare-extload.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+; rdar://7304838
+
+; CodeGenPrepare should move the zext into the block with the load
+; so that SelectionDAG can select it with the load.
+
+; CHECK: movzbl (%rdi), %eax
+
+define void @foo(i8* %p, i32* %q) {
+entry:
+ %t = load i8* %p
+ %a = icmp slt i8 %t, 20
+ br i1 %a, label %true, label %false
+true:
+ %s = zext i8 %t to i32
+ store i32 %s, i32* %q
+ ret void
+false:
+ ret void
+}
diff --git a/test/CodeGen/X86/codemodel.ll b/test/CodeGen/X86/codemodel.ll
new file mode 100644
index 0000000..b6ca1ce
--- /dev/null
+++ b/test/CodeGen/X86/codemodel.ll
@@ -0,0 +1,67 @@
+; RUN: llc < %s -code-model=small | FileCheck -check-prefix CHECK-SMALL %s
+; RUN: llc < %s -code-model=kernel | FileCheck -check-prefix CHECK-KERNEL %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+@data = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
+
+define i32 @foo() nounwind readonly {
+entry:
+; CHECK-SMALL: foo:
+; CHECK-SMALL: movl data(%rip), %eax
+; CHECK-KERNEL: foo:
+; CHECK-KERNEL: movl data, %eax
+ %0 = load i32* getelementptr ([0 x i32]* @data, i64 0, i64 0), align 4 ; <i32> [#uses=1]
+ ret i32 %0
+}
+
+define i32 @foo2() nounwind readonly {
+entry:
+; CHECK-SMALL: foo2:
+; CHECK-SMALL: movl data+40(%rip), %eax
+; CHECK-KERNEL: foo2:
+; CHECK-KERNEL: movl data+40, %eax
+ %0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 10), align 4 ; <i32> [#uses=1]
+ ret i32 %0
+}
+
+define i32 @foo3() nounwind readonly {
+entry:
+; CHECK-SMALL: foo3:
+; CHECK-SMALL: movl data-40(%rip), %eax
+; CHECK-KERNEL: foo3:
+; CHECK-KERNEL: movq $-40, %rax
+ %0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 -10), align 4 ; <i32> [#uses=1]
+ ret i32 %0
+}
+
+define i32 @foo4() nounwind readonly {
+entry:
+; FIXME: We really can use movabsl here!
+; CHECK-SMALL: foo4:
+; CHECK-SMALL: movl $16777216, %eax
+; CHECK-SMALL: movl data(%rax), %eax
+; CHECK-KERNEL: foo4:
+; CHECK-KERNEL: movl data+16777216, %eax
+ %0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 4194304), align 4 ; <i32> [#uses=1]
+ ret i32 %0
+}
+
+define i32 @foo1() nounwind readonly {
+entry:
+; CHECK-SMALL: foo1:
+; CHECK-SMALL: movl data+16777212(%rip), %eax
+; CHECK-KERNEL: foo1:
+; CHECK-KERNEL: movl data+16777212, %eax
+ %0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 4194303), align 4 ; <i32> [#uses=1]
+ ret i32 %0
+}
+define i32 @foo5() nounwind readonly {
+entry:
+; CHECK-SMALL: foo5:
+; CHECK-SMALL: movl data-16777216(%rip), %eax
+; CHECK-KERNEL: foo5:
+; CHECK-KERNEL: movq $-16777216, %rax
+ %0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 -4194304), align 4 ; <i32> [#uses=1]
+ ret i32 %0
+}
diff --git a/test/CodeGen/X86/combine-lds.ll b/test/CodeGen/X86/combine-lds.ll
new file mode 100644
index 0000000..b49d081
--- /dev/null
+++ b/test/CodeGen/X86/combine-lds.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep fldl | count 1
+
+define double @doload64(i64 %x) nounwind {
+ %tmp717 = bitcast i64 %x to double
+ ret double %tmp717
+}
diff --git a/test/CodeGen/X86/combiner-aa-0.ll b/test/CodeGen/X86/combiner-aa-0.ll
new file mode 100644
index 0000000..a61ef7a
--- /dev/null
+++ b/test/CodeGen/X86/combiner-aa-0.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86-64 -combiner-global-alias-analysis -combiner-alias-analysis
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+ %struct.Hash_Key = type { [4 x i32], i32 }
+@g_flipV_hashkey = external global %struct.Hash_Key, align 16 ; <%struct.Hash_Key*> [#uses=1]
+
+define void @foo() nounwind {
+ %t0 = load i32* undef, align 16 ; <i32> [#uses=1]
+ %t1 = load i32* null, align 4 ; <i32> [#uses=1]
+ %t2 = srem i32 %t0, 32 ; <i32> [#uses=1]
+ %t3 = shl i32 1, %t2 ; <i32> [#uses=1]
+ %t4 = xor i32 %t3, %t1 ; <i32> [#uses=1]
+ store i32 %t4, i32* null, align 4
+ %t5 = getelementptr %struct.Hash_Key* @g_flipV_hashkey, i64 0, i32 0, i64 0 ; <i32*> [#uses=2]
+ %t6 = load i32* %t5, align 4 ; <i32> [#uses=1]
+ %t7 = shl i32 1, undef ; <i32> [#uses=1]
+ %t8 = xor i32 %t7, %t6 ; <i32> [#uses=1]
+ store i32 %t8, i32* %t5, align 4
+ unreachable
+}
diff --git a/test/CodeGen/X86/combiner-aa-1.ll b/test/CodeGen/X86/combiner-aa-1.ll
new file mode 100644
index 0000000..58a7129
--- /dev/null
+++ b/test/CodeGen/X86/combiner-aa-1.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s --combiner-alias-analysis --combiner-global-alias-analysis
+; PR4880
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
+
+%struct.alst_node = type { %struct.node }
+%struct.arg_node = type { %struct.node, i8*, %struct.alst_node* }
+%struct.arglst_node = type { %struct.alst_node, %struct.arg_node*, %struct.arglst_node* }
+%struct.lam_node = type { %struct.alst_node, %struct.arg_node*, %struct.alst_node* }
+%struct.node = type { i32 (...)**, %struct.node* }
+
+define i32 @._ZN8lam_node18resolve_name_clashEP8arg_nodeP9alst_node._ZNK8lam_nodeeqERK8exp_node._ZN11arglst_nodeD0Ev(%struct.lam_node* %this.this, %struct.arg_node* %outer_arg, %struct.alst_node* %env.cmp, %struct.arglst_node* %this, i32 %functionID) {
+comb_entry:
+ %.SV59 = alloca %struct.node* ; <%struct.node**> [#uses=1]
+ %0 = load i32 (...)*** null, align 4 ; <i32 (...)**> [#uses=1]
+ %1 = getelementptr inbounds i32 (...)** %0, i32 3 ; <i32 (...)**> [#uses=1]
+ %2 = load i32 (...)** %1, align 4 ; <i32 (...)*> [#uses=1]
+ store %struct.node* undef, %struct.node** %.SV59
+ %3 = bitcast i32 (...)* %2 to i32 (%struct.node*)* ; <i32 (%struct.node*)*> [#uses=1]
+ %4 = tail call i32 %3(%struct.node* undef) ; <i32> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/X86/commute-intrinsic.ll b/test/CodeGen/X86/commute-intrinsic.ll
new file mode 100644
index 0000000..d810cb1
--- /dev/null
+++ b/test/CodeGen/X86/commute-intrinsic.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -relocation-model=static | not grep movaps
+
+@a = external global <2 x i64> ; <<2 x i64>*> [#uses=1]
+
+define <2 x i64> @madd(<2 x i64> %b) nounwind {
+entry:
+ %tmp2 = load <2 x i64>* @a, align 16 ; <<2 x i64>> [#uses=1]
+ %tmp6 = bitcast <2 x i64> %b to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp9 = bitcast <2 x i64> %tmp2 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp11 = tail call <4 x i32> @llvm.x86.sse2.pmadd.wd( <8 x i16> %tmp9, <8 x i16> %tmp6 ) nounwind readnone ; <<4 x i32>> [#uses=1]
+ %tmp14 = bitcast <4 x i32> %tmp11 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp14
+}
+
+declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>) nounwind readnone
diff --git a/test/CodeGen/X86/commute-two-addr.ll b/test/CodeGen/X86/commute-two-addr.ll
new file mode 100644
index 0000000..56ea26b
--- /dev/null
+++ b/test/CodeGen/X86/commute-two-addr.ll
@@ -0,0 +1,25 @@
+; The register allocator can commute two-address instructions to avoid
+; insertion of register-register copies.
+
+; Make sure there are only 3 mov's for each testcase
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
+; RUN: grep {\\\<mov\\\>} | count 6
+
+
+target triple = "i686-pc-linux-gnu"
+@G = external global i32 ; <i32*> [#uses=2]
+
+declare void @ext(i32)
+
+define i32 @add_test(i32 %X, i32 %Y) {
+ %Z = add i32 %X, %Y ; <i32> [#uses=1]
+ store i32 %Z, i32* @G
+ ret i32 %X
+}
+
+define i32 @xor_test(i32 %X, i32 %Y) {
+ %Z = xor i32 %X, %Y ; <i32> [#uses=1]
+ store i32 %Z, i32* @G
+ ret i32 %X
+}
+
diff --git a/test/CodeGen/X86/compare-add.ll b/test/CodeGen/X86/compare-add.ll
new file mode 100644
index 0000000..358ee59
--- /dev/null
+++ b/test/CodeGen/X86/compare-add.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 | not grep add
+
+define i1 @X(i32 %X) {
+ %Y = add i32 %X, 14 ; <i32> [#uses=1]
+ %Z = icmp ne i32 %Y, 12345 ; <i1> [#uses=1]
+ ret i1 %Z
+}
+
diff --git a/test/CodeGen/X86/compare-inf.ll b/test/CodeGen/X86/compare-inf.ll
new file mode 100644
index 0000000..2be90c9
--- /dev/null
+++ b/test/CodeGen/X86/compare-inf.ll
@@ -0,0 +1,76 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+; Convert oeq and une to ole/oge/ule/uge when comparing with infinity
+; and negative infinity, because those are more efficient on x86.
+
+; CHECK: oeq_inff:
+; CHECK: ucomiss
+; CHECK: jae
+define float @oeq_inff(float %x, float %y) nounwind readonly {
+ %t0 = fcmp oeq float %x, 0x7FF0000000000000
+ %t1 = select i1 %t0, float 1.0, float %y
+ ret float %t1
+}
+
+; CHECK: oeq_inf:
+; CHECK: ucomisd
+; CHECK: jae
+define double @oeq_inf(double %x, double %y) nounwind readonly {
+ %t0 = fcmp oeq double %x, 0x7FF0000000000000
+ %t1 = select i1 %t0, double 1.0, double %y
+ ret double %t1
+}
+
+; CHECK: une_inff:
+; CHECK: ucomiss
+; CHECK: jb
+define float @une_inff(float %x, float %y) nounwind readonly {
+ %t0 = fcmp une float %x, 0x7FF0000000000000
+ %t1 = select i1 %t0, float 1.0, float %y
+ ret float %t1
+}
+
+; CHECK: une_inf:
+; CHECK: ucomisd
+; CHECK: jb
+define double @une_inf(double %x, double %y) nounwind readonly {
+ %t0 = fcmp une double %x, 0x7FF0000000000000
+ %t1 = select i1 %t0, double 1.0, double %y
+ ret double %t1
+}
+
+; CHECK: oeq_neg_inff:
+; CHECK: ucomiss
+; CHECK: jae
+define float @oeq_neg_inff(float %x, float %y) nounwind readonly {
+ %t0 = fcmp oeq float %x, 0xFFF0000000000000
+ %t1 = select i1 %t0, float 1.0, float %y
+ ret float %t1
+}
+
+; CHECK: oeq_neg_inf:
+; CHECK: ucomisd
+; CHECK: jae
+define double @oeq_neg_inf(double %x, double %y) nounwind readonly {
+ %t0 = fcmp oeq double %x, 0xFFF0000000000000
+ %t1 = select i1 %t0, double 1.0, double %y
+ ret double %t1
+}
+
+; CHECK: une_neg_inff:
+; CHECK: ucomiss
+; CHECK: jb
+define float @une_neg_inff(float %x, float %y) nounwind readonly {
+ %t0 = fcmp une float %x, 0xFFF0000000000000
+ %t1 = select i1 %t0, float 1.0, float %y
+ ret float %t1
+}
+
+; CHECK: une_neg_inf:
+; CHECK: ucomisd
+; CHECK: jb
+define double @une_neg_inf(double %x, double %y) nounwind readonly {
+ %t0 = fcmp une double %x, 0xFFF0000000000000
+ %t1 = select i1 %t0, double 1.0, double %y
+ ret double %t1
+}
diff --git a/test/CodeGen/X86/compare_folding.ll b/test/CodeGen/X86/compare_folding.ll
new file mode 100644
index 0000000..84c152d
--- /dev/null
+++ b/test/CodeGen/X86/compare_folding.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah | \
+; RUN: grep movsd | count 1
+; RUN: llc < %s -march=x86 -mcpu=yonah | \
+; RUN: grep ucomisd
+declare i1 @llvm.isunordered.f64(double, double)
+
+define i1 @test1(double %X, double %Y) {
+ %COM = fcmp uno double %X, %Y ; <i1> [#uses=1]
+ ret i1 %COM
+}
+
diff --git a/test/CodeGen/X86/compiler_used.ll b/test/CodeGen/X86/compiler_used.ll
new file mode 100644
index 0000000..be8de5e
--- /dev/null
+++ b/test/CodeGen/X86/compiler_used.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | grep no_dead_strip | count 1
+; We should have a .no_dead_strip directive for Z but not for X/Y.
+
+@X = internal global i8 4
+@Y = internal global i32 123
+@Z = internal global i8 4
+
[email protected] = appending global [1 x i8*] [ i8* @Z ], section "llvm.metadata"
[email protected]_used = appending global [2 x i8*] [ i8* @X, i8* bitcast (i32* @Y to i8*)], section "llvm.metadata"
diff --git a/test/CodeGen/X86/complex-fca.ll b/test/CodeGen/X86/complex-fca.ll
new file mode 100644
index 0000000..7e7acaa
--- /dev/null
+++ b/test/CodeGen/X86/complex-fca.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 | grep mov | count 2
+
+define void @ccosl({ x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 } %z) nounwind {
+entry:
+ %z8 = extractvalue { x86_fp80, x86_fp80 } %z, 0
+ %z9 = extractvalue { x86_fp80, x86_fp80 } %z, 1
+ %0 = fsub x86_fp80 0xK80000000000000000000, %z9
+ %insert = insertvalue { x86_fp80, x86_fp80 } undef, x86_fp80 %0, 0
+ %insert7 = insertvalue { x86_fp80, x86_fp80 } %insert, x86_fp80 %z8, 1
+ call void @ccoshl({ x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 } %insert7) nounwind
+ ret void
+}
+
+declare void @ccoshl({ x86_fp80, x86_fp80 }* noalias sret, { x86_fp80, x86_fp80 }) nounwind
diff --git a/test/CodeGen/X86/const-select.ll b/test/CodeGen/X86/const-select.ll
new file mode 100644
index 0000000..ca8cc14
--- /dev/null
+++ b/test/CodeGen/X86/const-select.ll
@@ -0,0 +1,22 @@
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin7"
+
+; RUN: llc < %s | grep {LCPI1_0(,%eax,4)}
+define float @f(i32 %x) nounwind readnone {
+entry:
+ %0 = icmp eq i32 %x, 0 ; <i1> [#uses=1]
+ %iftmp.0.0 = select i1 %0, float 4.200000e+01, float 2.300000e+01 ; <float> [#uses=1]
+ ret float %iftmp.0.0
+}
+
+; RUN: llc < %s | grep {movsbl.*(%e.x,%e.x,4), %eax}
+define signext i8 @test(i8* nocapture %P, double %F) nounwind readonly {
+entry:
+ %0 = fcmp olt double %F, 4.200000e+01 ; <i1> [#uses=1]
+ %iftmp.0.0 = select i1 %0, i32 4, i32 0 ; <i32> [#uses=1]
+ %1 = getelementptr i8* %P, i32 %iftmp.0.0 ; <i8*> [#uses=1]
+ %2 = load i8* %1, align 1 ; <i8> [#uses=1]
+ ret i8 %2
+}
+
diff --git a/test/CodeGen/X86/constant-pool-remat-0.ll b/test/CodeGen/X86/constant-pool-remat-0.ll
new file mode 100644
index 0000000..05388f9
--- /dev/null
+++ b/test/CodeGen/X86/constant-pool-remat-0.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86-64 | grep LCPI | count 3
+; RUN: llc < %s -march=x86-64 -stats -info-output-file - | grep asm-printer | grep 6
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep LCPI | count 3
+; RUN: llc < %s -march=x86 -mattr=+sse2 -stats -info-output-file - | grep asm-printer | grep 12
+
+declare float @qux(float %y)
+
+define float @array(float %a) nounwind {
+ %n = fmul float %a, 9.0
+ %m = call float @qux(float %n)
+ %o = fmul float %m, 9.0
+ ret float %o
+}
diff --git a/test/CodeGen/X86/constant-pool-sharing.ll b/test/CodeGen/X86/constant-pool-sharing.ll
new file mode 100644
index 0000000..c3e97ad
--- /dev/null
+++ b/test/CodeGen/X86/constant-pool-sharing.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+; llc should share constant pool entries between this integer vector
+; and this floating-point vector since they have the same encoding.
+
+; CHECK: LCPI1_0(%rip), %xmm0
+; CHECK: movaps %xmm0, (%rdi)
+; CHECK: movaps %xmm0, (%rsi)
+
+define void @foo(<4 x i32>* %p, <4 x float>* %q, i1 %t) nounwind {
+entry:
+ br label %loop
+loop:
+ store <4 x i32><i32 1073741824, i32 1073741824, i32 1073741824, i32 1073741824>, <4 x i32>* %p
+ store <4 x float><float 2.0, float 2.0, float 2.0, float 2.0>, <4 x float>* %q
+ br i1 %t, label %loop, label %ret
+ret:
+ ret void
+}
diff --git a/test/CodeGen/X86/constpool.ll b/test/CodeGen/X86/constpool.ll
new file mode 100644
index 0000000..2aac486
--- /dev/null
+++ b/test/CodeGen/X86/constpool.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s
+; RUN: llc < %s -fast-isel
+; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -fast-isel -march=x86-64
+; PR4466
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.7"
+
+define i32 @main() nounwind {
+entry:
+ %0 = fcmp oeq float undef, 0x7FF0000000000000 ; <i1> [#uses=1]
+ %1 = zext i1 %0 to i32 ; <i32> [#uses=1]
+ store i32 %1, i32* undef, align 4
+ ret i32 undef
+}
diff --git a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
new file mode 100644
index 0000000..8e38fe3
--- /dev/null
+++ b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=x86-64 -o %t -stats -info-output-file - | \
+; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 10
+; RUN: grep {leal 1(\%rsi),} %t
+
+define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2, i8* %ptr) nounwind optsize {
+entry:
+ %0 = add i32 %i2, 1 ; <i32> [#uses=1]
+ %1 = sext i32 %0 to i64 ; <i64> [#uses=1]
+ %2 = getelementptr i8* %ptr, i64 %1 ; <i8*> [#uses=1]
+ %3 = load i8* %2, align 1 ; <i8> [#uses=1]
+ %4 = icmp eq i8 0, %3 ; <i1> [#uses=1]
+ br i1 %4, label %bb3, label %bb34
+
+bb3: ; preds = %entry
+ %5 = add i32 %i2, 4 ; <i32> [#uses=0]
+ %6 = trunc i32 %5 to i8
+ ret i8 %6
+
+bb34: ; preds = %entry
+ ret i8 0
+}
+
diff --git a/test/CodeGen/X86/copysign-zero.ll b/test/CodeGen/X86/copysign-zero.ll
new file mode 100644
index 0000000..47522d8
--- /dev/null
+++ b/test/CodeGen/X86/copysign-zero.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s | not grep orpd
+; RUN: llc < %s | grep andpd | count 1
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin8"
+
+define double @test(double %X) nounwind {
+entry:
+ %tmp2 = tail call double @copysign( double 0.000000e+00, double %X ) nounwind readnone ; <double> [#uses=1]
+ ret double %tmp2
+}
+
+declare double @copysign(double, double) nounwind readnone
+
diff --git a/test/CodeGen/X86/critical-edge-split.ll b/test/CodeGen/X86/critical-edge-split.ll
new file mode 100644
index 0000000..4fe554d
--- /dev/null
+++ b/test/CodeGen/X86/critical-edge-split.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -tailcallopt=false -stats -info-output-file - | grep asm-printer | grep 31
+
+ %CC = type { %Register }
+ %II = type { %"struct.XX::II::$_74" }
+ %JITFunction = type %YYValue* (%CC*, %YYValue**)
+ %YYValue = type { i32 (...)** }
+ %Register = type { %"struct.XX::ByteCodeFeatures" }
+ %"struct.XX::ByteCodeFeatures" = type { i32 }
+ %"struct.XX::II::$_74" = type { i8* }
[email protected] = appending global [1 x i8*] [ i8* bitcast (%JITFunction* @loop to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define %YYValue* @loop(%CC*, %YYValue**) nounwind {
+; <label>:2
+ %3 = getelementptr %CC* %0, i32 -9 ; <%CC*> [#uses=1]
+ %4 = bitcast %CC* %3 to %YYValue** ; <%YYValue**> [#uses=2]
+ %5 = load %YYValue** %4 ; <%YYValue*> [#uses=3]
+ %unique_1.i = ptrtoint %YYValue* %5 to i1 ; <i1> [#uses=1]
+ br i1 %unique_1.i, label %loop, label %11
+
+loop: ; preds = %6, %2
+ %.1 = phi %YYValue* [ inttoptr (i32 1 to %YYValue*), %2 ], [ %intAddValue, %6 ] ; <%YYValue*> [#uses=3]
+ %immediateCmp = icmp slt %YYValue* %.1, %5 ; <i1> [#uses=1]
+ br i1 %immediateCmp, label %6, label %8
+
+; <label>:6 ; preds = %loop
+ %lhsInt = ptrtoint %YYValue* %.1 to i32 ; <i32> [#uses=1]
+ %7 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %lhsInt, i32 2) ; <{ i32, i1 }> [#uses=2]
+ %intAdd = extractvalue { i32, i1 } %7, 0 ; <i32> [#uses=1]
+ %intAddValue = inttoptr i32 %intAdd to %YYValue* ; <%YYValue*> [#uses=1]
+ %intAddOverflow = extractvalue { i32, i1 } %7, 1 ; <i1> [#uses=1]
+ br i1 %intAddOverflow, label %.loopexit, label %loop
+
+; <label>:8 ; preds = %loop
+ ret %YYValue* inttoptr (i32 10 to %YYValue*)
+
+.loopexit: ; preds = %6
+ %9 = bitcast %CC* %0 to %YYValue** ; <%YYValue**> [#uses=1]
+ store %YYValue* %.1, %YYValue** %9
+ store %YYValue* %5, %YYValue** %4
+ %10 = call fastcc %YYValue* @foobar(%II* inttoptr (i32 3431104 to %II*), %CC* %0, %YYValue** %1) ; <%YYValue*> [#uses=1]
+ ret %YYValue* %10
+
+; <label>:11 ; preds = %2
+ %12 = call fastcc %YYValue* @foobar(%II* inttoptr (i32 3431080 to %II*), %CC* %0, %YYValue** %1) ; <%YYValue*> [#uses=1]
+ ret %YYValue* %12
+}
+
+declare fastcc %YYValue* @foobar(%II*, %CC*, %YYValue**) nounwind
+
+declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) nounwind
diff --git a/test/CodeGen/X86/cstring.ll b/test/CodeGen/X86/cstring.ll
new file mode 100644
index 0000000..5b5a766
--- /dev/null
+++ b/test/CodeGen/X86/cstring.ll
@@ -0,0 +1,4 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | not grep comm
+; rdar://6479858
+
+@str1 = internal constant [1 x i8] zeroinitializer
diff --git a/test/CodeGen/X86/dag-rauw-cse.ll b/test/CodeGen/X86/dag-rauw-cse.ll
new file mode 100644
index 0000000..edcfeb7
--- /dev/null
+++ b/test/CodeGen/X86/dag-rauw-cse.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 | grep {orl \$1}
+; PR3018
+
+define i32 @test(i32 %A) nounwind {
+ %B = or i32 %A, 1
+ %C = or i32 %B, 1
+ %D = and i32 %C, 7057
+ ret i32 %D
+}
diff --git a/test/CodeGen/X86/dagcombine-buildvector.ll b/test/CodeGen/X86/dagcombine-buildvector.ll
new file mode 100644
index 0000000..c0ee2ac
--- /dev/null
+++ b/test/CodeGen/X86/dagcombine-buildvector.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86 -mcpu=penryn -disable-mmx -o %t
+; RUN: grep unpcklpd %t | count 1
+; RUN: grep movapd %t | count 1
+; RUN: grep movaps %t | count 1
+
+; Shows a dag combine bug that will generate an illegal build vector
+; with v2i64 build_vector i32, i32.
+
+define void @test(<2 x double>* %dst, <4 x double> %src) nounwind {
+entry:
+ %tmp7.i = shufflevector <4 x double> %src, <4 x double> undef, <2 x i32> < i32 0, i32 2 >
+ store <2 x double> %tmp7.i, <2 x double>* %dst
+ ret void
+}
+
+define void @test2(<4 x i16>* %src, <4 x i32>* %dest) nounwind {
+entry:
+ %tmp1 = load <4 x i16>* %src
+ %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+ %0 = tail call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3)
+ store <4 x i32> %0, <4 x i32>* %dest
+ ret void
+}
+
+declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone
diff --git a/test/CodeGen/X86/dagcombine-cse.ll b/test/CodeGen/X86/dagcombine-cse.ll
new file mode 100644
index 0000000..c3c7990
--- /dev/null
+++ b/test/CodeGen/X86/dagcombine-cse.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -stats |& grep asm-printer | grep 14
+
+define i32 @t(i8* %ref_frame_ptr, i32 %ref_frame_stride, i32 %idxX, i32 %idxY) nounwind {
+entry:
+ %tmp7 = mul i32 %idxY, %ref_frame_stride ; <i32> [#uses=2]
+ %tmp9 = add i32 %tmp7, %idxX ; <i32> [#uses=1]
+ %tmp11 = getelementptr i8* %ref_frame_ptr, i32 %tmp9 ; <i8*> [#uses=1]
+ %tmp1112 = bitcast i8* %tmp11 to i32* ; <i32*> [#uses=1]
+ %tmp13 = load i32* %tmp1112, align 4 ; <i32> [#uses=1]
+ %tmp18 = add i32 %idxX, 4 ; <i32> [#uses=1]
+ %tmp20.sum = add i32 %tmp18, %tmp7 ; <i32> [#uses=1]
+ %tmp21 = getelementptr i8* %ref_frame_ptr, i32 %tmp20.sum ; <i8*> [#uses=1]
+ %tmp2122 = bitcast i8* %tmp21 to i16* ; <i16*> [#uses=1]
+ %tmp23 = load i16* %tmp2122, align 2 ; <i16> [#uses=1]
+ %tmp2425 = zext i16 %tmp23 to i64 ; <i64> [#uses=1]
+ %tmp26 = shl i64 %tmp2425, 32 ; <i64> [#uses=1]
+ %tmp2728 = zext i32 %tmp13 to i64 ; <i64> [#uses=1]
+ %tmp29 = or i64 %tmp26, %tmp2728 ; <i64> [#uses=1]
+ %tmp3454 = bitcast i64 %tmp29 to double ; <double> [#uses=1]
+ %tmp35 = insertelement <2 x double> undef, double %tmp3454, i32 0 ; <<2 x double>> [#uses=1]
+ %tmp36 = insertelement <2 x double> %tmp35, double 0.000000e+00, i32 1 ; <<2 x double>> [#uses=1]
+ %tmp42 = bitcast <2 x double> %tmp36 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp43 = shufflevector <8 x i16> %tmp42, <8 x i16> undef, <8 x i32> < i32 0, i32 1, i32 1, i32 2, i32 4, i32 5, i32 6, i32 7 > ; <<8 x i16>> [#uses=1]
+ %tmp47 = bitcast <8 x i16> %tmp43 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp48 = extractelement <4 x i32> %tmp47, i32 0 ; <i32> [#uses=1]
+ ret i32 %tmp48
+}
diff --git a/test/CodeGen/X86/darwin-bzero.ll b/test/CodeGen/X86/darwin-bzero.ll
new file mode 100644
index 0000000..a9573cf
--- /dev/null
+++ b/test/CodeGen/X86/darwin-bzero.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin10 | grep __bzero
+
+declare void @llvm.memset.i32(i8*, i8, i32, i32)
+
+define void @foo(i8* %p, i32 %len) {
+ call void @llvm.memset.i32(i8* %p, i8 0, i32 %len, i32 1)
+ ret void
+}
diff --git a/test/CodeGen/X86/darwin-no-dead-strip.ll b/test/CodeGen/X86/darwin-no-dead-strip.ll
new file mode 100644
index 0000000..452d1f8
--- /dev/null
+++ b/test/CodeGen/X86/darwin-no-dead-strip.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s | grep no_dead_strip
+
+target datalayout = "e-p:32:32"
+target triple = "i686-apple-darwin8.7.2"
+@x = weak global i32 0 ; <i32*> [#uses=1]
[email protected] = appending global [1 x i8*] [ i8* bitcast (i32* @x to i8*) ] ; <[1 x i8*]*> [#uses=0]
+
diff --git a/test/CodeGen/X86/darwin-quote.ll b/test/CodeGen/X86/darwin-quote.ll
new file mode 100644
index 0000000..8fddc11
--- /dev/null
+++ b/test/CodeGen/X86/darwin-quote.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
+
+
+define internal i64 @baz() nounwind {
+ %tmp = load i64* @"+x"
+ ret i64 %tmp
+; CHECK: _baz:
+; CHECK: movl "L_+x$non_lazy_ptr", %ecx
+}
+
+
+@"+x" = external global i64
+
+; CHECK: "L_+x$non_lazy_ptr":
+; CHECK: .indirect_symbol "_+x"
diff --git a/test/CodeGen/X86/darwin-stub.ll b/test/CodeGen/X86/darwin-stub.ll
new file mode 100644
index 0000000..b4d2e1a
--- /dev/null
+++ b/test/CodeGen/X86/darwin-stub.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep stub
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | not grep stub
+
+@"\01LC" = internal constant [13 x i8] c"Hello World!\00" ; <[13 x i8]*> [#uses=1]
+
+define i32 @main() nounwind {
+entry:
+ %0 = tail call i32 @puts(i8* getelementptr ([13 x i8]* @"\01LC", i32 0, i32 0)) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
+
+declare i32 @puts(i8*)
diff --git a/test/CodeGen/X86/dg.exp b/test/CodeGen/X86/dg.exp
new file mode 100644
index 0000000..629a147
--- /dev/null
+++ b/test/CodeGen/X86/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target X86] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/X86/discontiguous-loops.ll b/test/CodeGen/X86/discontiguous-loops.ll
new file mode 100644
index 0000000..479c450
--- /dev/null
+++ b/test/CodeGen/X86/discontiguous-loops.ll
@@ -0,0 +1,72 @@
+; RUN: llc -verify-loop-info -verify-dom-info -march=x86-64 < %s
+; PR5243
+
[email protected] = external constant [37 x i8], align 8 ; <[37 x i8]*> [#uses=1]
+
+define void @foo() nounwind {
+bb:
+ br label %ybb1
+
+ybb1: ; preds = %yybb13, %xbb6, %bb
+ switch i32 undef, label %bb18 [
+ i32 150, label %ybb2
+ i32 151, label %bb17
+ i32 152, label %bb19
+ i32 157, label %ybb8
+ ]
+
+ybb2: ; preds = %ybb1
+ %tmp = icmp eq i8** undef, null ; <i1> [#uses=1]
+ br i1 %tmp, label %bb3, label %xbb6
+
+bb3: ; preds = %ybb2
+ unreachable
+
+xbb4: ; preds = %xbb6
+ store i32 0, i32* undef, align 8
+ br i1 undef, label %xbb6, label %bb5
+
+bb5: ; preds = %xbb4
+ call fastcc void @decl_mode_check_failed() nounwind
+ unreachable
+
+xbb6: ; preds = %xbb4, %ybb2
+ %tmp7 = icmp slt i32 undef, 0 ; <i1> [#uses=1]
+ br i1 %tmp7, label %xbb4, label %ybb1
+
+ybb8: ; preds = %ybb1
+ %tmp9 = icmp eq i8** undef, null ; <i1> [#uses=1]
+ br i1 %tmp9, label %bb10, label %ybb12
+
+bb10: ; preds = %ybb8
+ %tmp11 = load i8** undef, align 8 ; <i8*> [#uses=1]
+ call void (i8*, ...)* @fatal(i8* getelementptr inbounds ([37 x i8]* @.str96, i64 0, i64 0), i8* %tmp11) nounwind
+ unreachable
+
+ybb12: ; preds = %ybb8
+ br i1 undef, label %bb15, label %ybb13
+
+ybb13: ; preds = %ybb12
+ %tmp14 = icmp sgt i32 undef, 0 ; <i1> [#uses=1]
+ br i1 %tmp14, label %bb16, label %ybb1
+
+bb15: ; preds = %ybb12
+ call void (i8*, ...)* @fatal(i8* getelementptr inbounds ([37 x i8]* @.str96, i64 0, i64 0), i8* undef) nounwind
+ unreachable
+
+bb16: ; preds = %ybb13
+ unreachable
+
+bb17: ; preds = %ybb1
+ unreachable
+
+bb18: ; preds = %ybb1
+ unreachable
+
+bb19: ; preds = %ybb1
+ unreachable
+}
+
+declare void @fatal(i8*, ...)
+
+declare fastcc void @decl_mode_check_failed() nounwind
diff --git a/test/CodeGen/X86/div_const.ll b/test/CodeGen/X86/div_const.ll
new file mode 100644
index 0000000..f0ada41
--- /dev/null
+++ b/test/CodeGen/X86/div_const.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86 | grep 365384439
+
+define i32 @f9188_mul365384439_shift27(i32 %A) {
+ %tmp1 = udiv i32 %A, 1577682821 ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
diff --git a/test/CodeGen/X86/divrem.ll b/test/CodeGen/X86/divrem.ll
new file mode 100644
index 0000000..e86b52f
--- /dev/null
+++ b/test/CodeGen/X86/divrem.ll
@@ -0,0 +1,58 @@
+; RUN: llc < %s -march=x86-64 | grep div | count 8
+
+define void @si64(i64 %x, i64 %y, i64* %p, i64* %q) {
+ %r = sdiv i64 %x, %y
+ %t = srem i64 %x, %y
+ store i64 %r, i64* %p
+ store i64 %t, i64* %q
+ ret void
+}
+define void @si32(i32 %x, i32 %y, i32* %p, i32* %q) {
+ %r = sdiv i32 %x, %y
+ %t = srem i32 %x, %y
+ store i32 %r, i32* %p
+ store i32 %t, i32* %q
+ ret void
+}
+define void @si16(i16 %x, i16 %y, i16* %p, i16* %q) {
+ %r = sdiv i16 %x, %y
+ %t = srem i16 %x, %y
+ store i16 %r, i16* %p
+ store i16 %t, i16* %q
+ ret void
+}
+define void @si8(i8 %x, i8 %y, i8* %p, i8* %q) {
+ %r = sdiv i8 %x, %y
+ %t = srem i8 %x, %y
+ store i8 %r, i8* %p
+ store i8 %t, i8* %q
+ ret void
+}
+define void @ui64(i64 %x, i64 %y, i64* %p, i64* %q) {
+ %r = udiv i64 %x, %y
+ %t = urem i64 %x, %y
+ store i64 %r, i64* %p
+ store i64 %t, i64* %q
+ ret void
+}
+define void @ui32(i32 %x, i32 %y, i32* %p, i32* %q) {
+ %r = udiv i32 %x, %y
+ %t = urem i32 %x, %y
+ store i32 %r, i32* %p
+ store i32 %t, i32* %q
+ ret void
+}
+define void @ui16(i16 %x, i16 %y, i16* %p, i16* %q) {
+ %r = udiv i16 %x, %y
+ %t = urem i16 %x, %y
+ store i16 %r, i16* %p
+ store i16 %t, i16* %q
+ ret void
+}
+define void @ui8(i8 %x, i8 %y, i8* %p, i8* %q) {
+ %r = udiv i8 %x, %y
+ %t = urem i8 %x, %y
+ store i8 %r, i8* %p
+ store i8 %t, i8* %q
+ ret void
+}
diff --git a/test/CodeGen/X86/dll-linkage.ll b/test/CodeGen/X86/dll-linkage.ll
new file mode 100644
index 0000000..c634c7e
--- /dev/null
+++ b/test/CodeGen/X86/dll-linkage.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=i386-pc-mingw32 | FileCheck %s
+
+declare dllimport void @foo()
+
+define void @bar() nounwind {
+; CHECK: call *__imp__foo
+ call void @foo()
+ ret void
+}
diff --git a/test/CodeGen/X86/dollar-name.ll b/test/CodeGen/X86/dollar-name.ll
new file mode 100644
index 0000000..3b26319
--- /dev/null
+++ b/test/CodeGen/X86/dollar-name.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux | FileCheck %s
+; PR1339
+
+@"$bar" = global i32 zeroinitializer
+@"$qux" = external global i32
+
+define i32 @"$foo"() nounwind {
+; CHECK: movl ($bar),
+; CHECK: addl ($qux),
+; CHECK: call ($hen)
+ %m = load i32* @"$bar"
+ %n = load i32* @"$qux"
+ %t = add i32 %m, %n
+ %u = call i32 @"$hen"(i32 %t)
+ ret i32 %u
+}
+
+declare i32 @"$hen"(i32 %a)
diff --git a/test/CodeGen/X86/dyn-stackalloc.ll b/test/CodeGen/X86/dyn-stackalloc.ll
new file mode 100644
index 0000000..1df0920
--- /dev/null
+++ b/test/CodeGen/X86/dyn-stackalloc.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86 | not egrep {\\\$4294967289|-7}
+; RUN: llc < %s -march=x86 | egrep {\\\$4294967280|-16}
+; RUN: llc < %s -march=x86-64 | grep {\\-16}
+
+define void @t() nounwind {
+A:
+ br label %entry
+
+entry:
+ %m1 = alloca i32, align 4
+ %m2 = alloca [7 x i8], align 16
+ call void @s( i32* %m1, [7 x i8]* %m2 )
+ ret void
+}
+
+declare void @s(i32*, [7 x i8]*)
diff --git a/test/CodeGen/X86/empty-struct-return-type.ll b/test/CodeGen/X86/empty-struct-return-type.ll
new file mode 100644
index 0000000..34cd5d9
--- /dev/null
+++ b/test/CodeGen/X86/empty-struct-return-type.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86-64 | grep call
+; PR4688
+
+; Return types can be empty structs, which can be awkward.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @_ZN15QtSharedPointer22internalSafetyCheckAddEPVKv(i8* %ptr) {
+entry:
+ %0 = call { } @_ZNK5QHashIPv15QHashDummyValueE5valueERKS0_(i8** undef) ; <{ }> [#uses=0]
+ ret void
+}
+
+declare hidden { } @_ZNK5QHashIPv15QHashDummyValueE5valueERKS0_(i8** nocapture) nounwind
diff --git a/test/CodeGen/X86/epilogue.ll b/test/CodeGen/X86/epilogue.ll
new file mode 100644
index 0000000..52dcb61
--- /dev/null
+++ b/test/CodeGen/X86/epilogue.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 | not grep lea
+; RUN: llc < %s -march=x86 | grep {movl %ebp}
+
+declare void @bar(<2 x i64>* %n)
+
+define void @foo(i64 %h) {
+ %k = trunc i64 %h to i32
+ %p = alloca <2 x i64>, i32 %k
+ call void @bar(<2 x i64>* %p)
+ ret void
+}
diff --git a/test/CodeGen/X86/extend.ll b/test/CodeGen/X86/extend.ll
new file mode 100644
index 0000000..9553b1b
--- /dev/null
+++ b/test/CodeGen/X86/extend.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | grep movzx | count 1
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | grep movsx | count 1
+
+@G1 = internal global i8 0 ; <i8*> [#uses=1]
+@G2 = internal global i8 0 ; <i8*> [#uses=1]
+
+define i16 @test1() {
+ %tmp.0 = load i8* @G1 ; <i8> [#uses=1]
+ %tmp.3 = zext i8 %tmp.0 to i16 ; <i16> [#uses=1]
+ ret i16 %tmp.3
+}
+
+define i16 @test2() {
+ %tmp.0 = load i8* @G2 ; <i8> [#uses=1]
+ %tmp.3 = sext i8 %tmp.0 to i16 ; <i16> [#uses=1]
+ ret i16 %tmp.3
+}
+
diff --git a/test/CodeGen/X86/extern_weak.ll b/test/CodeGen/X86/extern_weak.ll
new file mode 100644
index 0000000..01e32aa
--- /dev/null
+++ b/test/CodeGen/X86/extern_weak.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin | grep weak_reference | count 2
+
+@Y = global i32 (i8*)* @X ; <i32 (i8*)**> [#uses=0]
+
+declare extern_weak i32 @X(i8*)
+
+define void @bar() {
+ tail call void (...)* @foo( )
+ ret void
+}
+
+declare extern_weak void @foo(...)
+
diff --git a/test/CodeGen/X86/extmul128.ll b/test/CodeGen/X86/extmul128.ll
new file mode 100644
index 0000000..9b59829
--- /dev/null
+++ b/test/CodeGen/X86/extmul128.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86-64 | grep mul | count 2
+
+define i128 @i64_sext_i128(i64 %a, i64 %b) {
+ %aa = sext i64 %a to i128
+ %bb = sext i64 %b to i128
+ %cc = mul i128 %aa, %bb
+ ret i128 %cc
+}
+define i128 @i64_zext_i128(i64 %a, i64 %b) {
+ %aa = zext i64 %a to i128
+ %bb = zext i64 %b to i128
+ %cc = mul i128 %aa, %bb
+ ret i128 %cc
+}
diff --git a/test/CodeGen/X86/extmul64.ll b/test/CodeGen/X86/extmul64.ll
new file mode 100644
index 0000000..9e20ded
--- /dev/null
+++ b/test/CodeGen/X86/extmul64.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 | grep mul | count 2
+
+define i64 @i32_sext_i64(i32 %a, i32 %b) {
+ %aa = sext i32 %a to i64
+ %bb = sext i32 %b to i64
+ %cc = mul i64 %aa, %bb
+ ret i64 %cc
+}
+define i64 @i32_zext_i64(i32 %a, i32 %b) {
+ %aa = zext i32 %a to i64
+ %bb = zext i32 %b to i64
+ %cc = mul i64 %aa, %bb
+ ret i64 %cc
+}
diff --git a/test/CodeGen/X86/extract-combine.ll b/test/CodeGen/X86/extract-combine.ll
new file mode 100644
index 0000000..2040e87
--- /dev/null
+++ b/test/CodeGen/X86/extract-combine.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86-64 -mcpu=core2 -o %t
+; RUN: not grep unpcklps %t
+
+define i32 @foo() nounwind {
+entry:
+ %tmp74.i25762 = shufflevector <16 x float> zeroinitializer, <16 x float> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19> ; <<16 x float>> [#uses=1]
+ %tmp518 = shufflevector <16 x float> %tmp74.i25762, <16 x float> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15> ; <<4 x float>> [#uses=1]
+ %movss.i25611 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp518, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
+ %conv3.i25615 = shufflevector <4 x float> %movss.i25611, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1]
+ %sub.i25620 = fsub <4 x float> %conv3.i25615, zeroinitializer ; <<4 x float>> [#uses=1]
+ %mul.i25621 = fmul <4 x float> zeroinitializer, %sub.i25620 ; <<4 x float>> [#uses=1]
+ %add.i25622 = fadd <4 x float> zeroinitializer, %mul.i25621 ; <<4 x float>> [#uses=1]
+ store <4 x float> %add.i25622, <4 x float>* null
+ unreachable
+}
diff --git a/test/CodeGen/X86/extract-extract.ll b/test/CodeGen/X86/extract-extract.ll
new file mode 100644
index 0000000..ad79ab9
--- /dev/null
+++ b/test/CodeGen/X86/extract-extract.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 >/dev/null
+; PR4699
+
+; Handle this extractvalue-of-extractvalue case without getting in
+; trouble with CSE in DAGCombine.
+
+ %cc = type { %crd }
+ %cr = type { i32 }
+ %crd = type { i64, %cr* }
+ %pp = type { %cc }
+
+define fastcc void @foo(%pp* nocapture byval %p_arg) {
+entry:
+ %tmp2 = getelementptr %pp* %p_arg, i64 0, i32 0 ; <%cc*> [#uses=
+ %tmp3 = load %cc* %tmp2 ; <%cc> [#uses=1]
+ %tmp34 = extractvalue %cc %tmp3, 0 ; <%crd> [#uses=1]
+ %tmp345 = extractvalue %crd %tmp34, 0 ; <i64> [#uses=1]
+ %.ptr.i = load %cr** undef ; <%cr*> [#uses=0]
+ %tmp15.i = shl i64 %tmp345, 3 ; <i64> [#uses=0]
+ store %cr* undef, %cr** undef
+ ret void
+}
+
+
diff --git a/test/CodeGen/X86/extractelement-from-arg.ll b/test/CodeGen/X86/extractelement-from-arg.ll
new file mode 100644
index 0000000..4ea37f0
--- /dev/null
+++ b/test/CodeGen/X86/extractelement-from-arg.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse2
+
+define void @test(float* %R, <4 x float> %X) nounwind {
+ %tmp = extractelement <4 x float> %X, i32 3
+ store float %tmp, float* %R
+ ret void
+}
diff --git a/test/CodeGen/X86/extractelement-load.ll b/test/CodeGen/X86/extractelement-load.ll
new file mode 100644
index 0000000..ee57d9b
--- /dev/null
+++ b/test/CodeGen/X86/extractelement-load.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=yonah | not grep movd
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | not grep movd
+
+define i32 @t(<2 x i64>* %val) nounwind {
+ %tmp2 = load <2 x i64>* %val, align 16 ; <<2 x i64>> [#uses=1]
+ %tmp3 = bitcast <2 x i64> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp4 = extractelement <4 x i32> %tmp3, i32 2 ; <i32> [#uses=1]
+ ret i32 %tmp4
+}
diff --git a/test/CodeGen/X86/extractelement-shuffle.ll b/test/CodeGen/X86/extractelement-shuffle.ll
new file mode 100644
index 0000000..d1ba9a8
--- /dev/null
+++ b/test/CodeGen/X86/extractelement-shuffle.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s
+
+; Examples that exhibits a bug in DAGCombine. The case is triggered by the
+; following program. The bug is DAGCombine assumes that the bit convert
+; preserves the number of elements so the optimization code tries to read
+; through the 3rd mask element, which doesn't exist.
+define i32 @update(<2 x i64> %val1, <2 x i64> %val2) nounwind readnone {
+entry:
+ %shuf = shufflevector <2 x i64> %val1, <2 x i64> %val2, <2 x i32> <i32 0, i32 3>
+ %bit = bitcast <2 x i64> %shuf to <4 x i32>
+ %res = extractelement <4 x i32> %bit, i32 3
+ ret i32 %res
+}
diff --git a/test/CodeGen/X86/extractps.ll b/test/CodeGen/X86/extractps.ll
new file mode 100644
index 0000000..14778f0
--- /dev/null
+++ b/test/CodeGen/X86/extractps.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=x86 -mcpu=penryn > %t
+; RUN: not grep movd %t
+; RUN: grep {movss %xmm} %t | count 1
+; RUN: grep {extractps \\\$1, %xmm0, } %t | count 1
+; PR2647
+
+external global float, align 16 ; <float*>:0 [#uses=2]
+
+define internal void @""() nounwind {
+ load float* @0, align 16 ; <float>:1 [#uses=1]
+ insertelement <4 x float> undef, float %1, i32 0 ; <<4 x float>>:2 [#uses=1]
+ call <4 x float> @llvm.x86.sse.rsqrt.ss( <4 x float> %2 ) ; <<4 x float>>:3 [#uses=1]
+ extractelement <4 x float> %3, i32 0 ; <float>:4 [#uses=1]
+ store float %4, float* @0, align 16
+ ret void
+}
+define internal void @""() nounwind {
+ load float* @0, align 16 ; <float>:1 [#uses=1]
+ insertelement <4 x float> undef, float %1, i32 1 ; <<4 x float>>:2 [#uses=1]
+ call <4 x float> @llvm.x86.sse.rsqrt.ss( <4 x float> %2 ) ; <<4 x float>>:3 [#uses=1]
+ extractelement <4 x float> %3, i32 1 ; <float>:4 [#uses=1]
+ store float %4, float* @0, align 16
+ ret void
+}
+
+declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
+
diff --git a/test/CodeGen/X86/fabs.ll b/test/CodeGen/X86/fabs.ll
new file mode 100644
index 0000000..54947c3
--- /dev/null
+++ b/test/CodeGen/X86/fabs.ll
@@ -0,0 +1,28 @@
+; Make sure this testcase codegens to the fabs instruction, not a call to fabsf
+; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3,-sse | grep fabs\$ | \
+; RUN: count 2
+; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
+; RUN: grep fabs\$ | count 3
+
+declare float @fabsf(float)
+
+declare x86_fp80 @fabsl(x86_fp80)
+
+define float @test1(float %X) {
+ %Y = call float @fabsf(float %X)
+ ret float %Y
+}
+
+define double @test2(double %X) {
+ %Y = fcmp oge double %X, -0.0
+ %Z = fsub double -0.0, %X
+ %Q = select i1 %Y, double %X, double %Z
+ ret double %Q
+}
+
+define x86_fp80 @test3(x86_fp80 %X) {
+ %Y = call x86_fp80 @fabsl(x86_fp80 %X)
+ ret x86_fp80 %Y
+}
+
+
diff --git a/test/CodeGen/X86/fast-cc-callee-pops.ll b/test/CodeGen/X86/fast-cc-callee-pops.ll
new file mode 100644
index 0000000..5e88ed7
--- /dev/null
+++ b/test/CodeGen/X86/fast-cc-callee-pops.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -mcpu=yonah | grep {ret 20}
+
+; Check that a fastcc function pops its stack variables before returning.
+
+define x86_fastcallcc void @func(i64 %X, i64 %Y, float %G, double %Z) nounwind {
+ ret void
+}
diff --git a/test/CodeGen/X86/fast-cc-merge-stack-adj.ll b/test/CodeGen/X86/fast-cc-merge-stack-adj.ll
new file mode 100644
index 0000000..e151821
--- /dev/null
+++ b/test/CodeGen/X86/fast-cc-merge-stack-adj.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
+; RUN: grep {add ESP, 8}
+
+target triple = "i686-pc-linux-gnu"
+
+declare x86_fastcallcc void @func(i32*, i64)
+
+define x86_fastcallcc void @caller(i32, i64) {
+ %X = alloca i32 ; <i32*> [#uses=1]
+ call x86_fastcallcc void @func( i32* %X, i64 0 )
+ ret void
+}
+
diff --git a/test/CodeGen/X86/fast-cc-pass-in-regs.ll b/test/CodeGen/X86/fast-cc-pass-in-regs.ll
new file mode 100644
index 0000000..fe96c0c
--- /dev/null
+++ b/test/CodeGen/X86/fast-cc-pass-in-regs.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
+; RUN: grep {mov EDX, 1}
+; check that fastcc is passing stuff in regs.
+
+declare x86_fastcallcc i64 @callee(i64)
+
+define i64 @caller() {
+ %X = call x86_fastcallcc i64 @callee( i64 4294967299 ) ; <i64> [#uses=1]
+ ret i64 %X
+}
+
+define x86_fastcallcc i64 @caller2(i64 %X) {
+ ret i64 %X
+}
+
diff --git a/test/CodeGen/X86/fast-isel-bail.ll b/test/CodeGen/X86/fast-isel-bail.ll
new file mode 100644
index 0000000..9072c5c
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-bail.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 -O0
+
+; This file is for regression tests for cases where FastISel needs
+; to gracefully bail out and let SelectionDAGISel take over.
+
+ type { i64, i8* } ; type %0
+
+declare void @bar(%0)
+
+define fastcc void @foo() nounwind {
+entry:
+ call void @bar(%0 zeroinitializer)
+ unreachable
+}
diff --git a/test/CodeGen/X86/fast-isel-bc.ll b/test/CodeGen/X86/fast-isel-bc.ll
new file mode 100644
index 0000000..f2696ce
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-bc.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -O0 -march=x86-64 -mattr=+mmx | FileCheck %s
+; PR4684
+
+target datalayout =
+"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin9.8"
+
+declare void @func2(<1 x i64>)
+
+define void @func1() nounwind {
+
+; This isn't spectacular, but it's MMX code at -O0...
+; CHECK: movl $2, %eax
+; CHECK: movd %rax, %mm0
+; CHECK: movd %mm0, %rdi
+
+ call void @func2(<1 x i64> <i64 2>)
+ ret void
+}
diff --git a/test/CodeGen/X86/fast-isel-call.ll b/test/CodeGen/X86/fast-isel-call.ll
new file mode 100644
index 0000000..5fcdbbb
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-call.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -fast-isel -march=x86 | grep and
+
+define i32 @t() nounwind {
+tak:
+ %tmp = call i1 @foo()
+ br i1 %tmp, label %BB1, label %BB2
+BB1:
+ ret i32 1
+BB2:
+ ret i32 0
+}
+
+declare i1 @foo() zeroext nounwind
diff --git a/test/CodeGen/X86/fast-isel-constpool.ll b/test/CodeGen/X86/fast-isel-constpool.ll
new file mode 100644
index 0000000..84d10f3
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-constpool.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -fast-isel | grep {LCPI1_0(%rip)}
+; Make sure fast isel uses rip-relative addressing when required.
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin9.0"
+
+define i32 @f0(double %x) nounwind {
+entry:
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ %x.addr = alloca double ; <double*> [#uses=2]
+ store double %x, double* %x.addr
+ %tmp = load double* %x.addr ; <double> [#uses=1]
+ %cmp = fcmp olt double %tmp, 8.500000e-01 ; <i1> [#uses=1]
+ %conv = zext i1 %cmp to i32 ; <i32> [#uses=1]
+ store i32 %conv, i32* %retval
+ %0 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %0
+}
diff --git a/test/CodeGen/X86/fast-isel-fneg.ll b/test/CodeGen/X86/fast-isel-fneg.ll
new file mode 100644
index 0000000..5ffd48b
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-fneg.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86-64 | FileCheck %s
+; RUN: llc < %s -fast-isel -march=x86 -mattr=+sse2 | grep xor | count 2
+
+; CHECK: doo:
+; CHECK: xor
+define double @doo(double %x) nounwind {
+ %y = fsub double -0.0, %x
+ ret double %y
+}
+
+; CHECK: foo:
+; CHECK: xor
+define float @foo(float %x) nounwind {
+ %y = fsub float -0.0, %x
+ ret float %y
+}
diff --git a/test/CodeGen/X86/fast-isel-gep.ll b/test/CodeGen/X86/fast-isel-gep.ll
new file mode 100644
index 0000000..5b8acec
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-gep.ll
@@ -0,0 +1,53 @@
+; RUN: llc < %s -march=x86-64 -O0 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -march=x86 -O0 | FileCheck %s --check-prefix=X32
+
+; GEP indices are interpreted as signed integers, so they
+; should be sign-extended to 64 bits on 64-bit targets.
+; PR3181
+define i32 @test1(i32 %t3, i32* %t1) nounwind {
+ %t9 = getelementptr i32* %t1, i32 %t3 ; <i32*> [#uses=1]
+ %t15 = load i32* %t9 ; <i32> [#uses=1]
+ ret i32 %t15
+; X32: test1:
+; X32: movl (%ecx,%eax,4), %eax
+; X32: ret
+
+; X64: test1:
+; X64: movslq %edi, %rax
+; X64: movl (%rsi,%rax,4), %eax
+; X64: ret
+
+}
+define i32 @test2(i64 %t3, i32* %t1) nounwind {
+ %t9 = getelementptr i32* %t1, i64 %t3 ; <i32*> [#uses=1]
+ %t15 = load i32* %t9 ; <i32> [#uses=1]
+ ret i32 %t15
+; X32: test2:
+; X32: movl (%eax,%ecx,4), %eax
+; X32: ret
+
+; X64: test2:
+; X64: movl (%rsi,%rdi,4), %eax
+; X64: ret
+}
+
+
+
+; PR4984
+define i8 @test3(i8* %start) nounwind {
+entry:
+ %A = getelementptr i8* %start, i64 -2 ; <i8*> [#uses=1]
+ %B = load i8* %A, align 1 ; <i8> [#uses=1]
+ ret i8 %B
+
+
+; X32: test3:
+; X32: movl 4(%esp), %eax
+; X32: movb -2(%eax), %al
+; X32: ret
+
+; X64: test3:
+; X64: movb -2(%rdi), %al
+; X64: ret
+
+}
diff --git a/test/CodeGen/X86/fast-isel-gv.ll b/test/CodeGen/X86/fast-isel-gv.ll
new file mode 100644
index 0000000..34f8b38
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-gv.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -fast-isel | grep {_kill@GOTPCREL(%rip)}
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin10.0"
+@f = global i8 (...)* @kill ; <i8 (...)**> [#uses=1]
+
+declare signext i8 @kill(...)
+
+define i32 @main() nounwind ssp {
+entry:
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ %0 = alloca i32 ; <i32*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %1 = load i8 (...)** @f, align 8 ; <i8 (...)*> [#uses=1]
+ %2 = icmp ne i8 (...)* %1, @kill ; <i1> [#uses=1]
+ %3 = zext i1 %2 to i32 ; <i32> [#uses=1]
+ store i32 %3, i32* %0, align 4
+ %4 = load i32* %0, align 4 ; <i32> [#uses=1]
+ store i32 %4, i32* %retval, align 4
+ br label %return
+
+return: ; preds = %entry
+ %retval1 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval1
+}
diff --git a/test/CodeGen/X86/fast-isel-i1.ll b/test/CodeGen/X86/fast-isel-i1.ll
new file mode 100644
index 0000000..d066578
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-i1.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86 -fast-isel | grep {andb \$1, %}
+
+declare i64 @bar(i64)
+
+define i32 @foo(i64 %x) nounwind {
+ %y = add i64 %x, -3 ; <i64> [#uses=1]
+ %t = call i64 @bar(i64 %y) ; <i64> [#uses=1]
+ %s = mul i64 %t, 77 ; <i64> [#uses=1]
+ %z = trunc i64 %s to i1 ; <i1> [#uses=1]
+ br label %next
+
+next: ; preds = %0
+ %u = zext i1 %z to i32 ; <i32> [#uses=1]
+ %v = add i32 %u, 1999 ; <i32> [#uses=1]
+ br label %exit
+
+exit: ; preds = %next
+ ret i32 %v
+}
diff --git a/test/CodeGen/X86/fast-isel-mem.ll b/test/CodeGen/X86/fast-isel-mem.ll
new file mode 100644
index 0000000..35ec1e7
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-mem.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -fast-isel -mtriple=i386-apple-darwin | \
+; RUN: grep lazy_ptr, | count 2
+; RUN: llc < %s -fast-isel -march=x86 -relocation-model=static | \
+; RUN: grep lea
+
+@src = external global i32
+
+define i32 @loadgv() nounwind {
+entry:
+ %0 = load i32* @src, align 4
+ %1 = load i32* @src, align 4
+ %2 = add i32 %0, %1
+ store i32 %2, i32* @src
+ ret i32 %2
+}
+
+%stuff = type { i32 (...)** }
+@LotsStuff = external constant [4 x i32 (...)*]
+
+define void @t(%stuff* %this) nounwind {
+entry:
+ store i32 (...)** getelementptr ([4 x i32 (...)*]* @LotsStuff, i32 0, i32 2), i32 (...)*** null, align 4
+ ret void
+}
diff --git a/test/CodeGen/X86/fast-isel-phys.ll b/test/CodeGen/X86/fast-isel-phys.ll
new file mode 100644
index 0000000..158ef55
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-phys.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86
+
+define i8 @t2(i8 %a, i8 %c) nounwind {
+ %tmp = shl i8 %a, %c
+ ret i8 %tmp
+}
+
+define i8 @t1(i8 %a) nounwind {
+ %tmp = mul i8 %a, 17
+ ret i8 %tmp
+}
diff --git a/test/CodeGen/X86/fast-isel-shift-imm.ll b/test/CodeGen/X86/fast-isel-shift-imm.ll
new file mode 100644
index 0000000..35f7a72
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-shift-imm.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86 -O0 | grep {sarl \$80, %eax}
+; PR3242
+
+define i32 @foo(i32 %x) nounwind {
+ %y = ashr i32 %x, 50000
+ ret i32 %y
+}
diff --git a/test/CodeGen/X86/fast-isel-tailcall.ll b/test/CodeGen/X86/fast-isel-tailcall.ll
new file mode 100644
index 0000000..c3e527c
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-tailcall.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -fast-isel -tailcallopt -march=x86 | not grep add
+; PR4154
+
+; On x86, -tailcallopt changes the ABI so the caller shouldn't readjust
+; the stack pointer after the call in this code.
+
+define i32 @stub(i8* %t0) nounwind {
+entry:
+ %t1 = load i32* inttoptr (i32 139708680 to i32*) ; <i32> [#uses=1]
+ %t2 = bitcast i8* %t0 to i32 (i32)* ; <i32 (i32)*> [#uses=1]
+ %t3 = call fastcc i32 %t2(i32 %t1) ; <i32> [#uses=1]
+ ret i32 %t3
+}
diff --git a/test/CodeGen/X86/fast-isel-tls.ll b/test/CodeGen/X86/fast-isel-tls.ll
new file mode 100644
index 0000000..a5e6642
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-tls.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 -relocation-model=pic -mtriple=i686-unknown-linux-gnu -fast-isel | grep __tls_get_addr
+; PR3654
+
+@v = thread_local global i32 0
+define i32 @f() nounwind {
+entry:
+ %t = load i32* @v
+ %s = add i32 %t, 1
+ ret i32 %s
+}
diff --git a/test/CodeGen/X86/fast-isel-trunc.ll b/test/CodeGen/X86/fast-isel-trunc.ll
new file mode 100644
index 0000000..69b26c5
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-trunc.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -fast-isel -fast-isel-abort
+; RUN: llc < %s -march=x86-64 -fast-isel -fast-isel-abort
+
+define i8 @t1(i32 %x) signext nounwind {
+ %tmp1 = trunc i32 %x to i8
+ ret i8 %tmp1
+}
+
+define i8 @t2(i16 signext %x) signext nounwind {
+ %tmp1 = trunc i16 %x to i8
+ ret i8 %tmp1
+}
diff --git a/test/CodeGen/X86/fast-isel.ll b/test/CodeGen/X86/fast-isel.ll
new file mode 100644
index 0000000..84b3fd7
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel.ll
@@ -0,0 +1,75 @@
+; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86 -mattr=sse2
+
+; This tests very minimal fast-isel functionality.
+
+define i32* @foo(i32* %p, i32* %q, i32** %z) nounwind {
+entry:
+ %r = load i32* %p
+ %s = load i32* %q
+ %y = load i32** %z
+ br label %fast
+
+fast:
+ %t0 = add i32 %r, %s
+ %t1 = mul i32 %t0, %s
+ %t2 = sub i32 %t1, %s
+ %t3 = and i32 %t2, %s
+ %t4 = xor i32 %t3, 3
+ %t5 = xor i32 %t4, %s
+ %t6 = add i32 %t5, 2
+ %t7 = getelementptr i32* %y, i32 1
+ %t8 = getelementptr i32* %t7, i32 %t6
+ br label %exit
+
+exit:
+ ret i32* %t8
+}
+
+define double @bar(double* %p, double* %q) nounwind {
+entry:
+ %r = load double* %p
+ %s = load double* %q
+ br label %fast
+
+fast:
+ %t0 = fadd double %r, %s
+ %t1 = fmul double %t0, %s
+ %t2 = fsub double %t1, %s
+ %t3 = fadd double %t2, 707.0
+ br label %exit
+
+exit:
+ ret double %t3
+}
+
+define i32 @cast() nounwind {
+entry:
+ %tmp2 = bitcast i32 0 to i32
+ ret i32 %tmp2
+}
+
+define i1 @ptrtoint_i1(i8* %p) nounwind {
+ %t = ptrtoint i8* %p to i1
+ ret i1 %t
+}
+define i8* @inttoptr_i1(i1 %p) nounwind {
+ %t = inttoptr i1 %p to i8*
+ ret i8* %t
+}
+define i32 @ptrtoint_i32(i8* %p) nounwind {
+ %t = ptrtoint i8* %p to i32
+ ret i32 %t
+}
+define i8* @inttoptr_i32(i32 %p) nounwind {
+ %t = inttoptr i32 %p to i8*
+ ret i8* %t
+}
+
+define void @store_i1(i1* %p, i1 %t) nounwind {
+ store i1 %t, i1* %p
+ ret void
+}
+define i1 @load_i1(i1* %p) nounwind {
+ %t = load i1* %p
+ ret i1 %t
+}
diff --git a/test/CodeGen/X86/fastcall-correct-mangling.ll b/test/CodeGen/X86/fastcall-correct-mangling.ll
new file mode 100644
index 0000000..2b48f5f
--- /dev/null
+++ b/test/CodeGen/X86/fastcall-correct-mangling.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=i386-unknown-mingw32 | \
+; RUN: grep {@12}
+
+; Check that a fastcall function gets correct mangling
+
+define x86_fastcallcc void @func(i64 %X, i8 %Y, i8 %G, i16 %Z) {
+ ret void
+}
+
diff --git a/test/CodeGen/X86/fastcc-2.ll b/test/CodeGen/X86/fastcc-2.ll
new file mode 100644
index 0000000..d044a2a
--- /dev/null
+++ b/test/CodeGen/X86/fastcc-2.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | grep movsd
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | grep mov | count 1
+
+define i32 @foo() nounwind {
+entry:
+ tail call fastcc void @bar( double 1.000000e+00 ) nounwind
+ ret i32 0
+}
+
+declare fastcc void @bar(double)
diff --git a/test/CodeGen/X86/fastcc-byval.ll b/test/CodeGen/X86/fastcc-byval.ll
new file mode 100644
index 0000000..52b3e57
--- /dev/null
+++ b/test/CodeGen/X86/fastcc-byval.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -tailcallopt=false | grep {movl\[\[:space:\]\]*8(%esp), %eax} | count 2
+; PR3122
+; rdar://6400815
+
+; byval requires a copy, even with fastcc.
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.5"
+ %struct.MVT = type { i32 }
+
+define fastcc i32 @bar() nounwind {
+ %V = alloca %struct.MVT
+ %a = getelementptr %struct.MVT* %V, i32 0, i32 0
+ store i32 1, i32* %a
+ call fastcc void @foo(%struct.MVT* byval %V) nounwind
+ %t = load i32* %a
+ ret i32 %t
+}
+
+declare fastcc void @foo(%struct.MVT* byval)
diff --git a/test/CodeGen/X86/fastcc-sret.ll b/test/CodeGen/X86/fastcc-sret.ll
new file mode 100644
index 0000000..d4574188
--- /dev/null
+++ b/test/CodeGen/X86/fastcc-sret.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86 -tailcallopt=false | grep ret | not grep 4
+
+ %struct.foo = type { [4 x i32] }
+
+define fastcc void @bar(%struct.foo* noalias sret %agg.result) nounwind {
+entry:
+ %tmp1 = getelementptr %struct.foo* %agg.result, i32 0, i32 0
+ %tmp3 = getelementptr [4 x i32]* %tmp1, i32 0, i32 0
+ store i32 1, i32* %tmp3, align 8
+ ret void
+}
+
+@dst = external global i32
+
+define void @foo() nounwind {
+ %memtmp = alloca %struct.foo, align 4
+ call fastcc void @bar( %struct.foo* sret %memtmp ) nounwind
+ %tmp4 = getelementptr %struct.foo* %memtmp, i32 0, i32 0
+ %tmp5 = getelementptr [4 x i32]* %tmp4, i32 0, i32 0
+ %tmp6 = load i32* %tmp5
+ store i32 %tmp6, i32* @dst
+ ret void
+}
diff --git a/test/CodeGen/X86/fastcc.ll b/test/CodeGen/X86/fastcc.ll
new file mode 100644
index 0000000..705ab7b
--- /dev/null
+++ b/test/CodeGen/X86/fastcc.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -post-RA-scheduler=false | FileCheck %s
+; CHECK: movsd %xmm0, 8(%esp)
+; CHECK: xorl %ecx, %ecx
+
+@d = external global double ; <double*> [#uses=1]
+@c = external global double ; <double*> [#uses=1]
+@b = external global double ; <double*> [#uses=1]
+@a = external global double ; <double*> [#uses=1]
+
+define i32 @foo() nounwind {
+entry:
+ %0 = load double* @d, align 8 ; <double> [#uses=1]
+ %1 = load double* @c, align 8 ; <double> [#uses=1]
+ %2 = load double* @b, align 8 ; <double> [#uses=1]
+ %3 = load double* @a, align 8 ; <double> [#uses=1]
+ tail call fastcc void @bar( i32 0, i32 1, i32 2, double 1.000000e+00, double %3, double %2, double %1, double %0 ) nounwind
+ ret i32 0
+}
+
+declare fastcc void @bar(i32, i32, i32, double, double, double, double, double)
diff --git a/test/CodeGen/X86/fastcc3struct.ll b/test/CodeGen/X86/fastcc3struct.ll
new file mode 100644
index 0000000..84f8ef6
--- /dev/null
+++ b/test/CodeGen/X86/fastcc3struct.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -o %t
+; RUN: grep "movl .48, %ecx" %t
+; RUN: grep "movl .24, %edx" %t
+; RUN: grep "movl .12, %eax" %t
+
+%0 = type { i32, i32, i32 }
+
+define internal fastcc %0 @ReturnBigStruct() nounwind readnone {
+entry:
+ %0 = insertvalue %0 zeroinitializer, i32 12, 0
+ %1 = insertvalue %0 %0, i32 24, 1
+ %2 = insertvalue %0 %1, i32 48, 2
+ ret %0 %2
+}
+
diff --git a/test/CodeGen/X86/field-extract-use-trunc.ll b/test/CodeGen/X86/field-extract-use-trunc.ll
new file mode 100644
index 0000000..6020530
--- /dev/null
+++ b/test/CodeGen/X86/field-extract-use-trunc.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s -march=x86 | grep sar | count 1
+; RUN: llc < %s -march=x86-64 | not grep sar
+
+define i32 @test(i32 %f12) {
+ %tmp7.25 = lshr i32 %f12, 16
+ %tmp7.26 = trunc i32 %tmp7.25 to i8
+ %tmp78.2 = sext i8 %tmp7.26 to i32
+ ret i32 %tmp78.2
+}
+
+define i32 @test2(i32 %f12) {
+ %f11 = shl i32 %f12, 8
+ %tmp7.25 = ashr i32 %f11, 24
+ ret i32 %tmp7.25
+}
+
+define i32 @test3(i32 %f12) {
+ %f11 = shl i32 %f12, 13
+ %tmp7.25 = ashr i32 %f11, 24
+ ret i32 %tmp7.25
+}
+
+define i64 @test4(i64 %f12) {
+ %f11 = shl i64 %f12, 32
+ %tmp7.25 = ashr i64 %f11, 32
+ ret i64 %tmp7.25
+}
+
+define i16 @test5(i16 %f12) {
+ %f11 = shl i16 %f12, 2
+ %tmp7.25 = ashr i16 %f11, 8
+ ret i16 %tmp7.25
+}
+
+define i16 @test6(i16 %f12) {
+ %f11 = shl i16 %f12, 8
+ %tmp7.25 = ashr i16 %f11, 8
+ ret i16 %tmp7.25
+}
diff --git a/test/CodeGen/X86/fildll.ll b/test/CodeGen/X86/fildll.ll
new file mode 100644
index 0000000..c5a3765
--- /dev/null
+++ b/test/CodeGen/X86/fildll.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=att -mattr=-sse2 | grep fildll | count 2
+
+define fastcc double @sint64_to_fp(i64 %X) {
+ %R = sitofp i64 %X to double ; <double> [#uses=1]
+ ret double %R
+}
+
+define fastcc double @uint64_to_fp(i64 %X) {
+ %R = uitofp i64 %X to double ; <double> [#uses=1]
+ ret double %R
+}
+
diff --git a/test/CodeGen/X86/fmul-zero.ll b/test/CodeGen/X86/fmul-zero.ll
new file mode 100644
index 0000000..03bad65
--- /dev/null
+++ b/test/CodeGen/X86/fmul-zero.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86-64 -enable-unsafe-fp-math | not grep mulps
+; RUN: llc < %s -march=x86-64 | grep mulps
+
+define void @test14(<4 x float>*) nounwind {
+ load <4 x float>* %0, align 1
+ fmul <4 x float> %2, zeroinitializer
+ store <4 x float> %3, <4 x float>* %0, align 1
+ ret void
+}
diff --git a/test/CodeGen/X86/fold-add.ll b/test/CodeGen/X86/fold-add.ll
new file mode 100644
index 0000000..5e80ea5
--- /dev/null
+++ b/test/CodeGen/X86/fold-add.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86-64 | grep {cmpb \$0, (%r.\*,%r.\*)}
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin9.6"
+@prev_length = internal global i32 0 ; <i32*> [#uses=1]
+@window = internal global [65536 x i8] zeroinitializer, align 32 ; <[65536 x i8]*> [#uses=1]
[email protected] = appending global [1 x i8*] [i8* bitcast (i32 (i32)* @longest_match to i8*)] ; <[1 x i8*]*> [#uses=0]
+
+define fastcc i32 @longest_match(i32 %cur_match) nounwind {
+entry:
+ %0 = load i32* @prev_length, align 4 ; <i32> [#uses=3]
+ %1 = zext i32 %cur_match to i64 ; <i64> [#uses=1]
+ %2 = sext i32 %0 to i64 ; <i64> [#uses=1]
+ %.sum3 = add i64 %1, %2 ; <i64> [#uses=1]
+ %3 = getelementptr [65536 x i8]* @window, i64 0, i64 %.sum3 ; <i8*> [#uses=1]
+ %4 = load i8* %3, align 1 ; <i8> [#uses=1]
+ %5 = icmp eq i8 %4, 0 ; <i1> [#uses=1]
+ br i1 %5, label %bb5, label %bb23
+
+bb5: ; preds = %entry
+ ret i32 %0
+
+bb23: ; preds = %entry
+ ret i32 %0
+}
diff --git a/test/CodeGen/X86/fold-and-shift.ll b/test/CodeGen/X86/fold-and-shift.ll
new file mode 100644
index 0000000..9f79f77
--- /dev/null
+++ b/test/CodeGen/X86/fold-and-shift.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=x86 | not grep and
+
+define i32 @t1(i8* %X, i32 %i) {
+entry:
+ %tmp2 = shl i32 %i, 2 ; <i32> [#uses=1]
+ %tmp4 = and i32 %tmp2, 1020 ; <i32> [#uses=1]
+ %tmp7 = getelementptr i8* %X, i32 %tmp4 ; <i8*> [#uses=1]
+ %tmp78 = bitcast i8* %tmp7 to i32* ; <i32*> [#uses=1]
+ %tmp9 = load i32* %tmp78, align 4 ; <i32> [#uses=1]
+ ret i32 %tmp9
+}
+
+define i32 @t2(i16* %X, i32 %i) {
+entry:
+ %tmp2 = shl i32 %i, 1 ; <i32> [#uses=1]
+ %tmp4 = and i32 %tmp2, 131070 ; <i32> [#uses=1]
+ %tmp7 = getelementptr i16* %X, i32 %tmp4 ; <i16*> [#uses=1]
+ %tmp78 = bitcast i16* %tmp7 to i32* ; <i32*> [#uses=1]
+ %tmp9 = load i32* %tmp78, align 4 ; <i32> [#uses=1]
+ ret i32 %tmp9
+}
diff --git a/test/CodeGen/X86/fold-call-2.ll b/test/CodeGen/X86/fold-call-2.ll
new file mode 100644
index 0000000..7a2b038
--- /dev/null
+++ b/test/CodeGen/X86/fold-call-2.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep mov | count 1
+
+@f = external global void ()* ; <void ()**> [#uses=1]
+
+define i32 @main() nounwind {
+entry:
+ load void ()** @f, align 8 ; <void ()*>:0 [#uses=1]
+ tail call void %0( ) nounwind
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/fold-call-3.ll b/test/CodeGen/X86/fold-call-3.ll
new file mode 100644
index 0000000..337a7ed
--- /dev/null
+++ b/test/CodeGen/X86/fold-call-3.ll
@@ -0,0 +1,45 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep call | grep 560
+; rdar://6522427
+
+ %"struct.clang::Action" = type { %"struct.clang::ActionBase" }
+ %"struct.clang::ActionBase" = type { i32 (...)** }
+ %"struct.clang::ActionBase::ActionResult<0u>" = type { i8*, i8 }
+@NumTrials = internal global i32 10000000 ; <i32*> [#uses=2]
[email protected] = appending global [1 x i8*] [ i8* bitcast (void (i8*, %"struct.clang::Action"*)* @_Z25RawPointerPerformanceTestPvRN5clang6ActionE to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define void @_Z25RawPointerPerformanceTestPvRN5clang6ActionE(i8* %Val, %"struct.clang::Action"* %Actions) nounwind {
+entry:
+ %0 = alloca %"struct.clang::ActionBase::ActionResult<0u>", align 8 ; <%"struct.clang::ActionBase::ActionResult<0u>"*> [#uses=3]
+ %1 = load i32* @NumTrials, align 4 ; <i32> [#uses=1]
+ %2 = icmp eq i32 %1, 0 ; <i1> [#uses=1]
+ br i1 %2, label %return, label %bb.nph
+
+bb.nph: ; preds = %entry
+ %3 = getelementptr %"struct.clang::Action"* %Actions, i64 0, i32 0, i32 0 ; <i32 (...)***> [#uses=1]
+ %mrv_gep = bitcast %"struct.clang::ActionBase::ActionResult<0u>"* %0 to i64* ; <i64*> [#uses=1]
+ %mrv_gep1 = getelementptr %"struct.clang::ActionBase::ActionResult<0u>"* %0, i64 0, i32 1 ; <i8*> [#uses=1]
+ %4 = bitcast i8* %mrv_gep1 to i64* ; <i64*> [#uses=1]
+ %5 = getelementptr %"struct.clang::ActionBase::ActionResult<0u>"* %0, i64 0, i32 0 ; <i8**> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %bb.nph
+ %Trial.01 = phi i32 [ 0, %bb.nph ], [ %12, %bb ] ; <i32> [#uses=1]
+ %Val_addr.02 = phi i8* [ %Val, %bb.nph ], [ %11, %bb ] ; <i8*> [#uses=1]
+ %6 = load i32 (...)*** %3, align 8 ; <i32 (...)**> [#uses=1]
+ %7 = getelementptr i32 (...)** %6, i64 70 ; <i32 (...)**> [#uses=1]
+ %8 = load i32 (...)** %7, align 8 ; <i32 (...)*> [#uses=1]
+ %9 = bitcast i32 (...)* %8 to { i64, i64 } (%"struct.clang::Action"*, i8*)* ; <{ i64, i64 } (%"struct.clang::Action"*, i8*)*> [#uses=1]
+ %10 = call { i64, i64 } %9(%"struct.clang::Action"* %Actions, i8* %Val_addr.02) nounwind ; <{ i64, i64 }> [#uses=2]
+ %mrv_gr = extractvalue { i64, i64 } %10, 0 ; <i64> [#uses=1]
+ store i64 %mrv_gr, i64* %mrv_gep
+ %mrv_gr2 = extractvalue { i64, i64 } %10, 1 ; <i64> [#uses=1]
+ store i64 %mrv_gr2, i64* %4
+ %11 = load i8** %5, align 8 ; <i8*> [#uses=1]
+ %12 = add i32 %Trial.01, 1 ; <i32> [#uses=2]
+ %13 = load i32* @NumTrials, align 4 ; <i32> [#uses=1]
+ %14 = icmp ult i32 %12, %13 ; <i1> [#uses=1]
+ br i1 %14, label %bb, label %return
+
+return: ; preds = %bb, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/fold-call.ll b/test/CodeGen/X86/fold-call.ll
new file mode 100644
index 0000000..603e9ad
--- /dev/null
+++ b/test/CodeGen/X86/fold-call.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 | not grep mov
+; RUN: llc < %s -march=x86-64 | not grep mov
+
+declare void @bar()
+
+define void @foo(i32 %i0, i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, void()* %arg) nounwind {
+ call void @bar()
+ call void %arg()
+ ret void
+}
diff --git a/test/CodeGen/X86/fold-imm.ll b/test/CodeGen/X86/fold-imm.ll
new file mode 100644
index 0000000..f1fcbcf
--- /dev/null
+++ b/test/CodeGen/X86/fold-imm.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 | grep inc
+; RUN: llc < %s -march=x86 | grep add | grep 4
+
+define i32 @test(i32 %X) nounwind {
+entry:
+ %0 = add i32 %X, 1
+ ret i32 %0
+}
+
+define i32 @test2(i32 %X) nounwind {
+entry:
+ %0 = add i32 %X, 4
+ ret i32 %0
+}
diff --git a/test/CodeGen/X86/fold-load.ll b/test/CodeGen/X86/fold-load.ll
new file mode 100644
index 0000000..5525af2
--- /dev/null
+++ b/test/CodeGen/X86/fold-load.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s -march=x86 | FileCheck %s
+ %struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
+ %struct.obstack = type { i32, %struct._obstack_chunk*, i8*, i8*, i8*, i32, i32, %struct._obstack_chunk* (...)*, void (...)*, i8*, i8 }
+@stmt_obstack = external global %struct.obstack ; <%struct.obstack*> [#uses=1]
+
+; This should just not crash.
+define void @test1() nounwind {
+entry:
+ br i1 true, label %cond_true, label %cond_next
+
+cond_true: ; preds = %entry
+ %new_size.0.i = select i1 false, i32 0, i32 0 ; <i32> [#uses=1]
+ %tmp.i = load i32* bitcast (i8* getelementptr (%struct.obstack* @stmt_obstack, i32 0, i32 10) to i32*) ; <i32> [#uses=1]
+ %tmp.i.upgrd.1 = trunc i32 %tmp.i to i8 ; <i8> [#uses=1]
+ %tmp21.i = and i8 %tmp.i.upgrd.1, 1 ; <i8> [#uses=1]
+ %tmp22.i = icmp eq i8 %tmp21.i, 0 ; <i1> [#uses=1]
+ br i1 %tmp22.i, label %cond_false30.i, label %cond_true23.i
+
+cond_true23.i: ; preds = %cond_true
+ ret void
+
+cond_false30.i: ; preds = %cond_true
+ %tmp35.i = tail call %struct._obstack_chunk* null( i32 %new_size.0.i ) ; <%struct._obstack_chunk*> [#uses=0]
+ ret void
+
+cond_next: ; preds = %entry
+ ret void
+}
+
+
+
+define i32 @test2(i16* %P, i16* %Q) nounwind {
+ %A = load i16* %P, align 4 ; <i16> [#uses=11]
+ %C = zext i16 %A to i32 ; <i32> [#uses=1]
+ %D = and i32 %C, 255 ; <i32> [#uses=1]
+ br label %L
+L:
+
+ store i16 %A, i16* %Q
+ ret i32 %D
+
+; CHECK: test2:
+; CHECK: movl 4(%esp), %eax
+; CHECK-NEXT: movzwl (%eax), %ecx
+
+}
+
diff --git a/test/CodeGen/X86/fold-mul-lohi.ll b/test/CodeGen/X86/fold-mul-lohi.ll
new file mode 100644
index 0000000..0351eca
--- /dev/null
+++ b/test/CodeGen/X86/fold-mul-lohi.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=x86 | not grep lea
+; RUN: llc < %s -march=x86-64 | not grep lea
+
+@B = external global [1000 x i8], align 32
+@A = external global [1000 x i8], align 32
+@P = external global [1000 x i8], align 32
+
+define void @foo(i32 %m) nounwind {
+entry:
+ %tmp1 = icmp sgt i32 %m, 0
+ br i1 %tmp1, label %bb, label %return
+
+bb:
+ %i.019.0 = phi i32 [ %indvar.next, %bb ], [ 0, %entry ]
+ %tmp2 = getelementptr [1000 x i8]* @B, i32 0, i32 %i.019.0
+ %tmp3 = load i8* %tmp2, align 4
+ %tmp4 = mul i8 %tmp3, 2
+ %tmp5 = getelementptr [1000 x i8]* @A, i32 0, i32 %i.019.0
+ store i8 %tmp4, i8* %tmp5, align 4
+ %tmp8 = mul i32 %i.019.0, 9
+ %tmp10 = getelementptr [1000 x i8]* @P, i32 0, i32 %tmp8
+ store i8 17, i8* %tmp10, align 4
+ %indvar.next = add i32 %i.019.0, 1
+ %exitcond = icmp eq i32 %indvar.next, %m
+ br i1 %exitcond, label %return, label %bb
+
+return:
+ ret void
+}
+
diff --git a/test/CodeGen/X86/fold-pcmpeqd-0.ll b/test/CodeGen/X86/fold-pcmpeqd-0.ll
new file mode 100644
index 0000000..ef5202f
--- /dev/null
+++ b/test/CodeGen/X86/fold-pcmpeqd-0.ll
@@ -0,0 +1,105 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | not grep pcmpeqd
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | grep orps | grep CPI1_2 | count 2
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1
+
+; This testcase shouldn't need to spill the -1 value,
+; so it should just use pcmpeqd to materialize an all-ones vector.
+; For i386, cp load of -1 are folded.
+
+ %struct.__ImageExecInfo = type <{ <4 x i32>, <4 x float>, <2 x i64>, i8*, i8*, i8*, i32, i32, i32, i32, i32 }>
+ %struct._cl_image_format_t = type <{ i32, i32, i32 }>
+ %struct._image2d_t = type <{ i8*, %struct._cl_image_format_t, i32, i32, i32, i32, i32, i32 }>
+
+define void @program_1(%struct._image2d_t* %dest, %struct._image2d_t* %t0, <4 x float> %p0, <4 x float> %p1, <4 x float> %p4, <4 x float> %p5, <4 x float> %p6) nounwind {
+entry:
+ %tmp3.i = load i32* null ; <i32> [#uses=1]
+ %cmp = icmp sgt i32 %tmp3.i, 200 ; <i1> [#uses=1]
+ br i1 %cmp, label %forcond, label %ifthen
+
+ifthen: ; preds = %entry
+ ret void
+
+forcond: ; preds = %entry
+ %tmp3.i536 = load i32* null ; <i32> [#uses=1]
+ %cmp12 = icmp slt i32 0, %tmp3.i536 ; <i1> [#uses=1]
+ br i1 %cmp12, label %forbody, label %afterfor
+
+forbody: ; preds = %forcond
+ %bitcast204.i313 = bitcast <4 x i32> zeroinitializer to <4 x float> ; <<4 x float>> [#uses=1]
+ %mul233 = fmul <4 x float> %bitcast204.i313, zeroinitializer ; <<4 x float>> [#uses=1]
+ %mul257 = fmul <4 x float> %mul233, zeroinitializer ; <<4 x float>> [#uses=1]
+ %mul275 = fmul <4 x float> %mul257, zeroinitializer ; <<4 x float>> [#uses=1]
+ %tmp51 = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %mul275, <4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]
+ %bitcast198.i182 = bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=0]
+ %bitcast204.i185 = bitcast <4 x i32> zeroinitializer to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp69 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> zeroinitializer) nounwind ; <<4 x i32>> [#uses=1]
+ %tmp70 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %tmp69) nounwind ; <<4 x float>> [#uses=1]
+ %sub140.i78 = fsub <4 x float> zeroinitializer, %tmp70 ; <<4 x float>> [#uses=2]
+ %mul166.i86 = fmul <4 x float> zeroinitializer, %sub140.i78 ; <<4 x float>> [#uses=1]
+ %add167.i87 = fadd <4 x float> %mul166.i86, < float 0x3FE62ACB60000000, float 0x3FE62ACB60000000, float 0x3FE62ACB60000000, float 0x3FE62ACB60000000 > ; <<4 x float>> [#uses=1]
+ %mul171.i88 = fmul <4 x float> %add167.i87, %sub140.i78 ; <<4 x float>> [#uses=1]
+ %add172.i89 = fadd <4 x float> %mul171.i88, < float 0x3FF0000A40000000, float 0x3FF0000A40000000, float 0x3FF0000A40000000, float 0x3FF0000A40000000 > ; <<4 x float>> [#uses=1]
+ %bitcast176.i90 = bitcast <4 x float> %add172.i89 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %andnps178.i92 = and <4 x i32> %bitcast176.i90, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %bitcast179.i93 = bitcast <4 x i32> %andnps178.i92 to <4 x float> ; <<4 x float>> [#uses=1]
+ %mul186.i96 = fmul <4 x float> %bitcast179.i93, zeroinitializer ; <<4 x float>> [#uses=1]
+ %bitcast190.i98 = bitcast <4 x float> %mul186.i96 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %andnps192.i100 = and <4 x i32> %bitcast190.i98, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %xorps.i102 = xor <4 x i32> zeroinitializer, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %orps203.i103 = or <4 x i32> %andnps192.i100, %xorps.i102 ; <<4 x i32>> [#uses=1]
+ %bitcast204.i104 = bitcast <4 x i32> %orps203.i103 to <4 x float> ; <<4 x float>> [#uses=1]
+ %cmple.i = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> zeroinitializer, <4 x float> %tmp51, i8 2) nounwind ; <<4 x float>> [#uses=1]
+ %tmp80 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]
+ %sub140.i = fsub <4 x float> zeroinitializer, %tmp80 ; <<4 x float>> [#uses=1]
+ %bitcast148.i = bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %andnps150.i = and <4 x i32> %bitcast148.i, < i32 -2139095041, i32 -2139095041, i32 -2139095041, i32 -2139095041 > ; <<4 x i32>> [#uses=0]
+ %mul171.i = fmul <4 x float> zeroinitializer, %sub140.i ; <<4 x float>> [#uses=1]
+ %add172.i = fadd <4 x float> %mul171.i, < float 0x3FF0000A40000000, float 0x3FF0000A40000000, float 0x3FF0000A40000000, float 0x3FF0000A40000000 > ; <<4 x float>> [#uses=1]
+ %bitcast176.i = bitcast <4 x float> %add172.i to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %andnps178.i = and <4 x i32> %bitcast176.i, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %bitcast179.i = bitcast <4 x i32> %andnps178.i to <4 x float> ; <<4 x float>> [#uses=1]
+ %mul186.i = fmul <4 x float> %bitcast179.i, zeroinitializer ; <<4 x float>> [#uses=1]
+ %bitcast189.i = bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=0]
+ %bitcast190.i = bitcast <4 x float> %mul186.i to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %andnps192.i = and <4 x i32> %bitcast190.i, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %bitcast198.i = bitcast <4 x float> %cmple.i to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %xorps.i = xor <4 x i32> %bitcast198.i, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %orps203.i = or <4 x i32> %andnps192.i, %xorps.i ; <<4 x i32>> [#uses=1]
+ %bitcast204.i = bitcast <4 x i32> %orps203.i to <4 x float> ; <<4 x float>> [#uses=1]
+ %mul307 = fmul <4 x float> %bitcast204.i185, zeroinitializer ; <<4 x float>> [#uses=1]
+ %mul310 = fmul <4 x float> %bitcast204.i104, zeroinitializer ; <<4 x float>> [#uses=2]
+ %mul313 = fmul <4 x float> %bitcast204.i, zeroinitializer ; <<4 x float>> [#uses=1]
+ %tmp82 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %mul307, <4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]
+ %bitcast11.i15 = bitcast <4 x float> %tmp82 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %andnps.i17 = and <4 x i32> %bitcast11.i15, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %orps.i18 = or <4 x i32> %andnps.i17, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %bitcast17.i19 = bitcast <4 x i32> %orps.i18 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp83 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %mul310, <4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]
+ %bitcast.i3 = bitcast <4 x float> %mul310 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %bitcast6.i4 = bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=2]
+ %andps.i5 = and <4 x i32> %bitcast.i3, %bitcast6.i4 ; <<4 x i32>> [#uses=1]
+ %bitcast11.i6 = bitcast <4 x float> %tmp83 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %not.i7 = xor <4 x i32> %bitcast6.i4, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %andnps.i8 = and <4 x i32> %bitcast11.i6, %not.i7 ; <<4 x i32>> [#uses=1]
+ %orps.i9 = or <4 x i32> %andnps.i8, %andps.i5 ; <<4 x i32>> [#uses=1]
+ %bitcast17.i10 = bitcast <4 x i32> %orps.i9 to <4 x float> ; <<4 x float>> [#uses=1]
+ %bitcast.i = bitcast <4 x float> %mul313 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %andps.i = and <4 x i32> %bitcast.i, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %orps.i = or <4 x i32> zeroinitializer, %andps.i ; <<4 x i32>> [#uses=1]
+ %bitcast17.i = bitcast <4 x i32> %orps.i to <4 x float> ; <<4 x float>> [#uses=1]
+ call void null(<4 x float> %bitcast17.i19, <4 x float> %bitcast17.i10, <4 x float> %bitcast17.i, <4 x float> zeroinitializer, %struct.__ImageExecInfo* null, <4 x i32> zeroinitializer) nounwind
+ unreachable
+
+afterfor: ; preds = %forcond
+ ret void
+}
+
+declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone
+
+declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
+
+declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone
+
+declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>) nounwind readnone
+
+declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone
diff --git a/test/CodeGen/X86/fold-pcmpeqd-1.ll b/test/CodeGen/X86/fold-pcmpeqd-1.ll
new file mode 100644
index 0000000..cc4198d
--- /dev/null
+++ b/test/CodeGen/X86/fold-pcmpeqd-1.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
+; RUN: grep pcmpeqd %t | count 1
+; RUN: grep xor %t | count 1
+; RUN: not grep LCP %t
+
+define <2 x double> @foo() nounwind {
+ ret <2 x double> bitcast (<2 x i64><i64 -1, i64 -1> to <2 x double>)
+}
+define <2 x double> @bar() nounwind {
+ ret <2 x double> bitcast (<2 x i64><i64 0, i64 0> to <2 x double>)
+}
diff --git a/test/CodeGen/X86/fold-pcmpeqd-2.ll b/test/CodeGen/X86/fold-pcmpeqd-2.ll
new file mode 100644
index 0000000..49f8795
--- /dev/null
+++ b/test/CodeGen/X86/fold-pcmpeqd-2.ll
@@ -0,0 +1,83 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | not grep pcmpeqd
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1
+
+; This testcase should need to spill the -1 value on x86-32,
+; so it shouldn't use pcmpeqd to materialize an all-ones vector; it
+; should use a constant-pool load instead.
+
+ %struct.__ImageExecInfo = type <{ <4 x i32>, <4 x float>, <2 x i64>, i8*, i8*, i8*, i32, i32, i32, i32, i32 }>
+ %struct._cl_image_format_t = type <{ i32, i32, i32 }>
+ %struct._image2d_t = type <{ i8*, %struct._cl_image_format_t, i32, i32, i32, i32, i32, i32 }>
+
+define void @program_1(%struct._image2d_t* %dest, %struct._image2d_t* %t0, <4 x float> %p0, <4 x float> %p1, <4 x float> %p4, <4 x float> %p5, <4 x float> %p6) nounwind {
+entry:
+ %tmp3.i = load i32* null ; <i32> [#uses=1]
+ %cmp = icmp slt i32 0, %tmp3.i ; <i1> [#uses=1]
+ br i1 %cmp, label %forcond, label %ifthen
+
+ifthen: ; preds = %entry
+ ret void
+
+forcond: ; preds = %entry
+ %tmp3.i536 = load i32* null ; <i32> [#uses=1]
+ %cmp12 = icmp slt i32 0, %tmp3.i536 ; <i1> [#uses=1]
+ br i1 %cmp12, label %forbody, label %afterfor
+
+forbody: ; preds = %forcond
+ %bitcast204.i104 = bitcast <4 x i32> zeroinitializer to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp78 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> < float 1.280000e+02, float 1.280000e+02, float 1.280000e+02, float 1.280000e+02 >, <4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=2]
+ %tmp79 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %tmp78) nounwind ; <<4 x i32>> [#uses=1]
+ %tmp80 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %tmp79) nounwind ; <<4 x float>> [#uses=1]
+ %sub140.i = fsub <4 x float> %tmp78, %tmp80 ; <<4 x float>> [#uses=2]
+ %mul166.i = fmul <4 x float> zeroinitializer, %sub140.i ; <<4 x float>> [#uses=1]
+ %add167.i = fadd <4 x float> %mul166.i, < float 0x3FE62ACB60000000, float 0x3FE62ACB60000000, float 0x3FE62ACB60000000, float 0x3FE62ACB60000000 > ; <<4 x float>> [#uses=1]
+ %mul171.i = fmul <4 x float> %add167.i, %sub140.i ; <<4 x float>> [#uses=1]
+ %add172.i = fadd <4 x float> %mul171.i, < float 0x3FF0000A40000000, float 0x3FF0000A40000000, float 0x3FF0000A40000000, float 0x3FF0000A40000000 > ; <<4 x float>> [#uses=1]
+ %bitcast176.i = bitcast <4 x float> %add172.i to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %andnps178.i = and <4 x i32> %bitcast176.i, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %bitcast179.i = bitcast <4 x i32> %andnps178.i to <4 x float> ; <<4 x float>> [#uses=1]
+ %mul186.i = fmul <4 x float> %bitcast179.i, zeroinitializer ; <<4 x float>> [#uses=1]
+ %bitcast190.i = bitcast <4 x float> %mul186.i to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %andnps192.i = and <4 x i32> %bitcast190.i, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %xorps.i = xor <4 x i32> zeroinitializer, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %orps203.i = or <4 x i32> %andnps192.i, %xorps.i ; <<4 x i32>> [#uses=1]
+ %bitcast204.i = bitcast <4 x i32> %orps203.i to <4 x float> ; <<4 x float>> [#uses=1]
+ %mul310 = fmul <4 x float> %bitcast204.i104, zeroinitializer ; <<4 x float>> [#uses=2]
+ %mul313 = fmul <4 x float> %bitcast204.i, zeroinitializer ; <<4 x float>> [#uses=1]
+ %cmpunord.i11 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> zeroinitializer, <4 x float> zeroinitializer, i8 3) nounwind ; <<4 x float>> [#uses=1]
+ %bitcast6.i13 = bitcast <4 x float> %cmpunord.i11 to <4 x i32> ; <<4 x i32>> [#uses=2]
+ %andps.i14 = and <4 x i32> zeroinitializer, %bitcast6.i13 ; <<4 x i32>> [#uses=1]
+ %not.i16 = xor <4 x i32> %bitcast6.i13, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %andnps.i17 = and <4 x i32> zeroinitializer, %not.i16 ; <<4 x i32>> [#uses=1]
+ %orps.i18 = or <4 x i32> %andnps.i17, %andps.i14 ; <<4 x i32>> [#uses=1]
+ %bitcast17.i19 = bitcast <4 x i32> %orps.i18 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp83 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %mul310, <4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]
+ %bitcast.i3 = bitcast <4 x float> %mul310 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %andps.i5 = and <4 x i32> %bitcast.i3, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %bitcast11.i6 = bitcast <4 x float> %tmp83 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %not.i7 = xor <4 x i32> zeroinitializer, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %andnps.i8 = and <4 x i32> %bitcast11.i6, %not.i7 ; <<4 x i32>> [#uses=1]
+ %orps.i9 = or <4 x i32> %andnps.i8, %andps.i5 ; <<4 x i32>> [#uses=1]
+ %bitcast17.i10 = bitcast <4 x i32> %orps.i9 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp84 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %mul313, <4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1]
+ %bitcast6.i = bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=2]
+ %andps.i = and <4 x i32> zeroinitializer, %bitcast6.i ; <<4 x i32>> [#uses=1]
+ %bitcast11.i = bitcast <4 x float> %tmp84 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %not.i = xor <4 x i32> %bitcast6.i, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %andnps.i = and <4 x i32> %bitcast11.i, %not.i ; <<4 x i32>> [#uses=1]
+ %orps.i = or <4 x i32> %andnps.i, %andps.i ; <<4 x i32>> [#uses=1]
+ %bitcast17.i = bitcast <4 x i32> %orps.i to <4 x float> ; <<4 x float>> [#uses=1]
+ call void null(<4 x float> %bitcast17.i19, <4 x float> %bitcast17.i10, <4 x float> %bitcast17.i, <4 x float> zeroinitializer, %struct.__ImageExecInfo* null, <4 x i32> zeroinitializer) nounwind
+ unreachable
+
+afterfor: ; preds = %forcond
+ ret void
+}
+
+declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone
+
+declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
+
+declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone
+
+declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>) nounwind readnone
diff --git a/test/CodeGen/X86/fold-sext-trunc.ll b/test/CodeGen/X86/fold-sext-trunc.ll
new file mode 100644
index 0000000..2605123
--- /dev/null
+++ b/test/CodeGen/X86/fold-sext-trunc.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86-64 | grep movslq | count 1
+; PR4050
+
+ type { i64 } ; type %0
+ %struct.S1 = type { i16, i32 }
+@g_10 = external global %struct.S1 ; <%struct.S1*> [#uses=2]
+
+declare void @func_28(i64, i64)
+
+define void @int322(i32 %foo) nounwind {
+entry:
+ %val = load i64* getelementptr (%0* bitcast (%struct.S1* @g_10 to %0*), i32 0, i32 0) ; <i64> [#uses=1]
+ %0 = load i32* getelementptr (%struct.S1* @g_10, i32 0, i32 1), align 4 ; <i32> [#uses=1]
+ %1 = sext i32 %0 to i64 ; <i64> [#uses=1]
+ %tmp4.i = lshr i64 %val, 32 ; <i64> [#uses=1]
+ %tmp5.i = trunc i64 %tmp4.i to i32 ; <i32> [#uses=1]
+ %2 = sext i32 %tmp5.i to i64 ; <i64> [#uses=1]
+ tail call void @func_28(i64 %2, i64 %1) nounwind
+ ret void
+}
diff --git a/test/CodeGen/X86/fp-immediate-shorten.ll b/test/CodeGen/X86/fp-immediate-shorten.ll
new file mode 100644
index 0000000..cafc61a
--- /dev/null
+++ b/test/CodeGen/X86/fp-immediate-shorten.ll
@@ -0,0 +1,9 @@
+;; Test that this FP immediate is stored in the constant pool as a float.
+
+; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3 | \
+; RUN: grep {.long.1123418112}
+
+define double @D() {
+ ret double 1.230000e+02
+}
+
diff --git a/test/CodeGen/X86/fp-in-intregs.ll b/test/CodeGen/X86/fp-in-intregs.ll
new file mode 100644
index 0000000..08ea77d
--- /dev/null
+++ b/test/CodeGen/X86/fp-in-intregs.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah | not egrep {\(\(xor\|and\)ps\|movd\)}
+
+; These operations should be done in integer registers, eliminating constant
+; pool loads, movd's etc.
+
+define i32 @test1(float %x) nounwind {
+entry:
+ %tmp2 = fsub float -0.000000e+00, %x ; <float> [#uses=1]
+ %tmp210 = bitcast float %tmp2 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp210
+}
+
+define i32 @test2(float %x) nounwind {
+entry:
+ %tmp2 = tail call float @copysignf( float 1.000000e+00, float %x ) nounwind readnone ; <float> [#uses=1]
+ %tmp210 = bitcast float %tmp2 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp210
+}
+
+declare float @copysignf(float, float) nounwind readnone
+
diff --git a/test/CodeGen/X86/fp-stack-2results.ll b/test/CodeGen/X86/fp-stack-2results.ll
new file mode 100644
index 0000000..321e267
--- /dev/null
+++ b/test/CodeGen/X86/fp-stack-2results.ll
@@ -0,0 +1,60 @@
+; RUN: llc < %s -march=x86 | grep fldz
+; RUN: llc < %s -march=x86-64 | grep fld1
+
+; This is basically this code on x86-64:
+; _Complex long double test() { return 1.0; }
+define {x86_fp80, x86_fp80} @test() {
+ %A = fpext double 1.0 to x86_fp80
+ %B = fpext double 0.0 to x86_fp80
+ ret x86_fp80 %A, x86_fp80 %B
+}
+
+
+;_test2:
+; fld1
+; fld %st(0)
+; ret
+define {x86_fp80, x86_fp80} @test2() {
+ %A = fpext double 1.0 to x86_fp80
+ ret x86_fp80 %A, x86_fp80 %A
+}
+
+; Uses both values.
+define void @call1(x86_fp80 *%P1, x86_fp80 *%P2) {
+ %a = call {x86_fp80,x86_fp80} @test()
+ %b = getresult {x86_fp80,x86_fp80} %a, 0
+ store x86_fp80 %b, x86_fp80* %P1
+
+ %c = getresult {x86_fp80,x86_fp80} %a, 1
+ store x86_fp80 %c, x86_fp80* %P2
+ ret void
+}
+
+; Uses both values, requires fxch
+define void @call2(x86_fp80 *%P1, x86_fp80 *%P2) {
+ %a = call {x86_fp80,x86_fp80} @test()
+ %b = getresult {x86_fp80,x86_fp80} %a, 1
+ store x86_fp80 %b, x86_fp80* %P1
+
+ %c = getresult {x86_fp80,x86_fp80} %a, 0
+ store x86_fp80 %c, x86_fp80* %P2
+ ret void
+}
+
+; Uses ST(0), ST(1) is dead but must be popped.
+define void @call3(x86_fp80 *%P1, x86_fp80 *%P2) {
+ %a = call {x86_fp80,x86_fp80} @test()
+ %b = getresult {x86_fp80,x86_fp80} %a, 0
+ store x86_fp80 %b, x86_fp80* %P1
+ ret void
+}
+
+; Uses ST(1), ST(0) is dead and must be popped.
+define void @call4(x86_fp80 *%P1, x86_fp80 *%P2) {
+ %a = call {x86_fp80,x86_fp80} @test()
+
+ %c = getresult {x86_fp80,x86_fp80} %a, 1
+ store x86_fp80 %c, x86_fp80* %P2
+ ret void
+}
+
diff --git a/test/CodeGen/X86/fp-stack-O0-crash.ll b/test/CodeGen/X86/fp-stack-O0-crash.ll
new file mode 100644
index 0000000..4768ea2
--- /dev/null
+++ b/test/CodeGen/X86/fp-stack-O0-crash.ll
@@ -0,0 +1,30 @@
+; RUN: llc %s -O0 -fast-isel -regalloc=local -o -
+; PR4767
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin10"
+
+define void @fn(x86_fp80 %x) nounwind ssp {
+entry:
+ %x.addr = alloca x86_fp80 ; <x86_fp80*> [#uses=5]
+ store x86_fp80 %x, x86_fp80* %x.addr
+ br i1 false, label %cond.true, label %cond.false
+
+cond.true: ; preds = %entry
+ %tmp = load x86_fp80* %x.addr ; <x86_fp80> [#uses=1]
+ %tmp1 = load x86_fp80* %x.addr ; <x86_fp80> [#uses=1]
+ %cmp = fcmp oeq x86_fp80 %tmp, %tmp1 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+cond.false: ; preds = %entry
+ %tmp2 = load x86_fp80* %x.addr ; <x86_fp80> [#uses=1]
+ %tmp3 = load x86_fp80* %x.addr ; <x86_fp80> [#uses=1]
+ %cmp4 = fcmp une x86_fp80 %tmp2, %tmp3 ; <i1> [#uses=1]
+ br i1 %cmp4, label %if.then, label %if.end
+
+if.then: ; preds = %cond.false, %cond.true
+ br label %if.end
+
+if.end: ; preds = %if.then, %cond.false, %cond.true
+ ret void
+}
diff --git a/test/CodeGen/X86/fp-stack-compare.ll b/test/CodeGen/X86/fp-stack-compare.ll
new file mode 100644
index 0000000..4bdf459
--- /dev/null
+++ b/test/CodeGen/X86/fp-stack-compare.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mcpu=i386 | \
+; RUN: grep {fucomi.*st.\[12\]}
+; PR1012
+
+define float @foo(float* %col.2.0) {
+ %tmp = load float* %col.2.0 ; <float> [#uses=3]
+ %tmp16 = fcmp olt float %tmp, 0.000000e+00 ; <i1> [#uses=1]
+ %tmp20 = fsub float -0.000000e+00, %tmp ; <float> [#uses=1]
+ %iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp ; <float> [#uses=1]
+ ret float %iftmp.2.0
+}
+
diff --git a/test/CodeGen/X86/fp-stack-direct-ret.ll b/test/CodeGen/X86/fp-stack-direct-ret.ll
new file mode 100644
index 0000000..5a28bb5
--- /dev/null
+++ b/test/CodeGen/X86/fp-stack-direct-ret.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 | not grep fstp
+; RUN: llc < %s -march=x86 -mcpu=yonah | not grep movsd
+
+declare double @foo()
+
+define double @bar() {
+entry:
+ %tmp5 = tail call double @foo()
+ ret double %tmp5
+}
+
diff --git a/test/CodeGen/X86/fp-stack-ret-conv.ll b/test/CodeGen/X86/fp-stack-ret-conv.ll
new file mode 100644
index 0000000..f220b24
--- /dev/null
+++ b/test/CodeGen/X86/fp-stack-ret-conv.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mcpu=yonah | grep cvtss2sd
+; RUN: llc < %s -mcpu=yonah | grep fstps
+; RUN: llc < %s -mcpu=yonah | not grep cvtsd2ss
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+
+define void @test(double *%b) {
+entry:
+ %tmp13 = tail call double @foo()
+ %tmp1314 = fptrunc double %tmp13 to float ; <float> [#uses=1]
+ %tmp3940 = fpext float %tmp1314 to double ; <double> [#uses=1]
+ volatile store double %tmp3940, double* %b
+ ret void
+}
+
+declare double @foo()
diff --git a/test/CodeGen/X86/fp-stack-ret-store.ll b/test/CodeGen/X86/fp-stack-ret-store.ll
new file mode 100644
index 0000000..05dfc54
--- /dev/null
+++ b/test/CodeGen/X86/fp-stack-ret-store.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -mcpu=yonah | not grep movss
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin8"
+
+; This should store directly into P from the FP stack. It should not
+; go through a stack slot to get there.
+
+define void @bar(double* %P) {
+entry:
+ %tmp = tail call double (...)* @foo( ) ; <double> [#uses=1]
+ store double %tmp, double* %P, align 8
+ ret void
+}
+
+declare double @foo(...)
+
+define void @bar2(float* %P) {
+entry:
+ %tmp = tail call double (...)* @foo2( ) ; <double> [#uses=1]
+ %tmp1 = fptrunc double %tmp to float ; <float> [#uses=1]
+ store float %tmp1, float* %P, align 4
+ ret void
+}
+
+declare double @foo2(...)
+
diff --git a/test/CodeGen/X86/fp-stack-ret.ll b/test/CodeGen/X86/fp-stack-ret.ll
new file mode 100644
index 0000000..c83a0cb
--- /dev/null
+++ b/test/CodeGen/X86/fp-stack-ret.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin8 -mcpu=yonah -march=x86 > %t
+; RUN: grep fldl %t | count 1
+; RUN: not grep xmm %t
+; RUN: grep {sub.*esp} %t | count 1
+
+; These testcases shouldn't require loading into an XMM register then storing
+; to memory, then reloading into an FPStack reg.
+
+define double @test1(double *%P) {
+ %A = load double* %P
+ ret double %A
+}
+
+; fastcc should return a value
+define fastcc double @test2(<2 x double> %A) {
+ %B = extractelement <2 x double> %A, i32 0
+ ret double %B
+}
+
+define fastcc double @test3(<4 x float> %A) {
+ %B = bitcast <4 x float> %A to <2 x double>
+ %C = call fastcc double @test2(<2 x double> %B)
+ ret double %C
+}
+
diff --git a/test/CodeGen/X86/fp-stack-retcopy.ll b/test/CodeGen/X86/fp-stack-retcopy.ll
new file mode 100644
index 0000000..67dcb18
--- /dev/null
+++ b/test/CodeGen/X86/fp-stack-retcopy.ll
@@ -0,0 +1,12 @@
+; This should not copy the result of foo into an xmm register.
+; RUN: llc < %s -march=x86 -mcpu=yonah -mtriple=i686-apple-darwin9 | not grep xmm
+; rdar://5689903
+
+declare double @foo()
+
+define double @carg({ double, double }* byval %z) nounwind {
+entry:
+ %tmp5 = tail call double @foo() nounwind ; <double> [#uses=1]
+ ret double %tmp5
+}
+
diff --git a/test/CodeGen/X86/fp-stack-set-st1.ll b/test/CodeGen/X86/fp-stack-set-st1.ll
new file mode 100644
index 0000000..894897a
--- /dev/null
+++ b/test/CodeGen/X86/fp-stack-set-st1.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86 | grep fxch | count 2
+
+define i32 @main() nounwind {
+entry:
+ %asmtmp = tail call { double, double } asm sideeffect "fmul\09%st(1),%st\0A\09fst\09%st(1)\0A\09frndint\0A\09fxch %st(1)\0A\09fsub\09%st(1),%st\0A\09f2xm1\0A\09", "={st},={st(1)},0,1,~{dirflag},~{fpsr},~{flags}"(double 0x4030FEFBD582097D, double 4.620000e+01) nounwind ; <{ double, double }> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/X86/fp2sint.ll b/test/CodeGen/X86/fp2sint.ll
new file mode 100644
index 0000000..1675444
--- /dev/null
+++ b/test/CodeGen/X86/fp2sint.ll
@@ -0,0 +1,18 @@
+;; LowerFP_TO_SINT should not create a stack object if it's not needed.
+
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep add
+
+define i32 @main(i32 %argc, i8** %argv) {
+cond_false.i.i.i: ; preds = %bb.i5
+ %tmp35.i = load double* null, align 8 ; <double> [#uses=1]
+ %tmp3536.i = fptosi double %tmp35.i to i32 ; <i32> [#uses=1]
+ %tmp3536140.i = zext i32 %tmp3536.i to i64 ; <i64> [#uses=1]
+ %tmp39.i = load double* null, align 4 ; <double> [#uses=1]
+ %tmp3940.i = fptosi double %tmp39.i to i32 ; <i32> [#uses=1]
+ %tmp3940137.i = zext i32 %tmp3940.i to i64 ; <i64> [#uses=1]
+ %tmp3940137138.i = shl i64 %tmp3940137.i, 32 ; <i64> [#uses=1]
+ %tmp3940137138.ins.i = or i64 %tmp3940137138.i, %tmp3536140.i ; <i64> [#uses=1]
+ %tmp95.i.i = trunc i64 %tmp3940137138.ins.i to i32 ; <i32> [#uses=1]
+ store i32 %tmp95.i.i, i32* null, align 4
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/fp_constant_op.ll b/test/CodeGen/X86/fp_constant_op.ll
new file mode 100644
index 0000000..b3ec538
--- /dev/null
+++ b/test/CodeGen/X86/fp_constant_op.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -mcpu=i486 | FileCheck %s
+; Test that the load of the constant is folded into the operation.
+
+
+define double @foo_add(double %P) {
+ %tmp.1 = fadd double %P, 1.230000e+02 ; <double> [#uses=1]
+ ret double %tmp.1
+}
+; CHECK: foo_add:
+; CHECK: fadd DWORD PTR
+
+define double @foo_mul(double %P) {
+ %tmp.1 = fmul double %P, 1.230000e+02 ; <double> [#uses=1]
+ ret double %tmp.1
+}
+; CHECK: foo_mul:
+; CHECK: fmul DWORD PTR
+
+define double @foo_sub(double %P) {
+ %tmp.1 = fsub double %P, 1.230000e+02 ; <double> [#uses=1]
+ ret double %tmp.1
+}
+; CHECK: foo_sub:
+; CHECK: fadd DWORD PTR
+
+define double @foo_subr(double %P) {
+ %tmp.1 = fsub double 1.230000e+02, %P ; <double> [#uses=1]
+ ret double %tmp.1
+}
+; CHECK: foo_subr:
+; CHECK: fsub QWORD PTR
+
+define double @foo_div(double %P) {
+ %tmp.1 = fdiv double %P, 1.230000e+02 ; <double> [#uses=1]
+ ret double %tmp.1
+}
+; CHECK: foo_div:
+; CHECK: fdiv DWORD PTR
+
+define double @foo_divr(double %P) {
+ %tmp.1 = fdiv double 1.230000e+02, %P ; <double> [#uses=1]
+ ret double %tmp.1
+}
+; CHECK: foo_divr:
+; CHECK: fdiv QWORD PTR
+
diff --git a/test/CodeGen/X86/fp_load_cast_fold.ll b/test/CodeGen/X86/fp_load_cast_fold.ll
new file mode 100644
index 0000000..a160ac6
--- /dev/null
+++ b/test/CodeGen/X86/fp_load_cast_fold.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86 | grep fild | not grep ESP
+
+define double @short(i16* %P) {
+ %V = load i16* %P ; <i16> [#uses=1]
+ %V2 = sitofp i16 %V to double ; <double> [#uses=1]
+ ret double %V2
+}
+
+define double @int(i32* %P) {
+ %V = load i32* %P ; <i32> [#uses=1]
+ %V2 = sitofp i32 %V to double ; <double> [#uses=1]
+ ret double %V2
+}
+
+define double @long(i64* %P) {
+ %V = load i64* %P ; <i64> [#uses=1]
+ %V2 = sitofp i64 %V to double ; <double> [#uses=1]
+ ret double %V2
+}
+
diff --git a/test/CodeGen/X86/fp_load_fold.ll b/test/CodeGen/X86/fp_load_fold.ll
new file mode 100644
index 0000000..0145069
--- /dev/null
+++ b/test/CodeGen/X86/fp_load_fold.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
+; RUN: grep -i ST | not grep {fadd\\|fsub\\|fdiv\\|fmul}
+
+; Test that the load of the memory location is folded into the operation.
+
+define double @test_add(double %X, double* %P) {
+ %Y = load double* %P ; <double> [#uses=1]
+ %R = fadd double %X, %Y ; <double> [#uses=1]
+ ret double %R
+}
+
+define double @test_mul(double %X, double* %P) {
+ %Y = load double* %P ; <double> [#uses=1]
+ %R = fmul double %X, %Y ; <double> [#uses=1]
+ ret double %R
+}
+
+define double @test_sub(double %X, double* %P) {
+ %Y = load double* %P ; <double> [#uses=1]
+ %R = fsub double %X, %Y ; <double> [#uses=1]
+ ret double %R
+}
+
+define double @test_subr(double %X, double* %P) {
+ %Y = load double* %P ; <double> [#uses=1]
+ %R = fsub double %Y, %X ; <double> [#uses=1]
+ ret double %R
+}
+
+define double @test_div(double %X, double* %P) {
+ %Y = load double* %P ; <double> [#uses=1]
+ %R = fdiv double %X, %Y ; <double> [#uses=1]
+ ret double %R
+}
+
+define double @test_divr(double %X, double* %P) {
+ %Y = load double* %P ; <double> [#uses=1]
+ %R = fdiv double %Y, %X ; <double> [#uses=1]
+ ret double %R
+}
diff --git a/test/CodeGen/X86/fsxor-alignment.ll b/test/CodeGen/X86/fsxor-alignment.ll
new file mode 100644
index 0000000..6a8dbcf
--- /dev/null
+++ b/test/CodeGen/X86/fsxor-alignment.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -enable-unsafe-fp-math | \
+; RUN: grep -v sp | grep xorps | count 2
+
+; Don't fold the incoming stack arguments into the xorps instructions used
+; to do floating-point negations, because the arguments aren't vectors
+; and aren't vector-aligned.
+
+define void @foo(float* %p, float* %q, float %s, float %y) {
+ %ss = fsub float -0.0, %s
+ %yy = fsub float -0.0, %y
+ store float %ss, float* %p
+ store float %yy, float* %q
+ ret void
+}
diff --git a/test/CodeGen/X86/full-lsr.ll b/test/CodeGen/X86/full-lsr.ll
new file mode 100644
index 0000000..3bd58b6
--- /dev/null
+++ b/test/CodeGen/X86/full-lsr.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s -march=x86 >%t
+
+; TODO: Enhance full lsr mode to get this:
+; RUNX: grep {addl \\\$4,} %t | count 3
+; RUNX: not grep {,%} %t
+
+; For now, it should find this, which is still pretty good:
+; RUN: not grep {addl \\\$4,} %t
+; RUN: grep {,%} %t | count 6
+
+define void @foo(float* nocapture %A, float* nocapture %B, float* nocapture %C, i32 %N) nounwind {
+entry:
+ %0 = icmp sgt i32 %N, 0 ; <i1> [#uses=1]
+ br i1 %0, label %bb, label %return
+
+bb: ; preds = %bb, %entry
+ %i.03 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=5]
+ %1 = getelementptr float* %A, i32 %i.03 ; <float*> [#uses=1]
+ %2 = load float* %1, align 4 ; <float> [#uses=1]
+ %3 = getelementptr float* %B, i32 %i.03 ; <float*> [#uses=1]
+ %4 = load float* %3, align 4 ; <float> [#uses=1]
+ %5 = fadd float %2, %4 ; <float> [#uses=1]
+ %6 = getelementptr float* %C, i32 %i.03 ; <float*> [#uses=1]
+ store float %5, float* %6, align 4
+ %7 = add i32 %i.03, 10 ; <i32> [#uses=3]
+ %8 = getelementptr float* %A, i32 %7 ; <float*> [#uses=1]
+ %9 = load float* %8, align 4 ; <float> [#uses=1]
+ %10 = getelementptr float* %B, i32 %7 ; <float*> [#uses=1]
+ %11 = load float* %10, align 4 ; <float> [#uses=1]
+ %12 = fadd float %9, %11 ; <float> [#uses=1]
+ %13 = getelementptr float* %C, i32 %7 ; <float*> [#uses=1]
+ store float %12, float* %13, align 4
+ %indvar.next = add i32 %i.03, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %N ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/ga-offset.ll b/test/CodeGen/X86/ga-offset.ll
new file mode 100644
index 0000000..9f6d3f7
--- /dev/null
+++ b/test/CodeGen/X86/ga-offset.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 > %t
+; RUN: not grep lea %t
+; RUN: not grep add %t
+; RUN: grep mov %t | count 1
+; RUN: llc < %s -mtriple=x86_64-linux -relocation-model=static > %t
+; RUN: not grep lea %t
+; RUN: not grep add %t
+; RUN: grep mov %t | count 1
+
+; This store should fold to a single mov instruction.
+
+@ptr = global i32* null
+@dst = global [131072 x i32] zeroinitializer
+
+define void @foo() nounwind {
+ store i32* getelementptr ([131072 x i32]* @dst, i32 0, i32 16), i32** @ptr
+ ret void
+}
diff --git a/test/CodeGen/X86/global-sections-tls.ll b/test/CodeGen/X86/global-sections-tls.ll
new file mode 100644
index 0000000..2c23030
--- /dev/null
+++ b/test/CodeGen/X86/global-sections-tls.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX
+
+; PR4639
+@G1 = internal thread_local global i32 0 ; <i32*> [#uses=1]
+; LINUX: .section .tbss,"awT",@nobits
+; LINUX: G1:
+
+
+define i32* @foo() nounwind readnone {
+entry:
+ ret i32* @G1
+}
+
+
diff --git a/test/CodeGen/X86/global-sections.ll b/test/CodeGen/X86/global-sections.ll
new file mode 100644
index 0000000..1a7b577
--- /dev/null
+++ b/test/CodeGen/X86/global-sections.ll
@@ -0,0 +1,137 @@
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=i386-apple-darwin9.7 | FileCheck %s -check-prefix=DARWIN
+
+
+; int G1;
+@G1 = common global i32 0
+
+; LINUX: .type G1,@object
+; LINUX: .comm G1,4,4
+
+; DARWIN: .comm _G1,4,2
+
+
+
+
+; const int G2 __attribute__((weak)) = 42;
+@G2 = weak_odr constant i32 42
+
+
+; TODO: linux drops this into .rodata, we drop it into ".gnu.linkonce.r.G2"
+
+; DARWIN: .section __TEXT,__const_coal,coalesced
+; DARWIN: _G2:
+; DARWIN: .long 42
+
+
+; int * const G3 = &G1;
+@G3 = constant i32* @G1
+
+; DARWIN: .section __DATA,__const
+; DARWIN: .globl _G3
+; DARWIN: _G3:
+; DARWIN: .long _G1
+
+
+; _Complex long long const G4 = 34;
+@G4 = constant {i64,i64} { i64 34, i64 0 }
+
+; DARWIN: .section __TEXT,__const
+; DARWIN: _G4:
+; DARWIN: .long 34
+
+
+; int G5 = 47;
+@G5 = global i32 47
+
+; LINUX: .data
+; LINUX: .globl G5
+; LINUX: G5:
+; LINUX: .long 47
+
+; DARWIN: .section __DATA,__data
+; DARWIN: .globl _G5
+; DARWIN: _G5:
+; DARWIN: .long 47
+
+
+; PR4584
+@"foo bar" = linkonce global i32 42
+
+; LINUX: .type foo_20_bar,@object
+; LINUX:.section .gnu.linkonce.d.foo_20_bar,"aw",@progbits
+; LINUX: .weak foo_20_bar
+; LINUX: foo_20_bar:
+
+; DARWIN: .section __DATA,__datacoal_nt,coalesced
+; DARWIN: .globl "_foo bar"
+; DARWIN: .weak_definition "_foo bar"
+; DARWIN: "_foo bar":
+
+; PR4650
+@G6 = weak_odr constant [1 x i8] c"\01"
+
+; LINUX: .type G6,@object
+; LINUX: .section .gnu.linkonce.r.G6,"a",@progbits
+; LINUX: .weak G6
+; LINUX: G6:
+; LINUX: .byte 1
+; LINUX: .size G6, 1
+
+; DARWIN: .section __TEXT,__const_coal,coalesced
+; DARWIN: .globl _G6
+; DARWIN: .weak_definition _G6
+; DARWIN:_G6:
+; DARWIN: .byte 1
+
+
+@G7 = constant [10 x i8] c"abcdefghi\00"
+
+; DARWIN: __TEXT,__cstring,cstring_literals
+; DARWIN: .globl _G7
+; DARWIN: _G7:
+; DARWIN: .asciz "abcdefghi"
+
+; LINUX: .section .rodata.str1.1,"aMS",@progbits,1
+; LINUX: .globl G7
+; LINUX: G7:
+; LINUX: .asciz "abcdefghi"
+
+
+@G8 = constant [4 x i16] [ i16 1, i16 2, i16 3, i16 0 ]
+
+; DARWIN: .section __TEXT,__ustring
+; DARWIN: .globl _G8
+; DARWIN: _G8:
+
+; LINUX: .section .rodata.str2.2,"aMS",@progbits,2
+; LINUX: .globl G8
+; LINUX:G8:
+
+@G9 = constant [4 x i32] [ i32 1, i32 2, i32 3, i32 0 ]
+
+; DARWIN: .section __TEXT,__const
+; DARWIN: .globl _G9
+; DARWIN: _G9:
+
+; LINUX: .section .rodata.str4.4,"aMS",@progbits,4
+; LINUX: .globl G9
+; LINUX:G9
+
+
+@G10 = weak global [100 x i32] zeroinitializer, align 32 ; <[100 x i32]*> [#uses=0]
+
+
+; DARWIN: .section __DATA,__datacoal_nt,coalesced
+; DARWIN: .globl _G10
+; DARWIN: .weak_definition _G10
+; DARWIN: .align 5
+; DARWIN: _G10:
+; DARWIN: .space 400
+
+; LINUX: .bss
+; LINUX: .weak G10
+; LINUX: .align 32
+; LINUX: G10:
+; LINUX: .zero 400
+
diff --git a/test/CodeGen/X86/h-register-addressing-32.ll b/test/CodeGen/X86/h-register-addressing-32.ll
new file mode 100644
index 0000000..76ffd665
--- /dev/null
+++ b/test/CodeGen/X86/h-register-addressing-32.ll
@@ -0,0 +1,53 @@
+; RUN: llc < %s -march=x86 | grep {movzbl %\[abcd\]h,} | count 7
+
+; Use h-register extract and zero-extend.
+
+define double @foo8(double* nocapture inreg %p, i32 inreg %x) nounwind readonly {
+ %t0 = lshr i32 %x, 8
+ %t1 = and i32 %t0, 255
+ %t2 = getelementptr double* %p, i32 %t1
+ %t3 = load double* %t2, align 8
+ ret double %t3
+}
+define float @foo4(float* nocapture inreg %p, i32 inreg %x) nounwind readonly {
+ %t0 = lshr i32 %x, 8
+ %t1 = and i32 %t0, 255
+ %t2 = getelementptr float* %p, i32 %t1
+ %t3 = load float* %t2, align 8
+ ret float %t3
+}
+define i16 @foo2(i16* nocapture inreg %p, i32 inreg %x) nounwind readonly {
+ %t0 = lshr i32 %x, 8
+ %t1 = and i32 %t0, 255
+ %t2 = getelementptr i16* %p, i32 %t1
+ %t3 = load i16* %t2, align 8
+ ret i16 %t3
+}
+define i8 @foo1(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
+ %t0 = lshr i32 %x, 8
+ %t1 = and i32 %t0, 255
+ %t2 = getelementptr i8* %p, i32 %t1
+ %t3 = load i8* %t2, align 8
+ ret i8 %t3
+}
+define i8 @bar8(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
+ %t0 = lshr i32 %x, 5
+ %t1 = and i32 %t0, 2040
+ %t2 = getelementptr i8* %p, i32 %t1
+ %t3 = load i8* %t2, align 8
+ ret i8 %t3
+}
+define i8 @bar4(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
+ %t0 = lshr i32 %x, 6
+ %t1 = and i32 %t0, 1020
+ %t2 = getelementptr i8* %p, i32 %t1
+ %t3 = load i8* %t2, align 8
+ ret i8 %t3
+}
+define i8 @bar2(i8* nocapture inreg %p, i32 inreg %x) nounwind readonly {
+ %t0 = lshr i32 %x, 7
+ %t1 = and i32 %t0, 510
+ %t2 = getelementptr i8* %p, i32 %t1
+ %t3 = load i8* %t2, align 8
+ ret i8 %t3
+}
diff --git a/test/CodeGen/X86/h-register-addressing-64.ll b/test/CodeGen/X86/h-register-addressing-64.ll
new file mode 100644
index 0000000..98817f3
--- /dev/null
+++ b/test/CodeGen/X86/h-register-addressing-64.ll
@@ -0,0 +1,53 @@
+; RUN: llc < %s -march=x86-64 | grep {movzbl %\[abcd\]h,} | count 7
+
+; Use h-register extract and zero-extend.
+
+define double @foo8(double* nocapture inreg %p, i64 inreg %x) nounwind readonly {
+ %t0 = lshr i64 %x, 8
+ %t1 = and i64 %t0, 255
+ %t2 = getelementptr double* %p, i64 %t1
+ %t3 = load double* %t2, align 8
+ ret double %t3
+}
+define float @foo4(float* nocapture inreg %p, i64 inreg %x) nounwind readonly {
+ %t0 = lshr i64 %x, 8
+ %t1 = and i64 %t0, 255
+ %t2 = getelementptr float* %p, i64 %t1
+ %t3 = load float* %t2, align 8
+ ret float %t3
+}
+define i16 @foo2(i16* nocapture inreg %p, i64 inreg %x) nounwind readonly {
+ %t0 = lshr i64 %x, 8
+ %t1 = and i64 %t0, 255
+ %t2 = getelementptr i16* %p, i64 %t1
+ %t3 = load i16* %t2, align 8
+ ret i16 %t3
+}
+define i8 @foo1(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
+ %t0 = lshr i64 %x, 8
+ %t1 = and i64 %t0, 255
+ %t2 = getelementptr i8* %p, i64 %t1
+ %t3 = load i8* %t2, align 8
+ ret i8 %t3
+}
+define i8 @bar8(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
+ %t0 = lshr i64 %x, 5
+ %t1 = and i64 %t0, 2040
+ %t2 = getelementptr i8* %p, i64 %t1
+ %t3 = load i8* %t2, align 8
+ ret i8 %t3
+}
+define i8 @bar4(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
+ %t0 = lshr i64 %x, 6
+ %t1 = and i64 %t0, 1020
+ %t2 = getelementptr i8* %p, i64 %t1
+ %t3 = load i8* %t2, align 8
+ ret i8 %t3
+}
+define i8 @bar2(i8* nocapture inreg %p, i64 inreg %x) nounwind readonly {
+ %t0 = lshr i64 %x, 7
+ %t1 = and i64 %t0, 510
+ %t2 = getelementptr i8* %p, i64 %t1
+ %t3 = load i8* %t2, align 8
+ ret i8 %t3
+}
diff --git a/test/CodeGen/X86/h-register-store.ll b/test/CodeGen/X86/h-register-store.ll
new file mode 100644
index 0000000..d30e6b3
--- /dev/null
+++ b/test/CodeGen/X86/h-register-store.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: grep mov %t | count 6
+; RUN: grep {movb %ah, (%rsi)} %t | count 3
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep mov %t | count 3
+; RUN: grep {movb %ah, (%e} %t | count 3
+
+; Use h-register extract and store.
+
+define void @foo16(i16 inreg %p, i8* inreg %z) nounwind {
+ %q = lshr i16 %p, 8
+ %t = trunc i16 %q to i8
+ store i8 %t, i8* %z
+ ret void
+}
+define void @foo32(i32 inreg %p, i8* inreg %z) nounwind {
+ %q = lshr i32 %p, 8
+ %t = trunc i32 %q to i8
+ store i8 %t, i8* %z
+ ret void
+}
+define void @foo64(i64 inreg %p, i8* inreg %z) nounwind {
+ %q = lshr i64 %p, 8
+ %t = trunc i64 %q to i8
+ store i8 %t, i8* %z
+ ret void
+}
diff --git a/test/CodeGen/X86/h-registers-0.ll b/test/CodeGen/X86/h-registers-0.ll
new file mode 100644
index 0000000..878fd93
--- /dev/null
+++ b/test/CodeGen/X86/h-registers-0.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -march=x86-64 | grep {movzbl %\[abcd\]h,} | count 4
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep {incb %ah} %t | count 3
+; RUN: grep {movzbl %ah,} %t | count 3
+
+; Use h registers. On x86-64, codegen doesn't support general allocation
+; of h registers yet, due to x86 encoding complications.
+
+define void @bar64(i64 inreg %x, i8* inreg %p) nounwind {
+ %t0 = lshr i64 %x, 8
+ %t1 = trunc i64 %t0 to i8
+ %t2 = add i8 %t1, 1
+ store i8 %t2, i8* %p
+ ret void
+}
+
+define void @bar32(i32 inreg %x, i8* inreg %p) nounwind {
+ %t0 = lshr i32 %x, 8
+ %t1 = trunc i32 %t0 to i8
+ %t2 = add i8 %t1, 1
+ store i8 %t2, i8* %p
+ ret void
+}
+
+define void @bar16(i16 inreg %x, i8* inreg %p) nounwind {
+ %t0 = lshr i16 %x, 8
+ %t1 = trunc i16 %t0 to i8
+ %t2 = add i8 %t1, 1
+ store i8 %t2, i8* %p
+ ret void
+}
+
+define i64 @qux64(i64 inreg %x) nounwind {
+ %t0 = lshr i64 %x, 8
+ %t1 = and i64 %t0, 255
+ ret i64 %t1
+}
+
+define i32 @qux32(i32 inreg %x) nounwind {
+ %t0 = lshr i32 %x, 8
+ %t1 = and i32 %t0, 255
+ ret i32 %t1
+}
+
+define i16 @qux16(i16 inreg %x) nounwind {
+ %t0 = lshr i16 %x, 8
+ ret i16 %t0
+}
diff --git a/test/CodeGen/X86/h-registers-1.ll b/test/CodeGen/X86/h-registers-1.ll
new file mode 100644
index 0000000..e97ebab
--- /dev/null
+++ b/test/CodeGen/X86/h-registers-1.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: grep {movzbl %\[abcd\]h,} %t | count 8
+; RUN: grep {%\[abcd\]h} %t | not grep {%r\[\[:digit:\]\]*d}
+
+; LLVM creates virtual registers for values live across blocks
+; based on the type of the value. Make sure that the extracts
+; here use the GR64_NOREX register class for their result,
+; instead of plain GR64.
+
+define i64 @foo(i64 %a, i64 %b, i64 %c, i64 %d,
+ i64 %e, i64 %f, i64 %g, i64 %h) {
+ %sa = lshr i64 %a, 8
+ %A = and i64 %sa, 255
+ %sb = lshr i64 %b, 8
+ %B = and i64 %sb, 255
+ %sc = lshr i64 %c, 8
+ %C = and i64 %sc, 255
+ %sd = lshr i64 %d, 8
+ %D = and i64 %sd, 255
+ %se = lshr i64 %e, 8
+ %E = and i64 %se, 255
+ %sf = lshr i64 %f, 8
+ %F = and i64 %sf, 255
+ %sg = lshr i64 %g, 8
+ %G = and i64 %sg, 255
+ %sh = lshr i64 %h, 8
+ %H = and i64 %sh, 255
+ br label %next
+
+next:
+ %u = add i64 %A, %B
+ %v = add i64 %C, %D
+ %w = add i64 %E, %F
+ %x = add i64 %G, %H
+ %y = add i64 %u, %v
+ %z = add i64 %w, %x
+ %t = add i64 %y, %z
+ ret i64 %t
+}
diff --git a/test/CodeGen/X86/h-registers-2.ll b/test/CodeGen/X86/h-registers-2.ll
new file mode 100644
index 0000000..16e13f8
--- /dev/null
+++ b/test/CodeGen/X86/h-registers-2.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep {movzbl %\[abcd\]h,} %t | count 1
+; RUN: grep {shll \$3,} %t | count 1
+
+; Use an h register, but don't omit the explicit shift for
+; non-address use(s).
+
+define i32 @foo(i8* %x, i32 %y) nounwind {
+ %t0 = lshr i32 %y, 8 ; <i32> [#uses=1]
+ %t1 = and i32 %t0, 255 ; <i32> [#uses=2]
+ %t2 = shl i32 %t1, 3
+ %t3 = getelementptr i8* %x, i32 %t2 ; <i8*> [#uses=1]
+ store i8 77, i8* %t3, align 4
+ ret i32 %t2
+}
diff --git a/test/CodeGen/X86/h-registers-3.ll b/test/CodeGen/X86/h-registers-3.ll
new file mode 100644
index 0000000..8a0b07b
--- /dev/null
+++ b/test/CodeGen/X86/h-registers-3.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 | grep mov | count 1
+; RUN: llc < %s -march=x86-64 | grep mov | count 1
+
+define zeroext i8 @foo() nounwind ssp {
+entry:
+ %0 = tail call zeroext i16 (...)* @bar() nounwind
+ %1 = lshr i16 %0, 8
+ %2 = trunc i16 %1 to i8
+ ret i8 %2
+}
+
+declare zeroext i16 @bar(...)
diff --git a/test/CodeGen/X86/hidden-vis-2.ll b/test/CodeGen/X86/hidden-vis-2.ll
new file mode 100644
index 0000000..74554d1
--- /dev/null
+++ b/test/CodeGen/X86/hidden-vis-2.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | grep mov | count 1
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | not grep GOT
+
+@x = weak hidden global i32 0 ; <i32*> [#uses=1]
+
+define i32 @t() nounwind readonly {
+entry:
+ %0 = load i32* @x, align 4 ; <i32> [#uses=1]
+ ret i32 %0
+}
diff --git a/test/CodeGen/X86/hidden-vis-3.ll b/test/CodeGen/X86/hidden-vis-3.ll
new file mode 100644
index 0000000..4be881e
--- /dev/null
+++ b/test/CodeGen/X86/hidden-vis-3.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | FileCheck %s -check-prefix=X64
+
+@x = external hidden global i32 ; <i32*> [#uses=1]
+@y = extern_weak hidden global i32 ; <i32*> [#uses=1]
+
+define i32 @t() nounwind readonly {
+entry:
+; X32: _t:
+; X32: movl _y, %eax
+
+; X64: _t:
+; X64: movl _y(%rip), %eax
+
+ %0 = load i32* @x, align 4 ; <i32> [#uses=1]
+ %1 = load i32* @y, align 4 ; <i32> [#uses=1]
+ %2 = add i32 %1, %0 ; <i32> [#uses=1]
+ ret i32 %2
+}
diff --git a/test/CodeGen/X86/hidden-vis-4.ll b/test/CodeGen/X86/hidden-vis-4.ll
new file mode 100644
index 0000000..a8aede5
--- /dev/null
+++ b/test/CodeGen/X86/hidden-vis-4.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s
+
+@x = common hidden global i32 0 ; <i32*> [#uses=1]
+
+define i32 @t() nounwind readonly {
+entry:
+; CHECK: t:
+; CHECK: movl _x, %eax
+; CHECK: .comm _x,4
+ %0 = load i32* @x, align 4 ; <i32> [#uses=1]
+ ret i32 %0
+}
diff --git a/test/CodeGen/X86/hidden-vis-5.ll b/test/CodeGen/X86/hidden-vis-5.ll
new file mode 100644
index 0000000..88fae37
--- /dev/null
+++ b/test/CodeGen/X86/hidden-vis-5.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin9 -relocation-model=pic -disable-fp-elim -unwind-tables | FileCheck %s
+; <rdar://problem/7383328>
+
[email protected] = private constant [12 x i8] c"hello world\00", align 1 ; <[12 x i8]*> [#uses=1]
+
+define hidden void @func() nounwind ssp {
+entry:
+ %0 = call i32 @puts(i8* getelementptr inbounds ([12 x i8]* @.str, i64 0, i64 0)) nounwind ; <i32> [#uses=0]
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare i32 @puts(i8*)
+
+define hidden i32 @main() nounwind ssp {
+entry:
+ %retval = alloca i32 ; <i32*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ call void @func() nounwind
+ br label %return
+
+return: ; preds = %entry
+ %retval1 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval1
+}
+
+; CHECK: .private_extern _func.eh
+; CHECK: .private_extern _main.eh
diff --git a/test/CodeGen/X86/hidden-vis.ll b/test/CodeGen/X86/hidden-vis.ll
new file mode 100644
index 0000000..a948bdf
--- /dev/null
+++ b/test/CodeGen/X86/hidden-vis.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=i686-apple-darwin8 | FileCheck %s -check-prefix=DARWIN
+
+@a = hidden global i32 0
+@b = external global i32
+
+define weak hidden void @t1() nounwind {
+; LINUX: .hidden t1
+; LINUX: t1:
+
+; DARWIN: .private_extern _t1
+; DARWIN: t1:
+ ret void
+}
+
+define weak void @t2() nounwind {
+; LINUX: t2:
+; LINUX: .hidden a
+
+; DARWIN: t2:
+; DARWIN: .private_extern _a
+ ret void
+}
+
diff --git a/test/CodeGen/X86/i128-and-beyond.ll b/test/CodeGen/X86/i128-and-beyond.ll
new file mode 100644
index 0000000..b741681
--- /dev/null
+++ b/test/CodeGen/X86/i128-and-beyond.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep -- -1 | count 14
+
+; These static initializers are too big to hand off to assemblers
+; as monolithic blobs.
+
+@x = global i128 -1
+@y = global i256 -1
+@z = global i512 -1
diff --git a/test/CodeGen/X86/i128-immediate.ll b/test/CodeGen/X86/i128-immediate.ll
new file mode 100644
index 0000000..c47569e
--- /dev/null
+++ b/test/CodeGen/X86/i128-immediate.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=x86-64 | grep movq | count 2
+
+define i128 @__addvti3() {
+ ret i128 -1
+}
diff --git a/test/CodeGen/X86/i128-mul.ll b/test/CodeGen/X86/i128-mul.ll
new file mode 100644
index 0000000..e9d30d6
--- /dev/null
+++ b/test/CodeGen/X86/i128-mul.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86-64
+; PR1198
+
+define i64 @foo(i64 %x, i64 %y) {
+ %tmp0 = zext i64 %x to i128
+ %tmp1 = zext i64 %y to i128
+ %tmp2 = mul i128 %tmp0, %tmp1
+ %tmp7 = zext i32 64 to i128
+ %tmp3 = lshr i128 %tmp2, %tmp7
+ %tmp4 = trunc i128 %tmp3 to i64
+ ret i64 %tmp4
+}
diff --git a/test/CodeGen/X86/i128-ret.ll b/test/CodeGen/X86/i128-ret.ll
new file mode 100644
index 0000000..277f428
--- /dev/null
+++ b/test/CodeGen/X86/i128-ret.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86-64 | grep {movq 8(%rdi), %rdx}
+; RUN: llc < %s -march=x86-64 | grep {movq (%rdi), %rax}
+
+define i128 @test(i128 *%P) {
+ %A = load i128* %P
+ ret i128 %A
+}
+
diff --git a/test/CodeGen/X86/i256-add.ll b/test/CodeGen/X86/i256-add.ll
new file mode 100644
index 0000000..5a7a7a7
--- /dev/null
+++ b/test/CodeGen/X86/i256-add.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep adcl %t | count 7
+; RUN: grep sbbl %t | count 7
+
+define void @add(i256* %p, i256* %q) nounwind {
+ %a = load i256* %p
+ %b = load i256* %q
+ %c = add i256 %a, %b
+ store i256 %c, i256* %p
+ ret void
+}
+define void @sub(i256* %p, i256* %q) nounwind {
+ %a = load i256* %p
+ %b = load i256* %q
+ %c = sub i256 %a, %b
+ store i256 %c, i256* %p
+ ret void
+}
diff --git a/test/CodeGen/X86/i2k.ll b/test/CodeGen/X86/i2k.ll
new file mode 100644
index 0000000..6116c2e
--- /dev/null
+++ b/test/CodeGen/X86/i2k.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86
+
+define void @foo(i2011* %x, i2011* %y, i2011* %p) nounwind {
+ %a = load i2011* %x
+ %b = load i2011* %y
+ %c = add i2011 %a, %b
+ store i2011 %c, i2011* %p
+ ret void
+}
diff --git a/test/CodeGen/X86/i64-mem-copy.ll b/test/CodeGen/X86/i64-mem-copy.ll
new file mode 100644
index 0000000..847e209
--- /dev/null
+++ b/test/CodeGen/X86/i64-mem-copy.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86-64 | grep {movq.*(%rsi), %rax}
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {movsd.*(%eax),}
+
+; Uses movsd to load / store i64 values if sse2 is available.
+
+; rdar://6659858
+
+define void @foo(i64* %x, i64* %y) nounwind {
+entry:
+ %tmp1 = load i64* %y, align 8 ; <i64> [#uses=1]
+ store i64 %tmp1, i64* %x, align 8
+ ret void
+}
diff --git a/test/CodeGen/X86/iabs.ll b/test/CodeGen/X86/iabs.ll
new file mode 100644
index 0000000..6a79ee8
--- /dev/null
+++ b/test/CodeGen/X86/iabs.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86-64 -stats |& \
+; RUN: grep {6 .*Number of machine instrs printed}
+
+;; Integer absolute value, should produce something at least as good as:
+;; movl %edi, %eax
+;; sarl $31, %eax
+;; addl %eax, %edi
+;; xorl %eax, %edi
+;; movl %edi, %eax
+;; ret
+define i32 @test(i32 %a) nounwind {
+ %tmp1neg = sub i32 0, %a
+ %b = icmp sgt i32 %a, -1
+ %abs = select i1 %b, i32 %a, i32 %tmp1neg
+ ret i32 %abs
+}
+
diff --git a/test/CodeGen/X86/illegal-insert.ll b/test/CodeGen/X86/illegal-insert.ll
new file mode 100644
index 0000000..dbf1b14
--- /dev/null
+++ b/test/CodeGen/X86/illegal-insert.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86-64
+
+define <4 x double> @foo0(<4 x double> %t) {
+ %r = insertelement <4 x double> %t, double 2.3, i32 0
+ ret <4 x double> %r
+}
+define <4 x double> @foo1(<4 x double> %t) {
+ %r = insertelement <4 x double> %t, double 2.3, i32 1
+ ret <4 x double> %r
+}
+define <4 x double> @foo2(<4 x double> %t) {
+ %r = insertelement <4 x double> %t, double 2.3, i32 2
+ ret <4 x double> %r
+}
+define <4 x double> @foo3(<4 x double> %t) {
+ %r = insertelement <4 x double> %t, double 2.3, i32 3
+ ret <4 x double> %r
+}
diff --git a/test/CodeGen/X86/illegal-vector-args-return.ll b/test/CodeGen/X86/illegal-vector-args-return.ll
new file mode 100644
index 0000000..cecf77a
--- /dev/null
+++ b/test/CodeGen/X86/illegal-vector-args-return.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {mulpd %xmm3, %xmm1}
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {mulpd %xmm2, %xmm0}
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {addps %xmm3, %xmm1}
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {addps %xmm2, %xmm0}
+
+define <4 x double> @foo(<4 x double> %x, <4 x double> %z) {
+ %y = fmul <4 x double> %x, %z
+ ret <4 x double> %y
+}
+
+define <8 x float> @bar(<8 x float> %x, <8 x float> %z) {
+ %y = fadd <8 x float> %x, %z
+ ret <8 x float> %y
+}
diff --git a/test/CodeGen/X86/imp-def-copies.ll b/test/CodeGen/X86/imp-def-copies.ll
new file mode 100644
index 0000000..9117840
--- /dev/null
+++ b/test/CodeGen/X86/imp-def-copies.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=x86 | not grep mov
+
+ %struct.active_line = type { %struct.gs_fixed_point, %struct.gs_fixed_point, i32, i32, i32, %struct.line_segment*, i32, i16, i16, %struct.active_line*, %struct.active_line* }
+ %struct.gs_fixed_point = type { i32, i32 }
+ %struct.line_list = type { %struct.active_line*, i32, i16, %struct.active_line*, %struct.active_line*, %struct.active_line*, %struct.active_line, i32 }
+ %struct.line_segment = type { %struct.line_segment*, %struct.line_segment*, i32, %struct.gs_fixed_point }
+ %struct.subpath = type { %struct.line_segment*, %struct.line_segment*, i32, %struct.gs_fixed_point, %struct.line_segment*, i32, i32, i8 }
+
+define fastcc void @add_y_list(%struct.subpath* %ppath.0.4.val, i16 signext %tag, %struct.line_list* %ll, i32 %pbox.0.0.1.val, i32 %pbox.0.1.0.val, i32 %pbox.0.1.1.val) nounwind {
+entry:
+ br i1 false, label %return, label %bb
+bb: ; preds = %bb280, %entry
+ %psub.1.reg2mem.0 = phi %struct.subpath* [ %psub.0.reg2mem.0, %bb280 ], [ undef, %entry ] ; <%struct.subpath*> [#uses=1]
+ %plast.1.reg2mem.0 = phi %struct.line_segment* [ %plast.0.reg2mem.0, %bb280 ], [ undef, %entry ] ; <%struct.line_segment*> [#uses=1]
+ %prev_dir.0.reg2mem.0 = phi i32 [ %dir.0.reg2mem.0, %bb280 ], [ undef, %entry ] ; <i32> [#uses=1]
+ br i1 false, label %bb280, label %bb109
+bb109: ; preds = %bb
+ %tmp113 = icmp sgt i32 0, %prev_dir.0.reg2mem.0 ; <i1> [#uses=1]
+ br i1 %tmp113, label %bb116, label %bb280
+bb116: ; preds = %bb109
+ ret void
+bb280: ; preds = %bb109, %bb
+ %psub.0.reg2mem.0 = phi %struct.subpath* [ null, %bb ], [ %psub.1.reg2mem.0, %bb109 ] ; <%struct.subpath*> [#uses=1]
+ %plast.0.reg2mem.0 = phi %struct.line_segment* [ null, %bb ], [ %plast.1.reg2mem.0, %bb109 ] ; <%struct.line_segment*> [#uses=1]
+ %dir.0.reg2mem.0 = phi i32 [ 0, %bb ], [ 0, %bb109 ] ; <i32> [#uses=1]
+ br i1 false, label %return, label %bb
+return: ; preds = %bb280, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/imul-lea-2.ll b/test/CodeGen/X86/imul-lea-2.ll
new file mode 100644
index 0000000..1cb54b3
--- /dev/null
+++ b/test/CodeGen/X86/imul-lea-2.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86-64 | grep lea | count 3
+; RUN: llc < %s -march=x86-64 | grep shl | count 1
+; RUN: llc < %s -march=x86-64 | not grep imul
+
+define i64 @t1(i64 %a) nounwind readnone {
+entry:
+ %0 = mul i64 %a, 81 ; <i64> [#uses=1]
+ ret i64 %0
+}
+
+define i64 @t2(i64 %a) nounwind readnone {
+entry:
+ %0 = mul i64 %a, 40 ; <i64> [#uses=1]
+ ret i64 %0
+}
diff --git a/test/CodeGen/X86/imul-lea.ll b/test/CodeGen/X86/imul-lea.ll
new file mode 100644
index 0000000..4e8e2af
--- /dev/null
+++ b/test/CodeGen/X86/imul-lea.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 | grep lea
+
+declare i32 @foo()
+
+define i32 @test() {
+ %tmp.0 = tail call i32 @foo( ) ; <i32> [#uses=1]
+ %tmp.1 = mul i32 %tmp.0, 9 ; <i32> [#uses=1]
+ ret i32 %tmp.1
+}
+
diff --git a/test/CodeGen/X86/inline-asm-2addr.ll b/test/CodeGen/X86/inline-asm-2addr.ll
new file mode 100644
index 0000000..4a2c7fc
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-2addr.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86-64 | not grep movq
+
+define i64 @t(i64 %a, i64 %b) nounwind ssp {
+entry:
+ %asmtmp = tail call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i64 %a) nounwind ; <i64> [#uses=1]
+ %asmtmp1 = tail call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i64 %b) nounwind ; <i64> [#uses=1]
+ %0 = add i64 %asmtmp1, %asmtmp ; <i64> [#uses=1]
+ ret i64 %0
+}
diff --git a/test/CodeGen/X86/inline-asm-R-constraint.ll b/test/CodeGen/X86/inline-asm-R-constraint.ll
new file mode 100644
index 0000000..66c27ac
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-R-constraint.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=x86-64 < %s | FileCheck %s
+; 7282062
+; ModuleID = '<stdin>'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin10.0"
+
+define void @udiv8(i8* %quotient, i16 zeroext %a, i8 zeroext %b, i8 zeroext %c, i8* %remainder) nounwind ssp {
+entry:
+; CHECK: udiv8:
+; CHECK-NOT: movb %ah, (%r8)
+ %a_addr = alloca i16, align 2 ; <i16*> [#uses=2]
+ %b_addr = alloca i8, align 1 ; <i8*> [#uses=2]
+ store i16 %a, i16* %a_addr
+ store i8 %b, i8* %b_addr
+ call void asm "\09\09movw\09$2, %ax\09\09\0A\09\09divb\09$3\09\09\09\0A\09\09movb\09%al, $0\09\0A\09\09movb %ah, ($4)", "=*m,=*m,*m,*m,R,~{dirflag},~{fpsr},~{flags},~{ax}"(i8* %quotient, i8* %remainder, i16* %a_addr, i8* %b_addr, i8* %remainder) nounwind
+ ret void
+; CHECK: ret
+}
diff --git a/test/CodeGen/X86/inline-asm-flag-clobber.ll b/test/CodeGen/X86/inline-asm-flag-clobber.ll
new file mode 100644
index 0000000..51ea843
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-flag-clobber.ll
@@ -0,0 +1,19 @@
+; RUN: llc -march=x86-64 < %s | FileCheck %s
+; PR3701
+
+define i64 @t(i64* %arg) nounwind {
+ br i1 true, label %1, label %5
+
+; <label>:1 ; preds = %0
+ %2 = icmp eq i64* null, %arg ; <i1> [#uses=1]
+ %3 = tail call i64* asm sideeffect "movl %fs:0,$0", "=r,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%struct.thread*> [#uses=0]
+; CHECK: test
+; CHECK-NEXT: j
+ br i1 %2, label %4, label %5
+
+; <label>:4 ; preds = %1
+ ret i64 1
+
+; <label>:5 ; preds = %1
+ ret i64 0
+}
diff --git a/test/CodeGen/X86/inline-asm-fpstack.ll b/test/CodeGen/X86/inline-asm-fpstack.ll
new file mode 100644
index 0000000..09b0929
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-fpstack.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -march=x86
+
+define x86_fp80 @test1() {
+ %tmp85 = call x86_fp80 asm sideeffect "fld0", "={st(0)}"()
+ ret x86_fp80 %tmp85
+}
+
+define double @test2() {
+ %tmp85 = call double asm sideeffect "fld0", "={st(0)}"()
+ ret double %tmp85
+}
+
+define void @test3(x86_fp80 %X) {
+ call void asm sideeffect "frob ", "{st(0)},~{dirflag},~{fpsr},~{flags}"( x86_fp80 %X)
+ ret void
+}
+
+define void @test4(double %X) {
+ call void asm sideeffect "frob ", "{st(0)},~{dirflag},~{fpsr},~{flags}"( double %X)
+ ret void
+}
+
+define void @test5(double %X) {
+ %Y = fadd double %X, 123.0
+ call void asm sideeffect "frob ", "{st(0)},~{dirflag},~{fpsr},~{flags}"( double %Y)
+ ret void
+}
+
+define void @test6(double %A, double %B, double %C,
+ double %D, double %E) nounwind {
+entry:
+ ; Uses the same value twice, should have one fstp after the asm.
+ tail call void asm sideeffect "foo $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %A, double %A ) nounwind
+ ; Uses two different values, should be in st(0)/st(1) and both be popped.
+ tail call void asm sideeffect "bar $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %B, double %C ) nounwind
+ ; Uses two different values, one of which isn't killed in this asm, it
+ ; should not be popped after the asm.
+ tail call void asm sideeffect "baz $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %D, double %E ) nounwind
+ ; This is the last use of %D, so it should be popped after.
+ tail call void asm sideeffect "baz $0", "f,~{dirflag},~{fpsr},~{flags}"( double %D ) nounwind
+ ret void
+}
+
diff --git a/test/CodeGen/X86/inline-asm-fpstack2.ll b/test/CodeGen/X86/inline-asm-fpstack2.ll
new file mode 100644
index 0000000..ffa6ee6
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-fpstack2.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep {fld %%st(0)} %t
+; PR4185
+
+define void @test() {
+return:
+ call void asm sideeffect "fistpl $0", "{st}"(double 1.000000e+06)
+ call void asm sideeffect "fistpl $0", "{st}"(double 1.000000e+06)
+ ret void
+}
diff --git a/test/CodeGen/X86/inline-asm-fpstack3.ll b/test/CodeGen/X86/inline-asm-fpstack3.ll
new file mode 100644
index 0000000..17945fe
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-fpstack3.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep {fld %%st(0)} %t
+; PR4459
+
+declare x86_fp80 @ceil(x86_fp80)
+
+declare void @test(x86_fp80)
+
+define void @test2(x86_fp80 %a) {
+entry:
+ %0 = call x86_fp80 @ceil(x86_fp80 %a)
+ call void asm sideeffect "fistpl $0", "{st}"( x86_fp80 %0)
+ call void @test(x86_fp80 %0 )
+ ret void
+}
diff --git a/test/CodeGen/X86/inline-asm-fpstack4.ll b/test/CodeGen/X86/inline-asm-fpstack4.ll
new file mode 100644
index 0000000..bae2970
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-fpstack4.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86
+; PR4484
+
+declare x86_fp80 @ceil()
+
+declare void @test(x86_fp80)
+
+define void @test2(x86_fp80 %a) {
+entry:
+ %0 = call x86_fp80 @ceil()
+ call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %a)
+ call void @test(x86_fp80 %0)
+ ret void
+}
+
diff --git a/test/CodeGen/X86/inline-asm-fpstack5.ll b/test/CodeGen/X86/inline-asm-fpstack5.ll
new file mode 100644
index 0000000..8b219cf
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-fpstack5.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86
+; PR4485
+
+define void @test(x86_fp80* %a) {
+entry:
+ %0 = load x86_fp80* %a, align 16
+ %1 = fmul x86_fp80 %0, 0xK4006B400000000000000
+ %2 = fmul x86_fp80 %1, 0xK4012F424000000000000
+ tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %2)
+ %3 = load x86_fp80* %a, align 16
+ %4 = fmul x86_fp80 %3, 0xK4006B400000000000000
+ %5 = fmul x86_fp80 %4, 0xK4012F424000000000000
+ tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %5)
+ ret void
+}
diff --git a/test/CodeGen/X86/inline-asm-modifier-n.ll b/test/CodeGen/X86/inline-asm-modifier-n.ll
new file mode 100644
index 0000000..5e76b6c
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-modifier-n.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 | grep { 37}
+; rdar://7008959
+
+define void @bork() nounwind {
+entry:
+ tail call void asm sideeffect "BORK ${0:n}", "i,~{dirflag},~{fpsr},~{flags}"(i32 -37) nounwind
+ ret void
+}
diff --git a/test/CodeGen/X86/inline-asm-mrv.ll b/test/CodeGen/X86/inline-asm-mrv.ll
new file mode 100644
index 0000000..78d7e77
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-mrv.ll
@@ -0,0 +1,35 @@
+; PR2094
+; RUN: llc < %s -march=x86-64 | grep movslq
+; RUN: llc < %s -march=x86-64 | grep addps
+; RUN: llc < %s -march=x86-64 | grep paddd
+; RUN: llc < %s -march=x86-64 | not grep movq
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin8"
+
+define i32 @test1(i8* %v, i8* %blk2, i8* %blk1, i32 %stride, i32 %h) nounwind {
+ %tmp12 = sext i32 %stride to i64 ; <i64> [#uses=1]
+ %mrv = call {i32, i8*, i8*} asm sideeffect "$0 $1 $2 $3 $4 $5 $6",
+ "=r,=r,=r,r,r,r,r"( i64 %tmp12, i32 %h, i8* %blk1, i8* %blk2 ) nounwind
+ %tmp6 = getresult {i32, i8*, i8*} %mrv, 0
+ %tmp7 = call i32 asm sideeffect "set $0",
+ "=r,~{dirflag},~{fpsr},~{flags}"( ) nounwind
+ ret i32 %tmp7
+}
+
+define <4 x float> @test2() nounwind {
+ %mrv = call {<4 x float>, <4 x float>} asm "set $0, $1", "=x,=x"()
+ %a = getresult {<4 x float>, <4 x float>} %mrv, 0
+ %b = getresult {<4 x float>, <4 x float>} %mrv, 1
+ %c = fadd <4 x float> %a, %b
+ ret <4 x float> %c
+}
+
+define <4 x i32> @test3() nounwind {
+ %mrv = call {<4 x i32>, <4 x i32>} asm "set $0, $1", "=x,=x"()
+ %a = getresult {<4 x i32>, <4 x i32>} %mrv, 0
+ %b = getresult {<4 x i32>, <4 x i32>} %mrv, 1
+ %c = add <4 x i32> %a, %b
+ ret <4 x i32> %c
+}
+
diff --git a/test/CodeGen/X86/inline-asm-out-regs.ll b/test/CodeGen/X86/inline-asm-out-regs.ll
new file mode 100644
index 0000000..46966f5
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-out-regs.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu
+; PR3391
+
+@pci_indirect = external global { } ; <{ }*> [#uses=1]
+@pcibios_last_bus = external global i32 ; <i32*> [#uses=2]
+
+define void @pci_pcbios_init() nounwind section ".init.text" {
+entry:
+ br label %bb1.i
+
+bb1.i: ; preds = %bb6.i.i, %bb1.i, %entry
+ %0 = load i32* null, align 8 ; <i32> [#uses=1]
+ %1 = icmp ugt i32 %0, 1048575 ; <i1> [#uses=1]
+ br i1 %1, label %bb2.i, label %bb1.i
+
+bb2.i: ; preds = %bb1.i
+ %asmtmp.i.i = tail call { i32, i32, i32, i32 } asm "lcall *(%edi); cld\0A\09jc 1f\0A\09xor %ah, %ah\0A1:", "={dx},={ax},={bx},={cx},1,{di},~{dirflag},~{fpsr},~{flags},~{memory}"(i32 45313, { }* @pci_indirect) nounwind ; <{ i32, i32, i32, i32 }> [#uses=2]
+ %asmresult2.i.i = extractvalue { i32, i32, i32, i32 } %asmtmp.i.i, 1
+ ; <i32> [#uses=1]
+ %2 = lshr i32 %asmresult2.i.i, 8 ; <i32> [#uses=1]
+ %3 = trunc i32 %2 to i8 ; <i8> [#uses=1]
+ %4 = load i32* @pcibios_last_bus, align 4 ; <i32> [#uses=1]
+ %5 = icmp slt i32 %4, 0 ; <i1> [#uses=1]
+ br i1 %5, label %bb5.i.i, label %bb6.i.i
+
+bb5.i.i: ; preds = %bb2.i
+ %asmresult4.i.i = extractvalue { i32, i32, i32, i32 } %asmtmp.i.i, 3
+ ; <i32> [#uses=1]
+ %6 = and i32 %asmresult4.i.i, 255 ; <i32> [#uses=1]
+ store i32 %6, i32* @pcibios_last_bus, align 4
+ br label %bb6.i.i
+
+bb6.i.i: ; preds = %bb5.i.i, %bb2.i
+ %7 = icmp eq i8 %3, 0 ; <i1> [#uses=1]
+ %or.cond.i.i = and i1 %7, false ; <i1> [#uses=1]
+ br i1 %or.cond.i.i, label %bb1.i, label %bb8.i.i
+
+bb8.i.i: ; preds = %bb6.i.i
+ unreachable
+}
diff --git a/test/CodeGen/X86/inline-asm-pic.ll b/test/CodeGen/X86/inline-asm-pic.ll
new file mode 100644
index 0000000..0b5ff08
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-pic.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic | grep lea
+; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic | grep call
+
+@main_q = internal global i8* null ; <i8**> [#uses=1]
+
+define void @func2() nounwind {
+entry:
+ tail call void asm "mov $1,%gs:$0", "=*m,ri,~{dirflag},~{fpsr},~{flags}"(i8** inttoptr (i32 152 to i8**), i8* bitcast (i8** @main_q to i8*)) nounwind
+ ret void
+}
diff --git a/test/CodeGen/X86/inline-asm-q-regs.ll b/test/CodeGen/X86/inline-asm-q-regs.ll
new file mode 100644
index 0000000..ab44206
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-q-regs.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86-64
+; rdar://7066579
+
+ type { i64, i64, i64, i64, i64 } ; type %0
+
+define void @t() nounwind {
+entry:
+ %asmtmp = call %0 asm sideeffect "mov %cr0, $0 \0Amov %cr2, $1 \0Amov %cr3, $2 \0Amov %cr4, $3 \0Amov %cr8, $0 \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%0> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/X86/inline-asm-tied.ll b/test/CodeGen/X86/inline-asm-tied.ll
new file mode 100644
index 0000000..1f4a13f
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-tied.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 | grep {movl %edx, 12(%esp)} | count 2
+; rdar://6992609
+
+target triple = "i386-apple-darwin9.0"
[email protected] = appending global [1 x i8*] [i8* bitcast (i64 (i64)* @_OSSwapInt64 to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define i64 @_OSSwapInt64(i64 %_data) nounwind {
+entry:
+ %retval = alloca i64 ; <i64*> [#uses=2]
+ %_data.addr = alloca i64 ; <i64*> [#uses=4]
+ store i64 %_data, i64* %_data.addr
+ %tmp = load i64* %_data.addr ; <i64> [#uses=1]
+ %0 = call i64 asm "bswap %eax\0A\09bswap %edx\0A\09xchgl %eax, %edx", "=A,0,~{dirflag},~{fpsr},~{flags}"(i64 %tmp) nounwind ; <i64> [#uses=1]
+ store i64 %0, i64* %_data.addr
+ %tmp1 = load i64* %_data.addr ; <i64> [#uses=1]
+ store i64 %tmp1, i64* %retval
+ %1 = load i64* %retval ; <i64> [#uses=1]
+ ret i64 %1
+}
diff --git a/test/CodeGen/X86/inline-asm-x-scalar.ll b/test/CodeGen/X86/inline-asm-x-scalar.ll
new file mode 100644
index 0000000..5a9628b
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-x-scalar.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah
+
+define void @test1() {
+ tail call void asm sideeffect "ucomiss $0", "x"( float 0x41E0000000000000)
+ ret void
+}
+
+define void @test2() {
+ %tmp53 = tail call i32 asm "ucomiss $1, $3\0Acmovae $2, $0 ", "=r,mx,mr,x,0,~{dirflag},~{fpsr},~{flags},~{cc}"( float 0x41E0000000000000, i32 2147483647, float 0.000000e+00, i32 0 ) ; <i32> [#uses
+ unreachable
+}
+
+define void @test3() {
+ tail call void asm sideeffect "ucomiss $0, $1", "mx,x,~{dirflag},~{fpsr},~{flags},~{cc}"( float 0x41E0000000000000, i32 65536 )
+ ret void
+}
+
+define void @test4() {
+ %tmp1 = tail call float asm "", "=x,0,~{dirflag},~{fpsr},~{flags}"( float 0x47EFFFFFE0000000 ); <float> [#uses=1]
+ %tmp4 = fsub float %tmp1, 0x3810000000000000 ; <float> [#uses=1]
+ tail call void asm sideeffect "", "x,~{dirflag},~{fpsr},~{flags}"( float %tmp4 )
+ ret void
+}
+
diff --git a/test/CodeGen/X86/inline-asm.ll b/test/CodeGen/X86/inline-asm.ll
new file mode 100644
index 0000000..c66d7a8
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86
+
+define i32 @test1() nounwind {
+ ; Dest is AX, dest type = i32.
+ %tmp4 = call i32 asm sideeffect "FROB $0", "={ax}"()
+ ret i32 %tmp4
+}
+
+define void @test2(i32 %V) nounwind {
+ ; input is AX, in type = i32.
+ call void asm sideeffect "FROB $0", "{ax}"(i32 %V)
+ ret void
+}
+
+define void @test3() nounwind {
+ ; FP constant as a memory operand.
+ tail call void asm sideeffect "frob $0", "m"( float 0x41E0000000000000)
+ ret void
+}
+
+define void @test4() nounwind {
+ ; J means a constant in range 0 to 63.
+ tail call void asm sideeffect "bork $0", "J"(i32 37) nounwind
+ ret void
+}
diff --git a/test/CodeGen/X86/ins_subreg_coalesce-1.ll b/test/CodeGen/X86/ins_subreg_coalesce-1.ll
new file mode 100644
index 0000000..2243f93
--- /dev/null
+++ b/test/CodeGen/X86/ins_subreg_coalesce-1.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 | grep mov | count 3
+
+define fastcc i32 @sqlite3ExprResolveNames() nounwind {
+entry:
+ br i1 false, label %UnifiedReturnBlock, label %bb4
+bb4: ; preds = %entry
+ br i1 false, label %bb17, label %bb22
+bb17: ; preds = %bb4
+ ret i32 1
+bb22: ; preds = %bb4
+ br i1 true, label %walkExprTree.exit, label %bb4.i
+bb4.i: ; preds = %bb22
+ ret i32 0
+walkExprTree.exit: ; preds = %bb22
+ %tmp83 = load i16* null, align 4 ; <i16> [#uses=1]
+ %tmp84 = or i16 %tmp83, 2 ; <i16> [#uses=2]
+ store i16 %tmp84, i16* null, align 4
+ %tmp98993 = zext i16 %tmp84 to i32 ; <i32> [#uses=1]
+ %tmp1004 = lshr i32 %tmp98993, 3 ; <i32> [#uses=1]
+ %tmp100.lobit5 = and i32 %tmp1004, 1 ; <i32> [#uses=1]
+ ret i32 %tmp100.lobit5
+UnifiedReturnBlock: ; preds = %entry
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/ins_subreg_coalesce-2.ll b/test/CodeGen/X86/ins_subreg_coalesce-2.ll
new file mode 100644
index 0000000..f2c9cc7
--- /dev/null
+++ b/test/CodeGen/X86/ins_subreg_coalesce-2.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86-64 | not grep movw
+
+define i16 @test5(i16 %f12) nounwind {
+ %f11 = shl i16 %f12, 2 ; <i16> [#uses=1]
+ %tmp7.25 = ashr i16 %f11, 8 ; <i16> [#uses=1]
+ ret i16 %tmp7.25
+}
diff --git a/test/CodeGen/X86/ins_subreg_coalesce-3.ll b/test/CodeGen/X86/ins_subreg_coalesce-3.ll
new file mode 100644
index 0000000..627edc5
--- /dev/null
+++ b/test/CodeGen/X86/ins_subreg_coalesce-3.ll
@@ -0,0 +1,93 @@
+; RUN: llc < %s -march=x86-64 | grep mov | count 5
+
+ %struct.COMPOSITE = type { i8, i16, i16 }
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.FILE_POS = type { i8, i8, i16, i32 }
+ %struct.FIRST_UNION = type { %struct.FILE_POS }
+ %struct.FONT_INFO = type { %struct.metrics*, i8*, i16*, %struct.COMPOSITE*, i32, %struct.rec*, %struct.rec*, i16, i16, i16*, i8*, i8*, i16* }
+ %struct.FOURTH_UNION = type { %struct.STYLE }
+ %struct.GAP = type { i8, i8, i16 }
+ %struct.LIST = type { %struct.rec*, %struct.rec* }
+ %struct.SECOND_UNION = type { { i16, i8, i8 } }
+ %struct.STYLE = type { { %struct.GAP }, { %struct.GAP }, i16, i16, i32 }
+ %struct.THIRD_UNION = type { %struct.FILE*, [8 x i8] }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+ %struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, %struct.rec*, { %struct.rec* }, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i32 }
+ %struct.metrics = type { i16, i16, i16, i16, i16 }
+ %struct.rec = type { %struct.head_type }
+
+define void @FontChange(i1 %foo) nounwind {
+entry:
+ br i1 %foo, label %bb298, label %bb49
+bb49: ; preds = %entry
+ ret void
+bb298: ; preds = %entry
+ br i1 %foo, label %bb304, label %bb366
+bb304: ; preds = %bb298
+ br i1 %foo, label %bb330, label %bb428
+bb330: ; preds = %bb366, %bb304
+ br label %bb366
+bb366: ; preds = %bb330, %bb298
+ br i1 %foo, label %bb330, label %bb428
+bb428: ; preds = %bb366, %bb304
+ br i1 %foo, label %bb650, label %bb433
+bb433: ; preds = %bb428
+ ret void
+bb650: ; preds = %bb650, %bb428
+ %tmp658 = load i8* null, align 8 ; <i8> [#uses=1]
+ %tmp659 = icmp eq i8 %tmp658, 0 ; <i1> [#uses=1]
+ br i1 %tmp659, label %bb650, label %bb662
+bb662: ; preds = %bb650
+ %tmp685 = icmp eq %struct.rec* null, null ; <i1> [#uses=1]
+ br i1 %tmp685, label %bb761, label %bb688
+bb688: ; preds = %bb662
+ ret void
+bb761: ; preds = %bb662
+ %tmp487248736542 = load i32* null, align 4 ; <i32> [#uses=2]
+ %tmp487648776541 = and i32 %tmp487248736542, 57344 ; <i32> [#uses=1]
+ %tmp4881 = icmp eq i32 %tmp487648776541, 8192 ; <i1> [#uses=1]
+ br i1 %tmp4881, label %bb4884, label %bb4897
+bb4884: ; preds = %bb761
+ %tmp488948906540 = and i32 %tmp487248736542, 7168 ; <i32> [#uses=1]
+ %tmp4894 = icmp eq i32 %tmp488948906540, 1024 ; <i1> [#uses=1]
+ br i1 %tmp4894, label %bb4932, label %bb4897
+bb4897: ; preds = %bb4884, %bb761
+ ret void
+bb4932: ; preds = %bb4884
+ %tmp4933 = load i32* null, align 4 ; <i32> [#uses=1]
+ br i1 %foo, label %bb5054, label %bb4940
+bb4940: ; preds = %bb4932
+ %tmp4943 = load i32* null, align 4 ; <i32> [#uses=2]
+ switch i32 %tmp4933, label %bb5054 [
+ i32 159, label %bb4970
+ i32 160, label %bb5002
+ ]
+bb4970: ; preds = %bb4940
+ %tmp49746536 = trunc i32 %tmp4943 to i16 ; <i16> [#uses=1]
+ %tmp49764977 = and i16 %tmp49746536, 4095 ; <i16> [#uses=1]
+ %mask498049814982 = zext i16 %tmp49764977 to i64 ; <i64> [#uses=1]
+ %tmp4984 = getelementptr %struct.FONT_INFO* null, i64 %mask498049814982, i32 5 ; <%struct.rec**> [#uses=1]
+ %tmp4985 = load %struct.rec** %tmp4984, align 8 ; <%struct.rec*> [#uses=1]
+ %tmp4988 = getelementptr %struct.rec* %tmp4985, i64 0, i32 0, i32 3 ; <%struct.THIRD_UNION*> [#uses=1]
+ %tmp4991 = bitcast %struct.THIRD_UNION* %tmp4988 to i32* ; <i32*> [#uses=1]
+ %tmp4992 = load i32* %tmp4991, align 8 ; <i32> [#uses=1]
+ %tmp49924993 = trunc i32 %tmp4992 to i16 ; <i16> [#uses=1]
+ %tmp4996 = add i16 %tmp49924993, 0 ; <i16> [#uses=1]
+ br label %bb5054
+bb5002: ; preds = %bb4940
+ %tmp50066537 = trunc i32 %tmp4943 to i16 ; <i16> [#uses=1]
+ %tmp50085009 = and i16 %tmp50066537, 4095 ; <i16> [#uses=1]
+ %mask501250135014 = zext i16 %tmp50085009 to i64 ; <i64> [#uses=1]
+ %tmp5016 = getelementptr %struct.FONT_INFO* null, i64 %mask501250135014, i32 5 ; <%struct.rec**> [#uses=1]
+ %tmp5017 = load %struct.rec** %tmp5016, align 8 ; <%struct.rec*> [#uses=1]
+ %tmp5020 = getelementptr %struct.rec* %tmp5017, i64 0, i32 0, i32 3 ; <%struct.THIRD_UNION*> [#uses=1]
+ %tmp5023 = bitcast %struct.THIRD_UNION* %tmp5020 to i32* ; <i32*> [#uses=1]
+ %tmp5024 = load i32* %tmp5023, align 8 ; <i32> [#uses=1]
+ %tmp50245025 = trunc i32 %tmp5024 to i16 ; <i16> [#uses=1]
+ %tmp5028 = sub i16 %tmp50245025, 0 ; <i16> [#uses=1]
+ br label %bb5054
+bb5054: ; preds = %bb5002, %bb4970, %bb4940, %bb4932
+ %flen.0.reg2mem.0 = phi i16 [ %tmp4996, %bb4970 ], [ %tmp5028, %bb5002 ], [ 0, %bb4932 ], [ undef, %bb4940 ] ; <i16> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/X86/insertelement-copytoregs.ll b/test/CodeGen/X86/insertelement-copytoregs.ll
new file mode 100644
index 0000000..34a29ca
--- /dev/null
+++ b/test/CodeGen/X86/insertelement-copytoregs.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86-64 | grep -v IMPLICIT_DEF
+
+define void @foo(<2 x float>* %p) {
+ %t = insertelement <2 x float> undef, float 0.0, i32 0
+ %v = insertelement <2 x float> %t, float 0.0, i32 1
+ br label %bb8
+
+bb8:
+ store <2 x float> %v, <2 x float>* %p
+ ret void
+}
diff --git a/test/CodeGen/X86/insertelement-legalize.ll b/test/CodeGen/X86/insertelement-legalize.ll
new file mode 100644
index 0000000..18aade2
--- /dev/null
+++ b/test/CodeGen/X86/insertelement-legalize.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 -disable-mmx
+
+; Test to check that we properly legalize an insert vector element
+define void @test(<2 x i64> %val, <2 x i64>* %dst, i64 %x) nounwind {
+entry:
+ %tmp4 = insertelement <2 x i64> %val, i64 %x, i32 0 ; <<2 x i64>> [#uses=1]
+ %add = add <2 x i64> %tmp4, %val ; <<2 x i64>> [#uses=1]
+ store <2 x i64> %add, <2 x i64>* %dst
+ ret void
+}
diff --git a/test/CodeGen/X86/invalid-shift-immediate.ll b/test/CodeGen/X86/invalid-shift-immediate.ll
new file mode 100644
index 0000000..77a9f7e
--- /dev/null
+++ b/test/CodeGen/X86/invalid-shift-immediate.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=x86
+; PR2098
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+
+define void @foo(i32 %x) {
+entry:
+ %x_addr = alloca i32 ; <i32*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %x, i32* %x_addr
+ %tmp = load i32* %x_addr, align 4 ; <i32> [#uses=1]
+ %tmp1 = ashr i32 %tmp, -2 ; <i32> [#uses=1]
+ %tmp2 = and i32 %tmp1, 1 ; <i32> [#uses=1]
+ %tmp23 = trunc i32 %tmp2 to i8 ; <i8> [#uses=1]
+ %toBool = icmp ne i8 %tmp23, 0 ; <i1> [#uses=1]
+ br i1 %toBool, label %bb, label %bb5
+
+bb: ; preds = %entry
+ %tmp4 = call i32 (...)* @bar( ) nounwind ; <i32> [#uses=0]
+ br label %bb5
+
+bb5: ; preds = %bb, %entry
+ br label %return
+
+return: ; preds = %bb5
+ ret void
+}
+
+declare i32 @bar(...)
diff --git a/test/CodeGen/X86/isel-sink.ll b/test/CodeGen/X86/isel-sink.ll
new file mode 100644
index 0000000..0f94b23
--- /dev/null
+++ b/test/CodeGen/X86/isel-sink.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 | not grep lea
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin8 | \
+; RUN: grep {movl \$4, (.*,.*,4)}
+
+define i32 @test(i32* %X, i32 %B) {
+ ; This gep should be sunk out of this block into the load/store users.
+ %P = getelementptr i32* %X, i32 %B
+ %G = icmp ult i32 %B, 1234
+ br i1 %G, label %T, label %F
+T:
+ store i32 4, i32* %P
+ ret i32 141
+F:
+ %V = load i32* %P
+ ret i32 %V
+}
+
+
diff --git a/test/CodeGen/X86/isel-sink2.ll b/test/CodeGen/X86/isel-sink2.ll
new file mode 100644
index 0000000..5ed0e00
--- /dev/null
+++ b/test/CodeGen/X86/isel-sink2.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep {movb.7(%...)} %t
+; RUN: not grep leal %t
+
+define i8 @test(i32 *%P) nounwind {
+ %Q = getelementptr i32* %P, i32 1
+ %R = bitcast i32* %Q to i8*
+ %S = load i8* %R
+ %T = icmp eq i8 %S, 0
+ br i1 %T, label %TB, label %F
+TB:
+ ret i8 4
+F:
+ %U = getelementptr i8* %R, i32 3
+ %V = load i8* %U
+ ret i8 %V
+}
diff --git a/test/CodeGen/X86/isel-sink3.ll b/test/CodeGen/X86/isel-sink3.ll
new file mode 100644
index 0000000..8d3d97a
--- /dev/null
+++ b/test/CodeGen/X86/isel-sink3.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s | grep {addl.\$4, %ecx}
+; RUN: llc < %s | not grep leal
+; this should not sink %1 into bb1, that would increase reg pressure.
+
+; rdar://6399178
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin7"
+
+define i32 @bar(i32** %P) nounwind {
+entry:
+ %0 = load i32** %P, align 4 ; <i32*> [#uses=2]
+ %1 = getelementptr i32* %0, i32 1 ; <i32*> [#uses=1]
+ %2 = icmp ugt i32* %1, inttoptr (i64 1233 to i32*) ; <i1> [#uses=1]
+ br i1 %2, label %bb1, label %bb
+
+bb: ; preds = %entry
+ store i32* inttoptr (i64 123 to i32*), i32** %P, align 4
+ br label %bb1
+
+bb1: ; preds = %entry, %bb
+ %3 = getelementptr i32* %1, i32 1 ; <i32*> [#uses=1]
+ %4 = load i32* %3, align 4 ; <i32> [#uses=1]
+ ret i32 %4
+}
diff --git a/test/CodeGen/X86/isint.ll b/test/CodeGen/X86/isint.ll
new file mode 100644
index 0000000..507a328
--- /dev/null
+++ b/test/CodeGen/X86/isint.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
+; RUN: not grep cmp %t
+; RUN: not grep xor %t
+; RUN: grep jne %t | count 1
+; RUN: grep jp %t | count 1
+; RUN: grep setnp %t | count 1
+; RUN: grep sete %t | count 1
+; RUN: grep and %t | count 1
+; RUN: grep cvt %t | count 4
+
+define i32 @isint_return(double %d) nounwind {
+ %i = fptosi double %d to i32
+ %e = sitofp i32 %i to double
+ %c = fcmp oeq double %d, %e
+ %z = zext i1 %c to i32
+ ret i32 %z
+}
+
+declare void @foo()
+
+define void @isint_branch(double %d) nounwind {
+ %i = fptosi double %d to i32
+ %e = sitofp i32 %i to double
+ %c = fcmp oeq double %d, %e
+ br i1 %c, label %true, label %false
+true:
+ call void @foo()
+ ret void
+false:
+ ret void
+}
diff --git a/test/CodeGen/X86/isnan.ll b/test/CodeGen/X86/isnan.ll
new file mode 100644
index 0000000..4d465c0
--- /dev/null
+++ b/test/CodeGen/X86/isnan.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 | not grep call
+
+declare i1 @llvm.isunordered.f64(double)
+
+define i1 @test_isnan(double %X) {
+ %R = fcmp uno double %X, %X ; <i1> [#uses=1]
+ ret i1 %R
+}
+
diff --git a/test/CodeGen/X86/isnan2.ll b/test/CodeGen/X86/isnan2.ll
new file mode 100644
index 0000000..7753346
--- /dev/null
+++ b/test/CodeGen/X86/isnan2.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah | not grep pxor
+
+; This should not need to materialize 0.0 to evaluate the condition.
+
+define i32 @test(double %X) nounwind {
+entry:
+ %tmp6 = fcmp uno double %X, 0.000000e+00 ; <i1> [#uses=1]
+ %tmp67 = zext i1 %tmp6 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp67
+}
+
diff --git a/test/CodeGen/X86/ispositive.ll b/test/CodeGen/X86/ispositive.ll
new file mode 100644
index 0000000..8adf723
--- /dev/null
+++ b/test/CodeGen/X86/ispositive.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 | grep {shrl.*31}
+
+define i32 @test1(i32 %X) {
+entry:
+ icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]
+ zext i1 %0 to i32 ; <i32>:1 [#uses=1]
+ ret i32 %1
+}
+
diff --git a/test/CodeGen/X86/iv-users-in-other-loops.ll b/test/CodeGen/X86/iv-users-in-other-loops.ll
new file mode 100644
index 0000000..c695c29
--- /dev/null
+++ b/test/CodeGen/X86/iv-users-in-other-loops.ll
@@ -0,0 +1,296 @@
+; RUN: llc < %s -march=x86-64 -o %t
+; RUN: grep inc %t | count 1
+; RUN: grep dec %t | count 2
+; RUN: grep addq %t | count 13
+; RUN: not grep addb %t
+; RUN: grep leaq %t | count 9
+; RUN: grep leal %t | count 3
+; RUN: grep movq %t | count 5
+
+; IV users in each of the loops from other loops shouldn't cause LSR
+; to insert new induction variables. Previously it would create a
+; flood of new induction variables.
+; Also, the loop reversal should kick in once.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @foo(float* %A, i32 %IA, float* %B, i32 %IB, float* nocapture %C, i32 %N) nounwind {
+entry:
+ %0 = xor i32 %IA, 1 ; <i32> [#uses=1]
+ %1 = xor i32 %IB, 1 ; <i32> [#uses=1]
+ %2 = or i32 %1, %0 ; <i32> [#uses=1]
+ %3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
+ br i1 %3, label %bb2, label %bb13
+
+bb: ; preds = %bb3
+ %4 = load float* %A_addr.0, align 4 ; <float> [#uses=1]
+ %5 = load float* %B_addr.0, align 4 ; <float> [#uses=1]
+ %6 = fmul float %4, %5 ; <float> [#uses=1]
+ %7 = fadd float %6, %Sum0.0 ; <float> [#uses=1]
+ %indvar.next154 = add i64 %B_addr.0.rec, 1 ; <i64> [#uses=1]
+ br label %bb2
+
+bb2: ; preds = %entry, %bb
+ %B_addr.0.rec = phi i64 [ %indvar.next154, %bb ], [ 0, %entry ] ; <i64> [#uses=14]
+ %Sum0.0 = phi float [ %7, %bb ], [ 0.000000e+00, %entry ] ; <float> [#uses=5]
+ %indvar146 = trunc i64 %B_addr.0.rec to i32 ; <i32> [#uses=1]
+ %N_addr.0 = sub i32 %N, %indvar146 ; <i32> [#uses=6]
+ %A_addr.0 = getelementptr float* %A, i64 %B_addr.0.rec ; <float*> [#uses=4]
+ %B_addr.0 = getelementptr float* %B, i64 %B_addr.0.rec ; <float*> [#uses=4]
+ %8 = icmp sgt i32 %N_addr.0, 0 ; <i1> [#uses=1]
+ br i1 %8, label %bb3, label %bb4
+
+bb3: ; preds = %bb2
+ %9 = ptrtoint float* %A_addr.0 to i64 ; <i64> [#uses=1]
+ %10 = and i64 %9, 15 ; <i64> [#uses=1]
+ %11 = icmp eq i64 %10, 0 ; <i1> [#uses=1]
+ br i1 %11, label %bb4, label %bb
+
+bb4: ; preds = %bb3, %bb2
+ %12 = ptrtoint float* %B_addr.0 to i64 ; <i64> [#uses=1]
+ %13 = and i64 %12, 15 ; <i64> [#uses=1]
+ %14 = icmp eq i64 %13, 0 ; <i1> [#uses=1]
+ %15 = icmp sgt i32 %N_addr.0, 15 ; <i1> [#uses=2]
+ br i1 %14, label %bb6.preheader, label %bb10.preheader
+
+bb10.preheader: ; preds = %bb4
+ br i1 %15, label %bb9, label %bb12.loopexit
+
+bb6.preheader: ; preds = %bb4
+ br i1 %15, label %bb5, label %bb8.loopexit
+
+bb5: ; preds = %bb5, %bb6.preheader
+ %indvar143 = phi i64 [ 0, %bb6.preheader ], [ %indvar.next144, %bb5 ] ; <i64> [#uses=3]
+ %vSum0.072 = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %21, %bb5 ] ; <<4 x float>> [#uses=1]
+ %vSum1.070 = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %29, %bb5 ] ; <<4 x float>> [#uses=1]
+ %vSum2.069 = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %37, %bb5 ] ; <<4 x float>> [#uses=1]
+ %vSum3.067 = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %45, %bb5 ] ; <<4 x float>> [#uses=1]
+ %indvar145 = trunc i64 %indvar143 to i32 ; <i32> [#uses=1]
+ %tmp150 = mul i32 %indvar145, -16 ; <i32> [#uses=1]
+ %N_addr.268 = add i32 %tmp150, %N_addr.0 ; <i32> [#uses=1]
+ %A_addr.273.rec = shl i64 %indvar143, 4 ; <i64> [#uses=5]
+ %B_addr.0.sum180 = add i64 %B_addr.0.rec, %A_addr.273.rec ; <i64> [#uses=2]
+ %B_addr.271 = getelementptr float* %B, i64 %B_addr.0.sum180 ; <float*> [#uses=1]
+ %A_addr.273 = getelementptr float* %A, i64 %B_addr.0.sum180 ; <float*> [#uses=1]
+ tail call void asm sideeffect ";# foo", "~{dirflag},~{fpsr},~{flags}"() nounwind
+ %16 = bitcast float* %A_addr.273 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %17 = load <4 x float>* %16, align 16 ; <<4 x float>> [#uses=1]
+ %18 = bitcast float* %B_addr.271 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %19 = load <4 x float>* %18, align 16 ; <<4 x float>> [#uses=1]
+ %20 = fmul <4 x float> %17, %19 ; <<4 x float>> [#uses=1]
+ %21 = fadd <4 x float> %20, %vSum0.072 ; <<4 x float>> [#uses=2]
+ %A_addr.273.sum163 = or i64 %A_addr.273.rec, 4 ; <i64> [#uses=1]
+ %A_addr.0.sum175 = add i64 %B_addr.0.rec, %A_addr.273.sum163 ; <i64> [#uses=2]
+ %22 = getelementptr float* %A, i64 %A_addr.0.sum175 ; <float*> [#uses=1]
+ %23 = bitcast float* %22 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %24 = load <4 x float>* %23, align 16 ; <<4 x float>> [#uses=1]
+ %25 = getelementptr float* %B, i64 %A_addr.0.sum175 ; <float*> [#uses=1]
+ %26 = bitcast float* %25 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %27 = load <4 x float>* %26, align 16 ; <<4 x float>> [#uses=1]
+ %28 = fmul <4 x float> %24, %27 ; <<4 x float>> [#uses=1]
+ %29 = fadd <4 x float> %28, %vSum1.070 ; <<4 x float>> [#uses=2]
+ %A_addr.273.sum161 = or i64 %A_addr.273.rec, 8 ; <i64> [#uses=1]
+ %A_addr.0.sum174 = add i64 %B_addr.0.rec, %A_addr.273.sum161 ; <i64> [#uses=2]
+ %30 = getelementptr float* %A, i64 %A_addr.0.sum174 ; <float*> [#uses=1]
+ %31 = bitcast float* %30 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %32 = load <4 x float>* %31, align 16 ; <<4 x float>> [#uses=1]
+ %33 = getelementptr float* %B, i64 %A_addr.0.sum174 ; <float*> [#uses=1]
+ %34 = bitcast float* %33 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %35 = load <4 x float>* %34, align 16 ; <<4 x float>> [#uses=1]
+ %36 = fmul <4 x float> %32, %35 ; <<4 x float>> [#uses=1]
+ %37 = fadd <4 x float> %36, %vSum2.069 ; <<4 x float>> [#uses=2]
+ %A_addr.273.sum159 = or i64 %A_addr.273.rec, 12 ; <i64> [#uses=1]
+ %A_addr.0.sum173 = add i64 %B_addr.0.rec, %A_addr.273.sum159 ; <i64> [#uses=2]
+ %38 = getelementptr float* %A, i64 %A_addr.0.sum173 ; <float*> [#uses=1]
+ %39 = bitcast float* %38 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %40 = load <4 x float>* %39, align 16 ; <<4 x float>> [#uses=1]
+ %41 = getelementptr float* %B, i64 %A_addr.0.sum173 ; <float*> [#uses=1]
+ %42 = bitcast float* %41 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %43 = load <4 x float>* %42, align 16 ; <<4 x float>> [#uses=1]
+ %44 = fmul <4 x float> %40, %43 ; <<4 x float>> [#uses=1]
+ %45 = fadd <4 x float> %44, %vSum3.067 ; <<4 x float>> [#uses=2]
+ %.rec83 = add i64 %A_addr.273.rec, 16 ; <i64> [#uses=1]
+ %A_addr.0.sum172 = add i64 %B_addr.0.rec, %.rec83 ; <i64> [#uses=2]
+ %46 = getelementptr float* %A, i64 %A_addr.0.sum172 ; <float*> [#uses=1]
+ %47 = getelementptr float* %B, i64 %A_addr.0.sum172 ; <float*> [#uses=1]
+ %48 = add i32 %N_addr.268, -16 ; <i32> [#uses=2]
+ %49 = icmp sgt i32 %48, 15 ; <i1> [#uses=1]
+ %indvar.next144 = add i64 %indvar143, 1 ; <i64> [#uses=1]
+ br i1 %49, label %bb5, label %bb8.loopexit
+
+bb7: ; preds = %bb7, %bb8.loopexit
+ %indvar130 = phi i64 [ 0, %bb8.loopexit ], [ %indvar.next131, %bb7 ] ; <i64> [#uses=3]
+ %vSum0.260 = phi <4 x float> [ %vSum0.0.lcssa, %bb8.loopexit ], [ %55, %bb7 ] ; <<4 x float>> [#uses=1]
+ %indvar132 = trunc i64 %indvar130 to i32 ; <i32> [#uses=1]
+ %tmp133 = mul i32 %indvar132, -4 ; <i32> [#uses=1]
+ %N_addr.358 = add i32 %tmp133, %N_addr.2.lcssa ; <i32> [#uses=1]
+ %A_addr.361.rec = shl i64 %indvar130, 2 ; <i64> [#uses=3]
+ %B_addr.359 = getelementptr float* %B_addr.2.lcssa, i64 %A_addr.361.rec ; <float*> [#uses=1]
+ %A_addr.361 = getelementptr float* %A_addr.2.lcssa, i64 %A_addr.361.rec ; <float*> [#uses=1]
+ %50 = bitcast float* %A_addr.361 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %51 = load <4 x float>* %50, align 16 ; <<4 x float>> [#uses=1]
+ %52 = bitcast float* %B_addr.359 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %53 = load <4 x float>* %52, align 16 ; <<4 x float>> [#uses=1]
+ %54 = fmul <4 x float> %51, %53 ; <<4 x float>> [#uses=1]
+ %55 = fadd <4 x float> %54, %vSum0.260 ; <<4 x float>> [#uses=2]
+ %.rec85 = add i64 %A_addr.361.rec, 4 ; <i64> [#uses=2]
+ %56 = getelementptr float* %A_addr.2.lcssa, i64 %.rec85 ; <float*> [#uses=1]
+ %57 = getelementptr float* %B_addr.2.lcssa, i64 %.rec85 ; <float*> [#uses=1]
+ %58 = add i32 %N_addr.358, -4 ; <i32> [#uses=2]
+ %59 = icmp sgt i32 %58, 3 ; <i1> [#uses=1]
+ %indvar.next131 = add i64 %indvar130, 1 ; <i64> [#uses=1]
+ br i1 %59, label %bb7, label %bb13
+
+bb8.loopexit: ; preds = %bb5, %bb6.preheader
+ %A_addr.2.lcssa = phi float* [ %A_addr.0, %bb6.preheader ], [ %46, %bb5 ] ; <float*> [#uses=3]
+ %vSum0.0.lcssa = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %21, %bb5 ] ; <<4 x float>> [#uses=2]
+ %B_addr.2.lcssa = phi float* [ %B_addr.0, %bb6.preheader ], [ %47, %bb5 ] ; <float*> [#uses=3]
+ %vSum1.0.lcssa = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %29, %bb5 ] ; <<4 x float>> [#uses=2]
+ %vSum2.0.lcssa = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %37, %bb5 ] ; <<4 x float>> [#uses=2]
+ %N_addr.2.lcssa = phi i32 [ %N_addr.0, %bb6.preheader ], [ %48, %bb5 ] ; <i32> [#uses=3]
+ %vSum3.0.lcssa = phi <4 x float> [ zeroinitializer, %bb6.preheader ], [ %45, %bb5 ] ; <<4 x float>> [#uses=2]
+ %60 = icmp sgt i32 %N_addr.2.lcssa, 3 ; <i1> [#uses=1]
+ br i1 %60, label %bb7, label %bb13
+
+bb9: ; preds = %bb9, %bb10.preheader
+ %indvar106 = phi i64 [ 0, %bb10.preheader ], [ %indvar.next107, %bb9 ] ; <i64> [#uses=3]
+ %vSum0.339 = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %75, %bb9 ] ; <<4 x float>> [#uses=1]
+ %vSum1.237 = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %80, %bb9 ] ; <<4 x float>> [#uses=1]
+ %vSum2.236 = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %85, %bb9 ] ; <<4 x float>> [#uses=1]
+ %vSum3.234 = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %90, %bb9 ] ; <<4 x float>> [#uses=1]
+ %indvar108 = trunc i64 %indvar106 to i32 ; <i32> [#uses=1]
+ %tmp113 = mul i32 %indvar108, -16 ; <i32> [#uses=1]
+ %N_addr.435 = add i32 %tmp113, %N_addr.0 ; <i32> [#uses=1]
+ %A_addr.440.rec = shl i64 %indvar106, 4 ; <i64> [#uses=5]
+ %B_addr.0.sum = add i64 %B_addr.0.rec, %A_addr.440.rec ; <i64> [#uses=2]
+ %B_addr.438 = getelementptr float* %B, i64 %B_addr.0.sum ; <float*> [#uses=1]
+ %A_addr.440 = getelementptr float* %A, i64 %B_addr.0.sum ; <float*> [#uses=1]
+ %61 = bitcast float* %B_addr.438 to <4 x float>* ; <i8*> [#uses=1]
+ %62 = load <4 x float>* %61, align 1
+ %B_addr.438.sum169 = or i64 %A_addr.440.rec, 4 ; <i64> [#uses=1]
+ %B_addr.0.sum187 = add i64 %B_addr.0.rec, %B_addr.438.sum169 ; <i64> [#uses=2]
+ %63 = getelementptr float* %B, i64 %B_addr.0.sum187 ; <float*> [#uses=1]
+ %64 = bitcast float* %63 to <4 x float>* ; <i8*> [#uses=1]
+ %65 = load <4 x float>* %64, align 1
+ %B_addr.438.sum168 = or i64 %A_addr.440.rec, 8 ; <i64> [#uses=1]
+ %B_addr.0.sum186 = add i64 %B_addr.0.rec, %B_addr.438.sum168 ; <i64> [#uses=2]
+ %66 = getelementptr float* %B, i64 %B_addr.0.sum186 ; <float*> [#uses=1]
+ %67 = bitcast float* %66 to <4 x float>* ; <i8*> [#uses=1]
+ %68 = load <4 x float>* %67, align 1
+ %B_addr.438.sum167 = or i64 %A_addr.440.rec, 12 ; <i64> [#uses=1]
+ %B_addr.0.sum185 = add i64 %B_addr.0.rec, %B_addr.438.sum167 ; <i64> [#uses=2]
+ %69 = getelementptr float* %B, i64 %B_addr.0.sum185 ; <float*> [#uses=1]
+ %70 = bitcast float* %69 to <4 x float>* ; <i8*> [#uses=1]
+ %71 = load <4 x float>* %70, align 1
+ %72 = bitcast float* %A_addr.440 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %73 = load <4 x float>* %72, align 16 ; <<4 x float>> [#uses=1]
+ %74 = fmul <4 x float> %73, %62 ; <<4 x float>> [#uses=1]
+ %75 = fadd <4 x float> %74, %vSum0.339 ; <<4 x float>> [#uses=2]
+ %76 = getelementptr float* %A, i64 %B_addr.0.sum187 ; <float*> [#uses=1]
+ %77 = bitcast float* %76 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %78 = load <4 x float>* %77, align 16 ; <<4 x float>> [#uses=1]
+ %79 = fmul <4 x float> %78, %65 ; <<4 x float>> [#uses=1]
+ %80 = fadd <4 x float> %79, %vSum1.237 ; <<4 x float>> [#uses=2]
+ %81 = getelementptr float* %A, i64 %B_addr.0.sum186 ; <float*> [#uses=1]
+ %82 = bitcast float* %81 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %83 = load <4 x float>* %82, align 16 ; <<4 x float>> [#uses=1]
+ %84 = fmul <4 x float> %83, %68 ; <<4 x float>> [#uses=1]
+ %85 = fadd <4 x float> %84, %vSum2.236 ; <<4 x float>> [#uses=2]
+ %86 = getelementptr float* %A, i64 %B_addr.0.sum185 ; <float*> [#uses=1]
+ %87 = bitcast float* %86 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %88 = load <4 x float>* %87, align 16 ; <<4 x float>> [#uses=1]
+ %89 = fmul <4 x float> %88, %71 ; <<4 x float>> [#uses=1]
+ %90 = fadd <4 x float> %89, %vSum3.234 ; <<4 x float>> [#uses=2]
+ %.rec89 = add i64 %A_addr.440.rec, 16 ; <i64> [#uses=1]
+ %A_addr.0.sum170 = add i64 %B_addr.0.rec, %.rec89 ; <i64> [#uses=2]
+ %91 = getelementptr float* %A, i64 %A_addr.0.sum170 ; <float*> [#uses=1]
+ %92 = getelementptr float* %B, i64 %A_addr.0.sum170 ; <float*> [#uses=1]
+ %93 = add i32 %N_addr.435, -16 ; <i32> [#uses=2]
+ %94 = icmp sgt i32 %93, 15 ; <i1> [#uses=1]
+ %indvar.next107 = add i64 %indvar106, 1 ; <i64> [#uses=1]
+ br i1 %94, label %bb9, label %bb12.loopexit
+
+bb11: ; preds = %bb11, %bb12.loopexit
+ %indvar = phi i64 [ 0, %bb12.loopexit ], [ %indvar.next, %bb11 ] ; <i64> [#uses=3]
+ %vSum0.428 = phi <4 x float> [ %vSum0.3.lcssa, %bb12.loopexit ], [ %100, %bb11 ] ; <<4 x float>> [#uses=1]
+ %indvar96 = trunc i64 %indvar to i32 ; <i32> [#uses=1]
+ %tmp = mul i32 %indvar96, -4 ; <i32> [#uses=1]
+ %N_addr.526 = add i32 %tmp, %N_addr.4.lcssa ; <i32> [#uses=1]
+ %A_addr.529.rec = shl i64 %indvar, 2 ; <i64> [#uses=3]
+ %B_addr.527 = getelementptr float* %B_addr.4.lcssa, i64 %A_addr.529.rec ; <float*> [#uses=1]
+ %A_addr.529 = getelementptr float* %A_addr.4.lcssa, i64 %A_addr.529.rec ; <float*> [#uses=1]
+ %95 = bitcast float* %B_addr.527 to <4 x float>* ; <i8*> [#uses=1]
+ %96 = load <4 x float>* %95, align 1
+ %97 = bitcast float* %A_addr.529 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %98 = load <4 x float>* %97, align 16 ; <<4 x float>> [#uses=1]
+ %99 = fmul <4 x float> %98, %96 ; <<4 x float>> [#uses=1]
+ %100 = fadd <4 x float> %99, %vSum0.428 ; <<4 x float>> [#uses=2]
+ %.rec91 = add i64 %A_addr.529.rec, 4 ; <i64> [#uses=2]
+ %101 = getelementptr float* %A_addr.4.lcssa, i64 %.rec91 ; <float*> [#uses=1]
+ %102 = getelementptr float* %B_addr.4.lcssa, i64 %.rec91 ; <float*> [#uses=1]
+ %103 = add i32 %N_addr.526, -4 ; <i32> [#uses=2]
+ %104 = icmp sgt i32 %103, 3 ; <i1> [#uses=1]
+ %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1]
+ br i1 %104, label %bb11, label %bb13
+
+bb12.loopexit: ; preds = %bb9, %bb10.preheader
+ %A_addr.4.lcssa = phi float* [ %A_addr.0, %bb10.preheader ], [ %91, %bb9 ] ; <float*> [#uses=3]
+ %vSum0.3.lcssa = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %75, %bb9 ] ; <<4 x float>> [#uses=2]
+ %B_addr.4.lcssa = phi float* [ %B_addr.0, %bb10.preheader ], [ %92, %bb9 ] ; <float*> [#uses=3]
+ %vSum1.2.lcssa = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %80, %bb9 ] ; <<4 x float>> [#uses=2]
+ %vSum2.2.lcssa = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %85, %bb9 ] ; <<4 x float>> [#uses=2]
+ %N_addr.4.lcssa = phi i32 [ %N_addr.0, %bb10.preheader ], [ %93, %bb9 ] ; <i32> [#uses=3]
+ %vSum3.2.lcssa = phi <4 x float> [ zeroinitializer, %bb10.preheader ], [ %90, %bb9 ] ; <<4 x float>> [#uses=2]
+ %105 = icmp sgt i32 %N_addr.4.lcssa, 3 ; <i1> [#uses=1]
+ br i1 %105, label %bb11, label %bb13
+
+bb13: ; preds = %bb12.loopexit, %bb11, %bb8.loopexit, %bb7, %entry
+ %Sum0.1 = phi float [ 0.000000e+00, %entry ], [ %Sum0.0, %bb7 ], [ %Sum0.0, %bb8.loopexit ], [ %Sum0.0, %bb11 ], [ %Sum0.0, %bb12.loopexit ] ; <float> [#uses=1]
+ %vSum3.1 = phi <4 x float> [ zeroinitializer, %entry ], [ %vSum3.0.lcssa, %bb7 ], [ %vSum3.0.lcssa, %bb8.loopexit ], [ %vSum3.2.lcssa, %bb11 ], [ %vSum3.2.lcssa, %bb12.loopexit ] ; <<4 x float>> [#uses=1]
+ %N_addr.1 = phi i32 [ %N, %entry ], [ %N_addr.2.lcssa, %bb8.loopexit ], [ %58, %bb7 ], [ %N_addr.4.lcssa, %bb12.loopexit ], [ %103, %bb11 ] ; <i32> [#uses=2]
+ %vSum2.1 = phi <4 x float> [ zeroinitializer, %entry ], [ %vSum2.0.lcssa, %bb7 ], [ %vSum2.0.lcssa, %bb8.loopexit ], [ %vSum2.2.lcssa, %bb11 ], [ %vSum2.2.lcssa, %bb12.loopexit ] ; <<4 x float>> [#uses=1]
+ %vSum1.1 = phi <4 x float> [ zeroinitializer, %entry ], [ %vSum1.0.lcssa, %bb7 ], [ %vSum1.0.lcssa, %bb8.loopexit ], [ %vSum1.2.lcssa, %bb11 ], [ %vSum1.2.lcssa, %bb12.loopexit ] ; <<4 x float>> [#uses=1]
+ %B_addr.1 = phi float* [ %B, %entry ], [ %B_addr.2.lcssa, %bb8.loopexit ], [ %57, %bb7 ], [ %B_addr.4.lcssa, %bb12.loopexit ], [ %102, %bb11 ] ; <float*> [#uses=1]
+ %vSum0.1 = phi <4 x float> [ zeroinitializer, %entry ], [ %vSum0.0.lcssa, %bb8.loopexit ], [ %55, %bb7 ], [ %vSum0.3.lcssa, %bb12.loopexit ], [ %100, %bb11 ] ; <<4 x float>> [#uses=1]
+ %A_addr.1 = phi float* [ %A, %entry ], [ %A_addr.2.lcssa, %bb8.loopexit ], [ %56, %bb7 ], [ %A_addr.4.lcssa, %bb12.loopexit ], [ %101, %bb11 ] ; <float*> [#uses=1]
+ %106 = fadd <4 x float> %vSum0.1, %vSum2.1 ; <<4 x float>> [#uses=1]
+ %107 = fadd <4 x float> %vSum1.1, %vSum3.1 ; <<4 x float>> [#uses=1]
+ %108 = fadd <4 x float> %106, %107 ; <<4 x float>> [#uses=4]
+ %tmp23 = extractelement <4 x float> %108, i32 0 ; <float> [#uses=1]
+ %tmp21 = extractelement <4 x float> %108, i32 1 ; <float> [#uses=1]
+ %109 = fadd float %tmp23, %tmp21 ; <float> [#uses=1]
+ %tmp19 = extractelement <4 x float> %108, i32 2 ; <float> [#uses=1]
+ %tmp17 = extractelement <4 x float> %108, i32 3 ; <float> [#uses=1]
+ %110 = fadd float %tmp19, %tmp17 ; <float> [#uses=1]
+ %111 = fadd float %109, %110 ; <float> [#uses=1]
+ %Sum0.254 = fadd float %111, %Sum0.1 ; <float> [#uses=2]
+ %112 = icmp sgt i32 %N_addr.1, 0 ; <i1> [#uses=1]
+ br i1 %112, label %bb.nph56, label %bb16
+
+bb.nph56: ; preds = %bb13
+ %tmp. = zext i32 %N_addr.1 to i64 ; <i64> [#uses=1]
+ br label %bb14
+
+bb14: ; preds = %bb14, %bb.nph56
+ %indvar117 = phi i64 [ 0, %bb.nph56 ], [ %indvar.next118, %bb14 ] ; <i64> [#uses=3]
+ %Sum0.255 = phi float [ %Sum0.254, %bb.nph56 ], [ %Sum0.2, %bb14 ] ; <float> [#uses=1]
+ %tmp.122 = sext i32 %IB to i64 ; <i64> [#uses=1]
+ %B_addr.652.rec = mul i64 %indvar117, %tmp.122 ; <i64> [#uses=1]
+ %tmp.124 = sext i32 %IA to i64 ; <i64> [#uses=1]
+ %A_addr.653.rec = mul i64 %indvar117, %tmp.124 ; <i64> [#uses=1]
+ %B_addr.652 = getelementptr float* %B_addr.1, i64 %B_addr.652.rec ; <float*> [#uses=1]
+ %A_addr.653 = getelementptr float* %A_addr.1, i64 %A_addr.653.rec ; <float*> [#uses=1]
+ %113 = load float* %A_addr.653, align 4 ; <float> [#uses=1]
+ %114 = load float* %B_addr.652, align 4 ; <float> [#uses=1]
+ %115 = fmul float %113, %114 ; <float> [#uses=1]
+ %Sum0.2 = fadd float %115, %Sum0.255 ; <float> [#uses=2]
+ %indvar.next118 = add i64 %indvar117, 1 ; <i64> [#uses=2]
+ %exitcond = icmp eq i64 %indvar.next118, %tmp. ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb16, label %bb14
+
+bb16: ; preds = %bb14, %bb13
+ %Sum0.2.lcssa = phi float [ %Sum0.254, %bb13 ], [ %Sum0.2, %bb14 ] ; <float> [#uses=1]
+ store float %Sum0.2.lcssa, float* %C, align 4
+ ret void
+}
diff --git a/test/CodeGen/X86/jump_sign.ll b/test/CodeGen/X86/jump_sign.ll
new file mode 100644
index 0000000..5e8e162
--- /dev/null
+++ b/test/CodeGen/X86/jump_sign.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86 | grep jns
+
+define i32 @f(i32 %X) {
+entry:
+ %tmp1 = add i32 %X, 1 ; <i32> [#uses=1]
+ %tmp = icmp slt i32 %tmp1, 0 ; <i1> [#uses=1]
+ br i1 %tmp, label %cond_true, label %cond_next
+
+cond_true: ; preds = %entry
+ %tmp2 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ br label %cond_next
+
+cond_next: ; preds = %cond_true, %entry
+ %tmp3 = tail call i32 (...)* @baz( ) ; <i32> [#uses=0]
+ ret i32 undef
+}
+
+declare i32 @bar(...)
+
+declare i32 @baz(...)
diff --git a/test/CodeGen/X86/large-gep-scale.ll b/test/CodeGen/X86/large-gep-scale.ll
new file mode 100644
index 0000000..143294e
--- /dev/null
+++ b/test/CodeGen/X86/large-gep-scale.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 | FileCheck %s
+; PR5281
+
+; After scaling, this type doesn't fit in memory. Codegen should generate
+; correct addressing still.
+
+; CHECK: shll $2, %edx
+
+define fastcc i32* @_ada_smkr([2147483647 x i32]* %u, i32 %t) nounwind {
+ %x = getelementptr [2147483647 x i32]* %u, i32 %t, i32 0
+ ret i32* %x
+}
diff --git a/test/CodeGen/X86/ldzero.ll b/test/CodeGen/X86/ldzero.ll
new file mode 100644
index 0000000..dab04bc
--- /dev/null
+++ b/test/CodeGen/X86/ldzero.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s
+; verify PR 1700 is still fixed
+; ModuleID = 'hh.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin8"
+
+define x86_fp80 @x() {
+entry:
+ %retval = alloca x86_fp80, align 16 ; <x86_fp80*> [#uses=2]
+ %tmp = alloca x86_fp80, align 16 ; <x86_fp80*> [#uses=2]
+ %d = alloca double, align 8 ; <double*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store double 0.000000e+00, double* %d, align 8
+ %tmp1 = load double* %d, align 8 ; <double> [#uses=1]
+ %tmp12 = fpext double %tmp1 to x86_fp80 ; <x86_fp80> [#uses=1]
+ store x86_fp80 %tmp12, x86_fp80* %tmp, align 16
+ %tmp3 = load x86_fp80* %tmp, align 16 ; <x86_fp80> [#uses=1]
+ store x86_fp80 %tmp3, x86_fp80* %retval, align 16
+ br label %return
+
+return: ; preds = %entry
+ %retval4 = load x86_fp80* %retval ; <x86_fp80> [#uses=1]
+ ret x86_fp80 %retval4
+}
+
+define double @y() {
+entry:
+ %retval = alloca double, align 8 ; <double*> [#uses=2]
+ %tmp = alloca double, align 8 ; <double*> [#uses=2]
+ %ld = alloca x86_fp80, align 16 ; <x86_fp80*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store x86_fp80 0xK00000000000000000000, x86_fp80* %ld, align 16
+ %tmp1 = load x86_fp80* %ld, align 16 ; <x86_fp80> [#uses=1]
+ %tmp12 = fptrunc x86_fp80 %tmp1 to double ; <double> [#uses=1]
+ store double %tmp12, double* %tmp, align 8
+ %tmp3 = load double* %tmp, align 8 ; <double> [#uses=1]
+ store double %tmp3, double* %retval, align 8
+ br label %return
+
+return: ; preds = %entry
+ %retval4 = load double* %retval ; <double> [#uses=1]
+ ret double %retval4
+}
diff --git a/test/CodeGen/X86/lea-2.ll b/test/CodeGen/X86/lea-2.ll
new file mode 100644
index 0000000..6930350
--- /dev/null
+++ b/test/CodeGen/X86/lea-2.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
+; RUN: grep {lea EAX, DWORD PTR \\\[... + 4\\*... - 5\\\]}
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
+; RUN: not grep add
+
+define i32 @test1(i32 %A, i32 %B) {
+ %tmp1 = shl i32 %A, 2 ; <i32> [#uses=1]
+ %tmp3 = add i32 %B, -5 ; <i32> [#uses=1]
+ %tmp4 = add i32 %tmp3, %tmp1 ; <i32> [#uses=1]
+ ret i32 %tmp4
+}
+
+
diff --git a/test/CodeGen/X86/lea-3.ll b/test/CodeGen/X86/lea-3.ll
new file mode 100644
index 0000000..44413d6
--- /dev/null
+++ b/test/CodeGen/X86/lea-3.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86-64 | grep {leal (%rdi,%rdi,2), %eax}
+define i32 @test(i32 %a) {
+ %tmp2 = mul i32 %a, 3 ; <i32> [#uses=1]
+ ret i32 %tmp2
+}
+
+; RUN: llc < %s -march=x86-64 | grep {leaq (,%rdi,4), %rax}
+define i64 @test2(i64 %a) {
+ %tmp2 = shl i64 %a, 2
+ %tmp3 = or i64 %tmp2, %a
+ ret i64 %tmp3
+}
+
+;; TODO! LEA instead of shift + copy.
+define i64 @test3(i64 %a) {
+ %tmp2 = shl i64 %a, 3
+ ret i64 %tmp2
+}
+
diff --git a/test/CodeGen/X86/lea-4.ll b/test/CodeGen/X86/lea-4.ll
new file mode 100644
index 0000000..2171204
--- /dev/null
+++ b/test/CodeGen/X86/lea-4.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86-64 | grep lea | count 2
+
+define zeroext i16 @t1(i32 %on_off) nounwind {
+entry:
+ %0 = sub i32 %on_off, 1
+ %1 = mul i32 %0, 2
+ %2 = trunc i32 %1 to i16
+ %3 = zext i16 %2 to i32
+ %4 = trunc i32 %3 to i16
+ ret i16 %4
+}
+
+define i32 @t2(i32 %on_off) nounwind {
+entry:
+ %0 = sub i32 %on_off, 1
+ %1 = mul i32 %0, 2
+ %2 = and i32 %1, 65535
+ ret i32 %2
+}
diff --git a/test/CodeGen/X86/lea-recursion.ll b/test/CodeGen/X86/lea-recursion.ll
new file mode 100644
index 0000000..3f32fd2
--- /dev/null
+++ b/test/CodeGen/X86/lea-recursion.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s -march=x86-64 | grep lea | count 12
+
+; This testcase was written to demonstrate an instruction-selection problem,
+; however it also happens to expose a limitation in the DAGCombiner's
+; expression reassociation which causes it to miss opportunities for
+; constant folding due to the intermediate adds having multiple uses.
+; The Reassociate pass has similar limitations. If these limitations are
+; fixed, the test commands above will need to be updated to expect fewer
+; lea instructions.
+
+@g0 = weak global [1000 x i32] zeroinitializer, align 32 ; <[1000 x i32]*> [#uses=8]
+@g1 = weak global [1000 x i32] zeroinitializer, align 32 ; <[1000 x i32]*> [#uses=7]
+
+define void @foo() {
+entry:
+ %tmp4 = load i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 0) ; <i32> [#uses=1]
+ %tmp8 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 0) ; <i32> [#uses=1]
+ %tmp9 = add i32 %tmp4, 1 ; <i32> [#uses=1]
+ %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=2]
+ store i32 %tmp10, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 1)
+ %tmp8.1 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 1) ; <i32> [#uses=1]
+ %tmp9.1 = add i32 %tmp10, 1 ; <i32> [#uses=1]
+ %tmp10.1 = add i32 %tmp9.1, %tmp8.1 ; <i32> [#uses=2]
+ store i32 %tmp10.1, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 2)
+ %tmp8.2 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 2) ; <i32> [#uses=1]
+ %tmp9.2 = add i32 %tmp10.1, 1 ; <i32> [#uses=1]
+ %tmp10.2 = add i32 %tmp9.2, %tmp8.2 ; <i32> [#uses=2]
+ store i32 %tmp10.2, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 3)
+ %tmp8.3 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 3) ; <i32> [#uses=1]
+ %tmp9.3 = add i32 %tmp10.2, 1 ; <i32> [#uses=1]
+ %tmp10.3 = add i32 %tmp9.3, %tmp8.3 ; <i32> [#uses=2]
+ store i32 %tmp10.3, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 4)
+ %tmp8.4 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 4) ; <i32> [#uses=1]
+ %tmp9.4 = add i32 %tmp10.3, 1 ; <i32> [#uses=1]
+ %tmp10.4 = add i32 %tmp9.4, %tmp8.4 ; <i32> [#uses=2]
+ store i32 %tmp10.4, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 5)
+ %tmp8.5 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 5) ; <i32> [#uses=1]
+ %tmp9.5 = add i32 %tmp10.4, 1 ; <i32> [#uses=1]
+ %tmp10.5 = add i32 %tmp9.5, %tmp8.5 ; <i32> [#uses=2]
+ store i32 %tmp10.5, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 6)
+ %tmp8.6 = load i32* getelementptr ([1000 x i32]* @g1, i32 0, i32 6) ; <i32> [#uses=1]
+ %tmp9.6 = add i32 %tmp10.5, 1 ; <i32> [#uses=1]
+ %tmp10.6 = add i32 %tmp9.6, %tmp8.6 ; <i32> [#uses=1]
+ store i32 %tmp10.6, i32* getelementptr ([1000 x i32]* @g0, i32 0, i32 7)
+ ret void
+}
+
diff --git a/test/CodeGen/X86/lea.ll b/test/CodeGen/X86/lea.ll
new file mode 100644
index 0000000..22a9644
--- /dev/null
+++ b/test/CodeGen/X86/lea.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+define i32 @test1(i32 %x) nounwind {
+ %tmp1 = shl i32 %x, 3
+ %tmp2 = add i32 %tmp1, 7
+ ret i32 %tmp2
+; CHECK: test1:
+; CHECK: leal 7(,%rdi,8), %eax
+}
+
+
+; ISel the add of -4 with a neg and use an lea for the rest of the
+; arithemtic.
+define i32 @test2(i32 %x_offs) nounwind readnone {
+entry:
+ %t0 = icmp sgt i32 %x_offs, 4
+ br i1 %t0, label %bb.nph, label %bb2
+
+bb.nph:
+ %tmp = add i32 %x_offs, -5
+ %tmp6 = lshr i32 %tmp, 2
+ %tmp7 = mul i32 %tmp6, -4
+ %tmp8 = add i32 %tmp7, %x_offs
+ %tmp9 = add i32 %tmp8, -4
+ ret i32 %tmp9
+
+bb2:
+ ret i32 %x_offs
+; CHECK: test2:
+; CHECK: leal -5(%rdi), %eax
+; CHECK: andl $-4, %eax
+; CHECK: negl %eax
+; CHECK: leal -4(%rdi,%rax), %eax
+}
diff --git a/test/CodeGen/X86/legalize-fmp-oeq-vector-select.ll b/test/CodeGen/X86/legalize-fmp-oeq-vector-select.ll
new file mode 100644
index 0000000..6a8c154
--- /dev/null
+++ b/test/CodeGen/X86/legalize-fmp-oeq-vector-select.ll
@@ -0,0 +1,11 @@
+; RUN: llc -march=x86-64 -enable-legalize-types-checking < %s
+; PR5092
+
+define <4 x float> @bug(float %a) nounwind {
+entry:
+ %cmp = fcmp oeq float %a, 0.000000e+00 ; <i1> [#uses=1]
+ %temp = select i1 %cmp, <4 x float> <float 1.000000e+00, float 0.000000e+00,
+float 0.000000e+00, float 0.000000e+00>, <4 x float> zeroinitializer
+ ret <4 x float> %temp
+}
+
diff --git a/test/CodeGen/X86/legalizedag_vec.ll b/test/CodeGen/X86/legalizedag_vec.ll
new file mode 100644
index 0000000..574b46a
--- /dev/null
+++ b/test/CodeGen/X86/legalizedag_vec.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mattr=sse2 -disable-mmx -o %t
+; RUN: grep {call.*divdi3} %t | count 2
+
+
+; Test case for r63760 where we generate a legalization assert that an illegal
+; type has been inserted by LegalizeDAG after LegalizeType has run. With sse2,
+; v2i64 is a legal type but with mmx disabled, i64 is an illegal type. When
+; legalizing the divide in LegalizeDAG, we scalarize the vector divide and make
+; two 64 bit divide library calls which introduces i64 nodes that needs to be
+; promoted.
+
+define <2 x i64> @test_long_div(<2 x i64> %num, <2 x i64> %div) {
+ %div.r = sdiv <2 x i64> %num, %div
+ ret <2 x i64> %div.r
+}
diff --git a/test/CodeGen/X86/lfence.ll b/test/CodeGen/X86/lfence.ll
new file mode 100644
index 0000000..7a96ca3
--- /dev/null
+++ b/test/CodeGen/X86/lfence.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep lfence
+
+declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1)
+
+define void @test() {
+ call void @llvm.memory.barrier( i1 true, i1 false, i1 false, i1 false, i1 true)
+ ret void
+}
diff --git a/test/CodeGen/X86/limited-prec.ll b/test/CodeGen/X86/limited-prec.ll
new file mode 100644
index 0000000..7bf4ac2
--- /dev/null
+++ b/test/CodeGen/X86/limited-prec.ll
@@ -0,0 +1,60 @@
+; RUN: llc < %s -limit-float-precision=6 -march=x86 | \
+; RUN: not grep exp | not grep log | not grep pow
+; RUN: llc < %s -limit-float-precision=12 -march=x86 | \
+; RUN: not grep exp | not grep log | not grep pow
+; RUN: llc < %s -limit-float-precision=18 -march=x86 | \
+; RUN: not grep exp | not grep log | not grep pow
+
+define float @f1(float %x) nounwind noinline {
+entry:
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %0 = call float @llvm.exp.f32(float %x) ; <float> [#uses=1]
+ ret float %0
+}
+
+declare float @llvm.exp.f32(float) nounwind readonly
+
+define float @f2(float %x) nounwind noinline {
+entry:
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %0 = call float @llvm.exp2.f32(float %x) ; <float> [#uses=1]
+ ret float %0
+}
+
+declare float @llvm.exp2.f32(float) nounwind readonly
+
+define float @f3(float %x) nounwind noinline {
+entry:
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %0 = call float @llvm.pow.f32(float 1.000000e+01, float %x) ; <float> [#uses=1]
+ ret float %0
+}
+
+declare float @llvm.pow.f32(float, float) nounwind readonly
+
+define float @f4(float %x) nounwind noinline {
+entry:
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %0 = call float @llvm.log.f32(float %x) ; <float> [#uses=1]
+ ret float %0
+}
+
+declare float @llvm.log.f32(float) nounwind readonly
+
+define float @f5(float %x) nounwind noinline {
+entry:
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %0 = call float @llvm.log2.f32(float %x) ; <float> [#uses=1]
+ ret float %0
+}
+
+declare float @llvm.log2.f32(float) nounwind readonly
+
+define float @f6(float %x) nounwind noinline {
+entry:
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ %0 = call float @llvm.log10.f32(float %x) ; <float> [#uses=1]
+ ret float %0
+}
+
+declare float @llvm.log10.f32(float) nounwind readonly
diff --git a/test/CodeGen/X86/live-out-reg-info.ll b/test/CodeGen/X86/live-out-reg-info.ll
new file mode 100644
index 0000000..8cd9774
--- /dev/null
+++ b/test/CodeGen/X86/live-out-reg-info.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86-64 | grep testb
+
+; Make sure dagcombine doesn't eliminate the comparison due
+; to an off-by-one bug with ComputeMaskedBits information.
+
+declare void @qux()
+
+define void @foo(i32 %a) {
+ %t0 = lshr i32 %a, 23
+ br label %next
+next:
+ %t1 = and i32 %t0, 256
+ %t2 = icmp eq i32 %t1, 0
+ br i1 %t2, label %true, label %false
+true:
+ call void @qux()
+ ret void
+false:
+ ret void
+}
diff --git a/test/CodeGen/X86/local-liveness.ll b/test/CodeGen/X86/local-liveness.ll
new file mode 100644
index 0000000..321f208
--- /dev/null
+++ b/test/CodeGen/X86/local-liveness.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=x86 -regalloc=local | grep {subl %eax, %edx}
+
+; Local regalloc shouldn't assume that both the uses of the
+; sub instruction are kills, because one of them is tied
+; to an output. Previously, it was allocating both inputs
+; in the same register.
+
+define i32 @func_3() nounwind {
+entry:
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ %g_323 = alloca i8 ; <i8*> [#uses=2]
+ %p_5 = alloca i64, align 8 ; <i64*> [#uses=2]
+ %0 = alloca i32 ; <i32*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i64 0, i64* %p_5, align 8
+ store i8 1, i8* %g_323, align 1
+ %1 = load i8* %g_323, align 1 ; <i8> [#uses=1]
+ %2 = sext i8 %1 to i64 ; <i64> [#uses=1]
+ %3 = load i64* %p_5, align 8 ; <i64> [#uses=1]
+ %4 = sub i64 %3, %2 ; <i64> [#uses=1]
+ %5 = icmp sge i64 %4, 0 ; <i1> [#uses=1]
+ %6 = zext i1 %5 to i32 ; <i32> [#uses=1]
+ store i32 %6, i32* %0, align 4
+ %7 = load i32* %0, align 4 ; <i32> [#uses=1]
+ store i32 %7, i32* %retval, align 4
+ br label %return
+
+return: ; preds = %entry
+ %retval1 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval1
+}
diff --git a/test/CodeGen/X86/long-setcc.ll b/test/CodeGen/X86/long-setcc.ll
new file mode 100644
index 0000000..e0165fb
--- /dev/null
+++ b/test/CodeGen/X86/long-setcc.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 | grep cmp | count 1
+; RUN: llc < %s -march=x86 | grep shr | count 1
+; RUN: llc < %s -march=x86 | grep xor | count 1
+
+define i1 @t1(i64 %x) nounwind {
+ %B = icmp slt i64 %x, 0
+ ret i1 %B
+}
+
+define i1 @t2(i64 %x) nounwind {
+ %tmp = icmp ult i64 %x, 4294967296
+ ret i1 %tmp
+}
+
+define i1 @t3(i32 %x) nounwind {
+ %tmp = icmp ugt i32 %x, -1
+ ret i1 %tmp
+}
diff --git a/test/CodeGen/X86/longlong-deadload.ll b/test/CodeGen/X86/longlong-deadload.ll
new file mode 100644
index 0000000..9a4c8f2
--- /dev/null
+++ b/test/CodeGen/X86/longlong-deadload.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 | not grep '4{(%...)}
+; This should not load or store the top part of *P.
+
+define void @test(i64* %P) nounwind {
+entry:
+ %tmp1 = load i64* %P, align 8 ; <i64> [#uses=1]
+ %tmp2 = xor i64 %tmp1, 1 ; <i64> [#uses=1]
+ store i64 %tmp2, i64* %P, align 8
+ ret void
+}
+
diff --git a/test/CodeGen/X86/loop-blocks.ll b/test/CodeGen/X86/loop-blocks.ll
new file mode 100644
index 0000000..a125e54
--- /dev/null
+++ b/test/CodeGen/X86/loop-blocks.ll
@@ -0,0 +1,207 @@
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false | FileCheck %s
+
+; These tests check for loop branching structure, and that the loop align
+; directive is placed in the expected place.
+
+; CodeGen should insert a branch into the middle of the loop in
+; order to avoid a branch within the loop.
+
+; CHECK: simple:
+; CHECK: jmp .LBB1_1
+; CHECK-NEXT: align
+; CHECK-NEXT: .LBB1_2:
+; CHECK-NEXT: callq loop_latch
+; CHECK-NEXT: .LBB1_1:
+; CHECK-NEXT: callq loop_header
+
+define void @simple() nounwind {
+entry:
+ br label %loop
+
+loop:
+ call void @loop_header()
+ %t0 = tail call i32 @get()
+ %t1 = icmp slt i32 %t0, 0
+ br i1 %t1, label %done, label %bb
+
+bb:
+ call void @loop_latch()
+ br label %loop
+
+done:
+ call void @exit()
+ ret void
+}
+
+; CodeGen should move block_a to the top of the loop so that it
+; falls through into the loop, avoiding a branch within the loop.
+
+; CHECK: slightly_more_involved:
+; CHECK: jmp .LBB2_1
+; CHECK-NEXT: align
+; CHECK-NEXT: .LBB2_4:
+; CHECK-NEXT: callq bar99
+; CHECK-NEXT: .LBB2_1:
+; CHECK-NEXT: callq body
+
+define void @slightly_more_involved() nounwind {
+entry:
+ br label %loop
+
+loop:
+ call void @body()
+ %t0 = call i32 @get()
+ %t1 = icmp slt i32 %t0, 2
+ br i1 %t1, label %block_a, label %bb
+
+bb:
+ %t2 = call i32 @get()
+ %t3 = icmp slt i32 %t2, 99
+ br i1 %t3, label %exit, label %loop
+
+block_a:
+ call void @bar99()
+ br label %loop
+
+exit:
+ call void @exit()
+ ret void
+}
+
+; Same as slightly_more_involved, but block_a is now a CFG diamond with
+; fallthrough edges which should be preserved.
+
+; CHECK: yet_more_involved:
+; CHECK: jmp .LBB3_1
+; CHECK-NEXT: align
+; CHECK-NEXT: .LBB3_4:
+; CHECK-NEXT: callq bar99
+; CHECK-NEXT: callq get
+; CHECK-NEXT: cmpl $2999, %eax
+; CHECK-NEXT: jg .LBB3_6
+; CHECK-NEXT: callq block_a_true_func
+; CHECK-NEXT: jmp .LBB3_7
+; CHECK-NEXT: .LBB3_6:
+; CHECK-NEXT: callq block_a_false_func
+; CHECK-NEXT: .LBB3_7:
+; CHECK-NEXT: callq block_a_merge_func
+; CHECK-NEXT: .LBB3_1:
+; CHECK-NEXT: callq body
+
+define void @yet_more_involved() nounwind {
+entry:
+ br label %loop
+
+loop:
+ call void @body()
+ %t0 = call i32 @get()
+ %t1 = icmp slt i32 %t0, 2
+ br i1 %t1, label %block_a, label %bb
+
+bb:
+ %t2 = call i32 @get()
+ %t3 = icmp slt i32 %t2, 99
+ br i1 %t3, label %exit, label %loop
+
+block_a:
+ call void @bar99()
+ %z0 = call i32 @get()
+ %z1 = icmp slt i32 %z0, 3000
+ br i1 %z1, label %block_a_true, label %block_a_false
+
+block_a_true:
+ call void @block_a_true_func()
+ br label %block_a_merge
+
+block_a_false:
+ call void @block_a_false_func()
+ br label %block_a_merge
+
+block_a_merge:
+ call void @block_a_merge_func()
+ br label %loop
+
+exit:
+ call void @exit()
+ ret void
+}
+
+; CodeGen should move the CFG islands that are part of the loop but don't
+; conveniently fit anywhere so that they are at least contiguous with the
+; loop.
+
+; CHECK: cfg_islands:
+; CHECK: jmp .LBB4_1
+; CHECK-NEXT: align
+; CHECK-NEXT: .LBB4_7:
+; CHECK-NEXT: callq bar100
+; CHECK-NEXT: jmp .LBB4_1
+; CHECK-NEXT: .LBB4_8:
+; CHECK-NEXT: callq bar101
+; CHECK-NEXT: jmp .LBB4_1
+; CHECK-NEXT: .LBB4_9:
+; CHECK-NEXT: callq bar102
+; CHECK-NEXT: jmp .LBB4_1
+; CHECK-NEXT: .LBB4_5:
+; CHECK-NEXT: callq loop_latch
+; CHECK-NEXT: .LBB4_1:
+; CHECK-NEXT: callq loop_header
+
+define void @cfg_islands() nounwind {
+entry:
+ br label %loop
+
+loop:
+ call void @loop_header()
+ %t0 = call i32 @get()
+ %t1 = icmp slt i32 %t0, 100
+ br i1 %t1, label %block100, label %bb
+
+bb:
+ %t2 = call i32 @get()
+ %t3 = icmp slt i32 %t2, 101
+ br i1 %t3, label %block101, label %bb1
+
+bb1:
+ %t4 = call i32 @get()
+ %t5 = icmp slt i32 %t4, 102
+ br i1 %t5, label %block102, label %bb2
+
+bb2:
+ %t6 = call i32 @get()
+ %t7 = icmp slt i32 %t6, 103
+ br i1 %t7, label %exit, label %bb3
+
+bb3:
+ call void @loop_latch()
+ br label %loop
+
+exit:
+ call void @exit()
+ ret void
+
+block100:
+ call void @bar100()
+ br label %loop
+
+block101:
+ call void @bar101()
+ br label %loop
+
+block102:
+ call void @bar102()
+ br label %loop
+}
+
+declare void @bar99() nounwind
+declare void @bar100() nounwind
+declare void @bar101() nounwind
+declare void @bar102() nounwind
+declare void @body() nounwind
+declare void @exit() nounwind
+declare void @loop_header() nounwind
+declare void @loop_latch() nounwind
+declare i32 @get() nounwind
+declare void @block_a_true_func() nounwind
+declare void @block_a_false_func() nounwind
+declare void @block_a_merge_func() nounwind
diff --git a/test/CodeGen/X86/loop-hoist.ll b/test/CodeGen/X86/loop-hoist.ll
new file mode 100644
index 0000000..b9008e5
--- /dev/null
+++ b/test/CodeGen/X86/loop-hoist.ll
@@ -0,0 +1,27 @@
+; LSR should hoist the load from the "Arr" stub out of the loop.
+
+; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=i686-apple-darwin8.7.2 | FileCheck %s
+
+; CHECK: _foo:
+; CHECK: L_Arr$non_lazy_ptr
+; CHECK: LBB1_1:
+
+@Arr = external global [0 x i32] ; <[0 x i32]*> [#uses=1]
+
+define void @foo(i32 %N.in, i32 %x) nounwind {
+entry:
+ %N = bitcast i32 %N.in to i32 ; <i32> [#uses=1]
+ br label %cond_true
+
+cond_true: ; preds = %cond_true, %entry
+ %indvar = phi i32 [ %x, %entry ], [ %indvar.next, %cond_true ] ; <i32> [#uses=2]
+ %i.0.0 = bitcast i32 %indvar to i32 ; <i32> [#uses=2]
+ %tmp = getelementptr [0 x i32]* @Arr, i32 0, i32 %i.0.0 ; <i32*> [#uses=1]
+ store i32 %i.0.0, i32* %tmp
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %N ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %cond_true
+
+return: ; preds = %cond_true
+ ret void
+}
diff --git a/test/CodeGen/X86/loop-strength-reduce-2.ll b/test/CodeGen/X86/loop-strength-reduce-2.ll
new file mode 100644
index 0000000..30b5114
--- /dev/null
+++ b/test/CodeGen/X86/loop-strength-reduce-2.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=x86 -relocation-model=pic | \
+; RUN: grep {, 4} | count 1
+; RUN: llc < %s -march=x86 | not grep lea
+;
+; Make sure the common loop invariant A is hoisted up to preheader,
+; since too many registers are needed to subsume it into the addressing modes.
+; It's safe to sink A in when it's not pic.
+
+@A = global [16 x [16 x i32]] zeroinitializer, align 32 ; <[16 x [16 x i32]]*> [#uses=2]
+
+define void @test(i32 %row, i32 %N.in) nounwind {
+entry:
+ %N = bitcast i32 %N.in to i32 ; <i32> [#uses=1]
+ %tmp5 = icmp sgt i32 %N.in, 0 ; <i1> [#uses=1]
+ br i1 %tmp5, label %cond_true, label %return
+
+cond_true: ; preds = %cond_true, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %cond_true ] ; <i32> [#uses=2]
+ %i.0.0 = bitcast i32 %indvar to i32 ; <i32> [#uses=2]
+ %tmp2 = add i32 %i.0.0, 1 ; <i32> [#uses=1]
+ %tmp = getelementptr [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp2 ; <i32*> [#uses=1]
+ store i32 4, i32* %tmp
+ %tmp5.upgrd.1 = add i32 %i.0.0, 2 ; <i32> [#uses=1]
+ %tmp7 = getelementptr [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp5.upgrd.1 ; <i32*> [#uses=1]
+ store i32 5, i32* %tmp7
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %N ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %cond_true
+
+return: ; preds = %cond_true, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/loop-strength-reduce-3.ll b/test/CodeGen/X86/loop-strength-reduce-3.ll
new file mode 100644
index 0000000..70c9134
--- /dev/null
+++ b/test/CodeGen/X86/loop-strength-reduce-3.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=dynamic-no-pic | \
+; RUN: grep {A+} | count 2
+;
+; Make sure the common loop invariant A is not hoisted up to preheader,
+; since it can be subsumed it into the addressing modes.
+
+@A = global [16 x [16 x i32]] zeroinitializer, align 32 ; <[16 x [16 x i32]]*> [#uses=2]
+
+define void @test(i32 %row, i32 %N.in) nounwind {
+entry:
+ %N = bitcast i32 %N.in to i32 ; <i32> [#uses=1]
+ %tmp5 = icmp sgt i32 %N.in, 0 ; <i1> [#uses=1]
+ br i1 %tmp5, label %cond_true, label %return
+
+cond_true: ; preds = %cond_true, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %cond_true ] ; <i32> [#uses=2]
+ %i.0.0 = bitcast i32 %indvar to i32 ; <i32> [#uses=2]
+ %tmp2 = add i32 %i.0.0, 1 ; <i32> [#uses=1]
+ %tmp = getelementptr [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp2 ; <i32*> [#uses=1]
+ store i32 4, i32* %tmp
+ %tmp5.upgrd.1 = add i32 %i.0.0, 2 ; <i32> [#uses=1]
+ %tmp7 = getelementptr [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp5.upgrd.1 ; <i32*> [#uses=1]
+ store i32 5, i32* %tmp7
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %N ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %cond_true
+
+return: ; preds = %cond_true, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/loop-strength-reduce.ll b/test/CodeGen/X86/loop-strength-reduce.ll
new file mode 100644
index 0000000..4cb56ca
--- /dev/null
+++ b/test/CodeGen/X86/loop-strength-reduce.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=x86 -relocation-model=static | \
+; RUN: grep {A+} | count 2
+;
+; Make sure the common loop invariant A is not hoisted up to preheader,
+; since it can be subsumed into the addressing mode in all uses.
+
+@A = internal global [16 x [16 x i32]] zeroinitializer, align 32 ; <[16 x [16 x i32]]*> [#uses=2]
+
+define void @test(i32 %row, i32 %N.in) nounwind {
+entry:
+ %N = bitcast i32 %N.in to i32 ; <i32> [#uses=1]
+ %tmp5 = icmp sgt i32 %N.in, 0 ; <i1> [#uses=1]
+ br i1 %tmp5, label %cond_true, label %return
+
+cond_true: ; preds = %cond_true, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %cond_true ] ; <i32> [#uses=2]
+ %i.0.0 = bitcast i32 %indvar to i32 ; <i32> [#uses=2]
+ %tmp2 = add i32 %i.0.0, 1 ; <i32> [#uses=1]
+ %tmp = getelementptr [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp2 ; <i32*> [#uses=1]
+ store i32 4, i32* %tmp
+ %tmp5.upgrd.1 = add i32 %i.0.0, 2 ; <i32> [#uses=1]
+ %tmp7 = getelementptr [16 x [16 x i32]]* @A, i32 0, i32 %row, i32 %tmp5.upgrd.1 ; <i32*> [#uses=1]
+ store i32 5, i32* %tmp7
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %N ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %cond_true
+
+return: ; preds = %cond_true, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/loop-strength-reduce2.ll b/test/CodeGen/X86/loop-strength-reduce2.ll
new file mode 100644
index 0000000..9b53adb
--- /dev/null
+++ b/test/CodeGen/X86/loop-strength-reduce2.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin -relocation-model=pic | grep {\$pb} | grep mov
+;
+; Make sure the PIC label flags2-"L1$pb" is not moved up to the preheader.
+
+@flags2 = internal global [8193 x i8] zeroinitializer, align 32 ; <[8193 x i8]*> [#uses=1]
+
+define void @test(i32 %k, i32 %i) nounwind {
+entry:
+ %k_addr.012 = shl i32 %i, 1 ; <i32> [#uses=1]
+ %tmp14 = icmp sgt i32 %k_addr.012, 8192 ; <i1> [#uses=1]
+ br i1 %tmp14, label %return, label %bb
+
+bb: ; preds = %bb, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
+ %tmp. = shl i32 %i, 1 ; <i32> [#uses=1]
+ %tmp.15 = mul i32 %indvar, %i ; <i32> [#uses=1]
+ %tmp.16 = add i32 %tmp.15, %tmp. ; <i32> [#uses=2]
+ %k_addr.0.0 = bitcast i32 %tmp.16 to i32 ; <i32> [#uses=1]
+ %gep.upgrd.1 = zext i32 %tmp.16 to i64 ; <i64> [#uses=1]
+ %tmp = getelementptr [8193 x i8]* @flags2, i32 0, i64 %gep.upgrd.1 ; <i8*> [#uses=1]
+ store i8 0, i8* %tmp
+ %k_addr.0 = add i32 %k_addr.0.0, %i ; <i32> [#uses=1]
+ %tmp.upgrd.2 = icmp sgt i32 %k_addr.0, 8192 ; <i1> [#uses=1]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br i1 %tmp.upgrd.2, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/loop-strength-reduce3.ll b/test/CodeGen/X86/loop-strength-reduce3.ll
new file mode 100644
index 0000000..c45a374
--- /dev/null
+++ b/test/CodeGen/X86/loop-strength-reduce3.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=x86 | grep cmp | grep 240
+; RUN: llc < %s -march=x86 | grep inc | count 1
+
+define i32 @foo(i32 %A, i32 %B, i32 %C, i32 %D) nounwind {
+entry:
+ %tmp2955 = icmp sgt i32 %C, 0 ; <i1> [#uses=1]
+ br i1 %tmp2955, label %bb26.outer.us, label %bb40.split
+
+bb26.outer.us: ; preds = %bb26.bb32_crit_edge.us, %entry
+ %i.044.0.ph.us = phi i32 [ 0, %entry ], [ %indvar.next57, %bb26.bb32_crit_edge.us ] ; <i32> [#uses=2]
+ %k.1.ph.us = phi i32 [ 0, %entry ], [ %k.0.us, %bb26.bb32_crit_edge.us ] ; <i32> [#uses=1]
+ %tmp3.us = mul i32 %i.044.0.ph.us, 6 ; <i32> [#uses=1]
+ br label %bb1.us
+
+bb1.us: ; preds = %bb1.us, %bb26.outer.us
+ %j.053.us = phi i32 [ 0, %bb26.outer.us ], [ %tmp25.us, %bb1.us ] ; <i32> [#uses=2]
+ %k.154.us = phi i32 [ %k.1.ph.us, %bb26.outer.us ], [ %k.0.us, %bb1.us ] ; <i32> [#uses=1]
+ %tmp5.us = add i32 %tmp3.us, %j.053.us ; <i32> [#uses=1]
+ %tmp7.us = shl i32 %D, %tmp5.us ; <i32> [#uses=2]
+ %tmp9.us = icmp eq i32 %tmp7.us, %B ; <i1> [#uses=1]
+ %tmp910.us = zext i1 %tmp9.us to i32 ; <i32> [#uses=1]
+ %tmp12.us = and i32 %tmp7.us, %A ; <i32> [#uses=1]
+ %tmp19.us = and i32 %tmp12.us, %tmp910.us ; <i32> [#uses=1]
+ %k.0.us = add i32 %tmp19.us, %k.154.us ; <i32> [#uses=3]
+ %tmp25.us = add i32 %j.053.us, 1 ; <i32> [#uses=2]
+ %tmp29.us = icmp slt i32 %tmp25.us, %C ; <i1> [#uses=1]
+ br i1 %tmp29.us, label %bb1.us, label %bb26.bb32_crit_edge.us
+
+bb26.bb32_crit_edge.us: ; preds = %bb1.us
+ %indvar.next57 = add i32 %i.044.0.ph.us, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next57, 40 ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb40.split, label %bb26.outer.us
+
+bb40.split: ; preds = %bb26.bb32_crit_edge.us, %entry
+ %k.1.lcssa.lcssa.us-lcssa = phi i32 [ %k.0.us, %bb26.bb32_crit_edge.us ], [ 0, %entry ] ; <i32> [#uses=1]
+ ret i32 %k.1.lcssa.lcssa.us-lcssa
+}
diff --git a/test/CodeGen/X86/loop-strength-reduce4.ll b/test/CodeGen/X86/loop-strength-reduce4.ll
new file mode 100644
index 0000000..07e46ec
--- /dev/null
+++ b/test/CodeGen/X86/loop-strength-reduce4.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=x86 | grep cmp | grep 64
+; RUN: llc < %s -march=x86 | not grep inc
+
+@state = external global [0 x i32] ; <[0 x i32]*> [#uses=4]
+@S = external global [0 x i32] ; <[0 x i32]*> [#uses=4]
+
+define i32 @foo() nounwind {
+entry:
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
+ %t.063.0 = phi i32 [ 0, %entry ], [ %tmp47, %bb ] ; <i32> [#uses=1]
+ %j.065.0 = shl i32 %indvar, 2 ; <i32> [#uses=4]
+ %tmp3 = getelementptr [0 x i32]* @state, i32 0, i32 %j.065.0 ; <i32*> [#uses=2]
+ %tmp4 = load i32* %tmp3, align 4 ; <i32> [#uses=1]
+ %tmp6 = getelementptr [0 x i32]* @S, i32 0, i32 %t.063.0 ; <i32*> [#uses=1]
+ %tmp7 = load i32* %tmp6, align 4 ; <i32> [#uses=1]
+ %tmp8 = xor i32 %tmp7, %tmp4 ; <i32> [#uses=2]
+ store i32 %tmp8, i32* %tmp3, align 4
+ %tmp1378 = or i32 %j.065.0, 1 ; <i32> [#uses=1]
+ %tmp16 = getelementptr [0 x i32]* @state, i32 0, i32 %tmp1378 ; <i32*> [#uses=2]
+ %tmp17 = load i32* %tmp16, align 4 ; <i32> [#uses=1]
+ %tmp19 = getelementptr [0 x i32]* @S, i32 0, i32 %tmp8 ; <i32*> [#uses=1]
+ %tmp20 = load i32* %tmp19, align 4 ; <i32> [#uses=1]
+ %tmp21 = xor i32 %tmp20, %tmp17 ; <i32> [#uses=2]
+ store i32 %tmp21, i32* %tmp16, align 4
+ %tmp2680 = or i32 %j.065.0, 2 ; <i32> [#uses=1]
+ %tmp29 = getelementptr [0 x i32]* @state, i32 0, i32 %tmp2680 ; <i32*> [#uses=2]
+ %tmp30 = load i32* %tmp29, align 4 ; <i32> [#uses=1]
+ %tmp32 = getelementptr [0 x i32]* @S, i32 0, i32 %tmp21 ; <i32*> [#uses=1]
+ %tmp33 = load i32* %tmp32, align 4 ; <i32> [#uses=1]
+ %tmp34 = xor i32 %tmp33, %tmp30 ; <i32> [#uses=2]
+ store i32 %tmp34, i32* %tmp29, align 4
+ %tmp3982 = or i32 %j.065.0, 3 ; <i32> [#uses=1]
+ %tmp42 = getelementptr [0 x i32]* @state, i32 0, i32 %tmp3982 ; <i32*> [#uses=2]
+ %tmp43 = load i32* %tmp42, align 4 ; <i32> [#uses=1]
+ %tmp45 = getelementptr [0 x i32]* @S, i32 0, i32 %tmp34 ; <i32*> [#uses=1]
+ %tmp46 = load i32* %tmp45, align 4 ; <i32> [#uses=1]
+ %tmp47 = xor i32 %tmp46, %tmp43 ; <i32> [#uses=3]
+ store i32 %tmp47, i32* %tmp42, align 4
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, 4 ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb57, label %bb
+
+bb57: ; preds = %bb
+ %tmp59 = and i32 %tmp47, 255 ; <i32> [#uses=1]
+ ret i32 %tmp59
+}
diff --git a/test/CodeGen/X86/loop-strength-reduce5.ll b/test/CodeGen/X86/loop-strength-reduce5.ll
new file mode 100644
index 0000000..b07eeb6
--- /dev/null
+++ b/test/CodeGen/X86/loop-strength-reduce5.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86 | grep inc | count 1
+
+@X = weak global i16 0 ; <i16*> [#uses=1]
+@Y = weak global i16 0 ; <i16*> [#uses=1]
+
+define void @foo(i32 %N) nounwind {
+entry:
+ %tmp1019 = icmp sgt i32 %N, 0 ; <i1> [#uses=1]
+ br i1 %tmp1019, label %bb, label %return
+
+bb: ; preds = %bb, %entry
+ %i.014.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
+ %tmp1 = trunc i32 %i.014.0 to i16 ; <i16> [#uses=2]
+ volatile store i16 %tmp1, i16* @X, align 2
+ %tmp34 = shl i16 %tmp1, 2 ; <i16> [#uses=1]
+ volatile store i16 %tmp34, i16* @Y, align 2
+ %indvar.next = add i32 %i.014.0, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %N ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/loop-strength-reduce6.ll b/test/CodeGen/X86/loop-strength-reduce6.ll
new file mode 100644
index 0000000..bbafcf7c
--- /dev/null
+++ b/test/CodeGen/X86/loop-strength-reduce6.ll
@@ -0,0 +1,66 @@
+; RUN: llc < %s -march=x86-64 | not grep inc
+
+define fastcc i32 @decodeMP3(i32 %isize, i32* %done) nounwind {
+entry:
+ br i1 false, label %cond_next191, label %cond_true189
+
+cond_true189: ; preds = %entry
+ ret i32 0
+
+cond_next191: ; preds = %entry
+ br i1 false, label %cond_next37.i, label %cond_false.i9
+
+cond_false.i9: ; preds = %cond_next191
+ ret i32 0
+
+cond_next37.i: ; preds = %cond_next191
+ br i1 false, label %cond_false50.i, label %cond_true44.i
+
+cond_true44.i: ; preds = %cond_next37.i
+ br i1 false, label %cond_true11.i.i, label %bb414.preheader.i
+
+cond_true11.i.i: ; preds = %cond_true44.i
+ ret i32 0
+
+cond_false50.i: ; preds = %cond_next37.i
+ ret i32 0
+
+bb414.preheader.i: ; preds = %cond_true44.i
+ br i1 false, label %bb.i18, label %do_layer3.exit
+
+bb.i18: ; preds = %bb414.preheader.i
+ br i1 false, label %bb358.i, label %cond_true79.i
+
+cond_true79.i: ; preds = %bb.i18
+ ret i32 0
+
+bb331.i: ; preds = %bb358.i, %cond_true.i149.i
+ br i1 false, label %cond_true.i149.i, label %cond_false.i151.i
+
+cond_true.i149.i: ; preds = %bb331.i
+ br i1 false, label %bb178.preheader.i.i, label %bb331.i
+
+cond_false.i151.i: ; preds = %bb331.i
+ ret i32 0
+
+bb163.i.i: ; preds = %bb178.preheader.i.i, %bb163.i.i
+ %rawout2.451.rec.i.i = phi i64 [ 0, %bb178.preheader.i.i ], [ %indvar.next260.i, %bb163.i.i ] ; <i64> [#uses=2]
+ %i.052.i.i = trunc i64 %rawout2.451.rec.i.i to i32 ; <i32> [#uses=1]
+ %tmp165.i144.i = shl i32 %i.052.i.i, 5 ; <i32> [#uses=1]
+ %tmp165169.i.i = sext i32 %tmp165.i144.i to i64 ; <i64> [#uses=0]
+ %indvar.next260.i = add i64 %rawout2.451.rec.i.i, 1 ; <i64> [#uses=2]
+ %exitcond261.i = icmp eq i64 %indvar.next260.i, 18 ; <i1> [#uses=1]
+ br i1 %exitcond261.i, label %bb178.preheader.i.i, label %bb163.i.i
+
+bb178.preheader.i.i: ; preds = %bb163.i.i, %cond_true.i149.i
+ br label %bb163.i.i
+
+bb358.i: ; preds = %bb.i18
+ br i1 false, label %bb331.i, label %bb406.i
+
+bb406.i: ; preds = %bb358.i
+ ret i32 0
+
+do_layer3.exit: ; preds = %bb414.preheader.i
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/loop-strength-reduce7.ll b/test/CodeGen/X86/loop-strength-reduce7.ll
new file mode 100644
index 0000000..4b565a6
--- /dev/null
+++ b/test/CodeGen/X86/loop-strength-reduce7.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -march=x86 | not grep imul
+
+target triple = "i386-apple-darwin9.6"
+ %struct.III_psy_xmin = type { [22 x double], [13 x [3 x double]] }
+ %struct.III_scalefac_t = type { [22 x i32], [13 x [3 x i32]] }
+ %struct.gr_info = type { i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32*, [4 x i32] }
+ %struct.lame_global_flags = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, float, float, float, float, i32, i32, i32, i32, i32, i32, i32, i32 }
+
+define fastcc void @outer_loop(%struct.lame_global_flags* nocapture %gfp, double* nocapture %xr, i32 %targ_bits, double* nocapture %best_noise, %struct.III_psy_xmin* nocapture %l3_xmin, i32* nocapture %l3_enc, %struct.III_scalefac_t* nocapture %scalefac, %struct.gr_info* nocapture %cod_info, i32 %ch) nounwind {
+entry:
+ br label %bb4
+
+bb4: ; preds = %bb4, %entry
+ br i1 true, label %bb5, label %bb4
+
+bb5: ; preds = %bb4
+ br i1 true, label %bb28.i37, label %bb.i4
+
+bb.i4: ; preds = %bb.i4, %bb5
+ br label %bb.i4
+
+bb28.i37: ; preds = %bb33.i47, %bb5
+ %i.1.reg2mem.0.i = phi i32 [ %0, %bb33.i47 ], [ 0, %bb5 ] ; <i32> [#uses=2]
+ %0 = add i32 %i.1.reg2mem.0.i, 1 ; <i32> [#uses=2]
+ br label %bb29.i38
+
+bb29.i38: ; preds = %bb33.i47, %bb28.i37
+ %indvar32.i = phi i32 [ %indvar.next33.i, %bb33.i47 ], [ 0, %bb28.i37 ] ; <i32> [#uses=2]
+ %sfb.314.i = add i32 %indvar32.i, 0 ; <i32> [#uses=3]
+ %1 = getelementptr [4 x [21 x double]]* null, i32 0, i32 %0, i32 %sfb.314.i ; <double*> [#uses=1]
+ %2 = load double* %1, align 8 ; <double> [#uses=0]
+ br i1 false, label %bb30.i41, label %bb33.i47
+
+bb30.i41: ; preds = %bb29.i38
+ %3 = getelementptr %struct.III_scalefac_t* null, i32 0, i32 1, i32 %sfb.314.i, i32 %i.1.reg2mem.0.i ; <i32*> [#uses=1]
+ store i32 0, i32* %3, align 4
+ br label %bb33.i47
+
+bb33.i47: ; preds = %bb30.i41, %bb29.i38
+ %4 = add i32 %sfb.314.i, 1 ; <i32> [#uses=1]
+ %phitmp.i46 = icmp ugt i32 %4, 11 ; <i1> [#uses=1]
+ %indvar.next33.i = add i32 %indvar32.i, 1 ; <i32> [#uses=1]
+ br i1 %phitmp.i46, label %bb28.i37, label %bb29.i38
+}
diff --git a/test/CodeGen/X86/loop-strength-reduce8.ll b/test/CodeGen/X86/loop-strength-reduce8.ll
new file mode 100644
index 0000000..e14cd8a
--- /dev/null
+++ b/test/CodeGen/X86/loop-strength-reduce8.ll
@@ -0,0 +1,78 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep leal | not grep 16
+
+ %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32 }
+ %struct.bitmap_element = type { %struct.bitmap_element*, %struct.bitmap_element*, i32, [2 x i64] }
+ %struct.bitmap_head_def = type { %struct.bitmap_element*, %struct.bitmap_element*, i32 }
+ %struct.branch_path = type { %struct.rtx_def*, i32 }
+ %struct.c_lang_decl = type <{ i8, [3 x i8] }>
+ %struct.constant_descriptor = type { %struct.constant_descriptor*, i8*, %struct.rtx_def*, { x86_fp80 } }
+ %struct.eh_region = type { %struct.eh_region*, %struct.eh_region*, %struct.eh_region*, i32, %struct.bitmap_head_def*, i32, { { %struct.eh_region*, %struct.eh_region*, %struct.eh_region*, %struct.rtx_def* } }, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+ %struct.eh_status = type { %struct.eh_region*, %struct.eh_region**, %struct.eh_region*, %struct.eh_region*, %struct.tree_node*, %struct.rtx_def*, %struct.rtx_def*, i32, i32, %struct.varray_head_tag*, %struct.varray_head_tag*, %struct.varray_head_tag*, %struct.branch_path*, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+ %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.tree_node*, %struct.sequence_stack*, i32, i32, i8*, i32, i8*, %struct.tree_node**, %struct.rtx_def** }
+ %struct.equiv_table = type { %struct.rtx_def*, %struct.rtx_def* }
+ %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }
+ %struct.function = type { %struct.eh_status*, %struct.stmt_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, i8*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, i8*, %struct.initial_value_struct*, i32, %struct.tree_node*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.tree_node*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.rtx_def*, i32, %struct.rtx_def**, %struct.temp_slot*, i32, i32, i32, %struct.var_refs_queue*, i32, i32, i8*, %struct.tree_node*, %struct.rtx_def*, i32, i32, %struct.machine_function*, i32, i32, %struct.language_function*, %struct.rtx_def*, i8, i8, i8 }
+ %struct.goto_fixup = type { %struct.goto_fixup*, %struct.rtx_def*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.rtx_def*, %struct.tree_node* }
+ %struct.initial_value_struct = type { i32, i32, %struct.equiv_table* }
+ %struct.label_chain = type { %struct.label_chain*, %struct.tree_node* }
+ %struct.lang_decl = type { %struct.c_lang_decl, %struct.tree_node* }
+ %struct.language_function = type { %struct.stmt_tree_s, %struct.tree_node* }
+ %struct.machine_function = type { [59 x [3 x %struct.rtx_def*]], i32, i32 }
+ %struct.nesting = type { %struct.nesting*, %struct.nesting*, i32, %struct.rtx_def*, { { i32, %struct.rtx_def*, %struct.rtx_def*, %struct.nesting*, %struct.tree_node*, %struct.tree_node*, %struct.label_chain*, i32, i32, i32, i32, %struct.rtx_def*, %struct.tree_node** } } }
+ %struct.pool_constant = type { %struct.constant_descriptor*, %struct.pool_constant*, %struct.pool_constant*, %struct.rtx_def*, i32, i32, i32, i64, i32 }
+ %struct.rtunion = type { i64 }
+ %struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] }
+ %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.tree_node*, %struct.sequence_stack* }
+ %struct.stmt_status = type { %struct.nesting*, %struct.nesting*, %struct.nesting*, %struct.nesting*, %struct.nesting*, %struct.nesting*, i32, i32, %struct.tree_node*, %struct.rtx_def*, i32, i8*, i32, %struct.goto_fixup* }
+ %struct.stmt_tree_s = type { %struct.tree_node*, %struct.tree_node*, i8*, i32 }
+ %struct.temp_slot = type { %struct.temp_slot*, %struct.rtx_def*, %struct.rtx_def*, i32, i64, %struct.tree_node*, %struct.tree_node*, i8, i8, i32, i32, i64, i64 }
+ %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, i8, i8, i8, i8 }
+ %struct.tree_decl = type { %struct.tree_common, i8*, i32, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, %struct.rtunion, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.rtx_def*, { %struct.function* }, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
+ %struct.tree_exp = type { %struct.tree_common, i32, [1 x %struct.tree_node*] }
+ %struct.tree_node = type { %struct.tree_decl }
+ %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
+ %struct.varasm_status = type { %struct.constant_descriptor**, %struct.pool_constant**, %struct.pool_constant*, %struct.pool_constant*, i64, %struct.rtx_def* }
+ %struct.varray_data = type { [1 x i64] }
+ %struct.varray_head_tag = type { i32, i32, i32, i8*, %struct.varray_data }
+@lineno = internal global i32 0 ; <i32*> [#uses=1]
+@tree_code_length = internal global [256 x i32] zeroinitializer
[email protected] = appending global [1 x i8*] [ i8* bitcast (%struct.tree_node* (i32, ...)* @build_stmt to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define %struct.tree_node* @build_stmt(i32 %code, ...) nounwind {
+entry:
+ %p = alloca i8* ; <i8**> [#uses=3]
+ %p1 = bitcast i8** %p to i8* ; <i8*> [#uses=2]
+ call void @llvm.va_start(i8* %p1)
+ %0 = call fastcc %struct.tree_node* @make_node(i32 %code) nounwind ; <%struct.tree_node*> [#uses=2]
+ %1 = getelementptr [256 x i32]* @tree_code_length, i32 0, i32 %code ; <i32*> [#uses=1]
+ %2 = load i32* %1, align 4 ; <i32> [#uses=2]
+ %3 = load i32* @lineno, align 4 ; <i32> [#uses=1]
+ %4 = bitcast %struct.tree_node* %0 to %struct.tree_exp* ; <%struct.tree_exp*> [#uses=2]
+ %5 = getelementptr %struct.tree_exp* %4, i32 0, i32 1 ; <i32*> [#uses=1]
+ store i32 %3, i32* %5, align 4
+ %6 = icmp sgt i32 %2, 0 ; <i1> [#uses=1]
+ br i1 %6, label %bb, label %bb3
+
+bb: ; preds = %bb, %entry
+ %i.01 = phi i32 [ %indvar.next, %bb ], [ 0, %entry ] ; <i32> [#uses=2]
+ %7 = load i8** %p, align 4 ; <i8*> [#uses=2]
+ %8 = getelementptr i8* %7, i32 4 ; <i8*> [#uses=1]
+ store i8* %8, i8** %p, align 4
+ %9 = bitcast i8* %7 to %struct.tree_node** ; <%struct.tree_node**> [#uses=1]
+ %10 = load %struct.tree_node** %9, align 4 ; <%struct.tree_node*> [#uses=1]
+ %11 = getelementptr %struct.tree_exp* %4, i32 0, i32 2, i32 %i.01 ; <%struct.tree_node**> [#uses=1]
+ store %struct.tree_node* %10, %struct.tree_node** %11, align 4
+ %indvar.next = add i32 %i.01, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %2 ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb3, label %bb
+
+bb3: ; preds = %bb, %entry
+ call void @llvm.va_end(i8* %p1)
+ ret %struct.tree_node* %0
+}
+
+declare void @llvm.va_start(i8*) nounwind
+
+declare void @llvm.va_end(i8*) nounwind
+
+declare fastcc %struct.tree_node* @make_node(i32) nounwind
diff --git a/test/CodeGen/X86/lsr-loop-exit-cond.ll b/test/CodeGen/X86/lsr-loop-exit-cond.ll
new file mode 100644
index 0000000..474450a
--- /dev/null
+++ b/test/CodeGen/X86/lsr-loop-exit-cond.ll
@@ -0,0 +1,137 @@
+; RUN: llc -march=x86-64 < %s | FileCheck %s
+
+; CHECK: decq
+; CHECK-NEXT: jne
+
+@Te0 = external global [256 x i32] ; <[256 x i32]*> [#uses=5]
+@Te1 = external global [256 x i32] ; <[256 x i32]*> [#uses=4]
+@Te3 = external global [256 x i32] ; <[256 x i32]*> [#uses=2]
+
+define void @t(i8* nocapture %in, i8* nocapture %out, i32* nocapture %rk, i32 %r) nounwind ssp {
+entry:
+ %0 = load i32* %rk, align 4 ; <i32> [#uses=1]
+ %1 = getelementptr i32* %rk, i64 1 ; <i32*> [#uses=1]
+ %2 = load i32* %1, align 4 ; <i32> [#uses=1]
+ %tmp15 = add i32 %r, -1 ; <i32> [#uses=1]
+ %tmp.16 = zext i32 %tmp15 to i64 ; <i64> [#uses=2]
+ br label %bb
+
+bb: ; preds = %bb1, %entry
+ %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %bb1 ] ; <i64> [#uses=3]
+ %s1.0 = phi i32 [ %2, %entry ], [ %56, %bb1 ] ; <i32> [#uses=2]
+ %s0.0 = phi i32 [ %0, %entry ], [ %43, %bb1 ] ; <i32> [#uses=2]
+ %tmp18 = shl i64 %indvar, 4 ; <i64> [#uses=4]
+ %rk26 = bitcast i32* %rk to i8* ; <i8*> [#uses=6]
+ %3 = lshr i32 %s0.0, 24 ; <i32> [#uses=1]
+ %4 = zext i32 %3 to i64 ; <i64> [#uses=1]
+ %5 = getelementptr [256 x i32]* @Te0, i64 0, i64 %4 ; <i32*> [#uses=1]
+ %6 = load i32* %5, align 4 ; <i32> [#uses=1]
+ %7 = lshr i32 %s1.0, 16 ; <i32> [#uses=1]
+ %8 = and i32 %7, 255 ; <i32> [#uses=1]
+ %9 = zext i32 %8 to i64 ; <i64> [#uses=1]
+ %10 = getelementptr [256 x i32]* @Te1, i64 0, i64 %9 ; <i32*> [#uses=1]
+ %11 = load i32* %10, align 4 ; <i32> [#uses=1]
+ %ctg2.sum2728 = or i64 %tmp18, 8 ; <i64> [#uses=1]
+ %12 = getelementptr i8* %rk26, i64 %ctg2.sum2728 ; <i8*> [#uses=1]
+ %13 = bitcast i8* %12 to i32* ; <i32*> [#uses=1]
+ %14 = load i32* %13, align 4 ; <i32> [#uses=1]
+ %15 = xor i32 %11, %6 ; <i32> [#uses=1]
+ %16 = xor i32 %15, %14 ; <i32> [#uses=3]
+ %17 = lshr i32 %s1.0, 24 ; <i32> [#uses=1]
+ %18 = zext i32 %17 to i64 ; <i64> [#uses=1]
+ %19 = getelementptr [256 x i32]* @Te0, i64 0, i64 %18 ; <i32*> [#uses=1]
+ %20 = load i32* %19, align 4 ; <i32> [#uses=1]
+ %21 = and i32 %s0.0, 255 ; <i32> [#uses=1]
+ %22 = zext i32 %21 to i64 ; <i64> [#uses=1]
+ %23 = getelementptr [256 x i32]* @Te3, i64 0, i64 %22 ; <i32*> [#uses=1]
+ %24 = load i32* %23, align 4 ; <i32> [#uses=1]
+ %ctg2.sum2930 = or i64 %tmp18, 12 ; <i64> [#uses=1]
+ %25 = getelementptr i8* %rk26, i64 %ctg2.sum2930 ; <i8*> [#uses=1]
+ %26 = bitcast i8* %25 to i32* ; <i32*> [#uses=1]
+ %27 = load i32* %26, align 4 ; <i32> [#uses=1]
+ %28 = xor i32 %24, %20 ; <i32> [#uses=1]
+ %29 = xor i32 %28, %27 ; <i32> [#uses=4]
+ %30 = lshr i32 %16, 24 ; <i32> [#uses=1]
+ %31 = zext i32 %30 to i64 ; <i64> [#uses=1]
+ %32 = getelementptr [256 x i32]* @Te0, i64 0, i64 %31 ; <i32*> [#uses=1]
+ %33 = load i32* %32, align 4 ; <i32> [#uses=2]
+ %exitcond = icmp eq i64 %indvar, %tmp.16 ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb2, label %bb1
+
+bb1: ; preds = %bb
+ %ctg2.sum31 = add i64 %tmp18, 16 ; <i64> [#uses=1]
+ %34 = getelementptr i8* %rk26, i64 %ctg2.sum31 ; <i8*> [#uses=1]
+ %35 = bitcast i8* %34 to i32* ; <i32*> [#uses=1]
+ %36 = lshr i32 %29, 16 ; <i32> [#uses=1]
+ %37 = and i32 %36, 255 ; <i32> [#uses=1]
+ %38 = zext i32 %37 to i64 ; <i64> [#uses=1]
+ %39 = getelementptr [256 x i32]* @Te1, i64 0, i64 %38 ; <i32*> [#uses=1]
+ %40 = load i32* %39, align 4 ; <i32> [#uses=1]
+ %41 = load i32* %35, align 4 ; <i32> [#uses=1]
+ %42 = xor i32 %40, %33 ; <i32> [#uses=1]
+ %43 = xor i32 %42, %41 ; <i32> [#uses=1]
+ %44 = lshr i32 %29, 24 ; <i32> [#uses=1]
+ %45 = zext i32 %44 to i64 ; <i64> [#uses=1]
+ %46 = getelementptr [256 x i32]* @Te0, i64 0, i64 %45 ; <i32*> [#uses=1]
+ %47 = load i32* %46, align 4 ; <i32> [#uses=1]
+ %48 = and i32 %16, 255 ; <i32> [#uses=1]
+ %49 = zext i32 %48 to i64 ; <i64> [#uses=1]
+ %50 = getelementptr [256 x i32]* @Te3, i64 0, i64 %49 ; <i32*> [#uses=1]
+ %51 = load i32* %50, align 4 ; <i32> [#uses=1]
+ %ctg2.sum32 = add i64 %tmp18, 20 ; <i64> [#uses=1]
+ %52 = getelementptr i8* %rk26, i64 %ctg2.sum32 ; <i8*> [#uses=1]
+ %53 = bitcast i8* %52 to i32* ; <i32*> [#uses=1]
+ %54 = load i32* %53, align 4 ; <i32> [#uses=1]
+ %55 = xor i32 %51, %47 ; <i32> [#uses=1]
+ %56 = xor i32 %55, %54 ; <i32> [#uses=1]
+ %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1]
+ br label %bb
+
+bb2: ; preds = %bb
+ %tmp10 = shl i64 %tmp.16, 4 ; <i64> [#uses=2]
+ %ctg2.sum = add i64 %tmp10, 16 ; <i64> [#uses=1]
+ %tmp1213 = getelementptr i8* %rk26, i64 %ctg2.sum ; <i8*> [#uses=1]
+ %57 = bitcast i8* %tmp1213 to i32* ; <i32*> [#uses=1]
+ %58 = and i32 %33, -16777216 ; <i32> [#uses=1]
+ %59 = lshr i32 %29, 16 ; <i32> [#uses=1]
+ %60 = and i32 %59, 255 ; <i32> [#uses=1]
+ %61 = zext i32 %60 to i64 ; <i64> [#uses=1]
+ %62 = getelementptr [256 x i32]* @Te1, i64 0, i64 %61 ; <i32*> [#uses=1]
+ %63 = load i32* %62, align 4 ; <i32> [#uses=1]
+ %64 = and i32 %63, 16711680 ; <i32> [#uses=1]
+ %65 = or i32 %64, %58 ; <i32> [#uses=1]
+ %66 = load i32* %57, align 4 ; <i32> [#uses=1]
+ %67 = xor i32 %65, %66 ; <i32> [#uses=2]
+ %68 = lshr i32 %29, 8 ; <i32> [#uses=1]
+ %69 = zext i32 %68 to i64 ; <i64> [#uses=1]
+ %70 = getelementptr [256 x i32]* @Te0, i64 0, i64 %69 ; <i32*> [#uses=1]
+ %71 = load i32* %70, align 4 ; <i32> [#uses=1]
+ %72 = and i32 %71, -16777216 ; <i32> [#uses=1]
+ %73 = and i32 %16, 255 ; <i32> [#uses=1]
+ %74 = zext i32 %73 to i64 ; <i64> [#uses=1]
+ %75 = getelementptr [256 x i32]* @Te1, i64 0, i64 %74 ; <i32*> [#uses=1]
+ %76 = load i32* %75, align 4 ; <i32> [#uses=1]
+ %77 = and i32 %76, 16711680 ; <i32> [#uses=1]
+ %78 = or i32 %77, %72 ; <i32> [#uses=1]
+ %ctg2.sum25 = add i64 %tmp10, 20 ; <i64> [#uses=1]
+ %79 = getelementptr i8* %rk26, i64 %ctg2.sum25 ; <i8*> [#uses=1]
+ %80 = bitcast i8* %79 to i32* ; <i32*> [#uses=1]
+ %81 = load i32* %80, align 4 ; <i32> [#uses=1]
+ %82 = xor i32 %78, %81 ; <i32> [#uses=2]
+ %83 = lshr i32 %67, 24 ; <i32> [#uses=1]
+ %84 = trunc i32 %83 to i8 ; <i8> [#uses=1]
+ store i8 %84, i8* %out, align 1
+ %85 = lshr i32 %67, 16 ; <i32> [#uses=1]
+ %86 = trunc i32 %85 to i8 ; <i8> [#uses=1]
+ %87 = getelementptr i8* %out, i64 1 ; <i8*> [#uses=1]
+ store i8 %86, i8* %87, align 1
+ %88 = getelementptr i8* %out, i64 4 ; <i8*> [#uses=1]
+ %89 = lshr i32 %82, 24 ; <i32> [#uses=1]
+ %90 = trunc i32 %89 to i8 ; <i8> [#uses=1]
+ store i8 %90, i8* %88, align 1
+ %91 = lshr i32 %82, 16 ; <i32> [#uses=1]
+ %92 = trunc i32 %91 to i8 ; <i8> [#uses=1]
+ %93 = getelementptr i8* %out, i64 5 ; <i8*> [#uses=1]
+ store i8 %92, i8* %93, align 1
+ ret void
+}
diff --git a/test/CodeGen/X86/lsr-negative-stride.ll b/test/CodeGen/X86/lsr-negative-stride.ll
new file mode 100644
index 0000000..b08356c
--- /dev/null
+++ b/test/CodeGen/X86/lsr-negative-stride.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -march=x86 > %t
+; RUN: not grep neg %t
+; RUN: not grep sub.*esp %t
+; RUN: not grep esi %t
+; RUN: not grep push %t
+
+; This corresponds to:
+;int t(int a, int b) {
+; while (a != b) {
+; if (a > b)
+; a -= b;
+; else
+; b -= a;
+; }
+; return a;
+;}
+
+
+define i32 @t(i32 %a, i32 %b) nounwind {
+entry:
+ %tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1]
+ br i1 %tmp1434, label %bb17, label %bb.outer
+
+bb.outer: ; preds = %cond_false, %entry
+ %b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ] ; <i32> [#uses=5]
+ %a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1]
+ br label %bb
+
+bb: ; preds = %cond_true, %bb.outer
+ %indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ] ; <i32> [#uses=2]
+ %tmp. = sub i32 0, %b_addr.021.0.ph ; <i32> [#uses=1]
+ %tmp.40 = mul i32 %indvar, %tmp. ; <i32> [#uses=1]
+ %a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph ; <i32> [#uses=6]
+ %tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph ; <i1> [#uses=1]
+ br i1 %tmp3, label %cond_true, label %cond_false
+
+cond_true: ; preds = %bb
+ %tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph ; <i32> [#uses=2]
+ %tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph ; <i1> [#uses=1]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br i1 %tmp1437, label %bb17, label %bb
+
+cond_false: ; preds = %bb
+ %tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0 ; <i32> [#uses=2]
+ %tmp14 = icmp eq i32 %a_addr.026.0, %tmp10 ; <i1> [#uses=1]
+ br i1 %tmp14, label %bb17, label %bb.outer
+
+bb17: ; preds = %cond_false, %cond_true, %entry
+ %a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1]
+ ret i32 %a_addr.026.1
+}
diff --git a/test/CodeGen/X86/lsr-sort.ll b/test/CodeGen/X86/lsr-sort.ll
new file mode 100644
index 0000000..1f3b59a
--- /dev/null
+++ b/test/CodeGen/X86/lsr-sort.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: grep inc %t | count 1
+; RUN: not grep incw %t
+
+@X = common global i16 0 ; <i16*> [#uses=1]
+
+define i32 @foo(i32 %N) nounwind {
+entry:
+ %0 = icmp sgt i32 %N, 0 ; <i1> [#uses=1]
+ br i1 %0, label %bb, label %return
+
+bb: ; preds = %bb, %entry
+ %i.03 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
+ %1 = trunc i32 %i.03 to i16 ; <i16> [#uses=1]
+ volatile store i16 %1, i16* @X, align 2
+ %indvar.next = add i32 %i.03, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, %N ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ %h = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]
+ ret i32 %h
+}
diff --git a/test/CodeGen/X86/masked-iv-safe.ll b/test/CodeGen/X86/masked-iv-safe.ll
new file mode 100644
index 0000000..bc493bd
--- /dev/null
+++ b/test/CodeGen/X86/masked-iv-safe.ll
@@ -0,0 +1,244 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: not grep and %t
+; RUN: not grep movz %t
+; RUN: not grep sar %t
+; RUN: not grep shl %t
+; RUN: grep add %t | count 2
+; RUN: grep inc %t | count 4
+; RUN: grep dec %t | count 2
+; RUN: grep lea %t | count 2
+
+; Optimize away zext-inreg and sext-inreg on the loop induction
+; variable using trip-count information.
+
+define void @count_up(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+ %indvar.i8 = and i64 %indvar, 255
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %indvar.i24 = and i64 %indvar, 16777215
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = add i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 10
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @count_down(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+ %indvar.i8 = and i64 %indvar, 255
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %indvar.i24 = and i64 %indvar, 16777215
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = sub i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 0
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @count_up_signed(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+ %s0 = shl i64 %indvar, 8
+ %indvar.i8 = ashr i64 %s0, 8
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %s1 = shl i64 %indvar, 24
+ %indvar.i24 = ashr i64 %s1, 24
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = add i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 10
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @count_down_signed(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+ %s0 = shl i64 %indvar, 8
+ %indvar.i8 = ashr i64 %s0, 8
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %s1 = shl i64 %indvar, 24
+ %indvar.i24 = ashr i64 %s1, 24
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = sub i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 0
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @another_count_up(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 18446744073709551615, %entry ], [ %indvar.next, %loop ]
+ %indvar.i8 = and i64 %indvar, 255
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %indvar.i24 = and i64 %indvar, 16777215
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = add i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 0
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @another_count_down(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+ %indvar.i8 = and i64 %indvar, 255
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %indvar.i24 = and i64 %indvar, 16777215
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = sub i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 18446744073709551615
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @another_count_up_signed(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 18446744073709551615, %entry ], [ %indvar.next, %loop ]
+ %s0 = shl i64 %indvar, 8
+ %indvar.i8 = ashr i64 %s0, 8
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %s1 = shl i64 %indvar, 24
+ %indvar.i24 = ashr i64 %s1, 24
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = add i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 0
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @another_count_down_signed(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+ %s0 = shl i64 %indvar, 8
+ %indvar.i8 = ashr i64 %s0, 8
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %s1 = shl i64 %indvar, 24
+ %indvar.i24 = ashr i64 %s1, 24
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = sub i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 18446744073709551615
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
diff --git a/test/CodeGen/X86/masked-iv-unsafe.ll b/test/CodeGen/X86/masked-iv-unsafe.ll
new file mode 100644
index 0000000..f23c020
--- /dev/null
+++ b/test/CodeGen/X86/masked-iv-unsafe.ll
@@ -0,0 +1,386 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: grep and %t | count 6
+; RUN: grep movzb %t | count 6
+; RUN: grep sar %t | count 12
+
+; Don't optimize away zext-inreg and sext-inreg on the loop induction
+; variable, because it isn't safe to do so in these cases.
+
+define void @count_up(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+ %indvar.i8 = and i64 %indvar, 255
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %indvar.i24 = and i64 %indvar, 16777215
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = add i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 0
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @count_down(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+ %indvar.i8 = and i64 %indvar, 255
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %indvar.i24 = and i64 %indvar, 16777215
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = sub i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 20
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @count_up_signed(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+ %s0 = shl i64 %indvar, 8
+ %indvar.i8 = ashr i64 %s0, 8
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %s1 = shl i64 %indvar, 24
+ %indvar.i24 = ashr i64 %s1, 24
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = add i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 0
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @count_down_signed(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+ %s0 = shl i64 %indvar, 8
+ %indvar.i8 = ashr i64 %s0, 8
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %s1 = shl i64 %indvar, 24
+ %indvar.i24 = ashr i64 %s1, 24
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = sub i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 20
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @another_count_up(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+ %indvar.i8 = and i64 %indvar, 255
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %indvar.i24 = and i64 %indvar, 16777215
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = add i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, %n
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @another_count_down(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ %n, %entry ], [ %indvar.next, %loop ]
+ %indvar.i8 = and i64 %indvar, 255
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %indvar.i24 = and i64 %indvar, 16777215
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = sub i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 10
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @another_count_up_signed(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+ %s0 = shl i64 %indvar, 8
+ %indvar.i8 = ashr i64 %s0, 8
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %s1 = shl i64 %indvar, 24
+ %indvar.i24 = ashr i64 %s1, 24
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = add i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, %n
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @another_count_down_signed(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ %n, %entry ], [ %indvar.next, %loop ]
+ %s0 = shl i64 %indvar, 8
+ %indvar.i8 = ashr i64 %s0, 8
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %s1 = shl i64 %indvar, 24
+ %indvar.i24 = ashr i64 %s1, 24
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = sub i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 10
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @yet_another_count_down(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+ %indvar.i8 = and i64 %indvar, 255
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %indvar.i24 = and i64 %indvar, 16777215
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = sub i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 18446744073709551615
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @yet_another_count_up(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+ %indvar.i8 = and i64 %indvar, 255
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %indvar.i24 = and i64 %indvar, 16777215
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = add i64 %indvar, 3
+ %exitcond = icmp eq i64 %indvar.next, 10
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @still_another_count_down(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+ %indvar.i8 = and i64 %indvar, 255
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %indvar.i24 = and i64 %indvar, 16777215
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = sub i64 %indvar, 3
+ %exitcond = icmp eq i64 %indvar.next, 0
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @yet_another_count_up_signed(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop ]
+ %s0 = shl i64 %indvar, 8
+ %indvar.i8 = ashr i64 %s0, 8
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %s1 = shl i64 %indvar, 24
+ %indvar.i24 = ashr i64 %s1, 24
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = add i64 %indvar, 3
+ %exitcond = icmp eq i64 %indvar.next, 10
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+define void @yet_another_count_down_signed(double* %d, i64 %n) nounwind {
+entry:
+ br label %loop
+
+loop:
+ %indvar = phi i64 [ 10, %entry ], [ %indvar.next, %loop ]
+ %s0 = shl i64 %indvar, 8
+ %indvar.i8 = ashr i64 %s0, 8
+ %t0 = getelementptr double* %d, i64 %indvar.i8
+ %t1 = load double* %t0
+ %t2 = fmul double %t1, 0.1
+ store double %t2, double* %t0
+ %s1 = shl i64 %indvar, 24
+ %indvar.i24 = ashr i64 %s1, 24
+ %t3 = getelementptr double* %d, i64 %indvar.i24
+ %t4 = load double* %t3
+ %t5 = fmul double %t4, 2.3
+ store double %t5, double* %t3
+ %t6 = getelementptr double* %d, i64 %indvar
+ %t7 = load double* %t6
+ %t8 = fmul double %t7, 4.5
+ store double %t8, double* %t6
+ %indvar.next = sub i64 %indvar, 3
+ %exitcond = icmp eq i64 %indvar.next, 0
+ br i1 %exitcond, label %return, label %loop
+
+return:
+ ret void
+}
+
+
+
diff --git a/test/CodeGen/X86/maskmovdqu.ll b/test/CodeGen/X86/maskmovdqu.ll
new file mode 100644
index 0000000..7796f0e
--- /dev/null
+++ b/test/CodeGen/X86/maskmovdqu.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep -i EDI
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep -i RDI
+; rdar://6573467
+
+define void @test(<16 x i8> %a, <16 x i8> %b, i32 %dummy, i8* %c) nounwind {
+entry:
+ tail call void @llvm.x86.sse2.maskmov.dqu( <16 x i8> %a, <16 x i8> %b, i8* %c )
+ ret void
+}
+
+declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, i8*) nounwind
diff --git a/test/CodeGen/X86/memcmp.ll b/test/CodeGen/X86/memcmp.ll
new file mode 100644
index 0000000..b90d2e2
--- /dev/null
+++ b/test/CodeGen/X86/memcmp.ll
@@ -0,0 +1,110 @@
+; RUN: llc %s -o - -march=x86-64 | FileCheck %s
+
+; This tests codegen time inlining/optimization of memcmp
+; rdar://6480398
+
[email protected] = private constant [23 x i8] c"fooooooooooooooooooooo\00", align 1 ; <[23 x i8]*> [#uses=1]
+
+declare i32 @memcmp(...)
+
+define void @memcmp2(i8* %X, i8* %Y, i32* nocapture %P) nounwind {
+entry:
+ %0 = tail call i32 (...)* @memcmp(i8* %X, i8* %Y, i32 2) nounwind ; <i32> [#uses=1]
+ %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %return, label %bb
+
+bb: ; preds = %entry
+ store i32 4, i32* %P, align 4
+ ret void
+
+return: ; preds = %entry
+ ret void
+; CHECK: memcmp2:
+; CHECK: movw (%rsi), %ax
+; CHECK: cmpw %ax, (%rdi)
+}
+
+define void @memcmp2a(i8* %X, i32* nocapture %P) nounwind {
+entry:
+ %0 = tail call i32 (...)* @memcmp(i8* %X, i8* getelementptr inbounds ([23 x i8]* @.str, i32 0, i32 1), i32 2) nounwind ; <i32> [#uses=1]
+ %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %return, label %bb
+
+bb: ; preds = %entry
+ store i32 4, i32* %P, align 4
+ ret void
+
+return: ; preds = %entry
+ ret void
+; CHECK: memcmp2a:
+; CHECK: cmpw $28527, (%rdi)
+}
+
+
+define void @memcmp4(i8* %X, i8* %Y, i32* nocapture %P) nounwind {
+entry:
+ %0 = tail call i32 (...)* @memcmp(i8* %X, i8* %Y, i32 4) nounwind ; <i32> [#uses=1]
+ %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %return, label %bb
+
+bb: ; preds = %entry
+ store i32 4, i32* %P, align 4
+ ret void
+
+return: ; preds = %entry
+ ret void
+; CHECK: memcmp4:
+; CHECK: movl (%rsi), %eax
+; CHECK: cmpl %eax, (%rdi)
+}
+
+define void @memcmp4a(i8* %X, i32* nocapture %P) nounwind {
+entry:
+ %0 = tail call i32 (...)* @memcmp(i8* %X, i8* getelementptr inbounds ([23 x i8]* @.str, i32 0, i32 1), i32 4) nounwind ; <i32> [#uses=1]
+ %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %return, label %bb
+
+bb: ; preds = %entry
+ store i32 4, i32* %P, align 4
+ ret void
+
+return: ; preds = %entry
+ ret void
+; CHECK: memcmp4a:
+; CHECK: cmpl $1869573999, (%rdi)
+}
+
+define void @memcmp8(i8* %X, i8* %Y, i32* nocapture %P) nounwind {
+entry:
+ %0 = tail call i32 (...)* @memcmp(i8* %X, i8* %Y, i32 8) nounwind ; <i32> [#uses=1]
+ %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %return, label %bb
+
+bb: ; preds = %entry
+ store i32 4, i32* %P, align 4
+ ret void
+
+return: ; preds = %entry
+ ret void
+; CHECK: memcmp8:
+; CHECK: movq (%rsi), %rax
+; CHECK: cmpq %rax, (%rdi)
+}
+
+define void @memcmp8a(i8* %X, i32* nocapture %P) nounwind {
+entry:
+ %0 = tail call i32 (...)* @memcmp(i8* %X, i8* getelementptr inbounds ([23 x i8]* @.str, i32 0, i32 0), i32 8) nounwind ; <i32> [#uses=1]
+ %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
+ br i1 %1, label %return, label %bb
+
+bb: ; preds = %entry
+ store i32 4, i32* %P, align 4
+ ret void
+
+return: ; preds = %entry
+ ret void
+; CHECK: memcmp8a:
+; CHECK: movabsq $8029759185026510694, %rax
+; CHECK: cmpq %rax, (%rdi)
+}
+
diff --git a/test/CodeGen/X86/memcpy-2.ll b/test/CodeGen/X86/memcpy-2.ll
new file mode 100644
index 0000000..2dc939e
--- /dev/null
+++ b/test/CodeGen/X86/memcpy-2.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mattr=-sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 7
+; RUN: llc < %s -march=x86 -mattr=+sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 5
+
+ %struct.ParmT = type { [25 x i8], i8, i8* }
[email protected] = internal constant [25 x i8] c"image\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00" ; <[25 x i8]*> [#uses=1]
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind
+
+define void @t(i32 %argc, i8** %argv) nounwind {
+entry:
+ %parms.i = alloca [13 x %struct.ParmT] ; <[13 x %struct.ParmT]*> [#uses=1]
+ %parms1.i = getelementptr [13 x %struct.ParmT]* %parms.i, i32 0, i32 0, i32 0, i32 0 ; <i8*> [#uses=1]
+ call void @llvm.memcpy.i32( i8* %parms1.i, i8* getelementptr ([25 x i8]* @.str12, i32 0, i32 0), i32 25, i32 1 ) nounwind
+ unreachable
+}
diff --git a/test/CodeGen/X86/memcpy.ll b/test/CodeGen/X86/memcpy.ll
new file mode 100644
index 0000000..24530cd
--- /dev/null
+++ b/test/CodeGen/X86/memcpy.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86-64 | grep call.*memcpy | count 2
+
+declare void @llvm.memcpy.i64(i8*, i8*, i64, i32)
+
+define i8* @my_memcpy(i8* %a, i8* %b, i64 %n) {
+entry:
+ tail call void @llvm.memcpy.i64( i8* %a, i8* %b, i64 %n, i32 1 )
+ ret i8* %a
+}
+
+define i8* @my_memcpy2(i64* %a, i64* %b, i64 %n) {
+entry:
+ %tmp14 = bitcast i64* %a to i8*
+ %tmp25 = bitcast i64* %b to i8*
+ tail call void @llvm.memcpy.i64(i8* %tmp14, i8* %tmp25, i64 %n, i32 8 )
+ ret i8* %tmp14
+}
diff --git a/test/CodeGen/X86/memmove-0.ll b/test/CodeGen/X86/memmove-0.ll
new file mode 100644
index 0000000..d405068
--- /dev/null
+++ b/test/CodeGen/X86/memmove-0.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {call memcpy}
+
+declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
+
+define void @foo(i8* noalias %d, i8* noalias %s, i64 %l)
+{
+ call void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 1)
+ ret void
+}
diff --git a/test/CodeGen/X86/memmove-1.ll b/test/CodeGen/X86/memmove-1.ll
new file mode 100644
index 0000000..2057be88
--- /dev/null
+++ b/test/CodeGen/X86/memmove-1.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {call memmove}
+
+declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
+
+define void @foo(i8* %d, i8* %s, i64 %l)
+{
+ call void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 1)
+ ret void
+}
diff --git a/test/CodeGen/X86/memmove-2.ll b/test/CodeGen/X86/memmove-2.ll
new file mode 100644
index 0000000..68a9f4d
--- /dev/null
+++ b/test/CodeGen/X86/memmove-2.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | not grep call
+
+declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
+
+define void @foo(i8* noalias %d, i8* noalias %s)
+{
+ call void @llvm.memmove.i64(i8* %d, i8* %s, i64 32, i32 1)
+ ret void
+}
diff --git a/test/CodeGen/X86/memmove-3.ll b/test/CodeGen/X86/memmove-3.ll
new file mode 100644
index 0000000..d8a419c
--- /dev/null
+++ b/test/CodeGen/X86/memmove-3.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep {call memmove}
+
+declare void @llvm.memmove.i64(i8* %d, i8* %s, i64 %l, i32 %a)
+
+define void @foo(i8* %d, i8* %s)
+{
+ call void @llvm.memmove.i64(i8* %d, i8* %s, i64 32, i32 1)
+ ret void
+}
diff --git a/test/CodeGen/X86/memmove-4.ll b/test/CodeGen/X86/memmove-4.ll
new file mode 100644
index 0000000..027db1f
--- /dev/null
+++ b/test/CodeGen/X86/memmove-4.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s | not grep call
+
+target triple = "i686-pc-linux-gnu"
+
+define void @a(i8* %a, i8* %b) nounwind {
+ %tmp2 = bitcast i8* %a to i8*
+ %tmp3 = bitcast i8* %b to i8*
+ tail call void @llvm.memmove.i32( i8* %tmp2, i8* %tmp3, i32 12, i32 4 )
+ ret void
+}
+
+declare void @llvm.memmove.i32(i8*, i8*, i32, i32)
diff --git a/test/CodeGen/X86/memset-2.ll b/test/CodeGen/X86/memset-2.ll
new file mode 100644
index 0000000..7deb52f
--- /dev/null
+++ b/test/CodeGen/X86/memset-2.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s | not grep rep
+; RUN: llc < %s | grep memset
+
+target triple = "i386"
+
+declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind
+
+define fastcc i32 @cli_scanzip(i32 %desc) nounwind {
+entry:
+ br label %bb8.i.i.i.i
+
+bb8.i.i.i.i: ; preds = %bb8.i.i.i.i, %entry
+ icmp eq i32 0, 0 ; <i1>:0 [#uses=1]
+ br i1 %0, label %bb61.i.i.i, label %bb8.i.i.i.i
+
+bb32.i.i.i: ; preds = %bb61.i.i.i
+ ptrtoint i8* %tail.0.i.i.i to i32 ; <i32>:1 [#uses=1]
+ sub i32 0, %1 ; <i32>:2 [#uses=1]
+ icmp sgt i32 %2, 19 ; <i1>:3 [#uses=1]
+ br i1 %3, label %bb34.i.i.i, label %bb61.i.i.i
+
+bb34.i.i.i: ; preds = %bb32.i.i.i
+ load i32* null, align 4 ; <i32>:4 [#uses=1]
+ icmp eq i32 %4, 101010256 ; <i1>:5 [#uses=1]
+ br i1 %5, label %bb8.i11.i.i.i, label %bb61.i.i.i
+
+bb8.i11.i.i.i: ; preds = %bb8.i11.i.i.i, %bb34.i.i.i
+ icmp eq i32 0, 0 ; <i1>:6 [#uses=1]
+ br i1 %6, label %cli_dbgmsg.exit49.i, label %bb8.i11.i.i.i
+
+cli_dbgmsg.exit49.i: ; preds = %bb8.i11.i.i.i
+ icmp eq [32768 x i8]* null, null ; <i1>:7 [#uses=1]
+ br i1 %7, label %bb1.i28.i, label %bb8.i.i
+
+bb61.i.i.i: ; preds = %bb61.i.i.i, %bb34.i.i.i, %bb32.i.i.i, %bb8.i.i.i.i
+ %tail.0.i.i.i = getelementptr [1024 x i8]* null, i32 0, i32 0 ; <i8*> [#uses=2]
+ load i8* %tail.0.i.i.i, align 1 ; <i8>:8 [#uses=1]
+ icmp eq i8 %8, 80 ; <i1>:9 [#uses=1]
+ br i1 %9, label %bb32.i.i.i, label %bb61.i.i.i
+
+bb1.i28.i: ; preds = %cli_dbgmsg.exit49.i
+ call void @llvm.memset.i32( i8* null, i8 0, i32 88, i32 1 ) nounwind
+ unreachable
+
+bb8.i.i: ; preds = %bb8.i.i, %cli_dbgmsg.exit49.i
+ br label %bb8.i.i
+}
diff --git a/test/CodeGen/X86/memset.ll b/test/CodeGen/X86/memset.ll
new file mode 100644
index 0000000..cf7464d
--- /dev/null
+++ b/test/CodeGen/X86/memset.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 -mattr=-sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 9
+; RUN: llc < %s -march=x86 -mattr=+sse -mtriple=i686-apple-darwin8.8.0 | grep mov | count 3
+
+ %struct.x = type { i16, i16 }
+
+define void @t() nounwind {
+entry:
+ %up_mvd = alloca [8 x %struct.x] ; <[8 x %struct.x]*> [#uses=2]
+ %up_mvd116 = getelementptr [8 x %struct.x]* %up_mvd, i32 0, i32 0 ; <%struct.x*> [#uses=1]
+ %tmp110117 = bitcast [8 x %struct.x]* %up_mvd to i8* ; <i8*> [#uses=1]
+ call void @llvm.memset.i64( i8* %tmp110117, i8 0, i64 32, i32 8 )
+ call void @foo( %struct.x* %up_mvd116 ) nounwind
+ ret void
+}
+
+declare void @foo(%struct.x*)
+
+declare void @llvm.memset.i64(i8*, i8, i64, i32) nounwind
diff --git a/test/CodeGen/X86/memset64-on-x86-32.ll b/test/CodeGen/X86/memset64-on-x86-32.ll
new file mode 100644
index 0000000..da8fc51
--- /dev/null
+++ b/test/CodeGen/X86/memset64-on-x86-32.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | grep stosl
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movq | count 10
+
+define void @bork() nounwind {
+entry:
+ call void @llvm.memset.i64( i8* null, i8 0, i64 80, i32 4 )
+ ret void
+}
+
+declare void @llvm.memset.i64(i8*, i8, i64, i32) nounwind
+
diff --git a/test/CodeGen/X86/mfence.ll b/test/CodeGen/X86/mfence.ll
new file mode 100644
index 0000000..a1b2283
--- /dev/null
+++ b/test/CodeGen/X86/mfence.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep sfence
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep lfence
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep mfence
+
+
+declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1)
+
+define void @test() {
+ call void @llvm.memory.barrier( i1 true, i1 true, i1 false, i1 false, i1 true)
+ call void @llvm.memory.barrier( i1 true, i1 false, i1 true, i1 false, i1 true)
+ call void @llvm.memory.barrier( i1 true, i1 false, i1 false, i1 true, i1 true)
+
+ call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 false, i1 true)
+ call void @llvm.memory.barrier( i1 true, i1 true, i1 false, i1 true, i1 true)
+ call void @llvm.memory.barrier( i1 true, i1 false, i1 true, i1 true, i1 true)
+
+ call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true , i1 true)
+ call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 false , i1 true)
+ ret void
+}
diff --git a/test/CodeGen/X86/mingw-alloca.ll b/test/CodeGen/X86/mingw-alloca.ll
new file mode 100644
index 0000000..7dcd84d
--- /dev/null
+++ b/test/CodeGen/X86/mingw-alloca.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i386-pc-mingw32"
+
+define void @foo1(i32 %N) nounwind {
+entry:
+; CHECK: _foo1:
+; CHECK: call __alloca
+ %tmp14 = alloca i32, i32 %N ; <i32*> [#uses=1]
+ call void @bar1( i32* %tmp14 )
+ ret void
+}
+
+declare void @bar1(i32*)
+
+define void @foo2(i32 inreg %N) nounwind {
+entry:
+; CHECK: _foo2:
+; CHECK: andl $-16, %esp
+; CHECK: pushl %eax
+; CHECK: call __alloca
+; CHECK: movl 8028(%esp), %eax
+ %A2 = alloca [2000 x i32], align 16 ; <[2000 x i32]*> [#uses=1]
+ %A2.sub = getelementptr [2000 x i32]* %A2, i32 0, i32 0 ; <i32*> [#uses=1]
+ call void @bar2( i32* %A2.sub, i32 %N )
+ ret void
+}
+
+declare void @bar2(i32*, i32)
diff --git a/test/CodeGen/X86/mmx-arg-passing.ll b/test/CodeGen/X86/mmx-arg-passing.ll
new file mode 100644
index 0000000..426e98e
--- /dev/null
+++ b/test/CodeGen/X86/mmx-arg-passing.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | grep mm0 | count 3
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | grep esp | count 1
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep xmm0
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep rdi
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | not grep movups
+;
+; On Darwin x86-32, v8i8, v4i16, v2i32 values are passed in MM[0-2].
+; On Darwin x86-32, v1i64 values are passed in memory.
+; On Darwin x86-64, v8i8, v4i16, v2i32 values are passed in XMM[0-7].
+; On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.
+
+@u1 = external global <8 x i8>
+
+define void @t1(<8 x i8> %v1) nounwind {
+ store <8 x i8> %v1, <8 x i8>* @u1, align 8
+ ret void
+}
+
+@u2 = external global <1 x i64>
+
+define void @t2(<1 x i64> %v1) nounwind {
+ store <1 x i64> %v1, <1 x i64>* @u2, align 8
+ ret void
+}
diff --git a/test/CodeGen/X86/mmx-arg-passing2.ll b/test/CodeGen/X86/mmx-arg-passing2.ll
new file mode 100644
index 0000000..c42af08
--- /dev/null
+++ b/test/CodeGen/X86/mmx-arg-passing2.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep movq2dq | count 1
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep movdq2q | count 2
+
+@g_v8qi = external global <8 x i8>
+
+define void @t1() nounwind {
+ %tmp3 = load <8 x i8>* @g_v8qi, align 8
+ %tmp4 = tail call i32 (...)* @pass_v8qi( <8 x i8> %tmp3 ) nounwind
+ ret void
+}
+
+define void @t2(<8 x i8> %v1, <8 x i8> %v2) nounwind {
+ %tmp3 = add <8 x i8> %v1, %v2
+ %tmp4 = tail call i32 (...)* @pass_v8qi( <8 x i8> %tmp3 ) nounwind
+ ret void
+}
+
+define void @t3() nounwind {
+ call void @pass_v1di( <1 x i64> zeroinitializer )
+ ret void
+}
+
+declare i32 @pass_v8qi(...)
+declare void @pass_v1di(<1 x i64>)
diff --git a/test/CodeGen/X86/mmx-arith.ll b/test/CodeGen/X86/mmx-arith.ll
new file mode 100644
index 0000000..e4dfdbf
--- /dev/null
+++ b/test/CodeGen/X86/mmx-arith.ll
@@ -0,0 +1,131 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx
+
+;; A basic sanity check to make sure that MMX arithmetic actually compiles.
+
+define void @foo(<8 x i8>* %A, <8 x i8>* %B) {
+entry:
+ %tmp1 = load <8 x i8>* %A ; <<8 x i8>> [#uses=1]
+ %tmp3 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1]
+ %tmp4 = add <8 x i8> %tmp1, %tmp3 ; <<8 x i8>> [#uses=2]
+ store <8 x i8> %tmp4, <8 x i8>* %A
+ %tmp7 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1]
+ %tmp12 = tail call <8 x i8> @llvm.x86.mmx.padds.b( <8 x i8> %tmp4, <8 x i8> %tmp7 ) ; <<8 x i8>> [#uses=2]
+ store <8 x i8> %tmp12, <8 x i8>* %A
+ %tmp16 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1]
+ %tmp21 = tail call <8 x i8> @llvm.x86.mmx.paddus.b( <8 x i8> %tmp12, <8 x i8> %tmp16 ) ; <<8 x i8>> [#uses=2]
+ store <8 x i8> %tmp21, <8 x i8>* %A
+ %tmp27 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1]
+ %tmp28 = sub <8 x i8> %tmp21, %tmp27 ; <<8 x i8>> [#uses=2]
+ store <8 x i8> %tmp28, <8 x i8>* %A
+ %tmp31 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1]
+ %tmp36 = tail call <8 x i8> @llvm.x86.mmx.psubs.b( <8 x i8> %tmp28, <8 x i8> %tmp31 ) ; <<8 x i8>> [#uses=2]
+ store <8 x i8> %tmp36, <8 x i8>* %A
+ %tmp40 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1]
+ %tmp45 = tail call <8 x i8> @llvm.x86.mmx.psubus.b( <8 x i8> %tmp36, <8 x i8> %tmp40 ) ; <<8 x i8>> [#uses=2]
+ store <8 x i8> %tmp45, <8 x i8>* %A
+ %tmp51 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1]
+ %tmp52 = mul <8 x i8> %tmp45, %tmp51 ; <<8 x i8>> [#uses=2]
+ store <8 x i8> %tmp52, <8 x i8>* %A
+ %tmp57 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1]
+ %tmp58 = and <8 x i8> %tmp52, %tmp57 ; <<8 x i8>> [#uses=2]
+ store <8 x i8> %tmp58, <8 x i8>* %A
+ %tmp63 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1]
+ %tmp64 = or <8 x i8> %tmp58, %tmp63 ; <<8 x i8>> [#uses=2]
+ store <8 x i8> %tmp64, <8 x i8>* %A
+ %tmp69 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1]
+ %tmp70 = xor <8 x i8> %tmp64, %tmp69 ; <<8 x i8>> [#uses=1]
+ store <8 x i8> %tmp70, <8 x i8>* %A
+ tail call void @llvm.x86.mmx.emms( )
+ ret void
+}
+
+define void @baz(<2 x i32>* %A, <2 x i32>* %B) {
+entry:
+ %tmp1 = load <2 x i32>* %A ; <<2 x i32>> [#uses=1]
+ %tmp3 = load <2 x i32>* %B ; <<2 x i32>> [#uses=1]
+ %tmp4 = add <2 x i32> %tmp1, %tmp3 ; <<2 x i32>> [#uses=2]
+ store <2 x i32> %tmp4, <2 x i32>* %A
+ %tmp9 = load <2 x i32>* %B ; <<2 x i32>> [#uses=1]
+ %tmp10 = sub <2 x i32> %tmp4, %tmp9 ; <<2 x i32>> [#uses=2]
+ store <2 x i32> %tmp10, <2 x i32>* %A
+ %tmp15 = load <2 x i32>* %B ; <<2 x i32>> [#uses=1]
+ %tmp16 = mul <2 x i32> %tmp10, %tmp15 ; <<2 x i32>> [#uses=2]
+ store <2 x i32> %tmp16, <2 x i32>* %A
+ %tmp21 = load <2 x i32>* %B ; <<2 x i32>> [#uses=1]
+ %tmp22 = and <2 x i32> %tmp16, %tmp21 ; <<2 x i32>> [#uses=2]
+ store <2 x i32> %tmp22, <2 x i32>* %A
+ %tmp27 = load <2 x i32>* %B ; <<2 x i32>> [#uses=1]
+ %tmp28 = or <2 x i32> %tmp22, %tmp27 ; <<2 x i32>> [#uses=2]
+ store <2 x i32> %tmp28, <2 x i32>* %A
+ %tmp33 = load <2 x i32>* %B ; <<2 x i32>> [#uses=1]
+ %tmp34 = xor <2 x i32> %tmp28, %tmp33 ; <<2 x i32>> [#uses=1]
+ store <2 x i32> %tmp34, <2 x i32>* %A
+ tail call void @llvm.x86.mmx.emms( )
+ ret void
+}
+
+define void @bar(<4 x i16>* %A, <4 x i16>* %B) {
+entry:
+ %tmp1 = load <4 x i16>* %A ; <<4 x i16>> [#uses=1]
+ %tmp3 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1]
+ %tmp4 = add <4 x i16> %tmp1, %tmp3 ; <<4 x i16>> [#uses=2]
+ store <4 x i16> %tmp4, <4 x i16>* %A
+ %tmp7 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1]
+ %tmp12 = tail call <4 x i16> @llvm.x86.mmx.padds.w( <4 x i16> %tmp4, <4 x i16> %tmp7 ) ; <<4 x i16>> [#uses=2]
+ store <4 x i16> %tmp12, <4 x i16>* %A
+ %tmp16 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1]
+ %tmp21 = tail call <4 x i16> @llvm.x86.mmx.paddus.w( <4 x i16> %tmp12, <4 x i16> %tmp16 ) ; <<4 x i16>> [#uses=2]
+ store <4 x i16> %tmp21, <4 x i16>* %A
+ %tmp27 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1]
+ %tmp28 = sub <4 x i16> %tmp21, %tmp27 ; <<4 x i16>> [#uses=2]
+ store <4 x i16> %tmp28, <4 x i16>* %A
+ %tmp31 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1]
+ %tmp36 = tail call <4 x i16> @llvm.x86.mmx.psubs.w( <4 x i16> %tmp28, <4 x i16> %tmp31 ) ; <<4 x i16>> [#uses=2]
+ store <4 x i16> %tmp36, <4 x i16>* %A
+ %tmp40 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1]
+ %tmp45 = tail call <4 x i16> @llvm.x86.mmx.psubus.w( <4 x i16> %tmp36, <4 x i16> %tmp40 ) ; <<4 x i16>> [#uses=2]
+ store <4 x i16> %tmp45, <4 x i16>* %A
+ %tmp51 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1]
+ %tmp52 = mul <4 x i16> %tmp45, %tmp51 ; <<4 x i16>> [#uses=2]
+ store <4 x i16> %tmp52, <4 x i16>* %A
+ %tmp55 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1]
+ %tmp60 = tail call <4 x i16> @llvm.x86.mmx.pmulh.w( <4 x i16> %tmp52, <4 x i16> %tmp55 ) ; <<4 x i16>> [#uses=2]
+ store <4 x i16> %tmp60, <4 x i16>* %A
+ %tmp64 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1]
+ %tmp69 = tail call <2 x i32> @llvm.x86.mmx.pmadd.wd( <4 x i16> %tmp60, <4 x i16> %tmp64 ) ; <<2 x i32>> [#uses=1]
+ %tmp70 = bitcast <2 x i32> %tmp69 to <4 x i16> ; <<4 x i16>> [#uses=2]
+ store <4 x i16> %tmp70, <4 x i16>* %A
+ %tmp75 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1]
+ %tmp76 = and <4 x i16> %tmp70, %tmp75 ; <<4 x i16>> [#uses=2]
+ store <4 x i16> %tmp76, <4 x i16>* %A
+ %tmp81 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1]
+ %tmp82 = or <4 x i16> %tmp76, %tmp81 ; <<4 x i16>> [#uses=2]
+ store <4 x i16> %tmp82, <4 x i16>* %A
+ %tmp87 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1]
+ %tmp88 = xor <4 x i16> %tmp82, %tmp87 ; <<4 x i16>> [#uses=1]
+ store <4 x i16> %tmp88, <4 x i16>* %A
+ tail call void @llvm.x86.mmx.emms( )
+ ret void
+}
+
+declare <8 x i8> @llvm.x86.mmx.padds.b(<8 x i8>, <8 x i8>)
+
+declare <8 x i8> @llvm.x86.mmx.paddus.b(<8 x i8>, <8 x i8>)
+
+declare <8 x i8> @llvm.x86.mmx.psubs.b(<8 x i8>, <8 x i8>)
+
+declare <8 x i8> @llvm.x86.mmx.psubus.b(<8 x i8>, <8 x i8>)
+
+declare <4 x i16> @llvm.x86.mmx.padds.w(<4 x i16>, <4 x i16>)
+
+declare <4 x i16> @llvm.x86.mmx.paddus.w(<4 x i16>, <4 x i16>)
+
+declare <4 x i16> @llvm.x86.mmx.psubs.w(<4 x i16>, <4 x i16>)
+
+declare <4 x i16> @llvm.x86.mmx.psubus.w(<4 x i16>, <4 x i16>)
+
+declare <4 x i16> @llvm.x86.mmx.pmulh.w(<4 x i16>, <4 x i16>)
+
+declare <2 x i32> @llvm.x86.mmx.pmadd.wd(<4 x i16>, <4 x i16>)
+
+declare void @llvm.x86.mmx.emms()
diff --git a/test/CodeGen/X86/mmx-bitcast-to-i64.ll b/test/CodeGen/X86/mmx-bitcast-to-i64.ll
new file mode 100644
index 0000000..1fd8f67
--- /dev/null
+++ b/test/CodeGen/X86/mmx-bitcast-to-i64.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86-64 | grep movd | count 4
+
+define i64 @foo(<1 x i64>* %p) {
+ %t = load <1 x i64>* %p
+ %u = add <1 x i64> %t, %t
+ %s = bitcast <1 x i64> %u to i64
+ ret i64 %s
+}
+define i64 @goo(<2 x i32>* %p) {
+ %t = load <2 x i32>* %p
+ %u = add <2 x i32> %t, %t
+ %s = bitcast <2 x i32> %u to i64
+ ret i64 %s
+}
+define i64 @hoo(<4 x i16>* %p) {
+ %t = load <4 x i16>* %p
+ %u = add <4 x i16> %t, %t
+ %s = bitcast <4 x i16> %u to i64
+ ret i64 %s
+}
+define i64 @ioo(<8 x i8>* %p) {
+ %t = load <8 x i8>* %p
+ %u = add <8 x i8> %t, %t
+ %s = bitcast <8 x i8> %u to i64
+ ret i64 %s
+}
diff --git a/test/CodeGen/X86/mmx-copy-gprs.ll b/test/CodeGen/X86/mmx-copy-gprs.ll
new file mode 100644
index 0000000..3607043
--- /dev/null
+++ b/test/CodeGen/X86/mmx-copy-gprs.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86-64 | grep {movq.*(%rsi), %rax}
+; RUN: llc < %s -march=x86 -mattr=-sse2 | grep {movl.*4(%eax),}
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {movsd.(%eax),}
+
+; This test should use GPRs to copy the mmx value, not MMX regs. Using mmx regs,
+; increases the places that need to use emms.
+
+; rdar://5741668
+
+define void @foo(<1 x i64>* %x, <1 x i64>* %y) nounwind {
+entry:
+ %tmp1 = load <1 x i64>* %y, align 8 ; <<1 x i64>> [#uses=1]
+ store <1 x i64> %tmp1, <1 x i64>* %x, align 8
+ ret void
+}
diff --git a/test/CodeGen/X86/mmx-emms.ll b/test/CodeGen/X86/mmx-emms.ll
new file mode 100644
index 0000000..5ff2588
--- /dev/null
+++ b/test/CodeGen/X86/mmx-emms.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx | grep emms
+define void @foo() {
+entry:
+ call void @llvm.x86.mmx.emms( )
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+declare void @llvm.x86.mmx.emms()
diff --git a/test/CodeGen/X86/mmx-insert-element.ll b/test/CodeGen/X86/mmx-insert-element.ll
new file mode 100644
index 0000000..a063ee1
--- /dev/null
+++ b/test/CodeGen/X86/mmx-insert-element.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx | not grep movq
+; RUN: llc < %s -march=x86 -mattr=+mmx | grep psllq
+
+define <2 x i32> @qux(i32 %A) nounwind {
+ %tmp3 = insertelement <2 x i32> < i32 0, i32 undef >, i32 %A, i32 1 ; <<2 x i32>> [#uses=1]
+ ret <2 x i32> %tmp3
+}
diff --git a/test/CodeGen/X86/mmx-pinsrw.ll b/test/CodeGen/X86/mmx-pinsrw.ll
new file mode 100644
index 0000000..3af09f4
--- /dev/null
+++ b/test/CodeGen/X86/mmx-pinsrw.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx | grep pinsrw | count 1
+; PR2562
+
+external global i16 ; <i16*>:0 [#uses=1]
+external global <4 x i16> ; <<4 x i16>*>:1 [#uses=2]
+
+declare void @abort()
+
+define void @""() {
+ load i16* @0 ; <i16>:1 [#uses=1]
+ load <4 x i16>* @1 ; <<4 x i16>>:2 [#uses=1]
+ insertelement <4 x i16> %2, i16 %1, i32 0 ; <<4 x i16>>:3 [#uses=1]
+ store <4 x i16> %3, <4 x i16>* @1
+ ret void
+}
diff --git a/test/CodeGen/X86/mmx-punpckhdq.ll b/test/CodeGen/X86/mmx-punpckhdq.ll
new file mode 100644
index 0000000..0af7e01
--- /dev/null
+++ b/test/CodeGen/X86/mmx-punpckhdq.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx | grep punpckhdq | count 1
+
+define void @bork(<1 x i64>* %x) {
+entry:
+ %tmp2 = load <1 x i64>* %x ; <<1 x i64>> [#uses=1]
+ %tmp6 = bitcast <1 x i64> %tmp2 to <2 x i32> ; <<2 x i32>> [#uses=1]
+ %tmp9 = shufflevector <2 x i32> %tmp6, <2 x i32> undef, <2 x i32> < i32 1, i32 1 > ; <<2 x i32>> [#uses=1]
+ %tmp10 = bitcast <2 x i32> %tmp9 to <1 x i64> ; <<1 x i64>> [#uses=1]
+ store <1 x i64> %tmp10, <1 x i64>* %x
+ tail call void @llvm.x86.mmx.emms( )
+ ret void
+}
+
+declare void @llvm.x86.mmx.emms()
diff --git a/test/CodeGen/X86/mmx-s2v.ll b/test/CodeGen/X86/mmx-s2v.ll
new file mode 100644
index 0000000..c98023c
--- /dev/null
+++ b/test/CodeGen/X86/mmx-s2v.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx
+; PR2574
+
+define void @entry(i32 %m_task_id, i32 %start_x, i32 %end_x) {; <label>:0
+ br i1 true, label %bb.nph, label %._crit_edge
+
+bb.nph: ; preds = %bb.nph, %0
+ %t2206f2.0 = phi <2 x float> [ %2, %bb.nph ], [ undef, %0 ] ; <<2 x float>> [#uses=1]
+ insertelement <2 x float> %t2206f2.0, float 0.000000e+00, i32 0 ; <<2 x float>>:1 [#uses=1]
+ insertelement <2 x float> %1, float 0.000000e+00, i32 1 ; <<2 x float>>:2 [#uses=1]
+ br label %bb.nph
+
+._crit_edge: ; preds = %0
+ ret void
+}
diff --git a/test/CodeGen/X86/mmx-shift.ll b/test/CodeGen/X86/mmx-shift.ll
new file mode 100644
index 0000000..dd0aa2c
--- /dev/null
+++ b/test/CodeGen/X86/mmx-shift.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx | grep psllq | grep 32
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep psllq | grep 32
+; RUN: llc < %s -march=x86 -mattr=+mmx | grep psrad
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep psrlw
+
+define i64 @t1(<1 x i64> %mm1) nounwind {
+entry:
+ %tmp6 = tail call <1 x i64> @llvm.x86.mmx.pslli.q( <1 x i64> %mm1, i32 32 ) ; <<1 x i64>> [#uses=1]
+ %retval1112 = bitcast <1 x i64> %tmp6 to i64 ; <i64> [#uses=1]
+ ret i64 %retval1112
+}
+
+declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32) nounwind readnone
+
+define i64 @t2(<2 x i32> %mm1, <2 x i32> %mm2) nounwind {
+entry:
+ %tmp7 = tail call <2 x i32> @llvm.x86.mmx.psra.d( <2 x i32> %mm1, <2 x i32> %mm2 ) nounwind readnone ; <<2 x i32>> [#uses=1]
+ %retval1112 = bitcast <2 x i32> %tmp7 to i64 ; <i64> [#uses=1]
+ ret i64 %retval1112
+}
+
+declare <2 x i32> @llvm.x86.mmx.psra.d(<2 x i32>, <2 x i32>) nounwind readnone
+
+define i64 @t3(<1 x i64> %mm1, i32 %bits) nounwind {
+entry:
+ %tmp6 = bitcast <1 x i64> %mm1 to <4 x i16> ; <<4 x i16>> [#uses=1]
+ %tmp8 = tail call <4 x i16> @llvm.x86.mmx.psrli.w( <4 x i16> %tmp6, i32 %bits ) nounwind readnone ; <<4 x i16>> [#uses=1]
+ %retval1314 = bitcast <4 x i16> %tmp8 to i64 ; <i64> [#uses=1]
+ ret i64 %retval1314
+}
+
+declare <4 x i16> @llvm.x86.mmx.psrli.w(<4 x i16>, i32) nounwind readnone
diff --git a/test/CodeGen/X86/mmx-shuffle.ll b/test/CodeGen/X86/mmx-shuffle.ll
new file mode 100644
index 0000000..e3125c7
--- /dev/null
+++ b/test/CodeGen/X86/mmx-shuffle.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mcpu=yonah
+; PR1427
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-pc-linux-gnu"
+ %struct.DrawHelper = type { void (i32, %struct.QT_FT_Span*, i8*)*, void (i32, %struct.QT_FT_Span*, i8*)*, void (%struct.QRasterBuffer*, i32, i32, i32, i8*, i32, i32, i32)*, void (%struct.QRasterBuffer*, i32, i32, i32, i8*, i32, i32, i32)*, void (%struct.QRasterBuffer*, i32, i32, i32, i32, i32)* }
+ %struct.QBasicAtomic = type { i32 }
+ %struct.QClipData = type { i32, "struct.QClipData::ClipLine"*, i32, i32, %struct.QT_FT_Span*, i32, i32, i32, i32 }
+ "struct.QClipData::ClipLine" = type { i32, %struct.QT_FT_Span* }
+ %struct.QRasterBuffer = type { %struct.QRect, %struct.QRegion, %struct.QClipData*, %struct.QClipData*, i8, i32, i32, %struct.DrawHelper*, i32, i32, i32, i8* }
+ %struct.QRect = type { i32, i32, i32, i32 }
+ %struct.QRegion = type { "struct.QRegion::QRegionData"* }
+ "struct.QRegion::QRegionData" = type { %struct.QBasicAtomic, %struct._XRegion*, i8*, %struct.QRegionPrivate* }
+ %struct.QRegionPrivate = type opaque
+ %struct.QT_FT_Span = type { i16, i16, i16, i8 }
+ %struct._XRegion = type opaque
+
+define void @_Z19qt_bitmapblit16_sseP13QRasterBufferiijPKhiii(%struct.QRasterBuffer* %rasterBuffer, i32 %x, i32 %y, i32 %color, i8* %src, i32 %width, i32 %height, i32 %stride) {
+entry:
+ %tmp528 = bitcast <8 x i8> zeroinitializer to <2 x i32> ; <<2 x i32>> [#uses=1]
+ %tmp529 = and <2 x i32> %tmp528, bitcast (<4 x i16> < i16 -32640, i16 16448, i16 8224, i16 4112 > to <2 x i32>) ; <<2 x i32>> [#uses=1]
+ %tmp542 = bitcast <2 x i32> %tmp529 to <4 x i16> ; <<4 x i16>> [#uses=1]
+ %tmp543 = add <4 x i16> %tmp542, < i16 0, i16 16448, i16 24672, i16 28784 > ; <<4 x i16>> [#uses=1]
+ %tmp555 = bitcast <4 x i16> %tmp543 to <8 x i8> ; <<8 x i8>> [#uses=1]
+ tail call void @llvm.x86.mmx.maskmovq( <8 x i8> zeroinitializer, <8 x i8> %tmp555, i8* null )
+ ret void
+}
+
+declare void @llvm.x86.mmx.maskmovq(<8 x i8>, <8 x i8>, i8*)
diff --git a/test/CodeGen/X86/mmx-vzmovl-2.ll b/test/CodeGen/X86/mmx-vzmovl-2.ll
new file mode 100644
index 0000000..8253c20
--- /dev/null
+++ b/test/CodeGen/X86/mmx-vzmovl-2.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep pxor
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep punpckldq
+
+ %struct.vS1024 = type { [8 x <4 x i32>] }
+ %struct.vS512 = type { [4 x <4 x i32>] }
+
+declare <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64>, i32) nounwind readnone
+
+define void @t() nounwind {
+entry:
+ br label %bb554
+
+bb554: ; preds = %bb554, %entry
+ %sum.0.reg2mem.0 = phi <1 x i64> [ %tmp562, %bb554 ], [ zeroinitializer, %entry ] ; <<1 x i64>> [#uses=1]
+ %0 = load <1 x i64>* null, align 8 ; <<1 x i64>> [#uses=2]
+ %1 = bitcast <1 x i64> %0 to <2 x i32> ; <<2 x i32>> [#uses=1]
+ %tmp555 = and <2 x i32> %1, < i32 -1, i32 0 > ; <<2 x i32>> [#uses=1]
+ %2 = bitcast <2 x i32> %tmp555 to <1 x i64> ; <<1 x i64>> [#uses=1]
+ %3 = call <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64> %0, i32 32) nounwind readnone ; <<1 x i64>> [#uses=1]
+ store <1 x i64> %sum.0.reg2mem.0, <1 x i64>* null
+ %tmp558 = add <1 x i64> %sum.0.reg2mem.0, %2 ; <<1 x i64>> [#uses=1]
+ %4 = call <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64> %tmp558, i32 32) nounwind readnone ; <<1 x i64>> [#uses=1]
+ %tmp562 = add <1 x i64> %4, %3 ; <<1 x i64>> [#uses=1]
+ br label %bb554
+}
diff --git a/test/CodeGen/X86/mmx-vzmovl.ll b/test/CodeGen/X86/mmx-vzmovl.ll
new file mode 100644
index 0000000..d21e240
--- /dev/null
+++ b/test/CodeGen/X86/mmx-vzmovl.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep movd
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep movq
+
+define void @foo(<1 x i64>* %a, <1 x i64>* %b) nounwind {
+entry:
+ %0 = load <1 x i64>* %a, align 8 ; <<1 x i64>> [#uses=1]
+ %1 = bitcast <1 x i64> %0 to <2 x i32> ; <<2 x i32>> [#uses=1]
+ %2 = and <2 x i32> %1, < i32 -1, i32 0 > ; <<2 x i32>> [#uses=1]
+ %3 = bitcast <2 x i32> %2 to <1 x i64> ; <<1 x i64>> [#uses=1]
+ store <1 x i64> %3, <1 x i64>* %b, align 8
+ br label %bb2
+
+bb2: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/movfs.ll b/test/CodeGen/X86/movfs.ll
new file mode 100644
index 0000000..823e986
--- /dev/null
+++ b/test/CodeGen/X86/movfs.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 | grep fs
+
+define i32 @foo() nounwind readonly {
+entry:
+ %tmp = load i32* addrspace(257)* getelementptr (i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31) ; <i32*> [#uses=1]
+ %tmp1 = load i32* %tmp ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/X86/movgs.ll b/test/CodeGen/X86/movgs.ll
new file mode 100644
index 0000000..b04048b
--- /dev/null
+++ b/test/CodeGen/X86/movgs.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 | grep gs
+
+define i32 @foo() nounwind readonly {
+entry:
+ %tmp = load i32* addrspace(256)* getelementptr (i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31) ; <i32*> [#uses=1]
+ %tmp1 = load i32* %tmp ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/X86/mul-legalize.ll b/test/CodeGen/X86/mul-legalize.ll
new file mode 100644
index 0000000..069737d
--- /dev/null
+++ b/test/CodeGen/X86/mul-legalize.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 | grep 24576
+; PR2135
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-pc-linux-gnu"
[email protected] = constant [13 x i8] c"c45531m.adb\00\00"
+
+define void @main() nounwind {
+entry:
+ %tmp1 = call i1 @report__equal( i32 3, i32 3 )
+ %b.0 = select i1 %tmp1, i64 35184372088832, i64 0
+ %tmp7 = mul i64 3, %b.0
+ %tmp32 = icmp eq i64 %tmp7, 105553116266496
+ br i1 %tmp32, label %return, label %bb35
+bb35:
+ call void @abort( )
+ unreachable
+return:
+ ret void
+}
+
+declare i1 @report__equal(i32 %x, i32 %y) nounwind
+
+declare void @abort()
diff --git a/test/CodeGen/X86/mul-remat.ll b/test/CodeGen/X86/mul-remat.ll
new file mode 100644
index 0000000..3fa0050
--- /dev/null
+++ b/test/CodeGen/X86/mul-remat.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 | grep mov | count 1
+; PR1874
+
+define i32 @test(i32 %a, i32 %b) {
+entry:
+ %tmp3 = mul i32 %b, %a
+ ret i32 %tmp3
+}
diff --git a/test/CodeGen/X86/mul-shift-reassoc.ll b/test/CodeGen/X86/mul-shift-reassoc.ll
new file mode 100644
index 0000000..3777d8b
--- /dev/null
+++ b/test/CodeGen/X86/mul-shift-reassoc.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 | grep lea
+; RUN: llc < %s -march=x86 | not grep add
+
+define i32 @test(i32 %X, i32 %Y) {
+ ; Push the shl through the mul to allow an LEA to be formed, instead
+ ; of using a shift and add separately.
+ %tmp.2 = shl i32 %X, 1 ; <i32> [#uses=1]
+ %tmp.3 = mul i32 %tmp.2, %Y ; <i32> [#uses=1]
+ %tmp.5 = add i32 %tmp.3, %Y ; <i32> [#uses=1]
+ ret i32 %tmp.5
+}
+
diff --git a/test/CodeGen/X86/mul128.ll b/test/CodeGen/X86/mul128.ll
new file mode 100644
index 0000000..6825b99
--- /dev/null
+++ b/test/CodeGen/X86/mul128.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86-64 | grep mul | count 3
+
+define i128 @foo(i128 %t, i128 %u) {
+ %k = mul i128 %t, %u
+ ret i128 %k
+}
diff --git a/test/CodeGen/X86/mul64.ll b/test/CodeGen/X86/mul64.ll
new file mode 100644
index 0000000..5a25c5d
--- /dev/null
+++ b/test/CodeGen/X86/mul64.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86 | grep mul | count 3
+
+define i64 @foo(i64 %t, i64 %u) {
+ %k = mul i64 %t, %u
+ ret i64 %k
+}
diff --git a/test/CodeGen/X86/multiple-return-values-cross-block.ll b/test/CodeGen/X86/multiple-return-values-cross-block.ll
new file mode 100644
index 0000000..e9837d0
--- /dev/null
+++ b/test/CodeGen/X86/multiple-return-values-cross-block.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86
+
+declare {x86_fp80, x86_fp80} @test()
+
+define void @call2(x86_fp80 *%P1, x86_fp80 *%P2) {
+ %a = call {x86_fp80,x86_fp80} @test()
+ %b = getresult {x86_fp80,x86_fp80} %a, 1
+ store x86_fp80 %b, x86_fp80* %P1
+br label %L
+
+L:
+ %c = getresult {x86_fp80,x86_fp80} %a, 0
+ store x86_fp80 %c, x86_fp80* %P2
+ ret void
+}
diff --git a/test/CodeGen/X86/multiple-return-values.ll b/test/CodeGen/X86/multiple-return-values.ll
new file mode 100644
index 0000000..018d997
--- /dev/null
+++ b/test/CodeGen/X86/multiple-return-values.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86
+
+define {i64, float} @bar(i64 %a, float %b) {
+ %y = add i64 %a, 7
+ %z = fadd float %b, 7.0
+ ret i64 %y, float %z
+}
+
+define i64 @foo() {
+ %M = call {i64, float} @bar(i64 21, float 21.0)
+ %N = getresult {i64, float} %M, 0
+ %O = getresult {i64, float} %M, 1
+ %P = fptosi float %O to i64
+ %Q = add i64 %P, %N
+ ret i64 %Q
+}
diff --git a/test/CodeGen/X86/nancvt.ll b/test/CodeGen/X86/nancvt.ll
new file mode 100644
index 0000000..82b7331
--- /dev/null
+++ b/test/CodeGen/X86/nancvt.ll
@@ -0,0 +1,183 @@
+; RUN: opt < %s -std-compile-opts | llc > %t
+; RUN: grep 2147027116 %t | count 3
+; RUN: grep 2147228864 %t | count 3
+; RUN: grep 2146502828 %t | count 3
+; RUN: grep 2143034560 %t | count 3
+; Compile time conversions of NaNs.
+; ModuleID = 'nan2.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin8"
+ %struct..0anon = type { float }
+ %struct..1anon = type { double }
+@fnan = constant [3 x i32] [ i32 2143831397, i32 2143831396, i32 2143831398 ] ; <[3 x i32]*> [#uses=1]
+@dnan = constant [3 x i64] [ i64 9223235251041752696, i64 9223235251041752697, i64 9223235250773317239 ], align 8 ; <[3 x i64]*> [#uses=1]
+@fsnan = constant [3 x i32] [ i32 2139637093, i32 2139637092, i32 2139637094 ] ; <[3 x i32]*> [#uses=1]
+@dsnan = constant [3 x i64] [ i64 9220983451228067448, i64 9220983451228067449, i64 9220983450959631991 ], align 8 ; <[3 x i64]*> [#uses=1]
[email protected] = internal constant [10 x i8] c"%08x%08x\0A\00" ; <[10 x i8]*> [#uses=2]
[email protected] = internal constant [6 x i8] c"%08x\0A\00" ; <[6 x i8]*> [#uses=2]
+
+@var = external global i32
+
+define i32 @main() {
+entry:
+ %retval = alloca i32, align 4 ; <i32*> [#uses=1]
+ %i = alloca i32, align 4 ; <i32*> [#uses=20]
+ %uf = alloca %struct..0anon, align 4 ; <%struct..0anon*> [#uses=8]
+ %ud = alloca %struct..1anon, align 8 ; <%struct..1anon*> [#uses=10]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 0, i32* %i, align 4
+ br label %bb23
+
+bb: ; preds = %bb23
+ %tmp = load i32* %i, align 4 ; <i32> [#uses=1]
+ %tmp1 = getelementptr [3 x i32]* @fnan, i32 0, i32 %tmp ; <i32*> [#uses=1]
+ %tmp2 = load i32* %tmp1, align 4 ; <i32> [#uses=1]
+ %tmp3 = getelementptr %struct..0anon* %uf, i32 0, i32 0 ; <float*> [#uses=1]
+ %tmp34 = bitcast float* %tmp3 to i32* ; <i32*> [#uses=1]
+ store i32 %tmp2, i32* %tmp34, align 4
+ %tmp5 = getelementptr %struct..0anon* %uf, i32 0, i32 0 ; <float*> [#uses=1]
+ %tmp6 = load float* %tmp5, align 4 ; <float> [#uses=1]
+ %tmp67 = fpext float %tmp6 to double ; <double> [#uses=1]
+ %tmp8 = getelementptr %struct..1anon* %ud, i32 0, i32 0 ; <double*> [#uses=1]
+ store double %tmp67, double* %tmp8, align 8
+ %tmp9 = getelementptr %struct..1anon* %ud, i32 0, i32 0 ; <double*> [#uses=1]
+ %tmp910 = bitcast double* %tmp9 to i64* ; <i64*> [#uses=1]
+ %tmp11 = load i64* %tmp910, align 8 ; <i64> [#uses=1]
+ %tmp1112 = trunc i64 %tmp11 to i32 ; <i32> [#uses=1]
+ %tmp13 = and i32 %tmp1112, -1 ; <i32> [#uses=1]
+ %tmp14 = getelementptr %struct..1anon* %ud, i32 0, i32 0 ; <double*> [#uses=1]
+ %tmp1415 = bitcast double* %tmp14 to i64* ; <i64*> [#uses=1]
+ %tmp16 = load i64* %tmp1415, align 8 ; <i64> [#uses=1]
+ %.cast = zext i32 32 to i64 ; <i64> [#uses=1]
+ %tmp17 = ashr i64 %tmp16, %.cast ; <i64> [#uses=1]
+ %tmp1718 = trunc i64 %tmp17 to i32 ; <i32> [#uses=1]
+ %tmp19 = getelementptr [10 x i8]* @.str, i32 0, i32 0 ; <i8*> [#uses=1]
+ volatile store i32 %tmp1718, i32* @var
+ volatile store i32 %tmp13, i32* @var
+ %tmp21 = load i32* %i, align 4 ; <i32> [#uses=1]
+ %tmp22 = add i32 %tmp21, 1 ; <i32> [#uses=1]
+ store i32 %tmp22, i32* %i, align 4
+ br label %bb23
+
+bb23: ; preds = %bb, %entry
+ %tmp24 = load i32* %i, align 4 ; <i32> [#uses=1]
+ %tmp25 = icmp sle i32 %tmp24, 2 ; <i1> [#uses=1]
+ %tmp2526 = zext i1 %tmp25 to i8 ; <i8> [#uses=1]
+ %toBool = icmp ne i8 %tmp2526, 0 ; <i1> [#uses=1]
+ br i1 %toBool, label %bb, label %bb27
+
+bb27: ; preds = %bb23
+ store i32 0, i32* %i, align 4
+ br label %bb46
+
+bb28: ; preds = %bb46
+ %tmp29 = load i32* %i, align 4 ; <i32> [#uses=1]
+ %tmp30 = getelementptr [3 x i64]* @dnan, i32 0, i32 %tmp29 ; <i64*> [#uses=1]
+ %tmp31 = load i64* %tmp30, align 8 ; <i64> [#uses=1]
+ %tmp32 = getelementptr %struct..1anon* %ud, i32 0, i32 0 ; <double*> [#uses=1]
+ %tmp3233 = bitcast double* %tmp32 to i64* ; <i64*> [#uses=1]
+ store i64 %tmp31, i64* %tmp3233, align 8
+ %tmp35 = getelementptr %struct..1anon* %ud, i32 0, i32 0 ; <double*> [#uses=1]
+ %tmp36 = load double* %tmp35, align 8 ; <double> [#uses=1]
+ %tmp3637 = fptrunc double %tmp36 to float ; <float> [#uses=1]
+ %tmp38 = getelementptr %struct..0anon* %uf, i32 0, i32 0 ; <float*> [#uses=1]
+ store float %tmp3637, float* %tmp38, align 4
+ %tmp39 = getelementptr %struct..0anon* %uf, i32 0, i32 0 ; <float*> [#uses=1]
+ %tmp3940 = bitcast float* %tmp39 to i32* ; <i32*> [#uses=1]
+ %tmp41 = load i32* %tmp3940, align 4 ; <i32> [#uses=1]
+ %tmp42 = getelementptr [6 x i8]* @.str1, i32 0, i32 0 ; <i8*> [#uses=1]
+ volatile store i32 %tmp41, i32* @var
+ %tmp44 = load i32* %i, align 4 ; <i32> [#uses=1]
+ %tmp45 = add i32 %tmp44, 1 ; <i32> [#uses=1]
+ store i32 %tmp45, i32* %i, align 4
+ br label %bb46
+
+bb46: ; preds = %bb28, %bb27
+ %tmp47 = load i32* %i, align 4 ; <i32> [#uses=1]
+ %tmp48 = icmp sle i32 %tmp47, 2 ; <i1> [#uses=1]
+ %tmp4849 = zext i1 %tmp48 to i8 ; <i8> [#uses=1]
+ %toBool50 = icmp ne i8 %tmp4849, 0 ; <i1> [#uses=1]
+ br i1 %toBool50, label %bb28, label %bb51
+
+bb51: ; preds = %bb46
+ store i32 0, i32* %i, align 4
+ br label %bb78
+
+bb52: ; preds = %bb78
+ %tmp53 = load i32* %i, align 4 ; <i32> [#uses=1]
+ %tmp54 = getelementptr [3 x i32]* @fsnan, i32 0, i32 %tmp53 ; <i32*> [#uses=1]
+ %tmp55 = load i32* %tmp54, align 4 ; <i32> [#uses=1]
+ %tmp56 = getelementptr %struct..0anon* %uf, i32 0, i32 0 ; <float*> [#uses=1]
+ %tmp5657 = bitcast float* %tmp56 to i32* ; <i32*> [#uses=1]
+ store i32 %tmp55, i32* %tmp5657, align 4
+ %tmp58 = getelementptr %struct..0anon* %uf, i32 0, i32 0 ; <float*> [#uses=1]
+ %tmp59 = load float* %tmp58, align 4 ; <float> [#uses=1]
+ %tmp5960 = fpext float %tmp59 to double ; <double> [#uses=1]
+ %tmp61 = getelementptr %struct..1anon* %ud, i32 0, i32 0 ; <double*> [#uses=1]
+ store double %tmp5960, double* %tmp61, align 8
+ %tmp62 = getelementptr %struct..1anon* %ud, i32 0, i32 0 ; <double*> [#uses=1]
+ %tmp6263 = bitcast double* %tmp62 to i64* ; <i64*> [#uses=1]
+ %tmp64 = load i64* %tmp6263, align 8 ; <i64> [#uses=1]
+ %tmp6465 = trunc i64 %tmp64 to i32 ; <i32> [#uses=1]
+ %tmp66 = and i32 %tmp6465, -1 ; <i32> [#uses=1]
+ %tmp68 = getelementptr %struct..1anon* %ud, i32 0, i32 0 ; <double*> [#uses=1]
+ %tmp6869 = bitcast double* %tmp68 to i64* ; <i64*> [#uses=1]
+ %tmp70 = load i64* %tmp6869, align 8 ; <i64> [#uses=1]
+ %.cast71 = zext i32 32 to i64 ; <i64> [#uses=1]
+ %tmp72 = ashr i64 %tmp70, %.cast71 ; <i64> [#uses=1]
+ %tmp7273 = trunc i64 %tmp72 to i32 ; <i32> [#uses=1]
+ %tmp74 = getelementptr [10 x i8]* @.str, i32 0, i32 0 ; <i8*> [#uses=1]
+ volatile store i32 %tmp7273, i32* @var
+ volatile store i32 %tmp66, i32* @var
+ %tmp76 = load i32* %i, align 4 ; <i32> [#uses=1]
+ %tmp77 = add i32 %tmp76, 1 ; <i32> [#uses=1]
+ store i32 %tmp77, i32* %i, align 4
+ br label %bb78
+
+bb78: ; preds = %bb52, %bb51
+ %tmp79 = load i32* %i, align 4 ; <i32> [#uses=1]
+ %tmp80 = icmp sle i32 %tmp79, 2 ; <i1> [#uses=1]
+ %tmp8081 = zext i1 %tmp80 to i8 ; <i8> [#uses=1]
+ %toBool82 = icmp ne i8 %tmp8081, 0 ; <i1> [#uses=1]
+ br i1 %toBool82, label %bb52, label %bb83
+
+bb83: ; preds = %bb78
+ store i32 0, i32* %i, align 4
+ br label %bb101
+
+bb84: ; preds = %bb101
+ %tmp85 = load i32* %i, align 4 ; <i32> [#uses=1]
+ %tmp86 = getelementptr [3 x i64]* @dsnan, i32 0, i32 %tmp85 ; <i64*> [#uses=1]
+ %tmp87 = load i64* %tmp86, align 8 ; <i64> [#uses=1]
+ %tmp88 = getelementptr %struct..1anon* %ud, i32 0, i32 0 ; <double*> [#uses=1]
+ %tmp8889 = bitcast double* %tmp88 to i64* ; <i64*> [#uses=1]
+ store i64 %tmp87, i64* %tmp8889, align 8
+ %tmp90 = getelementptr %struct..1anon* %ud, i32 0, i32 0 ; <double*> [#uses=1]
+ %tmp91 = load double* %tmp90, align 8 ; <double> [#uses=1]
+ %tmp9192 = fptrunc double %tmp91 to float ; <float> [#uses=1]
+ %tmp93 = getelementptr %struct..0anon* %uf, i32 0, i32 0 ; <float*> [#uses=1]
+ store float %tmp9192, float* %tmp93, align 4
+ %tmp94 = getelementptr %struct..0anon* %uf, i32 0, i32 0 ; <float*> [#uses=1]
+ %tmp9495 = bitcast float* %tmp94 to i32* ; <i32*> [#uses=1]
+ %tmp96 = load i32* %tmp9495, align 4 ; <i32> [#uses=1]
+ %tmp97 = getelementptr [6 x i8]* @.str1, i32 0, i32 0 ; <i8*> [#uses=1]
+ volatile store i32 %tmp96, i32* @var
+ %tmp99 = load i32* %i, align 4 ; <i32> [#uses=1]
+ %tmp100 = add i32 %tmp99, 1 ; <i32> [#uses=1]
+ store i32 %tmp100, i32* %i, align 4
+ br label %bb101
+
+bb101: ; preds = %bb84, %bb83
+ %tmp102 = load i32* %i, align 4 ; <i32> [#uses=1]
+ %tmp103 = icmp sle i32 %tmp102, 2 ; <i1> [#uses=1]
+ %tmp103104 = zext i1 %tmp103 to i8 ; <i8> [#uses=1]
+ %toBool105 = icmp ne i8 %tmp103104, 0 ; <i1> [#uses=1]
+ br i1 %toBool105, label %bb84, label %bb106
+
+bb106: ; preds = %bb101
+ br label %return
+
+return: ; preds = %bb106
+ %retval107 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval107
+}
diff --git a/test/CodeGen/X86/narrow_op-1.ll b/test/CodeGen/X86/narrow_op-1.ll
new file mode 100644
index 0000000..18f1108
--- /dev/null
+++ b/test/CodeGen/X86/narrow_op-1.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86-64 | grep orb | count 1
+; RUN: llc < %s -march=x86-64 | grep orb | grep 1
+; RUN: llc < %s -march=x86-64 | grep orl | count 1
+; RUN: llc < %s -march=x86-64 | grep orl | grep 16842752
+
+ %struct.bf = type { i64, i16, i16, i32 }
+@bfi = common global %struct.bf zeroinitializer, align 16
+
+define void @t1() nounwind optsize ssp {
+entry:
+ %0 = load i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
+ %1 = or i32 %0, 65536
+ store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
+ ret void
+}
+
+define void @t2() nounwind optsize ssp {
+entry:
+ %0 = load i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
+ %1 = or i32 %0, 16842752
+ store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
+ ret void
+}
diff --git a/test/CodeGen/X86/narrow_op-2.ll b/test/CodeGen/X86/narrow_op-2.ll
new file mode 100644
index 0000000..796ef7a
--- /dev/null
+++ b/test/CodeGen/X86/narrow_op-2.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+ %struct.bf = type { i64, i16, i16, i32 }
+@bfi = external global %struct.bf*
+
+define void @t1() nounwind ssp {
+entry:
+
+; CHECK: andb $-2, 10(
+; CHECK: andb $-3, 10(
+
+ %0 = load %struct.bf** @bfi, align 8
+ %1 = getelementptr %struct.bf* %0, i64 0, i32 1
+ %2 = bitcast i16* %1 to i32*
+ %3 = load i32* %2, align 1
+ %4 = and i32 %3, -65537
+ store i32 %4, i32* %2, align 1
+ %5 = load %struct.bf** @bfi, align 8
+ %6 = getelementptr %struct.bf* %5, i64 0, i32 1
+ %7 = bitcast i16* %6 to i32*
+ %8 = load i32* %7, align 1
+ %9 = and i32 %8, -131073
+ store i32 %9, i32* %7, align 1
+ ret void
+}
diff --git a/test/CodeGen/X86/neg-shl-add.ll b/test/CodeGen/X86/neg-shl-add.ll
new file mode 100644
index 0000000..7aebc38
--- /dev/null
+++ b/test/CodeGen/X86/neg-shl-add.ll
@@ -0,0 +1,17 @@
+; RUN: llc -march=x86-64 < %s | not grep negq
+
+; These sequences don't need neg instructions; they can be done with
+; a single shift and sub each.
+
+define i64 @foo(i64 %x, i64 %y, i64 %n) nounwind {
+ %a = sub i64 0, %y
+ %b = shl i64 %a, %n
+ %c = add i64 %b, %x
+ ret i64 %c
+}
+define i64 @boo(i64 %x, i64 %y, i64 %n) nounwind {
+ %a = sub i64 0, %y
+ %b = shl i64 %a, %n
+ %c = add i64 %x, %b
+ ret i64 %c
+}
diff --git a/test/CodeGen/X86/neg_fp.ll b/test/CodeGen/X86/neg_fp.ll
new file mode 100644
index 0000000..57164f2
--- /dev/null
+++ b/test/CodeGen/X86/neg_fp.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mattr=+sse41 -o %t
+; RUN: grep xorps %t | count 1
+
+; Test that when we don't -enable-unsafe-fp-math, we don't do the optimization
+; -0 - (A - B) to (B - A) because A==B, -0 != 0
+
+define float @negfp(float %a, float %b) {
+entry:
+ %sub = fsub float %a, %b ; <float> [#uses=1]
+ %neg = fsub float -0.000000e+00, %sub ; <float> [#uses=1]
+ ret float %neg
+}
diff --git a/test/CodeGen/X86/negate-add-zero.ll b/test/CodeGen/X86/negate-add-zero.ll
new file mode 100644
index 0000000..c3f412e
--- /dev/null
+++ b/test/CodeGen/X86/negate-add-zero.ll
@@ -0,0 +1,1145 @@
+; RUN: llc < %s -enable-unsafe-fp-math -march=x86 | not grep xor
+; PR3374
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin7"
+ %struct.AtomList = type { %"struct.CDSListRep<IVMAtom*>"* }
+ %struct.AtomTree = type { %struct.IVM*, %"struct.CDSList<CDSList<HingeNode*> >" }
+ %"struct.CDS::DefaultAlloc" = type <{ i8 }>
+ %"struct.CDS::SingularError" = type { %"struct.CDS::exception" }
+ %"struct.CDS::auto_ptr<IVMAtom>" = type { %struct.IVMAtom* }
+ %"struct.CDS::exception" = type { [300 x i8] }
+ %"struct.CDSList<CDSList<HingeNode*> >" = type { %"struct.CDSListRep<CDSList<HingeNode*> >"* }
+ %"struct.CDSList<CDSList<int> >" = type { %"struct.CDSListRep<CDSList<int> >"* }
+ %"struct.CDSList<HingeNode*>" = type { %"struct.CDSListRep<HingeNode*>"* }
+ %"struct.CDSList<InternalDynamics::HingeSpec>" = type { %"struct.CDSListRep<InternalDynamics::HingeSpec>"* }
+ %"struct.CDSList<Loop>" = type { %"struct.CDSListRep<Loop>"* }
+ %"struct.CDSList<Pair<int, int> >" = type { %"struct.CDSListRep<Pair<int, int> >"* }
+ %"struct.CDSList<int>" = type { %"struct.CDSListRep<int>"* }
+ %"struct.CDSListRep<CDSList<HingeNode*> >" = type opaque
+ %"struct.CDSListRep<CDSList<int> >" = type opaque
+ %"struct.CDSListRep<HingeNode*>" = type { i32, i32, %struct.HingeNode**, i32 }
+ %"struct.CDSListRep<IVMAtom*>" = type { i32, i32, %struct.IVMAtom**, i32 }
+ %"struct.CDSListRep<InternalDynamics::HingeSpec>" = type opaque
+ %"struct.CDSListRep<Loop>" = type opaque
+ %"struct.CDSListRep<Pair<int, int> >" = type opaque
+ %"struct.CDSListRep<int>" = type { i32, i32, i32*, i32 }
+ %"struct.CDSMatrixBase<double>" = type { %"struct.CDSMatrixRep<double>"* }
+ %"struct.CDSMatrixRep<double>" = type opaque
+ %"struct.CDSStringRep<char>" = type { i8*, i32, i32, i32, i32 }
+ %"struct.CDSVector<Vec3,0,CDS::DefaultAlloc>" = type { %"struct.CDSVectorBase<Vec3,CDS::DefaultAlloc>" }
+ %"struct.CDSVector<double,0,CDS::DefaultAlloc>" = type { %"struct.CDSVectorBase<double,CDS::DefaultAlloc>" }
+ %"struct.CDSVectorBase<Vec3,CDS::DefaultAlloc>" = type { %"struct.CDSVectorRep<Vec3,CDS::DefaultAlloc>"* }
+ %"struct.CDSVectorBase<double,CDS::DefaultAlloc>" = type { %"struct.CDSVectorRep<double,CDS::DefaultAlloc>"* }
+ %"struct.CDSVectorRep<Vec3,CDS::DefaultAlloc>" = type { i32, %"struct.CDS::DefaultAlloc", %struct.Vec3*, i32 }
+ %"struct.CDSVectorRep<double,CDS::DefaultAlloc>" = type { i32, %"struct.CDS::DefaultAlloc", double*, i32 }
+ %"struct.FixedMatrix<double,1,1,0,0>" = type { %"struct.FixedMatrixBase<double,1,1>" }
+ %"struct.FixedMatrix<double,1,3,0,0>" = type { %"struct.FixedMatrixBase<double,1,3>" }
+ %"struct.FixedMatrix<double,1,6,0,0>" = type { %"struct.FixedMatrixBase<double,1,6>" }
+ %"struct.FixedMatrix<double,2,2,0,0>" = type { %"struct.FixedMatrixBase<double,2,2>" }
+ %"struct.FixedMatrix<double,2,6,0,0>" = type { %"struct.FixedMatrixBase<double,2,6>" }
+ %"struct.FixedMatrix<double,3,3,0,0>" = type { %"struct.FixedMatrixBase<double,3,3>" }
+ %"struct.FixedMatrix<double,3,6,0,0>" = type { %"struct.FixedMatrixBase<double,3,6>" }
+ %"struct.FixedMatrix<double,5,5,0,0>" = type { %"struct.FixedMatrixBase<double,5,5>" }
+ %"struct.FixedMatrix<double,5,6,0,0>" = type { %"struct.FixedMatrixBase<double,5,6>" }
+ %"struct.FixedMatrixBase<double,1,1>" = type { [1 x double] }
+ %"struct.FixedMatrixBase<double,1,3>" = type { [3 x double] }
+ %"struct.FixedMatrixBase<double,1,6>" = type { [6 x double] }
+ %"struct.FixedMatrixBase<double,2,2>" = type { [4 x double] }
+ %"struct.FixedMatrixBase<double,2,6>" = type { [12 x double] }
+ %"struct.FixedMatrixBase<double,3,3>" = type { [9 x double] }
+ %"struct.FixedMatrixBase<double,3,6>" = type { [18 x double] }
+ %"struct.FixedMatrixBase<double,5,5>" = type { [25 x double] }
+ %"struct.FixedMatrixBase<double,5,6>" = type { [30 x double] }
+ %"struct.FixedMatrixBase<double,6,6>" = type { [36 x double] }
+ %"struct.FixedVector<double,2,0>" = type { %"struct.FixedVectorBase<double,2>" }
+ %"struct.FixedVector<double,5,0>" = type { %"struct.FixedVectorBase<double,5>" }
+ %"struct.FixedVectorBase<double,2>" = type { [2 x double] }
+ %"struct.FixedVectorBase<double,5>" = type { [5 x double] }
+ %struct.HNodeOrigin = type { %struct.HingeNode }
+ %struct.HNodeRotate2 = type { %"struct.HingeNodeSpec<2>", %struct.Vec3, %struct.Vec3, %struct.Vec3, %struct.Vec3, %struct.Vec3, %struct.Mat3, %struct.Mat3, %struct.Vec3, %"struct.CDS::auto_ptr<IVMAtom>", %"struct.CDSVector<Vec3,0,CDS::DefaultAlloc>" }
+ %struct.HNodeRotate3 = type { %"struct.HingeNodeSpec<3>", %struct.Vec4, %struct.Vec4, %struct.Vec4, %struct.Vec3, %"struct.CDS::auto_ptr<IVMAtom>", %"struct.CDSVector<Vec3,0,CDS::DefaultAlloc>", double, double, double, double, double, double, i8 }
+ %struct.HNodeTorsion = type { %"struct.HingeNodeSpec<1>", %struct.Vec3, %"struct.CDSVector<Vec3,0,CDS::DefaultAlloc>", %struct.Vec3, %struct.Mat3 }
+ %struct.HNodeTranslate = type { %"struct.HingeNodeSpec<3>", %struct.IVMAtom*, %struct.Vec3, %"struct.CDSVector<Vec3,0,CDS::DefaultAlloc>" }
+ %struct.HNodeTranslateRotate2 = type { %"struct.HingeNodeSpec<5>", %struct.Vec3, %struct.Vec3, %struct.Vec3, %struct.Vec3, %struct.Vec3, %struct.Mat3, %struct.Mat3, %struct.Vec3, %"struct.CDS::auto_ptr<IVMAtom>", %"struct.CDSVector<Vec3,0,CDS::DefaultAlloc>" }
+ %struct.HNodeTranslateRotate3 = type { %"struct.HingeNodeSpec<6>", %struct.Vec4, %struct.Vec4, %struct.Vec4, %struct.Vec3, %"struct.CDS::auto_ptr<IVMAtom>", %"struct.CDSVector<Vec3,0,CDS::DefaultAlloc>", double, double, double, double, double, double, i8 }
+ %struct.HingeNode = type { i32 (...)**, %struct.HingeNode*, %"struct.CDSList<HingeNode*>", i32, %struct.AtomList, %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %struct.PhiMatrix, %struct.Mat6, %struct.Mat6, %"struct.FixedMatrix<double,1,6,0,0>", %struct.Mat6, %"struct.FixedMatrix<double,1,6,0,0>", %struct.Mat3, %struct.Mat6, %struct.IVM*, %struct.IVMAtom* }
+ %"struct.HingeNodeSpec<1>" = type { %struct.HingeNode, i32, double, %struct.InertiaTensor, %struct.Mat6, %struct.Vec3, %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,1,0,0>", %"struct.FixedMatrix<double,1,1,0,0>", %"struct.FixedMatrix<double,1,1,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,1,0,0>", %"struct.FixedMatrix<double,1,1,0,0>", %"struct.FixedMatrix<double,1,1,0,0>", %"struct.FixedMatrix<double,1,1,0,0>", %"struct.FixedMatrix<double,1,6,0,0>" }
+ %"struct.HingeNodeSpec<2>" = type { %struct.HingeNode, i32, double, %struct.InertiaTensor, %struct.Mat6, %struct.Vec3, %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedVector<double,2,0>", %"struct.FixedVector<double,2,0>", %"struct.FixedVector<double,2,0>", %"struct.FixedMatrix<double,2,6,0,0>", %"struct.FixedVector<double,2,0>", %"struct.FixedVector<double,2,0>", %"struct.FixedVector<double,2,0>", %"struct.FixedMatrix<double,2,2,0,0>", %"struct.FixedMatrix<double,2,6,0,0>" }
+ %"struct.HingeNodeSpec<3>" = type { %struct.HingeNode, i32, double, %struct.InertiaTensor, %struct.Mat6, %struct.Vec3, %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,3,0,0>", %"struct.FixedMatrix<double,1,3,0,0>", %"struct.FixedMatrix<double,1,3,0,0>", %"struct.FixedMatrix<double,3,6,0,0>", %"struct.FixedMatrix<double,1,3,0,0>", %"struct.FixedMatrix<double,1,3,0,0>", %"struct.FixedMatrix<double,1,3,0,0>", %"struct.FixedMatrix<double,3,3,0,0>", %"struct.FixedMatrix<double,3,6,0,0>" }
+ %"struct.HingeNodeSpec<5>" = type { %struct.HingeNode, i32, double, %struct.InertiaTensor, %struct.Mat6, %struct.Vec3, %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedVector<double,5,0>", %"struct.FixedVector<double,5,0>", %"struct.FixedVector<double,5,0>", %"struct.FixedMatrix<double,5,6,0,0>", %"struct.FixedVector<double,5,0>", %"struct.FixedVector<double,5,0>", %"struct.FixedVector<double,5,0>", %"struct.FixedMatrix<double,5,5,0,0>", %"struct.FixedMatrix<double,5,6,0,0>" }
+ %"struct.HingeNodeSpec<6>" = type { %struct.HingeNode, i32, double, %struct.InertiaTensor, %struct.Mat6, %struct.Vec3, %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %struct.Mat6, %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %"struct.FixedMatrix<double,1,6,0,0>", %struct.Mat6, %struct.Mat6 }
+ %struct.IVM = type { i32 (...)**, %struct.AtomTree*, %struct.Integrator*, %struct.LengthConstraints*, i32, i32, i32, i8, i8, i8, i8, double, double, double, double, double, double, double, double, double, i32, double, double, double, double, double, double, %"struct.CDSList<Loop>", %"struct.CDSList<Pair<int, int> >", %struct.AtomList, %"struct.CDSList<CDSList<int> >", %"struct.CDSList<InternalDynamics::HingeSpec>", %struct.String, %"struct.CDSList<int>", i32 (%"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)*, double (%"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)*, i32 (%"struct.CDSVector<Vec3,0,CDS::DefaultAlloc>"*)*, double (%"struct.CDSVector<Vec3,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<Vec3,0,CDS::DefaultAlloc>"*)* }
+ %struct.IVMAtom = type { i32, %struct.HingeNode*, %struct.AtomList, %struct.Vec3, %struct.Vec3, %struct.Vec3, double, double }
+ %struct.InertiaTensor = type { %struct.Mat3 }
+ %struct.Integrator = type { i32 (...)**, %"struct.CDSVector<double,0,CDS::DefaultAlloc>", %"struct.CDSVector<double,0,CDS::DefaultAlloc>", %struct.IVM* }
+ %"struct.InternalDynamics::HingeSpec" = type { %struct.String, i32, i32, %"struct.CDSList<int>" }
+ %struct.LengthConstraints = type { double, i32, i32, %struct.IVM*, %struct.LengthConstraintsPrivates* }
+ %struct.LengthConstraintsPrivates = type opaque
+ %struct.Mat3 = type { %"struct.FixedMatrix<double,3,3,0,0>" }
+ %struct.Mat6 = type { %"struct.FixedMatrixBase<double,6,6>" }
+ %"struct.MatrixTools::InverseResults<FullMatrix<double> >" = type { %"struct.CDSVector<double,0,CDS::DefaultAlloc>", i32 }
+ %struct.PhiMatrix = type { %struct.Vec3 }
+ %struct.PhiMatrixTranspose = type { %struct.PhiMatrix* }
+ %struct.RMat = type { %"struct.CDSMatrixBase<double>" }
+ %struct.String = type { %"struct.CDSStringRep<char>"* }
+ %"struct.SubMatrix<FixedMatrix<double, 6, 6, 0, 0> >" = type { %struct.Mat6*, i32, i32, i32, i32 }
+ %"struct.SubVector<CDSVector<double, 1, CDS::DefaultAlloc> >" = type { %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, i32, i32 }
+ %"struct.SubVector<FixedVector<double, 6, 0> >" = type { %"struct.FixedMatrix<double,1,6,0,0>"*, i32, i32 }
+ %struct.Vec3 = type { %"struct.FixedMatrix<double,1,3,0,0>" }
+ %struct.Vec4 = type { %"struct.FixedMatrix<double,2,2,0,0>" }
+ %struct.__class_type_info_pseudo = type { %struct.__type_info_pseudo }
+ %struct.__si_class_type_info_pseudo = type { %struct.__type_info_pseudo, %"struct.std::type_info"* }
+ %struct.__type_info_pseudo = type { i8*, i8* }
+ %"struct.std::basic_ios<char,std::char_traits<char> >" = type { %"struct.std::ios_base", %"struct.std::basic_ostream<char,std::char_traits<char> >"*, i8, i8, %"struct.std::basic_streambuf<char,std::char_traits<char> >"*, %"struct.std::ctype<char>"*, %"struct.std::num_get<char,std::istreambuf_iterator<char, std::char_traits<char> > >"*, %"struct.std::num_get<char,std::istreambuf_iterator<char, std::char_traits<char> > >"* }
+ %"struct.std::basic_ostream<char,std::char_traits<char> >" = type { i32 (...)**, %"struct.std::basic_ios<char,std::char_traits<char> >" }
+ %"struct.std::basic_streambuf<char,std::char_traits<char> >" = type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %"struct.std::locale" }
+ %"struct.std::ctype<char>" = type { %"struct.std::locale::facet", i32*, i8, i32*, i32*, i32*, i8, [256 x i8], [256 x i8], i8 }
+ %"struct.std::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, %"struct.std::ios_base::_Callback_list"*, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, %"struct.std::ios_base::_Words"*, %"struct.std::locale" }
+ %"struct.std::ios_base::_Callback_list" = type { %"struct.std::ios_base::_Callback_list"*, void (i32, %"struct.std::ios_base"*, i32)*, i32, i32 }
+ %"struct.std::ios_base::_Words" = type { i8*, i32 }
+ %"struct.std::locale" = type { %"struct.std::locale::_Impl"* }
+ %"struct.std::locale::_Impl" = type { i32, %"struct.std::locale::facet"**, i32, %"struct.std::locale::facet"**, i8** }
+ %"struct.std::locale::facet" = type { i32 (...)**, i32 }
+ %"struct.std::num_get<char,std::istreambuf_iterator<char, std::char_traits<char> > >" = type { %"struct.std::locale::facet" }
+ %"struct.std::type_info" = type { i32 (...)**, i8* }
+@_ZN9HingeNode7DEG2RADE = external constant double, align 8 ; <double*> [#uses=0]
+@"\01LC" = external constant [8 x i8] ; <[8 x i8]*> [#uses=0]
+@"\01LC1" = external constant [7 x i8] ; <[7 x i8]*> [#uses=0]
+@"\01LC2" = external constant [10 x i8] ; <[10 x i8]*> [#uses=0]
+@"\01LC3" = external constant [5 x i8] ; <[5 x i8]*> [#uses=0]
+@"\01LC4" = external constant [8 x i8] ; <[8 x i8]*> [#uses=0]
+@"\01LC5" = external constant [8 x i8] ; <[8 x i8]*> [#uses=0]
+@"\01LC6" = external constant [7 x i8] ; <[7 x i8]*> [#uses=0]
+@"\01LC7" = external constant [8 x i8] ; <[8 x i8]*> [#uses=0]
+@"\01LC8" = external constant [3 x i8] ; <[3 x i8]*> [#uses=0]
+@"\01LC9" = external constant [3 x i8] ; <[3 x i8]*> [#uses=0]
+@"\01LC10" = external constant [3 x i8] ; <[3 x i8]*> [#uses=0]
+@_ZStL8__ioinit = external global %"struct.CDS::DefaultAlloc" ; <%"struct.CDS::DefaultAlloc"*> [#uses=0]
+@__dso_handle = external global i8* ; <i8**> [#uses=0]
+@_ZTIN9HingeNode17VirtualBaseMethodE = external constant %struct.__class_type_info_pseudo ; <%struct.__class_type_info_pseudo*> [#uses=0]
+@_ZTVN10__cxxabiv117__class_type_infoE = external constant [0 x i32 (...)*] ; <[0 x i32 (...)*]*> [#uses=0]
+@_ZTSN9HingeNode17VirtualBaseMethodE = external constant [32 x i8], align 4 ; <[32 x i8]*> [#uses=0]
+@_ZTV9HingeNode = external constant [31 x i32 (...)*], align 32 ; <[31 x i32 (...)*]*> [#uses=0]
+@_ZTI9HingeNode = external constant %struct.__class_type_info_pseudo ; <%struct.__class_type_info_pseudo*> [#uses=0]
+@_ZTS9HingeNode = external constant [11 x i8] ; <[11 x i8]*> [#uses=0]
+@_ZTV11HNodeOrigin = external constant [31 x i32 (...)*], align 32 ; <[31 x i32 (...)*]*> [#uses=0]
+@_ZTI11HNodeOrigin = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0]
+@_ZTVN10__cxxabiv120__si_class_type_infoE = external constant [0 x i32 (...)*] ; <[0 x i32 (...)*]*> [#uses=0]
+@_ZTS11HNodeOrigin = external constant [14 x i8] ; <[14 x i8]*> [#uses=0]
+@_ZTV13HingeNodeSpecILi1EE = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0]
+@_ZTI13HingeNodeSpecILi1EE = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0]
+@_ZTS13HingeNodeSpecILi1EE = external constant [22 x i8] ; <[22 x i8]*> [#uses=0]
+@_ZTV13HingeNodeSpecILi3EE = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0]
+@_ZTI13HingeNodeSpecILi3EE = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0]
+@_ZTS13HingeNodeSpecILi3EE = external constant [22 x i8] ; <[22 x i8]*> [#uses=0]
+@_ZTV13HingeNodeSpecILi2EE = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0]
+@_ZTI13HingeNodeSpecILi2EE = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0]
+@_ZTS13HingeNodeSpecILi2EE = external constant [22 x i8] ; <[22 x i8]*> [#uses=0]
+@_ZTV13HingeNodeSpecILi6EE = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0]
+@_ZTI13HingeNodeSpecILi6EE = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0]
+@_ZTS13HingeNodeSpecILi6EE = external constant [22 x i8] ; <[22 x i8]*> [#uses=0]
+@_ZTV13HingeNodeSpecILi5EE = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0]
+@_ZTI13HingeNodeSpecILi5EE = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0]
+@_ZTS13HingeNodeSpecILi5EE = external constant [22 x i8] ; <[22 x i8]*> [#uses=0]
+@_ZSt4cout = external global %"struct.std::basic_ostream<char,std::char_traits<char> >" ; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=0]
+@"\01LC11" = external constant [10 x i8] ; <[10 x i8]*> [#uses=0]
+@"\01LC12" = external constant [8 x i8] ; <[8 x i8]*> [#uses=0]
+@"\01LC13" = external constant [10 x i8] ; <[10 x i8]*> [#uses=0]
+@_ZSt4cerr = external global %"struct.std::basic_ostream<char,std::char_traits<char> >" ; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=0]
+@"\01LC14" = external constant [29 x i8] ; <[29 x i8]*> [#uses=0]
+@"\01LC15" = external constant [11 x i8] ; <[11 x i8]*> [#uses=0]
+@"\01LC16" = external constant [13 x i8] ; <[13 x i8]*> [#uses=0]
+@"\01LC17" = external constant [21 x i8] ; <[21 x i8]*> [#uses=0]
+@"\01LC18" = external constant [8 x i8] ; <[8 x i8]*> [#uses=0]
+@"\01LC19" = external constant [4 x i8] ; <[4 x i8]*> [#uses=0]
+@"\01LC20" = external constant [42 x i8] ; <[42 x i8]*> [#uses=0]
+@_ZTIN16InternalDynamics9ExceptionE = external constant %struct.__class_type_info_pseudo ; <%struct.__class_type_info_pseudo*> [#uses=0]
+@_ZTSN16InternalDynamics9ExceptionE = external constant [31 x i8], align 4 ; <[31 x i8]*> [#uses=0]
+@_ZTIN3CDS13SingularErrorE = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0]
+@_ZTSN3CDS13SingularErrorE = external constant [22 x i8] ; <[22 x i8]*> [#uses=0]
+@_ZTIN3CDS9exceptionE = external constant %struct.__class_type_info_pseudo ; <%struct.__class_type_info_pseudo*> [#uses=0]
+@_ZTSN3CDS9exceptionE = external constant [17 x i8] ; <[17 x i8]*> [#uses=0]
+@_ZTV12HNodeTorsion = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0]
+@_ZTI12HNodeTorsion = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0]
+@_ZTS12HNodeTorsion = external constant [15 x i8] ; <[15 x i8]*> [#uses=0]
+@_ZTV12HNodeRotate3 = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0]
+@_ZTI12HNodeRotate3 = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0]
+@_ZTS12HNodeRotate3 = external constant [15 x i8] ; <[15 x i8]*> [#uses=0]
+@_ZTV12HNodeRotate2 = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0]
+@_ZTI12HNodeRotate2 = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0]
+@_ZTS12HNodeRotate2 = external constant [15 x i8] ; <[15 x i8]*> [#uses=0]
+@_ZTV21HNodeTranslateRotate3 = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0]
+@_ZTI21HNodeTranslateRotate3 = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0]
+@_ZTS21HNodeTranslateRotate3 = external constant [24 x i8] ; <[24 x i8]*> [#uses=0]
+@_ZTV21HNodeTranslateRotate2 = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0]
+@_ZTI21HNodeTranslateRotate2 = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0]
+@_ZTS21HNodeTranslateRotate2 = external constant [24 x i8] ; <[24 x i8]*> [#uses=0]
+@_ZTV14HNodeTranslate = external constant [33 x i32 (...)*], align 32 ; <[33 x i32 (...)*]*> [#uses=0]
+@_ZTI14HNodeTranslate = external constant %struct.__si_class_type_info_pseudo ; <%struct.__si_class_type_info_pseudo*> [#uses=0]
+@_ZTS14HNodeTranslate = external constant [17 x i8] ; <[17 x i8]*> [#uses=0]
+@"\01LC21" = external constant [31 x i8] ; <[31 x i8]*> [#uses=0]
+@"\01LC22" = external constant [6 x i8] ; <[6 x i8]*> [#uses=0]
+@"\01LC23" = external constant [12 x i8] ; <[12 x i8]*> [#uses=0]
+@"\01LC24" = external constant [5 x i8] ; <[5 x i8]*> [#uses=0]
+@"\01LC25" = external constant [7 x i8] ; <[7 x i8]*> [#uses=0]
+@"\01LC26" = external constant [7 x i8] ; <[7 x i8]*> [#uses=0]
+@"\01LC27" = external constant [43 x i8] ; <[43 x i8]*> [#uses=0]
+@"\01LC28" = external constant [15 x i8] ; <[15 x i8]*> [#uses=0]
+@"\01LC29" = external constant [20 x i8] ; <[20 x i8]*> [#uses=0]
+@"\01LC30" = external constant [41 x i8] ; <[41 x i8]*> [#uses=0]
[email protected]_ctors = external global [1 x { i32, void ()* }] ; <[1 x { i32, void ()* }]*> [#uses=0]
+
+declare void @_GLOBAL__I__ZN9HingeNode7DEG2RADE() section "__TEXT,__StaticInit,regular,pure_instructions"
+
+declare void @_ZN9HingeNode16velFromCartesianEv(%struct.HingeNode*) nounwind
+
+declare i32 @_ZNK9HingeNode6offsetEv(%struct.HingeNode*) nounwind
+
+declare i32 @_ZNK9HingeNode6getDOFEv(%struct.HingeNode*) nounwind
+
+declare i32 @_ZNK9HingeNode6getDimEv(%struct.HingeNode*) nounwind
+
+declare double @_ZN9HingeNode8kineticEEv(%struct.HingeNode*) nounwind
+
+declare double @_ZN9HingeNode8approxKEEv(%struct.HingeNode*) nounwind
+
+declare i8* @_ZN9HingeNode4typeEv(%struct.HingeNode*) nounwind
+
+declare i8* @_ZN11HNodeOrigin4typeEv(%struct.HNodeOrigin*) nounwind
+
+declare void @_ZN11HNodeOrigin5calcPEv(%struct.HNodeOrigin*) nounwind
+
+declare void @_ZN11HNodeOrigin5calcZEv(%struct.HNodeOrigin*) nounwind
+
+declare void @_ZN11HNodeOrigin9calcPandZEv(%struct.HNodeOrigin*) nounwind
+
+declare void @_ZN11HNodeOrigin9calcAccelEv(%struct.HNodeOrigin*) nounwind
+
+declare void @_ZN11HNodeOrigin17calcInternalForceEv(%struct.HNodeOrigin*) nounwind
+
+declare void @_ZN11HNodeOrigin18prepareVelInternalEv(%struct.HNodeOrigin*) nounwind
+
+declare void @_ZN11HNodeOrigin13propagateSVelERK11FixedVectorIdLi6ELi0EE(%struct.HNodeOrigin*, %"struct.FixedMatrix<double,1,6,0,0>"*) nounwind
+
+declare void @_ZN11HNodeOrigin9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%struct.HNodeOrigin*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*) nounwind
+
+declare void @_ZN11HNodeOrigin6setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeOrigin*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*) nounwind
+
+declare void @_ZN11HNodeOrigin14setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%struct.HNodeOrigin*, %"struct.FixedMatrix<double,1,6,0,0>"*) nounwind
+
+declare void @_ZN11HNodeOrigin18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES4_(%struct.HNodeOrigin*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*) nounwind
+
+declare void @_ZN11HNodeOrigin5printEi(%struct.HNodeOrigin*, i32) nounwind
+
+declare void @_ZN11HNodeOrigin6getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeOrigin*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*) nounwind
+
+declare void @_ZN11HNodeOrigin6getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeOrigin*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*) nounwind
+
+declare void @_ZN11HNodeOrigin8getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeOrigin*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*) nounwind
+
+declare void @_ZN11HNodeOrigin16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeOrigin*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*) nounwind
+
+declare void @_ZN11HNodeOrigin5calcYEv(%struct.HNodeOrigin*) nounwind
+
+declare i8* @_ZN14HNodeTranslate4typeEv(%struct.HNodeTranslate*) nounwind
+
+declare i8* @_ZN21HNodeTranslateRotate34typeEv(%struct.HNodeTranslateRotate3*) nounwind
+
+declare i32 @_ZNK21HNodeTranslateRotate36getDimEv(%struct.HNodeTranslateRotate3*) nounwind
+
+declare i8* @_ZN12HNodeRotate34typeEv(%struct.HNodeRotate3*) nounwind
+
+declare i32 @_ZNK12HNodeRotate36getDimEv(%struct.HNodeRotate3*) nounwind
+
+declare i8* @_ZN12HNodeRotate24typeEv(%struct.HNodeRotate2*) nounwind
+
+declare i32 @_ZNK12HNodeRotate26getDimEv(%struct.HNodeRotate2*) nounwind
+
+declare i8* @_ZN21HNodeTranslateRotate24typeEv(%struct.HNodeTranslateRotate2*) nounwind
+
+declare i32 @_ZNK21HNodeTranslateRotate26getDimEv(%struct.HNodeTranslateRotate2*) nounwind
+
+declare i8* @_ZN12HNodeTorsion4typeEv(%struct.HNodeTorsion*) nounwind
+
+declare fastcc double @_ZL12sumMassToTipPK9HingeNode(%struct.HingeNode*)
+
+declare void @_ZN13InertiaTensor4calcERK4Vec3RK7CDSListIP7IVMAtomE(%struct.InertiaTensor*, %struct.Vec3*, %struct.AtomList*) nounwind
+
+declare fastcc double @_ZL15sumInertiaToTipPK9HingeNodeRK4Vec3S4_(%struct.HingeNode*, %struct.Vec3*, %struct.Vec3*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsI11FixedVectorIdLi6ELi0EEERSoS2_RK9SubVectorIT_E(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.SubVector<FixedVector<double, 6, 0> >"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St5_Setw(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, i32)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, i8*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZNSolsEd(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, double)
+
+declare void @_Z14orthoTransformIdLi3ELi3EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix<double,3,3,0,0>"* noalias sret, %"struct.FixedMatrix<double,3,3,0,0>"*, %"struct.FixedMatrix<double,3,3,0,0>"*)
+
+declare void @_ZN12HNodeRotate27calcRotEv(%struct.HNodeRotate2*)
+
+declare void @_ZN21HNodeTranslateRotate27calcRotEv(%struct.HNodeTranslateRotate2*)
+
+declare void @_ZmlIdLi6ELi6EE11FixedVectorIT_XT0_ELi0EERK11FixedMatrixIS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_ELi0EE(%"struct.FixedMatrix<double,1,6,0,0>"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZmlIdLi6ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%struct.Mat6* noalias sret, %struct.Mat6*, %struct.Mat6*)
+
+declare void @_ZmlIdLi6ELi6ELi3EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix<double,3,6,0,0>"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix<double,3,6,0,0>"*)
+
+declare void @_ZmlIdLi6ELi6ELi2EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix<double,2,6,0,0>"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix<double,2,6,0,0>"*)
+
+declare void @_ZmlIdLi5ELi6EE11FixedVectorIT_XT0_ELi0EERK11FixedMatrixIS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_ELi0EE(%"struct.FixedVector<double,5,0>"* noalias sret, %"struct.FixedMatrix<double,5,6,0,0>"*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZmlIdLi6ELi6ELi5EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix<double,5,6,0,0>"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix<double,5,6,0,0>"*)
+
+declare void @_ZN12HNodeRotate39setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%struct.HNodeRotate3*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeRotate29setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%struct.HNodeRotate2*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN21HNodeTranslateRotate39setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%struct.HNodeTranslateRotate3*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN21HNodeTranslateRotate29setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%struct.HNodeTranslateRotate2*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare i32 @_ZNK13HingeNodeSpecILi1EE6offsetEv(%"struct.HingeNodeSpec<1>"*) nounwind
+
+declare %struct.Vec3* @_ZNK13HingeNodeSpecILi1EE5posCMEv(%"struct.HingeNodeSpec<1>"*) nounwind
+
+declare double* @_ZNK13HingeNodeSpecILi1EE4massEv(%"struct.HingeNodeSpec<1>"*) nounwind
+
+declare void @_ZN13HingeNodeSpecILi1EE9calcPandZEv(%"struct.HingeNodeSpec<1>"*)
+
+declare i32 @_ZNK13HingeNodeSpecILi1EE6getDOFEv(%"struct.HingeNodeSpec<1>"*) nounwind
+
+declare i32 @_ZNK13HingeNodeSpecILi1EE6getDimEv(%"struct.HingeNodeSpec<1>"*) nounwind
+
+declare void @_ZN13HingeNodeSpecILi1EE18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*) nounwind
+
+declare i32 @_ZNK13HingeNodeSpecILi5EE6offsetEv(%"struct.HingeNodeSpec<5>"*) nounwind
+
+declare %struct.Vec3* @_ZNK13HingeNodeSpecILi5EE5posCMEv(%"struct.HingeNodeSpec<5>"*) nounwind
+
+declare double* @_ZNK13HingeNodeSpecILi5EE4massEv(%"struct.HingeNodeSpec<5>"*) nounwind
+
+declare void @_ZN13HingeNodeSpecILi5EE9calcPandZEv(%"struct.HingeNodeSpec<5>"*)
+
+declare i32 @_ZNK13HingeNodeSpecILi5EE6getDOFEv(%"struct.HingeNodeSpec<5>"*) nounwind
+
+declare i32 @_ZNK13HingeNodeSpecILi5EE6getDimEv(%"struct.HingeNodeSpec<5>"*) nounwind
+
+declare void @_ZN13HingeNodeSpecILi5EE18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%"struct.HingeNodeSpec<5>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*) nounwind
+
+declare i32 @_ZNK13HingeNodeSpecILi2EE6offsetEv(%"struct.HingeNodeSpec<2>"*) nounwind
+
+declare %struct.Vec3* @_ZNK13HingeNodeSpecILi2EE5posCMEv(%"struct.HingeNodeSpec<2>"*) nounwind
+
+declare double* @_ZNK13HingeNodeSpecILi2EE4massEv(%"struct.HingeNodeSpec<2>"*) nounwind
+
+declare void @_ZN13HingeNodeSpecILi2EE9calcPandZEv(%"struct.HingeNodeSpec<2>"*)
+
+declare i32 @_ZNK13HingeNodeSpecILi2EE6getDOFEv(%"struct.HingeNodeSpec<2>"*) nounwind
+
+declare i32 @_ZNK13HingeNodeSpecILi2EE6getDimEv(%"struct.HingeNodeSpec<2>"*) nounwind
+
+declare void @_ZN13HingeNodeSpecILi2EE18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*) nounwind
+
+declare i32 @_ZNK13HingeNodeSpecILi3EE6offsetEv(%"struct.HingeNodeSpec<3>"*) nounwind
+
+declare %struct.Vec3* @_ZNK13HingeNodeSpecILi3EE5posCMEv(%"struct.HingeNodeSpec<3>"*) nounwind
+
+declare double* @_ZNK13HingeNodeSpecILi3EE4massEv(%"struct.HingeNodeSpec<3>"*) nounwind
+
+declare void @_ZN13HingeNodeSpecILi3EE9calcPandZEv(%"struct.HingeNodeSpec<3>"*)
+
+declare i32 @_ZNK13HingeNodeSpecILi3EE6getDOFEv(%"struct.HingeNodeSpec<3>"*) nounwind
+
+declare i32 @_ZNK13HingeNodeSpecILi6EE6offsetEv(%"struct.HingeNodeSpec<6>"*) nounwind
+
+declare %struct.Vec3* @_ZNK13HingeNodeSpecILi6EE5posCMEv(%"struct.HingeNodeSpec<6>"*) nounwind
+
+declare double* @_ZNK13HingeNodeSpecILi6EE4massEv(%"struct.HingeNodeSpec<6>"*) nounwind
+
+declare void @_ZN13HingeNodeSpecILi6EE9calcPandZEv(%"struct.HingeNodeSpec<6>"*)
+
+declare i32 @_ZNK13HingeNodeSpecILi6EE6getDOFEv(%"struct.HingeNodeSpec<6>"*) nounwind
+
+declare i32 @_ZNK13HingeNodeSpecILi6EE6getDimEv(%"struct.HingeNodeSpec<6>"*) nounwind
+
+declare void @_ZN13HingeNodeSpecILi6EE9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES6_(%"struct.HingeNodeSpec<6>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%"struct.HingeNodeSpec<6>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*) nounwind
+
+declare i32 @_ZNK13HingeNodeSpecILi3EE6getDimEv(%"struct.HingeNodeSpec<3>"*) nounwind
+
+declare void @_ZN13HingeNodeSpecILi3EE9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES6_(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*) nounwind
+
+declare void @_Z14orthoTransformIdLi6ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret, %struct.Mat6*, %struct.Mat6*)
+
+declare double @_ZN13HingeNodeSpecILi1EE8kineticEEv(%"struct.HingeNodeSpec<1>"*)
+
+declare double @_ZN13HingeNodeSpecILi3EE8kineticEEv(%"struct.HingeNodeSpec<3>"*)
+
+declare double @_ZN13HingeNodeSpecILi2EE8kineticEEv(%"struct.HingeNodeSpec<2>"*)
+
+declare double @_ZN13HingeNodeSpecILi6EE8kineticEEv(%"struct.HingeNodeSpec<6>"*)
+
+declare double @_ZN13HingeNodeSpecILi5EE8kineticEEv(%"struct.HingeNodeSpec<5>"*)
+
+declare void @_ZmlIdLi6ELi5ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix<double,5,6,0,0>"*, %"struct.FixedMatrix<double,5,6,0,0>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES6_(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES6_(%"struct.HingeNodeSpec<5>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES6_(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_Z14orthoTransformIdLi3ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix<double,3,3,0,0>"*, %"struct.FixedMatrix<double,3,6,0,0>"*)
+
+declare void @_ZmlIdLi6ELi1ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix<double,1,6,0,0>"*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZmlIdLi6ELi5ELi5EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix<double,5,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,5,6,0,0>"*, %"struct.FixedMatrix<double,5,5,0,0>"*)
+
+declare void @_Z14orthoTransformIdLi5ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix<double,5,5,0,0>"*, %"struct.FixedMatrix<double,5,6,0,0>"*)
+
+declare void @_Z14orthoTransformIdLi2ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix<double,2,2,0,0>"*, %"struct.FixedMatrix<double,2,6,0,0>"*)
+
+declare void @_ZmlIdLi1ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix<double,1,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,1,6,0,0>"*, %struct.Mat6*)
+
+declare void @_ZmlIdLi5ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix<double,5,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,5,6,0,0>"*, %struct.Mat6*)
+
+declare void @_Z14orthoTransformIdLi6ELi5EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix<double,5,5,0,0>"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix<double,5,6,0,0>"*)
+
+declare void @_ZmlIdLi2ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix<double,2,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,2,6,0,0>"*, %struct.Mat6*)
+
+declare void @_Z14orthoTransformIdLi6ELi2EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix<double,2,2,0,0>"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix<double,2,6,0,0>"*)
+
+declare void @_ZmlIdLi3ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix<double,3,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,3,6,0,0>"*, %struct.Mat6*)
+
+declare void @_Z14orthoTransformIdLi6ELi3EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix<double,3,3,0,0>"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix<double,3,6,0,0>"*)
+
+declare void @_ZNSt8ios_base4InitC1Ev(%"struct.CDS::DefaultAlloc"*)
+
+declare i32 @__cxa_atexit(void (i8*)*, i8*, i8*) nounwind
+
+declare void @__tcf_0(i8* nocapture)
+
+declare void @_ZNSt8ios_base4InitD1Ev(%"struct.CDS::DefaultAlloc"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsRSoRK9HingeNode(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %struct.HingeNode*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsRSoPK7IVMAtom(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %struct.IVMAtom*)
+
+declare void @_ZN9HingeNode8addChildEPS_(%struct.HingeNode*, %struct.HingeNode*)
+
+declare void @_ZN7CDSListIP9HingeNodeE6appendES1_(%"struct.CDSList<HingeNode*>"*, %struct.HingeNode*)
+
+declare void @_ZN9HingeNode4getHEv(%struct.RMat* noalias sret, %struct.HingeNode*)
+
+declare i8* @__cxa_allocate_exception(i32) nounwind
+
+declare void @__cxa_throw(i8*, i8*, void (i8*)*) noreturn
+
+declare void @_ZN9HingeNode16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HingeNode*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN9HingeNode9calcAccelEv(%struct.HingeNode*)
+
+declare void @_ZN9HingeNode8getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HingeNode*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN9HingeNode6getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HingeNode*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN9HingeNode6getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HingeNode*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN9HingeNode5printEi(%struct.HingeNode*, i32)
+
+declare void @_ZN9HingeNode18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES4_(%struct.HingeNode*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN9HingeNode14setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%struct.HingeNode*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZN9HingeNode6setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HingeNode*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN9HingeNode9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%struct.HingeNode*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN9HingeNode13propagateSVelERK11FixedVectorIdLi6ELi0EE(%struct.HingeNode*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZN9HingeNode18prepareVelInternalEv(%struct.HingeNode*)
+
+declare void @_ZN9HingeNode17calcInternalForceEv(%struct.HingeNode*)
+
+declare void @_ZN9HingeNode5calcYEv(%struct.HingeNode*)
+
+declare void @_ZN9HingeNode9calcPandZEv(%struct.HingeNode*)
+
+declare void @_ZN9HingeNode5calcZEv(%struct.HingeNode*)
+
+declare void @_ZN9HingeNode5calcPEv(%struct.HingeNode*)
+
+declare double* @_ZNK9HingeNode4massEv(%struct.HingeNode*)
+
+declare %struct.Vec3* @_ZNK9HingeNode5posCMEv(%struct.HingeNode*)
+
+declare i8* @_Znam(i32)
+
+declare void @_ZN7CDSListIP9HingeNodeEC1Eii(%"struct.CDSList<HingeNode*>"*, i32, i32)
+
+declare i8* @_Znwm(i32)
+
+declare i8* @llvm.eh.exception() nounwind
+
+declare i32 @llvm.eh.selector.i32(i8*, i8*, ...) nounwind
+
+declare i32 @llvm.eh.typeid.for.i32(i8*) nounwind
+
+declare void @_ZdlPv(i8*) nounwind
+
+declare i32 @__gxx_personality_v0(...)
+
+declare void @_Unwind_Resume_or_Rethrow(i8*)
+
+declare void @_ZN7CDSListIP7IVMAtomEC1Eii(%struct.AtomList*, i32, i32)
+
+declare void @_ZN13CDSVectorBaseIdN3CDS12DefaultAllocEE8splitRepEv(%"struct.CDSVectorBase<double,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeTorsion16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTorsion*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE8getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE6getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE6getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeRotate316getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate3*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE8getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE6getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE6getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeRotate216getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate2*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeRotate28getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate2*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeRotate26getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate2*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeRotate26getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate2*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeRotate38getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate3*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeRotate36getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate3*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeRotate36getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate3*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE8getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE6getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE6getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN21HNodeTranslateRotate316getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate3*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN21HNodeTranslateRotate38getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate3*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN21HNodeTranslateRotate36getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate3*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN21HNodeTranslateRotate36getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate3*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<6>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE8getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<6>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE6getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<6>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE6getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<6>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN21HNodeTranslateRotate216getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate2*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN21HNodeTranslateRotate28getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate2*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN21HNodeTranslateRotate26getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate2*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN21HNodeTranslateRotate26getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate2*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE16getInternalForceER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<5>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE8getAccelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<5>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE6getVelER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<5>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE6getPosER9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<5>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13CDSVectorBaseI4Vec3N3CDS12DefaultAllocEE8splitRepEv(%"struct.CDSVectorBase<Vec3,CDS::DefaultAlloc>"*)
+
+declare void @_ZN7CDSListIP7IVMAtomE8splitRepEv(%struct.AtomList*)
+
+declare void @_ZN7CDSListIP9HingeNodeE8splitRepEv(%"struct.CDSList<HingeNode*>"*)
+
+declare void @_ZdaPv(i8*) nounwind
+
+declare void @_ZSt9terminatev() noreturn nounwind
+
+declare void @_ZN9HingeNodeC2EPK3IVMP7IVMAtomPKS3_PS_(%struct.HingeNode*, %struct.IVM*, %struct.IVMAtom*, %struct.IVMAtom*, %struct.HingeNode*)
+
+declare void @_ZN9HingeNodeD1Ev(%struct.HingeNode*)
+
+declare void @_ZN9HingeNodeD0Ev(%struct.HingeNode*)
+
+declare void @_ZN7CDSListIP7IVMAtomE6appendES1_(%struct.AtomList*, %struct.IVMAtom*)
+
+declare void @_ZN9HingeNodeC1EPK3IVMP7IVMAtomPKS3_PS_(%struct.HingeNode*, %struct.IVM*, %struct.IVMAtom*, %struct.IVMAtom*, %struct.HingeNode*)
+
+declare void @_ZN9HingeNodeD2Ev(%struct.HingeNode*)
+
+declare void @_ZN11HNodeOriginD0Ev(%struct.HNodeOrigin*)
+
+declare void @_ZN11HNodeOriginD1Ev(%struct.HNodeOrigin*)
+
+declare void @_ZN13HingeNodeSpecILi1EED0Ev(%"struct.HingeNodeSpec<1>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EED1Ev(%"struct.HingeNodeSpec<1>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE5calcPEv(%"struct.HingeNodeSpec<1>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE5calcZEv(%"struct.HingeNodeSpec<1>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE5calcYEv(%"struct.HingeNodeSpec<1>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE17calcInternalForceEv(%"struct.HingeNodeSpec<1>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE18prepareVelInternalEv(%"struct.HingeNodeSpec<1>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE13propagateSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<1>"*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare double @_ZN13HingeNodeSpecILi1EE8approxKEEv(%"struct.HingeNodeSpec<1>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE6setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE14setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<1>"*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE5printEi(%"struct.HingeNodeSpec<1>"*, i32)
+
+declare void @_ZN13HingeNodeSpecILi1EE9calcAccelEv(%"struct.HingeNodeSpec<1>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<1>"*)
+
+declare void @__cxa_pure_virtual() nounwind
+
+declare void @_ZN13HingeNodeSpecILi3EED0Ev(%"struct.HingeNodeSpec<3>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EED1Ev(%"struct.HingeNodeSpec<3>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE5calcPEv(%"struct.HingeNodeSpec<3>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE5calcZEv(%"struct.HingeNodeSpec<3>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE5calcYEv(%"struct.HingeNodeSpec<3>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE17calcInternalForceEv(%"struct.HingeNodeSpec<3>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE18prepareVelInternalEv(%"struct.HingeNodeSpec<3>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE13propagateSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<3>"*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare double @_ZN13HingeNodeSpecILi3EE8approxKEEv(%"struct.HingeNodeSpec<3>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE6setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE14setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<3>"*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE5printEi(%"struct.HingeNodeSpec<3>"*, i32)
+
+declare void @_ZN13HingeNodeSpecILi3EE9calcAccelEv(%"struct.HingeNodeSpec<3>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<3>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EED0Ev(%"struct.HingeNodeSpec<2>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EED1Ev(%"struct.HingeNodeSpec<2>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE5calcPEv(%"struct.HingeNodeSpec<2>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE5calcZEv(%"struct.HingeNodeSpec<2>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE5calcYEv(%"struct.HingeNodeSpec<2>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE17calcInternalForceEv(%"struct.HingeNodeSpec<2>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE18prepareVelInternalEv(%"struct.HingeNodeSpec<2>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE13propagateSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<2>"*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare double @_ZN13HingeNodeSpecILi2EE8approxKEEv(%"struct.HingeNodeSpec<2>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE6setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE14setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<2>"*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE5printEi(%"struct.HingeNodeSpec<2>"*, i32)
+
+declare void @_ZN13HingeNodeSpecILi2EE9calcAccelEv(%"struct.HingeNodeSpec<2>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<2>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EED0Ev(%"struct.HingeNodeSpec<6>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EED1Ev(%"struct.HingeNodeSpec<6>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE5calcPEv(%"struct.HingeNodeSpec<6>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE5calcZEv(%"struct.HingeNodeSpec<6>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE5calcYEv(%"struct.HingeNodeSpec<6>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE17calcInternalForceEv(%"struct.HingeNodeSpec<6>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE18prepareVelInternalEv(%"struct.HingeNodeSpec<6>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE13propagateSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<6>"*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare double @_ZN13HingeNodeSpecILi6EE8approxKEEv(%"struct.HingeNodeSpec<6>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE6setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<6>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE14setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<6>"*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE5printEi(%"struct.HingeNodeSpec<6>"*, i32)
+
+declare void @_ZN13HingeNodeSpecILi6EE9calcAccelEv(%"struct.HingeNodeSpec<6>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<6>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EED0Ev(%"struct.HingeNodeSpec<5>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EED1Ev(%"struct.HingeNodeSpec<5>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE5calcPEv(%"struct.HingeNodeSpec<5>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE5calcZEv(%"struct.HingeNodeSpec<5>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE5calcYEv(%"struct.HingeNodeSpec<5>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE17calcInternalForceEv(%"struct.HingeNodeSpec<5>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE18prepareVelInternalEv(%"struct.HingeNodeSpec<5>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE13propagateSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<5>"*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare double @_ZN13HingeNodeSpecILi5EE8approxKEEv(%"struct.HingeNodeSpec<5>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE6setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%"struct.HingeNodeSpec<5>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE14setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%"struct.HingeNodeSpec<5>"*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE5printEi(%"struct.HingeNodeSpec<5>"*, i32)
+
+declare void @_ZN13HingeNodeSpecILi5EE9calcAccelEv(%"struct.HingeNodeSpec<5>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<5>"*)
+
+declare void @_ZN12HNodeTorsion7calcRotEv(%struct.HNodeTorsion*)
+
+declare double @sin(double) nounwind readnone
+
+declare double @cos(double) nounwind readnone
+
+declare void @_ZN12HNodeRotate37calcRotEv(%struct.HNodeRotate3*)
+
+declare void @_ZN21HNodeTranslateRotate37calcRotEv(%struct.HNodeTranslateRotate3*)
+
+declare void @_ZN9HingeNodeC2ERKS_(%struct.HingeNode*, %struct.HingeNode*)
+
+declare void @_ZN7CDSListIP9HingeNodeEC1ERKS2_(%"struct.CDSList<HingeNode*>"*, %"struct.CDSList<HingeNode*>"*)
+
+declare void @_ZN7CDSListIP7IVMAtomEC1ERKS2_(%struct.AtomList*, %struct.AtomList*)
+
+declare void @_ZN11HNodeOriginC2EPK9HingeNode(%struct.HNodeOrigin*, %struct.HingeNode*)
+
+declare void @_ZN13HingeNodeSpecILi1EEC2EPK9HingeNodeRi(%"struct.HingeNodeSpec<1>"*, %struct.HingeNode*, i32*)
+
+declare void @_ZN13HingeNodeSpecILi3EEC2EPK9HingeNodeRi(%"struct.HingeNodeSpec<3>"*, %struct.HingeNode*, i32*)
+
+declare void @_ZN13HingeNodeSpecILi2EEC2EPK9HingeNodeRi(%"struct.HingeNodeSpec<2>"*, %struct.HingeNode*, i32*)
+
+declare void @_ZN13HingeNodeSpecILi6EEC2EPK9HingeNodeRi(%"struct.HingeNodeSpec<6>"*, %struct.HingeNode*, i32*)
+
+declare void @_ZN13HingeNodeSpecILi5EEC2EPK9HingeNodeRi(%"struct.HingeNodeSpec<5>"*, %struct.HingeNode*, i32*)
+
+declare void @_ZplI4Vec3K11FixedVectorIdLi6ELi0EEET_RK9SubVectorIT0_ERKS4_(%struct.Vec3* noalias sret, %"struct.SubVector<FixedVector<double, 6, 0> >"*, %struct.Vec3*)
+
+declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi1ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix<double,1,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZN12HNodeRotate314setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%struct.HNodeRotate3*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZN12HNodeRotate214setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%struct.HNodeRotate2*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZN21HNodeTranslateRotate314setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%struct.HNodeTranslateRotate3*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZN21HNodeTranslateRotate214setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%struct.HNodeTranslateRotate2*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE9calcPropsEv(%"struct.HingeNodeSpec<1>"*)
+
+declare zeroext i8 @_ZNK3IVM12minimizationEv(%struct.IVM*)
+
+declare void @_Z8blockVecIdLi3ELi3EE11FixedVectorIT_XplT0_T1_ELi0EERKS0_IS1_XT0_ELi0EERKS0_IS1_XT1_ELi0EE(%"struct.FixedMatrix<double,1,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,1,3,0,0>"*, %"struct.FixedMatrix<double,1,3,0,0>"*)
+
+declare void @_ZN12HNodeTorsion11toCartesianEv(%struct.HNodeTorsion*)
+
+declare void @_ZN13HingeNodeSpecILi1EE18calcCartesianForceEv(%"struct.HingeNodeSpec<1>"*)
+
+declare void @_ZN13HingeNodeSpecILi3EE18calcCartesianForceEv(%"struct.HingeNodeSpec<3>"*)
+
+declare void @_ZN13HingeNodeSpecILi2EE18calcCartesianForceEv(%"struct.HingeNodeSpec<2>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE18calcCartesianForceEv(%"struct.HingeNodeSpec<6>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE18calcCartesianForceEv(%"struct.HingeNodeSpec<5>"*)
+
+declare void @_ZN12HNodeTorsion5calcHEv(%struct.HNodeTorsion*)
+
+declare void @_Z10blockMat12IdLi1ELi3ELi3EE11FixedMatrixIT_XT0_EXplT1_T2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT2_ELi0ELi0EE(%"struct.FixedMatrix<double,1,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,1,3,0,0>"*, %"struct.FixedMatrix<double,1,3,0,0>"*)
+
+declare void @_ZN13CDSMatrixBaseIdEC2I11FixedMatrixIdLi1ELi6ELi0ELi0EEEERKT_(%"struct.CDSMatrixBase<double>"*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi1ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix<double,1,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St13_Setprecision(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, i32)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi6EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedMatrixBase<double,1,6>"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, i8 signext)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi3EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedMatrixBase<double,1,3>"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi1EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedMatrixBase<double,1,1>"*)
+
+declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi1ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix<double,1,3,0,0>"* noalias sret, %"struct.FixedMatrix<double,1,6,0,0>"*, i32, i32, i32)
+
+declare %"struct.FixedMatrixBase<double,6,6>"* @_ZN15FixedMatrixBaseIdLi6ELi6EEpLERKS0_(%"struct.FixedMatrixBase<double,6,6>"*, %"struct.FixedMatrixBase<double,6,6>"*)
+
+declare void @_ZN13HingeNodeSpecILi6EE9calcPropsEv(%"struct.HingeNodeSpec<6>"*)
+
+declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%struct.Mat6* noalias sret, %struct.Mat6*)
+
+declare void @_ZN21HNodeTranslateRotate311toCartesianEv(%struct.HNodeTranslateRotate3*)
+
+define linkonce void @_ZN21HNodeTranslateRotate36setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate3* %this, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"* %velv) {
+entry:
+ %0 = add i32 0, -1 ; <i32> [#uses=1]
+ %1 = getelementptr double* null, i32 %0 ; <double*> [#uses=1]
+ %2 = load double* %1, align 8 ; <double> [#uses=1]
+ %3 = load double* null, align 8 ; <double> [#uses=2]
+ %4 = load double* null, align 8 ; <double> [#uses=2]
+ %5 = load double* null, align 8 ; <double> [#uses=3]
+ %6 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 0 ; <double*> [#uses=0]
+ %7 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 1 ; <double*> [#uses=0]
+ %8 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 2 ; <double*> [#uses=0]
+ %9 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 3 ; <double*> [#uses=0]
+ %10 = load double* null, align 8 ; <double> [#uses=2]
+ %11 = fsub double -0.000000e+00, %10 ; <double> [#uses=1]
+ %12 = load double* null, align 8 ; <double> [#uses=2]
+ %13 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 1, i32 0, i32 0, i32 0, i32 3 ; <double*> [#uses=1]
+ %14 = load double* %13, align 8 ; <double> [#uses=2]
+ %15 = fsub double -0.000000e+00, %14 ; <double> [#uses=1]
+ %16 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 1, i32 0, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ %17 = load double* %16, align 8 ; <double> [#uses=2]
+ %18 = fsub double -0.000000e+00, %17 ; <double> [#uses=1]
+ %19 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 0 ; <double*> [#uses=0]
+ %20 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 3 ; <double*> [#uses=0]
+ %21 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 6 ; <double*> [#uses=0]
+ %22 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 9 ; <double*> [#uses=0]
+ %23 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 1 ; <double*> [#uses=0]
+ %24 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 4 ; <double*> [#uses=0]
+ %25 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 7 ; <double*> [#uses=0]
+ %26 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 10 ; <double*> [#uses=0]
+ %27 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 2 ; <double*> [#uses=0]
+ %28 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 5 ; <double*> [#uses=0]
+ %29 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 8 ; <double*> [#uses=0]
+ %30 = getelementptr %"struct.FixedMatrix<double,2,6,0,0>"* null, i32 0, i32 0, i32 0, i32 11 ; <double*> [#uses=0]
+ %31 = getelementptr %"struct.FixedMatrix<double,1,3,0,0>"* null, i32 0, i32 0, i32 0, i32 0 ; <double*> [#uses=0]
+ %32 = getelementptr %"struct.FixedMatrix<double,1,3,0,0>"* null, i32 0, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ %33 = getelementptr %"struct.FixedMatrix<double,1,3,0,0>"* null, i32 0, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ %34 = fmul double %17, %5 ; <double> [#uses=1]
+ %35 = fadd double 0.000000e+00, %34 ; <double> [#uses=1]
+ %36 = fadd double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ %37 = fmul double %14, %3 ; <double> [#uses=1]
+ %38 = fadd double %36, %37 ; <double> [#uses=1]
+ %39 = fmul double %12, %4 ; <double> [#uses=1]
+ %40 = fadd double %38, %39 ; <double> [#uses=1]
+ %41 = fmul double %5, %11 ; <double> [#uses=1]
+ %42 = fadd double %40, %41 ; <double> [#uses=2]
+ store double %42, double* %32, align 8
+ %43 = fmul double %2, %15 ; <double> [#uses=1]
+ %44 = fadd double %43, 0.000000e+00 ; <double> [#uses=1]
+ %45 = fmul double %3, %18 ; <double> [#uses=1]
+ %46 = fadd double %44, %45 ; <double> [#uses=1]
+ %47 = fmul double %10, %4 ; <double> [#uses=1]
+ %48 = fadd double %46, %47 ; <double> [#uses=1]
+ %49 = fmul double %12, %5 ; <double> [#uses=1]
+ %50 = fadd double %48, %49 ; <double> [#uses=2]
+ store double %50, double* %33, align 8
+ %51 = fmul double %35, 2.000000e+00 ; <double> [#uses=1]
+ %52 = fmul double %42, 2.000000e+00 ; <double> [#uses=1]
+ %53 = fmul double %50, 2.000000e+00 ; <double> [#uses=1]
+ %54 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 0, i32 10, i32 0, i32 0, i32 0 ; <double*> [#uses=1]
+ store double %51, double* %54, align 8
+ %55 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 0, i32 10, i32 0, i32 0, i32 1 ; <double*> [#uses=1]
+ store double %52, double* %55, align 8
+ %56 = getelementptr %struct.HNodeTranslateRotate3* %this, i32 0, i32 0, i32 10, i32 0, i32 0, i32 2 ; <double*> [#uses=1]
+ store double %53, double* %56, align 8
+ %57 = add i32 0, 4 ; <i32> [#uses=1]
+ %58 = getelementptr %"struct.SubVector<CDSVector<double, 1, CDS::DefaultAlloc> >"* null, i32 0, i32 0 ; <%"struct.CDSVector<double,0,CDS::DefaultAlloc>"**> [#uses=1]
+ store %"struct.CDSVector<double,0,CDS::DefaultAlloc>"* %velv, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"** %58, align 8
+ %59 = getelementptr %"struct.SubVector<CDSVector<double, 1, CDS::DefaultAlloc> >"* null, i32 0, i32 1 ; <i32*> [#uses=1]
+ store i32 %57, i32* %59, align 4
+ %60 = getelementptr %"struct.SubVector<CDSVector<double, 1, CDS::DefaultAlloc> >"* null, i32 0, i32 2 ; <i32*> [#uses=1]
+ store i32 3, i32* %60, align 8
+ unreachable
+}
+
+declare void @_ZmlRK11FixedMatrixIdLi6ELi6ELi0ELi0EERK18PhiMatrixTranspose(%struct.Mat6* noalias sret, %struct.Mat6*, %struct.PhiMatrixTranspose*)
+
+declare void @_ZmlI4Mat3K11FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS4_(%struct.Mat3* noalias sret, %"struct.SubMatrix<FixedMatrix<double, 6, 6, 0, 0> >"*, %struct.Mat3*)
+
+declare void @_ZmiI4Mat3K11FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS4_(%struct.Mat3* noalias sret, %"struct.SubMatrix<FixedMatrix<double, 6, 6, 0, 0> >"*, %struct.Mat3*)
+
+declare %"struct.FixedMatrixBase<double,3,3>"* @_ZN15FixedMatrixBaseIdLi3ELi3EEmIERKS0_(%"struct.FixedMatrixBase<double,3,3>"*, %"struct.FixedMatrixBase<double,3,3>"*)
+
+declare void @_ZplI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RKS3_RK9SubMatrixIT0_E(%struct.Mat3* noalias sret, %struct.Mat3*, %"struct.SubMatrix<FixedMatrix<double, 6, 6, 0, 0> >"*)
+
+declare void @_ZN13CDSVectorBaseIdN3CDS12DefaultAllocEED2Ev(%"struct.CDSVectorBase<double,CDS::DefaultAlloc>"*)
+
+declare void @_ZN13HingeNodeSpecILi1EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<1>"*, %struct.Mat6*)
+
+declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi1ELi1ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix<double,1,1,0,0>"* noalias sret, %"struct.FixedMatrix<double,1,1,0,0>"*, %"struct.MatrixTools::InverseResults<FullMatrix<double> >"*)
+
+declare i8* @__cxa_get_exception_ptr(i8*) nounwind
+
+declare i8* @__cxa_begin_catch(i8*) nounwind
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi1ELi1EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedMatrixBase<double,1,1>"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi1ELi6EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedMatrixBase<double,1,6>"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZNSolsEi(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, i32)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIcERSoS0_RK9CDSStringIT_E(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %struct.String*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZNSolsEPFRSoS_E(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.std::basic_ostream<char,std::char_traits<char> >"* (%"struct.std::basic_ostream<char,std::char_traits<char> >"*)*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_(%"struct.std::basic_ostream<char,std::char_traits<char> >"*)
+
+declare void @__cxa_end_catch()
+
+declare void @_ZmlI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RKS3_RK9SubMatrixIT0_E(%struct.Mat3* noalias sret, %struct.Mat3*, %"struct.SubMatrix<FixedMatrix<double, 6, 6, 0, 0> >"*)
+
+declare void @_ZmlI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS3_(%struct.Mat3* noalias sret, %"struct.SubMatrix<FixedMatrix<double, 6, 6, 0, 0> >"*, %struct.Mat3*)
+
+declare void @_ZmiI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS3_(%struct.Mat3* noalias sret, %"struct.SubMatrix<FixedMatrix<double, 6, 6, 0, 0> >"*, %struct.Mat3*)
+
+declare %"struct.FixedMatrixBase<double,6,6>"* @_ZN15FixedMatrixBaseIdLi6ELi6EEmIERKS0_(%"struct.FixedMatrixBase<double,6,6>"*, %"struct.FixedMatrixBase<double,6,6>"*)
+
+declare void @_ZN13CDSVectorBaseI4Vec3N3CDS12DefaultAllocEEC2EiS2_(%"struct.CDSVectorBase<Vec3,CDS::DefaultAlloc>"*, i32, %"struct.CDS::DefaultAlloc"* byval align 4)
+
+declare void @_ZN13CDSVectorBaseI4Vec3N3CDS12DefaultAllocEED2Ev(%"struct.CDSVectorBase<Vec3,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeTorsionD0Ev(%struct.HNodeTorsion*)
+
+declare void @_ZN12HNodeTorsionD1Ev(%struct.HNodeTorsion*)
+
+declare void @_ZN12HNodeRotate3D0Ev(%struct.HNodeRotate3*)
+
+declare void @_ZN12HNodeRotate3D1Ev(%struct.HNodeRotate3*)
+
+declare void @_ZN12HNodeRotate36setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate3*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeRotate318enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES4_(%struct.HNodeRotate3*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeRotate35printEi(%struct.HNodeRotate3*, i32)
+
+declare void @_ZN12HNodeRotate35calcHEv(%struct.HNodeRotate3*)
+
+declare void @_ZN12HNodeRotate311toCartesianEv(%struct.HNodeRotate3*)
+
+declare void @_ZN12HNodeRotate2D0Ev(%struct.HNodeRotate2*)
+
+declare void @_ZN12HNodeRotate2D1Ev(%struct.HNodeRotate2*)
+
+declare void @_ZN12HNodeRotate26setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeRotate2*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeRotate218enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES4_(%struct.HNodeRotate2*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN12HNodeRotate25printEi(%struct.HNodeRotate2*, i32)
+
+declare void @_ZN12HNodeRotate25calcHEv(%struct.HNodeRotate2*)
+
+declare void @_ZN12HNodeRotate211toCartesianEv(%struct.HNodeRotate2*)
+
+declare void @_ZN21HNodeTranslateRotate3D0Ev(%struct.HNodeTranslateRotate3*)
+
+declare void @_ZN21HNodeTranslateRotate3D1Ev(%struct.HNodeTranslateRotate3*)
+
+declare void @_ZN21HNodeTranslateRotate318enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES4_(%struct.HNodeTranslateRotate3*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN21HNodeTranslateRotate35printEi(%struct.HNodeTranslateRotate3*, i32)
+
+declare void @_ZN21HNodeTranslateRotate35calcHEv(%struct.HNodeTranslateRotate3*)
+
+declare void @_ZN21HNodeTranslateRotate2D0Ev(%struct.HNodeTranslateRotate2*)
+
+declare void @_ZN21HNodeTranslateRotate2D1Ev(%struct.HNodeTranslateRotate2*)
+
+declare void @_ZN21HNodeTranslateRotate26setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate2*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN21HNodeTranslateRotate218enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES4_(%struct.HNodeTranslateRotate2*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"*)
+
+declare void @_ZN21HNodeTranslateRotate25printEi(%struct.HNodeTranslateRotate2*, i32)
+
+declare void @_ZN21HNodeTranslateRotate25calcHEv(%struct.HNodeTranslateRotate2*)
+
+declare void @_ZN21HNodeTranslateRotate211toCartesianEv(%struct.HNodeTranslateRotate2*)
+
+declare void @_ZN14HNodeTranslateC2EPK9HingeNodeP7IVMAtomRi(%struct.HNodeTranslate*, %struct.HingeNode*, %struct.IVMAtom*, i32*)
+
+declare void @_ZN14HNodeTranslateD1Ev(%struct.HNodeTranslate*)
+
+declare void @_ZN14HNodeTranslateD0Ev(%struct.HNodeTranslate*)
+
+declare void @_ZN14HNodeTranslate5calcHEv(%struct.HNodeTranslate*)
+
+declare void @_ZN14HNodeTranslate11toCartesianEv(%struct.HNodeTranslate*)
+
+declare void @_ZN12HNodeRotate3C2EPK9HingeNodeP7IVMAtomRib(%struct.HNodeRotate3*, %struct.HingeNode*, %struct.IVMAtom*, i32*, i8 zeroext)
+
+declare void @_ZN8AtomTree6findCMEPK9HingeNode(%struct.Vec3* noalias sret, %struct.HingeNode*)
+
+declare %struct.IVMAtom** @_ZN7CDSListIP7IVMAtomE7prependERKS1_(%struct.AtomList*, %struct.IVMAtom**)
+
+declare %"struct.CDSVectorBase<Vec3,CDS::DefaultAlloc>"* @_ZN13CDSVectorBaseI4Vec3N3CDS12DefaultAllocEE6resizeEi(%"struct.CDSVectorBase<Vec3,CDS::DefaultAlloc>"*, i32)
+
+declare void @_ZN12HNodeRotate2C2EPK9HingeNodeRK4Vec3Ri(%struct.HNodeRotate2*, %struct.HingeNode*, %struct.Vec3*, i32*)
+
+declare void @_ZN21HNodeTranslateRotate3C2EPK9HingeNodeP7IVMAtomRib(%struct.HNodeTranslateRotate3*, %struct.HingeNode*, %struct.IVMAtom*, i32*, i8 zeroext)
+
+declare void @_ZN13HingeNodeSpecILi3EE9calcPropsEv(%"struct.HingeNodeSpec<3>"*)
+
+declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi3ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix<double,3,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,3,6,0,0>"*)
+
+declare void @_ZN11MatrixTools9transposeI4Mat3EENT_13TransposeTypeERKS2_(%struct.Mat3* noalias sret, %struct.Mat3*)
+
+declare void @_Z10blockMat12IdLi3ELi3ELi3EE11FixedMatrixIT_XT0_EXplT1_T2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT2_ELi0ELi0EE(%"struct.FixedMatrix<double,3,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,3,3,0,0>"*, %"struct.FixedMatrix<double,3,3,0,0>"*)
+
+declare void @_ZN13CDSMatrixBaseIdEC2I11FixedMatrixIdLi3ELi6ELi0ELi0EEEERKT_(%"struct.CDSMatrixBase<double>"*, %"struct.FixedMatrix<double,3,6,0,0>"*)
+
+declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi3ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix<double,3,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,3,6,0,0>"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi4EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedMatrixBase<double,2,2>"*)
+
+declare double @_Z4normIdLi4EET_RK11FixedVectorIS0_XT0_ELi0EE(%"struct.FixedMatrix<double,2,2,0,0>"*)
+
+declare %"struct.FixedMatrixBase<double,2,2>"* @_ZN15FixedVectorBaseIdLi4EEdVERKd(%"struct.FixedMatrixBase<double,2,2>"*, double*)
+
+declare %"struct.FixedMatrixBase<double,2,2>"* @_ZN15FixedVectorBaseIdLi4EEmIERKS0_(%"struct.FixedMatrixBase<double,2,2>"*, %"struct.FixedMatrixBase<double,2,2>"*)
+
+declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi3ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix<double,1,3,0,0>"* noalias sret, %"struct.FixedMatrix<double,3,6,0,0>"*, i32, i32, i32)
+
+declare void @_ZN13HingeNodeSpecILi3EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<3>"*, %struct.Mat6*)
+
+declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi3ELi3ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix<double,3,3,0,0>"* noalias sret, %"struct.FixedMatrix<double,3,3,0,0>"*, %"struct.MatrixTools::InverseResults<FullMatrix<double> >"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi3ELi3EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedMatrixBase<double,3,3>"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi3ELi6EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedMatrixBase<double,3,6>"*)
+
+declare void @_Z7unitVecRK4Vec3(%struct.Vec3* noalias sret, %struct.Vec3*)
+
+declare double @_Z4normIdLi3EET_RK11FixedVectorIS0_XT0_ELi0EE(%"struct.FixedMatrix<double,1,3,0,0>"*)
+
+declare void @_ZN12HNodeTorsionC2EPK9HingeNodeRK4Vec3Ri(%struct.HNodeTorsion*, %struct.HingeNode*, %struct.Vec3*, i32*)
+
+declare double @acos(double) nounwind readnone
+
+declare double @atan2(double, double) nounwind readnone
+
+declare void @_ZN21HNodeTranslateRotate2C2EPK9HingeNodeRi(%struct.HNodeTranslateRotate2*, %struct.HingeNode*, i32*)
+
+declare void @_ZN13HingeNodeSpecILi2EE9calcPropsEv(%"struct.HingeNodeSpec<2>"*)
+
+declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi2ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix<double,2,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,2,6,0,0>"*)
+
+declare void @_Z10blockMat21IdLi1ELi3ELi1EE11FixedMatrixIT_XplT0_T2_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT2_EXT1_ELi0ELi0EE(%"struct.FixedMatrix<double,1,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,1,3,0,0>"*, %"struct.FixedMatrix<double,1,3,0,0>"*)
+
+declare void @_Z10blockMat12IdLi2ELi3ELi3EE11FixedMatrixIT_XT0_EXplT1_T2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT2_ELi0ELi0EE(%"struct.FixedMatrix<double,2,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,1,6,0,0>"*, %"struct.FixedMatrix<double,1,6,0,0>"*)
+
+declare void @_ZN13CDSMatrixBaseIdEC2I11FixedMatrixIdLi2ELi6ELi0ELi0EEEERKT_(%"struct.CDSMatrixBase<double>"*, %"struct.FixedMatrix<double,2,6,0,0>"*)
+
+declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi2ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix<double,2,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,2,6,0,0>"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi2EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedVectorBase<double,2>"*)
+
+declare %"struct.FixedMatrixBase<double,1,3>"* @_ZN15FixedVectorBaseIdLi3EEdVERKd(%"struct.FixedMatrixBase<double,1,3>"*, double*)
+
+declare %"struct.FixedMatrixBase<double,1,3>"* @_ZN15FixedVectorBaseIdLi3EEmIERKS0_(%"struct.FixedMatrixBase<double,1,3>"*, %"struct.FixedMatrixBase<double,1,3>"*)
+
+declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi2ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix<double,1,3,0,0>"* noalias sret, %"struct.FixedMatrix<double,2,6,0,0>"*, i32, i32, i32)
+
+declare void @_ZN13HingeNodeSpecILi2EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<2>"*, %struct.Mat6*)
+
+declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi2ELi2ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix<double,2,2,0,0>"* noalias sret, %"struct.FixedMatrix<double,2,2,0,0>"*, %"struct.MatrixTools::InverseResults<FullMatrix<double> >"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi2ELi2EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedMatrixBase<double,2,2>"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi2ELi6EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedMatrixBase<double,2,6>"*)
+
+declare zeroext i8 @_ZNK9CDSStringIcE7matchesEPKcb(%struct.String*, i8*, i8 zeroext)
+
+declare %struct.HingeNode* @_Z9constructP9HingeNodeRKN16InternalDynamics9HingeSpecERi(%struct.HingeNode*, %"struct.InternalDynamics::HingeSpec"*, i32*)
+
+declare void @_ZN9CDSStringIcEC1ERKS0_(%struct.String*, %struct.String*)
+
+declare void @_ZN9CDSStringIcE8downcaseEv(%struct.String*)
+
+declare %struct.String* @_ZN9CDSStringIcEaSEPKc(%struct.String*, i8*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIP7IVMAtomERSoS2_RK7CDSListIT_E(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %struct.AtomList*)
+
+declare i32 @_ZNK7CDSListIP9HingeNodeE8getIndexERKS1_(%"struct.CDSList<HingeNode*>"*, %struct.HingeNode**)
+
+declare void @_ZN13CDSMatrixBaseIdEC2I11FixedMatrixIdLi6ELi6ELi0ELi0EEEERKT_(%"struct.CDSMatrixBase<double>"*, %struct.Mat6*)
+
+declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi6ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix<double,1,3,0,0>"* noalias sret, %struct.Mat6*, i32, i32, i32)
+
+declare void @_ZN13HingeNodeSpecILi6EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<6>"*, %struct.Mat6*)
+
+declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi6ELi6ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%struct.Mat6* noalias sret, %struct.Mat6*, %"struct.MatrixTools::InverseResults<FullMatrix<double> >"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi6ELi6EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedMatrixBase<double,6,6>"*)
+
+declare void @_ZN13HingeNodeSpecILi5EE9calcPropsEv(%"struct.HingeNodeSpec<5>"*)
+
+declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi5ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix<double,5,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,5,6,0,0>"*)
+
+declare void @_ZN13CDSMatrixBaseIdEC2I11FixedMatrixIdLi5ELi6ELi0ELi0EEEERKT_(%"struct.CDSMatrixBase<double>"*, %"struct.FixedMatrix<double,5,6,0,0>"*)
+
+declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi5ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix<double,5,6,0,0>"* noalias sret, %"struct.FixedMatrix<double,5,6,0,0>"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi5EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedVectorBase<double,5>"*)
+
+declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi5ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix<double,1,3,0,0>"* noalias sret, %"struct.FixedMatrix<double,5,6,0,0>"*, i32, i32, i32)
+
+declare void @_ZN13HingeNodeSpecILi5EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<5>"*, %struct.Mat6*)
+
+declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi5ELi5ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix<double,5,5,0,0>"* noalias sret, %"struct.FixedMatrix<double,5,5,0,0>"*, %"struct.MatrixTools::InverseResults<FullMatrix<double> >"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi5ELi5EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedMatrixBase<double,5,5>"*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZlsIdLi5ELi6EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, %"struct.FixedMatrixBase<double,5,6>"*)
+
+declare void @llvm.memset.i64(i8* nocapture, i8, i64, i32) nounwind
diff --git a/test/CodeGen/X86/negative-sin.ll b/test/CodeGen/X86/negative-sin.ll
new file mode 100644
index 0000000..7842eb8
--- /dev/null
+++ b/test/CodeGen/X86/negative-sin.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -enable-unsafe-fp-math -march=x86-64 | \
+; RUN: not egrep {addsd|subsd|xor}
+
+declare double @sin(double %f)
+
+define double @foo(double %e)
+{
+ %f = fsub double 0.0, %e
+ %g = call double @sin(double %f) readonly
+ %h = fsub double 0.0, %g
+ ret double %h
+}
diff --git a/test/CodeGen/X86/negative-stride-fptosi-user.ll b/test/CodeGen/X86/negative-stride-fptosi-user.ll
new file mode 100644
index 0000000..332e0b9
--- /dev/null
+++ b/test/CodeGen/X86/negative-stride-fptosi-user.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86-64 | grep cvtsi2sd
+
+; LSR previously eliminated the sitofp by introducing an induction
+; variable which stepped by a bogus ((double)UINT32_C(-1)). It's theoretically
+; possible to eliminate the sitofp using a proper -1.0 step though; this
+; test should be changed if that is done.
+
+define void @foo(i32 %N) nounwind {
+entry:
+ %0 = icmp slt i32 %N, 0 ; <i1> [#uses=1]
+ br i1 %0, label %bb, label %return
+
+bb: ; preds = %bb, %entry
+ %i.03 = phi i32 [ 0, %entry ], [ %2, %bb ] ; <i32> [#uses=2]
+ %1 = sitofp i32 %i.03 to double ; <double> [#uses=1]
+ tail call void @bar(double %1) nounwind
+ %2 = add nsw i32 %i.03, -1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %2, %N ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
+
+return: ; preds = %bb, %entry
+ ret void
+}
+
+declare void @bar(double)
diff --git a/test/CodeGen/X86/negative-subscript.ll b/test/CodeGen/X86/negative-subscript.ll
new file mode 100644
index 0000000..28f7d6b
--- /dev/null
+++ b/test/CodeGen/X86/negative-subscript.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86
+; rdar://6559995
+
+@a = external global [255 x i8*], align 32
+
+define i32 @main() nounwind {
+entry:
+ store i8* bitcast (i8** getelementptr ([255 x i8*]* @a, i32 0, i32 -2147483624) to i8*), i8** getelementptr ([255 x i8*]* @a, i32 0, i32 16), align 32
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/negative_zero.ll b/test/CodeGen/X86/negative_zero.ll
new file mode 100644
index 0000000..29474c2
--- /dev/null
+++ b/test/CodeGen/X86/negative_zero.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3 | grep fchs
+
+
+define double @T() {
+ ret double -1.0 ;; codegen as fld1/fchs, not as a load from cst pool
+}
diff --git a/test/CodeGen/X86/nobt.ll b/test/CodeGen/X86/nobt.ll
new file mode 100644
index 0000000..35090e3
--- /dev/null
+++ b/test/CodeGen/X86/nobt.ll
@@ -0,0 +1,70 @@
+; RUN: llc < %s -march=x86 | not grep btl
+
+; This tests some cases where BT must not be generated. See also bt.ll.
+; Fixes 20040709-[12].c in gcc testsuite.
+
+define void @test2(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp1 = and i32 %x, 1
+ %tmp2 = urem i32 %tmp1, 15
+ %tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1]
+ %tmp4 = icmp eq i32 %tmp3, %tmp2 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @test3(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp1 = and i32 %x, 1
+ %tmp2 = urem i32 %tmp1, 15
+ %tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1]
+ %tmp4 = icmp eq i32 %tmp2, %tmp3 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @test4(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp1 = and i32 %x, 1
+ %tmp2 = urem i32 %tmp1, 15
+ %tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1]
+ %tmp4 = icmp ne i32 %tmp2, %tmp3 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+define void @test5(i32 %x, i32 %n) nounwind {
+entry:
+ %tmp1 = and i32 %x, 1
+ %tmp2 = urem i32 %tmp1, 15
+ %tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1]
+ %tmp4 = icmp ne i32 %tmp2, %tmp3 ; <i1> [#uses=1]
+ br i1 %tmp4, label %bb, label %UnifiedReturnBlock
+
+bb: ; preds = %entry
+ call void @foo()
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+declare void @foo()
diff --git a/test/CodeGen/X86/nofence.ll b/test/CodeGen/X86/nofence.ll
new file mode 100644
index 0000000..244d2e9
--- /dev/null
+++ b/test/CodeGen/X86/nofence.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep fence
+
+declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1)
+
+define void @test() {
+ call void @llvm.memory.barrier( i1 true, i1 false, i1 false, i1 false, i1 false)
+ call void @llvm.memory.barrier( i1 false, i1 true, i1 false, i1 false, i1 false)
+ call void @llvm.memory.barrier( i1 false, i1 false, i1 true, i1 false, i1 false)
+ call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 false)
+
+ call void @llvm.memory.barrier( i1 true, i1 true, i1 false, i1 false, i1 false)
+ call void @llvm.memory.barrier( i1 true, i1 false, i1 true, i1 false, i1 false)
+ call void @llvm.memory.barrier( i1 true, i1 false, i1 false, i1 true, i1 false)
+ call void @llvm.memory.barrier( i1 false, i1 true, i1 true, i1 false, i1 false)
+ call void @llvm.memory.barrier( i1 false, i1 true, i1 false, i1 true, i1 false)
+ call void @llvm.memory.barrier( i1 false, i1 false, i1 true, i1 true, i1 false)
+
+ call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 false, i1 false)
+ call void @llvm.memory.barrier( i1 true, i1 true, i1 false, i1 true, i1 false)
+ call void @llvm.memory.barrier( i1 true, i1 false, i1 true, i1 true, i1 false)
+ call void @llvm.memory.barrier( i1 false, i1 true, i1 true, i1 true, i1 false)
+
+
+ call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true , i1 false)
+ call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 false , i1 false)
+ ret void
+}
diff --git a/test/CodeGen/X86/nosse-error1.ll b/test/CodeGen/X86/nosse-error1.ll
new file mode 100644
index 0000000..16cbb73
--- /dev/null
+++ b/test/CodeGen/X86/nosse-error1.ll
@@ -0,0 +1,33 @@
+; RUN: llvm-as < %s > %t1
+; RUN: not llc -march=x86-64 -mattr=-sse < %t1 2> %t2
+; RUN: grep "SSE register return with SSE disabled" %t2
+; RUN: llc -march=x86-64 < %t1 | grep xmm
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+@f = external global float ; <float*> [#uses=4]
+@d = external global double ; <double*> [#uses=4]
+
+define void @test() nounwind {
+entry:
+ %0 = load float* @f, align 4 ; <float> [#uses=1]
+ %1 = tail call float @foo1(float %0) nounwind ; <float> [#uses=1]
+ store float %1, float* @f, align 4
+ %2 = load double* @d, align 8 ; <double> [#uses=1]
+ %3 = tail call double @foo2(double %2) nounwind ; <double> [#uses=1]
+ store double %3, double* @d, align 8
+ %4 = load float* @f, align 4 ; <float> [#uses=1]
+ %5 = tail call float @foo3(float %4) nounwind ; <float> [#uses=1]
+ store float %5, float* @f, align 4
+ %6 = load double* @d, align 8 ; <double> [#uses=1]
+ %7 = tail call double @foo4(double %6) nounwind ; <double> [#uses=1]
+ store double %7, double* @d, align 8
+ ret void
+}
+
+declare float @foo1(float)
+
+declare double @foo2(double)
+
+declare float @foo3(float)
+
+declare double @foo4(double)
diff --git a/test/CodeGen/X86/nosse-error2.ll b/test/CodeGen/X86/nosse-error2.ll
new file mode 100644
index 0000000..45a5eaf
--- /dev/null
+++ b/test/CodeGen/X86/nosse-error2.ll
@@ -0,0 +1,33 @@
+; RUN: llvm-as < %s > %t1
+; RUN: not llc -march=x86 -mcpu=i686 -mattr=-sse < %t1 2> %t2
+; RUN: grep "SSE register return with SSE disabled" %t2
+; RUN: llc -march=x86 -mcpu=i686 -mattr=+sse < %t1 | grep xmm
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-unknown-linux-gnu"
+@f = external global float ; <float*> [#uses=4]
+@d = external global double ; <double*> [#uses=4]
+
+define void @test() nounwind {
+entry:
+ %0 = load float* @f, align 4 ; <float> [#uses=1]
+ %1 = tail call inreg float @foo1(float inreg %0) nounwind ; <float> [#uses=1]
+ store float %1, float* @f, align 4
+ %2 = load double* @d, align 8 ; <double> [#uses=1]
+ %3 = tail call inreg double @foo2(double inreg %2) nounwind ; <double> [#uses=1]
+ store double %3, double* @d, align 8
+ %4 = load float* @f, align 4 ; <float> [#uses=1]
+ %5 = tail call inreg float @foo3(float inreg %4) nounwind ; <float> [#uses=1]
+ store float %5, float* @f, align 4
+ %6 = load double* @d, align 8 ; <double> [#uses=1]
+ %7 = tail call inreg double @foo4(double inreg %6) nounwind ; <double> [#uses=1]
+ store double %7, double* @d, align 8
+ ret void
+}
+
+declare inreg float @foo1(float inreg)
+
+declare inreg double @foo2(double inreg)
+
+declare inreg float @foo3(float inreg)
+
+declare inreg double @foo4(double inreg)
diff --git a/test/CodeGen/X86/nosse-varargs.ll b/test/CodeGen/X86/nosse-varargs.ll
new file mode 100644
index 0000000..e6da0ab
--- /dev/null
+++ b/test/CodeGen/X86/nosse-varargs.ll
@@ -0,0 +1,46 @@
+; RUN: llvm-as < %s > %t
+; RUN: llc -march=x86-64 -mattr=-sse < %t | not grep xmm
+; RUN: llc -march=x86-64 < %t | grep xmm
+; PR3403
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+ %struct.__va_list_tag = type { i32, i32, i8*, i8* }
+
+define i32 @foo(float %a, i8* nocapture %fmt, ...) nounwind {
+entry:
+ %ap = alloca [1 x %struct.__va_list_tag], align 8 ; <[1 x %struct.__va_list_tag]*> [#uses=4]
+ %ap12 = bitcast [1 x %struct.__va_list_tag]* %ap to i8* ; <i8*> [#uses=2]
+ call void @llvm.va_start(i8* %ap12)
+ %0 = getelementptr [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0, i32 0 ; <i32*> [#uses=2]
+ %1 = load i32* %0, align 8 ; <i32> [#uses=3]
+ %2 = icmp ult i32 %1, 48 ; <i1> [#uses=1]
+ br i1 %2, label %bb, label %bb3
+
+bb: ; preds = %entry
+ %3 = getelementptr [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0, i32 3 ; <i8**> [#uses=1]
+ %4 = load i8** %3, align 8 ; <i8*> [#uses=1]
+ %5 = inttoptr i32 %1 to i8* ; <i8*> [#uses=1]
+ %6 = ptrtoint i8* %5 to i64 ; <i64> [#uses=1]
+ %ctg2 = getelementptr i8* %4, i64 %6 ; <i8*> [#uses=1]
+ %7 = add i32 %1, 8 ; <i32> [#uses=1]
+ store i32 %7, i32* %0, align 8
+ br label %bb4
+
+bb3: ; preds = %entry
+ %8 = getelementptr [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0, i32 2 ; <i8**> [#uses=2]
+ %9 = load i8** %8, align 8 ; <i8*> [#uses=2]
+ %10 = getelementptr i8* %9, i64 8 ; <i8*> [#uses=1]
+ store i8* %10, i8** %8, align 8
+ br label %bb4
+
+bb4: ; preds = %bb3, %bb
+ %addr.0.0 = phi i8* [ %ctg2, %bb ], [ %9, %bb3 ] ; <i8*> [#uses=1]
+ %11 = bitcast i8* %addr.0.0 to i32* ; <i32*> [#uses=1]
+ %12 = load i32* %11, align 4 ; <i32> [#uses=1]
+ call void @llvm.va_end(i8* %ap12)
+ ret i32 %12
+}
+
+declare void @llvm.va_start(i8*) nounwind
+
+declare void @llvm.va_end(i8*) nounwind
diff --git a/test/CodeGen/X86/object-size.ll b/test/CodeGen/X86/object-size.ll
new file mode 100644
index 0000000..eed3cfc
--- /dev/null
+++ b/test/CodeGen/X86/object-size.ll
@@ -0,0 +1,55 @@
+; RUN: llc -O0 < %s -march=x86-64 | FileCheck %s -check-prefix=X64
+
+; ModuleID = 'ts.c'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-darwin10.0"
+
+@p = common global i8* null, align 8 ; <i8**> [#uses=4]
[email protected] = private constant [3 x i8] c"Hi\00" ; <[3 x i8]*> [#uses=1]
+
+define void @bar() nounwind ssp {
+entry:
+ %tmp = load i8** @p ; <i8*> [#uses=1]
+ %0 = call i64 @llvm.objectsize.i64(i8* %tmp, i1 0) ; <i64> [#uses=1]
+ %cmp = icmp ne i64 %0, -1 ; <i1> [#uses=1]
+; X64: movq $-1, %rax
+; X64: cmpq $-1, %rax
+ br i1 %cmp, label %cond.true, label %cond.false
+
+cond.true: ; preds = %entry
+ %tmp1 = load i8** @p ; <i8*> [#uses=1]
+ %tmp2 = load i8** @p ; <i8*> [#uses=1]
+ %1 = call i64 @llvm.objectsize.i64(i8* %tmp2, i1 1) ; <i64> [#uses=1]
+ %call = call i8* @__strcpy_chk(i8* %tmp1, i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i64 %1) ssp ; <i8*> [#uses=1]
+ br label %cond.end
+
+cond.false: ; preds = %entry
+ %tmp3 = load i8** @p ; <i8*> [#uses=1]
+ %call4 = call i8* @__inline_strcpy_chk(i8* %tmp3, i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0)) ssp ; <i8*> [#uses=1]
+ br label %cond.end
+
+cond.end: ; preds = %cond.false, %cond.true
+ %cond = phi i8* [ %call, %cond.true ], [ %call4, %cond.false ] ; <i8*> [#uses=0]
+ ret void
+}
+
+declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readonly
+
+declare i8* @__strcpy_chk(i8*, i8*, i64) ssp
+
+define internal i8* @__inline_strcpy_chk(i8* %__dest, i8* %__src) nounwind ssp {
+entry:
+ %retval = alloca i8* ; <i8**> [#uses=2]
+ %__dest.addr = alloca i8* ; <i8**> [#uses=3]
+ %__src.addr = alloca i8* ; <i8**> [#uses=2]
+ store i8* %__dest, i8** %__dest.addr
+ store i8* %__src, i8** %__src.addr
+ %tmp = load i8** %__dest.addr ; <i8*> [#uses=1]
+ %tmp1 = load i8** %__src.addr ; <i8*> [#uses=1]
+ %tmp2 = load i8** %__dest.addr ; <i8*> [#uses=1]
+ %0 = call i64 @llvm.objectsize.i64(i8* %tmp2, i1 1) ; <i64> [#uses=1]
+ %call = call i8* @__strcpy_chk(i8* %tmp, i8* %tmp1, i64 %0) ssp ; <i8*> [#uses=1]
+ store i8* %call, i8** %retval
+ %1 = load i8** %retval ; <i8*> [#uses=1]
+ ret i8* %1
+}
diff --git a/test/CodeGen/X86/omit-label.ll b/test/CodeGen/X86/omit-label.ll
new file mode 100644
index 0000000..0ec03eb
--- /dev/null
+++ b/test/CodeGen/X86/omit-label.ll
@@ -0,0 +1,57 @@
+; RUN: llc < %s -asm-verbose=false -mtriple=x86_64-linux-gnu | FileCheck %s
+; PR4126
+; PR4732
+
+; Don't omit these labels' definitions.
+
+; CHECK: bux:
+; CHECK: LBB1_1:
+
+define void @bux(i32 %p_53) nounwind optsize {
+entry:
+ %0 = icmp eq i32 %p_53, 0 ; <i1> [#uses=1]
+ %1 = icmp sgt i32 %p_53, 0 ; <i1> [#uses=1]
+ %or.cond = and i1 %0, %1 ; <i1> [#uses=1]
+ br i1 %or.cond, label %bb.i, label %bb3
+
+bb.i: ; preds = %entry
+ %2 = add i32 %p_53, 1 ; <i32> [#uses=1]
+ %3 = icmp slt i32 %2, 0 ; <i1> [#uses=0]
+ br label %bb3
+
+bb3: ; preds = %bb.i, %entry
+ %4 = tail call i32 (...)* @baz(i32 0) nounwind ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @baz(...)
+
+; Don't omit this label in the assembly output.
+; CHECK: int321:
+; CHECK: LBB2_1
+; CHECK: LBB2_1
+; CHECK: LBB2_1:
+
+define void @int321(i8 signext %p_103, i32 %uint8p_104) nounwind readnone {
+entry:
+ %tobool = icmp eq i8 %p_103, 0 ; <i1> [#uses=1]
+ %cmp.i = icmp sgt i8 %p_103, 0 ; <i1> [#uses=1]
+ %or.cond = and i1 %tobool, %cmp.i ; <i1> [#uses=1]
+ br i1 %or.cond, label %land.end.i, label %for.cond.preheader
+
+land.end.i: ; preds = %entry
+ %conv3.i = sext i8 %p_103 to i32 ; <i32> [#uses=1]
+ %div.i = sdiv i32 1, %conv3.i ; <i32> [#uses=1]
+ %tobool.i = icmp eq i32 %div.i, -2147483647 ; <i1> [#uses=0]
+ br label %for.cond.preheader
+
+for.cond.preheader: ; preds = %land.end.i, %entry
+ %cmp = icmp sgt i8 %p_103, 1 ; <i1> [#uses=1]
+ br i1 %cmp, label %for.end.split, label %for.cond
+
+for.cond: ; preds = %for.cond.preheader, %for.cond
+ br label %for.cond
+
+for.end.split: ; preds = %for.cond.preheader
+ ret void
+}
diff --git a/test/CodeGen/X86/opt-ext-uses.ll b/test/CodeGen/X86/opt-ext-uses.ll
new file mode 100644
index 0000000..fa2aef5
--- /dev/null
+++ b/test/CodeGen/X86/opt-ext-uses.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86 | grep movw | count 1
+
+define i16 @t() signext {
+entry:
+ %tmp180 = load i16* null, align 2 ; <i16> [#uses=3]
+ %tmp180181 = sext i16 %tmp180 to i32 ; <i32> [#uses=1]
+ %tmp182 = add i16 %tmp180, 10
+ %tmp185 = icmp slt i16 %tmp182, 0 ; <i1> [#uses=1]
+ br i1 %tmp185, label %cond_true188, label %cond_next245
+
+cond_true188: ; preds = %entry
+ %tmp195196 = trunc i16 %tmp180 to i8 ; <i8> [#uses=0]
+ ret i16 %tmp180
+
+cond_next245: ; preds = %entry
+ %tmp256 = and i32 %tmp180181, 15 ; <i32> [#uses=0]
+ %tmp3 = trunc i32 %tmp256 to i16
+ ret i16 %tmp3
+}
diff --git a/test/CodeGen/X86/optimize-max-0.ll b/test/CodeGen/X86/optimize-max-0.ll
new file mode 100644
index 0000000..162c7a5
--- /dev/null
+++ b/test/CodeGen/X86/optimize-max-0.ll
@@ -0,0 +1,461 @@
+; RUN: llc < %s -march=x86 | not grep cmov
+
+; LSR should be able to eliminate the max computations by
+; making the loops use slt/ult comparisons instead of ne comparisons.
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9"
+
+define void @foo(i8* %r, i32 %s, i32 %w, i32 %x, i8* %j, i32 %d) nounwind {
+entry:
+ %0 = mul i32 %x, %w ; <i32> [#uses=2]
+ %1 = mul i32 %x, %w ; <i32> [#uses=1]
+ %2 = sdiv i32 %1, 4 ; <i32> [#uses=1]
+ %.sum2 = add i32 %2, %0 ; <i32> [#uses=2]
+ %cond = icmp eq i32 %d, 1 ; <i1> [#uses=1]
+ br i1 %cond, label %bb29, label %bb10.preheader
+
+bb10.preheader: ; preds = %entry
+ %3 = icmp sgt i32 %x, 0 ; <i1> [#uses=1]
+ br i1 %3, label %bb.nph9, label %bb18.loopexit
+
+bb.nph7: ; preds = %bb7.preheader
+ %4 = mul i32 %y.08, %w ; <i32> [#uses=1]
+ %5 = mul i32 %y.08, %s ; <i32> [#uses=1]
+ %6 = add i32 %5, 1 ; <i32> [#uses=1]
+ %tmp8 = icmp sgt i32 1, %w ; <i1> [#uses=1]
+ %smax9 = select i1 %tmp8, i32 1, i32 %w ; <i32> [#uses=1]
+ br label %bb6
+
+bb6: ; preds = %bb7, %bb.nph7
+ %x.06 = phi i32 [ 0, %bb.nph7 ], [ %indvar.next7, %bb7 ] ; <i32> [#uses=3]
+ %7 = add i32 %x.06, %4 ; <i32> [#uses=1]
+ %8 = shl i32 %x.06, 1 ; <i32> [#uses=1]
+ %9 = add i32 %6, %8 ; <i32> [#uses=1]
+ %10 = getelementptr i8* %r, i32 %9 ; <i8*> [#uses=1]
+ %11 = load i8* %10, align 1 ; <i8> [#uses=1]
+ %12 = getelementptr i8* %j, i32 %7 ; <i8*> [#uses=1]
+ store i8 %11, i8* %12, align 1
+ br label %bb7
+
+bb7: ; preds = %bb6
+ %indvar.next7 = add i32 %x.06, 1 ; <i32> [#uses=2]
+ %exitcond10 = icmp ne i32 %indvar.next7, %smax9 ; <i1> [#uses=1]
+ br i1 %exitcond10, label %bb6, label %bb7.bb9_crit_edge
+
+bb7.bb9_crit_edge: ; preds = %bb7
+ br label %bb9
+
+bb9: ; preds = %bb7.preheader, %bb7.bb9_crit_edge
+ br label %bb10
+
+bb10: ; preds = %bb9
+ %indvar.next11 = add i32 %y.08, 1 ; <i32> [#uses=2]
+ %exitcond12 = icmp ne i32 %indvar.next11, %x ; <i1> [#uses=1]
+ br i1 %exitcond12, label %bb7.preheader, label %bb10.bb18.loopexit_crit_edge
+
+bb10.bb18.loopexit_crit_edge: ; preds = %bb10
+ br label %bb10.bb18.loopexit_crit_edge.split
+
+bb10.bb18.loopexit_crit_edge.split: ; preds = %bb.nph9, %bb10.bb18.loopexit_crit_edge
+ br label %bb18.loopexit
+
+bb.nph9: ; preds = %bb10.preheader
+ %13 = icmp sgt i32 %w, 0 ; <i1> [#uses=1]
+ br i1 %13, label %bb.nph9.split, label %bb10.bb18.loopexit_crit_edge.split
+
+bb.nph9.split: ; preds = %bb.nph9
+ br label %bb7.preheader
+
+bb7.preheader: ; preds = %bb.nph9.split, %bb10
+ %y.08 = phi i32 [ 0, %bb.nph9.split ], [ %indvar.next11, %bb10 ] ; <i32> [#uses=3]
+ br i1 true, label %bb.nph7, label %bb9
+
+bb.nph5: ; preds = %bb18.loopexit
+ %14 = sdiv i32 %w, 2 ; <i32> [#uses=1]
+ %15 = icmp slt i32 %w, 2 ; <i1> [#uses=1]
+ %16 = sdiv i32 %x, 2 ; <i32> [#uses=2]
+ br i1 %15, label %bb18.bb20_crit_edge.split, label %bb.nph5.split
+
+bb.nph5.split: ; preds = %bb.nph5
+ %tmp2 = icmp sgt i32 1, %16 ; <i1> [#uses=1]
+ %smax3 = select i1 %tmp2, i32 1, i32 %16 ; <i32> [#uses=1]
+ br label %bb13
+
+bb13: ; preds = %bb18, %bb.nph5.split
+ %y.14 = phi i32 [ 0, %bb.nph5.split ], [ %indvar.next1, %bb18 ] ; <i32> [#uses=4]
+ %17 = mul i32 %14, %y.14 ; <i32> [#uses=2]
+ %18 = shl i32 %y.14, 1 ; <i32> [#uses=1]
+ %19 = srem i32 %y.14, 2 ; <i32> [#uses=1]
+ %20 = add i32 %19, %18 ; <i32> [#uses=1]
+ %21 = mul i32 %20, %s ; <i32> [#uses=2]
+ br i1 true, label %bb.nph3, label %bb17
+
+bb.nph3: ; preds = %bb13
+ %22 = add i32 %17, %0 ; <i32> [#uses=1]
+ %23 = add i32 %17, %.sum2 ; <i32> [#uses=1]
+ %24 = sdiv i32 %w, 2 ; <i32> [#uses=2]
+ %tmp = icmp sgt i32 1, %24 ; <i1> [#uses=1]
+ %smax = select i1 %tmp, i32 1, i32 %24 ; <i32> [#uses=1]
+ br label %bb14
+
+bb14: ; preds = %bb15, %bb.nph3
+ %x.12 = phi i32 [ 0, %bb.nph3 ], [ %indvar.next, %bb15 ] ; <i32> [#uses=5]
+ %25 = shl i32 %x.12, 2 ; <i32> [#uses=1]
+ %26 = add i32 %25, %21 ; <i32> [#uses=1]
+ %27 = getelementptr i8* %r, i32 %26 ; <i8*> [#uses=1]
+ %28 = load i8* %27, align 1 ; <i8> [#uses=1]
+ %.sum = add i32 %22, %x.12 ; <i32> [#uses=1]
+ %29 = getelementptr i8* %j, i32 %.sum ; <i8*> [#uses=1]
+ store i8 %28, i8* %29, align 1
+ %30 = shl i32 %x.12, 2 ; <i32> [#uses=1]
+ %31 = or i32 %30, 2 ; <i32> [#uses=1]
+ %32 = add i32 %31, %21 ; <i32> [#uses=1]
+ %33 = getelementptr i8* %r, i32 %32 ; <i8*> [#uses=1]
+ %34 = load i8* %33, align 1 ; <i8> [#uses=1]
+ %.sum6 = add i32 %23, %x.12 ; <i32> [#uses=1]
+ %35 = getelementptr i8* %j, i32 %.sum6 ; <i8*> [#uses=1]
+ store i8 %34, i8* %35, align 1
+ br label %bb15
+
+bb15: ; preds = %bb14
+ %indvar.next = add i32 %x.12, 1 ; <i32> [#uses=2]
+ %exitcond = icmp ne i32 %indvar.next, %smax ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb14, label %bb15.bb17_crit_edge
+
+bb15.bb17_crit_edge: ; preds = %bb15
+ br label %bb17
+
+bb17: ; preds = %bb15.bb17_crit_edge, %bb13
+ br label %bb18
+
+bb18.loopexit: ; preds = %bb10.bb18.loopexit_crit_edge.split, %bb10.preheader
+ %36 = icmp slt i32 %x, 2 ; <i1> [#uses=1]
+ br i1 %36, label %bb20, label %bb.nph5
+
+bb18: ; preds = %bb17
+ %indvar.next1 = add i32 %y.14, 1 ; <i32> [#uses=2]
+ %exitcond4 = icmp ne i32 %indvar.next1, %smax3 ; <i1> [#uses=1]
+ br i1 %exitcond4, label %bb13, label %bb18.bb20_crit_edge
+
+bb18.bb20_crit_edge: ; preds = %bb18
+ br label %bb18.bb20_crit_edge.split
+
+bb18.bb20_crit_edge.split: ; preds = %bb18.bb20_crit_edge, %bb.nph5
+ br label %bb20
+
+bb20: ; preds = %bb18.bb20_crit_edge.split, %bb18.loopexit
+ switch i32 %d, label %return [
+ i32 3, label %bb22
+ i32 1, label %bb29
+ ]
+
+bb22: ; preds = %bb20
+ %37 = mul i32 %x, %w ; <i32> [#uses=1]
+ %38 = sdiv i32 %37, 4 ; <i32> [#uses=1]
+ %.sum3 = add i32 %38, %.sum2 ; <i32> [#uses=2]
+ %39 = add i32 %x, 15 ; <i32> [#uses=1]
+ %40 = and i32 %39, -16 ; <i32> [#uses=1]
+ %41 = add i32 %w, 15 ; <i32> [#uses=1]
+ %42 = and i32 %41, -16 ; <i32> [#uses=1]
+ %43 = mul i32 %40, %s ; <i32> [#uses=1]
+ %44 = icmp sgt i32 %x, 0 ; <i1> [#uses=1]
+ br i1 %44, label %bb.nph, label %bb26
+
+bb.nph: ; preds = %bb22
+ br label %bb23
+
+bb23: ; preds = %bb24, %bb.nph
+ %y.21 = phi i32 [ 0, %bb.nph ], [ %indvar.next5, %bb24 ] ; <i32> [#uses=3]
+ %45 = mul i32 %y.21, %42 ; <i32> [#uses=1]
+ %.sum1 = add i32 %45, %43 ; <i32> [#uses=1]
+ %46 = getelementptr i8* %r, i32 %.sum1 ; <i8*> [#uses=1]
+ %47 = mul i32 %y.21, %w ; <i32> [#uses=1]
+ %.sum5 = add i32 %47, %.sum3 ; <i32> [#uses=1]
+ %48 = getelementptr i8* %j, i32 %.sum5 ; <i8*> [#uses=1]
+ tail call void @llvm.memcpy.i32(i8* %48, i8* %46, i32 %w, i32 1)
+ br label %bb24
+
+bb24: ; preds = %bb23
+ %indvar.next5 = add i32 %y.21, 1 ; <i32> [#uses=2]
+ %exitcond6 = icmp ne i32 %indvar.next5, %x ; <i1> [#uses=1]
+ br i1 %exitcond6, label %bb23, label %bb24.bb26_crit_edge
+
+bb24.bb26_crit_edge: ; preds = %bb24
+ br label %bb26
+
+bb26: ; preds = %bb24.bb26_crit_edge, %bb22
+ %49 = mul i32 %x, %w ; <i32> [#uses=1]
+ %.sum4 = add i32 %.sum3, %49 ; <i32> [#uses=1]
+ %50 = getelementptr i8* %j, i32 %.sum4 ; <i8*> [#uses=1]
+ %51 = mul i32 %x, %w ; <i32> [#uses=1]
+ %52 = sdiv i32 %51, 2 ; <i32> [#uses=1]
+ tail call void @llvm.memset.i32(i8* %50, i8 -128, i32 %52, i32 1)
+ ret void
+
+bb29: ; preds = %bb20, %entry
+ %53 = add i32 %w, 15 ; <i32> [#uses=1]
+ %54 = and i32 %53, -16 ; <i32> [#uses=1]
+ %55 = icmp sgt i32 %x, 0 ; <i1> [#uses=1]
+ br i1 %55, label %bb.nph11, label %bb33
+
+bb.nph11: ; preds = %bb29
+ br label %bb30
+
+bb30: ; preds = %bb31, %bb.nph11
+ %y.310 = phi i32 [ 0, %bb.nph11 ], [ %indvar.next13, %bb31 ] ; <i32> [#uses=3]
+ %56 = mul i32 %y.310, %54 ; <i32> [#uses=1]
+ %57 = getelementptr i8* %r, i32 %56 ; <i8*> [#uses=1]
+ %58 = mul i32 %y.310, %w ; <i32> [#uses=1]
+ %59 = getelementptr i8* %j, i32 %58 ; <i8*> [#uses=1]
+ tail call void @llvm.memcpy.i32(i8* %59, i8* %57, i32 %w, i32 1)
+ br label %bb31
+
+bb31: ; preds = %bb30
+ %indvar.next13 = add i32 %y.310, 1 ; <i32> [#uses=2]
+ %exitcond14 = icmp ne i32 %indvar.next13, %x ; <i1> [#uses=1]
+ br i1 %exitcond14, label %bb30, label %bb31.bb33_crit_edge
+
+bb31.bb33_crit_edge: ; preds = %bb31
+ br label %bb33
+
+bb33: ; preds = %bb31.bb33_crit_edge, %bb29
+ %60 = mul i32 %x, %w ; <i32> [#uses=1]
+ %61 = getelementptr i8* %j, i32 %60 ; <i8*> [#uses=1]
+ %62 = mul i32 %x, %w ; <i32> [#uses=1]
+ %63 = sdiv i32 %62, 2 ; <i32> [#uses=1]
+ tail call void @llvm.memset.i32(i8* %61, i8 -128, i32 %63, i32 1)
+ ret void
+
+return: ; preds = %bb20
+ ret void
+}
+
+define void @bar(i8* %r, i32 %s, i32 %w, i32 %x, i8* %j, i32 %d) nounwind {
+entry:
+ %0 = mul i32 %x, %w ; <i32> [#uses=2]
+ %1 = mul i32 %x, %w ; <i32> [#uses=1]
+ %2 = udiv i32 %1, 4 ; <i32> [#uses=1]
+ %.sum2 = add i32 %2, %0 ; <i32> [#uses=2]
+ %cond = icmp eq i32 %d, 1 ; <i1> [#uses=1]
+ br i1 %cond, label %bb29, label %bb10.preheader
+
+bb10.preheader: ; preds = %entry
+ %3 = icmp ne i32 %x, 0 ; <i1> [#uses=1]
+ br i1 %3, label %bb.nph9, label %bb18.loopexit
+
+bb.nph7: ; preds = %bb7.preheader
+ %4 = mul i32 %y.08, %w ; <i32> [#uses=1]
+ %5 = mul i32 %y.08, %s ; <i32> [#uses=1]
+ %6 = add i32 %5, 1 ; <i32> [#uses=1]
+ %tmp8 = icmp ugt i32 1, %w ; <i1> [#uses=1]
+ %smax9 = select i1 %tmp8, i32 1, i32 %w ; <i32> [#uses=1]
+ br label %bb6
+
+bb6: ; preds = %bb7, %bb.nph7
+ %x.06 = phi i32 [ 0, %bb.nph7 ], [ %indvar.next7, %bb7 ] ; <i32> [#uses=3]
+ %7 = add i32 %x.06, %4 ; <i32> [#uses=1]
+ %8 = shl i32 %x.06, 1 ; <i32> [#uses=1]
+ %9 = add i32 %6, %8 ; <i32> [#uses=1]
+ %10 = getelementptr i8* %r, i32 %9 ; <i8*> [#uses=1]
+ %11 = load i8* %10, align 1 ; <i8> [#uses=1]
+ %12 = getelementptr i8* %j, i32 %7 ; <i8*> [#uses=1]
+ store i8 %11, i8* %12, align 1
+ br label %bb7
+
+bb7: ; preds = %bb6
+ %indvar.next7 = add i32 %x.06, 1 ; <i32> [#uses=2]
+ %exitcond10 = icmp ne i32 %indvar.next7, %smax9 ; <i1> [#uses=1]
+ br i1 %exitcond10, label %bb6, label %bb7.bb9_crit_edge
+
+bb7.bb9_crit_edge: ; preds = %bb7
+ br label %bb9
+
+bb9: ; preds = %bb7.preheader, %bb7.bb9_crit_edge
+ br label %bb10
+
+bb10: ; preds = %bb9
+ %indvar.next11 = add i32 %y.08, 1 ; <i32> [#uses=2]
+ %exitcond12 = icmp ne i32 %indvar.next11, %x ; <i1> [#uses=1]
+ br i1 %exitcond12, label %bb7.preheader, label %bb10.bb18.loopexit_crit_edge
+
+bb10.bb18.loopexit_crit_edge: ; preds = %bb10
+ br label %bb10.bb18.loopexit_crit_edge.split
+
+bb10.bb18.loopexit_crit_edge.split: ; preds = %bb.nph9, %bb10.bb18.loopexit_crit_edge
+ br label %bb18.loopexit
+
+bb.nph9: ; preds = %bb10.preheader
+ %13 = icmp ugt i32 %w, 0 ; <i1> [#uses=1]
+ br i1 %13, label %bb.nph9.split, label %bb10.bb18.loopexit_crit_edge.split
+
+bb.nph9.split: ; preds = %bb.nph9
+ br label %bb7.preheader
+
+bb7.preheader: ; preds = %bb.nph9.split, %bb10
+ %y.08 = phi i32 [ 0, %bb.nph9.split ], [ %indvar.next11, %bb10 ] ; <i32> [#uses=3]
+ br i1 true, label %bb.nph7, label %bb9
+
+bb.nph5: ; preds = %bb18.loopexit
+ %14 = udiv i32 %w, 2 ; <i32> [#uses=1]
+ %15 = icmp ult i32 %w, 2 ; <i1> [#uses=1]
+ %16 = udiv i32 %x, 2 ; <i32> [#uses=2]
+ br i1 %15, label %bb18.bb20_crit_edge.split, label %bb.nph5.split
+
+bb.nph5.split: ; preds = %bb.nph5
+ %tmp2 = icmp ugt i32 1, %16 ; <i1> [#uses=1]
+ %smax3 = select i1 %tmp2, i32 1, i32 %16 ; <i32> [#uses=1]
+ br label %bb13
+
+bb13: ; preds = %bb18, %bb.nph5.split
+ %y.14 = phi i32 [ 0, %bb.nph5.split ], [ %indvar.next1, %bb18 ] ; <i32> [#uses=4]
+ %17 = mul i32 %14, %y.14 ; <i32> [#uses=2]
+ %18 = shl i32 %y.14, 1 ; <i32> [#uses=1]
+ %19 = urem i32 %y.14, 2 ; <i32> [#uses=1]
+ %20 = add i32 %19, %18 ; <i32> [#uses=1]
+ %21 = mul i32 %20, %s ; <i32> [#uses=2]
+ br i1 true, label %bb.nph3, label %bb17
+
+bb.nph3: ; preds = %bb13
+ %22 = add i32 %17, %0 ; <i32> [#uses=1]
+ %23 = add i32 %17, %.sum2 ; <i32> [#uses=1]
+ %24 = udiv i32 %w, 2 ; <i32> [#uses=2]
+ %tmp = icmp ugt i32 1, %24 ; <i1> [#uses=1]
+ %smax = select i1 %tmp, i32 1, i32 %24 ; <i32> [#uses=1]
+ br label %bb14
+
+bb14: ; preds = %bb15, %bb.nph3
+ %x.12 = phi i32 [ 0, %bb.nph3 ], [ %indvar.next, %bb15 ] ; <i32> [#uses=5]
+ %25 = shl i32 %x.12, 2 ; <i32> [#uses=1]
+ %26 = add i32 %25, %21 ; <i32> [#uses=1]
+ %27 = getelementptr i8* %r, i32 %26 ; <i8*> [#uses=1]
+ %28 = load i8* %27, align 1 ; <i8> [#uses=1]
+ %.sum = add i32 %22, %x.12 ; <i32> [#uses=1]
+ %29 = getelementptr i8* %j, i32 %.sum ; <i8*> [#uses=1]
+ store i8 %28, i8* %29, align 1
+ %30 = shl i32 %x.12, 2 ; <i32> [#uses=1]
+ %31 = or i32 %30, 2 ; <i32> [#uses=1]
+ %32 = add i32 %31, %21 ; <i32> [#uses=1]
+ %33 = getelementptr i8* %r, i32 %32 ; <i8*> [#uses=1]
+ %34 = load i8* %33, align 1 ; <i8> [#uses=1]
+ %.sum6 = add i32 %23, %x.12 ; <i32> [#uses=1]
+ %35 = getelementptr i8* %j, i32 %.sum6 ; <i8*> [#uses=1]
+ store i8 %34, i8* %35, align 1
+ br label %bb15
+
+bb15: ; preds = %bb14
+ %indvar.next = add i32 %x.12, 1 ; <i32> [#uses=2]
+ %exitcond = icmp ne i32 %indvar.next, %smax ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb14, label %bb15.bb17_crit_edge
+
+bb15.bb17_crit_edge: ; preds = %bb15
+ br label %bb17
+
+bb17: ; preds = %bb15.bb17_crit_edge, %bb13
+ br label %bb18
+
+bb18.loopexit: ; preds = %bb10.bb18.loopexit_crit_edge.split, %bb10.preheader
+ %36 = icmp ult i32 %x, 2 ; <i1> [#uses=1]
+ br i1 %36, label %bb20, label %bb.nph5
+
+bb18: ; preds = %bb17
+ %indvar.next1 = add i32 %y.14, 1 ; <i32> [#uses=2]
+ %exitcond4 = icmp ne i32 %indvar.next1, %smax3 ; <i1> [#uses=1]
+ br i1 %exitcond4, label %bb13, label %bb18.bb20_crit_edge
+
+bb18.bb20_crit_edge: ; preds = %bb18
+ br label %bb18.bb20_crit_edge.split
+
+bb18.bb20_crit_edge.split: ; preds = %bb18.bb20_crit_edge, %bb.nph5
+ br label %bb20
+
+bb20: ; preds = %bb18.bb20_crit_edge.split, %bb18.loopexit
+ switch i32 %d, label %return [
+ i32 3, label %bb22
+ i32 1, label %bb29
+ ]
+
+bb22: ; preds = %bb20
+ %37 = mul i32 %x, %w ; <i32> [#uses=1]
+ %38 = udiv i32 %37, 4 ; <i32> [#uses=1]
+ %.sum3 = add i32 %38, %.sum2 ; <i32> [#uses=2]
+ %39 = add i32 %x, 15 ; <i32> [#uses=1]
+ %40 = and i32 %39, -16 ; <i32> [#uses=1]
+ %41 = add i32 %w, 15 ; <i32> [#uses=1]
+ %42 = and i32 %41, -16 ; <i32> [#uses=1]
+ %43 = mul i32 %40, %s ; <i32> [#uses=1]
+ %44 = icmp ugt i32 %x, 0 ; <i1> [#uses=1]
+ br i1 %44, label %bb.nph, label %bb26
+
+bb.nph: ; preds = %bb22
+ br label %bb23
+
+bb23: ; preds = %bb24, %bb.nph
+ %y.21 = phi i32 [ 0, %bb.nph ], [ %indvar.next5, %bb24 ] ; <i32> [#uses=3]
+ %45 = mul i32 %y.21, %42 ; <i32> [#uses=1]
+ %.sum1 = add i32 %45, %43 ; <i32> [#uses=1]
+ %46 = getelementptr i8* %r, i32 %.sum1 ; <i8*> [#uses=1]
+ %47 = mul i32 %y.21, %w ; <i32> [#uses=1]
+ %.sum5 = add i32 %47, %.sum3 ; <i32> [#uses=1]
+ %48 = getelementptr i8* %j, i32 %.sum5 ; <i8*> [#uses=1]
+ tail call void @llvm.memcpy.i32(i8* %48, i8* %46, i32 %w, i32 1)
+ br label %bb24
+
+bb24: ; preds = %bb23
+ %indvar.next5 = add i32 %y.21, 1 ; <i32> [#uses=2]
+ %exitcond6 = icmp ne i32 %indvar.next5, %x ; <i1> [#uses=1]
+ br i1 %exitcond6, label %bb23, label %bb24.bb26_crit_edge
+
+bb24.bb26_crit_edge: ; preds = %bb24
+ br label %bb26
+
+bb26: ; preds = %bb24.bb26_crit_edge, %bb22
+ %49 = mul i32 %x, %w ; <i32> [#uses=1]
+ %.sum4 = add i32 %.sum3, %49 ; <i32> [#uses=1]
+ %50 = getelementptr i8* %j, i32 %.sum4 ; <i8*> [#uses=1]
+ %51 = mul i32 %x, %w ; <i32> [#uses=1]
+ %52 = udiv i32 %51, 2 ; <i32> [#uses=1]
+ tail call void @llvm.memset.i32(i8* %50, i8 -128, i32 %52, i32 1)
+ ret void
+
+bb29: ; preds = %bb20, %entry
+ %53 = add i32 %w, 15 ; <i32> [#uses=1]
+ %54 = and i32 %53, -16 ; <i32> [#uses=1]
+ %55 = icmp ugt i32 %x, 0 ; <i1> [#uses=1]
+ br i1 %55, label %bb.nph11, label %bb33
+
+bb.nph11: ; preds = %bb29
+ br label %bb30
+
+bb30: ; preds = %bb31, %bb.nph11
+ %y.310 = phi i32 [ 0, %bb.nph11 ], [ %indvar.next13, %bb31 ] ; <i32> [#uses=3]
+ %56 = mul i32 %y.310, %54 ; <i32> [#uses=1]
+ %57 = getelementptr i8* %r, i32 %56 ; <i8*> [#uses=1]
+ %58 = mul i32 %y.310, %w ; <i32> [#uses=1]
+ %59 = getelementptr i8* %j, i32 %58 ; <i8*> [#uses=1]
+ tail call void @llvm.memcpy.i32(i8* %59, i8* %57, i32 %w, i32 1)
+ br label %bb31
+
+bb31: ; preds = %bb30
+ %indvar.next13 = add i32 %y.310, 1 ; <i32> [#uses=2]
+ %exitcond14 = icmp ne i32 %indvar.next13, %x ; <i1> [#uses=1]
+ br i1 %exitcond14, label %bb30, label %bb31.bb33_crit_edge
+
+bb31.bb33_crit_edge: ; preds = %bb31
+ br label %bb33
+
+bb33: ; preds = %bb31.bb33_crit_edge, %bb29
+ %60 = mul i32 %x, %w ; <i32> [#uses=1]
+ %61 = getelementptr i8* %j, i32 %60 ; <i8*> [#uses=1]
+ %62 = mul i32 %x, %w ; <i32> [#uses=1]
+ %63 = udiv i32 %62, 2 ; <i32> [#uses=1]
+ tail call void @llvm.memset.i32(i8* %61, i8 -128, i32 %63, i32 1)
+ ret void
+
+return: ; preds = %bb20
+ ret void
+}
+
+declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind
+
+declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind
diff --git a/test/CodeGen/X86/optimize-max-1.ll b/test/CodeGen/X86/optimize-max-1.ll
new file mode 100644
index 0000000..ad6c24d
--- /dev/null
+++ b/test/CodeGen/X86/optimize-max-1.ll
@@ -0,0 +1,78 @@
+; RUN: llc < %s -march=x86-64 | not grep cmov
+
+; LSR should be able to eliminate both smax and umax expressions
+; in loop trip counts.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+
+define void @fs(double* nocapture %p, i64 %n) nounwind {
+entry:
+ %tmp = icmp slt i64 %n, 1 ; <i1> [#uses=1]
+ %smax = select i1 %tmp, i64 1, i64 %n ; <i64> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %i.0 = phi i64 [ 0, %entry ], [ %0, %bb ] ; <i64> [#uses=2]
+ %scevgep = getelementptr double* %p, i64 %i.0 ; <double*> [#uses=1]
+ store double 0.000000e+00, double* %scevgep, align 8
+ %0 = add i64 %i.0, 1 ; <i64> [#uses=2]
+ %exitcond = icmp eq i64 %0, %smax ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
+
+return: ; preds = %bb
+ ret void
+}
+
+define void @bs(double* nocapture %p, i64 %n) nounwind {
+entry:
+ %tmp = icmp sge i64 %n, 1 ; <i1> [#uses=1]
+ %smax = select i1 %tmp, i64 %n, i64 1 ; <i64> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %i.0 = phi i64 [ 0, %entry ], [ %0, %bb ] ; <i64> [#uses=2]
+ %scevgep = getelementptr double* %p, i64 %i.0 ; <double*> [#uses=1]
+ store double 0.000000e+00, double* %scevgep, align 8
+ %0 = add i64 %i.0, 1 ; <i64> [#uses=2]
+ %exitcond = icmp eq i64 %0, %smax ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
+
+return: ; preds = %bb
+ ret void
+}
+
+define void @fu(double* nocapture %p, i64 %n) nounwind {
+entry:
+ %tmp = icmp eq i64 %n, 0 ; <i1> [#uses=1]
+ %umax = select i1 %tmp, i64 1, i64 %n ; <i64> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %i.0 = phi i64 [ 0, %entry ], [ %0, %bb ] ; <i64> [#uses=2]
+ %scevgep = getelementptr double* %p, i64 %i.0 ; <double*> [#uses=1]
+ store double 0.000000e+00, double* %scevgep, align 8
+ %0 = add i64 %i.0, 1 ; <i64> [#uses=2]
+ %exitcond = icmp eq i64 %0, %umax ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
+
+return: ; preds = %bb
+ ret void
+}
+
+define void @bu(double* nocapture %p, i64 %n) nounwind {
+entry:
+ %tmp = icmp ne i64 %n, 0 ; <i1> [#uses=1]
+ %umax = select i1 %tmp, i64 %n, i64 1 ; <i64> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %i.0 = phi i64 [ 0, %entry ], [ %0, %bb ] ; <i64> [#uses=2]
+ %scevgep = getelementptr double* %p, i64 %i.0 ; <double*> [#uses=1]
+ store double 0.000000e+00, double* %scevgep, align 8
+ %0 = add i64 %i.0, 1 ; <i64> [#uses=2]
+ %exitcond = icmp eq i64 %0, %umax ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb
+
+return: ; preds = %bb
+ ret void
+}
diff --git a/test/CodeGen/X86/optimize-max-2.ll b/test/CodeGen/X86/optimize-max-2.ll
new file mode 100644
index 0000000..8851c5b
--- /dev/null
+++ b/test/CodeGen/X86/optimize-max-2.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: grep cmov %t | count 2
+; RUN: grep jne %t | count 1
+
+; LSR's OptimizeMax function shouldn't try to eliminate this max, because
+; it has three operands.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+
+define void @foo(double* nocapture %p, i64 %x, i64 %y) nounwind {
+entry:
+ %tmp = icmp eq i64 %y, 0 ; <i1> [#uses=1]
+ %umax = select i1 %tmp, i64 1, i64 %y ; <i64> [#uses=2]
+ %tmp8 = icmp ugt i64 %umax, %x ; <i1> [#uses=1]
+ %umax9 = select i1 %tmp8, i64 %umax, i64 %x ; <i64> [#uses=1]
+ br label %bb4
+
+bb4: ; preds = %bb4, %entry
+ %i.07 = phi i64 [ 0, %entry ], [ %2, %bb4 ] ; <i64> [#uses=2]
+ %scevgep = getelementptr double* %p, i64 %i.07 ; <double*> [#uses=2]
+ %0 = load double* %scevgep, align 8 ; <double> [#uses=1]
+ %1 = fmul double %0, 2.000000e+00 ; <double> [#uses=1]
+ store double %1, double* %scevgep, align 8
+ %2 = add i64 %i.07, 1 ; <i64> [#uses=2]
+ %exitcond = icmp eq i64 %2, %umax9 ; <i1> [#uses=1]
+ br i1 %exitcond, label %return, label %bb4
+
+return: ; preds = %bb4
+ ret void
+}
diff --git a/test/CodeGen/X86/or-branch.ll b/test/CodeGen/X86/or-branch.ll
new file mode 100644
index 0000000..9ebf890
--- /dev/null
+++ b/test/CodeGen/X86/or-branch.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86 | not grep set
+
+define void @foo(i32 %X, i32 %Y, i32 %Z) nounwind {
+entry:
+ %tmp = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ %tmp.upgrd.1 = icmp eq i32 %X, 0 ; <i1> [#uses=1]
+ %tmp3 = icmp slt i32 %Y, 5 ; <i1> [#uses=1]
+ %tmp4 = or i1 %tmp3, %tmp.upgrd.1 ; <i1> [#uses=1]
+ br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
+
+cond_true: ; preds = %entry
+ %tmp5 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
+ ret void
+
+UnifiedReturnBlock: ; preds = %entry
+ ret void
+}
+
+declare i32 @bar(...)
diff --git a/test/CodeGen/X86/overlap-shift.ll b/test/CodeGen/X86/overlap-shift.ll
new file mode 100644
index 0000000..c1fc041
--- /dev/null
+++ b/test/CodeGen/X86/overlap-shift.ll
@@ -0,0 +1,19 @@
+;; X's live range extends beyond the shift, so the register allocator
+;; cannot coalesce it with Y. Because of this, a copy needs to be
+;; emitted before the shift to save the register value before it is
+;; clobbered. However, this copy is not needed if the register
+;; allocator turns the shift into an LEA. This also occurs for ADD.
+
+; Check that the shift gets turned into an LEA.
+
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
+; RUN: not grep {mov E.X, E.X}
+
+@G = external global i32 ; <i32*> [#uses=1]
+
+define i32 @test1(i32 %X) {
+ %Z = shl i32 %X, 2 ; <i32> [#uses=1]
+ volatile store i32 %Z, i32* @G
+ ret i32 %X
+}
+
diff --git a/test/CodeGen/X86/packed_struct.ll b/test/CodeGen/X86/packed_struct.ll
new file mode 100644
index 0000000..da6e8f8
--- /dev/null
+++ b/test/CodeGen/X86/packed_struct.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep foos+5 %t
+; RUN: grep foos+1 %t
+; RUN: grep foos+9 %t
+; RUN: grep bara+19 %t
+; RUN: grep bara+4 %t
+
+; make sure we compute the correct offset for a packed structure
+
+;Note: codegen for this could change rendering the above checks wrong
+
+target datalayout = "e-p:32:32"
+target triple = "i686-pc-linux-gnu"
+ %struct.anon = type <{ i8, i32, i32, i32 }>
+@foos = external global %struct.anon ; <%struct.anon*> [#uses=3]
+@bara = weak global [4 x <{ i32, i8 }>] zeroinitializer ; <[4 x <{ i32, i8 }>]*> [#uses=2]
+
+define i32 @foo() nounwind {
+entry:
+ %tmp = load i32* getelementptr (%struct.anon* @foos, i32 0, i32 1) ; <i32> [#uses=1]
+ %tmp3 = load i32* getelementptr (%struct.anon* @foos, i32 0, i32 2) ; <i32> [#uses=1]
+ %tmp6 = load i32* getelementptr (%struct.anon* @foos, i32 0, i32 3) ; <i32> [#uses=1]
+ %tmp4 = add i32 %tmp3, %tmp ; <i32> [#uses=1]
+ %tmp7 = add i32 %tmp4, %tmp6 ; <i32> [#uses=1]
+ ret i32 %tmp7
+}
+
+define i8 @bar() nounwind {
+entry:
+ %tmp = load i8* getelementptr ([4 x <{ i32, i8 }>]* @bara, i32 0, i32 0, i32 1) ; <i8> [#uses=1]
+ %tmp4 = load i8* getelementptr ([4 x <{ i32, i8 }>]* @bara, i32 0, i32 3, i32 1) ; <i8> [#uses=1]
+ %tmp5 = add i8 %tmp4, %tmp ; <i8> [#uses=1]
+ ret i8 %tmp5
+}
diff --git a/test/CodeGen/X86/palignr-2.ll b/test/CodeGen/X86/palignr-2.ll
new file mode 100644
index 0000000..116d4c7
--- /dev/null
+++ b/test/CodeGen/X86/palignr-2.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=x86 -mattr=+ssse3 | FileCheck %s
+; rdar://7341330
+
+@a = global [4 x i32] [i32 4, i32 5, i32 6, i32 7], align 16 ; <[4 x i32]*> [#uses=1]
+@c = common global [4 x i32] zeroinitializer, align 16 ; <[4 x i32]*> [#uses=1]
+@b = global [4 x i32] [i32 0, i32 1, i32 2, i32 3], align 16 ; <[4 x i32]*> [#uses=1]
+
+define void @t1(<2 x i64> %a, <2 x i64> %b) nounwind ssp {
+entry:
+; CHECK: t1:
+; palignr $3, %xmm1, %xmm0
+ %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i8 24) nounwind readnone
+ store <2 x i64> %0, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16
+ ret void
+}
+
+declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
+
+define void @t2() nounwind ssp {
+entry:
+; CHECK: t2:
+; palignr $4, _b, %xmm0
+ %0 = load <2 x i64>* bitcast ([4 x i32]* @b to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1]
+ %1 = load <2 x i64>* bitcast ([4 x i32]* @a to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1]
+ %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) nounwind readnone
+ store <2 x i64> %2, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16
+ ret void
+}
diff --git a/test/CodeGen/X86/palignr.ll b/test/CodeGen/X86/palignr.ll
new file mode 100644
index 0000000..3812c72
--- /dev/null
+++ b/test/CodeGen/X86/palignr.ll
@@ -0,0 +1,58 @@
+; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s
+; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck --check-prefix=YONAH %s
+
+define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: pshufd
+; CHECK-YONAH: pshufd
+ %C = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> < i32 1, i32 2, i32 3, i32 0 >
+ ret <4 x i32> %C
+}
+
+define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: palignr
+; CHECK-YONAH: shufps
+ %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 3, i32 4 >
+ ret <4 x i32> %C
+}
+
+define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: palignr
+ %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 undef, i32 4 >
+ ret <4 x i32> %C
+}
+
+define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: palignr
+ %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 >
+ ret <4 x i32> %C
+}
+
+define <4 x float> @test5(<4 x float> %A, <4 x float> %B) nounwind {
+; CHECK: palignr
+ %C = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 >
+ ret <4 x float> %C
+}
+
+define <8 x i16> @test6(<8 x i16> %A, <8 x i16> %B) nounwind {
+; CHECK: palignr
+ %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 3, i32 4, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10 >
+ ret <8 x i16> %C
+}
+
+define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) nounwind {
+; CHECK: palignr
+ %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 undef, i32 6, i32 undef, i32 8, i32 9, i32 10, i32 11, i32 12 >
+ ret <8 x i16> %C
+}
+
+define <8 x i16> @test8(<8 x i16> %A, <8 x i16> %B) nounwind {
+; CHECK: palignr
+ %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 undef, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0 >
+ ret <8 x i16> %C
+}
+
+define <16 x i8> @test9(<16 x i8> %A, <16 x i8> %B) nounwind {
+; CHECK: palignr
+ %C = shufflevector <16 x i8> %A, <16 x i8> %B, <16 x i32> < i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20 >
+ ret <16 x i8> %C
+}
diff --git a/test/CodeGen/X86/peep-test-0.ll b/test/CodeGen/X86/peep-test-0.ll
new file mode 100644
index 0000000..e521d8e
--- /dev/null
+++ b/test/CodeGen/X86/peep-test-0.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: not grep cmp %t
+; RUN: not grep test %t
+
+define void @loop(i64 %n, double* nocapture %d) nounwind {
+entry:
+ br label %bb
+
+bb:
+ %indvar = phi i64 [ %n, %entry ], [ %indvar.next, %bb ]
+ %i.03 = add i64 %indvar, %n
+ %0 = getelementptr double* %d, i64 %i.03
+ %1 = load double* %0, align 8
+ %2 = fmul double %1, 3.000000e+00
+ store double %2, double* %0, align 8
+ %indvar.next = add i64 %indvar, 1
+ %exitcond = icmp eq i64 %indvar.next, 0
+ br i1 %exitcond, label %return, label %bb
+
+return:
+ ret void
+}
diff --git a/test/CodeGen/X86/peep-test-1.ll b/test/CodeGen/X86/peep-test-1.ll
new file mode 100644
index 0000000..f83f0f6
--- /dev/null
+++ b/test/CodeGen/X86/peep-test-1.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep dec %t | count 1
+; RUN: not grep test %t
+; RUN: not grep cmp %t
+
+define void @foo(i32 %n, double* nocapture %p) nounwind {
+ br label %bb
+
+bb:
+ %indvar = phi i32 [ 0, %0 ], [ %indvar.next, %bb ]
+ %i.03 = sub i32 %n, %indvar
+ %1 = getelementptr double* %p, i32 %i.03
+ %2 = load double* %1, align 4
+ %3 = fmul double %2, 2.930000e+00
+ store double %3, double* %1, align 4
+ %4 = add i32 %i.03, -1
+ %phitmp = icmp slt i32 %4, 0
+ %indvar.next = add i32 %indvar, 1
+ br i1 %phitmp, label %bb, label %return
+
+return:
+ ret void
+}
diff --git a/test/CodeGen/X86/peep-test-2.ll b/test/CodeGen/X86/peep-test-2.ll
new file mode 100644
index 0000000..2745172
--- /dev/null
+++ b/test/CodeGen/X86/peep-test-2.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 | grep testl
+
+; It's tempting to eliminate the testl instruction here and just use the
+; EFLAGS value from the incl, however it can't be known whether the add
+; will overflow, and if it does the incl would set OF, and the
+; subsequent setg would return true.
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.6"
+
+define i32 @f(i32 %j) nounwind readnone {
+entry:
+ %0 = add i32 %j, 1 ; <i32> [#uses=1]
+ %1 = icmp sgt i32 %0, 0 ; <i1> [#uses=1]
+ %2 = zext i1 %1 to i32 ; <i32> [#uses=1]
+ ret i32 %2
+}
diff --git a/test/CodeGen/X86/peep-test-3.ll b/test/CodeGen/X86/peep-test-3.ll
new file mode 100644
index 0000000..a34a978
--- /dev/null
+++ b/test/CodeGen/X86/peep-test-3.ll
@@ -0,0 +1,89 @@
+; RUN: llc < %s -march=x86 -post-RA-scheduler=false | FileCheck %s
+; rdar://7226797
+
+; LLVM should omit the testl and use the flags result from the orl.
+
+; CHECK: or:
+define void @or(float* %A, i32 %IA, i32 %N) nounwind {
+entry:
+ %0 = ptrtoint float* %A to i32 ; <i32> [#uses=1]
+ %1 = and i32 %0, 3 ; <i32> [#uses=1]
+ %2 = xor i32 %IA, 1 ; <i32> [#uses=1]
+; CHECK: orl %ecx, %edx
+; CHECK-NEXT: je
+ %3 = or i32 %2, %1 ; <i32> [#uses=1]
+ %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1]
+ br i1 %4, label %return, label %bb
+
+bb: ; preds = %entry
+ store float 0.000000e+00, float* %A, align 4
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
+; CHECK: xor:
+define void @xor(float* %A, i32 %IA, i32 %N) nounwind {
+entry:
+ %0 = ptrtoint float* %A to i32 ; <i32> [#uses=1]
+ %1 = and i32 %0, 3 ; <i32> [#uses=1]
+; CHECK: xorl $1, %e
+; CHECK-NEXT: je
+ %2 = xor i32 %IA, 1 ; <i32> [#uses=1]
+ %3 = xor i32 %2, %1 ; <i32> [#uses=1]
+ %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1]
+ br i1 %4, label %return, label %bb
+
+bb: ; preds = %entry
+ store float 0.000000e+00, float* %A, align 4
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
+; CHECK: and:
+define void @and(float* %A, i32 %IA, i32 %N, i8* %p) nounwind {
+entry:
+ store i8 0, i8* %p
+ %0 = ptrtoint float* %A to i32 ; <i32> [#uses=1]
+ %1 = and i32 %0, 3 ; <i32> [#uses=1]
+ %2 = xor i32 %IA, 1 ; <i32> [#uses=1]
+; CHECK: andl $3, %
+; CHECK-NEXT: movb %
+; CHECK-NEXT: je
+ %3 = and i32 %2, %1 ; <i32> [#uses=1]
+ %t = trunc i32 %3 to i8
+ store i8 %t, i8* %p
+ %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1]
+ br i1 %4, label %return, label %bb
+
+bb: ; preds = %entry
+ store float 0.000000e+00, float* null, align 4
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
+
+; Just like @and, but without the trunc+store. This should use a testb
+; instead of an andl.
+; CHECK: test:
+define void @test(float* %A, i32 %IA, i32 %N, i8* %p) nounwind {
+entry:
+ store i8 0, i8* %p
+ %0 = ptrtoint float* %A to i32 ; <i32> [#uses=1]
+ %1 = and i32 %0, 3 ; <i32> [#uses=1]
+ %2 = xor i32 %IA, 1 ; <i32> [#uses=1]
+; CHECK: testb $3, %
+; CHECK-NEXT: je
+ %3 = and i32 %2, %1 ; <i32> [#uses=1]
+ %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1]
+ br i1 %4, label %return, label %bb
+
+bb: ; preds = %entry
+ store float 0.000000e+00, float* null, align 4
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/peep-vector-extract-concat.ll b/test/CodeGen/X86/peep-vector-extract-concat.ll
new file mode 100644
index 0000000..e4ab2b5
--- /dev/null
+++ b/test/CodeGen/X86/peep-vector-extract-concat.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | grep {pshufd \$3, %xmm0, %xmm0}
+
+define float @foo(<8 x float> %a) nounwind {
+ %c = extractelement <8 x float> %a, i32 3
+ ret float %c
+}
diff --git a/test/CodeGen/X86/peep-vector-extract-insert.ll b/test/CodeGen/X86/peep-vector-extract-insert.ll
new file mode 100644
index 0000000..5e18044
--- /dev/null
+++ b/test/CodeGen/X86/peep-vector-extract-insert.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86-64 | grep {pxor %xmm0, %xmm0} | count 2
+
+define float @foo(<4 x float> %a) {
+ %b = insertelement <4 x float> %a, float 0.0, i32 3
+ %c = extractelement <4 x float> %b, i32 3
+ ret float %c
+}
+define float @bar(float %a) {
+ %b = insertelement <4 x float> <float 0x400B333340000000, float 4.5, float 0.0, float 0x4022666660000000>, float %a, i32 3
+ %c = extractelement <4 x float> %b, i32 2
+ ret float %c
+}
diff --git a/test/CodeGen/X86/personality.ll b/test/CodeGen/X86/personality.ll
new file mode 100644
index 0000000..ce57e8f
--- /dev/null
+++ b/test/CodeGen/X86/personality.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s -check-prefix=X32
+; PR1632
+
+define void @_Z1fv() {
+entry:
+ invoke void @_Z1gv( )
+ to label %return unwind label %unwind
+
+unwind: ; preds = %entry
+ br i1 false, label %eh_then, label %cleanup20
+
+eh_then: ; preds = %unwind
+ invoke void @__cxa_end_catch( )
+ to label %return unwind label %unwind10
+
+unwind10: ; preds = %eh_then
+ %eh_select13 = tail call i64 (i8*, i8*, ...)* @llvm.eh.selector.i64( i8* null, i8* bitcast (void ()* @__gxx_personality_v0 to i8*), i32 1 ) ; <i32> [#uses=2]
+ %tmp18 = icmp slt i64 %eh_select13, 0 ; <i1> [#uses=1]
+ br i1 %tmp18, label %filter, label %cleanup20
+
+filter: ; preds = %unwind10
+ unreachable
+
+cleanup20: ; preds = %unwind10, %unwind
+ %eh_selector.0 = phi i64 [ 0, %unwind ], [ %eh_select13, %unwind10 ] ; <i32> [#uses=0]
+ ret void
+
+return: ; preds = %eh_then, %entry
+ ret void
+}
+
+declare void @_Z1gv()
+
+declare i64 @llvm.eh.selector.i64(i8*, i8*, ...)
+
+declare void @__gxx_personality_v0()
+
+declare void @__cxa_end_catch()
+
+; X64: Leh_frame_common_begin:
+; X64: .long (___gxx_personality_v0@GOTPCREL)+4
+
+; X32: Leh_frame_common_begin:
+; X32: .long L___gxx_personality_v0$non_lazy_ptr-
+; ....
+
+; X32: .section __IMPORT,__pointers,non_lazy_symbol_pointers
+; X32: L___gxx_personality_v0$non_lazy_ptr:
+; X32: .indirect_symbol ___gxx_personality_v0
diff --git a/test/CodeGen/X86/phi-immediate-factoring.ll b/test/CodeGen/X86/phi-immediate-factoring.ll
new file mode 100644
index 0000000..9f9f921
--- /dev/null
+++ b/test/CodeGen/X86/phi-immediate-factoring.ll
@@ -0,0 +1,54 @@
+; PR1296
+; RUN: llc < %s -march=x86 | grep {movl \$1} | count 1
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+
+define i32 @foo(i32 %A, i32 %B, i32 %C) {
+entry:
+ switch i32 %A, label %out [
+ i32 1, label %bb
+ i32 0, label %bb13
+ i32 2, label %bb35
+ ]
+
+bb: ; preds = %cond_next, %entry
+ %i.144.1 = phi i32 [ 0, %entry ], [ %tmp7, %cond_next ] ; <i32> [#uses=2]
+ %tmp4 = and i32 %i.144.1, %B ; <i32> [#uses=1]
+ icmp eq i32 %tmp4, 0 ; <i1>:0 [#uses=1]
+ br i1 %0, label %cond_next, label %out
+
+cond_next: ; preds = %bb
+ %tmp7 = add i32 %i.144.1, 1 ; <i32> [#uses=2]
+ icmp slt i32 %tmp7, 1000 ; <i1>:1 [#uses=1]
+ br i1 %1, label %bb, label %out
+
+bb13: ; preds = %cond_next18, %entry
+ %i.248.1 = phi i32 [ 0, %entry ], [ %tmp20, %cond_next18 ] ; <i32> [#uses=2]
+ %tmp16 = and i32 %i.248.1, %C ; <i32> [#uses=1]
+ icmp eq i32 %tmp16, 0 ; <i1>:2 [#uses=1]
+ br i1 %2, label %cond_next18, label %out
+
+cond_next18: ; preds = %bb13
+ %tmp20 = add i32 %i.248.1, 1 ; <i32> [#uses=2]
+ icmp slt i32 %tmp20, 1000 ; <i1>:3 [#uses=1]
+ br i1 %3, label %bb13, label %out
+
+bb27: ; preds = %bb35
+ %tmp30 = and i32 %i.3, %C ; <i32> [#uses=1]
+ icmp eq i32 %tmp30, 0 ; <i1>:4 [#uses=1]
+ br i1 %4, label %cond_next32, label %out
+
+cond_next32: ; preds = %bb27
+ %indvar.next = add i32 %i.3, 1 ; <i32> [#uses=1]
+ br label %bb35
+
+bb35: ; preds = %entry, %cond_next32
+ %i.3 = phi i32 [ %indvar.next, %cond_next32 ], [ 0, %entry ] ; <i32> [#uses=3]
+ icmp slt i32 %i.3, 1000 ; <i1>:5 [#uses=1]
+ br i1 %5, label %bb27, label %out
+
+out: ; preds = %bb27, %bb35, %bb13, %cond_next18, %bb, %cond_next, %entry
+ %result.0 = phi i32 [ 0, %entry ], [ 1, %bb ], [ 0, %cond_next ], [ 1, %bb13 ], [ 0, %cond_next18 ], [ 1, %bb27 ], [ 0, %bb35 ] ; <i32> [#uses=1]
+ ret i32 %result.0
+}
diff --git a/test/CodeGen/X86/phys-reg-local-regalloc.ll b/test/CodeGen/X86/phys-reg-local-regalloc.ll
new file mode 100644
index 0000000..045841e
--- /dev/null
+++ b/test/CodeGen/X86/phys-reg-local-regalloc.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=local | FileCheck %s
+; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=local | FileCheck %s
+; CHECKed instructions should be the same with or without -O0.
+
[email protected] = private constant [12 x i8] c"x + y = %i\0A\00", align 1 ; <[12 x i8]*> [#uses=1]
+
+define i32 @main() nounwind {
+entry:
+; CHECK: movl 24(%esp), %eax
+; CHECK-NOT: movl
+; CHECK: movl %eax, 36(%esp)
+; CHECK-NOT: movl
+; CHECK: movl 28(%esp), %ebx
+; CHECK-NOT: movl
+; CHECK: movl %ebx, 40(%esp)
+; CHECK-NOT: movl
+; CHECK: addl %ebx, %eax
+ %retval = alloca i32 ; <i32*> [#uses=2]
+ %"%ebx" = alloca i32 ; <i32*> [#uses=1]
+ %"%eax" = alloca i32 ; <i32*> [#uses=2]
+ %result = alloca i32 ; <i32*> [#uses=2]
+ %y = alloca i32 ; <i32*> [#uses=2]
+ %x = alloca i32 ; <i32*> [#uses=2]
+ %0 = alloca i32 ; <i32*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 1, i32* %x, align 4
+ store i32 2, i32* %y, align 4
+ call void asm sideeffect alignstack "# top of block", "~{dirflag},~{fpsr},~{flags},~{edi},~{esi},~{edx},~{ecx},~{eax}"() nounwind
+ %asmtmp = call i32 asm sideeffect alignstack "movl $1, $0", "=={eax},*m,~{dirflag},~{fpsr},~{flags},~{memory}"(i32* %x) nounwind ; <i32> [#uses=1]
+ store i32 %asmtmp, i32* %"%eax"
+ %asmtmp1 = call i32 asm sideeffect alignstack "movl $1, $0", "=={ebx},*m,~{dirflag},~{fpsr},~{flags},~{memory}"(i32* %y) nounwind ; <i32> [#uses=1]
+ store i32 %asmtmp1, i32* %"%ebx"
+ %1 = call i32 asm "", "={bx}"() nounwind ; <i32> [#uses=1]
+ %2 = call i32 asm "", "={ax}"() nounwind ; <i32> [#uses=1]
+ %asmtmp2 = call i32 asm sideeffect alignstack "addl $1, $0", "=={eax},{ebx},{eax},~{dirflag},~{fpsr},~{flags},~{memory}"(i32 %1, i32 %2) nounwind ; <i32> [#uses=1]
+ store i32 %asmtmp2, i32* %"%eax"
+ %3 = call i32 asm "", "={ax}"() nounwind ; <i32> [#uses=1]
+ call void asm sideeffect alignstack "movl $0, $1", "{eax},*m,~{dirflag},~{fpsr},~{flags},~{memory}"(i32 %3, i32* %result) nounwind
+ %4 = load i32* %result, align 4 ; <i32> [#uses=1]
+ %5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), i32 %4) nounwind ; <i32> [#uses=0]
+ store i32 0, i32* %0, align 4
+ %6 = load i32* %0, align 4 ; <i32> [#uses=1]
+ store i32 %6, i32* %retval, align 4
+ br label %return
+
+return: ; preds = %entry
+ %retval3 = load i32* %retval ; <i32> [#uses=1]
+ ret i32 %retval3
+}
+
+declare i32 @printf(i8*, ...) nounwind
diff --git a/test/CodeGen/X86/phys_subreg_coalesce-2.ll b/test/CodeGen/X86/phys_subreg_coalesce-2.ll
new file mode 100644
index 0000000..23c509c
--- /dev/null
+++ b/test/CodeGen/X86/phys_subreg_coalesce-2.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=x86 | grep mov | count 5
+; PR2659
+
+define i32 @binomial(i32 %n, i32 %k) nounwind {
+entry:
+ %cmp = icmp ugt i32 %k, %n ; <i1> [#uses=1]
+ br i1 %cmp, label %ifthen, label %forcond.preheader
+
+forcond.preheader: ; preds = %entry
+ %cmp44 = icmp eq i32 %k, 0 ; <i1> [#uses=1]
+ br i1 %cmp44, label %afterfor, label %forbody
+
+ifthen: ; preds = %entry
+ ret i32 0
+
+forbody: ; preds = %forbody, %forcond.preheader
+ %indvar = phi i32 [ 0, %forcond.preheader ], [ %divisor.02, %forbody ] ; <i32> [#uses=3]
+ %accumulator.01 = phi i32 [ 1, %forcond.preheader ], [ %div, %forbody ] ; <i32> [#uses=1]
+ %divisor.02 = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %n.addr.03 = sub i32 %n, %indvar ; <i32> [#uses=1]
+ %mul = mul i32 %n.addr.03, %accumulator.01 ; <i32> [#uses=1]
+ %div = udiv i32 %mul, %divisor.02 ; <i32> [#uses=2]
+ %inc = add i32 %indvar, 2 ; <i32> [#uses=1]
+ %cmp4 = icmp ugt i32 %inc, %k ; <i1> [#uses=1]
+ br i1 %cmp4, label %afterfor, label %forbody
+
+afterfor: ; preds = %forbody, %forcond.preheader
+ %accumulator.0.lcssa = phi i32 [ 1, %forcond.preheader ], [ %div, %forbody ] ; <i32> [#uses=1]
+ ret i32 %accumulator.0.lcssa
+}
diff --git a/test/CodeGen/X86/phys_subreg_coalesce.ll b/test/CodeGen/X86/phys_subreg_coalesce.ll
new file mode 100644
index 0000000..2c855ce
--- /dev/null
+++ b/test/CodeGen/X86/phys_subreg_coalesce.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=+sse2 | not grep movl
+
+ %struct.dpoint = type { double, double }
+
+define %struct.dpoint @midpoint(i64 %p1.0, i64 %p2.0) nounwind readnone {
+entry:
+ %0 = trunc i64 %p1.0 to i32 ; <i32> [#uses=1]
+ %1 = sitofp i32 %0 to double ; <double> [#uses=1]
+ %2 = trunc i64 %p2.0 to i32 ; <i32> [#uses=1]
+ %3 = sitofp i32 %2 to double ; <double> [#uses=1]
+ %4 = fadd double %1, %3 ; <double> [#uses=1]
+ %5 = fmul double %4, 5.000000e-01 ; <double> [#uses=1]
+ %6 = lshr i64 %p1.0, 32 ; <i64> [#uses=1]
+ %7 = trunc i64 %6 to i32 ; <i32> [#uses=1]
+ %8 = sitofp i32 %7 to double ; <double> [#uses=1]
+ %9 = lshr i64 %p2.0, 32 ; <i64> [#uses=1]
+ %10 = trunc i64 %9 to i32 ; <i32> [#uses=1]
+ %11 = sitofp i32 %10 to double ; <double> [#uses=1]
+ %12 = fadd double %8, %11 ; <double> [#uses=1]
+ %13 = fmul double %12, 5.000000e-01 ; <double> [#uses=1]
+ %mrv3 = insertvalue %struct.dpoint undef, double %5, 0 ; <%struct.dpoint> [#uses=1]
+ %mrv4 = insertvalue %struct.dpoint %mrv3, double %13, 1 ; <%struct.dpoint> [#uses=1]
+ ret %struct.dpoint %mrv4
+}
diff --git a/test/CodeGen/X86/pic-load-remat.ll b/test/CodeGen/X86/pic-load-remat.ll
new file mode 100644
index 0000000..7729752
--- /dev/null
+++ b/test/CodeGen/X86/pic-load-remat.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -relocation-model=pic | grep psllw | grep pb
+
+define void @f() nounwind {
+entry:
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %tmp4403 = tail call <8 x i16> @llvm.x86.sse2.psubs.w( <8 x i16> zeroinitializer, <8 x i16> zeroinitializer ) nounwind readnone ; <<8 x i16>> [#uses=2]
+ %tmp4443 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> zeroinitializer, <8 x i16> zeroinitializer ) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp4609 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> zeroinitializer, <8 x i16> bitcast (<4 x i32> < i32 3, i32 5, i32 6, i32 9 > to <8 x i16>) ) ; <<8 x i16>> [#uses=1]
+ %tmp4651 = add <8 x i16> %tmp4609, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1 > ; <<8 x i16>> [#uses=1]
+ %tmp4658 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp4651, <8 x i16> bitcast (<4 x i32> < i32 4, i32 1, i32 2, i32 3 > to <8 x i16>) ) ; <<8 x i16>> [#uses=1]
+ %tmp4669 = tail call <8 x i16> @llvm.x86.sse2.pavg.w( <8 x i16> < i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170 >, <8 x i16> %tmp4443 ) nounwind readnone ; <<8 x i16>> [#uses=2]
+ %tmp4679 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4669, <8 x i16> %tmp4669 ) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp4689 = add <8 x i16> %tmp4679, %tmp4658 ; <<8 x i16>> [#uses=1]
+ %tmp4700 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4689, <8 x i16> zeroinitializer ) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp4708 = bitcast <8 x i16> %tmp4700 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp4772 = add <8 x i16> zeroinitializer, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1 > ; <<8 x i16>> [#uses=1]
+ %tmp4779 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp4772, <8 x i16> bitcast (<4 x i32> < i32 3, i32 5, i32 undef, i32 7 > to <8 x i16>) ) ; <<8 x i16>> [#uses=1]
+ %tmp4810 = add <8 x i16> zeroinitializer, %tmp4779 ; <<8 x i16>> [#uses=1]
+ %tmp4821 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4810, <8 x i16> zeroinitializer ) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp4829 = bitcast <8 x i16> %tmp4821 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp4900 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> zeroinitializer, <8 x i16> bitcast (<4 x i32> < i32 1, i32 1, i32 2, i32 2 > to <8 x i16>) ) ; <<8 x i16>> [#uses=1]
+ %tmp4911 = tail call <8 x i16> @llvm.x86.sse2.pavg.w( <8 x i16> < i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170 >, <8 x i16> zeroinitializer ) nounwind readnone ; <<8 x i16>> [#uses=2]
+ %tmp4921 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4911, <8 x i16> %tmp4911 ) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp4931 = add <8 x i16> %tmp4921, %tmp4900 ; <<8 x i16>> [#uses=1]
+ %tmp4942 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4931, <8 x i16> zeroinitializer ) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp4950 = bitcast <8 x i16> %tmp4942 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp4957 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4403, <8 x i16> zeroinitializer ) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp4958 = bitcast <8 x i16> %tmp4957 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp4967 = tail call <8 x i16> @llvm.x86.sse2.psubs.w( <8 x i16> %tmp4403, <8 x i16> zeroinitializer ) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp4968 = bitcast <8 x i16> %tmp4967 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ store <2 x i64> %tmp4829, <2 x i64>* null, align 16
+ store <2 x i64> %tmp4958, <2 x i64>* null, align 16
+ store <2 x i64> %tmp4968, <2 x i64>* null, align 16
+ store <2 x i64> %tmp4950, <2 x i64>* null, align 16
+ store <2 x i64> %tmp4708, <2 x i64>* null, align 16
+ br label %bb
+}
+
+declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+declare <8 x i16> @llvm.x86.sse2.padds.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+declare <8 x i16> @llvm.x86.sse2.psubs.w(<8 x i16>, <8 x i16>) nounwind readnone
diff --git a/test/CodeGen/X86/pic.ll b/test/CodeGen/X86/pic.ll
new file mode 100644
index 0000000..d3c28a0
--- /dev/null
+++ b/test/CodeGen/X86/pic.ll
@@ -0,0 +1,208 @@
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu -relocation-model=pic -asm-verbose=false -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX
+
+@ptr = external global i32*
+@dst = external global i32
+@src = external global i32
+
+define void @test1() nounwind {
+entry:
+ store i32* @dst, i32** @ptr
+ %tmp.s = load i32* @src
+ store i32 %tmp.s, i32* @dst
+ ret void
+
+; LINUX: test1:
+; LINUX: call .L1$pb
+; LINUX-NEXT: .L1$pb:
+; LINUX-NEXT: popl
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref1-.L1$pb),
+; LINUX: movl dst@GOT(%eax),
+; LINUX: movl ptr@GOT(%eax),
+; LINUX: movl src@GOT(%eax),
+; LINUX: ret
+}
+
+@ptr2 = global i32* null
+@dst2 = global i32 0
+@src2 = global i32 0
+
+define void @test2() nounwind {
+entry:
+ store i32* @dst2, i32** @ptr2
+ %tmp.s = load i32* @src2
+ store i32 %tmp.s, i32* @dst2
+ ret void
+
+; LINUX: test2:
+; LINUX: call .L2$pb
+; LINUX-NEXT: .L2$pb:
+; LINUX-NEXT: popl
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref2-.L2$pb), %eax
+; LINUX: movl dst2@GOT(%eax),
+; LINUX: movl ptr2@GOT(%eax),
+; LINUX: movl src2@GOT(%eax),
+; LINUX: ret
+
+}
+
+declare i8* @malloc(i32)
+
+define void @test3() nounwind {
+entry:
+ %ptr = call i8* @malloc(i32 40)
+ ret void
+; LINUX: test3:
+; LINUX: pushl %ebx
+; LINUX-NEXT: subl $8, %esp
+; LINUX-NEXT: call .L3$pb
+; LINUX-NEXT: .L3$pb:
+; LINUX-NEXT: popl %ebx
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref3-.L3$pb), %ebx
+; LINUX: movl $40, (%esp)
+; LINUX: call malloc@PLT
+; LINUX: addl $8, %esp
+; LINUX: popl %ebx
+; LINUX: ret
+}
+
+@pfoo = external global void(...)*
+
+define void @test4() nounwind {
+entry:
+ %tmp = call void(...)*(...)* @afoo()
+ store void(...)* %tmp, void(...)** @pfoo
+ %tmp1 = load void(...)** @pfoo
+ call void(...)* %tmp1()
+ ret void
+; LINUX: test4:
+; LINUX: call .L4$pb
+; LINUX-NEXT: .L4$pb:
+; LINUX: popl
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref4-.L4$pb),
+; LINUX: movl pfoo@GOT(%esi),
+; LINUX: call afoo@PLT
+; LINUX: call *
+}
+
+declare void(...)* @afoo(...)
+
+define void @test5() nounwind {
+entry:
+ call void(...)* @foo()
+ ret void
+; LINUX: test5:
+; LINUX: call .L5$pb
+; LINUX: popl %ebx
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref5-.L5$pb), %ebx
+; LINUX: call foo@PLT
+}
+
+declare void @foo(...)
+
+
+@ptr6 = internal global i32* null
+@dst6 = internal global i32 0
+@src6 = internal global i32 0
+
+define void @test6() nounwind {
+entry:
+ store i32* @dst6, i32** @ptr6
+ %tmp.s = load i32* @src6
+ store i32 %tmp.s, i32* @dst6
+ ret void
+
+; LINUX: test6:
+; LINUX: call .L6$pb
+; LINUX-NEXT: .L6$pb:
+; LINUX-NEXT: popl %eax
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref6-.L6$pb), %eax
+; LINUX: leal dst6@GOTOFF(%eax), %ecx
+; LINUX: movl %ecx, ptr6@GOTOFF(%eax)
+; LINUX: movl src6@GOTOFF(%eax), %ecx
+; LINUX: movl %ecx, dst6@GOTOFF(%eax)
+; LINUX: ret
+}
+
+
+;; Test constant pool references.
+define double @test7(i32 %a.u) nounwind {
+entry:
+ %tmp = icmp eq i32 %a.u,0
+ %retval = select i1 %tmp, double 4.561230e+02, double 1.234560e+02
+ ret double %retval
+
+; LINUX: .LCPI7_0:
+
+; LINUX: test7:
+; LINUX: call .L7$pb
+; LINUX: .L7$pb:
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref7-.L7$pb),
+; LINUX: fldl .LCPI7_0@GOTOFF(
+}
+
+
+;; Test jump table references.
+define void @test8(i32 %n.u) nounwind {
+entry:
+ switch i32 %n.u, label %bb12 [i32 1, label %bb i32 2, label %bb6 i32 4, label %bb7 i32 5, label %bb8 i32 6, label %bb10 i32 7, label %bb1 i32 8, label %bb3 i32 9, label %bb4 i32 10, label %bb9 i32 11, label %bb2 i32 12, label %bb5 i32 13, label %bb11 ]
+bb:
+ tail call void(...)* @foo1()
+ ret void
+bb1:
+ tail call void(...)* @foo2()
+ ret void
+bb2:
+ tail call void(...)* @foo6()
+ ret void
+bb3:
+ tail call void(...)* @foo3()
+ ret void
+bb4:
+ tail call void(...)* @foo4()
+ ret void
+bb5:
+ tail call void(...)* @foo5()
+ ret void
+bb6:
+ tail call void(...)* @foo1()
+ ret void
+bb7:
+ tail call void(...)* @foo2()
+ ret void
+bb8:
+ tail call void(...)* @foo6()
+ ret void
+bb9:
+ tail call void(...)* @foo3()
+ ret void
+bb10:
+ tail call void(...)* @foo4()
+ ret void
+bb11:
+ tail call void(...)* @foo5()
+ ret void
+bb12:
+ tail call void(...)* @foo6()
+ ret void
+
+; LINUX: test8:
+; LINUX: call .L8$pb
+; LINUX: .L8$pb:
+; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref8-.L8$pb),
+; LINUX: addl .LJTI8_0@GOTOFF(
+; LINUX: jmpl *
+
+; LINUX: .LJTI8_0:
+; LINUX: .long .LBB8_2@GOTOFF
+; LINUX: .long .LBB8_2@GOTOFF
+; LINUX: .long .LBB8_7@GOTOFF
+; LINUX: .long .LBB8_3@GOTOFF
+; LINUX: .long .LBB8_7@GOTOFF
+}
+
+declare void @foo1(...)
+declare void @foo2(...)
+declare void @foo6(...)
+declare void @foo3(...)
+declare void @foo4(...)
+declare void @foo5(...)
diff --git a/test/CodeGen/X86/pic_jumptable.ll b/test/CodeGen/X86/pic_jumptable.ll
new file mode 100644
index 0000000..b3750c1
--- /dev/null
+++ b/test/CodeGen/X86/pic_jumptable.ll
@@ -0,0 +1,78 @@
+; RUN: llc < %s -relocation-model=pic -mtriple=i386-linux-gnu -asm-verbose=false | not grep -F .text
+; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | not grep lea
+; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | grep add | count 2
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep 'lJTI'
+; rdar://6971437
+
+declare void @_Z3bari(i32)
+
+define linkonce void @_Z3fooILi1EEvi(i32 %Y) nounwind {
+entry:
+ %Y_addr = alloca i32 ; <i32*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store i32 %Y, i32* %Y_addr
+ %tmp = load i32* %Y_addr ; <i32> [#uses=1]
+ switch i32 %tmp, label %bb10 [
+ i32 0, label %bb3
+ i32 1, label %bb
+ i32 2, label %bb
+ i32 3, label %bb
+ i32 4, label %bb
+ i32 5, label %bb
+ i32 6, label %bb
+ i32 7, label %bb
+ i32 8, label %bb
+ i32 9, label %bb
+ i32 10, label %bb
+ i32 12, label %bb1
+ i32 13, label %bb5
+ i32 14, label %bb6
+ i32 16, label %bb2
+ i32 17, label %bb4
+ i32 23, label %bb8
+ i32 27, label %bb7
+ i32 34, label %bb9
+ ]
+
+bb: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry
+ br label %bb1
+
+bb1: ; preds = %bb, %entry
+ br label %bb2
+
+bb2: ; preds = %bb1, %entry
+ call void @_Z3bari( i32 1 )
+ br label %bb11
+
+bb3: ; preds = %entry
+ br label %bb4
+
+bb4: ; preds = %bb3, %entry
+ br label %bb5
+
+bb5: ; preds = %bb4, %entry
+ br label %bb6
+
+bb6: ; preds = %bb5, %entry
+ call void @_Z3bari( i32 2 )
+ br label %bb11
+
+bb7: ; preds = %entry
+ br label %bb8
+
+bb8: ; preds = %bb7, %entry
+ br label %bb9
+
+bb9: ; preds = %bb8, %entry
+ call void @_Z3bari( i32 3 )
+ br label %bb11
+
+bb10: ; preds = %entry
+ br label %bb11
+
+bb11: ; preds = %bb10, %bb9, %bb6, %bb2
+ br label %return
+
+return: ; preds = %bb11
+ ret void
+}
diff --git a/test/CodeGen/X86/pmul.ll b/test/CodeGen/X86/pmul.ll
new file mode 100644
index 0000000..e2746a8
--- /dev/null
+++ b/test/CodeGen/X86/pmul.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=x86 -mattr=sse41 -stack-alignment=16 > %t
+; RUN: grep pmul %t | count 12
+; RUN: grep mov %t | count 12
+
+define <4 x i32> @a(<4 x i32> %i) nounwind {
+ %A = mul <4 x i32> %i, < i32 117, i32 117, i32 117, i32 117 >
+ ret <4 x i32> %A
+}
+define <2 x i64> @b(<2 x i64> %i) nounwind {
+ %A = mul <2 x i64> %i, < i64 117, i64 117 >
+ ret <2 x i64> %A
+}
+define <4 x i32> @c(<4 x i32> %i, <4 x i32> %j) nounwind {
+ %A = mul <4 x i32> %i, %j
+ ret <4 x i32> %A
+}
+define <2 x i64> @d(<2 x i64> %i, <2 x i64> %j) nounwind {
+ %A = mul <2 x i64> %i, %j
+ ret <2 x i64> %A
+}
+; Use a call to force spills.
+declare void @foo()
+define <4 x i32> @e(<4 x i32> %i, <4 x i32> %j) nounwind {
+ call void @foo()
+ %A = mul <4 x i32> %i, %j
+ ret <4 x i32> %A
+}
+define <2 x i64> @f(<2 x i64> %i, <2 x i64> %j) nounwind {
+ call void @foo()
+ %A = mul <2 x i64> %i, %j
+ ret <2 x i64> %A
+}
diff --git a/test/CodeGen/X86/postalloc-coalescing.ll b/test/CodeGen/X86/postalloc-coalescing.ll
new file mode 100644
index 0000000..a171436
--- /dev/null
+++ b/test/CodeGen/X86/postalloc-coalescing.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -march=x86 | grep mov | count 3
+
+define fastcc i32 @_Z18yy_get_next_bufferv() {
+entry:
+ br label %bb131
+
+bb116: ; preds = %bb131
+ %tmp125126 = trunc i32 %c.1 to i8 ; <i8> [#uses=1]
+ store i8 %tmp125126, i8* null, align 1
+ br label %bb131
+
+bb131: ; preds = %bb116, %entry
+ %c.2 = phi i32 [ %c.1, %bb116 ], [ 42, %entry ] ; <i32> [#uses=1]
+ %c.1 = select i1 false, i32 0, i32 %c.2 ; <i32> [#uses=4]
+ %tmp181 = icmp eq i32 %c.1, -1 ; <i1> [#uses=1]
+ br i1 %tmp181, label %bb158, label %bb116
+
+bb158: ; preds = %bb131
+ br i1 true, label %cond_true163, label %cond_next178
+
+cond_true163: ; preds = %bb158
+ %tmp172173 = trunc i32 %c.1 to i8 ; <i8> [#uses=1]
+ store i8 %tmp172173, i8* null, align 1
+ br label %cond_next178
+
+cond_next178: ; preds = %cond_true163, %bb158
+ %tmp180 = icmp eq i32 %c.1, -1 ; <i1> [#uses=1]
+ br i1 %tmp180, label %cond_next184, label %cond_next199
+
+cond_next184: ; preds = %cond_next178
+ ret i32 0
+
+cond_next199: ; preds = %cond_next178
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/powi.ll b/test/CodeGen/X86/powi.ll
new file mode 100644
index 0000000..c3d6831
--- /dev/null
+++ b/test/CodeGen/X86/powi.ll
@@ -0,0 +1,11 @@
+; RUN: llc %s -march=x86 -mcpu=yonah -o - | grep mulsd | count 6
+; Ideally this would compile to 5 multiplies.
+
+define double @_Z3f10d(double %a) nounwind readonly ssp noredzone {
+entry:
+ %0 = tail call double @llvm.powi.f64(double %a, i32 15) nounwind ; <double> [#uses=1]
+ ret double %0
+}
+
+declare double @llvm.powi.f64(double, i32) nounwind readonly
+
diff --git a/test/CodeGen/X86/pr1462.ll b/test/CodeGen/X86/pr1462.ll
new file mode 100644
index 0000000..62549a5
--- /dev/null
+++ b/test/CodeGen/X86/pr1462.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s
+; PR1462
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-
+v64:64:64-v128:128:128-a0:0:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+define hidden i128 @__addvti3(i128 %a1, i128 %b2) {
+entry:
+ %tmp8 = add i128 %b2, %a1 ; <i128> [#uses=3]
+ %tmp10 = icmp sgt i128 %b2, -1 ; <i1> [#uses=1]
+ %tmp18 = icmp sgt i128 %tmp8, %a1 ; <i1> [#uses=1]
+ %tmp14 = icmp slt i128 %tmp8, %a1 ; <i1> [#uses=1]
+ %iftmp.0.0.in = select i1 %tmp10, i1 %tmp14, i1 %tmp18 ; <i1> [#uses=1]
+ br i1 %iftmp.0.0.in, label %cond_true22, label %cond_next23
+
+cond_true22: ; preds = %entry
+ tail call void @abort( )
+ unreachable
+
+cond_next23: ; preds = %entry
+ ret i128 %tmp8
+}
+
+declare void @abort()
diff --git a/test/CodeGen/X86/pr1489.ll b/test/CodeGen/X86/pr1489.ll
new file mode 100644
index 0000000..c9e24bf
--- /dev/null
+++ b/test/CodeGen/X86/pr1489.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -disable-fp-elim -O0 -mcpu=i486 | grep 1082126238 | count 3
+; RUN: llc < %s -disable-fp-elim -O0 -mcpu=i486 | grep -- -1236950581 | count 1
+;; magic constants are 3.999f and half of 3.999
+; ModuleID = '1489.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
[email protected] = internal constant [13 x i8] c"%d %d %d %d\0A\00" ; <[13 x i8]*> [#uses=1]
+
+define i32 @quux() nounwind {
+entry:
+ %tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; <i32> [#uses=1]
+ %tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1]
+ %tmp23 = zext i1 %tmp2 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp23
+}
+
+declare i32 @lrintf(float)
+
+define i32 @foo() nounwind {
+entry:
+ %tmp1 = tail call i32 @lrint( double 3.999000e+00 ) ; <i32> [#uses=1]
+ %tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1]
+ %tmp23 = zext i1 %tmp2 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp23
+}
+
+declare i32 @lrint(double)
+
+define i32 @bar() nounwind {
+entry:
+ %tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; <i32> [#uses=1]
+ %tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1]
+ %tmp23 = zext i1 %tmp2 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp23
+}
+
+define i32 @baz() nounwind {
+entry:
+ %tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; <i32> [#uses=1]
+ %tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1]
+ %tmp23 = zext i1 %tmp2 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp23
+}
+
+define i32 @main() nounwind {
+entry:
+ %tmp = tail call i32 @baz( ) ; <i32> [#uses=1]
+ %tmp1 = tail call i32 @bar( ) ; <i32> [#uses=1]
+ %tmp2 = tail call i32 @foo( ) ; <i32> [#uses=1]
+ %tmp3 = tail call i32 @quux( ) ; <i32> [#uses=1]
+ %tmp5 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([13 x i8]* @.str, i32 0, i32 0), i32 %tmp3, i32 %tmp2, i32 %tmp1, i32 %tmp ) ; <i32> [#uses=0]
+ ret i32 undef
+}
+
+declare i32 @printf(i8*, ...)
diff --git a/test/CodeGen/X86/pr1505.ll b/test/CodeGen/X86/pr1505.ll
new file mode 100644
index 0000000..883a806
--- /dev/null
+++ b/test/CodeGen/X86/pr1505.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mcpu=i486 | not grep fldl
+; PR1505
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+@G = weak global float 0.000000e+00 ; <float*> [#uses=1]
+
+define void @t1(float %F) {
+entry:
+ store float %F, float* @G
+ ret void
+}
diff --git a/test/CodeGen/X86/pr1505b.ll b/test/CodeGen/X86/pr1505b.ll
new file mode 100644
index 0000000..12736cd
--- /dev/null
+++ b/test/CodeGen/X86/pr1505b.ll
@@ -0,0 +1,59 @@
+; RUN: llc < %s -mcpu=i486 | grep fstpl | count 4
+; RUN: llc < %s -mcpu=i486 | grep fstps | count 3
+; PR1505
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "i686-apple-darwin8"
+ %"struct.std::basic_ios<char,std::char_traits<char> >" = type { %"struct.std::ios_base", %"struct.std::basic_ostream<char,std::char_traits<char> >"*, i8, i8, %"struct.std::basic_streambuf<char,std::char_traits<char> >"*, %"struct.std::ctype<char>"*, %"struct.std::num_get<char,std::istreambuf_iterator<char, std::char_traits<char> > >"*, %"struct.std::num_get<char,std::istreambuf_iterator<char, std::char_traits<char> > >"* }
+ %"struct.std::basic_ostream<char,std::char_traits<char> >" = type { i32 (...)**, %"struct.std::basic_ios<char,std::char_traits<char> >" }
+ %"struct.std::basic_streambuf<char,std::char_traits<char> >" = type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %"struct.std::locale" }
+ %"struct.std::ctype<char>" = type { %"struct.std::locale::facet", i32*, i8, i32*, i32*, i32*, i8, [256 x i8], [256 x i8], i8 }
+ %"struct.std::ctype_base" = type <{ i8 }>
+ %"struct.std::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, %"struct.std::ios_base::_Callback_list"*, %"struct.std::ios_base::_Words", [8 x %"struct.std::ios_base::_Words"], i32, %"struct.std::ios_base::_Words"*, %"struct.std::locale" }
+ %"struct.std::ios_base::_Callback_list" = type { %"struct.std::ios_base::_Callback_list"*, void (i32, %"struct.std::ios_base"*, i32)*, i32, i32 }
+ %"struct.std::ios_base::_Words" = type { i8*, i32 }
+ %"struct.std::locale" = type { %"struct.std::locale::_Impl"* }
+ %"struct.std::locale::_Impl" = type { i32, %"struct.std::locale::facet"**, i32, %"struct.std::locale::facet"**, i8** }
+ %"struct.std::locale::facet" = type { i32 (...)**, i32 }
+ %"struct.std::num_get<char,std::istreambuf_iterator<char, std::char_traits<char> > >" = type { %"struct.std::locale::facet" }
+@a = global float 0x3FD3333340000000 ; <float*> [#uses=1]
+@b = global double 6.000000e-01, align 8 ; <double*> [#uses=1]
+@_ZSt8__ioinit = internal global %"struct.std::ctype_base" zeroinitializer ; <%"struct.std::ctype_base"*> [#uses=2]
+@__dso_handle = external global i8* ; <i8**> [#uses=1]
+@_ZSt4cout = external global %"struct.std::basic_ostream<char,std::char_traits<char> >" ; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=2]
[email protected] = internal constant [12 x i8] c"tan float: \00" ; <[12 x i8]*> [#uses=1]
[email protected] = internal constant [13 x i8] c"tan double: \00" ; <[13 x i8]*> [#uses=1]
+
+declare void @_ZNSt8ios_base4InitD1Ev(%"struct.std::ctype_base"*)
+
+declare void @_ZNSt8ios_base4InitC1Ev(%"struct.std::ctype_base"*)
+
+declare i32 @__cxa_atexit(void (i8*)*, i8*, i8*)
+
+define i32 @main() {
+entry:
+ %tmp6 = volatile load float* @a ; <float> [#uses=1]
+ %tmp9 = tail call float @tanf( float %tmp6 ) ; <float> [#uses=1]
+ %tmp12 = volatile load double* @b ; <double> [#uses=1]
+ %tmp13 = tail call double @tan( double %tmp12 ) ; <double> [#uses=1]
+ %tmp1314 = fptrunc double %tmp13 to float ; <float> [#uses=1]
+ %tmp16 = tail call %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc( %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZSt4cout, i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0) ) ; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=1]
+ %tmp1920 = fpext float %tmp9 to double ; <double> [#uses=1]
+ %tmp22 = tail call %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZNSolsEd( %"struct.std::basic_ostream<char,std::char_traits<char> >"* %tmp16, double %tmp1920 ) ; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=1]
+ %tmp30 = tail call %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_( %"struct.std::basic_ostream<char,std::char_traits<char> >"* %tmp22 ) ; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=0]
+ %tmp34 = tail call %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc( %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZSt4cout, i8* getelementptr ([13 x i8]* @.str1, i32 0, i32 0) ) ; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=1]
+ %tmp3940 = fpext float %tmp1314 to double ; <double> [#uses=1]
+ %tmp42 = tail call %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZNSolsEd( %"struct.std::basic_ostream<char,std::char_traits<char> >"* %tmp34, double %tmp3940 ) ; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=1]
+ %tmp51 = tail call %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_( %"struct.std::basic_ostream<char,std::char_traits<char> >"* %tmp42 ) ; <%"struct.std::basic_ostream<char,std::char_traits<char> >"*> [#uses=0]
+ ret i32 0
+}
+
+declare float @tanf(float)
+
+declare double @tan(double)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, i8*)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZNSolsEd(%"struct.std::basic_ostream<char,std::char_traits<char> >"*, double)
+
+declare %"struct.std::basic_ostream<char,std::char_traits<char> >"* @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_(%"struct.std::basic_ostream<char,std::char_traits<char> >"*)
diff --git a/test/CodeGen/X86/pr2177.ll b/test/CodeGen/X86/pr2177.ll
new file mode 100644
index 0000000..e941bf7
--- /dev/null
+++ b/test/CodeGen/X86/pr2177.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s
+; PR2177
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin9.1.0"
+ %struct.S2259 = type { <4 x i16>, i8, i64 }
+
+define void @check2259va(i32 %z, ...) {
+entry:
+ br i1 false, label %bb5, label %return
+bb5: ; preds = %entry
+ switch i32 0, label %bb155 [
+ i32 16, label %bb10
+ i32 17, label %bb118
+ i32 18, label %bb54
+ i32 32, label %bb118
+ i32 33, label %bb118
+ i32 36, label %bb118
+ ]
+bb10: ; preds = %bb5
+ ret void
+bb54: ; preds = %bb5
+ ret void
+bb118: ; preds = %bb5, %bb5, %bb5, %bb5
+ %tmp125 = load i8** null, align 8 ; <i8*> [#uses=1]
+ %tmp125126 = bitcast i8* %tmp125 to %struct.S2259* ; <%struct.S2259*> [#uses=1]
+ %tmp128 = getelementptr %struct.S2259* %tmp125126, i32 0, i32 0 ; <<4 x i16>*> [#uses=1]
+ %tmp129 = load <4 x i16>* %tmp128, align 8 ; <<4 x i16>> [#uses=1]
+ store <4 x i16> %tmp129, <4 x i16>* null, align 8
+ ret void
+bb155: ; preds = %bb5
+ ret void
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/pr2182.ll b/test/CodeGen/X86/pr2182.ll
new file mode 100644
index 0000000..f97663c
--- /dev/null
+++ b/test/CodeGen/X86/pr2182.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s | grep {addl \$3, (%eax)} | count 4
+; PR2182
+
+target datalayout =
+"e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+@x = weak global i32 0 ; <i32*> [#uses=8]
+
+define void @loop_2() nounwind {
+entry:
+ %tmp = volatile load i32* @x, align 4 ; <i32> [#uses=1]
+ %tmp1 = add i32 %tmp, 3 ; <i32> [#uses=1]
+ volatile store i32 %tmp1, i32* @x, align 4
+ %tmp.1 = volatile load i32* @x, align 4 ; <i32> [#uses=1]
+ %tmp1.1 = add i32 %tmp.1, 3 ; <i32> [#uses=1]
+ volatile store i32 %tmp1.1, i32* @x, align 4
+ %tmp.2 = volatile load i32* @x, align 4 ; <i32> [#uses=1]
+ %tmp1.2 = add i32 %tmp.2, 3 ; <i32> [#uses=1]
+ volatile store i32 %tmp1.2, i32* @x, align 4
+ %tmp.3 = volatile load i32* @x, align 4 ; <i32> [#uses=1]
+ %tmp1.3 = add i32 %tmp.3, 3 ; <i32> [#uses=1]
+ volatile store i32 %tmp1.3, i32* @x, align 4
+ ret void
+}
diff --git a/test/CodeGen/X86/pr2326.ll b/test/CodeGen/X86/pr2326.ll
new file mode 100644
index 0000000..f82dcb5
--- /dev/null
+++ b/test/CodeGen/X86/pr2326.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 | grep sete
+; PR2326
+
+define i32 @func_59(i32 %p_60) nounwind {
+entry:
+ %l_108 = alloca i32 ; <i32*> [#uses=2]
+ %tmp15 = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp16 = load i32* %l_108, align 4 ; <i32> [#uses=1]
+ %tmp17 = icmp eq i32 %tmp15, %tmp16 ; <i1> [#uses=1]
+ %tmp1718 = zext i1 %tmp17 to i8 ; <i8> [#uses=1]
+ %tmp19 = load i32* null, align 4 ; <i32> [#uses=1]
+ %tmp20 = load i32* %l_108, align 4 ; <i32> [#uses=1]
+ %tmp21 = icmp ule i32 %tmp19, %tmp20 ; <i1> [#uses=1]
+ %tmp2122 = zext i1 %tmp21 to i8 ; <i8> [#uses=1]
+ %toBool23 = icmp ne i8 %tmp1718, 0 ; <i1> [#uses=1]
+ %toBool24 = icmp ne i8 %tmp2122, 0 ; <i1> [#uses=1]
+ %tmp25 = and i1 %toBool23, %toBool24 ; <i1> [#uses=1]
+ %tmp2526 = zext i1 %tmp25 to i8 ; <i8> [#uses=1]
+ %tmp252627 = zext i8 %tmp2526 to i32 ; <i32> [#uses=1]
+ %tmp29 = call i32 (...)* @func_15( i32 %tmp252627, i32 0 ) nounwind ; <i32> [#uses=0]
+ unreachable
+}
+
+declare i32 @func_15(...)
diff --git a/test/CodeGen/X86/pr2623.ll b/test/CodeGen/X86/pr2623.ll
new file mode 100644
index 0000000..5d0eb5d
--- /dev/null
+++ b/test/CodeGen/X86/pr2623.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s
+; PR2623
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-unknown-freebsd7.0"
+ %.objc_id = type { %.objc_id }*
+ %.objc_selector = type { i8*, i8* }*
[email protected]_sel_ptr = external constant %.objc_selector ; <%.objc_selector*> [#uses=1]
[email protected]_sel_ptr13 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1]
[email protected]_sel_ptr14 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1]
[email protected]_sel_ptr15 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1]
[email protected]_sel_ptr16 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1]
[email protected]_sel_ptr17 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1]
[email protected]_sel_ptr18 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1]
[email protected]_sel_ptr19 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1]
[email protected]_sel_ptr20 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1]
[email protected]_sel_ptr21 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1]
+
[email protected]_untyped_selector_alias = alias internal %.objc_selector* @.objc_sel_ptr15 ; <%.objc_selector*> [#uses=0]
[email protected]_untyped_selector_alias1 = alias internal %.objc_selector* @.objc_sel_ptr ; <%.objc_selector*> [#uses=0]
[email protected]_untyped_selector_alias2 = alias internal %.objc_selector* @.objc_sel_ptr17 ; <%.objc_selector*> [#uses=0]
[email protected]_untyped_selector_alias3 = alias internal %.objc_selector* @.objc_sel_ptr16 ; <%.objc_selector*> [#uses=0]
[email protected]_untyped_selector_alias4 = alias internal %.objc_selector* @.objc_sel_ptr13 ; <%.objc_selector*> [#uses=0]
[email protected]_untyped_selector_alias7 = alias internal %.objc_selector* @.objc_sel_ptr14 ; <%.objc_selector*> [#uses=0]
+@getRange = alias internal %.objc_selector* @.objc_sel_ptr18 ; <%.objc_selector*> [#uses=0]
+@"valueWithRange:" = alias internal %.objc_selector* @.objc_sel_ptr21 ; <%.objc_selector*> [#uses=0]
+@rangeValue = alias internal %.objc_selector* @.objc_sel_ptr20 ; <%.objc_selector*> [#uses=0]
+@"printRange:" = alias internal %.objc_selector* @.objc_sel_ptr19 ; <%.objc_selector*> [#uses=0]
+
+define void @"._objc_method_SmalltalkTool()-run"(i8* %self, %.objc_selector %_cmd) {
+entry:
+ br i1 false, label %small_int_messagerangeValue, label %real_object_messagerangeValue
+
+small_int_messagerangeValue: ; preds = %entry
+ br label %Continue
+
+real_object_messagerangeValue: ; preds = %entry
+ br label %Continue
+
+Continue: ; preds = %real_object_messagerangeValue, %small_int_messagerangeValue
+ %rangeValue = phi { i32, i32 } [ undef, %small_int_messagerangeValue ], [ undef, %real_object_messagerangeValue ] ; <{ i32, i32 }> [#uses=1]
+ call void (%.objc_id, %.objc_selector, ...)* null( %.objc_id null, %.objc_selector null, { i32, i32 } %rangeValue )
+ ret void
+}
diff --git a/test/CodeGen/X86/pr2656.ll b/test/CodeGen/X86/pr2656.ll
new file mode 100644
index 0000000..afd7114
--- /dev/null
+++ b/test/CodeGen/X86/pr2656.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {xorps.\*sp} | count 1
+; PR2656
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin9.4.0"
+ %struct.anon = type <{ float, float }>
[email protected] = internal constant [17 x i8] c"pt: %.0f, %.0f\0A\00\00" ; <[17 x i8]*> [#uses=1]
+
+define void @foo(%struct.anon* byval %p) nounwind {
+entry:
+ %tmp = getelementptr %struct.anon* %p, i32 0, i32 0 ; <float*> [#uses=1]
+ %tmp1 = load float* %tmp ; <float> [#uses=1]
+ %tmp2 = getelementptr %struct.anon* %p, i32 0, i32 1 ; <float*> [#uses=1]
+ %tmp3 = load float* %tmp2 ; <float> [#uses=1]
+ %neg = fsub float -0.000000e+00, %tmp1 ; <float> [#uses=1]
+ %conv = fpext float %neg to double ; <double> [#uses=1]
+ %neg4 = fsub float -0.000000e+00, %tmp3 ; <float> [#uses=1]
+ %conv5 = fpext float %neg4 to double ; <double> [#uses=1]
+ %call = call i32 (...)* @printf( i8* getelementptr ([17 x i8]* @.str, i32 0, i32 0), double %conv, double %conv5 ) ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @printf(...)
diff --git a/test/CodeGen/X86/pr2659.ll b/test/CodeGen/X86/pr2659.ll
new file mode 100644
index 0000000..0760e4c
--- /dev/null
+++ b/test/CodeGen/X86/pr2659.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 5
+; PR2659
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin9.4.0"
+
+define i32 @binomial(i32 %n, i32 %k) nounwind {
+entry:
+ %cmp = icmp ugt i32 %k, %n ; <i1> [#uses=1]
+ br i1 %cmp, label %ifthen, label %forcond.preheader
+
+forcond.preheader: ; preds = %entry
+ %cmp44 = icmp eq i32 %k, 0 ; <i1> [#uses=1]
+ br i1 %cmp44, label %afterfor, label %forbody
+
+ifthen: ; preds = %entry
+ ret i32 0
+
+forbody: ; preds = %forbody, %forcond.preheader
+ %indvar = phi i32 [ 0, %forcond.preheader ], [ %divisor.02, %forbody ] ; <i32> [#uses=3]
+ %accumulator.01 = phi i32 [ 1, %forcond.preheader ], [ %div, %forbody ] ; <i32> [#uses=1]
+ %divisor.02 = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %n.addr.03 = sub i32 %n, %indvar ; <i32> [#uses=1]
+ %mul = mul i32 %n.addr.03, %accumulator.01 ; <i32> [#uses=1]
+ %div = udiv i32 %mul, %divisor.02 ; <i32> [#uses=2]
+ %inc = add i32 %indvar, 2 ; <i32> [#uses=1]
+ %cmp4 = icmp ugt i32 %inc, %k ; <i1> [#uses=1]
+ br i1 %cmp4, label %afterfor, label %forbody
+
+afterfor: ; preds = %forbody, %forcond.preheader
+ %accumulator.0.lcssa = phi i32 [ 1, %forcond.preheader ], [ %div, %forbody ] ; <i32> [#uses=1]
+ ret i32 %accumulator.0.lcssa
+}
diff --git a/test/CodeGen/X86/pr2849.ll b/test/CodeGen/X86/pr2849.ll
new file mode 100644
index 0000000..0fec481
--- /dev/null
+++ b/test/CodeGen/X86/pr2849.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s
+; PR2849
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+ %struct.BaseBoundPtrs = type { i8*, i8* }
+ %struct.HashEntry = type { %struct.BaseBoundPtrs }
+ %struct.NODE = type { i8, i8, %struct.anon }
+ %struct.anon = type { %struct.xlist }
+ %struct.xlist = type { %struct.NODE*, %struct.NODE* }
+ %struct.xvect = type { %struct.NODE** }
+@hash_table_begin = external global %struct.HashEntry*
+
+define void @obshow() {
+entry:
+ %tmp = load %struct.HashEntry** @hash_table_begin, align 8
+ br i1 false, label %xlygetvalue.exit, label %xlygetvalue.exit
+
+xlygetvalue.exit:
+ %storemerge.in.i = phi %struct.NODE** [ null, %entry ], [ null, %entry ]
+ %storemerge.i = load %struct.NODE** %storemerge.in.i
+ %tmp1 = ptrtoint %struct.NODE** %storemerge.in.i to i64
+ %tmp2 = lshr i64 %tmp1, 3
+ %tmp3 = and i64 %tmp2, 2147483647
+ %tmp4 = getelementptr %struct.HashEntry* %tmp, i64 %tmp3, i32 0, i32 1
+ %tmp7 = load i8** %tmp4, align 8
+ %tmp8 = getelementptr %struct.NODE* %storemerge.i, i64 0, i32 2
+ %tmp9 = bitcast %struct.anon* %tmp8 to %struct.NODE***
+ %tmp11 = load %struct.NODE*** %tmp9, align 8
+ %tmp12 = ptrtoint %struct.NODE** %tmp11 to i64
+ %tmp13 = lshr i64 %tmp12, 3
+ %tmp14 = and i64 %tmp13, 2147483647
+ %tmp15 = getelementptr %struct.HashEntry* %tmp, i64 %tmp14, i32 0, i32 1
+ call fastcc void @xlprint(i8** %tmp4, i8* %tmp7, i8** %tmp15)
+ ret void
+}
+
+declare fastcc void @xlprint(i8**, i8*, i8**)
diff --git a/test/CodeGen/X86/pr2924.ll b/test/CodeGen/X86/pr2924.ll
new file mode 100644
index 0000000..b9e8dc1
--- /dev/null
+++ b/test/CodeGen/X86/pr2924.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s
+; PR2924
+
+target datalayout =
+"e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i686-pc-linux-gnu"
+
+define x86_stdcallcc { i32, i8* } @_D3std6string7toupperFAaZAa({ i32, i8* } %s) {
+entry_std.string.toupper:
+ %tmp58 = load i32* null
+ %tmp59 = icmp eq i32 %tmp58, 0
+ %r.val = load { i32, i8* }* null, align 8
+ %condtmp.0 = select i1 %tmp59, { i32, i8* } undef, { i32, i8* } %r.val
+
+ ret { i32, i8* } %condtmp.0
+}
+define { } @empty({ } %s) {
+entry_std.string.toupper:
+ %tmp58 = load i32* null
+ %tmp59 = icmp eq i32 %tmp58, 0
+ %r.val = load { }* null, align 8
+ %condtmp.0 = select i1 %tmp59, { } undef, { } %r.val
+ ret { } %condtmp.0
+}
diff --git a/test/CodeGen/X86/pr2982.ll b/test/CodeGen/X86/pr2982.ll
new file mode 100644
index 0000000..3f9a595
--- /dev/null
+++ b/test/CodeGen/X86/pr2982.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86
+; PR2982
+
+target datalayout =
+"e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.5"
+@g_279 = external global i32 ; <i32*> [#uses=1]
+@g_265 = external global i32 ; <i32*> [#uses=1]
+@g_3 = external global i8 ; <i8*> [#uses=1]
+
+declare i32 @rshift_u_u(...)
+
+define void @bar() nounwind {
+entry:
+ %0 = load i32* @g_279, align 4 ; <i32> [#uses=1]
+ %1 = shl i32 %0, 1 ; <i32> [#uses=1]
+ %2 = and i32 %1, 2 ; <i32> [#uses=1]
+ %3 = load i32* @g_265, align 4 ; <i32> [#uses=1]
+ %4 = load i8* @g_3, align 1 ; <i8> [#uses=1]
+ %5 = sext i8 %4 to i32 ; <i32> [#uses=1]
+ %6 = add i32 %2, %3 ; <i32> [#uses=1]
+ %7 = add i32 %6, %5 ; <i32> [#uses=1]
+ %8 = tail call i32 (...)* @rshift_u_u(i32 %7, i32 0) nounwind
+; <i32> [#uses=0]
+ ret void
+}
diff --git a/test/CodeGen/X86/pr3154.ll b/test/CodeGen/X86/pr3154.ll
new file mode 100644
index 0000000..18df97c
--- /dev/null
+++ b/test/CodeGen/X86/pr3154.ll
@@ -0,0 +1,104 @@
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu -mattr=+sse2
+; RUN: llc < %s -mtriple=i386-pc-linux-gnu -mattr=+sse2 -relocation-model=pic -disable-fp-elim
+; PR3154
+
+define void @ff_flac_compute_autocorr_sse2(i32* %data, i32 %len, i32 %lag, double* %autoc) nounwind {
+entry:
+ %c = alloca double, align 8 ; <double*> [#uses=2]
+ %0 = add i32 %len, 2 ; <i32> [#uses=1]
+ %1 = add i32 %0, %lag ; <i32> [#uses=1]
+ %2 = alloca double, i32 %1 ; <double*> [#uses=2]
+ %3 = getelementptr double* %2, i32 %lag ; <double*> [#uses=2]
+ %4 = ptrtoint double* %3 to i32 ; <i32> [#uses=1]
+ %5 = and i32 %4, 8 ; <i32> [#uses=1]
+ %6 = icmp eq i32 %5, 0 ; <i1> [#uses=1]
+ br i1 %6, label %bb19, label %bb
+
+bb: ; preds = %entry
+ %.sum = add i32 %lag, 1 ; <i32> [#uses=1]
+ %7 = getelementptr double* %2, i32 %.sum ; <double*> [#uses=1]
+ br label %bb19
+
+bb19: ; preds = %bb, %entry
+ %data15.0 = phi double* [ %7, %bb ], [ %3, %entry ] ; <double*> [#uses=5]
+ %8 = sitofp i32 %len to double ; <double> [#uses=1]
+ %9 = fsub double %8, 1.000000e+00 ; <double> [#uses=1]
+ %10 = fdiv double 2.000000e+00, %9 ; <double> [#uses=1]
+ store double %10, double* %c, align 8
+ %11 = ashr i32 %len, 1 ; <i32> [#uses=3]
+ %12 = mul i32 %11, -4 ; <i32> [#uses=2]
+ %13 = shl i32 %len, 1 ; <i32> [#uses=1]
+ %14 = and i32 %13, -4 ; <i32> [#uses=2]
+ call void asm sideeffect "movsd $0, %xmm7 \0A\09movapd ff_pd_1, %xmm6 \0A\09movapd ff_pd_2, %xmm5 \0A\09movlhps %xmm7, %xmm7 \0A\09subpd %xmm5, %xmm7 \0A\09addsd %xmm6, %xmm7 \0A\09", "*m,~{dirflag},~{fpsr},~{flags}"(double* %c) nounwind
+ %15 = and i32 %len, 1 ; <i32> [#uses=1]
+ %toBool = icmp eq i32 %15, 0 ; <i1> [#uses=1]
+ %16 = getelementptr double* %data15.0, i32 %11 ; <double*> [#uses=2]
+ %17 = getelementptr i32* %data, i32 %11 ; <i32*> [#uses=2]
+ br i1 %toBool, label %bb22, label %bb20
+
+bb20: ; preds = %bb19
+ %asmtmp = call { i32, i32 } asm sideeffect "1: \0A\09movapd %xmm7, %xmm1 \0A\09mulpd %xmm1, %xmm1 \0A\09movapd %xmm6, %xmm0 \0A\09subpd %xmm1, %xmm0 \0A\09pshufd $$0x4e, %xmm0, %xmm1 \0A\09cvtpi2pd ($3,$0), %xmm2 \0A\09cvtpi2pd -1*4($3,$1), %xmm3 \0A\09mulpd %xmm0, %xmm2 \0A\09mulpd %xmm1, %xmm3 \0A\09movapd %xmm2, ($2,$0,2) \0A\09movupd %xmm3, -1*8($2,$1,2) \0A\09subpd %xmm5, %xmm7 \0A\09sub $$8, $1 \0A\09add $$8, $0 \0A\09jl 1b \0A\09", "=&r,=&r,r,r,0,1,~{dirflag},~{fpsr},~{flags}"(double* %16, i32* %17, i32 %12, i32 %14) nounwind ; <{ i32, i32 }> [#uses=0]
+ br label %bb28.preheader
+
+bb22: ; preds = %bb19
+ %asmtmp23 = call { i32, i32 } asm sideeffect "1: \0A\09movapd %xmm7, %xmm1 \0A\09mulpd %xmm1, %xmm1 \0A\09movapd %xmm6, %xmm0 \0A\09subpd %xmm1, %xmm0 \0A\09pshufd $$0x4e, %xmm0, %xmm1 \0A\09cvtpi2pd ($3,$0), %xmm2 \0A\09cvtpi2pd -2*4($3,$1), %xmm3 \0A\09mulpd %xmm0, %xmm2 \0A\09mulpd %xmm1, %xmm3 \0A\09movapd %xmm2, ($2,$0,2) \0A\09movapd %xmm3, -2*8($2,$1,2) \0A\09subpd %xmm5, %xmm7 \0A\09sub $$8, $1 \0A\09add $$8, $0 \0A\09jl 1b \0A\09", "=&r,=&r,r,r,0,1,~{dirflag},~{fpsr},~{flags}"(double* %16, i32* %17, i32 %12, i32 %14) nounwind ; <{ i32, i32 }> [#uses=0]
+ br label %bb28.preheader
+
+bb28.preheader: ; preds = %bb22, %bb20
+ %18 = icmp sgt i32 %lag, 0 ; <i1> [#uses=2]
+ br i1 %18, label %bb27, label %bb29
+
+bb27: ; preds = %bb27, %bb28.preheader
+ %j4.042 = phi i32 [ 0, %bb28.preheader ], [ %indvar.next45, %bb27 ] ; <i32> [#uses=2]
+ %19 = sub i32 %j4.042, %lag ; <i32> [#uses=1]
+ %20 = getelementptr double* %data15.0, i32 %19 ; <double*> [#uses=1]
+ store double 0.000000e+00, double* %20, align 8
+ %indvar.next45 = add i32 %j4.042, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next45, %lag ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb29, label %bb27
+
+bb29: ; preds = %bb27, %bb28.preheader
+ %21 = getelementptr double* %data15.0, i32 %len ; <double*> [#uses=3]
+ store double 0.000000e+00, double* %21, align 8
+ br i1 %18, label %bb.nph, label %bb37
+
+bb.nph: ; preds = %bb29
+ %22 = mul i32 %len, -8 ; <i32> [#uses=2]
+ %23 = add i32 %lag, -2 ; <i32> [#uses=1]
+ br label %bb30
+
+bb30: ; preds = %bb35, %bb.nph
+ %indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb35 ] ; <i32> [#uses=2]
+ %j4.141 = shl i32 %indvar, 1 ; <i32> [#uses=8]
+ %24 = icmp eq i32 %23, %j4.141 ; <i1> [#uses=1]
+ %25 = or i32 %j4.141, 1 ; <i32> [#uses=2]
+ br i1 %24, label %bb31, label %bb33
+
+bb31: ; preds = %bb30
+ %26 = add i32 %j4.141, 2 ; <i32> [#uses=2]
+ %.sum38 = sub i32 %len, %j4.141 ; <i32> [#uses=1]
+ %27 = getelementptr double* %data15.0, i32 %.sum38 ; <double*> [#uses=1]
+ %28 = getelementptr double* %autoc, i32 %j4.141 ; <double*> [#uses=1]
+ %29 = getelementptr double* %autoc, i32 %25 ; <double*> [#uses=1]
+ %30 = getelementptr double* %autoc, i32 %26 ; <double*> [#uses=1]
+ %asmtmp32 = call i32 asm sideeffect "movsd ff_pd_1, %xmm0 \0A\09movsd ff_pd_1, %xmm1 \0A\09movsd ff_pd_1, %xmm2 \0A\091: \0A\09movapd ($4,$0), %xmm3 \0A\09movupd -8($5,$0), %xmm4 \0A\09movapd ($5,$0), %xmm5 \0A\09mulpd %xmm3, %xmm4 \0A\09mulpd %xmm3, %xmm5 \0A\09mulpd -16($5,$0), %xmm3 \0A\09addpd %xmm4, %xmm1 \0A\09addpd %xmm5, %xmm0 \0A\09addpd %xmm3, %xmm2 \0A\09add $$16, $0 \0A\09jl 1b \0A\09movhlps %xmm0, %xmm3 \0A\09movhlps %xmm1, %xmm4 \0A\09movhlps %xmm2, %xmm5 \0A\09addsd %xmm3, %xmm0 \0A\09addsd %xmm4, %xmm1 \0A\09addsd %xmm5, %xmm2 \0A\09movsd %xmm0, $1 \0A\09movsd %xmm1, $2 \0A\09movsd %xmm2, $3 \0A\09", "=&r,=*m,=*m,=*m,r,r,0,~{dirflag},~{fpsr},~{flags}"(double* %28, double* %29, double* %30, double* %21, double* %27, i32 %22) nounwind ; <i32> [#uses=0]
+ br label %bb35
+
+bb33: ; preds = %bb30
+ %.sum39 = sub i32 %len, %j4.141 ; <i32> [#uses=1]
+ %31 = getelementptr double* %data15.0, i32 %.sum39 ; <double*> [#uses=1]
+ %32 = getelementptr double* %autoc, i32 %j4.141 ; <double*> [#uses=1]
+ %33 = getelementptr double* %autoc, i32 %25 ; <double*> [#uses=1]
+ %asmtmp34 = call i32 asm sideeffect "movsd ff_pd_1, %xmm0 \0A\09movsd ff_pd_1, %xmm1 \0A\091: \0A\09movapd ($3,$0), %xmm3 \0A\09movupd -8($4,$0), %xmm4 \0A\09mulpd %xmm3, %xmm4 \0A\09mulpd ($4,$0), %xmm3 \0A\09addpd %xmm4, %xmm1 \0A\09addpd %xmm3, %xmm0 \0A\09add $$16, $0 \0A\09jl 1b \0A\09movhlps %xmm0, %xmm3 \0A\09movhlps %xmm1, %xmm4 \0A\09addsd %xmm3, %xmm0 \0A\09addsd %xmm4, %xmm1 \0A\09movsd %xmm0, $1 \0A\09movsd %xmm1, $2 \0A\09", "=&r,=*m,=*m,r,r,0,~{dirflag},~{fpsr},~{flags}"(double* %32, double* %33, double* %21, double* %31, i32 %22) nounwind ; <i32> [#uses=0]
+ %.pre = add i32 %j4.141, 2 ; <i32> [#uses=1]
+ br label %bb35
+
+bb35: ; preds = %bb33, %bb31
+ %.pre-phi = phi i32 [ %.pre, %bb33 ], [ %26, %bb31 ] ; <i32> [#uses=1]
+ %34 = icmp slt i32 %.pre-phi, %lag ; <i1> [#uses=1]
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br i1 %34, label %bb30, label %bb37
+
+bb37: ; preds = %bb35, %bb29
+ ret void
+}
diff --git a/test/CodeGen/X86/pr3216.ll b/test/CodeGen/X86/pr3216.ll
new file mode 100644
index 0000000..38c9f32
--- /dev/null
+++ b/test/CodeGen/X86/pr3216.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 | grep {sar. \$5}
+
+@foo = global i8 127
+
+define i32 @main() nounwind {
+entry:
+ %tmp = load i8* @foo
+ %bf.lo = lshr i8 %tmp, 5
+ %bf.lo.cleared = and i8 %bf.lo, 7
+ %0 = shl i8 %bf.lo.cleared, 5
+ %bf.val.sext = ashr i8 %0, 5
+ %conv = sext i8 %bf.val.sext to i32
+ ret i32 %conv
+}
diff --git a/test/CodeGen/X86/pr3241.ll b/test/CodeGen/X86/pr3241.ll
new file mode 100644
index 0000000..2f7917b
--- /dev/null
+++ b/test/CodeGen/X86/pr3241.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=x86
+; PR3241
+
+@g_620 = external global i32
+
+define void @func_18(i32 %p_21) nounwind {
+entry:
+ %t0 = call i32 @func_31(i32 %p_21) nounwind
+ %t1 = call i32 @safe_add_macro_uint32_t_u_u() nounwind
+ %t2 = icmp sgt i32 %t1, 0
+ %t3 = zext i1 %t2 to i32
+ %t4 = load i32* @g_620, align 4
+ %t5 = icmp eq i32 %t3, %t4
+ %t6 = xor i32 %p_21, 1
+ %t7 = call i32 @func_55(i32 %t6) nounwind
+ br i1 %t5, label %return, label %bb
+
+bb:
+ unreachable
+
+return:
+ unreachable
+}
+
+declare i32 @func_31(i32)
+
+declare i32 @safe_add_macro_uint32_t_u_u()
+
+declare i32 @func_55(i32)
diff --git a/test/CodeGen/X86/pr3243.ll b/test/CodeGen/X86/pr3243.ll
new file mode 100644
index 0000000..483b5bf
--- /dev/null
+++ b/test/CodeGen/X86/pr3243.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86
+; PR3243
+
+declare signext i16 @safe_mul_func_int16_t_s_s(i16 signext, i32) nounwind readnone optsize
+
+define i32 @func_120(i32 %p_121) nounwind optsize {
+entry:
+ %0 = trunc i32 %p_121 to i16 ; <i16> [#uses=1]
+ %1 = urem i16 %0, -15461 ; <i16> [#uses=1]
+ %phitmp1 = trunc i16 %1 to i8 ; <i8> [#uses=1]
+ %phitmp2 = urem i8 %phitmp1, -1 ; <i8> [#uses=1]
+ %phitmp3 = zext i8 %phitmp2 to i16 ; <i16> [#uses=1]
+ %2 = tail call signext i16 @safe_mul_func_int16_t_s_s(i16 signext %phitmp3, i32 1) nounwind ; <i16> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/X86/pr3244.ll b/test/CodeGen/X86/pr3244.ll
new file mode 100644
index 0000000..2598c2f
--- /dev/null
+++ b/test/CodeGen/X86/pr3244.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86
+; PR3244
+
+@g_62 = external global i16 ; <i16*> [#uses=1]
+@g_487 = external global i32 ; <i32*> [#uses=1]
+
+define i32 @func_42(i32 %p_43, i32 %p_44, i32 %p_45, i32 %p_46) nounwind {
+entry:
+ %0 = load i16* @g_62, align 2 ; <i16> [#uses=1]
+ %1 = load i32* @g_487, align 4 ; <i32> [#uses=1]
+ %2 = trunc i16 %0 to i8 ; <i8> [#uses=1]
+ %3 = trunc i32 %1 to i8 ; <i8> [#uses=1]
+ %4 = tail call i32 (...)* @func_7(i64 -4455561449541442965, i32 1)
+nounwind ; <i32> [#uses=1]
+ %5 = trunc i32 %4 to i8 ; <i8> [#uses=1]
+ %6 = mul i8 %3, %2 ; <i8> [#uses=1]
+ %7 = mul i8 %6, %5 ; <i8> [#uses=1]
+ %8 = sext i8 %7 to i16 ; <i16> [#uses=1]
+ %9 = tail call i32 @func_85(i16 signext %8, i32 1, i32 1) nounwind
+ ; <i32> [#uses=0]
+ ret i32 undef
+}
+
+declare i32 @func_7(...)
+
+declare i32 @func_85(i16 signext, i32, i32)
diff --git a/test/CodeGen/X86/pr3250.ll b/test/CodeGen/X86/pr3250.ll
new file mode 100644
index 0000000..cccbf54
--- /dev/null
+++ b/test/CodeGen/X86/pr3250.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86
+; PR3250
+
+declare i32 @safe_sub_func_short_u_u(i16 signext, i16 signext) nounwind
+
+define i32 @func_106(i32 %p_107) nounwind {
+entry:
+ %0 = tail call i32 (...)* @safe_div_(i32 %p_107, i32 1) nounwind
+ ; <i32> [#uses=1]
+ %1 = lshr i32 %0, -9 ; <i32> [#uses=1]
+ %2 = trunc i32 %1 to i16 ; <i16> [#uses=1]
+ %3 = tail call i32 @safe_sub_func_short_u_u(i16 signext 1, i16 signext
+%2) nounwind ; <i32> [#uses=0]
+ ret i32 undef
+}
+
+declare i32 @safe_div_(...)
diff --git a/test/CodeGen/X86/pr3317.ll b/test/CodeGen/X86/pr3317.ll
new file mode 100644
index 0000000..9d6626b
--- /dev/null
+++ b/test/CodeGen/X86/pr3317.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s -march=x86
+; PR3317
+
+ %ArraySInt16 = type { %JavaObject, i8*, [0 x i16] }
+ %ArraySInt8 = type { %JavaObject, i8*, [0 x i8] }
+ %Attribut = type { %ArraySInt16*, i32, i32 }
+ %CacheNode = type { i8*, %JavaCommonClass*, %CacheNode*, %Enveloppe* }
+ %Enveloppe = type { %CacheNode*, %ArraySInt16*, %ArraySInt16*, i8, %JavaClass*, %CacheNode }
+ %JavaArray = type { %JavaObject, i8* }
+ %JavaClass = type { %JavaCommonClass, i32, %VT*, [1 x %TaskClassMirror], i8*, %JavaField*, i16, %JavaField*, i16, %JavaMethod*, i16, %JavaMethod*, i16, i8*, %ArraySInt8*, i8*, %Attribut*, i16, %JavaClass**, i16, %JavaClass*, i16, i8, i32, i32, i8*, void (i8*)* }
+ %JavaCommonClass = type { %JavaCommonClass**, i32, [1 x %JavaObject*], i16, %JavaClass**, i16, %ArraySInt16*, %JavaClass*, i8* }
+ %JavaField = type { i8*, i16, %ArraySInt16*, %ArraySInt16*, %Attribut*, i16, %JavaClass*, i32, i16, i8* }
+ %JavaMethod = type { i8*, i16, %Attribut*, i16, %Enveloppe*, i16, %JavaClass*, %ArraySInt16*, %ArraySInt16*, i8, i8*, i32, i8* }
+ %JavaObject = type { %VT*, %JavaCommonClass*, i8* }
+ %TaskClassMirror = type { i32, i8* }
+ %UTF8 = type { %JavaObject, i8*, [0 x i16] }
+ %VT = type [0 x i32 (...)*]
+
+declare void @jnjvmNullPointerException()
+
+define i32 @JnJVM_java_rmi_activation_ActivationGroupID_hashCode__(%JavaObject* nocapture) nounwind {
+start:
+ %1 = getelementptr %JavaObject* %0, i64 1, i32 1 ; <%JavaCommonClass**> [#uses=1]
+ %2 = load %JavaCommonClass** %1 ; <%JavaCommonClass*> [#uses=4]
+ %3 = icmp eq %JavaCommonClass* %2, null ; <i1> [#uses=1]
+ br i1 %3, label %verifyNullExit1, label %verifyNullCont2
+
+verifyNullExit1: ; preds = %start
+ tail call void @jnjvmNullPointerException()
+ unreachable
+
+verifyNullCont2: ; preds = %start
+ %4 = bitcast %JavaCommonClass* %2 to { %JavaObject, i16, i32, i64 }* ; <{ %JavaObject, i16, i32, i64 }*> [#uses=1]
+ %5 = getelementptr { %JavaObject, i16, i32, i64 }* %4, i64 0, i32 2 ; <i32*> [#uses=1]
+ %6 = load i32* %5 ; <i32> [#uses=1]
+ %7 = getelementptr %JavaCommonClass* %2, i64 0, i32 4 ; <%JavaClass***> [#uses=1]
+ %8 = bitcast %JavaClass*** %7 to i64* ; <i64*> [#uses=1]
+ %9 = load i64* %8 ; <i64> [#uses=1]
+ %10 = trunc i64 %9 to i32 ; <i32> [#uses=1]
+ %11 = getelementptr %JavaCommonClass* %2, i64 0, i32 3 ; <i16*> [#uses=1]
+ %12 = load i16* %11 ; <i16> [#uses=1]
+ %13 = sext i16 %12 to i32 ; <i32> [#uses=1]
+ %14 = xor i32 %10, %6 ; <i32> [#uses=1]
+ %15 = xor i32 %14, %13 ; <i32> [#uses=1]
+ ret i32 %15
+}
diff --git a/test/CodeGen/X86/pr3366.ll b/test/CodeGen/X86/pr3366.ll
new file mode 100644
index 0000000..f813e2e
--- /dev/null
+++ b/test/CodeGen/X86/pr3366.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=x86 | grep movzbl
+; PR3366
+
+define void @_ada_c34002a() nounwind {
+entry:
+ %0 = load i8* null, align 1
+ %1 = sdiv i8 90, %0
+ %2 = icmp ne i8 %1, 3
+ %3 = zext i1 %2 to i8
+ %toBool449 = icmp ne i8 %3, 0
+ %4 = or i1 false, %toBool449
+ %5 = zext i1 %4 to i8
+ %toBool450 = icmp ne i8 %5, 0
+ br i1 %toBool450, label %bb451, label %bb457
+
+bb451:
+ br label %bb457
+
+bb457:
+ unreachable
+}
diff --git a/test/CodeGen/X86/pr3457.ll b/test/CodeGen/X86/pr3457.ll
new file mode 100644
index 0000000..f7af927
--- /dev/null
+++ b/test/CodeGen/X86/pr3457.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | not grep fstpt
+; PR3457
+; rdar://6548010
+
+define void @foo(double* nocapture %P) nounwind {
+entry:
+ %0 = tail call double (...)* @test() nounwind ; <double> [#uses=2]
+ %1 = tail call double (...)* @test() nounwind ; <double> [#uses=2]
+ %2 = fmul double %0, %0 ; <double> [#uses=1]
+ %3 = fmul double %1, %1 ; <double> [#uses=1]
+ %4 = fadd double %2, %3 ; <double> [#uses=1]
+ store double %4, double* %P, align 8
+ ret void
+}
+
+declare double @test(...)
diff --git a/test/CodeGen/X86/pr3495-2.ll b/test/CodeGen/X86/pr3495-2.ll
new file mode 100644
index 0000000..71aa5a0
--- /dev/null
+++ b/test/CodeGen/X86/pr3495-2.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -march=x86 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of reloads omited}
+
+target datalayout = "e-p:32:32:32"
+target triple = "i386-apple-darwin9.6"
+ %struct.constraintVCGType = type { i32, i32, i32, i32 }
+ %struct.nodeVCGType = type { %struct.constraintVCGType*, i32, i32, i32, %struct.constraintVCGType*, i32, i32, i32 }
+
+define fastcc void @SCC_DFSBelowVCG(%struct.nodeVCGType* %VCG, i32 %net, i32 %label) nounwind {
+entry:
+ %0 = getelementptr %struct.nodeVCGType* %VCG, i32 %net, i32 5 ; <i32*> [#uses=2]
+ %1 = load i32* %0, align 4 ; <i32> [#uses=1]
+ %2 = icmp eq i32 %1, 0 ; <i1> [#uses=1]
+ br i1 %2, label %bb5, label %bb.nph3
+
+bb.nph3: ; preds = %entry
+ %3 = getelementptr %struct.nodeVCGType* %VCG, i32 %net, i32 4 ; <%struct.constraintVCGType**> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb3, %bb.nph3
+ %s.02 = phi i32 [ 0, %bb.nph3 ], [ %12, %bb3 ] ; <i32> [#uses=2]
+ %4 = load %struct.constraintVCGType** %3, align 4 ; <%struct.constraintVCGType*> [#uses=1]
+ %5 = icmp eq i32 0, 0 ; <i1> [#uses=1]
+ br i1 %5, label %bb1, label %bb3
+
+bb1: ; preds = %bb
+ %6 = getelementptr %struct.constraintVCGType* %4, i32 %s.02, i32 0 ; <i32*> [#uses=1]
+ %7 = load i32* %6, align 4 ; <i32> [#uses=2]
+ %8 = getelementptr %struct.nodeVCGType* %VCG, i32 %7, i32 7 ; <i32*> [#uses=1]
+ %9 = load i32* %8, align 4 ; <i32> [#uses=1]
+ %10 = icmp eq i32 %9, 0 ; <i1> [#uses=1]
+ br i1 %10, label %bb2, label %bb3
+
+bb2: ; preds = %bb1
+ %11 = getelementptr %struct.nodeVCGType* %VCG, i32 %7, i32 4 ; <%struct.constraintVCGType**> [#uses=0]
+ br label %bb.i
+
+bb.i: ; preds = %bb.i, %bb2
+ br label %bb.i
+
+bb3: ; preds = %bb1, %bb
+ %12 = add i32 %s.02, 1 ; <i32> [#uses=2]
+ %13 = load i32* %0, align 4 ; <i32> [#uses=1]
+ %14 = icmp ugt i32 %13, %12 ; <i1> [#uses=1]
+ br i1 %14, label %bb, label %bb5
+
+bb5: ; preds = %bb3, %entry
+ %15 = getelementptr %struct.nodeVCGType* %VCG, i32 %net, i32 6 ; <i32*> [#uses=1]
+ store i32 %label, i32* %15, align 4
+ ret void
+}
diff --git a/test/CodeGen/X86/pr3495.ll b/test/CodeGen/X86/pr3495.ll
new file mode 100644
index 0000000..1795970
--- /dev/null
+++ b/test/CodeGen/X86/pr3495.ll
@@ -0,0 +1,80 @@
+; RUN: llc < %s -march=x86 -stats |& grep {Number of loads added} | grep 2
+; RUN: llc < %s -march=x86 -stats |& grep {Number of register spills} | grep 1
+; RUN: llc < %s -march=x86 -stats |& grep {Number of machine instrs printed} | grep 38
+; PR3495
+; The loop reversal kicks in once here, resulting in one fewer instruction.
+
+target triple = "i386-pc-linux-gnu"
+@x = external global [8 x i32], align 32 ; <[8 x i32]*> [#uses=1]
+@rows = external global [8 x i32], align 32 ; <[8 x i32]*> [#uses=2]
+@up = external global [15 x i32], align 32 ; <[15 x i32]*> [#uses=2]
+@down = external global [15 x i32], align 32 ; <[15 x i32]*> [#uses=1]
+
+define i32 @queens(i32 %c) nounwind {
+entry:
+ %tmp91 = add i32 %c, 1 ; <i32> [#uses=3]
+ %tmp135 = getelementptr [8 x i32]* @x, i32 0, i32 %tmp91 ; <i32*> [#uses=1]
+ br label %bb
+
+bb: ; preds = %bb569, %entry
+ %r25.0.reg2mem.0 = phi i32 [ 0, %entry ], [ %indvar.next715, %bb569 ] ; <i32> [#uses=4]
+ %tmp27 = getelementptr [8 x i32]* @rows, i32 0, i32 %r25.0.reg2mem.0 ; <i32*> [#uses=1]
+ %tmp28 = load i32* %tmp27, align 4 ; <i32> [#uses=1]
+ %tmp29 = icmp eq i32 %tmp28, 0 ; <i1> [#uses=1]
+ br i1 %tmp29, label %bb569, label %bb31
+
+bb31: ; preds = %bb
+ %tmp35 = sub i32 %r25.0.reg2mem.0, 0 ; <i32> [#uses=1]
+ %tmp36 = getelementptr [15 x i32]* @up, i32 0, i32 %tmp35 ; <i32*> [#uses=1]
+ %tmp37 = load i32* %tmp36, align 4 ; <i32> [#uses=1]
+ %tmp38 = icmp eq i32 %tmp37, 0 ; <i1> [#uses=1]
+ br i1 %tmp38, label %bb569, label %bb41
+
+bb41: ; preds = %bb31
+ %tmp54 = sub i32 %r25.0.reg2mem.0, %c ; <i32> [#uses=1]
+ %tmp55 = add i32 %tmp54, 7 ; <i32> [#uses=1]
+ %tmp62 = getelementptr [15 x i32]* @up, i32 0, i32 %tmp55 ; <i32*> [#uses=2]
+ store i32 0, i32* %tmp62, align 4
+ br label %bb92
+
+bb92: ; preds = %bb545, %bb41
+ %r20.0.reg2mem.0 = phi i32 [ 0, %bb41 ], [ %indvar.next711, %bb545 ] ; <i32> [#uses=5]
+ %tmp94 = getelementptr [8 x i32]* @rows, i32 0, i32 %r20.0.reg2mem.0 ; <i32*> [#uses=1]
+ %tmp95 = load i32* %tmp94, align 4 ; <i32> [#uses=0]
+ %tmp112 = add i32 %r20.0.reg2mem.0, %tmp91 ; <i32> [#uses=1]
+ %tmp113 = getelementptr [15 x i32]* @down, i32 0, i32 %tmp112 ; <i32*> [#uses=2]
+ %tmp114 = load i32* %tmp113, align 4 ; <i32> [#uses=1]
+ %tmp115 = icmp eq i32 %tmp114, 0 ; <i1> [#uses=1]
+ br i1 %tmp115, label %bb545, label %bb118
+
+bb118: ; preds = %bb92
+ %tmp122 = sub i32 %r20.0.reg2mem.0, %tmp91 ; <i32> [#uses=0]
+ store i32 0, i32* %tmp113, align 4
+ store i32 %r20.0.reg2mem.0, i32* %tmp135, align 4
+ br label %bb142
+
+bb142: ; preds = %bb142, %bb118
+ %k18.0.reg2mem.0 = phi i32 [ 0, %bb118 ], [ %indvar.next709, %bb142 ] ; <i32> [#uses=1]
+ %indvar.next709 = add i32 %k18.0.reg2mem.0, 1 ; <i32> [#uses=2]
+ %exitcond710 = icmp eq i32 %indvar.next709, 8 ; <i1> [#uses=1]
+ br i1 %exitcond710, label %bb155, label %bb142
+
+bb155: ; preds = %bb142
+ %tmp156 = tail call i32 @putchar(i32 10) nounwind ; <i32> [#uses=0]
+ br label %bb545
+
+bb545: ; preds = %bb155, %bb92
+ %indvar.next711 = add i32 %r20.0.reg2mem.0, 1 ; <i32> [#uses=2]
+ %exitcond712 = icmp eq i32 %indvar.next711, 8 ; <i1> [#uses=1]
+ br i1 %exitcond712, label %bb553, label %bb92
+
+bb553: ; preds = %bb545
+ store i32 1, i32* %tmp62, align 4
+ br label %bb569
+
+bb569: ; preds = %bb553, %bb31, %bb
+ %indvar.next715 = add i32 %r25.0.reg2mem.0, 1 ; <i32> [#uses=1]
+ br label %bb
+}
+
+declare i32 @putchar(i32)
diff --git a/test/CodeGen/X86/pr3522.ll b/test/CodeGen/X86/pr3522.ll
new file mode 100644
index 0000000..7cdeaa0
--- /dev/null
+++ b/test/CodeGen/X86/pr3522.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=x86 -stats |& not grep machine-sink
+; PR3522
+
+target triple = "i386-pc-linux-gnu"
[email protected] = external constant [13 x i8] ; <[13 x i8]*> [#uses=1]
+
+define void @_ada_c34018a() {
+entry:
+ %0 = tail call i32 @report__ident_int(i32 90) ; <i32> [#uses=1]
+ %1 = trunc i32 %0 to i8 ; <i8> [#uses=1]
+ invoke void @__gnat_rcheck_12(i8* getelementptr ([13 x i8]* @.str, i32 0, i32 0), i32 32) noreturn
+ to label %invcont unwind label %lpad
+
+invcont: ; preds = %entry
+ unreachable
+
+bb22: ; preds = %lpad
+ ret void
+
+return: ; preds = %lpad
+ ret void
+
+lpad: ; preds = %entry
+ %2 = icmp eq i8 %1, 90 ; <i1> [#uses=1]
+ br i1 %2, label %return, label %bb22
+}
+
+declare void @__gnat_rcheck_12(i8*, i32) noreturn
+
+declare i32 @report__ident_int(i32)
diff --git a/test/CodeGen/X86/pre-split1.ll b/test/CodeGen/X86/pre-split1.ll
new file mode 100644
index 0000000..e89b507
--- /dev/null
+++ b/test/CodeGen/X86/pre-split1.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
+; XFAIL: *
+
+define void @test(double* %P, i32 %cond) nounwind {
+entry:
+ %0 = load double* %P, align 8 ; <double> [#uses=1]
+ %1 = fadd double %0, 4.000000e+00 ; <double> [#uses=2]
+ %2 = icmp eq i32 %cond, 0 ; <i1> [#uses=1]
+ br i1 %2, label %bb1, label %bb
+
+bb: ; preds = %entry
+ %3 = fadd double %1, 4.000000e+00 ; <double> [#uses=1]
+ br label %bb1
+
+bb1: ; preds = %bb, %entry
+ %A.0 = phi double [ %3, %bb ], [ %1, %entry ] ; <double> [#uses=1]
+ %4 = fmul double %A.0, 4.000000e+00 ; <double> [#uses=1]
+ %5 = tail call i32 (...)* @bar() nounwind ; <i32> [#uses=0]
+ store double %4, double* %P, align 8
+ ret void
+}
+
+declare i32 @bar(...)
diff --git a/test/CodeGen/X86/pre-split10.ll b/test/CodeGen/X86/pre-split10.ll
new file mode 100644
index 0000000..db039bd
--- /dev/null
+++ b/test/CodeGen/X86/pre-split10.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+ br label %bb14.i
+
+bb14.i: ; preds = %bb14.i, %entry
+ %i8.0.reg2mem.0.i = phi i32 [ 0, %entry ], [ %0, %bb14.i ] ; <i32> [#uses=1]
+ %0 = add i32 %i8.0.reg2mem.0.i, 1 ; <i32> [#uses=2]
+ %1 = fadd double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ %2 = fadd double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ %3 = fadd double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ %exitcond75.i = icmp eq i32 %0, 32 ; <i1> [#uses=1]
+ br i1 %exitcond75.i, label %bb24.i, label %bb14.i
+
+bb24.i: ; preds = %bb14.i
+ %4 = fdiv double 0.000000e+00, 0.000000e+00 ; <double> [#uses=1]
+ %5 = fdiv double %1, 0.000000e+00 ; <double> [#uses=1]
+ %6 = fdiv double %2, 0.000000e+00 ; <double> [#uses=1]
+ %7 = fdiv double %3, 0.000000e+00 ; <double> [#uses=1]
+ br label %bb31.i
+
+bb31.i: ; preds = %bb31.i, %bb24.i
+ %tmp.0.reg2mem.0.i = phi i32 [ 0, %bb24.i ], [ %indvar.next64.i, %bb31.i ] ; <i32> [#uses=1]
+ %indvar.next64.i = add i32 %tmp.0.reg2mem.0.i, 1 ; <i32> [#uses=2]
+ %exitcond65.i = icmp eq i32 %indvar.next64.i, 64 ; <i1> [#uses=1]
+ br i1 %exitcond65.i, label %bb33.i, label %bb31.i
+
+bb33.i: ; preds = %bb31.i
+ br label %bb35.preheader.i
+
+bb5.i.i: ; preds = %bb35.preheader.i
+ %8 = call double @floor(double 0.000000e+00) nounwind readnone ; <double> [#uses=0]
+ br label %bb7.i.i
+
+bb7.i.i: ; preds = %bb35.preheader.i, %bb5.i.i
+ br label %bb35.preheader.i
+
+bb35.preheader.i: ; preds = %bb7.i.i, %bb33.i
+ %9 = fsub double 0.000000e+00, %4 ; <double> [#uses=1]
+ store double %9, double* null, align 8
+ %10 = fsub double 0.000000e+00, %5 ; <double> [#uses=1]
+ store double %10, double* null, align 8
+ %11 = fsub double 0.000000e+00, %6 ; <double> [#uses=1]
+ store double %11, double* null, align 8
+ %12 = fsub double 0.000000e+00, %7 ; <double> [#uses=1]
+ store double %12, double* null, align 8
+ br i1 false, label %bb7.i.i, label %bb5.i.i
+}
+
+declare double @floor(double) nounwind readnone
diff --git a/test/CodeGen/X86/pre-split11.ll b/test/CodeGen/X86/pre-split11.ll
new file mode 100644
index 0000000..0a9f4e3
--- /dev/null
+++ b/test/CodeGen/X86/pre-split11.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 -pre-alloc-split | FileCheck %s
+
[email protected] = private constant [28 x i8] c"\0A\0ADOUBLE D = %f\0A\00", align 1 ; <[28 x i8]*> [#uses=1]
[email protected] = private constant [37 x i8] c"double to long l1 = %ld\09\09(0x%lx)\0A\00", align 8 ; <[37 x i8]*> [#uses=1]
[email protected] = private constant [35 x i8] c"double to uint ui1 = %u\09\09(0x%x)\0A\00", align 8 ; <[35 x i8]*> [#uses=1]
[email protected] = private constant [37 x i8] c"double to ulong ul1 = %lu\09\09(0x%lx)\0A\00", align 8 ; <[37 x i8]*> [#uses=1]
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp {
+; CHECK: movsd %xmm0, (%rsp)
+entry:
+ %0 = icmp sgt i32 %argc, 4 ; <i1> [#uses=1]
+ br i1 %0, label %bb, label %bb2
+
+bb: ; preds = %entry
+ %1 = getelementptr inbounds i8** %argv, i64 4 ; <i8**> [#uses=1]
+ %2 = load i8** %1, align 8 ; <i8*> [#uses=1]
+ %3 = tail call double @atof(i8* %2) nounwind ; <double> [#uses=1]
+ br label %bb2
+
+bb2: ; preds = %bb, %entry
+ %storemerge = phi double [ %3, %bb ], [ 2.000000e+00, %entry ] ; <double> [#uses=4]
+ %4 = fptoui double %storemerge to i32 ; <i32> [#uses=2]
+ %5 = fptoui double %storemerge to i64 ; <i64> [#uses=2]
+ %6 = fptosi double %storemerge to i64 ; <i64> [#uses=2]
+ %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([28 x i8]* @.str, i64 0, i64 0), double %storemerge) nounwind ; <i32> [#uses=0]
+ %8 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([37 x i8]* @.str1, i64 0, i64 0), i64 %6, i64 %6) nounwind ; <i32> [#uses=0]
+ %9 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([35 x i8]* @.str2, i64 0, i64 0), i32 %4, i32 %4) nounwind ; <i32> [#uses=0]
+ %10 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([37 x i8]* @.str3, i64 0, i64 0), i64 %5, i64 %5) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
+
+declare double @atof(i8* nocapture) nounwind readonly
+
+declare i32 @printf(i8* nocapture, ...) nounwind
diff --git a/test/CodeGen/X86/pre-split2.ll b/test/CodeGen/X86/pre-split2.ll
new file mode 100644
index 0000000..ba902f9
--- /dev/null
+++ b/test/CodeGen/X86/pre-split2.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: grep {pre-alloc-split} | count 2
+
+define i32 @t(i32 %arg) {
+entry:
+ br label %bb6
+
+.noexc6: ; preds = %bb6
+ %0 = and i32 %2, -8 ; <i32> [#uses=1]
+ tail call void @llvm.memmove.i32(i8* %3, i8* null, i32 %0, i32 1) nounwind
+ store double %1, double* null, align 8
+ br label %bb6
+
+bb6: ; preds = %.noexc6, %entry
+ %1 = uitofp i32 %arg to double ; <double> [#uses=1]
+ %2 = sub i32 0, 0 ; <i32> [#uses=1]
+ %3 = invoke i8* @_Znwm(i32 0)
+ to label %.noexc6 unwind label %lpad32 ; <i8*> [#uses=1]
+
+lpad32: ; preds = %bb6
+ unreachable
+}
+
+declare void @llvm.memmove.i32(i8*, i8*, i32, i32) nounwind
+
+declare i8* @_Znwm(i32)
diff --git a/test/CodeGen/X86/pre-split3.ll b/test/CodeGen/X86/pre-split3.ll
new file mode 100644
index 0000000..2e31420
--- /dev/null
+++ b/test/CodeGen/X86/pre-split3.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
+
+define i32 @t(i32 %arg) {
+entry:
+ br label %bb6
+
+.noexc6: ; preds = %bb6
+ %0 = and i32 %2, -8 ; <i32> [#uses=1]
+ tail call void @llvm.memmove.i32(i8* %3, i8* null, i32 %0, i32 1) nounwind
+ store double %1, double* null, align 8
+ br label %bb6
+
+bb6: ; preds = %.noexc6, %entry
+ %1 = uitofp i32 %arg to double ; <double> [#uses=1]
+ %2 = sub i32 0, 0 ; <i32> [#uses=1]
+ %3 = invoke i8* @_Znwm(i32 0)
+ to label %.noexc6 unwind label %lpad32 ; <i8*> [#uses=1]
+
+lpad32: ; preds = %bb6
+ unreachable
+}
+
+declare void @llvm.memmove.i32(i8*, i8*, i32, i32) nounwind
+
+declare i8* @_Znwm(i32)
diff --git a/test/CodeGen/X86/pre-split4.ll b/test/CodeGen/X86/pre-split4.ll
new file mode 100644
index 0000000..10cef27
--- /dev/null
+++ b/test/CodeGen/X86/pre-split4.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 2
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+ br label %bb
+
+bb: ; preds = %bb, %entry
+ %k.0.reg2mem.0 = phi double [ 1.000000e+00, %entry ], [ %6, %bb ] ; <double> [#uses=2]
+ %Flint.0.reg2mem.0 = phi double [ 0.000000e+00, %entry ], [ %5, %bb ] ; <double> [#uses=1]
+ %twoThrd.0.reg2mem.0 = phi double [ 0.000000e+00, %entry ], [ %1, %bb ] ; <double> [#uses=1]
+ %0 = tail call double @llvm.pow.f64(double 0x3FE5555555555555, double 0.000000e+00) ; <double> [#uses=1]
+ %1 = fadd double %0, %twoThrd.0.reg2mem.0 ; <double> [#uses=1]
+ %2 = tail call double @sin(double %k.0.reg2mem.0) nounwind readonly ; <double> [#uses=1]
+ %3 = fmul double 0.000000e+00, %2 ; <double> [#uses=1]
+ %4 = fdiv double 1.000000e+00, %3 ; <double> [#uses=1]
+ store double %Flint.0.reg2mem.0, double* null
+ store double %twoThrd.0.reg2mem.0, double* null
+ %5 = fadd double %4, %Flint.0.reg2mem.0 ; <double> [#uses=1]
+ %6 = fadd double %k.0.reg2mem.0, 1.000000e+00 ; <double> [#uses=1]
+ br label %bb
+}
+
+declare double @llvm.pow.f64(double, double) nounwind readonly
+
+declare double @sin(double) nounwind readonly
diff --git a/test/CodeGen/X86/pre-split5.ll b/test/CodeGen/X86/pre-split5.ll
new file mode 100644
index 0000000..8def460
--- /dev/null
+++ b/test/CodeGen/X86/pre-split5.ll
@@ -0,0 +1,56 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split
+
+target triple = "i386-apple-darwin9.5"
+ %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+ %struct.__sFILEX = type opaque
+ %struct.__sbuf = type { i8*, i32 }
+@"\01LC1" = external constant [48 x i8] ; <[48 x i8]*> [#uses=1]
+
+define i32 @main() nounwind {
+entry:
+ br label %bb5.us
+
+bb5.us: ; preds = %bb8.split, %bb5.us, %entry
+ %i.0.reg2mem.0.ph = phi i32 [ 0, %entry ], [ %indvar.next53, %bb8.split ], [ %i.0.reg2mem.0.ph, %bb5.us ] ; <i32> [#uses=2]
+ %j.0.reg2mem.0.us = phi i32 [ %indvar.next47, %bb5.us ], [ 0, %bb8.split ], [ 0, %entry ] ; <i32> [#uses=1]
+ %indvar.next47 = add i32 %j.0.reg2mem.0.us, 1 ; <i32> [#uses=2]
+ %exitcond48 = icmp eq i32 %indvar.next47, 256 ; <i1> [#uses=1]
+ br i1 %exitcond48, label %bb8.split, label %bb5.us
+
+bb8.split: ; preds = %bb5.us
+ %indvar.next53 = add i32 %i.0.reg2mem.0.ph, 1 ; <i32> [#uses=2]
+ %exitcond54 = icmp eq i32 %indvar.next53, 256 ; <i1> [#uses=1]
+ br i1 %exitcond54, label %bb11, label %bb5.us
+
+bb11: ; preds = %bb11, %bb8.split
+ %i.1.reg2mem.0 = phi i32 [ %indvar.next44, %bb11 ], [ 0, %bb8.split ] ; <i32> [#uses=1]
+ %indvar.next44 = add i32 %i.1.reg2mem.0, 1 ; <i32> [#uses=2]
+ %exitcond45 = icmp eq i32 %indvar.next44, 63 ; <i1> [#uses=1]
+ br i1 %exitcond45, label %bb14, label %bb11
+
+bb14: ; preds = %bb14, %bb11
+ %indvar = phi i32 [ %indvar.next40, %bb14 ], [ 0, %bb11 ] ; <i32> [#uses=1]
+ %indvar.next40 = add i32 %indvar, 1 ; <i32> [#uses=2]
+ %exitcond41 = icmp eq i32 %indvar.next40, 32768 ; <i1> [#uses=1]
+ br i1 %exitcond41, label %bb28, label %bb14
+
+bb28: ; preds = %bb14
+ %0 = fdiv double 2.550000e+02, 0.000000e+00 ; <double> [#uses=1]
+ br label %bb30
+
+bb30: ; preds = %bb36, %bb28
+ %m.1.reg2mem.0 = phi i32 [ %m.0, %bb36 ], [ 0, %bb28 ] ; <i32> [#uses=1]
+ %1 = fmul double 0.000000e+00, %0 ; <double> [#uses=1]
+ %2 = fptosi double %1 to i32 ; <i32> [#uses=1]
+ br i1 false, label %bb36, label %bb35
+
+bb35: ; preds = %bb30
+ %3 = tail call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* null, i8* getelementptr ([48 x i8]* @"\01LC1", i32 0, i32 0), i32 0, i32 0, i32 0, i32 %2) nounwind ; <i32> [#uses=0]
+ br label %bb36
+
+bb36: ; preds = %bb35, %bb30
+ %m.0 = phi i32 [ 0, %bb35 ], [ %m.1.reg2mem.0, %bb30 ] ; <i32> [#uses=1]
+ br label %bb30
+}
+
+declare i32 @fprintf(%struct.FILE*, i8*, ...) nounwind
diff --git a/test/CodeGen/X86/pre-split6.ll b/test/CodeGen/X86/pre-split6.ll
new file mode 100644
index 0000000..d38e630
--- /dev/null
+++ b/test/CodeGen/X86/pre-split6.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split | grep {divsd 8} | count 1
+
+@current_surfaces.b = external global i1 ; <i1*> [#uses=1]
+
+declare double @sin(double) nounwind readonly
+
+declare double @asin(double) nounwind readonly
+
+define fastcc void @trace_line(i32 %line) nounwind {
+entry:
+ %.b3 = load i1* @current_surfaces.b ; <i1> [#uses=1]
+ br i1 %.b3, label %bb.nph, label %return
+
+bb.nph: ; preds = %entry
+ %0 = load double* null, align 8 ; <double> [#uses=1]
+ %1 = load double* null, align 8 ; <double> [#uses=2]
+ %2 = fcmp une double %0, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %2, label %bb9.i, label %bb13.i
+
+bb9.i: ; preds = %bb.nph
+ %3 = tail call double @asin(double 0.000000e+00) nounwind readonly ; <double> [#uses=0]
+ %4 = fdiv double 1.000000e+00, %1 ; <double> [#uses=1]
+ %5 = fmul double %4, 0.000000e+00 ; <double> [#uses=1]
+ %6 = tail call double @asin(double %5) nounwind readonly ; <double> [#uses=0]
+ unreachable
+
+bb13.i: ; preds = %bb.nph
+ %7 = fdiv double 1.000000e+00, %1 ; <double> [#uses=1]
+ %8 = tail call double @sin(double 0.000000e+00) nounwind readonly ; <double> [#uses=1]
+ %9 = fmul double %7, %8 ; <double> [#uses=1]
+ %10 = tail call double @asin(double %9) nounwind readonly ; <double> [#uses=0]
+ unreachable
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/pre-split7.ll b/test/CodeGen/X86/pre-split7.ll
new file mode 100644
index 0000000..0b81c0b
--- /dev/null
+++ b/test/CodeGen/X86/pre-split7.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split
+
+@object_distance = external global double, align 8 ; <double*> [#uses=1]
+@axis_slope_angle = external global double, align 8 ; <double*> [#uses=1]
+@current_surfaces.b = external global i1 ; <i1*> [#uses=1]
+
+declare double @sin(double) nounwind readonly
+
+declare double @asin(double) nounwind readonly
+
+declare double @tan(double) nounwind readonly
+
+define fastcc void @trace_line(i32 %line) nounwind {
+entry:
+ %.b3 = load i1* @current_surfaces.b ; <i1> [#uses=1]
+ br i1 %.b3, label %bb, label %return
+
+bb: ; preds = %bb, %entry
+ %0 = tail call double @asin(double 0.000000e+00) nounwind readonly ; <double> [#uses=1]
+ %1 = fadd double 0.000000e+00, %0 ; <double> [#uses=2]
+ %2 = tail call double @asin(double 0.000000e+00) nounwind readonly ; <double> [#uses=1]
+ %3 = fsub double %1, %2 ; <double> [#uses=2]
+ store double %3, double* @axis_slope_angle, align 8
+ %4 = fdiv double %1, 2.000000e+00 ; <double> [#uses=1]
+ %5 = tail call double @sin(double %4) nounwind readonly ; <double> [#uses=1]
+ %6 = fmul double 0.000000e+00, %5 ; <double> [#uses=1]
+ %7 = tail call double @tan(double %3) nounwind readonly ; <double> [#uses=0]
+ %8 = fadd double 0.000000e+00, %6 ; <double> [#uses=1]
+ store double %8, double* @object_distance, align 8
+ br label %bb
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/pre-split8.ll b/test/CodeGen/X86/pre-split8.ll
new file mode 100644
index 0000000..ea4b949
--- /dev/null
+++ b/test/CodeGen/X86/pre-split8.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
+
+@current_surfaces.b = external global i1 ; <i1*> [#uses=1]
+
+declare double @asin(double) nounwind readonly
+
+declare double @tan(double) nounwind readonly
+
+define fastcc void @trace_line(i32 %line) nounwind {
+entry:
+ %.b3 = load i1* @current_surfaces.b ; <i1> [#uses=1]
+ br i1 %.b3, label %bb, label %return
+
+bb: ; preds = %bb9.i, %entry
+ %.rle4 = phi double [ %7, %bb9.i ], [ 0.000000e+00, %entry ] ; <double> [#uses=1]
+ %0 = load double* null, align 8 ; <double> [#uses=3]
+ %1 = fcmp une double %0, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %1, label %bb9.i, label %bb13.i
+
+bb9.i: ; preds = %bb
+ %2 = fsub double %.rle4, %0 ; <double> [#uses=0]
+ %3 = tail call double @asin(double 0.000000e+00) nounwind readonly ; <double> [#uses=0]
+ %4 = fmul double 0.000000e+00, %0 ; <double> [#uses=1]
+ %5 = tail call double @tan(double 0.000000e+00) nounwind readonly ; <double> [#uses=0]
+ %6 = fmul double %4, 0.000000e+00 ; <double> [#uses=1]
+ %7 = fadd double %6, 0.000000e+00 ; <double> [#uses=1]
+ br i1 false, label %return, label %bb
+
+bb13.i: ; preds = %bb
+ unreachable
+
+return: ; preds = %bb9.i, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/pre-split9.ll b/test/CodeGen/X86/pre-split9.ll
new file mode 100644
index 0000000..c27d925
--- /dev/null
+++ b/test/CodeGen/X86/pre-split9.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
+
+@current_surfaces.b = external global i1 ; <i1*> [#uses=1]
+
+declare double @sin(double) nounwind readonly
+
+declare double @asin(double) nounwind readonly
+
+declare double @tan(double) nounwind readonly
+
+define fastcc void @trace_line(i32 %line) nounwind {
+entry:
+ %.b3 = load i1* @current_surfaces.b ; <i1> [#uses=1]
+ br i1 %.b3, label %bb, label %return
+
+bb: ; preds = %bb9.i, %entry
+ %.rle4 = phi double [ %8, %bb9.i ], [ 0.000000e+00, %entry ] ; <double> [#uses=1]
+ %0 = load double* null, align 8 ; <double> [#uses=3]
+ %1 = fcmp une double %0, 0.000000e+00 ; <i1> [#uses=1]
+ br i1 %1, label %bb9.i, label %bb13.i
+
+bb9.i: ; preds = %bb
+ %2 = fsub double %.rle4, %0 ; <double> [#uses=0]
+ %3 = tail call double @asin(double 0.000000e+00) nounwind readonly ; <double> [#uses=0]
+ %4 = tail call double @sin(double 0.000000e+00) nounwind readonly ; <double> [#uses=1]
+ %5 = fmul double %4, %0 ; <double> [#uses=1]
+ %6 = tail call double @tan(double 0.000000e+00) nounwind readonly ; <double> [#uses=0]
+ %7 = fmul double %5, 0.000000e+00 ; <double> [#uses=1]
+ %8 = fadd double %7, 0.000000e+00 ; <double> [#uses=1]
+ br i1 false, label %return, label %bb
+
+bb13.i: ; preds = %bb
+ unreachable
+
+return: ; preds = %bb9.i, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/prefetch.ll b/test/CodeGen/X86/prefetch.ll
new file mode 100644
index 0000000..fac5915
--- /dev/null
+++ b/test/CodeGen/X86/prefetch.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86 -mattr=+sse > %t
+; RUN: grep prefetchnta %t
+; RUN: grep prefetcht0 %t
+; RUN: grep prefetcht1 %t
+; RUN: grep prefetcht2 %t
+
+define void @t(i8* %ptr) nounwind {
+entry:
+ tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1 )
+ tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2 )
+ tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 )
+ tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0 )
+ ret void
+}
+
+declare void @llvm.prefetch(i8*, i32, i32) nounwind
diff --git a/test/CodeGen/X86/private-2.ll b/test/CodeGen/X86/private-2.ll
new file mode 100644
index 0000000..8aa744e
--- /dev/null
+++ b/test/CodeGen/X86/private-2.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | grep L__ZZ20
+; Quote should be outside of private prefix.
+; rdar://6855766x
+
+ %struct.A = type { i32*, i32 }
+@"_ZZ20-[Example1 whatever]E4C.91" = private constant %struct.A { i32* null, i32 1 } ; <%struct.A*> [#uses=1]
+
+define internal i32* @"\01-[Example1 whatever]"() nounwind optsize ssp {
+entry:
+ %0 = getelementptr %struct.A* @"_ZZ20-[Example1 whatever]E4C.91", i64 0, i32 0 ; <i32**> [#uses=1]
+ %1 = load i32** %0, align 8 ; <i32*> [#uses=1]
+ ret i32* %1
+}
diff --git a/test/CodeGen/X86/private.ll b/test/CodeGen/X86/private.ll
new file mode 100644
index 0000000..f52f8c7
--- /dev/null
+++ b/test/CodeGen/X86/private.ll
@@ -0,0 +1,20 @@
+; Test to make sure that the 'private' is used correctly.
+;
+; RUN: llc < %s -mtriple=x86_64-pc-linux | grep .Lfoo:
+; RUN: llc < %s -mtriple=x86_64-pc-linux | grep call.*\.Lfoo
+; RUN: llc < %s -mtriple=x86_64-pc-linux | grep .Lbaz:
+; RUN: llc < %s -mtriple=x86_64-pc-linux | grep movl.*\.Lbaz
+
+declare void @foo()
+
+define private void @foo() {
+ ret void
+}
+
+@baz = private global i32 4
+
+define i32 @bar() {
+ call void @foo()
+ %1 = load i32* @baz, align 4
+ ret i32 %1
+}
diff --git a/test/CodeGen/X86/ptrtoint-constexpr.ll b/test/CodeGen/X86/ptrtoint-constexpr.ll
new file mode 100644
index 0000000..dd97905
--- /dev/null
+++ b/test/CodeGen/X86/ptrtoint-constexpr.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=i386-linux | FileCheck %s
+ %union.x = type { i64 }
+
+; CHECK: .globl r
+; CHECK: r:
+; CHECK: .quad r&4294967295
+
+@r = global %union.x { i64 ptrtoint (%union.x* @r to i64) }, align 4
+
+; CHECK: .globl x
+; CHECK: x:
+; CHECK: .quad 3
+
+@x = global i64 mul (i64 3, i64 ptrtoint (i2* getelementptr (i2* null, i64 1) to i64))
diff --git a/test/CodeGen/X86/rdtsc.ll b/test/CodeGen/X86/rdtsc.ll
new file mode 100644
index 0000000..f21a44c
--- /dev/null
+++ b/test/CodeGen/X86/rdtsc.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 | grep rdtsc
+; RUN: llc < %s -march=x86-64 | grep rdtsc
+declare i64 @llvm.readcyclecounter()
+
+define i64 @foo() {
+ %tmp.1 = call i64 @llvm.readcyclecounter( ) ; <i64> [#uses=1]
+ ret i64 %tmp.1
+}
diff --git a/test/CodeGen/X86/red-zone.ll b/test/CodeGen/X86/red-zone.ll
new file mode 100644
index 0000000..1ffb4e3
--- /dev/null
+++ b/test/CodeGen/X86/red-zone.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+; First without noredzone.
+; CHECK: f0:
+; CHECK: -4(%rsp)
+; CHECK: -4(%rsp)
+; CHECK: ret
+define x86_fp80 @f0(float %f) nounwind readnone {
+entry:
+ %0 = fpext float %f to x86_fp80 ; <x86_fp80> [#uses=1]
+ ret x86_fp80 %0
+}
+
+; Then with noredzone.
+; CHECK: f1:
+; CHECK: subq $4, %rsp
+; CHECK: (%rsp)
+; CHECK: (%rsp)
+; CHECK: addq $4, %rsp
+; CHECK: ret
+define x86_fp80 @f1(float %f) nounwind readnone noredzone {
+entry:
+ %0 = fpext float %f to x86_fp80 ; <x86_fp80> [#uses=1]
+ ret x86_fp80 %0
+}
diff --git a/test/CodeGen/X86/red-zone2.ll b/test/CodeGen/X86/red-zone2.ll
new file mode 100644
index 0000000..9557d17
--- /dev/null
+++ b/test/CodeGen/X86/red-zone2.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: grep subq %t | count 1
+; RUN: grep addq %t | count 1
+
+define x86_fp80 @f0(float %f) nounwind readnone noredzone {
+entry:
+ %0 = fpext float %f to x86_fp80 ; <x86_fp80> [#uses=1]
+ ret x86_fp80 %0
+}
diff --git a/test/CodeGen/X86/regpressure.ll b/test/CodeGen/X86/regpressure.ll
new file mode 100644
index 0000000..e0b5f7a
--- /dev/null
+++ b/test/CodeGen/X86/regpressure.ll
@@ -0,0 +1,114 @@
+;; Both functions in this testcase should codegen to the same function, and
+;; neither of them should require spilling anything to the stack.
+
+; RUN: llc < %s -march=x86 -stats |& \
+; RUN: not grep {Number of register spills}
+
+;; This can be compiled to use three registers if the loads are not
+;; folded into the multiplies, 2 registers otherwise.
+
+define i32 @regpressure1(i32* %P) {
+ %A = load i32* %P ; <i32> [#uses=1]
+ %Bp = getelementptr i32* %P, i32 1 ; <i32*> [#uses=1]
+ %B = load i32* %Bp ; <i32> [#uses=1]
+ %s1 = mul i32 %A, %B ; <i32> [#uses=1]
+ %Cp = getelementptr i32* %P, i32 2 ; <i32*> [#uses=1]
+ %C = load i32* %Cp ; <i32> [#uses=1]
+ %s2 = mul i32 %s1, %C ; <i32> [#uses=1]
+ %Dp = getelementptr i32* %P, i32 3 ; <i32*> [#uses=1]
+ %D = load i32* %Dp ; <i32> [#uses=1]
+ %s3 = mul i32 %s2, %D ; <i32> [#uses=1]
+ %Ep = getelementptr i32* %P, i32 4 ; <i32*> [#uses=1]
+ %E = load i32* %Ep ; <i32> [#uses=1]
+ %s4 = mul i32 %s3, %E ; <i32> [#uses=1]
+ %Fp = getelementptr i32* %P, i32 5 ; <i32*> [#uses=1]
+ %F = load i32* %Fp ; <i32> [#uses=1]
+ %s5 = mul i32 %s4, %F ; <i32> [#uses=1]
+ %Gp = getelementptr i32* %P, i32 6 ; <i32*> [#uses=1]
+ %G = load i32* %Gp ; <i32> [#uses=1]
+ %s6 = mul i32 %s5, %G ; <i32> [#uses=1]
+ %Hp = getelementptr i32* %P, i32 7 ; <i32*> [#uses=1]
+ %H = load i32* %Hp ; <i32> [#uses=1]
+ %s7 = mul i32 %s6, %H ; <i32> [#uses=1]
+ %Ip = getelementptr i32* %P, i32 8 ; <i32*> [#uses=1]
+ %I = load i32* %Ip ; <i32> [#uses=1]
+ %s8 = mul i32 %s7, %I ; <i32> [#uses=1]
+ %Jp = getelementptr i32* %P, i32 9 ; <i32*> [#uses=1]
+ %J = load i32* %Jp ; <i32> [#uses=1]
+ %s9 = mul i32 %s8, %J ; <i32> [#uses=1]
+ ret i32 %s9
+}
+
+define i32 @regpressure2(i32* %P) {
+ %A = load i32* %P ; <i32> [#uses=1]
+ %Bp = getelementptr i32* %P, i32 1 ; <i32*> [#uses=1]
+ %B = load i32* %Bp ; <i32> [#uses=1]
+ %Cp = getelementptr i32* %P, i32 2 ; <i32*> [#uses=1]
+ %C = load i32* %Cp ; <i32> [#uses=1]
+ %Dp = getelementptr i32* %P, i32 3 ; <i32*> [#uses=1]
+ %D = load i32* %Dp ; <i32> [#uses=1]
+ %Ep = getelementptr i32* %P, i32 4 ; <i32*> [#uses=1]
+ %E = load i32* %Ep ; <i32> [#uses=1]
+ %Fp = getelementptr i32* %P, i32 5 ; <i32*> [#uses=1]
+ %F = load i32* %Fp ; <i32> [#uses=1]
+ %Gp = getelementptr i32* %P, i32 6 ; <i32*> [#uses=1]
+ %G = load i32* %Gp ; <i32> [#uses=1]
+ %Hp = getelementptr i32* %P, i32 7 ; <i32*> [#uses=1]
+ %H = load i32* %Hp ; <i32> [#uses=1]
+ %Ip = getelementptr i32* %P, i32 8 ; <i32*> [#uses=1]
+ %I = load i32* %Ip ; <i32> [#uses=1]
+ %Jp = getelementptr i32* %P, i32 9 ; <i32*> [#uses=1]
+ %J = load i32* %Jp ; <i32> [#uses=1]
+ %s1 = mul i32 %A, %B ; <i32> [#uses=1]
+ %s2 = mul i32 %s1, %C ; <i32> [#uses=1]
+ %s3 = mul i32 %s2, %D ; <i32> [#uses=1]
+ %s4 = mul i32 %s3, %E ; <i32> [#uses=1]
+ %s5 = mul i32 %s4, %F ; <i32> [#uses=1]
+ %s6 = mul i32 %s5, %G ; <i32> [#uses=1]
+ %s7 = mul i32 %s6, %H ; <i32> [#uses=1]
+ %s8 = mul i32 %s7, %I ; <i32> [#uses=1]
+ %s9 = mul i32 %s8, %J ; <i32> [#uses=1]
+ ret i32 %s9
+}
+
+define i32 @regpressure3(i16* %P, i1 %Cond, i32* %Other) {
+ %A = load i16* %P ; <i16> [#uses=1]
+ %Bp = getelementptr i16* %P, i32 1 ; <i16*> [#uses=1]
+ %B = load i16* %Bp ; <i16> [#uses=1]
+ %Cp = getelementptr i16* %P, i32 2 ; <i16*> [#uses=1]
+ %C = load i16* %Cp ; <i16> [#uses=1]
+ %Dp = getelementptr i16* %P, i32 3 ; <i16*> [#uses=1]
+ %D = load i16* %Dp ; <i16> [#uses=1]
+ %Ep = getelementptr i16* %P, i32 4 ; <i16*> [#uses=1]
+ %E = load i16* %Ep ; <i16> [#uses=1]
+ %Fp = getelementptr i16* %P, i32 5 ; <i16*> [#uses=1]
+ %F = load i16* %Fp ; <i16> [#uses=1]
+ %Gp = getelementptr i16* %P, i32 6 ; <i16*> [#uses=1]
+ %G = load i16* %Gp ; <i16> [#uses=1]
+ %Hp = getelementptr i16* %P, i32 7 ; <i16*> [#uses=1]
+ %H = load i16* %Hp ; <i16> [#uses=1]
+ %Ip = getelementptr i16* %P, i32 8 ; <i16*> [#uses=1]
+ %I = load i16* %Ip ; <i16> [#uses=1]
+ %Jp = getelementptr i16* %P, i32 9 ; <i16*> [#uses=1]
+ %J = load i16* %Jp ; <i16> [#uses=1]
+ %A.upgrd.1 = sext i16 %A to i32 ; <i32> [#uses=1]
+ %B.upgrd.2 = sext i16 %B to i32 ; <i32> [#uses=1]
+ %D.upgrd.3 = sext i16 %D to i32 ; <i32> [#uses=1]
+ %C.upgrd.4 = sext i16 %C to i32 ; <i32> [#uses=1]
+ %E.upgrd.5 = sext i16 %E to i32 ; <i32> [#uses=1]
+ %F.upgrd.6 = sext i16 %F to i32 ; <i32> [#uses=1]
+ %G.upgrd.7 = sext i16 %G to i32 ; <i32> [#uses=1]
+ %H.upgrd.8 = sext i16 %H to i32 ; <i32> [#uses=1]
+ %I.upgrd.9 = sext i16 %I to i32 ; <i32> [#uses=1]
+ %J.upgrd.10 = sext i16 %J to i32 ; <i32> [#uses=1]
+ %s1 = add i32 %A.upgrd.1, %B.upgrd.2 ; <i32> [#uses=1]
+ %s2 = add i32 %C.upgrd.4, %s1 ; <i32> [#uses=1]
+ %s3 = add i32 %D.upgrd.3, %s2 ; <i32> [#uses=1]
+ %s4 = add i32 %E.upgrd.5, %s3 ; <i32> [#uses=1]
+ %s5 = add i32 %F.upgrd.6, %s4 ; <i32> [#uses=1]
+ %s6 = add i32 %G.upgrd.7, %s5 ; <i32> [#uses=1]
+ %s7 = add i32 %H.upgrd.8, %s6 ; <i32> [#uses=1]
+ %s8 = add i32 %I.upgrd.9, %s7 ; <i32> [#uses=1]
+ %s9 = add i32 %J.upgrd.10, %s8 ; <i32> [#uses=1]
+ ret i32 %s9
+}
diff --git a/test/CodeGen/X86/rem-2.ll b/test/CodeGen/X86/rem-2.ll
new file mode 100644
index 0000000..1b2af4b
--- /dev/null
+++ b/test/CodeGen/X86/rem-2.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86 | not grep cltd
+
+define i32 @test(i32 %X) nounwind readnone {
+entry:
+ %0 = srem i32 41, %X
+ ret i32 %0
+}
diff --git a/test/CodeGen/X86/rem.ll b/test/CodeGen/X86/rem.ll
new file mode 100644
index 0000000..394070e
--- /dev/null
+++ b/test/CodeGen/X86/rem.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=x86 | not grep div
+
+define i32 @test1(i32 %X) {
+ %tmp1 = srem i32 %X, 255 ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32 @test2(i32 %X) {
+ %tmp1 = srem i32 %X, 256 ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32 @test3(i32 %X) {
+ %tmp1 = urem i32 %X, 255 ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+define i32 @test4(i32 %X) {
+ %tmp1 = urem i32 %X, 256 ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
diff --git a/test/CodeGen/X86/remat-constant.ll b/test/CodeGen/X86/remat-constant.ll
new file mode 100644
index 0000000..3e81320
--- /dev/null
+++ b/test/CodeGen/X86/remat-constant.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=x86_64-linux -relocation-model=static | grep xmm | count 2
+
+declare void @bar() nounwind
+
+@a = external constant float
+
+declare void @qux(float %f) nounwind
+
+define void @foo() nounwind {
+ %f = load float* @a
+ call void @bar()
+ call void @qux(float %f)
+ call void @qux(float %f)
+ ret void
+}
diff --git a/test/CodeGen/X86/remat-mov-0.ll b/test/CodeGen/X86/remat-mov-0.ll
new file mode 100644
index 0000000..5fb445c
--- /dev/null
+++ b/test/CodeGen/X86/remat-mov-0.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+
+; CodeGen should remat the zero instead of spilling it.
+
+declare void @foo(i64 %p)
+
+; CHECK: bar:
+; CHECK: xorl %edi, %edi
+; CHECK: xorl %edi, %edi
+define void @bar() nounwind {
+ call void @foo(i64 0)
+ call void @foo(i64 0)
+ ret void
+}
+
+; CHECK: bat:
+; CHECK: movq $-1, %rdi
+; CHECK: movq $-1, %rdi
+define void @bat() nounwind {
+ call void @foo(i64 -1)
+ call void @foo(i64 -1)
+ ret void
+}
+
+; CHECK: bau:
+; CHECK: movl $1, %edi
+; CHECK: movl $1, %edi
+define void @bau() nounwind {
+ call void @foo(i64 1)
+ call void @foo(i64 1)
+ ret void
+}
+
diff --git a/test/CodeGen/X86/remat-scalar-zero.ll b/test/CodeGen/X86/remat-scalar-zero.ll
new file mode 100644
index 0000000..2da96ab
--- /dev/null
+++ b/test/CodeGen/X86/remat-scalar-zero.ll
@@ -0,0 +1,95 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu > %t
+; RUN: not grep xor %t
+; RUN: not grep movap %t
+; RUN: grep {\\.quad.*0} %t
+
+; Remat should be able to fold the zero constant into the div instructions
+; as a constant-pool load.
+
+define void @foo(double* nocapture %x, double* nocapture %y) nounwind {
+entry:
+ %tmp1 = load double* %x ; <double> [#uses=1]
+ %arrayidx4 = getelementptr inbounds double* %x, i64 1 ; <double*> [#uses=1]
+ %tmp5 = load double* %arrayidx4 ; <double> [#uses=1]
+ %arrayidx8 = getelementptr inbounds double* %x, i64 2 ; <double*> [#uses=1]
+ %tmp9 = load double* %arrayidx8 ; <double> [#uses=1]
+ %arrayidx12 = getelementptr inbounds double* %x, i64 3 ; <double*> [#uses=1]
+ %tmp13 = load double* %arrayidx12 ; <double> [#uses=1]
+ %arrayidx16 = getelementptr inbounds double* %x, i64 4 ; <double*> [#uses=1]
+ %tmp17 = load double* %arrayidx16 ; <double> [#uses=1]
+ %arrayidx20 = getelementptr inbounds double* %x, i64 5 ; <double*> [#uses=1]
+ %tmp21 = load double* %arrayidx20 ; <double> [#uses=1]
+ %arrayidx24 = getelementptr inbounds double* %x, i64 6 ; <double*> [#uses=1]
+ %tmp25 = load double* %arrayidx24 ; <double> [#uses=1]
+ %arrayidx28 = getelementptr inbounds double* %x, i64 7 ; <double*> [#uses=1]
+ %tmp29 = load double* %arrayidx28 ; <double> [#uses=1]
+ %arrayidx32 = getelementptr inbounds double* %x, i64 8 ; <double*> [#uses=1]
+ %tmp33 = load double* %arrayidx32 ; <double> [#uses=1]
+ %arrayidx36 = getelementptr inbounds double* %x, i64 9 ; <double*> [#uses=1]
+ %tmp37 = load double* %arrayidx36 ; <double> [#uses=1]
+ %arrayidx40 = getelementptr inbounds double* %x, i64 10 ; <double*> [#uses=1]
+ %tmp41 = load double* %arrayidx40 ; <double> [#uses=1]
+ %arrayidx44 = getelementptr inbounds double* %x, i64 11 ; <double*> [#uses=1]
+ %tmp45 = load double* %arrayidx44 ; <double> [#uses=1]
+ %arrayidx48 = getelementptr inbounds double* %x, i64 12 ; <double*> [#uses=1]
+ %tmp49 = load double* %arrayidx48 ; <double> [#uses=1]
+ %arrayidx52 = getelementptr inbounds double* %x, i64 13 ; <double*> [#uses=1]
+ %tmp53 = load double* %arrayidx52 ; <double> [#uses=1]
+ %arrayidx56 = getelementptr inbounds double* %x, i64 14 ; <double*> [#uses=1]
+ %tmp57 = load double* %arrayidx56 ; <double> [#uses=1]
+ %arrayidx60 = getelementptr inbounds double* %x, i64 15 ; <double*> [#uses=1]
+ %tmp61 = load double* %arrayidx60 ; <double> [#uses=1]
+ %arrayidx64 = getelementptr inbounds double* %x, i64 16 ; <double*> [#uses=1]
+ %tmp65 = load double* %arrayidx64 ; <double> [#uses=1]
+ %div = fdiv double %tmp1, 0.000000e+00 ; <double> [#uses=1]
+ store double %div, double* %y
+ %div70 = fdiv double %tmp5, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx72 = getelementptr inbounds double* %y, i64 1 ; <double*> [#uses=1]
+ store double %div70, double* %arrayidx72
+ %div74 = fdiv double %tmp9, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx76 = getelementptr inbounds double* %y, i64 2 ; <double*> [#uses=1]
+ store double %div74, double* %arrayidx76
+ %div78 = fdiv double %tmp13, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx80 = getelementptr inbounds double* %y, i64 3 ; <double*> [#uses=1]
+ store double %div78, double* %arrayidx80
+ %div82 = fdiv double %tmp17, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx84 = getelementptr inbounds double* %y, i64 4 ; <double*> [#uses=1]
+ store double %div82, double* %arrayidx84
+ %div86 = fdiv double %tmp21, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx88 = getelementptr inbounds double* %y, i64 5 ; <double*> [#uses=1]
+ store double %div86, double* %arrayidx88
+ %div90 = fdiv double %tmp25, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx92 = getelementptr inbounds double* %y, i64 6 ; <double*> [#uses=1]
+ store double %div90, double* %arrayidx92
+ %div94 = fdiv double %tmp29, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx96 = getelementptr inbounds double* %y, i64 7 ; <double*> [#uses=1]
+ store double %div94, double* %arrayidx96
+ %div98 = fdiv double %tmp33, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx100 = getelementptr inbounds double* %y, i64 8 ; <double*> [#uses=1]
+ store double %div98, double* %arrayidx100
+ %div102 = fdiv double %tmp37, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx104 = getelementptr inbounds double* %y, i64 9 ; <double*> [#uses=1]
+ store double %div102, double* %arrayidx104
+ %div106 = fdiv double %tmp41, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx108 = getelementptr inbounds double* %y, i64 10 ; <double*> [#uses=1]
+ store double %div106, double* %arrayidx108
+ %div110 = fdiv double %tmp45, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx112 = getelementptr inbounds double* %y, i64 11 ; <double*> [#uses=1]
+ store double %div110, double* %arrayidx112
+ %div114 = fdiv double %tmp49, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx116 = getelementptr inbounds double* %y, i64 12 ; <double*> [#uses=1]
+ store double %div114, double* %arrayidx116
+ %div118 = fdiv double %tmp53, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx120 = getelementptr inbounds double* %y, i64 13 ; <double*> [#uses=1]
+ store double %div118, double* %arrayidx120
+ %div122 = fdiv double %tmp57, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx124 = getelementptr inbounds double* %y, i64 14 ; <double*> [#uses=1]
+ store double %div122, double* %arrayidx124
+ %div126 = fdiv double %tmp61, 2.000000e-01 ; <double> [#uses=1]
+ %arrayidx128 = getelementptr inbounds double* %y, i64 15 ; <double*> [#uses=1]
+ store double %div126, double* %arrayidx128
+ %div130 = fdiv double %tmp65, 0.000000e+00 ; <double> [#uses=1]
+ %arrayidx132 = getelementptr inbounds double* %y, i64 16 ; <double*> [#uses=1]
+ store double %div130, double* %arrayidx132
+ ret void
+}
diff --git a/test/CodeGen/X86/ret-addr.ll b/test/CodeGen/X86/ret-addr.ll
new file mode 100644
index 0000000..b7b57ab
--- /dev/null
+++ b/test/CodeGen/X86/ret-addr.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -disable-fp-elim -march=x86 | not grep xor
+; RUN: llc < %s -disable-fp-elim -march=x86-64 | not grep xor
+
+define i8* @h() nounwind readnone optsize {
+entry:
+ %0 = tail call i8* @llvm.returnaddress(i32 2) ; <i8*> [#uses=1]
+ ret i8* %0
+}
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+define i8* @g() nounwind readnone optsize {
+entry:
+ %0 = tail call i8* @llvm.returnaddress(i32 1) ; <i8*> [#uses=1]
+ ret i8* %0
+}
+
+define i8* @f() nounwind readnone optsize {
+entry:
+ %0 = tail call i8* @llvm.returnaddress(i32 0) ; <i8*> [#uses=1]
+ ret i8* %0
+}
diff --git a/test/CodeGen/X86/ret-i64-0.ll b/test/CodeGen/X86/ret-i64-0.ll
new file mode 100644
index 0000000..bca0f05
--- /dev/null
+++ b/test/CodeGen/X86/ret-i64-0.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=x86 | grep xor | count 2
+
+define i64 @foo() nounwind {
+ ret i64 0
+}
diff --git a/test/CodeGen/X86/ret-mmx.ll b/test/CodeGen/X86/ret-mmx.ll
new file mode 100644
index 0000000..04b57dd
--- /dev/null
+++ b/test/CodeGen/X86/ret-mmx.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2
+; rdar://6602459
+
+@g_v1di = external global <1 x i64>
+
+define void @t1() nounwind {
+entry:
+ %call = call <1 x i64> @return_v1di() ; <<1 x i64>> [#uses=0]
+ store <1 x i64> %call, <1 x i64>* @g_v1di
+ ret void
+}
+
+declare <1 x i64> @return_v1di()
+
+define <1 x i64> @t2() nounwind {
+ ret <1 x i64> <i64 1>
+}
+
+define <2 x i32> @t3() nounwind {
+ ret <2 x i32> <i32 1, i32 0>
+}
+
+define double @t4() nounwind {
+ ret double bitcast (<2 x i32> <i32 1, i32 0> to double)
+}
+
diff --git a/test/CodeGen/X86/rip-rel-address.ll b/test/CodeGen/X86/rip-rel-address.ll
new file mode 100644
index 0000000..24ff07b
--- /dev/null
+++ b/test/CodeGen/X86/rip-rel-address.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86-64 -relocation-model=pic -mtriple=x86_64-apple-darwin10 | FileCheck %s -check-prefix=PIC64
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -relocation-model=static | FileCheck %s -check-prefix=STATIC64
+
+; Use %rip-relative addressing even in static mode on x86-64, because
+; it has a smaller encoding.
+
+@a = internal global double 3.4
+define double @foo() nounwind {
+ %a = load double* @a
+ ret double %a
+
+; PIC64: movsd _a(%rip), %xmm0
+; STATIC64: movsd a(%rip), %xmm0
+}
diff --git a/test/CodeGen/X86/rodata-relocs.ll b/test/CodeGen/X86/rodata-relocs.ll
new file mode 100644
index 0000000..276f8bb
--- /dev/null
+++ b/test/CodeGen/X86/rodata-relocs.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -relocation-model=static | grep rodata | count 3
+; RUN: llc < %s -relocation-model=static | grep -F "rodata.cst" | count 2
+; RUN: llc < %s -relocation-model=pic | grep rodata | count 2
+; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel.ro" | count 2
+; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel.ro.local" | count 1
+; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel" | count 4
+; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel.local" | count 1
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+@a = internal constant [2 x i32] [i32 1, i32 2]
+@a1 = constant [2 x i32] [i32 1, i32 2]
+@e = internal constant [2 x [2 x i32]] [[2 x i32] [i32 1, i32 2], [2 x i32] [i32 3, i32 4]], align 16
+@e1 = constant [2 x [2 x i32]] [[2 x i32] [i32 1, i32 2], [2 x i32] [i32 3, i32 4]], align 16
+@p = constant i8* bitcast ([2 x i32]* @a to i8*)
+@t = constant i8* bitcast ([2 x [2 x i32]]* @e to i8*)
+@p1 = constant i8* bitcast ([2 x i32]* @a1 to i8*)
+@t1 = constant i8* bitcast ([2 x [2 x i32]]* @e1 to i8*)
+@p2 = internal global i8* bitcast([2 x i32]* @a1 to i8*)
+@t2 = internal global i8* bitcast([2 x [2 x i32]]* @e1 to i8*)
+@p3 = internal global i8* bitcast([2 x i32]* @a to i8*)
+@t3 = internal global i8* bitcast([2 x [2 x i32]]* @e to i8*)
+
diff --git a/test/CodeGen/X86/rot16.ll b/test/CodeGen/X86/rot16.ll
new file mode 100644
index 0000000..42ece47
--- /dev/null
+++ b/test/CodeGen/X86/rot16.ll
@@ -0,0 +1,73 @@
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep rol %t | count 3
+; RUN: grep ror %t | count 1
+; RUN: grep shld %t | count 2
+; RUN: grep shrd %t | count 2
+
+define i16 @foo(i16 %x, i16 %y, i16 %z) nounwind readnone {
+entry:
+ %0 = shl i16 %x, %z
+ %1 = sub i16 16, %z
+ %2 = lshr i16 %x, %1
+ %3 = or i16 %2, %0
+ ret i16 %3
+}
+
+define i16 @bar(i16 %x, i16 %y, i16 %z) nounwind readnone {
+entry:
+ %0 = shl i16 %y, %z
+ %1 = sub i16 16, %z
+ %2 = lshr i16 %x, %1
+ %3 = or i16 %2, %0
+ ret i16 %3
+}
+
+define i16 @un(i16 %x, i16 %y, i16 %z) nounwind readnone {
+entry:
+ %0 = lshr i16 %x, %z
+ %1 = sub i16 16, %z
+ %2 = shl i16 %x, %1
+ %3 = or i16 %2, %0
+ ret i16 %3
+}
+
+define i16 @bu(i16 %x, i16 %y, i16 %z) nounwind readnone {
+entry:
+ %0 = lshr i16 %y, %z
+ %1 = sub i16 16, %z
+ %2 = shl i16 %x, %1
+ %3 = or i16 %2, %0
+ ret i16 %3
+}
+
+define i16 @xfoo(i16 %x, i16 %y, i16 %z) nounwind readnone {
+entry:
+ %0 = lshr i16 %x, 11
+ %1 = shl i16 %x, 5
+ %2 = or i16 %0, %1
+ ret i16 %2
+}
+
+define i16 @xbar(i16 %x, i16 %y, i16 %z) nounwind readnone {
+entry:
+ %0 = shl i16 %y, 5
+ %1 = lshr i16 %x, 11
+ %2 = or i16 %0, %1
+ ret i16 %2
+}
+
+define i16 @xun(i16 %x, i16 %y, i16 %z) nounwind readnone {
+entry:
+ %0 = lshr i16 %x, 5
+ %1 = shl i16 %x, 11
+ %2 = or i16 %0, %1
+ ret i16 %2
+}
+
+define i16 @xbu(i16 %x, i16 %y, i16 %z) nounwind readnone {
+entry:
+ %0 = lshr i16 %y, 5
+ %1 = shl i16 %x, 11
+ %2 = or i16 %0, %1
+ ret i16 %2
+}
diff --git a/test/CodeGen/X86/rot32.ll b/test/CodeGen/X86/rot32.ll
new file mode 100644
index 0000000..655ed27
--- /dev/null
+++ b/test/CodeGen/X86/rot32.ll
@@ -0,0 +1,73 @@
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep rol %t | count 3
+; RUN: grep ror %t | count 1
+; RUN: grep shld %t | count 2
+; RUN: grep shrd %t | count 2
+
+define i32 @foo(i32 %x, i32 %y, i32 %z) nounwind readnone {
+entry:
+ %0 = shl i32 %x, %z
+ %1 = sub i32 32, %z
+ %2 = lshr i32 %x, %1
+ %3 = or i32 %2, %0
+ ret i32 %3
+}
+
+define i32 @bar(i32 %x, i32 %y, i32 %z) nounwind readnone {
+entry:
+ %0 = shl i32 %y, %z
+ %1 = sub i32 32, %z
+ %2 = lshr i32 %x, %1
+ %3 = or i32 %2, %0
+ ret i32 %3
+}
+
+define i32 @un(i32 %x, i32 %y, i32 %z) nounwind readnone {
+entry:
+ %0 = lshr i32 %x, %z
+ %1 = sub i32 32, %z
+ %2 = shl i32 %x, %1
+ %3 = or i32 %2, %0
+ ret i32 %3
+}
+
+define i32 @bu(i32 %x, i32 %y, i32 %z) nounwind readnone {
+entry:
+ %0 = lshr i32 %y, %z
+ %1 = sub i32 32, %z
+ %2 = shl i32 %x, %1
+ %3 = or i32 %2, %0
+ ret i32 %3
+}
+
+define i32 @xfoo(i32 %x, i32 %y, i32 %z) nounwind readnone {
+entry:
+ %0 = lshr i32 %x, 25
+ %1 = shl i32 %x, 7
+ %2 = or i32 %0, %1
+ ret i32 %2
+}
+
+define i32 @xbar(i32 %x, i32 %y, i32 %z) nounwind readnone {
+entry:
+ %0 = shl i32 %y, 7
+ %1 = lshr i32 %x, 25
+ %2 = or i32 %0, %1
+ ret i32 %2
+}
+
+define i32 @xun(i32 %x, i32 %y, i32 %z) nounwind readnone {
+entry:
+ %0 = lshr i32 %x, 7
+ %1 = shl i32 %x, 25
+ %2 = or i32 %0, %1
+ ret i32 %2
+}
+
+define i32 @xbu(i32 %x, i32 %y, i32 %z) nounwind readnone {
+entry:
+ %0 = lshr i32 %y, 7
+ %1 = shl i32 %x, 25
+ %2 = or i32 %0, %1
+ ret i32 %2
+}
diff --git a/test/CodeGen/X86/rot64.ll b/test/CodeGen/X86/rot64.ll
new file mode 100644
index 0000000..4e082bb
--- /dev/null
+++ b/test/CodeGen/X86/rot64.ll
@@ -0,0 +1,73 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: grep rol %t | count 3
+; RUN: grep ror %t | count 1
+; RUN: grep shld %t | count 2
+; RUN: grep shrd %t | count 2
+
+define i64 @foo(i64 %x, i64 %y, i64 %z) nounwind readnone {
+entry:
+ %0 = shl i64 %x, %z
+ %1 = sub i64 64, %z
+ %2 = lshr i64 %x, %1
+ %3 = or i64 %2, %0
+ ret i64 %3
+}
+
+define i64 @bar(i64 %x, i64 %y, i64 %z) nounwind readnone {
+entry:
+ %0 = shl i64 %y, %z
+ %1 = sub i64 64, %z
+ %2 = lshr i64 %x, %1
+ %3 = or i64 %2, %0
+ ret i64 %3
+}
+
+define i64 @un(i64 %x, i64 %y, i64 %z) nounwind readnone {
+entry:
+ %0 = lshr i64 %x, %z
+ %1 = sub i64 64, %z
+ %2 = shl i64 %x, %1
+ %3 = or i64 %2, %0
+ ret i64 %3
+}
+
+define i64 @bu(i64 %x, i64 %y, i64 %z) nounwind readnone {
+entry:
+ %0 = lshr i64 %y, %z
+ %1 = sub i64 64, %z
+ %2 = shl i64 %x, %1
+ %3 = or i64 %2, %0
+ ret i64 %3
+}
+
+define i64 @xfoo(i64 %x, i64 %y, i64 %z) nounwind readnone {
+entry:
+ %0 = lshr i64 %x, 57
+ %1 = shl i64 %x, 7
+ %2 = or i64 %0, %1
+ ret i64 %2
+}
+
+define i64 @xbar(i64 %x, i64 %y, i64 %z) nounwind readnone {
+entry:
+ %0 = shl i64 %y, 7
+ %1 = lshr i64 %x, 57
+ %2 = or i64 %0, %1
+ ret i64 %2
+}
+
+define i64 @xun(i64 %x, i64 %y, i64 %z) nounwind readnone {
+entry:
+ %0 = lshr i64 %x, 7
+ %1 = shl i64 %x, 57
+ %2 = or i64 %0, %1
+ ret i64 %2
+}
+
+define i64 @xbu(i64 %x, i64 %y, i64 %z) nounwind readnone {
+entry:
+ %0 = lshr i64 %y, 7
+ %1 = shl i64 %x, 57
+ %2 = or i64 %0, %1
+ ret i64 %2
+}
diff --git a/test/CodeGen/X86/rotate.ll b/test/CodeGen/X86/rotate.ll
new file mode 100644
index 0000000..1e20273
--- /dev/null
+++ b/test/CodeGen/X86/rotate.ll
@@ -0,0 +1,100 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
+; RUN: grep {ro\[rl\]} | count 12
+
+define i32 @rotl32(i32 %A, i8 %Amt) {
+ %shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
+ %B = shl i32 %A, %shift.upgrd.1 ; <i32> [#uses=1]
+ %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
+ %shift.upgrd.2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
+ %C = lshr i32 %A, %shift.upgrd.2 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+define i32 @rotr32(i32 %A, i8 %Amt) {
+ %shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
+ %B = lshr i32 %A, %shift.upgrd.3 ; <i32> [#uses=1]
+ %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
+ %shift.upgrd.4 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
+ %C = shl i32 %A, %shift.upgrd.4 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+define i32 @rotli32(i32 %A) {
+ %B = shl i32 %A, 5 ; <i32> [#uses=1]
+ %C = lshr i32 %A, 27 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+define i32 @rotri32(i32 %A) {
+ %B = lshr i32 %A, 5 ; <i32> [#uses=1]
+ %C = shl i32 %A, 27 ; <i32> [#uses=1]
+ %D = or i32 %B, %C ; <i32> [#uses=1]
+ ret i32 %D
+}
+
+define i16 @rotl16(i16 %A, i8 %Amt) {
+ %shift.upgrd.5 = zext i8 %Amt to i16 ; <i16> [#uses=1]
+ %B = shl i16 %A, %shift.upgrd.5 ; <i16> [#uses=1]
+ %Amt2 = sub i8 16, %Amt ; <i8> [#uses=1]
+ %shift.upgrd.6 = zext i8 %Amt2 to i16 ; <i16> [#uses=1]
+ %C = lshr i16 %A, %shift.upgrd.6 ; <i16> [#uses=1]
+ %D = or i16 %B, %C ; <i16> [#uses=1]
+ ret i16 %D
+}
+
+define i16 @rotr16(i16 %A, i8 %Amt) {
+ %shift.upgrd.7 = zext i8 %Amt to i16 ; <i16> [#uses=1]
+ %B = lshr i16 %A, %shift.upgrd.7 ; <i16> [#uses=1]
+ %Amt2 = sub i8 16, %Amt ; <i8> [#uses=1]
+ %shift.upgrd.8 = zext i8 %Amt2 to i16 ; <i16> [#uses=1]
+ %C = shl i16 %A, %shift.upgrd.8 ; <i16> [#uses=1]
+ %D = or i16 %B, %C ; <i16> [#uses=1]
+ ret i16 %D
+}
+
+define i16 @rotli16(i16 %A) {
+ %B = shl i16 %A, 5 ; <i16> [#uses=1]
+ %C = lshr i16 %A, 11 ; <i16> [#uses=1]
+ %D = or i16 %B, %C ; <i16> [#uses=1]
+ ret i16 %D
+}
+
+define i16 @rotri16(i16 %A) {
+ %B = lshr i16 %A, 5 ; <i16> [#uses=1]
+ %C = shl i16 %A, 11 ; <i16> [#uses=1]
+ %D = or i16 %B, %C ; <i16> [#uses=1]
+ ret i16 %D
+}
+
+define i8 @rotl8(i8 %A, i8 %Amt) {
+ %B = shl i8 %A, %Amt ; <i8> [#uses=1]
+ %Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
+ %C = lshr i8 %A, %Amt2 ; <i8> [#uses=1]
+ %D = or i8 %B, %C ; <i8> [#uses=1]
+ ret i8 %D
+}
+
+define i8 @rotr8(i8 %A, i8 %Amt) {
+ %B = lshr i8 %A, %Amt ; <i8> [#uses=1]
+ %Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
+ %C = shl i8 %A, %Amt2 ; <i8> [#uses=1]
+ %D = or i8 %B, %C ; <i8> [#uses=1]
+ ret i8 %D
+}
+
+define i8 @rotli8(i8 %A) {
+ %B = shl i8 %A, 5 ; <i8> [#uses=1]
+ %C = lshr i8 %A, 3 ; <i8> [#uses=1]
+ %D = or i8 %B, %C ; <i8> [#uses=1]
+ ret i8 %D
+}
+
+define i8 @rotri8(i8 %A) {
+ %B = lshr i8 %A, 5 ; <i8> [#uses=1]
+ %C = shl i8 %A, 3 ; <i8> [#uses=1]
+ %D = or i8 %B, %C ; <i8> [#uses=1]
+ ret i8 %D
+}
diff --git a/test/CodeGen/X86/rotate2.ll b/test/CodeGen/X86/rotate2.ll
new file mode 100644
index 0000000..2eea399
--- /dev/null
+++ b/test/CodeGen/X86/rotate2.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86-64 | grep rol | count 2
+
+define i64 @test1(i64 %x) nounwind {
+entry:
+ %tmp2 = lshr i64 %x, 55 ; <i64> [#uses=1]
+ %tmp4 = shl i64 %x, 9 ; <i64> [#uses=1]
+ %tmp5 = or i64 %tmp2, %tmp4 ; <i64> [#uses=1]
+ ret i64 %tmp5
+}
+
+define i64 @test2(i32 %x) nounwind {
+entry:
+ %tmp2 = lshr i32 %x, 22 ; <i32> [#uses=1]
+ %tmp4 = shl i32 %x, 10 ; <i32> [#uses=1]
+ %tmp5 = or i32 %tmp2, %tmp4 ; <i32> [#uses=1]
+ %tmp56 = zext i32 %tmp5 to i64 ; <i64> [#uses=1]
+ ret i64 %tmp56
+}
+
diff --git a/test/CodeGen/X86/scalar-extract.ll b/test/CodeGen/X86/scalar-extract.ll
new file mode 100644
index 0000000..2845838
--- /dev/null
+++ b/test/CodeGen/X86/scalar-extract.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx -o %t
+; RUN: not grep movq %t
+
+; Check that widening doesn't introduce a mmx register in this case when
+; a simple load/store would suffice.
+
+define void @foo(<2 x i16>* %A, <2 x i16>* %B) {
+entry:
+ %tmp1 = load <2 x i16>* %A ; <<2 x i16>> [#uses=1]
+ store <2 x i16> %tmp1, <2 x i16>* %B
+ ret void
+}
+
diff --git a/test/CodeGen/X86/scalar-min-max-fill-operand.ll b/test/CodeGen/X86/scalar-min-max-fill-operand.ll
new file mode 100644
index 0000000..fe40758
--- /dev/null
+++ b/test/CodeGen/X86/scalar-min-max-fill-operand.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86-64 | grep min | count 1
+; RUN: llc < %s -march=x86-64 | grep max | count 1
+; RUN: llc < %s -march=x86-64 | grep mov | count 2
+
+declare float @bar()
+
+define float @foo(float %a) nounwind
+{
+ %s = call float @bar()
+ %t = fcmp olt float %s, %a
+ %u = select i1 %t, float %s, float %a
+ ret float %u
+}
+define float @hem(float %a) nounwind
+{
+ %s = call float @bar()
+ %t = fcmp ogt float %s, %a
+ %u = select i1 %t, float %s, float %a
+ ret float %u
+}
diff --git a/test/CodeGen/X86/scalar_sse_minmax.ll b/test/CodeGen/X86/scalar_sse_minmax.ll
new file mode 100644
index 0000000..bc4ab5d
--- /dev/null
+++ b/test/CodeGen/X86/scalar_sse_minmax.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -march=x86 -mattr=+sse,+sse2 | \
+; RUN: grep mins | count 3
+; RUN: llc < %s -march=x86 -mattr=+sse,+sse2 | \
+; RUN: grep maxs | count 2
+
+declare i1 @llvm.isunordered.f64(double, double)
+
+declare i1 @llvm.isunordered.f32(float, float)
+
+define float @min1(float %x, float %y) {
+ %tmp = fcmp olt float %x, %y ; <i1> [#uses=1]
+ %retval = select i1 %tmp, float %x, float %y ; <float> [#uses=1]
+ ret float %retval
+}
+
+define double @min2(double %x, double %y) {
+ %tmp = fcmp olt double %x, %y ; <i1> [#uses=1]
+ %retval = select i1 %tmp, double %x, double %y ; <double> [#uses=1]
+ ret double %retval
+}
+
+define float @max1(float %x, float %y) {
+ %tmp = fcmp oge float %x, %y ; <i1> [#uses=1]
+ %tmp2 = fcmp uno float %x, %y ; <i1> [#uses=1]
+ %tmp3 = or i1 %tmp2, %tmp ; <i1> [#uses=1]
+ %retval = select i1 %tmp3, float %x, float %y ; <float> [#uses=1]
+ ret float %retval
+}
+
+define double @max2(double %x, double %y) {
+ %tmp = fcmp oge double %x, %y ; <i1> [#uses=1]
+ %tmp2 = fcmp uno double %x, %y ; <i1> [#uses=1]
+ %tmp3 = or i1 %tmp2, %tmp ; <i1> [#uses=1]
+ %retval = select i1 %tmp3, double %x, double %y ; <double> [#uses=1]
+ ret double %retval
+}
+
+define <4 x float> @min3(float %tmp37) {
+ %tmp375 = insertelement <4 x float> undef, float %tmp37, i32 0 ; <<4 x float>> [#uses=1]
+ %tmp48 = tail call <4 x float> @llvm.x86.sse.min.ss( <4 x float> %tmp375, <4 x float> < float 6.553500e+04, float undef, float undef, float undef > ) ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp48
+}
+
+declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>)
diff --git a/test/CodeGen/X86/scalar_widen_div.ll b/test/CodeGen/X86/scalar_widen_div.ll
new file mode 100644
index 0000000..fc67e44
--- /dev/null
+++ b/test/CodeGen/X86/scalar_widen_div.ll
@@ -0,0 +1,154 @@
+; RUN: llc < %s -disable-mmx -march=x86-64 -mattr=+sse42 | FileCheck %s
+
+; Verify when widening a divide/remainder operation, we only generate a
+; divide/rem per element since divide/remainder can trap.
+
+define void @vectorDiv (<2 x i32> addrspace(1)* %nsource, <2 x i32> addrspace(1)* %dsource, <2 x i32> addrspace(1)* %qdest) nounwind {
+; CHECK: idivl
+; CHECK: idivl
+; CHECK-NOT: idivl
+; CHECK: ret
+entry:
+ %nsource.addr = alloca <2 x i32> addrspace(1)*, align 4
+ %dsource.addr = alloca <2 x i32> addrspace(1)*, align 4
+ %qdest.addr = alloca <2 x i32> addrspace(1)*, align 4
+ %index = alloca i32, align 4
+ store <2 x i32> addrspace(1)* %nsource, <2 x i32> addrspace(1)** %nsource.addr
+ store <2 x i32> addrspace(1)* %dsource, <2 x i32> addrspace(1)** %dsource.addr
+ store <2 x i32> addrspace(1)* %qdest, <2 x i32> addrspace(1)** %qdest.addr
+ %tmp = load <2 x i32> addrspace(1)** %qdest.addr
+ %tmp1 = load i32* %index
+ %arrayidx = getelementptr <2 x i32> addrspace(1)* %tmp, i32 %tmp1
+ %tmp2 = load <2 x i32> addrspace(1)** %nsource.addr
+ %tmp3 = load i32* %index
+ %arrayidx4 = getelementptr <2 x i32> addrspace(1)* %tmp2, i32 %tmp3
+ %tmp5 = load <2 x i32> addrspace(1)* %arrayidx4
+ %tmp6 = load <2 x i32> addrspace(1)** %dsource.addr
+ %tmp7 = load i32* %index
+ %arrayidx8 = getelementptr <2 x i32> addrspace(1)* %tmp6, i32 %tmp7
+ %tmp9 = load <2 x i32> addrspace(1)* %arrayidx8
+ %tmp10 = sdiv <2 x i32> %tmp5, %tmp9
+ store <2 x i32> %tmp10, <2 x i32> addrspace(1)* %arrayidx
+ ret void
+}
+
+define <3 x i8> @test_char_div(<3 x i8> %num, <3 x i8> %div) {
+; CHECK: idivb
+; CHECK: idivb
+; CHECK: idivb
+; CHECK-NOT: idivb
+; CHECK: ret
+ %div.r = sdiv <3 x i8> %num, %div
+ ret <3 x i8> %div.r
+}
+
+define <3 x i8> @test_uchar_div(<3 x i8> %num, <3 x i8> %div) {
+; CHECK: divb
+; CHECK: divb
+; CHECK: divb
+; CHECK-NOT: divb
+; CHECK: ret
+ %div.r = udiv <3 x i8> %num, %div
+ ret <3 x i8> %div.r
+}
+
+define <5 x i16> @test_short_div(<5 x i16> %num, <5 x i16> %div) {
+; CHECK: idivw
+; CHECK: idivw
+; CHECK: idivw
+; CHECK: idivw
+; CHECK: idivw
+; CHECK-NOT: idivw
+; CHECK: ret
+ %div.r = sdiv <5 x i16> %num, %div
+ ret <5 x i16> %div.r
+}
+
+define <4 x i16> @test_ushort_div(<4 x i16> %num, <4 x i16> %div) {
+; CHECK: divw
+; CHECK: divw
+; CHECK: divw
+; CHECK: divw
+; CHECK-NOT: divw
+; CHECK: ret
+ %div.r = udiv <4 x i16> %num, %div
+ ret <4 x i16> %div.r
+}
+
+define <3 x i32> @test_uint_div(<3 x i32> %num, <3 x i32> %div) {
+; CHECK: divl
+; CHECK: divl
+; CHECK: divl
+; CHECK-NOT: divl
+; CHECK: ret
+ %div.r = udiv <3 x i32> %num, %div
+ ret <3 x i32> %div.r
+}
+
+define <3 x i64> @test_long_div(<3 x i64> %num, <3 x i64> %div) {
+; CHECK: idivq
+; CHECK: idivq
+; CHECK: idivq
+; CHECK-NOT: idivq
+; CHECK: ret
+ %div.r = sdiv <3 x i64> %num, %div
+ ret <3 x i64> %div.r
+}
+
+define <3 x i64> @test_ulong_div(<3 x i64> %num, <3 x i64> %div) {
+; CHECK: divq
+; CHECK: divq
+; CHECK: divq
+; CHECK-NOT: divq
+; CHECK: ret
+ %div.r = udiv <3 x i64> %num, %div
+ ret <3 x i64> %div.r
+}
+
+
+define <4 x i8> @test_char_rem(<4 x i8> %num, <4 x i8> %rem) {
+; CHECK: idivb
+; CHECK: idivb
+; CHECK: idivb
+; CHECK: idivb
+; CHECK-NOT: idivb
+; CHECK: ret
+ %rem.r = srem <4 x i8> %num, %rem
+ ret <4 x i8> %rem.r
+}
+
+define <5 x i16> @test_short_rem(<5 x i16> %num, <5 x i16> %rem) {
+; CHECK: idivw
+; CHECK: idivw
+; CHECK: idivw
+; CHECK: idivw
+; CHECK: idivw
+; CHECK-NOT: idivw
+; CHECK: ret
+ %rem.r = srem <5 x i16> %num, %rem
+ ret <5 x i16> %rem.r
+}
+
+define <4 x i32> @test_uint_rem(<4 x i32> %num, <4 x i32> %rem) {
+; CHECK: idivl
+; CHECK: idivl
+; CHECK: idivl
+; CHECK: idivl
+; CHECK-NOT: idivl
+; CHECK: ret
+ %rem.r = srem <4 x i32> %num, %rem
+ ret <4 x i32> %rem.r
+}
+
+
+define <5 x i64> @test_ulong_rem(<5 x i64> %num, <5 x i64> %rem) {
+; CHECK: divq
+; CHECK: divq
+; CHECK: divq
+; CHECK: divq
+; CHECK: divq
+; CHECK-NOT: divq
+; CHECK: ret
+ %rem.r = urem <5 x i64> %num, %rem
+ ret <5 x i64> %rem.r
+}
diff --git a/test/CodeGen/X86/scalarize-bitcast.ll b/test/CodeGen/X86/scalarize-bitcast.ll
new file mode 100644
index 0000000..f6b29ec
--- /dev/null
+++ b/test/CodeGen/X86/scalarize-bitcast.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=x86-64
+; PR3886
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "x86_64-pc-linux-gnu"
+
+define void @mmxCombineMaskU(i32* nocapture %src, i32* nocapture %mask) nounwind {
+entry:
+ %tmp1 = load i32* %src ; <i32> [#uses=1]
+ %0 = insertelement <2 x i32> undef, i32 %tmp1, i32 0 ; <<2 x i32>> [#uses=1]
+ %1 = insertelement <2 x i32> %0, i32 0, i32 1 ; <<2 x i32>> [#uses=1]
+ %conv.i.i = bitcast <2 x i32> %1 to <1 x i64> ; <<1 x i64>> [#uses=1]
+ %tmp2.i.i = extractelement <1 x i64> %conv.i.i, i32 0 ; <i64> [#uses=1]
+ %tmp22.i = bitcast i64 %tmp2.i.i to <1 x i64> ; <<1 x i64>> [#uses=1]
+ %tmp15.i = extractelement <1 x i64> %tmp22.i, i32 0 ; <i64> [#uses=1]
+ %conv.i26.i = bitcast i64 %tmp15.i to <8 x i8> ; <<8 x i8>> [#uses=1]
+ %shuffle.i.i = shufflevector <8 x i8> %conv.i26.i, <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef>, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> ; <<8 x i8>> [#uses=1]
+ %conv6.i.i = bitcast <8 x i8> %shuffle.i.i to <1 x i64> ; <<1 x i64>> [#uses=1]
+ %tmp12.i.i = extractelement <1 x i64> %conv6.i.i, i32 0 ; <i64> [#uses=1]
+ %tmp10.i = bitcast i64 %tmp12.i.i to <1 x i64> ; <<1 x i64>> [#uses=1]
+ %tmp24.i = extractelement <1 x i64> %tmp10.i, i32 0 ; <i64> [#uses=1]
+ %tmp10 = bitcast i64 %tmp24.i to <1 x i64> ; <<1 x i64>> [#uses=1]
+ %tmp7 = extractelement <1 x i64> %tmp10, i32 0 ; <i64> [#uses=1]
+ %call6 = tail call i32 (...)* @store8888(i64 %tmp7) ; <i32> [#uses=1]
+ store i32 %call6, i32* %src
+ ret void
+}
+
+declare i32 @store8888(...)
diff --git a/test/CodeGen/X86/scev-interchange.ll b/test/CodeGen/X86/scev-interchange.ll
new file mode 100644
index 0000000..81c919f
--- /dev/null
+++ b/test/CodeGen/X86/scev-interchange.ll
@@ -0,0 +1,338 @@
+; RUN: llc < %s -march=x86-64
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+ %"struct.DataOutBase::GmvFlags" = type { i32 }
+ %"struct.FE_DGPNonparametric<3>" = type { [1156 x i8], i32, %"struct.PolynomialSpace<1>" }
+ %"struct.FiniteElementData<1>" = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+ %struct.Line = type { [2 x i32] }
+ %"struct.PolynomialSpace<1>" = type { %"struct.std::vector<Polynomials::Polynomial<double>,std::allocator<Polynomials::Polynomial<double> > >", i32, %"struct.std::vector<int,std::allocator<int> >", %"struct.std::vector<int,std::allocator<int> >" }
+ %"struct.Polynomials::Polynomial<double>" = type { %struct.Subscriptor, %"struct.std::vector<double,std::allocator<double> >" }
+ %struct.Subscriptor = type { i32 (...)**, i32, %"struct.std::type_info"* }
+ %"struct.TableBase<2,double>" = type { %struct.Subscriptor, double*, i32, %"struct.TableIndices<2>" }
+ %"struct.TableIndices<2>" = type { %struct.Line }
+ %"struct.std::_Bit_const_iterator" = type { %"struct.std::_Bit_iterator_base" }
+ %"struct.std::_Bit_iterator_base" = type { i64*, i32 }
+ %"struct.std::_Bvector_base<std::allocator<bool> >" = type { %"struct.std::_Bvector_base<std::allocator<bool> >::_Bvector_impl" }
+ %"struct.std::_Bvector_base<std::allocator<bool> >::_Bvector_impl" = type { %"struct.std::_Bit_const_iterator", %"struct.std::_Bit_const_iterator", i64* }
+ %"struct.std::_Vector_base<Polynomials::Polynomial<double>,std::allocator<Polynomials::Polynomial<double> > >" = type { %"struct.std::_Vector_base<Polynomials::Polynomial<double>,std::allocator<Polynomials::Polynomial<double> > >::_Vector_impl" }
+ %"struct.std::_Vector_base<Polynomials::Polynomial<double>,std::allocator<Polynomials::Polynomial<double> > >::_Vector_impl" = type { %"struct.Polynomials::Polynomial<double>"*, %"struct.Polynomials::Polynomial<double>"*, %"struct.Polynomials::Polynomial<double>"* }
+ %"struct.std::_Vector_base<double,std::allocator<double> >" = type { %"struct.std::_Vector_base<double,std::allocator<double> >::_Vector_impl" }
+ %"struct.std::_Vector_base<double,std::allocator<double> >::_Vector_impl" = type { double*, double*, double* }
+ %"struct.std::_Vector_base<int,std::allocator<int> >" = type { %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl" }
+ %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl" = type { i32*, i32*, i32* }
+ %"struct.std::_Vector_base<std::vector<bool, std::allocator<bool> >,std::allocator<std::vector<bool, std::allocator<bool> > > >" = type { %"struct.std::_Vector_base<std::vector<bool, std::allocator<bool> >,std::allocator<std::vector<bool, std::allocator<bool> > > >::_Vector_impl" }
+ %"struct.std::_Vector_base<std::vector<bool, std::allocator<bool> >,std::allocator<std::vector<bool, std::allocator<bool> > > >::_Vector_impl" = type { %"struct.std::vector<bool,std::allocator<bool> >"*, %"struct.std::vector<bool,std::allocator<bool> >"*, %"struct.std::vector<bool,std::allocator<bool> >"* }
+ %"struct.std::type_info" = type { i32 (...)**, i8* }
+ %"struct.std::vector<Polynomials::Polynomial<double>,std::allocator<Polynomials::Polynomial<double> > >" = type { %"struct.std::_Vector_base<Polynomials::Polynomial<double>,std::allocator<Polynomials::Polynomial<double> > >" }
+ %"struct.std::vector<bool,std::allocator<bool> >" = type { %"struct.std::_Bvector_base<std::allocator<bool> >" }
+ %"struct.std::vector<double,std::allocator<double> >" = type { %"struct.std::_Vector_base<double,std::allocator<double> >" }
+ %"struct.std::vector<int,std::allocator<int> >" = type { %"struct.std::_Vector_base<int,std::allocator<int> >" }
+ %"struct.std::vector<std::vector<bool, std::allocator<bool> >,std::allocator<std::vector<bool, std::allocator<bool> > > >" = type { %"struct.std::_Vector_base<std::vector<bool, std::allocator<bool> >,std::allocator<std::vector<bool, std::allocator<bool> > > >" }
+
+declare void @_Unwind_Resume(i8*)
+
+declare i8* @_Znwm(i64)
+
+declare fastcc void @_ZNSt6vectorIjSaIjEEaSERKS1_(%"struct.std::vector<int,std::allocator<int> >"*, %"struct.std::vector<int,std::allocator<int> >"*)
+
+declare fastcc void @_ZN9TableBaseILi2EdE6reinitERK12TableIndicesILi2EE(%"struct.TableBase<2,double>"* nocapture, i32, i32)
+
+declare fastcc void @_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_(%"struct.std::vector<bool,std::allocator<bool> >"* nocapture, i64, i8* nocapture)
+
+declare fastcc void @_ZNSt6vectorIS_IbSaIbEESaIS1_EEC2EmRKS1_RKS2_(%"struct.std::vector<std::vector<bool, std::allocator<bool> >,std::allocator<std::vector<bool, std::allocator<bool> > > >"* nocapture, i64, %"struct.std::vector<bool,std::allocator<bool> >"* nocapture)
+
+declare fastcc void @_ZNSt6vectorIN11Polynomials10PolynomialIdEESaIS2_EED1Ev(%"struct.std::vector<Polynomials::Polynomial<double>,std::allocator<Polynomials::Polynomial<double> > >"* nocapture)
+
+declare fastcc void @_ZN24TensorProductPolynomialsILi3EEC2IN11Polynomials10PolynomialIdEEEERKSt6vectorIT_SaIS6_EE(%"struct.PolynomialSpace<1>"* nocapture, %"struct.std::vector<Polynomials::Polynomial<double>,std::allocator<Polynomials::Polynomial<double> > >"* nocapture)
+
+declare fastcc void @_ZN7FE_PolyI24TensorProductPolynomialsILi3EELi3EEC2EjRKS1_RK17FiniteElementDataILi3EERKSt6vectorIbSaIbEERKS9_ISB_SaISB_EE(%"struct.FE_DGPNonparametric<3>"*, i32, %"struct.PolynomialSpace<1>"* nocapture, %"struct.FiniteElementData<1>"* nocapture, %"struct.std::vector<bool,std::allocator<bool> >"* nocapture, %"struct.std::vector<std::vector<bool, std::allocator<bool> >,std::allocator<std::vector<bool, std::allocator<bool> > > >"* nocapture)
+
+declare fastcc void @_ZN11FE_Q_Helper12_GLOBAL__N_116invert_numberingERKSt6vectorIjSaIjEE(%"struct.std::vector<int,std::allocator<int> >"* noalias nocapture sret, %"struct.std::vector<int,std::allocator<int> >"* nocapture)
+
+declare fastcc void @_ZN4FE_QILi3EE14get_dpo_vectorEj(%"struct.std::vector<int,std::allocator<int> >"* noalias nocapture sret, i32)
+
+define fastcc void @_ZN4FE_QILi3EEC1Ej(i32 %degree) {
+entry:
+ invoke fastcc void @_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_(%"struct.std::vector<bool,std::allocator<bool> >"* undef, i64 1, i8* undef)
+ to label %invcont.i unwind label %lpad.i
+
+invcont.i: ; preds = %entry
+ invoke fastcc void @_ZN4FE_QILi3EE14get_dpo_vectorEj(%"struct.std::vector<int,std::allocator<int> >"* noalias sret undef, i32 %degree)
+ to label %invcont1.i unwind label %lpad120.i
+
+invcont1.i: ; preds = %invcont.i
+ invoke fastcc void @_ZNSt6vectorIS_IbSaIbEESaIS1_EEC2EmRKS1_RKS2_(%"struct.std::vector<std::vector<bool, std::allocator<bool> >,std::allocator<std::vector<bool, std::allocator<bool> > > >"* undef, i64 undef, %"struct.std::vector<bool,std::allocator<bool> >"* undef)
+ to label %invcont3.i unwind label %lpad124.i
+
+invcont3.i: ; preds = %invcont1.i
+ invoke fastcc void @_ZN4FE_QILi3EE14get_dpo_vectorEj(%"struct.std::vector<int,std::allocator<int> >"* noalias sret undef, i32 %degree)
+ to label %invcont4.i unwind label %lpad128.i
+
+invcont4.i: ; preds = %invcont3.i
+ invoke fastcc void @_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_(%"struct.std::vector<bool,std::allocator<bool> >"* undef, i64 undef, i8* undef)
+ to label %invcont6.i unwind label %lpad132.i
+
+invcont6.i: ; preds = %invcont4.i
+ invoke fastcc void @_ZN4FE_QILi3EE14get_dpo_vectorEj(%"struct.std::vector<int,std::allocator<int> >"* noalias sret undef, i32 %degree)
+ to label %invcont7.i unwind label %lpad136.i
+
+invcont7.i: ; preds = %invcont6.i
+ invoke fastcc void @_ZN11Polynomials19LagrangeEquidistant23generate_complete_basisEj(%"struct.std::vector<Polynomials::Polynomial<double>,std::allocator<Polynomials::Polynomial<double> > >"* noalias sret undef, i32 %degree)
+ to label %invcont9.i unwind label %lpad140.i
+
+invcont9.i: ; preds = %invcont7.i
+ invoke fastcc void @_ZN24TensorProductPolynomialsILi3EEC2IN11Polynomials10PolynomialIdEEEERKSt6vectorIT_SaIS6_EE(%"struct.PolynomialSpace<1>"* undef, %"struct.std::vector<Polynomials::Polynomial<double>,std::allocator<Polynomials::Polynomial<double> > >"* undef)
+ to label %invcont10.i unwind label %lpad144.i
+
+invcont10.i: ; preds = %invcont9.i
+ invoke fastcc void @_ZN7FE_PolyI24TensorProductPolynomialsILi3EELi3EEC2EjRKS1_RK17FiniteElementDataILi3EERKSt6vectorIbSaIbEERKS9_ISB_SaISB_EE(%"struct.FE_DGPNonparametric<3>"* undef, i32 %degree, %"struct.PolynomialSpace<1>"* undef, %"struct.FiniteElementData<1>"* undef, %"struct.std::vector<bool,std::allocator<bool> >"* undef, %"struct.std::vector<std::vector<bool, std::allocator<bool> >,std::allocator<std::vector<bool, std::allocator<bool> > > >"* undef)
+ to label %bb14.i unwind label %lpad148.i
+
+bb14.i: ; preds = %invcont10.i
+ br i1 false, label %bb3.i164.i, label %bb.i.i.i.i160.i
+
+bb.i.i.i.i160.i: ; preds = %bb14.i
+ unreachable
+
+bb3.i164.i: ; preds = %bb14.i
+ br i1 undef, label %bb10.i168.i, label %bb.i.i.i20.i166.i
+
+bb.i.i.i20.i166.i: ; preds = %bb3.i164.i
+ unreachable
+
+bb10.i168.i: ; preds = %bb3.i164.i
+ invoke fastcc void @_ZNSt6vectorIN11Polynomials10PolynomialIdEESaIS2_EED1Ev(%"struct.std::vector<Polynomials::Polynomial<double>,std::allocator<Polynomials::Polynomial<double> > >"* undef)
+ to label %bb21.i unwind label %lpad144.i
+
+bb21.i: ; preds = %bb10.i168.i
+ invoke fastcc void @_ZNSt6vectorIN11Polynomials10PolynomialIdEESaIS2_EED1Ev(%"struct.std::vector<Polynomials::Polynomial<double>,std::allocator<Polynomials::Polynomial<double> > >"* undef)
+ to label %bb28.i unwind label %lpad140.i
+
+bb28.i: ; preds = %bb21.i
+ br i1 undef, label %bb35.i, label %bb.i.i.i175.i
+
+bb.i.i.i175.i: ; preds = %bb28.i
+ br label %bb35.i
+
+bb35.i: ; preds = %bb.i.i.i175.i, %bb28.i
+ br i1 undef, label %bb42.i, label %bb.i.i.i205.i
+
+bb.i.i.i205.i: ; preds = %bb35.i
+ unreachable
+
+bb42.i: ; preds = %bb35.i
+ br i1 undef, label %bb47.i, label %bb.i.i.i213.i
+
+bb.i.i.i213.i: ; preds = %bb42.i
+ unreachable
+
+bb47.i: ; preds = %bb42.i
+ br i1 undef, label %bb59.i, label %bb.i.i.i247.i
+
+bb.i.i.i247.i: ; preds = %bb47.i
+ unreachable
+
+bb59.i: ; preds = %bb47.i
+ br i1 undef, label %bb66.i, label %bb.i.i.i255.i
+
+bb.i.i.i255.i: ; preds = %bb59.i
+ unreachable
+
+bb66.i: ; preds = %bb59.i
+ br i1 undef, label %bb71.i, label %bb.i.i.i262.i
+
+bb.i.i.i262.i: ; preds = %bb66.i
+ br label %bb71.i
+
+bb71.i: ; preds = %bb.i.i.i262.i, %bb66.i
+ %tmp11.i.i29.i.i.i.i.i.i = invoke i8* @_Znwm(i64 12)
+ to label %_ZNSt12_Vector_baseIjSaIjEEC2EmRKS0_.exit.i.i.i.i.i unwind label %lpad.i.i.i.i.i.i ; <i8*> [#uses=0]
+
+lpad.i.i.i.i.i.i: ; preds = %bb71.i
+ unreachable
+
+_ZNSt12_Vector_baseIjSaIjEEC2EmRKS0_.exit.i.i.i.i.i: ; preds = %bb71.i
+ br i1 undef, label %_ZNSt6vectorIjSaIjEED1Ev.exit.i.i, label %bb.i.i.i.i94.i
+
+bb.i.i.i.i94.i: ; preds = %_ZNSt12_Vector_baseIjSaIjEEC2EmRKS0_.exit.i.i.i.i.i
+ unreachable
+
+_ZNSt6vectorIjSaIjEED1Ev.exit.i.i: ; preds = %_ZNSt12_Vector_baseIjSaIjEEC2EmRKS0_.exit.i.i.i.i.i
+ %tmp11.i.i29.i.i.i.i5.i.i = invoke i8* @_Znwm(i64 undef)
+ to label %_ZNSt12_Vector_baseIjSaIjEEC2EmRKS0_.exit.i.i.i12.i.i unwind label %lpad.i.i.i.i8.i.i ; <i8*> [#uses=0]
+
+lpad.i.i.i.i8.i.i: ; preds = %_ZNSt6vectorIjSaIjEED1Ev.exit.i.i
+ invoke void @_Unwind_Resume(i8* undef)
+ to label %.noexc.i9.i.i unwind label %lpad.i19.i.i
+
+.noexc.i9.i.i: ; preds = %lpad.i.i.i.i8.i.i
+ unreachable
+
+_ZNSt12_Vector_baseIjSaIjEEC2EmRKS0_.exit.i.i.i12.i.i: ; preds = %_ZNSt6vectorIjSaIjEED1Ev.exit.i.i
+ br i1 undef, label %bb50.i.i.i, label %bb.i.i.i.i.i.i.i.i.i.i
+
+bb.i.i.i.i.i.i.i.i.i.i: ; preds = %bb.i.i.i.i.i.i.i.i.i.i, %_ZNSt12_Vector_baseIjSaIjEEC2EmRKS0_.exit.i.i.i12.i.i
+ br i1 undef, label %bb50.i.i.i, label %bb.i.i.i.i.i.i.i.i.i.i
+
+bb50.i.i.i: ; preds = %bb.i.i.i.i.i.i.i.i.i.i, %_ZNSt12_Vector_baseIjSaIjEEC2EmRKS0_.exit.i.i.i12.i.i
+ invoke fastcc void @_ZN11FE_Q_Helper12_GLOBAL__N_116invert_numberingERKSt6vectorIjSaIjEE(%"struct.std::vector<int,std::allocator<int> >"* noalias sret undef, %"struct.std::vector<int,std::allocator<int> >"* undef)
+ to label %bb83.i unwind label %lpad188.i
+
+lpad.i19.i.i: ; preds = %lpad.i.i.i.i8.i.i
+ unreachable
+
+bb83.i: ; preds = %bb50.i.i.i
+ br i1 undef, label %invcont84.i, label %bb.i.i.i221.i
+
+bb.i.i.i221.i: ; preds = %bb83.i
+ unreachable
+
+invcont84.i: ; preds = %bb83.i
+ %tmp11.i.i29.i.i.i.i.i = invoke i8* @_Znwm(i64 undef)
+ to label %_ZNSt12_Vector_baseIjSaIjEEC2EmRKS0_.exit.i.i.i.i unwind label %lpad.i.i.i.i315.i ; <i8*> [#uses=0]
+
+lpad.i.i.i.i315.i: ; preds = %invcont84.i
+ invoke void @_Unwind_Resume(i8* undef)
+ to label %.noexc.i316.i unwind label %lpad.i352.i
+
+.noexc.i316.i: ; preds = %lpad.i.i.i.i315.i
+ unreachable
+
+_ZNSt12_Vector_baseIjSaIjEEC2EmRKS0_.exit.i.i.i.i: ; preds = %invcont84.i
+ br i1 undef, label %bb50.i.i, label %bb.i.i.i.i.i.i.i.i320.i
+
+bb.i.i.i.i.i.i.i.i320.i: ; preds = %bb.i.i.i.i.i.i.i.i320.i, %_ZNSt12_Vector_baseIjSaIjEEC2EmRKS0_.exit.i.i.i.i
+ br i1 undef, label %bb50.i.i, label %bb.i.i.i.i.i.i.i.i320.i
+
+bb50.i.i: ; preds = %bb.i.i.i.i.i.i.i.i320.i, %_ZNSt12_Vector_baseIjSaIjEEC2EmRKS0_.exit.i.i.i.i
+ invoke fastcc void @_ZN11FE_Q_Helper12_GLOBAL__N_116invert_numberingERKSt6vectorIjSaIjEE(%"struct.std::vector<int,std::allocator<int> >"* noalias sret undef, %"struct.std::vector<int,std::allocator<int> >"* undef)
+ to label %invcont86.i unwind label %lpad200.i
+
+lpad.i352.i: ; preds = %lpad.i.i.i.i315.i
+ unreachable
+
+invcont86.i: ; preds = %bb50.i.i
+ invoke fastcc void @_ZNSt6vectorIjSaIjEEaSERKS1_(%"struct.std::vector<int,std::allocator<int> >"* undef, %"struct.std::vector<int,std::allocator<int> >"* undef)
+ to label %.noexc380.i unwind label %lpad204.i
+
+.noexc380.i: ; preds = %invcont86.i
+ br i1 undef, label %bb100.i, label %bb.i.i.i198.i
+
+bb.i.i.i198.i: ; preds = %.noexc380.i
+ unreachable
+
+bb100.i: ; preds = %.noexc380.i
+ br i1 undef, label %invcont101.i, label %bb.i.i.i190.i
+
+bb.i.i.i190.i: ; preds = %bb100.i
+ unreachable
+
+invcont101.i: ; preds = %bb100.i
+ invoke fastcc void @_ZN9TableBaseILi2EdE6reinitERK12TableIndicesILi2EE(%"struct.TableBase<2,double>"* undef, i32 undef, i32 undef)
+ to label %_ZN10FullMatrixIdEC1Ejj.exit.i.i unwind label %lpad.i.i.i.i.i
+
+lpad.i.i.i.i.i: ; preds = %invcont101.i
+ unreachable
+
+_ZN10FullMatrixIdEC1Ejj.exit.i.i: ; preds = %invcont101.i
+ invoke fastcc void @_ZN9TableBaseILi2EdE6reinitERK12TableIndicesILi2EE(%"struct.TableBase<2,double>"* undef, i32 undef, i32 undef)
+ to label %_ZN10FullMatrixIdEC1Ejj.exit28.i.i unwind label %lpad.i.i.i27.i.i
+
+lpad.i.i.i27.i.i: ; preds = %_ZN10FullMatrixIdEC1Ejj.exit.i.i
+ invoke void @_Unwind_Resume(i8* undef)
+ to label %.noexc.i.i unwind label %lpad.i.i
+
+.noexc.i.i: ; preds = %lpad.i.i.i27.i.i
+ unreachable
+
+_ZN10FullMatrixIdEC1Ejj.exit28.i.i: ; preds = %_ZN10FullMatrixIdEC1Ejj.exit.i.i
+ br i1 undef, label %bb58.i.i, label %bb.i.i.i304.i.i
+
+bb.i.i.i304.i.i: ; preds = %_ZN10FullMatrixIdEC1Ejj.exit28.i.i
+ unreachable
+
+bb58.i.i: ; preds = %_ZN10FullMatrixIdEC1Ejj.exit28.i.i
+ br i1 false, label %bb.i191.i, label %bb.i.i.i297.i.i
+
+bb.i.i.i297.i.i: ; preds = %bb58.i.i
+ unreachable
+
+lpad.i.i: ; preds = %lpad.i.i.i27.i.i
+ unreachable
+
+bb.i191.i: ; preds = %.noexc232.i, %bb58.i.i
+ invoke fastcc void @_ZN9TableBaseILi2EdE6reinitERK12TableIndicesILi2EE(%"struct.TableBase<2,double>"* undef, i32 undef, i32 undef)
+ to label %.noexc232.i unwind label %lpad196.i
+
+.noexc232.i: ; preds = %bb.i191.i
+ br i1 undef, label %bb29.loopexit.i.i, label %bb.i191.i
+
+bb7.i215.i: ; preds = %bb9.i216.i
+ br i1 undef, label %bb16.preheader.i.i, label %bb8.i.i
+
+bb8.i.i: ; preds = %bb7.i215.i
+ %tmp60.i.i = add i32 %0, 1 ; <i32> [#uses=1]
+ br label %bb9.i216.i
+
+bb9.i216.i: ; preds = %bb29.loopexit.i.i, %bb8.i.i
+ %0 = phi i32 [ 0, %bb29.loopexit.i.i ], [ %tmp60.i.i, %bb8.i.i ] ; <i32> [#uses=2]
+ br i1 undef, label %bb7.i215.i, label %bb16.preheader.i.i
+
+bb15.i.i: ; preds = %bb16.preheader.i.i, %bb15.i.i
+ %j1.0212.i.i = phi i32 [ %1, %bb15.i.i ], [ 0, %bb16.preheader.i.i ] ; <i32> [#uses=2]
+ %tmp6.i.i195.i.i = load i32* undef, align 4 ; <i32> [#uses=1]
+ %tmp231.i.i = mul i32 %0, %tmp6.i.i195.i.i ; <i32> [#uses=1]
+ %tmp13.i197.i.i = add i32 %j1.0212.i.i, %tmp231.i.i ; <i32> [#uses=0]
+ %1 = add i32 %j1.0212.i.i, 1 ; <i32> [#uses=1]
+ br i1 undef, label %bb15.i.i, label %bb17.i.i
+
+bb17.i.i: ; preds = %bb16.preheader.i.i, %bb15.i.i
+ br label %bb16.preheader.i.i
+
+bb16.preheader.i.i: ; preds = %bb17.i.i, %bb9.i216.i, %bb7.i215.i
+ br i1 undef, label %bb17.i.i, label %bb15.i.i
+
+bb29.loopexit.i.i: ; preds = %.noexc232.i
+ br label %bb9.i216.i
+
+lpad.i: ; preds = %entry
+ unreachable
+
+lpad120.i: ; preds = %invcont.i
+ unreachable
+
+lpad124.i: ; preds = %invcont1.i
+ unreachable
+
+lpad128.i: ; preds = %invcont3.i
+ unreachable
+
+lpad132.i: ; preds = %invcont4.i
+ unreachable
+
+lpad136.i: ; preds = %invcont6.i
+ unreachable
+
+lpad140.i: ; preds = %bb21.i, %invcont7.i
+ unreachable
+
+lpad144.i: ; preds = %bb10.i168.i, %invcont9.i
+ unreachable
+
+lpad148.i: ; preds = %invcont10.i
+ unreachable
+
+lpad188.i: ; preds = %bb50.i.i.i
+ unreachable
+
+lpad196.i: ; preds = %bb.i191.i
+ unreachable
+
+lpad200.i: ; preds = %bb50.i.i
+ unreachable
+
+lpad204.i: ; preds = %invcont86.i
+ unreachable
+}
+
+declare fastcc void @_ZN11Polynomials19LagrangeEquidistant23generate_complete_basisEj(%"struct.std::vector<Polynomials::Polynomial<double>,std::allocator<Polynomials::Polynomial<double> > >"* noalias nocapture sret, i32)
diff --git a/test/CodeGen/X86/select-aggregate.ll b/test/CodeGen/X86/select-aggregate.ll
new file mode 100644
index 0000000..44cafe2
--- /dev/null
+++ b/test/CodeGen/X86/select-aggregate.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+; PR5757
+
+; CHECK: cmovneq %rdi, %rsi
+; CHECK: movl (%rsi), %eax
+
+%0 = type { i64, i32 }
+
+define i32 @foo(%0* %p, %0* %q, i1 %r) nounwind {
+ %t0 = load %0* %p
+ %t1 = load %0* %q
+ %t4 = select i1 %r, %0 %t0, %0 %t1
+ %t5 = extractvalue %0 %t4, 1
+ ret i32 %t5
+}
diff --git a/test/CodeGen/X86/select-zero-one.ll b/test/CodeGen/X86/select-zero-one.ll
new file mode 100644
index 0000000..c38a020
--- /dev/null
+++ b/test/CodeGen/X86/select-zero-one.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep cmov
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep xor
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movzbl | count 1
+
+@r1 = weak global i32 0
+
+define void @t1(i32 %a, double %b) {
+ %tmp114 = fcmp ugt double %b, 1.000000e-09
+ %tmp120 = icmp eq i32 %a, 0 ; <i1> [#uses=1]
+ %bothcond = or i1 %tmp114, %tmp120 ; <i1> [#uses=1]
+ %storemerge = select i1 %bothcond, i32 0, i32 1 ; <i32> [#uses=2]
+ store i32 %storemerge, i32* @r1, align 4
+ ret void
+}
+
+@r2 = weak global i8 0
+
+define void @t2(i32 %a, double %b) {
+ %tmp114 = fcmp ugt double %b, 1.000000e-09
+ %tmp120 = icmp eq i32 %a, 0 ; <i1> [#uses=1]
+ %bothcond = or i1 %tmp114, %tmp120 ; <i1> [#uses=1]
+ %storemerge = select i1 %bothcond, i8 0, i8 1 ; <i32> [#uses=2]
+ store i8 %storemerge, i8* @r2, align 4
+ ret void
+}
diff --git a/test/CodeGen/X86/select.ll b/test/CodeGen/X86/select.ll
new file mode 100644
index 0000000..95ed9e9
--- /dev/null
+++ b/test/CodeGen/X86/select.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s -march=x86 -mcpu=pentium
+; RUN: llc < %s -march=x86 -mcpu=yonah
+; RUN: llc < %s -march=x86 -mcpu=yonah | not grep set
+
+define i1 @boolSel(i1 %A, i1 %B, i1 %C) nounwind {
+ %X = select i1 %A, i1 %B, i1 %C ; <i1> [#uses=1]
+ ret i1 %X
+}
+
+define i8 @byteSel(i1 %A, i8 %B, i8 %C) nounwind {
+ %X = select i1 %A, i8 %B, i8 %C ; <i8> [#uses=1]
+ ret i8 %X
+}
+
+define i16 @shortSel(i1 %A, i16 %B, i16 %C) nounwind {
+ %X = select i1 %A, i16 %B, i16 %C ; <i16> [#uses=1]
+ ret i16 %X
+}
+
+define i32 @intSel(i1 %A, i32 %B, i32 %C) nounwind {
+ %X = select i1 %A, i32 %B, i32 %C ; <i32> [#uses=1]
+ ret i32 %X
+}
+
+define i64 @longSel(i1 %A, i64 %B, i64 %C) nounwind {
+ %X = select i1 %A, i64 %B, i64 %C ; <i64> [#uses=1]
+ ret i64 %X
+}
+
+define double @doubleSel(i1 %A, double %B, double %C) nounwind {
+ %X = select i1 %A, double %B, double %C ; <double> [#uses=1]
+ ret double %X
+}
+
+define i8 @foldSel(i1 %A, i8 %B, i8 %C) nounwind {
+ %Cond = icmp slt i8 %B, %C ; <i1> [#uses=1]
+ %X = select i1 %Cond, i8 %B, i8 %C ; <i8> [#uses=1]
+ ret i8 %X
+}
+
+define i32 @foldSel2(i1 %A, i32 %B, i32 %C) nounwind {
+ %Cond = icmp eq i32 %B, %C ; <i1> [#uses=1]
+ %X = select i1 %Cond, i32 %B, i32 %C ; <i32> [#uses=1]
+ ret i32 %X
+}
+
+define i32 @foldSel2a(i1 %A, i32 %B, i32 %C, double %X, double %Y) nounwind {
+ %Cond = fcmp olt double %X, %Y ; <i1> [#uses=1]
+ %X.upgrd.1 = select i1 %Cond, i32 %B, i32 %C ; <i32> [#uses=1]
+ ret i32 %X.upgrd.1
+}
+
+define float @foldSel3(i1 %A, float %B, float %C, i32 %X, i32 %Y) nounwind {
+ %Cond = icmp ult i32 %X, %Y ; <i1> [#uses=1]
+ %X.upgrd.2 = select i1 %Cond, float %B, float %C ; <float> [#uses=1]
+ ret float %X.upgrd.2
+}
+
+define float @nofoldSel4(i1 %A, float %B, float %C, i32 %X, i32 %Y) nounwind {
+ %Cond = icmp slt i32 %X, %Y ; <i1> [#uses=1]
+ %X.upgrd.3 = select i1 %Cond, float %B, float %C ; <float> [#uses=1]
+ ret float %X.upgrd.3
+}
diff --git a/test/CodeGen/X86/setcc.ll b/test/CodeGen/X86/setcc.ll
new file mode 100644
index 0000000..c37e15d
--- /dev/null
+++ b/test/CodeGen/X86/setcc.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; rdar://7329206
+
+; Use sbb x, x to materialize carry bit in a GPR. The value is either
+; all 1's or all 0's.
+
+define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
+entry:
+; CHECK: t1:
+; CHECK: seta %al
+; CHECK: movzbl %al, %eax
+; CHECK: shll $5, %eax
+ %0 = icmp ugt i16 %x, 26 ; <i1> [#uses=1]
+ %iftmp.1.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]
+ ret i16 %iftmp.1.0
+}
+
+define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
+entry:
+; CHECK: t2:
+; CHECK: sbbl %eax, %eax
+; CHECK: andl $32, %eax
+ %0 = icmp ult i16 %x, 26 ; <i1> [#uses=1]
+ %iftmp.0.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]
+ ret i16 %iftmp.0.0
+}
+
+define i64 @t3(i64 %x) nounwind readnone ssp {
+entry:
+; CHECK: t3:
+; CHECK: sbbq %rax, %rax
+; CHECK: andq $64, %rax
+ %0 = icmp ult i64 %x, 18 ; <i1> [#uses=1]
+ %iftmp.2.0 = select i1 %0, i64 64, i64 0 ; <i64> [#uses=1]
+ ret i64 %iftmp.2.0
+}
diff --git a/test/CodeGen/X86/setoeq.ll b/test/CodeGen/X86/setoeq.ll
new file mode 100644
index 0000000..4a9c1ba
--- /dev/null
+++ b/test/CodeGen/X86/setoeq.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 | grep set | count 2
+; RUN: llc < %s -march=x86 | grep and
+
+define zeroext i8 @t(double %x) nounwind readnone {
+entry:
+ %0 = fptosi double %x to i32 ; <i32> [#uses=1]
+ %1 = sitofp i32 %0 to double ; <double> [#uses=1]
+ %2 = fcmp oeq double %1, %x ; <i1> [#uses=1]
+ %retval12 = zext i1 %2 to i8 ; <i8> [#uses=1]
+ ret i8 %retval12
+}
diff --git a/test/CodeGen/X86/setuge.ll b/test/CodeGen/X86/setuge.ll
new file mode 100644
index 0000000..4ca2f18
--- /dev/null
+++ b/test/CodeGen/X86/setuge.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 | not grep set
+
+declare i1 @llvm.isunordered.f32(float, float)
+
+define float @cmp(float %A, float %B, float %C, float %D) nounwind {
+entry:
+ %tmp.1 = fcmp uno float %A, %B ; <i1> [#uses=1]
+ %tmp.2 = fcmp oge float %A, %B ; <i1> [#uses=1]
+ %tmp.3 = or i1 %tmp.1, %tmp.2 ; <i1> [#uses=1]
+ %tmp.4 = select i1 %tmp.3, float %C, float %D ; <float> [#uses=1]
+ ret float %tmp.4
+}
+
diff --git a/test/CodeGen/X86/sext-i1.ll b/test/CodeGen/X86/sext-i1.ll
new file mode 100644
index 0000000..21c418d
--- /dev/null
+++ b/test/CodeGen/X86/sext-i1.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=32
+; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=64
+; rdar://7573216
+; PR6146
+
+define i32 @t1(i32 %x) nounwind readnone ssp {
+entry:
+; 32: t1:
+; 32: cmpl $1
+; 32: sbbl
+
+; 64: t1:
+; 64: cmpl $1
+; 64: sbbl
+ %0 = icmp eq i32 %x, 0
+ %iftmp.0.0 = select i1 %0, i32 -1, i32 0
+ ret i32 %iftmp.0.0
+}
+
+define i32 @t2(i32 %x) nounwind readnone ssp {
+entry:
+; 32: t2:
+; 32: cmpl $1
+; 32: sbbl
+
+; 64: t2:
+; 64: cmpl $1
+; 64: sbbl
+ %0 = icmp eq i32 %x, 0
+ %iftmp.0.0 = sext i1 %0 to i32
+ ret i32 %iftmp.0.0
+}
+
+%struct.zbookmark = type { i64, i64 }
+%struct.zstream = type { }
+
+define i32 @t3() nounwind readonly {
+entry:
+; 32: t3:
+; 32: cmpl $1
+; 32: sbbl
+; 32: cmpl
+; 32: xorl
+
+; 64: t3:
+; 64: cmpl $1
+; 64: sbbq
+; 64: cmpq
+; 64: xorl
+ %not.tobool = icmp eq i32 undef, 0 ; <i1> [#uses=2]
+ %cond = sext i1 %not.tobool to i32 ; <i32> [#uses=1]
+ %conv = sext i1 %not.tobool to i64 ; <i64> [#uses=1]
+ %add13 = add i64 0, %conv ; <i64> [#uses=1]
+ %cmp = icmp ult i64 undef, %add13 ; <i1> [#uses=1]
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ %xor27 = xor i32 undef, %cond ; <i32> [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/sext-load.ll b/test/CodeGen/X86/sext-load.ll
new file mode 100644
index 0000000..c9b39d3
--- /dev/null
+++ b/test/CodeGen/X86/sext-load.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 | grep movsbl
+
+define i32 @foo(i32 %X) nounwind {
+entry:
+ %tmp12 = trunc i32 %X to i8 ; <i8> [#uses=1]
+ %tmp123 = sext i8 %tmp12 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp123
+}
+
diff --git a/test/CodeGen/X86/sext-ret-val.ll b/test/CodeGen/X86/sext-ret-val.ll
new file mode 100644
index 0000000..da1a1871
--- /dev/null
+++ b/test/CodeGen/X86/sext-ret-val.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86 | grep movzbl | count 1
+; rdar://6699246
+
+define signext i8 @t1(i8* %A) nounwind readnone ssp {
+entry:
+ %0 = icmp ne i8* %A, null
+ %1 = zext i1 %0 to i8
+ ret i8 %1
+}
+
+define i8 @t2(i8* %A) nounwind readnone ssp {
+entry:
+ %0 = icmp ne i8* %A, null
+ %1 = zext i1 %0 to i8
+ ret i8 %1
+}
diff --git a/test/CodeGen/X86/sext-select.ll b/test/CodeGen/X86/sext-select.ll
new file mode 100644
index 0000000..4aca040
--- /dev/null
+++ b/test/CodeGen/X86/sext-select.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86 | grep movsw
+; PR2139
+
+declare void @abort()
+
+define i32 @main() {
+entry:
+ %tmp73 = tail call i1 @return_false() ; <i8> [#uses=1]
+ %g.0 = select i1 %tmp73, i16 0, i16 -480 ; <i16> [#uses=2]
+ %tmp7778 = sext i16 %g.0 to i32 ; <i32> [#uses=1]
+ %tmp80 = shl i32 %tmp7778, 3 ; <i32> [#uses=2]
+ %tmp87 = icmp sgt i32 %tmp80, 32767 ; <i1> [#uses=1]
+ br i1 %tmp87, label %bb90, label %bb91
+bb90: ; preds = %bb84, %bb72
+ tail call void @abort()
+ unreachable
+bb91: ; preds = %bb84
+ ret i32 0
+}
+
+define i1 @return_false() {
+ ret i1 0
+}
diff --git a/test/CodeGen/X86/sext-subreg.ll b/test/CodeGen/X86/sext-subreg.ll
new file mode 100644
index 0000000..b2b9f81
--- /dev/null
+++ b/test/CodeGen/X86/sext-subreg.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+; rdar://7529457
+
+define i64 @t(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
+; CHECK: t:
+; CHECK: movslq %e{{.*}}, %rax
+; CHECK: movq %rax
+; CHECK: movl %eax
+ %C = add i64 %A, %B
+ %D = trunc i64 %C to i32
+ volatile store i32 %D, i32* %P
+ %E = shl i64 %C, 32
+ %F = ashr i64 %E, 32
+ volatile store i64 %F, i64 *%P2
+ volatile store i32 %D, i32* %P
+ ret i64 undef
+}
diff --git a/test/CodeGen/X86/sext-trunc.ll b/test/CodeGen/X86/sext-trunc.ll
new file mode 100644
index 0000000..2eaf425
--- /dev/null
+++ b/test/CodeGen/X86/sext-trunc.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 > %t
+; RUN: grep movsbl %t
+; RUN: not grep movz %t
+; RUN: not grep and %t
+
+define i8 @foo(i16 signext %x) signext nounwind {
+ %retval56 = trunc i16 %x to i8
+ ret i8 %retval56
+}
diff --git a/test/CodeGen/X86/sfence.ll b/test/CodeGen/X86/sfence.ll
new file mode 100644
index 0000000..4782879
--- /dev/null
+++ b/test/CodeGen/X86/sfence.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep sfence
+
+declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1)
+
+define void @test() {
+ call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 true)
+ ret void
+}
diff --git a/test/CodeGen/X86/shift-and.ll b/test/CodeGen/X86/shift-and.ll
new file mode 100644
index 0000000..fd278c2
--- /dev/null
+++ b/test/CodeGen/X86/shift-and.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 | grep and | count 1
+; RUN: llc < %s -march=x86-64 | not grep and
+
+define i32 @t1(i32 %t, i32 %val) nounwind {
+ %shamt = and i32 %t, 31
+ %res = shl i32 %val, %shamt
+ ret i32 %res
+}
+
+@X = internal global i16 0
+
+define void @t2(i16 %t) nounwind {
+ %shamt = and i16 %t, 31
+ %tmp = load i16* @X
+ %tmp1 = ashr i16 %tmp, %shamt
+ store i16 %tmp1, i16* @X
+ ret void
+}
+
+define i64 @t3(i64 %t, i64 %val) nounwind {
+ %shamt = and i64 %t, 63
+ %res = lshr i64 %val, %shamt
+ ret i64 %res
+}
diff --git a/test/CodeGen/X86/shift-coalesce.ll b/test/CodeGen/X86/shift-coalesce.ll
new file mode 100644
index 0000000..d38f9a8
--- /dev/null
+++ b/test/CodeGen/X86/shift-coalesce.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
+; RUN: grep {shld.*CL}
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
+; RUN: not grep {mov CL, BL}
+
+; PR687
+
+define i64 @foo(i64 %x, i64* %X) {
+ %tmp.1 = load i64* %X ; <i64> [#uses=1]
+ %tmp.3 = trunc i64 %tmp.1 to i8 ; <i8> [#uses=1]
+ %shift.upgrd.1 = zext i8 %tmp.3 to i64 ; <i64> [#uses=1]
+ %tmp.4 = shl i64 %x, %shift.upgrd.1 ; <i64> [#uses=1]
+ ret i64 %tmp.4
+}
+
diff --git a/test/CodeGen/X86/shift-codegen.ll b/test/CodeGen/X86/shift-codegen.ll
new file mode 100644
index 0000000..4cba183
--- /dev/null
+++ b/test/CodeGen/X86/shift-codegen.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -relocation-model=static -march=x86 | \
+; RUN: grep {shll \$3} | count 2
+
+; This should produce two shll instructions, not any lea's.
+
+target triple = "i686-apple-darwin8"
+@Y = weak global i32 0 ; <i32*> [#uses=1]
+@X = weak global i32 0 ; <i32*> [#uses=2]
+
+
+define void @fn1() {
+entry:
+ %tmp = load i32* @Y ; <i32> [#uses=1]
+ %tmp1 = shl i32 %tmp, 3 ; <i32> [#uses=1]
+ %tmp2 = load i32* @X ; <i32> [#uses=1]
+ %tmp3 = or i32 %tmp1, %tmp2 ; <i32> [#uses=1]
+ store i32 %tmp3, i32* @X
+ ret void
+}
+
+define i32 @fn2(i32 %X, i32 %Y) {
+entry:
+ %tmp2 = shl i32 %Y, 3 ; <i32> [#uses=1]
+ %tmp4 = or i32 %tmp2, %X ; <i32> [#uses=1]
+ ret i32 %tmp4
+}
+
diff --git a/test/CodeGen/X86/shift-combine.ll b/test/CodeGen/X86/shift-combine.ll
new file mode 100644
index 0000000..e443ac1
--- /dev/null
+++ b/test/CodeGen/X86/shift-combine.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s | not grep shrl
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin8"
+@array = weak global [4 x i32] zeroinitializer ; <[4 x i32]*> [#uses=1]
+
+define i32 @foo(i32 %x) {
+entry:
+ %tmp2 = lshr i32 %x, 2 ; <i32> [#uses=1]
+ %tmp3 = and i32 %tmp2, 3 ; <i32> [#uses=1]
+ %tmp4 = getelementptr [4 x i32]* @array, i32 0, i32 %tmp3 ; <i32*> [#uses=1]
+ %tmp5 = load i32* %tmp4, align 4 ; <i32> [#uses=1]
+ ret i32 %tmp5
+}
+
diff --git a/test/CodeGen/X86/shift-double.ll b/test/CodeGen/X86/shift-double.ll
new file mode 100644
index 0000000..5adee7c
--- /dev/null
+++ b/test/CodeGen/X86/shift-double.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
+; RUN: grep {sh\[lr\]d} | count 5
+
+define i64 @test1(i64 %X, i8 %C) {
+ %shift.upgrd.1 = zext i8 %C to i64 ; <i64> [#uses=1]
+ %Y = shl i64 %X, %shift.upgrd.1 ; <i64> [#uses=1]
+ ret i64 %Y
+}
+
+define i64 @test2(i64 %X, i8 %C) {
+ %shift.upgrd.2 = zext i8 %C to i64 ; <i64> [#uses=1]
+ %Y = ashr i64 %X, %shift.upgrd.2 ; <i64> [#uses=1]
+ ret i64 %Y
+}
+
+define i64 @test3(i64 %X, i8 %C) {
+ %shift.upgrd.3 = zext i8 %C to i64 ; <i64> [#uses=1]
+ %Y = lshr i64 %X, %shift.upgrd.3 ; <i64> [#uses=1]
+ ret i64 %Y
+}
+
+define i32 @test4(i32 %A, i32 %B, i8 %C) {
+ %shift.upgrd.4 = zext i8 %C to i32 ; <i32> [#uses=1]
+ %X = shl i32 %A, %shift.upgrd.4 ; <i32> [#uses=1]
+ %Cv = sub i8 32, %C ; <i8> [#uses=1]
+ %shift.upgrd.5 = zext i8 %Cv to i32 ; <i32> [#uses=1]
+ %Y = lshr i32 %B, %shift.upgrd.5 ; <i32> [#uses=1]
+ %Z = or i32 %Y, %X ; <i32> [#uses=1]
+ ret i32 %Z
+}
+
+define i16 @test5(i16 %A, i16 %B, i8 %C) {
+ %shift.upgrd.6 = zext i8 %C to i16 ; <i16> [#uses=1]
+ %X = shl i16 %A, %shift.upgrd.6 ; <i16> [#uses=1]
+ %Cv = sub i8 16, %C ; <i8> [#uses=1]
+ %shift.upgrd.7 = zext i8 %Cv to i16 ; <i16> [#uses=1]
+ %Y = lshr i16 %B, %shift.upgrd.7 ; <i16> [#uses=1]
+ %Z = or i16 %Y, %X ; <i16> [#uses=1]
+ ret i16 %Z
+}
+
diff --git a/test/CodeGen/X86/shift-folding.ll b/test/CodeGen/X86/shift-folding.ll
new file mode 100644
index 0000000..872817f
--- /dev/null
+++ b/test/CodeGen/X86/shift-folding.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86 | \
+; RUN: grep {s\[ah\]\[rl\]l} | count 1
+
+define i32* @test1(i32* %P, i32 %X) {
+ %Y = lshr i32 %X, 2 ; <i32> [#uses=1]
+ %gep.upgrd.1 = zext i32 %Y to i64 ; <i64> [#uses=1]
+ %P2 = getelementptr i32* %P, i64 %gep.upgrd.1 ; <i32*> [#uses=1]
+ ret i32* %P2
+}
+
+define i32* @test2(i32* %P, i32 %X) {
+ %Y = shl i32 %X, 2 ; <i32> [#uses=1]
+ %gep.upgrd.2 = zext i32 %Y to i64 ; <i64> [#uses=1]
+ %P2 = getelementptr i32* %P, i64 %gep.upgrd.2 ; <i32*> [#uses=1]
+ ret i32* %P2
+}
+
+define i32* @test3(i32* %P, i32 %X) {
+ %Y = ashr i32 %X, 2 ; <i32> [#uses=1]
+ %P2 = getelementptr i32* %P, i32 %Y ; <i32*> [#uses=1]
+ ret i32* %P2
+}
+
diff --git a/test/CodeGen/X86/shift-i128.ll b/test/CodeGen/X86/shift-i128.ll
new file mode 100644
index 0000000..c4d15ae
--- /dev/null
+++ b/test/CodeGen/X86/shift-i128.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86-64
+
+define void @t(i128 %x, i128 %a, i128* nocapture %r) nounwind {
+entry:
+ %0 = lshr i128 %x, %a
+ store i128 %0, i128* %r, align 16
+ ret void
+}
diff --git a/test/CodeGen/X86/shift-i256.ll b/test/CodeGen/X86/shift-i256.ll
new file mode 100644
index 0000000..d5f65a6
--- /dev/null
+++ b/test/CodeGen/X86/shift-i256.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86-64
+
+define void @t(i256 %x, i256 %a, i256* nocapture %r) nounwind readnone {
+entry:
+ %0 = ashr i256 %x, %a
+ store i256 %0, i256* %r
+ ret void
+}
diff --git a/test/CodeGen/X86/shift-one.ll b/test/CodeGen/X86/shift-one.ll
new file mode 100644
index 0000000..0f80f90
--- /dev/null
+++ b/test/CodeGen/X86/shift-one.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 | not grep leal
+
+@x = external global i32 ; <i32*> [#uses=1]
+
+define i32 @test() {
+ %tmp.0 = load i32* @x ; <i32> [#uses=1]
+ %tmp.1 = shl i32 %tmp.0, 1 ; <i32> [#uses=1]
+ ret i32 %tmp.1
+}
+
diff --git a/test/CodeGen/X86/shift-parts.ll b/test/CodeGen/X86/shift-parts.ll
new file mode 100644
index 0000000..ce4f538
--- /dev/null
+++ b/test/CodeGen/X86/shift-parts.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=x86-64 | grep shrdq
+; PR4736
+
+%0 = type { i32, i8, [35 x i8] }
+
+@g_144 = external global %0, align 8 ; <%0*> [#uses=1]
+
+define i32 @int87(i32 %uint64p_8) nounwind {
+entry:
+ %srcval4 = load i320* bitcast (%0* @g_144 to i320*), align 8 ; <i320> [#uses=1]
+ br label %for.cond
+
+for.cond: ; preds = %for.cond, %entry
+ %call3.in.in.in.v = select i1 undef, i320 192, i320 128 ; <i320> [#uses=1]
+ %call3.in.in.in = lshr i320 %srcval4, %call3.in.in.in.v ; <i320> [#uses=1]
+ %call3.in = trunc i320 %call3.in.in.in to i32 ; <i32> [#uses=1]
+ %tobool = icmp eq i32 %call3.in, 0 ; <i1> [#uses=1]
+ br i1 %tobool, label %for.cond, label %if.then
+
+if.then: ; preds = %for.cond
+ ret i32 1
+}
diff --git a/test/CodeGen/X86/shl_elim.ll b/test/CodeGen/X86/shl_elim.ll
new file mode 100644
index 0000000..4458891
--- /dev/null
+++ b/test/CodeGen/X86/shl_elim.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 | grep {movl 8(.esp), %eax}
+; RUN: llc < %s -march=x86 | grep {shrl .eax}
+; RUN: llc < %s -march=x86 | grep {movswl .ax, .eax}
+
+define i32 @test1(i64 %a) {
+ %tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1]
+ %tmp23 = trunc i64 %tmp29 to i32 ; <i32> [#uses=1]
+ %tmp410 = lshr i32 %tmp23, 9 ; <i32> [#uses=1]
+ %tmp45 = trunc i32 %tmp410 to i16 ; <i16> [#uses=1]
+ %tmp456 = sext i16 %tmp45 to i32 ; <i32> [#uses=1]
+ ret i32 %tmp456
+}
+
diff --git a/test/CodeGen/X86/shrink-fp-const1.ll b/test/CodeGen/X86/shrink-fp-const1.ll
new file mode 100644
index 0000000..49b9fa3
--- /dev/null
+++ b/test/CodeGen/X86/shrink-fp-const1.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | not grep cvtss2sd
+; PR1264
+
+define double @foo(double %x) {
+ %y = fmul double %x, 5.000000e-01
+ ret double %y
+}
diff --git a/test/CodeGen/X86/shrink-fp-const2.ll b/test/CodeGen/X86/shrink-fp-const2.ll
new file mode 100644
index 0000000..3d5203b
--- /dev/null
+++ b/test/CodeGen/X86/shrink-fp-const2.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86 | grep flds
+; This should be a flds, not fldt.
+define x86_fp80 @test2() nounwind {
+entry:
+ ret x86_fp80 0xK3FFFC000000000000000
+}
+
diff --git a/test/CodeGen/X86/sincos.ll b/test/CodeGen/X86/sincos.ll
new file mode 100644
index 0000000..13f9329
--- /dev/null
+++ b/test/CodeGen/X86/sincos.ll
@@ -0,0 +1,48 @@
+; Make sure this testcase codegens to the sin and cos instructions, not calls
+; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
+; RUN: grep sin\$ | count 3
+; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
+; RUN: grep cos\$ | count 3
+
+declare float @sinf(float) readonly
+
+declare double @sin(double) readonly
+
+declare x86_fp80 @sinl(x86_fp80) readonly
+
+define float @test1(float %X) {
+ %Y = call float @sinf(float %X) readonly
+ ret float %Y
+}
+
+define double @test2(double %X) {
+ %Y = call double @sin(double %X) readonly
+ ret double %Y
+}
+
+define x86_fp80 @test3(x86_fp80 %X) {
+ %Y = call x86_fp80 @sinl(x86_fp80 %X) readonly
+ ret x86_fp80 %Y
+}
+
+declare float @cosf(float) readonly
+
+declare double @cos(double) readonly
+
+declare x86_fp80 @cosl(x86_fp80) readonly
+
+define float @test4(float %X) {
+ %Y = call float @cosf(float %X) readonly
+ ret float %Y
+}
+
+define double @test5(double %X) {
+ %Y = call double @cos(double %X) readonly
+ ret double %Y
+}
+
+define x86_fp80 @test6(x86_fp80 %X) {
+ %Y = call x86_fp80 @cosl(x86_fp80 %X) readonly
+ ret x86_fp80 %Y
+}
+
diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll
new file mode 100644
index 0000000..01d7373
--- /dev/null
+++ b/test/CodeGen/X86/sink-hoist.ll
@@ -0,0 +1,148 @@
+; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -post-RA-scheduler=true | FileCheck %s
+
+; Currently, floating-point selects are lowered to CFG triangles.
+; This means that one side of the select is always unconditionally
+; evaluated, however with MachineSink we can sink the other side so
+; that it's conditionally evaluated.
+
+; CHECK: foo:
+; CHECK: divsd
+; CHECK-NEXT: testb $1, %dil
+; CHECK-NEXT: jne
+; CHECK-NEXT: divsd
+
+define double @foo(double %x, double %y, i1 %c) nounwind {
+ %a = fdiv double %x, 3.2
+ %b = fdiv double %y, 3.3
+ %z = select i1 %c, double %a, double %b
+ ret double %z
+}
+
+; Hoist floating-point constant-pool loads out of loops.
+
+; CHECK: bar:
+; CHECK: movsd
+; CHECK: align
+define void @bar(double* nocapture %p, i64 %n) nounwind {
+entry:
+ %0 = icmp sgt i64 %n, 0
+ br i1 %0, label %bb, label %return
+
+bb:
+ %i.03 = phi i64 [ 0, %entry ], [ %3, %bb ]
+ %scevgep = getelementptr double* %p, i64 %i.03
+ %1 = load double* %scevgep, align 8
+ %2 = fdiv double 3.200000e+00, %1
+ store double %2, double* %scevgep, align 8
+ %3 = add nsw i64 %i.03, 1
+ %exitcond = icmp eq i64 %3, %n
+ br i1 %exitcond, label %return, label %bb
+
+return:
+ ret void
+}
+
+; Sink instructions with dead EFLAGS defs.
+
+; CHECK: zzz:
+; CHECK: je
+; CHECK-NEXT: orb
+
+define zeroext i8 @zzz(i8 zeroext %a, i8 zeroext %b) nounwind readnone {
+entry:
+ %tmp = zext i8 %a to i32 ; <i32> [#uses=1]
+ %tmp2 = icmp eq i8 %a, 0 ; <i1> [#uses=1]
+ %tmp3 = or i8 %b, -128 ; <i8> [#uses=1]
+ %tmp4 = and i8 %b, 127 ; <i8> [#uses=1]
+ %b_addr.0 = select i1 %tmp2, i8 %tmp4, i8 %tmp3 ; <i8> [#uses=1]
+ ret i8 %b_addr.0
+}
+
+; Codegen should hoist and CSE these constants.
+
+; CHECK: vv:
+; CHECK: LCPI4_0(%rip), %xmm0
+; CHECK: LCPI4_1(%rip), %xmm1
+; CHECK: LCPI4_2(%rip), %xmm2
+; CHECK: align
+; CHECK-NOT: LCPI
+; CHECK: ret
+
+@_minusZero.6007 = internal constant <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00> ; <<4 x float>*> [#uses=0]
[email protected] = internal constant <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06> ; <<4 x float>*> [#uses=0]
+
+define void @vv(float* %y, float* %x, i32* %n) nounwind ssp {
+entry:
+ br label %bb60
+
+bb: ; preds = %bb60
+ %0 = bitcast float* %x_addr.0 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %1 = load <4 x float>* %0, align 16 ; <<4 x float>> [#uses=4]
+ %tmp20 = bitcast <4 x float> %1 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp22 = and <4 x i32> %tmp20, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ; <<4 x i32>> [#uses=1]
+ %tmp23 = bitcast <4 x i32> %tmp22 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp25 = bitcast <4 x float> %1 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp27 = and <4 x i32> %tmp25, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=2]
+ %tmp30 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %tmp23, <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>, i8 5) ; <<4 x float>> [#uses=1]
+ %tmp34 = bitcast <4 x float> %tmp30 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp36 = xor <4 x i32> %tmp34, <i32 -1, i32 -1, i32 -1, i32 -1> ; <<4 x i32>> [#uses=1]
+ %tmp37 = and <4 x i32> %tmp36, <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200> ; <<4 x i32>> [#uses=1]
+ %tmp42 = or <4 x i32> %tmp37, %tmp27 ; <<4 x i32>> [#uses=1]
+ %tmp43 = bitcast <4 x i32> %tmp42 to <4 x float> ; <<4 x float>> [#uses=2]
+ %tmp45 = fadd <4 x float> %1, %tmp43 ; <<4 x float>> [#uses=1]
+ %tmp47 = fsub <4 x float> %tmp45, %tmp43 ; <<4 x float>> [#uses=2]
+ %tmp49 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %1, <4 x float> %tmp47, i8 1) ; <<4 x float>> [#uses=1]
+ %2 = bitcast <4 x float> %tmp49 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %3 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %2) nounwind readnone ; <<4 x float>> [#uses=1]
+ %tmp53 = fadd <4 x float> %tmp47, %3 ; <<4 x float>> [#uses=1]
+ %tmp55 = bitcast <4 x float> %tmp53 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp57 = or <4 x i32> %tmp55, %tmp27 ; <<4 x i32>> [#uses=1]
+ %tmp58 = bitcast <4 x i32> %tmp57 to <4 x float> ; <<4 x float>> [#uses=1]
+ %4 = bitcast float* %y_addr.0 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ store <4 x float> %tmp58, <4 x float>* %4, align 16
+ %5 = getelementptr float* %x_addr.0, i64 4 ; <float*> [#uses=1]
+ %6 = getelementptr float* %y_addr.0, i64 4 ; <float*> [#uses=1]
+ %7 = add i32 %i.0, 4 ; <i32> [#uses=1]
+ br label %bb60
+
+bb60: ; preds = %bb, %entry
+ %i.0 = phi i32 [ 0, %entry ], [ %7, %bb ] ; <i32> [#uses=2]
+ %x_addr.0 = phi float* [ %x, %entry ], [ %5, %bb ] ; <float*> [#uses=2]
+ %y_addr.0 = phi float* [ %y, %entry ], [ %6, %bb ] ; <float*> [#uses=2]
+ %8 = load i32* %n, align 4 ; <i32> [#uses=1]
+ %9 = icmp sgt i32 %8, %i.0 ; <i1> [#uses=1]
+ br i1 %9, label %bb, label %return
+
+return: ; preds = %bb60
+ ret void
+}
+
+declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone
+
+declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
+
+; CodeGen should use the correct register class when extracting
+; a load from a zero-extending load for hoisting.
+
+; CHECK: default_get_pch_validity:
+; CHECK: movl cl_options_count(%rip), %ecx
+
+@cl_options_count = external constant i32 ; <i32*> [#uses=2]
+
+define void @default_get_pch_validity() nounwind {
+entry:
+ %tmp4 = load i32* @cl_options_count, align 4 ; <i32> [#uses=1]
+ %tmp5 = icmp eq i32 %tmp4, 0 ; <i1> [#uses=1]
+ br i1 %tmp5, label %bb6, label %bb2
+
+bb2: ; preds = %bb2, %entry
+ %i.019 = phi i64 [ 0, %entry ], [ %tmp25, %bb2 ] ; <i64> [#uses=1]
+ %tmp25 = add i64 %i.019, 1 ; <i64> [#uses=2]
+ %tmp11 = load i32* @cl_options_count, align 4 ; <i32> [#uses=1]
+ %tmp12 = zext i32 %tmp11 to i64 ; <i64> [#uses=1]
+ %tmp13 = icmp ugt i64 %tmp12, %tmp25 ; <i1> [#uses=1]
+ br i1 %tmp13, label %bb2, label %bb6
+
+bb6: ; preds = %bb2, %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/small-byval-memcpy.ll b/test/CodeGen/X86/small-byval-memcpy.ll
new file mode 100644
index 0000000..9ec9182e
--- /dev/null
+++ b/test/CodeGen/X86/small-byval-memcpy.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s | not grep movs
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+
+define void @ccosl({ x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 }* byval align 4 %z) nounwind {
+entry:
+ %iz = alloca { x86_fp80, x86_fp80 } ; <{ x86_fp80, x86_fp80 }*> [#uses=3]
+ %tmp1 = getelementptr { x86_fp80, x86_fp80 }* %z, i32 0, i32 1 ; <x86_fp80*> [#uses=1]
+ %tmp2 = load x86_fp80* %tmp1, align 16 ; <x86_fp80> [#uses=1]
+ %tmp3 = fsub x86_fp80 0xK80000000000000000000, %tmp2 ; <x86_fp80> [#uses=1]
+ %tmp4 = getelementptr { x86_fp80, x86_fp80 }* %iz, i32 0, i32 1 ; <x86_fp80*> [#uses=1]
+ %real = getelementptr { x86_fp80, x86_fp80 }* %iz, i32 0, i32 0 ; <x86_fp80*> [#uses=1]
+ %tmp6 = getelementptr { x86_fp80, x86_fp80 }* %z, i32 0, i32 0 ; <x86_fp80*> [#uses=1]
+ %tmp7 = load x86_fp80* %tmp6, align 16 ; <x86_fp80> [#uses=1]
+ store x86_fp80 %tmp3, x86_fp80* %real, align 16
+ store x86_fp80 %tmp7, x86_fp80* %tmp4, align 16
+ call void @ccoshl( { x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 }* byval align 4 %iz ) nounwind
+ ret void
+}
+
+declare void @ccoshl({ x86_fp80, x86_fp80 }* noalias sret , { x86_fp80, x86_fp80 }* byval align 4 ) nounwind
diff --git a/test/CodeGen/X86/smul-with-overflow-2.ll b/test/CodeGen/X86/smul-with-overflow-2.ll
new file mode 100644
index 0000000..7c23adb
--- /dev/null
+++ b/test/CodeGen/X86/smul-with-overflow-2.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86 | grep mul | count 1
+; RUN: llc < %s -march=x86 | grep add | count 3
+
+define i32 @t1(i32 %a, i32 %b) nounwind readnone {
+entry:
+ %tmp0 = add i32 %b, %a
+ %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 2)
+ %tmp2 = extractvalue { i32, i1 } %tmp1, 0
+ ret i32 %tmp2
+}
+
+define i32 @t2(i32 %a, i32 %b) nounwind readnone {
+entry:
+ %tmp0 = add i32 %b, %a
+ %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 4)
+ %tmp2 = extractvalue { i32, i1 } %tmp1, 0
+ ret i32 %tmp2
+}
+
+declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32) nounwind
diff --git a/test/CodeGen/X86/smul-with-overflow-3.ll b/test/CodeGen/X86/smul-with-overflow-3.ll
new file mode 100644
index 0000000..49c31f5
--- /dev/null
+++ b/test/CodeGen/X86/smul-with-overflow-3.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86 | grep {jno} | count 1
+
+@ok = internal constant [4 x i8] c"%d\0A\00"
+@no = internal constant [4 x i8] c"no\0A\00"
+
+define i1 @func1(i32 %v1, i32 %v2) nounwind {
+entry:
+ %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
+ %sum = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %overflow, label %normal
+
+overflow:
+ %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+ ret i1 false
+
+normal:
+ %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+ ret i1 true
+}
+
+declare i32 @printf(i8*, ...) nounwind
+declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32)
diff --git a/test/CodeGen/X86/smul-with-overflow.ll b/test/CodeGen/X86/smul-with-overflow.ll
new file mode 100644
index 0000000..6d125e4
--- /dev/null
+++ b/test/CodeGen/X86/smul-with-overflow.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86 | grep {jo} | count 1
+
+@ok = internal constant [4 x i8] c"%d\0A\00"
+@no = internal constant [4 x i8] c"no\0A\00"
+
+define i1 @func1(i32 %v1, i32 %v2) nounwind {
+entry:
+ %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
+ %sum = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %overflow, label %normal
+
+normal:
+ %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+ ret i1 true
+
+overflow:
+ %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+ ret i1 false
+}
+
+declare i32 @printf(i8*, ...) nounwind
+declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32)
diff --git a/test/CodeGen/X86/soft-fp.ll b/test/CodeGen/X86/soft-fp.ll
new file mode 100644
index 0000000..a52135d
--- /dev/null
+++ b/test/CodeGen/X86/soft-fp.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -soft-float | not grep xmm
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 -soft-float | not grep xmm
+
+ %struct.__va_list_tag = type { i32, i32, i8*, i8* }
+
+define i32 @t1(i32 %a, ...) nounwind {
+entry:
+ %va = alloca [1 x %struct.__va_list_tag], align 8 ; <[1 x %struct.__va_list_tag]*> [#uses=2]
+ %va12 = bitcast [1 x %struct.__va_list_tag]* %va to i8* ; <i8*> [#uses=2]
+ call void @llvm.va_start(i8* %va12)
+ %va3 = getelementptr [1 x %struct.__va_list_tag]* %va, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
+ call void @bar(%struct.__va_list_tag* %va3) nounwind
+ call void @llvm.va_end(i8* %va12)
+ ret i32 undef
+}
+
+declare void @llvm.va_start(i8*) nounwind
+
+declare void @bar(%struct.__va_list_tag*)
+
+declare void @llvm.va_end(i8*) nounwind
+
+define float @t2(float %a, float %b) nounwind readnone {
+entry:
+ %0 = fadd float %a, %b ; <float> [#uses=1]
+ ret float %0
+}
diff --git a/test/CodeGen/X86/splat-scalar-load.ll b/test/CodeGen/X86/splat-scalar-load.ll
new file mode 100644
index 0000000..2b13029
--- /dev/null
+++ b/test/CodeGen/X86/splat-scalar-load.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 | FileCheck %s
+; rdar://7434544
+
+define <2 x i64> @t2() nounwind ssp {
+entry:
+; CHECK: t2:
+; CHECK: pshufd $85, (%esp), %xmm0
+ %array = alloca [8 x float], align 4
+ %arrayidx = getelementptr inbounds [8 x float]* %array, i32 0, i32 1
+ %tmp2 = load float* %arrayidx
+ %vecinit = insertelement <4 x float> undef, float %tmp2, i32 0
+ %vecinit5 = insertelement <4 x float> %vecinit, float %tmp2, i32 1
+ %vecinit7 = insertelement <4 x float> %vecinit5, float %tmp2, i32 2
+ %vecinit9 = insertelement <4 x float> %vecinit7, float %tmp2, i32 3
+ %0 = bitcast <4 x float> %vecinit9 to <2 x i64>
+ ret <2 x i64> %0
+}
diff --git a/test/CodeGen/X86/split-eh-lpad-edges.ll b/test/CodeGen/X86/split-eh-lpad-edges.ll
new file mode 100644
index 0000000..fd40a7f
--- /dev/null
+++ b/test/CodeGen/X86/split-eh-lpad-edges.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep jmp
+; rdar://6647639
+
+ %struct.FetchPlanHeader = type { i8*, i8*, i32, i8*, i8*, i8*, i8*, i8*, %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...)*, %struct.__attributeDescriptionFlags }
+ %struct.NSArray = type { %struct.NSObject }
+ %struct.NSAutoreleasePool = type { %struct.NSObject, i8*, i8*, i8*, i8* }
+ %struct.NSObject = type { %struct.NSObject* }
+ %struct.__attributeDescriptionFlags = type <{ i32 }>
+ %struct._message_ref_t = type { %struct.NSObject* (%struct.NSObject*, %struct._message_ref_t*, ...)*, %struct.objc_selector* }
+ %struct.objc_selector = type opaque
+@"\01l_objc_msgSend_fixup_alloc" = external global %struct._message_ref_t, align 16 ; <%struct._message_ref_t*> [#uses=2]
+
+define %struct.NSArray* @newFetchedRowsForFetchPlan_MT(%struct.FetchPlanHeader* %fetchPlan, %struct.objc_selector* %selectionMethod, %struct.NSObject* %selectionParameter) ssp {
+entry:
+ %0 = invoke %struct.NSObject* null(%struct.NSObject* null, %struct._message_ref_t* @"\01l_objc_msgSend_fixup_alloc")
+ to label %invcont unwind label %lpad ; <%struct.NSObject*> [#uses=1]
+
+invcont: ; preds = %entry
+ %1 = invoke %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...)* @objc_msgSend(%struct.NSObject* %0, %struct.objc_selector* null)
+ to label %invcont26 unwind label %lpad ; <%struct.NSObject*> [#uses=0]
+
+invcont26: ; preds = %invcont
+ %2 = invoke %struct.NSObject* null(%struct.NSObject* null, %struct._message_ref_t* @"\01l_objc_msgSend_fixup_alloc")
+ to label %invcont27 unwind label %lpad ; <%struct.NSObject*> [#uses=0]
+
+invcont27: ; preds = %invcont26
+ unreachable
+
+lpad: ; preds = %invcont26, %invcont, %entry
+ %pool.1 = phi %struct.NSAutoreleasePool* [ null, %entry ], [ null, %invcont ], [ null, %invcont26 ] ; <%struct.NSAutoreleasePool*> [#uses=0]
+ unreachable
+}
+
+declare %struct.NSObject* @objc_msgSend(%struct.NSObject*, %struct.objc_selector*, ...)
diff --git a/test/CodeGen/X86/split-select.ll b/test/CodeGen/X86/split-select.ll
new file mode 100644
index 0000000..07d4d52
--- /dev/null
+++ b/test/CodeGen/X86/split-select.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86-64 | grep test | count 1
+
+define void @foo(i1 %c, <2 x i16> %a, <2 x i16> %b, <2 x i16>* %p) {
+ %x = select i1 %c, <2 x i16> %a, <2 x i16> %b
+ store <2 x i16> %x, <2 x i16>* %p
+ ret void
+}
diff --git a/test/CodeGen/X86/split-vector-rem.ll b/test/CodeGen/X86/split-vector-rem.ll
new file mode 100644
index 0000000..681c6b0
--- /dev/null
+++ b/test/CodeGen/X86/split-vector-rem.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86-64 | grep div | count 16
+; RUN: llc < %s -march=x86-64 | grep fmodf | count 8
+
+define <8 x i32> @foo(<8 x i32> %t, <8 x i32> %u) {
+ %m = srem <8 x i32> %t, %u
+ ret <8 x i32> %m
+}
+define <8 x i32> @bar(<8 x i32> %t, <8 x i32> %u) {
+ %m = urem <8 x i32> %t, %u
+ ret <8 x i32> %m
+}
+define <8 x float> @qux(<8 x float> %t, <8 x float> %u) {
+ %m = frem <8 x float> %t, %u
+ ret <8 x float> %m
+}
diff --git a/test/CodeGen/X86/sret.ll b/test/CodeGen/X86/sret.ll
new file mode 100644
index 0000000..b945530
--- /dev/null
+++ b/test/CodeGen/X86/sret.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86 | grep ret | grep 4
+
+ %struct.foo = type { [4 x i32] }
+
+define void @bar(%struct.foo* noalias sret %agg.result) nounwind {
+entry:
+ %tmp1 = getelementptr %struct.foo* %agg.result, i32 0, i32 0
+ %tmp3 = getelementptr [4 x i32]* %tmp1, i32 0, i32 0
+ store i32 1, i32* %tmp3, align 8
+ ret void
+}
+
+@dst = external global i32
+
+define void @foo() nounwind {
+ %memtmp = alloca %struct.foo, align 4
+ call void @bar( %struct.foo* sret %memtmp ) nounwind
+ %tmp4 = getelementptr %struct.foo* %memtmp, i32 0, i32 0
+ %tmp5 = getelementptr [4 x i32]* %tmp4, i32 0, i32 0
+ %tmp6 = load i32* %tmp5
+ store i32 %tmp6, i32* @dst
+ ret void
+}
diff --git a/test/CodeGen/X86/sse-align-0.ll b/test/CodeGen/X86/sse-align-0.ll
new file mode 100644
index 0000000..b12a87d
--- /dev/null
+++ b/test/CodeGen/X86/sse-align-0.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86-64 | not grep mov
+
+define <4 x float> @foo(<4 x float>* %p, <4 x float> %x) nounwind {
+ %t = load <4 x float>* %p
+ %z = fmul <4 x float> %t, %x
+ ret <4 x float> %z
+}
+define <2 x double> @bar(<2 x double>* %p, <2 x double> %x) nounwind {
+ %t = load <2 x double>* %p
+ %z = fmul <2 x double> %t, %x
+ ret <2 x double> %z
+}
diff --git a/test/CodeGen/X86/sse-align-1.ll b/test/CodeGen/X86/sse-align-1.ll
new file mode 100644
index 0000000..c7a5cd5
--- /dev/null
+++ b/test/CodeGen/X86/sse-align-1.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86-64 | grep movap | count 2
+
+define <4 x float> @foo(<4 x float>* %p) nounwind {
+ %t = load <4 x float>* %p
+ ret <4 x float> %t
+}
+define <2 x double> @bar(<2 x double>* %p) nounwind {
+ %t = load <2 x double>* %p
+ ret <2 x double> %t
+}
diff --git a/test/CodeGen/X86/sse-align-10.ll b/test/CodeGen/X86/sse-align-10.ll
new file mode 100644
index 0000000..0f91697
--- /dev/null
+++ b/test/CodeGen/X86/sse-align-10.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86-64 | grep movups | count 1
+
+define <2 x i64> @bar(<2 x i64>* %p) nounwind {
+ %t = load <2 x i64>* %p, align 8
+ ret <2 x i64> %t
+}
diff --git a/test/CodeGen/X86/sse-align-11.ll b/test/CodeGen/X86/sse-align-11.ll
new file mode 100644
index 0000000..aa1b437
--- /dev/null
+++ b/test/CodeGen/X86/sse-align-11.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah -mtriple=i686-apple-darwin8 | grep movaps
+; RUN: llc < %s -march=x86 -mcpu=yonah -mtriple=linux | grep movups
+
+define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind {
+entry:
+ %tmp6 = insertelement <4 x float> undef, float %a, i32 0
+ %tmp7 = insertelement <4 x float> %tmp6, float %b, i32 1
+ %tmp8 = insertelement <4 x float> %tmp7, float %c, i32 2
+ %tmp9 = insertelement <4 x float> %tmp8, float %d, i32 3
+ ret <4 x float> %tmp9
+}
+
diff --git a/test/CodeGen/X86/sse-align-12.ll b/test/CodeGen/X86/sse-align-12.ll
new file mode 100644
index 0000000..4f025b9
--- /dev/null
+++ b/test/CodeGen/X86/sse-align-12.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: grep unpck %t | count 2
+; RUN: grep shuf %t | count 2
+; RUN: grep ps %t | count 4
+; RUN: grep pd %t | count 4
+; RUN: grep movup %t | count 4
+
+define <4 x float> @a(<4 x float>* %y) nounwind {
+ %x = load <4 x float>* %y, align 4
+ %a = extractelement <4 x float> %x, i32 0
+ %b = extractelement <4 x float> %x, i32 1
+ %c = extractelement <4 x float> %x, i32 2
+ %d = extractelement <4 x float> %x, i32 3
+ %p = insertelement <4 x float> undef, float %d, i32 0
+ %q = insertelement <4 x float> %p, float %c, i32 1
+ %r = insertelement <4 x float> %q, float %b, i32 2
+ %s = insertelement <4 x float> %r, float %a, i32 3
+ ret <4 x float> %s
+}
+define <4 x float> @b(<4 x float>* %y, <4 x float> %z) nounwind {
+ %x = load <4 x float>* %y, align 4
+ %a = extractelement <4 x float> %x, i32 2
+ %b = extractelement <4 x float> %x, i32 3
+ %c = extractelement <4 x float> %z, i32 2
+ %d = extractelement <4 x float> %z, i32 3
+ %p = insertelement <4 x float> undef, float %c, i32 0
+ %q = insertelement <4 x float> %p, float %a, i32 1
+ %r = insertelement <4 x float> %q, float %d, i32 2
+ %s = insertelement <4 x float> %r, float %b, i32 3
+ ret <4 x float> %s
+}
+define <2 x double> @c(<2 x double>* %y) nounwind {
+ %x = load <2 x double>* %y, align 8
+ %a = extractelement <2 x double> %x, i32 0
+ %c = extractelement <2 x double> %x, i32 1
+ %p = insertelement <2 x double> undef, double %c, i32 0
+ %r = insertelement <2 x double> %p, double %a, i32 1
+ ret <2 x double> %r
+}
+define <2 x double> @d(<2 x double>* %y, <2 x double> %z) nounwind {
+ %x = load <2 x double>* %y, align 8
+ %a = extractelement <2 x double> %x, i32 1
+ %c = extractelement <2 x double> %z, i32 1
+ %p = insertelement <2 x double> undef, double %c, i32 0
+ %r = insertelement <2 x double> %p, double %a, i32 1
+ ret <2 x double> %r
+}
diff --git a/test/CodeGen/X86/sse-align-2.ll b/test/CodeGen/X86/sse-align-2.ll
new file mode 100644
index 0000000..102c3fb
--- /dev/null
+++ b/test/CodeGen/X86/sse-align-2.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86-64 | grep movup | count 2
+
+define <4 x float> @foo(<4 x float>* %p, <4 x float> %x) nounwind {
+ %t = load <4 x float>* %p, align 4
+ %z = fmul <4 x float> %t, %x
+ ret <4 x float> %z
+}
+define <2 x double> @bar(<2 x double>* %p, <2 x double> %x) nounwind {
+ %t = load <2 x double>* %p, align 8
+ %z = fmul <2 x double> %t, %x
+ ret <2 x double> %z
+}
diff --git a/test/CodeGen/X86/sse-align-3.ll b/test/CodeGen/X86/sse-align-3.ll
new file mode 100644
index 0000000..c42f7f0
--- /dev/null
+++ b/test/CodeGen/X86/sse-align-3.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86-64 | grep movap | count 2
+
+define void @foo(<4 x float>* %p, <4 x float> %x) nounwind {
+ store <4 x float> %x, <4 x float>* %p
+ ret void
+}
+define void @bar(<2 x double>* %p, <2 x double> %x) nounwind {
+ store <2 x double> %x, <2 x double>* %p
+ ret void
+}
diff --git a/test/CodeGen/X86/sse-align-4.ll b/test/CodeGen/X86/sse-align-4.ll
new file mode 100644
index 0000000..4c59934
--- /dev/null
+++ b/test/CodeGen/X86/sse-align-4.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86-64 | grep movup | count 2
+
+define void @foo(<4 x float>* %p, <4 x float> %x) nounwind {
+ store <4 x float> %x, <4 x float>* %p, align 4
+ ret void
+}
+define void @bar(<2 x double>* %p, <2 x double> %x) nounwind {
+ store <2 x double> %x, <2 x double>* %p, align 8
+ ret void
+}
diff --git a/test/CodeGen/X86/sse-align-5.ll b/test/CodeGen/X86/sse-align-5.ll
new file mode 100644
index 0000000..21cd231
--- /dev/null
+++ b/test/CodeGen/X86/sse-align-5.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86-64 | grep movaps | count 1
+
+define <2 x i64> @bar(<2 x i64>* %p) nounwind {
+ %t = load <2 x i64>* %p
+ ret <2 x i64> %t
+}
diff --git a/test/CodeGen/X86/sse-align-6.ll b/test/CodeGen/X86/sse-align-6.ll
new file mode 100644
index 0000000..0bbf4228
--- /dev/null
+++ b/test/CodeGen/X86/sse-align-6.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86-64 | grep movups | count 1
+
+define <2 x i64> @bar(<2 x i64>* %p, <2 x i64> %x) nounwind {
+ %t = load <2 x i64>* %p, align 8
+ %z = mul <2 x i64> %t, %x
+ ret <2 x i64> %z
+}
diff --git a/test/CodeGen/X86/sse-align-7.ll b/test/CodeGen/X86/sse-align-7.ll
new file mode 100644
index 0000000..5784481
--- /dev/null
+++ b/test/CodeGen/X86/sse-align-7.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86-64 | grep movaps | count 1
+
+define void @bar(<2 x i64>* %p, <2 x i64> %x) nounwind {
+ store <2 x i64> %x, <2 x i64>* %p
+ ret void
+}
diff --git a/test/CodeGen/X86/sse-align-8.ll b/test/CodeGen/X86/sse-align-8.ll
new file mode 100644
index 0000000..cfeff81
--- /dev/null
+++ b/test/CodeGen/X86/sse-align-8.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86-64 | grep movups | count 1
+
+define void @bar(<2 x i64>* %p, <2 x i64> %x) nounwind {
+ store <2 x i64> %x, <2 x i64>* %p, align 8
+ ret void
+}
diff --git a/test/CodeGen/X86/sse-align-9.ll b/test/CodeGen/X86/sse-align-9.ll
new file mode 100644
index 0000000..cb26b95
--- /dev/null
+++ b/test/CodeGen/X86/sse-align-9.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86-64 | grep movup | count 2
+
+define <4 x float> @foo(<4 x float>* %p) nounwind {
+ %t = load <4 x float>* %p, align 4
+ ret <4 x float> %t
+}
+define <2 x double> @bar(<2 x double>* %p) nounwind {
+ %t = load <2 x double>* %p, align 8
+ ret <2 x double> %t
+}
diff --git a/test/CodeGen/X86/sse-fcopysign.ll b/test/CodeGen/X86/sse-fcopysign.ll
new file mode 100644
index 0000000..0e0e4a9
--- /dev/null
+++ b/test/CodeGen/X86/sse-fcopysign.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep test
+
+define float @tst1(float %a, float %b) {
+ %tmp = tail call float @copysignf( float %b, float %a )
+ ret float %tmp
+}
+
+define double @tst2(double %a, float %b, float %c) {
+ %tmp1 = fadd float %b, %c
+ %tmp2 = fpext float %tmp1 to double
+ %tmp = tail call double @copysign( double %a, double %tmp2 )
+ ret double %tmp
+}
+
+declare float @copysignf(float, float)
+declare double @copysign(double, double)
diff --git a/test/CodeGen/X86/sse-load-ret.ll b/test/CodeGen/X86/sse-load-ret.ll
new file mode 100644
index 0000000..1ebcb1a
--- /dev/null
+++ b/test/CodeGen/X86/sse-load-ret.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah | not grep movss
+; RUN: llc < %s -march=x86 -mcpu=yonah | not grep xmm
+
+define double @test1(double* %P) {
+ %X = load double* %P ; <double> [#uses=1]
+ ret double %X
+}
+
+define double @test2() {
+ ret double 1.234560e+03
+}
+
+
+; FIXME: Todo
+;double %test3(bool %B) {
+; %C = select bool %B, double 123.412, double 523.01123123
+; ret double %C
+;}
+
diff --git a/test/CodeGen/X86/sse-minmax.ll b/test/CodeGen/X86/sse-minmax.ll
new file mode 100644
index 0000000..17ffb5e
--- /dev/null
+++ b/test/CodeGen/X86/sse-minmax.ll
@@ -0,0 +1,392 @@
+; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s
+
+; Some of these patterns can be matched as SSE min or max. Some of
+; then can be matched provided that the operands are swapped.
+; Some of them can't be matched at all and require a comparison
+; and a conditional branch.
+
+; The naming convention is {,x_}{o,u}{gt,lt,ge,le}{,_inverse}
+; x_ : use 0.0 instead of %y
+; _inverse : swap the arms of the select.
+
+; CHECK: ogt:
+; CHECK-NEXT: maxsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @ogt(double %x, double %y) nounwind {
+ %c = fcmp ogt double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: olt:
+; CHECK-NEXT: minsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @olt(double %x, double %y) nounwind {
+ %c = fcmp olt double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: ogt_inverse:
+; CHECK-NEXT: minsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @ogt_inverse(double %x, double %y) nounwind {
+ %c = fcmp ogt double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: olt_inverse:
+; CHECK-NEXT: maxsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @olt_inverse(double %x, double %y) nounwind {
+ %c = fcmp olt double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: oge:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+define double @oge(double %x, double %y) nounwind {
+ %c = fcmp oge double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: ole:
+; CHECK-NEXT: ucomisd %xmm0, %xmm1
+define double @ole(double %x, double %y) nounwind {
+ %c = fcmp ole double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: oge_inverse:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+define double @oge_inverse(double %x, double %y) nounwind {
+ %c = fcmp oge double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: ole_inverse:
+; CHECK-NEXT: ucomisd %xmm0, %xmm1
+define double @ole_inverse(double %x, double %y) nounwind {
+ %c = fcmp ole double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: x_ogt:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ogt(double %x) nounwind {
+ %c = fcmp ogt double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_olt:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_olt(double %x) nounwind {
+ %c = fcmp olt double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_ogt_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ogt_inverse(double %x) nounwind {
+ %c = fcmp ogt double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; CHECK: x_olt_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_olt_inverse(double %x) nounwind {
+ %c = fcmp olt double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; CHECK: x_oge:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_oge(double %x) nounwind {
+ %c = fcmp oge double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_ole:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ole(double %x) nounwind {
+ %c = fcmp ole double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_oge_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_oge_inverse(double %x) nounwind {
+ %c = fcmp oge double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; CHECK: x_ole_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ole_inverse(double %x) nounwind {
+ %c = fcmp ole double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; CHECK: ugt:
+; CHECK-NEXT: ucomisd %xmm0, %xmm1
+define double @ugt(double %x, double %y) nounwind {
+ %c = fcmp ugt double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: ult:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+define double @ult(double %x, double %y) nounwind {
+ %c = fcmp ult double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: ugt_inverse:
+; CHECK-NEXT: ucomisd %xmm0, %xmm1
+define double @ugt_inverse(double %x, double %y) nounwind {
+ %c = fcmp ugt double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: ult_inverse:
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+define double @ult_inverse(double %x, double %y) nounwind {
+ %c = fcmp ult double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: uge:
+; CHECK-NEXT: maxsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @uge(double %x, double %y) nounwind {
+ %c = fcmp uge double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: ule:
+; CHECK-NEXT: minsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @ule(double %x, double %y) nounwind {
+ %c = fcmp ule double %x, %y
+ %d = select i1 %c, double %x, double %y
+ ret double %d
+}
+
+; CHECK: uge_inverse:
+; CHECK-NEXT: minsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @uge_inverse(double %x, double %y) nounwind {
+ %c = fcmp uge double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: ule_inverse:
+; CHECK-NEXT: maxsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @ule_inverse(double %x, double %y) nounwind {
+ %c = fcmp ule double %x, %y
+ %d = select i1 %c, double %y, double %x
+ ret double %d
+}
+
+; CHECK: x_ugt:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ugt(double %x) nounwind {
+ %c = fcmp ugt double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_ult:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ult(double %x) nounwind {
+ %c = fcmp ult double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_ugt_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ugt_inverse(double %x) nounwind {
+ %c = fcmp ugt double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; CHECK: x_ult_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ult_inverse(double %x) nounwind {
+ %c = fcmp ult double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; CHECK: x_uge:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_uge(double %x) nounwind {
+ %c = fcmp uge double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_ule:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm0, %xmm1
+; CHECK-NEXT: movapd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ule(double %x) nounwind {
+ %c = fcmp ule double %x, 0.000000e+00
+ %d = select i1 %c, double %x, double 0.000000e+00
+ ret double %d
+}
+
+; CHECK: x_uge_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: minsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_uge_inverse(double %x) nounwind {
+ %c = fcmp uge double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; CHECK: x_ule_inverse:
+; CHECK-NEXT: pxor %xmm1, %xmm1
+; CHECK-NEXT: maxsd %xmm1, %xmm0
+; CHECK-NEXT: ret
+define double @x_ule_inverse(double %x) nounwind {
+ %c = fcmp ule double %x, 0.000000e+00
+ %d = select i1 %c, double 0.000000e+00, double %x
+ ret double %d
+}
+
+; Test a few more misc. cases.
+
+; CHECK: clampTo3k_a:
+; CHECK: minsd
+define double @clampTo3k_a(double %x) nounwind readnone {
+entry:
+ %0 = fcmp ogt double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
+
+; CHECK: clampTo3k_b:
+; CHECK: minsd
+define double @clampTo3k_b(double %x) nounwind readnone {
+entry:
+ %0 = fcmp uge double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
+
+; CHECK: clampTo3k_c:
+; CHECK: maxsd
+define double @clampTo3k_c(double %x) nounwind readnone {
+entry:
+ %0 = fcmp olt double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
+
+; CHECK: clampTo3k_d:
+; CHECK: maxsd
+define double @clampTo3k_d(double %x) nounwind readnone {
+entry:
+ %0 = fcmp ule double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
+
+; CHECK: clampTo3k_e:
+; CHECK: maxsd
+define double @clampTo3k_e(double %x) nounwind readnone {
+entry:
+ %0 = fcmp olt double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
+
+; CHECK: clampTo3k_f:
+; CHECK: maxsd
+define double @clampTo3k_f(double %x) nounwind readnone {
+entry:
+ %0 = fcmp ule double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
+
+; CHECK: clampTo3k_g:
+; CHECK: minsd
+define double @clampTo3k_g(double %x) nounwind readnone {
+entry:
+ %0 = fcmp ogt double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
+
+; CHECK: clampTo3k_h:
+; CHECK: minsd
+define double @clampTo3k_h(double %x) nounwind readnone {
+entry:
+ %0 = fcmp uge double %x, 3.000000e+03 ; <i1> [#uses=1]
+ %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]
+ ret double %x_addr.0
+}
diff --git a/test/CodeGen/X86/sse-varargs.ll b/test/CodeGen/X86/sse-varargs.ll
new file mode 100644
index 0000000..da38f0e
--- /dev/null
+++ b/test/CodeGen/X86/sse-varargs.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep xmm | grep esp
+
+define i32 @t() nounwind {
+entry:
+ tail call void (i32, ...)* @foo( i32 1, <4 x i32> < i32 10, i32 11, i32 12, i32 13 > ) nounwind
+ ret i32 0
+}
+
+declare void @foo(i32, ...)
diff --git a/test/CodeGen/X86/sse2.ll b/test/CodeGen/X86/sse2.ll
new file mode 100644
index 0000000..f2b8010
--- /dev/null
+++ b/test/CodeGen/X86/sse2.ll
@@ -0,0 +1,34 @@
+; Tests for SSE2 and below, without SSE3+.
+; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=pentium4 -O3 | FileCheck %s
+
+define void @t1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind {
+ %tmp3 = load <2 x double>* %A, align 16
+ %tmp7 = insertelement <2 x double> undef, double %B, i32 0
+ %tmp9 = shufflevector <2 x double> %tmp3, <2 x double> %tmp7, <2 x i32> < i32 2, i32 1 >
+ store <2 x double> %tmp9, <2 x double>* %r, align 16
+ ret void
+
+; CHECK: t1:
+; CHECK: movl 8(%esp), %eax
+; CHECK-NEXT: movl 4(%esp), %ecx
+; CHECK-NEXT: movapd (%eax), %xmm0
+; CHECK-NEXT: movlpd 12(%esp), %xmm0
+; CHECK-NEXT: movapd %xmm0, (%ecx)
+; CHECK-NEXT: ret
+}
+
+define void @t2(<2 x double>* %r, <2 x double>* %A, double %B) nounwind {
+ %tmp3 = load <2 x double>* %A, align 16
+ %tmp7 = insertelement <2 x double> undef, double %B, i32 0
+ %tmp9 = shufflevector <2 x double> %tmp3, <2 x double> %tmp7, <2 x i32> < i32 0, i32 2 >
+ store <2 x double> %tmp9, <2 x double>* %r, align 16
+ ret void
+
+; CHECK: t2:
+; CHECK: movl 8(%esp), %eax
+; CHECK-NEXT: movl 4(%esp), %ecx
+; CHECK-NEXT: movapd (%eax), %xmm0
+; CHECK-NEXT: movhpd 12(%esp), %xmm0
+; CHECK-NEXT: movapd %xmm0, (%ecx)
+; CHECK-NEXT: ret
+}
diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll
new file mode 100644
index 0000000..b2af7c9
--- /dev/null
+++ b/test/CodeGen/X86/sse3.ll
@@ -0,0 +1,263 @@
+; These are tests for SSE3 codegen. Yonah has SSE3 and earlier but not SSSE3+.
+
+; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9 -O3 \
+; RUN: | FileCheck %s --check-prefix=X64
+
+; Test for v8xi16 lowering where we extract the first element of the vector and
+; placed it in the second element of the result.
+
+define void @t0(<8 x i16>* %dest, <8 x i16>* %old) nounwind {
+entry:
+ %tmp3 = load <8 x i16>* %old
+ %tmp6 = shufflevector <8 x i16> %tmp3,
+ <8 x i16> < i16 0, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef >,
+ <8 x i32> < i32 8, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef >
+ store <8 x i16> %tmp6, <8 x i16>* %dest
+ ret void
+
+; X64: t0:
+; X64: movddup (%rsi), %xmm0
+; X64: xorl %eax, %eax
+; X64: pshuflw $0, %xmm0, %xmm0
+; X64: pinsrw $0, %eax, %xmm0
+; X64: movaps %xmm0, (%rdi)
+; X64: ret
+}
+
+define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
+ ret <8 x i16> %tmp3
+
+; X64: t1:
+; X64: movl (%rsi), %eax
+; X64: movaps (%rdi), %xmm0
+; X64: pinsrw $0, %eax, %xmm0
+; X64: ret
+}
+
+define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) nounwind {
+ %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 9, i32 1, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7 >
+ ret <8 x i16> %tmp
+; X64: t2:
+; X64: pextrw $1, %xmm1, %eax
+; X64: pinsrw $0, %eax, %xmm0
+; X64: pinsrw $3, %eax, %xmm0
+; X64: ret
+}
+
+define <8 x i16> @t3(<8 x i16> %A, <8 x i16> %B) nounwind {
+ %tmp = shufflevector <8 x i16> %A, <8 x i16> %A, <8 x i32> < i32 8, i32 3, i32 2, i32 13, i32 7, i32 6, i32 5, i32 4 >
+ ret <8 x i16> %tmp
+; X64: t3:
+; X64: pextrw $5, %xmm0, %eax
+; X64: pshuflw $44, %xmm0, %xmm0
+; X64: pshufhw $27, %xmm0, %xmm0
+; X64: pinsrw $3, %eax, %xmm0
+; X64: ret
+}
+
+define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind {
+ %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 7, i32 2, i32 3, i32 1, i32 5, i32 6, i32 5 >
+ ret <8 x i16> %tmp
+; X64: t4:
+; X64: pextrw $7, %xmm0, %eax
+; X64: pshufhw $100, %xmm0, %xmm2
+; X64: pinsrw $1, %eax, %xmm2
+; X64: pextrw $1, %xmm0, %eax
+; X64: movaps %xmm2, %xmm0
+; X64: pinsrw $4, %eax, %xmm0
+; X64: ret
+}
+
+define <8 x i16> @t5(<8 x i16> %A, <8 x i16> %B) nounwind {
+ %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 0, i32 1, i32 10, i32 11, i32 2, i32 3 >
+ ret <8 x i16> %tmp
+; X64: t5:
+; X64: movlhps %xmm1, %xmm0
+; X64: pshufd $114, %xmm0, %xmm0
+; X64: ret
+}
+
+define <8 x i16> @t6(<8 x i16> %A, <8 x i16> %B) nounwind {
+ %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
+ ret <8 x i16> %tmp
+; X64: t6:
+; X64: movss %xmm1, %xmm0
+; X64: ret
+}
+
+define <8 x i16> @t7(<8 x i16> %A, <8 x i16> %B) nounwind {
+ %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 0, i32 3, i32 2, i32 4, i32 6, i32 4, i32 7 >
+ ret <8 x i16> %tmp
+; X64: t7:
+; X64: pshuflw $-80, %xmm0, %xmm0
+; X64: pshufhw $-56, %xmm0, %xmm0
+; X64: ret
+}
+
+define void @t8(<2 x i64>* %res, <2 x i64>* %A) nounwind {
+ %tmp = load <2 x i64>* %A
+ %tmp.upgrd.1 = bitcast <2 x i64> %tmp to <8 x i16>
+ %tmp0 = extractelement <8 x i16> %tmp.upgrd.1, i32 0
+ %tmp1 = extractelement <8 x i16> %tmp.upgrd.1, i32 1
+ %tmp2 = extractelement <8 x i16> %tmp.upgrd.1, i32 2
+ %tmp3 = extractelement <8 x i16> %tmp.upgrd.1, i32 3
+ %tmp4 = extractelement <8 x i16> %tmp.upgrd.1, i32 4
+ %tmp5 = extractelement <8 x i16> %tmp.upgrd.1, i32 5
+ %tmp6 = extractelement <8 x i16> %tmp.upgrd.1, i32 6
+ %tmp7 = extractelement <8 x i16> %tmp.upgrd.1, i32 7
+ %tmp8 = insertelement <8 x i16> undef, i16 %tmp2, i32 0
+ %tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp1, i32 1
+ %tmp10 = insertelement <8 x i16> %tmp9, i16 %tmp0, i32 2
+ %tmp11 = insertelement <8 x i16> %tmp10, i16 %tmp3, i32 3
+ %tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp6, i32 4
+ %tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 5
+ %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp4, i32 6
+ %tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 7
+ %tmp15.upgrd.2 = bitcast <8 x i16> %tmp15 to <2 x i64>
+ store <2 x i64> %tmp15.upgrd.2, <2 x i64>* %res
+ ret void
+; X64: t8:
+; X64: pshuflw $-58, (%rsi), %xmm0
+; X64: pshufhw $-58, %xmm0, %xmm0
+; X64: movaps %xmm0, (%rdi)
+; X64: ret
+}
+
+define void @t9(<4 x float>* %r, <2 x i32>* %A) nounwind {
+ %tmp = load <4 x float>* %r
+ %tmp.upgrd.3 = bitcast <2 x i32>* %A to double*
+ %tmp.upgrd.4 = load double* %tmp.upgrd.3
+ %tmp.upgrd.5 = insertelement <2 x double> undef, double %tmp.upgrd.4, i32 0
+ %tmp5 = insertelement <2 x double> %tmp.upgrd.5, double undef, i32 1
+ %tmp6 = bitcast <2 x double> %tmp5 to <4 x float>
+ %tmp.upgrd.6 = extractelement <4 x float> %tmp, i32 0
+ %tmp7 = extractelement <4 x float> %tmp, i32 1
+ %tmp8 = extractelement <4 x float> %tmp6, i32 0
+ %tmp9 = extractelement <4 x float> %tmp6, i32 1
+ %tmp10 = insertelement <4 x float> undef, float %tmp.upgrd.6, i32 0
+ %tmp11 = insertelement <4 x float> %tmp10, float %tmp7, i32 1
+ %tmp12 = insertelement <4 x float> %tmp11, float %tmp8, i32 2
+ %tmp13 = insertelement <4 x float> %tmp12, float %tmp9, i32 3
+ store <4 x float> %tmp13, <4 x float>* %r
+ ret void
+; X64: t9:
+; X64: movsd (%rsi), %xmm0
+; X64: movaps (%rdi), %xmm1
+; X64: movlhps %xmm0, %xmm1
+; X64: movaps %xmm1, (%rdi)
+; X64: ret
+}
+
+
+
+; FIXME: This testcase produces icky code. It can be made much better!
+; PR2585
+
+@g1 = external constant <4 x i32>
+@g2 = external constant <4 x i16>
+
+define internal void @t10() nounwind {
+ load <4 x i32>* @g1, align 16
+ bitcast <4 x i32> %1 to <8 x i16>
+ shufflevector <8 x i16> %2, <8 x i16> undef, <8 x i32> < i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef >
+ bitcast <8 x i16> %3 to <2 x i64>
+ extractelement <2 x i64> %4, i32 0
+ bitcast i64 %5 to <4 x i16>
+ store <4 x i16> %6, <4 x i16>* @g2, align 8
+ ret void
+; X64: t10:
+; X64: pextrw $4, %xmm0, %eax
+; X64: pextrw $6, %xmm0, %edx
+; X64: movlhps %xmm1, %xmm1
+; X64: pshuflw $8, %xmm1, %xmm1
+; X64: pinsrw $2, %eax, %xmm1
+; X64: pinsrw $3, %edx, %xmm1
+}
+
+
+; Pack various elements via shuffles.
+define <8 x i16> @t11(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp7 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 1, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
+ ret <8 x i16> %tmp7
+
+; X64: t11:
+; X64: movlhps %xmm0, %xmm0
+; X64: movd %xmm1, %eax
+; X64: pshuflw $1, %xmm0, %xmm0
+; X64: pinsrw $1, %eax, %xmm0
+; X64: ret
+}
+
+
+define <8 x i16> @t12(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 0, i32 1, i32 undef, i32 undef, i32 3, i32 11, i32 undef , i32 undef >
+ ret <8 x i16> %tmp9
+
+; X64: t12:
+; X64: movlhps %xmm0, %xmm0
+; X64: pextrw $3, %xmm1, %eax
+; X64: pshufhw $3, %xmm0, %xmm0
+; X64: pinsrw $5, %eax, %xmm0
+; X64: ret
+}
+
+
+define <8 x i16> @t13(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 11, i32 3, i32 undef , i32 undef >
+ ret <8 x i16> %tmp9
+; X64: t13:
+; X64: punpcklqdq %xmm0, %xmm1
+; X64: pextrw $3, %xmm1, %eax
+; X64: pshufd $52, %xmm1, %xmm0
+; X64: pinsrw $4, %eax, %xmm0
+; X64: ret
+}
+
+
+define <8 x i16> @t14(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 2, i32 undef , i32 undef >
+ ret <8 x i16> %tmp9
+; X64: t14:
+; X64: punpcklqdq %xmm0, %xmm1
+; X64: pshufhw $8, %xmm1, %xmm0
+; X64: ret
+}
+
+
+
+define <8 x i16> @t15(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef >
+ ret <8 x i16> %tmp8
+; X64: t15:
+; X64: pextrw $7, %xmm0, %eax
+; X64: punpcklqdq %xmm1, %xmm0
+; X64: pshuflw $-128, %xmm0, %xmm0
+; X64: pinsrw $2, %eax, %xmm0
+; X64: ret
+}
+
+
+; Test yonah where we convert a shuffle to pextrw and pinrsw
+define <16 x i8> @t16(<16 x i8> %T0) nounwind readnone {
+entry:
+ %tmp8 = shufflevector <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 16, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
+ %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
+ ret <16 x i8> %tmp9
+; X64: t16:
+; X64: pinsrw $0, %eax, %xmm1
+; X64: pextrw $8, %xmm0, %eax
+; X64: pinsrw $1, %eax, %xmm1
+; X64: pextrw $1, %xmm1, %ecx
+; X64: movd %xmm1, %edx
+; X64: pinsrw $0, %edx, %xmm1
+; X64: pinsrw $1, %eax, %xmm0
+; X64: ret
+}
diff --git a/test/CodeGen/X86/sse41.ll b/test/CodeGen/X86/sse41.ll
new file mode 100644
index 0000000..a734c05
--- /dev/null
+++ b/test/CodeGen/X86/sse41.ll
@@ -0,0 +1,226 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse41 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse41 | FileCheck %s -check-prefix=X64
+
+@g16 = external global i16
+
+define <4 x i32> @pinsrd_1(i32 %s, <4 x i32> %tmp) nounwind {
+ %tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 1
+ ret <4 x i32> %tmp1
+; X32: pinsrd_1:
+; X32: pinsrd $1, 4(%esp), %xmm0
+
+; X64: pinsrd_1:
+; X64: pinsrd $1, %edi, %xmm0
+}
+
+define <16 x i8> @pinsrb_1(i8 %s, <16 x i8> %tmp) nounwind {
+ %tmp1 = insertelement <16 x i8> %tmp, i8 %s, i32 1
+ ret <16 x i8> %tmp1
+; X32: pinsrb_1:
+; X32: pinsrb $1, 4(%esp), %xmm0
+
+; X64: pinsrb_1:
+; X64: pinsrb $1, %edi, %xmm0
+}
+
+
+define <2 x i64> @pmovsxbd_1(i32* %p) nounwind {
+entry:
+ %0 = load i32* %p, align 4
+ %1 = insertelement <4 x i32> undef, i32 %0, i32 0
+ %2 = insertelement <4 x i32> %1, i32 0, i32 1
+ %3 = insertelement <4 x i32> %2, i32 0, i32 2
+ %4 = insertelement <4 x i32> %3, i32 0, i32 3
+ %5 = bitcast <4 x i32> %4 to <16 x i8>
+ %6 = tail call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %5) nounwind readnone
+ %7 = bitcast <4 x i32> %6 to <2 x i64>
+ ret <2 x i64> %7
+
+; X32: _pmovsxbd_1:
+; X32: movl 4(%esp), %eax
+; X32: pmovsxbd (%eax), %xmm0
+
+; X64: _pmovsxbd_1:
+; X64: pmovsxbd (%rdi), %xmm0
+}
+
+define <2 x i64> @pmovsxwd_1(i64* %p) nounwind readonly {
+entry:
+ %0 = load i64* %p ; <i64> [#uses=1]
+ %tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0 ; <<2 x i64>> [#uses=1]
+ %1 = bitcast <2 x i64> %tmp2 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone ; <<4 x i32>> [#uses=1]
+ %3 = bitcast <4 x i32> %2 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %3
+
+; X32: _pmovsxwd_1:
+; X32: movl 4(%esp), %eax
+; X32: pmovsxwd (%eax), %xmm0
+
+; X64: _pmovsxwd_1:
+; X64: pmovsxwd (%rdi), %xmm0
+}
+
+
+
+
+define <2 x i64> @pmovzxbq_1() nounwind {
+entry:
+ %0 = load i16* @g16, align 2 ; <i16> [#uses=1]
+ %1 = insertelement <8 x i16> undef, i16 %0, i32 0 ; <<8 x i16>> [#uses=1]
+ %2 = bitcast <8 x i16> %1 to <16 x i8> ; <<16 x i8>> [#uses=1]
+ %3 = tail call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %2) nounwind readnone ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %3
+
+; X32: _pmovzxbq_1:
+; X32: movl L_g16$non_lazy_ptr, %eax
+; X32: pmovzxbq (%eax), %xmm0
+
+; X64: _pmovzxbq_1:
+; X64: movq _g16@GOTPCREL(%rip), %rax
+; X64: pmovzxbq (%rax), %xmm0
+}
+
+declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
+declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
+declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
+
+
+
+
+define i32 @extractps_1(<4 x float> %v) nounwind {
+ %s = extractelement <4 x float> %v, i32 3
+ %i = bitcast float %s to i32
+ ret i32 %i
+
+; X32: _extractps_1:
+; X32: extractps $3, %xmm0, %eax
+
+; X64: _extractps_1:
+; X64: extractps $3, %xmm0, %eax
+}
+define i32 @extractps_2(<4 x float> %v) nounwind {
+ %t = bitcast <4 x float> %v to <4 x i32>
+ %s = extractelement <4 x i32> %t, i32 3
+ ret i32 %s
+
+; X32: _extractps_2:
+; X32: extractps $3, %xmm0, %eax
+
+; X64: _extractps_2:
+; X64: extractps $3, %xmm0, %eax
+}
+
+
+; The non-store form of extractps puts its result into a GPR.
+; This makes it suitable for an extract from a <4 x float> that
+; is bitcasted to i32, but unsuitable for much of anything else.
+
+define float @ext_1(<4 x float> %v) nounwind {
+ %s = extractelement <4 x float> %v, i32 3
+ %t = fadd float %s, 1.0
+ ret float %t
+
+; X32: _ext_1:
+; X32: pshufd $3, %xmm0, %xmm0
+; X32: addss LCPI8_0, %xmm0
+
+; X64: _ext_1:
+; X64: pshufd $3, %xmm0, %xmm0
+; X64: addss LCPI8_0(%rip), %xmm0
+}
+define float @ext_2(<4 x float> %v) nounwind {
+ %s = extractelement <4 x float> %v, i32 3
+ ret float %s
+
+; X32: _ext_2:
+; X32: pshufd $3, %xmm0, %xmm0
+
+; X64: _ext_2:
+; X64: pshufd $3, %xmm0, %xmm0
+}
+define i32 @ext_3(<4 x i32> %v) nounwind {
+ %i = extractelement <4 x i32> %v, i32 3
+ ret i32 %i
+
+; X32: _ext_3:
+; X32: pextrd $3, %xmm0, %eax
+
+; X64: _ext_3:
+; X64: pextrd $3, %xmm0, %eax
+}
+
+define <4 x float> @insertps_1(<4 x float> %t1, <4 x float> %t2) nounwind {
+ %tmp1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %t1, <4 x float> %t2, i32 1) nounwind readnone
+ ret <4 x float> %tmp1
+; X32: _insertps_1:
+; X32: insertps $1, %xmm1, %xmm0
+
+; X64: _insertps_1:
+; X64: insertps $1, %xmm1, %xmm0
+}
+
+declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
+
+define <4 x float> @insertps_2(<4 x float> %t1, float %t2) nounwind {
+ %tmp1 = insertelement <4 x float> %t1, float %t2, i32 0
+ ret <4 x float> %tmp1
+; X32: _insertps_2:
+; X32: insertps $0, 4(%esp), %xmm0
+
+; X64: _insertps_2:
+; X64: insertps $0, %xmm1, %xmm0
+}
+
+define <4 x float> @insertps_3(<4 x float> %t1, <4 x float> %t2) nounwind {
+ %tmp2 = extractelement <4 x float> %t2, i32 0
+ %tmp1 = insertelement <4 x float> %t1, float %tmp2, i32 0
+ ret <4 x float> %tmp1
+; X32: _insertps_3:
+; X32: insertps $0, %xmm1, %xmm0
+
+; X64: _insertps_3:
+; X64: insertps $0, %xmm1, %xmm0
+}
+
+define i32 @ptestz_1(<4 x float> %t1, <4 x float> %t2) nounwind {
+ %tmp1 = call i32 @llvm.x86.sse41.ptestz(<4 x float> %t1, <4 x float> %t2) nounwind readnone
+ ret i32 %tmp1
+; X32: _ptestz_1:
+; X32: ptest %xmm1, %xmm0
+; X32: sete %al
+
+; X64: _ptestz_1:
+; X64: ptest %xmm1, %xmm0
+; X64: sete %al
+}
+
+define i32 @ptestz_2(<4 x float> %t1, <4 x float> %t2) nounwind {
+ %tmp1 = call i32 @llvm.x86.sse41.ptestc(<4 x float> %t1, <4 x float> %t2) nounwind readnone
+ ret i32 %tmp1
+; X32: _ptestz_2:
+; X32: ptest %xmm1, %xmm0
+; X32: setb %al
+
+; X64: _ptestz_2:
+; X64: ptest %xmm1, %xmm0
+; X64: setb %al
+}
+
+define i32 @ptestz_3(<4 x float> %t1, <4 x float> %t2) nounwind {
+ %tmp1 = call i32 @llvm.x86.sse41.ptestnzc(<4 x float> %t1, <4 x float> %t2) nounwind readnone
+ ret i32 %tmp1
+; X32: _ptestz_3:
+; X32: ptest %xmm1, %xmm0
+; X32: seta %al
+
+; X64: _ptestz_3:
+; X64: ptest %xmm1, %xmm0
+; X64: seta %al
+}
+
+
+declare i32 @llvm.x86.sse41.ptestz(<4 x float>, <4 x float>) nounwind readnone
+declare i32 @llvm.x86.sse41.ptestc(<4 x float>, <4 x float>) nounwind readnone
+declare i32 @llvm.x86.sse41.ptestnzc(<4 x float>, <4 x float>) nounwind readnone
+
diff --git a/test/CodeGen/X86/sse42.ll b/test/CodeGen/X86/sse42.ll
new file mode 100644
index 0000000..c9c4d01
--- /dev/null
+++ b/test/CodeGen/X86/sse42.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64
+
+declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind
+declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind
+declare i32 @llvm.x86.sse42.crc32.32(i32, i32) nounwind
+
+define i32 @crc32_8(i32 %a, i8 %b) nounwind {
+ %tmp = call i32 @llvm.x86.sse42.crc32.8(i32 %a, i8 %b)
+ ret i32 %tmp
+; X32: _crc32_8:
+; X32: crc32 8(%esp), %eax
+
+; X64: _crc32_8:
+; X64: crc32 %sil, %eax
+}
+
+
+define i32 @crc32_16(i32 %a, i16 %b) nounwind {
+ %tmp = call i32 @llvm.x86.sse42.crc32.16(i32 %a, i16 %b)
+ ret i32 %tmp
+; X32: _crc32_16:
+; X32: crc32 8(%esp), %eax
+
+; X64: _crc32_16:
+; X64: crc32 %si, %eax
+}
+
+
+define i32 @crc32_32(i32 %a, i32 %b) nounwind {
+ %tmp = call i32 @llvm.x86.sse42.crc32.32(i32 %a, i32 %b)
+ ret i32 %tmp
+; X32: _crc32_32:
+; X32: crc32 8(%esp), %eax
+
+; X64: _crc32_32:
+; X64: crc32 %esi, %eax
+}
diff --git a/test/CodeGen/X86/sse_reload_fold.ll b/test/CodeGen/X86/sse_reload_fold.ll
new file mode 100644
index 0000000..dc3d6fe
--- /dev/null
+++ b/test/CodeGen/X86/sse_reload_fold.ll
@@ -0,0 +1,124 @@
+; RUN: llc < %s -march=x86-64 -mattr=+64bit,+sse3 -print-failed-fuse-candidates |& \
+; RUN: grep fail | count 1
+
+declare float @test_f(float %f)
+declare double @test_d(double %f)
+declare <4 x float> @test_vf(<4 x float> %f)
+declare <2 x double> @test_vd(<2 x double> %f)
+declare float @llvm.sqrt.f32(float)
+declare double @llvm.sqrt.f64(double)
+
+declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>)
+declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>)
+declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>)
+declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8)
+declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>)
+declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>)
+declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>)
+declare <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double>, <2 x double>, i8)
+declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>)
+declare <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double>, <2 x double>)
+declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>)
+
+define float @foo(float %f) {
+ %a = call float @test_f(float %f)
+ %t = call float @llvm.sqrt.f32(float %f)
+ ret float %t
+}
+define double @doo(double %f) {
+ %a = call double @test_d(double %f)
+ %t = call double @llvm.sqrt.f64(double %f)
+ ret double %t
+}
+define <4 x float> @a0(<4 x float> %f) {
+ %a = call <4 x float> @test_vf(<4 x float> %f)
+ %t = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %f)
+ ret <4 x float> %t
+}
+define <4 x float> @a1(<4 x float> %f) {
+ %a = call <4 x float> @test_vf(<4 x float> %f)
+ %t = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %f)
+ ret <4 x float> %t
+}
+define <4 x float> @a2(<4 x float> %f) {
+ %a = call <4 x float> @test_vf(<4 x float> %f)
+ %t = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %f)
+ ret <4 x float> %t
+}
+define <4 x float> @b3(<4 x float> %f) {
+ %y = call <4 x float> @test_vf(<4 x float> %f)
+ %t = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %y, <4 x float> %f)
+ ret <4 x float> %t
+}
+define <4 x float> @b4(<4 x float> %f) {
+ %y = call <4 x float> @test_vf(<4 x float> %f)
+ %t = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %y, <4 x float> %f)
+ ret <4 x float> %t
+}
+define <4 x float> @b5(<4 x float> %f) {
+ %y = call <4 x float> @test_vf(<4 x float> %f)
+ %t = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %y, <4 x float> %f, i8 7)
+ ret <4 x float> %t
+}
+define <4 x float> @b6(<4 x float> %f) {
+ %y = call <4 x float> @test_vf(<4 x float> %f)
+ %t = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %y, <4 x float> %f)
+ ret <4 x float> %t
+}
+define <4 x float> @b7(<4 x float> %f) {
+ %y = call <4 x float> @test_vf(<4 x float> %f)
+ %t = call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %y, <4 x float> %f)
+ ret <4 x float> %t
+}
+define <4 x float> @b8(<4 x float> %f) {
+ %y = call <4 x float> @test_vf(<4 x float> %f)
+ %t = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %y, <4 x float> %f)
+ ret <4 x float> %t
+}
+define <2 x double> @c1(<2 x double> %f) {
+ %a = call <2 x double> @test_vd(<2 x double> %f)
+ %t = call <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double> %f)
+ ret <2 x double> %t
+}
+define <2 x double> @d3(<2 x double> %f) {
+ %y = call <2 x double> @test_vd(<2 x double> %f)
+ %t = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %y, <2 x double> %f)
+ ret <2 x double> %t
+}
+define <2 x double> @d4(<2 x double> %f) {
+ %y = call <2 x double> @test_vd(<2 x double> %f)
+ %t = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %y, <2 x double> %f)
+ ret <2 x double> %t
+}
+define <2 x double> @d5(<2 x double> %f) {
+ %y = call <2 x double> @test_vd(<2 x double> %f)
+ %t = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %y, <2 x double> %f, i8 7)
+ ret <2 x double> %t
+}
+define <2 x double> @d6(<2 x double> %f) {
+ %y = call <2 x double> @test_vd(<2 x double> %f)
+ %t = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %y, <2 x double> %f)
+ ret <2 x double> %t
+}
+define <2 x double> @d7(<2 x double> %f) {
+ %y = call <2 x double> @test_vd(<2 x double> %f)
+ %t = call <2 x double> @llvm.x86.sse3.hadd.pd(<2 x double> %y, <2 x double> %f)
+ ret <2 x double> %t
+}
+define <2 x double> @d8(<2 x double> %f) {
+ %y = call <2 x double> @test_vd(<2 x double> %f)
+ %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %y, <2 x double> %f)
+ ret <2 x double> %t
+}
+
+; This one should fail to fuse.
+define <2 x double> @z0(<2 x double> %f) {
+ %y = call <2 x double> @test_vd(<2 x double> %f)
+ %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %f, <2 x double> %y)
+ ret <2 x double> %t
+}
diff --git a/test/CodeGen/X86/stack-align.ll b/test/CodeGen/X86/stack-align.ll
new file mode 100644
index 0000000..cb65e9b
--- /dev/null
+++ b/test/CodeGen/X86/stack-align.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -relocation-model=static -mcpu=yonah | grep {andpd.*4(%esp), %xmm}
+
+; The double argument is at 4(esp) which is 16-byte aligned, allowing us to
+; fold the load into the andpd.
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin8"
+@G = external global double
+
+define void @test({ double, double }* byval %z, double* %P) {
+entry:
+ %tmp = getelementptr { double, double }* %z, i32 0, i32 0 ; <double*> [#uses=1]
+ %tmp1 = load double* %tmp, align 8 ; <double> [#uses=1]
+ %tmp2 = tail call double @fabs( double %tmp1 ) ; <double> [#uses=1]
+ %tmp3 = load double* @G, align 16 ; <double> [#uses=1]
+ %tmp4 = tail call double @fabs( double %tmp3 ) ; <double> [#uses=1]
+ %tmp6 = fadd double %tmp4, %tmp2 ; <double> [#uses=1]
+ store double %tmp6, double* %P, align 8
+ ret void
+}
+
+declare double @fabs(double)
diff --git a/test/CodeGen/X86/stack-color-with-reg-2.ll b/test/CodeGen/X86/stack-color-with-reg-2.ll
new file mode 100644
index 0000000..c1f2672
--- /dev/null
+++ b/test/CodeGen/X86/stack-color-with-reg-2.ll
@@ -0,0 +1,230 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs | grep {movl\[\[:space:\]\]%eax, %ebx}
+
+ %"struct..0$_67" = type { i32, %"struct.llvm::MachineOperand"**, %"struct.llvm::MachineOperand"* }
+ %"struct..1$_69" = type { i32 }
+ %"struct.llvm::AbstractTypeUser" = type { i32 (...)** }
+ %"struct.llvm::AliasAnalysis" = type opaque
+ %"struct.llvm::AnalysisResolver" = type { %"struct.std::vector<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >", %"struct.llvm::PMDataManager"* }
+ %"struct.llvm::Annotable" = type { %"struct.llvm::Annotation"* }
+ %"struct.llvm::Annotation" = type { i32 (...)**, %"struct..1$_69", %"struct.llvm::Annotation"* }
+ %"struct.llvm::Argument" = type { %"struct.llvm::Value", %"struct.llvm::ilist_node<llvm::Argument>", %"struct.llvm::Function"* }
+ %"struct.llvm::AttrListPtr" = type { %"struct.llvm::AttributeListImpl"* }
+ %"struct.llvm::AttributeListImpl" = type opaque
+ %"struct.llvm::BasicBlock" = type { %"struct.llvm::Value", %"struct.llvm::ilist_node<llvm::BasicBlock>", %"struct.llvm::iplist<llvm::Instruction,llvm::ilist_traits<llvm::Instruction> >", %"struct.llvm::Function"* }
+ %"struct.llvm::BitVector" = type { i32*, i32, i32 }
+ %"struct.llvm::BumpPtrAllocator" = type { i8* }
+ %"struct.llvm::CalleeSavedInfo" = type { i32, %"struct.llvm::TargetRegisterClass"*, i32 }
+ %"struct.llvm::Constant" = type { %"struct.llvm::User" }
+ %"struct.llvm::DebugLocTracker" = type { %"struct.std::vector<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >", %"struct.llvm::DenseMap<llvm::DebugLocTuple,unsigned int,llvm::DenseMapInfo<llvm::DebugLocTuple>,llvm::DenseMapInfo<unsigned int> >" }
+ %"struct.llvm::DebugLocTuple" = type { %"struct.llvm::GlobalVariable"*, i32, i32 }
+ %"struct.llvm::DenseMap<llvm::DebugLocTuple,unsigned int,llvm::DenseMapInfo<llvm::DebugLocTuple>,llvm::DenseMapInfo<unsigned int> >" = type { i32, %"struct.std::pair<llvm::DebugLocTuple,unsigned int>"*, i32, i32 }
+ %"struct.llvm::DenseMap<llvm::MachineInstr*,unsigned int,llvm::DenseMapInfo<llvm::MachineInstr*>,llvm::DenseMapInfo<unsigned int> >" = type { i32, %"struct.std::pair<llvm::MachineInstr*,unsigned int>"*, i32, i32 }
+ %"struct.llvm::DenseMap<unsigned int,char,llvm::DenseMapInfo<unsigned int>,llvm::DenseMapInfo<char> >" = type { i32, %"struct.std::pair<unsigned int,char>"*, i32, i32 }
+ %"struct.llvm::DenseMap<unsigned int,llvm::LiveInterval*,llvm::DenseMapInfo<unsigned int>,llvm::DenseMapInfo<llvm::LiveInterval*> >" = type { i32, %"struct.std::pair<unsigned int,llvm::LiveInterval*>"*, i32, i32 }
+ %"struct.llvm::DenseSet<unsigned int,llvm::DenseMapInfo<unsigned int> >" = type { %"struct.llvm::DenseMap<unsigned int,char,llvm::DenseMapInfo<unsigned int>,llvm::DenseMapInfo<char> >" }
+ %"struct.llvm::Function" = type { %"struct.llvm::GlobalValue", %"struct.llvm::Annotable", %"struct.llvm::ilist_node<llvm::Function>", %"struct.llvm::iplist<llvm::BasicBlock,llvm::ilist_traits<llvm::BasicBlock> >", %"struct.llvm::iplist<llvm::Argument,llvm::ilist_traits<llvm::Argument> >", %"struct.llvm::ValueSymbolTable"*, %"struct.llvm::AttrListPtr" }
+ %"struct.llvm::FunctionPass" = type { %"struct.llvm::Pass" }
+ %"struct.llvm::GlobalValue" = type { %"struct.llvm::Constant", %"struct.llvm::Module"*, i32, %"struct.std::string" }
+ %"struct.llvm::GlobalVariable" = type opaque
+ %"struct.llvm::Instruction" = type { %"struct.llvm::User", %"struct.llvm::ilist_node<llvm::Instruction>", %"struct.llvm::BasicBlock"* }
+ %"struct.llvm::LiveInterval" = type <{ i32, float, i16, [6 x i8], %"struct.llvm::SmallVector<llvm::LiveRange,4u>", %"struct.llvm::SmallVector<llvm::MachineBasicBlock*,4u>" }>
+ %"struct.llvm::LiveIntervals" = type { %"struct.llvm::MachineFunctionPass", %"struct.llvm::MachineFunction"*, %"struct.llvm::MachineRegisterInfo"*, %"struct.llvm::TargetMachine"*, %"struct.llvm::TargetRegisterInfo"*, %"struct.llvm::TargetInstrInfo"*, %"struct.llvm::AliasAnalysis"*, %"struct.llvm::LiveVariables"*, %"struct.llvm::BumpPtrAllocator", %"struct.std::vector<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >", %"struct.std::vector<std::pair<unsigned int, llvm::MachineBasicBlock*>,std::allocator<std::pair<unsigned int, llvm::MachineBasicBlock*> > >", i64, %"struct.llvm::DenseMap<llvm::MachineInstr*,unsigned int,llvm::DenseMapInfo<llvm::MachineInstr*>,llvm::DenseMapInfo<unsigned int> >", %"struct.std::vector<llvm::MachineInstr*,std::allocator<llvm::MachineInstr*> >", %"struct.llvm::DenseMap<unsigned int,llvm::LiveInterval*,llvm::DenseMapInfo<unsigned int>,llvm::DenseMapInfo<llvm::LiveInterval*> >", %"struct.llvm::BitVector", %"struct.std::vector<llvm::MachineInstr*,std::allocator<llvm::MachineInstr*> >" }
+ %"struct.llvm::LiveVariables" = type opaque
+ %"struct.llvm::MVT" = type { %"struct..1$_69" }
+ %"struct.llvm::MachineBasicBlock" = type { %"struct.llvm::ilist_node<llvm::MachineBasicBlock>", %"struct.llvm::ilist<llvm::MachineInstr>", %"struct.llvm::BasicBlock"*, i32, %"struct.llvm::MachineFunction"*, %"struct.std::vector<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >", %"struct.std::vector<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >", %"struct.std::vector<int,std::allocator<int> >", i32, i8 }
+ %"struct.llvm::MachineConstantPool" = type opaque
+ %"struct.llvm::MachineFrameInfo" = type { %"struct.std::vector<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >", i32, i8, i8, i64, i32, i32, i8, i32, i32, %"struct.std::vector<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >", %"struct.llvm::MachineModuleInfo"*, %"struct.llvm::TargetFrameInfo"* }
+ %"struct.llvm::MachineFrameInfo::StackObject" = type { i64, i32, i8, i64 }
+ %"struct.llvm::MachineFunction" = type { %"struct.llvm::Annotation", %"struct.llvm::Function"*, %"struct.llvm::TargetMachine"*, %"struct.llvm::MachineRegisterInfo"*, %"struct.llvm::AbstractTypeUser"*, %"struct.llvm::MachineFrameInfo"*, %"struct.llvm::MachineConstantPool"*, %"struct.llvm::MachineJumpTableInfo"*, %"struct.std::vector<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >", %"struct.llvm::BumpPtrAllocator", %"struct.llvm::Recycler<llvm::MachineBasicBlock,80ul,4ul>", %"struct.llvm::Recycler<llvm::MachineBasicBlock,80ul,4ul>", %"struct.llvm::ilist<llvm::MachineBasicBlock>", %"struct..1$_69", %"struct.llvm::DebugLocTracker" }
+ %"struct.llvm::MachineFunctionPass" = type { %"struct.llvm::FunctionPass" }
+ %"struct.llvm::MachineInstr" = type { %"struct.llvm::ilist_node<llvm::MachineInstr>", %"struct.llvm::TargetInstrDesc"*, i16, %"struct.std::vector<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >", %"struct.std::list<llvm::MachineMemOperand,std::allocator<llvm::MachineMemOperand> >", %"struct.llvm::MachineBasicBlock"*, %"struct..1$_69" }
+ %"struct.llvm::MachineJumpTableInfo" = type opaque
+ %"struct.llvm::MachineModuleInfo" = type opaque
+ %"struct.llvm::MachineOperand" = type { i8, i8, i8, %"struct.llvm::MachineInstr"*, %"struct.llvm::MachineOperand::$_66" }
+ %"struct.llvm::MachineOperand::$_66" = type { %"struct..0$_67" }
+ %"struct.llvm::MachineRegisterInfo" = type { %"struct.std::vector<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >", %"struct.std::vector<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >", %"struct.llvm::MachineOperand"**, %"struct.llvm::BitVector", %"struct.std::vector<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >", %"struct.std::vector<int,std::allocator<int> >" }
+ %"struct.llvm::Module" = type opaque
+ %"struct.llvm::PATypeHandle" = type { %"struct.llvm::Type"*, %"struct.llvm::AbstractTypeUser"* }
+ %"struct.llvm::PATypeHolder" = type { %"struct.llvm::Type"* }
+ %"struct.llvm::PMDataManager" = type opaque
+ %"struct.llvm::Pass" = type { i32 (...)**, %"struct.llvm::AnalysisResolver"*, i32 }
+ %"struct.llvm::PassInfo" = type { i8*, i8*, i32, i8, i8, i8, %"struct.std::vector<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >", %"struct.llvm::Pass"* ()* }
+ %"struct.llvm::Recycler<llvm::MachineBasicBlock,80ul,4ul>" = type { %"struct.llvm::iplist<llvm::RecyclerStruct,llvm::ilist_traits<llvm::RecyclerStruct> >" }
+ %"struct.llvm::RecyclerStruct" = type { %"struct.llvm::RecyclerStruct"*, %"struct.llvm::RecyclerStruct"* }
+ %"struct.llvm::SmallVector<llvm::LiveRange,4u>" = type <{ [17 x i8], [47 x i8] }>
+ %"struct.llvm::SmallVector<llvm::MachineBasicBlock*,4u>" = type <{ [17 x i8], [15 x i8] }>
+ %"struct.llvm::TargetAsmInfo" = type opaque
+ %"struct.llvm::TargetFrameInfo" = type opaque
+ %"struct.llvm::TargetInstrDesc" = type { i16, i16, i16, i16, i8*, i32, i32, i32*, i32*, %"struct.llvm::TargetRegisterClass"**, %"struct.llvm::TargetOperandInfo"* }
+ %"struct.llvm::TargetInstrInfo" = type { i32 (...)**, %"struct.llvm::TargetInstrDesc"*, i32 }
+ %"struct.llvm::TargetMachine" = type { i32 (...)**, %"struct.llvm::TargetAsmInfo"* }
+ %"struct.llvm::TargetOperandInfo" = type { i16, i16, i32 }
+ %"struct.llvm::TargetRegisterClass" = type { i32 (...)**, i32, i8*, %"struct.llvm::MVT"*, %"struct.llvm::TargetRegisterClass"**, %"struct.llvm::TargetRegisterClass"**, %"struct.llvm::TargetRegisterClass"**, %"struct.llvm::TargetRegisterClass"**, i32, i32, i32, i32*, i32*, %"struct.llvm::DenseSet<unsigned int,llvm::DenseMapInfo<unsigned int> >" }
+ %"struct.llvm::TargetRegisterDesc" = type { i8*, i8*, i32*, i32*, i32* }
+ %"struct.llvm::TargetRegisterInfo" = type { i32 (...)**, i32*, i32, i32*, i32, i32*, i32, %"struct.llvm::TargetRegisterDesc"*, i32, %"struct.llvm::TargetRegisterClass"**, %"struct.llvm::TargetRegisterClass"**, i32, i32 }
+ %"struct.llvm::Type" = type { %"struct.llvm::AbstractTypeUser", i8, [3 x i8], i32, %"struct.llvm::Type"*, %"struct.std::vector<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >", i32, %"struct.llvm::PATypeHandle"* }
+ %"struct.llvm::Use" = type { %"struct.llvm::Value"*, %"struct.llvm::Use"*, %"struct..1$_69" }
+ %"struct.llvm::User" = type { %"struct.llvm::Value", %"struct.llvm::Use"*, i32 }
+ %"struct.llvm::Value" = type { i32 (...)**, i8, i8, i16, %"struct.llvm::PATypeHolder", %"struct.llvm::Use"*, %"struct.llvm::ValueName"* }
+ %"struct.llvm::ValueName" = type opaque
+ %"struct.llvm::ValueSymbolTable" = type opaque
+ %"struct.llvm::ilist<llvm::MachineBasicBlock>" = type { %"struct.llvm::iplist<llvm::MachineBasicBlock,llvm::ilist_traits<llvm::MachineBasicBlock> >" }
+ %"struct.llvm::ilist<llvm::MachineInstr>" = type { %"struct.llvm::iplist<llvm::MachineInstr,llvm::ilist_traits<llvm::MachineInstr> >" }
+ %"struct.llvm::ilist_node<llvm::Argument>" = type { %"struct.llvm::Argument"*, %"struct.llvm::Argument"* }
+ %"struct.llvm::ilist_node<llvm::BasicBlock>" = type { %"struct.llvm::BasicBlock"*, %"struct.llvm::BasicBlock"* }
+ %"struct.llvm::ilist_node<llvm::Function>" = type { %"struct.llvm::Function"*, %"struct.llvm::Function"* }
+ %"struct.llvm::ilist_node<llvm::Instruction>" = type { %"struct.llvm::Instruction"*, %"struct.llvm::Instruction"* }
+ %"struct.llvm::ilist_node<llvm::MachineBasicBlock>" = type { %"struct.llvm::MachineBasicBlock"*, %"struct.llvm::MachineBasicBlock"* }
+ %"struct.llvm::ilist_node<llvm::MachineInstr>" = type { %"struct.llvm::MachineInstr"*, %"struct.llvm::MachineInstr"* }
+ %"struct.llvm::ilist_traits<llvm::Argument>" = type { %"struct.llvm::ilist_node<llvm::Argument>" }
+ %"struct.llvm::ilist_traits<llvm::BasicBlock>" = type { %"struct.llvm::ilist_node<llvm::BasicBlock>" }
+ %"struct.llvm::ilist_traits<llvm::Instruction>" = type { %"struct.llvm::ilist_node<llvm::Instruction>" }
+ %"struct.llvm::ilist_traits<llvm::MachineBasicBlock>" = type { %"struct.llvm::ilist_node<llvm::MachineBasicBlock>" }
+ %"struct.llvm::ilist_traits<llvm::MachineInstr>" = type { %"struct.llvm::ilist_node<llvm::MachineInstr>", %"struct.llvm::MachineBasicBlock"* }
+ %"struct.llvm::ilist_traits<llvm::RecyclerStruct>" = type { %"struct.llvm::RecyclerStruct" }
+ %"struct.llvm::iplist<llvm::Argument,llvm::ilist_traits<llvm::Argument> >" = type { %"struct.llvm::ilist_traits<llvm::Argument>", %"struct.llvm::Argument"* }
+ %"struct.llvm::iplist<llvm::BasicBlock,llvm::ilist_traits<llvm::BasicBlock> >" = type { %"struct.llvm::ilist_traits<llvm::BasicBlock>", %"struct.llvm::BasicBlock"* }
+ %"struct.llvm::iplist<llvm::Instruction,llvm::ilist_traits<llvm::Instruction> >" = type { %"struct.llvm::ilist_traits<llvm::Instruction>", %"struct.llvm::Instruction"* }
+ %"struct.llvm::iplist<llvm::MachineBasicBlock,llvm::ilist_traits<llvm::MachineBasicBlock> >" = type { %"struct.llvm::ilist_traits<llvm::MachineBasicBlock>", %"struct.llvm::MachineBasicBlock"* }
+ %"struct.llvm::iplist<llvm::MachineInstr,llvm::ilist_traits<llvm::MachineInstr> >" = type { %"struct.llvm::ilist_traits<llvm::MachineInstr>", %"struct.llvm::MachineInstr"* }
+ %"struct.llvm::iplist<llvm::RecyclerStruct,llvm::ilist_traits<llvm::RecyclerStruct> >" = type { %"struct.llvm::ilist_traits<llvm::RecyclerStruct>", %"struct.llvm::RecyclerStruct"* }
+ %"struct.std::IdxMBBPair" = type { i32, %"struct.llvm::MachineBasicBlock"* }
+ %"struct.std::_List_base<llvm::MachineMemOperand,std::allocator<llvm::MachineMemOperand> >" = type { %"struct.llvm::ilist_traits<llvm::RecyclerStruct>" }
+ %"struct.std::_Vector_base<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >" = type { %"struct.std::_Vector_base<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >::_Vector_impl" }
+ %"struct.std::_Vector_base<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >::_Vector_impl" = type { %"struct.llvm::PassInfo"**, %"struct.llvm::PassInfo"**, %"struct.llvm::PassInfo"** }
+ %"struct.std::_Vector_base<int,std::allocator<int> >" = type { %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl" }
+ %"struct.std::_Vector_base<int,std::allocator<int> >::_Vector_impl" = type { i32*, i32*, i32* }
+ %"struct.std::_Vector_base<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >" = type { %"struct.std::_Vector_base<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >::_Vector_impl" }
+ %"struct.std::_Vector_base<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >::_Vector_impl" = type { %"struct.llvm::AbstractTypeUser"**, %"struct.llvm::AbstractTypeUser"**, %"struct.llvm::AbstractTypeUser"** }
+ %"struct.std::_Vector_base<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >" = type { %"struct.std::_Vector_base<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >::_Vector_impl" }
+ %"struct.std::_Vector_base<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >::_Vector_impl" = type { %"struct.llvm::CalleeSavedInfo"*, %"struct.llvm::CalleeSavedInfo"*, %"struct.llvm::CalleeSavedInfo"* }
+ %"struct.std::_Vector_base<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >" = type { %"struct.std::_Vector_base<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >::_Vector_impl" }
+ %"struct.std::_Vector_base<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >::_Vector_impl" = type { %"struct.llvm::DebugLocTuple"*, %"struct.llvm::DebugLocTuple"*, %"struct.llvm::DebugLocTuple"* }
+ %"struct.std::_Vector_base<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >" = type { %"struct.std::_Vector_base<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >::_Vector_impl" }
+ %"struct.std::_Vector_base<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >::_Vector_impl" = type { %"struct.llvm::MachineBasicBlock"**, %"struct.llvm::MachineBasicBlock"**, %"struct.llvm::MachineBasicBlock"** }
+ %"struct.std::_Vector_base<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >" = type { %"struct.std::_Vector_base<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >::_Vector_impl" }
+ %"struct.std::_Vector_base<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >::_Vector_impl" = type { %"struct.llvm::MachineFrameInfo::StackObject"*, %"struct.llvm::MachineFrameInfo::StackObject"*, %"struct.llvm::MachineFrameInfo::StackObject"* }
+ %"struct.std::_Vector_base<llvm::MachineInstr*,std::allocator<llvm::MachineInstr*> >" = type { %"struct.std::_Vector_base<llvm::MachineInstr*,std::allocator<llvm::MachineInstr*> >::_Vector_impl" }
+ %"struct.std::_Vector_base<llvm::MachineInstr*,std::allocator<llvm::MachineInstr*> >::_Vector_impl" = type { %"struct.llvm::MachineInstr"**, %"struct.llvm::MachineInstr"**, %"struct.llvm::MachineInstr"** }
+ %"struct.std::_Vector_base<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >" = type { %"struct.std::_Vector_base<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >::_Vector_impl" }
+ %"struct.std::_Vector_base<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >::_Vector_impl" = type { %"struct.llvm::MachineOperand"*, %"struct.llvm::MachineOperand"*, %"struct.llvm::MachineOperand"* }
+ %"struct.std::_Vector_base<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >" = type { %"struct.std::_Vector_base<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >::_Vector_impl" }
+ %"struct.std::_Vector_base<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >::_Vector_impl" = type { %"struct.std::pair<const llvm::PassInfo*,llvm::Pass*>"*, %"struct.std::pair<const llvm::PassInfo*,llvm::Pass*>"*, %"struct.std::pair<const llvm::PassInfo*,llvm::Pass*>"* }
+ %"struct.std::_Vector_base<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >" = type { %"struct.std::_Vector_base<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >::_Vector_impl" }
+ %"struct.std::_Vector_base<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >::_Vector_impl" = type { %"struct.std::pair<const llvm::TargetRegisterClass*,llvm::MachineOperand*>"*, %"struct.std::pair<const llvm::TargetRegisterClass*,llvm::MachineOperand*>"*, %"struct.std::pair<const llvm::TargetRegisterClass*,llvm::MachineOperand*>"* }
+ %"struct.std::_Vector_base<std::pair<unsigned int, llvm::MachineBasicBlock*>,std::allocator<std::pair<unsigned int, llvm::MachineBasicBlock*> > >" = type { %"struct.std::_Vector_base<std::pair<unsigned int, llvm::MachineBasicBlock*>,std::allocator<std::pair<unsigned int, llvm::MachineBasicBlock*> > >::_Vector_impl" }
+ %"struct.std::_Vector_base<std::pair<unsigned int, llvm::MachineBasicBlock*>,std::allocator<std::pair<unsigned int, llvm::MachineBasicBlock*> > >::_Vector_impl" = type { %"struct.std::IdxMBBPair"*, %"struct.std::IdxMBBPair"*, %"struct.std::IdxMBBPair"* }
+ %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >" = type { %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >::_Vector_impl" }
+ %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >::_Vector_impl" = type { %"struct.std::pair<unsigned int,int>"*, %"struct.std::pair<unsigned int,int>"*, %"struct.std::pair<unsigned int,int>"* }
+ %"struct.std::_Vector_base<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >" = type { %"struct.std::_Vector_base<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >::_Vector_impl" }
+ %"struct.std::_Vector_base<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >::_Vector_impl" = type { %"struct.std::vector<int,std::allocator<int> >"*, %"struct.std::vector<int,std::allocator<int> >"*, %"struct.std::vector<int,std::allocator<int> >"* }
+ %"struct.std::list<llvm::MachineMemOperand,std::allocator<llvm::MachineMemOperand> >" = type { %"struct.std::_List_base<llvm::MachineMemOperand,std::allocator<llvm::MachineMemOperand> >" }
+ %"struct.std::pair<const llvm::PassInfo*,llvm::Pass*>" = type { %"struct.llvm::PassInfo"*, %"struct.llvm::Pass"* }
+ %"struct.std::pair<const llvm::TargetRegisterClass*,llvm::MachineOperand*>" = type { %"struct.llvm::TargetRegisterClass"*, %"struct.llvm::MachineOperand"* }
+ %"struct.std::pair<llvm::DebugLocTuple,unsigned int>" = type { %"struct.llvm::DebugLocTuple", i32 }
+ %"struct.std::pair<llvm::MachineInstr*,unsigned int>" = type { %"struct.llvm::MachineInstr"*, i32 }
+ %"struct.std::pair<unsigned int,char>" = type { i32, i8 }
+ %"struct.std::pair<unsigned int,int>" = type { i32, i32 }
+ %"struct.std::pair<unsigned int,llvm::LiveInterval*>" = type { i32, %"struct.llvm::LiveInterval"* }
+ %"struct.std::string" = type { %"struct.llvm::BumpPtrAllocator" }
+ %"struct.std::vector<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >" = type { %"struct.std::_Vector_base<const llvm::PassInfo*,std::allocator<const llvm::PassInfo*> >" }
+ %"struct.std::vector<int,std::allocator<int> >" = type { %"struct.std::_Vector_base<int,std::allocator<int> >" }
+ %"struct.std::vector<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >" = type { %"struct.std::_Vector_base<llvm::AbstractTypeUser*,std::allocator<llvm::AbstractTypeUser*> >" }
+ %"struct.std::vector<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >" = type { %"struct.std::_Vector_base<llvm::CalleeSavedInfo,std::allocator<llvm::CalleeSavedInfo> >" }
+ %"struct.std::vector<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >" = type { %"struct.std::_Vector_base<llvm::DebugLocTuple,std::allocator<llvm::DebugLocTuple> >" }
+ %"struct.std::vector<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >" = type { %"struct.std::_Vector_base<llvm::MachineBasicBlock*,std::allocator<llvm::MachineBasicBlock*> >" }
+ %"struct.std::vector<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >" = type { %"struct.std::_Vector_base<llvm::MachineFrameInfo::StackObject,std::allocator<llvm::MachineFrameInfo::StackObject> >" }
+ %"struct.std::vector<llvm::MachineInstr*,std::allocator<llvm::MachineInstr*> >" = type { %"struct.std::_Vector_base<llvm::MachineInstr*,std::allocator<llvm::MachineInstr*> >" }
+ %"struct.std::vector<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >" = type { %"struct.std::_Vector_base<llvm::MachineOperand,std::allocator<llvm::MachineOperand> >" }
+ %"struct.std::vector<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >" = type { %"struct.std::_Vector_base<std::pair<const llvm::PassInfo*, llvm::Pass*>,std::allocator<std::pair<const llvm::PassInfo*, llvm::Pass*> > >" }
+ %"struct.std::vector<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >" = type { %"struct.std::_Vector_base<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*>,std::allocator<std::pair<const llvm::TargetRegisterClass*, llvm::MachineOperand*> > >" }
+ %"struct.std::vector<std::pair<unsigned int, llvm::MachineBasicBlock*>,std::allocator<std::pair<unsigned int, llvm::MachineBasicBlock*> > >" = type { %"struct.std::_Vector_base<std::pair<unsigned int, llvm::MachineBasicBlock*>,std::allocator<std::pair<unsigned int, llvm::MachineBasicBlock*> > >" }
+ %"struct.std::vector<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >" = type { %"struct.std::_Vector_base<std::pair<unsigned int, unsigned int>,std::allocator<std::pair<unsigned int, unsigned int> > >" }
+ %"struct.std::vector<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >" = type { %"struct.std::_Vector_base<std::vector<unsigned int, std::allocator<unsigned int> >,std::allocator<std::vector<unsigned int, std::allocator<unsigned int> > > >" }
+@_ZZNK4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE15LookupBucketForERKS2_RPSt4pairIS2_jEE8__func__ = external constant [16 x i8] ; <[16 x i8]*> [#uses=1]
+@"\01LC6" = external constant [56 x i8] ; <[56 x i8]*> [#uses=1]
+@"\01LC7" = external constant [134 x i8] ; <[134 x i8]*> [#uses=1]
+@"\01LC8" = external constant [72 x i8] ; <[72 x i8]*> [#uses=1]
+@_ZZN4llvm13LiveIntervals24InsertMachineInstrInMapsEPNS_12MachineInstrEjE8__func__ = external constant [25 x i8] ; <[25 x i8]*> [#uses=1]
+@"\01LC51" = external constant [42 x i8] ; <[42 x i8]*> [#uses=1]
+
+define void @_ZN4llvm13LiveIntervals24InsertMachineInstrInMapsEPNS_12MachineInstrEj(%"struct.llvm::LiveIntervals"* nocapture %this, %"struct.llvm::MachineInstr"* %MI, i32 %Index) nounwind ssp {
+entry:
+ %0 = call i64 @_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE4findERKS2_(%"struct.llvm::DenseMap<llvm::MachineInstr*,unsigned int,llvm::DenseMapInfo<llvm::MachineInstr*>,llvm::DenseMapInfo<unsigned int> >"* null, %"struct.llvm::MachineInstr"** null) nounwind ssp ; <i64> [#uses=1]
+ %1 = trunc i64 %0 to i32 ; <i32> [#uses=1]
+ %tmp11 = inttoptr i32 %1 to %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* ; <%"struct.std::pair<llvm::MachineInstr*,unsigned int>"*> [#uses=1]
+ %2 = load %"struct.std::pair<llvm::MachineInstr*,unsigned int>"** null, align 4 ; <%"struct.std::pair<llvm::MachineInstr*,unsigned int>"*> [#uses=3]
+ %3 = getelementptr %"struct.llvm::LiveIntervals"* %this, i32 0, i32 12, i32 0 ; <i32*> [#uses=1]
+ %4 = load i32* %3, align 4 ; <i32> [#uses=2]
+ %5 = getelementptr %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %2, i32 %4 ; <%"struct.std::pair<llvm::MachineInstr*,unsigned int>"*> [#uses=1]
+ br label %bb1.i.i.i
+
+bb.i.i.i: ; preds = %bb2.i.i.i
+ %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
+ br label %bb1.i.i.i
+
+bb1.i.i.i: ; preds = %bb.i.i.i, %entry
+ %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb.i.i.i ] ; <i32> [#uses=2]
+ %tmp32 = shl i32 %indvar, 3 ; <i32> [#uses=1]
+ %ctg2.sum = add i32 0, %tmp32 ; <i32> [#uses=1]
+ %ctg237 = getelementptr i8* null, i32 %ctg2.sum ; <i8*> [#uses=1]
+ %.0.0.i = bitcast i8* %ctg237 to %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* ; <%"struct.std::pair<llvm::MachineInstr*,unsigned int>"*> [#uses=2]
+ %6 = icmp eq %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %.0.0.i, %5 ; <i1> [#uses=1]
+ br i1 %6, label %_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE3endEv.exit, label %bb2.i.i.i
+
+bb2.i.i.i: ; preds = %bb1.i.i.i
+ %7 = load %"struct.llvm::MachineInstr"** null, align 4 ; <%"struct.llvm::MachineInstr"*> [#uses=1]
+ %8 = icmp eq %"struct.llvm::MachineInstr"* %7, inttoptr (i32 -8 to %"struct.llvm::MachineInstr"*) ; <i1> [#uses=1]
+ %or.cond.i.i.i21 = or i1 false, %8 ; <i1> [#uses=1]
+ br i1 %or.cond.i.i.i21, label %bb.i.i.i, label %_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE3endEv.exit
+
+_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE3endEv.exit: ; preds = %bb2.i.i.i, %bb1.i.i.i
+ %9 = icmp eq %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %tmp11, %.0.0.i ; <i1> [#uses=1]
+ br i1 %9, label %bb7, label %bb6
+
+bb6: ; preds = %_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE3endEv.exit
+ call void @__assert_rtn(i8* getelementptr ([25 x i8]* @_ZZN4llvm13LiveIntervals24InsertMachineInstrInMapsEPNS_12MachineInstrEjE8__func__, i32 0, i32 0), i8* getelementptr ([72 x i8]* @"\01LC8", i32 0, i32 0), i32 251, i8* getelementptr ([42 x i8]* @"\01LC51", i32 0, i32 0)) noreturn nounwind
+ unreachable
+
+bb7: ; preds = %_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE3endEv.exit
+ %10 = load %"struct.llvm::MachineInstr"** null, align 4 ; <%"struct.llvm::MachineInstr"*> [#uses=2]
+ %11 = icmp eq %"struct.llvm::MachineInstr"* %10, inttoptr (i32 -8 to %"struct.llvm::MachineInstr"*) ; <i1> [#uses=1]
+ %or.cond40.i.i.i = or i1 false, %11 ; <i1> [#uses=1]
+ br i1 %or.cond40.i.i.i, label %bb5.i.i.i, label %bb6.preheader.i.i.i
+
+bb6.preheader.i.i.i: ; preds = %bb7
+ %12 = add i32 %4, -1 ; <i32> [#uses=1]
+ br label %bb6.i.i.i
+
+bb5.i.i.i: ; preds = %bb7
+ call void @__assert_rtn(i8* getelementptr ([16 x i8]* @_ZZNK4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE15LookupBucketForERKS2_RPSt4pairIS2_jEE8__func__, i32 0, i32 0), i8* getelementptr ([56 x i8]* @"\01LC6", i32 0, i32 0), i32 390, i8* getelementptr ([134 x i8]* @"\01LC7", i32 0, i32 0)) noreturn nounwind
+ unreachable
+
+bb6.i.i.i: ; preds = %bb17.i.i.i, %bb6.preheader.i.i.i
+ %FoundTombstone.1.i.i.i = phi %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* [ %FoundTombstone.0.i.i.i, %bb17.i.i.i ], [ null, %bb6.preheader.i.i.i ] ; <%"struct.std::pair<llvm::MachineInstr*,unsigned int>"*> [#uses=2]
+ %ProbeAmt.0.i.i.i = phi i32 [ 0, %bb17.i.i.i ], [ 1, %bb6.preheader.i.i.i ] ; <i32> [#uses=1]
+ %BucketNo.0.i.i.i = phi i32 [ %20, %bb17.i.i.i ], [ 0, %bb6.preheader.i.i.i ] ; <i32> [#uses=2]
+ %13 = and i32 %BucketNo.0.i.i.i, %12 ; <i32> [#uses=2]
+ %14 = getelementptr %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %2, i32 %13 ; <%"struct.std::pair<llvm::MachineInstr*,unsigned int>"*> [#uses=2]
+ %15 = getelementptr %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %2, i32 %13, i32 0 ; <%"struct.llvm::MachineInstr"**> [#uses=1]
+ %16 = load %"struct.llvm::MachineInstr"** %15, align 4 ; <%"struct.llvm::MachineInstr"*> [#uses=2]
+ %17 = icmp eq %"struct.llvm::MachineInstr"* %16, %10 ; <i1> [#uses=1]
+ br i1 %17, label %_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEEixERKS2_.exit, label %bb17.i.i.i
+
+bb17.i.i.i: ; preds = %bb6.i.i.i
+ %18 = icmp eq %"struct.llvm::MachineInstr"* %16, inttoptr (i32 -8 to %"struct.llvm::MachineInstr"*) ; <i1> [#uses=1]
+ %19 = icmp eq %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %FoundTombstone.1.i.i.i, null ; <i1> [#uses=1]
+ %or.cond.i.i.i = and i1 %18, %19 ; <i1> [#uses=1]
+ %FoundTombstone.0.i.i.i = select i1 %or.cond.i.i.i, %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %14, %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %FoundTombstone.1.i.i.i ; <%"struct.std::pair<llvm::MachineInstr*,unsigned int>"*> [#uses=1]
+ %20 = add i32 %BucketNo.0.i.i.i, %ProbeAmt.0.i.i.i ; <i32> [#uses=1]
+ br label %bb6.i.i.i
+
+_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEEixERKS2_.exit: ; preds = %bb6.i.i.i
+ %21 = getelementptr %"struct.std::pair<llvm::MachineInstr*,unsigned int>"* %14, i32 0, i32 1 ; <i32*> [#uses=1]
+ store i32 %Index, i32* %21, align 4
+ ret void
+}
+
+declare void @__assert_rtn(i8*, i8*, i32, i8*) noreturn
+
+declare i64 @_ZN4llvm8DenseMapIPNS_12MachineInstrEjNS_12DenseMapInfoIS2_EENS3_IjEEE4findERKS2_(%"struct.llvm::DenseMap<llvm::MachineInstr*,unsigned int,llvm::DenseMapInfo<llvm::MachineInstr*>,llvm::DenseMapInfo<unsigned int> >"* nocapture, %"struct.llvm::MachineInstr"** nocapture) nounwind ssp
diff --git a/test/CodeGen/X86/stack-color-with-reg.ll b/test/CodeGen/X86/stack-color-with-reg.ll
new file mode 100644
index 0000000..7d85818
--- /dev/null
+++ b/test/CodeGen/X86/stack-color-with-reg.ll
@@ -0,0 +1,360 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t
+; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 14
+
+ type { [62 x %struct.Bitvec*] } ; type %0
+ type { i8* } ; type %1
+ type { double } ; type %2
+ %struct..5sPragmaType = type { i8*, i32 }
+ %struct.AggInfo = type { i8, i8, i32, %struct.ExprList*, i32, %struct.AggInfo_col*, i32, i32, i32, %struct.AggInfo_func*, i32, i32 }
+ %struct.AggInfo_col = type { %struct.Table*, i32, i32, i32, i32, %struct.Expr* }
+ %struct.AggInfo_func = type { %struct.Expr*, %struct.FuncDef*, i32, i32 }
+ %struct.AuxData = type { i8*, void (i8*)* }
+ %struct.Bitvec = type { i32, i32, i32, %0 }
+ %struct.BtCursor = type { %struct.Btree*, %struct.BtShared*, %struct.BtCursor*, %struct.BtCursor*, i32 (i8*, i32, i8*, i32, i8*)*, i8*, i32, %struct.MemPage*, i32, %struct.CellInfo, i8, i8, i8*, i64, i32, i8, i32* }
+ %struct.BtLock = type { %struct.Btree*, i32, i8, %struct.BtLock* }
+ %struct.BtShared = type { %struct.Pager*, %struct.sqlite3*, %struct.BtCursor*, %struct.MemPage*, i8, i8, i8, i8, i8, i8, i8, i8, i32, i16, i16, i32, i32, i32, i32, i8, i32, i8*, void (i8*)*, %struct.sqlite3_mutex*, %struct.BusyHandler, i32, %struct.BtShared*, %struct.BtLock*, %struct.Btree* }
+ %struct.Btree = type { %struct.sqlite3*, %struct.BtShared*, i8, i8, i8, i32, %struct.Btree*, %struct.Btree* }
+ %struct.BtreeMutexArray = type { i32, [11 x %struct.Btree*] }
+ %struct.BusyHandler = type { i32 (i8*, i32)*, i8*, i32 }
+ %struct.CellInfo = type { i8*, i64, i32, i32, i16, i16, i16, i16 }
+ %struct.CollSeq = type { i8*, i8, i8, i8*, i32 (i8*, i32, i8*, i32, i8*)*, void (i8*)* }
+ %struct.Column = type { i8*, %struct.Expr*, i8*, i8*, i8, i8, i8, i8 }
+ %struct.Context = type { i64, i32, %struct.Fifo }
+ %struct.CountCtx = type { i64 }
+ %struct.Cursor = type { %struct.BtCursor*, i32, i64, i64, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i64, %struct.Btree*, i32, i8*, i64, i8*, %struct.KeyInfo*, i32, i64, %struct.sqlite3_vtab_cursor*, %struct.sqlite3_module*, i32, i32, i32*, i32*, i8* }
+ %struct.Db = type { i8*, %struct.Btree*, i8, i8, i8*, void (i8*)*, %struct.Schema* }
+ %struct.DbPage = type { %struct.Pager*, i32, %struct.DbPage*, %struct.DbPage*, %struct.PagerLruLink, %struct.DbPage*, i8, i8, i8, i8, i8, i16, %struct.DbPage*, %struct.DbPage*, i8* }
+ %struct.Expr = type { i8, i8, i16, %struct.CollSeq*, %struct.Expr*, %struct.Expr*, %struct.ExprList*, %struct..5sPragmaType, %struct..5sPragmaType, i32, i32, %struct.AggInfo*, i32, i32, %struct.Select*, %struct.Table*, i32 }
+ %struct.ExprList = type { i32, i32, i32, %struct.ExprList_item* }
+ %struct.ExprList_item = type { %struct.Expr*, i8*, i8, i8, i8 }
+ %struct.FKey = type { %struct.Table*, %struct.FKey*, i8*, %struct.FKey*, i32, %struct.sColMap*, i8, i8, i8, i8 }
+ %struct.Fifo = type { i32, %struct.FifoPage*, %struct.FifoPage* }
+ %struct.FifoPage = type { i32, i32, i32, %struct.FifoPage*, [1 x i64] }
+ %struct.FuncDef = type { i16, i8, i8, i8, i8*, %struct.FuncDef*, void (%struct.sqlite3_context*, i32, %struct.Mem**)*, void (%struct.sqlite3_context*, i32, %struct.Mem**)*, void (%struct.sqlite3_context*)*, [1 x i8] }
+ %struct.Hash = type { i8, i8, i32, i32, %struct.HashElem*, %struct._ht* }
+ %struct.HashElem = type { %struct.HashElem*, %struct.HashElem*, i8*, i8*, i32 }
+ %struct.IdList = type { %struct..5sPragmaType*, i32, i32 }
+ %struct.Index = type { i8*, i32, i32*, i32*, %struct.Table*, i32, i8, i8, i8*, %struct.Index*, %struct.Schema*, i8*, i8** }
+ %struct.KeyInfo = type { %struct.sqlite3*, i8, i8, i8, i32, i8*, [1 x %struct.CollSeq*] }
+ %struct.Mem = type { %struct.CountCtx, double, %struct.sqlite3*, i8*, i32, i16, i8, i8, void (i8*)* }
+ %struct.MemPage = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i16, i16, i16, i16, i16, i16, [5 x %struct._OvflCell], %struct.BtShared*, i8*, %struct.DbPage*, i32, %struct.MemPage* }
+ %struct.Module = type { %struct.sqlite3_module*, i8*, i8*, void (i8*)* }
+ %struct.Op = type { i8, i8, i8, i8, i32, i32, i32, %1 }
+ %struct.Pager = type { %struct.sqlite3_vfs*, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.Bitvec*, %struct.Bitvec*, i8*, i8*, i8*, i8*, %struct.sqlite3_file*, %struct.sqlite3_file*, %struct.sqlite3_file*, %struct.BusyHandler*, %struct.PagerLruList, %struct.DbPage*, %struct.DbPage*, %struct.DbPage*, i64, i64, i64, i64, i64, i32, void (%struct.DbPage*, i32)*, void (%struct.DbPage*, i32)*, i32, %struct.DbPage**, i8*, [16 x i8] }
+ %struct.PagerLruLink = type { %struct.DbPage*, %struct.DbPage* }
+ %struct.PagerLruList = type { %struct.DbPage*, %struct.DbPage*, %struct.DbPage* }
+ %struct.Schema = type { i32, %struct.Hash, %struct.Hash, %struct.Hash, %struct.Hash, %struct.Table*, i8, i8, i16, i32, %struct.sqlite3* }
+ %struct.Select = type { %struct.ExprList*, i8, i8, i8, i8, i8, i8, i8, %struct.SrcList*, %struct.Expr*, %struct.ExprList*, %struct.Expr*, %struct.ExprList*, %struct.Select*, %struct.Select*, %struct.Select*, %struct.Expr*, %struct.Expr*, i32, i32, [3 x i32] }
+ %struct.SrcList = type { i16, i16, [1 x %struct.SrcList_item] }
+ %struct.SrcList_item = type { i8*, i8*, i8*, %struct.Table*, %struct.Select*, i8, i8, i32, %struct.Expr*, %struct.IdList*, i64 }
+ %struct.Table = type { i8*, i32, %struct.Column*, i32, %struct.Index*, i32, %struct.Select*, i32, %struct.Trigger*, %struct.FKey*, i8*, %struct.Expr*, i32, i8, i8, i8, i8, i8, i8, i8, %struct.Module*, %struct.sqlite3_vtab*, i32, i8**, %struct.Schema* }
+ %struct.Trigger = type { i8*, i8*, i8, i8, %struct.Expr*, %struct.IdList*, %struct..5sPragmaType, %struct.Schema*, %struct.Schema*, %struct.TriggerStep*, %struct.Trigger* }
+ %struct.TriggerStep = type { i32, i32, %struct.Trigger*, %struct.Select*, %struct..5sPragmaType, %struct.Expr*, %struct.ExprList*, %struct.IdList*, %struct.TriggerStep*, %struct.TriggerStep* }
+ %struct.Vdbe = type { %struct.sqlite3*, %struct.Vdbe*, %struct.Vdbe*, i32, i32, %struct.Op*, i32, i32, i32*, %struct.Mem**, %struct.Mem*, i32, %struct.Cursor**, i32, %struct.Mem*, i8**, i32, i32, i32, %struct.Mem*, i32, i32, %struct.Fifo, i32, i32, %struct.Context*, i32, i32, i32, i32, i32, [25 x i32], i32, i32, i8**, i8*, %struct.Mem*, i8, i8, i8, i8, i8, i8, i32, i64, i32, %struct.BtreeMutexArray, i32, i8*, i32 }
+ %struct.VdbeFunc = type { %struct.FuncDef*, i32, [1 x %struct.AuxData] }
+ %struct._OvflCell = type { i8*, i16 }
+ %struct._ht = type { i32, %struct.HashElem* }
+ %struct.sColMap = type { i32, i8* }
+ %struct.sqlite3 = type { %struct.sqlite3_vfs*, i32, %struct.Db*, i32, i32, i32, i32, i8, i8, i8, i8, i32, %struct.CollSeq*, i64, i64, i32, i32, i32, %struct.sqlite3_mutex*, %struct.sqlite3InitInfo, i32, i8**, %struct.Vdbe*, i32, void (i8*, i8*)*, i8*, void (i8*, i8*, i64)*, i8*, i8*, i32 (i8*)*, i8*, void (i8*)*, i8*, void (i8*, i32, i8*, i8*, i64)*, void (i8*, %struct.sqlite3*, i32, i8*)*, void (i8*, %struct.sqlite3*, i32, i8*)*, i8*, %struct.Mem*, i8*, i8*, %2, i32 (i8*, i32, i8*, i8*, i8*, i8*)*, i8*, i32 (i8*)*, i8*, i32, %struct.Hash, %struct.Table*, %struct.sqlite3_vtab**, i32, %struct.Hash, %struct.Hash, %struct.BusyHandler, i32, [2 x %struct.Db], i8 }
+ %struct.sqlite3InitInfo = type { i32, i32, i8 }
+ %struct.sqlite3_context = type { %struct.FuncDef*, %struct.VdbeFunc*, %struct.Mem, %struct.Mem*, i32, %struct.CollSeq* }
+ %struct.sqlite3_file = type { %struct.sqlite3_io_methods* }
+ %struct.sqlite3_index_constraint = type { i32, i8, i8, i32 }
+ %struct.sqlite3_index_constraint_usage = type { i32, i8 }
+ %struct.sqlite3_index_info = type { i32, %struct.sqlite3_index_constraint*, i32, %struct.sqlite3_index_constraint_usage*, %struct.sqlite3_index_constraint_usage*, i32, i8*, i32, i32, double }
+ %struct.sqlite3_io_methods = type { i32, i32 (%struct.sqlite3_file*)*, i32 (%struct.sqlite3_file*, i8*, i32, i64)*, i32 (%struct.sqlite3_file*, i8*, i32, i64)*, i32 (%struct.sqlite3_file*, i64)*, i32 (%struct.sqlite3_file*, i32)*, i32 (%struct.sqlite3_file*, i64*)*, i32 (%struct.sqlite3_file*, i32)*, i32 (%struct.sqlite3_file*, i32)*, i32 (%struct.sqlite3_file*)*, i32 (%struct.sqlite3_file*, i32, i8*)*, i32 (%struct.sqlite3_file*)*, i32 (%struct.sqlite3_file*)* }
+ %struct.sqlite3_module = type { i32, i32 (%struct.sqlite3*, i8*, i32, i8**, %struct.sqlite3_vtab**, i8**)*, i32 (%struct.sqlite3*, i8*, i32, i8**, %struct.sqlite3_vtab**, i8**)*, i32 (%struct.sqlite3_vtab*, %struct.sqlite3_index_info*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*, %struct.sqlite3_vtab_cursor**)*, i32 (%struct.sqlite3_vtab_cursor*)*, i32 (%struct.sqlite3_vtab_cursor*, i32, i8*, i32, %struct.Mem**)*, i32 (%struct.sqlite3_vtab_cursor*)*, i32 (%struct.sqlite3_vtab_cursor*)*, i32 (%struct.sqlite3_vtab_cursor*, %struct.sqlite3_context*, i32)*, i32 (%struct.sqlite3_vtab_cursor*, i64*)*, i32 (%struct.sqlite3_vtab*, i32, %struct.Mem**, i64*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*, i32, i8*, void (%struct.sqlite3_context*, i32, %struct.Mem**)**, i8**)*, i32 (%struct.sqlite3_vtab*, i8*)* }
+ %struct.sqlite3_mutex = type opaque
+ %struct.sqlite3_vfs = type { i32, i32, i32, %struct.sqlite3_vfs*, i8*, i8*, i32 (%struct.sqlite3_vfs*, i8*, %struct.sqlite3_file*, i32, i32*)*, i32 (%struct.sqlite3_vfs*, i8*, i32)*, i32 (%struct.sqlite3_vfs*, i8*, i32)*, i32 (%struct.sqlite3_vfs*, i32, i8*)*, i32 (%struct.sqlite3_vfs*, i8*, i32, i8*)*, i8* (%struct.sqlite3_vfs*, i8*)*, void (%struct.sqlite3_vfs*, i32, i8*)*, i8* (%struct.sqlite3_vfs*, i8*, i8*)*, void (%struct.sqlite3_vfs*, i8*)*, i32 (%struct.sqlite3_vfs*, i32, i8*)*, i32 (%struct.sqlite3_vfs*, i32)*, i32 (%struct.sqlite3_vfs*, double*)* }
+ %struct.sqlite3_vtab = type { %struct.sqlite3_module*, i32, i8* }
+ %struct.sqlite3_vtab_cursor = type { %struct.sqlite3_vtab* }
[email protected] = appending global [1 x i8*] [i8* bitcast (void (%struct.MemPage*, i32, i32)* @dropCell to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define fastcc void @dropCell(%struct.MemPage* nocapture %pPage, i32 %idx, i32 %sz) nounwind ssp {
+entry:
+ %0 = getelementptr %struct.MemPage* %pPage, i64 0, i32 18 ; <i8**> [#uses=1]
+ %1 = load i8** %0, align 8 ; <i8*> [#uses=34]
+ %2 = getelementptr %struct.MemPage* %pPage, i64 0, i32 12 ; <i16*> [#uses=1]
+ %3 = load i16* %2, align 2 ; <i16> [#uses=1]
+ %4 = zext i16 %3 to i32 ; <i32> [#uses=2]
+ %5 = shl i32 %idx, 1 ; <i32> [#uses=2]
+ %6 = add i32 %4, %5 ; <i32> [#uses=1]
+ %7 = sext i32 %6 to i64 ; <i64> [#uses=2]
+ %8 = getelementptr i8* %1, i64 %7 ; <i8*> [#uses=1]
+ %9 = load i8* %8, align 1 ; <i8> [#uses=2]
+ %10 = zext i8 %9 to i32 ; <i32> [#uses=1]
+ %11 = shl i32 %10, 8 ; <i32> [#uses=1]
+ %.sum3 = add i64 %7, 1 ; <i64> [#uses=1]
+ %12 = getelementptr i8* %1, i64 %.sum3 ; <i8*> [#uses=1]
+ %13 = load i8* %12, align 1 ; <i8> [#uses=2]
+ %14 = zext i8 %13 to i32 ; <i32> [#uses=1]
+ %15 = or i32 %11, %14 ; <i32> [#uses=3]
+ %16 = icmp slt i32 %sz, 4 ; <i1> [#uses=1]
+ %size_addr.0.i = select i1 %16, i32 4, i32 %sz ; <i32> [#uses=3]
+ %17 = getelementptr %struct.MemPage* %pPage, i64 0, i32 8 ; <i8*> [#uses=5]
+ %18 = load i8* %17, align 8 ; <i8> [#uses=1]
+ %19 = zext i8 %18 to i32 ; <i32> [#uses=4]
+ %20 = add i32 %19, 1 ; <i32> [#uses=2]
+ br label %bb3.i
+
+bb3.i: ; preds = %bb3.i, %entry
+ %addr.0.i = phi i32 [ %20, %entry ], [ %29, %bb3.i ] ; <i32> [#uses=1]
+ %21 = sext i32 %addr.0.i to i64 ; <i64> [#uses=2]
+ %22 = getelementptr i8* %1, i64 %21 ; <i8*> [#uses=2]
+ %23 = load i8* %22, align 1 ; <i8> [#uses=2]
+ %24 = zext i8 %23 to i32 ; <i32> [#uses=1]
+ %25 = shl i32 %24, 8 ; <i32> [#uses=1]
+ %.sum34.i = add i64 %21, 1 ; <i64> [#uses=1]
+ %26 = getelementptr i8* %1, i64 %.sum34.i ; <i8*> [#uses=2]
+ %27 = load i8* %26, align 1 ; <i8> [#uses=2]
+ %28 = zext i8 %27 to i32 ; <i32> [#uses=1]
+ %29 = or i32 %25, %28 ; <i32> [#uses=3]
+ %.not.i = icmp uge i32 %29, %15 ; <i1> [#uses=1]
+ %30 = icmp eq i32 %29, 0 ; <i1> [#uses=1]
+ %or.cond.i = or i1 %30, %.not.i ; <i1> [#uses=1]
+ br i1 %or.cond.i, label %bb5.i, label %bb3.i
+
+bb5.i: ; preds = %bb3.i
+ store i8 %9, i8* %22, align 1
+ store i8 %13, i8* %26, align 1
+ %31 = zext i32 %15 to i64 ; <i64> [#uses=2]
+ %32 = getelementptr i8* %1, i64 %31 ; <i8*> [#uses=1]
+ store i8 %23, i8* %32, align 1
+ %.sum32.i = add i64 %31, 1 ; <i64> [#uses=1]
+ %33 = getelementptr i8* %1, i64 %.sum32.i ; <i8*> [#uses=1]
+ store i8 %27, i8* %33, align 1
+ %34 = add i32 %15, 2 ; <i32> [#uses=1]
+ %35 = zext i32 %34 to i64 ; <i64> [#uses=2]
+ %36 = getelementptr i8* %1, i64 %35 ; <i8*> [#uses=1]
+ %37 = lshr i32 %size_addr.0.i, 8 ; <i32> [#uses=1]
+ %38 = trunc i32 %37 to i8 ; <i8> [#uses=1]
+ store i8 %38, i8* %36, align 1
+ %39 = trunc i32 %size_addr.0.i to i8 ; <i8> [#uses=1]
+ %.sum31.i = add i64 %35, 1 ; <i64> [#uses=1]
+ %40 = getelementptr i8* %1, i64 %.sum31.i ; <i8*> [#uses=1]
+ store i8 %39, i8* %40, align 1
+ %41 = getelementptr %struct.MemPage* %pPage, i64 0, i32 14 ; <i16*> [#uses=4]
+ %42 = load i16* %41, align 2 ; <i16> [#uses=1]
+ %43 = trunc i32 %size_addr.0.i to i16 ; <i16> [#uses=1]
+ %44 = add i16 %42, %43 ; <i16> [#uses=1]
+ store i16 %44, i16* %41, align 2
+ %45 = load i8* %17, align 8 ; <i8> [#uses=1]
+ %46 = zext i8 %45 to i32 ; <i32> [#uses=1]
+ %47 = add i32 %46, 1 ; <i32> [#uses=1]
+ br label %bb11.outer.i
+
+bb11.outer.i: ; preds = %bb6.i, %bb5.i
+ %addr.1.ph.i = phi i32 [ %47, %bb5.i ], [ %111, %bb6.i ] ; <i32> [#uses=1]
+ %48 = sext i32 %addr.1.ph.i to i64 ; <i64> [#uses=2]
+ %49 = getelementptr i8* %1, i64 %48 ; <i8*> [#uses=1]
+ %.sum30.i = add i64 %48, 1 ; <i64> [#uses=1]
+ %50 = getelementptr i8* %1, i64 %.sum30.i ; <i8*> [#uses=1]
+ br label %bb11.i
+
+bb6.i: ; preds = %bb11.i
+ %51 = zext i32 %111 to i64 ; <i64> [#uses=2]
+ %52 = getelementptr i8* %1, i64 %51 ; <i8*> [#uses=2]
+ %53 = load i8* %52, align 1 ; <i8> [#uses=1]
+ %54 = zext i8 %53 to i32 ; <i32> [#uses=1]
+ %55 = shl i32 %54, 8 ; <i32> [#uses=1]
+ %.sum24.i = add i64 %51, 1 ; <i64> [#uses=1]
+ %56 = getelementptr i8* %1, i64 %.sum24.i ; <i8*> [#uses=2]
+ %57 = load i8* %56, align 1 ; <i8> [#uses=3]
+ %58 = zext i8 %57 to i32 ; <i32> [#uses=1]
+ %59 = or i32 %55, %58 ; <i32> [#uses=5]
+ %60 = add i32 %111, 2 ; <i32> [#uses=1]
+ %61 = zext i32 %60 to i64 ; <i64> [#uses=2]
+ %62 = getelementptr i8* %1, i64 %61 ; <i8*> [#uses=2]
+ %63 = load i8* %62, align 1 ; <i8> [#uses=1]
+ %64 = zext i8 %63 to i32 ; <i32> [#uses=1]
+ %65 = shl i32 %64, 8 ; <i32> [#uses=1]
+ %.sum23.i = add i64 %61, 1 ; <i64> [#uses=1]
+ %66 = getelementptr i8* %1, i64 %.sum23.i ; <i8*> [#uses=2]
+ %67 = load i8* %66, align 1 ; <i8> [#uses=2]
+ %68 = zext i8 %67 to i32 ; <i32> [#uses=1]
+ %69 = or i32 %65, %68 ; <i32> [#uses=1]
+ %70 = add i32 %111, 3 ; <i32> [#uses=1]
+ %71 = add i32 %70, %69 ; <i32> [#uses=1]
+ %72 = icmp sge i32 %71, %59 ; <i1> [#uses=1]
+ %73 = icmp ne i32 %59, 0 ; <i1> [#uses=1]
+ %74 = and i1 %72, %73 ; <i1> [#uses=1]
+ br i1 %74, label %bb9.i, label %bb11.outer.i
+
+bb9.i: ; preds = %bb6.i
+ %75 = load i8* %17, align 8 ; <i8> [#uses=1]
+ %76 = zext i8 %75 to i32 ; <i32> [#uses=1]
+ %77 = add i32 %76, 7 ; <i32> [#uses=1]
+ %78 = zext i32 %77 to i64 ; <i64> [#uses=1]
+ %79 = getelementptr i8* %1, i64 %78 ; <i8*> [#uses=2]
+ %80 = load i8* %79, align 1 ; <i8> [#uses=1]
+ %81 = sub i8 %109, %57 ; <i8> [#uses=1]
+ %82 = add i8 %81, %67 ; <i8> [#uses=1]
+ %83 = add i8 %82, %80 ; <i8> [#uses=1]
+ store i8 %83, i8* %79, align 1
+ %84 = zext i32 %59 to i64 ; <i64> [#uses=2]
+ %85 = getelementptr i8* %1, i64 %84 ; <i8*> [#uses=1]
+ %86 = load i8* %85, align 1 ; <i8> [#uses=1]
+ store i8 %86, i8* %52, align 1
+ %.sum22.i = add i64 %84, 1 ; <i64> [#uses=1]
+ %87 = getelementptr i8* %1, i64 %.sum22.i ; <i8*> [#uses=1]
+ %88 = load i8* %87, align 1 ; <i8> [#uses=1]
+ store i8 %88, i8* %56, align 1
+ %89 = add i32 %59, 2 ; <i32> [#uses=1]
+ %90 = zext i32 %89 to i64 ; <i64> [#uses=2]
+ %91 = getelementptr i8* %1, i64 %90 ; <i8*> [#uses=1]
+ %92 = load i8* %91, align 1 ; <i8> [#uses=1]
+ %93 = zext i8 %92 to i32 ; <i32> [#uses=1]
+ %94 = shl i32 %93, 8 ; <i32> [#uses=1]
+ %.sum20.i = add i64 %90, 1 ; <i64> [#uses=1]
+ %95 = getelementptr i8* %1, i64 %.sum20.i ; <i8*> [#uses=2]
+ %96 = load i8* %95, align 1 ; <i8> [#uses=1]
+ %97 = zext i8 %96 to i32 ; <i32> [#uses=1]
+ %98 = or i32 %94, %97 ; <i32> [#uses=1]
+ %99 = sub i32 %59, %111 ; <i32> [#uses=1]
+ %100 = add i32 %99, %98 ; <i32> [#uses=1]
+ %101 = lshr i32 %100, 8 ; <i32> [#uses=1]
+ %102 = trunc i32 %101 to i8 ; <i8> [#uses=1]
+ store i8 %102, i8* %62, align 1
+ %103 = load i8* %95, align 1 ; <i8> [#uses=1]
+ %104 = sub i8 %57, %109 ; <i8> [#uses=1]
+ %105 = add i8 %104, %103 ; <i8> [#uses=1]
+ store i8 %105, i8* %66, align 1
+ br label %bb11.i
+
+bb11.i: ; preds = %bb9.i, %bb11.outer.i
+ %106 = load i8* %49, align 1 ; <i8> [#uses=1]
+ %107 = zext i8 %106 to i32 ; <i32> [#uses=1]
+ %108 = shl i32 %107, 8 ; <i32> [#uses=1]
+ %109 = load i8* %50, align 1 ; <i8> [#uses=3]
+ %110 = zext i8 %109 to i32 ; <i32> [#uses=1]
+ %111 = or i32 %108, %110 ; <i32> [#uses=6]
+ %112 = icmp eq i32 %111, 0 ; <i1> [#uses=1]
+ br i1 %112, label %bb12.i, label %bb6.i
+
+bb12.i: ; preds = %bb11.i
+ %113 = zext i32 %20 to i64 ; <i64> [#uses=2]
+ %114 = getelementptr i8* %1, i64 %113 ; <i8*> [#uses=2]
+ %115 = load i8* %114, align 1 ; <i8> [#uses=2]
+ %116 = add i32 %19, 5 ; <i32> [#uses=1]
+ %117 = zext i32 %116 to i64 ; <i64> [#uses=2]
+ %118 = getelementptr i8* %1, i64 %117 ; <i8*> [#uses=3]
+ %119 = load i8* %118, align 1 ; <i8> [#uses=1]
+ %120 = icmp eq i8 %115, %119 ; <i1> [#uses=1]
+ br i1 %120, label %bb13.i, label %bb1.preheader
+
+bb13.i: ; preds = %bb12.i
+ %121 = add i32 %19, 2 ; <i32> [#uses=1]
+ %122 = zext i32 %121 to i64 ; <i64> [#uses=1]
+ %123 = getelementptr i8* %1, i64 %122 ; <i8*> [#uses=1]
+ %124 = load i8* %123, align 1 ; <i8> [#uses=1]
+ %125 = add i32 %19, 6 ; <i32> [#uses=1]
+ %126 = zext i32 %125 to i64 ; <i64> [#uses=1]
+ %127 = getelementptr i8* %1, i64 %126 ; <i8*> [#uses=1]
+ %128 = load i8* %127, align 1 ; <i8> [#uses=1]
+ %129 = icmp eq i8 %124, %128 ; <i1> [#uses=1]
+ br i1 %129, label %bb14.i, label %bb1.preheader
+
+bb14.i: ; preds = %bb13.i
+ %130 = zext i8 %115 to i32 ; <i32> [#uses=1]
+ %131 = shl i32 %130, 8 ; <i32> [#uses=1]
+ %.sum29.i = add i64 %113, 1 ; <i64> [#uses=1]
+ %132 = getelementptr i8* %1, i64 %.sum29.i ; <i8*> [#uses=1]
+ %133 = load i8* %132, align 1 ; <i8> [#uses=1]
+ %134 = zext i8 %133 to i32 ; <i32> [#uses=1]
+ %135 = or i32 %134, %131 ; <i32> [#uses=2]
+ %136 = zext i32 %135 to i64 ; <i64> [#uses=1]
+ %137 = getelementptr i8* %1, i64 %136 ; <i8*> [#uses=1]
+ %138 = bitcast i8* %137 to i16* ; <i16*> [#uses=1]
+ %139 = bitcast i8* %114 to i16* ; <i16*> [#uses=1]
+ %tmp.i = load i16* %138, align 1 ; <i16> [#uses=1]
+ store i16 %tmp.i, i16* %139, align 1
+ %140 = load i8* %118, align 1 ; <i8> [#uses=1]
+ %141 = zext i8 %140 to i32 ; <i32> [#uses=1]
+ %142 = shl i32 %141, 8 ; <i32> [#uses=1]
+ %.sum28.i = add i64 %117, 1 ; <i64> [#uses=1]
+ %143 = getelementptr i8* %1, i64 %.sum28.i ; <i8*> [#uses=2]
+ %144 = load i8* %143, align 1 ; <i8> [#uses=2]
+ %145 = zext i8 %144 to i32 ; <i32> [#uses=1]
+ %146 = or i32 %142, %145 ; <i32> [#uses=1]
+ %147 = add i32 %135, 2 ; <i32> [#uses=1]
+ %148 = zext i32 %147 to i64 ; <i64> [#uses=2]
+ %149 = getelementptr i8* %1, i64 %148 ; <i8*> [#uses=1]
+ %150 = load i8* %149, align 1 ; <i8> [#uses=1]
+ %151 = zext i8 %150 to i32 ; <i32> [#uses=1]
+ %152 = shl i32 %151, 8 ; <i32> [#uses=1]
+ %.sum27.i = add i64 %148, 1 ; <i64> [#uses=1]
+ %153 = getelementptr i8* %1, i64 %.sum27.i ; <i8*> [#uses=2]
+ %154 = load i8* %153, align 1 ; <i8> [#uses=1]
+ %155 = zext i8 %154 to i32 ; <i32> [#uses=1]
+ %156 = or i32 %152, %155 ; <i32> [#uses=1]
+ %157 = add i32 %156, %146 ; <i32> [#uses=1]
+ %158 = lshr i32 %157, 8 ; <i32> [#uses=1]
+ %159 = trunc i32 %158 to i8 ; <i8> [#uses=1]
+ store i8 %159, i8* %118, align 1
+ %160 = load i8* %153, align 1 ; <i8> [#uses=1]
+ %161 = add i8 %160, %144 ; <i8> [#uses=1]
+ store i8 %161, i8* %143, align 1
+ br label %bb1.preheader
+
+bb1.preheader: ; preds = %bb14.i, %bb13.i, %bb12.i
+ %i.08 = add i32 %idx, 1 ; <i32> [#uses=2]
+ %162 = getelementptr %struct.MemPage* %pPage, i64 0, i32 15 ; <i16*> [#uses=4]
+ %163 = load i16* %162, align 4 ; <i16> [#uses=2]
+ %164 = zext i16 %163 to i32 ; <i32> [#uses=1]
+ %165 = icmp sgt i32 %164, %i.08 ; <i1> [#uses=1]
+ br i1 %165, label %bb, label %bb2
+
+bb: ; preds = %bb, %bb1.preheader
+ %indvar = phi i64 [ 0, %bb1.preheader ], [ %indvar.next, %bb ] ; <i64> [#uses=3]
+ %tmp16 = add i32 %5, %4 ; <i32> [#uses=1]
+ %tmp.17 = sext i32 %tmp16 to i64 ; <i64> [#uses=1]
+ %tmp19 = shl i64 %indvar, 1 ; <i64> [#uses=1]
+ %ctg2.sum = add i64 %tmp.17, %tmp19 ; <i64> [#uses=4]
+ %ctg229 = getelementptr i8* %1, i64 %ctg2.sum ; <i8*> [#uses=1]
+ %ctg229.sum31 = add i64 %ctg2.sum, 2 ; <i64> [#uses=1]
+ %166 = getelementptr i8* %1, i64 %ctg229.sum31 ; <i8*> [#uses=1]
+ %167 = load i8* %166, align 1 ; <i8> [#uses=1]
+ store i8 %167, i8* %ctg229
+ %ctg229.sum30 = add i64 %ctg2.sum, 3 ; <i64> [#uses=1]
+ %168 = getelementptr i8* %1, i64 %ctg229.sum30 ; <i8*> [#uses=1]
+ %169 = load i8* %168, align 1 ; <i8> [#uses=1]
+ %ctg229.sum = add i64 %ctg2.sum, 1 ; <i64> [#uses=1]
+ %170 = getelementptr i8* %1, i64 %ctg229.sum ; <i8*> [#uses=1]
+ store i8 %169, i8* %170, align 1
+ %indvar15 = trunc i64 %indvar to i32 ; <i32> [#uses=1]
+ %i.09 = add i32 %indvar15, %i.08 ; <i32> [#uses=1]
+ %i.0 = add i32 %i.09, 1 ; <i32> [#uses=1]
+ %171 = load i16* %162, align 4 ; <i16> [#uses=2]
+ %172 = zext i16 %171 to i32 ; <i32> [#uses=1]
+ %173 = icmp sgt i32 %172, %i.0 ; <i1> [#uses=1]
+ %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1]
+ br i1 %173, label %bb, label %bb2
+
+bb2: ; preds = %bb, %bb1.preheader
+ %174 = phi i16 [ %163, %bb1.preheader ], [ %171, %bb ] ; <i16> [#uses=1]
+ %175 = add i16 %174, -1 ; <i16> [#uses=2]
+ store i16 %175, i16* %162, align 4
+ %176 = load i8* %17, align 8 ; <i8> [#uses=1]
+ %177 = zext i8 %176 to i32 ; <i32> [#uses=1]
+ %178 = add i32 %177, 3 ; <i32> [#uses=1]
+ %179 = zext i32 %178 to i64 ; <i64> [#uses=1]
+ %180 = getelementptr i8* %1, i64 %179 ; <i8*> [#uses=1]
+ %181 = lshr i16 %175, 8 ; <i16> [#uses=1]
+ %182 = trunc i16 %181 to i8 ; <i8> [#uses=1]
+ store i8 %182, i8* %180, align 1
+ %183 = load i8* %17, align 8 ; <i8> [#uses=1]
+ %184 = zext i8 %183 to i32 ; <i32> [#uses=1]
+ %185 = add i32 %184, 3 ; <i32> [#uses=1]
+ %186 = zext i32 %185 to i64 ; <i64> [#uses=1]
+ %187 = load i16* %162, align 4 ; <i16> [#uses=1]
+ %188 = trunc i16 %187 to i8 ; <i8> [#uses=1]
+ %.sum = add i64 %186, 1 ; <i64> [#uses=1]
+ %189 = getelementptr i8* %1, i64 %.sum ; <i8*> [#uses=1]
+ store i8 %188, i8* %189, align 1
+ %190 = load i16* %41, align 2 ; <i16> [#uses=1]
+ %191 = add i16 %190, 2 ; <i16> [#uses=1]
+ store i16 %191, i16* %41, align 2
+ %192 = getelementptr %struct.MemPage* %pPage, i64 0, i32 1 ; <i8*> [#uses=1]
+ store i8 1, i8* %192, align 1
+ ret void
+}
diff --git a/test/CodeGen/X86/stdarg.ll b/test/CodeGen/X86/stdarg.ll
new file mode 100644
index 0000000..9778fa1
--- /dev/null
+++ b/test/CodeGen/X86/stdarg.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86-64 | grep {testb \[%\]al, \[%\]al}
+
+%struct.__va_list_tag = type { i32, i32, i8*, i8* }
+
+define void @foo(i32 %x, ...) nounwind {
+entry:
+ %ap = alloca [1 x %struct.__va_list_tag], align 8; <[1 x %struct.__va_list_tag]*> [#uses=2]
+ %ap12 = bitcast [1 x %struct.__va_list_tag]* %ap to i8*; <i8*> [#uses=2]
+ call void @llvm.va_start(i8* %ap12)
+ %ap3 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0; <%struct.__va_list_tag*> [#uses=1]
+ call void @bar(%struct.__va_list_tag* %ap3) nounwind
+ call void @llvm.va_end(i8* %ap12)
+ ret void
+}
+
+declare void @llvm.va_start(i8*) nounwind
+
+declare void @bar(%struct.__va_list_tag*)
+
+declare void @llvm.va_end(i8*) nounwind
diff --git a/test/CodeGen/X86/store-empty-member.ll b/test/CodeGen/X86/store-empty-member.ll
new file mode 100644
index 0000000..37f86c6
--- /dev/null
+++ b/test/CodeGen/X86/store-empty-member.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 | FileCheck %s
+
+; Don't crash on an empty struct member.
+
+; CHECK: movl $2, 4(%esp)
+; CHECK: movl $1, (%esp)
+
+%testType = type {i32, [0 x i32], i32}
+
+define void @foo() nounwind {
+ %1 = alloca %testType
+ volatile store %testType {i32 1, [0 x i32] zeroinitializer, i32 2}, %testType* %1
+ ret void
+}
diff --git a/test/CodeGen/X86/store-fp-constant.ll b/test/CodeGen/X86/store-fp-constant.ll
new file mode 100644
index 0000000..206886b
--- /dev/null
+++ b/test/CodeGen/X86/store-fp-constant.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86 | not grep rodata
+; RUN: llc < %s -march=x86 | not grep literal
+;
+; Check that no FP constants in this testcase ends up in the
+; constant pool.
+
+@G = external global float ; <float*> [#uses=1]
+
+declare void @extfloat(float)
+
+declare void @extdouble(double)
+
+define void @testfloatstore() {
+ call void @extfloat( float 0x40934999A0000000 )
+ call void @extdouble( double 0x409349A631F8A090 )
+ store float 0x402A064C20000000, float* @G
+ ret void
+}
+
diff --git a/test/CodeGen/X86/store-global-address.ll b/test/CodeGen/X86/store-global-address.ll
new file mode 100644
index 0000000..c8d4cbc
--- /dev/null
+++ b/test/CodeGen/X86/store-global-address.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 | grep movl | count 1
+
+@dst = global i32 0 ; <i32*> [#uses=1]
+@ptr = global i32* null ; <i32**> [#uses=1]
+
+define void @test() {
+ store i32* @dst, i32** @ptr
+ ret void
+}
+
diff --git a/test/CodeGen/X86/store_op_load_fold.ll b/test/CodeGen/X86/store_op_load_fold.ll
new file mode 100644
index 0000000..66d0e47
--- /dev/null
+++ b/test/CodeGen/X86/store_op_load_fold.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 | not grep mov
+;
+; Test the add and load are folded into the store instruction.
+
+@X = internal global i16 0 ; <i16*> [#uses=2]
+
+define void @foo() {
+ %tmp.0 = load i16* @X ; <i16> [#uses=1]
+ %tmp.3 = add i16 %tmp.0, 329 ; <i16> [#uses=1]
+ store i16 %tmp.3, i16* @X
+ ret void
+}
+
diff --git a/test/CodeGen/X86/store_op_load_fold2.ll b/test/CodeGen/X86/store_op_load_fold2.ll
new file mode 100644
index 0000000..0ccfe47
--- /dev/null
+++ b/test/CodeGen/X86/store_op_load_fold2.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
+; RUN: grep {and DWORD PTR} | count 2
+
+target datalayout = "e-p:32:32"
+ %struct.Macroblock = type { i32, i32, i32, i32, i32, [8 x i32], %struct.Macroblock*, %struct.Macroblock*, i32, [2 x [4 x [4 x [2 x i32]]]], [16 x i8], [16 x i8], i32, i64, [4 x i32], [4 x i32], i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, double, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+
+define internal fastcc i32 @dct_chroma(i32 %uv, i32 %cr_cbp) {
+entry:
+ br i1 true, label %cond_true2732.preheader, label %cond_true129
+cond_true129: ; preds = %entry
+ ret i32 0
+cond_true2732.preheader: ; preds = %entry
+ %tmp2666 = getelementptr %struct.Macroblock* null, i32 0, i32 13 ; <i64*> [#uses=2]
+ %tmp2674 = trunc i32 0 to i8 ; <i8> [#uses=1]
+ br i1 true, label %cond_true2732.preheader.split.us, label %cond_true2732.preheader.split
+cond_true2732.preheader.split.us: ; preds = %cond_true2732.preheader
+ br i1 true, label %cond_true2732.outer.us.us, label %cond_true2732.outer.us
+cond_true2732.outer.us.us: ; preds = %cond_true2732.preheader.split.us
+ %tmp2667.us.us = load i64* %tmp2666 ; <i64> [#uses=1]
+ %tmp2670.us.us = load i64* null ; <i64> [#uses=1]
+ %shift.upgrd.1 = zext i8 %tmp2674 to i64 ; <i64> [#uses=1]
+ %tmp2675.us.us = shl i64 %tmp2670.us.us, %shift.upgrd.1 ; <i64> [#uses=1]
+ %tmp2675not.us.us = xor i64 %tmp2675.us.us, -1 ; <i64> [#uses=1]
+ %tmp2676.us.us = and i64 %tmp2667.us.us, %tmp2675not.us.us ; <i64> [#uses=1]
+ store i64 %tmp2676.us.us, i64* %tmp2666
+ ret i32 0
+cond_true2732.outer.us: ; preds = %cond_true2732.preheader.split.us
+ ret i32 0
+cond_true2732.preheader.split: ; preds = %cond_true2732.preheader
+ ret i32 0
+cond_next2752: ; No predecessors!
+ ret i32 0
+}
+
diff --git a/test/CodeGen/X86/storetrunc-fp.ll b/test/CodeGen/X86/storetrunc-fp.ll
new file mode 100644
index 0000000..03ad093
--- /dev/null
+++ b/test/CodeGen/X86/storetrunc-fp.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 | not grep flds
+
+define void @foo(x86_fp80 %a, x86_fp80 %b, float* %fp) {
+ %c = fadd x86_fp80 %a, %b
+ %d = fptrunc x86_fp80 %c to float
+ store float %d, float* %fp
+ ret void
+}
diff --git a/test/CodeGen/X86/stride-nine-with-base-reg.ll b/test/CodeGen/X86/stride-nine-with-base-reg.ll
new file mode 100644
index 0000000..f4847a3
--- /dev/null
+++ b/test/CodeGen/X86/stride-nine-with-base-reg.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=x86 -relocation-model=static | not grep lea
+; RUN: llc < %s -march=x86-64 | not grep lea
+
+; P should be sunk into the loop and folded into the address mode. There
+; shouldn't be any lea instructions inside the loop.
+
+@B = external global [1000 x i8], align 32
+@A = external global [1000 x i8], align 32
+@P = external global [1000 x i8], align 32
+@Q = external global [1000 x i8], align 32
+
+define void @foo(i32 %m, i32 %p) nounwind {
+entry:
+ %tmp1 = icmp sgt i32 %m, 0
+ br i1 %tmp1, label %bb, label %return
+
+bb:
+ %i.019.0 = phi i32 [ %indvar.next, %bb ], [ 0, %entry ]
+ %tmp2 = getelementptr [1000 x i8]* @B, i32 0, i32 %i.019.0
+ %tmp3 = load i8* %tmp2, align 4
+ %tmp4 = mul i8 %tmp3, 2
+ %tmp5 = getelementptr [1000 x i8]* @A, i32 0, i32 %i.019.0
+ store i8 %tmp4, i8* %tmp5, align 4
+ %tmp8 = mul i32 %i.019.0, 9
+ %tmp0 = add i32 %tmp8, %p
+ %tmp10 = getelementptr [1000 x i8]* @P, i32 0, i32 %tmp0
+ store i8 17, i8* %tmp10, align 4
+ %tmp11 = getelementptr [1000 x i8]* @Q, i32 0, i32 %tmp0
+ store i8 19, i8* %tmp11, align 4
+ %indvar.next = add i32 %i.019.0, 1
+ %exitcond = icmp eq i32 %indvar.next, %m
+ br i1 %exitcond, label %return, label %bb
+
+return:
+ ret void
+}
+
diff --git a/test/CodeGen/X86/stride-reuse.ll b/test/CodeGen/X86/stride-reuse.ll
new file mode 100644
index 0000000..5cbd895
--- /dev/null
+++ b/test/CodeGen/X86/stride-reuse.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=x86 | not grep lea
+; RUN: llc < %s -march=x86-64 | not grep lea
+
+@B = external global [1000 x float], align 32
+@A = external global [1000 x float], align 32
+@P = external global [1000 x i32], align 32
+
+define void @foo(i32 %m) nounwind {
+entry:
+ %tmp1 = icmp sgt i32 %m, 0
+ br i1 %tmp1, label %bb, label %return
+
+bb:
+ %i.019.0 = phi i32 [ %indvar.next, %bb ], [ 0, %entry ]
+ %tmp2 = getelementptr [1000 x float]* @B, i32 0, i32 %i.019.0
+ %tmp3 = load float* %tmp2, align 4
+ %tmp4 = fmul float %tmp3, 2.000000e+00
+ %tmp5 = getelementptr [1000 x float]* @A, i32 0, i32 %i.019.0
+ store float %tmp4, float* %tmp5, align 4
+ %tmp8 = shl i32 %i.019.0, 1
+ %tmp9 = add i32 %tmp8, 64
+ %tmp10 = getelementptr [1000 x i32]* @P, i32 0, i32 %i.019.0
+ store i32 %tmp9, i32* %tmp10, align 4
+ %indvar.next = add i32 %i.019.0, 1
+ %exitcond = icmp eq i32 %indvar.next, %m
+ br i1 %exitcond, label %return, label %bb
+
+return:
+ ret void
+}
diff --git a/test/CodeGen/X86/sub-with-overflow.ll b/test/CodeGen/X86/sub-with-overflow.ll
new file mode 100644
index 0000000..19f4079
--- /dev/null
+++ b/test/CodeGen/X86/sub-with-overflow.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -march=x86 | grep {jo} | count 1
+; RUN: llc < %s -march=x86 | grep {jb} | count 1
+
+@ok = internal constant [4 x i8] c"%d\0A\00"
+@no = internal constant [4 x i8] c"no\0A\00"
+
+define i1 @func1(i32 %v1, i32 %v2) nounwind {
+entry:
+ %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
+ %sum = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %overflow, label %normal
+
+normal:
+ %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+ ret i1 true
+
+overflow:
+ %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+ ret i1 false
+}
+
+define i1 @func2(i32 %v1, i32 %v2) nounwind {
+entry:
+ %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
+ %sum = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %carry, label %normal
+
+normal:
+ %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+ ret i1 true
+
+carry:
+ %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+ ret i1 false
+}
+
+declare i32 @printf(i8*, ...) nounwind
+declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32)
+declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32)
diff --git a/test/CodeGen/X86/subreg-to-reg-0.ll b/test/CodeGen/X86/subreg-to-reg-0.ll
new file mode 100644
index 0000000..d718c85
--- /dev/null
+++ b/test/CodeGen/X86/subreg-to-reg-0.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86-64 | grep mov | count 1
+
+; Do eliminate the zero-extension instruction and rely on
+; x86-64's implicit zero-extension!
+
+define i64 @foo(i32* %p) nounwind {
+ %t = load i32* %p
+ %n = add i32 %t, 1
+ %z = zext i32 %n to i64
+ ret i64 %z
+}
diff --git a/test/CodeGen/X86/subreg-to-reg-1.ll b/test/CodeGen/X86/subreg-to-reg-1.ll
new file mode 100644
index 0000000..a297728
--- /dev/null
+++ b/test/CodeGen/X86/subreg-to-reg-1.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86-64 | grep {leal .*), %e.\*} | count 1
+
+; Don't eliminate or coalesce away the explicit zero-extension!
+; This is currently using an leal because of a 3-addressification detail,
+; though this isn't necessary; The point of this test is to make sure
+; a 32-bit add is used.
+
+define i64 @foo(i64 %a) nounwind {
+ %b = add i64 %a, 4294967295
+ %c = and i64 %b, 4294967295
+ %d = add i64 %c, 1
+ ret i64 %d
+}
diff --git a/test/CodeGen/X86/subreg-to-reg-2.ll b/test/CodeGen/X86/subreg-to-reg-2.ll
new file mode 100644
index 0000000..49d2e88
--- /dev/null
+++ b/test/CodeGen/X86/subreg-to-reg-2.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movl
+; rdar://6707985
+
+ %XXOO = type { %"struct.XXC::XXCC", i8*, %"struct.XXC::XXOO::$_71" }
+ %XXValue = type opaque
+ %"struct.XXC::ArrayStorage" = type { i32, i32, i32, i8*, i8*, [1 x %XXValue*] }
+ %"struct.XXC::XXArray" = type { %XXOO, i32, %"struct.XXC::ArrayStorage"* }
+ %"struct.XXC::XXCC" = type { i32 (...)**, i8* }
+ %"struct.XXC::XXOO::$_71" = type { [2 x %XXValue*] }
+
+define internal fastcc %XXValue* @t(i64* %out, %"struct.XXC::ArrayStorage"* %tmp9) nounwind {
+prologue:
+ %array = load %XXValue** inttoptr (i64 11111111 to %XXValue**) ; <%XXValue*> [#uses=0]
+ %index = load %XXValue** inttoptr (i64 22222222 to %XXValue**) ; <%XXValue*> [#uses=1]
+ %tmp = ptrtoint %XXValue* %index to i64 ; <i64> [#uses=2]
+ store i64 %tmp, i64* %out
+ %tmp6 = trunc i64 %tmp to i32 ; <i32> [#uses=1]
+ br label %bb5
+
+bb5: ; preds = %prologue
+ %tmp10 = zext i32 %tmp6 to i64 ; <i64> [#uses=1]
+ %tmp11 = getelementptr %"struct.XXC::ArrayStorage"* %tmp9, i64 0, i32 5, i64 %tmp10 ; <%XXValue**> [#uses=1]
+ %tmp12 = load %XXValue** %tmp11, align 8 ; <%XXValue*> [#uses=1]
+ ret %XXValue* %tmp12
+}
diff --git a/test/CodeGen/X86/subreg-to-reg-3.ll b/test/CodeGen/X86/subreg-to-reg-3.ll
new file mode 100644
index 0000000..931ae75
--- /dev/null
+++ b/test/CodeGen/X86/subreg-to-reg-3.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86-64 | grep imull
+
+; Don't eliminate or coalesce away the explicit zero-extension!
+
+define i64 @foo(i64 %a) {
+ %b = mul i64 %a, 7823
+ %c = and i64 %b, 4294967295
+ %d = add i64 %c, 1
+ ret i64 %d
+}
diff --git a/test/CodeGen/X86/subreg-to-reg-4.ll b/test/CodeGen/X86/subreg-to-reg-4.ll
new file mode 100644
index 0000000..0ea5541
--- /dev/null
+++ b/test/CodeGen/X86/subreg-to-reg-4.ll
@@ -0,0 +1,135 @@
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: not grep leaq %t
+; RUN: not grep incq %t
+; RUN: not grep decq %t
+; RUN: not grep negq %t
+; RUN: not grep addq %t
+; RUN: not grep subq %t
+; RUN: not grep {movl %} %t
+
+; Utilize implicit zero-extension on x86-64 to eliminate explicit
+; zero-extensions. Shrink 64-bit adds to 32-bit when the high
+; 32-bits will be zeroed.
+
+define void @bar(i64 %x, i64 %y, i64* %z) nounwind readnone {
+entry:
+ %t0 = add i64 %x, %y
+ %t1 = and i64 %t0, 4294967295
+ store i64 %t1, i64* %z
+ ret void
+}
+define void @easy(i32 %x, i32 %y, i64* %z) nounwind readnone {
+entry:
+ %t0 = add i32 %x, %y
+ %tn = zext i32 %t0 to i64
+ %t1 = and i64 %tn, 4294967295
+ store i64 %t1, i64* %z
+ ret void
+}
+define void @cola(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
+entry:
+ %p = load i64* %x
+ %t0 = add i64 %p, %y
+ %t1 = and i64 %t0, 4294967295
+ %t2 = xor i64 %t1, %u
+ store i64 %t2, i64* %z
+ ret void
+}
+define void @yaks(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
+entry:
+ %p = load i64* %x
+ %t0 = add i64 %p, %y
+ %t1 = xor i64 %t0, %u
+ %t2 = and i64 %t1, 4294967295
+ store i64 %t2, i64* %z
+ ret void
+}
+define void @foo(i64 *%x, i64 *%y, i64* %z) nounwind readnone {
+entry:
+ %a = load i64* %x
+ %b = load i64* %y
+ %t0 = add i64 %a, %b
+ %t1 = and i64 %t0, 4294967295
+ store i64 %t1, i64* %z
+ ret void
+}
+define void @avo(i64 %x, i64* %z, i64 %u) nounwind readnone {
+entry:
+ %t0 = add i64 %x, 734847
+ %t1 = and i64 %t0, 4294967295
+ %t2 = xor i64 %t1, %u
+ store i64 %t2, i64* %z
+ ret void
+}
+define void @phe(i64 %x, i64* %z, i64 %u) nounwind readnone {
+entry:
+ %t0 = add i64 %x, 734847
+ %t1 = xor i64 %t0, %u
+ %t2 = and i64 %t1, 4294967295
+ store i64 %t2, i64* %z
+ ret void
+}
+define void @oze(i64 %y, i64* %z) nounwind readnone {
+entry:
+ %t0 = add i64 %y, 1
+ %t1 = and i64 %t0, 4294967295
+ store i64 %t1, i64* %z
+ ret void
+}
+
+define void @sbar(i64 %x, i64 %y, i64* %z) nounwind readnone {
+entry:
+ %t0 = sub i64 %x, %y
+ %t1 = and i64 %t0, 4294967295
+ store i64 %t1, i64* %z
+ ret void
+}
+define void @seasy(i32 %x, i32 %y, i64* %z) nounwind readnone {
+entry:
+ %t0 = sub i32 %x, %y
+ %tn = zext i32 %t0 to i64
+ %t1 = and i64 %tn, 4294967295
+ store i64 %t1, i64* %z
+ ret void
+}
+define void @scola(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
+entry:
+ %p = load i64* %x
+ %t0 = sub i64 %p, %y
+ %t1 = and i64 %t0, 4294967295
+ %t2 = xor i64 %t1, %u
+ store i64 %t2, i64* %z
+ ret void
+}
+define void @syaks(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
+entry:
+ %p = load i64* %x
+ %t0 = sub i64 %p, %y
+ %t1 = xor i64 %t0, %u
+ %t2 = and i64 %t1, 4294967295
+ store i64 %t2, i64* %z
+ ret void
+}
+define void @sfoo(i64 *%x, i64 *%y, i64* %z) nounwind readnone {
+entry:
+ %a = load i64* %x
+ %b = load i64* %y
+ %t0 = sub i64 %a, %b
+ %t1 = and i64 %t0, 4294967295
+ store i64 %t1, i64* %z
+ ret void
+}
+define void @swya(i64 %y, i64* %z) nounwind readnone {
+entry:
+ %t0 = sub i64 0, %y
+ %t1 = and i64 %t0, 4294967295
+ store i64 %t1, i64* %z
+ ret void
+}
+define void @soze(i64 %y, i64* %z) nounwind readnone {
+entry:
+ %t0 = sub i64 %y, 1
+ %t1 = and i64 %t0, 4294967295
+ store i64 %t1, i64* %z
+ ret void
+}
diff --git a/test/CodeGen/X86/subreg-to-reg-6.ll b/test/CodeGen/X86/subreg-to-reg-6.ll
new file mode 100644
index 0000000..76430cd
--- /dev/null
+++ b/test/CodeGen/X86/subreg-to-reg-6.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=x86-64
+
+define i64 @foo() nounwind {
+entry:
+ %t0 = load i32* null, align 8
+ switch i32 %t0, label %bb65 [
+ i32 16, label %bb
+ i32 12, label %bb56
+ ]
+
+bb:
+ br label %bb65
+
+bb56:
+ unreachable
+
+bb65:
+ %a = phi i64 [ 0, %bb ], [ 0, %entry ]
+ tail call void asm "", "{cx}"(i64 %a) nounwind
+ %t15 = and i64 %a, 4294967295
+ ret i64 %t15
+}
+
+define i64 @bar(i64 %t0) nounwind {
+ call void asm "", "{cx}"(i64 0) nounwind
+ %t1 = sub i64 0, %t0
+ %t2 = and i64 %t1, 4294967295
+ ret i64 %t2
+}
diff --git a/test/CodeGen/X86/switch-crit-edge-constant.ll b/test/CodeGen/X86/switch-crit-edge-constant.ll
new file mode 100644
index 0000000..1f2ab0d
--- /dev/null
+++ b/test/CodeGen/X86/switch-crit-edge-constant.ll
@@ -0,0 +1,52 @@
+; PR925
+; RUN: llc < %s -march=x86 | \
+; RUN: grep mov.*str1 | count 1
+
+target datalayout = "e-p:32:32"
+target triple = "i686-apple-darwin8.7.2"
+@str1 = internal constant [5 x i8] c"bonk\00" ; <[5 x i8]*> [#uses=1]
+@str2 = internal constant [5 x i8] c"bork\00" ; <[5 x i8]*> [#uses=1]
+@str = internal constant [8 x i8] c"perfwap\00" ; <[8 x i8]*> [#uses=1]
+
+define void @foo(i32 %C) {
+entry:
+ switch i32 %C, label %bb2 [
+ i32 1, label %blahaha
+ i32 2, label %blahaha
+ i32 3, label %blahaha
+ i32 4, label %blahaha
+ i32 5, label %blahaha
+ i32 6, label %blahaha
+ i32 7, label %blahaha
+ i32 8, label %blahaha
+ i32 9, label %blahaha
+ i32 10, label %blahaha
+ ]
+
+bb2: ; preds = %entry
+ %tmp5 = and i32 %C, 123 ; <i32> [#uses=1]
+ %tmp = icmp eq i32 %tmp5, 0 ; <i1> [#uses=1]
+ br i1 %tmp, label %blahaha, label %cond_true
+
+cond_true: ; preds = %bb2
+ br label %blahaha
+
+blahaha: ; preds = %cond_true, %bb2, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry
+ %s.0 = phi i8* [ getelementptr ([8 x i8]* @str, i32 0, i64 0), %cond_true ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str1, i32 0, i64 0), %entry ], [ getelementptr ([5 x i8]* @str2, i32 0, i64 0), %bb2 ] ; <i8*> [#uses=13]
+ %tmp8 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0]
+ %tmp10 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0]
+ %tmp12 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0]
+ %tmp14 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0]
+ %tmp16 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0]
+ %tmp18 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0]
+ %tmp20 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0]
+ %tmp22 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0]
+ %tmp24 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0]
+ %tmp26 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0]
+ %tmp28 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0]
+ %tmp30 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0]
+ %tmp32 = tail call i32 (i8*, ...)* @printf( i8* %s.0 ) ; <i32> [#uses=0]
+ ret void
+}
+
+declare i32 @printf(i8*, ...)
diff --git a/test/CodeGen/X86/switch-zextload.ll b/test/CodeGen/X86/switch-zextload.ll
new file mode 100644
index 0000000..55425bc
--- /dev/null
+++ b/test/CodeGen/X86/switch-zextload.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=x86 | grep mov | count 1
+
+; Do zextload, instead of a load and a separate zext.
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin9.6"
+ %struct.move_s = type { i32, i32, i32, i32, i32, i32 }
+ %struct.node_t = type { i8, i8, i8, i8, i32, i32, %struct.node_t**, %struct.node_t*, %struct.move_s }
+
+define fastcc void @set_proof_and_disproof_numbers(%struct.node_t* nocapture %node) nounwind {
+entry:
+ %0 = load i8* null, align 1 ; <i8> [#uses=1]
+ switch i8 %0, label %return [
+ i8 2, label %bb31
+ i8 0, label %bb80
+ i8 1, label %bb82
+ i8 3, label %bb84
+ ]
+
+bb31: ; preds = %entry
+ unreachable
+
+bb80: ; preds = %entry
+ ret void
+
+bb82: ; preds = %entry
+ ret void
+
+bb84: ; preds = %entry
+ ret void
+
+return: ; preds = %entry
+ ret void
+}
diff --git a/test/CodeGen/X86/swizzle.ll b/test/CodeGen/X86/swizzle.ll
new file mode 100644
index 0000000..23e0c24
--- /dev/null
+++ b/test/CodeGen/X86/swizzle.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movlps
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movsd
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep movups
+; rdar://6523650
+
+ %struct.vector4_t = type { <4 x float> }
+
+define void @swizzle(i8* nocapture %a, %struct.vector4_t* nocapture %b, %struct.vector4_t* nocapture %c) nounwind {
+entry:
+ %0 = getelementptr %struct.vector4_t* %b, i32 0, i32 0 ; <<4 x float>*> [#uses=2]
+ %1 = load <4 x float>* %0, align 4 ; <<4 x float>> [#uses=1]
+ %tmp.i = bitcast i8* %a to double* ; <double*> [#uses=1]
+ %tmp1.i = load double* %tmp.i ; <double> [#uses=1]
+ %2 = insertelement <2 x double> undef, double %tmp1.i, i32 0 ; <<2 x double>> [#uses=1]
+ %tmp2.i = bitcast <2 x double> %2 to <4 x float> ; <<4 x float>> [#uses=1]
+ %3 = shufflevector <4 x float> %1, <4 x float> %tmp2.i, <4 x i32> < i32 4, i32 5, i32 2, i32 3 > ; <<4 x float>> [#uses=1]
+ store <4 x float> %3, <4 x float>* %0, align 4
+ ret void
+}
diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll
new file mode 100644
index 0000000..7b21e1b
--- /dev/null
+++ b/test/CodeGen/X86/tail-opts.ll
@@ -0,0 +1,408 @@
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false -post-RA-scheduler=true | FileCheck %s
+
+declare void @bar(i32)
+declare void @car(i32)
+declare void @dar(i32)
+declare void @ear(i32)
+declare void @far(i32)
+declare i1 @qux()
+
+@GHJK = global i32 0
+@HABC = global i32 0
+
+; BranchFolding should tail-merge the stores since they all precede
+; direct branches to the same place.
+
+; CHECK: tail_merge_me:
+; CHECK-NOT: GHJK
+; CHECK: movl $0, GHJK(%rip)
+; CHECK-NEXT: movl $1, HABC(%rip)
+; CHECK-NOT: GHJK
+
+define void @tail_merge_me() nounwind {
+entry:
+ %a = call i1 @qux()
+ br i1 %a, label %A, label %next
+next:
+ %b = call i1 @qux()
+ br i1 %b, label %B, label %C
+
+A:
+ call void @bar(i32 0)
+ store i32 0, i32* @GHJK
+ br label %M
+
+B:
+ call void @car(i32 1)
+ store i32 0, i32* @GHJK
+ br label %M
+
+C:
+ call void @dar(i32 2)
+ store i32 0, i32* @GHJK
+ br label %M
+
+M:
+ store i32 1, i32* @HABC
+ %c = call i1 @qux()
+ br i1 %c, label %return, label %altret
+
+return:
+ call void @ear(i32 1000)
+ ret void
+altret:
+ call void @far(i32 1001)
+ ret void
+}
+
+declare i8* @choose(i8*, i8*)
+
+; BranchFolding should tail-duplicate the indirect jump to avoid
+; redundant branching.
+
+; CHECK: tail_duplicate_me:
+; CHECK: movl $0, GHJK(%rip)
+; CHECK-NEXT: jmpq *%rbx
+; CHECK: movl $0, GHJK(%rip)
+; CHECK-NEXT: jmpq *%rbx
+; CHECK: movl $0, GHJK(%rip)
+; CHECK-NEXT: jmpq *%rbx
+
+define void @tail_duplicate_me() nounwind {
+entry:
+ %a = call i1 @qux()
+ %c = call i8* @choose(i8* blockaddress(@tail_duplicate_me, %return),
+ i8* blockaddress(@tail_duplicate_me, %altret))
+ br i1 %a, label %A, label %next
+next:
+ %b = call i1 @qux()
+ br i1 %b, label %B, label %C
+
+A:
+ call void @bar(i32 0)
+ store i32 0, i32* @GHJK
+ br label %M
+
+B:
+ call void @car(i32 1)
+ store i32 0, i32* @GHJK
+ br label %M
+
+C:
+ call void @dar(i32 2)
+ store i32 0, i32* @GHJK
+ br label %M
+
+M:
+ indirectbr i8* %c, [label %return, label %altret]
+
+return:
+ call void @ear(i32 1000)
+ ret void
+altret:
+ call void @far(i32 1001)
+ ret void
+}
+
+; BranchFolding shouldn't try to merge the tails of two blocks
+; with only a branch in common, regardless of the fallthrough situation.
+
+; CHECK: dont_merge_oddly:
+; CHECK-NOT: ret
+; CHECK: ucomiss %xmm1, %xmm2
+; CHECK-NEXT: jbe .LBB3_3
+; CHECK-NEXT: ucomiss %xmm0, %xmm1
+; CHECK-NEXT: ja .LBB3_4
+; CHECK-NEXT: .LBB3_2:
+; CHECK-NEXT: movb $1, %al
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB3_3:
+; CHECK-NEXT: ucomiss %xmm0, %xmm2
+; CHECK-NEXT: jbe .LBB3_2
+; CHECK-NEXT: .LBB3_4:
+; CHECK-NEXT: xorb %al, %al
+; CHECK-NEXT: ret
+
+define i1 @dont_merge_oddly(float* %result) nounwind {
+entry:
+ %tmp4 = getelementptr float* %result, i32 2
+ %tmp5 = load float* %tmp4, align 4
+ %tmp7 = getelementptr float* %result, i32 4
+ %tmp8 = load float* %tmp7, align 4
+ %tmp10 = getelementptr float* %result, i32 6
+ %tmp11 = load float* %tmp10, align 4
+ %tmp12 = fcmp olt float %tmp8, %tmp11
+ br i1 %tmp12, label %bb, label %bb21
+
+bb:
+ %tmp23469 = fcmp olt float %tmp5, %tmp8
+ br i1 %tmp23469, label %bb26, label %bb30
+
+bb21:
+ %tmp23 = fcmp olt float %tmp5, %tmp11
+ br i1 %tmp23, label %bb26, label %bb30
+
+bb26:
+ ret i1 0
+
+bb30:
+ ret i1 1
+}
+
+; Do any-size tail-merging when two candidate blocks will both require
+; an unconditional jump to complete a two-way conditional branch.
+
+; CHECK: c_expand_expr_stmt:
+; CHECK: jmp .LBB4_7
+; CHECK-NEXT: .LBB4_12:
+; CHECK-NEXT: movq 8(%rax), %rax
+; CHECK-NEXT: movb 16(%rax), %al
+; CHECK-NEXT: cmpb $16, %al
+; CHECK-NEXT: je .LBB4_6
+; CHECK-NEXT: cmpb $23, %al
+; CHECK-NEXT: je .LBB4_6
+; CHECK-NEXT: jmp .LBB4_15
+; CHECK-NEXT: .LBB4_14:
+; CHECK-NEXT: cmpb $23, %bl
+; CHECK-NEXT: jne .LBB4_15
+; CHECK-NEXT: .LBB4_15:
+
+%0 = type { %struct.rtx_def* }
+%struct.lang_decl = type opaque
+%struct.rtx_def = type { i16, i8, i8, [1 x %union.rtunion] }
+%struct.tree_decl = type { [24 x i8], i8*, i32, %union.tree_node*, i32, i8, i8, i8, i8, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %struct.rtx_def*, %union..2anon, %0, %union.tree_node*, %struct.lang_decl* }
+%union..2anon = type { i32 }
+%union.rtunion = type { i8* }
+%union.tree_node = type { %struct.tree_decl }
+
+define fastcc void @c_expand_expr_stmt(%union.tree_node* %expr) nounwind {
+entry:
+ %tmp4 = load i8* null, align 8 ; <i8> [#uses=3]
+ switch i8 %tmp4, label %bb3 [
+ i8 18, label %bb
+ ]
+
+bb: ; preds = %entry
+ switch i32 undef, label %bb1 [
+ i32 0, label %bb2.i
+ i32 37, label %bb.i
+ ]
+
+bb.i: ; preds = %bb
+ switch i32 undef, label %bb1 [
+ i32 0, label %lvalue_p.exit
+ ]
+
+bb2.i: ; preds = %bb
+ br label %bb3
+
+lvalue_p.exit: ; preds = %bb.i
+ %tmp21 = load %union.tree_node** null, align 8 ; <%union.tree_node*> [#uses=3]
+ %tmp22 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 0 ; <i8*> [#uses=1]
+ %tmp23 = load i8* %tmp22, align 8 ; <i8> [#uses=1]
+ %tmp24 = zext i8 %tmp23 to i32 ; <i32> [#uses=1]
+ switch i32 %tmp24, label %lvalue_p.exit4 [
+ i32 0, label %bb2.i3
+ i32 2, label %bb.i1
+ ]
+
+bb.i1: ; preds = %lvalue_p.exit
+ %tmp25 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 2 ; <i32*> [#uses=1]
+ %tmp26 = bitcast i32* %tmp25 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
+ %tmp27 = load %union.tree_node** %tmp26, align 8 ; <%union.tree_node*> [#uses=2]
+ %tmp28 = getelementptr inbounds %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
+ %tmp29 = load i8* %tmp28, align 8 ; <i8> [#uses=1]
+ %tmp30 = zext i8 %tmp29 to i32 ; <i32> [#uses=1]
+ switch i32 %tmp30, label %lvalue_p.exit4 [
+ i32 0, label %bb2.i.i2
+ i32 2, label %bb.i.i
+ ]
+
+bb.i.i: ; preds = %bb.i1
+ %tmp34 = tail call fastcc i32 @lvalue_p(%union.tree_node* null) nounwind ; <i32> [#uses=1]
+ %phitmp = icmp ne i32 %tmp34, 0 ; <i1> [#uses=1]
+ br label %lvalue_p.exit4
+
+bb2.i.i2: ; preds = %bb.i1
+ %tmp35 = getelementptr inbounds %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1]
+ %tmp36 = bitcast i8* %tmp35 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
+ %tmp37 = load %union.tree_node** %tmp36, align 8 ; <%union.tree_node*> [#uses=1]
+ %tmp38 = getelementptr inbounds %union.tree_node* %tmp37, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
+ %tmp39 = load i8* %tmp38, align 8 ; <i8> [#uses=1]
+ switch i8 %tmp39, label %bb2 [
+ i8 16, label %lvalue_p.exit4
+ i8 23, label %lvalue_p.exit4
+ ]
+
+bb2.i3: ; preds = %lvalue_p.exit
+ %tmp40 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1]
+ %tmp41 = bitcast i8* %tmp40 to %union.tree_node** ; <%union.tree_node**> [#uses=1]
+ %tmp42 = load %union.tree_node** %tmp41, align 8 ; <%union.tree_node*> [#uses=1]
+ %tmp43 = getelementptr inbounds %union.tree_node* %tmp42, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1]
+ %tmp44 = load i8* %tmp43, align 8 ; <i8> [#uses=1]
+ switch i8 %tmp44, label %bb2 [
+ i8 16, label %lvalue_p.exit4
+ i8 23, label %lvalue_p.exit4
+ ]
+
+lvalue_p.exit4: ; preds = %bb2.i3, %bb2.i3, %bb2.i.i2, %bb2.i.i2, %bb.i.i, %bb.i1, %lvalue_p.exit
+ %tmp45 = phi i1 [ %phitmp, %bb.i.i ], [ false, %bb2.i.i2 ], [ false, %bb2.i.i2 ], [ false, %bb.i1 ], [ false, %bb2.i3 ], [ false, %bb2.i3 ], [ false, %lvalue_p.exit ] ; <i1> [#uses=1]
+ %tmp46 = icmp eq i8 %tmp4, 0 ; <i1> [#uses=1]
+ %or.cond = or i1 %tmp45, %tmp46 ; <i1> [#uses=1]
+ br i1 %or.cond, label %bb2, label %bb3
+
+bb1: ; preds = %bb2.i.i, %bb.i, %bb
+ %.old = icmp eq i8 %tmp4, 23 ; <i1> [#uses=1]
+ br i1 %.old, label %bb2, label %bb3
+
+bb2: ; preds = %bb1, %lvalue_p.exit4, %bb2.i3, %bb2.i.i2
+ br label %bb3
+
+bb3: ; preds = %bb2, %bb1, %lvalue_p.exit4, %bb2.i, %entry
+ %expr_addr.0 = phi %union.tree_node* [ null, %bb2 ], [ %expr, %bb2.i ], [ %expr, %entry ], [ %expr, %bb1 ], [ %expr, %lvalue_p.exit4 ] ; <%union.tree_node*> [#uses=0]
+ unreachable
+}
+
+declare fastcc i32 @lvalue_p(%union.tree_node* nocapture) nounwind readonly
+
+declare fastcc %union.tree_node* @default_conversion(%union.tree_node*) nounwind
+
+
+; If one tail merging candidate falls through into the other,
+; tail merging is likely profitable regardless of how few
+; instructions are involved. This function should have only
+; one ret instruction.
+
+; CHECK: foo:
+; CHECK: callq func
+; CHECK-NEXT: .LBB5_2:
+; CHECK-NEXT: addq $8, %rsp
+; CHECK-NEXT: ret
+
+define void @foo(i1* %V) nounwind {
+entry:
+ %t0 = icmp eq i1* %V, null
+ br i1 %t0, label %return, label %bb
+
+bb:
+ call void @func()
+ ret void
+
+return:
+ ret void
+}
+
+declare void @func()
+
+; one - One instruction may be tail-duplicated even with optsize.
+
+; CHECK: one:
+; CHECK: movl $0, XYZ(%rip)
+; CHECK: movl $0, XYZ(%rip)
+
+@XYZ = external global i32
+
+define void @one() nounwind optsize {
+entry:
+ %0 = icmp eq i32 undef, 0
+ br i1 %0, label %bbx, label %bby
+
+bby:
+ switch i32 undef, label %bb7 [
+ i32 16, label %return
+ ]
+
+bb7:
+ volatile store i32 0, i32* @XYZ
+ unreachable
+
+bbx:
+ switch i32 undef, label %bb12 [
+ i32 128, label %return
+ ]
+
+bb12:
+ volatile store i32 0, i32* @XYZ
+ unreachable
+
+return:
+ ret void
+}
+
+; two - Same as one, but with two instructions in the common
+; tail instead of one. This is too much to be merged, given
+; the optsize attribute.
+
+; CHECK: two:
+; CHECK-NOT: XYZ
+; CHECK: movl $0, XYZ(%rip)
+; CHECK: movl $1, XYZ(%rip)
+; CHECK-NOT: XYZ
+; CHECK: ret
+
+define void @two() nounwind optsize {
+entry:
+ %0 = icmp eq i32 undef, 0
+ br i1 %0, label %bbx, label %bby
+
+bby:
+ switch i32 undef, label %bb7 [
+ i32 16, label %return
+ ]
+
+bb7:
+ volatile store i32 0, i32* @XYZ
+ volatile store i32 1, i32* @XYZ
+ unreachable
+
+bbx:
+ switch i32 undef, label %bb12 [
+ i32 128, label %return
+ ]
+
+bb12:
+ volatile store i32 0, i32* @XYZ
+ volatile store i32 1, i32* @XYZ
+ unreachable
+
+return:
+ ret void
+}
+
+; two_nosize - Same as two, but without the optsize attribute.
+; Now two instructions are enough to be tail-duplicated.
+
+; CHECK: two_nosize:
+; CHECK: movl $0, XYZ(%rip)
+; CHECK: movl $1, XYZ(%rip)
+; CHECK: movl $0, XYZ(%rip)
+; CHECK: movl $1, XYZ(%rip)
+
+define void @two_nosize() nounwind {
+entry:
+ %0 = icmp eq i32 undef, 0
+ br i1 %0, label %bbx, label %bby
+
+bby:
+ switch i32 undef, label %bb7 [
+ i32 16, label %return
+ ]
+
+bb7:
+ volatile store i32 0, i32* @XYZ
+ volatile store i32 1, i32* @XYZ
+ unreachable
+
+bbx:
+ switch i32 undef, label %bb12 [
+ i32 128, label %return
+ ]
+
+bb12:
+ volatile store i32 0, i32* @XYZ
+ volatile store i32 1, i32* @XYZ
+ unreachable
+
+return:
+ ret void
+}
diff --git a/test/CodeGen/X86/tailcall-fastisel.ll b/test/CodeGen/X86/tailcall-fastisel.ll
new file mode 100644
index 0000000..d54fb41
--- /dev/null
+++ b/test/CodeGen/X86/tailcall-fastisel.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86-64 -tailcallopt -fast-isel | grep TAILCALL
+
+; Fast-isel shouldn't attempt to handle this tail call, and it should
+; cleanly terminate instruction selection in the block after it's
+; done to avoid emitting invalid MachineInstrs.
+
+%0 = type { i64, i32, i8* }
+
+define fastcc i8* @"visit_array_aux<`Reference>"(%0 %arg, i32 %arg1) nounwind {
+fail: ; preds = %entry
+ %tmp20 = tail call fastcc i8* @"visit_array_aux<`Reference>"(%0 %arg, i32 undef) ; <i8*> [#uses=1]
+ ret i8* %tmp20
+}
diff --git a/test/CodeGen/X86/tailcall-i1.ll b/test/CodeGen/X86/tailcall-i1.ll
new file mode 100644
index 0000000..8ef1f11
--- /dev/null
+++ b/test/CodeGen/X86/tailcall-i1.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86 -tailcallopt | grep TAILCALL
+define fastcc i1 @i1test(i32, i32, i32, i32) {
+ entry:
+ %4 = tail call fastcc i1 @i1test( i32 %0, i32 %1, i32 %2, i32 %3)
+ ret i1 %4
+}
diff --git a/test/CodeGen/X86/tailcall-largecode.ll b/test/CodeGen/X86/tailcall-largecode.ll
new file mode 100644
index 0000000..8ddc405
--- /dev/null
+++ b/test/CodeGen/X86/tailcall-largecode.ll
@@ -0,0 +1,71 @@
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -tailcallopt -code-model=large | FileCheck %s
+
+declare fastcc i32 @callee(i32 %arg)
+define fastcc i32 @directcall(i32 %arg) {
+entry:
+; This is the large code model, so &callee may not fit into the jmp
+; instruction. Instead, stick it into a register.
+; CHECK: movabsq $callee, [[REGISTER:%r[a-z0-9]+]]
+; CHECK: jmpq *[[REGISTER]] # TAILCALL
+ %res = tail call fastcc i32 @callee(i32 %arg)
+ ret i32 %res
+}
+
+; Check that the register used for an indirect tail call doesn't
+; clobber any of the arguments.
+define fastcc i32 @indirect_manyargs(i32(i32,i32,i32,i32,i32,i32,i32)* %target) {
+; Adjust the stack to enter the function. (The amount of the
+; adjustment may change in the future, in which case the location of
+; the stack argument and the return adjustment will change too.)
+; CHECK: subq $8, %rsp
+; Put the call target into R11, which won't be clobbered while restoring
+; callee-saved registers and won't be used for passing arguments.
+; CHECK: movq %rdi, %r11
+; Pass the stack argument.
+; CHECK: movl $7, 16(%rsp)
+; Pass the register arguments, in the right registers.
+; CHECK: movl $1, %edi
+; CHECK: movl $2, %esi
+; CHECK: movl $3, %edx
+; CHECK: movl $4, %ecx
+; CHECK: movl $5, %r8d
+; CHECK: movl $6, %r9d
+; Adjust the stack to "return".
+; CHECK: addq $8, %rsp
+; And tail-call to the target.
+; CHECK: jmpq *%r11 # TAILCALL
+ %res = tail call fastcc i32 %target(i32 1, i32 2, i32 3, i32 4, i32 5,
+ i32 6, i32 7)
+ ret i32 %res
+}
+
+; Check that the register used for a direct tail call doesn't clobber
+; any of the arguments.
+declare fastcc i32 @manyargs_callee(i32,i32,i32,i32,i32,i32,i32)
+define fastcc i32 @direct_manyargs() {
+; Adjust the stack to enter the function. (The amount of the
+; adjustment may change in the future, in which case the location of
+; the stack argument and the return adjustment will change too.)
+; CHECK: subq $8, %rsp
+; Pass the stack argument.
+; CHECK: movl $7, 16(%rsp)
+; Pass the register arguments, in the right registers.
+; CHECK: movl $1, %edi
+; CHECK: movl $2, %esi
+; CHECK: movl $3, %edx
+; CHECK: movl $4, %ecx
+; CHECK: movl $5, %r8d
+; CHECK: movl $6, %r9d
+; This is the large code model, so &manyargs_callee may not fit into
+; the jmp instruction. Put it into R11, which won't be clobbered
+; while restoring callee-saved registers and won't be used for passing
+; arguments.
+; CHECK: movabsq $manyargs_callee, %r11
+; Adjust the stack to "return".
+; CHECK: addq $8, %rsp
+; And tail-call to the target.
+; CHECK: jmpq *%r11 # TAILCALL
+ %res = tail call fastcc i32 @manyargs_callee(i32 1, i32 2, i32 3, i32 4,
+ i32 5, i32 6, i32 7)
+ ret i32 %res
+}
diff --git a/test/CodeGen/X86/tailcall-stackalign.ll b/test/CodeGen/X86/tailcall-stackalign.ll
new file mode 100644
index 0000000..0233139
--- /dev/null
+++ b/test/CodeGen/X86/tailcall-stackalign.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -mtriple=i686-unknown-linux -tailcallopt | FileCheck %s
+; Linux has 8 byte alignment so the params cause stack size 20 when tailcallopt
+; is enabled, ensure that a normal fastcc call has matching stack size
+
+
+define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
+ ret i32 %a3
+}
+
+define fastcc i32 @tailcaller(i32 %in1, i32 %in2, i32 %in3, i32 %in4) {
+ %tmp11 = tail call fastcc i32 @tailcallee(i32 %in1, i32 %in2,
+ i32 %in1, i32 %in2)
+ ret i32 %tmp11
+}
+
+define i32 @main(i32 %argc, i8** %argv) {
+ %tmp1 = call fastcc i32 @tailcaller( i32 1, i32 2, i32 3, i32 4 )
+ ; expect match subl [stacksize] here
+ ret i32 0
+}
+
+; CHECK: call tailcaller
+; CHECK-NEXT: subl $12
diff --git a/test/CodeGen/X86/tailcall-structret.ll b/test/CodeGen/X86/tailcall-structret.ll
new file mode 100644
index 0000000..d8be4b2
--- /dev/null
+++ b/test/CodeGen/X86/tailcall-structret.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86 -tailcallopt | grep TAILCALL
+define fastcc { { i8*, i8* }*, i8*} @init({ { i8*, i8* }*, i8*}, i32) {
+entry:
+ %2 = tail call fastcc { { i8*, i8* }*, i8* } @init({ { i8*, i8*}*, i8*} %0, i32 %1)
+ ret { { i8*, i8* }*, i8*} %2
+}
diff --git a/test/CodeGen/X86/tailcall-void.ll b/test/CodeGen/X86/tailcall-void.ll
new file mode 100644
index 0000000..4e578d1
--- /dev/null
+++ b/test/CodeGen/X86/tailcall-void.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86 -tailcallopt | grep TAILCALL
+define fastcc void @i1test(i32, i32, i32, i32) {
+ entry:
+ tail call fastcc void @i1test( i32 %0, i32 %1, i32 %2, i32 %3)
+ ret void
+}
diff --git a/test/CodeGen/X86/tailcall1.ll b/test/CodeGen/X86/tailcall1.ll
new file mode 100644
index 0000000..f7ff5d5
--- /dev/null
+++ b/test/CodeGen/X86/tailcall1.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -march=x86 -tailcallopt | grep TAILCALL | count 5
+
+; With -tailcallopt, CodeGen guarantees a tail call optimization
+; for all of these.
+
+declare fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4)
+
+define fastcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
+entry:
+ %tmp11 = tail call fastcc i32 @tailcallee(i32 %in1, i32 %in2, i32 %in1, i32 %in2)
+ ret i32 %tmp11
+}
+
+declare fastcc i8* @alias_callee()
+
+define fastcc noalias i8* @noalias_caller() nounwind {
+ %p = tail call fastcc i8* @alias_callee()
+ ret i8* %p
+}
+
+declare fastcc noalias i8* @noalias_callee()
+
+define fastcc i8* @alias_caller() nounwind {
+ %p = tail call fastcc noalias i8* @noalias_callee()
+ ret i8* %p
+}
+
+declare fastcc i32 @i32_callee()
+
+define fastcc i32 @ret_undef() nounwind {
+ %p = tail call fastcc i32 @i32_callee()
+ ret i32 undef
+}
+
+declare fastcc void @does_not_return()
+
+define fastcc i32 @noret() nounwind {
+ tail call fastcc void @does_not_return()
+ unreachable
+}
diff --git a/test/CodeGen/X86/tailcall2.ll b/test/CodeGen/X86/tailcall2.ll
new file mode 100644
index 0000000..80bab61
--- /dev/null
+++ b/test/CodeGen/X86/tailcall2.ll
@@ -0,0 +1,197 @@
+; RUN: llc < %s -march=x86 -asm-verbose=false | FileCheck %s -check-prefix=32
+; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s -check-prefix=64
+
+define void @t1(i32 %x) nounwind ssp {
+entry:
+; 32: t1:
+; 32: jmp {{_?}}foo
+
+; 64: t1:
+; 64: jmp {{_?}}foo
+ tail call void @foo() nounwind
+ ret void
+}
+
+declare void @foo()
+
+define void @t2() nounwind ssp {
+entry:
+; 32: t2:
+; 32: jmp {{_?}}foo2
+
+; 64: t2:
+; 64: jmp {{_?}}foo2
+ %0 = tail call i32 @foo2() nounwind
+ ret void
+}
+
+declare i32 @foo2()
+
+define void @t3() nounwind ssp {
+entry:
+; 32: t3:
+; 32: jmp {{_?}}foo3
+
+; 64: t3:
+; 64: jmp {{_?}}foo3
+ %0 = tail call i32 @foo3() nounwind
+ ret void
+}
+
+declare i32 @foo3()
+
+define void @t4(void (i32)* nocapture %x) nounwind ssp {
+entry:
+; 32: t4:
+; 32: call *
+; FIXME: gcc can generate a tailcall for this. But it's tricky.
+
+; 64: t4:
+; 64-NOT: call
+; 64: jmpq *
+ tail call void %x(i32 0) nounwind
+ ret void
+}
+
+define void @t5(void ()* nocapture %x) nounwind ssp {
+entry:
+; 32: t5:
+; 32-NOT: call
+; 32: jmpl *
+
+; 64: t5:
+; 64-NOT: call
+; 64: jmpq *
+ tail call void %x() nounwind
+ ret void
+}
+
+define i32 @t6(i32 %x) nounwind ssp {
+entry:
+; 32: t6:
+; 32: call {{_?}}t6
+; 32: jmp {{_?}}bar
+
+; 64: t6:
+; 64: jmp {{_?}}t6
+; 64: jmp {{_?}}bar
+ %0 = icmp slt i32 %x, 10
+ br i1 %0, label %bb, label %bb1
+
+bb:
+ %1 = add nsw i32 %x, -1
+ %2 = tail call i32 @t6(i32 %1) nounwind ssp
+ ret i32 %2
+
+bb1:
+ %3 = tail call i32 @bar(i32 %x) nounwind
+ ret i32 %3
+}
+
+declare i32 @bar(i32)
+
+define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind ssp {
+entry:
+; 32: t7:
+; 32: jmp {{_?}}bar2
+
+; 64: t7:
+; 64: jmp {{_?}}bar2
+ %0 = tail call i32 @bar2(i32 %a, i32 %b, i32 %c) nounwind
+ ret i32 %0
+}
+
+declare i32 @bar2(i32, i32, i32)
+
+define signext i16 @t8() nounwind ssp {
+entry:
+; 32: t8:
+; 32: call {{_?}}bar3
+
+; 64: t8:
+; 64: callq {{_?}}bar3
+ %0 = tail call signext i16 @bar3() nounwind ; <i16> [#uses=1]
+ ret i16 %0
+}
+
+declare signext i16 @bar3()
+
+define signext i16 @t9(i32 (i32)* nocapture %x) nounwind ssp {
+entry:
+; 32: t9:
+; 32: call *
+
+; 64: t9:
+; 64: callq *
+ %0 = bitcast i32 (i32)* %x to i16 (i32)*
+ %1 = tail call signext i16 %0(i32 0) nounwind
+ ret i16 %1
+}
+
+define void @t10() nounwind ssp {
+entry:
+; 32: t10:
+; 32: call
+
+; 64: t10:
+; 64: callq
+ %0 = tail call i32 @foo4() noreturn nounwind
+ unreachable
+}
+
+declare i32 @foo4()
+
+define i32 @t11(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind ssp {
+; In 32-bit mode, it's emitting a bunch of dead loads that are not being
+; eliminated currently.
+
+; 32: t11:
+; 32-NOT: subl ${{[0-9]+}}, %esp
+; 32: jne
+; 32-NOT: movl
+; 32-NOT: addl ${{[0-9]+}}, %esp
+; 32: jmp {{_?}}foo5
+
+; 64: t11:
+; 64-NOT: subq ${{[0-9]+}}, %esp
+; 64-NOT: addq ${{[0-9]+}}, %esp
+; 64: jmp {{_?}}foo5
+entry:
+ %0 = icmp eq i32 %x, 0
+ br i1 %0, label %bb6, label %bb
+
+bb:
+ %1 = tail call i32 @foo5(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind
+ ret i32 %1
+
+bb6:
+ ret i32 0
+}
+
+declare i32 @foo5(i32, i32, i32, i32, i32)
+
+%struct.t = type { i32, i32, i32, i32, i32 }
+
+define i32 @t12(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind ssp {
+; 32: t12:
+; 32-NOT: subl ${{[0-9]+}}, %esp
+; 32-NOT: addl ${{[0-9]+}}, %esp
+; 32: jmp {{_?}}foo6
+
+; 64: t12:
+; 64-NOT: subq ${{[0-9]+}}, %esp
+; 64-NOT: addq ${{[0-9]+}}, %esp
+; 64: jmp {{_?}}foo6
+entry:
+ %0 = icmp eq i32 %x, 0
+ br i1 %0, label %bb2, label %bb
+
+bb:
+ %1 = tail call i32 @foo6(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind
+ ret i32 %1
+
+bb2:
+ ret i32 0
+}
+
+declare i32 @foo6(i32, i32, %struct.t* byval align 4)
diff --git a/test/CodeGen/X86/tailcallbyval.ll b/test/CodeGen/X86/tailcallbyval.ll
new file mode 100644
index 0000000..7002560
--- /dev/null
+++ b/test/CodeGen/X86/tailcallbyval.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 -tailcallopt | grep TAILCALL
+; RUN: llc < %s -march=x86 -tailcallopt | grep {movl\[\[:space:\]\]*4(%esp), %eax} | count 1
+%struct.s = type {i32, i32, i32, i32, i32, i32, i32, i32,
+ i32, i32, i32, i32, i32, i32, i32, i32,
+ i32, i32, i32, i32, i32, i32, i32, i32 }
+
+define fastcc i32 @tailcallee(%struct.s* byval %a) nounwind {
+entry:
+ %tmp2 = getelementptr %struct.s* %a, i32 0, i32 0
+ %tmp3 = load i32* %tmp2
+ ret i32 %tmp3
+}
+
+define fastcc i32 @tailcaller(%struct.s* byval %a) nounwind {
+entry:
+ %tmp4 = tail call fastcc i32 @tailcallee(%struct.s* %a byval)
+ ret i32 %tmp4
+}
diff --git a/test/CodeGen/X86/tailcallbyval64.ll b/test/CodeGen/X86/tailcallbyval64.ll
new file mode 100644
index 0000000..7c685b8
--- /dev/null
+++ b/test/CodeGen/X86/tailcallbyval64.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=x86-64 -tailcallopt | grep TAILCALL
+; Expect 2 rep;movs because of tail call byval lowering.
+; RUN: llc < %s -march=x86-64 -tailcallopt | grep rep | wc -l | grep 2
+; A sequence of copyto/copyfrom virtual registers is used to deal with byval
+; lowering appearing after moving arguments to registers. The following two
+; checks verify that the register allocator changes those sequences to direct
+; moves to argument register where it can (for registers that are not used in
+; byval lowering - not rsi, not rdi, not rcx).
+; Expect argument 4 to be moved directly to register edx.
+; RUN: llc < %s -march=x86-64 -tailcallopt | grep movl | grep {7} | grep edx
+; Expect argument 6 to be moved directly to register r8.
+; RUN: llc < %s -march=x86-64 -tailcallopt | grep movl | grep {17} | grep r8
+
+%struct.s = type { i64, i64, i64, i64, i64, i64, i64, i64,
+ i64, i64, i64, i64, i64, i64, i64, i64,
+ i64, i64, i64, i64, i64, i64, i64, i64 }
+
+declare fastcc i64 @tailcallee(%struct.s* byval %a, i64 %val, i64 %val2, i64 %val3, i64 %val4, i64 %val5)
+
+
+define fastcc i64 @tailcaller(i64 %b, %struct.s* byval %a) {
+entry:
+ %tmp2 = getelementptr %struct.s* %a, i32 0, i32 1
+ %tmp3 = load i64* %tmp2, align 8
+ %tmp4 = tail call fastcc i64 @tailcallee(%struct.s* %a byval, i64 %tmp3, i64 %b, i64 7, i64 13, i64 17)
+ ret i64 %tmp4
+}
+
+
diff --git a/test/CodeGen/X86/tailcallfp.ll b/test/CodeGen/X86/tailcallfp.ll
new file mode 100644
index 0000000..c0b609a
--- /dev/null
+++ b/test/CodeGen/X86/tailcallfp.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -tailcallopt | not grep call
+define fastcc i32 @bar(i32 %X, i32(double, i32) *%FP) {
+ %Y = tail call fastcc i32 %FP(double 0.0, i32 %X)
+ ret i32 %Y
+}
diff --git a/test/CodeGen/X86/tailcallfp2.ll b/test/CodeGen/X86/tailcallfp2.ll
new file mode 100644
index 0000000..3841f51
--- /dev/null
+++ b/test/CodeGen/X86/tailcallfp2.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86 -tailcallopt | grep {jmp} | grep {\\*%eax}
+
+declare i32 @putchar(i32)
+
+define fastcc i32 @checktail(i32 %x, i32* %f, i32 %g) nounwind {
+ %tmp1 = icmp sgt i32 %x, 0
+ br i1 %tmp1, label %if-then, label %if-else
+
+if-then:
+ %fun_ptr = bitcast i32* %f to i32(i32, i32*, i32)*
+ %arg1 = add i32 %x, -1
+ call i32 @putchar(i32 90)
+ %res = tail call fastcc i32 %fun_ptr( i32 %arg1, i32 * %f, i32 %g)
+ ret i32 %res
+
+if-else:
+ ret i32 %x
+}
+
+
+define i32 @main() nounwind {
+ %f = bitcast i32 (i32, i32*, i32)* @checktail to i32*
+ %res = tail call fastcc i32 @checktail( i32 10, i32* %f,i32 10)
+ ret i32 %res
+}
diff --git a/test/CodeGen/X86/tailcallpic1.ll b/test/CodeGen/X86/tailcallpic1.ll
new file mode 100644
index 0000000..60e3be5
--- /dev/null
+++ b/test/CodeGen/X86/tailcallpic1.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -tailcallopt -mtriple=i686-pc-linux-gnu -relocation-model=pic | grep TAILCALL
+
+define protected fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
+entry:
+ ret i32 %a3
+}
+
+define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
+entry:
+ %tmp11 = tail call fastcc i32 @tailcallee( i32 %in1, i32 %in2, i32 %in1, i32 %in2 ) ; <i32> [#uses=1]
+ ret i32 %tmp11
+}
diff --git a/test/CodeGen/X86/tailcallpic2.ll b/test/CodeGen/X86/tailcallpic2.ll
new file mode 100644
index 0000000..eaa7631
--- /dev/null
+++ b/test/CodeGen/X86/tailcallpic2.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -tailcallopt -mtriple=i686-pc-linux-gnu -relocation-model=pic | grep -v TAILCALL
+
+define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
+entry:
+ ret i32 %a3
+}
+
+define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
+entry:
+ %tmp11 = tail call fastcc i32 @tailcallee( i32 %in1, i32 %in2, i32 %in1, i32 %in2 ) ; <i32> [#uses=1]
+ ret i32 %tmp11
+}
diff --git a/test/CodeGen/X86/tailcallstack64.ll b/test/CodeGen/X86/tailcallstack64.ll
new file mode 100644
index 0000000..d05dff8
--- /dev/null
+++ b/test/CodeGen/X86/tailcallstack64.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -tailcallopt -march=x86-64 -post-RA-scheduler=true | FileCheck %s
+
+; Check that lowered arguments on the stack do not overwrite each other.
+; Add %in1 %p1 to a different temporary register (%eax).
+; CHECK: movl %edi, %eax
+; Move param %in1 to temp register (%r10d).
+; CHECK: movl 40(%rsp), %r10d
+; Move param %in2 to stack.
+; CHECK: movl %r10d, 32(%rsp)
+; Move result of addition to stack.
+; CHECK: movl %eax, 40(%rsp)
+; Eventually, do a TAILCALL
+; CHECK: TAILCALL
+
+declare fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %a, i32 %b) nounwind
+
+define fastcc i32 @tailcaller(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in1, i32 %in2) nounwind {
+entry:
+ %tmp = add i32 %in1, %p1
+ %retval = tail call fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in2,i32 %tmp)
+ ret i32 %retval
+}
+
diff --git a/test/CodeGen/X86/test-nofold.ll b/test/CodeGen/X86/test-nofold.ll
new file mode 100644
index 0000000..f1063dc
--- /dev/null
+++ b/test/CodeGen/X86/test-nofold.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
+; rdar://5752025
+
+; We want:
+; CHECK: movl 4(%esp), %ecx
+; CHECK-NEXT: andl $15, %ecx
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: cmovel %ecx, %eax
+; CHECK-NEXT: ret
+;
+; We don't want:
+; movl 4(%esp), %eax
+; movl %eax, %ecx # bad: extra copy
+; andl $15, %ecx
+; testl $15, %eax # bad: peep obstructed
+; movl $42, %eax
+; cmovel %ecx, %eax
+; ret
+;
+; We also don't want:
+; movl $15, %ecx # bad: larger encoding
+; andl 4(%esp), %ecx
+; movl $42, %eax
+; cmovel %ecx, %eax
+; ret
+;
+; We also don't want:
+; movl 4(%esp), %ecx
+; andl $15, %ecx
+; testl %ecx, %ecx # bad: unnecessary test
+; movl $42, %eax
+; cmovel %ecx, %eax
+; ret
+
+define i32 @t1(i32 %X) nounwind {
+entry:
+ %tmp2 = and i32 %X, 15 ; <i32> [#uses=2]
+ %tmp4 = icmp eq i32 %tmp2, 0 ; <i1> [#uses=1]
+ %retval = select i1 %tmp4, i32 %tmp2, i32 42 ; <i32> [#uses=1]
+ ret i32 %retval
+}
+
diff --git a/test/CodeGen/X86/test-shrink-bug.ll b/test/CodeGen/X86/test-shrink-bug.ll
new file mode 100644
index 0000000..64631ea
--- /dev/null
+++ b/test/CodeGen/X86/test-shrink-bug.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s | FileCheck %s
+
+; Codegen shouldn't reduce the comparison down to testb $-1, %al
+; because that changes the result of the signed test.
+; PR5132
+; CHECK: testw $255, %ax
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin10.0"
+
+@g_14 = global i8 -6, align 1 ; <i8*> [#uses=1]
+
+declare i32 @func_16(i8 signext %p_19, i32 %p_20) nounwind
+
+define i32 @func_35(i64 %p_38) nounwind ssp {
+entry:
+ %tmp = load i8* @g_14 ; <i8> [#uses=2]
+ %conv = zext i8 %tmp to i32 ; <i32> [#uses=1]
+ %cmp = icmp sle i32 1, %conv ; <i1> [#uses=1]
+ %conv2 = zext i1 %cmp to i32 ; <i32> [#uses=1]
+ %call = call i32 @func_16(i8 signext %tmp, i32 %conv2) ssp ; <i32> [#uses=1]
+ ret i32 1
+}
diff --git a/test/CodeGen/X86/test-shrink.ll b/test/CodeGen/X86/test-shrink.ll
new file mode 100644
index 0000000..1d63693
--- /dev/null
+++ b/test/CodeGen/X86/test-shrink.ll
@@ -0,0 +1,158 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32
+
+; CHECK-64: g64xh:
+; CHECK-64: testb $8, %ah
+; CHECK-64: ret
+; CHECK-32: g64xh:
+; CHECK-32: testb $8, %ah
+; CHECK-32: ret
+define void @g64xh(i64 inreg %x) nounwind {
+ %t = and i64 %x, 2048
+ %s = icmp eq i64 %t, 0
+ br i1 %s, label %yes, label %no
+
+yes:
+ call void @bar()
+ ret void
+no:
+ ret void
+}
+; CHECK-64: g64xl:
+; CHECK-64: testb $8, %dil
+; CHECK-64: ret
+; CHECK-32: g64xl:
+; CHECK-32: testb $8, %al
+; CHECK-32: ret
+define void @g64xl(i64 inreg %x) nounwind {
+ %t = and i64 %x, 8
+ %s = icmp eq i64 %t, 0
+ br i1 %s, label %yes, label %no
+
+yes:
+ call void @bar()
+ ret void
+no:
+ ret void
+}
+; CHECK-64: g32xh:
+; CHECK-64: testb $8, %ah
+; CHECK-64: ret
+; CHECK-32: g32xh:
+; CHECK-32: testb $8, %ah
+; CHECK-32: ret
+define void @g32xh(i32 inreg %x) nounwind {
+ %t = and i32 %x, 2048
+ %s = icmp eq i32 %t, 0
+ br i1 %s, label %yes, label %no
+
+yes:
+ call void @bar()
+ ret void
+no:
+ ret void
+}
+; CHECK-64: g32xl:
+; CHECK-64: testb $8, %dil
+; CHECK-64: ret
+; CHECK-32: g32xl:
+; CHECK-32: testb $8, %al
+; CHECK-32: ret
+define void @g32xl(i32 inreg %x) nounwind {
+ %t = and i32 %x, 8
+ %s = icmp eq i32 %t, 0
+ br i1 %s, label %yes, label %no
+
+yes:
+ call void @bar()
+ ret void
+no:
+ ret void
+}
+; CHECK-64: g16xh:
+; CHECK-64: testb $8, %ah
+; CHECK-64: ret
+; CHECK-32: g16xh:
+; CHECK-32: testb $8, %ah
+; CHECK-32: ret
+define void @g16xh(i16 inreg %x) nounwind {
+ %t = and i16 %x, 2048
+ %s = icmp eq i16 %t, 0
+ br i1 %s, label %yes, label %no
+
+yes:
+ call void @bar()
+ ret void
+no:
+ ret void
+}
+; CHECK-64: g16xl:
+; CHECK-64: testb $8, %dil
+; CHECK-64: ret
+; CHECK-32: g16xl:
+; CHECK-32: testb $8, %al
+; CHECK-32: ret
+define void @g16xl(i16 inreg %x) nounwind {
+ %t = and i16 %x, 8
+ %s = icmp eq i16 %t, 0
+ br i1 %s, label %yes, label %no
+
+yes:
+ call void @bar()
+ ret void
+no:
+ ret void
+}
+; CHECK-64: g64x16:
+; CHECK-64: testw $-32640, %di
+; CHECK-64: ret
+; CHECK-32: g64x16:
+; CHECK-32: testw $-32640, %ax
+; CHECK-32: ret
+define void @g64x16(i64 inreg %x) nounwind {
+ %t = and i64 %x, 32896
+ %s = icmp eq i64 %t, 0
+ br i1 %s, label %yes, label %no
+
+yes:
+ call void @bar()
+ ret void
+no:
+ ret void
+}
+; CHECK-64: g32x16:
+; CHECK-64: testw $-32640, %di
+; CHECK-64: ret
+; CHECK-32: g32x16:
+; CHECK-32: testw $-32640, %ax
+; CHECK-32: ret
+define void @g32x16(i32 inreg %x) nounwind {
+ %t = and i32 %x, 32896
+ %s = icmp eq i32 %t, 0
+ br i1 %s, label %yes, label %no
+
+yes:
+ call void @bar()
+ ret void
+no:
+ ret void
+}
+; CHECK-64: g64x32:
+; CHECK-64: testl $268468352, %edi
+; CHECK-64: ret
+; CHECK-32: g64x32:
+; CHECK-32: testl $268468352, %eax
+; CHECK-32: ret
+define void @g64x32(i64 inreg %x) nounwind {
+ %t = and i64 %x, 268468352
+ %s = icmp eq i64 %t, 0
+ br i1 %s, label %yes, label %no
+
+yes:
+ call void @bar()
+ ret void
+no:
+ ret void
+}
+
+declare void @bar()
diff --git a/test/CodeGen/X86/testl-commute.ll b/test/CodeGen/X86/testl-commute.ll
new file mode 100644
index 0000000..3d5f672
--- /dev/null
+++ b/test/CodeGen/X86/testl-commute.ll
@@ -0,0 +1,56 @@
+; RUN: llc < %s | grep {testl.*\(%r.i\), %} | count 3
+; rdar://5671654
+; The loads should fold into the testl instructions, no matter how
+; the inputs are commuted.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin7"
+
+define i32 @test(i32* %P, i32* %G) nounwind {
+entry:
+ %0 = load i32* %P, align 4 ; <i32> [#uses=3]
+ %1 = load i32* %G, align 4 ; <i32> [#uses=1]
+ %2 = and i32 %1, %0 ; <i32> [#uses=1]
+ %3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
+ br i1 %3, label %bb1, label %bb
+
+bb: ; preds = %entry
+ %4 = tail call i32 @bar() nounwind ; <i32> [#uses=0]
+ ret i32 %0
+
+bb1: ; preds = %entry
+ ret i32 %0
+}
+
+define i32 @test2(i32* %P, i32* %G) nounwind {
+entry:
+ %0 = load i32* %P, align 4 ; <i32> [#uses=3]
+ %1 = load i32* %G, align 4 ; <i32> [#uses=1]
+ %2 = and i32 %0, %1 ; <i32> [#uses=1]
+ %3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
+ br i1 %3, label %bb1, label %bb
+
+bb: ; preds = %entry
+ %4 = tail call i32 @bar() nounwind ; <i32> [#uses=0]
+ ret i32 %0
+
+bb1: ; preds = %entry
+ ret i32 %0
+}
+define i32 @test3(i32* %P, i32* %G) nounwind {
+entry:
+ %0 = load i32* %P, align 4 ; <i32> [#uses=3]
+ %1 = load i32* %G, align 4 ; <i32> [#uses=1]
+ %2 = and i32 %0, %1 ; <i32> [#uses=1]
+ %3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
+ br i1 %3, label %bb1, label %bb
+
+bb: ; preds = %entry
+ %4 = tail call i32 @bar() nounwind ; <i32> [#uses=0]
+ ret i32 %1
+
+bb1: ; preds = %entry
+ ret i32 %1
+}
+
+declare i32 @bar()
diff --git a/test/CodeGen/X86/tls-pic.ll b/test/CodeGen/X86/tls-pic.ll
new file mode 100644
index 0000000..4cad837
--- /dev/null
+++ b/test/CodeGen/X86/tls-pic.ll
@@ -0,0 +1,67 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -relocation-model=pic | FileCheck -check-prefix=X32 %s
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -relocation-model=pic | FileCheck -check-prefix=X64 %s
+
+@i = thread_local global i32 15
+
+define i32 @f1() {
+entry:
+ %tmp1 = load i32* @i
+ ret i32 %tmp1
+}
+
+; X32: f1:
+; X32: leal i@TLSGD(,%ebx), %eax
+; X32: call ___tls_get_addr@PLT
+
+; X64: f1:
+; X64: leaq i@TLSGD(%rip), %rdi
+; X64: call __tls_get_addr@PLT
+
+
+@i2 = external thread_local global i32
+
+define i32* @f2() {
+entry:
+ ret i32* @i
+}
+
+; X32: f2:
+; X32: leal i@TLSGD(,%ebx), %eax
+; X32: call ___tls_get_addr@PLT
+
+; X64: f2:
+; X64: leaq i@TLSGD(%rip), %rdi
+; X64: call __tls_get_addr@PLT
+
+
+
+define i32 @f3() {
+entry:
+ %tmp1 = load i32* @i ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
+
+; X32: f3:
+; X32: leal i@TLSGD(,%ebx), %eax
+; X32: call ___tls_get_addr@PLT
+
+; X64: f3:
+; X64: leaq i@TLSGD(%rip), %rdi
+; X64: call __tls_get_addr@PLT
+
+
+define i32* @f4() nounwind {
+entry:
+ ret i32* @i
+}
+
+; X32: f4:
+; X32: leal i@TLSGD(,%ebx), %eax
+; X32: call ___tls_get_addr@PLT
+
+; X64: f4:
+; X64: leaq i@TLSGD(%rip), %rdi
+; X64: call __tls_get_addr@PLT
+
+
+
diff --git a/test/CodeGen/X86/tls1.ll b/test/CodeGen/X86/tls1.ll
new file mode 100644
index 0000000..0cae5c4
--- /dev/null
+++ b/test/CodeGen/X86/tls1.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movl %gs:i@NTPOFF, %eax} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movl %fs:i@TPOFF, %eax} %t2
+
+@i = thread_local global i32 15
+
+define i32 @f() nounwind {
+entry:
+ %tmp1 = load i32* @i
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/X86/tls10.ll b/test/CodeGen/X86/tls10.ll
new file mode 100644
index 0000000..fb61596
--- /dev/null
+++ b/test/CodeGen/X86/tls10.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movl %gs:0, %eax} %t
+; RUN: grep {leal i@NTPOFF(%eax), %eax} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movq %fs:0, %rax} %t2
+; RUN: grep {leaq i@TPOFF(%rax), %rax} %t2
+
+@i = external hidden thread_local global i32
+
+define i32* @f() {
+entry:
+ ret i32* @i
+}
diff --git a/test/CodeGen/X86/tls11.ll b/test/CodeGen/X86/tls11.ll
new file mode 100644
index 0000000..a2c1a1f
--- /dev/null
+++ b/test/CodeGen/X86/tls11.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movw %gs:i@NTPOFF, %ax} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movw %fs:i@TPOFF, %ax} %t2
+
+@i = thread_local global i16 15
+
+define i16 @f() {
+entry:
+ %tmp1 = load i16* @i
+ ret i16 %tmp1
+}
diff --git a/test/CodeGen/X86/tls12.ll b/test/CodeGen/X86/tls12.ll
new file mode 100644
index 0000000..c29f6ad
--- /dev/null
+++ b/test/CodeGen/X86/tls12.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movb %gs:i@NTPOFF, %al} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movb %fs:i@TPOFF, %al} %t2
+
+@i = thread_local global i8 15
+
+define i8 @f() {
+entry:
+ %tmp1 = load i8* @i
+ ret i8 %tmp1
+}
diff --git a/test/CodeGen/X86/tls13.ll b/test/CodeGen/X86/tls13.ll
new file mode 100644
index 0000000..08778ec
--- /dev/null
+++ b/test/CodeGen/X86/tls13.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movswl %gs:i@NTPOFF, %eax} %t
+; RUN: grep {movzwl %gs:j@NTPOFF, %eax} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movswl %fs:i@TPOFF, %edi} %t2
+; RUN: grep {movzwl %fs:j@TPOFF, %edi} %t2
+
+@i = thread_local global i16 0
+@j = thread_local global i16 0
+
+define void @f() nounwind optsize {
+entry:
+ %0 = load i16* @i, align 2
+ %1 = sext i16 %0 to i32
+ tail call void @g(i32 %1) nounwind
+ %2 = load i16* @j, align 2
+ %3 = zext i16 %2 to i32
+ tail call void @h(i32 %3) nounwind
+ ret void
+}
+
+declare void @g(i32)
+
+declare void @h(i32)
diff --git a/test/CodeGen/X86/tls14.ll b/test/CodeGen/X86/tls14.ll
new file mode 100644
index 0000000..88426dd
--- /dev/null
+++ b/test/CodeGen/X86/tls14.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movsbl %gs:i@NTPOFF, %eax} %t
+; RUN: grep {movzbl %gs:j@NTPOFF, %eax} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movsbl %fs:i@TPOFF, %edi} %t2
+; RUN: grep {movzbl %fs:j@TPOFF, %edi} %t2
+
+@i = thread_local global i8 0
+@j = thread_local global i8 0
+
+define void @f() nounwind optsize {
+entry:
+ %0 = load i8* @i, align 2
+ %1 = sext i8 %0 to i32
+ tail call void @g(i32 %1) nounwind
+ %2 = load i8* @j, align 2
+ %3 = zext i8 %2 to i32
+ tail call void @h(i32 %3) nounwind
+ ret void
+}
+
+declare void @g(i32)
+
+declare void @h(i32)
diff --git a/test/CodeGen/X86/tls15.ll b/test/CodeGen/X86/tls15.ll
new file mode 100644
index 0000000..7abf070
--- /dev/null
+++ b/test/CodeGen/X86/tls15.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movl %gs:0, %eax} %t | count 1
+; RUN: grep {leal i@NTPOFF(%eax), %ecx} %t
+; RUN: grep {leal j@NTPOFF(%eax), %eax} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movq %fs:0, %rax} %t2 | count 1
+; RUN: grep {leaq i@TPOFF(%rax), %rcx} %t2
+; RUN: grep {leaq j@TPOFF(%rax), %rax} %t2
+
+@i = thread_local global i32 0
+@j = thread_local global i32 0
+
+define void @f(i32** %a, i32** %b) {
+entry:
+ store i32* @i, i32** %a, align 8
+ store i32* @j, i32** %b, align 8
+ ret void
+}
diff --git a/test/CodeGen/X86/tls2.ll b/test/CodeGen/X86/tls2.ll
new file mode 100644
index 0000000..5a94296
--- /dev/null
+++ b/test/CodeGen/X86/tls2.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movl %gs:0, %eax} %t
+; RUN: grep {leal i@NTPOFF(%eax), %eax} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movq %fs:0, %rax} %t2
+; RUN: grep {leaq i@TPOFF(%rax), %rax} %t2
+
+@i = thread_local global i32 15
+
+define i32* @f() {
+entry:
+ ret i32* @i
+}
diff --git a/test/CodeGen/X86/tls3.ll b/test/CodeGen/X86/tls3.ll
new file mode 100644
index 0000000..7327cc4
--- /dev/null
+++ b/test/CodeGen/X86/tls3.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movl i@INDNTPOFF, %eax} %t
+; RUN: grep {movl %gs:(%eax), %eax} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movq i@GOTTPOFF(%rip), %rax} %t2
+; RUN: grep {movl %fs:(%rax), %eax} %t2
+
+@i = external thread_local global i32 ; <i32*> [#uses=2]
+
+define i32 @f() nounwind {
+entry:
+ %tmp1 = load i32* @i ; <i32> [#uses=1]
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/X86/tls4.ll b/test/CodeGen/X86/tls4.ll
new file mode 100644
index 0000000..d2e40e3
--- /dev/null
+++ b/test/CodeGen/X86/tls4.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movl %gs:0, %eax} %t
+; RUN: grep {addl i@INDNTPOFF, %eax} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movq %fs:0, %rax} %t2
+; RUN: grep {addq i@GOTTPOFF(%rip), %rax} %t2
+
+@i = external thread_local global i32 ; <i32*> [#uses=2]
+
+define i32* @f() {
+entry:
+ ret i32* @i
+}
diff --git a/test/CodeGen/X86/tls5.ll b/test/CodeGen/X86/tls5.ll
new file mode 100644
index 0000000..4d2cc02
--- /dev/null
+++ b/test/CodeGen/X86/tls5.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movl %gs:i@NTPOFF, %eax} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movl %fs:i@TPOFF, %eax} %t2
+
+@i = internal thread_local global i32 15
+
+define i32 @f() {
+entry:
+ %tmp1 = load i32* @i
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/X86/tls6.ll b/test/CodeGen/X86/tls6.ll
new file mode 100644
index 0000000..505106e
--- /dev/null
+++ b/test/CodeGen/X86/tls6.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movl %gs:0, %eax} %t
+; RUN: grep {leal i@NTPOFF(%eax), %eax} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movq %fs:0, %rax} %t2
+; RUN: grep {leaq i@TPOFF(%rax), %rax} %t2
+
+@i = internal thread_local global i32 15
+
+define i32* @f() {
+entry:
+ ret i32* @i
+}
diff --git a/test/CodeGen/X86/tls7.ll b/test/CodeGen/X86/tls7.ll
new file mode 100644
index 0000000..e9116e7
--- /dev/null
+++ b/test/CodeGen/X86/tls7.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movl %gs:i@NTPOFF, %eax} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movl %fs:i@TPOFF, %eax} %t2
+
+@i = hidden thread_local global i32 15
+
+define i32 @f() {
+entry:
+ %tmp1 = load i32* @i
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/X86/tls8.ll b/test/CodeGen/X86/tls8.ll
new file mode 100644
index 0000000..375af94
--- /dev/null
+++ b/test/CodeGen/X86/tls8.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movl %gs:0, %eax} %t
+; RUN: grep {leal i@NTPOFF(%eax), %eax} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movq %fs:0, %rax} %t2
+; RUN: grep {leaq i@TPOFF(%rax), %rax} %t2
+
+@i = hidden thread_local global i32 15
+
+define i32* @f() {
+entry:
+ ret i32* @i
+}
diff --git a/test/CodeGen/X86/tls9.ll b/test/CodeGen/X86/tls9.ll
new file mode 100644
index 0000000..214146f
--- /dev/null
+++ b/test/CodeGen/X86/tls9.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
+; RUN: grep {movl %gs:i@NTPOFF, %eax} %t
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
+; RUN: grep {movl %fs:i@TPOFF, %eax} %t2
+
+@i = external hidden thread_local global i32
+
+define i32 @f() {
+entry:
+ %tmp1 = load i32* @i
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/X86/trap.ll b/test/CodeGen/X86/trap.ll
new file mode 100644
index 0000000..03ae6bfc
--- /dev/null
+++ b/test/CodeGen/X86/trap.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah | grep ud2
+define i32 @test() noreturn nounwind {
+entry:
+ tail call void @llvm.trap( )
+ unreachable
+}
+
+declare void @llvm.trap() nounwind
+
diff --git a/test/CodeGen/X86/trunc-to-bool.ll b/test/CodeGen/X86/trunc-to-bool.ll
new file mode 100644
index 0000000..bfab1ae
--- /dev/null
+++ b/test/CodeGen/X86/trunc-to-bool.ll
@@ -0,0 +1,54 @@
+; An integer truncation to i1 should be done with an and instruction to make
+; sure only the LSBit survives. Test that this is the case both for a returned
+; value and as the operand of a branch.
+; RUN: llc < %s -march=x86 | FileCheck %s
+
+define i1 @test1(i32 %X) zeroext {
+ %Y = trunc i32 %X to i1
+ ret i1 %Y
+}
+; CHECK: andl $1, %eax
+
+define i1 @test2(i32 %val, i32 %mask) {
+entry:
+ %shifted = ashr i32 %val, %mask
+ %anded = and i32 %shifted, 1
+ %trunced = trunc i32 %anded to i1
+ br i1 %trunced, label %ret_true, label %ret_false
+ret_true:
+ ret i1 true
+ret_false:
+ ret i1 false
+}
+; CHECK: testb $1, %al
+
+define i32 @test3(i8* %ptr) {
+ %val = load i8* %ptr
+ %tmp = trunc i8 %val to i1
+ br i1 %tmp, label %cond_true, label %cond_false
+cond_true:
+ ret i32 21
+cond_false:
+ ret i32 42
+}
+; CHECK: testb $1, %al
+
+define i32 @test4(i8* %ptr) {
+ %tmp = ptrtoint i8* %ptr to i1
+ br i1 %tmp, label %cond_true, label %cond_false
+cond_true:
+ ret i32 21
+cond_false:
+ ret i32 42
+}
+; CHECK: testb $1, %al
+
+define i32 @test6(double %d) {
+ %tmp = fptosi double %d to i1
+ br i1 %tmp, label %cond_true, label %cond_false
+cond_true:
+ ret i32 21
+cond_false:
+ ret i32 42
+}
+; CHECK: testb $1
diff --git a/test/CodeGen/X86/twoaddr-coalesce-2.ll b/test/CodeGen/X86/twoaddr-coalesce-2.ll
new file mode 100644
index 0000000..6f16a25
--- /dev/null
+++ b/test/CodeGen/X86/twoaddr-coalesce-2.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -stats |& \
+; RUN: grep {twoaddrinstr} | grep {Number of instructions aggressively commuted}
+; rdar://6480363
+
+target triple = "i386-apple-darwin9.6"
+
+define <2 x double> @t(<2 x double> %A, <2 x double> %B, <2 x double> %C) nounwind readnone {
+entry:
+ %tmp.i3 = bitcast <2 x double> %B to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp2.i = or <2 x i64> %tmp.i3, <i64 4607632778762754458, i64 4607632778762754458> ; <<2 x i64>> [#uses=1]
+ %tmp3.i = bitcast <2 x i64> %tmp2.i to <2 x double> ; <<2 x double>> [#uses=1]
+ %tmp.i2 = fadd <2 x double> %tmp3.i, %A ; <<2 x double>> [#uses=1]
+ %tmp.i = fadd <2 x double> %tmp.i2, %C ; <<2 x double>> [#uses=1]
+ ret <2 x double> %tmp.i
+}
diff --git a/test/CodeGen/X86/twoaddr-coalesce.ll b/test/CodeGen/X86/twoaddr-coalesce.ll
new file mode 100644
index 0000000..d0e13f6
--- /dev/null
+++ b/test/CodeGen/X86/twoaddr-coalesce.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 | grep mov | count 5
+; rdar://6523745
+
+@"\01LC" = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1]
+
+define i32 @main() nounwind {
+bb1.thread:
+ br label %bb1
+
+bb1: ; preds = %bb1, %bb1.thread
+ %i.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %indvar.next, %bb1 ] ; <i32> [#uses=2]
+ %0 = trunc i32 %i.0.reg2mem.0 to i8 ; <i8> [#uses=1]
+ %1 = sdiv i8 %0, 2 ; <i8> [#uses=1]
+ %2 = sext i8 %1 to i32 ; <i32> [#uses=1]
+ %3 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i32 0), i32 %2) nounwind ; <i32> [#uses=0]
+ %indvar.next = add i32 %i.0.reg2mem.0, 1 ; <i32> [#uses=2]
+ %exitcond = icmp eq i32 %indvar.next, 258 ; <i1> [#uses=1]
+ br i1 %exitcond, label %bb2, label %bb1
+
+bb2: ; preds = %bb1
+ ret i32 0
+}
+
+declare i32 @printf(i8*, ...) nounwind
diff --git a/test/CodeGen/X86/twoaddr-lea.ll b/test/CodeGen/X86/twoaddr-lea.ll
new file mode 100644
index 0000000..a245ed7
--- /dev/null
+++ b/test/CodeGen/X86/twoaddr-lea.ll
@@ -0,0 +1,24 @@
+;; X's live range extends beyond the shift, so the register allocator
+;; cannot coalesce it with Y. Because of this, a copy needs to be
+;; emitted before the shift to save the register value before it is
+;; clobbered. However, this copy is not needed if the register
+;; allocator turns the shift into an LEA. This also occurs for ADD.
+
+; Check that the shift gets turned into an LEA.
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
+; RUN: not grep {mov E.X, E.X}
+
+@G = external global i32 ; <i32*> [#uses=3]
+
+define i32 @test1(i32 %X, i32 %Y) {
+ %Z = add i32 %X, %Y ; <i32> [#uses=1]
+ volatile store i32 %Y, i32* @G
+ volatile store i32 %Z, i32* @G
+ ret i32 %X
+}
+
+define i32 @test2(i32 %X) {
+ %Z = add i32 %X, 1 ; <i32> [#uses=1]
+ volatile store i32 %Z, i32* @G
+ ret i32 %X
+}
diff --git a/test/CodeGen/X86/twoaddr-pass-sink.ll b/test/CodeGen/X86/twoaddr-pass-sink.ll
new file mode 100644
index 0000000..077fee0
--- /dev/null
+++ b/test/CodeGen/X86/twoaddr-pass-sink.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -stats |& grep {Number of 3-address instructions sunk}
+
+define void @t2(<2 x i64>* %vDct, <2 x i64>* %vYp, i8* %skiplist, <2 x i64> %a1) nounwind {
+entry:
+ %tmp25 = bitcast <2 x i64> %a1 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ br label %bb
+bb: ; preds = %bb, %entry
+ %skiplist_addr.0.rec = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
+ %vYp_addr.0.rec = shl i32 %skiplist_addr.0.rec, 3 ; <i32> [#uses=3]
+ %vDct_addr.0 = getelementptr <2 x i64>* %vDct, i32 %vYp_addr.0.rec ; <<2 x i64>*> [#uses=1]
+ %vYp_addr.0 = getelementptr <2 x i64>* %vYp, i32 %vYp_addr.0.rec ; <<2 x i64>*> [#uses=1]
+ %skiplist_addr.0 = getelementptr i8* %skiplist, i32 %skiplist_addr.0.rec ; <i8*> [#uses=1]
+ %vDct_addr.0.sum43 = or i32 %vYp_addr.0.rec, 1 ; <i32> [#uses=1]
+ %tmp7 = getelementptr <2 x i64>* %vDct, i32 %vDct_addr.0.sum43 ; <<2 x i64>*> [#uses=1]
+ %tmp8 = load <2 x i64>* %tmp7, align 16 ; <<2 x i64>> [#uses=1]
+ %tmp11 = load <2 x i64>* %vDct_addr.0, align 16 ; <<2 x i64>> [#uses=1]
+ %tmp13 = bitcast <2 x i64> %tmp8 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp15 = bitcast <2 x i64> %tmp11 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp16 = shufflevector <8 x i16> %tmp15, <8 x i16> %tmp13, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1]
+ %tmp26 = mul <8 x i16> %tmp25, %tmp16 ; <<8 x i16>> [#uses=1]
+ %tmp27 = bitcast <8 x i16> %tmp26 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ store <2 x i64> %tmp27, <2 x i64>* %vYp_addr.0, align 16
+ %tmp37 = load i8* %skiplist_addr.0, align 1 ; <i8> [#uses=1]
+ %tmp38 = icmp eq i8 %tmp37, 0 ; <i1> [#uses=1]
+ %indvar.next = add i32 %skiplist_addr.0.rec, 1 ; <i32> [#uses=1]
+ br i1 %tmp38, label %return, label %bb
+return: ; preds = %bb
+ ret void
+}
diff --git a/test/CodeGen/X86/twoaddr-remat.ll b/test/CodeGen/X86/twoaddr-remat.ll
new file mode 100644
index 0000000..4940c78
--- /dev/null
+++ b/test/CodeGen/X86/twoaddr-remat.ll
@@ -0,0 +1,67 @@
+; RUN: llc < %s -march=x86 | grep 59796 | count 3
+
+ %Args = type %Value*
+ %Exec = type opaque*
+ %Identifier = type opaque*
+ %JSFunction = type %Value (%Exec, %Scope, %Value, %Args)
+ %PropertyNameArray = type opaque*
+ %Scope = type opaque*
+ %Value = type opaque*
+
+declare i1 @X1(%Exec) readonly
+
+declare %Value @X2(%Exec)
+
+declare i32 @X3(%Exec, %Value)
+
+declare %Value @X4(i32) readnone
+
+define internal %Value @fast3bitlookup(%Exec %exec, %Scope %scope, %Value %this, %Args %args) nounwind {
+prologue:
+ %eh_check = tail call i1 @X1( %Exec %exec ) readonly ; <i1> [#uses=1]
+ br i1 %eh_check, label %exception, label %no_exception
+
+exception: ; preds = %no_exception, %prologue
+ %rethrow_result = tail call %Value @X2( %Exec %exec ) ; <%Value> [#uses=1]
+ ret %Value %rethrow_result
+
+no_exception: ; preds = %prologue
+ %args_intptr = bitcast %Args %args to i32* ; <i32*> [#uses=1]
+ %argc_val = load i32* %args_intptr ; <i32> [#uses=1]
+ %cmpParamArgc = icmp sgt i32 %argc_val, 0 ; <i1> [#uses=1]
+ %arg_ptr = getelementptr %Args %args, i32 1 ; <%Args> [#uses=1]
+ %arg_val = load %Args %arg_ptr ; <%Value> [#uses=1]
+ %ext_arg_val = select i1 %cmpParamArgc, %Value %arg_val, %Value inttoptr (i32 5 to %Value) ; <%Value> [#uses=1]
+ %toInt325 = tail call i32 @X3( %Exec %exec, %Value %ext_arg_val ) ; <i32> [#uses=3]
+ %eh_check6 = tail call i1 @X1( %Exec %exec ) readonly ; <i1> [#uses=1]
+ br i1 %eh_check6, label %exception, label %no_exception7
+
+no_exception7: ; preds = %no_exception
+ %shl_tmp_result = shl i32 %toInt325, 1 ; <i32> [#uses=1]
+ %rhs_masked13 = and i32 %shl_tmp_result, 14 ; <i32> [#uses=1]
+ %ashr_tmp_result = lshr i32 59796, %rhs_masked13 ; <i32> [#uses=1]
+ %and_tmp_result15 = and i32 %ashr_tmp_result, 3 ; <i32> [#uses=1]
+ %ashr_tmp_result3283 = lshr i32 %toInt325, 2 ; <i32> [#uses=1]
+ %rhs_masked38 = and i32 %ashr_tmp_result3283, 14 ; <i32> [#uses=1]
+ %ashr_tmp_result39 = lshr i32 59796, %rhs_masked38 ; <i32> [#uses=1]
+ %and_tmp_result41 = and i32 %ashr_tmp_result39, 3 ; <i32> [#uses=1]
+ %addconv = add i32 %and_tmp_result15, %and_tmp_result41 ; <i32> [#uses=1]
+ %ashr_tmp_result6181 = lshr i32 %toInt325, 5 ; <i32> [#uses=1]
+ %rhs_masked67 = and i32 %ashr_tmp_result6181, 6 ; <i32> [#uses=1]
+ %ashr_tmp_result68 = lshr i32 59796, %rhs_masked67 ; <i32> [#uses=1]
+ %and_tmp_result70 = and i32 %ashr_tmp_result68, 3 ; <i32> [#uses=1]
+ %addconv82 = add i32 %addconv, %and_tmp_result70 ; <i32> [#uses=3]
+ %rangetmp = add i32 %addconv82, 536870912 ; <i32> [#uses=1]
+ %rangecmp = icmp ult i32 %rangetmp, 1073741824 ; <i1> [#uses=1]
+ br i1 %rangecmp, label %NumberLiteralIntFast, label %NumberLiteralIntSlow
+
+NumberLiteralIntFast: ; preds = %no_exception7
+ %imm_shift = shl i32 %addconv82, 2 ; <i32> [#uses=1]
+ %imm_or = or i32 %imm_shift, 3 ; <i32> [#uses=1]
+ %imm_val = inttoptr i32 %imm_or to %Value ; <%Value> [#uses=1]
+ ret %Value %imm_val
+
+NumberLiteralIntSlow: ; preds = %no_exception7
+ %toVal = call %Value @X4( i32 %addconv82 ) ; <%Value> [#uses=1]
+ ret %Value %toVal
+}
diff --git a/test/CodeGen/X86/uint_to_fp-2.ll b/test/CodeGen/X86/uint_to_fp-2.ll
new file mode 100644
index 0000000..da5105d
--- /dev/null
+++ b/test/CodeGen/X86/uint_to_fp-2.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movsd | count 1
+; rdar://6504833
+
+define float @f(i32 %x) nounwind readnone {
+entry:
+ %0 = uitofp i32 %x to float
+ ret float %0
+}
diff --git a/test/CodeGen/X86/uint_to_fp.ll b/test/CodeGen/X86/uint_to_fp.ll
new file mode 100644
index 0000000..41ee194
--- /dev/null
+++ b/test/CodeGen/X86/uint_to_fp.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah | not grep {sub.*esp}
+; RUN: llc < %s -march=x86 -mcpu=yonah | grep cvtsi2ss
+; rdar://6034396
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i386-apple-darwin8"
+
+define void @test(i32 %x, float* %y) nounwind {
+entry:
+ lshr i32 %x, 23 ; <i32>:0 [#uses=1]
+ uitofp i32 %0 to float ; <float>:1 [#uses=1]
+ store float %1, float* %y
+ ret void
+}
diff --git a/test/CodeGen/X86/umul-with-carry.ll b/test/CodeGen/X86/umul-with-carry.ll
new file mode 100644
index 0000000..74160516
--- /dev/null
+++ b/test/CodeGen/X86/umul-with-carry.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86 | grep {jc} | count 1
+; XFAIL: *
+
+; FIXME: umul-with-overflow not supported yet.
+
+@ok = internal constant [4 x i8] c"%d\0A\00"
+@no = internal constant [4 x i8] c"no\0A\00"
+
+define i1 @func(i32 %v1, i32 %v2) nounwind {
+entry:
+ %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
+ %sum = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %carry, label %normal
+
+normal:
+ %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
+ ret i1 true
+
+carry:
+ %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
+ ret i1 false
+}
+
+declare i32 @printf(i8*, ...) nounwind
+declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32)
diff --git a/test/CodeGen/X86/umul-with-overflow.ll b/test/CodeGen/X86/umul-with-overflow.ll
new file mode 100644
index 0000000..d522bd8
--- /dev/null
+++ b/test/CodeGen/X86/umul-with-overflow.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 | grep "\\\\\\\<mul"
+
+declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b)
+define i1 @a(i32 %x) zeroext nounwind {
+ %res = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %x, i32 3)
+ %obil = extractvalue {i32, i1} %res, 1
+ ret i1 %obil
+}
diff --git a/test/CodeGen/X86/unaligned-load.ll b/test/CodeGen/X86/unaligned-load.ll
new file mode 100644
index 0000000..b61803d
--- /dev/null
+++ b/test/CodeGen/X86/unaligned-load.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=dynamic-no-pic --asm-verbose=0 | FileCheck %s
+
[email protected] = internal constant [31 x i8] c"DHRYSTONE PROGRAM, SOME STRING\00", align 8
[email protected] = internal constant [31 x i8] c"DHRYSTONE PROGRAM, 2'ND STRING\00", align 8
+
+define void @func() nounwind ssp {
+entry:
+ %String2Loc = alloca [31 x i8], align 1
+ br label %bb
+
+bb:
+ %String2Loc9 = getelementptr inbounds [31 x i8]* %String2Loc, i64 0, i64 0
+ call void @llvm.memcpy.i64(i8* %String2Loc9, i8* getelementptr inbounds ([31 x i8]* @.str3, i64 0, i64 0), i64 31, i32 1)
+; CHECK: movups _.str3
+ br label %bb
+
+return:
+ ret void
+}
+
+declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind
+
+; CHECK: .align 3
+; CHECK-NEXT: _.str1:
+; CHECK-NEXT: .asciz "DHRYSTONE PROGRAM, SOME STRING"
+; CHECK: .align 3
+; CHECK-NEXT: _.str3:
diff --git a/test/CodeGen/X86/urem-i8-constant.ll b/test/CodeGen/X86/urem-i8-constant.ll
new file mode 100644
index 0000000..e3cb69c
--- /dev/null
+++ b/test/CodeGen/X86/urem-i8-constant.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86 | grep 111
+
+define i8 @foo(i8 %tmp325) {
+ %t546 = urem i8 %tmp325, 37
+ ret i8 %t546
+}
diff --git a/test/CodeGen/X86/use-add-flags.ll b/test/CodeGen/X86/use-add-flags.ll
new file mode 100644
index 0000000..2dd2a4a
--- /dev/null
+++ b/test/CodeGen/X86/use-add-flags.ll
@@ -0,0 +1,56 @@
+; RUN: llc < %s -march=x86-64 -o - | FileCheck %s
+
+; Reuse the flags value from the add instructions instead of emitting separate
+; testl instructions.
+
+; Use the flags on the add.
+
+; CHECK: add_zf:
+; CHECK: addl (%rdi), %esi
+; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: cmovnsl %ecx, %eax
+; CHECK-NEXT: ret
+
+define i32 @add_zf(i32* %x, i32 %y, i32 %a, i32 %b) nounwind {
+ %tmp2 = load i32* %x, align 4 ; <i32> [#uses=1]
+ %tmp4 = add i32 %tmp2, %y ; <i32> [#uses=1]
+ %tmp5 = icmp slt i32 %tmp4, 0 ; <i1> [#uses=1]
+ %tmp.0 = select i1 %tmp5, i32 %a, i32 %b ; <i32> [#uses=1]
+ ret i32 %tmp.0
+}
+
+declare void @foo(i32)
+
+; Don't use the flags result of the and here, since the and has no
+; other use. A simple test is better.
+
+; CHECK: bar:
+; CHECK: testb $16, %dil
+
+define void @bar(i32 %x) nounwind {
+ %y = and i32 %x, 16
+ %t = icmp eq i32 %y, 0
+ br i1 %t, label %true, label %false
+true:
+ call void @foo(i32 %x)
+ ret void
+false:
+ ret void
+}
+
+; Do use the flags result of the and here, since the and has another use.
+
+; CHECK: qux:
+; CHECK: andl $16, %edi
+; CHECK-NEXT: jne
+
+define void @qux(i32 %x) nounwind {
+ %y = and i32 %x, 16
+ %t = icmp eq i32 %y, 0
+ br i1 %t, label %true, label %false
+true:
+ call void @foo(i32 %y)
+ ret void
+false:
+ ret void
+}
diff --git a/test/CodeGen/X86/v4f32-immediate.ll b/test/CodeGen/X86/v4f32-immediate.ll
new file mode 100644
index 0000000..b5ebaa7
--- /dev/null
+++ b/test/CodeGen/X86/v4f32-immediate.ll
@@ -0,0 +1,5 @@
+; RUN: llc < %s -march=x86 -mattr=+sse | grep movaps
+
+define <4 x float> @foo() {
+ ret <4 x float> <float 0x4009C9D0A0000000, float 0x4002666660000000, float 0x3FF3333340000000, float 0x3FB99999A0000000>
+}
diff --git a/test/CodeGen/X86/variable-sized-darwin-bzero.ll b/test/CodeGen/X86/variable-sized-darwin-bzero.ll
new file mode 100644
index 0000000..4817db2
--- /dev/null
+++ b/test/CodeGen/X86/variable-sized-darwin-bzero.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin10 | grep __bzero
+
+declare void @llvm.memset.i64(i8*, i8, i64, i32)
+
+define void @foo(i8* %p, i64 %n) {
+ call void @llvm.memset.i64(i8* %p, i8 0, i64 %n, i32 4)
+ ret void
+}
diff --git a/test/CodeGen/X86/variadic-node-pic.ll b/test/CodeGen/X86/variadic-node-pic.ll
new file mode 100644
index 0000000..1182a30
--- /dev/null
+++ b/test/CodeGen/X86/variadic-node-pic.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -relocation-model=pic -code-model=large
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin8"
+
+declare void @xscanf(i64) nounwind
+
+define void @foo() nounwind {
+ call void (i64)* @xscanf( i64 0 ) nounwind
+ unreachable
+}
diff --git a/test/CodeGen/X86/vec-trunc-store.ll b/test/CodeGen/X86/vec-trunc-store.ll
new file mode 100644
index 0000000..ea1a151
--- /dev/null
+++ b/test/CodeGen/X86/vec-trunc-store.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86-64 -disable-mmx | grep punpcklwd | count 2
+
+define void @foo() nounwind {
+ %cti69 = trunc <8 x i32> undef to <8 x i16> ; <<8 x i16>> [#uses=1]
+ store <8 x i16> %cti69, <8 x i16>* undef
+ ret void
+}
+
+define void @bar() nounwind {
+ %cti44 = trunc <4 x i32> undef to <4 x i16> ; <<4 x i16>> [#uses=1]
+ store <4 x i16> %cti44, <4 x i16>* undef
+ ret void
+}
diff --git a/test/CodeGen/X86/vec_add.ll b/test/CodeGen/X86/vec_add.ll
new file mode 100644
index 0000000..7c77d11
--- /dev/null
+++ b/test/CodeGen/X86/vec_add.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+
+define <2 x i64> @test(<2 x i64> %a, <2 x i64> %b) {
+entry:
+ %tmp9 = add <2 x i64> %b, %a ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp9
+}
diff --git a/test/CodeGen/X86/vec_align.ll b/test/CodeGen/X86/vec_align.ll
new file mode 100644
index 0000000..e273115
--- /dev/null
+++ b/test/CodeGen/X86/vec_align.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -mcpu=yonah -relocation-model=static | grep movaps | count 2
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin8"
+
+%f4 = type <4 x float>
+
+@G = external global { float,float,float,float}, align 16
+
+define %f4 @test1(float %W, float %X, float %Y, float %Z) nounwind {
+ %tmp = insertelement %f4 undef, float %W, i32 0
+ %tmp2 = insertelement %f4 %tmp, float %X, i32 1
+ %tmp4 = insertelement %f4 %tmp2, float %Y, i32 2
+ %tmp6 = insertelement %f4 %tmp4, float %Z, i32 3
+ ret %f4 %tmp6
+}
+
+define %f4 @test2() nounwind {
+ %Wp = getelementptr { float,float,float,float}* @G, i32 0, i32 0
+ %Xp = getelementptr { float,float,float,float}* @G, i32 0, i32 1
+ %Yp = getelementptr { float,float,float,float}* @G, i32 0, i32 2
+ %Zp = getelementptr { float,float,float,float}* @G, i32 0, i32 3
+
+ %W = load float* %Wp
+ %X = load float* %Xp
+ %Y = load float* %Yp
+ %Z = load float* %Zp
+
+ %tmp = insertelement %f4 undef, float %W, i32 0
+ %tmp2 = insertelement %f4 %tmp, float %X, i32 1
+ %tmp4 = insertelement %f4 %tmp2, float %Y, i32 2
+ %tmp6 = insertelement %f4 %tmp4, float %Z, i32 3
+ ret %f4 %tmp6
+}
+
diff --git a/test/CodeGen/X86/vec_call.ll b/test/CodeGen/X86/vec_call.ll
new file mode 100644
index 0000000..b3efc7b
--- /dev/null
+++ b/test/CodeGen/X86/vec_call.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin8 | \
+; RUN: grep {subl.*60}
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin8 | \
+; RUN: grep {movaps.*32}
+
+
+define void @test() {
+ tail call void @xx( i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, <2 x i64> bitcast (<4 x i32> < i32 4, i32 3, i32 2, i32 1 > to <2 x i64>), <2 x i64> bitcast (<4 x i32> < i32 8, i32 7, i32 6, i32 5 > to <2 x i64>), <2 x i64> bitcast (<4 x i32> < i32 6, i32 4, i32 2, i32 0 > to <2 x i64>), <2 x i64> bitcast (<4 x i32> < i32 8, i32 4, i32 2, i32 1 > to <2 x i64>), <2 x i64> bitcast (<4 x i32> < i32 0, i32 1, i32 3, i32 9 > to <2 x i64>) )
+ ret void
+}
+
+declare void @xx(i32, i32, i32, i32, i32, i32, i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>)
+
diff --git a/test/CodeGen/X86/vec_cast.ll b/test/CodeGen/X86/vec_cast.ll
new file mode 100644
index 0000000..1f899b3
--- /dev/null
+++ b/test/CodeGen/X86/vec_cast.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -march=x86-64 -disable-mmx
+
+define <8 x i32> @a(<8 x i16> %a) nounwind {
+ %c = sext <8 x i16> %a to <8 x i32>
+ ret <8 x i32> %c
+}
+
+define <3 x i32> @b(<3 x i16> %a) nounwind {
+ %c = sext <3 x i16> %a to <3 x i32>
+ ret <3 x i32> %c
+}
+
+define <1 x i32> @c(<1 x i16> %a) nounwind {
+ %c = sext <1 x i16> %a to <1 x i32>
+ ret <1 x i32> %c
+}
+
+define <8 x i32> @d(<8 x i16> %a) nounwind {
+ %c = zext <8 x i16> %a to <8 x i32>
+ ret <8 x i32> %c
+}
+
+define <3 x i32> @e(<3 x i16> %a) nounwind {
+ %c = zext <3 x i16> %a to <3 x i32>
+ ret <3 x i32> %c
+}
+
+define <1 x i32> @f(<1 x i16> %a) nounwind {
+ %c = zext <1 x i16> %a to <1 x i32>
+ ret <1 x i32> %c
+}
+
+; TODO: Legalize doesn't yet handle this.
+;define <8 x i16> @g(<8 x i32> %a) nounwind {
+; %c = trunc <8 x i32> %a to <8 x i16>
+; ret <8 x i16> %c
+;}
+
+define <3 x i16> @h(<3 x i32> %a) nounwind {
+ %c = trunc <3 x i32> %a to <3 x i16>
+ ret <3 x i16> %c
+}
+
+define <1 x i16> @i(<1 x i32> %a) nounwind {
+ %c = trunc <1 x i32> %a to <1 x i16>
+ ret <1 x i16> %c
+}
diff --git a/test/CodeGen/X86/vec_clear.ll b/test/CodeGen/X86/vec_clear.ll
new file mode 100644
index 0000000..166d436
--- /dev/null
+++ b/test/CodeGen/X86/vec_clear.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -o %t
+; RUN: not grep and %t
+; RUN: not grep psrldq %t
+; RUN: grep xorps %t
+
+define <4 x float> @test(<4 x float>* %v1) nounwind {
+ %tmp = load <4 x float>* %v1 ; <<4 x float>> [#uses=1]
+ %tmp15 = bitcast <4 x float> %tmp to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp24 = and <2 x i64> %tmp15, bitcast (<4 x i32> < i32 0, i32 0, i32 -1, i32 -1 > to <2 x i64>) ; <<2 x i64>> [#uses=1]
+ %tmp31 = bitcast <2 x i64> %tmp24 to <4 x float> ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp31
+}
+
diff --git a/test/CodeGen/X86/vec_compare-2.ll b/test/CodeGen/X86/vec_compare-2.ll
new file mode 100644
index 0000000..091641b
--- /dev/null
+++ b/test/CodeGen/X86/vec_compare-2.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=x86 -mcpu=penryn -disable-mmx | FileCheck %s
+
+declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
+
+declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
+
+define void @blackDespeckle_wrapper(i8** %args_list, i64* %gtid, i64 %xend) {
+entry:
+; CHECK-NOT: set
+; CHECK: pcmpgt
+; CHECK: blendvps
+ %shr.i = ashr <4 x i32> zeroinitializer, <i32 3, i32 3, i32 3, i32 3> ; <<4 x i32>> [#uses=1]
+ %cmp318.i = sext <4 x i1> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %sub322.i = sub <4 x i32> %shr.i, zeroinitializer ; <<4 x i32>> [#uses=1]
+ %cmp323.x = icmp slt <4 x i32> zeroinitializer, %sub322.i ; <<4 x i1>> [#uses=1]
+ %cmp323.i = sext <4 x i1> %cmp323.x to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %or.i = or <4 x i32> %cmp318.i, %cmp323.i ; <<4 x i32>> [#uses=1]
+ %tmp10.i83.i = bitcast <4 x i32> %or.i to <4 x float> ; <<4 x float>> [#uses=1]
+ %0 = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> undef, <4 x float> undef, <4 x float> %tmp10.i83.i) nounwind ; <<4 x float>> [#uses=1]
+ %conv.i.i15.i = bitcast <4 x float> %0 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %swz.i.i28.i = shufflevector <4 x i32> %conv.i.i15.i, <4 x i32> undef, <2 x i32> <i32 0, i32 1> ; <<2 x i32>> [#uses=1]
+ %tmp6.i29.i = bitcast <2 x i32> %swz.i.i28.i to <4 x i16> ; <<4 x i16>> [#uses=1]
+ %swz.i30.i = shufflevector <4 x i16> %tmp6.i29.i, <4 x i16> undef, <2 x i32> <i32 0, i32 1> ; <<2 x i16>> [#uses=1]
+ store <2 x i16> %swz.i30.i, <2 x i16>* undef
+ unreachable
+ ret void
+}
diff --git a/test/CodeGen/X86/vec_compare.ll b/test/CodeGen/X86/vec_compare.ll
new file mode 100644
index 0000000..c8c7257
--- /dev/null
+++ b/test/CodeGen/X86/vec_compare.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
+
+
+define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: test1:
+; CHECK: pcmpgtd
+; CHECK: ret
+
+ %C = icmp sgt <4 x i32> %A, %B
+ %D = sext <4 x i1> %C to <4 x i32>
+ ret <4 x i32> %D
+}
+
+define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: test2:
+; CHECK: pcmp
+; CHECK: pcmp
+; CHECK: xorps
+; CHECK: ret
+ %C = icmp sge <4 x i32> %A, %B
+ %D = sext <4 x i1> %C to <4 x i32>
+ ret <4 x i32> %D
+}
+
+define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: test3:
+; CHECK: pcmpgtd
+; CHECK: movaps
+; CHECK: ret
+ %C = icmp slt <4 x i32> %A, %B
+ %D = sext <4 x i1> %C to <4 x i32>
+ ret <4 x i32> %D
+}
+
+define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: test4:
+; CHECK: movaps
+; CHECK: pcmpgtd
+; CHECK: ret
+ %C = icmp ugt <4 x i32> %A, %B
+ %D = sext <4 x i1> %C to <4 x i32>
+ ret <4 x i32> %D
+}
diff --git a/test/CodeGen/X86/vec_ctbits.ll b/test/CodeGen/X86/vec_ctbits.ll
new file mode 100644
index 0000000..f0158d6
--- /dev/null
+++ b/test/CodeGen/X86/vec_ctbits.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86-64
+
+declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>)
+declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>)
+declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
+
+define <2 x i64> @footz(<2 x i64> %a) nounwind {
+ %c = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a)
+ ret <2 x i64> %c
+}
+define <2 x i64> @foolz(<2 x i64> %a) nounwind {
+ %c = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a)
+ ret <2 x i64> %c
+}
+define <2 x i64> @foopop(<2 x i64> %a) nounwind {
+ %c = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)
+ ret <2 x i64> %c
+}
diff --git a/test/CodeGen/X86/vec_ext_inreg.ll b/test/CodeGen/X86/vec_ext_inreg.ll
new file mode 100644
index 0000000..8d2a3c3
--- /dev/null
+++ b/test/CodeGen/X86/vec_ext_inreg.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -march=x86-64 -disable-mmx
+
+define <8 x i32> @a(<8 x i32> %a) nounwind {
+ %b = trunc <8 x i32> %a to <8 x i16>
+ %c = sext <8 x i16> %b to <8 x i32>
+ ret <8 x i32> %c
+}
+
+define <3 x i32> @b(<3 x i32> %a) nounwind {
+ %b = trunc <3 x i32> %a to <3 x i16>
+ %c = sext <3 x i16> %b to <3 x i32>
+ ret <3 x i32> %c
+}
+
+define <1 x i32> @c(<1 x i32> %a) nounwind {
+ %b = trunc <1 x i32> %a to <1 x i16>
+ %c = sext <1 x i16> %b to <1 x i32>
+ ret <1 x i32> %c
+}
+
+define <8 x i32> @d(<8 x i32> %a) nounwind {
+ %b = trunc <8 x i32> %a to <8 x i16>
+ %c = zext <8 x i16> %b to <8 x i32>
+ ret <8 x i32> %c
+}
+
+define <3 x i32> @e(<3 x i32> %a) nounwind {
+ %b = trunc <3 x i32> %a to <3 x i16>
+ %c = zext <3 x i16> %b to <3 x i32>
+ ret <3 x i32> %c
+}
+
+define <1 x i32> @f(<1 x i32> %a) nounwind {
+ %b = trunc <1 x i32> %a to <1 x i16>
+ %c = zext <1 x i16> %b to <1 x i32>
+ ret <1 x i32> %c
+}
diff --git a/test/CodeGen/X86/vec_extract-sse4.ll b/test/CodeGen/X86/vec_extract-sse4.ll
new file mode 100644
index 0000000..dab5dd1
--- /dev/null
+++ b/test/CodeGen/X86/vec_extract-sse4.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=x86 -mattr=+sse41 -o %t
+; RUN: grep extractps %t | count 1
+; RUN: grep pextrd %t | count 1
+; RUN: not grep pshufd %t
+; RUN: not grep movss %t
+
+define void @t1(float* %R, <4 x float>* %P1) nounwind {
+ %X = load <4 x float>* %P1
+ %tmp = extractelement <4 x float> %X, i32 3
+ store float %tmp, float* %R
+ ret void
+}
+
+define float @t2(<4 x float>* %P1) nounwind {
+ %X = load <4 x float>* %P1
+ %tmp = extractelement <4 x float> %X, i32 2
+ ret float %tmp
+}
+
+define void @t3(i32* %R, <4 x i32>* %P1) nounwind {
+ %X = load <4 x i32>* %P1
+ %tmp = extractelement <4 x i32> %X, i32 3
+ store i32 %tmp, i32* %R
+ ret void
+}
+
+define i32 @t4(<4 x i32>* %P1) nounwind {
+ %X = load <4 x i32>* %P1
+ %tmp = extractelement <4 x i32> %X, i32 3
+ ret i32 %tmp
+}
diff --git a/test/CodeGen/X86/vec_extract.ll b/test/CodeGen/X86/vec_extract.ll
new file mode 100644
index 0000000..b013730
--- /dev/null
+++ b/test/CodeGen/X86/vec_extract.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 -o %t
+; RUN: grep movss %t | count 3
+; RUN: grep movhlps %t | count 1
+; RUN: grep pshufd %t | count 1
+; RUN: grep unpckhpd %t | count 1
+
+define void @test1(<4 x float>* %F, float* %f) nounwind {
+ %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
+ %tmp7 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
+ %tmp2 = extractelement <4 x float> %tmp7, i32 0 ; <float> [#uses=1]
+ store float %tmp2, float* %f
+ ret void
+}
+
+define float @test2(<4 x float>* %F, float* %f) nounwind {
+ %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
+ %tmp7 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
+ %tmp2 = extractelement <4 x float> %tmp7, i32 2 ; <float> [#uses=1]
+ ret float %tmp2
+}
+
+define void @test3(float* %R, <4 x float>* %P1) nounwind {
+ %X = load <4 x float>* %P1 ; <<4 x float>> [#uses=1]
+ %tmp = extractelement <4 x float> %X, i32 3 ; <float> [#uses=1]
+ store float %tmp, float* %R
+ ret void
+}
+
+define double @test4(double %A) nounwind {
+ %tmp1 = call <2 x double> @foo( ) ; <<2 x double>> [#uses=1]
+ %tmp2 = extractelement <2 x double> %tmp1, i32 1 ; <double> [#uses=1]
+ %tmp3 = fadd double %tmp2, %A ; <double> [#uses=1]
+ ret double %tmp3
+}
+
+declare <2 x double> @foo()
diff --git a/test/CodeGen/X86/vec_fneg.ll b/test/CodeGen/X86/vec_fneg.ll
new file mode 100644
index 0000000..d49c70e
--- /dev/null
+++ b/test/CodeGen/X86/vec_fneg.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+
+define <4 x float> @t1(<4 x float> %Q) {
+ %tmp15 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %Q
+ ret <4 x float> %tmp15
+}
+
+define <4 x float> @t2(<4 x float> %Q) {
+ %tmp15 = fsub <4 x float> zeroinitializer, %Q
+ ret <4 x float> %tmp15
+}
diff --git a/test/CodeGen/X86/vec_i64.ll b/test/CodeGen/X86/vec_i64.ll
new file mode 100644
index 0000000..462e16e
--- /dev/null
+++ b/test/CodeGen/X86/vec_i64.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
+; RUN: grep movq %t | count 2
+
+; Used movq to load i64 into a v2i64 when the top i64 is 0.
+
+define <2 x i64> @foo1(i64* %y) nounwind {
+entry:
+ %tmp1 = load i64* %y, align 8 ; <i64> [#uses=1]
+ %s2v = insertelement <2 x i64> undef, i64 %tmp1, i32 0
+ %loadl = shufflevector <2 x i64> zeroinitializer, <2 x i64> %s2v, <2 x i32> <i32 2, i32 1>
+ ret <2 x i64> %loadl
+}
+
+
+define <4 x float> @foo2(i64* %p) nounwind {
+entry:
+ %load = load i64* %p
+ %s2v = insertelement <2 x i64> undef, i64 %load, i32 0
+ %loadl = shufflevector <2 x i64> zeroinitializer, <2 x i64> %s2v, <2 x i32> <i32 2, i32 1>
+ %0 = bitcast <2 x i64> %loadl to <4 x float>
+ ret <4 x float> %0
+}
diff --git a/test/CodeGen/X86/vec_ins_extract-1.ll b/test/CodeGen/X86/vec_ins_extract-1.ll
new file mode 100644
index 0000000..2951193
--- /dev/null
+++ b/test/CodeGen/X86/vec_ins_extract-1.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah | grep {(%esp,%eax,4)} | count 4
+
+; Inserts and extracts with variable indices must be lowered
+; to memory accesses.
+
+define i32 @t0(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
+ %t13 = insertelement <4 x i32> %t8, i32 76, i32 %t7
+ %t9 = extractelement <4 x i32> %t13, i32 0
+ ret i32 %t9
+}
+define i32 @t1(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
+ %t13 = insertelement <4 x i32> %t8, i32 76, i32 0
+ %t9 = extractelement <4 x i32> %t13, i32 %t7
+ ret i32 %t9
+}
+define <4 x i32> @t2(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
+ %t9 = extractelement <4 x i32> %t8, i32 %t7
+ %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 0
+ ret <4 x i32> %t13
+}
+define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
+ %t9 = extractelement <4 x i32> %t8, i32 0
+ %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 %t7
+ ret <4 x i32> %t13
+}
diff --git a/test/CodeGen/X86/vec_ins_extract.ll b/test/CodeGen/X86/vec_ins_extract.ll
new file mode 100644
index 0000000..daf222e
--- /dev/null
+++ b/test/CodeGen/X86/vec_ins_extract.ll
@@ -0,0 +1,52 @@
+; RUN: opt < %s -scalarrepl -instcombine | \
+; RUN: llc -march=x86 -mcpu=yonah | not grep sub.*esp
+
+; This checks that various insert/extract idiom work without going to the
+; stack.
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+
+define void @test(<4 x float>* %F, float %f) {
+entry:
+ %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
+ %tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
+ %tmp10 = insertelement <4 x float> %tmp3, float %f, i32 0 ; <<4 x float>> [#uses=2]
+ %tmp6 = fadd <4 x float> %tmp10, %tmp10 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp6, <4 x float>* %F
+ ret void
+}
+
+define void @test2(<4 x float>* %F, float %f) {
+entry:
+ %G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=3]
+ %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
+ %tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp3, <4 x float>* %G
+ %tmp.upgrd.1 = getelementptr <4 x float>* %G, i32 0, i32 2 ; <float*> [#uses=1]
+ store float %f, float* %tmp.upgrd.1
+ %tmp4 = load <4 x float>* %G ; <<4 x float>> [#uses=2]
+ %tmp6 = fadd <4 x float> %tmp4, %tmp4 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp6, <4 x float>* %F
+ ret void
+}
+
+define void @test3(<4 x float>* %F, float* %f) {
+entry:
+ %G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=2]
+ %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
+ %tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp3, <4 x float>* %G
+ %tmp.upgrd.2 = getelementptr <4 x float>* %G, i32 0, i32 2 ; <float*> [#uses=1]
+ %tmp.upgrd.3 = load float* %tmp.upgrd.2 ; <float> [#uses=1]
+ store float %tmp.upgrd.3, float* %f
+ ret void
+}
+
+define void @test4(<4 x float>* %F, float* %f) {
+entry:
+ %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
+ %tmp5.lhs = extractelement <4 x float> %tmp, i32 0 ; <float> [#uses=1]
+ %tmp5.rhs = extractelement <4 x float> %tmp, i32 0 ; <float> [#uses=1]
+ %tmp5 = fadd float %tmp5.lhs, %tmp5.rhs ; <float> [#uses=1]
+ store float %tmp5, float* %f
+ ret void
+}
diff --git a/test/CodeGen/X86/vec_insert-2.ll b/test/CodeGen/X86/vec_insert-2.ll
new file mode 100644
index 0000000..b08044b
--- /dev/null
+++ b/test/CodeGen/X86/vec_insert-2.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep {\$36,} | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep shufps | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep pinsrw | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movhpd | count 1
+; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | grep unpcklpd | count 1
+
+define <4 x float> @t1(float %s, <4 x float> %tmp) nounwind {
+ %tmp1 = insertelement <4 x float> %tmp, float %s, i32 3
+ ret <4 x float> %tmp1
+}
+
+define <4 x i32> @t2(i32 %s, <4 x i32> %tmp) nounwind {
+ %tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 3
+ ret <4 x i32> %tmp1
+}
+
+define <2 x double> @t3(double %s, <2 x double> %tmp) nounwind {
+ %tmp1 = insertelement <2 x double> %tmp, double %s, i32 1
+ ret <2 x double> %tmp1
+}
+
+define <8 x i16> @t4(i16 %s, <8 x i16> %tmp) nounwind {
+ %tmp1 = insertelement <8 x i16> %tmp, i16 %s, i32 5
+ ret <8 x i16> %tmp1
+}
diff --git a/test/CodeGen/X86/vec_insert-3.ll b/test/CodeGen/X86/vec_insert-3.ll
new file mode 100644
index 0000000..a18cd864
--- /dev/null
+++ b/test/CodeGen/X86/vec_insert-3.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | grep punpcklqdq | count 1
+
+define <2 x i64> @t1(i64 %s, <2 x i64> %tmp) nounwind {
+ %tmp1 = insertelement <2 x i64> %tmp, i64 %s, i32 1
+ ret <2 x i64> %tmp1
+}
diff --git a/test/CodeGen/X86/vec_insert-5.ll b/test/CodeGen/X86/vec_insert-5.ll
new file mode 100644
index 0000000..291fc04
--- /dev/null
+++ b/test/CodeGen/X86/vec_insert-5.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
+; RUN: grep psllq %t | grep 32
+; RUN: grep pslldq %t | grep 12
+; RUN: grep psrldq %t | grep 8
+; RUN: grep psrldq %t | grep 12
+
+define void @t1(i32 %a, <1 x i64>* %P) nounwind {
+ %tmp12 = shl i32 %a, 12
+ %tmp21 = insertelement <2 x i32> undef, i32 %tmp12, i32 1
+ %tmp22 = insertelement <2 x i32> %tmp21, i32 0, i32 0
+ %tmp23 = bitcast <2 x i32> %tmp22 to <1 x i64>
+ store <1 x i64> %tmp23, <1 x i64>* %P
+ ret void
+}
+
+define <4 x float> @t2(<4 x float>* %P) nounwind {
+ %tmp1 = load <4 x float>* %P
+ %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 4, i32 4, i32 4, i32 0 >
+ ret <4 x float> %tmp2
+}
+
+define <4 x float> @t3(<4 x float>* %P) nounwind {
+ %tmp1 = load <4 x float>* %P
+ %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 2, i32 3, i32 4, i32 4 >
+ ret <4 x float> %tmp2
+}
+
+define <4 x float> @t4(<4 x float>* %P) nounwind {
+ %tmp1 = load <4 x float>* %P
+ %tmp2 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp1, <4 x i32> < i32 7, i32 0, i32 0, i32 0 >
+ ret <4 x float> %tmp2
+}
diff --git a/test/CodeGen/X86/vec_insert-6.ll b/test/CodeGen/X86/vec_insert-6.ll
new file mode 100644
index 0000000..54aa43f
--- /dev/null
+++ b/test/CodeGen/X86/vec_insert-6.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pslldq
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 6
+
+define <4 x float> @t3(<4 x float>* %P) nounwind {
+ %tmp1 = load <4 x float>* %P
+ %tmp2 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp1, <4 x i32> < i32 4, i32 4, i32 4, i32 0 >
+ ret <4 x float> %tmp2
+}
diff --git a/test/CodeGen/X86/vec_insert-7.ll b/test/CodeGen/X86/vec_insert-7.ll
new file mode 100644
index 0000000..9ede10f
--- /dev/null
+++ b/test/CodeGen/X86/vec_insert-7.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 -mattr=+mmx -mtriple=i686-apple-darwin9 -o - | grep punpckldq
+
+define <2 x i32> @mmx_movzl(<2 x i32> %x) nounwind {
+entry:
+ %tmp3 = insertelement <2 x i32> %x, i32 32, i32 0 ; <<2 x i32>> [#uses=1]
+ %tmp8 = insertelement <2 x i32> %tmp3, i32 0, i32 1 ; <<2 x i32>> [#uses=1]
+ ret <2 x i32> %tmp8
+}
diff --git a/test/CodeGen/X86/vec_insert-8.ll b/test/CodeGen/X86/vec_insert-8.ll
new file mode 100644
index 0000000..650951c
--- /dev/null
+++ b/test/CodeGen/X86/vec_insert-8.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mattr=+sse41 -o %t
+
+; tests variable insert and extract of a 4 x i32
+
+define <4 x i32> @var_insert(<4 x i32> %x, i32 %val, i32 %idx) nounwind {
+entry:
+ %tmp3 = insertelement <4 x i32> %x, i32 %val, i32 %idx ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %tmp3
+}
+
+define i32 @var_extract(<4 x i32> %x, i32 %idx) nounwind {
+entry:
+ %tmp3 = extractelement <4 x i32> %x, i32 %idx ; <<i32>> [#uses=1]
+ ret i32 %tmp3
+}
diff --git a/test/CodeGen/X86/vec_insert.ll b/test/CodeGen/X86/vec_insert.ll
new file mode 100644
index 0000000..a7274a9
--- /dev/null
+++ b/test/CodeGen/X86/vec_insert.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movss | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | not grep pinsrw
+
+define void @test(<4 x float>* %F, i32 %I) {
+ %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=1]
+ %f = sitofp i32 %I to float ; <float> [#uses=1]
+ %tmp1 = insertelement <4 x float> %tmp, float %f, i32 0 ; <<4 x float>> [#uses=2]
+ %tmp18 = fadd <4 x float> %tmp1, %tmp1 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp18, <4 x float>* %F
+ ret void
+}
+
+define void @test2(<4 x float>* %F, i32 %I, float %g) {
+ %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=1]
+ %f = sitofp i32 %I to float ; <float> [#uses=1]
+ %tmp1 = insertelement <4 x float> %tmp, float %f, i32 2 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp1, <4 x float>* %F
+ ret void
+}
diff --git a/test/CodeGen/X86/vec_insert_4.ll b/test/CodeGen/X86/vec_insert_4.ll
new file mode 100644
index 0000000..2c31e56
--- /dev/null
+++ b/test/CodeGen/X86/vec_insert_4.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah | grep 1084227584 | count 1
+
+; ModuleID = '<stdin>'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin9.2.2"
+
+define <8 x float> @f(<8 x float> %a, i32 %b) nounwind {
+entry:
+ %vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b ; <<4 x float>> [#uses=1]
+ ret <8 x float> %vecins
+}
diff --git a/test/CodeGen/X86/vec_loadsingles.ll b/test/CodeGen/X86/vec_loadsingles.ll
new file mode 100644
index 0000000..8812c4f
--- /dev/null
+++ b/test/CodeGen/X86/vec_loadsingles.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
+
+define <4 x float> @a(<4 x float> %a, float* nocapture %p) nounwind readonly {
+entry:
+ %tmp1 = load float* %p
+ %vecins = insertelement <4 x float> undef, float %tmp1, i32 0
+ %add.ptr = getelementptr float* %p, i32 1
+ %tmp5 = load float* %add.ptr
+ %vecins7 = insertelement <4 x float> %vecins, float %tmp5, i32 1
+ ret <4 x float> %vecins7
+}
+
diff --git a/test/CodeGen/X86/vec_logical.ll b/test/CodeGen/X86/vec_logical.ll
new file mode 100644
index 0000000..1dc0b16
--- /dev/null
+++ b/test/CodeGen/X86/vec_logical.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
+; RUN: grep xorps %t | count 2
+; RUN: grep andnps %t
+; RUN: grep movaps %t | count 2
+
+define void @t(<4 x float> %A) {
+ %tmp1277 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %A
+ store <4 x float> %tmp1277, <4 x float>* null
+ ret void
+}
+
+define <4 x float> @t1(<4 x float> %a, <4 x float> %b) {
+entry:
+ %tmp9 = bitcast <4 x float> %a to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp10 = bitcast <4 x float> %b to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp11 = xor <4 x i32> %tmp9, %tmp10 ; <<4 x i32>> [#uses=1]
+ %tmp13 = bitcast <4 x i32> %tmp11 to <4 x float> ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp13
+}
+
+define <2 x double> @t2(<2 x double> %a, <2 x double> %b) {
+entry:
+ %tmp9 = bitcast <2 x double> %a to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp10 = bitcast <2 x double> %b to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp11 = and <2 x i64> %tmp9, %tmp10 ; <<2 x i64>> [#uses=1]
+ %tmp13 = bitcast <2 x i64> %tmp11 to <2 x double> ; <<2 x double>> [#uses=1]
+ ret <2 x double> %tmp13
+}
+
+define void @t3(<4 x float> %a, <4 x float> %b, <4 x float>* %c, <4 x float>* %d) {
+entry:
+ %tmp3 = load <4 x float>* %c ; <<4 x float>> [#uses=1]
+ %tmp11 = bitcast <4 x float> %a to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp12 = bitcast <4 x float> %b to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp13 = xor <4 x i32> %tmp11, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1]
+ %tmp14 = and <4 x i32> %tmp12, %tmp13 ; <<4 x i32>> [#uses=1]
+ %tmp27 = bitcast <4 x float> %tmp3 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp28 = or <4 x i32> %tmp14, %tmp27 ; <<4 x i32>> [#uses=1]
+ %tmp30 = bitcast <4 x i32> %tmp28 to <4 x float> ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp30, <4 x float>* %d
+ ret void
+}
diff --git a/test/CodeGen/X86/vec_return.ll b/test/CodeGen/X86/vec_return.ll
new file mode 100644
index 0000000..66762b4
--- /dev/null
+++ b/test/CodeGen/X86/vec_return.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
+; RUN: grep xorps %t | count 1
+; RUN: grep movaps %t | count 1
+; RUN: not grep shuf %t
+
+define <2 x double> @test() {
+ ret <2 x double> zeroinitializer
+}
+
+define <4 x i32> @test2() nounwind {
+ ret <4 x i32> < i32 0, i32 0, i32 1, i32 0 >
+}
diff --git a/test/CodeGen/X86/vec_select.ll b/test/CodeGen/X86/vec_select.ll
new file mode 100644
index 0000000..033e9f7
--- /dev/null
+++ b/test/CodeGen/X86/vec_select.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mattr=+sse
+
+define void @test(i32 %C, <4 x float>* %A, <4 x float>* %B) {
+ %tmp = load <4 x float>* %A ; <<4 x float>> [#uses=1]
+ %tmp3 = load <4 x float>* %B ; <<4 x float>> [#uses=2]
+ %tmp9 = fmul <4 x float> %tmp3, %tmp3 ; <<4 x float>> [#uses=1]
+ %tmp.upgrd.1 = icmp eq i32 %C, 0 ; <i1> [#uses=1]
+ %iftmp.38.0 = select i1 %tmp.upgrd.1, <4 x float> %tmp9, <4 x float> %tmp ; <<4 x float>> [#uses=1]
+ store <4 x float> %iftmp.38.0, <4 x float>* %A
+ ret void
+}
+
diff --git a/test/CodeGen/X86/vec_set-2.ll b/test/CodeGen/X86/vec_set-2.ll
new file mode 100644
index 0000000..a8f1187
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-2.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movss | count 1
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 1
+
+define <4 x float> @test1(float %a) nounwind {
+ %tmp = insertelement <4 x float> zeroinitializer, float %a, i32 0 ; <<4 x float>> [#uses=1]
+ %tmp5 = insertelement <4 x float> %tmp, float 0.000000e+00, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp6 = insertelement <4 x float> %tmp5, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp7 = insertelement <4 x float> %tmp6, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp7
+}
+
+define <2 x i64> @test(i32 %a) nounwind {
+ %tmp = insertelement <4 x i32> zeroinitializer, i32 %a, i32 0 ; <<8 x i16>> [#uses=1]
+ %tmp6 = insertelement <4 x i32> %tmp, i32 0, i32 1 ; <<8 x i32>> [#uses=1]
+ %tmp8 = insertelement <4 x i32> %tmp6, i32 0, i32 2 ; <<8 x i32>> [#uses=1]
+ %tmp10 = insertelement <4 x i32> %tmp8, i32 0, i32 3 ; <<8 x i32>> [#uses=1]
+ %tmp19 = bitcast <4 x i32> %tmp10 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp19
+}
diff --git a/test/CodeGen/X86/vec_set-3.ll b/test/CodeGen/X86/vec_set-3.ll
new file mode 100644
index 0000000..ada17e0
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-3.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
+; RUN: grep pshufd %t | count 2
+
+define <4 x float> @test(float %a) nounwind {
+ %tmp = insertelement <4 x float> zeroinitializer, float %a, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp5 = insertelement <4 x float> %tmp, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp6 = insertelement <4 x float> %tmp5, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp6
+}
+
+define <2 x i64> @test2(i32 %a) nounwind {
+ %tmp7 = insertelement <4 x i32> zeroinitializer, i32 %a, i32 2 ; <<4 x i32>> [#uses=1]
+ %tmp9 = insertelement <4 x i32> %tmp7, i32 0, i32 3 ; <<4 x i32>> [#uses=1]
+ %tmp10 = bitcast <4 x i32> %tmp9 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp10
+}
+
diff --git a/test/CodeGen/X86/vec_set-4.ll b/test/CodeGen/X86/vec_set-4.ll
new file mode 100644
index 0000000..332c8b7
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-4.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pinsrw | count 2
+
+define <2 x i64> @test(i16 %a) nounwind {
+entry:
+ %tmp10 = insertelement <8 x i16> zeroinitializer, i16 %a, i32 3 ; <<8 x i16>> [#uses=1]
+ %tmp12 = insertelement <8 x i16> %tmp10, i16 0, i32 4 ; <<8 x i16>> [#uses=1]
+ %tmp14 = insertelement <8 x i16> %tmp12, i16 0, i32 5 ; <<8 x i16>> [#uses=1]
+ %tmp16 = insertelement <8 x i16> %tmp14, i16 0, i32 6 ; <<8 x i16>> [#uses=1]
+ %tmp18 = insertelement <8 x i16> %tmp16, i16 0, i32 7 ; <<8 x i16>> [#uses=1]
+ %tmp19 = bitcast <8 x i16> %tmp18 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp19
+}
+
+define <2 x i64> @test2(i8 %a) nounwind {
+entry:
+ %tmp24 = insertelement <16 x i8> zeroinitializer, i8 %a, i32 10 ; <<16 x i8>> [#uses=1]
+ %tmp26 = insertelement <16 x i8> %tmp24, i8 0, i32 11 ; <<16 x i8>> [#uses=1]
+ %tmp28 = insertelement <16 x i8> %tmp26, i8 0, i32 12 ; <<16 x i8>> [#uses=1]
+ %tmp30 = insertelement <16 x i8> %tmp28, i8 0, i32 13 ; <<16 x i8>> [#uses=1]
+ %tmp32 = insertelement <16 x i8> %tmp30, i8 0, i32 14 ; <<16 x i8>> [#uses=1]
+ %tmp34 = insertelement <16 x i8> %tmp32, i8 0, i32 15 ; <<16 x i8>> [#uses=1]
+ %tmp35 = bitcast <16 x i8> %tmp34 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp35
+}
diff --git a/test/CodeGen/X86/vec_set-5.ll b/test/CodeGen/X86/vec_set-5.ll
new file mode 100644
index 0000000..f811a74
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-5.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
+; RUN: grep movlhps %t | count 1
+; RUN: grep movq %t | count 2
+
+define <4 x float> @test1(float %a, float %b) nounwind {
+ %tmp = insertelement <4 x float> zeroinitializer, float %a, i32 0 ; <<4 x float>> [#uses=1]
+ %tmp6 = insertelement <4 x float> %tmp, float 0.000000e+00, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp8 = insertelement <4 x float> %tmp6, float %b, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp9 = insertelement <4 x float> %tmp8, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp9
+}
+
+define <4 x float> @test2(float %a, float %b) nounwind {
+ %tmp = insertelement <4 x float> zeroinitializer, float %a, i32 0 ; <<4 x float>> [#uses=1]
+ %tmp7 = insertelement <4 x float> %tmp, float %b, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp8 = insertelement <4 x float> %tmp7, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp9 = insertelement <4 x float> %tmp8, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp9
+}
+
+define <2 x i64> @test3(i32 %a, i32 %b) nounwind {
+ %tmp = insertelement <4 x i32> zeroinitializer, i32 %a, i32 0 ; <<4 x i32>> [#uses=1]
+ %tmp6 = insertelement <4 x i32> %tmp, i32 %b, i32 1 ; <<4 x i32>> [#uses=1]
+ %tmp8 = insertelement <4 x i32> %tmp6, i32 0, i32 2 ; <<4 x i32>> [#uses=1]
+ %tmp10 = insertelement <4 x i32> %tmp8, i32 0, i32 3 ; <<4 x i32>> [#uses=1]
+ %tmp11 = bitcast <4 x i32> %tmp10 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp11
+}
diff --git a/test/CodeGen/X86/vec_set-6.ll b/test/CodeGen/X86/vec_set-6.ll
new file mode 100644
index 0000000..0713d95
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-6.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
+; RUN: grep movss %t | count 1
+; RUN: grep movq %t | count 1
+; RUN: grep shufps %t | count 1
+
+define <4 x float> @test(float %a, float %b, float %c) nounwind {
+ %tmp = insertelement <4 x float> zeroinitializer, float %a, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp8 = insertelement <4 x float> %tmp, float %b, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp10 = insertelement <4 x float> %tmp8, float %c, i32 3 ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp10
+}
+
diff --git a/test/CodeGen/X86/vec_set-7.ll b/test/CodeGen/X86/vec_set-7.ll
new file mode 100644
index 0000000..d993178
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-7.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movsd | count 1
+
+define <2 x i64> @test(<2 x i64>* %p) nounwind {
+ %tmp = bitcast <2 x i64>* %p to double*
+ %tmp.upgrd.1 = load double* %tmp
+ %tmp.upgrd.2 = insertelement <2 x double> undef, double %tmp.upgrd.1, i32 0
+ %tmp5 = insertelement <2 x double> %tmp.upgrd.2, double 0.0, i32 1
+ %tmp.upgrd.3 = bitcast <2 x double> %tmp5 to <2 x i64>
+ ret <2 x i64> %tmp.upgrd.3
+}
+
diff --git a/test/CodeGen/X86/vec_set-8.ll b/test/CodeGen/X86/vec_set-8.ll
new file mode 100644
index 0000000..9697f11
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-8.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86-64 | not grep movsd
+; RUN: llc < %s -march=x86-64 | grep {movd.*%rdi,.*%xmm0}
+
+define <2 x i64> @test(i64 %i) nounwind {
+entry:
+ %tmp10 = insertelement <2 x i64> undef, i64 %i, i32 0
+ %tmp11 = insertelement <2 x i64> %tmp10, i64 0, i32 1
+ ret <2 x i64> %tmp11
+}
+
diff --git a/test/CodeGen/X86/vec_set-9.ll b/test/CodeGen/X86/vec_set-9.ll
new file mode 100644
index 0000000..3656e5f
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-9.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86-64 | grep movd | count 1
+; RUN: llc < %s -march=x86-64 | grep {movlhps.*%xmm0, %xmm0}
+
+define <2 x i64> @test3(i64 %A) nounwind {
+entry:
+ %B = insertelement <2 x i64> undef, i64 %A, i32 1
+ ret <2 x i64> %B
+}
+
diff --git a/test/CodeGen/X86/vec_set-A.ll b/test/CodeGen/X86/vec_set-A.ll
new file mode 100644
index 0000000..f05eecf
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-A.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {movl.*\$1, %}
+define <2 x i64> @test1() nounwind {
+entry:
+ ret <2 x i64> < i64 1, i64 0 >
+}
+
diff --git a/test/CodeGen/X86/vec_set-B.ll b/test/CodeGen/X86/vec_set-B.ll
new file mode 100644
index 0000000..f5b3e8b
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-B.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep movaps
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep esp | count 2
+
+; These should both generate something like this:
+;_test3:
+; movl $1234567, %eax
+; andl 4(%esp), %eax
+; movd %eax, %xmm0
+; ret
+
+define <2 x i64> @test3(i64 %arg) nounwind {
+entry:
+ %A = and i64 %arg, 1234567
+ %B = insertelement <2 x i64> zeroinitializer, i64 %A, i32 0
+ ret <2 x i64> %B
+}
+
+define <2 x i64> @test2(i64 %arg) nounwind {
+entry:
+ %A = and i64 %arg, 1234567
+ %B = insertelement <2 x i64> undef, i64 %A, i32 0
+ ret <2 x i64> %B
+}
+
diff --git a/test/CodeGen/X86/vec_set-C.ll b/test/CodeGen/X86/vec_set-C.ll
new file mode 100644
index 0000000..7636ac3
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-C.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep mov | count 1
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd
+
+define <2 x i64> @t1(i64 %x) nounwind {
+ %tmp8 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
+ ret <2 x i64> %tmp8
+}
diff --git a/test/CodeGen/X86/vec_set-D.ll b/test/CodeGen/X86/vec_set-D.ll
new file mode 100644
index 0000000..3d6369e
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-D.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
+
+define <4 x i32> @t(i32 %x, i32 %y) nounwind {
+ %tmp1 = insertelement <4 x i32> zeroinitializer, i32 %x, i32 0
+ %tmp2 = insertelement <4 x i32> %tmp1, i32 %y, i32 1
+ ret <4 x i32> %tmp2
+}
diff --git a/test/CodeGen/X86/vec_set-E.ll b/test/CodeGen/X86/vec_set-E.ll
new file mode 100644
index 0000000..d78be66
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-E.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
+
+define <4 x float> @t(float %X) nounwind {
+ %tmp11 = insertelement <4 x float> undef, float %X, i32 0
+ %tmp12 = insertelement <4 x float> %tmp11, float %X, i32 1
+ %tmp27 = insertelement <4 x float> %tmp12, float 0.000000e+00, i32 2
+ %tmp28 = insertelement <4 x float> %tmp27, float 0.000000e+00, i32 3
+ ret <4 x float> %tmp28
+}
diff --git a/test/CodeGen/X86/vec_set-F.ll b/test/CodeGen/X86/vec_set-F.ll
new file mode 100644
index 0000000..4f0acb2
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-F.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movsd
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep mov | count 3
+
+define <2 x i64> @t1(<2 x i64>* %ptr) nounwind {
+ %tmp45 = bitcast <2 x i64>* %ptr to <2 x i32>*
+ %tmp615 = load <2 x i32>* %tmp45
+ %tmp7 = bitcast <2 x i32> %tmp615 to i64
+ %tmp8 = insertelement <2 x i64> zeroinitializer, i64 %tmp7, i32 0
+ ret <2 x i64> %tmp8
+}
+
+define <2 x i64> @t2(i64 %x) nounwind {
+ %tmp717 = bitcast i64 %x to double
+ %tmp8 = insertelement <2 x double> undef, double %tmp717, i32 0
+ %tmp9 = insertelement <2 x double> %tmp8, double 0.000000e+00, i32 1
+ %tmp11 = bitcast <2 x double> %tmp9 to <2 x i64>
+ ret <2 x i64> %tmp11
+}
diff --git a/test/CodeGen/X86/vec_set-G.ll b/test/CodeGen/X86/vec_set-G.ll
new file mode 100644
index 0000000..4a542fe
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-G.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movss
+
+define fastcc void @t(<4 x float> %A) nounwind {
+ %tmp41896 = extractelement <4 x float> %A, i32 0 ; <float> [#uses=1]
+ %tmp14082 = insertelement <4 x float> < float 0.000000e+00, float undef, float undef, float undef >, float %tmp41896, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp14083 = insertelement <4 x float> %tmp14082, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp14083, <4 x float>* null, align 16
+ ret void
+}
diff --git a/test/CodeGen/X86/vec_set-H.ll b/test/CodeGen/X86/vec_set-H.ll
new file mode 100644
index 0000000..5037e36
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-H.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep movz
+
+define <2 x i64> @doload64(i16 signext %x) nounwind {
+entry:
+ %tmp36 = insertelement <8 x i16> undef, i16 %x, i32 0 ; <<8 x i16>> [#uses=1]
+ %tmp37 = insertelement <8 x i16> %tmp36, i16 %x, i32 1 ; <<8 x i16>> [#uses=1]
+ %tmp38 = insertelement <8 x i16> %tmp37, i16 %x, i32 2 ; <<8 x i16>> [#uses=1]
+ %tmp39 = insertelement <8 x i16> %tmp38, i16 %x, i32 3 ; <<8 x i16>> [#uses=1]
+ %tmp40 = insertelement <8 x i16> %tmp39, i16 %x, i32 4 ; <<8 x i16>> [#uses=1]
+ %tmp41 = insertelement <8 x i16> %tmp40, i16 %x, i32 5 ; <<8 x i16>> [#uses=1]
+ %tmp42 = insertelement <8 x i16> %tmp41, i16 %x, i32 6 ; <<8 x i16>> [#uses=1]
+ %tmp43 = insertelement <8 x i16> %tmp42, i16 %x, i32 7 ; <<8 x i16>> [#uses=1]
+ %tmp46 = bitcast <8 x i16> %tmp43 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp46
+}
diff --git a/test/CodeGen/X86/vec_set-I.ll b/test/CodeGen/X86/vec_set-I.ll
new file mode 100644
index 0000000..64f36f9
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-I.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep xorp
+
+define void @t1() nounwind {
+ %tmp298.i.i = load <4 x float>* null, align 16
+ %tmp304.i.i = bitcast <4 x float> %tmp298.i.i to <4 x i32>
+ %tmp305.i.i = and <4 x i32> %tmp304.i.i, < i32 -1, i32 0, i32 0, i32 0 >
+ store <4 x i32> %tmp305.i.i, <4 x i32>* null, align 16
+ unreachable
+}
diff --git a/test/CodeGen/X86/vec_set-J.ll b/test/CodeGen/X86/vec_set-J.ll
new file mode 100644
index 0000000..d90ab85
--- /dev/null
+++ b/test/CodeGen/X86/vec_set-J.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movss
+; PR2472
+
+define <4 x i32> @a(<4 x i32> %a) nounwind {
+entry:
+ %vecext = extractelement <4 x i32> %a, i32 0
+ insertelement <4 x i32> zeroinitializer, i32 %vecext, i32 0
+ %add = add <4 x i32> %a, %0
+ ret <4 x i32> %add
+}
diff --git a/test/CodeGen/X86/vec_set.ll b/test/CodeGen/X86/vec_set.ll
new file mode 100644
index 0000000..c316df8
--- /dev/null
+++ b/test/CodeGen/X86/vec_set.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep punpckl | count 7
+
+define void @test(<8 x i16>* %b, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind {
+ %tmp = insertelement <8 x i16> zeroinitializer, i16 %a0, i32 0 ; <<8 x i16>> [#uses=1]
+ %tmp2 = insertelement <8 x i16> %tmp, i16 %a1, i32 1 ; <<8 x i16>> [#uses=1]
+ %tmp4 = insertelement <8 x i16> %tmp2, i16 %a2, i32 2 ; <<8 x i16>> [#uses=1]
+ %tmp6 = insertelement <8 x i16> %tmp4, i16 %a3, i32 3 ; <<8 x i16>> [#uses=1]
+ %tmp8 = insertelement <8 x i16> %tmp6, i16 %a4, i32 4 ; <<8 x i16>> [#uses=1]
+ %tmp10 = insertelement <8 x i16> %tmp8, i16 %a5, i32 5 ; <<8 x i16>> [#uses=1]
+ %tmp12 = insertelement <8 x i16> %tmp10, i16 %a6, i32 6 ; <<8 x i16>> [#uses=1]
+ %tmp14 = insertelement <8 x i16> %tmp12, i16 %a7, i32 7 ; <<8 x i16>> [#uses=1]
+ store <8 x i16> %tmp14, <8 x i16>* %b
+ ret void
+}
+
diff --git a/test/CodeGen/X86/vec_shift.ll b/test/CodeGen/X86/vec_shift.ll
new file mode 100644
index 0000000..ddf0469
--- /dev/null
+++ b/test/CodeGen/X86/vec_shift.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psllw
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psrlq
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psraw
+
+define <2 x i64> @t1(<2 x i64> %b1, <2 x i64> %c) nounwind {
+entry:
+ %tmp6 = bitcast <2 x i64> %c to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp8 = bitcast <2 x i64> %b1 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp9 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp8, <8 x i16> %tmp6 ) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp10 = bitcast <8 x i16> %tmp9 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp10
+}
+
+define <2 x i64> @t3(<2 x i64> %b1, i32 %c) nounwind {
+entry:
+ %tmp2 = bitcast <2 x i64> %b1 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp4 = insertelement <4 x i32> undef, i32 %c, i32 0 ; <<4 x i32>> [#uses=1]
+ %tmp8 = bitcast <4 x i32> %tmp4 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp9 = tail call <8 x i16> @llvm.x86.sse2.psra.w( <8 x i16> %tmp2, <8 x i16> %tmp8 ) ; <<8 x i16>> [#uses=1]
+ %tmp11 = bitcast <8 x i16> %tmp9 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp11
+}
+
+declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <2 x i64> @t2(<2 x i64> %b1, <2 x i64> %c) nounwind {
+entry:
+ %tmp9 = tail call <2 x i64> @llvm.x86.sse2.psrl.q( <2 x i64> %b1, <2 x i64> %c ) nounwind readnone ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp9
+}
+
+declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
diff --git a/test/CodeGen/X86/vec_shift2.ll b/test/CodeGen/X86/vec_shift2.ll
new file mode 100644
index 0000000..c5f9dc4
--- /dev/null
+++ b/test/CodeGen/X86/vec_shift2.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep CPI
+
+define <2 x i64> @t1(<2 x i64> %b1, <2 x i64> %c) nounwind {
+ %tmp1 = bitcast <2 x i64> %b1 to <8 x i16>
+ %tmp2 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp1, <8 x i16> bitcast (<4 x i32> < i32 14, i32 undef, i32 undef, i32 undef > to <8 x i16>) ) nounwind readnone
+ %tmp3 = bitcast <8 x i16> %tmp2 to <2 x i64>
+ ret <2 x i64> %tmp3
+}
+
+define <4 x i32> @t2(<2 x i64> %b1, <2 x i64> %c) nounwind {
+ %tmp1 = bitcast <2 x i64> %b1 to <4 x i32>
+ %tmp2 = tail call <4 x i32> @llvm.x86.sse2.psll.d( <4 x i32> %tmp1, <4 x i32> < i32 14, i32 undef, i32 undef, i32 undef > ) nounwind readnone
+ ret <4 x i32> %tmp2
+}
+
+declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone
diff --git a/test/CodeGen/X86/vec_shift3.ll b/test/CodeGen/X86/vec_shift3.ll
new file mode 100644
index 0000000..1ebf455
--- /dev/null
+++ b/test/CodeGen/X86/vec_shift3.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psllq
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psraw
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 2
+
+define <2 x i64> @t1(<2 x i64> %x1, i32 %bits) nounwind {
+entry:
+ %tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 %bits ) nounwind readnone ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp3
+}
+
+define <2 x i64> @t2(<2 x i64> %x1) nounwind {
+entry:
+ %tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 10 ) nounwind readnone ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp3
+}
+
+define <2 x i64> @t3(<2 x i64> %x1, i32 %bits) nounwind {
+entry:
+ %tmp2 = bitcast <2 x i64> %x1 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp4 = tail call <8 x i16> @llvm.x86.sse2.psrai.w( <8 x i16> %tmp2, i32 %bits ) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp5 = bitcast <8 x i16> %tmp4 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp5
+}
+
+declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone
+declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone
diff --git a/test/CodeGen/X86/vec_shuffle-10.ll b/test/CodeGen/X86/vec_shuffle-10.ll
new file mode 100644
index 0000000..a63e386
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-10.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
+; RUN: grep unpcklps %t | count 1
+; RUN: grep pshufd %t | count 1
+; RUN: not grep {sub.*esp} %t
+
+define void @test(<4 x float>* %res, <4 x float>* %A, <4 x float>* %B) {
+ %tmp = load <4 x float>* %B ; <<4 x float>> [#uses=2]
+ %tmp3 = load <4 x float>* %A ; <<4 x float>> [#uses=2]
+ %tmp.upgrd.1 = extractelement <4 x float> %tmp3, i32 0 ; <float> [#uses=1]
+ %tmp7 = extractelement <4 x float> %tmp, i32 0 ; <float> [#uses=1]
+ %tmp8 = extractelement <4 x float> %tmp3, i32 1 ; <float> [#uses=1]
+ %tmp9 = extractelement <4 x float> %tmp, i32 1 ; <float> [#uses=1]
+ %tmp10 = insertelement <4 x float> undef, float %tmp.upgrd.1, i32 0 ; <<4 x float>> [#uses=1]
+ %tmp11 = insertelement <4 x float> %tmp10, float %tmp7, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp12 = insertelement <4 x float> %tmp11, float %tmp8, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp13 = insertelement <4 x float> %tmp12, float %tmp9, i32 3 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp13, <4 x float>* %res
+ ret void
+}
+
+define void @test2(<4 x float> %X, <4 x float>* %res) {
+ %tmp5 = shufflevector <4 x float> %X, <4 x float> undef, <4 x i32> < i32 2, i32 6, i32 3, i32 7 > ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp5, <4 x float>* %res
+ ret void
+}
diff --git a/test/CodeGen/X86/vec_shuffle-11.ll b/test/CodeGen/X86/vec_shuffle-11.ll
new file mode 100644
index 0000000..640745a
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-11.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin | not grep mov
+
+define <4 x i32> @test() nounwind {
+ %tmp131 = call <2 x i64> @llvm.x86.sse2.psrl.dq( <2 x i64> < i64 -1, i64 -1 >, i32 96 ) ; <<2 x i64>> [#uses=1]
+ %tmp137 = bitcast <2 x i64> %tmp131 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp138 = and <4 x i32> %tmp137, bitcast (<2 x i64> < i64 -1, i64 -1 > to <4 x i32>) ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %tmp138
+}
+
+declare <2 x i64> @llvm.x86.sse2.psrl.dq(<2 x i64>, i32)
diff --git a/test/CodeGen/X86/vec_shuffle-14.ll b/test/CodeGen/X86/vec_shuffle-14.ll
new file mode 100644
index 0000000..f0cfc44
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-14.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 1
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd | count 2
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq | count 3
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep xor
+
+define <4 x i32> @t1(i32 %a) nounwind {
+entry:
+ %tmp = insertelement <4 x i32> undef, i32 %a, i32 0
+ %tmp6 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp, <4 x i32> < i32 4, i32 1, i32 2, i32 3 > ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %tmp6
+}
+
+define <2 x i64> @t2(i64 %a) nounwind {
+entry:
+ %tmp = insertelement <2 x i64> undef, i64 %a, i32 0
+ %tmp6 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %tmp, <2 x i32> < i32 2, i32 1 > ; <<4 x i32>> [#uses=1]
+ ret <2 x i64> %tmp6
+}
+
+define <2 x i64> @t3(<2 x i64>* %a) nounwind {
+entry:
+ %tmp4 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1]
+ %tmp6 = bitcast <2 x i64> %tmp4 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp7 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp6, <4 x i32> < i32 4, i32 5, i32 2, i32 3 > ; <<4 x i32>> [#uses=1]
+ %tmp8 = bitcast <4 x i32> %tmp7 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp8
+}
+
+define <2 x i64> @t4(<2 x i64> %a) nounwind {
+entry:
+ %tmp5 = bitcast <2 x i64> %a to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp6 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp5, <4 x i32> < i32 4, i32 5, i32 2, i32 3 > ; <<4 x i32>> [#uses=1]
+ %tmp7 = bitcast <4 x i32> %tmp6 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp7
+}
+
+define <2 x i64> @t5(<2 x i64> %a) nounwind {
+entry:
+ %tmp6 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %a, <2 x i32> < i32 2, i32 1 > ; <<4 x i32>> [#uses=1]
+ ret <2 x i64> %tmp6
+}
diff --git a/test/CodeGen/X86/vec_shuffle-15.ll b/test/CodeGen/X86/vec_shuffle-15.ll
new file mode 100644
index 0000000..5a9b8fd
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-15.ll
@@ -0,0 +1,81 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+
+define <2 x i64> @t00(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 0, i32 0 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t01(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 0, i32 1 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t02(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 0, i32 2 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t03(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 0, i32 3 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t10(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 1, i32 0 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t11(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 1, i32 1 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t12(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 1, i32 2 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t13(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 1, i32 3 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t20(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 2, i32 0 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t21(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 2, i32 1 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t22(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 2, i32 2 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t23(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 2, i32 3 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t30(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 3, i32 0 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t31(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 3, i32 1 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t32(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 3, i32 2 >
+ ret <2 x i64> %tmp
+}
+
+define <2 x i64> @t33(<2 x i64> %a, <2 x i64> %b) nounwind {
+ %tmp = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> < i32 3, i32 3 >
+ ret <2 x i64> %tmp
+}
diff --git a/test/CodeGen/X86/vec_shuffle-16.ll b/test/CodeGen/X86/vec_shuffle-16.ll
new file mode 100644
index 0000000..470f676
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-16.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=x86 -mattr=+sse,-sse2 -mtriple=i386-apple-darwin -o %t
+; RUN: grep shufps %t | count 4
+; RUN: grep movaps %t | count 2
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -o %t
+; RUN: grep pshufd %t | count 4
+; RUN: not grep shufps %t
+; RUN: not grep mov %t
+
+define <4 x float> @t1(<4 x float> %a, <4 x float> %b) nounwind {
+ %tmp1 = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
+ ret <4 x float> %tmp1
+}
+
+define <4 x float> @t2(<4 x float> %A, <4 x float> %B) nounwind {
+ %tmp = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >
+ ret <4 x float> %tmp
+}
+
+define <4 x float> @t3(<4 x float> %A, <4 x float> %B) nounwind {
+ %tmp = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> < i32 4, i32 4, i32 4, i32 4 >
+ ret <4 x float> %tmp
+}
+
+define <4 x float> @t4(<4 x float> %A, <4 x float> %B) nounwind {
+ %tmp = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> < i32 1, i32 3, i32 2, i32 0 >
+ ret <4 x float> %tmp
+}
diff --git a/test/CodeGen/X86/vec_shuffle-17.ll b/test/CodeGen/X86/vec_shuffle-17.ll
new file mode 100644
index 0000000..9c33abb
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-17.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86-64 | grep {movd.*%rdi, %xmm0}
+; RUN: llc < %s -march=x86-64 | not grep xor
+; PR2108
+
+define <2 x i64> @doload64(i64 %x) nounwind {
+entry:
+ %tmp717 = bitcast i64 %x to double ; <double> [#uses=1]
+ %tmp8 = insertelement <2 x double> undef, double %tmp717, i32 0 ; <<2 x double>> [#uses=1]
+ %tmp9 = insertelement <2 x double> %tmp8, double 0.000000e+00, i32 1 ; <<2 x double>> [#uses=1]
+ %tmp11 = bitcast <2 x double> %tmp9 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp11
+}
+
diff --git a/test/CodeGen/X86/vec_shuffle-18.ll b/test/CodeGen/X86/vec_shuffle-18.ll
new file mode 100644
index 0000000..1104a4a8
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-18.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin8.8.0 | grep mov | count 7
+
+ %struct.vector4_t = type { <4 x float> }
+
+define void @swizzle(i8* %a, %struct.vector4_t* %b, %struct.vector4_t* %c) nounwind {
+entry:
+ %tmp9 = getelementptr %struct.vector4_t* %b, i32 0, i32 0 ; <<4 x float>*> [#uses=2]
+ %tmp10 = load <4 x float>* %tmp9, align 16 ; <<4 x float>> [#uses=1]
+ %tmp14 = bitcast i8* %a to double* ; <double*> [#uses=1]
+ %tmp15 = load double* %tmp14 ; <double> [#uses=1]
+ %tmp16 = insertelement <2 x double> undef, double %tmp15, i32 0 ; <<2 x double>> [#uses=1]
+ %tmp18 = bitcast <2 x double> %tmp16 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp19 = shufflevector <4 x float> %tmp10, <4 x float> %tmp18, <4 x i32> < i32 4, i32 5, i32 2, i32 3 > ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp19, <4 x float>* %tmp9, align 16
+ %tmp28 = getelementptr %struct.vector4_t* %c, i32 0, i32 0 ; <<4 x float>*> [#uses=2]
+ %tmp29 = load <4 x float>* %tmp28, align 16 ; <<4 x float>> [#uses=1]
+ %tmp26 = getelementptr i8* %a, i32 8 ; <i8*> [#uses=1]
+ %tmp33 = bitcast i8* %tmp26 to double* ; <double*> [#uses=1]
+ %tmp34 = load double* %tmp33 ; <double> [#uses=1]
+ %tmp35 = insertelement <2 x double> undef, double %tmp34, i32 0 ; <<2 x double>> [#uses=1]
+ %tmp37 = bitcast <2 x double> %tmp35 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp38 = shufflevector <4 x float> %tmp29, <4 x float> %tmp37, <4 x i32> < i32 4, i32 5, i32 2, i32 3 > ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp38, <4 x float>* %tmp28, align 16
+ ret void
+}
diff --git a/test/CodeGen/X86/vec_shuffle-19.ll b/test/CodeGen/X86/vec_shuffle-19.ll
new file mode 100644
index 0000000..9fc09df
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-19.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 4
+; PR2485
+
+define <4 x i32> @t(<4 x i32> %a, <4 x i32> %b) nounwind {
+entry:
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> < i32 4, i32 0, i32 0, i32 0 > ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %shuffle
+}
diff --git a/test/CodeGen/X86/vec_shuffle-20.ll b/test/CodeGen/X86/vec_shuffle-20.ll
new file mode 100644
index 0000000..6d1bac0
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-20.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 3
+
+define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) nounwind {
+entry:
+ shufflevector <4 x float> %fp0, <4 x float> %fp1, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:0 [#uses=1]
+ ret <4 x float> %0
+}
diff --git a/test/CodeGen/X86/vec_shuffle-22.ll b/test/CodeGen/X86/vec_shuffle-22.ll
new file mode 100644
index 0000000..6807e4d
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-22.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mcpu=pentium-m | FileCheck %s
+
+define <4 x float> @t1(<4 x float> %a) nounwind {
+; CHECK: movlhps
+ %tmp1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> < i32 0, i32 1, i32 0, i32 1 > ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp1
+}
+
+define <4 x i32> @t2(<4 x i32>* %a) nounwind {
+; CHECK: pshufd
+; CHECK: ret
+ %tmp1 = load <4 x i32>* %a
+ %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> < i32 0, i32 1, i32 0, i32 1 > ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %tmp2
+}
diff --git a/test/CodeGen/X86/vec_shuffle-23.ll b/test/CodeGen/X86/vec_shuffle-23.ll
new file mode 100644
index 0000000..05a3a1e
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-23.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep punpck
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pshufd
+
+define i32 @t() nounwind {
+entry:
+ %a = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
+ %b = alloca <4 x i32> ; <<4 x i32>*> [#uses=5]
+ volatile store <4 x i32> < i32 0, i32 1, i32 2, i32 3 >, <4 x i32>* %a
+ %tmp = load <4 x i32>* %a ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %tmp, <4 x i32>* %b
+ %tmp1 = load <4 x i32>* %b ; <<4 x i32>> [#uses=1]
+ %tmp2 = load <4 x i32>* %b ; <<4 x i32>> [#uses=1]
+ %punpckldq = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %punpckldq, <4 x i32>* %b
+ %tmp3 = load <4 x i32>* %b ; <<4 x i32>> [#uses=1]
+ %result = extractelement <4 x i32> %tmp3, i32 0 ; <i32> [#uses=1]
+ ret i32 %result
+}
diff --git a/test/CodeGen/X86/vec_shuffle-24.ll b/test/CodeGen/X86/vec_shuffle-24.ll
new file mode 100644
index 0000000..7562f1d
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-24.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep punpck
+
+define i32 @t() nounwind optsize {
+entry:
+ %a = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
+ %b = alloca <4 x i32> ; <<4 x i32>*> [#uses=5]
+ volatile store <4 x i32> < i32 0, i32 1, i32 2, i32 3 >, <4 x i32>* %a
+ %tmp = load <4 x i32>* %a ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %tmp, <4 x i32>* %b
+ %tmp1 = load <4 x i32>* %b ; <<4 x i32>> [#uses=1]
+ %tmp2 = load <4 x i32>* %b ; <<4 x i32>> [#uses=1]
+ %punpckldq = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %punpckldq, <4 x i32>* %b
+ %tmp3 = load <4 x i32>* %b ; <<4 x i32>> [#uses=1]
+ %result = extractelement <4 x i32> %tmp3, i32 0 ; <i32> [#uses=1]
+ ret i32 %result
+}
diff --git a/test/CodeGen/X86/vec_shuffle-25.ll b/test/CodeGen/X86/vec_shuffle-25.ll
new file mode 100644
index 0000000..d9b2388
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-25.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
+; RUN: grep unpcklps %t | count 3
+; RUN: grep unpckhps %t | count 1
+
+; Transpose example using the more generic vector shuffle. We return
+; float8 instead of float16 since x86 can return that in register.
+; ModuleID = 'transpose2_opt.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-apple-cl.1.0"
+@r0 = common global <4 x float> zeroinitializer, align 16 ; <<4 x float>*> [#uses=1]
+@r1 = common global <4 x float> zeroinitializer, align 16 ; <<4 x float>*> [#uses=1]
+@r2 = common global <4 x float> zeroinitializer, align 16 ; <<4 x float>*> [#uses=1]
+@r3 = common global <4 x float> zeroinitializer, align 16 ; <<4 x float>*> [#uses=1]
+
+define <8 x float> @__transpose2(<4 x float> %p0, <4 x float> %p1, <4 x float> %p2, <4 x float> %p3) nounwind {
+entry:
+ %unpcklps = shufflevector <4 x float> %p0, <4 x float> %p2, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x float>> [#uses=2]
+ %unpckhps = shufflevector <4 x float> %p0, <4 x float> %p2, <4 x i32> < i32 2, i32 6, i32 3, i32 7 > ; <<4 x float>> [#uses=2]
+ %unpcklps8 = shufflevector <4 x float> %p1, <4 x float> %p3, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x float>> [#uses=2]
+ %unpckhps11 = shufflevector <4 x float> %p1, <4 x float> %p3, <4 x i32> < i32 2, i32 6, i32 3, i32 7 > ; <<4 x float>> [#uses=2]
+ %unpcklps14 = shufflevector <4 x float> %unpcklps, <4 x float> %unpcklps8, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x float>> [#uses=1]
+ %unpcklps14a = shufflevector <4 x float> %unpcklps14, <4 x float> undef, <16 x i32> < i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ %unpckhps17 = shufflevector <4 x float> %unpcklps, <4 x float> %unpcklps8, <4 x i32> < i32 2, i32 6, i32 3, i32 7 > ; <<4 x float>> [#uses=1]
+ %unpckhps17a = shufflevector <4 x float> %unpckhps17, <4 x float> undef, <16 x i32> < i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ %r1 = shufflevector <16 x float> %unpcklps14a, <16 x float> %unpckhps17a, <16 x i32> < i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %unpcklps20 = shufflevector <4 x float> %unpckhps, <4 x float> %unpckhps11, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x float>> [#uses=1]
+ %unpcklps20a = shufflevector <4 x float> %unpcklps20, <4 x float> undef, <16 x i32> < i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ %r2 = shufflevector <16 x float> %r1, <16 x float> %unpcklps20a, <16 x i32> < i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 12, i32 13, i32 14, i32 15>
+ %unpckhps23 = shufflevector <4 x float> %unpckhps, <4 x float> %unpckhps11, <4 x i32> < i32 2, i32 6, i32 3, i32 7 > ; <<4 x float>> [#uses=1]
+ %unpckhps23a = shufflevector <4 x float> %unpckhps23, <4 x float> undef, <16 x i32> < i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+ %r3 = shufflevector <16 x float> %r2, <16 x float> %unpckhps23a, <16 x i32> < i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
+ %r4 = shufflevector <16 x float> %r3, <16 x float> undef, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x float> %r4
+}
diff --git a/test/CodeGen/X86/vec_shuffle-26.ll b/test/CodeGen/X86/vec_shuffle-26.ll
new file mode 100644
index 0000000..086af6b
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-26.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
+; RUN: grep unpcklps %t | count 1
+; RUN: grep unpckhps %t | count 3
+
+; Transpose example using the more generic vector shuffle. Return float8
+; instead of float16
+; ModuleID = 'transpose2_opt.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i386-apple-cl.1.0"
+@r0 = common global <4 x float> zeroinitializer, align 16 ; <<4 x float>*> [#uses=1]
+@r1 = common global <4 x float> zeroinitializer, align 16 ; <<4 x float>*> [#uses=1]
+@r2 = common global <4 x float> zeroinitializer, align 16 ; <<4 x float>*> [#uses=1]
+@r3 = common global <4 x float> zeroinitializer, align 16 ; <<4 x float>*> [#uses=1]
+
+define <8 x float> @__transpose2(<4 x float> %p0, <4 x float> %p1, <4 x float> %p2, <4 x float> %p3) nounwind {
+entry:
+ %unpcklps = shufflevector <4 x float> %p0, <4 x float> %p2, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x float>> [#uses=2]
+ %unpckhps = shufflevector <4 x float> %p0, <4 x float> %p2, <4 x i32> < i32 2, i32 6, i32 3, i32 7 > ; <<4 x float>> [#uses=2]
+ %unpcklps8 = shufflevector <4 x float> %p1, <4 x float> %p3, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x float>> [#uses=2]
+ %unpckhps11 = shufflevector <4 x float> %p1, <4 x float> %p3, <4 x i32> < i32 2, i32 6, i32 3, i32 7 > ; <<4 x float>> [#uses=2]
+ %unpcklps14 = shufflevector <4 x float> %unpcklps, <4 x float> %unpcklps8, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x float>> [#uses=1]
+ %unpckhps17 = shufflevector <4 x float> %unpcklps, <4 x float> %unpcklps8, <4 x i32> < i32 2, i32 6, i32 3, i32 7 > ; <<4 x float>> [#uses=1]
+ %r1 = shufflevector <4 x float> %unpcklps14, <4 x float> %unpckhps17, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
+ %unpcklps20 = shufflevector <4 x float> %unpckhps, <4 x float> %unpckhps11, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x float>> [#uses=1]
+ %unpckhps23 = shufflevector <4 x float> %unpckhps, <4 x float> %unpckhps11, <4 x i32> < i32 2, i32 6, i32 3, i32 7 > ; <<4 x float>> [#uses=1]
+ %r2 = shufflevector <4 x float> %unpcklps20, <4 x float> %unpckhps23, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
+; %r3 = shufflevector <8 x float> %r1, <8 x float> %r2, <16 x i32> < i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15 >;
+ ret <8 x float> %r2
+}
diff --git a/test/CodeGen/X86/vec_shuffle-27.ll b/test/CodeGen/X86/vec_shuffle-27.ll
new file mode 100644
index 0000000..d700ccb
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-27.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
+; RUN: grep addps %t | count 2
+; RUN: grep mulps %t | count 2
+; RUN: grep subps %t | count 2
+
+; ModuleID = 'vec_shuffle-27.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
+target triple = "i686-apple-cl.1.0"
+
+define <8 x float> @my2filter4_1d(<4 x float> %a, <8 x float> %T0, <8 x float> %T1) nounwind readnone {
+entry:
+ %tmp7 = shufflevector <4 x float> %a, <4 x float> undef, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3 > ; <<8 x float>> [#uses=1]
+ %sub = fsub <8 x float> %T1, %T0 ; <<8 x float>> [#uses=1]
+ %mul = fmul <8 x float> %sub, %tmp7 ; <<8 x float>> [#uses=1]
+ %add = fadd <8 x float> %mul, %T0 ; <<8 x float>> [#uses=1]
+ ret <8 x float> %add
+}
diff --git a/test/CodeGen/X86/vec_shuffle-28.ll b/test/CodeGen/X86/vec_shuffle-28.ll
new file mode 100644
index 0000000..343685b
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-28.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mcpu=core2 -o %t
+; RUN: grep pshufb %t | count 1
+
+; FIXME: this test has a superfluous punpcklqdq pre-pshufb currently.
+; Don't XFAIL it because it's still better than the previous code.
+
+; Pack various elements via shuffles.
+define <8 x i16> @shuf1(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp7 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 1, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
+ ret <8 x i16> %tmp7
+}
diff --git a/test/CodeGen/X86/vec_shuffle-3.ll b/test/CodeGen/X86/vec_shuffle-3.ll
new file mode 100644
index 0000000..f4930b0
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-3.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
+; RUN: grep movlhps %t | count 1
+; RUN: grep movhlps %t | count 1
+
+define <4 x float> @test1(<4 x float>* %x, <4 x float>* %y) {
+ %tmp = load <4 x float>* %y ; <<4 x float>> [#uses=2]
+ %tmp5 = load <4 x float>* %x ; <<4 x float>> [#uses=2]
+ %tmp9 = fadd <4 x float> %tmp5, %tmp ; <<4 x float>> [#uses=1]
+ %tmp21 = fsub <4 x float> %tmp5, %tmp ; <<4 x float>> [#uses=1]
+ %tmp27 = shufflevector <4 x float> %tmp9, <4 x float> %tmp21, <4 x i32> < i32 0, i32 1, i32 4, i32 5 > ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp27
+}
+
+define <4 x float> @movhl(<4 x float>* %x, <4 x float>* %y) {
+entry:
+ %tmp = load <4 x float>* %y ; <<4 x float>> [#uses=1]
+ %tmp3 = load <4 x float>* %x ; <<4 x float>> [#uses=1]
+ %tmp4 = shufflevector <4 x float> %tmp3, <4 x float> %tmp, <4 x i32> < i32 2, i32 3, i32 6, i32 7 > ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp4
+}
diff --git a/test/CodeGen/X86/vec_shuffle-30.ll b/test/CodeGen/X86/vec_shuffle-30.ll
new file mode 100644
index 0000000..3f69150
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-30.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=x86 -mattr=sse41 -disable-mmx -o %t
+; RUN: grep pshufhw %t | grep -- -95 | count 1
+; RUN: grep shufps %t | count 1
+; RUN: not grep pslldq %t
+
+; Test case when creating pshufhw, we incorrectly set the higher order bit
+; for an undef,
+define void @test(<8 x i16>* %dest, <8 x i16> %in) nounwind {
+entry:
+ %0 = load <8 x i16>* %dest
+ %1 = shufflevector <8 x i16> %0, <8 x i16> %in, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 13, i32 undef, i32 14, i32 14>
+ store <8 x i16> %1, <8 x i16>* %dest
+ ret void
+}
+
+; A test case where we shouldn't generate a punpckldq but a pshufd and a pslldq
+define void @test2(<4 x i32>* %dest, <4 x i32> %in) nounwind {
+entry:
+ %0 = shufflevector <4 x i32> %in, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> < i32 undef, i32 5, i32 undef, i32 2>
+ store <4 x i32> %0, <4 x i32>* %dest
+ ret void
+}
diff --git a/test/CodeGen/X86/vec_shuffle-31.ll b/test/CodeGen/X86/vec_shuffle-31.ll
new file mode 100644
index 0000000..bb06e15
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-31.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 -mcpu=core2 -o %t
+; RUN: grep pshufb %t | count 1
+
+define <8 x i16> @shuf3(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 0, i32 1, i32 undef, i32 undef, i32 3, i32 11, i32 undef , i32 undef >
+ ret <8 x i16> %tmp9
+}
diff --git a/test/CodeGen/X86/vec_shuffle-34.ll b/test/CodeGen/X86/vec_shuffle-34.ll
new file mode 100644
index 0000000..d057b3f
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-34.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=x86 -mcpu=core2 | grep pshufb | count 2
+
+define <8 x i16> @shuf2(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef >
+ ret <8 x i16> %tmp8
+}
diff --git a/test/CodeGen/X86/vec_shuffle-35.ll b/test/CodeGen/X86/vec_shuffle-35.ll
new file mode 100644
index 0000000..7f0fcb5
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-35.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah -stack-alignment=16 -o %t
+; RUN: grep pextrw %t | count 13
+; RUN: grep pinsrw %t | count 14
+; RUN: grep rolw %t | count 13
+; RUN: not grep esp %t
+; RUN: not grep ebp %t
+; RUN: llc < %s -march=x86 -mcpu=core2 -stack-alignment=16 -o %t
+; RUN: grep pshufb %t | count 3
+
+define <16 x i8> @shuf1(<16 x i8> %T0) nounwind readnone {
+entry:
+ %tmp8 = shufflevector <16 x i8> %T0, <16 x i8> undef, <16 x i32> < i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 12, i32 13, i32 15 , i32 14 >
+ ret <16 x i8> %tmp8
+}
+
+define <16 x i8> @shuf2(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
+entry:
+ %tmp8 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> < i32 undef, i32 undef, i32 3, i32 2, i32 17, i32 16, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 12, i32 13, i32 15 , i32 14 >
+ ret <16 x i8> %tmp8
+}
diff --git a/test/CodeGen/X86/vec_shuffle-36.ll b/test/CodeGen/X86/vec_shuffle-36.ll
new file mode 100644
index 0000000..8a93a7ee
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-36.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
+; RUN: grep pshufb %t | count 1
+
+
+define <8 x i16> @shuf6(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 3, i32 2, i32 0, i32 2, i32 1, i32 5, i32 6 , i32 undef >
+ ret <8 x i16> %tmp9
+}
diff --git a/test/CodeGen/X86/vec_shuffle-4.ll b/test/CodeGen/X86/vec_shuffle-4.ll
new file mode 100644
index 0000000..829fedf
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-4.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 > %t
+; RUN: grep shuf %t | count 2
+; RUN: not grep unpck %t
+
+define void @test(<4 x float>* %res, <4 x float>* %A, <4 x float>* %B, <4 x float>* %C) {
+ %tmp3 = load <4 x float>* %B ; <<4 x float>> [#uses=1]
+ %tmp5 = load <4 x float>* %C ; <<4 x float>> [#uses=1]
+ %tmp11 = shufflevector <4 x float> %tmp3, <4 x float> %tmp5, <4 x i32> < i32 1, i32 4, i32 1, i32 5 > ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp11, <4 x float>* %res
+ ret void
+}
+
diff --git a/test/CodeGen/X86/vec_shuffle-5.ll b/test/CodeGen/X86/vec_shuffle-5.ll
new file mode 100644
index 0000000..c24167a
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-5.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
+; RUN: grep movhlps %t | count 1
+; RUN: grep shufps %t | count 1
+
+define void @test() nounwind {
+ %tmp1 = load <4 x float>* null ; <<4 x float>> [#uses=2]
+ %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 >, <4 x i32> < i32 0, i32 1, i32 6, i32 7 > ; <<4 x float>> [#uses=1]
+ %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 2, i32 3, i32 6, i32 7 > ; <<4 x float>> [#uses=1]
+ %tmp4 = fadd <4 x float> %tmp2, %tmp3 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp4, <4 x float>* null
+ ret void
+}
+
diff --git a/test/CodeGen/X86/vec_shuffle-6.ll b/test/CodeGen/X86/vec_shuffle-6.ll
new file mode 100644
index 0000000..f034b0a
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-6.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
+; RUN: grep movapd %t | count 1
+; RUN: grep movaps %t | count 1
+; RUN: grep movups %t | count 2
+
+target triple = "i686-apple-darwin"
+@x = global [4 x i32] [ i32 1, i32 2, i32 3, i32 4 ] ; <[4 x i32]*> [#uses=4]
+
+define <2 x i64> @test1() {
+ %tmp = load i32* getelementptr ([4 x i32]* @x, i32 0, i32 0) ; <i32> [#uses=1]
+ %tmp3 = load i32* getelementptr ([4 x i32]* @x, i32 0, i32 1) ; <i32> [#uses=1]
+ %tmp5 = load i32* getelementptr ([4 x i32]* @x, i32 0, i32 2) ; <i32> [#uses=1]
+ %tmp7 = load i32* getelementptr ([4 x i32]* @x, i32 0, i32 3) ; <i32> [#uses=1]
+ %tmp.upgrd.1 = insertelement <4 x i32> undef, i32 %tmp, i32 0 ; <<4 x i32>> [#uses=1]
+ %tmp13 = insertelement <4 x i32> %tmp.upgrd.1, i32 %tmp3, i32 1 ; <<4 x i32>> [#uses=1]
+ %tmp14 = insertelement <4 x i32> %tmp13, i32 %tmp5, i32 2 ; <<4 x i32>> [#uses=1]
+ %tmp15 = insertelement <4 x i32> %tmp14, i32 %tmp7, i32 3 ; <<4 x i32>> [#uses=1]
+ %tmp16 = bitcast <4 x i32> %tmp15 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp16
+}
+
+define <4 x float> @test2(i32 %dummy, float %a, float %b, float %c, float %d) {
+ %tmp = insertelement <4 x float> undef, float %a, i32 0 ; <<4 x float>> [#uses=1]
+ %tmp11 = insertelement <4 x float> %tmp, float %b, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3 ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp13
+}
+
+define <4 x float> @test3(float %a, float %b, float %c, float %d) {
+ %tmp = insertelement <4 x float> undef, float %a, i32 0 ; <<4 x float>> [#uses=1]
+ %tmp11 = insertelement <4 x float> %tmp, float %b, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3 ; <<4 x float>> [#uses=1]
+ ret <4 x float> %tmp13
+}
+
+define <2 x double> @test4(double %a, double %b) {
+ %tmp = insertelement <2 x double> undef, double %a, i32 0 ; <<2 x double>> [#uses=1]
+ %tmp7 = insertelement <2 x double> %tmp, double %b, i32 1 ; <<2 x double>> [#uses=1]
+ ret <2 x double> %tmp7
+}
diff --git a/test/CodeGen/X86/vec_shuffle-7.ll b/test/CodeGen/X86/vec_shuffle-7.ll
new file mode 100644
index 0000000..4cdca09
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-7.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
+; RUN: grep xorps %t | count 1
+; RUN: not grep shufps %t
+
+define void @test() {
+ bitcast <4 x i32> zeroinitializer to <4 x float> ; <<4 x float>>:1 [#uses=1]
+ shufflevector <4 x float> %1, <4 x float> zeroinitializer, <4 x i32> zeroinitializer ; <<4 x float>>:2 [#uses=1]
+ store <4 x float> %2, <4 x float>* null
+ unreachable
+}
+
diff --git a/test/CodeGen/X86/vec_shuffle-8.ll b/test/CodeGen/X86/vec_shuffle-8.ll
new file mode 100644
index 0000000..964ce7b
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-8.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | \
+; RUN: not grep shufps
+
+define void @test(<4 x float>* %res, <4 x float>* %A) {
+ %tmp1 = load <4 x float>* %A ; <<4 x float>> [#uses=1]
+ %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp2, <4 x float>* %res
+ ret void
+}
+
diff --git a/test/CodeGen/X86/vec_shuffle-9.ll b/test/CodeGen/X86/vec_shuffle-9.ll
new file mode 100644
index 0000000..fc16a26
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle-9.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
+
+define <4 x i32> @test(i8** %ptr) {
+; CHECK: xorps
+; CHECK: punpcklbw
+; CHECK: punpcklwd
+
+ %tmp = load i8** %ptr ; <i8*> [#uses=1]
+ %tmp.upgrd.1 = bitcast i8* %tmp to float* ; <float*> [#uses=1]
+ %tmp.upgrd.2 = load float* %tmp.upgrd.1 ; <float> [#uses=1]
+ %tmp.upgrd.3 = insertelement <4 x float> undef, float %tmp.upgrd.2, i32 0 ; <<4 x float>> [#uses=1]
+ %tmp9 = insertelement <4 x float> %tmp.upgrd.3, float 0.000000e+00, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp10 = insertelement <4 x float> %tmp9, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp11 = insertelement <4 x float> %tmp10, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
+ %tmp21 = bitcast <4 x float> %tmp11 to <16 x i8> ; <<16 x i8>> [#uses=1]
+ %tmp22 = shufflevector <16 x i8> %tmp21, <16 x i8> zeroinitializer, <16 x i32> < i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23 > ; <<16 x i8>> [#uses=1]
+ %tmp31 = bitcast <16 x i8> %tmp22 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp.upgrd.4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %tmp31, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1]
+ %tmp36 = bitcast <8 x i16> %tmp.upgrd.4 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %tmp36
+}
diff --git a/test/CodeGen/X86/vec_shuffle.ll b/test/CodeGen/X86/vec_shuffle.ll
new file mode 100644
index 0000000..c05b79a
--- /dev/null
+++ b/test/CodeGen/X86/vec_shuffle.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -march=x86 -mcpu=core2 -o %t
+; RUN: grep shufp %t | count 1
+; RUN: grep movupd %t | count 1
+; RUN: grep pshufhw %t | count 1
+
+define void @test_v4sf(<4 x float>* %P, float %X, float %Y) nounwind {
+ %tmp = insertelement <4 x float> zeroinitializer, float %X, i32 0 ; <<4 x float>> [#uses=1]
+ %tmp2 = insertelement <4 x float> %tmp, float %X, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp4 = insertelement <4 x float> %tmp2, float %Y, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp6 = insertelement <4 x float> %tmp4, float %Y, i32 3 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp6, <4 x float>* %P
+ ret void
+}
+
+define void @test_v2sd(<2 x double>* %P, double %X, double %Y) nounwind {
+ %tmp = insertelement <2 x double> zeroinitializer, double %X, i32 0 ; <<2 x double>> [#uses=1]
+ %tmp2 = insertelement <2 x double> %tmp, double %Y, i32 1 ; <<2 x double>> [#uses=1]
+ store <2 x double> %tmp2, <2 x double>* %P
+ ret void
+}
+
+define void @test_v8i16(<2 x i64>* %res, <2 x i64>* %A) nounwind {
+ %tmp = load <2 x i64>* %A ; <<2 x i64>> [#uses=1]
+ %tmp.upgrd.1 = bitcast <2 x i64> %tmp to <8 x i16> ; <<8 x i16>> [#uses=8]
+ %tmp.upgrd.2 = extractelement <8 x i16> %tmp.upgrd.1, i32 0 ; <i16> [#uses=1]
+ %tmp1 = extractelement <8 x i16> %tmp.upgrd.1, i32 1 ; <i16> [#uses=1]
+ %tmp2 = extractelement <8 x i16> %tmp.upgrd.1, i32 2 ; <i16> [#uses=1]
+ %tmp3 = extractelement <8 x i16> %tmp.upgrd.1, i32 3 ; <i16> [#uses=1]
+ %tmp4 = extractelement <8 x i16> %tmp.upgrd.1, i32 6 ; <i16> [#uses=1]
+ %tmp5 = extractelement <8 x i16> %tmp.upgrd.1, i32 5 ; <i16> [#uses=1]
+ %tmp6 = extractelement <8 x i16> %tmp.upgrd.1, i32 4 ; <i16> [#uses=1]
+ %tmp7 = extractelement <8 x i16> %tmp.upgrd.1, i32 7 ; <i16> [#uses=1]
+ %tmp8 = insertelement <8 x i16> undef, i16 %tmp.upgrd.2, i32 0 ; <<8 x i16>> [#uses=1]
+ %tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp1, i32 1 ; <<8 x i16>> [#uses=1]
+ %tmp10 = insertelement <8 x i16> %tmp9, i16 %tmp2, i32 2 ; <<8 x i16>> [#uses=1]
+ %tmp11 = insertelement <8 x i16> %tmp10, i16 %tmp3, i32 3 ; <<8 x i16>> [#uses=1]
+ %tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp4, i32 4 ; <<8 x i16>> [#uses=1]
+ %tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 5 ; <<8 x i16>> [#uses=1]
+ %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp6, i32 6 ; <<8 x i16>> [#uses=1]
+ %tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 7 ; <<8 x i16>> [#uses=1]
+ %tmp15.upgrd.3 = bitcast <8 x i16> %tmp15 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ store <2 x i64> %tmp15.upgrd.3, <2 x i64>* %res
+ ret void
+}
diff --git a/test/CodeGen/X86/vec_splat-2.ll b/test/CodeGen/X86/vec_splat-2.ll
new file mode 100644
index 0000000..cde5ae9
--- /dev/null
+++ b/test/CodeGen/X86/vec_splat-2.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pshufd | count 1
+
+define void @test(<2 x i64>* %P, i8 %x) nounwind {
+ %tmp = insertelement <16 x i8> zeroinitializer, i8 %x, i32 0 ; <<16 x i8>> [#uses=1]
+ %tmp36 = insertelement <16 x i8> %tmp, i8 %x, i32 1 ; <<16 x i8>> [#uses=1]
+ %tmp38 = insertelement <16 x i8> %tmp36, i8 %x, i32 2 ; <<16 x i8>> [#uses=1]
+ %tmp40 = insertelement <16 x i8> %tmp38, i8 %x, i32 3 ; <<16 x i8>> [#uses=1]
+ %tmp42 = insertelement <16 x i8> %tmp40, i8 %x, i32 4 ; <<16 x i8>> [#uses=1]
+ %tmp44 = insertelement <16 x i8> %tmp42, i8 %x, i32 5 ; <<16 x i8>> [#uses=1]
+ %tmp46 = insertelement <16 x i8> %tmp44, i8 %x, i32 6 ; <<16 x i8>> [#uses=1]
+ %tmp48 = insertelement <16 x i8> %tmp46, i8 %x, i32 7 ; <<16 x i8>> [#uses=1]
+ %tmp50 = insertelement <16 x i8> %tmp48, i8 %x, i32 8 ; <<16 x i8>> [#uses=1]
+ %tmp52 = insertelement <16 x i8> %tmp50, i8 %x, i32 9 ; <<16 x i8>> [#uses=1]
+ %tmp54 = insertelement <16 x i8> %tmp52, i8 %x, i32 10 ; <<16 x i8>> [#uses=1]
+ %tmp56 = insertelement <16 x i8> %tmp54, i8 %x, i32 11 ; <<16 x i8>> [#uses=1]
+ %tmp58 = insertelement <16 x i8> %tmp56, i8 %x, i32 12 ; <<16 x i8>> [#uses=1]
+ %tmp60 = insertelement <16 x i8> %tmp58, i8 %x, i32 13 ; <<16 x i8>> [#uses=1]
+ %tmp62 = insertelement <16 x i8> %tmp60, i8 %x, i32 14 ; <<16 x i8>> [#uses=1]
+ %tmp64 = insertelement <16 x i8> %tmp62, i8 %x, i32 15 ; <<16 x i8>> [#uses=1]
+ %tmp68 = load <2 x i64>* %P ; <<2 x i64>> [#uses=1]
+ %tmp71 = bitcast <2 x i64> %tmp68 to <16 x i8> ; <<16 x i8>> [#uses=1]
+ %tmp73 = add <16 x i8> %tmp71, %tmp64 ; <<16 x i8>> [#uses=1]
+ %tmp73.upgrd.1 = bitcast <16 x i8> %tmp73 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ store <2 x i64> %tmp73.upgrd.1, <2 x i64>* %P
+ ret void
+}
diff --git a/test/CodeGen/X86/vec_splat-3.ll b/test/CodeGen/X86/vec_splat-3.ll
new file mode 100644
index 0000000..649b85c
--- /dev/null
+++ b/test/CodeGen/X86/vec_splat-3.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
+; RUN: grep punpcklwd %t | count 4
+; RUN: grep punpckhwd %t | count 4
+; RUN: grep "pshufd" %t | count 8
+
+; Splat test for v8i16
+; Should generate with pshufd with masks $0, $85, $170, $255 (each mask is used twice)
+define <8 x i16> @shuf_8i16_0(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 0, i32 undef, i32 undef, i32 0, i32 undef, i32 undef, i32 undef , i32 undef >
+ ret <8 x i16> %tmp6
+}
+
+define <8 x i16> @shuf_8i16_1(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
+ ret <8 x i16> %tmp6
+}
+
+define <8 x i16> @shuf_8i16_2(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 undef , i32 undef >
+ ret <8 x i16> %tmp6
+}
+
+define <8 x i16> @shuf_8i16_3(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 3, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
+ ret <8 x i16> %tmp6
+}
+
+define <8 x i16> @shuf_8i16_4(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 4, i32 undef, i32 undef, i32 undef, i32 4, i32 undef, i32 undef , i32 undef >
+ ret <8 x i16> %tmp6
+}
+
+define <8 x i16> @shuf_8i16_5(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 5, i32 undef, i32 undef, i32 5, i32 undef, i32 undef, i32 undef , i32 undef >
+ ret <8 x i16> %tmp6
+}
+
+define <8 x i16> @shuf_8i16_6(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 6, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
+ ret <8 x i16> %tmp6
+}
+
+
+define <8 x i16> @shuf_8i16_7(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 7, i32 undef, i32 undef, i32 7, i32 undef, i32 undef, i32 undef , i32 undef >
+ ret <8 x i16> %tmp6
+}
diff --git a/test/CodeGen/X86/vec_splat-4.ll b/test/CodeGen/X86/vec_splat-4.ll
new file mode 100644
index 0000000..d9941e6
--- /dev/null
+++ b/test/CodeGen/X86/vec_splat-4.ll
@@ -0,0 +1,104 @@
+; RUN: llc < %s -march=x86 -mattr=sse41 -o %t
+; RUN: grep punpcklbw %t | count 16
+; RUN: grep punpckhbw %t | count 16
+; RUN: grep "pshufd" %t | count 16
+
+; Should generate with pshufd with masks $0, $85, $170, $255 (each mask is used 4 times)
+
+; Splat test for v16i8
+define <16 x i8 > @shuf_16i8_0(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 0, i32 undef, i32 undef, i32 0, i32 undef, i32 0, i32 0 , i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 >
+ ret <16 x i8 > %tmp6
+}
+
+define <16 x i8 > @shuf_16i8_1(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef, i32 undef, i32 undef, i32 undef >
+ ret <16 x i8 > %tmp6
+}
+
+define <16 x i8 > @shuf_16i8_2(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 2 , i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2 >
+ ret <16 x i8 > %tmp6
+}
+
+define <16 x i8 > @shuf_16i8_3(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 3, i32 undef, i32 undef, i32 3, i32 undef, i32 3, i32 3 , i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3 >
+ ret <16 x i8 > %tmp6
+}
+
+
+define <16 x i8 > @shuf_16i8_4(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 4, i32 undef, i32 undef, i32 undef, i32 4, i32 undef, i32 undef , i32 undef, i32 undef, i32 undef, i32 undef , i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
+ ret <16 x i8 > %tmp6
+}
+
+define <16 x i8 > @shuf_16i8_5(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 5, i32 undef, i32 undef, i32 5, i32 undef, i32 5, i32 5 , i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5 >
+ ret <16 x i8 > %tmp6
+}
+
+define <16 x i8 > @shuf_16i8_6(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 6, i32 undef, i32 undef, i32 6, i32 undef, i32 6, i32 6 , i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6 >
+ ret <16 x i8 > %tmp6
+}
+
+define <16 x i8 > @shuf_16i8_7(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 7, i32 undef, i32 undef, i32 7, i32 undef, i32 undef, i32 undef , i32 undef, i32 undef, i32 undef, i32 undef , i32 undef , i32 undef, i32 undef, i32 undef , i32 undef >
+ ret <16 x i8 > %tmp6
+}
+
+define <16 x i8 > @shuf_16i8_8(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 8, i32 undef, i32 undef, i32 8, i32 undef, i32 8, i32 8 , i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8 >
+ ret <16 x i8 > %tmp6
+}
+
+define <16 x i8 > @shuf_16i8_9(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 9, i32 undef, i32 undef, i32 9, i32 undef, i32 9, i32 9 , i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9 >
+ ret <16 x i8 > %tmp6
+}
+
+define <16 x i8 > @shuf_16i8_10(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 10, i32 undef, i32 undef, i32 10, i32 undef, i32 10, i32 10 , i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10 >
+ ret <16 x i8 > %tmp6
+}
+
+define <16 x i8 > @shuf_16i8_11(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 11, i32 undef, i32 undef, i32 11, i32 undef, i32 11, i32 11 , i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11 >
+ ret <16 x i8 > %tmp6
+}
+
+define <16 x i8 > @shuf_16i8_12(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 12, i32 undef, i32 undef, i32 12, i32 undef, i32 12, i32 12 , i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12 >
+ ret <16 x i8 > %tmp6
+}
+
+define <16 x i8 > @shuf_16i8_13(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 13, i32 undef, i32 undef, i32 13, i32 undef, i32 13, i32 13 , i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13 >
+ ret <16 x i8 > %tmp6
+}
+
+define <16 x i8 > @shuf_16i8_14(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 14, i32 undef, i32 undef, i32 14, i32 undef, i32 14, i32 14 , i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14 >
+ ret <16 x i8 > %tmp6
+}
+
+define <16 x i8 > @shuf_16i8_15(<16 x i8 > %T0, <16 x i8 > %T1) nounwind readnone {
+entry:
+ %tmp6 = shufflevector <16 x i8 > %T0, <16 x i8 > %T1, <16 x i32> < i32 15, i32 undef, i32 undef, i32 15, i32 undef, i32 15, i32 15 , i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15 >
+ ret <16 x i8 > %tmp6
+}
diff --git a/test/CodeGen/X86/vec_splat.ll b/test/CodeGen/X86/vec_splat.ll
new file mode 100644
index 0000000..a87fbd0
--- /dev/null
+++ b/test/CodeGen/X86/vec_splat.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep pshufd
+; RUN: llc < %s -march=x86 -mattr=+sse3 | grep movddup
+
+define void @test_v4sf(<4 x float>* %P, <4 x float>* %Q, float %X) nounwind {
+ %tmp = insertelement <4 x float> zeroinitializer, float %X, i32 0 ; <<4 x float>> [#uses=1]
+ %tmp2 = insertelement <4 x float> %tmp, float %X, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp4 = insertelement <4 x float> %tmp2, float %X, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp6 = insertelement <4 x float> %tmp4, float %X, i32 3 ; <<4 x float>> [#uses=1]
+ %tmp8 = load <4 x float>* %Q ; <<4 x float>> [#uses=1]
+ %tmp10 = fmul <4 x float> %tmp8, %tmp6 ; <<4 x float>> [#uses=1]
+ store <4 x float> %tmp10, <4 x float>* %P
+ ret void
+}
+
+define void @test_v2sd(<2 x double>* %P, <2 x double>* %Q, double %X) nounwind {
+ %tmp = insertelement <2 x double> zeroinitializer, double %X, i32 0 ; <<2 x double>> [#uses=1]
+ %tmp2 = insertelement <2 x double> %tmp, double %X, i32 1 ; <<2 x double>> [#uses=1]
+ %tmp4 = load <2 x double>* %Q ; <<2 x double>> [#uses=1]
+ %tmp6 = fmul <2 x double> %tmp4, %tmp2 ; <<2 x double>> [#uses=1]
+ store <2 x double> %tmp6, <2 x double>* %P
+ ret void
+}
diff --git a/test/CodeGen/X86/vec_ss_load_fold.ll b/test/CodeGen/X86/vec_ss_load_fold.ll
new file mode 100644
index 0000000..b1613fb
--- /dev/null
+++ b/test/CodeGen/X86/vec_ss_load_fold.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s -march=x86 -mattr=+sse,+sse2 -o %t
+; RUN: grep minss %t | grep CPI | count 2
+; RUN: grep CPI %t | not grep movss
+
+target datalayout = "e-p:32:32"
+target triple = "i686-apple-darwin8.7.2"
+
+define i16 @test1(float %f) nounwind {
+ %tmp = insertelement <4 x float> undef, float %f, i32 0 ; <<4 x float>> [#uses=1]
+ %tmp10 = insertelement <4 x float> %tmp, float 0.000000e+00, i32 1 ; <<4 x float>> [#uses=1]
+ %tmp11 = insertelement <4 x float> %tmp10, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
+ %tmp12 = insertelement <4 x float> %tmp11, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
+ %tmp28 = tail call <4 x float> @llvm.x86.sse.sub.ss( <4 x float> %tmp12, <4 x float> < float 1.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00 > ) ; <<4 x float>> [#uses=1]
+ %tmp37 = tail call <4 x float> @llvm.x86.sse.mul.ss( <4 x float> %tmp28, <4 x float> < float 5.000000e-01, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00 > ) ; <<4 x float>> [#uses=1]
+ %tmp48 = tail call <4 x float> @llvm.x86.sse.min.ss( <4 x float> %tmp37, <4 x float> < float 6.553500e+04, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00 > ) ; <<4 x float>> [#uses=1]
+ %tmp59 = tail call <4 x float> @llvm.x86.sse.max.ss( <4 x float> %tmp48, <4 x float> zeroinitializer ) ; <<4 x float>> [#uses=1]
+ %tmp.upgrd.1 = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 ) ; <i32> [#uses=1]
+ %tmp69 = trunc i32 %tmp.upgrd.1 to i16 ; <i16> [#uses=1]
+ ret i16 %tmp69
+}
+
+define i16 @test2(float %f) nounwind {
+ %tmp28 = fsub float %f, 1.000000e+00 ; <float> [#uses=1]
+ %tmp37 = fmul float %tmp28, 5.000000e-01 ; <float> [#uses=1]
+ %tmp375 = insertelement <4 x float> undef, float %tmp37, i32 0 ; <<4 x float>> [#uses=1]
+ %tmp48 = tail call <4 x float> @llvm.x86.sse.min.ss( <4 x float> %tmp375, <4 x float> < float 6.553500e+04, float undef, float undef, float undef > ) ; <<4 x float>> [#uses=1]
+ %tmp59 = tail call <4 x float> @llvm.x86.sse.max.ss( <4 x float> %tmp48, <4 x float> < float 0.000000e+00, float undef, float undef, float undef > ) ; <<4 x float>> [#uses=1]
+ %tmp = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 ) ; <i32> [#uses=1]
+ %tmp69 = trunc i32 %tmp to i16 ; <i16> [#uses=1]
+ ret i16 %tmp69
+}
+
+declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>)
+
+declare <4 x float> @llvm.x86.sse.mul.ss(<4 x float>, <4 x float>)
+
+declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>)
+
+declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>)
+
+declare i32 @llvm.x86.sse.cvttss2si(<4 x float>)
diff --git a/test/CodeGen/X86/vec_zero-2.ll b/test/CodeGen/X86/vec_zero-2.ll
new file mode 100644
index 0000000..cdb030e
--- /dev/null
+++ b/test/CodeGen/X86/vec_zero-2.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+
+define i32 @t() {
+entry:
+ br i1 true, label %bb4743, label %bb1656
+bb1656: ; preds = %entry
+ ret i32 0
+bb1664: ; preds = %entry
+ br i1 false, label %bb5310, label %bb4743
+bb4743: ; preds = %bb1664
+ %tmp5256 = bitcast <2 x i64> zeroinitializer to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp5257 = sub <8 x i16> %tmp5256, zeroinitializer ; <<8 x i16>> [#uses=1]
+ %tmp5258 = bitcast <8 x i16> %tmp5257 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp5265 = bitcast <2 x i64> %tmp5258 to <8 x i16> ; <<8 x i16>> [#uses=1]
+ %tmp5266 = call <16 x i8> @llvm.x86.sse2.packuswb.128( <8 x i16> %tmp5265, <8 x i16> zeroinitializer ) nounwind readnone ; <<8 x i16>> [#uses=1]
+ %tmp5267 = bitcast <16 x i8> %tmp5266 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp5294 = and <2 x i64> zeroinitializer, %tmp5267 ; <<2 x i64>> [#uses=1]
+ br label %bb5310
+bb5310: ; preds = %bb4743, %bb1664
+ %tmp5294.pn = phi <2 x i64> [ %tmp5294, %bb4743 ], [ zeroinitializer, %bb1664 ] ; <<2 x i64>> [#uses=0]
+ ret i32 0
+}
+
+declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>) nounwind readnone
diff --git a/test/CodeGen/X86/vec_zero.ll b/test/CodeGen/X86/vec_zero.ll
new file mode 100644
index 0000000..ae5af58
--- /dev/null
+++ b/test/CodeGen/X86/vec_zero.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | grep xorps | count 2
+
+define void @foo(<4 x float>* %P) {
+ %T = load <4 x float>* %P ; <<4 x float>> [#uses=1]
+ %S = fadd <4 x float> zeroinitializer, %T ; <<4 x float>> [#uses=1]
+ store <4 x float> %S, <4 x float>* %P
+ ret void
+}
+
+define void @bar(<4 x i32>* %P) {
+ %T = load <4 x i32>* %P ; <<4 x i32>> [#uses=1]
+ %S = add <4 x i32> zeroinitializer, %T ; <<4 x i32>> [#uses=1]
+ store <4 x i32> %S, <4 x i32>* %P
+ ret void
+}
+
diff --git a/test/CodeGen/X86/vec_zero_cse.ll b/test/CodeGen/X86/vec_zero_cse.ll
new file mode 100644
index 0000000..296378c
--- /dev/null
+++ b/test/CodeGen/X86/vec_zero_cse.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pxor | count 1
+; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep xorps | count 1
+; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pcmpeqd | count 2
+
+@M1 = external global <1 x i64>
+@M2 = external global <2 x i32>
+
+@S1 = external global <2 x i64>
+@S2 = external global <4 x i32>
+
+define void @test() {
+ store <1 x i64> zeroinitializer, <1 x i64>* @M1
+ store <2 x i32> zeroinitializer, <2 x i32>* @M2
+ ret void
+}
+
+define void @test2() {
+ store <1 x i64> < i64 -1 >, <1 x i64>* @M1
+ store <2 x i32> < i32 -1, i32 -1 >, <2 x i32>* @M2
+ ret void
+}
+
+define void @test3() {
+ store <2 x i64> zeroinitializer, <2 x i64>* @S1
+ store <4 x i32> zeroinitializer, <4 x i32>* @S2
+ ret void
+}
+
+define void @test4() {
+ store <2 x i64> < i64 -1, i64 -1>, <2 x i64>* @S1
+ store <4 x i32> < i32 -1, i32 -1, i32 -1, i32 -1 >, <4 x i32>* @S2
+ ret void
+}
+
+
diff --git a/test/CodeGen/X86/vector-intrinsics.ll b/test/CodeGen/X86/vector-intrinsics.ll
new file mode 100644
index 0000000..edf58b9
--- /dev/null
+++ b/test/CodeGen/X86/vector-intrinsics.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=x86-64 | grep call | count 16
+
+declare <4 x double> @llvm.sin.v4f64(<4 x double> %p)
+declare <4 x double> @llvm.cos.v4f64(<4 x double> %p)
+declare <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
+declare <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32)
+
+define <4 x double> @foo(<4 x double> %p)
+{
+ %t = call <4 x double> @llvm.sin.v4f64(<4 x double> %p)
+ ret <4 x double> %t
+}
+define <4 x double> @goo(<4 x double> %p)
+{
+ %t = call <4 x double> @llvm.cos.v4f64(<4 x double> %p)
+ ret <4 x double> %t
+}
+define <4 x double> @moo(<4 x double> %p, <4 x double> %q)
+{
+ %t = call <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
+ ret <4 x double> %t
+}
+define <4 x double> @zoo(<4 x double> %p, i32 %q)
+{
+ %t = call <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32 %q)
+ ret <4 x double> %t
+}
diff --git a/test/CodeGen/X86/vector-rem.ll b/test/CodeGen/X86/vector-rem.ll
new file mode 100644
index 0000000..51cd872
--- /dev/null
+++ b/test/CodeGen/X86/vector-rem.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86-64 | grep div | count 8
+; RUN: llc < %s -march=x86-64 | grep fmodf | count 4
+
+define <4 x i32> @foo(<4 x i32> %t, <4 x i32> %u) {
+ %m = srem <4 x i32> %t, %u
+ ret <4 x i32> %m
+}
+define <4 x i32> @bar(<4 x i32> %t, <4 x i32> %u) {
+ %m = urem <4 x i32> %t, %u
+ ret <4 x i32> %m
+}
+define <4 x float> @qux(<4 x float> %t, <4 x float> %u) {
+ %m = frem <4 x float> %t, %u
+ ret <4 x float> %m
+}
diff --git a/test/CodeGen/X86/vector-variable-idx.ll b/test/CodeGen/X86/vector-variable-idx.ll
new file mode 100644
index 0000000..2a4d18c
--- /dev/null
+++ b/test/CodeGen/X86/vector-variable-idx.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86-64 | grep movss | count 2
+; PR2676
+
+define float @foo(<4 x float> %p, i32 %t) {
+ %z = extractelement <4 x float> %p, i32 %t
+ ret float %z
+}
+define <4 x float> @bar(<4 x float> %p, float %f, i32 %t) {
+ %z = insertelement <4 x float> %p, float %f, i32 %t
+ ret <4 x float> %z
+}
diff --git a/test/CodeGen/X86/vector.ll b/test/CodeGen/X86/vector.ll
new file mode 100644
index 0000000..3fff8497
--- /dev/null
+++ b/test/CodeGen/X86/vector.ll
@@ -0,0 +1,156 @@
+; Test that vectors are scalarized/lowered correctly.
+; RUN: llc < %s -march=x86 -mcpu=i386 > %t
+; RUN: llc < %s -march=x86 -mcpu=yonah > %t
+
+%d8 = type <8 x double>
+%f1 = type <1 x float>
+%f2 = type <2 x float>
+%f4 = type <4 x float>
+%f8 = type <8 x float>
+%i4 = type <4 x i32>
+
+
+;;; TEST HANDLING OF VARIOUS VECTOR SIZES
+
+define void @test_f1(%f1* %P, %f1* %Q, %f1* %S) {
+ %p = load %f1* %P ; <%f1> [#uses=1]
+ %q = load %f1* %Q ; <%f1> [#uses=1]
+ %R = fadd %f1 %p, %q ; <%f1> [#uses=1]
+ store %f1 %R, %f1* %S
+ ret void
+}
+
+define void @test_f2(%f2* %P, %f2* %Q, %f2* %S) {
+ %p = load %f2* %P ; <%f2> [#uses=1]
+ %q = load %f2* %Q ; <%f2> [#uses=1]
+ %R = fadd %f2 %p, %q ; <%f2> [#uses=1]
+ store %f2 %R, %f2* %S
+ ret void
+}
+
+define void @test_f4(%f4* %P, %f4* %Q, %f4* %S) {
+ %p = load %f4* %P ; <%f4> [#uses=1]
+ %q = load %f4* %Q ; <%f4> [#uses=1]
+ %R = fadd %f4 %p, %q ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_f8(%f8* %P, %f8* %Q, %f8* %S) {
+ %p = load %f8* %P ; <%f8> [#uses=1]
+ %q = load %f8* %Q ; <%f8> [#uses=1]
+ %R = fadd %f8 %p, %q ; <%f8> [#uses=1]
+ store %f8 %R, %f8* %S
+ ret void
+}
+
+define void @test_fmul(%f8* %P, %f8* %Q, %f8* %S) {
+ %p = load %f8* %P ; <%f8> [#uses=1]
+ %q = load %f8* %Q ; <%f8> [#uses=1]
+ %R = fmul %f8 %p, %q ; <%f8> [#uses=1]
+ store %f8 %R, %f8* %S
+ ret void
+}
+
+define void @test_div(%f8* %P, %f8* %Q, %f8* %S) {
+ %p = load %f8* %P ; <%f8> [#uses=1]
+ %q = load %f8* %Q ; <%f8> [#uses=1]
+ %R = fdiv %f8 %p, %q ; <%f8> [#uses=1]
+ store %f8 %R, %f8* %S
+ ret void
+}
+
+;;; TEST VECTOR CONSTRUCTS
+
+define void @test_cst(%f4* %P, %f4* %S) {
+ %p = load %f4* %P ; <%f4> [#uses=1]
+ %R = fadd %f4 %p, < float 0x3FB99999A0000000, float 1.000000e+00, float 2.000000e+00, float 4.500000e+00 > ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_zero(%f4* %P, %f4* %S) {
+ %p = load %f4* %P ; <%f4> [#uses=1]
+ %R = fadd %f4 %p, zeroinitializer ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_undef(%f4* %P, %f4* %S) {
+ %p = load %f4* %P ; <%f4> [#uses=1]
+ %R = fadd %f4 %p, undef ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_constant_insert(%f4* %S) {
+ %R = insertelement %f4 zeroinitializer, float 1.000000e+01, i32 0 ; <%f4> [#uses
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_variable_buildvector(float %F, %f4* %S) {
+ %R = insertelement %f4 zeroinitializer, float %F, i32 0 ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define void @test_scalar_to_vector(float %F, %f4* %S) {
+ %R = insertelement %f4 undef, float %F, i32 0 ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %S
+ ret void
+}
+
+define float @test_extract_elt(%f8* %P) {
+ %p = load %f8* %P ; <%f8> [#uses=1]
+ %R = extractelement %f8 %p, i32 3 ; <float> [#uses=1]
+ ret float %R
+}
+
+define double @test_extract_elt2(%d8* %P) {
+ %p = load %d8* %P ; <%d8> [#uses=1]
+ %R = extractelement %d8 %p, i32 3 ; <double> [#uses=1]
+ ret double %R
+}
+
+define void @test_cast_1(%f4* %b, %i4* %a) {
+ %tmp = load %f4* %b ; <%f4> [#uses=1]
+ %tmp2 = fadd %f4 %tmp, < float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00 > ; <%f4> [#uses=1]
+ %tmp3 = bitcast %f4 %tmp2 to %i4 ; <%i4> [#uses=1]
+ %tmp4 = add %i4 %tmp3, < i32 1, i32 2, i32 3, i32 4 > ; <%i4> [#uses=1]
+ store %i4 %tmp4, %i4* %a
+ ret void
+}
+
+define void @test_cast_2(%f8* %a, <8 x i32>* %b) {
+ %T = load %f8* %a ; <%f8> [#uses=1]
+ %T2 = bitcast %f8 %T to <8 x i32> ; <<8 x i32>> [#uses=1]
+ store <8 x i32> %T2, <8 x i32>* %b
+ ret void
+}
+
+
+;;; TEST IMPORTANT IDIOMS
+
+define void @splat(%f4* %P, %f4* %Q, float %X) {
+ %tmp = insertelement %f4 undef, float %X, i32 0 ; <%f4> [#uses=1]
+ %tmp2 = insertelement %f4 %tmp, float %X, i32 1 ; <%f4> [#uses=1]
+ %tmp4 = insertelement %f4 %tmp2, float %X, i32 2 ; <%f4> [#uses=1]
+ %tmp6 = insertelement %f4 %tmp4, float %X, i32 3 ; <%f4> [#uses=1]
+ %q = load %f4* %Q ; <%f4> [#uses=1]
+ %R = fadd %f4 %q, %tmp6 ; <%f4> [#uses=1]
+ store %f4 %R, %f4* %P
+ ret void
+}
+
+define void @splat_i4(%i4* %P, %i4* %Q, i32 %X) {
+ %tmp = insertelement %i4 undef, i32 %X, i32 0 ; <%i4> [#uses=1]
+ %tmp2 = insertelement %i4 %tmp, i32 %X, i32 1 ; <%i4> [#uses=1]
+ %tmp4 = insertelement %i4 %tmp2, i32 %X, i32 2 ; <%i4> [#uses=1]
+ %tmp6 = insertelement %i4 %tmp4, i32 %X, i32 3 ; <%i4> [#uses=1]
+ %q = load %i4* %Q ; <%i4> [#uses=1]
+ %R = add %i4 %q, %tmp6 ; <%i4> [#uses=1]
+ store %i4 %R, %i4* %P
+ ret void
+}
+
diff --git a/test/CodeGen/X86/vfcmp.ll b/test/CodeGen/X86/vfcmp.ll
new file mode 100644
index 0000000..f5f5293
--- /dev/null
+++ b/test/CodeGen/X86/vfcmp.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+; PR2620
+
+
+define void @t2(i32 %m_task_id, i32 %start_x, i32 %end_x) nounwind {
+ %A = fcmp olt <2 x double> zeroinitializer, zeroinitializer ; <<2 x i64>>:1 [#uses=1]
+ sext <2 x i1> %A to <2 x i64>
+ extractelement <2 x i64> %1, i32 1 ; <i64>:2 [#uses=1]
+ lshr i64 %2, 63 ; <i64>:3 [#uses=1]
+ trunc i64 %3 to i1 ; <i1>:4 [#uses=1]
+ zext i1 %4 to i8 ; <i8>:5 [#uses=1]
+ insertelement <2 x i8> zeroinitializer, i8 %5, i32 1 ; <<2 x i8>>:6 [#uses=1]
+ store <2 x i8> %6, <2 x i8>* null
+ ret void
+}
diff --git a/test/CodeGen/X86/volatile.ll b/test/CodeGen/X86/volatile.ll
new file mode 100644
index 0000000..5e1e0c8
--- /dev/null
+++ b/test/CodeGen/X86/volatile.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 -mattr=sse2 | grep movsd | count 5
+; RUN: llc < %s -march=x86 -mattr=sse2 -O0 | grep movsd | count 5
+
+@x = external global double
+
+define void @foo() nounwind {
+ %a = volatile load double* @x
+ volatile store double 0.0, double* @x
+ volatile store double 0.0, double* @x
+ %b = volatile load double* @x
+ ret void
+}
+
+define void @bar() nounwind {
+ %c = volatile load double* @x
+ ret void
+}
diff --git a/test/CodeGen/X86/vortex-bug.ll b/test/CodeGen/X86/vortex-bug.ll
new file mode 100644
index 0000000..40f1117
--- /dev/null
+++ b/test/CodeGen/X86/vortex-bug.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=x86-64
+
+ %struct.blktkntype = type { i32, i32 }
+ %struct.fieldstruc = type { [128 x i8], %struct.blktkntype*, i32, i32 }
+
+define fastcc i32 @Env_GetFieldStruc(i8* %FieldName, i32* %Status, %struct.fieldstruc* %FieldStruc) nounwind {
+entry:
+ br label %bb137.i
+
+bb137.i: ; preds = %bb137.i, %entry
+ %FieldName_addr.0209.rec.i = phi i64 [ %tmp139.rec.i, %bb137.i ], [ 0, %entry ] ; <i64> [#uses=1]
+ %tmp147213.i = phi i32 [ %tmp147.i, %bb137.i ], [ 1, %entry ] ; <i32> [#uses=2]
+ %tmp139.rec.i = add i64 %FieldName_addr.0209.rec.i, 1 ; <i64> [#uses=2]
+ %tmp141142.i = sext i32 %tmp147213.i to i64 ; <i64> [#uses=0]
+ %tmp147.i = add i32 %tmp147213.i, 1 ; <i32> [#uses=1]
+ br i1 false, label %bb137.i, label %bb149.i.loopexit
+
+bb149.i.loopexit: ; preds = %bb137.i
+ %tmp139.i = getelementptr i8* %FieldName, i64 %tmp139.rec.i ; <i8*> [#uses=0]
+ unreachable
+}
diff --git a/test/CodeGen/X86/vshift-1.ll b/test/CodeGen/X86/vshift-1.ll
new file mode 100644
index 0000000..ae845e0
--- /dev/null
+++ b/test/CodeGen/X86/vshift-1.ll
@@ -0,0 +1,79 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
+
+; test vector shifts converted to proper SSE2 vector shifts when the shift
+; amounts are the same.
+
+define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
+entry:
+; CHECK: shift1a:
+; CHECK: psllq
+ %shl = shl <2 x i64> %val, < i64 32, i64 32 >
+ store <2 x i64> %shl, <2 x i64>* %dst
+ ret void
+}
+
+define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
+entry:
+; CHECK: shift1b:
+; CHECK: movd
+; CHECK-NEXT: psllq
+ %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
+ %1 = insertelement <2 x i64> %0, i64 %amt, i32 1
+ %shl = shl <2 x i64> %val, %1
+ store <2 x i64> %shl, <2 x i64>* %dst
+ ret void
+}
+
+
+define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
+entry:
+; CHECK: shift2a:
+; CHECK: pslld
+ %shl = shl <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
+ store <4 x i32> %shl, <4 x i32>* %dst
+ ret void
+}
+
+define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+entry:
+; CHECK: shift2b:
+; CHECK: movd
+; CHECK-NEXT: pslld
+ %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
+ %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
+ %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
+ %3 = insertelement <4 x i32> %2, i32 %amt, i32 3
+ %shl = shl <4 x i32> %val, %3
+ store <4 x i32> %shl, <4 x i32>* %dst
+ ret void
+}
+
+define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
+entry:
+; CHECK: shift3a:
+; CHECK: psllw
+ %shl = shl <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
+ store <8 x i16> %shl, <8 x i16>* %dst
+ ret void
+}
+
+; Make sure the shift amount is properly zero extended.
+define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
+entry:
+; CHECK: shift3b:
+; CHECK: movzwl
+; CHECK: movd
+; CHECK-NEXT: psllw
+ %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
+ %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
+ %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
+ %3 = insertelement <8 x i16> %0, i16 %amt, i32 3
+ %4 = insertelement <8 x i16> %0, i16 %amt, i32 4
+ %5 = insertelement <8 x i16> %0, i16 %amt, i32 5
+ %6 = insertelement <8 x i16> %0, i16 %amt, i32 6
+ %7 = insertelement <8 x i16> %0, i16 %amt, i32 7
+ %shl = shl <8 x i16> %val, %7
+ store <8 x i16> %shl, <8 x i16>* %dst
+ ret void
+}
+
diff --git a/test/CodeGen/X86/vshift-2.ll b/test/CodeGen/X86/vshift-2.ll
new file mode 100644
index 0000000..36feb11
--- /dev/null
+++ b/test/CodeGen/X86/vshift-2.ll
@@ -0,0 +1,78 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
+
+; test vector shifts converted to proper SSE2 vector shifts when the shift
+; amounts are the same.
+
+define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
+entry:
+; CHECK: shift1a:
+; CHECK: psrlq
+ %lshr = lshr <2 x i64> %val, < i64 32, i64 32 >
+ store <2 x i64> %lshr, <2 x i64>* %dst
+ ret void
+}
+
+define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
+entry:
+; CHECK: shift1b:
+; CHECK: movd
+; CHECK-NEXT: psrlq
+ %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
+ %1 = insertelement <2 x i64> %0, i64 %amt, i32 1
+ %lshr = lshr <2 x i64> %val, %1
+ store <2 x i64> %lshr, <2 x i64>* %dst
+ ret void
+}
+
+define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
+entry:
+; CHECK: shift2a:
+; CHECK: psrld
+ %lshr = lshr <4 x i32> %val, < i32 17, i32 17, i32 17, i32 17 >
+ store <4 x i32> %lshr, <4 x i32>* %dst
+ ret void
+}
+
+define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+entry:
+; CHECK: shift2b:
+; CHECK: movd
+; CHECK-NEXT: psrld
+ %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
+ %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
+ %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
+ %3 = insertelement <4 x i32> %2, i32 %amt, i32 3
+ %lshr = lshr <4 x i32> %val, %3
+ store <4 x i32> %lshr, <4 x i32>* %dst
+ ret void
+}
+
+
+define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
+entry:
+; CHECK: shift3a:
+; CHECK: psrlw
+ %lshr = lshr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
+ store <8 x i16> %lshr, <8 x i16>* %dst
+ ret void
+}
+
+; properly zero extend the shift amount
+define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
+entry:
+; CHECK: shift3b:
+; CHECK: movzwl
+; CHECK: movd
+; CHECK-NEXT: psrlw
+ %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
+ %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
+ %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
+ %3 = insertelement <8 x i16> %0, i16 %amt, i32 3
+ %4 = insertelement <8 x i16> %0, i16 %amt, i32 4
+ %5 = insertelement <8 x i16> %0, i16 %amt, i32 5
+ %6 = insertelement <8 x i16> %0, i16 %amt, i32 6
+ %7 = insertelement <8 x i16> %0, i16 %amt, i32 7
+ %lshr = lshr <8 x i16> %val, %7
+ store <8 x i16> %lshr, <8 x i16>* %dst
+ ret void
+}
diff --git a/test/CodeGen/X86/vshift-3.ll b/test/CodeGen/X86/vshift-3.ll
new file mode 100644
index 0000000..20d3f48
--- /dev/null
+++ b/test/CodeGen/X86/vshift-3.ll
@@ -0,0 +1,67 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
+
+; test vector shifts converted to proper SSE2 vector shifts when the shift
+; amounts are the same.
+
+; Note that x86 does have ashr
+
+; shift1a can't use a packed shift
+define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
+entry:
+; CHECK: shift1a:
+; CHECK: sarl
+ %ashr = ashr <2 x i64> %val, < i64 32, i64 32 >
+ store <2 x i64> %ashr, <2 x i64>* %dst
+ ret void
+}
+
+define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
+entry:
+; CHECK: shift2a:
+; CHECK: psrad $5
+ %ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
+ store <4 x i32> %ashr, <4 x i32>* %dst
+ ret void
+}
+
+define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+entry:
+; CHECK: shift2b:
+; CHECK: movd
+; CHECK-NEXT: psrad
+ %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
+ %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
+ %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
+ %3 = insertelement <4 x i32> %2, i32 %amt, i32 3
+ %ashr = ashr <4 x i32> %val, %3
+ store <4 x i32> %ashr, <4 x i32>* %dst
+ ret void
+}
+
+define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
+entry:
+; CHECK: shift3a:
+; CHECK: psraw $5
+ %ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
+ store <8 x i16> %ashr, <8 x i16>* %dst
+ ret void
+}
+
+define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
+entry:
+; CHECK: shift3b:
+; CHECK: movzwl
+; CHECK: movd
+; CHECK-NEXT: psraw
+ %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
+ %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
+ %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
+ %3 = insertelement <8 x i16> %0, i16 %amt, i32 3
+ %4 = insertelement <8 x i16> %0, i16 %amt, i32 4
+ %5 = insertelement <8 x i16> %0, i16 %amt, i32 5
+ %6 = insertelement <8 x i16> %0, i16 %amt, i32 6
+ %7 = insertelement <8 x i16> %0, i16 %amt, i32 7
+ %ashr = ashr <8 x i16> %val, %7
+ store <8 x i16> %ashr, <8 x i16>* %dst
+ ret void
+}
diff --git a/test/CodeGen/X86/vshift-4.ll b/test/CodeGen/X86/vshift-4.ll
new file mode 100644
index 0000000..9773cbe
--- /dev/null
+++ b/test/CodeGen/X86/vshift-4.ll
@@ -0,0 +1,85 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
+
+; test vector shifts converted to proper SSE2 vector shifts when the shift
+; amounts are the same when using a shuffle splat.
+
+define void @shift1a(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
+entry:
+; CHECK: shift1a:
+; CHECK: psllq
+ %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+ %shl = shl <2 x i64> %val, %shamt
+ store <2 x i64> %shl, <2 x i64>* %dst
+ ret void
+}
+
+; shift1b can't use a packed shift
+define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
+entry:
+; CHECK: shift1b:
+; CHECK: shll
+ %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
+ %shl = shl <2 x i64> %val, %shamt
+ store <2 x i64> %shl, <2 x i64>* %dst
+ ret void
+}
+
+define void @shift2a(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
+entry:
+; CHECK: shift2a:
+; CHECK: pslld
+ %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %shl = shl <4 x i32> %val, %shamt
+ store <4 x i32> %shl, <4 x i32>* %dst
+ ret void
+}
+
+define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
+entry:
+; CHECK: shift2b:
+; CHECK: pslld
+ %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
+ %shl = shl <4 x i32> %val, %shamt
+ store <4 x i32> %shl, <4 x i32>* %dst
+ ret void
+}
+
+define void @shift2c(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
+entry:
+; CHECK: shift2c:
+; CHECK: pslld
+ %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %shl = shl <4 x i32> %val, %shamt
+ store <4 x i32> %shl, <4 x i32>* %dst
+ ret void
+}
+
+define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
+entry:
+; CHECK: shift3a:
+; CHECK: movzwl
+; CHECK: psllw
+ %shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
+ %shl = shl <8 x i16> %val, %shamt
+ store <8 x i16> %shl, <8 x i16>* %dst
+ ret void
+}
+
+define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
+entry:
+; CHECK: shift3b:
+; CHECK: movzwl
+; CHECK: psllw
+ %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
+ %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
+ %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
+ %3 = insertelement <8 x i16> %0, i16 %amt, i32 3
+ %4 = insertelement <8 x i16> %0, i16 %amt, i32 4
+ %5 = insertelement <8 x i16> %0, i16 %amt, i32 5
+ %6 = insertelement <8 x i16> %0, i16 %amt, i32 6
+ %7 = insertelement <8 x i16> %0, i16 %amt, i32 7
+ %shl = shl <8 x i16> %val, %7
+ store <8 x i16> %shl, <8 x i16>* %dst
+ ret void
+}
+
diff --git a/test/CodeGen/X86/vshift-5.ll b/test/CodeGen/X86/vshift-5.ll
new file mode 100644
index 0000000..a543f38
--- /dev/null
+++ b/test/CodeGen/X86/vshift-5.ll
@@ -0,0 +1,56 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s
+
+; When loading the shift amount from memory, avoid generating the splat.
+
+define void @shift5a(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
+entry:
+; CHECK: shift5a:
+; CHECK: movd
+; CHECK-NEXT: pslld
+ %amt = load i32* %pamt
+ %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
+ %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
+ %shl = shl <4 x i32> %val, %shamt
+ store <4 x i32> %shl, <4 x i32>* %dst
+ ret void
+}
+
+
+define void @shift5b(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
+entry:
+; CHECK: shift5b:
+; CHECK: movd
+; CHECK-NEXT: psrad
+ %amt = load i32* %pamt
+ %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
+ %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
+ %shr = ashr <4 x i32> %val, %shamt
+ store <4 x i32> %shr, <4 x i32>* %dst
+ ret void
+}
+
+
+define void @shift5c(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+entry:
+; CHECK: shift5c:
+; CHECK: movd
+; CHECK-NEXT: pslld
+ %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
+ %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
+ %shl = shl <4 x i32> %val, %shamt
+ store <4 x i32> %shl, <4 x i32>* %dst
+ ret void
+}
+
+
+define void @shift5d(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+entry:
+; CHECK: shift5d:
+; CHECK: movd
+; CHECK-NEXT: psrad
+ %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
+ %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
+ %shr = ashr <4 x i32> %val, %shamt
+ store <4 x i32> %shr, <4 x i32>* %dst
+ ret void
+}
diff --git a/test/CodeGen/X86/vshift_scalar.ll b/test/CodeGen/X86/vshift_scalar.ll
new file mode 100644
index 0000000..9dd8478
--- /dev/null
+++ b/test/CodeGen/X86/vshift_scalar.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s
+
+; Legalization test that requires scalarizing a vector.
+
+define void @update(<1 x i32> %val, <1 x i32>* %dst) nounwind {
+entry:
+ %shl = shl <1 x i32> %val, < i32 2>
+ %shr = ashr <1 x i32> %val, < i32 4>
+ store <1 x i32> %shr, <1 x i32>* %dst
+ ret void
+}
diff --git a/test/CodeGen/X86/vshift_split.ll b/test/CodeGen/X86/vshift_split.ll
new file mode 100644
index 0000000..359d36d
--- /dev/null
+++ b/test/CodeGen/X86/vshift_split.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2
+
+; Example that requires splitting and expanding a vector shift.
+define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
+entry:
+ %shr = lshr <2 x i64> %val, < i64 2, i64 3 >
+ ret <2 x i64> %shr
+}
diff --git a/test/CodeGen/X86/vshift_split2.ll b/test/CodeGen/X86/vshift_split2.ll
new file mode 100644
index 0000000..0f8c2b8
--- /dev/null
+++ b/test/CodeGen/X86/vshift_split2.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mcpu=yonah
+
+; Legalization example that requires splitting a large vector into smaller pieces.
+
+define void @update(<8 x i32> %val, <8 x i32>* %dst) nounwind {
+entry:
+ %shl = shl <8 x i32> %val, < i32 2, i32 2, i32 2, i32 2, i32 4, i32 4, i32 4, i32 4 >
+ %shr = ashr <8 x i32> %val, < i32 2, i32 2, i32 2, i32 2, i32 4, i32 4, i32 4, i32 4 >
+ store <8 x i32> %shr, <8 x i32>* %dst
+ ret void
+}
diff --git a/test/CodeGen/X86/vsplit-and.ll b/test/CodeGen/X86/vsplit-and.ll
new file mode 100644
index 0000000..a247c6e
--- /dev/null
+++ b/test/CodeGen/X86/vsplit-and.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=x86 -disable-mmx | FileCheck %s
+
+
+define void @t(<2 x i64>* %dst, <2 x i64> %src1, <2 x i64> %src2) nounwind readonly {
+; CHECK: andb
+ %cmp1 = icmp ne <2 x i64> %src1, zeroinitializer
+ %cmp2 = icmp ne <2 x i64> %src2, zeroinitializer
+ %t1 = and <2 x i1> %cmp1, %cmp2
+ %t2 = sext <2 x i1> %t1 to <2 x i64>
+ store <2 x i64> %t2, <2 x i64>* %dst
+ ret void
+}
+
+define void @t2(<3 x i64>* %dst, <3 x i64> %src1, <3 x i64> %src2) nounwind readonly {
+; CHECK: andb
+ %cmp1 = icmp ne <3 x i64> %src1, zeroinitializer
+ %cmp2 = icmp ne <3 x i64> %src2, zeroinitializer
+ %t1 = and <3 x i1> %cmp1, %cmp2
+ %t2 = sext <3 x i1> %t1 to <3 x i64>
+ store <3 x i64> %t2, <3 x i64>* %dst
+ ret void
+}
diff --git a/test/CodeGen/X86/weak.ll b/test/CodeGen/X86/weak.ll
new file mode 100644
index 0000000..8590e8d
--- /dev/null
+++ b/test/CodeGen/X86/weak.ll
@@ -0,0 +1,4 @@
+; RUN: llc < %s -march=x86
+@a = extern_weak global i32 ; <i32*> [#uses=1]
+@b = global i32* @a ; <i32**> [#uses=0]
+
diff --git a/test/CodeGen/X86/wide-integer-fold.ll b/test/CodeGen/X86/wide-integer-fold.ll
new file mode 100644
index 0000000..b3b4d24
--- /dev/null
+++ b/test/CodeGen/X86/wide-integer-fold.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+; CHECK: movq $-65535, %rax
+
+; DAGCombiner should fold this to a simple constant.
+
+define i64 @foo(i192 %a) nounwind {
+ %t = or i192 %a, -22300404916163702203072254898040925442801665
+ %s = and i192 %t, -22300404916163702203072254898040929737768960
+ %u = lshr i192 %s, 128
+ %v = trunc i192 %u to i64
+ ret i64 %v
+}
diff --git a/test/CodeGen/X86/widen_arith-1.ll b/test/CodeGen/X86/widen_arith-1.ll
new file mode 100644
index 0000000..f8d0690
--- /dev/null
+++ b/test/CodeGen/X86/widen_arith-1.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+
+; Widen a v3i8 to v16i8 to use a vector add
+
+define void @update(<3 x i8>* %dst, <3 x i8>* %src, i32 %n) nounwind {
+entry:
+; CHECK-NOT: pextrw
+; CHECK: paddb
+; CHECK: pextrb
+ %dst.addr = alloca <3 x i8>* ; <<3 x i8>**> [#uses=2]
+ %src.addr = alloca <3 x i8>* ; <<3 x i8>**> [#uses=2]
+ %n.addr = alloca i32 ; <i32*> [#uses=2]
+ %i = alloca i32, align 4 ; <i32*> [#uses=6]
+ store <3 x i8>* %dst, <3 x i8>** %dst.addr
+ store <3 x i8>* %src, <3 x i8>** %src.addr
+ store i32 %n, i32* %n.addr
+ store i32 0, i32* %i
+ br label %forcond
+
+forcond: ; preds = %forinc, %entry
+ %tmp = load i32* %i ; <i32> [#uses=1]
+ %tmp1 = load i32* %n.addr ; <i32> [#uses=1]
+ %cmp = icmp slt i32 %tmp, %tmp1 ; <i1> [#uses=1]
+ br i1 %cmp, label %forbody, label %afterfor
+
+forbody: ; preds = %forcond
+ %tmp2 = load i32* %i ; <i32> [#uses=1]
+ %tmp3 = load <3 x i8>** %dst.addr ; <<3 x i8>*> [#uses=1]
+ %arrayidx = getelementptr <3 x i8>* %tmp3, i32 %tmp2 ; <<3 x i8>*> [#uses=1]
+ %tmp4 = load i32* %i ; <i32> [#uses=1]
+ %tmp5 = load <3 x i8>** %src.addr ; <<3 x i8>*> [#uses=1]
+ %arrayidx6 = getelementptr <3 x i8>* %tmp5, i32 %tmp4 ; <<3 x i8>*> [#uses=1]
+ %tmp7 = load <3 x i8>* %arrayidx6 ; <<3 x i8>> [#uses=1]
+ %add = add <3 x i8> %tmp7, < i8 1, i8 1, i8 1 > ; <<3 x i8>> [#uses=1]
+ store <3 x i8> %add, <3 x i8>* %arrayidx
+ br label %forinc
+
+forinc: ; preds = %forbody
+ %tmp8 = load i32* %i ; <i32> [#uses=1]
+ %inc = add i32 %tmp8, 1 ; <i32> [#uses=1]
+ store i32 %inc, i32* %i
+ br label %forcond
+
+afterfor: ; preds = %forcond
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_arith-2.ll b/test/CodeGen/X86/widen_arith-2.ll
new file mode 100644
index 0000000..fdecaa3
--- /dev/null
+++ b/test/CodeGen/X86/widen_arith-2.ll
@@ -0,0 +1,59 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: paddb
+; CHECK: pand
+
+; widen v8i8 to v16i8 (checks even power of 2 widening with add & and)
+
+define void @update(i64* %dst_i, i64* %src_i, i32 %n) nounwind {
+entry:
+ %dst_i.addr = alloca i64* ; <i64**> [#uses=2]
+ %src_i.addr = alloca i64* ; <i64**> [#uses=2]
+ %n.addr = alloca i32 ; <i32*> [#uses=2]
+ %i = alloca i32, align 4 ; <i32*> [#uses=8]
+ %dst = alloca <8 x i8>*, align 4 ; <<8 x i8>**> [#uses=2]
+ %src = alloca <8 x i8>*, align 4 ; <<8 x i8>**> [#uses=2]
+ store i64* %dst_i, i64** %dst_i.addr
+ store i64* %src_i, i64** %src_i.addr
+ store i32 %n, i32* %n.addr
+ store i32 0, i32* %i
+ br label %forcond
+
+forcond: ; preds = %forinc, %entry
+ %tmp = load i32* %i ; <i32> [#uses=1]
+ %tmp1 = load i32* %n.addr ; <i32> [#uses=1]
+ %cmp = icmp slt i32 %tmp, %tmp1 ; <i1> [#uses=1]
+ br i1 %cmp, label %forbody, label %afterfor
+
+forbody: ; preds = %forcond
+ %tmp2 = load i32* %i ; <i32> [#uses=1]
+ %tmp3 = load i64** %dst_i.addr ; <i64*> [#uses=1]
+ %arrayidx = getelementptr i64* %tmp3, i32 %tmp2 ; <i64*> [#uses=1]
+ %conv = bitcast i64* %arrayidx to <8 x i8>* ; <<8 x i8>*> [#uses=1]
+ store <8 x i8>* %conv, <8 x i8>** %dst
+ %tmp4 = load i32* %i ; <i32> [#uses=1]
+ %tmp5 = load i64** %src_i.addr ; <i64*> [#uses=1]
+ %arrayidx6 = getelementptr i64* %tmp5, i32 %tmp4 ; <i64*> [#uses=1]
+ %conv7 = bitcast i64* %arrayidx6 to <8 x i8>* ; <<8 x i8>*> [#uses=1]
+ store <8 x i8>* %conv7, <8 x i8>** %src
+ %tmp8 = load i32* %i ; <i32> [#uses=1]
+ %tmp9 = load <8 x i8>** %dst ; <<8 x i8>*> [#uses=1]
+ %arrayidx10 = getelementptr <8 x i8>* %tmp9, i32 %tmp8 ; <<8 x i8>*> [#uses=1]
+ %tmp11 = load i32* %i ; <i32> [#uses=1]
+ %tmp12 = load <8 x i8>** %src ; <<8 x i8>*> [#uses=1]
+ %arrayidx13 = getelementptr <8 x i8>* %tmp12, i32 %tmp11 ; <<8 x i8>*> [#uses=1]
+ %tmp14 = load <8 x i8>* %arrayidx13 ; <<8 x i8>> [#uses=1]
+ %add = add <8 x i8> %tmp14, < i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1 > ; <<8 x i8>> [#uses=1]
+ %and = and <8 x i8> %add, < i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4 > ; <<8 x i8>> [#uses=1]
+ store <8 x i8> %and, <8 x i8>* %arrayidx10
+ br label %forinc
+
+forinc: ; preds = %forbody
+ %tmp15 = load i32* %i ; <i32> [#uses=1]
+ %inc = add i32 %tmp15, 1 ; <i32> [#uses=1]
+ store i32 %inc, i32* %i
+ br label %forcond
+
+afterfor: ; preds = %forcond
+ ret void
+}
+
diff --git a/test/CodeGen/X86/widen_arith-3.ll b/test/CodeGen/X86/widen_arith-3.ll
new file mode 100644
index 0000000..1f2c250
--- /dev/null
+++ b/test/CodeGen/X86/widen_arith-3.ll
@@ -0,0 +1,52 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -post-RA-scheduler=true | FileCheck %s
+; CHECK: paddw
+; CHECK: pextrw
+; CHECK: movd
+
+; Widen a v3i16 to v8i16 to do a vector add
+
[email protected] = internal constant [4 x i8] c"%d \00" ; <[4 x i8]*> [#uses=1]
[email protected] = internal constant [2 x i8] c"\0A\00" ; <[2 x i8]*> [#uses=1]
+
+define void @update(<3 x i16>* %dst, <3 x i16>* %src, i32 %n) nounwind {
+entry:
+ %dst.addr = alloca <3 x i16>* ; <<3 x i16>**> [#uses=2]
+ %src.addr = alloca <3 x i16>* ; <<3 x i16>**> [#uses=2]
+ %n.addr = alloca i32 ; <i32*> [#uses=2]
+ %v = alloca <3 x i16>, align 8 ; <<3 x i16>*> [#uses=1]
+ %i = alloca i32, align 4 ; <i32*> [#uses=6]
+ store <3 x i16>* %dst, <3 x i16>** %dst.addr
+ store <3 x i16>* %src, <3 x i16>** %src.addr
+ store i32 %n, i32* %n.addr
+ store <3 x i16> < i16 1, i16 1, i16 1 >, <3 x i16>* %v
+ store i32 0, i32* %i
+ br label %forcond
+
+forcond: ; preds = %forinc, %entry
+ %tmp = load i32* %i ; <i32> [#uses=1]
+ %tmp1 = load i32* %n.addr ; <i32> [#uses=1]
+ %cmp = icmp slt i32 %tmp, %tmp1 ; <i1> [#uses=1]
+ br i1 %cmp, label %forbody, label %afterfor
+
+forbody: ; preds = %forcond
+ %tmp2 = load i32* %i ; <i32> [#uses=1]
+ %tmp3 = load <3 x i16>** %dst.addr ; <<3 x i16>*> [#uses=1]
+ %arrayidx = getelementptr <3 x i16>* %tmp3, i32 %tmp2 ; <<3 x i16>*> [#uses=1]
+ %tmp4 = load i32* %i ; <i32> [#uses=1]
+ %tmp5 = load <3 x i16>** %src.addr ; <<3 x i16>*> [#uses=1]
+ %arrayidx6 = getelementptr <3 x i16>* %tmp5, i32 %tmp4 ; <<3 x i16>*> [#uses=1]
+ %tmp7 = load <3 x i16>* %arrayidx6 ; <<3 x i16>> [#uses=1]
+ %add = add <3 x i16> %tmp7, < i16 1, i16 1, i16 1 > ; <<3 x i16>> [#uses=1]
+ store <3 x i16> %add, <3 x i16>* %arrayidx
+ br label %forinc
+
+forinc: ; preds = %forbody
+ %tmp8 = load i32* %i ; <i32> [#uses=1]
+ %inc = add i32 %tmp8, 1 ; <i32> [#uses=1]
+ store i32 %inc, i32* %i
+ br label %forcond
+
+afterfor: ; preds = %forcond
+ ret void
+}
+
diff --git a/test/CodeGen/X86/widen_arith-4.ll b/test/CodeGen/X86/widen_arith-4.ll
new file mode 100644
index 0000000..f7506ae
--- /dev/null
+++ b/test/CodeGen/X86/widen_arith-4.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: psubw
+; CHECK-NEXT: pmullw
+
+; Widen a v5i16 to v8i16 to do a vector sub and multiple
+
+define void @update(<5 x i16>* %dst, <5 x i16>* %src, i32 %n) nounwind {
+entry:
+ %dst.addr = alloca <5 x i16>* ; <<5 x i16>**> [#uses=2]
+ %src.addr = alloca <5 x i16>* ; <<5 x i16>**> [#uses=2]
+ %n.addr = alloca i32 ; <i32*> [#uses=2]
+ %v = alloca <5 x i16>, align 16 ; <<5 x i16>*> [#uses=1]
+ %i = alloca i32, align 4 ; <i32*> [#uses=6]
+ store <5 x i16>* %dst, <5 x i16>** %dst.addr
+ store <5 x i16>* %src, <5 x i16>** %src.addr
+ store i32 %n, i32* %n.addr
+ store <5 x i16> < i16 1, i16 1, i16 1, i16 0, i16 0 >, <5 x i16>* %v
+ store i32 0, i32* %i
+ br label %forcond
+
+forcond: ; preds = %forinc, %entry
+ %tmp = load i32* %i ; <i32> [#uses=1]
+ %tmp1 = load i32* %n.addr ; <i32> [#uses=1]
+ %cmp = icmp slt i32 %tmp, %tmp1 ; <i1> [#uses=1]
+ br i1 %cmp, label %forbody, label %afterfor
+
+forbody: ; preds = %forcond
+ %tmp2 = load i32* %i ; <i32> [#uses=1]
+ %tmp3 = load <5 x i16>** %dst.addr ; <<5 x i16>*> [#uses=1]
+ %arrayidx = getelementptr <5 x i16>* %tmp3, i32 %tmp2 ; <<5 x i16>*> [#uses=1]
+ %tmp4 = load i32* %i ; <i32> [#uses=1]
+ %tmp5 = load <5 x i16>** %src.addr ; <<5 x i16>*> [#uses=1]
+ %arrayidx6 = getelementptr <5 x i16>* %tmp5, i32 %tmp4 ; <<5 x i16>*> [#uses=1]
+ %tmp7 = load <5 x i16>* %arrayidx6 ; <<5 x i16>> [#uses=1]
+ %sub = sub <5 x i16> %tmp7, < i16 271, i16 271, i16 271, i16 271, i16 271 > ; <<5 x i16>> [#uses=1]
+ %mul = mul <5 x i16> %sub, < i16 2, i16 2, i16 2, i16 2, i16 2 > ; <<5 x i16>> [#uses=1]
+ store <5 x i16> %mul, <5 x i16>* %arrayidx
+ br label %forinc
+
+forinc: ; preds = %forbody
+ %tmp8 = load i32* %i ; <i32> [#uses=1]
+ %inc = add i32 %tmp8, 1 ; <i32> [#uses=1]
+ store i32 %inc, i32* %i
+ br label %forcond
+
+afterfor: ; preds = %forcond
+ ret void
+}
+
diff --git a/test/CodeGen/X86/widen_arith-5.ll b/test/CodeGen/X86/widen_arith-5.ll
new file mode 100644
index 0000000..f7f3408
--- /dev/null
+++ b/test/CodeGen/X86/widen_arith-5.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: movaps
+; CHECK: pmulld
+; CHECK: psubd
+
+; widen a v3i32 to v4i32 to do a vector multiple and a subtraction
+
+define void @update(<3 x i32>* %dst, <3 x i32>* %src, i32 %n) nounwind {
+entry:
+ %dst.addr = alloca <3 x i32>* ; <<3 x i32>**> [#uses=2]
+ %src.addr = alloca <3 x i32>* ; <<3 x i32>**> [#uses=2]
+ %n.addr = alloca i32 ; <i32*> [#uses=2]
+ %v = alloca <3 x i32>, align 16 ; <<3 x i32>*> [#uses=1]
+ %i = alloca i32, align 4 ; <i32*> [#uses=6]
+ store <3 x i32>* %dst, <3 x i32>** %dst.addr
+ store <3 x i32>* %src, <3 x i32>** %src.addr
+ store i32 %n, i32* %n.addr
+ store <3 x i32> < i32 1, i32 1, i32 1 >, <3 x i32>* %v
+ store i32 0, i32* %i
+ br label %forcond
+
+forcond: ; preds = %forinc, %entry
+ %tmp = load i32* %i ; <i32> [#uses=1]
+ %tmp1 = load i32* %n.addr ; <i32> [#uses=1]
+ %cmp = icmp slt i32 %tmp, %tmp1 ; <i1> [#uses=1]
+ br i1 %cmp, label %forbody, label %afterfor
+
+forbody: ; preds = %forcond
+ %tmp2 = load i32* %i ; <i32> [#uses=1]
+ %tmp3 = load <3 x i32>** %dst.addr ; <<3 x i32>*> [#uses=1]
+ %arrayidx = getelementptr <3 x i32>* %tmp3, i32 %tmp2 ; <<3 x i32>*> [#uses=1]
+ %tmp4 = load i32* %i ; <i32> [#uses=1]
+ %tmp5 = load <3 x i32>** %src.addr ; <<3 x i32>*> [#uses=1]
+ %arrayidx6 = getelementptr <3 x i32>* %tmp5, i32 %tmp4 ; <<3 x i32>*> [#uses=1]
+ %tmp7 = load <3 x i32>* %arrayidx6 ; <<3 x i32>> [#uses=1]
+ %mul = mul <3 x i32> %tmp7, < i32 4, i32 4, i32 4 > ; <<3 x i32>> [#uses=1]
+ %sub = sub <3 x i32> %mul, < i32 3, i32 3, i32 3 > ; <<3 x i32>> [#uses=1]
+ store <3 x i32> %sub, <3 x i32>* %arrayidx
+ br label %forinc
+
+forinc: ; preds = %forbody
+ %tmp8 = load i32* %i ; <i32> [#uses=1]
+ %inc = add i32 %tmp8, 1 ; <i32> [#uses=1]
+ store i32 %inc, i32* %i
+ br label %forcond
+
+afterfor: ; preds = %forcond
+ ret void
+}
+
diff --git a/test/CodeGen/X86/widen_arith-6.ll b/test/CodeGen/X86/widen_arith-6.ll
new file mode 100644
index 0000000..538123f
--- /dev/null
+++ b/test/CodeGen/X86/widen_arith-6.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: mulps
+; CHECK: addps
+
+; widen a v3f32 to vfi32 to do a vector multiple and an add
+
+define void @update(<3 x float>* %dst, <3 x float>* %src, i32 %n) nounwind {
+entry:
+ %dst.addr = alloca <3 x float>* ; <<3 x float>**> [#uses=2]
+ %src.addr = alloca <3 x float>* ; <<3 x float>**> [#uses=2]
+ %n.addr = alloca i32 ; <i32*> [#uses=2]
+ %v = alloca <3 x float>, align 16 ; <<3 x float>*> [#uses=2]
+ %i = alloca i32, align 4 ; <i32*> [#uses=6]
+ store <3 x float>* %dst, <3 x float>** %dst.addr
+ store <3 x float>* %src, <3 x float>** %src.addr
+ store i32 %n, i32* %n.addr
+ store <3 x float> < float 1.000000e+00, float 2.000000e+00, float 3.000000e+00 >, <3 x float>* %v
+ store i32 0, i32* %i
+ br label %forcond
+
+forcond: ; preds = %forinc, %entry
+ %tmp = load i32* %i ; <i32> [#uses=1]
+ %tmp1 = load i32* %n.addr ; <i32> [#uses=1]
+ %cmp = icmp slt i32 %tmp, %tmp1 ; <i1> [#uses=1]
+ br i1 %cmp, label %forbody, label %afterfor
+
+forbody: ; preds = %forcond
+ %tmp2 = load i32* %i ; <i32> [#uses=1]
+ %tmp3 = load <3 x float>** %dst.addr ; <<3 x float>*> [#uses=1]
+ %arrayidx = getelementptr <3 x float>* %tmp3, i32 %tmp2 ; <<3 x float>*> [#uses=1]
+ %tmp4 = load i32* %i ; <i32> [#uses=1]
+ %tmp5 = load <3 x float>** %src.addr ; <<3 x float>*> [#uses=1]
+ %arrayidx6 = getelementptr <3 x float>* %tmp5, i32 %tmp4 ; <<3 x float>*> [#uses=1]
+ %tmp7 = load <3 x float>* %arrayidx6 ; <<3 x float>> [#uses=1]
+ %tmp8 = load <3 x float>* %v ; <<3 x float>> [#uses=1]
+ %mul = fmul <3 x float> %tmp7, %tmp8 ; <<3 x float>> [#uses=1]
+ %add = fadd <3 x float> %mul, < float 0x409EE02900000000, float 0x409EE02900000000, float 0x409EE02900000000 > ; <<3 x float>> [#uses=1]
+ store <3 x float> %add, <3 x float>* %arrayidx
+ br label %forinc
+
+forinc: ; preds = %forbody
+ %tmp9 = load i32* %i ; <i32> [#uses=1]
+ %inc = add i32 %tmp9, 1 ; <i32> [#uses=1]
+ store i32 %inc, i32* %i
+ br label %forcond
+
+afterfor: ; preds = %forcond
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_cast-1.ll b/test/CodeGen/X86/widen_cast-1.ll
new file mode 100644
index 0000000..d4ab174ae
--- /dev/null
+++ b/test/CodeGen/X86/widen_cast-1.ll
@@ -0,0 +1,44 @@
+; RUN: llc -march=x86 -mattr=+sse42 < %s -disable-mmx | FileCheck %s
+; CHECK: paddw
+; CHECK: pextrd
+; CHECK: movd
+
+; bitcast a v4i16 to v2i32
+
+define void @convert(<2 x i32>* %dst, <4 x i16>* %src) nounwind {
+entry:
+ %dst.addr = alloca <2 x i32>* ; <<2 x i32>**> [#uses=2]
+ %src.addr = alloca <4 x i16>* ; <<4 x i16>**> [#uses=2]
+ %i = alloca i32, align 4 ; <i32*> [#uses=6]
+ store <2 x i32>* %dst, <2 x i32>** %dst.addr
+ store <4 x i16>* %src, <4 x i16>** %src.addr
+ store i32 0, i32* %i
+ br label %forcond
+
+forcond: ; preds = %forinc, %entry
+ %tmp = load i32* %i ; <i32> [#uses=1]
+ %cmp = icmp slt i32 %tmp, 4 ; <i1> [#uses=1]
+ br i1 %cmp, label %forbody, label %afterfor
+
+forbody: ; preds = %forcond
+ %tmp1 = load i32* %i ; <i32> [#uses=1]
+ %tmp2 = load <2 x i32>** %dst.addr ; <<2 x i32>*> [#uses=1]
+ %arrayidx = getelementptr <2 x i32>* %tmp2, i32 %tmp1 ; <<2 x i32>*> [#uses=1]
+ %tmp3 = load i32* %i ; <i32> [#uses=1]
+ %tmp4 = load <4 x i16>** %src.addr ; <<4 x i16>*> [#uses=1]
+ %arrayidx5 = getelementptr <4 x i16>* %tmp4, i32 %tmp3 ; <<4 x i16>*> [#uses=1]
+ %tmp6 = load <4 x i16>* %arrayidx5 ; <<4 x i16>> [#uses=1]
+ %add = add <4 x i16> %tmp6, < i16 1, i16 1, i16 1, i16 1 > ; <<4 x i16>> [#uses=1]
+ %conv = bitcast <4 x i16> %add to <2 x i32> ; <<2 x i32>> [#uses=1]
+ store <2 x i32> %conv, <2 x i32>* %arrayidx
+ br label %forinc
+
+forinc: ; preds = %forbody
+ %tmp7 = load i32* %i ; <i32> [#uses=1]
+ %inc = add i32 %tmp7, 1 ; <i32> [#uses=1]
+ store i32 %inc, i32* %i
+ br label %forcond
+
+afterfor: ; preds = %forcond
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_cast-2.ll b/test/CodeGen/X86/widen_cast-2.ll
new file mode 100644
index 0000000..1e626a2
--- /dev/null
+++ b/test/CodeGen/X86/widen_cast-2.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: pextrd
+; CHECK: pextrd
+; CHECK: movd
+; CHECK: movaps
+
+
+; bitcast v14i16 to v7i32
+
+define void @convert(<7 x i32>* %dst, <14 x i16>* %src) nounwind {
+entry:
+ %dst.addr = alloca <7 x i32>* ; <<7 x i32>**> [#uses=2]
+ %src.addr = alloca <14 x i16>* ; <<14 x i16>**> [#uses=2]
+ %i = alloca i32, align 4 ; <i32*> [#uses=6]
+ store <7 x i32>* %dst, <7 x i32>** %dst.addr
+ store <14 x i16>* %src, <14 x i16>** %src.addr
+ store i32 0, i32* %i
+ br label %forcond
+
+forcond: ; preds = %forinc, %entry
+ %tmp = load i32* %i ; <i32> [#uses=1]
+ %cmp = icmp slt i32 %tmp, 4 ; <i1> [#uses=1]
+ br i1 %cmp, label %forbody, label %afterfor
+
+forbody: ; preds = %forcond
+ %tmp1 = load i32* %i ; <i32> [#uses=1]
+ %tmp2 = load <7 x i32>** %dst.addr ; <<2 x i32>*> [#uses=1]
+ %arrayidx = getelementptr <7 x i32>* %tmp2, i32 %tmp1 ; <<7 x i32>*> [#uses=1]
+ %tmp3 = load i32* %i ; <i32> [#uses=1]
+ %tmp4 = load <14 x i16>** %src.addr ; <<4 x i16>*> [#uses=1]
+ %arrayidx5 = getelementptr <14 x i16>* %tmp4, i32 %tmp3 ; <<4 x i16>*> [#uses=1]
+ %tmp6 = load <14 x i16>* %arrayidx5 ; <<4 x i16>> [#uses=1]
+ %add = add <14 x i16> %tmp6, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1 > ; <<4 x i16>> [#uses=1]
+ %conv = bitcast <14 x i16> %add to <7 x i32> ; <<7 x i32>> [#uses=1]
+ store <7 x i32> %conv, <7 x i32>* %arrayidx
+ br label %forinc
+
+forinc: ; preds = %forbody
+ %tmp7 = load i32* %i ; <i32> [#uses=1]
+ %inc = add i32 %tmp7, 1 ; <i32> [#uses=1]
+ store i32 %inc, i32* %i
+ br label %forcond
+
+afterfor: ; preds = %forcond
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_cast-3.ll b/test/CodeGen/X86/widen_cast-3.ll
new file mode 100644
index 0000000..02674dd
--- /dev/null
+++ b/test/CodeGen/X86/widen_cast-3.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: paddd
+; CHECK: pextrd
+; CHECK: pextrd
+
+; bitcast v12i8 to v3i32
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target triple = "i686-apple-darwin10.0.0d2"
+
+define void @convert(<12 x i8>* %dst.addr, <3 x i32> %src) nounwind {
+entry:
+ %add = add <3 x i32> %src, < i32 1, i32 1, i32 1 > ; <<3 x i32>> [#uses=1]
+ %conv = bitcast <3 x i32> %add to <12 x i8> ; <<12 x i8>> [#uses=1]
+ store <12 x i8> %conv, <12 x i8>* %dst.addr
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_cast-4.ll b/test/CodeGen/X86/widen_cast-4.ll
new file mode 100644
index 0000000..5f31e56
--- /dev/null
+++ b/test/CodeGen/X86/widen_cast-4.ll
@@ -0,0 +1,67 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: sarb
+; CHECK: sarb
+; CHECK: sarb
+; CHECK: sarb
+; CHECK: sarb
+; CHECK: sarb
+; CHECK: sarb
+; CHECK: sarb
+
+; v8i8 that is widen to v16i8 then split
+; FIXME: This is widen to v16i8 and split to 16 and we then rebuild the vector.
+; Unfortunately, we don't split the store so we don't get the code we want.
+
+define void @update(i64* %dst_i, i64* %src_i, i32 %n) nounwind {
+entry:
+ %dst_i.addr = alloca i64* ; <i64**> [#uses=2]
+ %src_i.addr = alloca i64* ; <i64**> [#uses=2]
+ %n.addr = alloca i32 ; <i32*> [#uses=2]
+ %i = alloca i32, align 4 ; <i32*> [#uses=8]
+ %dst = alloca <8 x i8>*, align 4 ; <<8 x i8>**> [#uses=2]
+ %src = alloca <8 x i8>*, align 4 ; <<8 x i8>**> [#uses=2]
+ store i64* %dst_i, i64** %dst_i.addr
+ store i64* %src_i, i64** %src_i.addr
+ store i32 %n, i32* %n.addr
+ store i32 0, i32* %i
+ br label %forcond
+
+forcond: ; preds = %forinc, %entry
+ %tmp = load i32* %i ; <i32> [#uses=1]
+ %tmp1 = load i32* %n.addr ; <i32> [#uses=1]
+ %cmp = icmp slt i32 %tmp, %tmp1 ; <i1> [#uses=1]
+ br i1 %cmp, label %forbody, label %afterfor
+
+forbody: ; preds = %forcond
+ %tmp2 = load i32* %i ; <i32> [#uses=1]
+ %tmp3 = load i64** %dst_i.addr ; <i64*> [#uses=1]
+ %arrayidx = getelementptr i64* %tmp3, i32 %tmp2 ; <i64*> [#uses=1]
+ %conv = bitcast i64* %arrayidx to <8 x i8>* ; <<8 x i8>*> [#uses=1]
+ store <8 x i8>* %conv, <8 x i8>** %dst
+ %tmp4 = load i32* %i ; <i32> [#uses=1]
+ %tmp5 = load i64** %src_i.addr ; <i64*> [#uses=1]
+ %arrayidx6 = getelementptr i64* %tmp5, i32 %tmp4 ; <i64*> [#uses=1]
+ %conv7 = bitcast i64* %arrayidx6 to <8 x i8>* ; <<8 x i8>*> [#uses=1]
+ store <8 x i8>* %conv7, <8 x i8>** %src
+ %tmp8 = load i32* %i ; <i32> [#uses=1]
+ %tmp9 = load <8 x i8>** %dst ; <<8 x i8>*> [#uses=1]
+ %arrayidx10 = getelementptr <8 x i8>* %tmp9, i32 %tmp8 ; <<8 x i8>*> [#uses=1]
+ %tmp11 = load i32* %i ; <i32> [#uses=1]
+ %tmp12 = load <8 x i8>** %src ; <<8 x i8>*> [#uses=1]
+ %arrayidx13 = getelementptr <8 x i8>* %tmp12, i32 %tmp11 ; <<8 x i8>*> [#uses=1]
+ %tmp14 = load <8 x i8>* %arrayidx13 ; <<8 x i8>> [#uses=1]
+ %add = add <8 x i8> %tmp14, < i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1 > ; <<8 x i8>> [#uses=1]
+ %shr = ashr <8 x i8> %add, < i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2 > ; <<8 x i8>> [#uses=1]
+ store <8 x i8> %shr, <8 x i8>* %arrayidx10
+ br label %forinc
+
+forinc: ; preds = %forbody
+ %tmp15 = load i32* %i ; <i32> [#uses=1]
+ %inc = add i32 %tmp15, 1 ; <i32> [#uses=1]
+ store i32 %inc, i32* %i
+ br label %forcond
+
+afterfor: ; preds = %forcond
+ ret void
+}
+
diff --git a/test/CodeGen/X86/widen_cast-5.ll b/test/CodeGen/X86/widen_cast-5.ll
new file mode 100644
index 0000000..d1d7fec
--- /dev/null
+++ b/test/CodeGen/X86/widen_cast-5.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: movl
+; CHECK: movd
+
+; bitcast a i64 to v2i32
+
+define void @convert(<2 x i32>* %dst.addr, i64 %src) nounwind {
+entry:
+ %conv = bitcast i64 %src to <2 x i32>
+ %xor = xor <2 x i32> %conv, < i32 255, i32 32767 >
+ store <2 x i32> %xor, <2 x i32>* %dst.addr
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_cast-6.ll b/test/CodeGen/X86/widen_cast-6.ll
new file mode 100644
index 0000000..08759bf
--- /dev/null
+++ b/test/CodeGen/X86/widen_cast-6.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86 -mattr=+sse41 -disable-mmx | FileCheck %s
+; CHECK: movd
+
+; Test bit convert that requires widening in the operand.
+
+define i32 @return_v2hi() nounwind {
+entry:
+ %retval12 = bitcast <2 x i16> zeroinitializer to i32 ; <i32> [#uses=1]
+ ret i32 %retval12
+}
diff --git a/test/CodeGen/X86/widen_conv-1.ll b/test/CodeGen/X86/widen_conv-1.ll
new file mode 100644
index 0000000..a2029dd
--- /dev/null
+++ b/test/CodeGen/X86/widen_conv-1.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: pshufd
+; CHECK: paddd
+
+; truncate v2i64 to v2i32
+
+define void @convert(<2 x i32>* %dst.addr, <2 x i64> %src) nounwind {
+entry:
+ %val = trunc <2 x i64> %src to <2 x i32>
+ %add = add <2 x i32> %val, < i32 1, i32 1 >
+ store <2 x i32> %add, <2 x i32>* %dst.addr
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_conv-2.ll b/test/CodeGen/X86/widen_conv-2.ll
new file mode 100644
index 0000000..b24a9b3
--- /dev/null
+++ b/test/CodeGen/X86/widen_conv-2.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: movswl
+; CHECK: movswl
+
+; sign extension v2i32 to v2i16
+
+define void @convert(<2 x i32>* %dst.addr, <2 x i16> %src) nounwind {
+entry:
+ %signext = sext <2 x i16> %src to <2 x i32> ; <<12 x i8>> [#uses=1]
+ store <2 x i32> %signext, <2 x i32>* %dst.addr
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_conv-3.ll b/test/CodeGen/X86/widen_conv-3.ll
new file mode 100644
index 0000000..1a40800
--- /dev/null
+++ b/test/CodeGen/X86/widen_conv-3.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: cvtsi2ss
+
+; sign to float v2i16 to v2f32
+
+define void @convert(<2 x float>* %dst.addr, <2 x i16> %src) nounwind {
+entry:
+ %val = sitofp <2 x i16> %src to <2 x float>
+ store <2 x float> %val, <2 x float>* %dst.addr
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_conv-4.ll b/test/CodeGen/X86/widen_conv-4.ll
new file mode 100644
index 0000000..e505b62
--- /dev/null
+++ b/test/CodeGen/X86/widen_conv-4.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: cvtsi2ss
+
+; unsigned to float v7i16 to v7f32
+
+define void @convert(<7 x float>* %dst.addr, <7 x i16> %src) nounwind {
+entry:
+ %val = sitofp <7 x i16> %src to <7 x float>
+ store <7 x float> %val, <7 x float>* %dst.addr
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_extract-1.ll b/test/CodeGen/X86/widen_extract-1.ll
new file mode 100644
index 0000000..308e6b8
--- /dev/null
+++ b/test/CodeGen/X86/widen_extract-1.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s
+; widen extract subvector
+
+define void @convert(<2 x double>* %dst.addr, <3 x double> %src) {
+entry:
+; CHECK: convert:
+; CHECK: unpcklpd {{%xmm[0-7]}}, {{%xmm[0-7]}}
+; CHECK-NEXT: movapd
+ %val = shufflevector <3 x double> %src, <3 x double> undef, <2 x i32> < i32 0, i32 1>
+ store <2 x double> %val, <2 x double>* %dst.addr
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_load-0.ll b/test/CodeGen/X86/widen_load-0.ll
new file mode 100644
index 0000000..f6c4af0
--- /dev/null
+++ b/test/CodeGen/X86/widen_load-0.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -o - -march=x86-64 | FileCheck %s
+; PR4891
+
+; Both loads should happen before either store.
+
+; CHECK: movl (%rdi), %eax
+; CHECK: movl (%rsi), %ecx
+; CHECK: movl %ecx, (%rdi)
+; CHECK: movl %eax, (%rsi)
+
+define void @short2_int_swap(<2 x i16>* nocapture %b, i32* nocapture %c) nounwind {
+entry:
+ %0 = load <2 x i16>* %b, align 2 ; <<2 x i16>> [#uses=1]
+ %1 = load i32* %c, align 4 ; <i32> [#uses=1]
+ %tmp1 = bitcast i32 %1 to <2 x i16> ; <<2 x i16>> [#uses=1]
+ store <2 x i16> %tmp1, <2 x i16>* %b, align 2
+ %tmp5 = bitcast <2 x i16> %0 to <1 x i32> ; <<1 x i32>> [#uses=1]
+ %tmp3 = extractelement <1 x i32> %tmp5, i32 0 ; <i32> [#uses=1]
+ store i32 %tmp3, i32* %c, align 4
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_load-1.ll b/test/CodeGen/X86/widen_load-1.ll
new file mode 100644
index 0000000..d397645
--- /dev/null
+++ b/test/CodeGen/X86/widen_load-1.ll
@@ -0,0 +1,45 @@
+; RUN: llc %s -o - -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -disable-mmx | FileCheck %s
+; PR4891
+
+; This load should be before the call, not after.
+
+; CHECK: movaps compl+128(%rip), %xmm0
+; CHECK: movaps %xmm0, (%rsp)
+; CHECK: callq killcommon
+
+@compl = linkonce global [20 x i64] zeroinitializer, align 64 ; <[20 x i64]*> [#uses=1]
+
+declare void @killcommon(i32* noalias)
+
+define void @reset(<2 x float>* noalias %garbage1) {
+"file complex.c, line 27, bb1":
+ %changed = alloca i32, align 4 ; <i32*> [#uses=3]
+ br label %"file complex.c, line 27, bb13"
+
+"file complex.c, line 27, bb13": ; preds = %"file complex.c, line 27, bb1"
+ store i32 0, i32* %changed, align 4
+ %r2 = getelementptr float* bitcast ([20 x i64]* @compl to float*), i64 32 ; <float*> [#uses=1]
+ %r3 = bitcast float* %r2 to <2 x float>* ; <<2 x float>*> [#uses=1]
+ %r4 = load <2 x float>* %r3, align 4 ; <<2 x float>> [#uses=1]
+ call void @killcommon(i32* %changed)
+ br label %"file complex.c, line 34, bb4"
+
+"file complex.c, line 34, bb4": ; preds = %"file complex.c, line 27, bb13"
+ %r5 = load i32* %changed, align 4 ; <i32> [#uses=1]
+ %r6 = icmp eq i32 %r5, 0 ; <i1> [#uses=1]
+ %r7 = zext i1 %r6 to i32 ; <i32> [#uses=1]
+ %r8 = icmp ne i32 %r7, 0 ; <i1> [#uses=1]
+ br i1 %r8, label %"file complex.c, line 34, bb7", label %"file complex.c, line 27, bb5"
+
+"file complex.c, line 27, bb5": ; preds = %"file complex.c, line 34, bb4"
+ br label %"file complex.c, line 35, bb6"
+
+"file complex.c, line 35, bb6": ; preds = %"file complex.c, line 27, bb5"
+ %r11 = ptrtoint <2 x float>* %garbage1 to i64 ; <i64> [#uses=1]
+ %r12 = inttoptr i64 %r11 to <2 x float>* ; <<2 x float>*> [#uses=1]
+ store <2 x float> %r4, <2 x float>* %r12, align 4
+ br label %"file complex.c, line 34, bb7"
+
+"file complex.c, line 34, bb7": ; preds = %"file complex.c, line 35, bb6", %"file complex.c, line 34, bb4"
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_load-2.ll b/test/CodeGen/X86/widen_load-2.ll
new file mode 100644
index 0000000..11383fa
--- /dev/null
+++ b/test/CodeGen/X86/widen_load-2.ll
@@ -0,0 +1,155 @@
+; RUN: llc < %s -o - -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s
+
+; Test based on pr5626 to load/store
+;
+
+%i32vec3 = type <3 x i32>
+define void @add3i32(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) {
+; CHECK: movaps
+; CHECK: paddd
+; CHECK: pextrd
+; CHECK: movq
+ %a = load %i32vec3* %ap, align 16
+ %b = load %i32vec3* %bp, align 16
+ %x = add %i32vec3 %a, %b
+ store %i32vec3 %x, %i32vec3* %ret, align 16
+ ret void
+}
+
+define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) {
+; CHECK: movq
+; CHECK: pinsrd
+; CHECK: movq
+; CHECK: pinsrd
+; CHECK: paddd
+; CHECK: pextrd
+; CHECK: movq
+ %a = load %i32vec3* %ap
+ %b = load %i32vec3* %bp
+ %x = add %i32vec3 %a, %b
+ store %i32vec3 %x, %i32vec3* %ret
+ ret void
+}
+
+%i32vec7 = type <7 x i32>
+define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) {
+; CHECK: movaps
+; CHECK: movaps
+; CHECK: paddd
+; CHECK: paddd
+; CHECK: pextrd
+; CHECK: movq
+; CHECK: movaps
+ %a = load %i32vec7* %ap, align 16
+ %b = load %i32vec7* %bp, align 16
+ %x = add %i32vec7 %a, %b
+ store %i32vec7 %x, %i32vec7* %ret, align 16
+ ret void
+}
+
+%i32vec12 = type <12 x i32>
+define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) {
+; CHECK: movaps
+; CHECK: movaps
+; CHECK: movaps
+; CHECK: paddd
+; CHECK: paddd
+; CHECK: paddd
+; CHECK: movaps
+; CHECK: movaps
+; CHECK: movaps
+ %a = load %i32vec12* %ap, align 16
+ %b = load %i32vec12* %bp, align 16
+ %x = add %i32vec12 %a, %b
+ store %i32vec12 %x, %i32vec12* %ret, align 16
+ ret void
+}
+
+
+%i16vec3 = type <3 x i16>
+define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind {
+; CHECK: movaps
+; CHECK: paddw
+; CHECK: movd
+; CHECK: pextrw
+ %a = load %i16vec3* %ap, align 16
+ %b = load %i16vec3* %bp, align 16
+ %x = add %i16vec3 %a, %b
+ store %i16vec3 %x, %i16vec3* %ret, align 16
+ ret void
+}
+
+%i16vec4 = type <4 x i16>
+define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind {
+; CHECK: movaps
+; CHECK: paddw
+; CHECK: movq
+ %a = load %i16vec4* %ap, align 16
+ %b = load %i16vec4* %bp, align 16
+ %x = add %i16vec4 %a, %b
+ store %i16vec4 %x, %i16vec4* %ret, align 16
+ ret void
+}
+
+%i16vec12 = type <12 x i16>
+define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %bp) nounwind {
+; CHECK: movaps
+; CHECK: movaps
+; CHECK: paddw
+; CHECK: paddw
+; CHECK: movq
+; CHECK: movaps
+ %a = load %i16vec12* %ap, align 16
+ %b = load %i16vec12* %bp, align 16
+ %x = add %i16vec12 %a, %b
+ store %i16vec12 %x, %i16vec12* %ret, align 16
+ ret void
+}
+
+%i16vec18 = type <18 x i16>
+define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %bp) nounwind {
+; CHECK: movaps
+; CHECK: movaps
+; CHECK: movaps
+; CHECK: paddw
+; CHECK: paddw
+; CHECK: paddw
+; CHECK: movd
+; CHECK: movaps
+; CHECK: movaps
+ %a = load %i16vec18* %ap, align 16
+ %b = load %i16vec18* %bp, align 16
+ %x = add %i16vec18 %a, %b
+ store %i16vec18 %x, %i16vec18* %ret, align 16
+ ret void
+}
+
+
+%i8vec3 = type <3 x i8>
+define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind {
+; CHECK: movaps
+; CHECK: paddb
+; CHECK: pextrb
+; CHECK: movb
+ %a = load %i8vec3* %ap, align 16
+ %b = load %i8vec3* %bp, align 16
+ %x = add %i8vec3 %a, %b
+ store %i8vec3 %x, %i8vec3* %ret, align 16
+ ret void
+}
+
+%i8vec31 = type <31 x i8>
+define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind {
+; CHECK: movaps
+; CHECK: movaps
+; CHECK: paddb
+; CHECK: paddb
+; CHECK: movq
+; CHECK: pextrb
+; CHECK: pextrw
+ %a = load %i8vec31* %ap, align 16
+ %b = load %i8vec31* %bp, align 16
+ %x = add %i8vec31 %a, %b
+ store %i8vec31 %x, %i8vec31* %ret, align 16
+ ret void
+}
\ No newline at end of file
diff --git a/test/CodeGen/X86/widen_select-1.ll b/test/CodeGen/X86/widen_select-1.ll
new file mode 100644
index 0000000..d9de892
--- /dev/null
+++ b/test/CodeGen/X86/widen_select-1.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: jne
+
+; widening select v6i32 and then a sub
+
+define void @select(i1 %c, <6 x i32>* %dst.addr, <6 x i32> %src1,<6 x i32> %src2) nounwind {
+entry:
+ %x = select i1 %c, <6 x i32> %src1, <6 x i32> %src2
+ %val = sub <6 x i32> %x, < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
+ store <6 x i32> %val, <6 x i32>* %dst.addr
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_shuffle-1.ll b/test/CodeGen/X86/widen_shuffle-1.ll
new file mode 100644
index 0000000..47dba4b
--- /dev/null
+++ b/test/CodeGen/X86/widen_shuffle-1.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: insertps
+; CHECK: extractps
+
+; widening shuffle v3float and then a add
+
+define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
+entry:
+ %x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2>
+ %val = fadd <3 x float> %x, %src2
+ store <3 x float> %val, <3 x float>* %dst.addr
+ ret void
+}
diff --git a/test/CodeGen/X86/widen_shuffle-2.ll b/test/CodeGen/X86/widen_shuffle-2.ll
new file mode 100644
index 0000000..9374a02
--- /dev/null
+++ b/test/CodeGen/X86/widen_shuffle-2.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
+; CHECK: insertps
+; CHECK: extractps
+
+; widening shuffle v3float and then a add
+
+define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
+entry:
+ %x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2>
+ %val = fadd <3 x float> %x, %src2
+ store <3 x float> %val, <3 x float>* %dst.addr
+ ret void
+}
diff --git a/test/CodeGen/X86/x86-64-and-mask.ll b/test/CodeGen/X86/x86-64-and-mask.ll
new file mode 100644
index 0000000..2465f23
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-and-mask.ll
@@ -0,0 +1,49 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin8"
+
+; This should be a single mov, not a load of immediate + andq.
+; CHECK: test:
+; CHECK: movl %edi, %eax
+
+define i64 @test(i64 %x) nounwind {
+entry:
+ %tmp123 = and i64 %x, 4294967295 ; <i64> [#uses=1]
+ ret i64 %tmp123
+}
+
+; This copy can't be coalesced away because it needs the implicit zero-extend.
+; CHECK: bbb:
+; CHECK: movl %edi, %edi
+
+define void @bbb(i64 %x) nounwind {
+ %t = and i64 %x, 4294967295
+ call void @foo(i64 %t)
+ ret void
+}
+
+; This should use a 32-bit and with implicit zero-extension, not a 64-bit and
+; with a separate mov to materialize the mask.
+; rdar://7527390
+; CHECK: ccc:
+; CHECK: andl $-1048593, %edi
+
+declare void @foo(i64 %x) nounwind
+
+define void @ccc(i64 %x) nounwind {
+ %t = and i64 %x, 4293918703
+ call void @foo(i64 %t)
+ ret void
+}
+
+; This requires a mov and a 64-bit and.
+; CHECK: ddd:
+; CHECK: movabsq $4294967296, %rax
+; CHECK: andq %rax, %rdi
+
+define void @ddd(i64 %x) nounwind {
+ %t = and i64 %x, 4294967296
+ call void @foo(i64 %t)
+ ret void
+}
diff --git a/test/CodeGen/X86/x86-64-arg.ll b/test/CodeGen/X86/x86-64-arg.ll
new file mode 100644
index 0000000..ec8dd8e
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-arg.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s | grep {movl %edi, %eax}
+; The input value is already sign extended, don't re-extend it.
+; This testcase corresponds to:
+; int test(short X) { return (int)X; }
+
+target datalayout = "e-p:64:64"
+target triple = "x86_64-apple-darwin8"
+
+
+define i32 @test(i16 signext %X) {
+entry:
+ %tmp12 = sext i16 %X to i32 ; <i32> [#uses=1]
+ ret i32 %tmp12
+}
+
diff --git a/test/CodeGen/X86/x86-64-asm.ll b/test/CodeGen/X86/x86-64-asm.ll
new file mode 100644
index 0000000..2640e59
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-asm.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s
+; PR1029
+
+target datalayout = "e-p:64:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @frame_dummy() {
+entry:
+ %tmp1 = tail call void (i8*)* (void (i8*)*)* asm "", "=r,0,~{dirflag},~{fpsr},~{flags}"( void (i8*)* null ) ; <void (i8*)*> [#uses=0]
+ ret void
+}
+
diff --git a/test/CodeGen/X86/x86-64-dead-stack-adjust.ll b/test/CodeGen/X86/x86-64-dead-stack-adjust.ll
new file mode 100644
index 0000000..79316f2
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-dead-stack-adjust.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s | not grep rsp
+; RUN: llc < %s | grep cvttsd2siq
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin8"
+
+define double @a(double %b) nounwind {
+entry:
+ %tmp12 = fptoui double %b to i32 ; <i32> [#uses=1]
+ %tmp123 = uitofp i32 %tmp12 to double ; <double> [#uses=1]
+ ret double %tmp123
+}
diff --git a/test/CodeGen/X86/x86-64-disp.ll b/test/CodeGen/X86/x86-64-disp.ll
new file mode 100644
index 0000000..d8059eb
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-disp.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=x86-64 | grep mov | count 2
+
+; Fold an offset into an address even if it's not a 32-bit
+; signed integer.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+@call_used_regs = external global [53 x i8], align 32
+
+define fastcc void @foo() nounwind {
+ %t = getelementptr [53 x i8]* @call_used_regs, i64 0, i64 4294967295
+ store i8 1, i8* %t, align 1
+ ret void
+}
diff --git a/test/CodeGen/X86/x86-64-frameaddr.ll b/test/CodeGen/X86/x86-64-frameaddr.ll
new file mode 100644
index 0000000..57163d3
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-frameaddr.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86-64 | grep movq | grep rbp
+
+define i64* @stack_end_address() nounwind {
+entry:
+ tail call i8* @llvm.frameaddress( i32 0 )
+ bitcast i8* %0 to i64*
+ ret i64* %1
+}
+
+declare i8* @llvm.frameaddress(i32) nounwind readnone
diff --git a/test/CodeGen/X86/x86-64-gv-offset.ll b/test/CodeGen/X86/x86-64-gv-offset.ll
new file mode 100644
index 0000000..365e4af
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-gv-offset.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep lea
+
+ %struct.x = type { float, double }
+@X = global %struct.x { float 1.000000e+00, double 2.000000e+00 }, align 16 ; <%struct.x*> [#uses=2]
+
+define i32 @main() nounwind {
+entry:
+ %tmp2 = load float* getelementptr (%struct.x* @X, i32 0, i32 0), align 16 ; <float> [#uses=1]
+ %tmp4 = load double* getelementptr (%struct.x* @X, i32 0, i32 1), align 8 ; <double> [#uses=1]
+ tail call void @t( float %tmp2, double %tmp4 ) nounwind
+ ret i32 0
+}
+
+declare void @t(float, double)
diff --git a/test/CodeGen/X86/x86-64-jumps.ll b/test/CodeGen/X86/x86-64-jumps.ll
new file mode 100644
index 0000000..11b40c8
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-jumps.ll
@@ -0,0 +1,45 @@
+; RUN: llc < %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin10.0"
+
+define i8 @test1() nounwind ssp {
+entry:
+ %0 = select i1 undef, i8* blockaddress(@test1, %bb), i8* blockaddress(@test1, %bb6) ; <i8*> [#uses=1]
+ indirectbr i8* %0, [label %bb, label %bb6]
+
+bb: ; preds = %entry
+ ret i8 1
+
+bb6: ; preds = %entry
+ ret i8 2
+}
+
+
+; PR5930 - Trunc of block address differences.
[email protected] = internal constant [3 x i32] [i32 trunc (i64 sub (i64 ptrtoint (i8* blockaddress(@test2, %foo) to i64), i64 ptrtoint (i8* blockaddress(@test2, %foo) to i64)) to i32), i32 trunc (i64 sub (i64 ptrtoint (i8* blockaddress(@test2, %bar) to i64), i64 ptrtoint (i8* blockaddress(@test2, %foo) to i64)) to i32), i32 trunc (i64 sub (i64 ptrtoint (i8* blockaddress(@test2, %hack) to i64), i64 ptrtoint (i8* blockaddress(@test2, %foo) to i64)) to i32)] ; <[3 x i32]*> [#uses=1]
+
+define void @test2(i32 %i) nounwind ssp {
+entry:
+ %i.addr = alloca i32 ; <i32*> [#uses=2]
+ store i32 %i, i32* %i.addr
+ %tmp = load i32* %i.addr ; <i32> [#uses=1]
+ %idxprom = sext i32 %tmp to i64 ; <i64> [#uses=1]
+ %arrayidx = getelementptr inbounds i32* getelementptr inbounds ([3 x i32]* @test.array, i32 0, i32 0), i64 %idxprom ; <i32*> [#uses=1]
+ %tmp1 = load i32* %arrayidx ; <i32> [#uses=1]
+ %idx.ext = sext i32 %tmp1 to i64 ; <i64> [#uses=1]
+ %add.ptr = getelementptr i8* blockaddress(@test2, %foo), i64 %idx.ext ; <i8*> [#uses=1]
+ br label %indirectgoto
+
+foo: ; preds = %indirectgoto, %indirectgoto, %indirectgoto, %indirectgoto, %indirectgoto
+ br label %bar
+
+bar: ; preds = %foo, %indirectgoto
+ br label %hack
+
+hack: ; preds = %bar, %indirectgoto
+ ret void
+
+indirectgoto: ; preds = %entry
+ %indirect.goto.dest = phi i8* [ %add.ptr, %entry ] ; <i8*> [#uses=1]
+ indirectbr i8* %indirect.goto.dest, [label %foo, label %foo, label %bar, label %foo, label %hack, label %foo, label %foo]
+}
diff --git a/test/CodeGen/X86/x86-64-malloc.ll b/test/CodeGen/X86/x86-64-malloc.ll
new file mode 100644
index 0000000..b4f1fa6
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-malloc.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=x86-64 | grep {shll.*3, %edi}
+; PR3829
+; The generated code should multiply by 3 (sizeof i8*) as an i32,
+; not as an i64!
+
+define i8** @test(i32 %sz) {
+ %sub = add i32 %sz, 536870911 ; <i32> [#uses=1]
+ %call = malloc i8*, i32 %sub ; <i8**> [#uses=1]
+ ret i8** %call
+}
diff --git a/test/CodeGen/X86/x86-64-mem.ll b/test/CodeGen/X86/x86-64-mem.ll
new file mode 100644
index 0000000..d15f516
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-mem.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -o %t1
+; RUN: grep GOTPCREL %t1 | count 4
+; RUN: grep %%rip %t1 | count 6
+; RUN: grep movq %t1 | count 6
+; RUN: grep leaq %t1 | count 1
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=static -o %t2
+; RUN: grep movl %t2 | count 2
+; RUN: grep movq %t2 | count 2
+
+@ptr = external global i32* ; <i32**> [#uses=1]
+@src = external global [0 x i32] ; <[0 x i32]*> [#uses=1]
+@dst = external global [0 x i32] ; <[0 x i32]*> [#uses=1]
+@lptr = internal global i32* null ; <i32**> [#uses=1]
+@ldst = internal global [500 x i32] zeroinitializer, align 32 ; <[500 x i32]*> [#uses=1]
+@lsrc = internal global [500 x i32] zeroinitializer, align 32 ; <[500 x i32]*> [#uses=0]
+@bsrc = internal global [500000 x i32] zeroinitializer, align 32 ; <[500000 x i32]*> [#uses=0]
+@bdst = internal global [500000 x i32] zeroinitializer, align 32 ; <[500000 x i32]*> [#uses=0]
+
+define void @test1() nounwind {
+ %tmp = load i32* getelementptr ([0 x i32]* @src, i32 0, i32 0) ; <i32> [#uses=1]
+ store i32 %tmp, i32* getelementptr ([0 x i32]* @dst, i32 0, i32 0)
+ ret void
+}
+
+define void @test2() nounwind {
+ store i32* getelementptr ([0 x i32]* @dst, i32 0, i32 0), i32** @ptr
+ ret void
+}
+
+define void @test3() nounwind {
+ store i32* getelementptr ([500 x i32]* @ldst, i32 0, i32 0), i32** @lptr
+ br label %return
+
+return: ; preds = %0
+ ret void
+}
diff --git a/test/CodeGen/X86/x86-64-pic-1.ll b/test/CodeGen/X86/x86-64-pic-1.ll
new file mode 100644
index 0000000..46f6d33
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-pic-1.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: grep {callq f@PLT} %t1
+
+define void @g() {
+entry:
+ call void @f( )
+ ret void
+}
+
+declare void @f()
diff --git a/test/CodeGen/X86/x86-64-pic-10.ll b/test/CodeGen/X86/x86-64-pic-10.ll
new file mode 100644
index 0000000..b6f82e2
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-pic-10.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: grep {callq g@PLT} %t1
+
+@g = alias weak i32 ()* @f
+
+define void @h() {
+entry:
+ %tmp31 = call i32 @g()
+ ret void
+}
+
+declare extern_weak i32 @f()
diff --git a/test/CodeGen/X86/x86-64-pic-11.ll b/test/CodeGen/X86/x86-64-pic-11.ll
new file mode 100644
index 0000000..4db331c
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-pic-11.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: grep {callq __fixunsxfti@PLT} %t1
+
+define i128 @f(x86_fp80 %a) nounwind {
+entry:
+ %tmp78 = fptoui x86_fp80 %a to i128
+ ret i128 %tmp78
+}
diff --git a/test/CodeGen/X86/x86-64-pic-2.ll b/test/CodeGen/X86/x86-64-pic-2.ll
new file mode 100644
index 0000000..1ce2de7
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-pic-2.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: grep {callq f} %t1
+; RUN: not grep {callq f@PLT} %t1
+
+define void @g() {
+entry:
+ call void @f( )
+ ret void
+}
+
+declare hidden void @f()
diff --git a/test/CodeGen/X86/x86-64-pic-3.ll b/test/CodeGen/X86/x86-64-pic-3.ll
new file mode 100644
index 0000000..aa3c888
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-pic-3.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: grep {callq f} %t1
+; RUN: not grep {callq f@PLT} %t1
+
+define void @g() {
+entry:
+ call void @f( )
+ ret void
+}
+
+define internal void @f() {
+entry:
+ ret void
+}
diff --git a/test/CodeGen/X86/x86-64-pic-4.ll b/test/CodeGen/X86/x86-64-pic-4.ll
new file mode 100644
index 0000000..90fc119
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-pic-4.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: grep {movq a@GOTPCREL(%rip),} %t1
+
+@a = global i32 0
+
+define i32 @get_a() {
+entry:
+ %tmp1 = load i32* @a, align 4
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/X86/x86-64-pic-5.ll b/test/CodeGen/X86/x86-64-pic-5.ll
new file mode 100644
index 0000000..6369bde
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-pic-5.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: grep {movl a(%rip),} %t1
+; RUN: not grep GOTPCREL %t1
+
+@a = hidden global i32 0
+
+define i32 @get_a() {
+entry:
+ %tmp1 = load i32* @a, align 4
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/X86/x86-64-pic-6.ll b/test/CodeGen/X86/x86-64-pic-6.ll
new file mode 100644
index 0000000..6e19ad3
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-pic-6.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: grep {movl a(%rip),} %t1
+; RUN: not grep GOTPCREL %t1
+
+@a = internal global i32 0
+
+define i32 @get_a() nounwind {
+entry:
+ %tmp1 = load i32* @a, align 4
+ ret i32 %tmp1
+}
diff --git a/test/CodeGen/X86/x86-64-pic-7.ll b/test/CodeGen/X86/x86-64-pic-7.ll
new file mode 100644
index 0000000..4d98ee61
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-pic-7.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: grep {movq f@GOTPCREL(%rip),} %t1
+
+define void ()* @g() nounwind {
+entry:
+ ret void ()* @f
+}
+
+declare void @f()
diff --git a/test/CodeGen/X86/x86-64-pic-8.ll b/test/CodeGen/X86/x86-64-pic-8.ll
new file mode 100644
index 0000000..d3b567c
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-pic-8.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: grep {leaq f(%rip),} %t1
+; RUN: not grep GOTPCREL %t1
+
+define void ()* @g() {
+entry:
+ ret void ()* @f
+}
+
+declare hidden void @f()
diff --git a/test/CodeGen/X86/x86-64-pic-9.ll b/test/CodeGen/X86/x86-64-pic-9.ll
new file mode 100644
index 0000000..07610313
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-pic-9.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
+; RUN: grep {leaq f(%rip),} %t1
+; RUN: not grep GOTPCREL %t1
+
+define void ()* @g() nounwind {
+entry:
+ ret void ()* @f
+}
+
+define internal void @f() nounwind {
+entry:
+ ret void
+}
diff --git a/test/CodeGen/X86/x86-64-ret0.ll b/test/CodeGen/X86/x86-64-ret0.ll
new file mode 100644
index 0000000..c74f6d8
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-ret0.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=x86-64 | grep mov | count 1
+
+define i32 @f() nounwind {
+ tail call void @t( i32 1 ) nounwind
+ ret i32 0
+}
+
+declare void @t(i32)
diff --git a/test/CodeGen/X86/x86-64-shortint.ll b/test/CodeGen/X86/x86-64-shortint.ll
new file mode 100644
index 0000000..7f96543
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-shortint.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s | grep movswl
+
+target datalayout = "e-p:64:64"
+target triple = "x86_64-apple-darwin8"
+
+
+define void @bar(i16 zeroext %A) {
+ tail call void @foo( i16 %A signext )
+ ret void
+}
+declare void @foo(i16 signext )
+
diff --git a/test/CodeGen/X86/x86-64-sret-return.ll b/test/CodeGen/X86/x86-64-sret-return.ll
new file mode 100644
index 0000000..7b5f189
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-sret-return.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin8"
+ %struct.foo = type { [4 x i64] }
+
+; CHECK: bar:
+; CHECK: movq %rdi, %rax
+define void @bar(%struct.foo* noalias sret %agg.result, %struct.foo* %d) nounwind {
+entry:
+ %d_addr = alloca %struct.foo* ; <%struct.foo**> [#uses=2]
+ %memtmp = alloca %struct.foo, align 8 ; <%struct.foo*> [#uses=1]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ store %struct.foo* %d, %struct.foo** %d_addr
+ %tmp = load %struct.foo** %d_addr, align 8 ; <%struct.foo*> [#uses=1]
+ %tmp1 = getelementptr %struct.foo* %agg.result, i32 0, i32 0 ; <[4 x i64]*> [#uses=4]
+ %tmp2 = getelementptr %struct.foo* %tmp, i32 0, i32 0 ; <[4 x i64]*> [#uses=4]
+ %tmp3 = getelementptr [4 x i64]* %tmp1, i32 0, i32 0 ; <i64*> [#uses=1]
+ %tmp4 = getelementptr [4 x i64]* %tmp2, i32 0, i32 0 ; <i64*> [#uses=1]
+ %tmp5 = load i64* %tmp4, align 8 ; <i64> [#uses=1]
+ store i64 %tmp5, i64* %tmp3, align 8
+ %tmp6 = getelementptr [4 x i64]* %tmp1, i32 0, i32 1 ; <i64*> [#uses=1]
+ %tmp7 = getelementptr [4 x i64]* %tmp2, i32 0, i32 1 ; <i64*> [#uses=1]
+ %tmp8 = load i64* %tmp7, align 8 ; <i64> [#uses=1]
+ store i64 %tmp8, i64* %tmp6, align 8
+ %tmp9 = getelementptr [4 x i64]* %tmp1, i32 0, i32 2 ; <i64*> [#uses=1]
+ %tmp10 = getelementptr [4 x i64]* %tmp2, i32 0, i32 2 ; <i64*> [#uses=1]
+ %tmp11 = load i64* %tmp10, align 8 ; <i64> [#uses=1]
+ store i64 %tmp11, i64* %tmp9, align 8
+ %tmp12 = getelementptr [4 x i64]* %tmp1, i32 0, i32 3 ; <i64*> [#uses=1]
+ %tmp13 = getelementptr [4 x i64]* %tmp2, i32 0, i32 3 ; <i64*> [#uses=1]
+ %tmp14 = load i64* %tmp13, align 8 ; <i64> [#uses=1]
+ store i64 %tmp14, i64* %tmp12, align 8
+ %tmp15 = getelementptr %struct.foo* %memtmp, i32 0, i32 0 ; <[4 x i64]*> [#uses=4]
+ %tmp16 = getelementptr %struct.foo* %agg.result, i32 0, i32 0 ; <[4 x i64]*> [#uses=4]
+ %tmp17 = getelementptr [4 x i64]* %tmp15, i32 0, i32 0 ; <i64*> [#uses=1]
+ %tmp18 = getelementptr [4 x i64]* %tmp16, i32 0, i32 0 ; <i64*> [#uses=1]
+ %tmp19 = load i64* %tmp18, align 8 ; <i64> [#uses=1]
+ store i64 %tmp19, i64* %tmp17, align 8
+ %tmp20 = getelementptr [4 x i64]* %tmp15, i32 0, i32 1 ; <i64*> [#uses=1]
+ %tmp21 = getelementptr [4 x i64]* %tmp16, i32 0, i32 1 ; <i64*> [#uses=1]
+ %tmp22 = load i64* %tmp21, align 8 ; <i64> [#uses=1]
+ store i64 %tmp22, i64* %tmp20, align 8
+ %tmp23 = getelementptr [4 x i64]* %tmp15, i32 0, i32 2 ; <i64*> [#uses=1]
+ %tmp24 = getelementptr [4 x i64]* %tmp16, i32 0, i32 2 ; <i64*> [#uses=1]
+ %tmp25 = load i64* %tmp24, align 8 ; <i64> [#uses=1]
+ store i64 %tmp25, i64* %tmp23, align 8
+ %tmp26 = getelementptr [4 x i64]* %tmp15, i32 0, i32 3 ; <i64*> [#uses=1]
+ %tmp27 = getelementptr [4 x i64]* %tmp16, i32 0, i32 3 ; <i64*> [#uses=1]
+ %tmp28 = load i64* %tmp27, align 8 ; <i64> [#uses=1]
+ store i64 %tmp28, i64* %tmp26, align 8
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+; CHECK: foo:
+; CHECK: movq %rdi, %rax
+define void @foo({ i64 }* noalias nocapture sret %agg.result) nounwind {
+ store { i64 } { i64 0 }, { i64 }* %agg.result
+ ret void
+}
diff --git a/test/CodeGen/X86/x86-64-varargs.ll b/test/CodeGen/X86/x86-64-varargs.ll
new file mode 100644
index 0000000..428f449
--- /dev/null
+++ b/test/CodeGen/X86/x86-64-varargs.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -code-model=large -relocation-model=static | grep call | not grep rax
+
[email protected] = internal constant [26 x i8] c"%d, %f, %d, %lld, %d, %f\0A\00" ; <[26 x i8]*> [#uses=1]
+
+declare i32 @printf(i8*, ...) nounwind
+
+define i32 @main() nounwind {
+entry:
+ %tmp10.i = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([26 x i8]* @.str, i32 0, i64 0), i32 12, double 0x3FF3EB8520000000, i32 120, i64 123456677890, i32 -10, double 4.500000e+15 ) nounwind ; <i32> [#uses=0]
+ ret i32 0
+}
diff --git a/test/CodeGen/X86/x86-frameaddr.ll b/test/CodeGen/X86/x86-frameaddr.ll
new file mode 100644
index 0000000..d595874
--- /dev/null
+++ b/test/CodeGen/X86/x86-frameaddr.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 | grep mov | grep ebp
+
+define i8* @t() nounwind {
+entry:
+ %0 = tail call i8* @llvm.frameaddress(i32 0)
+ ret i8* %0
+}
+
+declare i8* @llvm.frameaddress(i32) nounwind readnone
diff --git a/test/CodeGen/X86/x86-frameaddr2.ll b/test/CodeGen/X86/x86-frameaddr2.ll
new file mode 100644
index 0000000..c509115
--- /dev/null
+++ b/test/CodeGen/X86/x86-frameaddr2.ll
@@ -0,0 +1,9 @@
+; RUN: llc < %s -march=x86 | grep mov | count 3
+
+define i8* @t() nounwind {
+entry:
+ %0 = tail call i8* @llvm.frameaddress(i32 2)
+ ret i8* %0
+}
+
+declare i8* @llvm.frameaddress(i32) nounwind readnone
diff --git a/test/CodeGen/X86/x86-store-gv-addr.ll b/test/CodeGen/X86/x86-store-gv-addr.ll
new file mode 100644
index 0000000..089517a
--- /dev/null
+++ b/test/CodeGen/X86/x86-store-gv-addr.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=static | not grep lea
+; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu -relocation-model=static | not grep lea
+
+@v = external global i32, align 8
+@v_addr = external global i32*, align 8
+
+define void @t() nounwind optsize {
+ store i32* @v, i32** @v_addr, align 8
+ unreachable
+}
diff --git a/test/CodeGen/X86/xmm-r64.ll b/test/CodeGen/X86/xmm-r64.ll
new file mode 100644
index 0000000..2a6b5c7
--- /dev/null
+++ b/test/CodeGen/X86/xmm-r64.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86-64
+
+define <4 x i32> @test() {
+ %tmp1039 = call <4 x i32> @llvm.x86.sse2.psll.d( <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <<4 x i32>> [#uses=1]
+ %tmp1040 = bitcast <4 x i32> %tmp1039 to <2 x i64> ; <<2 x i64>> [#uses=1]
+ %tmp1048 = add <2 x i64> %tmp1040, zeroinitializer ; <<2 x i64>> [#uses=1]
+ %tmp1048.upgrd.1 = bitcast <2 x i64> %tmp1048 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ ret <4 x i32> %tmp1048.upgrd.1
+}
+
+declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>)
+
diff --git a/test/CodeGen/X86/xor-icmp.ll b/test/CodeGen/X86/xor-icmp.ll
new file mode 100644
index 0000000..a6bdb13
--- /dev/null
+++ b/test/CodeGen/X86/xor-icmp.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X64
+
+define i32 @t(i32 %a, i32 %b) nounwind ssp {
+entry:
+; X32: t:
+; X32: xorb
+; X32-NOT: andb
+; X32-NOT: shrb
+; X32: testb $64
+; X32: jne
+
+; X64: t:
+; X64-NOT: setne
+; X64: xorl
+; X64: testb $64
+; X64: jne
+ %0 = and i32 %a, 16384
+ %1 = icmp ne i32 %0, 0
+ %2 = and i32 %b, 16384
+ %3 = icmp ne i32 %2, 0
+ %4 = xor i1 %1, %3
+ br i1 %4, label %bb1, label %bb
+
+bb: ; preds = %entry
+ %5 = tail call i32 (...)* @foo() nounwind ; <i32> [#uses=1]
+ ret i32 %5
+
+bb1: ; preds = %entry
+ %6 = tail call i32 (...)* @bar() nounwind ; <i32> [#uses=1]
+ ret i32 %6
+}
+
+declare i32 @foo(...)
+
+declare i32 @bar(...)
diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll
new file mode 100644
index 0000000..9bfff8a0
--- /dev/null
+++ b/test/CodeGen/X86/xor.ll
@@ -0,0 +1,144 @@
+; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X64
+
+; Though it is undefined, we want xor undef,undef to produce zero.
+define <4 x i32> @test1() nounwind {
+ %tmp = xor <4 x i32> undef, undef
+ ret <4 x i32> %tmp
+
+; X32: test1:
+; X32: xorps %xmm0, %xmm0
+; X32: ret
+}
+
+; Though it is undefined, we want xor undef,undef to produce zero.
+define i32 @test2() nounwind{
+ %tmp = xor i32 undef, undef
+ ret i32 %tmp
+; X32: test2:
+; X32: xorl %eax, %eax
+; X32: ret
+}
+
+define i32 @test3(i32 %a, i32 %b) nounwind {
+entry:
+ %tmp1not = xor i32 %b, -2
+ %tmp3 = and i32 %tmp1not, %a
+ %tmp4 = lshr i32 %tmp3, 1
+ ret i32 %tmp4
+
+; X64: test3:
+; X64: notl %esi
+; X64: andl %edi, %esi
+; X64: movl %esi, %eax
+; X64: shrl %eax
+; X64: ret
+
+; X32: test3:
+; X32: movl 8(%esp), %eax
+; X32: notl %eax
+; X32: andl 4(%esp), %eax
+; X32: shrl %eax
+; X32: ret
+}
+
+define i32 @test4(i32 %a, i32 %b) nounwind {
+entry:
+ br label %bb
+bb:
+ %b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
+ %a_addr.0 = phi i32 [ %a, %entry ], [ %tmp3, %bb ]
+ %tmp3 = xor i32 %a_addr.0, %b_addr.0
+ %tmp4not = xor i32 %tmp3, 2147483647
+ %tmp6 = and i32 %tmp4not, %b_addr.0
+ %tmp8 = shl i32 %tmp6, 1
+ %tmp10 = icmp eq i32 %tmp8, 0
+ br i1 %tmp10, label %bb12, label %bb
+bb12:
+ ret i32 %tmp3
+
+; X64: test4:
+; X64: notl [[REG:%[a-z]+]]
+; X64: andl {{.*}}[[REG]]
+; X32: test4:
+; X32: notl [[REG:%[a-z]+]]
+; X32: andl {{.*}}[[REG]]
+}
+
+define i16 @test5(i16 %a, i16 %b) nounwind {
+entry:
+ br label %bb
+bb:
+ %b_addr.0 = phi i16 [ %b, %entry ], [ %tmp8, %bb ]
+ %a_addr.0 = phi i16 [ %a, %entry ], [ %tmp3, %bb ]
+ %tmp3 = xor i16 %a_addr.0, %b_addr.0
+ %tmp4not = xor i16 %tmp3, 32767
+ %tmp6 = and i16 %tmp4not, %b_addr.0
+ %tmp8 = shl i16 %tmp6, 1
+ %tmp10 = icmp eq i16 %tmp8, 0
+ br i1 %tmp10, label %bb12, label %bb
+bb12:
+ ret i16 %tmp3
+; X64: test5:
+; X64: notw [[REG:%[a-z]+]]
+; X64: andw {{.*}}[[REG]]
+; X32: test5:
+; X32: notw [[REG:%[a-z]+]]
+; X32: andw {{.*}}[[REG]]
+}
+
+define i8 @test6(i8 %a, i8 %b) nounwind {
+entry:
+ br label %bb
+bb:
+ %b_addr.0 = phi i8 [ %b, %entry ], [ %tmp8, %bb ]
+ %a_addr.0 = phi i8 [ %a, %entry ], [ %tmp3, %bb ]
+ %tmp3 = xor i8 %a_addr.0, %b_addr.0
+ %tmp4not = xor i8 %tmp3, 127
+ %tmp6 = and i8 %tmp4not, %b_addr.0
+ %tmp8 = shl i8 %tmp6, 1
+ %tmp10 = icmp eq i8 %tmp8, 0
+ br i1 %tmp10, label %bb12, label %bb
+bb12:
+ ret i8 %tmp3
+; X64: test6:
+; X64: notb [[REG:%[a-z]+]]
+; X64: andb {{.*}}[[REG]]
+; X32: test6:
+; X32: notb [[REG:%[a-z]+]]
+; X32: andb {{.*}}[[REG]]
+}
+
+define i32 @test7(i32 %a, i32 %b) nounwind {
+entry:
+ br label %bb
+bb:
+ %b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
+ %a_addr.0 = phi i32 [ %a, %entry ], [ %tmp3, %bb ]
+ %tmp3 = xor i32 %a_addr.0, %b_addr.0
+ %tmp4not = xor i32 %tmp3, 2147483646
+ %tmp6 = and i32 %tmp4not, %b_addr.0
+ %tmp8 = shl i32 %tmp6, 1
+ %tmp10 = icmp eq i32 %tmp8, 0
+ br i1 %tmp10, label %bb12, label %bb
+bb12:
+ ret i32 %tmp3
+; X64: test7:
+; X64: xorl $2147483646, [[REG:%[a-z]+]]
+; X64: andl {{.*}}[[REG]]
+; X32: test7:
+; X32: xorl $2147483646, [[REG:%[a-z]+]]
+; X32: andl {{.*}}[[REG]]
+}
+
+define i32 @test8(i32 %a) nounwind {
+; rdar://7553032
+entry:
+ %t1 = sub i32 0, %a
+ %t2 = add i32 %t1, -1
+ ret i32 %t2
+; X64: test8:
+; X64: notl %eax
+; X32: test8:
+; X32: notl %eax
+}
diff --git a/test/CodeGen/X86/zero-remat.ll b/test/CodeGen/X86/zero-remat.ll
new file mode 100644
index 0000000..3e3bb95d
--- /dev/null
+++ b/test/CodeGen/X86/zero-remat.ll
@@ -0,0 +1,40 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc < %s -march=x86-64 -stats -info-output-file - | grep asm-printer | grep 12
+; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32
+
+declare void @bar(double %x)
+declare void @barf(float %x)
+
+define double @foo() nounwind {
+
+ call void @bar(double 0.0)
+ ret double 0.0
+
+;CHECK-32: foo:
+;CHECK-32: call
+;CHECK-32: fldz
+;CHECK-32: ret
+
+;CHECK-64: foo:
+;CHECK-64: pxor
+;CHECK-64: call
+;CHECK-64: pxor
+;CHECK-64: ret
+}
+
+
+define float @foof() nounwind {
+ call void @barf(float 0.0)
+ ret float 0.0
+
+;CHECK-32: foof:
+;CHECK-32: call
+;CHECK-32: fldz
+;CHECK-32: ret
+
+;CHECK-64: foof:
+;CHECK-64: pxor
+;CHECK-64: call
+;CHECK-64: pxor
+;CHECK-64: ret
+}
diff --git a/test/CodeGen/X86/zext-inreg-0.ll b/test/CodeGen/X86/zext-inreg-0.ll
new file mode 100644
index 0000000..ae6221a
--- /dev/null
+++ b/test/CodeGen/X86/zext-inreg-0.ll
@@ -0,0 +1,66 @@
+; RUN: llc < %s -march=x86 | not grep and
+; RUN: llc < %s -march=x86-64 > %t
+; RUN: not grep and %t
+; RUN: not grep movzbq %t
+; RUN: not grep movzwq %t
+; RUN: not grep movzlq %t
+
+; These should use movzbl instead of 'and 255'.
+; This related to not having a ZERO_EXTEND_REG opcode.
+
+define i32 @a(i32 %d) nounwind {
+ %e = add i32 %d, 1
+ %retval = and i32 %e, 255
+ ret i32 %retval
+}
+define i32 @b(float %d) nounwind {
+ %tmp12 = fptoui float %d to i8
+ %retval = zext i8 %tmp12 to i32
+ ret i32 %retval
+}
+define i32 @c(i32 %d) nounwind {
+ %e = add i32 %d, 1
+ %retval = and i32 %e, 65535
+ ret i32 %retval
+}
+define i64 @d(i64 %d) nounwind {
+ %e = add i64 %d, 1
+ %retval = and i64 %e, 255
+ ret i64 %retval
+}
+define i64 @e(i64 %d) nounwind {
+ %e = add i64 %d, 1
+ %retval = and i64 %e, 65535
+ ret i64 %retval
+}
+define i64 @f(i64 %d) nounwind {
+ %e = add i64 %d, 1
+ %retval = and i64 %e, 4294967295
+ ret i64 %retval
+}
+
+define i32 @g(i8 %d) nounwind {
+ %e = add i8 %d, 1
+ %retval = zext i8 %e to i32
+ ret i32 %retval
+}
+define i32 @h(i16 %d) nounwind {
+ %e = add i16 %d, 1
+ %retval = zext i16 %e to i32
+ ret i32 %retval
+}
+define i64 @i(i8 %d) nounwind {
+ %e = add i8 %d, 1
+ %retval = zext i8 %e to i64
+ ret i64 %retval
+}
+define i64 @j(i16 %d) nounwind {
+ %e = add i16 %d, 1
+ %retval = zext i16 %e to i64
+ ret i64 %retval
+}
+define i64 @k(i32 %d) nounwind {
+ %e = add i32 %d, 1
+ %retval = zext i32 %e to i64
+ ret i64 %retval
+}
diff --git a/test/CodeGen/X86/zext-inreg-1.ll b/test/CodeGen/X86/zext-inreg-1.ll
new file mode 100644
index 0000000..17fe374
--- /dev/null
+++ b/test/CodeGen/X86/zext-inreg-1.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=x86 | not grep and
+
+; These tests differ from the ones in zext-inreg-0.ll in that
+; on x86-64 they do require and instructions.
+
+; These should use movzbl instead of 'and 255'.
+; This related to not having ZERO_EXTEND_REG node.
+
+define i64 @l(i64 %d) nounwind {
+ %e = add i64 %d, 1
+ %retval = and i64 %e, 1099511627775
+ ret i64 %retval
+}
+define i64 @m(i64 %d) nounwind {
+ %e = add i64 %d, 1
+ %retval = and i64 %e, 281474976710655
+ ret i64 %retval
+}
diff --git a/test/CodeGen/X86/zext-shl.ll b/test/CodeGen/X86/zext-shl.ll
new file mode 100644
index 0000000..928848e
--- /dev/null
+++ b/test/CodeGen/X86/zext-shl.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=x86 | FileCheck %s
+
+define i32 @t1(i8 zeroext %x) nounwind readnone ssp {
+entry:
+; CHECK: t1:
+; CHECK: shll
+; CHECK-NOT: movzwl
+; CHECK: ret
+ %0 = zext i8 %x to i16
+ %1 = shl i16 %0, 5
+ %2 = zext i16 %1 to i32
+ ret i32 %2
+}
+
+define i32 @t2(i8 zeroext %x) nounwind readnone ssp {
+entry:
+; CHECK: t2:
+; CHECK: shrl
+; CHECK-NOT: movzwl
+; CHECK: ret
+ %0 = zext i8 %x to i16
+ %1 = lshr i16 %0, 3
+ %2 = zext i16 %1 to i32
+ ret i32 %2
+}
diff --git a/test/CodeGen/X86/zext-trunc.ll b/test/CodeGen/X86/zext-trunc.ll
new file mode 100644
index 0000000..b9ffbe8
--- /dev/null
+++ b/test/CodeGen/X86/zext-trunc.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+; rdar://7570931
+
+define i64 @foo(i64 %a, i64 %b) nounwind {
+; CHECK: foo:
+; CHECK: leal
+; CHECK-NOT: movl
+; CHECK: ret
+ %c = add i64 %a, %b
+ %d = trunc i64 %c to i32
+ %e = zext i32 %d to i64
+ ret i64 %e
+}
diff --git a/test/CodeGen/XCore/2008-11-17-Shl64.ll b/test/CodeGen/XCore/2008-11-17-Shl64.ll
new file mode 100644
index 0000000..04b1b5a
--- /dev/null
+++ b/test/CodeGen/XCore/2008-11-17-Shl64.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; PR3080
+define i64 @test(i64 %a) {
+ %result = shl i64 %a, 1
+ ret i64 %result
+}
diff --git a/test/CodeGen/XCore/2009-01-08-Crash.ll b/test/CodeGen/XCore/2009-01-08-Crash.ll
new file mode 100644
index 0000000..a31ea1e2
--- /dev/null
+++ b/test/CodeGen/XCore/2009-01-08-Crash.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=xcore > %t1.s
+;; This caused a compilation failure since the
+;; address arithmetic was folded into the LDWSP instruction,
+;; resulting in a negative offset which eliminateFrameIndex was
+;; unable to eliminate.
+define i32 @test(i32 %bar) nounwind readnone {
+entry:
+ %bar_addr = alloca i32
+ %0 = getelementptr i32* %bar_addr, i32 -1
+ %1 = load i32* %0, align 4
+ ret i32 %1
+}
diff --git a/test/CodeGen/XCore/2009-01-14-Remat-Crash.ll b/test/CodeGen/XCore/2009-01-14-Remat-Crash.ll
new file mode 100644
index 0000000..b2bbcb1
--- /dev/null
+++ b/test/CodeGen/XCore/2009-01-14-Remat-Crash.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; PR3324
+define double @f1(double %a, double %b, double %c, double %d, double %e, double %f, double %g) nounwind {
+entry:
+ br i1 false, label %bb113, label %bb129
+
+bb113: ; preds = %entry
+ ret double 0.000000e+00
+
+bb129: ; preds = %entry
+ %tmp134 = fsub double %b, %a ; <double> [#uses=1]
+ %tmp136 = fsub double %tmp134, %c ; <double> [#uses=1]
+ %tmp138 = fadd double %tmp136, %d ; <double> [#uses=1]
+ %tmp140 = fsub double %tmp138, %e ; <double> [#uses=1]
+ %tmp142 = fadd double %tmp140, %f ; <double> [#uses=1]
+ %tmp.0 = fmul double %tmp142, 0.000000e+00 ; <double> [#uses=1]
+ ret double %tmp.0
+}
diff --git a/test/CodeGen/XCore/2009-03-27-v2f64-param.ll b/test/CodeGen/XCore/2009-03-27-v2f64-param.ll
new file mode 100644
index 0000000..e35a36a
--- /dev/null
+++ b/test/CodeGen/XCore/2009-03-27-v2f64-param.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=xcore
+; PR3898
+
+define i32 @vector_param(<2 x double> %x) nounwind {
+ ret i32 1
+}
diff --git a/test/CodeGen/XCore/2009-07-15-store192.ll b/test/CodeGen/XCore/2009-07-15-store192.ll
new file mode 100644
index 0000000..5278af8
--- /dev/null
+++ b/test/CodeGen/XCore/2009-07-15-store192.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=xcore > %t1.s
+define void @store32(i8* %p) nounwind {
+entry:
+ %0 = bitcast i8* %p to i192*
+ store i192 0, i192* %0, align 4
+ ret void
+}
diff --git a/test/CodeGen/XCore/addsub64.ll b/test/CodeGen/XCore/addsub64.ll
new file mode 100644
index 0000000..a1494ad
--- /dev/null
+++ b/test/CodeGen/XCore/addsub64.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=xcore -mcpu=xs1b-generic > %t1.s
+; RUN: grep ladd %t1.s | count 2
+; RUN: grep lsub %t1.s | count 2
+define i64 @add64(i64 %a, i64 %b) {
+ %result = add i64 %a, %b
+ ret i64 %result
+}
+
+define i64 @sub64(i64 %a, i64 %b) {
+ %result = sub i64 %a, %b
+ ret i64 %result
+}
diff --git a/test/CodeGen/XCore/ashr.ll b/test/CodeGen/XCore/ashr.ll
new file mode 100644
index 0000000..d99808f
--- /dev/null
+++ b/test/CodeGen/XCore/ashr.ll
@@ -0,0 +1,76 @@
+; RUN: llc < %s -march=xcore -asm-verbose=0 | FileCheck %s
+define i32 @ashr(i32 %a, i32 %b) {
+ %1 = ashr i32 %a, %b
+ ret i32 %1
+}
+; CHECK: ashr:
+; CHECK-NEXT: ashr r0, r0, r1
+
+define i32 @ashri1(i32 %a) {
+ %1 = ashr i32 %a, 24
+ ret i32 %1
+}
+; CHECK: ashri1:
+; CHECK-NEXT: ashr r0, r0, 24
+
+define i32 @ashri2(i32 %a) {
+ %1 = ashr i32 %a, 31
+ ret i32 %1
+}
+; CHECK: ashri2:
+; CHECK-NEXT: ashr r0, r0, 32
+
+define i32 @f1(i32 %a) {
+ %1 = icmp slt i32 %a, 0
+ br i1 %1, label %less, label %not_less
+less:
+ ret i32 10
+not_less:
+ ret i32 17
+}
+; CHECK: f1:
+; CHECK-NEXT: ashr r0, r0, 32
+; CHECK-NEXT: bf r0
+
+define i32 @f2(i32 %a) {
+ %1 = icmp sge i32 %a, 0
+ br i1 %1, label %greater, label %not_greater
+greater:
+ ret i32 10
+not_greater:
+ ret i32 17
+}
+; CHECK: f2:
+; CHECK-NEXT: ashr r0, r0, 32
+; CHECK-NEXT: bt r0
+
+define i32 @f3(i32 %a) {
+ %1 = icmp slt i32 %a, 0
+ %2 = select i1 %1, i32 10, i32 17
+ ret i32 %2
+}
+; CHECK: f3:
+; CHECK-NEXT: ashr r1, r0, 32
+; CHECK-NEXT: ldc r0, 10
+; CHECK-NEXT: bt r1
+; CHECK: ldc r0, 17
+
+define i32 @f4(i32 %a) {
+ %1 = icmp sge i32 %a, 0
+ %2 = select i1 %1, i32 10, i32 17
+ ret i32 %2
+}
+; CHECK: f4:
+; CHECK-NEXT: ashr r1, r0, 32
+; CHECK-NEXT: ldc r0, 17
+; CHECK-NEXT: bt r1
+; CHECK: ldc r0, 10
+
+define i32 @f5(i32 %a) {
+ %1 = icmp sge i32 %a, 0
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+; CHECK: f5:
+; CHECK-NEXT: ashr r0, r0, 32
+; CHECK-NEXT: eq r0, r0, 0
diff --git a/test/CodeGen/XCore/basictest.ll b/test/CodeGen/XCore/basictest.ll
new file mode 100644
index 0000000..de5eaff
--- /dev/null
+++ b/test/CodeGen/XCore/basictest.ll
@@ -0,0 +1,6 @@
+; RUN: llc < %s -march=xcore
+
+define i32 @test(i32 %X) {
+ %tmp.1 = add i32 %X, 1
+ ret i32 %tmp.1
+}
diff --git a/test/CodeGen/XCore/bigstructret.ll b/test/CodeGen/XCore/bigstructret.ll
new file mode 100644
index 0000000..56af930
--- /dev/null
+++ b/test/CodeGen/XCore/bigstructret.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+
+%0 = type { i32, i32, i32, i32 }
+%1 = type { i32, i32, i32, i32, i32 }
+
+; Structs of 4 words can be returned in registers
+define internal fastcc %0 @ReturnBigStruct() nounwind readnone {
+entry:
+ %0 = insertvalue %0 zeroinitializer, i32 12, 0
+ %1 = insertvalue %0 %0, i32 24, 1
+ %2 = insertvalue %0 %1, i32 48, 2
+ %3 = insertvalue %0 %2, i32 24601, 3
+ ret %0 %3
+}
+; CHECK: ReturnBigStruct:
+; CHECK: ldc r0, 12
+; CHECK: ldc r1, 24
+; CHECK: ldc r2, 48
+; CHECK: ldc r3, 24601
+; CHECK: retsp 0
+
+; Structs bigger than 4 words are returned via a hidden hidden sret-parameter
+define internal fastcc %1 @ReturnBigStruct2() nounwind readnone {
+entry:
+ %0 = insertvalue %1 zeroinitializer, i32 12, 0
+ %1 = insertvalue %1 %0, i32 24, 1
+ %2 = insertvalue %1 %1, i32 48, 2
+ %3 = insertvalue %1 %2, i32 24601, 3
+ %4 = insertvalue %1 %3, i32 4321, 4
+ ret %1 %4
+}
+; CHECK: ReturnBigStruct2:
+; CHECK: ldc r1, 4321
+; CHECK: stw r1, r0[4]
+; CHECK: ldc r1, 24601
+; CHECK: stw r1, r0[3]
+; CHECK: ldc r1, 48
+; CHECK: stw r1, r0[2]
+; CHECK: ldc r1, 24
+; CHECK: stw r1, r0[1]
+; CHECK: ldc r1, 12
+; CHECK: stw r1, r0[0]
+; CHECK: retsp 0
diff --git a/test/CodeGen/XCore/bitrev.ll b/test/CodeGen/XCore/bitrev.ll
new file mode 100644
index 0000000..09202d3
--- /dev/null
+++ b/test/CodeGen/XCore/bitrev.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep bitrev %t1.s | count 1
+declare i32 @llvm.xcore.bitrev(i32)
+
+define i32 @test(i32 %val) {
+ %result = call i32 @llvm.xcore.bitrev(i32 %val)
+ ret i32 %result
+}
diff --git a/test/CodeGen/XCore/constants.ll b/test/CodeGen/XCore/constants.ll
new file mode 100644
index 0000000..95fa11e
--- /dev/null
+++ b/test/CodeGen/XCore/constants.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=xcore -mcpu=xs1b-generic | FileCheck %s
+
+; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4
+; CHECK: .LCPI1_0:
+; CHECK: .long 12345678
+; CHECK: f:
+; CHECK: ldw r0, cp[.LCPI1_0]
+define i32 @f() {
+entry:
+ ret i32 12345678
+}
diff --git a/test/CodeGen/XCore/cos.ll b/test/CodeGen/XCore/cos.ll
new file mode 100644
index 0000000..8211f85
--- /dev/null
+++ b/test/CodeGen/XCore/cos.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "bl cosf" %t1.s | count 1
+; RUN: grep "bl cos" %t1.s | count 2
+declare double @llvm.cos.f64(double)
+
+define double @test(double %F) {
+ %result = call double @llvm.cos.f64(double %F)
+ ret double %result
+}
+
+declare float @llvm.cos.f32(float)
+
+define float @testf(float %F) {
+ %result = call float @llvm.cos.f32(float %F)
+ ret float %result
+}
diff --git a/test/CodeGen/XCore/dg.exp b/test/CodeGen/XCore/dg.exp
new file mode 100644
index 0000000..7110eab
--- /dev/null
+++ b/test/CodeGen/XCore/dg.exp
@@ -0,0 +1,5 @@
+load_lib llvm.exp
+
+if { [llvm_supports_target XCore] } {
+ RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
+}
diff --git a/test/CodeGen/XCore/exp.ll b/test/CodeGen/XCore/exp.ll
new file mode 100644
index 0000000..d23d484
--- /dev/null
+++ b/test/CodeGen/XCore/exp.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "bl expf" %t1.s | count 1
+; RUN: grep "bl exp" %t1.s | count 2
+declare double @llvm.exp.f64(double)
+
+define double @test(double %F) {
+ %result = call double @llvm.exp.f64(double %F)
+ ret double %result
+}
+
+declare float @llvm.exp.f32(float)
+
+define float @testf(float %F) {
+ %result = call float @llvm.exp.f32(float %F)
+ ret float %result
+}
diff --git a/test/CodeGen/XCore/exp2.ll b/test/CodeGen/XCore/exp2.ll
new file mode 100644
index 0000000..4c4d17f
--- /dev/null
+++ b/test/CodeGen/XCore/exp2.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "bl exp2f" %t1.s | count 1
+; RUN: grep "bl exp2" %t1.s | count 2
+declare double @llvm.exp2.f64(double)
+
+define double @test(double %F) {
+ %result = call double @llvm.exp2.f64(double %F)
+ ret double %result
+}
+
+declare float @llvm.exp2.f32(float)
+
+define float @testf(float %F) {
+ %result = call float @llvm.exp2.f32(float %F)
+ ret float %result
+}
diff --git a/test/CodeGen/XCore/fneg.ll b/test/CodeGen/XCore/fneg.ll
new file mode 100644
index 0000000..e3dd3dd
--- /dev/null
+++ b/test/CodeGen/XCore/fneg.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=xcore | grep "xor" | count 1
+define i1 @test(double %F) nounwind {
+entry:
+ %0 = fsub double -0.000000e+00, %F
+ %1 = fcmp olt double 0.000000e+00, %0
+ ret i1 %1
+}
diff --git a/test/CodeGen/XCore/getid.ll b/test/CodeGen/XCore/getid.ll
new file mode 100644
index 0000000..ecab65c
--- /dev/null
+++ b/test/CodeGen/XCore/getid.ll
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "get r11, id" %t1.s | count 1
+declare i32 @llvm.xcore.getid()
+
+define i32 @test() {
+ %result = call i32 @llvm.xcore.getid()
+ ret i32 %result
+}
diff --git a/test/CodeGen/XCore/globals.ll b/test/CodeGen/XCore/globals.ll
new file mode 100644
index 0000000..342e5932
--- /dev/null
+++ b/test/CodeGen/XCore/globals.ll
@@ -0,0 +1,92 @@
+; RUN: llc < %s -march=xcore -mcpu=xs1b-generic | FileCheck %s
+
+define i32 *@addr_G1() {
+entry:
+; CHECK: addr_G1:
+; CHECK: ldaw r0, dp[G1]
+ ret i32* @G1
+}
+
+define i32 *@addr_G2() {
+entry:
+; CHECK: addr_G2:
+; CHECK: ldaw r0, dp[G2]
+ ret i32* @G2
+}
+
+define i32 *@addr_G3() {
+entry:
+; CHECK: addr_G3:
+; CHECK: ldaw r11, cp[G3]
+; CHECK: mov r0, r11
+ ret i32* @G3
+}
+
+define i32 **@addr_G4() {
+entry:
+; CHECK: addr_G4:
+; CHECK: ldaw r0, dp[G4]
+ ret i32** @G4
+}
+
+define i32 **@addr_G5() {
+entry:
+; CHECK: addr_G5:
+; CHECK: ldaw r11, cp[G5]
+; CHECK: mov r0, r11
+ ret i32** @G5
+}
+
+define i32 **@addr_G6() {
+entry:
+; CHECK: addr_G6:
+; CHECK: ldaw r0, dp[G6]
+ ret i32** @G6
+}
+
+define i32 **@addr_G7() {
+entry:
+; CHECK: addr_G7:
+; CHECK: ldaw r11, cp[G7]
+; CHECK: mov r0, r11
+ ret i32** @G7
+}
+
+define i32 *@addr_G8() {
+entry:
+; CHECK: addr_G8:
+; CHECK: ldaw r0, dp[G8]
+ ret i32* @G8
+}
+
+@G1 = global i32 4712
+; CHECK: .section .dp.data,"awd",@progbits
+; CHECK: G1:
+
+@G2 = global i32 0
+; CHECK: .section .dp.bss,"awd",@nobits
+; CHECK: G2:
+
+@G3 = constant i32 9401
+; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4
+; CHECK: G3:
+
+@G4 = global i32* @G1
+; CHECK: .section .dp.data,"awd",@progbits
+; CHECK: G4:
+
+@G5 = constant i32* @G1
+; CHECK: .section .cp.rodata,"ac",@progbits
+; CHECK: G5:
+
+@G6 = global i32* @G8
+; CHECK: .section .dp.data,"awd",@progbits
+; CHECK: G6:
+
+@G7 = constant i32* @G8
+; CHECK: .section .cp.rodata,"ac",@progbits
+; CHECK: G7:
+
+@G8 = internal global i32 9312
+; CHECK: .section .dp.data,"awd",@progbits
+; CHECK: G8:
diff --git a/test/CodeGen/XCore/indirectbr.ll b/test/CodeGen/XCore/indirectbr.ll
new file mode 100644
index 0000000..a8f00cc
--- /dev/null
+++ b/test/CodeGen/XCore/indirectbr.ll
@@ -0,0 +1,45 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+
+@nextaddr = global i8* null ; <i8**> [#uses=2]
[email protected] = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
+
+define internal i32 @foo(i32 %i) nounwind {
+; CHECK: foo:
+entry:
+ %0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2]
+ %1 = icmp eq i8* %0, null ; <i1> [#uses=1]
+ br i1 %1, label %bb3, label %bb2
+
+bb2: ; preds = %entry, %bb3
+ %gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1]
+; CHECK: bau
+ indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
+
+bb3: ; preds = %entry
+ %2 = getelementptr inbounds [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1]
+ %gotovar.4.0.pre = load i8** %2, align 4 ; <i8*> [#uses=1]
+ br label %bb2
+
+L5: ; preds = %bb2
+ br label %L4
+
+L4: ; preds = %L5, %bb2
+ %res.0 = phi i32 [ 385, %L5 ], [ 35, %bb2 ] ; <i32> [#uses=1]
+ br label %L3
+
+L3: ; preds = %L4, %bb2
+ %res.1 = phi i32 [ %res.0, %L4 ], [ 5, %bb2 ] ; <i32> [#uses=1]
+ br label %L2
+
+L2: ; preds = %L3, %bb2
+ %res.2 = phi i32 [ %res.1, %L3 ], [ 1, %bb2 ] ; <i32> [#uses=1]
+ %phitmp = mul i32 %res.2, 6 ; <i32> [#uses=1]
+ br label %L1
+
+L1: ; preds = %L2, %bb2
+ %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1]
+; CHECK: ldap r11, .LBA3_foo_L5
+; CHECK: stw r11, dp[nextaddr]
+ store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
+ ret i32 %res.3
+}
diff --git a/test/CodeGen/XCore/load.ll b/test/CodeGen/XCore/load.ll
new file mode 100644
index 0000000..adfea21
--- /dev/null
+++ b/test/CodeGen/XCore/load.ll
@@ -0,0 +1,39 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: not grep add %t1.s
+; RUN: not grep ldaw %t1.s
+; RUN: not grep lda16 %t1.s
+; RUN: not grep zext %t1.s
+; RUN: not grep sext %t1.s
+; RUN: grep "ldw" %t1.s | count 2
+; RUN: grep "ld16s" %t1.s | count 1
+; RUN: grep "ld8u" %t1.s | count 1
+
+define i32 @load32(i32* %p, i32 %offset) nounwind {
+entry:
+ %0 = getelementptr i32* %p, i32 %offset
+ %1 = load i32* %0, align 4
+ ret i32 %1
+}
+
+define i32 @load32_imm(i32* %p) nounwind {
+entry:
+ %0 = getelementptr i32* %p, i32 11
+ %1 = load i32* %0, align 4
+ ret i32 %1
+}
+
+define i32 @load16(i16* %p, i32 %offset) nounwind {
+entry:
+ %0 = getelementptr i16* %p, i32 %offset
+ %1 = load i16* %0, align 2
+ %2 = sext i16 %1 to i32
+ ret i32 %2
+}
+
+define i32 @load8(i8* %p, i32 %offset) nounwind {
+entry:
+ %0 = getelementptr i8* %p, i32 %offset
+ %1 = load i8* %0, align 1
+ %2 = zext i8 %1 to i32
+ ret i32 %2
+}
diff --git a/test/CodeGen/XCore/log.ll b/test/CodeGen/XCore/log.ll
new file mode 100644
index 0000000..a08471f
--- /dev/null
+++ b/test/CodeGen/XCore/log.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "bl logf" %t1.s | count 1
+; RUN: grep "bl log" %t1.s | count 2
+declare double @llvm.log.f64(double)
+
+define double @test(double %F) {
+ %result = call double @llvm.log.f64(double %F)
+ ret double %result
+}
+
+declare float @llvm.log.f32(float)
+
+define float @testf(float %F) {
+ %result = call float @llvm.log.f32(float %F)
+ ret float %result
+}
diff --git a/test/CodeGen/XCore/log10.ll b/test/CodeGen/XCore/log10.ll
new file mode 100644
index 0000000..a72b8bf
--- /dev/null
+++ b/test/CodeGen/XCore/log10.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "bl log10f" %t1.s | count 1
+; RUN: grep "bl log10" %t1.s | count 2
+declare double @llvm.log10.f64(double)
+
+define double @test(double %F) {
+ %result = call double @llvm.log10.f64(double %F)
+ ret double %result
+}
+
+declare float @llvm.log10.f32(float)
+
+define float @testf(float %F) {
+ %result = call float @llvm.log10.f32(float %F)
+ ret float %result
+}
diff --git a/test/CodeGen/XCore/log2.ll b/test/CodeGen/XCore/log2.ll
new file mode 100644
index 0000000..d257433
--- /dev/null
+++ b/test/CodeGen/XCore/log2.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "bl log2f" %t1.s | count 1
+; RUN: grep "bl log2" %t1.s | count 2
+declare double @llvm.log2.f64(double)
+
+define double @test(double %F) {
+ %result = call double @llvm.log2.f64(double %F)
+ ret double %result
+}
+
+declare float @llvm.log2.f32(float)
+
+define float @testf(float %F) {
+ %result = call float @llvm.log2.f32(float %F)
+ ret float %result
+}
diff --git a/test/CodeGen/XCore/pow.ll b/test/CodeGen/XCore/pow.ll
new file mode 100644
index 0000000..b461185
--- /dev/null
+++ b/test/CodeGen/XCore/pow.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "bl powf" %t1.s | count 1
+; RUN: grep "bl pow" %t1.s | count 2
+declare double @llvm.pow.f64(double, double)
+
+define double @test(double %F, double %power) {
+ %result = call double @llvm.pow.f64(double %F, double %power)
+ ret double %result
+}
+
+declare float @llvm.pow.f32(float, float)
+
+define float @testf(float %F, float %power) {
+ %result = call float @llvm.pow.f32(float %F, float %power)
+ ret float %result
+}
diff --git a/test/CodeGen/XCore/powi.ll b/test/CodeGen/XCore/powi.ll
new file mode 100644
index 0000000..de31cbe
--- /dev/null
+++ b/test/CodeGen/XCore/powi.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "bl __powidf2" %t1.s | count 1
+; RUN: grep "bl __powisf2" %t1.s | count 1
+declare double @llvm.powi.f64(double, i32)
+
+define double @test(double %F, i32 %power) {
+ %result = call double @llvm.powi.f64(double %F, i32 %power)
+ ret double %result
+}
+
+declare float @llvm.powi.f32(float, i32)
+
+define float @testf(float %F, i32 %power) {
+ %result = call float @llvm.powi.f32(float %F, i32 %power)
+ ret float %result
+}
diff --git a/test/CodeGen/XCore/private.ll b/test/CodeGen/XCore/private.ll
new file mode 100644
index 0000000..c595a6df
--- /dev/null
+++ b/test/CodeGen/XCore/private.ll
@@ -0,0 +1,21 @@
+; Test to make sure that the 'private' is used correctly.
+;
+; RUN: llc < %s -march=xcore > %t
+; RUN: grep .Lfoo: %t
+; RUN: grep bl.*\.Lfoo %t
+; RUN: grep .Lbaz: %t
+; RUN: grep ldw.*\.Lbaz %t
+
+declare void @foo()
+
+define private void @foo() {
+ ret void
+}
+
+@baz = private global i32 4
+
+define i32 @bar() {
+ call void @foo()
+ %1 = load i32* @baz, align 4
+ ret i32 %1
+}
diff --git a/test/CodeGen/XCore/sext.ll b/test/CodeGen/XCore/sext.ll
new file mode 100644
index 0000000..9cd4ad6
--- /dev/null
+++ b/test/CodeGen/XCore/sext.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+define i32 @sext1(i32 %a) {
+ %1 = trunc i32 %a to i1
+ %2 = sext i1 %1 to i32
+ ret i32 %2
+}
+; CHECK: sext1:
+; CHECK: sext r0, 1
+
+define i32 @sext2(i32 %a) {
+ %1 = trunc i32 %a to i2
+ %2 = sext i2 %1 to i32
+ ret i32 %2
+}
+; CHECK: sext2:
+; CHECK: sext r0, 2
+
+define i32 @sext8(i32 %a) {
+ %1 = trunc i32 %a to i8
+ %2 = sext i8 %1 to i32
+ ret i32 %2
+}
+; CHECK: sext8:
+; CHECK: sext r0, 8
+
+define i32 @sext16(i32 %a) {
+ %1 = trunc i32 %a to i16
+ %2 = sext i16 %1 to i32
+ ret i32 %2
+}
+; CHECK: sext16:
+; CHECK: sext r0, 16
diff --git a/test/CodeGen/XCore/sin.ll b/test/CodeGen/XCore/sin.ll
new file mode 100644
index 0000000..ced026f
--- /dev/null
+++ b/test/CodeGen/XCore/sin.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "bl sinf" %t1.s | count 1
+; RUN: grep "bl sin" %t1.s | count 2
+declare double @llvm.sin.f64(double)
+
+define double @test(double %F) {
+ %result = call double @llvm.sin.f64(double %F)
+ ret double %result
+}
+
+declare float @llvm.sin.f32(float)
+
+define float @testf(float %F) {
+ %result = call float @llvm.sin.f32(float %F)
+ ret float %result
+}
diff --git a/test/CodeGen/XCore/sqrt.ll b/test/CodeGen/XCore/sqrt.ll
new file mode 100644
index 0000000..364d1a1
--- /dev/null
+++ b/test/CodeGen/XCore/sqrt.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "bl sqrtf" %t1.s | count 1
+; RUN: grep "bl sqrt" %t1.s | count 2
+declare double @llvm.sqrt.f64(double)
+
+define double @test(double %F) {
+ %result = call double @llvm.sqrt.f64(double %F)
+ ret double %result
+}
+
+declare float @llvm.sqrt.f32(float)
+
+define float @testf(float %F) {
+ %result = call float @llvm.sqrt.f32(float %F)
+ ret float %result
+}
diff --git a/test/CodeGen/XCore/store.ll b/test/CodeGen/XCore/store.ll
new file mode 100644
index 0000000..2213743
--- /dev/null
+++ b/test/CodeGen/XCore/store.ll
@@ -0,0 +1,35 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: not grep add %t1.s
+; RUN: not grep ldaw %t1.s
+; RUN: not grep lda16 %t1.s
+; RUN: grep "stw" %t1.s | count 2
+; RUN: grep "st16" %t1.s | count 1
+; RUN: grep "st8" %t1.s | count 1
+
+define void @store32(i32* %p, i32 %offset, i32 %val) nounwind {
+entry:
+ %0 = getelementptr i32* %p, i32 %offset
+ store i32 %val, i32* %0, align 4
+ ret void
+}
+
+define void @store32_imm(i32* %p, i32 %val) nounwind {
+entry:
+ %0 = getelementptr i32* %p, i32 11
+ store i32 %val, i32* %0, align 4
+ ret void
+}
+
+define void @store16(i16* %p, i32 %offset, i16 %val) nounwind {
+entry:
+ %0 = getelementptr i16* %p, i32 %offset
+ store i16 %val, i16* %0, align 2
+ ret void
+}
+
+define void @store8(i8* %p, i32 %offset, i8 %val) nounwind {
+entry:
+ %0 = getelementptr i8* %p, i32 %offset
+ store i8 %val, i8* %0, align 1
+ ret void
+}
diff --git a/test/CodeGen/XCore/tls.ll b/test/CodeGen/XCore/tls.ll
new file mode 100644
index 0000000..ed41afa
--- /dev/null
+++ b/test/CodeGen/XCore/tls.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=xcore -mcpu=xs1b-generic | FileCheck %s
+
+define i32 *@addr_G() {
+entry:
+; CHECK: addr_G:
+; CHECK: get r11, id
+ ret i32* @G
+}
+
+@G = thread_local global i32 15
+; CHECK: .section .dp.data,"awd",@progbits
+; CHECK: G:
+; CHECK: .long 15
+; CHECK: .long 15
+; CHECK: .long 15
+; CHECK: .long 15
+; CHECK: .long 15
+; CHECK: .long 15
+; CHECK: .long 15
+; CHECK: .long 15
diff --git a/test/CodeGen/XCore/trap.ll b/test/CodeGen/XCore/trap.ll
new file mode 100644
index 0000000..45f886d
--- /dev/null
+++ b/test/CodeGen/XCore/trap.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "ecallf" %t1.s | count 1
+; RUN: grep "ldc" %t1.s | count 1
+define i32 @test() noreturn nounwind {
+entry:
+ tail call void @llvm.trap( )
+ unreachable
+}
+
+declare void @llvm.trap() nounwind
+
diff --git a/test/CodeGen/XCore/unaligned_load.ll b/test/CodeGen/XCore/unaligned_load.ll
new file mode 100644
index 0000000..0ee8e1c
--- /dev/null
+++ b/test/CodeGen/XCore/unaligned_load.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "bl __misaligned_load" %t1.s | count 1
+; RUN: grep ld16s %t1.s | count 2
+; RUN: grep ldw %t1.s | count 2
+; RUN: grep shl %t1.s | count 2
+; RUN: grep shr %t1.s | count 1
+; RUN: grep zext %t1.s | count 1
+; RUN: grep "or " %t1.s | count 2
+
+; Byte aligned load. Expands to call to __misaligned_load.
+define i32 @align1(i32* %p) nounwind {
+entry:
+ %0 = load i32* %p, align 1 ; <i32> [#uses=1]
+ ret i32 %0
+}
+
+; Half word aligned load. Expands to two 16bit loads.
+define i32 @align2(i32* %p) nounwind {
+entry:
+ %0 = load i32* %p, align 2 ; <i32> [#uses=1]
+ ret i32 %0
+}
+
+@a = global [5 x i8] zeroinitializer, align 4
+
+; Constant offset from word aligned base. Expands to two 32bit loads.
+define i32 @align3() nounwind {
+entry:
+ %0 = load i32* bitcast (i8* getelementptr ([5 x i8]* @a, i32 0, i32 1) to i32*), align 1
+ ret i32 %0
+}
diff --git a/test/CodeGen/XCore/unaligned_store.ll b/test/CodeGen/XCore/unaligned_store.ll
new file mode 100644
index 0000000..62078e6
--- /dev/null
+++ b/test/CodeGen/XCore/unaligned_store.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "bl __misaligned_store" %t1.s | count 1
+; RUN: grep st16 %t1.s | count 2
+; RUN: grep shr %t1.s | count 1
+
+; Byte aligned store. Expands to call to __misaligned_store.
+define void @align1(i32* %p, i32 %val) nounwind {
+entry:
+ store i32 %val, i32* %p, align 1
+ ret void
+}
+
+; Half word aligned store. Expands to two 16bit stores.
+define void @align2(i32* %p, i32 %val) nounwind {
+entry:
+ store i32 %val, i32* %p, align 2
+ ret void
+}
diff --git a/test/CodeGen/XCore/unaligned_store_combine.ll b/test/CodeGen/XCore/unaligned_store_combine.ll
new file mode 100644
index 0000000..493ca6a
--- /dev/null
+++ b/test/CodeGen/XCore/unaligned_store_combine.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=xcore > %t1.s
+; RUN: grep "bl memmove" %t1.s | count 1
+; RUN: grep "ldc r., 8" %t1.s | count 1
+
+; Unaligned load / store pair. Should be combined into a memmove
+; of size 8
+define void @f(i64* %dst, i64* %src) nounwind {
+entry:
+ %0 = load i64* %src, align 1
+ store i64 %0, i64* %dst, align 1
+ ret void
+}
