Stephen Hines | 36b5688 | 2014-04-23 16:57:46 -0700 | [diff] [blame] | 1 | ; RUN: llc -march=arm64 -mcpu=cyclone < %s | FileCheck %s |
| 2 | |
| 3 | ; CHECK: foo |
Pirama Arumuga Nainar | de2d869 | 2016-09-19 22:57:26 -0700 | [diff] [blame] | 4 | ; CHECK: str w[[REG0:[0-9]+]], [x19, #264] |
| 5 | ; CHECK: mov w[[REG1:[0-9]+]], w[[REG0]] |
| 6 | ; CHECK: str w[[REG1]], [x19, #132] |
Stephen Hines | 36b5688 | 2014-04-23 16:57:46 -0700 | [diff] [blame] | 7 | |
| 8 | define i32 @foo(i32 %a) nounwind { |
| 9 | %retval = alloca i32, align 4 |
| 10 | %a.addr = alloca i32, align 4 |
| 11 | %arr = alloca [32 x i32], align 4 |
| 12 | %i = alloca i32, align 4 |
| 13 | %arr2 = alloca [32 x i32], align 4 |
| 14 | %j = alloca i32, align 4 |
| 15 | store i32 %a, i32* %a.addr, align 4 |
Pirama Arumuga Nainar | 4c5e43d | 2015-04-08 08:55:49 -0700 | [diff] [blame] | 16 | %tmp = load i32, i32* %a.addr, align 4 |
Stephen Hines | 36b5688 | 2014-04-23 16:57:46 -0700 | [diff] [blame] | 17 | %tmp1 = zext i32 %tmp to i64 |
| 18 | %v = mul i64 4, %tmp1 |
| 19 | %vla = alloca i8, i64 %v, align 4 |
| 20 | %tmp2 = bitcast i8* %vla to i32* |
Pirama Arumuga Nainar | 4c5e43d | 2015-04-08 08:55:49 -0700 | [diff] [blame] | 21 | %tmp3 = load i32, i32* %a.addr, align 4 |
Stephen Hines | 36b5688 | 2014-04-23 16:57:46 -0700 | [diff] [blame] | 22 | store i32 %tmp3, i32* %i, align 4 |
Pirama Arumuga Nainar | 4c5e43d | 2015-04-08 08:55:49 -0700 | [diff] [blame] | 23 | %tmp4 = load i32, i32* %a.addr, align 4 |
Stephen Hines | 36b5688 | 2014-04-23 16:57:46 -0700 | [diff] [blame] | 24 | store i32 %tmp4, i32* %j, align 4 |
Pirama Arumuga Nainar | 4c5e43d | 2015-04-08 08:55:49 -0700 | [diff] [blame] | 25 | %tmp5 = load i32, i32* %j, align 4 |
Stephen Hines | 36b5688 | 2014-04-23 16:57:46 -0700 | [diff] [blame] | 26 | store i32 %tmp5, i32* %retval |
Pirama Arumuga Nainar | 4c5e43d | 2015-04-08 08:55:49 -0700 | [diff] [blame] | 27 | %x = load i32, i32* %retval |
Stephen Hines | 36b5688 | 2014-04-23 16:57:46 -0700 | [diff] [blame] | 28 | ret i32 %x |
| 29 | } |