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android / platform / external / llvm / refs/heads/android15-tests-dev / . / test / CodeGen / AArch64 / directcond.ll
blob: f89d7603fd3ec79532413e6f6be9e4a858ff987d [file] [log] [blame]
Pirama Arumuga Nainarde2d8692016-09-19 22:57:26 -0700[diff] [blame]1; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 -aarch64-atomic-cfg-tidy=0 | FileCheck %s
Stephen Hinesc6a4f5e2014-07-21 00:45:20 -0700[diff] [blame]2; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 -aarch64-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-NOFP %s
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]3
4define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
Stephen Linb4dc0232013-07-13 20:38:47 +0000[diff] [blame]5; CHECK-LABEL: test_select_i32:
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]6 %val = select i1 %bit, i32 %a, i32 %b
Stephen Hinesdce4a402014-05-29 02:49:00 -0700[diff] [blame]7; CHECK: tst w0, #0x1
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]8; CHECK-NEXT: csel w0, w1, w2, ne
9
10 ret i32 %val
11}
12
13define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
Stephen Linb4dc0232013-07-13 20:38:47 +0000[diff] [blame]14; CHECK-LABEL: test_select_i64:
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]15 %val = select i1 %bit, i64 %a, i64 %b
Stephen Hinesdce4a402014-05-29 02:49:00 -0700[diff] [blame]16; CHECK: tst w0, #0x1
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]17; CHECK-NEXT: csel x0, x1, x2, ne
18
19 ret i64 %val
20}
21
22define float @test_select_float(i1 %bit, float %a, float %b) {
Stephen Linb4dc0232013-07-13 20:38:47 +0000[diff] [blame]23; CHECK-LABEL: test_select_float:
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]24 %val = select i1 %bit, float %a, float %b
Stephen Hinesdce4a402014-05-29 02:49:00 -0700[diff] [blame]25; CHECK: tst w0, #0x1
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]26; CHECK-NEXT: fcsel s0, s0, s1, ne
Amara Emersonc2884322013-10-31 09:32:11 +0000[diff] [blame]27; CHECK-NOFP-NOT: fcsel
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]28 ret float %val
29}
30
31define double @test_select_double(i1 %bit, double %a, double %b) {
Stephen Linb4dc0232013-07-13 20:38:47 +0000[diff] [blame]32; CHECK-LABEL: test_select_double:
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]33 %val = select i1 %bit, double %a, double %b
Stephen Hinesdce4a402014-05-29 02:49:00 -0700[diff] [blame]34; CHECK: tst w0, #0x1
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]35; CHECK-NEXT: fcsel d0, d0, d1, ne
Amara Emersonc2884322013-10-31 09:32:11 +0000[diff] [blame]36; CHECK-NOFP-NOT: fcsel
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]37
38 ret double %val
39}
40
41define i32 @test_brcond(i1 %bit) {
Stephen Linb4dc0232013-07-13 20:38:47 +0000[diff] [blame]42; CHECK-LABEL: test_brcond:
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]43 br i1 %bit, label %true, label %false
Stephen Hinesdce4a402014-05-29 02:49:00 -0700[diff] [blame]44; CHECK: tbz {{w[0-9]+}}, #0, {{.?LBB}}
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]45
46true:
47 ret i32 0
48false:
49 ret i32 42
50}
51
52define i1 @test_setcc_float(float %lhs, float %rhs) {
53; CHECK: test_setcc_float
54 %val = fcmp oeq float %lhs, %rhs
55; CHECK: fcmp s0, s1
Stephen Hinesdce4a402014-05-29 02:49:00 -0700[diff] [blame]56; CHECK: cset w0, eq
Amara Emersonc2884322013-10-31 09:32:11 +0000[diff] [blame]57; CHECK-NOFP-NOT: fcmp
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]58 ret i1 %val
59}
60
61define i1 @test_setcc_double(double %lhs, double %rhs) {
62; CHECK: test_setcc_double
63 %val = fcmp oeq double %lhs, %rhs
64; CHECK: fcmp d0, d1
Stephen Hinesdce4a402014-05-29 02:49:00 -0700[diff] [blame]65; CHECK: cset w0, eq
Amara Emersonc2884322013-10-31 09:32:11 +0000[diff] [blame]66; CHECK-NOFP-NOT: fcmp
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]67 ret i1 %val
68}
69
70define i1 @test_setcc_i32(i32 %lhs, i32 %rhs) {
71; CHECK: test_setcc_i32
72 %val = icmp ugt i32 %lhs, %rhs
73; CHECK: cmp w0, w1
Stephen Hinesdce4a402014-05-29 02:49:00 -0700[diff] [blame]74; CHECK: cset w0, hi
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]75 ret i1 %val
76}
77
78define i1 @test_setcc_i64(i64 %lhs, i64 %rhs) {
79; CHECK: test_setcc_i64
80 %val = icmp ne i64 %lhs, %rhs
81; CHECK: cmp x0, x1
Stephen Hinesdce4a402014-05-29 02:49:00 -0700[diff] [blame]82; CHECK: cset w0, ne
Tim Northover72062f52013-01-31 12:12:40 +0000[diff] [blame]83 ret i1 %val
84}