test/aarch32/config/cond-rd-rn-a32.json

// Copyright 2016, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
//     and/or other materials provided with the distribution.
//   * Neither the name of ARM Limited nor the names of its contributors may be
//     used to endorse or promote products derived from this software without
//     specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

{
  "mnemonics" : [
    "Clz",   // CLZ{<c>}{<q>} <Rd>, <Rm> ; A1
    "Rbit",  // RBIT{<c>}{<q>} <Rd>, <Rm> ; A1
    "Rev",   // REV{<c>}{<q>} <Rd>, <Rm> ; A1
    "Rev16", // REV16{<c>}{<q>} <Rd>, <Rm> ; A1
    "Revsh", // REVSH{<c>}{<q>} <Rd>, <Rm> ; A1
    "Rrx",   // RRX{<c>}{<q>} {<Rd>}, <Rm> ; A1
    "Rrxs"   // RRXS{<c>}{<q>} {<Rd>}, <Rm> ; A1
  ],
  "description" : {
    "operands": [
      {
        "name": "cond",
        "type": "Condition"
      },
      {
        "name": "rd",
        "type": "AllRegistersButPC"
      },
      {
        "name": "rn",
        "type": "AllRegistersButPC"
      }
    ],
    "inputs": [
      {
        "name": "apsr",
        "type": "NZCV"
      },
      {
        "name": "rd",
        "type": "Register"
      },
      {
        "name": "rn",
        "type": "Register"
      }
    ]
  },
  "test-files": [
    {
      "type": "assembler",
      "test-cases": [
        {
          "name": "Operands",
          "operands": [
            "cond", "rd", "rn"
          ],
          "operand-limit": 500
        }
      ]
    },
    {
      "type": "macro-assembler",
      "test-cases": [
        {
          "name": "Operands",
          "operands": [
            "cond", "rd", "rn"
          ],
          "operand-limit": 500
        }
      ]
    },
    {
      "type": "simulator",
      "test-cases": [
        {
          "name": "Condition",
          "operands": [
            "cond"
          ],
          "inputs": [
            "apsr"
          ]
        },
        // Test combinations of registers values with rd == rn.
        {
          "name": "RdIsRn",
          "operands": [
            "rd", "rn"
          ],
          "inputs": [
            "rd", "rn"
          ],
          "operand-filter": "rd == rn",
          "input-filter": "rd == rn"
        },
        // Test combinations of registers values with rd != rn.
        {
          "name": "RdIsNotRn",
          "operands": [
            "rd", "rn"
          ],
          "inputs": [
            "rd", "rn"
          ],
          "operand-filter": "rd != rn",
          "operand-limit": 10,
          "input-filter": "rd != rn"
        }
      ]
    }
  ]
}