test/aarch32/config/cond-rd-rn-operand-rm-shift-amount-1to31-t32.json

// Copyright 2016, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
//     and/or other materials provided with the distribution.
//   * Neither the name of ARM Limited nor the names of its contributors may be
//     used to endorse or promote products derived from this software without
//     specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

// Test description for instructions of the following form:
//   MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>, LSL|ROR #<amount>
//   MNEMONIC{<c>}.W <Rd>, SP,   <Rm>, LSL|ROR #<amount>

{
  "mnemonics": [
    "Adc",  // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
    "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
    "Add",  // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
            // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
    "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
            // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
    "And",  // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
    "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
    "Bic",  // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
    "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
    "Eor",  // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
    "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
    "Orn",  // ORN{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
    "Orns", // ORNS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
    "Orr",  // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
    "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
    "Rsb",  // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
    "Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
    "Sbc",  // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
    "Sbcs", // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
    "Sub",  // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
            // SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1
    "Subs"  // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
            // SUBS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1
  ],
  "description": {
    "operands": [
      {
        "name": "cond",
        "type": "Condition"
      },
      {
        "name": "rd",
        "type": "AllRegistersButPC"
      },
      {
        "name": "rn",
        "type": "AllRegistersButPC"
      },
      {
        "name": "op",
        "wrapper": "Operand",
        "operands": [
          {
            "name": "rm",
            "type": "AllRegistersButPC"
          },
          {
            "name": "shift",
            "type": "Shift1To31"
          },
          {
            "name": "amount",
            "type": "ShiftAmount1To31"
          }
        ]
      }
    ],
    "inputs": [
      {
        "name": "apsr",
        "type": "NZCV"
      },
      {
        "name": "rd",
        "type": "Register"
      },
      {
        "name": "rn",
        "type": "Register"
      },
      {
        "name": "rm",
        "type": "Register"
      }
    ]
  },
  "test-files": [
    {
      "type": "assembler",
      "test-cases": [
        {
          "name": "Operands",
          "operands": [
            "cond", "rd", "rn", "rm", "shift", "amount"
          ],
          "operand-filter": "cond == 'al'",
          "operand-limit": 500
        }
      ]
    },
    {
      "type": "simulator",
      "test-cases": [
        {
          "name": "Condition",
          "operands": [
            "cond"
          ],
          "inputs": [
            "apsr"
          ]
        },
        // Test combinations of registers values with rd == rn.
        {
          "name": "RdIsRn",
          "operands": [
            "rd", "rn", "rm"
          ],
          "inputs": [
            "rd", "rn", "rm"
          ],
          "operand-filter": "rd == rn and rn != rm",
          "operand-limit": 10,
          "input-filter": "rd == rn",
          "input-limit": 200
        },
        // Test combinations of registers values with rd == rm.
        {
          "name": "RdIsRm",
          "operands": [
            "rd", "rn", "rm"
          ],
          "inputs": [
            "rd", "rn", "rm"
          ],
          "operand-filter": "rd == rm and rn != rm",
          "operand-limit": 10,
          "input-filter": "rd == rm",
          "input-limit": 200
        },
        // Test combinations of registers values.
        {
          "name": "RdIsNotRnIsNotRm",
          "operands": [
            "rd", "rn", "rm"
          ],
          "inputs": [
            "rd", "rn", "rm"
          ],
          "operand-filter": "rd != rn != rm",
          "operand-limit": 10,
          "input-limit": 200
        },
        // Test combinations of shift types and shift amounts.
        {
          "name": "ShiftTypes",
          "operands": [
            "rd", "rn", "rm", "shift", "amount"
          ],
          "inputs": [
            "rm"
          ],
          // Specify exactly what registers to use in this test to make sure
          // that they are different. It makes the execution trace more
          // understandable.
          "operand-filter": "rd == 'r0' and rn == 'r1' and rm == 'r2'"
        }
      ]
    }
  ]
}