| // Copyright 2016, VIXL authors |
| // All rights reserved. |
| // |
| // Redistribution and use in source and binary forms, with or without |
| // modification, are permitted provided that the following conditions are met: |
| // |
| // * Redistributions of source code must retain the above copyright notice, |
| // this list of conditions and the following disclaimer. |
| // * Redistributions in binary form must reproduce the above copyright notice, |
| // this list of conditions and the following disclaimer in the documentation |
| // and/or other materials provided with the distribution. |
| // * Neither the name of ARM Limited nor the names of its contributors may be |
| // used to endorse or promote products derived from this software without |
| // specific prior written permission. |
| // |
| // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND |
| // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE |
| // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| |
| // Test description for instructions of the following forms: |
| // MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm> |
| // MNEMONIC{<c>}.W <Rd>, SP, <Rm> |
| // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } |
| // MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } |
| // |
| // MNEMONIC{<c>}.N <Rdm>, SP, <Rdm> |
| // MNEMONIC{<c>}.N SP, SP, <Rm> |
| // MNEMONIC{<c>}.N <Rd>, <Rn>, <Rm> |
| // MNEMONIC{<c>}.N <Rdn>, <Rdn>, <Rm> ; rm is not SP |
| // MNEMONIC{<c>}.N <Rdn>, <Rdn>, <Rm> ; low registers |
| // |
| // Note that this test only covers the cases where the optional shift |
| // operand is not provided. The shift operands are tested in |
| // "cond-rd-rn-operand-rm-shift-amount-*-t32.json". |
| |
| { |
| "mnemonics": [ |
| "Adc", // ADC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 |
| |
| "Adcs", // ADCS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 |
| |
| "Add", // ADD<c>{<q>} <Rd>, <Rn>, <Rm> ; T1 |
| // ADD<c>{<q>} <Rdn>, <Rm> ; T2 |
| // ADD{<c>}{<q>} {<Rdn>}, <Rdn>, <Rm> ; T2 |
| // ADD{<c>}{<q>} {<Rdm>}, SP, <Rdm> ; T1 |
| // ADD{<c>}{<q>} {SP}, SP, <Rm> ; T2 |
| // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3 |
| // ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3 |
| |
| "Adds", // ADDS{<q>} {<Rd>}, <Rn>, <Rm> ; T1 |
| // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3 |
| // ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3 |
| |
| "And", // AND<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 |
| |
| "Ands", // ANDS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 |
| |
| "Bic", // BIC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 |
| |
| "Bics", // BICS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 |
| |
| "Eor", // EOR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 |
| |
| "Eors", // EORS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 |
| |
| "Orn", // ORN{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1 |
| |
| "Orns", // ORNS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1 |
| |
| "Orr", // ORR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 |
| |
| "Orrs", // ORRS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 |
| |
| "Rsb", // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1 |
| |
| "Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1 |
| |
| "Sbc", // SBC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 |
| |
| "Sbcs", // SBCS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 |
| |
| "Sub", // SUB<c>{<q>} <Rd>, <Rn>, <Rm> ; T1 |
| // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 |
| // SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1 |
| // SUB{<c>} {<Rd>}, SP, <Rm> ; T1 |
| |
| "Subs", // SUBS{<q>} {<Rd>}, <Rn>, <Rm> ; T1 |
| // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2 |
| // SUBS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1 |
| |
| "Sxtab", // SXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1 |
| "Sxtab16", // SXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1 |
| "Sxtah", // SXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1 |
| "Uxtab", // UXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1 |
| "Uxtab16", // UXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1 |
| "Uxtah", // UXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1 |
| |
| // Shift instructions that alias to MOV. |
| // Note that we are not giving them a different input for their |
| // last operand since they are already tested in |
| // "cond-rd-operand-rn-shift-rs-t32.json". |
| // TODO: Add tests for MOV <Rd>, <Rn>, <shift>, <Rs>. |
| "Asr", // ASR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1 |
| // ASR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2 |
| |
| "Asrs", // ASRS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1 |
| // ASRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2 |
| |
| "Lsl", // LSL<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1 |
| // LSL{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2 |
| |
| "Lsls", // LSLS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1 |
| // LSLS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2 |
| |
| "Lsr", // LSR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1 |
| // LSR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2 |
| |
| "Lsrs", // LSRS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1 |
| // LSRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2 |
| |
| "Ror", // ROR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1 |
| // ROR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2 |
| |
| "Rors" // RORS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1 |
| // RORS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2 |
| ], |
| "description": { |
| "operands": [ |
| { |
| "name": "cond", |
| "type": "Condition" |
| }, |
| { |
| "name": "rd", |
| "type": "AllRegistersButPC" |
| }, |
| { |
| "name": "rn", |
| "type": "AllRegistersButPC" |
| }, |
| { |
| "name": "op", |
| "wrapper": "Operand", |
| "operands": [ |
| { |
| "name": "rm", |
| "type": "AllRegistersButPC" |
| } |
| ] |
| } |
| ], |
| "inputs": [ |
| { |
| "name": "apsr", |
| "type": "NZCV" |
| }, |
| { |
| "name": "rd", |
| "type": "Register" |
| }, |
| { |
| "name": "rn", |
| "type": "Register" |
| }, |
| { |
| "name": "rm", |
| "type": "Register" |
| } |
| ] |
| }, |
| "test-files": [ |
| { |
| "type": "assembler", |
| "test-cases": [ |
| { |
| "name": "Unconditional", |
| "operands": [ |
| "cond", "rd", "rn", "rm" |
| ], |
| "operand-filter": "cond == 'al'", |
| "operand-limit": 500 |
| } |
| ] |
| }, |
| // Test cases where an IT instruction is allowed. |
| { |
| "name": "all-low-in-it-block", |
| "type": "assembler", |
| "mnemonics": [ |
| "Add", // ADD<c>{<q>} <Rd>, <Rn>, <Rm> ; T1 |
| "Sub" // SUB<c>{<q>} <Rd>, <Rn>, <Rm> ; T1 |
| ], |
| "test-cases": [ |
| { |
| "name": "InITBlock", |
| "operands": [ |
| "cond", "rd", "rn", "rm" |
| ], |
| // Generate an extra IT instruction. |
| "in-it-block": "{cond}", |
| "operand-filter": "cond != 'al' and register_is_low(rd) and register_is_low(rn) and register_is_low(rm)", |
| "operand-limit": 500 |
| } |
| ] |
| }, |
| { |
| "name": "all-low-rd-is-rn-in-it-block", |
| "type": "assembler", |
| "mnemonics": [ |
| "Adc", // ADC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| "And", // AND<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| "Asr", // ASR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1 |
| "Bic", // BIC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| "Eor", // EOR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| "Lsl", // LSL<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1 |
| "Lsr", // LSR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1 |
| "Orr", // ORR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| "Ror", // ROR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1 |
| "Sbc" // SBC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1 |
| ], |
| "test-cases": [ |
| { |
| "name": "InITBlock", |
| "operands": [ |
| "cond", "rd", "rn", "rm" |
| ], |
| // Generate an extra IT instruction. |
| "in-it-block": "{cond}", |
| "operand-filter": "cond != 'al' and rd == rn and register_is_low(rn) and register_is_low(rm)", |
| "operand-limit": 500 |
| } |
| ] |
| }, |
| { |
| "name": "rd-is-rn-in-it-block", |
| "type": "assembler", |
| "mnemonics": [ |
| "Add" // ADD{<c>}{<q>} {<Rdn>}, <Rdn>, <Rm> ; T2 |
| ], |
| "test-cases": [ |
| { |
| "name": "InITBlock", |
| "operands": [ |
| "cond", "rd", "rn", "rm" |
| ], |
| // Generate an extra IT instruction. |
| "in-it-block": "{cond}", |
| "operand-filter": "cond != 'al' and rd == rn and rm != 'r13'", |
| "operand-limit": 500 |
| } |
| ] |
| }, |
| // Special case for a conditional ADD instruction with rn as SP. |
| { |
| "name": "rn-is-sp-in-it-block", |
| "type": "assembler", |
| "mnemonics": [ |
| "Add" // ADD{<c>}{<q>} {<Rdm>}, SP, <Rdm> ; T1 |
| ], |
| "test-cases": [ |
| { |
| "name": "InITBlock", |
| "operands": [ |
| "cond", "rd", "rn", "rm" |
| ], |
| // Generate an extra IT instruction. |
| "in-it-block": "{cond}", |
| "operand-filter": "cond != 'al' and rd == rm and register_is_low(rm) and rn == 'r13'" |
| } |
| ] |
| }, |
| // Special case for a conditional ADD instruction with rd and rn as SP. |
| { |
| "name": "rd-is-rn-is-sp-in-it-block", |
| "type": "assembler", |
| "mnemonics": [ |
| "Add" // ADD{<c>}{<q>} {SP}, SP, <Rm> ; T2 |
| ], |
| "test-cases": [ |
| { |
| "name": "InITBlock", |
| "operands": [ |
| "cond", "rd", "rn", "rm" |
| ], |
| // Generate an extra IT instruction. |
| "in-it-block": "{cond}", |
| "operand-filter": "cond != 'al' and rd == 'r13' and rn == 'r13'" |
| } |
| ] |
| }, |
| { |
| "type": "simulator", |
| "test-cases": [ |
| { |
| "name": "Condition", |
| "operands": [ |
| "cond" |
| ], |
| "inputs": [ |
| "apsr" |
| ] |
| }, |
| // Test combinations of registers values with rd == rn. |
| { |
| "name": "RdIsRn", |
| "operands": [ |
| "cond", "rd", "rn", "rm" |
| ], |
| "inputs": [ |
| "apsr", "rd", "rn", "rm" |
| ], |
| "operand-filter": "rd == rn and rn != rm", |
| "operand-limit": 10, |
| "input-filter": "rd == rn", |
| "input-limit": 200 |
| }, |
| // Test combinations of registers values with rd == rm. |
| { |
| "name": "RdIsRm", |
| "operands": [ |
| "cond", "rd", "rn", "rm" |
| ], |
| "inputs": [ |
| "apsr", "rd", "rn", "rm" |
| ], |
| "operand-filter": "rd == rm and rn != rm", |
| "operand-limit": 10, |
| "input-filter": "rd == rm", |
| "input-limit": 200 |
| }, |
| // Test combinations of registers values. |
| { |
| "name": "RdIsNotRnIsNotRm", |
| "operands": [ |
| "cond", "rd", "rn", "rm" |
| ], |
| "inputs": [ |
| "apsr", "rd", "rn", "rm" |
| ], |
| "operand-filter": "rd != rn != rm", |
| "operand-limit": 10, |
| "input-limit": 200 |
| } |
| ] |
| } |
| ] |
| } |
