test/aarch32/config/cond-rdlow-rnlow-rmlow-t32.json

// Copyright 2016, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
//     and/or other materials provided with the distribution.
//   * Neither the name of ARM Limited nor the names of its contributors may be
//     used to endorse or promote products derived from this software without
//     specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

// Test description for the MULS instruction with the following operands:
//   MNEMONIC{<c>}.N <Rdm>, <Rn>, <Rdm>

{
  "mnemonics": [
    "Mul", // MUL<c>{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1
    "Muls" // MULS{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1
  ],
  "description": {
    "operands": [
      {
        "name": "cond",
        "type": "Condition"
      },
      {
        "name": "rd",
        "type": "LowRegisters"
      },
      {
        "name": "rn",
        "type": "LowRegisters"
      },
      {
        "name": "rm",
        "type": "LowRegisters"
      }
    ],
    "inputs": [
      {
        "name": "apsr",
        "type": "NZCV"
      },
      {
        "name": "rd",
        "type": "Register"
      },
      {
        "name": "rn",
        "type": "Register"
      },
      {
        "name": "rm",
        "type": "Register"
      }
    ]
  },
  "test-files": [
    {
      "type": "assembler",
      "mnemonics": [
        "Muls" // MULS{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1
      ],
      "test-cases": [
        {
          "name": "OutItBlock",
          "operands": [
            "cond", "rd", "rn", "rm"
          ],
          "operand-filter": "cond == 'al' and rd == rm"
        }
      ]
    },
    {
      "name": "in-it-block",
      "type": "assembler",
      "mnemonics": [
        "Mul" // MUL<c>{<q>} <Rdm>, <Rn>, {<Rdm>} ; T1
      ],
      "test-cases": [
        {
          "name": "InITBlock",
          "operands": [
            "cond", "rd", "rn", "rm"
          ],
          // Generate an extra IT instruction.
          "in-it-block": "{cond}",
          "operand-filter": "cond != 'al' and rd == rm"
        }
      ]
    },
    {
      "type": "simulator",
      "test-cases": [
        {
          "name": "Condition",
          "operands": [
            "cond"
          ],
          "inputs": [
            "apsr"
          ]
        },
        {
          "name": "Unconditional",
          "operands": [
            "cond", "rd", "rn", "rm"
          ],
          "inputs": [
            "cond", "rd", "rn", "rm"
          ],
          "operand-filter": "cond == 'al' and rd == rm",
          "operand-limit": 20,
          "input-filter": "rd == rm",
          "input-limit": 500
        }
      ]
    }
  ]
}