src/hotspot/cpu/riscv/vmreg_riscv.hpp

/*
 * Copyright (c) 2006, 2019, Oracle and/or its affiliates. All rights reserved.
 * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 * published by the Free Software Foundation.
 *
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * version 2 for more details (a copy is included in the LICENSE file that
 * accompanied this code).
 *
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 * 2 along with this work; if not, write to the Free Software Foundation,
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#ifndef CPU_RISCV_VMREG_RISCV_HPP
#define CPU_RISCV_VMREG_RISCV_HPP

inline bool is_Register() {
  return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr;
}

inline bool is_FloatRegister() {
  return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr;
}

inline bool is_VectorRegister() {
  return value() >= ConcreteRegisterImpl::max_fpr && value() < ConcreteRegisterImpl::max_vpr;
}

inline Register as_Register() {
  assert(is_Register(), "must be");
  return ::as_Register(value() / Register::max_slots_per_register);
}

inline FloatRegister as_FloatRegister() {
  assert(is_FloatRegister() && is_even(value()), "must be");
  return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) /
                            FloatRegister::max_slots_per_register);
}

inline VectorRegister as_VectorRegister() {
  assert(is_VectorRegister() && ((value() & (VectorRegister::max_slots_per_register - 1)) == 0), "must be");
  return ::as_VectorRegister((value() - ConcreteRegisterImpl::max_fpr) /
                             VectorRegister::max_slots_per_register);
}

inline bool is_concrete() {
  assert(is_reg(), "must be");
  if (is_VectorRegister()) {
    int base = value() - ConcreteRegisterImpl::max_fpr;
    return (base % VectorRegister::max_slots_per_register) == 0;
  } else {
    return is_even(value());
  }
}

#endif // CPU_RISCV_VMREG_RISCV_HPP