| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s |
| |
| declare <8 x i16> @llvm.loongarch.lsx.vhsubw.h.b(<16 x i8>, <16 x i8>) |
| |
| define <8 x i16> @lsx_vhsubw_h_b(<16 x i8> %va, <16 x i8> %vb) nounwind { |
| ; CHECK-LABEL: lsx_vhsubw_h_b: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vhsubw.h.b $vr0, $vr0, $vr1 |
| ; CHECK-NEXT: ret |
| entry: |
| %res = call <8 x i16> @llvm.loongarch.lsx.vhsubw.h.b(<16 x i8> %va, <16 x i8> %vb) |
| ret <8 x i16> %res |
| } |
| |
| declare <4 x i32> @llvm.loongarch.lsx.vhsubw.w.h(<8 x i16>, <8 x i16>) |
| |
| define <4 x i32> @lsx_vhsubw_w_h(<8 x i16> %va, <8 x i16> %vb) nounwind { |
| ; CHECK-LABEL: lsx_vhsubw_w_h: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vhsubw.w.h $vr0, $vr0, $vr1 |
| ; CHECK-NEXT: ret |
| entry: |
| %res = call <4 x i32> @llvm.loongarch.lsx.vhsubw.w.h(<8 x i16> %va, <8 x i16> %vb) |
| ret <4 x i32> %res |
| } |
| |
| declare <2 x i64> @llvm.loongarch.lsx.vhsubw.d.w(<4 x i32>, <4 x i32>) |
| |
| define <2 x i64> @lsx_vhsubw_d_w(<4 x i32> %va, <4 x i32> %vb) nounwind { |
| ; CHECK-LABEL: lsx_vhsubw_d_w: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vhsubw.d.w $vr0, $vr0, $vr1 |
| ; CHECK-NEXT: ret |
| entry: |
| %res = call <2 x i64> @llvm.loongarch.lsx.vhsubw.d.w(<4 x i32> %va, <4 x i32> %vb) |
| ret <2 x i64> %res |
| } |
| |
| declare <2 x i64> @llvm.loongarch.lsx.vhsubw.q.d(<2 x i64>, <2 x i64>) |
| |
| define <2 x i64> @lsx_vhsubw_q_d(<2 x i64> %va, <2 x i64> %vb) nounwind { |
| ; CHECK-LABEL: lsx_vhsubw_q_d: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vhsubw.q.d $vr0, $vr0, $vr1 |
| ; CHECK-NEXT: ret |
| entry: |
| %res = call <2 x i64> @llvm.loongarch.lsx.vhsubw.q.d(<2 x i64> %va, <2 x i64> %vb) |
| ret <2 x i64> %res |
| } |
| |
| declare <8 x i16> @llvm.loongarch.lsx.vhsubw.hu.bu(<16 x i8>, <16 x i8>) |
| |
| define <8 x i16> @lsx_vhsubw_hu_bu(<16 x i8> %va, <16 x i8> %vb) nounwind { |
| ; CHECK-LABEL: lsx_vhsubw_hu_bu: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vhsubw.hu.bu $vr0, $vr0, $vr1 |
| ; CHECK-NEXT: ret |
| entry: |
| %res = call <8 x i16> @llvm.loongarch.lsx.vhsubw.hu.bu(<16 x i8> %va, <16 x i8> %vb) |
| ret <8 x i16> %res |
| } |
| |
| declare <4 x i32> @llvm.loongarch.lsx.vhsubw.wu.hu(<8 x i16>, <8 x i16>) |
| |
| define <4 x i32> @lsx_vhsubw_wu_hu(<8 x i16> %va, <8 x i16> %vb) nounwind { |
| ; CHECK-LABEL: lsx_vhsubw_wu_hu: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vhsubw.wu.hu $vr0, $vr0, $vr1 |
| ; CHECK-NEXT: ret |
| entry: |
| %res = call <4 x i32> @llvm.loongarch.lsx.vhsubw.wu.hu(<8 x i16> %va, <8 x i16> %vb) |
| ret <4 x i32> %res |
| } |
| |
| declare <2 x i64> @llvm.loongarch.lsx.vhsubw.du.wu(<4 x i32>, <4 x i32>) |
| |
| define <2 x i64> @lsx_vhsubw_du_wu(<4 x i32> %va, <4 x i32> %vb) nounwind { |
| ; CHECK-LABEL: lsx_vhsubw_du_wu: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vhsubw.du.wu $vr0, $vr0, $vr1 |
| ; CHECK-NEXT: ret |
| entry: |
| %res = call <2 x i64> @llvm.loongarch.lsx.vhsubw.du.wu(<4 x i32> %va, <4 x i32> %vb) |
| ret <2 x i64> %res |
| } |
| |
| declare <2 x i64> @llvm.loongarch.lsx.vhsubw.qu.du(<2 x i64>, <2 x i64>) |
| |
| define <2 x i64> @lsx_vhsubw_qu_du(<2 x i64> %va, <2 x i64> %vb) nounwind { |
| ; CHECK-LABEL: lsx_vhsubw_qu_du: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: vhsubw.qu.du $vr0, $vr0, $vr1 |
| ; CHECK-NEXT: ret |
| entry: |
| %res = call <2 x i64> @llvm.loongarch.lsx.vhsubw.qu.du(<2 x i64> %va, <2 x i64> %vb) |
| ret <2 x i64> %res |
| } |