llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fneg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

define void @fneg_v4f32(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: fneg_v4f32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vbitrevi.w $vr0, $vr0, 31
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %v0 = load <4 x float>, ptr %a0
  %v1 = fneg <4 x float> %v0
  store <4 x float> %v1, ptr %res
  ret void
}
define void @fneg_v2f64(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: fneg_v2f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vbitrevi.d $vr0, $vr0, 63
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %v0 = load <2 x double>, ptr %a0
  %v1 = fneg <2 x double> %v0
  store <2 x double> %v1, ptr %res
  ret void
}