| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 |
| ; RUN: opt -p loop-vectorize -force-vector-width=4 -S %s | FileCheck %s |
| |
| ; Test cases with trip counts containing UDIV expressions for |
| ; https://github.com/llvm/llvm-project/issues/89958. |
| |
| define i64 @multi_exit_1_exit_count_with_udiv_by_value_in_header(ptr %dst, i64 %N) { |
| ; CHECK-LABEL: define i64 @multi_exit_1_exit_count_with_udiv_by_value_in_header( |
| ; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 0) |
| ; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 42, [[N]] |
| ; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SMAX]], i64 [[TMP0]]) |
| ; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[UMIN]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP1]], 4 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 4 |
| ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i64 4, i64 [[N_MOD_VF]] |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[TMP3]] |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 0 |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP4]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i32 0 |
| ; CHECK-NEXT: store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr [[TMP6]], align 4 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: br label [[SCALAR_PH]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] |
| ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] |
| ; CHECK: loop.header: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]] |
| ; CHECK-NEXT: store i32 1, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[D:%.*]] = udiv i64 42, [[N]] |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp slt i64 [[IV]], [[D]] |
| ; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_LATCH]], label [[EXIT:%.*]] |
| ; CHECK: loop.latch: |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[C_0:%.*]] = icmp slt i64 [[IV]], [[N]] |
| ; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_HEADER]], label [[EXIT]], !llvm.loop [[LOOP3:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[P:%.*]] = phi i64 [ 1, [[LOOP_HEADER]] ], [ 0, [[LOOP_LATCH]] ] |
| ; CHECK-NEXT: ret i64 [[P]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %gep = getelementptr inbounds i32, ptr %dst, i64 %iv |
| store i32 1, ptr %gep |
| %d = udiv i64 42, %N |
| %c.1 = icmp slt i64 %iv, %d |
| br i1 %c.1, label %loop.latch, label %exit |
| |
| loop.latch: |
| %iv.next = add i64 %iv, 1 |
| %c.0 = icmp slt i64 %iv, %N |
| br i1 %c.0, label %loop.header, label %exit |
| |
| exit: |
| %p = phi i64 [ 1, %loop.header ], [ 0, %loop.latch] |
| ret i64 %p |
| } |
| |
| define i64 @multi_exit_1_exit_count_with_udiv_by_constant_in_header(ptr %dst, i64 %N) { |
| ; CHECK-LABEL: define i64 @multi_exit_1_exit_count_with_udiv_by_constant_in_header( |
| ; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 0) |
| ; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 [[N]], 42 |
| ; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SMAX]], i64 [[TMP0]]) |
| ; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[UMIN]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP1]], 4 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 4 |
| ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i64 4, i64 [[N_MOD_VF]] |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[TMP3]] |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 0 |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP4]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i32 0 |
| ; CHECK-NEXT: store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr [[TMP6]], align 4 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: br label [[SCALAR_PH]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] |
| ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] |
| ; CHECK: loop.header: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]] |
| ; CHECK-NEXT: store i32 1, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[D:%.*]] = udiv i64 [[N]], 42 |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp slt i64 [[IV]], [[D]] |
| ; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_LATCH]], label [[EXIT:%.*]] |
| ; CHECK: loop.latch: |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[C_0:%.*]] = icmp slt i64 [[IV]], [[N]] |
| ; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_HEADER]], label [[EXIT]], !llvm.loop [[LOOP5:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[P:%.*]] = phi i64 [ 1, [[LOOP_HEADER]] ], [ 0, [[LOOP_LATCH]] ] |
| ; CHECK-NEXT: ret i64 [[P]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %gep = getelementptr inbounds i32, ptr %dst, i64 %iv |
| store i32 1, ptr %gep |
| %d = udiv i64 %N, 42 |
| %c.1 = icmp slt i64 %iv, %d |
| br i1 %c.1, label %loop.latch, label %exit |
| |
| loop.latch: |
| %iv.next = add i64 %iv, 1 |
| %c.0 = icmp slt i64 %iv, %N |
| br i1 %c.0, label %loop.header, label %exit |
| |
| exit: |
| %p = phi i64 [ 1, %loop.header ], [ 0, %loop.latch] |
| ret i64 %p |
| } |
| |
| define i64 @multi_exit_2_exit_count_with_udiv_by_value_in_block_executed_unconditionally(ptr %A, i64 %N) { |
| ; CHECK-LABEL: define i64 @multi_exit_2_exit_count_with_udiv_by_value_in_block_executed_unconditionally( |
| ; CHECK-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 0) |
| ; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 42, [[N]] |
| ; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SMAX]], i64 [[TMP0]]) |
| ; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[UMIN]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP1]], 4 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 4 |
| ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i64 4, i64 [[N_MOD_VF]] |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[TMP3]] |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE6:%.*]] ] |
| ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 0 |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP4]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i32 0 |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4 |
| ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD]], <i32 10, i32 10, i32 10, i32 10> |
| ; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP7]], i32 0 |
| ; CHECK-NEXT: br i1 [[TMP8]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] |
| ; CHECK: pred.store.if: |
| ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP4]] |
| ; CHECK-NEXT: store i32 1, ptr [[TMP9]], align 4 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]] |
| ; CHECK: pred.store.continue: |
| ; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP7]], i32 1 |
| ; CHECK-NEXT: br i1 [[TMP10]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2:%.*]] |
| ; CHECK: pred.store.if1: |
| ; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 1 |
| ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP11]] |
| ; CHECK-NEXT: store i32 1, ptr [[TMP12]], align 4 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE2]] |
| ; CHECK: pred.store.continue2: |
| ; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i1> [[TMP7]], i32 2 |
| ; CHECK-NEXT: br i1 [[TMP13]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]] |
| ; CHECK: pred.store.if3: |
| ; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 2 |
| ; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP14]] |
| ; CHECK-NEXT: store i32 1, ptr [[TMP15]], align 4 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]] |
| ; CHECK: pred.store.continue4: |
| ; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i1> [[TMP7]], i32 3 |
| ; CHECK-NEXT: br i1 [[TMP16]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6]] |
| ; CHECK: pred.store.if5: |
| ; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[INDEX]], 3 |
| ; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP17]] |
| ; CHECK-NEXT: store i32 1, ptr [[TMP18]], align 4 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]] |
| ; CHECK: pred.store.continue6: |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP19]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: br label [[SCALAR_PH]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] |
| ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] |
| ; CHECK: loop.header: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] |
| ; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[C_2:%.*]] = icmp eq i32 [[L]], 10 |
| ; CHECK-NEXT: br i1 [[C_2]], label [[THEN:%.*]], label [[CONTINUE:%.*]] |
| ; CHECK: then: |
| ; CHECK-NEXT: store i32 1, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: br label [[CONTINUE]] |
| ; CHECK: continue: |
| ; CHECK-NEXT: [[D:%.*]] = udiv i64 42, [[N]] |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp slt i64 [[IV]], [[D]] |
| ; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_LATCH]], label [[EXIT:%.*]] |
| ; CHECK: loop.latch: |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[C_0:%.*]] = icmp slt i64 [[IV]], [[N]] |
| ; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_HEADER]], label [[EXIT]], !llvm.loop [[LOOP7:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[P:%.*]] = phi i64 [ 1, [[CONTINUE]] ], [ 0, [[LOOP_LATCH]] ] |
| ; CHECK-NEXT: ret i64 [[P]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %gep = getelementptr inbounds i32, ptr %A, i64 %iv |
| %l = load i32, ptr %gep |
| %c.2 = icmp eq i32 %l, 10 |
| br i1 %c.2, label %then, label %continue |
| |
| then: |
| store i32 1, ptr %gep |
| br label %continue |
| |
| continue: |
| %d = udiv i64 42, %N |
| %c.1 = icmp slt i64 %iv, %d |
| br i1 %c.1, label %loop.latch, label %exit |
| |
| loop.latch: |
| %iv.next = add i64 %iv, 1 |
| %c.0 = icmp slt i64 %iv, %N |
| br i1 %c.0, label %loop.header, label %exit |
| |
| exit: |
| %p = phi i64 [ 1, %continue ], [ 0, %loop.latch] |
| ret i64 %p |
| } |
| |
| define i64 @multi_exit_2_exit_count_with_udiv_by_constant_in_block_executed_unconditionally(ptr %A, i64 %N) { |
| ; CHECK-LABEL: define i64 @multi_exit_2_exit_count_with_udiv_by_constant_in_block_executed_unconditionally( |
| ; CHECK-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 0) |
| ; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 [[N]], 42 |
| ; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SMAX]], i64 [[TMP0]]) |
| ; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[UMIN]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP1]], 4 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 4 |
| ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i64 4, i64 [[N_MOD_VF]] |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[TMP3]] |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE6:%.*]] ] |
| ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 0 |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP4]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i32 0 |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4 |
| ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD]], <i32 10, i32 10, i32 10, i32 10> |
| ; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP7]], i32 0 |
| ; CHECK-NEXT: br i1 [[TMP8]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] |
| ; CHECK: pred.store.if: |
| ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP4]] |
| ; CHECK-NEXT: store i32 1, ptr [[TMP9]], align 4 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]] |
| ; CHECK: pred.store.continue: |
| ; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP7]], i32 1 |
| ; CHECK-NEXT: br i1 [[TMP10]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2:%.*]] |
| ; CHECK: pred.store.if1: |
| ; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 1 |
| ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP11]] |
| ; CHECK-NEXT: store i32 1, ptr [[TMP12]], align 4 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE2]] |
| ; CHECK: pred.store.continue2: |
| ; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i1> [[TMP7]], i32 2 |
| ; CHECK-NEXT: br i1 [[TMP13]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]] |
| ; CHECK: pred.store.if3: |
| ; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 2 |
| ; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP14]] |
| ; CHECK-NEXT: store i32 1, ptr [[TMP15]], align 4 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]] |
| ; CHECK: pred.store.continue4: |
| ; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i1> [[TMP7]], i32 3 |
| ; CHECK-NEXT: br i1 [[TMP16]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6]] |
| ; CHECK: pred.store.if5: |
| ; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[INDEX]], 3 |
| ; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP17]] |
| ; CHECK-NEXT: store i32 1, ptr [[TMP18]], align 4 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]] |
| ; CHECK: pred.store.continue6: |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP19]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: br label [[SCALAR_PH]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] |
| ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] |
| ; CHECK: loop.header: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] |
| ; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[C_2:%.*]] = icmp eq i32 [[L]], 10 |
| ; CHECK-NEXT: br i1 [[C_2]], label [[THEN:%.*]], label [[CONTINUE:%.*]] |
| ; CHECK: then: |
| ; CHECK-NEXT: store i32 1, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: br label [[CONTINUE]] |
| ; CHECK: continue: |
| ; CHECK-NEXT: [[D:%.*]] = udiv i64 [[N]], 42 |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp slt i64 [[IV]], [[D]] |
| ; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_LATCH]], label [[EXIT:%.*]] |
| ; CHECK: loop.latch: |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[C_0:%.*]] = icmp slt i64 [[IV]], [[N]] |
| ; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_HEADER]], label [[EXIT]], !llvm.loop [[LOOP9:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[P:%.*]] = phi i64 [ 1, [[CONTINUE]] ], [ 0, [[LOOP_LATCH]] ] |
| ; CHECK-NEXT: ret i64 [[P]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %gep = getelementptr inbounds i32, ptr %A, i64 %iv |
| %l = load i32, ptr %gep |
| %c.2 = icmp eq i32 %l, 10 |
| br i1 %c.2, label %then, label %continue |
| |
| then: |
| store i32 1, ptr %gep |
| br label %continue |
| |
| continue: |
| %d = udiv i64 %N, 42 |
| %c.1 = icmp slt i64 %iv, %d |
| br i1 %c.1, label %loop.latch, label %exit |
| |
| loop.latch: |
| %iv.next = add i64 %iv, 1 |
| %c.0 = icmp slt i64 %iv, %N |
| br i1 %c.0, label %loop.header, label %exit |
| |
| exit: |
| %p = phi i64 [ 1, %continue ], [ 0, %loop.latch] |
| ret i64 %p |
| } |
| |
| define i64 @multi_exit_3_exit_count_with_udiv_by_value_in_block_executed_conditionally(ptr %A, i64 %N) { |
| ; CHECK-LABEL: define i64 @multi_exit_3_exit_count_with_udiv_by_value_in_block_executed_conditionally( |
| ; CHECK-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] |
| ; CHECK: loop.header: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] |
| ; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[C_2:%.*]] = icmp eq i32 [[L]], 10 |
| ; CHECK-NEXT: br i1 [[C_2]], label [[THEN:%.*]], label [[LOOP_LATCH]] |
| ; CHECK: then: |
| ; CHECK-NEXT: [[D:%.*]] = udiv i64 42, [[N]] |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp slt i64 [[IV]], [[D]] |
| ; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_LATCH]], label [[EXIT:%.*]] |
| ; CHECK: loop.latch: |
| ; CHECK-NEXT: store i32 1, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[C_0:%.*]] = icmp slt i64 [[IV]], [[N]] |
| ; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_HEADER]], label [[EXIT]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[P:%.*]] = phi i64 [ 1, [[THEN]] ], [ 0, [[LOOP_LATCH]] ] |
| ; CHECK-NEXT: ret i64 [[P]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %gep = getelementptr inbounds i32, ptr %A, i64 %iv |
| %l = load i32, ptr %gep |
| %c.2 = icmp eq i32 %l, 10 |
| br i1 %c.2, label %then, label %loop.latch |
| |
| then: |
| %d = udiv i64 42, %N |
| %c.1 = icmp slt i64 %iv, %d |
| br i1 %c.1, label %loop.latch, label %exit |
| |
| loop.latch: |
| store i32 1, ptr %gep |
| %iv.next = add i64 %iv, 1 |
| %c.0 = icmp slt i64 %iv, %N |
| br i1 %c.0, label %loop.header, label %exit |
| |
| exit: |
| %p = phi i64 [ 1, %then ], [ 0, %loop.latch] |
| ret i64 %p |
| } |
| |
| define i64 @multi_exit_3_exit_count_with_udiv_by_constant_in_block_executed_conditionally(ptr %A, i64 %N) { |
| ; CHECK-LABEL: define i64 @multi_exit_3_exit_count_with_udiv_by_constant_in_block_executed_conditionally( |
| ; CHECK-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[D:%.*]] = udiv i64 [[N]], 42 |
| ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] |
| ; CHECK: loop.header: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] |
| ; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[C_2:%.*]] = icmp ne i32 [[L]], 10 |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp slt i64 [[IV]], [[D]] |
| ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C_2]], i1 true, i1 [[C_1]] |
| ; CHECK-NEXT: br i1 [[OR_COND]], label [[LOOP_LATCH]], label [[EXIT:%.*]] |
| ; CHECK: loop.latch: |
| ; CHECK-NEXT: store i32 1, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[C_0:%.*]] = icmp slt i64 [[IV]], [[N]] |
| ; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_HEADER]], label [[EXIT]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[P:%.*]] = phi i64 [ 0, [[LOOP_LATCH]] ], [ 1, [[LOOP_HEADER]] ] |
| ; CHECK-NEXT: ret i64 [[P]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %gep = getelementptr inbounds i32, ptr %A, i64 %iv |
| %l = load i32, ptr %gep |
| %c.2 = icmp eq i32 %l, 10 |
| br i1 %c.2, label %then, label %loop.latch |
| |
| then: |
| %d = udiv i64 %N, 42 |
| %c.1 = icmp slt i64 %iv, %d |
| br i1 %c.1, label %loop.latch, label %exit |
| |
| loop.latch: |
| store i32 1, ptr %gep |
| %iv.next = add i64 %iv, 1 |
| %c.0 = icmp slt i64 %iv, %N |
| br i1 %c.0, label %loop.header, label %exit |
| |
| exit: |
| %p = phi i64 [ 1, %then ], [ 0, %loop.latch] |
| ret i64 %p |
| } |
| |
| ; FIXME: Currently miscompiled as we unconditionally execute udiv after |
| ; vectorization. |
| define i64 @multi_exit_4_exit_count_with_udiv_by_value_in_latch(ptr %dst, i64 %N) { |
| ; CHECK-LABEL: define i64 @multi_exit_4_exit_count_with_udiv_by_value_in_latch( |
| ; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 0) |
| ; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 42, [[N]] |
| ; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SMAX]], i64 [[TMP0]]) |
| ; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[UMIN]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP1]], 4 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 4 |
| ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i64 4, i64 [[N_MOD_VF]] |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[TMP3]] |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 0 |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP4]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i32 0 |
| ; CHECK-NEXT: store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr [[TMP6]], align 4 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: br label [[SCALAR_PH]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] |
| ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] |
| ; CHECK: loop.header: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]] |
| ; CHECK-NEXT: store i32 1, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[C_0:%.*]] = icmp slt i64 [[IV]], [[N]] |
| ; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_LATCH]], label [[EXIT:%.*]] |
| ; CHECK: loop.latch: |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[D:%.*]] = udiv i64 42, [[N]] |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp slt i64 [[IV]], [[D]] |
| ; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_HEADER]], label [[EXIT]], !llvm.loop [[LOOP11:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[P:%.*]] = phi i64 [ 1, [[LOOP_HEADER]] ], [ 0, [[LOOP_LATCH]] ] |
| ; CHECK-NEXT: ret i64 [[P]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %gep = getelementptr inbounds i32, ptr %dst, i64 %iv |
| store i32 1, ptr %gep |
| %c.0 = icmp slt i64 %iv, %N |
| br i1 %c.0, label %loop.latch, label %exit |
| |
| loop.latch: |
| %iv.next = add i64 %iv, 1 |
| %d = udiv i64 42, %N |
| %c.1 = icmp slt i64 %iv, %d |
| br i1 %c.1, label %loop.header, label %exit |
| |
| exit: |
| %p = phi i64 [ 1, %loop.header ], [ 0, %loop.latch] |
| ret i64 %p |
| } |
| |
| define i64 @multi_exit_4_exit_count_with_udiv_by_constant_in_latch(ptr %dst, i64 %N) { |
| ; CHECK-LABEL: define i64 @multi_exit_4_exit_count_with_udiv_by_constant_in_latch( |
| ; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 0) |
| ; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 [[N]], 42 |
| ; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SMAX]], i64 [[TMP0]]) |
| ; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[UMIN]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP1]], 4 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 4 |
| ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i64 4, i64 [[N_MOD_VF]] |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[TMP3]] |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 0 |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP4]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i32 0 |
| ; CHECK-NEXT: store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr [[TMP6]], align 4 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: br label [[SCALAR_PH]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] |
| ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] |
| ; CHECK: loop.header: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]] |
| ; CHECK-NEXT: store i32 1, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[C_0:%.*]] = icmp slt i64 [[IV]], [[N]] |
| ; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_LATCH]], label [[EXIT:%.*]] |
| ; CHECK: loop.latch: |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[D:%.*]] = udiv i64 [[N]], 42 |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp slt i64 [[IV]], [[D]] |
| ; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_HEADER]], label [[EXIT]], !llvm.loop [[LOOP13:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[P:%.*]] = phi i64 [ 1, [[LOOP_HEADER]] ], [ 0, [[LOOP_LATCH]] ] |
| ; CHECK-NEXT: ret i64 [[P]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %gep = getelementptr inbounds i32, ptr %dst, i64 %iv |
| store i32 1, ptr %gep |
| %c.0 = icmp slt i64 %iv, %N |
| br i1 %c.0, label %loop.latch, label %exit |
| |
| loop.latch: |
| %iv.next = add i64 %iv, 1 |
| %d = udiv i64 %N, 42 |
| %c.1 = icmp slt i64 %iv, %d |
| br i1 %c.1, label %loop.header, label %exit |
| |
| exit: |
| %p = phi i64 [ 1, %loop.header ], [ 0, %loop.latch] |
| ret i64 %p |
| } |
| |
| define void @single_exit_tc_with_udiv(ptr %dst, i64 %N) { |
| ; CHECK-LABEL: define void @single_exit_tc_with_udiv( |
| ; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 42, [[N]] |
| ; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 4 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]] |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 0 |
| ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP2]] |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i32 0 |
| ; CHECK-NEXT: store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr [[TMP4]], align 4 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] |
| ; CHECK-NEXT: br label [[LOOP:%.*]] |
| ; CHECK: loop: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]] |
| ; CHECK-NEXT: store i32 1, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[D:%.*]] = udiv i64 42, [[N]] |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp slt i64 [[IV]], [[D]] |
| ; CHECK-NEXT: br i1 [[C_1]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP15:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %gep = getelementptr inbounds i32, ptr %dst, i64 %iv |
| store i32 1, ptr %gep |
| %iv.next = add i64 %iv, 1 |
| %d = udiv i64 42, %N |
| %c.1 = icmp slt i64 %iv, %d |
| br i1 %c.1, label %loop, label %exit |
| |
| exit: |
| ret void |
| } |
| |
| ; FIXME: Currently miscompiled as we unconditionally execute udiv after |
| ; vectorization. |
| define i64 @multi_exit_4_exit_count_with_urem_by_value_in_latch(ptr %dst, i64 %N) { |
| ; CHECK-LABEL: define i64 @multi_exit_4_exit_count_with_urem_by_value_in_latch( |
| ; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 0) |
| ; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 42, [[N]] |
| ; CHECK-NEXT: [[TMP1:%.*]] = mul nuw i64 [[N]], [[TMP0]] |
| ; CHECK-NEXT: [[TMP2:%.*]] = sub i64 42, [[TMP1]] |
| ; CHECK-NEXT: [[SMAX1:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP2]], i64 0) |
| ; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SMAX]], i64 [[SMAX1]]) |
| ; CHECK-NEXT: [[TMP3:%.*]] = add nuw i64 [[UMIN]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP3]], 4 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 4 |
| ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 4, i64 [[N_MOD_VF]] |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[TMP5]] |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 0 |
| ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP6]] |
| ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i32 0 |
| ; CHECK-NEXT: store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr [[TMP8]], align 4 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: br label [[SCALAR_PH]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] |
| ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] |
| ; CHECK: loop.header: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]] |
| ; CHECK-NEXT: store i32 1, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[C_0:%.*]] = icmp slt i64 [[IV]], [[N]] |
| ; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_LATCH]], label [[EXIT:%.*]] |
| ; CHECK: loop.latch: |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[D:%.*]] = urem i64 42, [[N]] |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp slt i64 [[IV]], [[D]] |
| ; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_HEADER]], label [[EXIT]], !llvm.loop [[LOOP17:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[P:%.*]] = phi i64 [ 1, [[LOOP_HEADER]] ], [ 0, [[LOOP_LATCH]] ] |
| ; CHECK-NEXT: ret i64 [[P]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %gep = getelementptr inbounds i32, ptr %dst, i64 %iv |
| store i32 1, ptr %gep |
| %c.0 = icmp slt i64 %iv, %N |
| br i1 %c.0, label %loop.latch, label %exit |
| |
| loop.latch: |
| %iv.next = add i64 %iv, 1 |
| %d = urem i64 42, %N |
| %c.1 = icmp slt i64 %iv, %d |
| br i1 %c.1, label %loop.header, label %exit |
| |
| exit: |
| %p = phi i64 [ 1, %loop.header ], [ 0, %loop.latch] |
| ret i64 %p |
| } |
| |
| define i64 @multi_exit_4_exit_count_with_urem_by_constant_in_latch(ptr %dst, i64 %N) { |
| ; CHECK-LABEL: define i64 @multi_exit_4_exit_count_with_urem_by_constant_in_latch( |
| ; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 0) |
| ; CHECK-NEXT: [[TMP2:%.*]] = urem i64 [[N]], 42 |
| ; CHECK-NEXT: [[SMAX1:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP2]], i64 0) |
| ; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SMAX]], i64 [[SMAX1]]) |
| ; CHECK-NEXT: [[TMP3:%.*]] = add nuw i64 [[UMIN]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP3]], 4 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 4 |
| ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 4, i64 [[N_MOD_VF]] |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[TMP5]] |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 0 |
| ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP6]] |
| ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP7]], i32 0 |
| ; CHECK-NEXT: store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, ptr [[TMP8]], align 4 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: br label [[SCALAR_PH]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] |
| ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] |
| ; CHECK: loop.header: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]] |
| ; CHECK-NEXT: store i32 1, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[C_0:%.*]] = icmp slt i64 [[IV]], [[N]] |
| ; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_LATCH]], label [[EXIT:%.*]] |
| ; CHECK: loop.latch: |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[D:%.*]] = urem i64 [[N]], 42 |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp slt i64 [[IV]], [[D]] |
| ; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_HEADER]], label [[EXIT]], !llvm.loop [[LOOP19:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[P:%.*]] = phi i64 [ 1, [[LOOP_HEADER]] ], [ 0, [[LOOP_LATCH]] ] |
| ; CHECK-NEXT: ret i64 [[P]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %gep = getelementptr inbounds i32, ptr %dst, i64 %iv |
| store i32 1, ptr %gep |
| %c.0 = icmp slt i64 %iv, %N |
| br i1 %c.0, label %loop.latch, label %exit |
| |
| loop.latch: |
| %iv.next = add i64 %iv, 1 |
| %d = urem i64 %N, 42 |
| %c.1 = icmp slt i64 %iv, %d |
| br i1 %c.1, label %loop.header, label %exit |
| |
| exit: |
| %p = phi i64 [ 1, %loop.header ], [ 0, %loop.latch] |
| ret i64 %p |
| } |
| |
| define i64 @multi_exit_4_exit_count_with_srem_by_value_in_latch(ptr %dst, i64 %N) { |
| ; CHECK-LABEL: define i64 @multi_exit_4_exit_count_with_srem_by_value_in_latch( |
| ; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] |
| ; CHECK: loop.header: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]] |
| ; CHECK-NEXT: store i32 1, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[C_0:%.*]] = icmp slt i64 [[IV]], [[N]] |
| ; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_LATCH]], label [[EXIT:%.*]] |
| ; CHECK: loop.latch: |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[D:%.*]] = srem i64 42, [[N]] |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp slt i64 [[IV]], [[D]] |
| ; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_HEADER]], label [[EXIT]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[P:%.*]] = phi i64 [ 1, [[LOOP_HEADER]] ], [ 0, [[LOOP_LATCH]] ] |
| ; CHECK-NEXT: ret i64 [[P]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %gep = getelementptr inbounds i32, ptr %dst, i64 %iv |
| store i32 1, ptr %gep |
| %c.0 = icmp slt i64 %iv, %N |
| br i1 %c.0, label %loop.latch, label %exit |
| |
| loop.latch: |
| %iv.next = add i64 %iv, 1 |
| %d = srem i64 42, %N |
| %c.1 = icmp slt i64 %iv, %d |
| br i1 %c.1, label %loop.header, label %exit |
| |
| exit: |
| %p = phi i64 [ 1, %loop.header ], [ 0, %loop.latch] |
| ret i64 %p |
| } |
| |
| define i64 @multi_exit_4_exit_count_with_sdiv_by_value_in_latch(ptr %dst, i64 %N) { |
| ; CHECK-LABEL: define i64 @multi_exit_4_exit_count_with_sdiv_by_value_in_latch( |
| ; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] |
| ; CHECK: loop.header: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]] |
| ; CHECK-NEXT: store i32 1, ptr [[GEP]], align 4 |
| ; CHECK-NEXT: [[C_0:%.*]] = icmp slt i64 [[IV]], [[N]] |
| ; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_LATCH]], label [[EXIT:%.*]] |
| ; CHECK: loop.latch: |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[D:%.*]] = sdiv i64 42, [[N]] |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp slt i64 [[IV]], [[D]] |
| ; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_HEADER]], label [[EXIT]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[P:%.*]] = phi i64 [ 1, [[LOOP_HEADER]] ], [ 0, [[LOOP_LATCH]] ] |
| ; CHECK-NEXT: ret i64 [[P]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %gep = getelementptr inbounds i32, ptr %dst, i64 %iv |
| store i32 1, ptr %gep |
| %c.0 = icmp slt i64 %iv, %N |
| br i1 %c.0, label %loop.latch, label %exit |
| |
| loop.latch: |
| %iv.next = add i64 %iv, 1 |
| %d = sdiv i64 42, %N |
| %c.1 = icmp slt i64 %iv, %d |
| br i1 %c.1, label %loop.header, label %exit |
| |
| exit: |
| %p = phi i64 [ 1, %loop.header ], [ 0, %loop.latch] |
| ret i64 %p |
| } |
| |
| ;. |
| ; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} |
| ; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} |
| ; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} |
| ; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} |
| ; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} |
| ; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]} |
| ; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]} |
| ; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META2]], [[META1]]} |
| ; CHECK: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP13]] = distinct !{[[LOOP13]], [[META2]], [[META1]]} |
| ; CHECK: [[LOOP14]] = distinct !{[[LOOP14]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP15]] = distinct !{[[LOOP15]], [[META2]], [[META1]]} |
| ; CHECK: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP17]] = distinct !{[[LOOP17]], [[META2]], [[META1]]} |
| ; CHECK: [[LOOP18]] = distinct !{[[LOOP18]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP19]] = distinct !{[[LOOP19]], [[META2]], [[META1]]} |
| ;. |
