llvm/test/Transforms/SLPVectorizer/RISCV/reduction-extension-after-bitwidth.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt -S -mtriple=riscv64-unknown-linux-gnu -mattr="+v" --passes=slp-vectorizer < %s | FileCheck %s

define i32 @test(ptr %0, ptr %1) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: ptr [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[LOAD_5:%.*]] = load i32, ptr [[TMP1]], align 4
; CHECK-NEXT:    [[TMP2:%.*]] = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> <i8 1, i8 1, i8 1, i8 1>)
; CHECK-NEXT:    [[TMP3:%.*]] = sext i8 [[TMP2]] to i32
; CHECK-NEXT:    [[OP_RDX:%.*]] = and i32 [[TMP3]], [[LOAD_5]]
; CHECK-NEXT:    ret i32 [[OP_RDX]]
;
entry:
  %zext.0 = zext i8 1 to i32
  %zext.1 = zext i8 1 to i32
  %zext.2 = zext i8 1 to i32
  %zext.3 = zext i8 1 to i32
  %select.zext.0 = select i1 false, i32 -1, i32 %zext.0
  %select.zext.1 = select i1 false, i32 0, i32 %zext.1
  %select.zext.2 = select i1 false, i32 0, i32 %zext.2
  %select.zext.3 = select i1 false, i32 0, i32 %zext.3

  %load.5 = load i32, ptr %1, align 4

  %and.0 = and i32 %load.5, %select.zext.0
  %and.1 = and i32 %and.0, %select.zext.1
  %and.2 = and i32 %and.1, %select.zext.2
  %and.3 = and i32 %and.2, %select.zext.3

  ret i32 %and.3
}