llvm/test/Transforms/SROA/scalable-vector-array.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s
; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s

; This test checks that SROA runs mem2reg on arrays of scalable vectors.

define [ 2 x <vscale x 4 x i32> ] @alloca(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
; CHECK-LABEL: define [2 x <vscale x 4 x i32>] @alloca
; CHECK-SAME: (<vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32> [[Y:%.*]]) {
; CHECK-NEXT:    [[AGG0:%.*]] = insertvalue [2 x <vscale x 4 x i32>] poison, <vscale x 4 x i32> [[X]], 0
; CHECK-NEXT:    [[AGG1:%.*]] = insertvalue [2 x <vscale x 4 x i32>] [[AGG0]], <vscale x 4 x i32> [[Y]], 1
; CHECK-NEXT:    ret [2 x <vscale x 4 x i32>] [[AGG1]]
;
  %addr = alloca [ 2 x <vscale x 4 x i32> ], align 4
  %agg0 = insertvalue [ 2 x <vscale x 4 x i32> ] poison, <vscale x 4 x i32> %x, 0
  %agg1 = insertvalue [ 2 x <vscale x 4 x i32> ] %agg0, <vscale x 4 x i32> %y, 1
  store [ 2 x <vscale x 4 x i32> ] %agg1, ptr %addr, align 4
  %val = load [ 2 x <vscale x 4 x i32> ], ptr %addr, align 4
  ret [ 2 x <vscale x 4 x i32> ] %val
}