| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 4 |
| // RUN: %clang_cc1 -std=c++11 -triple riscv64-linux-gnu -target-feature +i -target-feature +m -emit-llvm %s -o - | FileCheck %s |
| |
| __attribute__((target_clones("default", "arch=+m"))) int foo1(void) { |
| return 1; |
| } |
| __attribute__((target_clones("default", "arch=+zbb", "arch=+m"))) int foo2(void) { return 2; } |
| __attribute__((target_clones("default", "arch=+zbb,+c"))) int foo3(void) { return 3; } |
| __attribute__((target_clones("default", "arch=+zbb,+v"))) int |
| foo4(void) { |
| return 4; |
| } |
| __attribute__((target_clones("default"))) int foo5(void) { return 5; } |
| __attribute__((target_clones("default", "arch=+zvkt"))) int foo6(void) { return 2; } |
| |
| __attribute__((target_clones("default", "arch=+zbb", "arch=+zba", "arch=+zbb,+zba"))) int foo7(void) { return 2; } |
| __attribute__((target_clones("default", "arch=+zbb;priority=2", "arch=+zba;priority=1", "arch=+zbb,+zba;priority=3"))) int foo8(void) { return 2; } |
| __attribute__((target_clones("default", "arch=+zbb;priority=1", "priority=2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo9(void) { return 2; } |
| |
| int bar() { return foo1() + foo2() + foo3() + foo4() + foo5()+ foo6() + foo7() + foo8() + foo9(); } |
| |
| //. |
| // CHECK: @__riscv_feature_bits = external dso_local global { i32, [2 x i64] } |
| // CHECK: @_Z4foo1v.ifunc = weak_odr alias i32 (), ptr @_Z4foo1v |
| // CHECK: @_Z4foo2v.ifunc = weak_odr alias i32 (), ptr @_Z4foo2v |
| // CHECK: @_Z4foo3v.ifunc = weak_odr alias i32 (), ptr @_Z4foo3v |
| // CHECK: @_Z4foo4v.ifunc = weak_odr alias i32 (), ptr @_Z4foo4v |
| // CHECK: @_Z4foo5v.ifunc = weak_odr alias i32 (), ptr @_Z4foo5v |
| // CHECK: @_Z4foo6v.ifunc = weak_odr alias i32 (), ptr @_Z4foo6v |
| // CHECK: @_Z4foo7v.ifunc = weak_odr alias i32 (), ptr @_Z4foo7v |
| // CHECK: @_Z4foo8v.ifunc = weak_odr alias i32 (), ptr @_Z4foo8v |
| // CHECK: @_Z4foo9v.ifunc = weak_odr alias i32 (), ptr @_Z4foo9v |
| // CHECK: @_Z4foo1v = weak_odr ifunc i32 (), ptr @_Z4foo1v.resolver |
| // CHECK: @_Z4foo2v = weak_odr ifunc i32 (), ptr @_Z4foo2v.resolver |
| // CHECK: @_Z4foo3v = weak_odr ifunc i32 (), ptr @_Z4foo3v.resolver |
| // CHECK: @_Z4foo4v = weak_odr ifunc i32 (), ptr @_Z4foo4v.resolver |
| // CHECK: @_Z4foo5v = weak_odr ifunc i32 (), ptr @_Z4foo5v.resolver |
| // CHECK: @_Z4foo6v = weak_odr ifunc i32 (), ptr @_Z4foo6v.resolver |
| // CHECK: @_Z4foo7v = weak_odr ifunc i32 (), ptr @_Z4foo7v.resolver |
| // CHECK: @_Z4foo8v = weak_odr ifunc i32 (), ptr @_Z4foo8v.resolver |
| // CHECK: @_Z4foo9v = weak_odr ifunc i32 (), ptr @_Z4foo9v.resolver |
| //. |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v.default( |
| // CHECK-SAME: ) #[[ATTR0:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v._m( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4096 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @_Z4foo1v._m |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @_Z4foo1v.default |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._zbb( |
| // CHECK-SAME: ) #[[ATTR1:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._m( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435456 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @_Z4foo2v._zbb |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 4096 |
| // CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 4096 |
| // CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @_Z4foo2v._m |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: ret ptr @_Z4foo2v.default |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 3 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v._c_zbb( |
| // CHECK-SAME: ) #[[ATTR2:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 3 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435460 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435460 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @_Z4foo3v._c_zbb |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @_Z4foo3v.default |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 4 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._v_zbb( |
| // CHECK-SAME: ) #[[ATTR3:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 4 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 270532608 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 270532608 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @_Z4foo4v._v_zbb |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @_Z4foo4v.default |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 5 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @_Z4foo5v.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: ret ptr @_Z4foo5v.default |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zvkt( |
| // CHECK-SAME: ) #[[ATTR4:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 576460752303423488 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 576460752303423488 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @_Z4foo6v._zvkt |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @_Z4foo6v.default |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zbb( |
| // CHECK-SAME: ) #[[ATTR1]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba( |
| // CHECK-SAME: ) #[[ATTR5:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba_zbb( |
| // CHECK-SAME: ) #[[ATTR6:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @_Z4foo7v.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435456 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @_Z4foo7v._zbb |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 134217728 |
| // CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728 |
| // CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @_Z4foo7v._zba |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 402653184 |
| // CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 402653184 |
| // CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] |
| // CHECK: resolver_return3: |
| // CHECK-NEXT: ret ptr @_Z4foo7v._zba_zbb |
| // CHECK: resolver_else4: |
| // CHECK-NEXT: ret ptr @_Z4foo7v.default |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zbb( |
| // CHECK-SAME: ) #[[ATTR1]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zba( |
| // CHECK-SAME: ) #[[ATTR5]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zba_zbb( |
| // CHECK-SAME: ) #[[ATTR6]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @_Z4foo8v.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @_Z4foo8v._zba_zbb |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 268435456 |
| // CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456 |
| // CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @_Z4foo8v._zbb |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 134217728 |
| // CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 134217728 |
| // CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] |
| // CHECK: resolver_return3: |
| // CHECK-NEXT: ret ptr @_Z4foo8v._zba |
| // CHECK: resolver_else4: |
| // CHECK-NEXT: ret ptr @_Z4foo8v.default |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v.default( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v._zbb( |
| // CHECK-SAME: ) #[[ATTR1]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v._zba( |
| // CHECK-SAME: ) #[[ATTR5]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v._zba_zbb( |
| // CHECK-SAME: ) #[[ATTR6]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK-LABEL: define weak_odr ptr @_Z4foo9v.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null) |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184 |
| // CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @_Z4foo9v._zba_zbb |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 134217728 |
| // CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728 |
| // CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @_Z4foo9v._zba |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 268435456 |
| // CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456 |
| // CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] |
| // CHECK: resolver_return3: |
| // CHECK-NEXT: ret ptr @_Z4foo9v._zbb |
| // CHECK: resolver_else4: |
| // CHECK-NEXT: ret ptr @_Z4foo9v.default |
| // |
| // |
| // CHECK-LABEL: define dso_local noundef signext i32 @_Z3barv( |
| // CHECK-SAME: ) #[[ATTR0]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z4foo1v() |
| // CHECK-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_Z4foo2v() |
| // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] |
| // CHECK-NEXT: [[CALL2:%.*]] = call noundef signext i32 @_Z4foo3v() |
| // CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] |
| // CHECK-NEXT: [[CALL4:%.*]] = call noundef signext i32 @_Z4foo4v() |
| // CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]] |
| // CHECK-NEXT: [[CALL6:%.*]] = call noundef signext i32 @_Z4foo5v() |
| // CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]] |
| // CHECK-NEXT: [[CALL8:%.*]] = call noundef signext i32 @_Z4foo6v() |
| // CHECK-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CALL8]] |
| // CHECK-NEXT: [[CALL10:%.*]] = call noundef signext i32 @_Z4foo7v() |
| // CHECK-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]] |
| // CHECK-NEXT: [[CALL12:%.*]] = call noundef signext i32 @_Z4foo8v() |
| // CHECK-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CALL12]] |
| // CHECK-NEXT: [[CALL14:%.*]] = call noundef signext i32 @_Z4foo9v() |
| // CHECK-NEXT: [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CALL14]] |
| // CHECK-NEXT: ret i32 [[ADD15]] |
| // |
| //. |
| // CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" } |
| // CHECK: attributes #[[ATTR1]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zbb,+zmmul" } |
| // CHECK: attributes #[[ATTR2]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+m,+zbb,+zmmul" } |
| // CHECK: attributes #[[ATTR3]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+m,+v,+zbb,+zicsr,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } |
| // CHECK: attributes #[[ATTR4]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul,+zvkt" } |
| // CHECK: attributes #[[ATTR5]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zba,+zmmul" } |
| // CHECK: attributes #[[ATTR6]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zba,+zbb,+zmmul" } |
| //. |
| // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} |
| // CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"} |
| // CHECK: [[META2:![0-9]+]] = !{i32 6, !"riscv-isa", [[META3:![0-9]+]]} |
| // CHECK: [[META3]] = !{!"rv64i2p1_m2p0_zmmul1p0"} |
| // CHECK: [[META4:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0} |
| // CHECK: [[META5:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} |
| //. |
