blob: 50ea706144730fad523c97ea09652283dc2f7f33 [file] [log] [blame]
Dan Albert2a18e9f2018-05-17 09:13:22 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_LINUX_CYCLADES_H
20#define _UAPI_LINUX_CYCLADES_H
21#include <linux/types.h>
22struct cyclades_monitor {
23 unsigned long int_count;
24 unsigned long char_count;
25 unsigned long char_max;
26 unsigned long char_last;
27};
28struct cyclades_idle_stats {
29 __kernel_time_t in_use;
30 __kernel_time_t recv_idle;
31 __kernel_time_t xmit_idle;
32 unsigned long recv_bytes;
33 unsigned long xmit_bytes;
34 unsigned long overruns;
35 unsigned long frame_errs;
36 unsigned long parity_errs;
37};
38#define CYCLADES_MAGIC 0x4359
39#define CYGETMON 0x435901
40#define CYGETTHRESH 0x435902
41#define CYSETTHRESH 0x435903
42#define CYGETDEFTHRESH 0x435904
43#define CYSETDEFTHRESH 0x435905
44#define CYGETTIMEOUT 0x435906
45#define CYSETTIMEOUT 0x435907
46#define CYGETDEFTIMEOUT 0x435908
47#define CYSETDEFTIMEOUT 0x435909
48#define CYSETRFLOW 0x43590a
49#define CYGETRFLOW 0x43590b
50#define CYSETRTSDTR_INV 0x43590c
51#define CYGETRTSDTR_INV 0x43590d
52#define CYZSETPOLLCYCLE 0x43590e
53#define CYZGETPOLLCYCLE 0x43590f
54#define CYGETCD1400VER 0x435910
55#define CYSETWAIT 0x435912
56#define CYGETWAIT 0x435913
57#define CZIOC ('M' << 8)
58#define CZ_NBOARDS (CZIOC | 0xfa)
59#define CZ_BOOT_START (CZIOC | 0xfb)
60#define CZ_BOOT_DATA (CZIOC | 0xfc)
61#define CZ_BOOT_END (CZIOC | 0xfd)
62#define CZ_TEST (CZIOC | 0xfe)
63#define CZ_DEF_POLL (HZ / 25)
64#define MAX_BOARD 4
65#define MAX_DEV 256
66#define CYZ_MAX_SPEED 921600
67#define CYZ_FIFO_SIZE 16
68#define CYZ_BOOT_NWORDS 0x100
69struct CYZ_BOOT_CTRL {
70 unsigned short nboard;
71 int status[MAX_BOARD];
72 int nchannel[MAX_BOARD];
73 int fw_rev[MAX_BOARD];
74 unsigned long offset;
75 unsigned long data[CYZ_BOOT_NWORDS];
76};
77#ifndef DP_WINDOW_SIZE
78#define DP_WINDOW_SIZE (0x00080000)
79#define ZE_DP_WINDOW_SIZE (0x00100000)
80#define CTRL_WINDOW_SIZE (0x00000080)
81struct CUSTOM_REG {
82 __u32 fpga_id;
83 __u32 fpga_version;
84 __u32 cpu_start;
85 __u32 cpu_stop;
86 __u32 misc_reg;
87 __u32 idt_mode;
88 __u32 uart_irq_status;
89 __u32 clear_timer0_irq;
90 __u32 clear_timer1_irq;
91 __u32 clear_timer2_irq;
92 __u32 test_register;
93 __u32 test_count;
94 __u32 timer_select;
95 __u32 pr_uart_irq_status;
96 __u32 ram_wait_state;
97 __u32 uart_wait_state;
98 __u32 timer_wait_state;
99 __u32 ack_wait_state;
100};
101struct RUNTIME_9060 {
102 __u32 loc_addr_range;
103 __u32 loc_addr_base;
104 __u32 loc_arbitr;
105 __u32 endian_descr;
106 __u32 loc_rom_range;
107 __u32 loc_rom_base;
108 __u32 loc_bus_descr;
109 __u32 loc_range_mst;
110 __u32 loc_base_mst;
111 __u32 loc_range_io;
112 __u32 pci_base_mst;
113 __u32 pci_conf_io;
114 __u32 filler1;
115 __u32 filler2;
116 __u32 filler3;
117 __u32 filler4;
118 __u32 mail_box_0;
119 __u32 mail_box_1;
120 __u32 mail_box_2;
121 __u32 mail_box_3;
122 __u32 filler5;
123 __u32 filler6;
124 __u32 filler7;
125 __u32 filler8;
126 __u32 pci_doorbell;
127 __u32 loc_doorbell;
128 __u32 intr_ctrl_stat;
129 __u32 init_ctrl;
130};
131#define WIN_RAM 0x00000001L
132#define WIN_CREG 0x14000001L
133#define TIMER_BY_1M 0x00
134#define TIMER_BY_256K 0x01
135#define TIMER_BY_128K 0x02
136#define TIMER_BY_32K 0x03
137#endif
138#ifndef ZFIRM_ID
139#define MAX_CHAN 64
140#define ID_ADDRESS 0x00000180L
141#define ZFIRM_ID 0x5557465AL
142#define ZFIRM_HLT 0x59505B5CL
143#define ZFIRM_RST 0x56040674L
144#define ZF_TINACT_DEF 1000
145#define ZF_TINACT ZF_TINACT_DEF
146struct FIRM_ID {
147 __u32 signature;
148 __u32 zfwctrl_addr;
149};
150#define C_OS_LINUX 0x00000030
151#define C_CH_DISABLE 0x00000000
152#define C_CH_TXENABLE 0x00000001
153#define C_CH_RXENABLE 0x00000002
154#define C_CH_ENABLE 0x00000003
155#define C_CH_LOOPBACK 0x00000004
156#define C_PR_NONE 0x00000000
157#define C_PR_ODD 0x00000001
158#define C_PR_EVEN 0x00000002
159#define C_PR_MARK 0x00000004
160#define C_PR_SPACE 0x00000008
161#define C_PR_PARITY 0x000000ff
162#define C_PR_DISCARD 0x00000100
163#define C_PR_IGNORE 0x00000200
164#define C_DL_CS5 0x00000001
165#define C_DL_CS6 0x00000002
166#define C_DL_CS7 0x00000004
167#define C_DL_CS8 0x00000008
168#define C_DL_CS 0x0000000f
169#define C_DL_1STOP 0x00000010
170#define C_DL_15STOP 0x00000020
171#define C_DL_2STOP 0x00000040
172#define C_DL_STOP 0x000000f0
173#define C_IN_DISABLE 0x00000000
174#define C_IN_TXBEMPTY 0x00000001
175#define C_IN_TXLOWWM 0x00000002
176#define C_IN_RXHIWM 0x00000010
177#define C_IN_RXNNDT 0x00000020
178#define C_IN_MDCD 0x00000100
179#define C_IN_MDSR 0x00000200
180#define C_IN_MRI 0x00000400
181#define C_IN_MCTS 0x00000800
182#define C_IN_RXBRK 0x00001000
183#define C_IN_PR_ERROR 0x00002000
184#define C_IN_FR_ERROR 0x00004000
185#define C_IN_OVR_ERROR 0x00008000
186#define C_IN_RXOFL 0x00010000
187#define C_IN_IOCTLW 0x00020000
188#define C_IN_MRTS 0x00040000
189#define C_IN_ICHAR 0x00080000
190#define C_FL_OXX 0x00000001
191#define C_FL_IXX 0x00000002
192#define C_FL_OIXANY 0x00000004
193#define C_FL_SWFLOW 0x0000000f
194#define C_FS_TXIDLE 0x00000000
195#define C_FS_SENDING 0x00000001
196#define C_FS_SWFLOW 0x00000002
197#define C_RS_PARAM 0x80000000
198#define C_RS_RTS 0x00000001
199#define C_RS_DTR 0x00000004
200#define C_RS_DCD 0x00000100
201#define C_RS_DSR 0x00000200
202#define C_RS_RI 0x00000400
203#define C_RS_CTS 0x00000800
204#define C_CM_RESET 0x01
205#define C_CM_IOCTL 0x02
206#define C_CM_IOCTLW 0x03
207#define C_CM_IOCTLM 0x04
208#define C_CM_SENDXOFF 0x10
209#define C_CM_SENDXON 0x11
210#define C_CM_CLFLOW 0x12
211#define C_CM_SENDBRK 0x41
212#define C_CM_INTBACK 0x42
213#define C_CM_SET_BREAK 0x43
214#define C_CM_CLR_BREAK 0x44
215#define C_CM_CMD_DONE 0x45
216#define C_CM_INTBACK2 0x46
217#define C_CM_TINACT 0x51
218#define C_CM_IRQ_ENBL 0x52
219#define C_CM_IRQ_DSBL 0x53
220#define C_CM_ACK_ENBL 0x54
221#define C_CM_ACK_DSBL 0x55
222#define C_CM_FLUSH_RX 0x56
223#define C_CM_FLUSH_TX 0x57
224#define C_CM_Q_ENABLE 0x58
225#define C_CM_Q_DISABLE 0x59
226#define C_CM_TXBEMPTY 0x60
227#define C_CM_TXLOWWM 0x61
228#define C_CM_RXHIWM 0x62
229#define C_CM_RXNNDT 0x63
230#define C_CM_TXFEMPTY 0x64
231#define C_CM_ICHAR 0x65
232#define C_CM_MDCD 0x70
233#define C_CM_MDSR 0x71
234#define C_CM_MRI 0x72
235#define C_CM_MCTS 0x73
236#define C_CM_MRTS 0x74
237#define C_CM_RXBRK 0x84
238#define C_CM_PR_ERROR 0x85
239#define C_CM_FR_ERROR 0x86
240#define C_CM_OVR_ERROR 0x87
241#define C_CM_RXOFL 0x88
242#define C_CM_CMDERROR 0x90
243#define C_CM_FATAL 0x91
244#define C_CM_HW_RESET 0x92
245struct CH_CTRL {
246 __u32 op_mode;
247 __u32 intr_enable;
248 __u32 sw_flow;
249 __u32 flow_status;
250 __u32 comm_baud;
251 __u32 comm_parity;
252 __u32 comm_data_l;
253 __u32 comm_flags;
254 __u32 hw_flow;
255 __u32 rs_control;
256 __u32 rs_status;
257 __u32 flow_xon;
258 __u32 flow_xoff;
259 __u32 hw_overflow;
260 __u32 sw_overflow;
261 __u32 comm_error;
262 __u32 ichar;
263 __u32 filler[7];
264};
265struct BUF_CTRL {
266 __u32 flag_dma;
267 __u32 tx_bufaddr;
268 __u32 tx_bufsize;
269 __u32 tx_threshold;
270 __u32 tx_get;
271 __u32 tx_put;
272 __u32 rx_bufaddr;
273 __u32 rx_bufsize;
274 __u32 rx_threshold;
275 __u32 rx_get;
276 __u32 rx_put;
277 __u32 filler[5];
278};
279struct BOARD_CTRL {
280 __u32 n_channel;
281 __u32 fw_version;
282 __u32 op_system;
283 __u32 dr_version;
284 __u32 inactivity;
285 __u32 hcmd_channel;
286 __u32 hcmd_param;
287 __u32 fwcmd_channel;
288 __u32 fwcmd_param;
289 __u32 zf_int_queue_addr;
290 __u32 filler[6];
291};
292#define QUEUE_SIZE (10 * MAX_CHAN)
293struct INT_QUEUE {
294 unsigned char intr_code[QUEUE_SIZE];
295 unsigned long channel[QUEUE_SIZE];
296 unsigned long param[QUEUE_SIZE];
297 unsigned long put;
298 unsigned long get;
299};
300struct ZFW_CTRL {
301 struct BOARD_CTRL board_ctrl;
302 struct CH_CTRL ch_ctrl[MAX_CHAN];
303 struct BUF_CTRL buf_ctrl[MAX_CHAN];
304};
305#endif
306#endif