src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s

---
name: atomicrmw_xor_global_i32_ss
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2
    ; CHECK-LABEL: name: atomicrmw_xor_global_i32_ss
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
    %0:_(p1) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 1)
...

---
name: atomicrmw_xor_flat_i32_ss
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2
    ; CHECK-LABEL: name: atomicrmw_xor_flat_i32_ss
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
    %0:_(p0) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 0)
...

---
name: atomicrmw_xor_local_i32_ss
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: atomicrmw_xor_local_i32_ss
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_ADD [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
    %0:_(p3) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4, addrspace 3)
...